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core, nfqueue, openvswitch: Orphan frags in skb_zerocopy and handle errors
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
90b1ebe7 44#include <linux/netdevice.h>
b046ffe5 45#include <linux/kmod.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
48#include <linux/mlx4/doorbell.h>
49
50#include "mlx4.h"
51#include "fw.h"
52#include "icm.h"
53
54MODULE_AUTHOR("Roland Dreier");
55MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
56MODULE_LICENSE("Dual BSD/GPL");
57MODULE_VERSION(DRV_VERSION);
58
27bf91d6
YP		 59struct workqueue_struct *mlx4_wq;
60
225c7b1f
RD		 61#ifdef CONFIG_MLX4_DEBUG
62
63int mlx4_debug_level = 0;
64module_param_named(debug_level, mlx4_debug_level, int, 0644);
65MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66
67#endif /* CONFIG_MLX4_DEBUG */
68
69#ifdef CONFIG_PCI_MSI
70
08fb1055 71static int msi_x = 1;
225c7b1f
RD		 72module_param(msi_x, int, 0444);
73MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74
75#else /* CONFIG_PCI_MSI */
76
77#define msi_x (0)
78
79#endif /* CONFIG_PCI_MSI */
80
ab9c17a0
JM		 81static int num_vfs;
82module_param(num_vfs, int, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
84
85static int probe_vf;
86module_param(probe_vf, int, 0644);
87MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
88
3c439b55 89int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 90module_param_named(log_num_mgm_entry_size,
91 mlx4_log_num_mgm_entry_size, int, 0444);
92MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
93 " of qp per mcg, for example:"
3c439b55 94 " 10 gives 248.range: 7 <="
0ff1fb65 95 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 96 " To activate device managed"
97 " flow steering when available, set to -1");
0ec2c0f8 98
be902ab1 99static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 100module_param(enable_64b_cqe_eqe, bool, 0444);
101MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 102 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 103
ab9c17a0 104#define HCA_GLOBAL_CAP_MASK 0
08ff3235
OG		 105
106#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
ab9c17a0 107
f57e6848 108static char mlx4_version[] =
225c7b1f
RD		 109 DRV_NAME ": Mellanox ConnectX core driver v"
110 DRV_VERSION " (" DRV_RELDATE ")\n";
111
112static struct mlx4_profile default_profile = {
ab9c17a0 113 .num_qp = 1 << 18,
225c7b1f 114 .num_srq = 1 << 16,
c9f2ba5e 115 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 116 .num_cq = 1 << 16,
117 .num_mcg = 1 << 13,
ab9c17a0 118 .num_mpt = 1 << 19,
9fd7a1e1 119 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 120};
121
ab9c17a0 122static int log_num_mac = 7;
93fc9e1b
YP		 123module_param_named(log_num_mac, log_num_mac, int, 0444);
124MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
125
126static int log_num_vlan;
127module_param_named(log_num_vlan, log_num_vlan, int, 0444);
128MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 129/* Log2 max number of VLANs per ETH port (0-7) */
130#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 131
eb939922 132static bool use_prio;
93fc9e1b
YP		 133module_param_named(use_prio, use_prio, bool, 0444);
134MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
135 "(0/1, default 0)");
136
2b8fb286 137int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 138module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 139MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 140
8d0fc7b6 141static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 142static int arr_argc = 2;
143module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 144MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
145 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 146
147struct mlx4_port_config {
148 struct list_head list;
149 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
150 struct pci_dev *pdev;
151};
152
97989356
AV		 153static atomic_t pf_loading = ATOMIC_INIT(0);
154
27bf91d6
YP		 155int mlx4_check_port_params(struct mlx4_dev *dev,
156 enum mlx4_port_type *port_type)
7ff93f8b
YP		 157{
158 int i;
159
160 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 161 if (port_type[i] != port_type[i + 1]) {
162 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
163 mlx4_err(dev, "Only same port types supported "
164 "on this HCA, aborting.\n");
165 return -EINVAL;
166 }
7ff93f8b
YP		 167 }
168 }
7ff93f8b
YP		 169
170 for (i = 0; i < dev->caps.num_ports; i++) {
171 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
172 mlx4_err(dev, "Requested port type for port %d is not "
173 "supported on this HCA\n", i + 1);
174 return -EINVAL;
175 }
176 }
177 return 0;
178}
179
180static void mlx4_set_port_mask(struct mlx4_dev *dev)
181{
182 int i;
183
7ff93f8b 184 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 185 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 186}
f2a3f6a3 187
3d73c288 188static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 189{
190 int err;
5ae2a7a8 191 int i;
225c7b1f
RD		 192
193 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
194 if (err) {
195 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
196 return err;
197 }
198
199 if (dev_cap->min_page_sz > PAGE_SIZE) {
200 mlx4_err(dev, "HCA minimum page size of %d bigger than "
201 "kernel PAGE_SIZE of %ld, aborting.\n",
202 dev_cap->min_page_sz, PAGE_SIZE);
203 return -ENODEV;
204 }
205 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
206 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
207 "aborting.\n",
208 dev_cap->num_ports, MLX4_MAX_PORTS);
209 return -ENODEV;
210 }
211
212 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
213 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
214 "PCI resource 2 size of 0x%llx, aborting.\n",
215 dev_cap->uar_size,
216 (unsigned long long) pci_resource_len(dev->pdev, 2));
217 return -ENODEV;
218 }
219
220 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 221 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 222 for (i = 1; i <= dev->caps.num_ports; ++i) {
223 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 224 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 225 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
226 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
227 /* set gid and pkey table operating lengths by default
228 * to non-sriov values */
5ae2a7a8
RD		 229 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
230 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
231 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 232 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
233 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 234 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 235 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
236 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 237 dev->caps.trans_type[i] = dev_cap->trans_type[i];
238 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
239 dev->caps.wavelength[i] = dev_cap->wavelength[i];
240 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 241 }
242
ab9c17a0 243 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 244 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 245 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
246 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
247 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
248 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
249 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
250 dev->caps.max_wqes = dev_cap->max_qp_sz;
251 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 252 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
253 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
254 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
255 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
256 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 257 /*
258 * Subtract 1 from the limit because we need to allocate a
259 * spare CQE so the HCA HW can tell the difference between an
260 * empty CQ and a full CQ.
261 */
262 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
263 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
264 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 265 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 266 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 267
268 /* The first 128 UARs are used for EQ doorbells */
269 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 270 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 271 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
272 dev_cap->reserved_xrcds : 0;
273 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
274 dev_cap->max_xrcds : 0;
2b8fb286
MA		 275 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
276
149983af 277 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 278 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
279 dev->caps.flags = dev_cap->flags;
b3416f44 280 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 281 dev->caps.bmme_flags = dev_cap->bmme_flags;
282 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 283 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 284 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 285 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 286
ca3e57a5
RD		 287 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
288 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 289 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 290 /* Don't do sense port on multifunction devices (for now at least) */
291 if (mlx4_is_mfunc(dev))
292 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 293
93fc9e1b 294 dev->caps.log_num_macs = log_num_mac;
cb29688a 295 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 296 dev->caps.log_num_prios = use_prio ? 3 : 0;
297
298 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 299 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
300 if (dev->caps.supported_type[i]) {
301 /* if only ETH is supported - assign ETH */
302 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
303 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 304 /* if only IB is supported, assign IB */
ab9c17a0 305 else if (dev->caps.supported_type[i] ==
105c320f
JM		 306 MLX4_PORT_TYPE_IB)
307 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 308 else {
105c320f
JM		 309 /* if IB and ETH are supported, we set the port
310 * type according to user selection of port type;
311 * if user selected none, take the FW hint */
312 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 313 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
314 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 315 else
105c320f 316 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 317 }
318 }
8d0fc7b6
YP		 319 /*
320 * Link sensing is allowed on the port if 3 conditions are true:
321 * 1. Both protocols are supported on the port.
322 * 2. Different types are supported on the port
323 * 3. FW declared that it supports link sensing
324 */
27bf91d6 325 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 326 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 327 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 328 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 329
8d0fc7b6
YP		 330 /*
331 * If "default_sense" bit is set, we move the port to "AUTO" mode
332 * and perform sense_port FW command to try and set the correct
333 * port type from beginning
334 */
46c46747 335 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 336 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
337 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
338 mlx4_SENSE_PORT(dev, i, &sensed_port);
339 if (sensed_port != MLX4_PORT_TYPE_NONE)
340 dev->caps.port_type[i] = sensed_port;
341 } else {
342 dev->caps.possible_type[i] = dev->caps.port_type[i];
343 }
344
93fc9e1b
YP		 345 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
346 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
347 mlx4_warn(dev, "Requested number of MACs is too much "
348 "for port %d, reducing to %d.\n",
349 i, 1 << dev->caps.log_num_macs);
350 }
351 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
352 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
353 mlx4_warn(dev, "Requested number of VLANs is too much "
354 "for port %d, reducing to %d.\n",
355 i, 1 << dev->caps.log_num_vlans);
356 }
357 }
358
f2a3f6a3
OG		 359 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
360
93fc9e1b
YP		 361 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
362 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
363 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
364 (1 << dev->caps.log_num_macs) *
365 (1 << dev->caps.log_num_vlans) *
366 (1 << dev->caps.log_num_prios) *
367 dev->caps.num_ports;
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
369
370 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
372 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
374
e2c76824 375 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 376
b3051320 377 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 378 if (dev_cap->flags &
379 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
380 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
381 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
382 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
383 }
384 }
385
f97b4b5d 386 if ((dev->caps.flags &
08ff3235
OG		 387 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
388 mlx4_is_master(dev))
389 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
390
225c7b1f
RD		 391 return 0;
392}
b912b2f8
EP		 393
394static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
395 enum pci_bus_speed *speed,
396 enum pcie_link_width *width)
397{
398 u32 lnkcap1, lnkcap2;
399 int err1, err2;
400
401#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
402
403 *speed = PCI_SPEED_UNKNOWN;
404 *width = PCIE_LNK_WIDTH_UNKNOWN;
405
406 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
407 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
408 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
409 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
410 *speed = PCIE_SPEED_8_0GT;
411 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
412 *speed = PCIE_SPEED_5_0GT;
413 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
414 *speed = PCIE_SPEED_2_5GT;
415 }
416 if (!err1) {
417 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
418 if (!lnkcap2) { /* pre-r3.0 */
419 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
420 *speed = PCIE_SPEED_5_0GT;
421 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
422 *speed = PCIE_SPEED_2_5GT;
423 }
424 }
425
426 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
427 return err1 ? err1 :
428 err2 ? err2 : -EINVAL;
429 }
430 return 0;
431}
432
433static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
434{
435 enum pcie_link_width width, width_cap;
436 enum pci_bus_speed speed, speed_cap;
437 int err;
438
439#define PCIE_SPEED_STR(speed) \
440 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
441 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
442 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
443 "Unknown")
444
445 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
446 if (err) {
447 mlx4_warn(dev,
448 "Unable to determine PCIe device BW capabilities\n");
449 return;
450 }
451
452 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
453 if (err || speed == PCI_SPEED_UNKNOWN ||
454 width == PCIE_LNK_WIDTH_UNKNOWN) {
455 mlx4_warn(dev,
456 "Unable to determine PCI device chain minimum BW\n");
457 return;
458 }
459
460 if (width != width_cap || speed != speed_cap)
461 mlx4_warn(dev,
462 "PCIe BW is different than device's capability\n");
463
464 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
465 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
466 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
467 width, width_cap);
468 return;
469}
470
ab9c17a0
JM		 471/*The function checks if there are live vf, return the num of them*/
472static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
473{
474 struct mlx4_priv *priv = mlx4_priv(dev);
475 struct mlx4_slave_state *s_state;
476 int i;
477 int ret = 0;
478
479 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
480 s_state = &priv->mfunc.master.slave_state[i];
481 if (s_state->active && s_state->last_cmd !=
482 MLX4_COMM_CMD_RESET) {
483 mlx4_warn(dev, "%s: slave: %d is still active\n",
484 __func__, i);
485 ret++;
486 }
487 }
488 return ret;
489}
490
396f2feb
JM		 491int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
492{
493 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 494
495 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
496 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 497 return -EINVAL;
498
47605df9 499 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 500 /* tunnel qp */
47605df9 501 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 502 else
47605df9 503 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 504 *qkey = qk;
505 return 0;
506}
507EXPORT_SYMBOL(mlx4_get_parav_qkey);
508
54679e14
JM		 509void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
510{
511 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
512
513 if (!mlx4_is_master(dev))
514 return;
515
516 priv->virt2phys_pkey[slave][port - 1][i] = val;
517}
518EXPORT_SYMBOL(mlx4_sync_pkey_table);
519
afa8fd1d
JM		 520void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
521{
522 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
523
524 if (!mlx4_is_master(dev))
525 return;
526
527 priv->slave_node_guids[slave] = guid;
528}
529EXPORT_SYMBOL(mlx4_put_slave_node_guid);
530
531__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
532{
533 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
534
535 if (!mlx4_is_master(dev))
536 return 0;
537
538 return priv->slave_node_guids[slave];
539}
540EXPORT_SYMBOL(mlx4_get_slave_node_guid);
541
e10903b0 542int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 543{
544 struct mlx4_priv *priv = mlx4_priv(dev);
545 struct mlx4_slave_state *s_slave;
546
547 if (!mlx4_is_master(dev))
548 return 0;
549
550 s_slave = &priv->mfunc.master.slave_state[slave];
551 return !!s_slave->active;
552}
553EXPORT_SYMBOL(mlx4_is_slave_active);
554
7b8157be
JM		 555static void slave_adjust_steering_mode(struct mlx4_dev *dev,
556 struct mlx4_dev_cap *dev_cap,
557 struct mlx4_init_hca_param *hca_param)
558{
559 dev->caps.steering_mode = hca_param->steering_mode;
560 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
561 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
562 dev->caps.fs_log_max_ucast_qp_range_size =
563 dev_cap->fs_log_max_ucast_qp_range_size;
564 } else
565 dev->caps.num_qp_per_mgm =
566 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
567
568 mlx4_dbg(dev, "Steering mode is: %s\n",
569 mlx4_steering_mode_str(dev->caps.steering_mode));
570}
571
ab9c17a0
JM		 572static int mlx4_slave_cap(struct mlx4_dev *dev)
573{
574 int err;
575 u32 page_size;
576 struct mlx4_dev_cap dev_cap;
577 struct mlx4_func_cap func_cap;
578 struct mlx4_init_hca_param hca_param;
579 int i;
580
581 memset(&hca_param, 0, sizeof(hca_param));
582 err = mlx4_QUERY_HCA(dev, &hca_param);
583 if (err) {
584 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
585 return err;
586 }
587
588 /*fail if the hca has an unknown capability */
589 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
590 HCA_GLOBAL_CAP_MASK) {
591 mlx4_err(dev, "Unknown hca global capabilities\n");
592 return -ENOSYS;
593 }
594
595 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
596
ddd8a6c1
EE		 597 dev->caps.hca_core_clock = hca_param.hca_core_clock;
598
ab9c17a0 599 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 600 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 601 err = mlx4_dev_cap(dev, &dev_cap);
602 if (err) {
603 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
604 return err;
605 }
606
b91cb3eb
JM		 607 err = mlx4_QUERY_FW(dev);
608 if (err)
609 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
610
ab9c17a0
JM		 611 page_size = ~dev->caps.page_size_cap + 1;
612 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
613 if (page_size > PAGE_SIZE) {
614 mlx4_err(dev, "HCA minimum page size of %d bigger than "
615 "kernel PAGE_SIZE of %ld, aborting.\n",
616 page_size, PAGE_SIZE);
617 return -ENODEV;
618 }
619
620 /* slave gets uar page size from QUERY_HCA fw command */
621 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
622
623 /* TODO: relax this assumption */
624 if (dev->caps.uar_page_size != PAGE_SIZE) {
625 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
626 dev->caps.uar_page_size, PAGE_SIZE);
627 return -ENODEV;
628 }
629
630 memset(&func_cap, 0, sizeof(func_cap));
47605df9 631 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 632 if (err) {
47605df9
JM		 633 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
634 err);
ab9c17a0
JM		 635 return err;
636 }
637
638 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
639 PF_CONTEXT_BEHAVIOUR_MASK) {
640 mlx4_err(dev, "Unknown pf context behaviour\n");
641 return -ENOSYS;
642 }
643
ab9c17a0 644 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 645 dev->quotas.qp = func_cap.qp_quota;
646 dev->quotas.srq = func_cap.srq_quota;
647 dev->quotas.cq = func_cap.cq_quota;
648 dev->quotas.mpt = func_cap.mpt_quota;
649 dev->quotas.mtt = func_cap.mtt_quota;
650 dev->caps.num_qps = 1 << hca_param.log_num_qps;
651 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
652 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
653 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
654 dev->caps.num_eqs = func_cap.max_eq;
655 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 656 dev->caps.num_pds = MLX4_NUM_PDS;
657 dev->caps.num_mgms = 0;
658 dev->caps.num_amgms = 0;
659
ab9c17a0
JM		 660 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
661 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
662 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
663 return -ENODEV;
664 }
665
47605df9
JM		 666 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
667 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
668 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
669 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
670
671 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
672 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
673 err = -ENOMEM;
674 goto err_mem;
675 }
676
6634961c 677 for (i = 1; i <= dev->caps.num_ports; ++i) {
47605df9
JM		 678 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
679 if (err) {
680 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
681 " port %d, aborting (%d).\n", i, err);
682 goto err_mem;
683 }
684 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
685 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
686 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
687 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 688 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 689 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 690 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
691 &dev->caps.gid_table_len[i],
692 &dev->caps.pkey_table_len[i]))
47605df9 693 goto err_mem;
6634961c 694 }
6230bb23 695
ab9c17a0
JM		 696 if (dev->caps.uar_page_size * (dev->caps.num_uars -
697 dev->caps.reserved_uars) >
698 pci_resource_len(dev->pdev, 2)) {
699 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
700 "PCI resource 2 size of 0x%llx, aborting.\n",
701 dev->caps.uar_page_size * dev->caps.num_uars,
702 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 703 goto err_mem;
ab9c17a0
JM		 704 }
705
08ff3235
OG		 706 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
707 dev->caps.eqe_size = 64;
708 dev->caps.eqe_factor = 1;
709 } else {
710 dev->caps.eqe_size = 32;
711 dev->caps.eqe_factor = 0;
712 }
713
714 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
715 dev->caps.cqe_size = 64;
716 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
717 } else {
718 dev->caps.cqe_size = 32;
719 }
720
f9bd2d7f
AV		 721 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
722 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
723
7b8157be
JM		 724 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
725
ab9c17a0 726 return 0;
47605df9
JM		 727
728err_mem:
729 kfree(dev->caps.qp0_tunnel);
730 kfree(dev->caps.qp0_proxy);
731 kfree(dev->caps.qp1_tunnel);
732 kfree(dev->caps.qp1_proxy);
733 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
734 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
735
736 return err;
ab9c17a0 737}
225c7b1f 738
b046ffe5
EP		 739static void mlx4_request_modules(struct mlx4_dev *dev)
740{
741 int port;
742 int has_ib_port = false;
743 int has_eth_port = false;
744#define EN_DRV_NAME "mlx4_en"
745#define IB_DRV_NAME "mlx4_ib"
746
747 for (port = 1; port <= dev->caps.num_ports; port++) {
748 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
749 has_ib_port = true;
750 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
751 has_eth_port = true;
752 }
753
7855bff4 754 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
b046ffe5
EP		 755 request_module_nowait(IB_DRV_NAME);
756 if (has_eth_port)
757 request_module_nowait(EN_DRV_NAME);
758}
759
7ff93f8b
YP		 760/*
761 * Change the port configuration of the device.
762 * Every user of this function must hold the port mutex.
763 */
27bf91d6
YP		 764int mlx4_change_port_types(struct mlx4_dev *dev,
765 enum mlx4_port_type *port_types)
7ff93f8b
YP		 766{
767 int err = 0;
768 int change = 0;
769 int port;
770
771 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 772 /* Change the port type only if the new type is different
773 * from the current, and not set to Auto */
3d8f9308 774 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 775 change = 1;
7ff93f8b
YP		 776 }
777 if (change) {
778 mlx4_unregister_device(dev);
779 for (port = 1; port <= dev->caps.num_ports; port++) {
780 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 781 dev->caps.port_type[port] = port_types[port - 1];
6634961c 782 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b
YP		 783 if (err) {
784 mlx4_err(dev, "Failed to set port %d, "
785 "aborting\n", port);
786 goto out;
787 }
788 }
789 mlx4_set_port_mask(dev);
790 err = mlx4_register_device(dev);
b046ffe5
EP		 791 if (err) {
792 mlx4_err(dev, "Failed to register device\n");
793 goto out;
794 }
795 mlx4_request_modules(dev);
7ff93f8b
YP		 796 }
797
798out:
799 return err;
800}
801
802static ssize_t show_port_type(struct device *dev,
803 struct device_attribute *attr,
804 char *buf)
805{
806 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
807 port_attr);
808 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 809 char type[8];
810
811 sprintf(type, "%s",
812 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
813 "ib" : "eth");
814 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
815 sprintf(buf, "auto (%s)\n", type);
816 else
817 sprintf(buf, "%s\n", type);
7ff93f8b 818
27bf91d6 819 return strlen(buf);
7ff93f8b
YP		 820}
821
822static ssize_t set_port_type(struct device *dev,
823 struct device_attribute *attr,
824 const char *buf, size_t count)
825{
826 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
827 port_attr);
828 struct mlx4_dev *mdev = info->dev;
829 struct mlx4_priv *priv = mlx4_priv(mdev);
830 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 831 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 832 int i;
833 int err = 0;
834
835 if (!strcmp(buf, "ib\n"))
836 info->tmp_type = MLX4_PORT_TYPE_IB;
837 else if (!strcmp(buf, "eth\n"))
838 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 839 else if (!strcmp(buf, "auto\n"))
840 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 841 else {
842 mlx4_err(mdev, "%s is not supported port type\n", buf);
843 return -EINVAL;
844 }
845
27bf91d6 846 mlx4_stop_sense(mdev);
7ff93f8b 847 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 848 /* Possible type is always the one that was delivered */
849 mdev->caps.possible_type[info->port] = info->tmp_type;
850
851 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 852 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 853 mdev->caps.possible_type[i+1];
854 if (types[i] == MLX4_PORT_TYPE_AUTO)
855 types[i] = mdev->caps.port_type[i+1];
856 }
7ff93f8b 857
58a60168
YP		 858 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
859 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 860 for (i = 1; i <= mdev->caps.num_ports; i++) {
861 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
862 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
863 err = -EINVAL;
864 }
865 }
866 }
867 if (err) {
868 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
869 "Set only 'eth' or 'ib' for both ports "
870 "(should be the same)\n");
871 goto out;
872 }
873
874 mlx4_do_sense_ports(mdev, new_types, types);
875
876 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 877 if (err)
878 goto out;
879
27bf91d6
YP		 880 /* We are about to apply the changes after the configuration
881 * was verified, no need to remember the temporary types
882 * any more */
883 for (i = 0; i < mdev->caps.num_ports; i++)
884 priv->port[i + 1].tmp_type = 0;
7ff93f8b 885
27bf91d6 886 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 887
888out:
27bf91d6 889 mlx4_start_sense(mdev);
7ff93f8b
YP		 890 mutex_unlock(&priv->port_mutex);
891 return err ? err : count;
892}
893
096335b3
OG		 894enum ibta_mtu {
895 IB_MTU_256 = 1,
896 IB_MTU_512 = 2,
897 IB_MTU_1024 = 3,
898 IB_MTU_2048 = 4,
899 IB_MTU_4096 = 5
900};
901
902static inline int int_to_ibta_mtu(int mtu)
903{
904 switch (mtu) {
905 case 256: return IB_MTU_256;
906 case 512: return IB_MTU_512;
907 case 1024: return IB_MTU_1024;
908 case 2048: return IB_MTU_2048;
909 case 4096: return IB_MTU_4096;
910 default: return -1;
911 }
912}
913
914static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
915{
916 switch (mtu) {
917 case IB_MTU_256: return 256;
918 case IB_MTU_512: return 512;
919 case IB_MTU_1024: return 1024;
920 case IB_MTU_2048: return 2048;
921 case IB_MTU_4096: return 4096;
922 default: return -1;
923 }
924}
925
926static ssize_t show_port_ib_mtu(struct device *dev,
927 struct device_attribute *attr,
928 char *buf)
929{
930 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
931 port_mtu_attr);
932 struct mlx4_dev *mdev = info->dev;
933
934 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
935 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
936
937 sprintf(buf, "%d\n",
938 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
939 return strlen(buf);
940}
941
942static ssize_t set_port_ib_mtu(struct device *dev,
943 struct device_attribute *attr,
944 const char *buf, size_t count)
945{
946 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
947 port_mtu_attr);
948 struct mlx4_dev *mdev = info->dev;
949 struct mlx4_priv *priv = mlx4_priv(mdev);
950 int err, port, mtu, ibta_mtu = -1;
951
952 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
953 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
954 return -EINVAL;
955 }
956
618fad95
DB		 957 err = kstrtoint(buf, 0, &mtu);
958 if (!err)
096335b3
OG		 959 ibta_mtu = int_to_ibta_mtu(mtu);
960
618fad95 961 if (err || ibta_mtu < 0) {
096335b3
OG		 962 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
963 return -EINVAL;
964 }
965
966 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
967
968 mlx4_stop_sense(mdev);
969 mutex_lock(&priv->port_mutex);
970 mlx4_unregister_device(mdev);
971 for (port = 1; port <= mdev->caps.num_ports; port++) {
972 mlx4_CLOSE_PORT(mdev, port);
6634961c 973 err = mlx4_SET_PORT(mdev, port, -1);
096335b3
OG		 974 if (err) {
975 mlx4_err(mdev, "Failed to set port %d, "
976 "aborting\n", port);
977 goto err_set_port;
978 }
979 }
980 err = mlx4_register_device(mdev);
981err_set_port:
982 mutex_unlock(&priv->port_mutex);
983 mlx4_start_sense(mdev);
984 return err ? err : count;
985}
986
e8f9b2ed 987static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 988{
989 struct mlx4_priv *priv = mlx4_priv(dev);
990 int err;
991
992 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 993 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 994 if (!priv->fw.fw_icm) {
995 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
996 return -ENOMEM;
997 }
998
999 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1000 if (err) {
1001 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1002 goto err_free;
1003 }
1004
1005 err = mlx4_RUN_FW(dev);
1006 if (err) {
1007 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1008 goto err_unmap_fa;
1009 }
1010
1011 return 0;
1012
1013err_unmap_fa:
1014 mlx4_UNMAP_FA(dev);
1015
1016err_free:
5b0bf5e2 1017 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1018 return err;
1019}
1020
e8f9b2ed
RD		 1021static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1022 int cmpt_entry_sz)
225c7b1f
RD		 1023{
1024 struct mlx4_priv *priv = mlx4_priv(dev);
1025 int err;
ab9c17a0 1026 int num_eqs;
225c7b1f
RD		 1027
1028 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1029 cmpt_base +
1030 ((u64) (MLX4_CMPT_TYPE_QP *
1031 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1032 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1033 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1034 0, 0);
225c7b1f
RD		 1035 if (err)
1036 goto err;
1037
1038 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1039 cmpt_base +
1040 ((u64) (MLX4_CMPT_TYPE_SRQ *
1041 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1042 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1043 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1044 if (err)
1045 goto err_qp;
1046
1047 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1048 cmpt_base +
1049 ((u64) (MLX4_CMPT_TYPE_CQ *
1050 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1051 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1052 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1053 if (err)
1054 goto err_srq;
1055
3fc929e2
MA		 1056 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1057 dev->caps.num_eqs;
225c7b1f
RD		 1058 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1059 cmpt_base +
1060 ((u64) (MLX4_CMPT_TYPE_EQ *
1061 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1062 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1063 if (err)
1064 goto err_cq;
1065
1066 return 0;
1067
1068err_cq:
1069 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1070
1071err_srq:
1072 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1073
1074err_qp:
1075 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1076
1077err:
1078 return err;
1079}
1080
3d73c288
RD		 1081static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1082 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1083{
1084 struct mlx4_priv *priv = mlx4_priv(dev);
1085 u64 aux_pages;
ab9c17a0 1086 int num_eqs;
225c7b1f
RD		 1087 int err;
1088
1089 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1090 if (err) {
1091 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1092 return err;
1093 }
1094
1095 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1096 (unsigned long long) icm_size >> 10,
1097 (unsigned long long) aux_pages << 2);
1098
1099 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1100 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 1101 if (!priv->fw.aux_icm) {
1102 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1103 return -ENOMEM;
1104 }
1105
1106 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1107 if (err) {
1108 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1109 goto err_free_aux;
1110 }
1111
1112 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1113 if (err) {
1114 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1115 goto err_unmap_aux;
1116 }
1117
ab9c17a0 1118
3fc929e2
MA		 1119 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1120 dev->caps.num_eqs;
fa0681d2
RD		 1121 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1122 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1123 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1124 if (err) {
1125 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1126 goto err_unmap_cmpt;
1127 }
1128
d7bb58fb
JM		 1129 /*
1130 * Reserved MTT entries must be aligned up to a cacheline
1131 * boundary, since the FW will write to them, while the driver
1132 * writes to all other MTT entries. (The variable
1133 * dev->caps.mtt_entry_sz below is really the MTT segment
1134 * size, not the raw entry size)
1135 */
1136 dev->caps.reserved_mtts =
1137 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1138 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1139
225c7b1f
RD		 1140 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1141 init_hca->mtt_base,
1142 dev->caps.mtt_entry_sz,
2b8fb286 1143 dev->caps.num_mtts,
5b0bf5e2 1144 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 1145 if (err) {
1146 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1147 goto err_unmap_eq;
1148 }
1149
1150 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1151 init_hca->dmpt_base,
1152 dev_cap->dmpt_entry_sz,
1153 dev->caps.num_mpts,
5b0bf5e2 1154 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 1155 if (err) {
1156 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1157 goto err_unmap_mtt;
1158 }
1159
1160 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1161 init_hca->qpc_base,
1162 dev_cap->qpc_entry_sz,
1163 dev->caps.num_qps,
93fc9e1b
YP		 1164 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1165 0, 0);
225c7b1f
RD		 1166 if (err) {
1167 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1168 goto err_unmap_dmpt;
1169 }
1170
1171 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1172 init_hca->auxc_base,
1173 dev_cap->aux_entry_sz,
1174 dev->caps.num_qps,
93fc9e1b
YP		 1175 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1176 0, 0);
225c7b1f
RD		 1177 if (err) {
1178 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1179 goto err_unmap_qp;
1180 }
1181
1182 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1183 init_hca->altc_base,
1184 dev_cap->altc_entry_sz,
1185 dev->caps.num_qps,
93fc9e1b
YP		 1186 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1187 0, 0);
225c7b1f
RD		 1188 if (err) {
1189 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1190 goto err_unmap_auxc;
1191 }
1192
1193 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1194 init_hca->rdmarc_base,
1195 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1196 dev->caps.num_qps,
93fc9e1b
YP		 1197 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1198 0, 0);
225c7b1f
RD		 1199 if (err) {
1200 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1201 goto err_unmap_altc;
1202 }
1203
1204 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1205 init_hca->cqc_base,
1206 dev_cap->cqc_entry_sz,
1207 dev->caps.num_cqs,
5b0bf5e2 1208 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1209 if (err) {
1210 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1211 goto err_unmap_rdmarc;
1212 }
1213
1214 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1215 init_hca->srqc_base,
1216 dev_cap->srq_entry_sz,
1217 dev->caps.num_srqs,
5b0bf5e2 1218 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1219 if (err) {
1220 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1221 goto err_unmap_cq;
1222 }
1223
1224 /*
0ff1fb65
HHZ		 1225 * For flow steering device managed mode it is required to use
1226 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1227 * required, but for simplicity just map the whole multicast
1228 * group table now. The table isn't very big and it's a lot
1229 * easier than trying to track ref counts.
225c7b1f
RD		 1230 */
1231 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1232 init_hca->mc_base,
1233 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1234 dev->caps.num_mgms + dev->caps.num_amgms,
1235 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1236 0, 0);
225c7b1f
RD		 1237 if (err) {
1238 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1239 goto err_unmap_srq;
1240 }
1241
1242 return 0;
1243
1244err_unmap_srq:
1245 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1246
1247err_unmap_cq:
1248 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1249
1250err_unmap_rdmarc:
1251 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1252
1253err_unmap_altc:
1254 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1255
1256err_unmap_auxc:
1257 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1258
1259err_unmap_qp:
1260 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1261
1262err_unmap_dmpt:
1263 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1264
1265err_unmap_mtt:
1266 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1267
1268err_unmap_eq:
fa0681d2 1269 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1270
1271err_unmap_cmpt:
1272 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1273 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1274 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1275 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1276
1277err_unmap_aux:
1278 mlx4_UNMAP_ICM_AUX(dev);
1279
1280err_free_aux:
5b0bf5e2 1281 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1282
1283 return err;
1284}
1285
1286static void mlx4_free_icms(struct mlx4_dev *dev)
1287{
1288 struct mlx4_priv *priv = mlx4_priv(dev);
1289
1290 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1291 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1292 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1293 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1294 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1295 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1296 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1297 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1298 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1299 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1300 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1301 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1302 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1303 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1304
1305 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1306 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1307}
1308
ab9c17a0
JM		 1309static void mlx4_slave_exit(struct mlx4_dev *dev)
1310{
1311 struct mlx4_priv *priv = mlx4_priv(dev);
1312
f3d4c89e 1313 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1314 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1315 mlx4_warn(dev, "Failed to close slave function.\n");
f3d4c89e 1316 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1317}
1318
c1b43dca
EC		 1319static int map_bf_area(struct mlx4_dev *dev)
1320{
1321 struct mlx4_priv *priv = mlx4_priv(dev);
1322 resource_size_t bf_start;
1323 resource_size_t bf_len;
1324 int err = 0;
1325
3d747473
JM		 1326 if (!dev->caps.bf_reg_size)
1327 return -ENXIO;
1328
ab9c17a0
JM		 1329 bf_start = pci_resource_start(dev->pdev, 2) +
1330 (dev->caps.num_uars << PAGE_SHIFT);
1331 bf_len = pci_resource_len(dev->pdev, 2) -
1332 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1333 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1334 if (!priv->bf_mapping)
1335 err = -ENOMEM;
1336
1337 return err;
1338}
1339
1340static void unmap_bf_area(struct mlx4_dev *dev)
1341{
1342 if (mlx4_priv(dev)->bf_mapping)
1343 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1344}
1345
ec693d47
AV		 1346cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1347{
1348 u32 clockhi, clocklo, clockhi1;
1349 cycle_t cycles;
1350 int i;
1351 struct mlx4_priv *priv = mlx4_priv(dev);
1352
1353 for (i = 0; i < 10; i++) {
1354 clockhi = swab32(readl(priv->clock_mapping));
1355 clocklo = swab32(readl(priv->clock_mapping + 4));
1356 clockhi1 = swab32(readl(priv->clock_mapping));
1357 if (clockhi == clockhi1)
1358 break;
1359 }
1360
1361 cycles = (u64) clockhi << 32 | (u64) clocklo;
1362
1363 return cycles;
1364}
1365EXPORT_SYMBOL_GPL(mlx4_read_clock);
1366
1367
ddd8a6c1
EE		 1368static int map_internal_clock(struct mlx4_dev *dev)
1369{
1370 struct mlx4_priv *priv = mlx4_priv(dev);
1371
1372 priv->clock_mapping =
1373 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1374 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1375
1376 if (!priv->clock_mapping)
1377 return -ENOMEM;
1378
1379 return 0;
1380}
1381
1382static void unmap_internal_clock(struct mlx4_dev *dev)
1383{
1384 struct mlx4_priv *priv = mlx4_priv(dev);
1385
1386 if (priv->clock_mapping)
1387 iounmap(priv->clock_mapping);
1388}
1389
225c7b1f
RD		 1390static void mlx4_close_hca(struct mlx4_dev *dev)
1391{
ddd8a6c1 1392 unmap_internal_clock(dev);
c1b43dca 1393 unmap_bf_area(dev);
ab9c17a0
JM		 1394 if (mlx4_is_slave(dev))
1395 mlx4_slave_exit(dev);
1396 else {
1397 mlx4_CLOSE_HCA(dev, 0);
1398 mlx4_free_icms(dev);
1399 mlx4_UNMAP_FA(dev);
1400 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1401 }
1402}
1403
1404static int mlx4_init_slave(struct mlx4_dev *dev)
1405{
1406 struct mlx4_priv *priv = mlx4_priv(dev);
1407 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1408 int ret_from_reset = 0;
1409 u32 slave_read;
1410 u32 cmd_channel_ver;
1411
97989356
AV		 1412 if (atomic_read(&pf_loading)) {
1413 mlx4_warn(dev, "PF is not ready. Deferring probe\n");
1414 return -EPROBE_DEFER;
1415 }
1416
f3d4c89e 1417 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1418 priv->cmd.max_cmds = 1;
1419 mlx4_warn(dev, "Sending reset\n");
1420 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1421 MLX4_COMM_TIME);
1422 /* if we are in the middle of flr the slave will try
1423 * NUM_OF_RESET_RETRIES times before leaving.*/
1424 if (ret_from_reset) {
1425 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
5efe5355
JM		 1426 mlx4_warn(dev, "slave is currently in the "
1427 "middle of FLR. Deferring probe.\n");
1428 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1429 return -EPROBE_DEFER;
ab9c17a0
JM		 1430 } else
1431 goto err;
1432 }
1433
1434 /* check the driver version - the slave I/F revision
1435 * must match the master's */
1436 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1437 cmd_channel_ver = mlx4_comm_get_version();
1438
1439 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1440 MLX4_COMM_GET_IF_REV(slave_read)) {
1441 mlx4_err(dev, "slave driver version is not supported"
1442 " by the master\n");
1443 goto err;
1444 }
1445
1446 mlx4_warn(dev, "Sending vhcr0\n");
1447 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1448 MLX4_COMM_TIME))
1449 goto err;
1450 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1451 MLX4_COMM_TIME))
1452 goto err;
1453 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1454 MLX4_COMM_TIME))
1455 goto err;
1456 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1457 goto err;
f3d4c89e
RD		 1458
1459 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1460 return 0;
1461
1462err:
1463 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1464 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1465 return -EIO;
225c7b1f
RD		 1466}
1467
6634961c
JM		 1468static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1469{
1470 int i;
1471
1472 for (i = 1; i <= dev->caps.num_ports; i++) {
1473 dev->caps.gid_table_len[i] = 1;
1474 dev->caps.pkey_table_len[i] =
1475 dev->phys_caps.pkey_phys_table_len[i] - 1;
1476 }
1477}
1478
3c439b55
JM		 1479static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1480{
1481 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1482
1483 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1484 i++) {
1485 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1486 break;
1487 }
1488
1489 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1490}
1491
7b8157be
JM		 1492static void choose_steering_mode(struct mlx4_dev *dev,
1493 struct mlx4_dev_cap *dev_cap)
1494{
3c439b55
JM		 1495 if (mlx4_log_num_mgm_entry_size == -1 &&
1496 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1497 (!mlx4_is_mfunc(dev) ||
3c439b55
JM		 1498 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1499 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1500 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1501 dev->oper_log_mgm_entry_size =
1502 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1503 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1504 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1505 dev->caps.fs_log_max_ucast_qp_range_size =
1506 dev_cap->fs_log_max_ucast_qp_range_size;
1507 } else {
1508 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1509 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1510 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1511 else {
1512 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1513
1514 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1515 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1516 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1517 "set to use B0 steering. Falling back to A0 steering mode.\n");
1518 }
3c439b55
JM		 1519 dev->oper_log_mgm_entry_size =
1520 mlx4_log_num_mgm_entry_size > 0 ?
1521 mlx4_log_num_mgm_entry_size :
1522 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1523 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1524 }
3c439b55
JM		 1525 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1526 "modparam log_num_mgm_entry_size = %d\n",
1527 mlx4_steering_mode_str(dev->caps.steering_mode),
1528 dev->oper_log_mgm_entry_size,
1529 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1530}
1531
7ffdf726
OG		 1532static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1533 struct mlx4_dev_cap *dev_cap)
1534{
1535 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1536 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1537 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1538 else
1539 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1540
1541 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1542 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1543}
1544
3d73c288 1545static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1546{
1547 struct mlx4_priv *priv = mlx4_priv(dev);
1548 struct mlx4_adapter adapter;
1549 struct mlx4_dev_cap dev_cap;
2d928651 1550 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1551 struct mlx4_profile profile;
1552 struct mlx4_init_hca_param init_hca;
1553 u64 icm_size;
1554 int err;
1555
ab9c17a0
JM		 1556 if (!mlx4_is_slave(dev)) {
1557 err = mlx4_QUERY_FW(dev);
1558 if (err) {
1559 if (err == -EACCES)
1560 mlx4_info(dev, "non-primary physical function, skipping.\n");
1561 else
1562 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
bef772eb 1563 return err;
ab9c17a0 1564 }
225c7b1f 1565
ab9c17a0
JM		 1566 err = mlx4_load_fw(dev);
1567 if (err) {
1568 mlx4_err(dev, "Failed to start FW, aborting.\n");
bef772eb 1569 return err;
ab9c17a0 1570 }
225c7b1f 1571
ab9c17a0
JM		 1572 mlx4_cfg.log_pg_sz_m = 1;
1573 mlx4_cfg.log_pg_sz = 0;
1574 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1575 if (err)
1576 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1577
ab9c17a0
JM		 1578 err = mlx4_dev_cap(dev, &dev_cap);
1579 if (err) {
1580 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1581 goto err_stop_fw;
1582 }
225c7b1f 1583
7b8157be 1584 choose_steering_mode(dev, &dev_cap);
7ffdf726 1585 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1586
8e1a28e8
HHZ		 1587 err = mlx4_get_phys_port_id(dev);
1588 if (err)
1589 mlx4_err(dev, "Fail to get physical port id\n");
1590
6634961c
JM		 1591 if (mlx4_is_master(dev))
1592 mlx4_parav_master_pf_caps(dev);
1593
ab9c17a0 1594 profile = default_profile;
0ff1fb65
HHZ		 1595 if (dev->caps.steering_mode ==
1596 MLX4_STEERING_MODE_DEVICE_MANAGED)
1597 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1598
ab9c17a0
JM		 1599 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1600 &init_hca);
1601 if ((long long) icm_size < 0) {
1602 err = icm_size;
1603 goto err_stop_fw;
1604 }
225c7b1f 1605
a5bbe892
EC		 1606 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1607
ab9c17a0
JM		 1608 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1609 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1610 init_hca.mw_enabled = 0;
1611 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1612 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1613 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1614
ab9c17a0
JM		 1615 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1616 if (err)
1617 goto err_stop_fw;
225c7b1f 1618
ab9c17a0
JM		 1619 err = mlx4_INIT_HCA(dev, &init_hca);
1620 if (err) {
1621 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1622 goto err_free_icm;
1623 }
ddd8a6c1
EE		 1624 /*
1625 * If TS is supported by FW
1626 * read HCA frequency by QUERY_HCA command
1627 */
1628 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1629 memset(&init_hca, 0, sizeof(init_hca));
1630 err = mlx4_QUERY_HCA(dev, &init_hca);
1631 if (err) {
1632 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1633 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1634 } else {
1635 dev->caps.hca_core_clock =
1636 init_hca.hca_core_clock;
1637 }
1638
1639 /* In case we got HCA frequency 0 - disable timestamping
1640 * to avoid dividing by zero
1641 */
1642 if (!dev->caps.hca_core_clock) {
1643 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1644 mlx4_err(dev,
1645 "HCA frequency is 0. Timestamping is not supported.");
1646 } else if (map_internal_clock(dev)) {
1647 /*
1648 * Map internal clock,
1649 * in case of failure disable timestamping
1650 */
1651 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1652 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1653 }
1654 }
ab9c17a0
JM		 1655 } else {
1656 err = mlx4_init_slave(dev);
1657 if (err) {
5efe5355
JM		 1658 if (err != -EPROBE_DEFER)
1659 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1660 return err;
ab9c17a0 1661 }
225c7b1f 1662
ab9c17a0
JM		 1663 err = mlx4_slave_cap(dev);
1664 if (err) {
1665 mlx4_err(dev, "Failed to obtain slave caps\n");
1666 goto err_close;
1667 }
225c7b1f
RD		 1668 }
1669
ab9c17a0
JM		 1670 if (map_bf_area(dev))
1671 mlx4_dbg(dev, "Failed to map blue flame area\n");
1672
1673 /*Only the master set the ports, all the rest got it from it.*/
1674 if (!mlx4_is_slave(dev))
1675 mlx4_set_port_mask(dev);
1676
225c7b1f
RD		 1677 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1678 if (err) {
1679 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
bef772eb 1680 goto unmap_bf;
225c7b1f
RD		 1681 }
1682
1683 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1684 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1685
1686 return 0;
1687
bef772eb 1688unmap_bf:
ddd8a6c1 1689 unmap_internal_clock(dev);
bef772eb
AY		 1690 unmap_bf_area(dev);
1691
225c7b1f 1692err_close:
41929ed2
DB		 1693 if (mlx4_is_slave(dev))
1694 mlx4_slave_exit(dev);
1695 else
1696 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1697
1698err_free_icm:
ab9c17a0
JM		 1699 if (!mlx4_is_slave(dev))
1700 mlx4_free_icms(dev);
225c7b1f
RD		 1701
1702err_stop_fw:
ab9c17a0
JM		 1703 if (!mlx4_is_slave(dev)) {
1704 mlx4_UNMAP_FA(dev);
1705 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1706 }
225c7b1f
RD		 1707 return err;
1708}
1709
f2a3f6a3
OG		 1710static int mlx4_init_counters_table(struct mlx4_dev *dev)
1711{
1712 struct mlx4_priv *priv = mlx4_priv(dev);
1713 int nent;
1714
1715 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1716 return -ENOENT;
1717
1718 nent = dev->caps.max_counters;
1719 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1720}
1721
1722static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1723{
1724 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1725}
1726
ba062d52 1727int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1728{
1729 struct mlx4_priv *priv = mlx4_priv(dev);
1730
1731 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1732 return -ENOENT;
1733
1734 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1735 if (*idx == -1)
1736 return -ENOMEM;
1737
1738 return 0;
1739}
ba062d52
JM		 1740
1741int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1742{
1743 u64 out_param;
1744 int err;
1745
1746 if (mlx4_is_mfunc(dev)) {
1747 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1748 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1749 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1750 if (!err)
1751 *idx = get_param_l(&out_param);
1752
1753 return err;
1754 }
1755 return __mlx4_counter_alloc(dev, idx);
1756}
f2a3f6a3
OG		 1757EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1758
ba062d52 1759void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 1760{
7c6d74d2 1761 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 1762 return;
1763}
ba062d52
JM		 1764
1765void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1766{
e7dbeba8 1767 u64 in_param = 0;
ba062d52
JM		 1768
1769 if (mlx4_is_mfunc(dev)) {
1770 set_param_l(&in_param, idx);
1771 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1772 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1773 MLX4_CMD_WRAPPED);
1774 return;
1775 }
1776 __mlx4_counter_free(dev, idx);
1777}
f2a3f6a3
OG		 1778EXPORT_SYMBOL_GPL(mlx4_counter_free);
1779
3d73c288 1780static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1781{
1782 struct mlx4_priv *priv = mlx4_priv(dev);
1783 int err;
7ff93f8b 1784 int port;
9a5aa622 1785 __be32 ib_port_default_caps;
225c7b1f 1786
225c7b1f
RD		 1787 err = mlx4_init_uar_table(dev);
1788 if (err) {
1789 mlx4_err(dev, "Failed to initialize "
1790 "user access region table, aborting.\n");
1791 return err;
1792 }
1793
1794 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1795 if (err) {
1796 mlx4_err(dev, "Failed to allocate driver access region, "
1797 "aborting.\n");
1798 goto err_uar_table_free;
1799 }
1800
4979d18f 1801 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1802 if (!priv->kar) {
1803 mlx4_err(dev, "Couldn't map kernel access region, "
1804 "aborting.\n");
1805 err = -ENOMEM;
1806 goto err_uar_free;
1807 }
1808
1809 err = mlx4_init_pd_table(dev);
1810 if (err) {
1811 mlx4_err(dev, "Failed to initialize "
1812 "protection domain table, aborting.\n");
1813 goto err_kar_unmap;
1814 }
1815
012a8ff5
SH		 1816 err = mlx4_init_xrcd_table(dev);
1817 if (err) {
1818 mlx4_err(dev, "Failed to initialize "
1819 "reliable connection domain table, aborting.\n");
1820 goto err_pd_table_free;
1821 }
1822
225c7b1f
RD		 1823 err = mlx4_init_mr_table(dev);
1824 if (err) {
1825 mlx4_err(dev, "Failed to initialize "
1826 "memory region table, aborting.\n");
012a8ff5 1827 goto err_xrcd_table_free;
225c7b1f
RD		 1828 }
1829
fe6f700d
YP		 1830 if (!mlx4_is_slave(dev)) {
1831 err = mlx4_init_mcg_table(dev);
1832 if (err) {
1833 mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1834 goto err_mr_table_free;
1835 }
1836 }
1837
225c7b1f
RD		 1838 err = mlx4_init_eq_table(dev);
1839 if (err) {
1840 mlx4_err(dev, "Failed to initialize "
1841 "event queue table, aborting.\n");
fe6f700d 1842 goto err_mcg_table_free;
225c7b1f
RD		 1843 }
1844
1845 err = mlx4_cmd_use_events(dev);
1846 if (err) {
1847 mlx4_err(dev, "Failed to switch to event-driven "
1848 "firmware commands, aborting.\n");
1849 goto err_eq_table_free;
1850 }
1851
1852 err = mlx4_NOP(dev);
1853 if (err) {
08fb1055
MT		 1854 if (dev->flags & MLX4_FLAG_MSI_X) {
1855 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1856 "interrupt IRQ %d).\n",
b8dd786f 1857 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1858 mlx4_warn(dev, "Trying again without MSI-X.\n");
1859 } else {
1860 mlx4_err(dev, "NOP command failed to generate interrupt "
1861 "(IRQ %d), aborting.\n",
b8dd786f 1862 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1863 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1864 }
225c7b1f
RD		 1865
1866 goto err_cmd_poll;
1867 }
1868
1869 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1870
1871 err = mlx4_init_cq_table(dev);
1872 if (err) {
1873 mlx4_err(dev, "Failed to initialize "
1874 "completion queue table, aborting.\n");
1875 goto err_cmd_poll;
1876 }
1877
1878 err = mlx4_init_srq_table(dev);
1879 if (err) {
1880 mlx4_err(dev, "Failed to initialize "
1881 "shared receive queue table, aborting.\n");
1882 goto err_cq_table_free;
1883 }
1884
1885 err = mlx4_init_qp_table(dev);
1886 if (err) {
1887 mlx4_err(dev, "Failed to initialize "
1888 "queue pair table, aborting.\n");
1889 goto err_srq_table_free;
1890 }
1891
f2a3f6a3
OG		 1892 err = mlx4_init_counters_table(dev);
1893 if (err && err != -ENOENT) {
1894 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
fe6f700d 1895 goto err_qp_table_free;
f2a3f6a3
OG		 1896 }
1897
ab9c17a0
JM		 1898 if (!mlx4_is_slave(dev)) {
1899 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1900 ib_port_default_caps = 0;
1901 err = mlx4_get_port_ib_caps(dev, port,
1902 &ib_port_default_caps);
1903 if (err)
1904 mlx4_warn(dev, "failed to get port %d default "
1905 "ib capabilities (%d). Continuing "
1906 "with caps = 0\n", port, err);
1907 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1908
2aca1172
JM		 1909 /* initialize per-slave default ib port capabilities */
1910 if (mlx4_is_master(dev)) {
1911 int i;
1912 for (i = 0; i < dev->num_slaves; i++) {
1913 if (i == mlx4_master_func_num(dev))
1914 continue;
1915 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1916 ib_port_default_caps;
1917 }
1918 }
1919
096335b3
OG		 1920 if (mlx4_is_mfunc(dev))
1921 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1922 else
1923 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1924
6634961c
JM		 1925 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1926 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 1927 if (err) {
1928 mlx4_err(dev, "Failed to set port %d, aborting\n",
1929 port);
1930 goto err_counters_table_free;
1931 }
7ff93f8b
YP		 1932 }
1933 }
1934
225c7b1f
RD		 1935 return 0;
1936
f2a3f6a3
OG		 1937err_counters_table_free:
1938 mlx4_cleanup_counters_table(dev);
1939
225c7b1f
RD		 1940err_qp_table_free:
1941 mlx4_cleanup_qp_table(dev);
1942
1943err_srq_table_free:
1944 mlx4_cleanup_srq_table(dev);
1945
1946err_cq_table_free:
1947 mlx4_cleanup_cq_table(dev);
1948
1949err_cmd_poll:
1950 mlx4_cmd_use_polling(dev);
1951
1952err_eq_table_free:
1953 mlx4_cleanup_eq_table(dev);
1954
fe6f700d
YP		 1955err_mcg_table_free:
1956 if (!mlx4_is_slave(dev))
1957 mlx4_cleanup_mcg_table(dev);
1958
ee49bd93 1959err_mr_table_free:
225c7b1f
RD		 1960 mlx4_cleanup_mr_table(dev);
1961
012a8ff5
SH		 1962err_xrcd_table_free:
1963 mlx4_cleanup_xrcd_table(dev);
1964
225c7b1f
RD		 1965err_pd_table_free:
1966 mlx4_cleanup_pd_table(dev);
1967
1968err_kar_unmap:
1969 iounmap(priv->kar);
1970
1971err_uar_free:
1972 mlx4_uar_free(dev, &priv->driver_uar);
1973
1974err_uar_table_free:
1975 mlx4_cleanup_uar_table(dev);
1976 return err;
1977}
1978
e8f9b2ed 1979static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1980{
1981 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1982 struct msix_entry *entries;
0b7ca5a9 1983 int nreq = min_t(int, dev->caps.num_ports *
90b1ebe7
YM		 1984 min_t(int, netif_get_num_default_rss_queues() + 1,
1985 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1986 int err;
1987 int i;
1988
1989 if (msi_x) {
ca4c7b35
OG		 1990 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1991 nreq);
ab9c17a0 1992
b8dd786f
YP		 1993 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1994 if (!entries)
1995 goto no_msi;
1996
1997 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1998 entries[i].entry = i;
1999
b8dd786f
YP		 2000 retry:
2001 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 2002 if (err) {
b8dd786f
YP		 2003 /* Try again if at least 2 vectors are available */
2004 if (err > 1) {
2005 mlx4_info(dev, "Requested %d vectors, "
2006 "but only %d MSI-X vectors available, "
2007 "trying again\n", nreq, err);
2008 nreq = err;
2009 goto retry;
2010 }
5bf0da7d 2011 kfree(entries);
225c7b1f
RD		 2012 goto no_msi;
2013 }
2014
0b7ca5a9
YP		 2015 if (nreq <
2016 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
2017 /*Working in legacy mode , all EQ's shared*/
2018 dev->caps.comp_pool = 0;
2019 dev->caps.num_comp_vectors = nreq - 1;
2020 } else {
2021 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2022 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2023 }
b8dd786f 2024 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2025 priv->eq_table.eq[i].irq = entries[i].vector;
2026
2027 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2028
2029 kfree(entries);
225c7b1f
RD		 2030 return;
2031 }
2032
2033no_msi:
b8dd786f 2034 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2035 dev->caps.comp_pool = 0;
b8dd786f
YP		 2036
2037 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2038 priv->eq_table.eq[i].irq = dev->pdev->irq;
2039}
2040
7ff93f8b 2041static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2042{
2043 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2044 int err = 0;
2a2336f8
YP		 2045
2046 info->dev = dev;
2047 info->port = port;
ab9c17a0 2048 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2049 mlx4_init_mac_table(dev, &info->mac_table);
2050 mlx4_init_vlan_table(dev, &info->vlan_table);
16a10ffd 2051 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2052 }
7ff93f8b
YP		 2053
2054 sprintf(info->dev_name, "mlx4_port%d", port);
2055 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2056 if (mlx4_is_mfunc(dev))
2057 info->port_attr.attr.mode = S_IRUGO;
2058 else {
2059 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2060 info->port_attr.store = set_port_type;
2061 }
7ff93f8b 2062 info->port_attr.show = show_port_type;
3691c964 2063 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2064
2065 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2066 if (err) {
2067 mlx4_err(dev, "Failed to create file for port %d\n", port);
2068 info->port = -1;
2069 }
2070
096335b3
OG		 2071 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2072 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2073 if (mlx4_is_mfunc(dev))
2074 info->port_mtu_attr.attr.mode = S_IRUGO;
2075 else {
2076 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2077 info->port_mtu_attr.store = set_port_ib_mtu;
2078 }
2079 info->port_mtu_attr.show = show_port_ib_mtu;
2080 sysfs_attr_init(&info->port_mtu_attr.attr);
2081
2082 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2083 if (err) {
2084 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2085 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2086 info->port = -1;
2087 }
2088
7ff93f8b
YP		 2089 return err;
2090}
2091
2092static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2093{
2094 if (info->port < 0)
2095 return;
2096
2097 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2098 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2099}
2100
b12d93d6
YP		 2101static int mlx4_init_steering(struct mlx4_dev *dev)
2102{
2103 struct mlx4_priv *priv = mlx4_priv(dev);
2104 int num_entries = dev->caps.num_ports;
2105 int i, j;
2106
2107 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2108 if (!priv->steer)
2109 return -ENOMEM;
2110
45b51365 2111 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2112 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2113 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2114 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2115 }
b12d93d6
YP		 2116 return 0;
2117}
2118
2119static void mlx4_clear_steering(struct mlx4_dev *dev)
2120{
2121 struct mlx4_priv *priv = mlx4_priv(dev);
2122 struct mlx4_steer_index *entry, *tmp_entry;
2123 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2124 int num_entries = dev->caps.num_ports;
2125 int i, j;
2126
2127 for (i = 0; i < num_entries; i++) {
2128 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2129 list_for_each_entry_safe(pqp, tmp_pqp,
2130 &priv->steer[i].promisc_qps[j],
2131 list) {
2132 list_del(&pqp->list);
2133 kfree(pqp);
2134 }
2135 list_for_each_entry_safe(entry, tmp_entry,
2136 &priv->steer[i].steer_entries[j],
2137 list) {
2138 list_del(&entry->list);
2139 list_for_each_entry_safe(pqp, tmp_pqp,
2140 &entry->duplicates,
2141 list) {
2142 list_del(&pqp->list);
2143 kfree(pqp);
2144 }
2145 kfree(entry);
2146 }
2147 }
2148 }
2149 kfree(priv->steer);
2150}
2151
ab9c17a0
JM		 2152static int extended_func_num(struct pci_dev *pdev)
2153{
2154 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2155}
2156
2157#define MLX4_OWNER_BASE 0x8069c
2158#define MLX4_OWNER_SIZE 4
2159
2160static int mlx4_get_ownership(struct mlx4_dev *dev)
2161{
2162 void __iomem *owner;
2163 u32 ret;
2164
57dbf29a
KSS		 2165 if (pci_channel_offline(dev->pdev))
2166 return -EIO;
2167
ab9c17a0
JM		 2168 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2169 MLX4_OWNER_SIZE);
2170 if (!owner) {
2171 mlx4_err(dev, "Failed to obtain ownership bit\n");
2172 return -ENOMEM;
2173 }
2174
2175 ret = readl(owner);
2176 iounmap(owner);
2177 return (int) !!ret;
2178}
2179
2180static void mlx4_free_ownership(struct mlx4_dev *dev)
2181{
2182 void __iomem *owner;
2183
57dbf29a
KSS		 2184 if (pci_channel_offline(dev->pdev))
2185 return;
2186
ab9c17a0
JM		 2187 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2188 MLX4_OWNER_SIZE);
2189 if (!owner) {
2190 mlx4_err(dev, "Failed to obtain ownership bit\n");
2191 return;
2192 }
2193 writel(0, owner);
2194 msleep(1000);
2195 iounmap(owner);
2196}
2197
839f1243 2198static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
225c7b1f 2199{
225c7b1f
RD		 2200 struct mlx4_priv *priv;
2201 struct mlx4_dev *dev;
2202 int err;
2a2336f8 2203 int port;
225c7b1f 2204
0a645e80 2205 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 2206
2207 err = pci_enable_device(pdev);
2208 if (err) {
2209 dev_err(&pdev->dev, "Cannot enable PCI device, "
2210 "aborting.\n");
2211 return err;
2212 }
5a0d0a61
JM		 2213
2214 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2215 * per port, we must limit the number of VFs to 63 (since their are
2216 * 128 MACs)
2217 */
2218 if (num_vfs >= MLX4_MAX_NUM_VF) {
2219 dev_err(&pdev->dev,
2220 "Requested more VF's (%d) than allowed (%d)\n",
2221 num_vfs, MLX4_MAX_NUM_VF - 1);
ab9c17a0
JM		 2222 return -EINVAL;
2223 }
30e514a7
JM		 2224
2225 if (num_vfs < 0) {
2226 pr_err("num_vfs module parameter cannot be negative\n");
2227 return -EINVAL;
2228 }
225c7b1f 2229 /*
ab9c17a0 2230 * Check for BARs.
225c7b1f 2231 */
839f1243 2232 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
ab9c17a0
JM		 2233 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2234 dev_err(&pdev->dev, "Missing DCS, aborting."
839f1243
RD		 2235 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2236 pci_dev_data, pci_resource_flags(pdev, 0));
225c7b1f
RD		 2237 err = -ENODEV;
2238 goto err_disable_pdev;
2239 }
2240 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2241 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2242 err = -ENODEV;
2243 goto err_disable_pdev;
2244 }
2245
a01df0fe 2246 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 2247 if (err) {
a01df0fe 2248 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 2249 goto err_disable_pdev;
2250 }
2251
225c7b1f
RD		 2252 pci_set_master(pdev);
2253
6a35528a 2254 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2255 if (err) {
2256 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 2257 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2258 if (err) {
2259 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 2260 goto err_release_regions;
225c7b1f
RD		 2261 }
2262 }
6a35528a 2263 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2264 if (err) {
2265 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2266 "consistent PCI DMA mask.\n");
284901a9 2267 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2268 if (err) {
2269 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2270 "aborting.\n");
a01df0fe 2271 goto err_release_regions;
225c7b1f
RD		 2272 }
2273 }
2274
7f9e5c48
DD		 2275 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2276 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2277
b2adaca9 2278 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
225c7b1f 2279 if (!priv) {
225c7b1f 2280 err = -ENOMEM;
a01df0fe 2281 goto err_release_regions;
225c7b1f
RD		 2282 }
2283
2284 dev = &priv->dev;
2285 dev->pdev = pdev;
b581401e
RD		 2286 INIT_LIST_HEAD(&priv->ctx_list);
2287 spin_lock_init(&priv->ctx_lock);
225c7b1f 2288
7ff93f8b
YP		 2289 mutex_init(&priv->port_mutex);
2290
6296883c
YP		 2291 INIT_LIST_HEAD(&priv->pgdir_list);
2292 mutex_init(&priv->pgdir_mutex);
2293
c1b43dca
EC		 2294 INIT_LIST_HEAD(&priv->bf_list);
2295 mutex_init(&priv->bf_mutex);
2296
aca7a3ac 2297 dev->rev_id = pdev->revision;
6e7136ed 2298 dev->numa_node = dev_to_node(&pdev->dev);
ab9c17a0 2299 /* Detect if this device is a virtual function */
839f1243 2300 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2301 /* When acting as pf, we normally skip vfs unless explicitly
2302 * requested to probe them. */
2303 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2304 mlx4_warn(dev, "Skipping virtual function:%d\n",
2305 extended_func_num(pdev));
2306 err = -ENODEV;
2307 goto err_free_dev;
2308 }
2309 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2310 dev->flags |= MLX4_FLAG_SLAVE;
2311 } else {
2312 /* We reset the device and enable SRIOV only for physical
2313 * devices. Try to claim ownership on the device;
2314 * if already taken, skip -- do not allow multiple PFs */
2315 err = mlx4_get_ownership(dev);
2316 if (err) {
2317 if (err < 0)
2318 goto err_free_dev;
2319 else {
2320 mlx4_warn(dev, "Multiple PFs not yet supported."
2321 " Skipping PF.\n");
2322 err = -EINVAL;
2323 goto err_free_dev;
2324 }
2325 }
aca7a3ac 2326
ab9c17a0 2327 if (num_vfs) {
84b1f153 2328 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
97989356
AV		 2329
2330 atomic_inc(&pf_loading);
ab9c17a0 2331 err = pci_enable_sriov(pdev, num_vfs);
97989356
AV		 2332 atomic_dec(&pf_loading);
2333
ab9c17a0 2334 if (err) {
84b1f153
RD		 2335 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2336 err);
ab9c17a0
JM		 2337 err = 0;
2338 } else {
2339 mlx4_warn(dev, "Running in master mode\n");
2340 dev->flags |= MLX4_FLAG_SRIOV |
2341 MLX4_FLAG_MASTER;
2342 dev->num_vfs = num_vfs;
2343 }
2344 }
2345
fe6f700d
YP		 2346 atomic_set(&priv->opreq_count, 0);
2347 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2348
ab9c17a0
JM		 2349 /*
2350 * Now reset the HCA before we touch the PCI capabilities or
2351 * attempt a firmware command, since a boot ROM may have left
2352 * the HCA in an undefined state.
2353 */
2354 err = mlx4_reset(dev);
2355 if (err) {
2356 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2357 goto err_rel_own;
2358 }
225c7b1f
RD		 2359 }
2360
ab9c17a0 2361slave_start:
521130d1
EE		 2362 err = mlx4_cmd_init(dev);
2363 if (err) {
225c7b1f 2364 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 2365 goto err_sriov;
2366 }
2367
2368 /* In slave functions, the communication channel must be initialized
2369 * before posting commands. Also, init num_slaves before calling
2370 * mlx4_init_hca */
2371 if (mlx4_is_mfunc(dev)) {
2372 if (mlx4_is_master(dev))
2373 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2374 else {
2375 dev->num_slaves = 0;
f356fcbe
JM		 2376 err = mlx4_multi_func_init(dev);
2377 if (err) {
ab9c17a0
JM		 2378 mlx4_err(dev, "Failed to init slave mfunc"
2379 " interface, aborting.\n");
2380 goto err_cmd;
2381 }
2382 }
225c7b1f
RD		 2383 }
2384
2385 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2386 if (err) {
2387 if (err == -EACCES) {
2388 /* Not primary Physical function
2389 * Running in slave mode */
2390 mlx4_cmd_cleanup(dev);
2391 dev->flags |= MLX4_FLAG_SLAVE;
2392 dev->flags &= ~MLX4_FLAG_MASTER;
2393 goto slave_start;
2394 } else
2395 goto err_mfunc;
2396 }
2397
b912b2f8
EP		 2398 /* check if the device is functioning at its maximum possible speed.
2399 * No return code for this call, just warn the user in case of PCI
2400 * express device capabilities are under-satisfied by the bus.
2401 */
2402 mlx4_check_pcie_caps(dev);
2403
ab9c17a0
JM		 2404 /* In master functions, the communication channel must be initialized
2405 * after obtaining its address from fw */
2406 if (mlx4_is_master(dev)) {
f356fcbe
JM		 2407 err = mlx4_multi_func_init(dev);
2408 if (err) {
ab9c17a0
JM		 2409 mlx4_err(dev, "Failed to init master mfunc"
2410 "interface, aborting.\n");
2411 goto err_close;
2412 }
2413 }
225c7b1f 2414
b8dd786f
YP		 2415 err = mlx4_alloc_eq_table(dev);
2416 if (err)
ab9c17a0 2417 goto err_master_mfunc;
b8dd786f 2418
0b7ca5a9 2419 priv->msix_ctl.pool_bm = 0;
730c41d5 2420 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2421
08fb1055 2422 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2423 if ((mlx4_is_mfunc(dev)) &&
2424 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2425 err = -ENOSYS;
ab9c17a0
JM		 2426 mlx4_err(dev, "INTx is not supported in multi-function mode."
2427 " aborting.\n");
b12d93d6 2428 goto err_free_eq;
ab9c17a0
JM		 2429 }
2430
2431 if (!mlx4_is_slave(dev)) {
2432 err = mlx4_init_steering(dev);
2433 if (err)
2434 goto err_free_eq;
2435 }
b12d93d6 2436
225c7b1f 2437 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2438 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2439 !mlx4_is_mfunc(dev)) {
08fb1055 2440 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2441 dev->caps.num_comp_vectors = 1;
2442 dev->caps.comp_pool = 0;
08fb1055
MT		 2443 pci_disable_msix(pdev);
2444 err = mlx4_setup_hca(dev);
2445 }
2446
225c7b1f 2447 if (err)
b12d93d6 2448 goto err_steer;
225c7b1f 2449
5a0d0a61
JM		 2450 mlx4_init_quotas(dev);
2451
7ff93f8b
YP		 2452 for (port = 1; port <= dev->caps.num_ports; port++) {
2453 err = mlx4_init_port_info(dev, port);
2454 if (err)
2455 goto err_port;
2456 }
2a2336f8 2457
225c7b1f
RD		 2458 err = mlx4_register_device(dev);
2459 if (err)
7ff93f8b 2460 goto err_port;
225c7b1f 2461
b046ffe5
EP		 2462 mlx4_request_modules(dev);
2463
27bf91d6
YP		 2464 mlx4_sense_init(dev);
2465 mlx4_start_sense(dev);
2466
839f1243 2467 priv->pci_dev_data = pci_dev_data;
225c7b1f
RD		 2468 pci_set_drvdata(pdev, dev);
2469
2470 return 0;
2471
7ff93f8b 2472err_port:
b4f77264 2473 for (--port; port >= 1; --port)
7ff93f8b
YP		 2474 mlx4_cleanup_port_info(&priv->port[port]);
2475
f2a3f6a3 2476 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2477 mlx4_cleanup_qp_table(dev);
2478 mlx4_cleanup_srq_table(dev);
2479 mlx4_cleanup_cq_table(dev);
2480 mlx4_cmd_use_polling(dev);
2481 mlx4_cleanup_eq_table(dev);
fe6f700d 2482 mlx4_cleanup_mcg_table(dev);
225c7b1f 2483 mlx4_cleanup_mr_table(dev);
012a8ff5 2484 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2485 mlx4_cleanup_pd_table(dev);
2486 mlx4_cleanup_uar_table(dev);
2487
b12d93d6 2488err_steer:
ab9c17a0
JM		 2489 if (!mlx4_is_slave(dev))
2490 mlx4_clear_steering(dev);
b12d93d6 2491
b8dd786f
YP		 2492err_free_eq:
2493 mlx4_free_eq_table(dev);
2494
ab9c17a0
JM		 2495err_master_mfunc:
2496 if (mlx4_is_master(dev))
2497 mlx4_multi_func_cleanup(dev);
2498
225c7b1f 2499err_close:
08fb1055
MT		 2500 if (dev->flags & MLX4_FLAG_MSI_X)
2501 pci_disable_msix(pdev);
2502
225c7b1f
RD		 2503 mlx4_close_hca(dev);
2504
ab9c17a0
JM		 2505err_mfunc:
2506 if (mlx4_is_slave(dev))
2507 mlx4_multi_func_cleanup(dev);
2508
225c7b1f
RD		 2509err_cmd:
2510 mlx4_cmd_cleanup(dev);
2511
ab9c17a0 2512err_sriov:
681372a7 2513 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2514 pci_disable_sriov(pdev);
2515
2516err_rel_own:
2517 if (!mlx4_is_slave(dev))
2518 mlx4_free_ownership(dev);
2519
225c7b1f 2520err_free_dev:
225c7b1f
RD		 2521 kfree(priv);
2522
a01df0fe
RD		 2523err_release_regions:
2524 pci_release_regions(pdev);
225c7b1f
RD		 2525
2526err_disable_pdev:
2527 pci_disable_device(pdev);
2528 pci_set_drvdata(pdev, NULL);
2529 return err;
2530}
2531
1dd06ae8 2532static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2533{
0a645e80 2534 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2535
839f1243 2536 return __mlx4_init_one(pdev, id->driver_data);
3d73c288
RD		 2537}
2538
2539static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2540{
2541 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2542 struct mlx4_priv *priv = mlx4_priv(dev);
2543 int p;
2544
2545 if (dev) {
ab9c17a0
JM		 2546 /* in SRIOV it is not allowed to unload the pf's
2547 * driver while there are alive vf's */
2548 if (mlx4_is_master(dev)) {
2549 if (mlx4_how_many_lives_vf(dev))
2550 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2551 }
27bf91d6 2552 mlx4_stop_sense(dev);
225c7b1f
RD		 2553 mlx4_unregister_device(dev);
2554
7ff93f8b
YP		 2555 for (p = 1; p <= dev->caps.num_ports; p++) {
2556 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 2557 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 2558 }
225c7b1f 2559
b8924951
JM		 2560 if (mlx4_is_master(dev))
2561 mlx4_free_resource_tracker(dev,
2562 RES_TR_FREE_SLAVES_ONLY);
2563
f2a3f6a3 2564 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2565 mlx4_cleanup_qp_table(dev);
2566 mlx4_cleanup_srq_table(dev);
2567 mlx4_cleanup_cq_table(dev);
2568 mlx4_cmd_use_polling(dev);
2569 mlx4_cleanup_eq_table(dev);
fe6f700d 2570 mlx4_cleanup_mcg_table(dev);
225c7b1f 2571 mlx4_cleanup_mr_table(dev);
012a8ff5 2572 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2573 mlx4_cleanup_pd_table(dev);
2574
ab9c17a0 2575 if (mlx4_is_master(dev))
b8924951
JM		 2576 mlx4_free_resource_tracker(dev,
2577 RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 2578
225c7b1f
RD		 2579 iounmap(priv->kar);
2580 mlx4_uar_free(dev, &priv->driver_uar);
2581 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 2582 if (!mlx4_is_slave(dev))
2583 mlx4_clear_steering(dev);
b8dd786f 2584 mlx4_free_eq_table(dev);
ab9c17a0
JM		 2585 if (mlx4_is_master(dev))
2586 mlx4_multi_func_cleanup(dev);
225c7b1f 2587 mlx4_close_hca(dev);
ab9c17a0
JM		 2588 if (mlx4_is_slave(dev))
2589 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 2590 mlx4_cmd_cleanup(dev);
2591
2592 if (dev->flags & MLX4_FLAG_MSI_X)
2593 pci_disable_msix(pdev);
681372a7 2594 if (dev->flags & MLX4_FLAG_SRIOV) {
84b1f153 2595 mlx4_warn(dev, "Disabling SR-IOV\n");
ab9c17a0
JM		 2596 pci_disable_sriov(pdev);
2597 }
225c7b1f 2598
ab9c17a0
JM		 2599 if (!mlx4_is_slave(dev))
2600 mlx4_free_ownership(dev);
47605df9
JM		 2601
2602 kfree(dev->caps.qp0_tunnel);
2603 kfree(dev->caps.qp0_proxy);
2604 kfree(dev->caps.qp1_tunnel);
2605 kfree(dev->caps.qp1_proxy);
2606
225c7b1f 2607 kfree(priv);
a01df0fe 2608 pci_release_regions(pdev);
225c7b1f
RD		 2609 pci_disable_device(pdev);
2610 pci_set_drvdata(pdev, NULL);
2611 }
2612}
2613
ee49bd93
JM		 2614int mlx4_restart_one(struct pci_dev *pdev)
2615{
839f1243
RD		 2616 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2617 struct mlx4_priv *priv = mlx4_priv(dev);
2618 int pci_dev_data;
2619
2620 pci_dev_data = priv->pci_dev_data;
ee49bd93 2621 mlx4_remove_one(pdev);
839f1243 2622 return __mlx4_init_one(pdev, pci_dev_data);
ee49bd93
JM		 2623}
2624
a3aa1884 2625static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0 2626 /* MT25408 "Hermon" SDR */
ca3e57a5 2627 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2628 /* MT25408 "Hermon" DDR */
ca3e57a5 2629 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2630 /* MT25408 "Hermon" QDR */
ca3e57a5 2631 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2632 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 2633 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2634 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 2635 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2636 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 2637 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2638 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 2639 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2640 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 2641 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2642 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 2643 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2644 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 2645 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2646 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 2647 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2648 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 2649 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2650 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 2651 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2652 /* MT27500 Family [ConnectX-3] */
2653 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2654 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 2655 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2656 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2657 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2658 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2659 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2660 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2661 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2662 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2663 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2664 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2665 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2666 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2667 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2668 { 0, }
2669};
2670
2671MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2672
57dbf29a
KSS		 2673static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2674 pci_channel_state_t state)
2675{
2676 mlx4_remove_one(pdev);
2677
2678 return state == pci_channel_io_perm_failure ?
2679 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2680}
2681
2682static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2683{
839f1243 2684 int ret = __mlx4_init_one(pdev, 0);
57dbf29a
KSS		 2685
2686 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2687}
2688
3646f0e5 2689static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 2690 .error_detected = mlx4_pci_err_detected,
2691 .slot_reset = mlx4_pci_slot_reset,
2692};
2693
225c7b1f
RD		 2694static struct pci_driver mlx4_driver = {
2695 .name = DRV_NAME,
2696 .id_table = mlx4_pci_table,
2697 .probe = mlx4_init_one,
367d56f7 2698 .shutdown = mlx4_remove_one,
f57e6848 2699 .remove = mlx4_remove_one,
57dbf29a 2700 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2701};
2702
7ff93f8b
YP		 2703static int __init mlx4_verify_params(void)
2704{
2705 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2706 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2707 return -1;
2708 }
2709
cb29688a
OG		 2710 if (log_num_vlan != 0)
2711 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2712 MLX4_LOG_NUM_VLANS);
7ff93f8b 2713
0498628f 2714 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2715 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2716 return -1;
2717 }
2718
ab9c17a0
JM		 2719 /* Check if module param for ports type has legal combination */
2720 if (port_type_array[0] == false && port_type_array[1] == true) {
2721 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2722 port_type_array[0] = true;
2723 }
2724
3c439b55
JM		 2725 if (mlx4_log_num_mgm_entry_size != -1 &&
2726 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2727 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2728 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2729 "in legal range (-1 or %d..%d)\n",
2730 mlx4_log_num_mgm_entry_size,
2731 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2732 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2733 return -1;
2734 }
2735
7ff93f8b
YP		 2736 return 0;
2737}
2738
225c7b1f
RD		 2739static int __init mlx4_init(void)
2740{
2741 int ret;
2742
7ff93f8b
YP		 2743 if (mlx4_verify_params())
2744 return -EINVAL;
2745
27bf91d6
YP		 2746 mlx4_catas_init();
2747
2748 mlx4_wq = create_singlethread_workqueue("mlx4");
2749 if (!mlx4_wq)
2750 return -ENOMEM;
ee49bd93 2751
225c7b1f 2752 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 2753 if (ret < 0)
2754 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2755 return ret < 0 ? ret : 0;
2756}
2757
2758static void __exit mlx4_cleanup(void)
2759{
2760 pci_unregister_driver(&mlx4_driver);
27bf91d6 2761 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2762}
2763
2764module_init(mlx4_init);
2765module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)