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mlx4: Implement devlink interface
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
09d4d087 45#include <net/devlink.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
48#include <linux/mlx4/doorbell.h>
49
50#include "mlx4.h"
51#include "fw.h"
52#include "icm.h"
53
54MODULE_AUTHOR("Roland Dreier");
55MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
56MODULE_LICENSE("Dual BSD/GPL");
57MODULE_VERSION(DRV_VERSION);
58
27bf91d6
YP		 59struct workqueue_struct *mlx4_wq;
60
225c7b1f
RD		 61#ifdef CONFIG_MLX4_DEBUG
62
63int mlx4_debug_level = 0;
64module_param_named(debug_level, mlx4_debug_level, int, 0644);
65MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66
67#endif /* CONFIG_MLX4_DEBUG */
68
69#ifdef CONFIG_PCI_MSI
70
08fb1055 71static int msi_x = 1;
225c7b1f
RD		 72module_param(msi_x, int, 0444);
73MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74
75#else /* CONFIG_PCI_MSI */
76
77#define msi_x (0)
78
79#endif /* CONFIG_PCI_MSI */
80
dd41cc3b 81static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 82static int num_vfs_argc;
dd41cc3b
MB		 83module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
84MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
85 "num_vfs=port1,port2,port1+2");
86
87static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 88static int probe_vfs_argc;
dd41cc3b
MB		 89module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
90MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
91 "probe_vf=port1,port2,port1+2");
ab9c17a0 92
3c439b55 93int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 94module_param_named(log_num_mgm_entry_size,
95 mlx4_log_num_mgm_entry_size, int, 0444);
96MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
97 " of qp per mcg, for example:"
3c439b55 98 " 10 gives 248.range: 7 <="
0ff1fb65 99 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 100 " To activate device managed"
101 " flow steering when available, set to -1");
0ec2c0f8 102
be902ab1 103static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 104module_param(enable_64b_cqe_eqe, bool, 0444);
105MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 106 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 107
77507aa2 108#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 109 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
110 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 111
55ad3592
YH		 112#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
113
f57e6848 114static char mlx4_version[] =
225c7b1f
RD		 115 DRV_NAME ": Mellanox ConnectX core driver v"
116 DRV_VERSION " (" DRV_RELDATE ")\n";
117
118static struct mlx4_profile default_profile = {
ab9c17a0 119 .num_qp = 1 << 18,
225c7b1f 120 .num_srq = 1 << 16,
c9f2ba5e 121 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 122 .num_cq = 1 << 16,
123 .num_mcg = 1 << 13,
ab9c17a0 124 .num_mpt = 1 << 19,
9fd7a1e1 125 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 126};
127
2599d858
AV		 128static struct mlx4_profile low_mem_profile = {
129 .num_qp = 1 << 17,
130 .num_srq = 1 << 6,
131 .rdmarc_per_qp = 1 << 4,
132 .num_cq = 1 << 8,
133 .num_mcg = 1 << 8,
134 .num_mpt = 1 << 9,
135 .num_mtt = 1 << 7,
136};
137
ab9c17a0 138static int log_num_mac = 7;
93fc9e1b
YP		 139module_param_named(log_num_mac, log_num_mac, int, 0444);
140MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
141
142static int log_num_vlan;
143module_param_named(log_num_vlan, log_num_vlan, int, 0444);
144MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 145/* Log2 max number of VLANs per ETH port (0-7) */
146#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 147#define MLX4_MIN_LOG_NUM_VLANS 0
148#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 149
eb939922 150static bool use_prio;
93fc9e1b 151module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 152MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 153
2b8fb286 154int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 155module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 156MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 157
8d0fc7b6 158static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 159static int arr_argc = 2;
160module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 161MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
162 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 163
164struct mlx4_port_config {
165 struct list_head list;
166 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
167 struct pci_dev *pdev;
168};
169
97989356
AV		 170static atomic_t pf_loading = ATOMIC_INIT(0);
171
85743f1e
HN		 172static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
173 struct mlx4_dev_cap *dev_cap)
174{
175 /* The reserved_uars is calculated by system page size unit.
176 * Therefore, adjustment is added when the uar page size is less
177 * than the system page size
178 */
179 dev->caps.reserved_uars =
180 max_t(int,
181 mlx4_get_num_reserved_uar(dev),
182 dev_cap->reserved_uars /
183 (1 << (PAGE_SHIFT - dev->uar_page_shift)));
184}
185
27bf91d6
YP		 186int mlx4_check_port_params(struct mlx4_dev *dev,
187 enum mlx4_port_type *port_type)
7ff93f8b
YP		 188{
189 int i;
190
0b997657
YS		 191 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
192 for (i = 0; i < dev->caps.num_ports - 1; i++) {
193 if (port_type[i] != port_type[i + 1]) {
1a91de28 194 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 195 return -EINVAL;
196 }
7ff93f8b
YP		 197 }
198 }
7ff93f8b
YP		 199
200 for (i = 0; i < dev->caps.num_ports; i++) {
201 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 202 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
203 i + 1);
7ff93f8b
YP		 204 return -EINVAL;
205 }
206 }
207 return 0;
208}
209
210static void mlx4_set_port_mask(struct mlx4_dev *dev)
211{
212 int i;
213
7ff93f8b 214 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 215 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 216}
f2a3f6a3 217
7ae0e400
MB		 218enum {
219 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
220};
221
222static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
223{
224 int err = 0;
225 struct mlx4_func func;
226
227 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
228 err = mlx4_QUERY_FUNC(dev, &func, 0);
229 if (err) {
230 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
231 return err;
232 }
233 dev_cap->max_eqs = func.max_eq;
234 dev_cap->reserved_eqs = func.rsvd_eqs;
235 dev_cap->reserved_uars = func.rsvd_uars;
236 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
237 }
238 return err;
239}
240
77507aa2
IS		 241static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
242{
243 struct mlx4_caps *dev_cap = &dev->caps;
244
245 /* FW not supporting or cancelled by user */
246 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
247 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
248 return;
249
250 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
251 * When FW has NCSI it may decide not to report 64B CQE/EQEs
252 */
253 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
254 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
255 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
256 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
257 return;
258 }
259
260 if (cache_line_size() == 128 || cache_line_size() == 256) {
261 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
262 /* Changing the real data inside CQE size to 32B */
263 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
264 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
265
266 if (mlx4_is_master(dev))
267 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
268 } else {
0fab541a
OG		 269 if (cache_line_size() != 32 && cache_line_size() != 64)
270 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
77507aa2
IS		 271 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
272 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
273 }
274}
275
431df8c7
MB		 276static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
277 struct mlx4_port_cap *port_cap)
278{
279 dev->caps.vl_cap[port] = port_cap->max_vl;
280 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
281 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
282 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
283 /* set gid and pkey table operating lengths by default
284 * to non-sriov values
285 */
286 dev->caps.gid_table_len[port] = port_cap->max_gids;
287 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
288 dev->caps.port_width_cap[port] = port_cap->max_port_width;
289 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
290 dev->caps.def_mac[port] = port_cap->def_mac;
291 dev->caps.supported_type[port] = port_cap->supported_port_types;
292 dev->caps.suggested_type[port] = port_cap->suggested_type;
293 dev->caps.default_sense[port] = port_cap->default_sense;
294 dev->caps.trans_type[port] = port_cap->trans_type;
295 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
296 dev->caps.wavelength[port] = port_cap->wavelength;
297 dev->caps.trans_code[port] = port_cap->trans_code;
298
299 return 0;
300}
301
302static int mlx4_dev_port(struct mlx4_dev *dev, int port,
303 struct mlx4_port_cap *port_cap)
304{
305 int err = 0;
306
307 err = mlx4_QUERY_PORT(dev, port, port_cap);
308
309 if (err)
310 mlx4_err(dev, "QUERY_PORT command failed.\n");
311
312 return err;
313}
314
78500b8c
MM		 315static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
316{
317 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
318 return;
319
320 if (mlx4_is_mfunc(dev)) {
321 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
322 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
323 return;
324 }
325
326 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
327 mlx4_dbg(dev,
328 "Keep FCS is not supported - Disabling Ignore FCS");
329 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
330 return;
331 }
332}
333
431df8c7 334#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 335static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 336{
337 int err;
5ae2a7a8 338 int i;
225c7b1f
RD		 339
340 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
341 if (err) {
1a91de28 342 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 343 return err;
344 }
c78e25ed 345 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 346
347 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 348 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 349 dev_cap->min_page_sz, PAGE_SIZE);
350 return -ENODEV;
351 }
352 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 353 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 354 dev_cap->num_ports, MLX4_MAX_PORTS);
355 return -ENODEV;
356 }
357
872bf2fb 358 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 359 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 360 dev_cap->uar_size,
872bf2fb
YH		 361 (unsigned long long)
362 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 363 return -ENODEV;
364 }
365
366 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 367 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
368 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
369 dev->caps.num_sys_eqs :
370 MLX4_MAX_EQ_NUM;
5ae2a7a8 371 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 372 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
373 if (err) {
374 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
375 return err;
376 }
5ae2a7a8
RD		 377 }
378
ab9c17a0 379 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 380 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 381 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
382 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
383 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
384 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
385 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
386 dev->caps.max_wqes = dev_cap->max_qp_sz;
387 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 388 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
389 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
390 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
391 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
392 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 393 /*
394 * Subtract 1 from the limit because we need to allocate a
395 * spare CQE so the HCA HW can tell the difference between an
396 * empty CQ and a full CQ.
397 */
398 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
399 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
400 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 401 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 402 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0 403
225c7b1f 404 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 405 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
406 dev_cap->reserved_xrcds : 0;
407 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
408 dev_cap->max_xrcds : 0;
2b8fb286
MA		 409 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
410
149983af 411 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 412 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
413 dev->caps.flags = dev_cap->flags;
b3416f44 414 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 415 dev->caps.bmme_flags = dev_cap->bmme_flags;
416 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 417 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 418 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 419 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 420
85743f1e
HN		 421 /* Save uar page shift */
422 if (!mlx4_is_slave(dev)) {
423 /* Virtual PCI function needs to determine UAR page size from
424 * firmware. Only master PCI function can set the uar page size
425 */
426 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
427 mlx4_set_num_reserved_uars(dev, dev_cap);
428 }
429
77fc29c4
HHZ		 430 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
431 struct mlx4_init_hca_param hca_param;
432
433 memset(&hca_param, 0, sizeof(hca_param));
434 err = mlx4_QUERY_HCA(dev, &hca_param);
435 /* Turn off PHV_EN flag in case phv_check_en is set.
436 * phv_check_en is a HW check that parse the packet and verify
437 * phv bit was reported correctly in the wqe. To allow QinQ
438 * PHV_EN flag should be set and phv_check_en must be cleared
439 * otherwise QinQ packets will be drop by the HW.
440 */
441 if (err || hca_param.phv_check_en)
442 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
443 }
444
ca3e57a5
RD		 445 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
446 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 447 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 448 /* Don't do sense port on multifunction devices (for now at least) */
449 if (mlx4_is_mfunc(dev))
450 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 451
2599d858
AV		 452 if (mlx4_low_memory_profile()) {
453 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
454 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
455 } else {
456 dev->caps.log_num_macs = log_num_mac;
457 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
458 }
93fc9e1b
YP		 459
460 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 461 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
462 if (dev->caps.supported_type[i]) {
463 /* if only ETH is supported - assign ETH */
464 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
465 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 466 /* if only IB is supported, assign IB */
ab9c17a0 467 else if (dev->caps.supported_type[i] ==
105c320f
JM		 468 MLX4_PORT_TYPE_IB)
469 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 470 else {
105c320f
JM		 471 /* if IB and ETH are supported, we set the port
472 * type according to user selection of port type;
473 * if user selected none, take the FW hint */
474 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 475 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
476 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 477 else
105c320f 478 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 479 }
480 }
8d0fc7b6
YP		 481 /*
482 * Link sensing is allowed on the port if 3 conditions are true:
483 * 1. Both protocols are supported on the port.
484 * 2. Different types are supported on the port
485 * 3. FW declared that it supports link sensing
486 */
27bf91d6 487 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 488 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 489 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 490 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 491
8d0fc7b6
YP		 492 /*
493 * If "default_sense" bit is set, we move the port to "AUTO" mode
494 * and perform sense_port FW command to try and set the correct
495 * port type from beginning
496 */
46c46747 497 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 498 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
499 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
500 mlx4_SENSE_PORT(dev, i, &sensed_port);
501 if (sensed_port != MLX4_PORT_TYPE_NONE)
502 dev->caps.port_type[i] = sensed_port;
503 } else {
504 dev->caps.possible_type[i] = dev->caps.port_type[i];
505 }
506
431df8c7
MB		 507 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
508 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 509 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 510 i, 1 << dev->caps.log_num_macs);
511 }
431df8c7
MB		 512 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
513 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 514 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 515 i, 1 << dev->caps.log_num_vlans);
516 }
517 }
518
ac0a72a3
OG		 519 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
520 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
521 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
522 mlx4_warn(dev,
523 "Granular QoS per VF not supported with IB/Eth configuration\n");
524 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
525 }
526
47d8417f 527 dev->caps.max_counters = dev_cap->max_counters;
f2a3f6a3 528
93fc9e1b
YP		 529 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
530 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
531 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
532 (1 << dev->caps.log_num_macs) *
533 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 534 dev->caps.num_ports;
535 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 536
537 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
538 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
539 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
540 else
541 dev->caps.dmfs_high_rate_qpn_base =
542 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
543
544 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
545 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
546 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
547 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
548 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
549 } else {
550 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
551 dev->caps.dmfs_high_rate_qpn_base =
552 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
553 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
554 }
555
fc31e256
OG		 556 dev->caps.rl_caps = dev_cap->rl_caps;
557
d57febe1 558 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 559 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 560
561 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
562 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
563 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
564 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
565
e2c76824 566 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 567
b3051320 568 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 569 if (dev_cap->flags &
570 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
571 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
572 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
573 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
574 }
77507aa2
IS		 575
576 if (dev_cap->flags2 &
577 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
578 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
579 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
580 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
581 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
582 }
08ff3235
OG		 583 }
584
f97b4b5d 585 if ((dev->caps.flags &
08ff3235
OG		 586 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
587 mlx4_is_master(dev))
588 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
589
ddae0349 590 if (!mlx4_is_slave(dev)) {
77507aa2 591 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 592 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 593 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
594 MLX4_RESERVE_A0_QP;
3742cc65
IS		 595
596 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
597 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
598 mlx4_warn(dev, "Old device ETS support detected\n");
599 mlx4_warn(dev, "Consider upgrading device FW.\n");
600 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
601 }
602
ddae0349
EE		 603 } else {
604 dev->caps.alloc_res_qp_mask = 0;
605 }
77507aa2 606
78500b8c
MM		 607 mlx4_enable_ignore_fcs(dev);
608
225c7b1f
RD		 609 return 0;
610}
b912b2f8
EP		 611
612static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
613 enum pci_bus_speed *speed,
614 enum pcie_link_width *width)
615{
616 u32 lnkcap1, lnkcap2;
617 int err1, err2;
618
619#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
620
621 *speed = PCI_SPEED_UNKNOWN;
622 *width = PCIE_LNK_WIDTH_UNKNOWN;
623
872bf2fb
YH		 624 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
625 &lnkcap1);
626 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
627 &lnkcap2);
b912b2f8
EP		 628 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
629 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
630 *speed = PCIE_SPEED_8_0GT;
631 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
632 *speed = PCIE_SPEED_5_0GT;
633 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
634 *speed = PCIE_SPEED_2_5GT;
635 }
636 if (!err1) {
637 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
638 if (!lnkcap2) { /* pre-r3.0 */
639 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
640 *speed = PCIE_SPEED_5_0GT;
641 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
642 *speed = PCIE_SPEED_2_5GT;
643 }
644 }
645
646 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
647 return err1 ? err1 :
648 err2 ? err2 : -EINVAL;
649 }
650 return 0;
651}
652
653static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
654{
655 enum pcie_link_width width, width_cap;
656 enum pci_bus_speed speed, speed_cap;
657 int err;
658
659#define PCIE_SPEED_STR(speed) \
660 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
661 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
662 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
663 "Unknown")
664
665 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
666 if (err) {
667 mlx4_warn(dev,
668 "Unable to determine PCIe device BW capabilities\n");
669 return;
670 }
671
872bf2fb 672 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
b912b2f8
EP		 673 if (err || speed == PCI_SPEED_UNKNOWN ||
674 width == PCIE_LNK_WIDTH_UNKNOWN) {
675 mlx4_warn(dev,
676 "Unable to determine PCI device chain minimum BW\n");
677 return;
678 }
679
680 if (width != width_cap || speed != speed_cap)
681 mlx4_warn(dev,
682 "PCIe BW is different than device's capability\n");
683
684 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
685 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
686 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
687 width, width_cap);
688 return;
689}
690
ab9c17a0
JM		 691/*The function checks if there are live vf, return the num of them*/
692static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
693{
694 struct mlx4_priv *priv = mlx4_priv(dev);
695 struct mlx4_slave_state *s_state;
696 int i;
697 int ret = 0;
698
699 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
700 s_state = &priv->mfunc.master.slave_state[i];
701 if (s_state->active && s_state->last_cmd !=
702 MLX4_COMM_CMD_RESET) {
703 mlx4_warn(dev, "%s: slave: %d is still active\n",
704 __func__, i);
705 ret++;
706 }
707 }
708 return ret;
709}
710
396f2feb
JM		 711int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
712{
713 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 714
715 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
716 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 717 return -EINVAL;
718
47605df9 719 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 720 /* tunnel qp */
47605df9 721 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 722 else
47605df9 723 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 724 *qkey = qk;
725 return 0;
726}
727EXPORT_SYMBOL(mlx4_get_parav_qkey);
728
54679e14
JM		 729void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
730{
731 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
732
733 if (!mlx4_is_master(dev))
734 return;
735
736 priv->virt2phys_pkey[slave][port - 1][i] = val;
737}
738EXPORT_SYMBOL(mlx4_sync_pkey_table);
739
afa8fd1d
JM		 740void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
741{
742 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
743
744 if (!mlx4_is_master(dev))
745 return;
746
747 priv->slave_node_guids[slave] = guid;
748}
749EXPORT_SYMBOL(mlx4_put_slave_node_guid);
750
751__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
752{
753 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
754
755 if (!mlx4_is_master(dev))
756 return 0;
757
758 return priv->slave_node_guids[slave];
759}
760EXPORT_SYMBOL(mlx4_get_slave_node_guid);
761
e10903b0 762int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 763{
764 struct mlx4_priv *priv = mlx4_priv(dev);
765 struct mlx4_slave_state *s_slave;
766
767 if (!mlx4_is_master(dev))
768 return 0;
769
770 s_slave = &priv->mfunc.master.slave_state[slave];
771 return !!s_slave->active;
772}
773EXPORT_SYMBOL(mlx4_is_slave_active);
774
7b8157be
JM		 775static void slave_adjust_steering_mode(struct mlx4_dev *dev,
776 struct mlx4_dev_cap *dev_cap,
777 struct mlx4_init_hca_param *hca_param)
778{
779 dev->caps.steering_mode = hca_param->steering_mode;
780 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
781 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
782 dev->caps.fs_log_max_ucast_qp_range_size =
783 dev_cap->fs_log_max_ucast_qp_range_size;
784 } else
785 dev->caps.num_qp_per_mgm =
786 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
787
788 mlx4_dbg(dev, "Steering mode is: %s\n",
789 mlx4_steering_mode_str(dev->caps.steering_mode));
790}
791
ab9c17a0
JM		 792static int mlx4_slave_cap(struct mlx4_dev *dev)
793{
794 int err;
795 u32 page_size;
796 struct mlx4_dev_cap dev_cap;
797 struct mlx4_func_cap func_cap;
798 struct mlx4_init_hca_param hca_param;
225c6c8c 799 u8 i;
ab9c17a0
JM		 800
801 memset(&hca_param, 0, sizeof(hca_param));
802 err = mlx4_QUERY_HCA(dev, &hca_param);
803 if (err) {
1a91de28 804 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 805 return err;
806 }
807
483e0132
EP		 808 /* fail if the hca has an unknown global capability
809 * at this time global_caps should be always zeroed
810 */
811 if (hca_param.global_caps) {
ab9c17a0
JM		 812 mlx4_err(dev, "Unknown hca global capabilities\n");
813 return -ENOSYS;
814 }
815
816 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
817
ddd8a6c1
EE		 818 dev->caps.hca_core_clock = hca_param.hca_core_clock;
819
ab9c17a0 820 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 821 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 822 err = mlx4_dev_cap(dev, &dev_cap);
823 if (err) {
1a91de28 824 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 825 return err;
826 }
827
b91cb3eb
JM		 828 err = mlx4_QUERY_FW(dev);
829 if (err)
1a91de28 830 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 831
ab9c17a0
JM		 832 page_size = ~dev->caps.page_size_cap + 1;
833 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
834 if (page_size > PAGE_SIZE) {
1a91de28 835 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 836 page_size, PAGE_SIZE);
837 return -ENODEV;
838 }
839
85743f1e
HN		 840 /* Set uar_page_shift for VF */
841 dev->uar_page_shift = hca_param.uar_page_sz + 12;
ab9c17a0 842
85743f1e
HN		 843 /* Make sure the master uar page size is valid */
844 if (dev->uar_page_shift > PAGE_SHIFT) {
845 mlx4_err(dev,
846 "Invalid configuration: uar page size is larger than system page size\n");
847 return -ENODEV;
ab9c17a0
JM		 848 }
849
85743f1e
HN		 850 /* Set reserved_uars based on the uar_page_shift */
851 mlx4_set_num_reserved_uars(dev, &dev_cap);
852
853 /* Although uar page size in FW differs from system page size,
854 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
855 * still works with assumption that uar page size == system page size
856 */
857 dev->caps.uar_page_size = PAGE_SIZE;
858
ab9c17a0 859 memset(&func_cap, 0, sizeof(func_cap));
47605df9 860 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 861 if (err) {
1a91de28
JP		 862 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
863 err);
ab9c17a0
JM		 864 return err;
865 }
866
867 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
868 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3
MB		 869 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
870 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
ab9c17a0
JM		 871 return -ENOSYS;
872 }
873
ab9c17a0 874 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 875 dev->quotas.qp = func_cap.qp_quota;
876 dev->quotas.srq = func_cap.srq_quota;
877 dev->quotas.cq = func_cap.cq_quota;
878 dev->quotas.mpt = func_cap.mpt_quota;
879 dev->quotas.mtt = func_cap.mtt_quota;
880 dev->caps.num_qps = 1 << hca_param.log_num_qps;
881 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
882 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
883 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
884 dev->caps.num_eqs = func_cap.max_eq;
885 dev->caps.reserved_eqs = func_cap.reserved_eq;
f0ce0615 886 dev->caps.reserved_lkey = func_cap.reserved_lkey;
ab9c17a0
JM		 887 dev->caps.num_pds = MLX4_NUM_PDS;
888 dev->caps.num_mgms = 0;
889 dev->caps.num_amgms = 0;
890
ab9c17a0 891 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 892 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
893 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 894 return -ENODEV;
895 }
896
2b3ddf27
JM		 897 mlx4_replace_zero_macs(dev);
898
99ec41d0 899 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 900 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
901 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
902 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
903 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
904
905 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 906 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
907 !dev->caps.qp0_qkey) {
47605df9
JM		 908 err = -ENOMEM;
909 goto err_mem;
910 }
911
6634961c 912 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 913 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 914 if (err) {
1a91de28
JP		 915 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
916 i, err);
47605df9
JM		 917 goto err_mem;
918 }
99ec41d0 919 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 920 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
921 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
922 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
923 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 924 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 925 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
d49c2197
NO		 926 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
927 &dev->caps.gid_table_len[i],
928 &dev->caps.pkey_table_len[i]);
929 if (err)
47605df9 930 goto err_mem;
6634961c 931 }
6230bb23 932
ab9c17a0
JM		 933 if (dev->caps.uar_page_size * (dev->caps.num_uars -
934 dev->caps.reserved_uars) >
872bf2fb
YH		 935 pci_resource_len(dev->persist->pdev,
936 2)) {
1a91de28 937 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 938 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 939 (unsigned long long)
940 pci_resource_len(dev->persist->pdev, 2));
d49c2197 941 err = -ENOMEM;
47605df9 942 goto err_mem;
ab9c17a0
JM		 943 }
944
08ff3235
OG		 945 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
946 dev->caps.eqe_size = 64;
947 dev->caps.eqe_factor = 1;
948 } else {
949 dev->caps.eqe_size = 32;
950 dev->caps.eqe_factor = 0;
951 }
952
953 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
954 dev->caps.cqe_size = 64;
77507aa2 955 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 956 } else {
957 dev->caps.cqe_size = 32;
958 }
959
77507aa2
IS		 960 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
961 dev->caps.eqe_size = hca_param.eqe_size;
962 dev->caps.eqe_factor = 0;
963 }
964
965 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
966 dev->caps.cqe_size = hca_param.cqe_size;
967 /* User still need to know when CQE > 32B */
968 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
969 }
970
f9bd2d7f 971 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 972 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 973
7b8157be 974 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
802f42a8
IS		 975 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
976 hca_param.rss_ip_frags ? "on" : "off");
7b8157be 977
ddae0349
EE		 978 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
979 dev->caps.bf_reg_size)
980 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
981
d57febe1
MB		 982 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
983 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
984
ab9c17a0 985 return 0;
47605df9
JM		 986
987err_mem:
99ec41d0 988 kfree(dev->caps.qp0_qkey);
47605df9
JM		 989 kfree(dev->caps.qp0_tunnel);
990 kfree(dev->caps.qp0_proxy);
991 kfree(dev->caps.qp1_tunnel);
992 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 993 dev->caps.qp0_qkey = NULL;
994 dev->caps.qp0_tunnel = NULL;
995 dev->caps.qp0_proxy = NULL;
996 dev->caps.qp1_tunnel = NULL;
997 dev->caps.qp1_proxy = NULL;
47605df9
JM		 998
999 return err;
ab9c17a0 1000}
225c7b1f 1001
b046ffe5
EP		 1002static void mlx4_request_modules(struct mlx4_dev *dev)
1003{
1004 int port;
1005 int has_ib_port = false;
1006 int has_eth_port = false;
1007#define EN_DRV_NAME "mlx4_en"
1008#define IB_DRV_NAME "mlx4_ib"
1009
1010 for (port = 1; port <= dev->caps.num_ports; port++) {
1011 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1012 has_ib_port = true;
1013 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1014 has_eth_port = true;
1015 }
1016
b046ffe5
EP		 1017 if (has_eth_port)
1018 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 1019 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1020 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 1021}
1022
7ff93f8b
YP		 1023/*
1024 * Change the port configuration of the device.
1025 * Every user of this function must hold the port mutex.
1026 */
27bf91d6
YP		 1027int mlx4_change_port_types(struct mlx4_dev *dev,
1028 enum mlx4_port_type *port_types)
7ff93f8b
YP		 1029{
1030 int err = 0;
1031 int change = 0;
1032 int port;
1033
1034 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 1035 /* Change the port type only if the new type is different
1036 * from the current, and not set to Auto */
3d8f9308 1037 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 1038 change = 1;
7ff93f8b
YP		 1039 }
1040 if (change) {
1041 mlx4_unregister_device(dev);
1042 for (port = 1; port <= dev->caps.num_ports; port++) {
1043 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 1044 dev->caps.port_type[port] = port_types[port - 1];
6634961c 1045 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 1046 if (err) {
1a91de28
JP		 1047 mlx4_err(dev, "Failed to set port %d, aborting\n",
1048 port);
7ff93f8b
YP		 1049 goto out;
1050 }
1051 }
1052 mlx4_set_port_mask(dev);
1053 err = mlx4_register_device(dev);
b046ffe5
EP		 1054 if (err) {
1055 mlx4_err(dev, "Failed to register device\n");
1056 goto out;
1057 }
1058 mlx4_request_modules(dev);
7ff93f8b
YP		 1059 }
1060
1061out:
1062 return err;
1063}
1064
1065static ssize_t show_port_type(struct device *dev,
1066 struct device_attribute *attr,
1067 char *buf)
1068{
1069 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1070 port_attr);
1071 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 1072 char type[8];
1073
1074 sprintf(type, "%s",
1075 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1076 "ib" : "eth");
1077 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1078 sprintf(buf, "auto (%s)\n", type);
1079 else
1080 sprintf(buf, "%s\n", type);
7ff93f8b 1081
27bf91d6 1082 return strlen(buf);
7ff93f8b
YP		 1083}
1084
1085static ssize_t set_port_type(struct device *dev,
1086 struct device_attribute *attr,
1087 const char *buf, size_t count)
1088{
1089 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1090 port_attr);
1091 struct mlx4_dev *mdev = info->dev;
1092 struct mlx4_priv *priv = mlx4_priv(mdev);
1093 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1094 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 1095 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 1096 int i;
1097 int err = 0;
1098
0a984556
AV		 1099 mutex_lock(&set_port_type_mutex);
1100
7ff93f8b
YP		 1101 if (!strcmp(buf, "ib\n"))
1102 info->tmp_type = MLX4_PORT_TYPE_IB;
1103 else if (!strcmp(buf, "eth\n"))
1104 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 1105 else if (!strcmp(buf, "auto\n"))
1106 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 1107 else {
1108 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 1109 err = -EINVAL;
1110 goto err_out;
7ff93f8b
YP		 1111 }
1112
27bf91d6 1113 mlx4_stop_sense(mdev);
7ff93f8b 1114 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 1115 /* Possible type is always the one that was delivered */
1116 mdev->caps.possible_type[info->port] = info->tmp_type;
1117
1118 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1119 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1120 mdev->caps.possible_type[i+1];
1121 if (types[i] == MLX4_PORT_TYPE_AUTO)
1122 types[i] = mdev->caps.port_type[i+1];
1123 }
7ff93f8b 1124
58a60168
YP		 1125 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1126 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1127 for (i = 1; i <= mdev->caps.num_ports; i++) {
1128 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1129 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1130 err = -EINVAL;
1131 }
1132 }
1133 }
1134 if (err) {
1a91de28 1135 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1136 goto out;
1137 }
1138
1139 mlx4_do_sense_ports(mdev, new_types, types);
1140
1141 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1142 if (err)
1143 goto out;
1144
27bf91d6
YP		 1145 /* We are about to apply the changes after the configuration
1146 * was verified, no need to remember the temporary types
1147 * any more */
1148 for (i = 0; i < mdev->caps.num_ports; i++)
1149 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1150
27bf91d6 1151 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1152
1153out:
27bf91d6 1154 mlx4_start_sense(mdev);
7ff93f8b 1155 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1156err_out:
1157 mutex_unlock(&set_port_type_mutex);
1158
7ff93f8b
YP		 1159 return err ? err : count;
1160}
1161
096335b3
OG		 1162enum ibta_mtu {
1163 IB_MTU_256 = 1,
1164 IB_MTU_512 = 2,
1165 IB_MTU_1024 = 3,
1166 IB_MTU_2048 = 4,
1167 IB_MTU_4096 = 5
1168};
1169
1170static inline int int_to_ibta_mtu(int mtu)
1171{
1172 switch (mtu) {
1173 case 256: return IB_MTU_256;
1174 case 512: return IB_MTU_512;
1175 case 1024: return IB_MTU_1024;
1176 case 2048: return IB_MTU_2048;
1177 case 4096: return IB_MTU_4096;
1178 default: return -1;
1179 }
1180}
1181
1182static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1183{
1184 switch (mtu) {
1185 case IB_MTU_256: return 256;
1186 case IB_MTU_512: return 512;
1187 case IB_MTU_1024: return 1024;
1188 case IB_MTU_2048: return 2048;
1189 case IB_MTU_4096: return 4096;
1190 default: return -1;
1191 }
1192}
1193
1194static ssize_t show_port_ib_mtu(struct device *dev,
1195 struct device_attribute *attr,
1196 char *buf)
1197{
1198 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1199 port_mtu_attr);
1200 struct mlx4_dev *mdev = info->dev;
1201
1202 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1203 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1204
1205 sprintf(buf, "%d\n",
1206 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1207 return strlen(buf);
1208}
1209
1210static ssize_t set_port_ib_mtu(struct device *dev,
1211 struct device_attribute *attr,
1212 const char *buf, size_t count)
1213{
1214 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1215 port_mtu_attr);
1216 struct mlx4_dev *mdev = info->dev;
1217 struct mlx4_priv *priv = mlx4_priv(mdev);
1218 int err, port, mtu, ibta_mtu = -1;
1219
1220 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1221 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1222 return -EINVAL;
1223 }
1224
618fad95
DB		 1225 err = kstrtoint(buf, 0, &mtu);
1226 if (!err)
096335b3
OG		 1227 ibta_mtu = int_to_ibta_mtu(mtu);
1228
618fad95 1229 if (err || ibta_mtu < 0) {
096335b3
OG		 1230 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1231 return -EINVAL;
1232 }
1233
1234 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1235
1236 mlx4_stop_sense(mdev);
1237 mutex_lock(&priv->port_mutex);
1238 mlx4_unregister_device(mdev);
1239 for (port = 1; port <= mdev->caps.num_ports; port++) {
1240 mlx4_CLOSE_PORT(mdev, port);
6634961c 1241 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1242 if (err) {
1a91de28
JP		 1243 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1244 port);
096335b3
OG		 1245 goto err_set_port;
1246 }
1247 }
1248 err = mlx4_register_device(mdev);
1249err_set_port:
1250 mutex_unlock(&priv->port_mutex);
1251 mlx4_start_sense(mdev);
1252 return err ? err : count;
1253}
1254
e57968a1
MS		 1255/* bond for multi-function device */
1256#define MAX_MF_BOND_ALLOWED_SLAVES 63
1257static int mlx4_mf_bond(struct mlx4_dev *dev)
1258{
1259 int err = 0;
1260 struct mlx4_slaves_pport slaves_port1;
1261 struct mlx4_slaves_pport slaves_port2;
1262 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1263
1264 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1265 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1266 bitmap_and(slaves_port_1_2,
1267 slaves_port1.slaves, slaves_port2.slaves,
1268 dev->persist->num_vfs + 1);
1269
1270 /* only single port vfs are allowed */
1271 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1272 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1273 return -EINVAL;
1274 }
1275
1276 /* limit on maximum allowed VFs */
1277 if ((bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1278 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1)) >
1279 MAX_MF_BOND_ALLOWED_SLAVES)
1280 return -EINVAL;
1281
1282 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1283 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1284 return -EINVAL;
1285 }
1286
1287 err = mlx4_bond_mac_table(dev);
1288 if (err)
1289 return err;
1290 err = mlx4_bond_vlan_table(dev);
1291 if (err)
1292 goto err1;
1293 err = mlx4_bond_fs_rules(dev);
1294 if (err)
1295 goto err2;
1296
1297 return 0;
1298err2:
1299 (void)mlx4_unbond_vlan_table(dev);
1300err1:
1301 (void)mlx4_unbond_mac_table(dev);
1302 return err;
1303}
1304
1305static int mlx4_mf_unbond(struct mlx4_dev *dev)
1306{
1307 int ret, ret1;
1308
1309 ret = mlx4_unbond_fs_rules(dev);
1310 if (ret)
1311 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1312 ret1 = mlx4_unbond_mac_table(dev);
1313 if (ret1) {
1314 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1315 ret = ret1;
1316 }
1317 ret1 = mlx4_unbond_vlan_table(dev);
1318 if (ret1) {
1319 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1320 ret = ret1;
1321 }
1322 return ret;
1323}
1324
53f33ae2
MS		 1325int mlx4_bond(struct mlx4_dev *dev)
1326{
1327 int ret = 0;
1328 struct mlx4_priv *priv = mlx4_priv(dev);
1329
1330 mutex_lock(&priv->bond_mutex);
1331
e57968a1 1332 if (!mlx4_is_bonded(dev)) {
53f33ae2 1333 ret = mlx4_do_bond(dev, true);
e57968a1
MS		 1334 if (ret)
1335 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1336 if (!ret && mlx4_is_master(dev)) {
1337 ret = mlx4_mf_bond(dev);
1338 if (ret) {
1339 mlx4_err(dev, "bond for multifunction failed\n");
1340 mlx4_do_bond(dev, false);
1341 }
1342 }
1343 }
53f33ae2
MS		 1344
1345 mutex_unlock(&priv->bond_mutex);
e57968a1 1346 if (!ret)
53f33ae2 1347 mlx4_dbg(dev, "Device is bonded\n");
e57968a1 1348
53f33ae2
MS		 1349 return ret;
1350}
1351EXPORT_SYMBOL_GPL(mlx4_bond);
1352
1353int mlx4_unbond(struct mlx4_dev *dev)
1354{
1355 int ret = 0;
1356 struct mlx4_priv *priv = mlx4_priv(dev);
1357
1358 mutex_lock(&priv->bond_mutex);
1359
e57968a1
MS		 1360 if (mlx4_is_bonded(dev)) {
1361 int ret2 = 0;
1362
53f33ae2 1363 ret = mlx4_do_bond(dev, false);
e57968a1
MS		 1364 if (ret)
1365 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1366 if (mlx4_is_master(dev))
1367 ret2 = mlx4_mf_unbond(dev);
1368 if (ret2) {
1369 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1370 ret = ret2;
1371 }
1372 }
53f33ae2
MS		 1373
1374 mutex_unlock(&priv->bond_mutex);
e57968a1 1375 if (!ret)
53f33ae2 1376 mlx4_dbg(dev, "Device is unbonded\n");
e57968a1 1377
53f33ae2
MS		 1378 return ret;
1379}
1380EXPORT_SYMBOL_GPL(mlx4_unbond);
1381
1382
1383int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1384{
1385 u8 port1 = v2p->port1;
1386 u8 port2 = v2p->port2;
1387 struct mlx4_priv *priv = mlx4_priv(dev);
1388 int err;
1389
1390 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1391 return -ENOTSUPP;
1392
1393 mutex_lock(&priv->bond_mutex);
1394
1395 /* zero means keep current mapping for this port */
1396 if (port1 == 0)
1397 port1 = priv->v2p.port1;
1398 if (port2 == 0)
1399 port2 = priv->v2p.port2;
1400
1401 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1402 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1403 (port1 == 2 && port2 == 1)) {
1404 /* besides boundary checks cross mapping makes
1405 * no sense and therefore not allowed */
1406 err = -EINVAL;
1407 } else if ((port1 == priv->v2p.port1) &&
1408 (port2 == priv->v2p.port2)) {
1409 err = 0;
1410 } else {
1411 err = mlx4_virt2phy_port_map(dev, port1, port2);
1412 if (!err) {
1413 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1414 port1, port2);
1415 priv->v2p.port1 = port1;
1416 priv->v2p.port2 = port2;
1417 } else {
1418 mlx4_err(dev, "Failed to change port mape: %d\n", err);
1419 }
1420 }
1421
1422 mutex_unlock(&priv->bond_mutex);
1423 return err;
1424}
1425EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1426
e8f9b2ed 1427static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1428{
1429 struct mlx4_priv *priv = mlx4_priv(dev);
1430 int err;
1431
1432 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1433 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1434 if (!priv->fw.fw_icm) {
1a91de28 1435 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1436 return -ENOMEM;
1437 }
1438
1439 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1440 if (err) {
1a91de28 1441 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1442 goto err_free;
1443 }
1444
1445 err = mlx4_RUN_FW(dev);
1446 if (err) {
1a91de28 1447 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1448 goto err_unmap_fa;
1449 }
1450
1451 return 0;
1452
1453err_unmap_fa:
1454 mlx4_UNMAP_FA(dev);
1455
1456err_free:
5b0bf5e2 1457 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1458 return err;
1459}
1460
e8f9b2ed
RD		 1461static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1462 int cmpt_entry_sz)
225c7b1f
RD		 1463{
1464 struct mlx4_priv *priv = mlx4_priv(dev);
1465 int err;
ab9c17a0 1466 int num_eqs;
225c7b1f
RD		 1467
1468 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1469 cmpt_base +
1470 ((u64) (MLX4_CMPT_TYPE_QP *
1471 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1472 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1473 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1474 0, 0);
225c7b1f
RD		 1475 if (err)
1476 goto err;
1477
1478 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1479 cmpt_base +
1480 ((u64) (MLX4_CMPT_TYPE_SRQ *
1481 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1482 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1483 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1484 if (err)
1485 goto err_qp;
1486
1487 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1488 cmpt_base +
1489 ((u64) (MLX4_CMPT_TYPE_CQ *
1490 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1491 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1492 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1493 if (err)
1494 goto err_srq;
1495
7ae0e400 1496 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1497 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1498 cmpt_base +
1499 ((u64) (MLX4_CMPT_TYPE_EQ *
1500 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1501 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1502 if (err)
1503 goto err_cq;
1504
1505 return 0;
1506
1507err_cq:
1508 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1509
1510err_srq:
1511 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1512
1513err_qp:
1514 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1515
1516err:
1517 return err;
1518}
1519
3d73c288
RD		 1520static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1521 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1522{
1523 struct mlx4_priv *priv = mlx4_priv(dev);
1524 u64 aux_pages;
ab9c17a0 1525 int num_eqs;
225c7b1f
RD		 1526 int err;
1527
1528 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1529 if (err) {
1a91de28 1530 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1531 return err;
1532 }
1533
1a91de28 1534 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1535 (unsigned long long) icm_size >> 10,
1536 (unsigned long long) aux_pages << 2);
1537
1538 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1539 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1540 if (!priv->fw.aux_icm) {
1a91de28 1541 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1542 return -ENOMEM;
1543 }
1544
1545 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1546 if (err) {
1a91de28 1547 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1548 goto err_free_aux;
1549 }
1550
1551 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1552 if (err) {
1a91de28 1553 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1554 goto err_unmap_aux;
1555 }
1556
ab9c17a0 1557
7ae0e400 1558 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1559 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1560 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1561 num_eqs, num_eqs, 0, 0);
225c7b1f 1562 if (err) {
1a91de28 1563 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1564 goto err_unmap_cmpt;
1565 }
1566
d7bb58fb
JM		 1567 /*
1568 * Reserved MTT entries must be aligned up to a cacheline
1569 * boundary, since the FW will write to them, while the driver
1570 * writes to all other MTT entries. (The variable
1571 * dev->caps.mtt_entry_sz below is really the MTT segment
1572 * size, not the raw entry size)
1573 */
1574 dev->caps.reserved_mtts =
1575 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1576 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1577
225c7b1f
RD		 1578 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1579 init_hca->mtt_base,
1580 dev->caps.mtt_entry_sz,
2b8fb286 1581 dev->caps.num_mtts,
5b0bf5e2 1582 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1583 if (err) {
1a91de28 1584 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1585 goto err_unmap_eq;
1586 }
1587
1588 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1589 init_hca->dmpt_base,
1590 dev_cap->dmpt_entry_sz,
1591 dev->caps.num_mpts,
5b0bf5e2 1592 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1593 if (err) {
1a91de28 1594 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1595 goto err_unmap_mtt;
1596 }
1597
1598 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1599 init_hca->qpc_base,
1600 dev_cap->qpc_entry_sz,
1601 dev->caps.num_qps,
93fc9e1b
YP		 1602 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1603 0, 0);
225c7b1f 1604 if (err) {
1a91de28 1605 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1606 goto err_unmap_dmpt;
1607 }
1608
1609 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1610 init_hca->auxc_base,
1611 dev_cap->aux_entry_sz,
1612 dev->caps.num_qps,
93fc9e1b
YP		 1613 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1614 0, 0);
225c7b1f 1615 if (err) {
1a91de28 1616 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1617 goto err_unmap_qp;
1618 }
1619
1620 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1621 init_hca->altc_base,
1622 dev_cap->altc_entry_sz,
1623 dev->caps.num_qps,
93fc9e1b
YP		 1624 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1625 0, 0);
225c7b1f 1626 if (err) {
1a91de28 1627 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1628 goto err_unmap_auxc;
1629 }
1630
1631 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1632 init_hca->rdmarc_base,
1633 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1634 dev->caps.num_qps,
93fc9e1b
YP		 1635 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1636 0, 0);
225c7b1f
RD		 1637 if (err) {
1638 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1639 goto err_unmap_altc;
1640 }
1641
1642 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1643 init_hca->cqc_base,
1644 dev_cap->cqc_entry_sz,
1645 dev->caps.num_cqs,
5b0bf5e2 1646 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1647 if (err) {
1a91de28 1648 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1649 goto err_unmap_rdmarc;
1650 }
1651
1652 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1653 init_hca->srqc_base,
1654 dev_cap->srq_entry_sz,
1655 dev->caps.num_srqs,
5b0bf5e2 1656 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1657 if (err) {
1a91de28 1658 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1659 goto err_unmap_cq;
1660 }
1661
1662 /*
0ff1fb65
HHZ		 1663 * For flow steering device managed mode it is required to use
1664 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1665 * required, but for simplicity just map the whole multicast
1666 * group table now. The table isn't very big and it's a lot
1667 * easier than trying to track ref counts.
225c7b1f
RD		 1668 */
1669 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1670 init_hca->mc_base,
1671 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1672 dev->caps.num_mgms + dev->caps.num_amgms,
1673 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1674 0, 0);
225c7b1f 1675 if (err) {
1a91de28 1676 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1677 goto err_unmap_srq;
1678 }
1679
1680 return 0;
1681
1682err_unmap_srq:
1683 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1684
1685err_unmap_cq:
1686 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1687
1688err_unmap_rdmarc:
1689 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1690
1691err_unmap_altc:
1692 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1693
1694err_unmap_auxc:
1695 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1696
1697err_unmap_qp:
1698 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1699
1700err_unmap_dmpt:
1701 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1702
1703err_unmap_mtt:
1704 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1705
1706err_unmap_eq:
fa0681d2 1707 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1708
1709err_unmap_cmpt:
1710 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1711 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1712 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1713 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1714
1715err_unmap_aux:
1716 mlx4_UNMAP_ICM_AUX(dev);
1717
1718err_free_aux:
5b0bf5e2 1719 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1720
1721 return err;
1722}
1723
1724static void mlx4_free_icms(struct mlx4_dev *dev)
1725{
1726 struct mlx4_priv *priv = mlx4_priv(dev);
1727
1728 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1729 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1730 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1731 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1732 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1733 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1734 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1735 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1736 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1737 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1738 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1739 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1740 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1741 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1742
1743 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1744 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1745}
1746
ab9c17a0
JM		 1747static void mlx4_slave_exit(struct mlx4_dev *dev)
1748{
1749 struct mlx4_priv *priv = mlx4_priv(dev);
1750
f3d4c89e 1751 mutex_lock(&priv->cmd.slave_cmd_mutex);
0cd93027
YH		 1752 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1753 MLX4_COMM_TIME))
1a91de28 1754 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1755 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1756}
1757
c1b43dca
EC		 1758static int map_bf_area(struct mlx4_dev *dev)
1759{
1760 struct mlx4_priv *priv = mlx4_priv(dev);
1761 resource_size_t bf_start;
1762 resource_size_t bf_len;
1763 int err = 0;
1764
3d747473
JM		 1765 if (!dev->caps.bf_reg_size)
1766 return -ENXIO;
1767
872bf2fb 1768 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1769 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1770 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1771 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1772 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1773 if (!priv->bf_mapping)
1774 err = -ENOMEM;
1775
1776 return err;
1777}
1778
1779static void unmap_bf_area(struct mlx4_dev *dev)
1780{
1781 if (mlx4_priv(dev)->bf_mapping)
1782 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1783}
1784
ec693d47
AV		 1785cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1786{
1787 u32 clockhi, clocklo, clockhi1;
1788 cycle_t cycles;
1789 int i;
1790 struct mlx4_priv *priv = mlx4_priv(dev);
1791
1792 for (i = 0; i < 10; i++) {
1793 clockhi = swab32(readl(priv->clock_mapping));
1794 clocklo = swab32(readl(priv->clock_mapping + 4));
1795 clockhi1 = swab32(readl(priv->clock_mapping));
1796 if (clockhi == clockhi1)
1797 break;
1798 }
1799
1800 cycles = (u64) clockhi << 32 | (u64) clocklo;
1801
1802 return cycles;
1803}
1804EXPORT_SYMBOL_GPL(mlx4_read_clock);
1805
1806
ddd8a6c1
EE		 1807static int map_internal_clock(struct mlx4_dev *dev)
1808{
1809 struct mlx4_priv *priv = mlx4_priv(dev);
1810
1811 priv->clock_mapping =
872bf2fb
YH		 1812 ioremap(pci_resource_start(dev->persist->pdev,
1813 priv->fw.clock_bar) +
ddd8a6c1
EE		 1814 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1815
1816 if (!priv->clock_mapping)
1817 return -ENOMEM;
1818
1819 return 0;
1820}
1821
52033cfb
MB		 1822int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1823 struct mlx4_clock_params *params)
1824{
1825 struct mlx4_priv *priv = mlx4_priv(dev);
1826
1827 if (mlx4_is_slave(dev))
1828 return -ENOTSUPP;
1829
1830 if (!params)
1831 return -EINVAL;
1832
1833 params->bar = priv->fw.clock_bar;
1834 params->offset = priv->fw.clock_offset;
1835 params->size = MLX4_CLOCK_SIZE;
1836
1837 return 0;
1838}
1839EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1840
ddd8a6c1
EE		 1841static void unmap_internal_clock(struct mlx4_dev *dev)
1842{
1843 struct mlx4_priv *priv = mlx4_priv(dev);
1844
1845 if (priv->clock_mapping)
1846 iounmap(priv->clock_mapping);
1847}
1848
225c7b1f
RD		 1849static void mlx4_close_hca(struct mlx4_dev *dev)
1850{
ddd8a6c1 1851 unmap_internal_clock(dev);
c1b43dca 1852 unmap_bf_area(dev);
ab9c17a0
JM		 1853 if (mlx4_is_slave(dev))
1854 mlx4_slave_exit(dev);
1855 else {
1856 mlx4_CLOSE_HCA(dev, 0);
1857 mlx4_free_icms(dev);
a0eacca9
MB		 1858 }
1859}
1860
1861static void mlx4_close_fw(struct mlx4_dev *dev)
1862{
1863 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1864 mlx4_UNMAP_FA(dev);
1865 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1866 }
1867}
1868
55ad3592
YH		 1869static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1870{
1871#define COMM_CHAN_OFFLINE_OFFSET 0x09
1872
1873 u32 comm_flags;
1874 u32 offline_bit;
1875 unsigned long end;
1876 struct mlx4_priv *priv = mlx4_priv(dev);
1877
1878 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1879 while (time_before(jiffies, end)) {
1880 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1881 MLX4_COMM_CHAN_FLAGS));
1882 offline_bit = (comm_flags &
1883 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1884 if (!offline_bit)
1885 return 0;
1886 /* There are cases as part of AER/Reset flow that PF needs
1887 * around 100 msec to load. We therefore sleep for 100 msec
1888 * to allow other tasks to make use of that CPU during this
1889 * time interval.
1890 */
1891 msleep(100);
1892 }
1893 mlx4_err(dev, "Communication channel is offline.\n");
1894 return -EIO;
1895}
1896
1897static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1898{
1899#define COMM_CHAN_RST_OFFSET 0x1e
1900
1901 struct mlx4_priv *priv = mlx4_priv(dev);
1902 u32 comm_rst;
1903 u32 comm_caps;
1904
1905 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1906 MLX4_COMM_CHAN_CAPS));
1907 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1908
1909 if (comm_rst)
1910 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1911}
1912
ab9c17a0
JM		 1913static int mlx4_init_slave(struct mlx4_dev *dev)
1914{
1915 struct mlx4_priv *priv = mlx4_priv(dev);
1916 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1917 int ret_from_reset = 0;
1918 u32 slave_read;
1919 u32 cmd_channel_ver;
1920
97989356 1921 if (atomic_read(&pf_loading)) {
1a91de28 1922 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1923 return -EPROBE_DEFER;
1924 }
1925
f3d4c89e 1926 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1927 priv->cmd.max_cmds = 1;
55ad3592
YH		 1928 if (mlx4_comm_check_offline(dev)) {
1929 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1930 goto err_offline;
1931 }
1932
1933 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 1934 mlx4_warn(dev, "Sending reset\n");
1935 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
0cd93027 1936 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
ab9c17a0
JM		 1937 /* if we are in the middle of flr the slave will try
1938 * NUM_OF_RESET_RETRIES times before leaving.*/
1939 if (ret_from_reset) {
1940 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1941 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1942 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1943 return -EPROBE_DEFER;
ab9c17a0
JM		 1944 } else
1945 goto err;
1946 }
1947
1948 /* check the driver version - the slave I/F revision
1949 * must match the master's */
1950 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1951 cmd_channel_ver = mlx4_comm_get_version();
1952
1953 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1954 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1955 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1956 goto err;
1957 }
1958
1959 mlx4_warn(dev, "Sending vhcr0\n");
1960 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
0cd93027 1961 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 1962 goto err;
1963 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
0cd93027 1964 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 1965 goto err;
1966 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
0cd93027 1967 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 1968 goto err;
0cd93027
YH		 1969 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1970 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 1971 goto err;
f3d4c89e
RD		 1972
1973 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1974 return 0;
1975
1976err:
0cd93027 1977 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
55ad3592 1978err_offline:
f3d4c89e 1979 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1980 return -EIO;
225c7b1f
RD		 1981}
1982
6634961c
JM		 1983static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1984{
1985 int i;
1986
1987 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1988 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1989 dev->caps.gid_table_len[i] =
449fc488 1990 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1991 else
1992 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1993 dev->caps.pkey_table_len[i] =
1994 dev->phys_caps.pkey_phys_table_len[i] - 1;
1995 }
1996}
1997
3c439b55
JM		 1998static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1999{
2000 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2001
2002 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2003 i++) {
2004 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2005 break;
2006 }
2007
2008 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2009}
2010
7d077cd3
MB		 2011static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2012{
2013 switch (dmfs_high_steer_mode) {
2014 case MLX4_STEERING_DMFS_A0_DEFAULT:
2015 return "default performance";
2016
2017 case MLX4_STEERING_DMFS_A0_DYNAMIC:
2018 return "dynamic hybrid mode";
2019
2020 case MLX4_STEERING_DMFS_A0_STATIC:
2021 return "performance optimized for limited rule configuration (static)";
2022
2023 case MLX4_STEERING_DMFS_A0_DISABLE:
2024 return "disabled performance optimized steering";
2025
2026 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2027 return "performance optimized steering not supported";
2028
2029 default:
2030 return "Unrecognized mode";
2031 }
2032}
2033
2034#define MLX4_DMFS_A0_STEERING (1UL << 2)
2035
7b8157be
JM		 2036static void choose_steering_mode(struct mlx4_dev *dev,
2037 struct mlx4_dev_cap *dev_cap)
2038{
7d077cd3
MB		 2039 if (mlx4_log_num_mgm_entry_size <= 0) {
2040 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2041 if (dev->caps.dmfs_high_steer_mode ==
2042 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2043 mlx4_err(dev, "DMFS high rate mode not supported\n");
2044 else
2045 dev->caps.dmfs_high_steer_mode =
2046 MLX4_STEERING_DMFS_A0_STATIC;
2047 }
2048 }
2049
2050 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 2051 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 2052 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 2053 (dev_cap->fs_max_num_qp_per_entry >=
2054 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 2055 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2056 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2057 dev->oper_log_mgm_entry_size =
2058 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 2059 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2060 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2061 dev->caps.fs_log_max_ucast_qp_range_size =
2062 dev_cap->fs_log_max_ucast_qp_range_size;
2063 } else {
7d077cd3
MB		 2064 if (dev->caps.dmfs_high_steer_mode !=
2065 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2066 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 2067 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2068 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2069 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2070 else {
2071 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2072
2073 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2074 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 2075 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 2076 }
3c439b55
JM		 2077 dev->oper_log_mgm_entry_size =
2078 mlx4_log_num_mgm_entry_size > 0 ?
2079 mlx4_log_num_mgm_entry_size :
2080 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 2081 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2082 }
1a91de28 2083 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 2084 mlx4_steering_mode_str(dev->caps.steering_mode),
2085 dev->oper_log_mgm_entry_size,
2086 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 2087}
2088
7ffdf726
OG		 2089static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2090 struct mlx4_dev_cap *dev_cap)
2091{
2092 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
5eff6dad 2093 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
7ffdf726
OG		 2094 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2095 else
2096 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2097
2098 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2099 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2100}
2101
7d077cd3
MB		 2102static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2103{
2104 int i;
2105 struct mlx4_port_cap port_cap;
2106
2107 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2108 return -EINVAL;
2109
2110 for (i = 1; i <= dev->caps.num_ports; i++) {
2111 if (mlx4_dev_port(dev, i, &port_cap)) {
2112 mlx4_err(dev,
2113 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2114 } else if ((dev->caps.dmfs_high_steer_mode !=
2115 MLX4_STEERING_DMFS_A0_DEFAULT) &&
2116 (port_cap.dmfs_optimized_state ==
2117 !!(dev->caps.dmfs_high_steer_mode ==
2118 MLX4_STEERING_DMFS_A0_DISABLE))) {
2119 mlx4_err(dev,
2120 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2121 dmfs_high_rate_steering_mode_str(
2122 dev->caps.dmfs_high_steer_mode),
2123 (port_cap.dmfs_optimized_state ?
2124 "enabled" : "disabled"));
2125 }
2126 }
2127
2128 return 0;
2129}
2130
a0eacca9 2131static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 2132{
2d928651 2133 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 2134 int err = 0;
225c7b1f 2135
ab9c17a0
JM		 2136 if (!mlx4_is_slave(dev)) {
2137 err = mlx4_QUERY_FW(dev);
2138 if (err) {
2139 if (err == -EACCES)
1a91de28 2140 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 2141 else
1a91de28 2142 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 2143 return err;
ab9c17a0 2144 }
225c7b1f 2145
ab9c17a0
JM		 2146 err = mlx4_load_fw(dev);
2147 if (err) {
1a91de28 2148 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 2149 return err;
ab9c17a0 2150 }
225c7b1f 2151
ab9c17a0
JM		 2152 mlx4_cfg.log_pg_sz_m = 1;
2153 mlx4_cfg.log_pg_sz = 0;
2154 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2155 if (err)
2156 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 2157 }
2d928651 2158
a0eacca9
MB		 2159 return err;
2160}
2161
2162static int mlx4_init_hca(struct mlx4_dev *dev)
2163{
2164 struct mlx4_priv *priv = mlx4_priv(dev);
2165 struct mlx4_adapter adapter;
2166 struct mlx4_dev_cap dev_cap;
2167 struct mlx4_profile profile;
2168 struct mlx4_init_hca_param init_hca;
2169 u64 icm_size;
2170 struct mlx4_config_dev_params params;
2171 int err;
2172
2173 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2174 err = mlx4_dev_cap(dev, &dev_cap);
2175 if (err) {
1a91de28 2176 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
d0d01250 2177 return err;
ab9c17a0 2178 }
225c7b1f 2179
7b8157be 2180 choose_steering_mode(dev, &dev_cap);
7ffdf726 2181 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 2182
7d077cd3
MB		 2183 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2184 mlx4_is_master(dev))
2185 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2186
8e1a28e8
HHZ		 2187 err = mlx4_get_phys_port_id(dev);
2188 if (err)
2189 mlx4_err(dev, "Fail to get physical port id\n");
2190
6634961c
JM		 2191 if (mlx4_is_master(dev))
2192 mlx4_parav_master_pf_caps(dev);
2193
2599d858
AV		 2194 if (mlx4_low_memory_profile()) {
2195 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2196 profile = low_mem_profile;
2197 } else {
2198 profile = default_profile;
2199 }
0ff1fb65
HHZ		 2200 if (dev->caps.steering_mode ==
2201 MLX4_STEERING_MODE_DEVICE_MANAGED)
2202 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 2203
ab9c17a0
JM		 2204 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2205 &init_hca);
2206 if ((long long) icm_size < 0) {
2207 err = icm_size;
d0d01250 2208 return err;
ab9c17a0 2209 }
225c7b1f 2210
a5bbe892
EC		 2211 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2212
85743f1e
HN		 2213 /* Always set UAR page size 4KB, set log_uar_sz accordingly */
2214 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2215 PAGE_SHIFT -
2216 DEFAULT_UAR_PAGE_SHIFT;
2217 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2218
e448834e
SM		 2219 init_hca.mw_enabled = 0;
2220 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2221 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2222 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 2223
ab9c17a0
JM		 2224 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2225 if (err)
d0d01250 2226 return err;
225c7b1f 2227
ab9c17a0
JM		 2228 err = mlx4_INIT_HCA(dev, &init_hca);
2229 if (err) {
1a91de28 2230 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 2231 goto err_free_icm;
2232 }
7ae0e400
MB		 2233
2234 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2235 err = mlx4_query_func(dev, &dev_cap);
2236 if (err < 0) {
2237 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 2238 goto err_close;
7ae0e400
MB		 2239 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2240 dev->caps.num_eqs = dev_cap.max_eqs;
2241 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2242 dev->caps.reserved_uars = dev_cap.reserved_uars;
2243 }
2244 }
2245
ddd8a6c1
EE		 2246 /*
2247 * If TS is supported by FW
2248 * read HCA frequency by QUERY_HCA command
2249 */
2250 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2251 memset(&init_hca, 0, sizeof(init_hca));
2252 err = mlx4_QUERY_HCA(dev, &init_hca);
2253 if (err) {
1a91de28 2254 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 2255 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2256 } else {
2257 dev->caps.hca_core_clock =
2258 init_hca.hca_core_clock;
2259 }
2260
2261 /* In case we got HCA frequency 0 - disable timestamping
2262 * to avoid dividing by zero
2263 */
2264 if (!dev->caps.hca_core_clock) {
2265 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2266 mlx4_err(dev,
1a91de28 2267 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 2268 } else if (map_internal_clock(dev)) {
2269 /*
2270 * Map internal clock,
2271 * in case of failure disable timestamping
2272 */
2273 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 2274 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 2275 }
2276 }
7d077cd3
MB		 2277
2278 if (dev->caps.dmfs_high_steer_mode !=
2279 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2280 if (mlx4_validate_optimized_steering(dev))
2281 mlx4_warn(dev, "Optimized steering validation failed\n");
2282
2283 if (dev->caps.dmfs_high_steer_mode ==
2284 MLX4_STEERING_DMFS_A0_DISABLE) {
2285 dev->caps.dmfs_high_rate_qpn_base =
2286 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2287 dev->caps.dmfs_high_rate_qpn_range =
2288 MLX4_A0_STEERING_TABLE_SIZE;
2289 }
2290
2291 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2292 dmfs_high_rate_steering_mode_str(
2293 dev->caps.dmfs_high_steer_mode));
2294 }
ab9c17a0
JM		 2295 } else {
2296 err = mlx4_init_slave(dev);
2297 if (err) {
5efe5355
JM		 2298 if (err != -EPROBE_DEFER)
2299 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2300 return err;
ab9c17a0 2301 }
225c7b1f 2302
ab9c17a0
JM		 2303 err = mlx4_slave_cap(dev);
2304 if (err) {
2305 mlx4_err(dev, "Failed to obtain slave caps\n");
2306 goto err_close;
2307 }
225c7b1f
RD		 2308 }
2309
ab9c17a0
JM		 2310 if (map_bf_area(dev))
2311 mlx4_dbg(dev, "Failed to map blue flame area\n");
2312
2313 /*Only the master set the ports, all the rest got it from it.*/
2314 if (!mlx4_is_slave(dev))
2315 mlx4_set_port_mask(dev);
2316
225c7b1f
RD		 2317 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2318 if (err) {
1a91de28 2319 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2320 goto unmap_bf;
225c7b1f
RD		 2321 }
2322
f8c6455b
SM		 2323 /* Query CONFIG_DEV parameters */
2324 err = mlx4_config_dev_retrieval(dev, &params);
2325 if (err && err != -ENOTSUPP) {
2326 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2327 } else if (!err) {
2328 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2329 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2330 }
225c7b1f 2331 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 2332 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 2333
2334 return 0;
2335
bef772eb 2336unmap_bf:
ddd8a6c1 2337 unmap_internal_clock(dev);
bef772eb
AY		 2338 unmap_bf_area(dev);
2339
b38f2879 2340 if (mlx4_is_slave(dev)) {
99ec41d0 2341 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2342 kfree(dev->caps.qp0_tunnel);
2343 kfree(dev->caps.qp0_proxy);
2344 kfree(dev->caps.qp1_tunnel);
2345 kfree(dev->caps.qp1_proxy);
2346 }
2347
225c7b1f 2348err_close:
41929ed2
DB		 2349 if (mlx4_is_slave(dev))
2350 mlx4_slave_exit(dev);
2351 else
2352 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2353
2354err_free_icm:
ab9c17a0
JM		 2355 if (!mlx4_is_slave(dev))
2356 mlx4_free_icms(dev);
225c7b1f 2357
225c7b1f
RD		 2358 return err;
2359}
2360
f2a3f6a3
OG		 2361static int mlx4_init_counters_table(struct mlx4_dev *dev)
2362{
2363 struct mlx4_priv *priv = mlx4_priv(dev);
47d8417f 2364 int nent_pow2;
f2a3f6a3
OG		 2365
2366 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2367 return -ENOENT;
2368
2632d18d
EBE		 2369 if (!dev->caps.max_counters)
2370 return -ENOSPC;
2371
47d8417f
EBE		 2372 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2373 /* reserve last counter index for sink counter */
2374 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2375 nent_pow2 - 1, 0,
2376 nent_pow2 - dev->caps.max_counters + 1);
f2a3f6a3
OG		 2377}
2378
2379static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2380{
efa6bc91
EBE		 2381 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2382 return;
2383
2632d18d
EBE		 2384 if (!dev->caps.max_counters)
2385 return;
2386
f2a3f6a3
OG		 2387 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2388}
2389
6de5f7f6
EBE		 2390static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2391{
2392 struct mlx4_priv *priv = mlx4_priv(dev);
2393 int port;
2394
2395 for (port = 0; port < dev->caps.num_ports; port++)
2396 if (priv->def_counter[port] != -1)
2397 mlx4_counter_free(dev, priv->def_counter[port]);
2398}
2399
2400static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2401{
2402 struct mlx4_priv *priv = mlx4_priv(dev);
2403 int port, err = 0;
2404 u32 idx;
2405
2406 for (port = 0; port < dev->caps.num_ports; port++)
2407 priv->def_counter[port] = -1;
2408
2409 for (port = 0; port < dev->caps.num_ports; port++) {
2410 err = mlx4_counter_alloc(dev, &idx);
2411
2412 if (!err || err == -ENOSPC) {
2413 priv->def_counter[port] = idx;
2414 } else if (err == -ENOENT) {
2415 err = 0;
2416 continue;
178d23e3
OG		 2417 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2418 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2419 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2420 MLX4_SINK_COUNTER_INDEX(dev));
2421 err = 0;
6de5f7f6
EBE		 2422 } else {
2423 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2424 __func__, port + 1, err);
2425 mlx4_cleanup_default_counters(dev);
2426 return err;
2427 }
2428
2429 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2430 __func__, priv->def_counter[port], port + 1);
2431 }
2432
2433 return err;
2434}
2435
ba062d52 2436int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2437{
2438 struct mlx4_priv *priv = mlx4_priv(dev);
2439
2440 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2441 return -ENOENT;
2442
2443 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
6de5f7f6
EBE		 2444 if (*idx == -1) {
2445 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2446 return -ENOSPC;
2447 }
f2a3f6a3
OG		 2448
2449 return 0;
2450}
ba062d52
JM		 2451
2452int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2453{
2454 u64 out_param;
2455 int err;
2456
2457 if (mlx4_is_mfunc(dev)) {
2458 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2459 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2460 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2461 if (!err)
2462 *idx = get_param_l(&out_param);
2463
2464 return err;
2465 }
2466 return __mlx4_counter_alloc(dev, idx);
2467}
f2a3f6a3
OG		 2468EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2469
b72ca7e9
EBE		 2470static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2471 u8 counter_index)
2472{
2473 struct mlx4_cmd_mailbox *if_stat_mailbox;
2474 int err;
2475 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2476
2477 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2478 if (IS_ERR(if_stat_mailbox))
2479 return PTR_ERR(if_stat_mailbox);
2480
2481 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2482 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2483 MLX4_CMD_NATIVE);
2484
2485 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2486 return err;
2487}
2488
ba062d52 2489void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2490{
efa6bc91
EBE		 2491 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2492 return;
2493
6de5f7f6
EBE		 2494 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2495 return;
2496
b72ca7e9
EBE		 2497 __mlx4_clear_if_stat(dev, idx);
2498
7c6d74d2 2499 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2500 return;
2501}
ba062d52
JM		 2502
2503void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2504{
e7dbeba8 2505 u64 in_param = 0;
ba062d52
JM		 2506
2507 if (mlx4_is_mfunc(dev)) {
2508 set_param_l(&in_param, idx);
2509 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2510 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2511 MLX4_CMD_WRAPPED);
2512 return;
2513 }
2514 __mlx4_counter_free(dev, idx);
2515}
f2a3f6a3
OG		 2516EXPORT_SYMBOL_GPL(mlx4_counter_free);
2517
6de5f7f6
EBE		 2518int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2519{
2520 struct mlx4_priv *priv = mlx4_priv(dev);
2521
2522 return priv->def_counter[port - 1];
2523}
2524EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2525
773af94e
YH		 2526void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2527{
2528 struct mlx4_priv *priv = mlx4_priv(dev);
2529
2530 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2531}
2532EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2533
2534__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2535{
2536 struct mlx4_priv *priv = mlx4_priv(dev);
2537
2538 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2539}
2540EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2541
fb517a4f
YH		 2542void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2543{
2544 struct mlx4_priv *priv = mlx4_priv(dev);
2545 __be64 guid;
2546
2547 /* hw GUID */
2548 if (entry == 0)
2549 return;
2550
2551 get_random_bytes((char *)&guid, sizeof(guid));
2552 guid &= ~(cpu_to_be64(1ULL << 56));
2553 guid |= cpu_to_be64(1ULL << 57);
2554 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2555}
2556
3d73c288 2557static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2558{
2559 struct mlx4_priv *priv = mlx4_priv(dev);
2560 int err;
7ff93f8b 2561 int port;
9a5aa622 2562 __be32 ib_port_default_caps;
225c7b1f 2563
225c7b1f
RD		 2564 err = mlx4_init_uar_table(dev);
2565 if (err) {
1a91de28
JP		 2566 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2567 return err;
225c7b1f
RD		 2568 }
2569
2570 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2571 if (err) {
1a91de28 2572 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2573 goto err_uar_table_free;
2574 }
2575
4979d18f 2576 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2577 if (!priv->kar) {
1a91de28 2578 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2579 err = -ENOMEM;
2580 goto err_uar_free;
2581 }
2582
2583 err = mlx4_init_pd_table(dev);
2584 if (err) {
1a91de28 2585 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2586 goto err_kar_unmap;
2587 }
2588
012a8ff5
SH		 2589 err = mlx4_init_xrcd_table(dev);
2590 if (err) {
1a91de28 2591 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2592 goto err_pd_table_free;
2593 }
2594
225c7b1f
RD		 2595 err = mlx4_init_mr_table(dev);
2596 if (err) {
1a91de28 2597 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2598 goto err_xrcd_table_free;
225c7b1f
RD		 2599 }
2600
fe6f700d
YP		 2601 if (!mlx4_is_slave(dev)) {
2602 err = mlx4_init_mcg_table(dev);
2603 if (err) {
1a91de28 2604 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2605 goto err_mr_table_free;
2606 }
114840c3
JM		 2607 err = mlx4_config_mad_demux(dev);
2608 if (err) {
2609 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2610 goto err_mcg_table_free;
2611 }
fe6f700d
YP		 2612 }
2613
225c7b1f
RD		 2614 err = mlx4_init_eq_table(dev);
2615 if (err) {
1a91de28 2616 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2617 goto err_mcg_table_free;
225c7b1f
RD		 2618 }
2619
2620 err = mlx4_cmd_use_events(dev);
2621 if (err) {
1a91de28 2622 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2623 goto err_eq_table_free;
2624 }
2625
2626 err = mlx4_NOP(dev);
2627 if (err) {
08fb1055 2628 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2629 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
c66fa19c 2630 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
1a91de28 2631 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2632 } else {
1a91de28 2633 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
c66fa19c 2634 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 2635 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2636 }
225c7b1f
RD		 2637
2638 goto err_cmd_poll;
2639 }
2640
2641 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2642
2643 err = mlx4_init_cq_table(dev);
2644 if (err) {
1a91de28 2645 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2646 goto err_cmd_poll;
2647 }
2648
2649 err = mlx4_init_srq_table(dev);
2650 if (err) {
1a91de28 2651 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2652 goto err_cq_table_free;
2653 }
2654
2655 err = mlx4_init_qp_table(dev);
2656 if (err) {
1a91de28 2657 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2658 goto err_srq_table_free;
2659 }
2660
2632d18d
EBE		 2661 if (!mlx4_is_slave(dev)) {
2662 err = mlx4_init_counters_table(dev);
2663 if (err && err != -ENOENT) {
2664 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2665 goto err_qp_table_free;
2666 }
f2a3f6a3
OG		 2667 }
2668
6de5f7f6
EBE		 2669 err = mlx4_allocate_default_counters(dev);
2670 if (err) {
2671 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2672 goto err_counters_table_free;
f2a3f6a3
OG		 2673 }
2674
ab9c17a0
JM		 2675 if (!mlx4_is_slave(dev)) {
2676 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2677 ib_port_default_caps = 0;
2678 err = mlx4_get_port_ib_caps(dev, port,
2679 &ib_port_default_caps);
2680 if (err)
1a91de28
JP		 2681 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2682 port, err);
ab9c17a0
JM		 2683 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2684
2aca1172
JM		 2685 /* initialize per-slave default ib port capabilities */
2686 if (mlx4_is_master(dev)) {
2687 int i;
2688 for (i = 0; i < dev->num_slaves; i++) {
2689 if (i == mlx4_master_func_num(dev))
2690 continue;
2691 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2692 ib_port_default_caps;
2aca1172
JM		 2693 }
2694 }
2695
096335b3
OG		 2696 if (mlx4_is_mfunc(dev))
2697 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2698 else
2699 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2700
6634961c
JM		 2701 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2702 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2703 if (err) {
2704 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2705 port);
6de5f7f6 2706 goto err_default_countes_free;
ab9c17a0 2707 }
7ff93f8b
YP		 2708 }
2709 }
2710
225c7b1f
RD		 2711 return 0;
2712
6de5f7f6
EBE		 2713err_default_countes_free:
2714 mlx4_cleanup_default_counters(dev);
2715
f2a3f6a3 2716err_counters_table_free:
2632d18d
EBE		 2717 if (!mlx4_is_slave(dev))
2718 mlx4_cleanup_counters_table(dev);
f2a3f6a3 2719
225c7b1f
RD		 2720err_qp_table_free:
2721 mlx4_cleanup_qp_table(dev);
2722
2723err_srq_table_free:
2724 mlx4_cleanup_srq_table(dev);
2725
2726err_cq_table_free:
2727 mlx4_cleanup_cq_table(dev);
2728
2729err_cmd_poll:
2730 mlx4_cmd_use_polling(dev);
2731
2732err_eq_table_free:
2733 mlx4_cleanup_eq_table(dev);
2734
fe6f700d
YP		 2735err_mcg_table_free:
2736 if (!mlx4_is_slave(dev))
2737 mlx4_cleanup_mcg_table(dev);
2738
ee49bd93 2739err_mr_table_free:
225c7b1f
RD		 2740 mlx4_cleanup_mr_table(dev);
2741
012a8ff5
SH		 2742err_xrcd_table_free:
2743 mlx4_cleanup_xrcd_table(dev);
2744
225c7b1f
RD		 2745err_pd_table_free:
2746 mlx4_cleanup_pd_table(dev);
2747
2748err_kar_unmap:
2749 iounmap(priv->kar);
2750
2751err_uar_free:
2752 mlx4_uar_free(dev, &priv->driver_uar);
2753
2754err_uar_table_free:
2755 mlx4_cleanup_uar_table(dev);
2756 return err;
2757}
2758
de161803
IS		 2759static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2760{
2761 int requested_cpu = 0;
2762 struct mlx4_priv *priv = mlx4_priv(dev);
2763 struct mlx4_eq *eq;
2764 int off = 0;
2765 int i;
2766
2767 if (eqn > dev->caps.num_comp_vectors)
2768 return -EINVAL;
2769
2770 for (i = 1; i < port; i++)
2771 off += mlx4_get_eqs_per_port(dev, i);
2772
2773 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2774
2775 /* Meaning EQs are shared, and this call comes from the second port */
2776 if (requested_cpu < 0)
2777 return 0;
2778
2779 eq = &priv->eq_table.eq[eqn];
2780
2781 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2782 return -ENOMEM;
2783
2784 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2785
2786 return 0;
2787}
2788
e8f9b2ed 2789static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2790{
2791 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2792 struct msix_entry *entries;
225c7b1f 2793 int i;
c66fa19c 2794 int port = 0;
225c7b1f
RD		 2795
2796 if (msi_x) {
c66fa19c 2797 int nreq = dev->caps.num_ports * num_online_cpus() + 1;
7ae0e400 2798
ca4c7b35
OG		 2799 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2800 nreq);
85121d6e 2801 if (nreq > MAX_MSIX)
9293267a 2802 nreq = MAX_MSIX;
ab9c17a0 2803
b8dd786f
YP		 2804 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2805 if (!entries)
2806 goto no_msi;
2807
2808 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2809 entries[i].entry = i;
2810
872bf2fb
YH		 2811 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2812 nreq);
66e2f9c1 2813
c66fa19c 2814 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
5bf0da7d 2815 kfree(entries);
225c7b1f 2816 goto no_msi;
0b7ca5a9 2817 }
c66fa19c
MB		 2818 /* 1 is reserved for events (asyncrounous EQ) */
2819 dev->caps.num_comp_vectors = nreq - 1;
2820
2821 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2822 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2823 dev->caps.num_ports);
2824
2825 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2826 if (i == MLX4_EQ_ASYNC)
2827 continue;
2828
2829 priv->eq_table.eq[i].irq =
2830 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2831
85121d6e 2832 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
c66fa19c
MB		 2833 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2834 dev->caps.num_ports);
de161803
IS		 2835 /* We don't set affinity hint when there
2836 * aren't enough EQs
2837 */
c66fa19c
MB		 2838 } else {
2839 set_bit(port,
2840 priv->eq_table.eq[i].actv_ports.ports);
de161803
IS		 2841 if (mlx4_init_affinity_hint(dev, port + 1, i))
2842 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2843 i);
c66fa19c
MB		 2844 }
2845 /* We divide the Eqs evenly between the two ports.
2846 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2847 * refers to the number of Eqs per port
2848 * (i.e eqs_per_port). Theoretically, we would like to
2849 * write something like (i + 1) % eqs_per_port == 0.
2850 * However, since there's an asynchronous Eq, we have
2851 * to skip over it by comparing this condition to
2852 * !!((i + 1) > MLX4_EQ_ASYNC).
2853 */
2854 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2855 ((i + 1) %
2856 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2857 !!((i + 1) > MLX4_EQ_ASYNC))
2858 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2859 * everything is shared anyway.
2860 */
2861 port++;
2862 }
225c7b1f
RD		 2863
2864 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2865
2866 kfree(entries);
225c7b1f
RD		 2867 return;
2868 }
2869
2870no_msi:
b8dd786f
YP		 2871 dev->caps.num_comp_vectors = 1;
2872
c66fa19c
MB		 2873 BUG_ON(MLX4_EQ_ASYNC >= 2);
2874 for (i = 0; i < 2; ++i) {
872bf2fb 2875 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
c66fa19c
MB		 2876 if (i != MLX4_EQ_ASYNC) {
2877 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2878 dev->caps.num_ports);
2879 }
2880 }
225c7b1f
RD		 2881}
2882
7ff93f8b 2883static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8 2884{
09d4d087 2885 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2a2336f8 2886 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
09d4d087
JP		 2887 int err;
2888
2889 err = devlink_port_register(devlink, &info->devlink_port, port);
2890 if (err)
2891 return err;
2a2336f8
YP		 2892
2893 info->dev = dev;
2894 info->port = port;
ab9c17a0 2895 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2896 mlx4_init_mac_table(dev, &info->mac_table);
2897 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2898 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2899 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2900 }
7ff93f8b
YP		 2901
2902 sprintf(info->dev_name, "mlx4_port%d", port);
2903 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2904 if (mlx4_is_mfunc(dev))
2905 info->port_attr.attr.mode = S_IRUGO;
2906 else {
2907 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2908 info->port_attr.store = set_port_type;
2909 }
7ff93f8b 2910 info->port_attr.show = show_port_type;
3691c964 2911 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 2912
872bf2fb 2913 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 2914 if (err) {
2915 mlx4_err(dev, "Failed to create file for port %d\n", port);
09d4d087 2916 devlink_port_unregister(&info->devlink_port);
7ff93f8b
YP		 2917 info->port = -1;
2918 }
2919
096335b3
OG		 2920 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2921 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2922 if (mlx4_is_mfunc(dev))
2923 info->port_mtu_attr.attr.mode = S_IRUGO;
2924 else {
2925 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2926 info->port_mtu_attr.store = set_port_ib_mtu;
2927 }
2928 info->port_mtu_attr.show = show_port_ib_mtu;
2929 sysfs_attr_init(&info->port_mtu_attr.attr);
2930
872bf2fb
YH		 2931 err = device_create_file(&dev->persist->pdev->dev,
2932 &info->port_mtu_attr);
096335b3
OG		 2933 if (err) {
2934 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 2935 device_remove_file(&info->dev->persist->pdev->dev,
2936 &info->port_attr);
096335b3
OG		 2937 info->port = -1;
2938 }
2939
7ff93f8b
YP		 2940 return err;
2941}
2942
2943static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2944{
2945 if (info->port < 0)
2946 return;
2947
872bf2fb
YH		 2948 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2949 device_remove_file(&info->dev->persist->pdev->dev,
2950 &info->port_mtu_attr);
c66fa19c
MB		 2951#ifdef CONFIG_RFS_ACCEL
2952 free_irq_cpu_rmap(info->rmap);
2953 info->rmap = NULL;
2954#endif
2a2336f8
YP		 2955}
2956
b12d93d6
YP		 2957static int mlx4_init_steering(struct mlx4_dev *dev)
2958{
2959 struct mlx4_priv *priv = mlx4_priv(dev);
2960 int num_entries = dev->caps.num_ports;
2961 int i, j;
2962
2963 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2964 if (!priv->steer)
2965 return -ENOMEM;
2966
45b51365 2967 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2968 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2969 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2970 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2971 }
b12d93d6
YP		 2972 return 0;
2973}
2974
2975static void mlx4_clear_steering(struct mlx4_dev *dev)
2976{
2977 struct mlx4_priv *priv = mlx4_priv(dev);
2978 struct mlx4_steer_index *entry, *tmp_entry;
2979 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2980 int num_entries = dev->caps.num_ports;
2981 int i, j;
2982
2983 for (i = 0; i < num_entries; i++) {
2984 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2985 list_for_each_entry_safe(pqp, tmp_pqp,
2986 &priv->steer[i].promisc_qps[j],
2987 list) {
2988 list_del(&pqp->list);
2989 kfree(pqp);
2990 }
2991 list_for_each_entry_safe(entry, tmp_entry,
2992 &priv->steer[i].steer_entries[j],
2993 list) {
2994 list_del(&entry->list);
2995 list_for_each_entry_safe(pqp, tmp_pqp,
2996 &entry->duplicates,
2997 list) {
2998 list_del(&pqp->list);
2999 kfree(pqp);
3000 }
3001 kfree(entry);
3002 }
3003 }
3004 }
3005 kfree(priv->steer);
3006}
3007
ab9c17a0
JM		 3008static int extended_func_num(struct pci_dev *pdev)
3009{
3010 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3011}
3012
3013#define MLX4_OWNER_BASE 0x8069c
3014#define MLX4_OWNER_SIZE 4
3015
3016static int mlx4_get_ownership(struct mlx4_dev *dev)
3017{
3018 void __iomem *owner;
3019 u32 ret;
3020
872bf2fb 3021 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3022 return -EIO;
3023
872bf2fb
YH		 3024 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3025 MLX4_OWNER_BASE,
ab9c17a0
JM		 3026 MLX4_OWNER_SIZE);
3027 if (!owner) {
3028 mlx4_err(dev, "Failed to obtain ownership bit\n");
3029 return -ENOMEM;
3030 }
3031
3032 ret = readl(owner);
3033 iounmap(owner);
3034 return (int) !!ret;
3035}
3036
3037static void mlx4_free_ownership(struct mlx4_dev *dev)
3038{
3039 void __iomem *owner;
3040
872bf2fb 3041 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3042 return;
3043
872bf2fb
YH		 3044 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3045 MLX4_OWNER_BASE,
ab9c17a0
JM		 3046 MLX4_OWNER_SIZE);
3047 if (!owner) {
3048 mlx4_err(dev, "Failed to obtain ownership bit\n");
3049 return;
3050 }
3051 writel(0, owner);
3052 msleep(1000);
3053 iounmap(owner);
3054}
3055
a0eacca9
MB		 3056#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3057 !!((flags) & MLX4_FLAG_MASTER))
3058
3059static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 3060 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 3061{
3062 u64 dev_flags = dev->flags;
da315679 3063 int err = 0;
0beb44b0
CS		 3064 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3065 MLX4_MAX_NUM_VF);
a0eacca9 3066
55ad3592
YH		 3067 if (reset_flow) {
3068 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3069 GFP_KERNEL);
3070 if (!dev->dev_vfs)
3071 goto free_mem;
3072 return dev_flags;
3073 }
3074
da315679
MB		 3075 atomic_inc(&pf_loading);
3076 if (dev->flags & MLX4_FLAG_SRIOV) {
3077 if (existing_vfs != total_vfs) {
3078 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3079 existing_vfs, total_vfs);
3080 total_vfs = existing_vfs;
3081 }
3082 }
3083
3084 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 3085 if (NULL == dev->dev_vfs) {
3086 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3087 goto disable_sriov;
da315679
MB		 3088 }
3089
3090 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
0beb44b0
CS		 3091 if (total_vfs > fw_enabled_sriov_vfs) {
3092 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3093 total_vfs, fw_enabled_sriov_vfs);
3094 err = -ENOMEM;
3095 goto disable_sriov;
3096 }
da315679
MB		 3097 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3098 err = pci_enable_sriov(pdev, total_vfs);
3099 }
3100 if (err) {
3101 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3102 err);
3103 goto disable_sriov;
3104 } else {
3105 mlx4_warn(dev, "Running in master mode\n");
3106 dev_flags |= MLX4_FLAG_SRIOV |
3107 MLX4_FLAG_MASTER;
3108 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 3109 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 3110 }
3111 return dev_flags;
3112
3113disable_sriov:
da315679 3114 atomic_dec(&pf_loading);
55ad3592 3115free_mem:
872bf2fb 3116 dev->persist->num_vfs = 0;
a0eacca9 3117 kfree(dev->dev_vfs);
5114a04e 3118 dev->dev_vfs = NULL;
a0eacca9
MB		 3119 return dev_flags & ~MLX4_FLAG_MASTER;
3120}
3121
de966c59
MB		 3122enum {
3123 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3124};
3125
3126static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3127 int *nvfs)
3128{
3129 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3130 /* Checking for 64 VFs as a limitation of CX2 */
3131 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3132 requested_vfs >= 64) {
3133 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3134 requested_vfs);
3135 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3136 }
3137 return 0;
3138}
3139
e1c00e10 3140static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 3141 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3142 int reset_flow)
225c7b1f 3143{
225c7b1f 3144 struct mlx4_dev *dev;
e1c00e10 3145 unsigned sum = 0;
225c7b1f 3146 int err;
2a2336f8 3147 int port;
e1c00e10 3148 int i;
7ae0e400 3149 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 3150 int existing_vfs = 0;
225c7b1f 3151
e1c00e10 3152 dev = &priv->dev;
225c7b1f 3153
b581401e
RD		 3154 INIT_LIST_HEAD(&priv->ctx_list);
3155 spin_lock_init(&priv->ctx_lock);
225c7b1f 3156
7ff93f8b 3157 mutex_init(&priv->port_mutex);
53f33ae2 3158 mutex_init(&priv->bond_mutex);
7ff93f8b 3159
6296883c
YP		 3160 INIT_LIST_HEAD(&priv->pgdir_list);
3161 mutex_init(&priv->pgdir_mutex);
3162
c1b43dca
EC		 3163 INIT_LIST_HEAD(&priv->bf_list);
3164 mutex_init(&priv->bf_mutex);
3165
aca7a3ac 3166 dev->rev_id = pdev->revision;
6e7136ed 3167 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 3168
ab9c17a0 3169 /* Detect if this device is a virtual function */
839f1243 3170 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 3171 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3172 dev->flags |= MLX4_FLAG_SLAVE;
3173 } else {
3174 /* We reset the device and enable SRIOV only for physical
3175 * devices. Try to claim ownership on the device;
3176 * if already taken, skip -- do not allow multiple PFs */
3177 err = mlx4_get_ownership(dev);
3178 if (err) {
3179 if (err < 0)
e1c00e10 3180 return err;
ab9c17a0 3181 else {
1a91de28 3182 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 3183 return -EINVAL;
ab9c17a0
JM		 3184 }
3185 }
aca7a3ac 3186
fe6f700d
YP		 3187 atomic_set(&priv->opreq_count, 0);
3188 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3189
ab9c17a0
JM		 3190 /*
3191 * Now reset the HCA before we touch the PCI capabilities or
3192 * attempt a firmware command, since a boot ROM may have left
3193 * the HCA in an undefined state.
3194 */
3195 err = mlx4_reset(dev);
3196 if (err) {
1a91de28 3197 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 3198 goto err_sriov;
ab9c17a0 3199 }
7ae0e400
MB		 3200
3201 if (total_vfs) {
7ae0e400 3202 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 3203 existing_vfs = pci_num_vf(pdev);
3204 if (existing_vfs)
3205 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 3206 dev->persist->num_vfs = total_vfs;
7ae0e400 3207 }
225c7b1f
RD		 3208 }
3209
f6bc11e4
YH		 3210 /* on load remove any previous indication of internal error,
3211 * device is up.
3212 */
3213 dev->persist->state = MLX4_DEVICE_STATE_UP;
3214
ab9c17a0 3215slave_start:
521130d1
EE		 3216 err = mlx4_cmd_init(dev);
3217 if (err) {
1a91de28 3218 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 3219 goto err_sriov;
3220 }
3221
3222 /* In slave functions, the communication channel must be initialized
3223 * before posting commands. Also, init num_slaves before calling
3224 * mlx4_init_hca */
3225 if (mlx4_is_mfunc(dev)) {
7ae0e400 3226 if (mlx4_is_master(dev)) {
ab9c17a0 3227 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 3228
3229 } else {
ab9c17a0 3230 dev->num_slaves = 0;
f356fcbe
JM		 3231 err = mlx4_multi_func_init(dev);
3232 if (err) {
1a91de28 3233 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 3234 goto err_cmd;
3235 }
3236 }
225c7b1f
RD		 3237 }
3238
a0eacca9
MB		 3239 err = mlx4_init_fw(dev);
3240 if (err) {
3241 mlx4_err(dev, "Failed to init fw, aborting.\n");
3242 goto err_mfunc;
3243 }
3244
7ae0e400 3245 if (mlx4_is_master(dev)) {
da315679 3246 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 3247 if (!dev_cap) {
3248 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3249
3250 if (!dev_cap) {
3251 err = -ENOMEM;
3252 goto err_fw;
3253 }
3254
3255 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3256 if (err) {
3257 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3258 goto err_fw;
3259 }
3260
de966c59
MB		 3261 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3262 goto err_fw;
3263
7ae0e400 3264 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3265 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3266 total_vfs,
3267 existing_vfs,
3268 reset_flow);
7ae0e400 3269
ed3d2276 3270 mlx4_close_fw(dev);
7ae0e400
MB		 3271 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3272 dev->flags = dev_flags;
3273 if (!SRIOV_VALID_STATE(dev->flags)) {
3274 mlx4_err(dev, "Invalid SRIOV state\n");
3275 goto err_sriov;
3276 }
3277 err = mlx4_reset(dev);
3278 if (err) {
3279 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3280 goto err_sriov;
3281 }
3282 goto slave_start;
3283 }
3284 } else {
3285 /* Legacy mode FW requires SRIOV to be enabled before
3286 * doing QUERY_DEV_CAP, since max_eq's value is different if
3287 * SRIOV is enabled.
3288 */
3289 memset(dev_cap, 0, sizeof(*dev_cap));
3290 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3291 if (err) {
3292 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3293 goto err_fw;
3294 }
de966c59
MB		 3295
3296 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3297 goto err_fw;
7ae0e400
MB		 3298 }
3299 }
3300
225c7b1f 3301 err = mlx4_init_hca(dev);
ab9c17a0
JM		 3302 if (err) {
3303 if (err == -EACCES) {
3304 /* Not primary Physical function
3305 * Running in slave mode */
ffc39f6d 3306 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 3307 /* We're not a PF */
3308 if (dev->flags & MLX4_FLAG_SRIOV) {
3309 if (!existing_vfs)
3310 pci_disable_sriov(pdev);
55ad3592 3311 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 3312 atomic_dec(&pf_loading);
3313 dev->flags &= ~MLX4_FLAG_SRIOV;
3314 }
3315 if (!mlx4_is_slave(dev))
3316 mlx4_free_ownership(dev);
ab9c17a0
JM		 3317 dev->flags |= MLX4_FLAG_SLAVE;
3318 dev->flags &= ~MLX4_FLAG_MASTER;
3319 goto slave_start;
3320 } else
a0eacca9 3321 goto err_fw;
ab9c17a0
JM		 3322 }
3323
7ae0e400 3324 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3325 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3326 existing_vfs, reset_flow);
7ae0e400
MB		 3327
3328 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3329 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3330 dev->flags = dev_flags;
3331 err = mlx4_cmd_init(dev);
3332 if (err) {
3333 /* Only VHCR is cleaned up, so could still
3334 * send FW commands
3335 */
3336 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3337 goto err_close;
3338 }
3339 } else {
3340 dev->flags = dev_flags;
3341 }
3342
3343 if (!SRIOV_VALID_STATE(dev->flags)) {
3344 mlx4_err(dev, "Invalid SRIOV state\n");
3345 goto err_close;
3346 }
3347 }
3348
b912b2f8
EP		 3349 /* check if the device is functioning at its maximum possible speed.
3350 * No return code for this call, just warn the user in case of PCI
3351 * express device capabilities are under-satisfied by the bus.
3352 */
83d3459a
EP		 3353 if (!mlx4_is_slave(dev))
3354 mlx4_check_pcie_caps(dev);
b912b2f8 3355
ab9c17a0
JM		 3356 /* In master functions, the communication channel must be initialized
3357 * after obtaining its address from fw */
3358 if (mlx4_is_master(dev)) {
e1c00e10
MD		 3359 if (dev->caps.num_ports < 2 &&
3360 num_vfs_argc > 1) {
3361 err = -EINVAL;
3362 mlx4_err(dev,
3363 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3364 dev->caps.num_ports);
ab9c17a0
JM		 3365 goto err_close;
3366 }
872bf2fb 3367 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 3368
872bf2fb
YH		 3369 for (i = 0;
3370 i < sizeof(dev->persist->nvfs)/
3371 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 3372 unsigned j;
3373
872bf2fb 3374 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 3375 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3376 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3377 dev->caps.num_ports;
1ab95d37
MB		 3378 }
3379 }
e1c00e10
MD		 3380
3381 /* In master functions, the communication channel
3382 * must be initialized after obtaining its address from fw
3383 */
3384 err = mlx4_multi_func_init(dev);
3385 if (err) {
3386 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3387 goto err_close;
3388 }
ab9c17a0 3389 }
225c7b1f 3390
b8dd786f
YP		 3391 err = mlx4_alloc_eq_table(dev);
3392 if (err)
ab9c17a0 3393 goto err_master_mfunc;
b8dd786f 3394
c66fa19c 3395 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
730c41d5 3396 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 3397
08fb1055 3398 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 3399 if ((mlx4_is_mfunc(dev)) &&
3400 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 3401 err = -ENOSYS;
1a91de28 3402 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 3403 goto err_free_eq;
ab9c17a0
JM		 3404 }
3405
3406 if (!mlx4_is_slave(dev)) {
3407 err = mlx4_init_steering(dev);
3408 if (err)
e1c00e10 3409 goto err_disable_msix;
ab9c17a0 3410 }
b12d93d6 3411
225c7b1f 3412 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 3413 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3414 !mlx4_is_mfunc(dev)) {
08fb1055 3415 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1 3416 dev->caps.num_comp_vectors = 1;
08fb1055
MT		 3417 pci_disable_msix(pdev);
3418 err = mlx4_setup_hca(dev);
3419 }
3420
225c7b1f 3421 if (err)
b12d93d6 3422 goto err_steer;
225c7b1f 3423
5a0d0a61 3424 mlx4_init_quotas(dev);
55ad3592
YH		 3425 /* When PF resources are ready arm its comm channel to enable
3426 * getting commands
3427 */
3428 if (mlx4_is_master(dev)) {
3429 err = mlx4_ARM_COMM_CHANNEL(dev);
3430 if (err) {
3431 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3432 err);
3433 goto err_steer;
3434 }
3435 }
5a0d0a61 3436
7ff93f8b
YP		 3437 for (port = 1; port <= dev->caps.num_ports; port++) {
3438 err = mlx4_init_port_info(dev, port);
3439 if (err)
3440 goto err_port;
3441 }
2a2336f8 3442
53f33ae2
MS		 3443 priv->v2p.port1 = 1;
3444 priv->v2p.port2 = 2;
3445
225c7b1f
RD		 3446 err = mlx4_register_device(dev);
3447 if (err)
7ff93f8b 3448 goto err_port;
225c7b1f 3449
b046ffe5
EP		 3450 mlx4_request_modules(dev);
3451
27bf91d6
YP		 3452 mlx4_sense_init(dev);
3453 mlx4_start_sense(dev);
3454
befdf897 3455 priv->removed = 0;
225c7b1f 3456
55ad3592 3457 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3458 atomic_dec(&pf_loading);
3459
da315679 3460 kfree(dev_cap);
225c7b1f
RD		 3461 return 0;
3462
7ff93f8b 3463err_port:
b4f77264 3464 for (--port; port >= 1; --port)
7ff93f8b
YP		 3465 mlx4_cleanup_port_info(&priv->port[port]);
3466
6de5f7f6 3467 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3468 if (!mlx4_is_slave(dev))
3469 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 3470 mlx4_cleanup_qp_table(dev);
3471 mlx4_cleanup_srq_table(dev);
3472 mlx4_cleanup_cq_table(dev);
3473 mlx4_cmd_use_polling(dev);
3474 mlx4_cleanup_eq_table(dev);
fe6f700d 3475 mlx4_cleanup_mcg_table(dev);
225c7b1f 3476 mlx4_cleanup_mr_table(dev);
012a8ff5 3477 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 3478 mlx4_cleanup_pd_table(dev);
3479 mlx4_cleanup_uar_table(dev);
3480
b12d93d6 3481err_steer:
ab9c17a0
JM		 3482 if (!mlx4_is_slave(dev))
3483 mlx4_clear_steering(dev);
b12d93d6 3484
e1c00e10
MD		 3485err_disable_msix:
3486 if (dev->flags & MLX4_FLAG_MSI_X)
3487 pci_disable_msix(pdev);
3488
b8dd786f
YP		 3489err_free_eq:
3490 mlx4_free_eq_table(dev);
3491
ab9c17a0 3492err_master_mfunc:
772103e6
JM		 3493 if (mlx4_is_master(dev)) {
3494 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 3495 mlx4_multi_func_cleanup(dev);
772103e6 3496 }
ab9c17a0 3497
b38f2879 3498 if (mlx4_is_slave(dev)) {
99ec41d0 3499 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 3500 kfree(dev->caps.qp0_tunnel);
3501 kfree(dev->caps.qp0_proxy);
3502 kfree(dev->caps.qp1_tunnel);
3503 kfree(dev->caps.qp1_proxy);
3504 }
3505
225c7b1f
RD		 3506err_close:
3507 mlx4_close_hca(dev);
3508
a0eacca9
MB		 3509err_fw:
3510 mlx4_close_fw(dev);
3511
ab9c17a0
JM		 3512err_mfunc:
3513 if (mlx4_is_slave(dev))
3514 mlx4_multi_func_cleanup(dev);
3515
225c7b1f 3516err_cmd:
ffc39f6d 3517 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3518
ab9c17a0 3519err_sriov:
55ad3592 3520 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3521 pci_disable_sriov(pdev);
55ad3592
YH		 3522 dev->flags &= ~MLX4_FLAG_SRIOV;
3523 }
ab9c17a0 3524
55ad3592 3525 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3526 atomic_dec(&pf_loading);
3527
1ab95d37
MB		 3528 kfree(priv->dev.dev_vfs);
3529
e1c00e10
MD		 3530 if (!mlx4_is_slave(dev))
3531 mlx4_free_ownership(dev);
3532
7ae0e400 3533 kfree(dev_cap);
e1c00e10
MD		 3534 return err;
3535}
3536
3537static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3538 struct mlx4_priv *priv)
3539{
3540 int err;
3541 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3542 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3543 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3544 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3545 unsigned total_vfs = 0;
3546 unsigned int i;
3547
3548 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3549
3550 err = pci_enable_device(pdev);
3551 if (err) {
3552 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3553 return err;
3554 }
3555
3556 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3557 * per port, we must limit the number of VFs to 63 (since their are
3558 * 128 MACs)
3559 */
3560 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3561 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3562 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3563 if (nvfs[i] < 0) {
3564 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3565 err = -EINVAL;
3566 goto err_disable_pdev;
3567 }
3568 }
3569 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3570 i++) {
3571 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3572 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3573 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3574 err = -EINVAL;
3575 goto err_disable_pdev;
3576 }
3577 }
0beb44b0 3578 if (total_vfs > MLX4_MAX_NUM_VF) {
e1c00e10 3579 dev_err(&pdev->dev,
0beb44b0
CS		 3580 "Requested more VF's (%d) than allowed by hw (%d)\n",
3581 total_vfs, MLX4_MAX_NUM_VF);
e1c00e10
MD		 3582 err = -EINVAL;
3583 goto err_disable_pdev;
3584 }
3585
3586 for (i = 0; i < MLX4_MAX_PORTS; i++) {
0beb44b0 3587 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
e1c00e10 3588 dev_err(&pdev->dev,
0beb44b0 3589 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
e1c00e10 3590 nvfs[i] + nvfs[2], i + 1,
0beb44b0 3591 MLX4_MAX_NUM_VF_P_PORT);
e1c00e10
MD		 3592 err = -EINVAL;
3593 goto err_disable_pdev;
3594 }
3595 }
3596
3597 /* Check for BARs. */
3598 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3599 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3600 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3601 pci_dev_data, pci_resource_flags(pdev, 0));
3602 err = -ENODEV;
3603 goto err_disable_pdev;
3604 }
3605 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3606 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3607 err = -ENODEV;
3608 goto err_disable_pdev;
3609 }
3610
3611 err = pci_request_regions(pdev, DRV_NAME);
3612 if (err) {
3613 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3614 goto err_disable_pdev;
3615 }
3616
3617 pci_set_master(pdev);
3618
3619 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3620 if (err) {
3621 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3622 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3623 if (err) {
3624 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3625 goto err_release_regions;
3626 }
3627 }
3628 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3629 if (err) {
3630 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3631 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3632 if (err) {
3633 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3634 goto err_release_regions;
3635 }
3636 }
3637
3638 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3639 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3640 /* Detect if this device is a virtual function */
3641 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3642 /* When acting as pf, we normally skip vfs unless explicitly
3643 * requested to probe them.
3644 */
3645 if (total_vfs) {
3646 unsigned vfs_offset = 0;
3647
3648 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3649 vfs_offset + nvfs[i] < extended_func_num(pdev);
3650 vfs_offset += nvfs[i], i++)
3651 ;
3652 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3653 err = -ENODEV;
3654 goto err_release_regions;
3655 }
3656 if ((extended_func_num(pdev) - vfs_offset)
3657 > prb_vf[i]) {
3658 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3659 extended_func_num(pdev));
3660 err = -ENODEV;
3661 goto err_release_regions;
3662 }
3663 }
3664 }
3665
ad9a0bf0 3666 err = mlx4_catas_init(&priv->dev);
e1c00e10
MD		 3667 if (err)
3668 goto err_release_regions;
ad9a0bf0 3669
55ad3592 3670 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3671 if (err)
3672 goto err_catas;
3673
e1c00e10 3674 return 0;
225c7b1f 3675
ad9a0bf0
YH		 3676err_catas:
3677 mlx4_catas_end(&priv->dev);
3678
a01df0fe
RD		 3679err_release_regions:
3680 pci_release_regions(pdev);
225c7b1f
RD		 3681
3682err_disable_pdev:
3683 pci_disable_device(pdev);
3684 pci_set_drvdata(pdev, NULL);
3685 return err;
3686}
3687
1dd06ae8 3688static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3689{
09d4d087 3690 struct devlink *devlink;
befdf897
WY		 3691 struct mlx4_priv *priv;
3692 struct mlx4_dev *dev;
e1c00e10 3693 int ret;
befdf897 3694
0a645e80 3695 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3696
09d4d087
JP		 3697 devlink = devlink_alloc(NULL, sizeof(*priv));
3698 if (!devlink)
befdf897 3699 return -ENOMEM;
09d4d087 3700 priv = devlink_priv(devlink);
befdf897
WY		 3701
3702 dev = &priv->dev;
872bf2fb
YH		 3703 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3704 if (!dev->persist) {
09d4d087
JP		 3705 ret = -ENOMEM;
3706 goto err_devlink_free;
872bf2fb
YH		 3707 }
3708 dev->persist->pdev = pdev;
3709 dev->persist->dev = dev;
3710 pci_set_drvdata(pdev, dev->persist);
befdf897 3711 priv->pci_dev_data = id->driver_data;
f6bc11e4 3712 mutex_init(&dev->persist->device_state_mutex);
c69453e2 3713 mutex_init(&dev->persist->interface_state_mutex);
befdf897 3714
09d4d087
JP		 3715 ret = devlink_register(devlink, &pdev->dev);
3716 if (ret)
3717 goto err_persist_free;
3718
e1c00e10 3719 ret = __mlx4_init_one(pdev, id->driver_data, priv);
09d4d087
JP		 3720 if (ret)
3721 goto err_devlink_unregister;
2ba5fbd6 3722
09d4d087
JP		 3723 pci_save_state(pdev);
3724 return 0;
3725
3726err_devlink_unregister:
3727 devlink_unregister(devlink);
3728err_persist_free:
3729 kfree(dev->persist);
3730err_devlink_free:
3731 devlink_free(devlink);
e1c00e10 3732 return ret;
3d73c288
RD		 3733}
3734
dd0eefe3
YH		 3735static void mlx4_clean_dev(struct mlx4_dev *dev)
3736{
3737 struct mlx4_dev_persistent *persist = dev->persist;
3738 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3739 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 3740
3741 memset(priv, 0, sizeof(*priv));
3742 priv->dev.persist = persist;
55ad3592 3743 priv->dev.flags = flags;
dd0eefe3
YH		 3744}
3745
e1c00e10 3746static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 3747{
872bf2fb
YH		 3748 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3749 struct mlx4_dev *dev = persist->dev;
225c7b1f 3750 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3751 int pci_dev_data;
dd0eefe3 3752 int p, i;
225c7b1f 3753
befdf897
WY		 3754 if (priv->removed)
3755 return;
225c7b1f 3756
dd0eefe3
YH		 3757 /* saving current ports type for further use */
3758 for (i = 0; i < dev->caps.num_ports; i++) {
3759 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3760 dev->persist->curr_port_poss_type[i] = dev->caps.
3761 possible_type[i + 1];
3762 }
3763
befdf897 3764 pci_dev_data = priv->pci_dev_data;
225c7b1f 3765
befdf897
WY		 3766 mlx4_stop_sense(dev);
3767 mlx4_unregister_device(dev);
225c7b1f 3768
befdf897
WY		 3769 for (p = 1; p <= dev->caps.num_ports; p++) {
3770 mlx4_cleanup_port_info(&priv->port[p]);
3771 mlx4_CLOSE_PORT(dev, p);
3772 }
3773
3774 if (mlx4_is_master(dev))
3775 mlx4_free_resource_tracker(dev,
3776 RES_TR_FREE_SLAVES_ONLY);
3777
6de5f7f6 3778 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3779 if (!mlx4_is_slave(dev))
3780 mlx4_cleanup_counters_table(dev);
befdf897
WY		 3781 mlx4_cleanup_qp_table(dev);
3782 mlx4_cleanup_srq_table(dev);
3783 mlx4_cleanup_cq_table(dev);
3784 mlx4_cmd_use_polling(dev);
3785 mlx4_cleanup_eq_table(dev);
3786 mlx4_cleanup_mcg_table(dev);
3787 mlx4_cleanup_mr_table(dev);
3788 mlx4_cleanup_xrcd_table(dev);
3789 mlx4_cleanup_pd_table(dev);
225c7b1f 3790
befdf897
WY		 3791 if (mlx4_is_master(dev))
3792 mlx4_free_resource_tracker(dev,
3793 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3794
befdf897
WY		 3795 iounmap(priv->kar);
3796 mlx4_uar_free(dev, &priv->driver_uar);
3797 mlx4_cleanup_uar_table(dev);
3798 if (!mlx4_is_slave(dev))
3799 mlx4_clear_steering(dev);
3800 mlx4_free_eq_table(dev);
3801 if (mlx4_is_master(dev))
3802 mlx4_multi_func_cleanup(dev);
3803 mlx4_close_hca(dev);
a0eacca9 3804 mlx4_close_fw(dev);
befdf897
WY		 3805 if (mlx4_is_slave(dev))
3806 mlx4_multi_func_cleanup(dev);
ffc39f6d 3807 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3808
befdf897
WY		 3809 if (dev->flags & MLX4_FLAG_MSI_X)
3810 pci_disable_msix(pdev);
befdf897
WY		 3811
3812 if (!mlx4_is_slave(dev))
3813 mlx4_free_ownership(dev);
3814
99ec41d0 3815 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3816 kfree(dev->caps.qp0_tunnel);
3817 kfree(dev->caps.qp0_proxy);
3818 kfree(dev->caps.qp1_tunnel);
3819 kfree(dev->caps.qp1_proxy);
3820 kfree(dev->dev_vfs);
3821
dd0eefe3 3822 mlx4_clean_dev(dev);
befdf897
WY		 3823 priv->pci_dev_data = pci_dev_data;
3824 priv->removed = 1;
3825}
3826
3827static void mlx4_remove_one(struct pci_dev *pdev)
3828{
872bf2fb
YH		 3829 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3830 struct mlx4_dev *dev = persist->dev;
befdf897 3831 struct mlx4_priv *priv = mlx4_priv(dev);
09d4d087 3832 struct devlink *devlink = priv_to_devlink(priv);
55ad3592 3833 int active_vfs = 0;
befdf897 3834
c69453e2
YH		 3835 mutex_lock(&persist->interface_state_mutex);
3836 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3837 mutex_unlock(&persist->interface_state_mutex);
3838
55ad3592
YH		 3839 /* Disabling SR-IOV is not allowed while there are active vf's */
3840 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3841 active_vfs = mlx4_how_many_lives_vf(dev);
3842 if (active_vfs) {
3843 pr_warn("Removing PF when there are active VF's !!\n");
3844 pr_warn("Will not disable SR-IOV.\n");
3845 }
3846 }
3847
c69453e2
YH		 3848 /* device marked to be under deletion running now without the lock
3849 * letting other tasks to be terminated
3850 */
3851 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3852 mlx4_unload_one(pdev);
3853 else
3854 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 3855 mlx4_catas_end(dev);
55ad3592
YH		 3856 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3857 mlx4_warn(dev, "Disabling SR-IOV\n");
3858 pci_disable_sriov(pdev);
3859 }
3860
e1c00e10
MD		 3861 pci_release_regions(pdev);
3862 pci_disable_device(pdev);
09d4d087 3863 devlink_unregister(devlink);
872bf2fb 3864 kfree(dev->persist);
09d4d087 3865 devlink_free(devlink);
befdf897 3866 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3867}
3868
dd0eefe3
YH		 3869static int restore_current_port_types(struct mlx4_dev *dev,
3870 enum mlx4_port_type *types,
3871 enum mlx4_port_type *poss_types)
3872{
3873 struct mlx4_priv *priv = mlx4_priv(dev);
3874 int err, i;
3875
3876 mlx4_stop_sense(dev);
3877
3878 mutex_lock(&priv->port_mutex);
3879 for (i = 0; i < dev->caps.num_ports; i++)
3880 dev->caps.possible_type[i + 1] = poss_types[i];
3881 err = mlx4_change_port_types(dev, types);
3882 mlx4_start_sense(dev);
3883 mutex_unlock(&priv->port_mutex);
3884
3885 return err;
3886}
3887
ee49bd93
JM		 3888int mlx4_restart_one(struct pci_dev *pdev)
3889{
872bf2fb
YH		 3890 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3891 struct mlx4_dev *dev = persist->dev;
839f1243 3892 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3893 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3894 int pci_dev_data, err, total_vfs;
839f1243
RD		 3895
3896 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 3897 total_vfs = dev->persist->num_vfs;
3898 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10
MD		 3899
3900 mlx4_unload_one(pdev);
55ad3592 3901 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 3902 if (err) {
3903 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3904 __func__, pci_name(pdev), err);
3905 return err;
3906 }
3907
dd0eefe3
YH		 3908 err = restore_current_port_types(dev, dev->persist->curr_port_type,
3909 dev->persist->curr_port_poss_type);
3910 if (err)
3911 mlx4_err(dev, "could not restore original port types (%d)\n",
3912 err);
3913
e1c00e10 3914 return err;
ee49bd93
JM		 3915}
3916
9baa3c34 3917static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3918 /* MT25408 "Hermon" SDR */
ca3e57a5 3919 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3920 /* MT25408 "Hermon" DDR */
ca3e57a5 3921 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3922 /* MT25408 "Hermon" QDR */
ca3e57a5 3923 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3924 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3925 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3926 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3927 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3928 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3929 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3930 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3931 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3932 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3933 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3934 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3935 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3936 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3937 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3938 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3939 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3940 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3941 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3942 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3943 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3944 /* MT27500 Family [ConnectX-3] */
3945 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3946 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3947 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3948 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3949 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3950 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3951 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3952 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3953 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3954 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3955 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3956 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3957 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3958 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3959 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3960 { 0, }
3961};
3962
3963MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3964
57dbf29a
KSS		 3965static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3966 pci_channel_state_t state)
3967{
2ba5fbd6
YH		 3968 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3969
3970 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
3971 mlx4_enter_error_state(persist);
57dbf29a 3972
2ba5fbd6
YH		 3973 mutex_lock(&persist->interface_state_mutex);
3974 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3975 mlx4_unload_one(pdev);
3976
3977 mutex_unlock(&persist->interface_state_mutex);
3978 if (state == pci_channel_io_perm_failure)
3979 return PCI_ERS_RESULT_DISCONNECT;
3980
3981 pci_disable_device(pdev);
3982 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 3983}
3984
3985static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3986{
2ba5fbd6
YH		 3987 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3988 struct mlx4_dev *dev = persist->dev;
befdf897
WY		 3989 struct mlx4_priv *priv = mlx4_priv(dev);
3990 int ret;
2ba5fbd6
YH		 3991 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3992 int total_vfs;
97a5221f 3993
2ba5fbd6
YH		 3994 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
3995 ret = pci_enable_device(pdev);
3996 if (ret) {
3997 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret);
3998 return PCI_ERS_RESULT_DISCONNECT;
3999 }
4000
4001 pci_set_master(pdev);
4002 pci_restore_state(pdev);
4003 pci_save_state(pdev);
4004
4005 total_vfs = dev->persist->num_vfs;
4006 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4007
4008 mutex_lock(&persist->interface_state_mutex);
4009 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4010 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 4011 priv, 1);
2ba5fbd6
YH		 4012 if (ret) {
4013 mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n",
4014 __func__, ret);
4015 goto end;
4016 }
4017
4018 ret = restore_current_port_types(dev, dev->persist->
4019 curr_port_type, dev->persist->
4020 curr_port_poss_type);
4021 if (ret)
4022 mlx4_err(dev, "could not restore original port types (%d)\n", ret);
4023 }
4024end:
4025 mutex_unlock(&persist->interface_state_mutex);
57dbf29a
KSS		 4026
4027 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
4028}
4029
2ba5fbd6
YH		 4030static void mlx4_shutdown(struct pci_dev *pdev)
4031{
4032 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4033
4034 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4035 mutex_lock(&persist->interface_state_mutex);
4036 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4037 mlx4_unload_one(pdev);
4038 mutex_unlock(&persist->interface_state_mutex);
4039}
4040
3646f0e5 4041static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 4042 .error_detected = mlx4_pci_err_detected,
4043 .slot_reset = mlx4_pci_slot_reset,
4044};
4045
225c7b1f
RD		 4046static struct pci_driver mlx4_driver = {
4047 .name = DRV_NAME,
4048 .id_table = mlx4_pci_table,
4049 .probe = mlx4_init_one,
2ba5fbd6 4050 .shutdown = mlx4_shutdown,
f57e6848 4051 .remove = mlx4_remove_one,
57dbf29a 4052 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 4053};
4054
7ff93f8b
YP		 4055static int __init mlx4_verify_params(void)
4056{
4057 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 4058 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 4059 return -1;
4060 }
4061
cb29688a 4062 if (log_num_vlan != 0)
c20862c8
AV		 4063 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4064 MLX4_LOG_NUM_VLANS);
7ff93f8b 4065
ecc8fb11
AV		 4066 if (use_prio != 0)
4067 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 4068
0498628f 4069 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 4070 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4071 log_mtts_per_seg);
ab6bf42e
EC		 4072 return -1;
4073 }
4074
ab9c17a0
JM		 4075 /* Check if module param for ports type has legal combination */
4076 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 4077 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 4078 port_type_array[0] = true;
4079 }
4080
7d077cd3
MB		 4081 if (mlx4_log_num_mgm_entry_size < -7 ||
4082 (mlx4_log_num_mgm_entry_size > 0 &&
4083 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4084 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4085 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 4086 mlx4_log_num_mgm_entry_size,
4087 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4088 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 4089 return -1;
4090 }
4091
7ff93f8b
YP		 4092 return 0;
4093}
4094
225c7b1f
RD		 4095static int __init mlx4_init(void)
4096{
4097 int ret;
4098
7ff93f8b
YP		 4099 if (mlx4_verify_params())
4100 return -EINVAL;
4101
27bf91d6
YP		 4102
4103 mlx4_wq = create_singlethread_workqueue("mlx4");
4104 if (!mlx4_wq)
4105 return -ENOMEM;
ee49bd93 4106
225c7b1f 4107 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 4108 if (ret < 0)
4109 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4110 return ret < 0 ? ret : 0;
4111}
4112
4113static void __exit mlx4_cleanup(void)
4114{
4115 pci_unregister_driver(&mlx4_driver);
27bf91d6 4116 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4117}
4118
4119module_init(mlx4_init);
4120module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)