[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2006, 2007 Cisco Systems.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_FW_H
#define MLX4_FW_H

#include "mlx4.h"
#include "icm.h"

struct mlx4_mod_stat_cfg {
	u8 log_pg_sz;
	u8 log_pg_sz_m;
};

struct mlx4_port_cap {
	u8  link_state;
	u8  supported_port_types;
	u8  suggested_type;
	u8  default_sense;
	u8  log_max_macs;
	u8  log_max_vlans;
	int ib_mtu;
	int max_port_width;
	int max_vl;
	int max_gids;
	int max_pkeys;
	u64 def_mac;
	u16 eth_mtu;
	int trans_type;
	int vendor_oui;
	u16 wavelength;
	u64 trans_code;
	u8 dmfs_optimized_state;
};

struct mlx4_dev_cap {
	int max_srq_sz;
	int max_qp_sz;
	int reserved_qps;
	int max_qps;
	int reserved_srqs;
	int max_srqs;
	int max_cq_sz;
	int reserved_cqs;
	int max_cqs;
	int max_mpts;
	int reserved_eqs;
	int max_eqs;
	int num_sys_eqs;
	int reserved_mtts;
	int max_mrw_sz;
	int reserved_mrws;
	int max_mtt_seg;
	int max_requester_per_qp;
	int max_responder_per_qp;
	int max_rdma_global;
	int local_ca_ack_delay;
	int num_ports;
	u32 max_msg_sz;
	u16 stat_rate_support;
	int fs_log_max_ucast_qp_range_size;
	int fs_max_num_qp_per_entry;
	u64 flags;
	u64 flags2;
	int reserved_uars;
	int uar_size;
	int min_page_sz;
	int bf_reg_size;
	int bf_regs_per_page;
	int max_sq_sg;
	int max_sq_desc_sz;
	int max_rq_sg;
	int max_rq_desc_sz;
	int max_qp_per_mcg;
	int reserved_mgms;
	int max_mcgs;
	int reserved_pds;
	int max_pds;
	int reserved_xrcds;
	int max_xrcds;
	int qpc_entry_sz;
	int rdmarc_entry_sz;
	int altc_entry_sz;
	int aux_entry_sz;
	int srq_entry_sz;
	int cqc_entry_sz;
	int eqc_entry_sz;
	int dmpt_entry_sz;
	int cmpt_entry_sz;
	int mtt_entry_sz;
	int resize_srq;
	u32 bmme_flags;
	u32 reserved_lkey;
	u64 max_icm_sz;
	int max_gso_sz;
	int max_rss_tbl_sz;
	u32 max_counters;
	u32 dmfs_high_rate_qpn_base;
	u32 dmfs_high_rate_qpn_range;
	struct mlx4_rate_limit_caps rl_caps;
	struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1];
};

struct mlx4_func_cap {
	u8	num_ports;
	u8	flags;
	u32	pf_context_behaviour;
	int	qp_quota;
	int	cq_quota;
	int	srq_quota;
	int	mpt_quota;
	int	mtt_quota;
	int	max_eq;
	int	reserved_eq;
	int	mcg_quota;
	u32	qp0_qkey;
	u32	qp0_tunnel_qpn;
	u32	qp0_proxy_qpn;
	u32	qp1_tunnel_qpn;
	u32	qp1_proxy_qpn;
	u32	reserved_lkey;
	u8	physical_port;
	u8	port_flags;
	u8	flags1;
	u64	phys_port_id;
	u32	extra_flags;
};

struct mlx4_func {
	int	bus;
	int	device;
	int	function;
	int	physical_function;
	int	rsvd_eqs;
	int	max_eq;
	int	rsvd_uars;
};

struct mlx4_adapter {
	char board_id[MLX4_BOARD_ID_LEN];
	u8   inta_pin;
};

struct mlx4_init_hca_param {
	u64 qpc_base;
	u64 rdmarc_base;
	u64 auxc_base;
	u64 altc_base;
	u64 srqc_base;
	u64 cqc_base;
	u64 eqc_base;
	u64 mc_base;
	u64 dmpt_base;
	u64 cmpt_base;
	u64 mtt_base;
	u64 global_caps;
	u16 log_mc_entry_sz;
	u16 log_mc_hash_sz;
	u16 hca_core_clock; /* Internal Clock Frequency (in MHz) */
	u8  log_num_qps;
	u8  log_num_srqs;
	u8  log_num_cqs;
	u8  log_num_eqs;
	u16 num_sys_eqs;
	u8  log_rd_per_qp;
	u8  log_mc_table_sz;
	u8  log_mpt_sz;
	u8  log_uar_sz;
	u8  mw_enabled;  /* Enable memory windows */
	u8  uar_page_sz; /* log pg sz in 4k chunks */
	u8  steering_mode; /* for QUERY_HCA */
	u8  dmfs_high_steer_mode; /* for QUERY_HCA */
	u64 dev_cap_enabled;
	u16 cqe_size; /* For use only when CQE stride feature enabled */
	u16 eqe_size; /* For use only when EQE stride feature enabled */
	u8 rss_ip_frags;
	u8 phv_check_en; /* for QUERY_HCA */
};

struct mlx4_init_ib_param {
	int port_width;
	int vl_cap;
	int mtu_cap;
	u16 gid_cap;
	u16 pkey_cap;
	int set_guid0;
	u64 guid0;
	int set_node_guid;
	u64 node_guid;
	int set_si_guid;
	u64 si_guid;
};

struct mlx4_set_ib_param {
	int set_si_guid;
	int reset_qkey_viol;
	u64 si_guid;
	u32 cap_mask;
};

void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap);
int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
			struct mlx4_func_cap *func_cap);
int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
				struct mlx4_vhcr *vhcr,
				struct mlx4_cmd_mailbox *inbox,
				struct mlx4_cmd_mailbox *outbox,
				struct mlx4_cmd_info *cmd);
int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave);
int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
int mlx4_UNMAP_FA(struct mlx4_dev *dev);
int mlx4_RUN_FW(struct mlx4_dev *dev);
int mlx4_QUERY_FW(struct mlx4_dev *dev);
int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
int mlx4_NOP(struct mlx4_dev *dev);
int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
void mlx4_opreq_action(struct work_struct *work);

#endif /* MLX4_FW_H */
Commit	Line	Data
225c7b1f RD	1	/*
225c7b1f RD	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0	3	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	4	* Copyright (c) 2006, 2007 Cisco Systems. All rights reserved.
	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
	33	*/
	34
	35	#ifndef MLX4_FW_H
	36	#define MLX4_FW_H
	37
	38	#include "mlx4.h"
	39	#include "icm.h"
	40
2d928651 VS	41	struct mlx4_mod_stat_cfg {
	42	u8 log_pg_sz;
	43	u8 log_pg_sz_m;
	44	};
	45
431df8c7	46	struct mlx4_port_cap {
e34305c8	47	u8 link_state;
431df8c7 MB	48	u8 supported_port_types;
	49	u8 suggested_type;
	50	u8 default_sense;
	51	u8 log_max_macs;
	52	u8 log_max_vlans;
	53	int ib_mtu;
	54	int max_port_width;
	55	int max_vl;
	56	int max_gids;
	57	int max_pkeys;
	58	u64 def_mac;
	59	u16 eth_mtu;
	60	int trans_type;
	61	int vendor_oui;
	62	u16 wavelength;
	63	u64 trans_code;
7d077cd3	64	u8 dmfs_optimized_state;
431df8c7 MB	65	};
431df8c7 MB	66
225c7b1f RD	67	struct mlx4_dev_cap {
	68	int max_srq_sz;
	69	int max_qp_sz;
	70	int reserved_qps;
	71	int max_qps;
	72	int reserved_srqs;
	73	int max_srqs;
	74	int max_cq_sz;
	75	int reserved_cqs;
	76	int max_cqs;
	77	int max_mpts;
	78	int reserved_eqs;
	79	int max_eqs;
7ae0e400	80	int num_sys_eqs;
225c7b1f RD	81	int reserved_mtts;
	82	int max_mrw_sz;
	83	int reserved_mrws;
	84	int max_mtt_seg;
	85	int max_requester_per_qp;
	86	int max_responder_per_qp;
	87	int max_rdma_global;
	88	int local_ca_ack_delay;
225c7b1f	89	int num_ports;
149983af	90	u32 max_msg_sz;
225c7b1f	91	u16 stat_rate_support;
0ff1fb65 HHZ	92	int fs_log_max_ucast_qp_range_size;
0ff1fb65 HHZ	93	int fs_max_num_qp_per_entry;
52eafc68	94	u64 flags;
b3416f44	95	u64 flags2;
225c7b1f RD	96	int reserved_uars;
	97	int uar_size;
	98	int min_page_sz;
	99	int bf_reg_size;
	100	int bf_regs_per_page;
	101	int max_sq_sg;
	102	int max_sq_desc_sz;
	103	int max_rq_sg;
	104	int max_rq_desc_sz;
	105	int max_qp_per_mcg;
	106	int reserved_mgms;
	107	int max_mcgs;
	108	int reserved_pds;
	109	int max_pds;
012a8ff5 SH	110	int reserved_xrcds;
012a8ff5 SH	111	int max_xrcds;
225c7b1f RD	112	int qpc_entry_sz;
	113	int rdmarc_entry_sz;
	114	int altc_entry_sz;
	115	int aux_entry_sz;
	116	int srq_entry_sz;
	117	int cqc_entry_sz;
	118	int eqc_entry_sz;
	119	int dmpt_entry_sz;
	120	int cmpt_entry_sz;
	121	int mtt_entry_sz;
	122	int resize_srq;
95d04f07	123	u32 bmme_flags;
225c7b1f RD	124	u32 reserved_lkey;
225c7b1f RD	125	u64 max_icm_sz;
b832be1e	126	int max_gso_sz;
b3416f44	127	int max_rss_tbl_sz;
f2a3f6a3	128	u32 max_counters;
7d077cd3 MB	129	u32 dmfs_high_rate_qpn_base;
7d077cd3 MB	130	u32 dmfs_high_rate_qpn_range;
fc31e256	131	struct mlx4_rate_limit_caps rl_caps;
431df8c7	132	struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1];
225c7b1f RD	133	};
225c7b1f RD	134
5cc914f1	135	struct mlx4_func_cap {
5cc914f1 MA	136	u8 num_ports;
	137	u8 flags;
	138	u32 pf_context_behaviour;
	139	int qp_quota;
	140	int cq_quota;
	141	int srq_quota;
	142	int mpt_quota;
	143	int mtt_quota;
	144	int max_eq;
	145	int reserved_eq;
	146	int mcg_quota;
99ec41d0	147	u32 qp0_qkey;
47605df9 JM	148	u32 qp0_tunnel_qpn;
	149	u32 qp0_proxy_qpn;
	150	u32 qp1_tunnel_qpn;
	151	u32 qp1_proxy_qpn;
f0ce0615	152	u32 reserved_lkey;
47605df9 JM	153	u8 physical_port;
47605df9 JM	154	u8 port_flags;
eb17711b	155	u8 flags1;
8e1a28e8	156	u64 phys_port_id;
ddae0349	157	u32 extra_flags;
5cc914f1 MA	158	};
5cc914f1 MA	159
e8c4265b MB	160	struct mlx4_func {
	161	int bus;
	162	int device;
	163	int function;
	164	int physical_function;
	165	int rsvd_eqs;
	166	int max_eq;
	167	int rsvd_uars;
	168	};
	169
225c7b1f	170	struct mlx4_adapter {
225c7b1f RD	171	char board_id[MLX4_BOARD_ID_LEN];
	172	u8 inta_pin;
	173	};
	174
	175	struct mlx4_init_hca_param {
	176	u64 qpc_base;
	177	u64 rdmarc_base;
	178	u64 auxc_base;
	179	u64 altc_base;
	180	u64 srqc_base;
	181	u64 cqc_base;
	182	u64 eqc_base;
	183	u64 mc_base;
	184	u64 dmpt_base;
	185	u64 cmpt_base;
	186	u64 mtt_base;
5cc914f1	187	u64 global_caps;
225c7b1f RD	188	u16 log_mc_entry_sz;
225c7b1f RD	189	u16 log_mc_hash_sz;
ddd8a6c1	190	u16 hca_core_clock; /* Internal Clock Frequency (in MHz) */
225c7b1f RD	191	u8 log_num_qps;
	192	u8 log_num_srqs;
	193	u8 log_num_cqs;
	194	u8 log_num_eqs;
7ae0e400	195	u16 num_sys_eqs;
225c7b1f RD	196	u8 log_rd_per_qp;
	197	u8 log_mc_table_sz;
	198	u8 log_mpt_sz;
	199	u8 log_uar_sz;
e448834e	200	u8 mw_enabled; /* Enable memory windows */
ab9c17a0	201	u8 uar_page_sz; /* log pg sz in 4k chunks */
7b8157be	202	u8 steering_mode; /* for QUERY_HCA */
7d077cd3	203	u8 dmfs_high_steer_mode; /* for QUERY_HCA */
08ff3235	204	u64 dev_cap_enabled;
77507aa2 IS	205	u16 cqe_size; /* For use only when CQE stride feature enabled */
77507aa2 IS	206	u16 eqe_size; /* For use only when EQE stride feature enabled */
802f42a8	207	u8 rss_ip_frags;
77fc29c4	208	u8 phv_check_en; /* for QUERY_HCA */
225c7b1f RD	209	};
	210
	211	struct mlx4_init_ib_param {
	212	int port_width;
	213	int vl_cap;
	214	int mtu_cap;
	215	u16 gid_cap;
	216	u16 pkey_cap;
	217	int set_guid0;
	218	u64 guid0;
	219	int set_node_guid;
	220	u64 node_guid;
	221	int set_si_guid;
	222	u64 si_guid;
	223	};
	224
	225	struct mlx4_set_ib_param {
	226	int set_si_guid;
	227	int reset_qkey_viol;
	228	u64 si_guid;
	229	u32 cap_mask;
	230	};
	231
c78e25ed	232	void mlx4_dev_cap_dump(struct mlx4_dev dev, struct mlx4_dev_cap dev_cap);
225c7b1f	233	int mlx4_QUERY_DEV_CAP(struct mlx4_dev dev, struct mlx4_dev_cap dev_cap);
431df8c7	234	int mlx4_QUERY_PORT(struct mlx4_dev dev, int port, struct mlx4_port_cap port_cap);
225c6c8c	235	int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9	236	struct mlx4_func_cap *func_cap);
5cc914f1 MA	237	int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
	238	struct mlx4_vhcr *vhcr,
	239	struct mlx4_cmd_mailbox *inbox,
	240	struct mlx4_cmd_mailbox *outbox,
	241	struct mlx4_cmd_info *cmd);
e8c4265b	242	int mlx4_QUERY_FUNC(struct mlx4_dev dev, struct mlx4_func func, int slave);
225c7b1f RD	243	int mlx4_MAP_FA(struct mlx4_dev dev, struct mlx4_icm icm);
	244	int mlx4_UNMAP_FA(struct mlx4_dev *dev);
	245	int mlx4_RUN_FW(struct mlx4_dev *dev);
	246	int mlx4_QUERY_FW(struct mlx4_dev *dev);
	247	int mlx4_QUERY_ADAPTER(struct mlx4_dev dev, struct mlx4_adapter adapter);
	248	int mlx4_INIT_HCA(struct mlx4_dev dev, struct mlx4_init_hca_param param);
ab9c17a0	249	int mlx4_QUERY_HCA(struct mlx4_dev dev, struct mlx4_init_hca_param param);
225c7b1f RD	250	int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
	251	int mlx4_map_cmd(struct mlx4_dev dev, u16 op, struct mlx4_icm icm, u64 virt);
	252	int mlx4_SET_ICM_SIZE(struct mlx4_dev dev, u64 icm_size, u64 aux_pages);
	253	int mlx4_MAP_ICM_AUX(struct mlx4_dev dev, struct mlx4_icm icm);
	254	int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
	255	int mlx4_NOP(struct mlx4_dev *dev);
2d928651	256	int mlx4_MOD_STAT_CFG(struct mlx4_dev dev, struct mlx4_mod_stat_cfg cfg);
fe6f700d	257	void mlx4_opreq_action(struct work_struct *work);
225c7b1f RD	258
225c7b1f RD	259	#endif /* MLX4_FW_H */