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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
29d40c90 | 40 | #include <linux/prefetch.h> |
c27a02cd | 41 | #include <linux/vmalloc.h> |
fa37a958 | 42 | #include <linux/tcp.h> |
837052d0 | 43 | #include <linux/ip.h> |
6eb07caf | 44 | #include <linux/moduleparam.h> |
c27a02cd YP |
45 | |
46 | #include "mlx4_en.h" | |
47 | ||
c27a02cd | 48 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 49 | struct mlx4_en_tx_ring **pring, int qpn, u32 size, |
d03a68f8 | 50 | u16 stride, int node, int queue_index) |
c27a02cd YP |
51 | { |
52 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 53 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
54 | int tmp; |
55 | int err; | |
56 | ||
163561a4 | 57 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 58 | if (!ring) { |
163561a4 EE |
59 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
60 | if (!ring) { | |
61 | en_err(priv, "Failed allocating TX ring\n"); | |
62 | return -ENOMEM; | |
63 | } | |
41d942d5 EE |
64 | } |
65 | ||
c27a02cd YP |
66 | ring->size = size; |
67 | ring->size_mask = size - 1; | |
68 | ring->stride = stride; | |
b97b33a3 | 69 | ring->inline_thold = priv->prof->inline_thold; |
c27a02cd | 70 | |
c27a02cd | 71 | tmp = size * sizeof(struct mlx4_en_tx_info); |
dc9b06d1 | 72 | ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); |
41d942d5 | 73 | if (!ring->tx_info) { |
163561a4 EE |
74 | ring->tx_info = vmalloc(tmp); |
75 | if (!ring->tx_info) { | |
76 | err = -ENOMEM; | |
77 | goto err_ring; | |
78 | } | |
41d942d5 | 79 | } |
e404decb | 80 | |
453a6082 | 81 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
82 | ring->tx_info, tmp); |
83 | ||
163561a4 | 84 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 85 | if (!ring->bounce_buf) { |
163561a4 EE |
86 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
87 | if (!ring->bounce_buf) { | |
88 | err = -ENOMEM; | |
89 | goto err_info; | |
90 | } | |
c27a02cd YP |
91 | } |
92 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
93 | ||
163561a4 EE |
94 | /* Allocate HW buffers on provided NUMA node */ |
95 | set_dev_node(&mdev->dev->pdev->dev, node); | |
c27a02cd YP |
96 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, |
97 | 2 * PAGE_SIZE); | |
163561a4 | 98 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 99 | if (err) { |
453a6082 | 100 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
101 | goto err_bounce; |
102 | } | |
103 | ||
104 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
105 | if (err) { | |
453a6082 | 106 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
107 | goto err_hwq_res; |
108 | } | |
109 | ||
110 | ring->buf = ring->wqres.buf.direct.buf; | |
111 | ||
1a91de28 JP |
112 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
113 | ring, ring->buf, ring->size, ring->buf_size, | |
114 | (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd | 115 | |
87a5c389 | 116 | ring->qpn = qpn; |
40f2287b | 117 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); |
c27a02cd | 118 | if (err) { |
453a6082 | 119 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
87a5c389 | 120 | goto err_map; |
c27a02cd | 121 | } |
966508f7 | 122 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd | 123 | |
163561a4 | 124 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 | 125 | if (err) { |
1a91de28 | 126 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
87a5c389 YP |
127 | ring->bf.uar = &mdev->priv_uar; |
128 | ring->bf.uar->map = mdev->uar_map; | |
129 | ring->bf_enabled = false; | |
0fef9d03 AV |
130 | ring->bf_alloced = false; |
131 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
132 | } else { | |
133 | ring->bf_alloced = true; | |
134 | ring->bf_enabled = !!(priv->pflags & | |
135 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
136 | } | |
87a5c389 | 137 | |
ec693d47 | 138 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
139 | ring->queue_index = queue_index; |
140 | ||
141 | if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index)) | |
142 | cpumask_set_cpu(queue_index, &ring->affinity_mask); | |
ec693d47 | 143 | |
41d942d5 | 144 | *pring = ring; |
c27a02cd YP |
145 | return 0; |
146 | ||
c27a02cd YP |
147 | err_map: |
148 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
149 | err_hwq_res: | |
150 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
151 | err_bounce: | |
152 | kfree(ring->bounce_buf); | |
153 | ring->bounce_buf = NULL; | |
41d942d5 | 154 | err_info: |
dc9b06d1 | 155 | kvfree(ring->tx_info); |
c27a02cd | 156 | ring->tx_info = NULL; |
41d942d5 EE |
157 | err_ring: |
158 | kfree(ring); | |
159 | *pring = NULL; | |
c27a02cd YP |
160 | return err; |
161 | } | |
162 | ||
163 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 164 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
165 | { |
166 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 167 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 168 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 169 | |
0fef9d03 | 170 | if (ring->bf_alloced) |
87a5c389 | 171 | mlx4_bf_free(mdev->dev, &ring->bf); |
c27a02cd YP |
172 | mlx4_qp_remove(mdev->dev, &ring->qp); |
173 | mlx4_qp_free(mdev->dev, &ring->qp); | |
c27a02cd YP |
174 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
175 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
176 | kfree(ring->bounce_buf); | |
177 | ring->bounce_buf = NULL; | |
dc9b06d1 | 178 | kvfree(ring->tx_info); |
c27a02cd | 179 | ring->tx_info = NULL; |
41d942d5 EE |
180 | kfree(ring); |
181 | *pring = NULL; | |
c27a02cd YP |
182 | } |
183 | ||
184 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
185 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 186 | int cq, int user_prio) |
c27a02cd YP |
187 | { |
188 | struct mlx4_en_dev *mdev = priv->mdev; | |
189 | int err; | |
190 | ||
191 | ring->cqn = cq; | |
192 | ring->prod = 0; | |
193 | ring->cons = 0xffffffff; | |
194 | ring->last_nr_txbb = 1; | |
c27a02cd YP |
195 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
196 | memset(ring->buf, 0, ring->buf_size); | |
197 | ||
198 | ring->qp_state = MLX4_QP_STATE_RST; | |
6a4e8121 ED |
199 | ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8); |
200 | ring->mr_key = cpu_to_be32(mdev->mr.key); | |
c27a02cd YP |
201 | |
202 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
0e98b523 | 203 | ring->cqn, user_prio, &ring->context); |
0fef9d03 | 204 | if (ring->bf_alloced) |
87a5c389 | 205 | ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); |
c27a02cd YP |
206 | |
207 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
208 | &ring->qp, &ring->qp_state); | |
d03a68f8 IS |
209 | if (!user_prio && cpu_online(ring->queue_index)) |
210 | netif_set_xps_queue(priv->dev, &ring->affinity_mask, | |
211 | ring->queue_index); | |
c27a02cd YP |
212 | |
213 | return err; | |
214 | } | |
215 | ||
216 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
217 | struct mlx4_en_tx_ring *ring) | |
218 | { | |
219 | struct mlx4_en_dev *mdev = priv->mdev; | |
220 | ||
221 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
222 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
223 | } | |
224 | ||
2d4b6466 EE |
225 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
226 | struct mlx4_en_tx_ring *ring, int index, | |
227 | u8 owner) | |
228 | { | |
229 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
230 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
231 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
232 | void *end = ring->buf + ring->buf_size; | |
233 | __be32 *ptr = (__be32 *)tx_desc; | |
234 | int i; | |
235 | ||
236 | /* Optimize the common case when there are no wraparounds */ | |
237 | if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
238 | /* Stamp the freed descriptor */ | |
239 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
240 | i += STAMP_STRIDE) { | |
241 | *ptr = stamp; | |
242 | ptr += STAMP_DWORDS; | |
243 | } | |
244 | } else { | |
245 | /* Stamp the freed descriptor */ | |
246 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
247 | i += STAMP_STRIDE) { | |
248 | *ptr = stamp; | |
249 | ptr += STAMP_DWORDS; | |
250 | if ((void *)ptr >= end) { | |
251 | ptr = ring->buf; | |
252 | stamp ^= cpu_to_be32(0x80000000); | |
253 | } | |
254 | } | |
255 | } | |
256 | } | |
257 | ||
c27a02cd YP |
258 | |
259 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
260 | struct mlx4_en_tx_ring *ring, | |
ec693d47 | 261 | int index, u8 owner, u64 timestamp) |
c27a02cd | 262 | { |
c27a02cd YP |
263 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
264 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
265 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
c27a02cd | 266 | void *end = ring->buf + ring->buf_size; |
3d03641c ED |
267 | struct sk_buff *skb = tx_info->skb; |
268 | int nr_maps = tx_info->nr_maps; | |
c27a02cd | 269 | int i; |
ec693d47 | 270 | |
29d40c90 ED |
271 | /* We do not touch skb here, so prefetch skb->users location |
272 | * to speedup consume_skb() | |
273 | */ | |
274 | prefetchw(&skb->users); | |
275 | ||
3d03641c ED |
276 | if (unlikely(timestamp)) { |
277 | struct skb_shared_hwtstamps hwts; | |
278 | ||
279 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); | |
ec693d47 AV |
280 | skb_tstamp_tx(skb, &hwts); |
281 | } | |
c27a02cd YP |
282 | |
283 | /* Optimize the common case when there are no wraparounds */ | |
284 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a | 285 | if (!tx_info->inl) { |
3d03641c | 286 | if (tx_info->linear) |
ebf8c9aa | 287 | dma_unmap_single(priv->ddev, |
3d03641c ED |
288 | tx_info->map0_dma, |
289 | tx_info->map0_byte_count, | |
290 | PCI_DMA_TODEVICE); | |
291 | else | |
292 | dma_unmap_page(priv->ddev, | |
293 | tx_info->map0_dma, | |
294 | tx_info->map0_byte_count, | |
295 | PCI_DMA_TODEVICE); | |
296 | for (i = 1; i < nr_maps; i++) { | |
297 | data++; | |
ebf8c9aa | 298 | dma_unmap_page(priv->ddev, |
3d03641c ED |
299 | (dma_addr_t)be64_to_cpu(data->addr), |
300 | be32_to_cpu(data->byte_count), | |
301 | PCI_DMA_TODEVICE); | |
41efea5a | 302 | } |
c27a02cd | 303 | } |
c27a02cd | 304 | } else { |
41efea5a YP |
305 | if (!tx_info->inl) { |
306 | if ((void *) data >= end) { | |
43d620c8 | 307 | data = ring->buf + ((void *)data - end); |
41efea5a | 308 | } |
c27a02cd | 309 | |
3d03641c | 310 | if (tx_info->linear) |
ebf8c9aa | 311 | dma_unmap_single(priv->ddev, |
3d03641c ED |
312 | tx_info->map0_dma, |
313 | tx_info->map0_byte_count, | |
314 | PCI_DMA_TODEVICE); | |
315 | else | |
316 | dma_unmap_page(priv->ddev, | |
317 | tx_info->map0_dma, | |
318 | tx_info->map0_byte_count, | |
319 | PCI_DMA_TODEVICE); | |
320 | for (i = 1; i < nr_maps; i++) { | |
321 | data++; | |
41efea5a YP |
322 | /* Check for wraparound before unmapping */ |
323 | if ((void *) data >= end) | |
43d620c8 | 324 | data = ring->buf; |
ebf8c9aa | 325 | dma_unmap_page(priv->ddev, |
3d03641c ED |
326 | (dma_addr_t)be64_to_cpu(data->addr), |
327 | be32_to_cpu(data->byte_count), | |
328 | PCI_DMA_TODEVICE); | |
41efea5a | 329 | } |
c27a02cd | 330 | } |
c27a02cd | 331 | } |
b89df95d | 332 | dev_consume_skb_any(skb); |
c27a02cd YP |
333 | return tx_info->nr_txbb; |
334 | } | |
335 | ||
336 | ||
337 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
338 | { | |
339 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
340 | int cnt = 0; | |
341 | ||
342 | /* Skip last polled descriptor */ | |
343 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 344 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
345 | ring->cons, ring->prod); |
346 | ||
347 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
348 | if (netif_msg_tx_err(priv)) | |
453a6082 | 349 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
350 | return 0; |
351 | } | |
352 | ||
353 | while (ring->cons != ring->prod) { | |
354 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
355 | ring->cons & ring->size_mask, | |
ec693d47 | 356 | !!(ring->cons & ring->size), 0); |
c27a02cd YP |
357 | ring->cons += ring->last_nr_txbb; |
358 | cnt++; | |
359 | } | |
360 | ||
41b74920 TH |
361 | netdev_tx_reset_queue(ring->tx_queue); |
362 | ||
c27a02cd | 363 | if (cnt) |
453a6082 | 364 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
365 | |
366 | return cnt; | |
367 | } | |
368 | ||
fbc6daf1 AV |
369 | static bool mlx4_en_process_tx_cq(struct net_device *dev, |
370 | struct mlx4_en_cq *cq) | |
c27a02cd YP |
371 | { |
372 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
373 | struct mlx4_cq *mcq = &cq->mcq; | |
41d942d5 | 374 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; |
f0ab34f0 | 375 | struct mlx4_cqe *cqe; |
c27a02cd | 376 | u16 index; |
2d4b6466 | 377 | u16 new_index, ring_index, stamp_index; |
c27a02cd | 378 | u32 txbbs_skipped = 0; |
2d4b6466 | 379 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
380 | u32 cons_index = mcq->cons_index; |
381 | int size = cq->size; | |
382 | u32 size_mask = ring->size_mask; | |
383 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
384 | u32 packets = 0; |
385 | u32 bytes = 0; | |
08ff3235 | 386 | int factor = priv->cqe_factor; |
ec693d47 | 387 | u64 timestamp = 0; |
0276a330 | 388 | int done = 0; |
fbc6daf1 | 389 | int budget = priv->tx_work_limit; |
fb1843ee ED |
390 | u32 last_nr_txbb; |
391 | u32 ring_cons; | |
c27a02cd YP |
392 | |
393 | if (!priv->port_up) | |
fbc6daf1 | 394 | return true; |
c27a02cd | 395 | |
29d40c90 | 396 | prefetchw(&ring->tx_queue->dql.limit); |
f0ab34f0 | 397 | index = cons_index & size_mask; |
b1b6b4da | 398 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
fb1843ee ED |
399 | last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); |
400 | ring_cons = ACCESS_ONCE(ring->cons); | |
401 | ring_index = ring_cons & size_mask; | |
2d4b6466 | 402 | stamp_index = ring_index; |
f0ab34f0 YP |
403 | |
404 | /* Process all completed CQEs */ | |
405 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 406 | cons_index & size) && (done < budget)) { |
f0ab34f0 YP |
407 | /* |
408 | * make sure we read the CQE after we read the | |
409 | * ownership bit | |
410 | */ | |
411 | rmb(); | |
412 | ||
bd2f631d AV |
413 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
414 | MLX4_CQE_OPCODE_ERROR)) { | |
415 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; | |
416 | ||
417 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", | |
418 | cqe_err->vendor_err_syndrome, | |
419 | cqe_err->syndrome); | |
420 | } | |
421 | ||
f0ab34f0 YP |
422 | /* Skip over last polled CQE */ |
423 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
424 | ||
c27a02cd | 425 | do { |
fb1843ee ED |
426 | txbbs_skipped += last_nr_txbb; |
427 | ring_index = (ring_index + last_nr_txbb) & size_mask; | |
ec693d47 AV |
428 | if (ring->tx_info[ring_index].ts_requested) |
429 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
430 | ||
f0ab34f0 | 431 | /* free next descriptor */ |
fb1843ee | 432 | last_nr_txbb = mlx4_en_free_tx_desc( |
f0ab34f0 | 433 | priv, ring, ring_index, |
fb1843ee | 434 | !!((ring_cons + txbbs_skipped) & |
ec693d47 | 435 | ring->size), timestamp); |
2d4b6466 EE |
436 | |
437 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
fb1843ee | 438 | !!((ring_cons + txbbs_stamp) & |
2d4b6466 EE |
439 | ring->size)); |
440 | stamp_index = ring_index; | |
441 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
442 | packets++; |
443 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 444 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
445 | |
446 | ++cons_index; | |
447 | index = cons_index & size_mask; | |
b1b6b4da | 448 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
f0ab34f0 | 449 | } |
c27a02cd | 450 | |
c27a02cd YP |
451 | |
452 | /* | |
453 | * To prevent CQ overflow we first update CQ consumer and only then | |
454 | * the ring consumer. | |
455 | */ | |
f0ab34f0 | 456 | mcq->cons_index = cons_index; |
c27a02cd YP |
457 | mlx4_cq_set_ci(mcq); |
458 | wmb(); | |
fb1843ee ED |
459 | |
460 | /* we want to dirty this cache line once */ | |
461 | ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; | |
462 | ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; | |
463 | ||
5b263f53 | 464 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 465 | |
c18520bd YP |
466 | /* |
467 | * Wakeup Tx queue if this stopped, and at least 1 packet | |
468 | * was completed | |
469 | */ | |
470 | if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { | |
471 | netif_tx_wake_queue(ring->tx_queue); | |
15bffdff | 472 | ring->wake_queue++; |
c27a02cd | 473 | } |
fbc6daf1 | 474 | return done < budget; |
c27a02cd YP |
475 | } |
476 | ||
477 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
478 | { | |
479 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
480 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 481 | |
0276a330 EE |
482 | if (priv->port_up) |
483 | napi_schedule(&cq->napi); | |
484 | else | |
485 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
486 | } |
487 | ||
0276a330 EE |
488 | /* TX CQ polling - called by NAPI */ |
489 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
490 | { | |
491 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
492 | struct net_device *dev = cq->dev; | |
493 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
fbc6daf1 | 494 | int clean_complete; |
0276a330 | 495 | |
fbc6daf1 AV |
496 | clean_complete = mlx4_en_process_tx_cq(dev, cq); |
497 | if (!clean_complete) | |
498 | return budget; | |
0276a330 | 499 | |
fbc6daf1 AV |
500 | napi_complete(napi); |
501 | mlx4_en_arm_cq(priv, cq); | |
502 | ||
503 | return 0; | |
0276a330 | 504 | } |
c27a02cd | 505 | |
c27a02cd YP |
506 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
507 | struct mlx4_en_tx_ring *ring, | |
508 | u32 index, | |
509 | unsigned int desc_size) | |
510 | { | |
511 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
512 | int i; | |
513 | ||
514 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
515 | if ((i & (TXBB_SIZE - 1)) == 0) | |
516 | wmb(); | |
517 | ||
518 | *((u32 *) (ring->buf + i)) = | |
519 | *((u32 *) (ring->bounce_buf + copy + i)); | |
520 | } | |
521 | ||
522 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
523 | if ((i & (TXBB_SIZE - 1)) == 0) | |
524 | wmb(); | |
525 | ||
526 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
527 | *((u32 *) (ring->bounce_buf + i)); | |
528 | } | |
529 | ||
530 | /* Return real descriptor location */ | |
531 | return ring->buf + index * TXBB_SIZE; | |
532 | } | |
533 | ||
7dfa4b41 ED |
534 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
535 | void **pfrag) | |
c27a02cd YP |
536 | { |
537 | void *ptr; | |
538 | ||
539 | if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { | |
540 | if (skb_shinfo(skb)->nr_frags == 1) { | |
311761c8 | 541 | ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]); |
c27a02cd YP |
542 | if (unlikely(!ptr)) |
543 | return 0; | |
544 | ||
545 | if (pfrag) | |
546 | *pfrag = ptr; | |
547 | ||
548 | return 1; | |
549 | } else if (unlikely(skb_shinfo(skb)->nr_frags)) | |
550 | return 0; | |
551 | else | |
552 | return 1; | |
553 | } | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
7dfa4b41 | 558 | static int inline_size(const struct sk_buff *skb) |
c27a02cd YP |
559 | { |
560 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
561 | <= MLX4_INLINE_ALIGN) | |
562 | return ALIGN(skb->len + CTRL_SIZE + | |
563 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
564 | else | |
565 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
566 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
567 | } | |
568 | ||
7dfa4b41 ED |
569 | static int get_real_size(const struct sk_buff *skb, |
570 | struct net_device *dev, | |
c27a02cd YP |
571 | int *lso_header_size) |
572 | { | |
573 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
574 | int real_size; |
575 | ||
576 | if (skb_is_gso(skb)) { | |
837052d0 OG |
577 | if (skb->encapsulation) |
578 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); | |
579 | else | |
580 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
c27a02cd YP |
581 | real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + |
582 | ALIGN(*lso_header_size + 4, DS_SIZE); | |
583 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
584 | /* We add a segment for the skb linear buffer only if | |
585 | * it contains data */ | |
586 | if (*lso_header_size < skb_headlen(skb)) | |
587 | real_size += DS_SIZE; | |
588 | else { | |
589 | if (netif_msg_tx_err(priv)) | |
453a6082 | 590 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
591 | return 0; |
592 | } | |
593 | } | |
c27a02cd YP |
594 | } else { |
595 | *lso_header_size = 0; | |
b97b33a3 | 596 | if (!is_inline(priv->prof->inline_thold, skb, NULL)) |
c27a02cd YP |
597 | real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; |
598 | else | |
599 | real_size = inline_size(skb); | |
600 | } | |
601 | ||
602 | return real_size; | |
603 | } | |
604 | ||
7dfa4b41 ED |
605 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
606 | const struct sk_buff *skb, | |
607 | int real_size, u16 *vlan_tag, | |
608 | int tx_ind, void *fragptr) | |
c27a02cd YP |
609 | { |
610 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
611 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
612 | ||
613 | if (skb->len <= spc) { | |
93591aaa EE |
614 | if (likely(skb->len >= MIN_PKT_LEN)) { |
615 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
616 | } else { | |
617 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
618 | memset(((void *)(inl + 1)) + skb->len, 0, | |
619 | MIN_PKT_LEN - skb->len); | |
620 | } | |
c27a02cd YP |
621 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); |
622 | if (skb_shinfo(skb)->nr_frags) | |
623 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, | |
9e903e08 | 624 | skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
625 | |
626 | } else { | |
627 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
628 | if (skb_headlen(skb) <= spc) { | |
629 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
630 | if (skb_headlen(skb) < spc) { | |
631 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), | |
632 | fragptr, spc - skb_headlen(skb)); | |
633 | fragptr += spc - skb_headlen(skb); | |
634 | } | |
635 | inl = (void *) (inl + 1) + spc; | |
636 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
637 | } else { | |
638 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
639 | inl = (void *) (inl + 1) + spc; | |
640 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
641 | skb_headlen(skb) - spc); | |
642 | if (skb_shinfo(skb)->nr_frags) | |
643 | memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, | |
9e903e08 | 644 | fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
645 | } |
646 | ||
647 | wmb(); | |
648 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); | |
649 | } | |
c27a02cd YP |
650 | } |
651 | ||
f663dd9a | 652 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 653 | void *accel_priv, select_queue_fallback_t fallback) |
c27a02cd | 654 | { |
bc6a4744 | 655 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 656 | u16 rings_p_up = priv->num_tx_rings_p_up; |
bc6a4744 | 657 | u8 up = 0; |
c27a02cd | 658 | |
bc6a4744 AV |
659 | if (dev->num_tc) |
660 | return skb_tx_hash(dev, skb); | |
661 | ||
662 | if (vlan_tx_tag_present(skb)) | |
663 | up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; | |
f813cad8 | 664 | |
99932d4f | 665 | return fallback(dev, skb) % rings_p_up + up * rings_p_up; |
c27a02cd YP |
666 | } |
667 | ||
7dfa4b41 ED |
668 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
669 | unsigned int bytecnt) | |
87a5c389 YP |
670 | { |
671 | __iowrite64_copy(dst, src, bytecnt / 8); | |
672 | } | |
673 | ||
61357325 | 674 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd YP |
675 | { |
676 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
237a3a3b | 677 | struct device *ddev = priv->ddev; |
c27a02cd | 678 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
679 | struct mlx4_en_tx_desc *tx_desc; |
680 | struct mlx4_wqe_data_seg *data; | |
c27a02cd YP |
681 | struct mlx4_en_tx_info *tx_info; |
682 | int tx_ind = 0; | |
683 | int nr_txbb; | |
684 | int desc_size; | |
685 | int real_size; | |
87a5c389 | 686 | u32 index, bf_index; |
c27a02cd | 687 | __be32 op_own; |
f813cad8 | 688 | u16 vlan_tag = 0; |
c27a02cd YP |
689 | int i; |
690 | int lso_header_size; | |
691 | void *fragptr; | |
87a5c389 | 692 | bool bounce = false; |
5804283d | 693 | bool send_doorbell; |
f905c79e | 694 | u32 ring_cons; |
c27a02cd | 695 | |
3005ad40 YP |
696 | if (!priv->port_up) |
697 | goto tx_drop; | |
698 | ||
f905c79e ED |
699 | tx_ind = skb_get_queue_mapping(skb); |
700 | ring = priv->tx_ring[tx_ind]; | |
701 | ||
702 | /* fetch ring->cons far ahead before needing it to avoid stall */ | |
703 | ring_cons = ACCESS_ONCE(ring->cons); | |
704 | ||
c27a02cd YP |
705 | real_size = get_real_size(skb, dev, &lso_header_size); |
706 | if (unlikely(!real_size)) | |
7e230913 | 707 | goto tx_drop; |
c27a02cd | 708 | |
25985edc | 709 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
710 | desc_size = ALIGN(real_size, TXBB_SIZE); |
711 | nr_txbb = desc_size / TXBB_SIZE; | |
712 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
713 | if (netif_msg_tx_err(priv)) | |
453a6082 | 714 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 715 | goto tx_drop; |
c27a02cd YP |
716 | } |
717 | ||
eab6d18d | 718 | if (vlan_tx_tag_present(skb)) |
f813cad8 | 719 | vlan_tag = vlan_tx_tag_get(skb); |
c27a02cd YP |
720 | |
721 | /* Check available TXBBs And 2K spare for prefetch */ | |
f905c79e | 722 | if (unlikely(((int)(ring->prod - ring_cons)) > |
c27a02cd | 723 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { |
f813cad8 | 724 | /* every full Tx ring stops queue */ |
5b263f53 | 725 | netif_tx_stop_queue(ring->tx_queue); |
15bffdff | 726 | ring->queue_stopped++; |
c27a02cd | 727 | |
72259225 AV |
728 | /* If queue was emptied after the if, and before the |
729 | * stop_queue - need to wake the queue, or else it will remain | |
730 | * stopped forever. | |
731 | * Need a memory barrier to make sure ring->cons was not | |
732 | * updated before queue was stopped. | |
733 | */ | |
734 | wmb(); | |
735 | ||
f905c79e ED |
736 | ring_cons = ACCESS_ONCE(ring->cons); |
737 | if (unlikely(((int)(ring->prod - ring_cons)) <= | |
72259225 AV |
738 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { |
739 | netif_tx_wake_queue(ring->tx_queue); | |
15bffdff | 740 | ring->wake_queue++; |
72259225 AV |
741 | } else { |
742 | return NETDEV_TX_BUSY; | |
743 | } | |
c27a02cd YP |
744 | } |
745 | ||
29d40c90 ED |
746 | prefetchw(&ring->tx_queue->dql); |
747 | ||
c27a02cd YP |
748 | /* Track current inflight packets for performance analysis */ |
749 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
f905c79e | 750 | (u32)(ring->prod - ring_cons - 1)); |
c27a02cd YP |
751 | |
752 | /* Packet is good - grab an index and transmit it */ | |
753 | index = ring->prod & ring->size_mask; | |
87a5c389 | 754 | bf_index = ring->prod; |
c27a02cd YP |
755 | |
756 | /* See if we have enough space for whole descriptor TXBB for setting | |
757 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
758 | if (likely(index + nr_txbb <= ring->size)) | |
759 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 760 | else { |
c27a02cd | 761 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 YP |
762 | bounce = true; |
763 | } | |
c27a02cd YP |
764 | |
765 | /* Save skb in tx_info ring */ | |
766 | tx_info = &ring->tx_info[index]; | |
767 | tx_info->skb = skb; | |
768 | tx_info->nr_txbb = nr_txbb; | |
769 | ||
7dfa4b41 | 770 | data = &tx_desc->data; |
237a3a3b AV |
771 | if (lso_header_size) |
772 | data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, | |
773 | DS_SIZE)); | |
237a3a3b AV |
774 | |
775 | /* valid only for none inline segments */ | |
776 | tx_info->data_offset = (void *)data - (void *)tx_desc; | |
777 | ||
778 | tx_info->linear = (lso_header_size < skb_headlen(skb) && | |
b97b33a3 | 779 | !is_inline(ring->inline_thold, skb, NULL)) ? 1 : 0; |
237a3a3b | 780 | |
3d03641c ED |
781 | tx_info->nr_maps = skb_shinfo(skb)->nr_frags + tx_info->linear; |
782 | data += tx_info->nr_maps - 1; | |
237a3a3b | 783 | |
b97b33a3 | 784 | if (is_inline(ring->inline_thold, skb, &fragptr)) { |
237a3a3b AV |
785 | tx_info->inl = 1; |
786 | } else { | |
3d03641c ED |
787 | dma_addr_t dma = 0; |
788 | u32 byte_count = 0; | |
789 | ||
7dfa4b41 | 790 | /* Map fragments if any */ |
237a3a3b | 791 | for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { |
7dfa4b41 | 792 | const struct skb_frag_struct *frag; |
237a3a3b | 793 | frag = &skb_shinfo(skb)->frags[i]; |
3d03641c | 794 | byte_count = skb_frag_size(frag); |
237a3a3b | 795 | dma = skb_frag_dma_map(ddev, frag, |
3d03641c | 796 | 0, byte_count, |
237a3a3b AV |
797 | DMA_TO_DEVICE); |
798 | if (dma_mapping_error(ddev, dma)) | |
799 | goto tx_drop_unmap; | |
800 | ||
801 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 802 | data->lkey = ring->mr_key; |
237a3a3b | 803 | wmb(); |
3d03641c | 804 | data->byte_count = cpu_to_be32(byte_count); |
237a3a3b AV |
805 | --data; |
806 | } | |
807 | ||
7dfa4b41 | 808 | /* Map linear part if needed */ |
237a3a3b | 809 | if (tx_info->linear) { |
3d03641c | 810 | byte_count = skb_headlen(skb) - lso_header_size; |
5f1cd200 | 811 | |
237a3a3b AV |
812 | dma = dma_map_single(ddev, skb->data + |
813 | lso_header_size, byte_count, | |
814 | PCI_DMA_TODEVICE); | |
815 | if (dma_mapping_error(ddev, dma)) | |
816 | goto tx_drop_unmap; | |
817 | ||
818 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 819 | data->lkey = ring->mr_key; |
237a3a3b AV |
820 | wmb(); |
821 | data->byte_count = cpu_to_be32(byte_count); | |
822 | } | |
823 | tx_info->inl = 0; | |
3d03641c ED |
824 | /* tx completion can avoid cache line miss for common cases */ |
825 | tx_info->map0_dma = dma; | |
826 | tx_info->map0_byte_count = byte_count; | |
237a3a3b AV |
827 | } |
828 | ||
ec693d47 AV |
829 | /* |
830 | * For timestamping add flag to skb_shinfo and | |
831 | * set flag for further reference | |
832 | */ | |
7dfa4b41 ED |
833 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
834 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { | |
835 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; | |
ec693d47 AV |
836 | tx_info->ts_requested = 1; |
837 | } | |
838 | ||
c27a02cd YP |
839 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
840 | * whether LSO is used */ | |
60d6fe99 | 841 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd YP |
842 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
843 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
844 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
ad04378c | 845 | ring->tx_csum++; |
c27a02cd YP |
846 | } |
847 | ||
79aeaccd | 848 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
849 | struct ethhdr *ethh; |
850 | ||
213815a1 YB |
851 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
852 | * so that VFs and PF can communicate with each other | |
853 | */ | |
854 | ethh = (struct ethhdr *)skb->data; | |
855 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
856 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
857 | } | |
858 | ||
c27a02cd YP |
859 | /* Handle LSO (TSO) packets */ |
860 | if (lso_header_size) { | |
861 | /* Mark opcode as LSO */ | |
862 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
863 | ((ring->prod & ring->size) ? | |
864 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
865 | ||
866 | /* Fill in the LSO prefix */ | |
867 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
868 | skb_shinfo(skb)->gso_size << 16 | lso_header_size); | |
869 | ||
870 | /* Copy headers; | |
871 | * note that we already verified that it is linear */ | |
872 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
c27a02cd | 873 | |
9fab426d | 874 | ring->tso_packets++; |
c27a02cd YP |
875 | i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + |
876 | !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); | |
5b263f53 | 877 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
878 | ring->packets += i; |
879 | } else { | |
880 | /* Normal (Non LSO) packet */ | |
881 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
882 | ((ring->prod & ring->size) ? | |
883 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 884 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd | 885 | ring->packets++; |
c27a02cd | 886 | } |
5b263f53 YP |
887 | ring->bytes += tx_info->nr_bytes; |
888 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); | |
c27a02cd YP |
889 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
890 | ||
237a3a3b | 891 | if (tx_info->inl) { |
c27a02cd | 892 | build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); |
41efea5a YP |
893 | tx_info->inl = 1; |
894 | } | |
c27a02cd | 895 | |
837052d0 OG |
896 | if (skb->encapsulation) { |
897 | struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); | |
898 | if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) | |
899 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); | |
900 | else | |
901 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
902 | } | |
903 | ||
c27a02cd YP |
904 | ring->prod += nr_txbb; |
905 | ||
906 | /* If we used a bounce buffer then copy descriptor back into place */ | |
7dfa4b41 | 907 | if (unlikely(bounce)) |
c27a02cd YP |
908 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
909 | ||
eb0cabbd AV |
910 | skb_tx_timestamp(skb); |
911 | ||
5804283d ED |
912 | send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); |
913 | ||
6a4e8121 ED |
914 | real_size = (real_size / 16) & 0x3f; |
915 | ||
5804283d ED |
916 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && |
917 | !vlan_tx_tag_present(skb) && send_doorbell) { | |
6a4e8121 ED |
918 | tx_desc->ctrl.bf_qpn = ring->doorbell_qpn | |
919 | cpu_to_be32(real_size); | |
ec570940 | 920 | |
87a5c389 | 921 | op_own |= htonl((bf_index & 0xffff) << 8); |
5804283d ED |
922 | /* Ensure new descriptor hits memory |
923 | * before setting ownership of this descriptor to HW | |
924 | */ | |
87a5c389 YP |
925 | wmb(); |
926 | tx_desc->ctrl.owner_opcode = op_own; | |
c27a02cd | 927 | |
87a5c389 YP |
928 | wmb(); |
929 | ||
7dfa4b41 ED |
930 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, |
931 | desc_size); | |
87a5c389 YP |
932 | |
933 | wmb(); | |
934 | ||
935 | ring->bf.offset ^= ring->bf.buf_size; | |
936 | } else { | |
7dfa4b41 ED |
937 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); |
938 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * | |
939 | !!vlan_tx_tag_present(skb); | |
940 | tx_desc->ctrl.fence_size = real_size; | |
941 | ||
5804283d ED |
942 | /* Ensure new descriptor hits memory |
943 | * before setting ownership of this descriptor to HW | |
944 | */ | |
87a5c389 YP |
945 | wmb(); |
946 | tx_desc->ctrl.owner_opcode = op_own; | |
5804283d ED |
947 | if (send_doorbell) { |
948 | wmb(); | |
6a4e8121 ED |
949 | iowrite32(ring->doorbell_qpn, |
950 | ring->bf.uar->map + MLX4_SEND_DOORBELL); | |
9fab426d ED |
951 | } else { |
952 | ring->xmit_more++; | |
5804283d | 953 | } |
87a5c389 | 954 | } |
c27a02cd | 955 | |
ec634fe3 | 956 | return NETDEV_TX_OK; |
7e230913 | 957 | |
237a3a3b AV |
958 | tx_drop_unmap: |
959 | en_err(priv, "DMA mapping error\n"); | |
960 | ||
961 | for (i++; i < skb_shinfo(skb)->nr_frags; i++) { | |
962 | data++; | |
963 | dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), | |
964 | be32_to_cpu(data->byte_count), | |
965 | PCI_DMA_TODEVICE); | |
966 | } | |
967 | ||
7e230913 YP |
968 | tx_drop: |
969 | dev_kfree_skb_any(skb); | |
970 | priv->stats.tx_dropped++; | |
971 | return NETDEV_TX_OK; | |
c27a02cd YP |
972 | } |
973 |