Commit | Line | Data |
---|---|---|
c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
c27a02cd | 35 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
b67bfe0d | 39 | #include <linux/rculist.h> |
c27a02cd YP |
40 | #include <linux/if_ether.h> |
41 | #include <linux/if_vlan.h> | |
42 | #include <linux/vmalloc.h> | |
35f6f453 | 43 | #include <linux/irq.h> |
c27a02cd | 44 | |
f8c6455b SM |
45 | #if IS_ENABLED(CONFIG_IPV6) |
46 | #include <net/ip6_checksum.h> | |
47 | #endif | |
48 | ||
c27a02cd YP |
49 | #include "mlx4_en.h" |
50 | ||
51151a16 ED |
51 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
52 | struct mlx4_en_rx_alloc *page_alloc, | |
53 | const struct mlx4_en_frag_info *frag_info, | |
54 | gfp_t _gfp) | |
55 | { | |
56 | int order; | |
57 | struct page *page; | |
58 | dma_addr_t dma; | |
59 | ||
60 | for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { | |
61 | gfp_t gfp = _gfp; | |
62 | ||
63 | if (order) | |
04aeb56a | 64 | gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC; |
51151a16 ED |
65 | page = alloc_pages(gfp, order); |
66 | if (likely(page)) | |
67 | break; | |
68 | if (--order < 0 || | |
69 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
70 | return -ENOMEM; | |
71 | } | |
72 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
73 | PCI_DMA_FROMDEVICE); | |
74 | if (dma_mapping_error(priv->ddev, dma)) { | |
75 | put_page(page); | |
76 | return -ENOMEM; | |
77 | } | |
70fbe079 | 78 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
79 | page_alloc->page = page; |
80 | page_alloc->dma = dma; | |
5f6e9800 | 81 | page_alloc->page_offset = 0; |
51151a16 | 82 | /* Not doing get_page() for each frag is a big win |
98226208 | 83 | * on asymetric workloads. Note we can not use atomic_set(). |
51151a16 | 84 | */ |
fe896d18 | 85 | page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1); |
51151a16 ED |
86 | return 0; |
87 | } | |
88 | ||
4cce66cd TLSC |
89 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
90 | struct mlx4_en_rx_desc *rx_desc, | |
91 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
92 | struct mlx4_en_rx_alloc *ring_alloc, |
93 | gfp_t gfp) | |
c27a02cd | 94 | { |
4cce66cd | 95 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 96 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
97 | struct page *page; |
98 | dma_addr_t dma; | |
4cce66cd | 99 | int i; |
c27a02cd | 100 | |
4cce66cd TLSC |
101 | for (i = 0; i < priv->num_frags; i++) { |
102 | frag_info = &priv->frag_info[i]; | |
51151a16 | 103 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
104 | page_alloc[i].page_offset += frag_info->frag_stride; |
105 | ||
106 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
107 | ring_alloc[i].page_size) | |
51151a16 | 108 | continue; |
70fbe079 | 109 | |
51151a16 ED |
110 | if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) |
111 | goto out; | |
4cce66cd | 112 | } |
c27a02cd | 113 | |
4cce66cd TLSC |
114 | for (i = 0; i < priv->num_frags; i++) { |
115 | frags[i] = ring_alloc[i]; | |
70fbe079 | 116 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
117 | ring_alloc[i] = page_alloc[i]; |
118 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 119 | } |
4cce66cd | 120 | |
c27a02cd | 121 | return 0; |
4cce66cd | 122 | |
4cce66cd TLSC |
123 | out: |
124 | while (i--) { | |
51151a16 | 125 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 126 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
70fbe079 | 127 | page_alloc[i].page_size, PCI_DMA_FROMDEVICE); |
51151a16 | 128 | page = page_alloc[i].page; |
851b10d6 KK |
129 | /* Revert changes done by mlx4_alloc_pages */ |
130 | page_ref_sub(page, page_alloc[i].page_size / | |
131 | priv->frag_info[i].frag_stride - 1); | |
51151a16 ED |
132 | put_page(page); |
133 | } | |
4cce66cd TLSC |
134 | } |
135 | return -ENOMEM; | |
136 | } | |
137 | ||
138 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
139 | struct mlx4_en_rx_alloc *frags, | |
140 | int i) | |
141 | { | |
51151a16 | 142 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 143 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 144 | |
021f1107 AV |
145 | |
146 | if (next_frag_end > frags[i].page_size) | |
70fbe079 AV |
147 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
148 | PCI_DMA_FROMDEVICE); | |
51151a16 | 149 | |
4cce66cd TLSC |
150 | if (frags[i].page) |
151 | put_page(frags[i].page); | |
c27a02cd YP |
152 | } |
153 | ||
154 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
155 | struct mlx4_en_rx_ring *ring) | |
156 | { | |
c27a02cd | 157 | int i; |
51151a16 | 158 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
159 | |
160 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 161 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 162 | |
51151a16 | 163 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
1ab25f86 | 164 | frag_info, GFP_KERNEL | __GFP_COLD)) |
4cce66cd | 165 | goto out; |
b110d2ce IS |
166 | |
167 | en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n", | |
168 | i, ring->page_alloc[i].page_size, | |
fe896d18 | 169 | page_ref_count(ring->page_alloc[i].page)); |
c27a02cd YP |
170 | } |
171 | return 0; | |
172 | ||
173 | out: | |
174 | while (i--) { | |
51151a16 ED |
175 | struct page *page; |
176 | ||
c27a02cd | 177 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 178 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 | 179 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
51151a16 | 180 | page = page_alloc->page; |
851b10d6 KK |
181 | /* Revert changes done by mlx4_alloc_pages */ |
182 | page_ref_sub(page, page_alloc->page_size / | |
183 | priv->frag_info[i].frag_stride - 1); | |
51151a16 | 184 | put_page(page); |
c27a02cd YP |
185 | page_alloc->page = NULL; |
186 | } | |
187 | return -ENOMEM; | |
188 | } | |
189 | ||
190 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
191 | struct mlx4_en_rx_ring *ring) | |
192 | { | |
193 | struct mlx4_en_rx_alloc *page_alloc; | |
194 | int i; | |
195 | ||
196 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
197 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
198 | ||
c27a02cd | 199 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
200 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
201 | i, page_count(page_alloc->page)); | |
c27a02cd | 202 | |
4cce66cd | 203 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 AV |
204 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
205 | while (page_alloc->page_offset + frag_info->frag_stride < | |
206 | page_alloc->page_size) { | |
51151a16 | 207 | put_page(page_alloc->page); |
70fbe079 | 208 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 209 | } |
c27a02cd YP |
210 | page_alloc->page = NULL; |
211 | } | |
212 | } | |
213 | ||
c27a02cd YP |
214 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
215 | struct mlx4_en_rx_ring *ring, int index) | |
216 | { | |
217 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
218 | int possible_frags; |
219 | int i; | |
220 | ||
c27a02cd YP |
221 | /* Set size and memtype fields */ |
222 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
223 | rx_desc->data[i].byte_count = |
224 | cpu_to_be32(priv->frag_info[i].frag_size); | |
225 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
226 | } | |
227 | ||
228 | /* If the number of used fragments does not fill up the ring stride, | |
229 | * remaining (unused) fragments must be padded with null address/size | |
230 | * and a special memory key */ | |
231 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
232 | for (i = priv->num_frags; i < possible_frags; i++) { | |
233 | rx_desc->data[i].byte_count = 0; | |
234 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
235 | rx_desc->data[i].addr = 0; | |
236 | } | |
237 | } | |
238 | ||
c27a02cd | 239 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
240 | struct mlx4_en_rx_ring *ring, int index, |
241 | gfp_t gfp) | |
c27a02cd YP |
242 | { |
243 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
244 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
245 | (index << priv->log_rx_info); | |
c27a02cd | 246 | |
51151a16 | 247 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
248 | } |
249 | ||
07841f9d IS |
250 | static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring) |
251 | { | |
07841f9d IS |
252 | return ring->prod == ring->cons; |
253 | } | |
254 | ||
c27a02cd YP |
255 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) |
256 | { | |
257 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
258 | } | |
259 | ||
38aab07c YP |
260 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
261 | struct mlx4_en_rx_ring *ring, | |
262 | int index) | |
263 | { | |
4cce66cd | 264 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
265 | int nr; |
266 | ||
4cce66cd | 267 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 268 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 269 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 270 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
271 | } |
272 | } | |
273 | ||
c27a02cd YP |
274 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
275 | { | |
c27a02cd YP |
276 | struct mlx4_en_rx_ring *ring; |
277 | int ring_ind; | |
278 | int buf_ind; | |
38aab07c | 279 | int new_size; |
c27a02cd YP |
280 | |
281 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
282 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 283 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
284 | |
285 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 | 286 | ring->actual_size, |
1ab25f86 | 287 | GFP_KERNEL | __GFP_COLD)) { |
c27a02cd | 288 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 289 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
290 | return -ENOMEM; |
291 | } else { | |
38aab07c | 292 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 293 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 294 | ring->actual_size, new_size); |
38aab07c | 295 | goto reduce_rings; |
c27a02cd YP |
296 | } |
297 | } | |
298 | ring->actual_size++; | |
299 | ring->prod++; | |
300 | } | |
301 | } | |
38aab07c YP |
302 | return 0; |
303 | ||
304 | reduce_rings: | |
305 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 306 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
307 | while (ring->actual_size > new_size) { |
308 | ring->actual_size--; | |
309 | ring->prod--; | |
310 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
311 | } | |
38aab07c YP |
312 | } |
313 | ||
c27a02cd YP |
314 | return 0; |
315 | } | |
316 | ||
c27a02cd YP |
317 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
318 | struct mlx4_en_rx_ring *ring) | |
319 | { | |
c27a02cd | 320 | int index; |
c27a02cd | 321 | |
453a6082 YP |
322 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
323 | ring->cons, ring->prod); | |
c27a02cd YP |
324 | |
325 | /* Unmap and free Rx buffers */ | |
07841f9d | 326 | while (!mlx4_en_is_ring_empty(ring)) { |
c27a02cd | 327 | index = ring->cons & ring->size_mask; |
453a6082 | 328 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 329 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
330 | ++ring->cons; |
331 | } | |
332 | } | |
333 | ||
02512482 IS |
334 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
335 | { | |
336 | int i; | |
337 | int num_of_eqs; | |
bb2146bc | 338 | int num_rx_rings; |
02512482 IS |
339 | struct mlx4_dev *dev = mdev->dev; |
340 | ||
341 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
c66fa19c MB |
342 | num_of_eqs = max_t(int, MIN_RX_RINGS, |
343 | min_t(int, | |
344 | mlx4_get_eqs_per_port(mdev->dev, i), | |
345 | DEF_RX_RINGS)); | |
02512482 | 346 | |
ea1c1af1 AV |
347 | num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : |
348 | min_t(int, num_of_eqs, | |
349 | netif_get_num_default_rss_queues()); | |
02512482 | 350 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 351 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
352 | } |
353 | } | |
354 | ||
c27a02cd | 355 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 356 | struct mlx4_en_rx_ring **pring, |
163561a4 | 357 | u32 size, u16 stride, int node) |
c27a02cd YP |
358 | { |
359 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 360 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 361 | int err = -ENOMEM; |
c27a02cd YP |
362 | int tmp; |
363 | ||
163561a4 | 364 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 365 | if (!ring) { |
163561a4 EE |
366 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
367 | if (!ring) { | |
368 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
369 | return -ENOMEM; | |
370 | } | |
41d942d5 EE |
371 | } |
372 | ||
c27a02cd YP |
373 | ring->prod = 0; |
374 | ring->cons = 0; | |
375 | ring->size = size; | |
376 | ring->size_mask = size - 1; | |
377 | ring->stride = stride; | |
378 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 379 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
380 | |
381 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 382 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 383 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 384 | if (!ring->rx_info) { |
163561a4 EE |
385 | ring->rx_info = vmalloc(tmp); |
386 | if (!ring->rx_info) { | |
387 | err = -ENOMEM; | |
388 | goto err_ring; | |
389 | } | |
41d942d5 | 390 | } |
e404decb | 391 | |
453a6082 | 392 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
393 | ring->rx_info, tmp); |
394 | ||
163561a4 | 395 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 396 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
73898db0 | 397 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
872bf2fb | 398 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 399 | if (err) |
41d942d5 | 400 | goto err_info; |
c27a02cd | 401 | |
c27a02cd YP |
402 | ring->buf = ring->wqres.buf.direct.buf; |
403 | ||
ec693d47 AV |
404 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
405 | ||
41d942d5 | 406 | *pring = ring; |
c27a02cd YP |
407 | return 0; |
408 | ||
41d942d5 | 409 | err_info: |
c27a02cd YP |
410 | vfree(ring->rx_info); |
411 | ring->rx_info = NULL; | |
41d942d5 EE |
412 | err_ring: |
413 | kfree(ring); | |
414 | *pring = NULL; | |
415 | ||
c27a02cd YP |
416 | return err; |
417 | } | |
418 | ||
419 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
420 | { | |
c27a02cd YP |
421 | struct mlx4_en_rx_ring *ring; |
422 | int i; | |
423 | int ring_ind; | |
424 | int err; | |
425 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
426 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
427 | |
428 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 429 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
430 | |
431 | ring->prod = 0; | |
432 | ring->cons = 0; | |
433 | ring->actual_size = 0; | |
41d942d5 | 434 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
435 | |
436 | ring->stride = stride; | |
9f519f68 YP |
437 | if (ring->stride <= TXBB_SIZE) |
438 | ring->buf += TXBB_SIZE; | |
439 | ||
c27a02cd YP |
440 | ring->log_stride = ffs(ring->stride) - 1; |
441 | ring->buf_size = ring->size * ring->stride; | |
442 | ||
443 | memset(ring->buf, 0, ring->buf_size); | |
444 | mlx4_en_update_rx_prod_db(ring); | |
445 | ||
4cce66cd | 446 | /* Initialize all descriptors */ |
c27a02cd YP |
447 | for (i = 0; i < ring->size; i++) |
448 | mlx4_en_init_rx_desc(priv, ring, i); | |
449 | ||
450 | /* Initialize page allocators */ | |
451 | err = mlx4_en_init_allocator(priv, ring); | |
452 | if (err) { | |
453a6082 | 453 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
454 | if (ring->stride <= TXBB_SIZE) |
455 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
456 | ring_ind--; |
457 | goto err_allocator; | |
c27a02cd | 458 | } |
c27a02cd | 459 | } |
b58515be IM |
460 | err = mlx4_en_fill_rx_buffers(priv); |
461 | if (err) | |
c27a02cd YP |
462 | goto err_buffers; |
463 | ||
464 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 465 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 466 | |
00d7d7bc | 467 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 468 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
469 | } |
470 | ||
471 | return 0; | |
472 | ||
c27a02cd YP |
473 | err_buffers: |
474 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 475 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
476 | |
477 | ring_ind = priv->rx_ring_num - 1; | |
478 | err_allocator: | |
479 | while (ring_ind >= 0) { | |
41d942d5 EE |
480 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
481 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
482 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
483 | ring_ind--; |
484 | } | |
485 | return err; | |
486 | } | |
487 | ||
07841f9d IS |
488 | /* We recover from out of memory by scheduling our napi poll |
489 | * function (mlx4_en_process_cq), which tries to allocate | |
490 | * all missing RX buffers (call to mlx4_en_refill_rx_buffers). | |
491 | */ | |
492 | void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) | |
493 | { | |
494 | int ring; | |
495 | ||
496 | if (!priv->port_up) | |
497 | return; | |
498 | ||
499 | for (ring = 0; ring < priv->rx_ring_num; ring++) { | |
500 | if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) | |
501 | napi_reschedule(&priv->rx_cq[ring]->napi); | |
502 | } | |
503 | } | |
504 | ||
c27a02cd | 505 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 EE |
506 | struct mlx4_en_rx_ring **pring, |
507 | u32 size, u16 stride) | |
c27a02cd YP |
508 | { |
509 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 510 | struct mlx4_en_rx_ring *ring = *pring; |
c27a02cd | 511 | |
68355f71 | 512 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
513 | vfree(ring->rx_info); |
514 | ring->rx_info = NULL; | |
41d942d5 EE |
515 | kfree(ring); |
516 | *pring = NULL; | |
c27a02cd YP |
517 | } |
518 | ||
519 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
520 | struct mlx4_en_rx_ring *ring) | |
521 | { | |
c27a02cd | 522 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
523 | if (ring->stride <= TXBB_SIZE) |
524 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
525 | mlx4_en_destroy_allocator(priv, ring); |
526 | } | |
527 | ||
528 | ||
c27a02cd YP |
529 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
530 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 531 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 532 | struct sk_buff *skb, |
c27a02cd YP |
533 | int length) |
534 | { | |
90278c9f | 535 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
536 | struct mlx4_en_frag_info *frag_info; |
537 | int nr; | |
538 | dma_addr_t dma; | |
539 | ||
4cce66cd | 540 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
541 | for (nr = 0; nr < priv->num_frags; nr++) { |
542 | frag_info = &priv->frag_info[nr]; | |
543 | if (length <= frag_info->frag_prefix_size) | |
544 | break; | |
4cce66cd TLSC |
545 | if (!frags[nr].page) |
546 | goto fail; | |
c27a02cd | 547 | |
c27a02cd | 548 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
549 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
550 | DMA_FROM_DEVICE); | |
c27a02cd | 551 | |
4cce66cd | 552 | /* Save page reference in skb */ |
4cce66cd TLSC |
553 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
554 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 555 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 556 | skb->truesize += frag_info->frag_stride; |
51151a16 | 557 | frags[nr].page = NULL; |
c27a02cd YP |
558 | } |
559 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 560 | if (nr > 0) |
9e903e08 ED |
561 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
562 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
563 | return nr; |
564 | ||
565 | fail: | |
c27a02cd YP |
566 | while (nr > 0) { |
567 | nr--; | |
311761c8 | 568 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
569 | } |
570 | return 0; | |
571 | } | |
572 | ||
573 | ||
574 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
575 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 576 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
577 | unsigned int length) |
578 | { | |
c27a02cd YP |
579 | struct sk_buff *skb; |
580 | void *va; | |
581 | int used_frags; | |
582 | dma_addr_t dma; | |
583 | ||
c056b734 | 584 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 585 | if (!skb) { |
453a6082 | 586 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
587 | return NULL; |
588 | } | |
c27a02cd YP |
589 | skb_reserve(skb, NET_IP_ALIGN); |
590 | skb->len = length; | |
c27a02cd YP |
591 | |
592 | /* Get pointer to first fragment so we could copy the headers into the | |
593 | * (linear part of the) skb */ | |
70fbe079 | 594 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
595 | |
596 | if (length <= SMALL_PACKET_SIZE) { | |
597 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 598 | * sync buffers for the copy */ |
c27a02cd | 599 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 600 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 601 | DMA_FROM_DEVICE); |
c27a02cd | 602 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
603 | skb->tail += length; |
604 | } else { | |
cfecec56 ED |
605 | unsigned int pull_len; |
606 | ||
c27a02cd | 607 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
608 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
609 | skb, length); | |
785a0982 YP |
610 | if (unlikely(!used_frags)) { |
611 | kfree_skb(skb); | |
612 | return NULL; | |
613 | } | |
c27a02cd YP |
614 | skb_shinfo(skb)->nr_frags = used_frags; |
615 | ||
cfecec56 | 616 | pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); |
c27a02cd | 617 | /* Copy headers into the skb linear buffer */ |
cfecec56 ED |
618 | memcpy(skb->data, va, pull_len); |
619 | skb->tail += pull_len; | |
c27a02cd YP |
620 | |
621 | /* Skip headers in first fragment */ | |
cfecec56 | 622 | skb_shinfo(skb)->frags[0].page_offset += pull_len; |
c27a02cd YP |
623 | |
624 | /* Adjust size of first fragment */ | |
cfecec56 ED |
625 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); |
626 | skb->data_len = length - pull_len; | |
c27a02cd YP |
627 | } |
628 | return skb; | |
629 | } | |
630 | ||
e7c1c2c4 YP |
631 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
632 | { | |
633 | int i; | |
634 | int offset = ETH_HLEN; | |
635 | ||
636 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
637 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
638 | goto out_loopback; | |
639 | } | |
640 | /* Loopback found */ | |
641 | priv->loopback_ok = 1; | |
642 | ||
643 | out_loopback: | |
644 | dev_kfree_skb_any(skb); | |
645 | } | |
c27a02cd | 646 | |
4cce66cd TLSC |
647 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
648 | struct mlx4_en_rx_ring *ring) | |
649 | { | |
650 | int index = ring->prod & ring->size_mask; | |
651 | ||
652 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
1ab25f86 IS |
653 | if (mlx4_en_prepare_rx_desc(priv, ring, index, |
654 | GFP_ATOMIC | __GFP_COLD)) | |
4cce66cd TLSC |
655 | break; |
656 | ring->prod++; | |
657 | index = ring->prod & ring->size_mask; | |
658 | } | |
659 | } | |
660 | ||
f8c6455b SM |
661 | /* When hardware doesn't strip the vlan, we need to calculate the checksum |
662 | * over it and add it to the hardware's checksum calculation | |
663 | */ | |
664 | static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, | |
665 | struct vlan_hdr *vlanh) | |
666 | { | |
667 | return csum_add(hw_checksum, *(__wsum *)vlanh); | |
668 | } | |
669 | ||
670 | /* Although the stack expects checksum which doesn't include the pseudo | |
671 | * header, the HW adds it. To address that, we are subtracting the pseudo | |
672 | * header checksum from the checksum value provided by the HW. | |
673 | */ | |
674 | static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, | |
675 | struct iphdr *iph) | |
676 | { | |
677 | __u16 length_for_csum = 0; | |
678 | __wsum csum_pseudo_header = 0; | |
679 | ||
680 | length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); | |
681 | csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, | |
682 | length_for_csum, iph->protocol, 0); | |
683 | skb->csum = csum_sub(hw_checksum, csum_pseudo_header); | |
684 | } | |
685 | ||
686 | #if IS_ENABLED(CONFIG_IPV6) | |
687 | /* In IPv6 packets, besides subtracting the pseudo header checksum, | |
688 | * we also compute/add the IP header checksum which | |
689 | * is not added by the HW. | |
690 | */ | |
691 | static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, | |
692 | struct ipv6hdr *ipv6h) | |
693 | { | |
694 | __wsum csum_pseudo_hdr = 0; | |
695 | ||
696 | if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS) | |
697 | return -1; | |
82d69203 | 698 | hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr)); |
f8c6455b SM |
699 | |
700 | csum_pseudo_hdr = csum_partial(&ipv6h->saddr, | |
701 | sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); | |
702 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); | |
703 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); | |
704 | ||
705 | skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); | |
706 | skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); | |
707 | return 0; | |
708 | } | |
709 | #endif | |
710 | static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, | |
79a25852 | 711 | netdev_features_t dev_features) |
f8c6455b SM |
712 | { |
713 | __wsum hw_checksum = 0; | |
714 | ||
715 | void *hdr = (u8 *)va + sizeof(struct ethhdr); | |
716 | ||
717 | hw_checksum = csum_unfold((__force __sum16)cqe->checksum); | |
718 | ||
e802f8e4 | 719 | if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && |
79a25852 | 720 | !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { |
f8c6455b SM |
721 | hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); |
722 | hdr += sizeof(struct vlan_hdr); | |
723 | } | |
724 | ||
725 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) | |
726 | get_fixed_ipv4_csum(hw_checksum, skb, hdr); | |
727 | #if IS_ENABLED(CONFIG_IPV6) | |
728 | else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) | |
729 | if (get_fixed_ipv6_csum(hw_checksum, skb, hdr)) | |
730 | return -1; | |
731 | #endif | |
732 | return 0; | |
733 | } | |
734 | ||
c27a02cd YP |
735 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
736 | { | |
737 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 738 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 739 | struct mlx4_cqe *cqe; |
41d942d5 | 740 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 741 | struct mlx4_en_rx_alloc *frags; |
c27a02cd YP |
742 | struct mlx4_en_rx_desc *rx_desc; |
743 | struct sk_buff *skb; | |
744 | int index; | |
745 | int nr; | |
746 | unsigned int length; | |
747 | int polled = 0; | |
748 | int ip_summed; | |
08ff3235 | 749 | int factor = priv->cqe_factor; |
ec693d47 | 750 | u64 timestamp; |
837052d0 | 751 | bool l2_tunnel; |
c27a02cd YP |
752 | |
753 | if (!priv->port_up) | |
754 | return 0; | |
755 | ||
38be0a34 EB |
756 | if (budget <= 0) |
757 | return polled; | |
758 | ||
c27a02cd YP |
759 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
760 | * descriptor offset can be deduced from the CQE index instead of | |
761 | * reading 'cqe->index' */ | |
762 | index = cq->mcq.cons_index & ring->size_mask; | |
b1b6b4da | 763 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
c27a02cd YP |
764 | |
765 | /* Process all completed CQEs */ | |
766 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
767 | cq->mcq.cons_index & cq->size)) { | |
768 | ||
4cce66cd | 769 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
770 | rx_desc = ring->buf + (index << ring->log_stride); |
771 | ||
772 | /* | |
773 | * make sure we read the CQE after we read the ownership bit | |
774 | */ | |
12b3375f | 775 | dma_rmb(); |
c27a02cd YP |
776 | |
777 | /* Drop packet on bad receive or bad checksum */ | |
778 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
779 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
780 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
781 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
782 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
783 | goto next; |
784 | } | |
785 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 786 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
787 | goto next; |
788 | } | |
789 | ||
79aeaccd YB |
790 | /* Check if we need to drop the packet if SRIOV is not enabled |
791 | * and not performing the selftest or flb disabled | |
792 | */ | |
793 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
794 | struct ethhdr *ethh; | |
795 | dma_addr_t dma; | |
79aeaccd YB |
796 | /* Get pointer to first fragment since we haven't |
797 | * skb yet and cast it to ethhdr struct | |
798 | */ | |
799 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
800 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
801 | DMA_FROM_DEVICE); | |
802 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 803 | frags[0].page_offset); |
79aeaccd | 804 | |
c07cb4b0 YB |
805 | if (is_multicast_ether_addr(ethh->h_dest)) { |
806 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
807 | struct hlist_head *bucket; |
808 | unsigned int mac_hash; | |
809 | ||
810 | /* Drop the packet, since HW loopback-ed it */ | |
811 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
812 | bucket = &priv->mac_hash[mac_hash]; | |
813 | rcu_read_lock(); | |
b67bfe0d | 814 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 YB |
815 | if (ether_addr_equal_64bits(entry->mac, |
816 | ethh->h_source)) { | |
817 | rcu_read_unlock(); | |
818 | goto next; | |
819 | } | |
820 | } | |
821 | rcu_read_unlock(); | |
822 | } | |
79aeaccd | 823 | } |
5b4c4d36 | 824 | |
c27a02cd YP |
825 | /* |
826 | * Packet is OK - process it. | |
827 | */ | |
828 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 829 | length -= ring->fcs_del; |
c27a02cd YP |
830 | ring->bytes += length; |
831 | ring->packets++; | |
837052d0 OG |
832 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
833 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 834 | |
c8c64cff | 835 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
f8c6455b SM |
836 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | |
837 | MLX4_CQE_STATUS_UDP)) { | |
838 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
839 | cqe->checksum == cpu_to_be16(0xffff)) { | |
840 | ip_summed = CHECKSUM_UNNECESSARY; | |
841 | ring->csum_ok++; | |
842 | } else { | |
843 | ip_summed = CHECKSUM_NONE; | |
844 | ring->csum_none++; | |
845 | } | |
c27a02cd | 846 | } else { |
f8c6455b SM |
847 | if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && |
848 | (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
849 | MLX4_CQE_STATUS_IPV6))) { | |
850 | ip_summed = CHECKSUM_COMPLETE; | |
851 | ring->csum_complete++; | |
852 | } else { | |
853 | ip_summed = CHECKSUM_NONE; | |
854 | ring->csum_none++; | |
855 | } | |
c27a02cd YP |
856 | } |
857 | } else { | |
858 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 859 | ring->csum_none++; |
c27a02cd YP |
860 | } |
861 | ||
dd65beac SM |
862 | /* This packet is eligible for GRO if it is: |
863 | * - DIX Ethernet (type interpretation) | |
864 | * - TCP/IP (v4) | |
865 | * - without IP options | |
866 | * - not an IP fragment | |
dd65beac | 867 | */ |
868fdb06 | 868 | if (dev->features & NETIF_F_GRO) { |
dd65beac SM |
869 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); |
870 | if (!gro_skb) | |
871 | goto next; | |
872 | ||
873 | nr = mlx4_en_complete_rx_desc(priv, | |
874 | rx_desc, frags, gro_skb, | |
875 | length); | |
876 | if (!nr) | |
877 | goto next; | |
878 | ||
f8c6455b SM |
879 | if (ip_summed == CHECKSUM_COMPLETE) { |
880 | void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); | |
79a25852 IS |
881 | if (check_csum(cqe, gro_skb, va, |
882 | dev->features)) { | |
f8c6455b SM |
883 | ip_summed = CHECKSUM_NONE; |
884 | ring->csum_none++; | |
885 | ring->csum_complete--; | |
886 | } | |
887 | } | |
888 | ||
dd65beac SM |
889 | skb_shinfo(gro_skb)->nr_frags = nr; |
890 | gro_skb->len = length; | |
891 | gro_skb->data_len = length; | |
892 | gro_skb->ip_summed = ip_summed; | |
893 | ||
894 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) | |
c58942f2 OG |
895 | gro_skb->csum_level = 1; |
896 | ||
dd65beac | 897 | if ((cqe->vlan_my_qpn & |
e802f8e4 | 898 | cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && |
dd65beac SM |
899 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { |
900 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
901 | ||
902 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); | |
e38af4fa HHZ |
903 | } else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
904 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
905 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) { | |
906 | __vlan_hwaccel_put_tag(gro_skb, | |
907 | htons(ETH_P_8021AD), | |
908 | be16_to_cpu(cqe->sl_vid)); | |
dd65beac SM |
909 | } |
910 | ||
911 | if (dev->features & NETIF_F_RXHASH) | |
912 | skb_set_hash(gro_skb, | |
913 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
914 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
915 | PKT_HASH_TYPE_L4 : | |
916 | PKT_HASH_TYPE_L3); | |
dd65beac SM |
917 | |
918 | skb_record_rx_queue(gro_skb, cq->ring); | |
dd65beac SM |
919 | |
920 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { | |
921 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
922 | mlx4_en_fill_hwtstamps(mdev, | |
923 | skb_hwtstamps(gro_skb), | |
924 | timestamp); | |
925 | } | |
926 | ||
927 | napi_gro_frags(&cq->napi); | |
928 | goto next; | |
929 | } | |
930 | ||
931 | /* GRO not possible, complete processing here */ | |
4cce66cd | 932 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd | 933 | if (!skb) { |
d21ed3a3 | 934 | ring->dropped++; |
c27a02cd YP |
935 | goto next; |
936 | } | |
937 | ||
e7c1c2c4 YP |
938 | if (unlikely(priv->validate_loopback)) { |
939 | validate_loopback(priv, skb); | |
940 | goto next; | |
941 | } | |
942 | ||
f8c6455b | 943 | if (ip_summed == CHECKSUM_COMPLETE) { |
79a25852 | 944 | if (check_csum(cqe, skb, skb->data, dev->features)) { |
f8c6455b SM |
945 | ip_summed = CHECKSUM_NONE; |
946 | ring->csum_complete--; | |
947 | ring->csum_none++; | |
948 | } | |
949 | } | |
950 | ||
c27a02cd YP |
951 | skb->ip_summed = ip_summed; |
952 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 953 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 954 | |
9ca8600e TH |
955 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) |
956 | skb->csum_level = 1; | |
837052d0 | 957 | |
ad86107f | 958 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
959 | skb_set_hash(skb, |
960 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
961 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
962 | PKT_HASH_TYPE_L4 : | |
963 | PKT_HASH_TYPE_L3); | |
ad86107f | 964 | |
ec693d47 | 965 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
e802f8e4 | 966 | MLX4_CQE_CVLAN_PRESENT_MASK) && |
ec693d47 | 967 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) |
86a9bad3 | 968 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
e38af4fa HHZ |
969 | else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
970 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
971 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) | |
972 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), | |
973 | be16_to_cpu(cqe->sl_vid)); | |
f1b553fb | 974 | |
ec693d47 AV |
975 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
976 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
977 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
978 | timestamp); | |
979 | } | |
980 | ||
868fdb06 | 981 | napi_gro_receive(&cq->napi, skb); |
c27a02cd | 982 | next: |
4cce66cd TLSC |
983 | for (nr = 0; nr < priv->num_frags; nr++) |
984 | mlx4_en_free_frag(priv, frags, nr); | |
985 | ||
c27a02cd YP |
986 | ++cq->mcq.cons_index; |
987 | index = (cq->mcq.cons_index) & ring->size_mask; | |
b1b6b4da | 988 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
f1d29a3f | 989 | if (++polled == budget) |
c27a02cd | 990 | goto out; |
c27a02cd YP |
991 | } |
992 | ||
c27a02cd YP |
993 | out: |
994 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
995 | mlx4_cq_set_ci(&cq->mcq); | |
996 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
997 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 998 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
999 | mlx4_en_update_rx_prod_db(ring); |
1000 | return polled; | |
1001 | } | |
1002 | ||
1003 | ||
1004 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
1005 | { | |
1006 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
1007 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
1008 | ||
477b35b4 ED |
1009 | if (likely(priv->port_up)) |
1010 | napi_schedule_irqoff(&cq->napi); | |
c27a02cd YP |
1011 | else |
1012 | mlx4_en_arm_cq(priv, cq); | |
1013 | } | |
1014 | ||
1015 | /* Rx CQ polling - called by NAPI */ | |
1016 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
1017 | { | |
1018 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
1019 | struct net_device *dev = cq->dev; | |
1020 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1021 | int done; | |
1022 | ||
1023 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
1024 | ||
1025 | /* If we used up all the quota - we're probably not done yet... */ | |
2eacc23c | 1026 | if (done == budget) { |
35f6f453 | 1027 | const struct cpumask *aff; |
dc2ec62f TG |
1028 | struct irq_data *idata; |
1029 | int cpu_curr; | |
35f6f453 | 1030 | |
c27a02cd | 1031 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
1032 | |
1033 | cpu_curr = smp_processor_id(); | |
dc2ec62f TG |
1034 | idata = irq_desc_get_irq_data(cq->irq_desc); |
1035 | aff = irq_data_get_affinity_mask(idata); | |
35f6f453 | 1036 | |
2e1af7d7 ED |
1037 | if (likely(cpumask_test_cpu(cpu_curr, aff))) |
1038 | return budget; | |
1039 | ||
1040 | /* Current cpu is not according to smp_irq_affinity - | |
1041 | * probably affinity changed. need to stop this NAPI | |
1042 | * poll, and restart it on the right CPU | |
1043 | */ | |
1044 | done = 0; | |
c27a02cd | 1045 | } |
1a288172 ED |
1046 | /* Done for now */ |
1047 | napi_complete_done(napi, done); | |
1048 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
1049 | return done; |
1050 | } | |
1051 | ||
51151a16 | 1052 | static const int frag_sizes[] = { |
c27a02cd YP |
1053 | FRAG_SZ0, |
1054 | FRAG_SZ1, | |
1055 | FRAG_SZ2, | |
1056 | FRAG_SZ3 | |
1057 | }; | |
1058 | ||
1059 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
1060 | { | |
1061 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
e38af4fa HHZ |
1062 | /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple |
1063 | * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). | |
1064 | */ | |
1065 | int eff_mtu = dev->mtu + ETH_HLEN + (2 * VLAN_HLEN); | |
c27a02cd YP |
1066 | int buf_size = 0; |
1067 | int i = 0; | |
1068 | ||
1069 | while (buf_size < eff_mtu) { | |
1070 | priv->frag_info[i].frag_size = | |
1071 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
1072 | frag_sizes[i] : eff_mtu - buf_size; | |
1073 | priv->frag_info[i].frag_prefix_size = buf_size; | |
e8e7f018 IS |
1074 | priv->frag_info[i].frag_stride = |
1075 | ALIGN(priv->frag_info[i].frag_size, | |
1076 | SMP_CACHE_BYTES); | |
c27a02cd YP |
1077 | buf_size += priv->frag_info[i].frag_size; |
1078 | i++; | |
1079 | } | |
1080 | ||
1081 | priv->num_frags = i; | |
1082 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 1083 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 1084 | |
1a91de28 JP |
1085 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
1086 | eff_mtu, priv->num_frags); | |
c27a02cd | 1087 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 | 1088 | en_err(priv, |
5f6e9800 | 1089 | " frag:%d - size:%d prefix:%d stride:%d\n", |
51151a16 ED |
1090 | i, |
1091 | priv->frag_info[i].frag_size, | |
1092 | priv->frag_info[i].frag_prefix_size, | |
51151a16 | 1093 | priv->frag_info[i].frag_stride); |
c27a02cd YP |
1094 | } |
1095 | } | |
1096 | ||
1097 | /* RSS related functions */ | |
1098 | ||
9f519f68 YP |
1099 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
1100 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
1101 | enum mlx4_qp_state *state, |
1102 | struct mlx4_qp *qp) | |
1103 | { | |
1104 | struct mlx4_en_dev *mdev = priv->mdev; | |
1105 | struct mlx4_qp_context *context; | |
1106 | int err = 0; | |
1107 | ||
14f8dc49 JP |
1108 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
1109 | if (!context) | |
c27a02cd | 1110 | return -ENOMEM; |
c27a02cd | 1111 | |
40f2287b | 1112 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 1113 | if (err) { |
453a6082 | 1114 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 1115 | goto out; |
c27a02cd YP |
1116 | } |
1117 | qp->event = mlx4_en_sqp_event; | |
1118 | ||
1119 | memset(context, 0, sizeof *context); | |
00d7d7bc | 1120 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 1121 | qpn, ring->cqn, -1, context); |
9f519f68 | 1122 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1123 | |
f3a9d1f2 | 1124 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1125 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1126 | context->param3 |= cpu_to_be32(1 << 29); |
f0df3503 MM |
1127 | if (priv->dev->features & NETIF_F_RXFCS) |
1128 | ring->fcs_del = 0; | |
1129 | else | |
1130 | ring->fcs_del = ETH_FCS_LEN; | |
4a5f4dd8 YP |
1131 | } else |
1132 | ring->fcs_del = 0; | |
f3a9d1f2 | 1133 | |
9f519f68 | 1134 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1135 | if (err) { |
1136 | mlx4_qp_remove(mdev->dev, qp); | |
1137 | mlx4_qp_free(mdev->dev, qp); | |
1138 | } | |
9f519f68 | 1139 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1140 | out: |
1141 | kfree(context); | |
1142 | return err; | |
1143 | } | |
1144 | ||
cabdc8ee HHZ |
1145 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1146 | { | |
1147 | int err; | |
1148 | u32 qpn; | |
1149 | ||
d57febe1 MB |
1150 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, |
1151 | MLX4_RESERVE_A0_QP); | |
cabdc8ee HHZ |
1152 | if (err) { |
1153 | en_err(priv, "Failed reserving drop qpn\n"); | |
1154 | return err; | |
1155 | } | |
40f2287b | 1156 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1157 | if (err) { |
1158 | en_err(priv, "Failed allocating drop qp\n"); | |
1159 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1160 | return err; | |
1161 | } | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1167 | { | |
1168 | u32 qpn; | |
1169 | ||
1170 | qpn = priv->drop_qp.qpn; | |
1171 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1172 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1173 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1174 | } | |
1175 | ||
c27a02cd YP |
1176 | /* Allocate rx qp's and configure them according to rss map */ |
1177 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1178 | { | |
1179 | struct mlx4_en_dev *mdev = priv->mdev; | |
1180 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1181 | struct mlx4_qp_context context; | |
876f6e67 | 1182 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1183 | int rss_rings; |
c27a02cd | 1184 | void *ptr; |
876f6e67 | 1185 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1186 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1187 | int i, qpn; |
c27a02cd YP |
1188 | int err = 0; |
1189 | int good_qps = 0; | |
1190 | ||
453a6082 | 1191 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1192 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1193 | priv->rx_ring_num, | |
ddae0349 | 1194 | &rss_map->base_qpn, 0); |
c27a02cd | 1195 | if (err) { |
b6b912e0 | 1196 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1197 | return err; |
1198 | } | |
1199 | ||
b6b912e0 | 1200 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1201 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1202 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1203 | &rss_map->state[i], |
1204 | &rss_map->qps[i]); | |
1205 | if (err) | |
1206 | goto rss_err; | |
1207 | ||
1208 | ++good_qps; | |
1209 | } | |
1210 | ||
1211 | /* Configure RSS indirection qp */ | |
40f2287b | 1212 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1213 | if (err) { |
453a6082 | 1214 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1215 | goto rss_err; |
c27a02cd YP |
1216 | } |
1217 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1218 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1219 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1220 | |
93d3e367 YP |
1221 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1222 | rss_rings = priv->rx_ring_num; | |
1223 | else | |
1224 | rss_rings = priv->prof->rss_rings; | |
1225 | ||
876f6e67 OG |
1226 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1227 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1228 | rss_context = ptr; |
93d3e367 | 1229 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1230 | (rss_map->base_qpn)); |
89efea25 | 1231 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1232 | if (priv->mdev->profile.udp_rss) { |
1233 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1234 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1235 | } | |
837052d0 OG |
1236 | |
1237 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1238 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1239 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1240 | } | |
1241 | ||
0533943c | 1242 | rss_context->flags = rss_mask; |
876f6e67 | 1243 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
947cbb0a EP |
1244 | if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { |
1245 | rss_context->hash_fn = MLX4_RSS_HASH_XOR; | |
1246 | } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { | |
1247 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; | |
1248 | memcpy(rss_context->rss_key, priv->rss_key, | |
1249 | MLX4_EN_RSS_KEY_SIZE); | |
947cbb0a EP |
1250 | } else { |
1251 | en_err(priv, "Unknown RSS hash function requested\n"); | |
1252 | err = -EINVAL; | |
1253 | goto indir_err; | |
1254 | } | |
c27a02cd YP |
1255 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, |
1256 | &rss_map->indir_qp, &rss_map->indir_state); | |
1257 | if (err) | |
1258 | goto indir_err; | |
1259 | ||
1260 | return 0; | |
1261 | ||
1262 | indir_err: | |
1263 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1264 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1265 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1266 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1267 | rss_err: |
1268 | for (i = 0; i < good_qps; i++) { | |
1269 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1270 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1271 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1272 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1273 | } | |
b6b912e0 | 1274 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1275 | return err; |
1276 | } | |
1277 | ||
1278 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1279 | { | |
1280 | struct mlx4_en_dev *mdev = priv->mdev; | |
1281 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1282 | int i; | |
1283 | ||
1284 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1285 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1286 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1287 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1288 | |
b6b912e0 | 1289 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1290 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1291 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1292 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1293 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1294 | } | |
b6b912e0 | 1295 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1296 | } |