Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
c27a02cd YP |
36 | #include <linux/mlx4/qp.h> |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/vmalloc.h> | |
41 | ||
42 | #include "mlx4_en.h" | |
43 | ||
c27a02cd | 44 | |
c27a02cd YP |
45 | static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv, |
46 | struct mlx4_en_rx_desc *rx_desc, | |
311761c8 | 47 | struct page_frag *skb_frags, |
c27a02cd YP |
48 | struct mlx4_en_rx_alloc *ring_alloc, |
49 | int i) | |
50 | { | |
51 | struct mlx4_en_dev *mdev = priv->mdev; | |
52 | struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; | |
53 | struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i]; | |
54 | struct page *page; | |
55 | dma_addr_t dma; | |
56 | ||
57 | if (page_alloc->offset == frag_info->last_offset) { | |
58 | /* Allocate new page */ | |
59 | page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER); | |
60 | if (!page) | |
61 | return -ENOMEM; | |
62 | ||
63 | skb_frags[i].page = page_alloc->page; | |
311761c8 | 64 | skb_frags[i].offset = page_alloc->offset; |
c27a02cd YP |
65 | page_alloc->page = page; |
66 | page_alloc->offset = frag_info->frag_align; | |
67 | } else { | |
68 | page = page_alloc->page; | |
69 | get_page(page); | |
70 | ||
71 | skb_frags[i].page = page; | |
311761c8 | 72 | skb_frags[i].offset = page_alloc->offset; |
c27a02cd YP |
73 | page_alloc->offset += frag_info->frag_stride; |
74 | } | |
75 | dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) + | |
311761c8 | 76 | skb_frags[i].offset, frag_info->frag_size, |
c27a02cd YP |
77 | PCI_DMA_FROMDEVICE); |
78 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
79 | return 0; | |
80 | } | |
81 | ||
82 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
83 | struct mlx4_en_rx_ring *ring) | |
84 | { | |
85 | struct mlx4_en_rx_alloc *page_alloc; | |
86 | int i; | |
87 | ||
88 | for (i = 0; i < priv->num_frags; i++) { | |
89 | page_alloc = &ring->page_alloc[i]; | |
90 | page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP, | |
91 | MLX4_EN_ALLOC_ORDER); | |
92 | if (!page_alloc->page) | |
93 | goto out; | |
94 | ||
95 | page_alloc->offset = priv->frag_info[i].frag_align; | |
453a6082 YP |
96 | en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n", |
97 | i, page_alloc->page); | |
c27a02cd YP |
98 | } |
99 | return 0; | |
100 | ||
101 | out: | |
102 | while (i--) { | |
103 | page_alloc = &ring->page_alloc[i]; | |
104 | put_page(page_alloc->page); | |
105 | page_alloc->page = NULL; | |
106 | } | |
107 | return -ENOMEM; | |
108 | } | |
109 | ||
110 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
111 | struct mlx4_en_rx_ring *ring) | |
112 | { | |
113 | struct mlx4_en_rx_alloc *page_alloc; | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < priv->num_frags; i++) { | |
117 | page_alloc = &ring->page_alloc[i]; | |
453a6082 YP |
118 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
119 | i, page_count(page_alloc->page)); | |
c27a02cd YP |
120 | |
121 | put_page(page_alloc->page); | |
122 | page_alloc->page = NULL; | |
123 | } | |
124 | } | |
125 | ||
126 | ||
127 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, | |
128 | struct mlx4_en_rx_ring *ring, int index) | |
129 | { | |
130 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
131 | struct skb_frag_struct *skb_frags = ring->rx_info + | |
132 | (index << priv->log_rx_info); | |
133 | int possible_frags; | |
134 | int i; | |
135 | ||
c27a02cd YP |
136 | /* Set size and memtype fields */ |
137 | for (i = 0; i < priv->num_frags; i++) { | |
9e903e08 | 138 | skb_frag_size_set(&skb_frags[i], priv->frag_info[i].frag_size); |
c27a02cd YP |
139 | rx_desc->data[i].byte_count = |
140 | cpu_to_be32(priv->frag_info[i].frag_size); | |
141 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
142 | } | |
143 | ||
144 | /* If the number of used fragments does not fill up the ring stride, | |
145 | * remaining (unused) fragments must be padded with null address/size | |
146 | * and a special memory key */ | |
147 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
148 | for (i = priv->num_frags; i < possible_frags; i++) { | |
149 | rx_desc->data[i].byte_count = 0; | |
150 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
151 | rx_desc->data[i].addr = 0; | |
152 | } | |
153 | } | |
154 | ||
155 | ||
156 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, | |
157 | struct mlx4_en_rx_ring *ring, int index) | |
158 | { | |
159 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
311761c8 IC |
160 | struct page_frag *skb_frags = ring->rx_info + |
161 | (index << priv->log_rx_info); | |
c27a02cd YP |
162 | int i; |
163 | ||
164 | for (i = 0; i < priv->num_frags; i++) | |
165 | if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i)) | |
166 | goto err; | |
167 | ||
168 | return 0; | |
169 | ||
170 | err: | |
7e2eb99c TLSC |
171 | while (i--) { |
172 | dma_addr_t dma = be64_to_cpu(rx_desc->data[i].addr); | |
173 | pci_unmap_single(priv->mdev->pdev, dma, skb_frags[i].size, | |
174 | PCI_DMA_FROMDEVICE); | |
c27a02cd | 175 | put_page(skb_frags[i].page); |
7e2eb99c | 176 | } |
c27a02cd YP |
177 | return -ENOMEM; |
178 | } | |
179 | ||
180 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
181 | { | |
182 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
183 | } | |
184 | ||
38aab07c YP |
185 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
186 | struct mlx4_en_rx_ring *ring, | |
187 | int index) | |
188 | { | |
189 | struct mlx4_en_dev *mdev = priv->mdev; | |
311761c8 | 190 | struct page_frag *skb_frags; |
38aab07c YP |
191 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride); |
192 | dma_addr_t dma; | |
193 | int nr; | |
194 | ||
195 | skb_frags = ring->rx_info + (index << priv->log_rx_info); | |
196 | for (nr = 0; nr < priv->num_frags; nr++) { | |
453a6082 | 197 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
38aab07c YP |
198 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
199 | ||
af901ca1 | 200 | en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma); |
311761c8 | 201 | pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size, |
38aab07c YP |
202 | PCI_DMA_FROMDEVICE); |
203 | put_page(skb_frags[nr].page); | |
204 | } | |
205 | } | |
206 | ||
c27a02cd YP |
207 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
208 | { | |
c27a02cd YP |
209 | struct mlx4_en_rx_ring *ring; |
210 | int ring_ind; | |
211 | int buf_ind; | |
38aab07c | 212 | int new_size; |
c27a02cd YP |
213 | |
214 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
215 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
216 | ring = &priv->rx_ring[ring_ind]; | |
217 | ||
218 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
219 | ring->actual_size)) { | |
220 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { | |
453a6082 YP |
221 | en_err(priv, "Failed to allocate " |
222 | "enough rx buffers\n"); | |
c27a02cd YP |
223 | return -ENOMEM; |
224 | } else { | |
38aab07c | 225 | new_size = rounddown_pow_of_two(ring->actual_size); |
453a6082 YP |
226 | en_warn(priv, "Only %d buffers allocated " |
227 | "reducing ring size to %d", | |
228 | ring->actual_size, new_size); | |
38aab07c | 229 | goto reduce_rings; |
c27a02cd YP |
230 | } |
231 | } | |
232 | ring->actual_size++; | |
233 | ring->prod++; | |
234 | } | |
235 | } | |
38aab07c YP |
236 | return 0; |
237 | ||
238 | reduce_rings: | |
239 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
240 | ring = &priv->rx_ring[ring_ind]; | |
241 | while (ring->actual_size > new_size) { | |
242 | ring->actual_size--; | |
243 | ring->prod--; | |
244 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
245 | } | |
38aab07c YP |
246 | } |
247 | ||
c27a02cd YP |
248 | return 0; |
249 | } | |
250 | ||
c27a02cd YP |
251 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
252 | struct mlx4_en_rx_ring *ring) | |
253 | { | |
c27a02cd | 254 | int index; |
c27a02cd | 255 | |
453a6082 YP |
256 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
257 | ring->cons, ring->prod); | |
c27a02cd YP |
258 | |
259 | /* Unmap and free Rx buffers */ | |
38aab07c | 260 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
261 | while (ring->cons != ring->prod) { |
262 | index = ring->cons & ring->size_mask; | |
453a6082 | 263 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 264 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
265 | ++ring->cons; |
266 | } | |
267 | } | |
268 | ||
c27a02cd YP |
269 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
270 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) | |
271 | { | |
272 | struct mlx4_en_dev *mdev = priv->mdev; | |
273 | int err; | |
274 | int tmp; | |
275 | ||
c27a02cd YP |
276 | |
277 | ring->prod = 0; | |
278 | ring->cons = 0; | |
279 | ring->size = size; | |
280 | ring->size_mask = size - 1; | |
281 | ring->stride = stride; | |
282 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 283 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
284 | |
285 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
286 | sizeof(struct skb_frag_struct)); | |
287 | ring->rx_info = vmalloc(tmp); | |
e404decb | 288 | if (!ring->rx_info) |
c27a02cd | 289 | return -ENOMEM; |
e404decb | 290 | |
453a6082 | 291 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
292 | ring->rx_info, tmp); |
293 | ||
294 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, | |
295 | ring->buf_size, 2 * PAGE_SIZE); | |
296 | if (err) | |
297 | goto err_ring; | |
298 | ||
299 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
300 | if (err) { | |
453a6082 | 301 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
302 | goto err_hwq; |
303 | } | |
304 | ring->buf = ring->wqres.buf.direct.buf; | |
305 | ||
c27a02cd YP |
306 | return 0; |
307 | ||
c27a02cd YP |
308 | err_hwq: |
309 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
310 | err_ring: | |
311 | vfree(ring->rx_info); | |
312 | ring->rx_info = NULL; | |
313 | return err; | |
314 | } | |
315 | ||
316 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
317 | { | |
c27a02cd YP |
318 | struct mlx4_en_rx_ring *ring; |
319 | int i; | |
320 | int ring_ind; | |
321 | int err; | |
322 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
323 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
324 | |
325 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
326 | ring = &priv->rx_ring[ring_ind]; | |
327 | ||
328 | ring->prod = 0; | |
329 | ring->cons = 0; | |
330 | ring->actual_size = 0; | |
331 | ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; | |
332 | ||
333 | ring->stride = stride; | |
9f519f68 YP |
334 | if (ring->stride <= TXBB_SIZE) |
335 | ring->buf += TXBB_SIZE; | |
336 | ||
c27a02cd YP |
337 | ring->log_stride = ffs(ring->stride) - 1; |
338 | ring->buf_size = ring->size * ring->stride; | |
339 | ||
340 | memset(ring->buf, 0, ring->buf_size); | |
341 | mlx4_en_update_rx_prod_db(ring); | |
342 | ||
343 | /* Initailize all descriptors */ | |
344 | for (i = 0; i < ring->size; i++) | |
345 | mlx4_en_init_rx_desc(priv, ring, i); | |
346 | ||
347 | /* Initialize page allocators */ | |
348 | err = mlx4_en_init_allocator(priv, ring); | |
349 | if (err) { | |
453a6082 | 350 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
351 | if (ring->stride <= TXBB_SIZE) |
352 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
353 | ring_ind--; |
354 | goto err_allocator; | |
c27a02cd | 355 | } |
c27a02cd | 356 | } |
b58515be IM |
357 | err = mlx4_en_fill_rx_buffers(priv); |
358 | if (err) | |
c27a02cd YP |
359 | goto err_buffers; |
360 | ||
361 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
362 | ring = &priv->rx_ring[ring_ind]; | |
363 | ||
00d7d7bc | 364 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 365 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
366 | } |
367 | ||
368 | return 0; | |
369 | ||
c27a02cd YP |
370 | err_buffers: |
371 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
372 | mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); | |
373 | ||
374 | ring_ind = priv->rx_ring_num - 1; | |
375 | err_allocator: | |
376 | while (ring_ind >= 0) { | |
60b1809f YP |
377 | if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE) |
378 | priv->rx_ring[ring_ind].buf -= TXBB_SIZE; | |
c27a02cd YP |
379 | mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); |
380 | ring_ind--; | |
381 | } | |
382 | return err; | |
383 | } | |
384 | ||
385 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
68355f71 | 386 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) |
c27a02cd YP |
387 | { |
388 | struct mlx4_en_dev *mdev = priv->mdev; | |
389 | ||
c27a02cd | 390 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
68355f71 | 391 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
392 | vfree(ring->rx_info); |
393 | ring->rx_info = NULL; | |
394 | } | |
395 | ||
396 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
397 | struct mlx4_en_rx_ring *ring) | |
398 | { | |
c27a02cd | 399 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
400 | if (ring->stride <= TXBB_SIZE) |
401 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
402 | mlx4_en_destroy_allocator(priv, ring); |
403 | } | |
404 | ||
405 | ||
406 | /* Unmap a completed descriptor and free unused pages */ | |
407 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, | |
408 | struct mlx4_en_rx_desc *rx_desc, | |
311761c8 | 409 | struct page_frag *skb_frags, |
90278c9f | 410 | struct sk_buff *skb, |
c27a02cd YP |
411 | struct mlx4_en_rx_alloc *page_alloc, |
412 | int length) | |
413 | { | |
90278c9f | 414 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
415 | struct mlx4_en_dev *mdev = priv->mdev; |
416 | struct mlx4_en_frag_info *frag_info; | |
417 | int nr; | |
418 | dma_addr_t dma; | |
419 | ||
420 | /* Collect used fragments while replacing them in the HW descirptors */ | |
421 | for (nr = 0; nr < priv->num_frags; nr++) { | |
422 | frag_info = &priv->frag_info[nr]; | |
423 | if (length <= frag_info->frag_prefix_size) | |
424 | break; | |
425 | ||
426 | /* Save page reference in skb */ | |
311761c8 IC |
427 | __skb_frag_set_page(&skb_frags_rx[nr], skb_frags[nr].page); |
428 | skb_frag_size_set(&skb_frags_rx[nr], skb_frags[nr].size); | |
429 | skb_frags_rx[nr].page_offset = skb_frags[nr].offset; | |
90278c9f | 430 | skb->truesize += frag_info->frag_stride; |
c27a02cd YP |
431 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
432 | ||
433 | /* Allocate a replacement page */ | |
434 | if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr)) | |
435 | goto fail; | |
436 | ||
437 | /* Unmap buffer */ | |
9e903e08 | 438 | pci_unmap_single(mdev->pdev, dma, skb_frag_size(&skb_frags_rx[nr]), |
c27a02cd YP |
439 | PCI_DMA_FROMDEVICE); |
440 | } | |
441 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 442 | if (nr > 0) |
9e903e08 ED |
443 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
444 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
445 | return nr; |
446 | ||
447 | fail: | |
448 | /* Drop all accumulated fragments (which have already been replaced in | |
449 | * the descriptor) of this packet; remaining fragments are reused... */ | |
450 | while (nr > 0) { | |
451 | nr--; | |
311761c8 | 452 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
453 | } |
454 | return 0; | |
455 | } | |
456 | ||
457 | ||
458 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
459 | struct mlx4_en_rx_desc *rx_desc, | |
311761c8 | 460 | struct page_frag *skb_frags, |
c27a02cd YP |
461 | struct mlx4_en_rx_alloc *page_alloc, |
462 | unsigned int length) | |
463 | { | |
464 | struct mlx4_en_dev *mdev = priv->mdev; | |
465 | struct sk_buff *skb; | |
466 | void *va; | |
467 | int used_frags; | |
468 | dma_addr_t dma; | |
469 | ||
c056b734 | 470 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 471 | if (!skb) { |
453a6082 | 472 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
473 | return NULL; |
474 | } | |
c27a02cd YP |
475 | skb_reserve(skb, NET_IP_ALIGN); |
476 | skb->len = length; | |
c27a02cd YP |
477 | |
478 | /* Get pointer to first fragment so we could copy the headers into the | |
479 | * (linear part of the) skb */ | |
311761c8 | 480 | va = page_address(skb_frags[0].page) + skb_frags[0].offset; |
c27a02cd YP |
481 | |
482 | if (length <= SMALL_PACKET_SIZE) { | |
483 | /* We are copying all relevant data to the skb - temporarily | |
484 | * synch buffers for the copy */ | |
485 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
e4fc8560 FT |
486 | dma_sync_single_for_cpu(&mdev->pdev->dev, dma, length, |
487 | DMA_FROM_DEVICE); | |
c27a02cd | 488 | skb_copy_to_linear_data(skb, va, length); |
e4fc8560 FT |
489 | dma_sync_single_for_device(&mdev->pdev->dev, dma, length, |
490 | DMA_FROM_DEVICE); | |
c27a02cd YP |
491 | skb->tail += length; |
492 | } else { | |
493 | ||
494 | /* Move relevant fragments to skb */ | |
495 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags, | |
90278c9f | 496 | skb, page_alloc, length); |
785a0982 YP |
497 | if (unlikely(!used_frags)) { |
498 | kfree_skb(skb); | |
499 | return NULL; | |
500 | } | |
c27a02cd YP |
501 | skb_shinfo(skb)->nr_frags = used_frags; |
502 | ||
503 | /* Copy headers into the skb linear buffer */ | |
504 | memcpy(skb->data, va, HEADER_COPY_SIZE); | |
505 | skb->tail += HEADER_COPY_SIZE; | |
506 | ||
507 | /* Skip headers in first fragment */ | |
508 | skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; | |
509 | ||
510 | /* Adjust size of first fragment */ | |
9e903e08 | 511 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE); |
c27a02cd YP |
512 | skb->data_len = length - HEADER_COPY_SIZE; |
513 | } | |
514 | return skb; | |
515 | } | |
516 | ||
e7c1c2c4 YP |
517 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
518 | { | |
519 | int i; | |
520 | int offset = ETH_HLEN; | |
521 | ||
522 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
523 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
524 | goto out_loopback; | |
525 | } | |
526 | /* Loopback found */ | |
527 | priv->loopback_ok = 1; | |
528 | ||
529 | out_loopback: | |
530 | dev_kfree_skb_any(skb); | |
531 | } | |
c27a02cd YP |
532 | |
533 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) | |
534 | { | |
535 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
536 | struct mlx4_cqe *cqe; |
537 | struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; | |
311761c8 | 538 | struct page_frag *skb_frags; |
c27a02cd YP |
539 | struct mlx4_en_rx_desc *rx_desc; |
540 | struct sk_buff *skb; | |
541 | int index; | |
542 | int nr; | |
543 | unsigned int length; | |
544 | int polled = 0; | |
545 | int ip_summed; | |
5b4c4d36 EE |
546 | struct ethhdr *ethh; |
547 | u64 s_mac; | |
c27a02cd YP |
548 | |
549 | if (!priv->port_up) | |
550 | return 0; | |
551 | ||
552 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx | |
553 | * descriptor offset can be deduced from the CQE index instead of | |
554 | * reading 'cqe->index' */ | |
555 | index = cq->mcq.cons_index & ring->size_mask; | |
556 | cqe = &cq->buf[index]; | |
557 | ||
558 | /* Process all completed CQEs */ | |
559 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
560 | cq->mcq.cons_index & cq->size)) { | |
561 | ||
562 | skb_frags = ring->rx_info + (index << priv->log_rx_info); | |
563 | rx_desc = ring->buf + (index << ring->log_stride); | |
564 | ||
565 | /* | |
566 | * make sure we read the CQE after we read the ownership bit | |
567 | */ | |
568 | rmb(); | |
569 | ||
570 | /* Drop packet on bad receive or bad checksum */ | |
571 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
572 | MLX4_CQE_OPCODE_ERROR)) { | |
453a6082 | 573 | en_err(priv, "CQE completed in error - vendor " |
c27a02cd YP |
574 | "syndrom:%d syndrom:%d\n", |
575 | ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, | |
576 | ((struct mlx4_err_cqe *) cqe)->syndrome); | |
577 | goto next; | |
578 | } | |
579 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 580 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
581 | goto next; |
582 | } | |
583 | ||
5b4c4d36 EE |
584 | /* Get pointer to first fragment since we haven't skb yet and |
585 | * cast it to ethhdr struct */ | |
586 | ethh = (struct ethhdr *)(page_address(skb_frags[0].page) + | |
587 | skb_frags[0].offset); | |
588 | s_mac = mlx4_en_mac_to_u64(ethh->h_source); | |
589 | ||
590 | /* If source MAC is equal to our own MAC and not performing | |
591 | * the selftest or flb disabled - drop the packet */ | |
592 | if (s_mac == priv->mac && | |
593 | (!(dev->features & NETIF_F_LOOPBACK) || | |
594 | !priv->validate_loopback)) | |
595 | goto next; | |
596 | ||
c27a02cd YP |
597 | /* |
598 | * Packet is OK - process it. | |
599 | */ | |
600 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 601 | length -= ring->fcs_del; |
c27a02cd YP |
602 | ring->bytes += length; |
603 | ring->packets++; | |
604 | ||
c8c64cff | 605 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
c27a02cd YP |
606 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && |
607 | (cqe->checksum == cpu_to_be16(0xffff))) { | |
ad04378c | 608 | ring->csum_ok++; |
c27a02cd YP |
609 | /* This packet is eligible for LRO if it is: |
610 | * - DIX Ethernet (type interpretation) | |
611 | * - TCP/IP (v4) | |
612 | * - without IP options | |
613 | * - not an IP fragment */ | |
fa37a958 YP |
614 | if (dev->features & NETIF_F_GRO) { |
615 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); | |
ebc872c7 YP |
616 | if (!gro_skb) |
617 | goto next; | |
c27a02cd YP |
618 | |
619 | nr = mlx4_en_complete_rx_desc( | |
620 | priv, rx_desc, | |
90278c9f | 621 | skb_frags, gro_skb, |
c27a02cd YP |
622 | ring->page_alloc, length); |
623 | if (!nr) | |
624 | goto next; | |
625 | ||
fa37a958 YP |
626 | skb_shinfo(gro_skb)->nr_frags = nr; |
627 | gro_skb->len = length; | |
628 | gro_skb->data_len = length; | |
fa37a958 YP |
629 | gro_skb->ip_summed = CHECKSUM_UNNECESSARY; |
630 | ||
f1b553fb JP |
631 | if (cqe->vlan_my_qpn & |
632 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) { | |
633 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
634 | ||
635 | __vlan_hwaccel_put_tag(gro_skb, vid); | |
636 | } | |
637 | ||
ad86107f YP |
638 | if (dev->features & NETIF_F_RXHASH) |
639 | gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); | |
640 | ||
3b61008d | 641 | skb_record_rx_queue(gro_skb, cq->ring); |
f1b553fb | 642 | napi_gro_frags(&cq->napi); |
c27a02cd YP |
643 | |
644 | goto next; | |
645 | } | |
646 | ||
647 | /* LRO not possible, complete processing here */ | |
648 | ip_summed = CHECKSUM_UNNECESSARY; | |
c27a02cd YP |
649 | } else { |
650 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 651 | ring->csum_none++; |
c27a02cd YP |
652 | } |
653 | } else { | |
654 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 655 | ring->csum_none++; |
c27a02cd YP |
656 | } |
657 | ||
658 | skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags, | |
659 | ring->page_alloc, length); | |
660 | if (!skb) { | |
661 | priv->stats.rx_dropped++; | |
662 | goto next; | |
663 | } | |
664 | ||
e7c1c2c4 YP |
665 | if (unlikely(priv->validate_loopback)) { |
666 | validate_loopback(priv, skb); | |
667 | goto next; | |
668 | } | |
669 | ||
c27a02cd YP |
670 | skb->ip_summed = ip_summed; |
671 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 672 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 673 | |
ad86107f YP |
674 | if (dev->features & NETIF_F_RXHASH) |
675 | skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); | |
676 | ||
f1b553fb JP |
677 | if (be32_to_cpu(cqe->vlan_my_qpn) & |
678 | MLX4_CQE_VLAN_PRESENT_MASK) | |
679 | __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid)); | |
680 | ||
c27a02cd | 681 | /* Push it up the stack */ |
f1b553fb | 682 | netif_receive_skb(skb); |
c27a02cd | 683 | |
c27a02cd YP |
684 | next: |
685 | ++cq->mcq.cons_index; | |
686 | index = (cq->mcq.cons_index) & ring->size_mask; | |
687 | cqe = &cq->buf[index]; | |
688 | if (++polled == budget) { | |
689 | /* We are here because we reached the NAPI budget - | |
690 | * flush only pending LRO sessions */ | |
c27a02cd YP |
691 | goto out; |
692 | } | |
693 | } | |
694 | ||
c27a02cd YP |
695 | out: |
696 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
697 | mlx4_cq_set_ci(&cq->mcq); | |
698 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
699 | ring->cons = cq->mcq.cons_index; | |
700 | ring->prod += polled; /* Polled descriptors were realocated in place */ | |
c27a02cd YP |
701 | mlx4_en_update_rx_prod_db(ring); |
702 | return polled; | |
703 | } | |
704 | ||
705 | ||
706 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
707 | { | |
708 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
709 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
710 | ||
711 | if (priv->port_up) | |
288379f0 | 712 | napi_schedule(&cq->napi); |
c27a02cd YP |
713 | else |
714 | mlx4_en_arm_cq(priv, cq); | |
715 | } | |
716 | ||
717 | /* Rx CQ polling - called by NAPI */ | |
718 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
719 | { | |
720 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
721 | struct net_device *dev = cq->dev; | |
722 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
723 | int done; | |
724 | ||
725 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
726 | ||
727 | /* If we used up all the quota - we're probably not done yet... */ | |
728 | if (done == budget) | |
729 | INC_PERF_COUNTER(priv->pstats.napi_quota); | |
730 | else { | |
731 | /* Done for now */ | |
288379f0 | 732 | napi_complete(napi); |
c27a02cd YP |
733 | mlx4_en_arm_cq(priv, cq); |
734 | } | |
735 | return done; | |
736 | } | |
737 | ||
738 | ||
25985edc | 739 | /* Calculate the last offset position that accommodates a full fragment |
c27a02cd YP |
740 | * (assuming fagment size = stride-align) */ |
741 | static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align) | |
742 | { | |
743 | u16 res = MLX4_EN_ALLOC_SIZE % stride; | |
744 | u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align; | |
745 | ||
453a6082 | 746 | en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d " |
c27a02cd YP |
747 | "res:%d offset:%d\n", stride, align, res, offset); |
748 | return offset; | |
749 | } | |
750 | ||
751 | ||
752 | static int frag_sizes[] = { | |
753 | FRAG_SZ0, | |
754 | FRAG_SZ1, | |
755 | FRAG_SZ2, | |
756 | FRAG_SZ3 | |
757 | }; | |
758 | ||
759 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
760 | { | |
761 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
762 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; | |
763 | int buf_size = 0; | |
764 | int i = 0; | |
765 | ||
766 | while (buf_size < eff_mtu) { | |
767 | priv->frag_info[i].frag_size = | |
768 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
769 | frag_sizes[i] : eff_mtu - buf_size; | |
770 | priv->frag_info[i].frag_prefix_size = buf_size; | |
771 | if (!i) { | |
772 | priv->frag_info[i].frag_align = NET_IP_ALIGN; | |
773 | priv->frag_info[i].frag_stride = | |
774 | ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); | |
775 | } else { | |
776 | priv->frag_info[i].frag_align = 0; | |
777 | priv->frag_info[i].frag_stride = | |
778 | ALIGN(frag_sizes[i], SMP_CACHE_BYTES); | |
779 | } | |
780 | priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset( | |
781 | priv, priv->frag_info[i].frag_stride, | |
782 | priv->frag_info[i].frag_align); | |
783 | buf_size += priv->frag_info[i].frag_size; | |
784 | i++; | |
785 | } | |
786 | ||
787 | priv->num_frags = i; | |
788 | priv->rx_skb_size = eff_mtu; | |
789 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct)); | |
790 | ||
453a6082 | 791 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " |
c27a02cd YP |
792 | "num_frags:%d):\n", eff_mtu, priv->num_frags); |
793 | for (i = 0; i < priv->num_frags; i++) { | |
453a6082 | 794 | en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d " |
c27a02cd YP |
795 | "stride:%d last_offset:%d\n", i, |
796 | priv->frag_info[i].frag_size, | |
797 | priv->frag_info[i].frag_prefix_size, | |
798 | priv->frag_info[i].frag_align, | |
799 | priv->frag_info[i].frag_stride, | |
800 | priv->frag_info[i].last_offset); | |
801 | } | |
802 | } | |
803 | ||
804 | /* RSS related functions */ | |
805 | ||
9f519f68 YP |
806 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
807 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
808 | enum mlx4_qp_state *state, |
809 | struct mlx4_qp *qp) | |
810 | { | |
811 | struct mlx4_en_dev *mdev = priv->mdev; | |
812 | struct mlx4_qp_context *context; | |
813 | int err = 0; | |
814 | ||
815 | context = kmalloc(sizeof *context , GFP_KERNEL); | |
816 | if (!context) { | |
453a6082 | 817 | en_err(priv, "Failed to allocate qp context\n"); |
c27a02cd YP |
818 | return -ENOMEM; |
819 | } | |
820 | ||
821 | err = mlx4_qp_alloc(mdev->dev, qpn, qp); | |
822 | if (err) { | |
453a6082 | 823 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 824 | goto out; |
c27a02cd YP |
825 | } |
826 | qp->event = mlx4_en_sqp_event; | |
827 | ||
828 | memset(context, 0, sizeof *context); | |
00d7d7bc | 829 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
9f519f68 YP |
830 | qpn, ring->cqn, context); |
831 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); | |
c27a02cd | 832 | |
f3a9d1f2 | 833 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 834 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 835 | context->param3 |= cpu_to_be32(1 << 29); |
4a5f4dd8 YP |
836 | ring->fcs_del = ETH_FCS_LEN; |
837 | } else | |
838 | ring->fcs_del = 0; | |
f3a9d1f2 | 839 | |
9f519f68 | 840 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
841 | if (err) { |
842 | mlx4_qp_remove(mdev->dev, qp); | |
843 | mlx4_qp_free(mdev->dev, qp); | |
844 | } | |
9f519f68 | 845 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
846 | out: |
847 | kfree(context); | |
848 | return err; | |
849 | } | |
850 | ||
851 | /* Allocate rx qp's and configure them according to rss map */ | |
852 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
853 | { | |
854 | struct mlx4_en_dev *mdev = priv->mdev; | |
855 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
856 | struct mlx4_qp_context context; | |
876f6e67 | 857 | struct mlx4_rss_context *rss_context; |
93d3e367 | 858 | int rss_rings; |
c27a02cd | 859 | void *ptr; |
876f6e67 | 860 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 861 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 862 | int i, qpn; |
c27a02cd YP |
863 | int err = 0; |
864 | int good_qps = 0; | |
ad86107f YP |
865 | static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, |
866 | 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, | |
867 | 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; | |
c27a02cd | 868 | |
453a6082 | 869 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
870 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
871 | priv->rx_ring_num, | |
872 | &rss_map->base_qpn); | |
c27a02cd | 873 | if (err) { |
b6b912e0 | 874 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
875 | return err; |
876 | } | |
877 | ||
b6b912e0 | 878 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 879 | qpn = rss_map->base_qpn + i; |
9f519f68 | 880 | err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i], |
c27a02cd YP |
881 | &rss_map->state[i], |
882 | &rss_map->qps[i]); | |
883 | if (err) | |
884 | goto rss_err; | |
885 | ||
886 | ++good_qps; | |
887 | } | |
888 | ||
889 | /* Configure RSS indirection qp */ | |
c27a02cd YP |
890 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); |
891 | if (err) { | |
453a6082 | 892 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 893 | goto rss_err; |
c27a02cd YP |
894 | } |
895 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
896 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
9f519f68 | 897 | priv->rx_ring[0].cqn, &context); |
c27a02cd | 898 | |
93d3e367 YP |
899 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
900 | rss_rings = priv->rx_ring_num; | |
901 | else | |
902 | rss_rings = priv->prof->rss_rings; | |
903 | ||
876f6e67 OG |
904 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
905 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 906 | rss_context = ptr; |
93d3e367 | 907 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 908 | (rss_map->base_qpn)); |
89efea25 | 909 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
910 | if (priv->mdev->profile.udp_rss) { |
911 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
912 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
913 | } | |
0533943c | 914 | rss_context->flags = rss_mask; |
876f6e67 | 915 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
ad86107f YP |
916 | for (i = 0; i < 10; i++) |
917 | rss_context->rss_key[i] = rsskey[i]; | |
c27a02cd YP |
918 | |
919 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, | |
920 | &rss_map->indir_qp, &rss_map->indir_state); | |
921 | if (err) | |
922 | goto indir_err; | |
923 | ||
924 | return 0; | |
925 | ||
926 | indir_err: | |
927 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
928 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
929 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
930 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
931 | rss_err: |
932 | for (i = 0; i < good_qps; i++) { | |
933 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
934 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
935 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
936 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
937 | } | |
b6b912e0 | 938 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
939 | return err; |
940 | } | |
941 | ||
942 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
943 | { | |
944 | struct mlx4_en_dev *mdev = priv->mdev; | |
945 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
946 | int i; | |
947 | ||
948 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
949 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
950 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
951 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 952 | |
b6b912e0 | 953 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
954 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
955 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
956 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
957 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
958 | } | |
b6b912e0 | 959 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
960 | } |
961 | ||
962 | ||
963 | ||
964 | ||
965 |