Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
c27a02cd | 35 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
b67bfe0d | 39 | #include <linux/rculist.h> |
c27a02cd YP |
40 | #include <linux/if_ether.h> |
41 | #include <linux/if_vlan.h> | |
42 | #include <linux/vmalloc.h> | |
35f6f453 | 43 | #include <linux/irq.h> |
c27a02cd YP |
44 | |
45 | #include "mlx4_en.h" | |
46 | ||
51151a16 ED |
47 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
48 | struct mlx4_en_rx_alloc *page_alloc, | |
49 | const struct mlx4_en_frag_info *frag_info, | |
50 | gfp_t _gfp) | |
51 | { | |
52 | int order; | |
53 | struct page *page; | |
54 | dma_addr_t dma; | |
55 | ||
56 | for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { | |
57 | gfp_t gfp = _gfp; | |
58 | ||
59 | if (order) | |
60 | gfp |= __GFP_COMP | __GFP_NOWARN; | |
61 | page = alloc_pages(gfp, order); | |
62 | if (likely(page)) | |
63 | break; | |
64 | if (--order < 0 || | |
65 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
66 | return -ENOMEM; | |
67 | } | |
68 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
69 | PCI_DMA_FROMDEVICE); | |
70 | if (dma_mapping_error(priv->ddev, dma)) { | |
71 | put_page(page); | |
72 | return -ENOMEM; | |
73 | } | |
70fbe079 | 74 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
75 | page_alloc->page = page; |
76 | page_alloc->dma = dma; | |
70fbe079 | 77 | page_alloc->page_offset = frag_info->frag_align; |
51151a16 ED |
78 | /* Not doing get_page() for each frag is a big win |
79 | * on asymetric workloads. | |
80 | */ | |
70fbe079 AV |
81 | atomic_set(&page->_count, |
82 | page_alloc->page_size / frag_info->frag_stride); | |
51151a16 ED |
83 | return 0; |
84 | } | |
85 | ||
4cce66cd TLSC |
86 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
87 | struct mlx4_en_rx_desc *rx_desc, | |
88 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
89 | struct mlx4_en_rx_alloc *ring_alloc, |
90 | gfp_t gfp) | |
c27a02cd | 91 | { |
4cce66cd | 92 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 93 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
94 | struct page *page; |
95 | dma_addr_t dma; | |
4cce66cd | 96 | int i; |
c27a02cd | 97 | |
4cce66cd TLSC |
98 | for (i = 0; i < priv->num_frags; i++) { |
99 | frag_info = &priv->frag_info[i]; | |
51151a16 | 100 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
101 | page_alloc[i].page_offset += frag_info->frag_stride; |
102 | ||
103 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
104 | ring_alloc[i].page_size) | |
51151a16 | 105 | continue; |
70fbe079 | 106 | |
51151a16 ED |
107 | if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) |
108 | goto out; | |
4cce66cd | 109 | } |
c27a02cd | 110 | |
4cce66cd TLSC |
111 | for (i = 0; i < priv->num_frags; i++) { |
112 | frags[i] = ring_alloc[i]; | |
70fbe079 | 113 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
114 | ring_alloc[i] = page_alloc[i]; |
115 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 116 | } |
4cce66cd | 117 | |
c27a02cd | 118 | return 0; |
4cce66cd | 119 | |
4cce66cd TLSC |
120 | out: |
121 | while (i--) { | |
122 | frag_info = &priv->frag_info[i]; | |
51151a16 | 123 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 124 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
70fbe079 | 125 | page_alloc[i].page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
126 | page = page_alloc[i].page; |
127 | atomic_set(&page->_count, 1); | |
128 | put_page(page); | |
129 | } | |
4cce66cd TLSC |
130 | } |
131 | return -ENOMEM; | |
132 | } | |
133 | ||
134 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
135 | struct mlx4_en_rx_alloc *frags, | |
136 | int i) | |
137 | { | |
51151a16 | 138 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 139 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 140 | |
021f1107 AV |
141 | |
142 | if (next_frag_end > frags[i].page_size) | |
70fbe079 AV |
143 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
144 | PCI_DMA_FROMDEVICE); | |
51151a16 | 145 | |
4cce66cd TLSC |
146 | if (frags[i].page) |
147 | put_page(frags[i].page); | |
c27a02cd YP |
148 | } |
149 | ||
150 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
151 | struct mlx4_en_rx_ring *ring) | |
152 | { | |
c27a02cd | 153 | int i; |
51151a16 | 154 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
155 | |
156 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 157 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 158 | |
51151a16 ED |
159 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
160 | frag_info, GFP_KERNEL)) | |
4cce66cd | 161 | goto out; |
c27a02cd YP |
162 | } |
163 | return 0; | |
164 | ||
165 | out: | |
166 | while (i--) { | |
51151a16 ED |
167 | struct page *page; |
168 | ||
c27a02cd | 169 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 170 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 | 171 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
172 | page = page_alloc->page; |
173 | atomic_set(&page->_count, 1); | |
174 | put_page(page); | |
c27a02cd YP |
175 | page_alloc->page = NULL; |
176 | } | |
177 | return -ENOMEM; | |
178 | } | |
179 | ||
180 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
181 | struct mlx4_en_rx_ring *ring) | |
182 | { | |
183 | struct mlx4_en_rx_alloc *page_alloc; | |
184 | int i; | |
185 | ||
186 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
187 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
188 | ||
c27a02cd | 189 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
190 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
191 | i, page_count(page_alloc->page)); | |
c27a02cd | 192 | |
4cce66cd | 193 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 AV |
194 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
195 | while (page_alloc->page_offset + frag_info->frag_stride < | |
196 | page_alloc->page_size) { | |
51151a16 | 197 | put_page(page_alloc->page); |
70fbe079 | 198 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 199 | } |
c27a02cd YP |
200 | page_alloc->page = NULL; |
201 | } | |
202 | } | |
203 | ||
c27a02cd YP |
204 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
205 | struct mlx4_en_rx_ring *ring, int index) | |
206 | { | |
207 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
208 | int possible_frags; |
209 | int i; | |
210 | ||
c27a02cd YP |
211 | /* Set size and memtype fields */ |
212 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
213 | rx_desc->data[i].byte_count = |
214 | cpu_to_be32(priv->frag_info[i].frag_size); | |
215 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
216 | } | |
217 | ||
218 | /* If the number of used fragments does not fill up the ring stride, | |
219 | * remaining (unused) fragments must be padded with null address/size | |
220 | * and a special memory key */ | |
221 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
222 | for (i = priv->num_frags; i < possible_frags; i++) { | |
223 | rx_desc->data[i].byte_count = 0; | |
224 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
225 | rx_desc->data[i].addr = 0; | |
226 | } | |
227 | } | |
228 | ||
c27a02cd | 229 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
230 | struct mlx4_en_rx_ring *ring, int index, |
231 | gfp_t gfp) | |
c27a02cd YP |
232 | { |
233 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
234 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
235 | (index << priv->log_rx_info); | |
c27a02cd | 236 | |
51151a16 | 237 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
238 | } |
239 | ||
240 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
241 | { | |
242 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
243 | } | |
244 | ||
38aab07c YP |
245 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
246 | struct mlx4_en_rx_ring *ring, | |
247 | int index) | |
248 | { | |
4cce66cd | 249 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
250 | int nr; |
251 | ||
4cce66cd | 252 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 253 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 254 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 255 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
256 | } |
257 | } | |
258 | ||
c27a02cd YP |
259 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
260 | { | |
c27a02cd YP |
261 | struct mlx4_en_rx_ring *ring; |
262 | int ring_ind; | |
263 | int buf_ind; | |
38aab07c | 264 | int new_size; |
c27a02cd YP |
265 | |
266 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
267 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 268 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
269 | |
270 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 ED |
271 | ring->actual_size, |
272 | GFP_KERNEL)) { | |
c27a02cd | 273 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 274 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
275 | return -ENOMEM; |
276 | } else { | |
38aab07c | 277 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 278 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 279 | ring->actual_size, new_size); |
38aab07c | 280 | goto reduce_rings; |
c27a02cd YP |
281 | } |
282 | } | |
283 | ring->actual_size++; | |
284 | ring->prod++; | |
285 | } | |
286 | } | |
38aab07c YP |
287 | return 0; |
288 | ||
289 | reduce_rings: | |
290 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 291 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
292 | while (ring->actual_size > new_size) { |
293 | ring->actual_size--; | |
294 | ring->prod--; | |
295 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
296 | } | |
38aab07c YP |
297 | } |
298 | ||
c27a02cd YP |
299 | return 0; |
300 | } | |
301 | ||
c27a02cd YP |
302 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
303 | struct mlx4_en_rx_ring *ring) | |
304 | { | |
c27a02cd | 305 | int index; |
c27a02cd | 306 | |
453a6082 YP |
307 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
308 | ring->cons, ring->prod); | |
c27a02cd YP |
309 | |
310 | /* Unmap and free Rx buffers */ | |
38aab07c | 311 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
312 | while (ring->cons != ring->prod) { |
313 | index = ring->cons & ring->size_mask; | |
453a6082 | 314 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 315 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
316 | ++ring->cons; |
317 | } | |
318 | } | |
319 | ||
02512482 IS |
320 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
321 | { | |
322 | int i; | |
323 | int num_of_eqs; | |
bb2146bc | 324 | int num_rx_rings; |
02512482 IS |
325 | struct mlx4_dev *dev = mdev->dev; |
326 | ||
327 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
328 | if (!dev->caps.comp_pool) | |
329 | num_of_eqs = max_t(int, MIN_RX_RINGS, | |
330 | min_t(int, | |
331 | dev->caps.num_comp_vectors, | |
332 | DEF_RX_RINGS)); | |
333 | else | |
334 | num_of_eqs = min_t(int, MAX_MSIX_P_PORT, | |
335 | dev->caps.comp_pool/ | |
336 | dev->caps.num_ports) - 1; | |
337 | ||
bb2146bc IS |
338 | num_rx_rings = min_t(int, num_of_eqs, |
339 | netif_get_num_default_rss_queues()); | |
02512482 | 340 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 341 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
342 | } |
343 | } | |
344 | ||
c27a02cd | 345 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 346 | struct mlx4_en_rx_ring **pring, |
163561a4 | 347 | u32 size, u16 stride, int node) |
c27a02cd YP |
348 | { |
349 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 350 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 351 | int err = -ENOMEM; |
c27a02cd YP |
352 | int tmp; |
353 | ||
163561a4 | 354 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 355 | if (!ring) { |
163561a4 EE |
356 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
357 | if (!ring) { | |
358 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
359 | return -ENOMEM; | |
360 | } | |
41d942d5 EE |
361 | } |
362 | ||
c27a02cd YP |
363 | ring->prod = 0; |
364 | ring->cons = 0; | |
365 | ring->size = size; | |
366 | ring->size_mask = size - 1; | |
367 | ring->stride = stride; | |
368 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 369 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
370 | |
371 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 372 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 373 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 374 | if (!ring->rx_info) { |
163561a4 EE |
375 | ring->rx_info = vmalloc(tmp); |
376 | if (!ring->rx_info) { | |
377 | err = -ENOMEM; | |
378 | goto err_ring; | |
379 | } | |
41d942d5 | 380 | } |
e404decb | 381 | |
453a6082 | 382 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
383 | ring->rx_info, tmp); |
384 | ||
163561a4 EE |
385 | /* Allocate HW buffers on provided NUMA node */ |
386 | set_dev_node(&mdev->dev->pdev->dev, node); | |
c27a02cd YP |
387 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, |
388 | ring->buf_size, 2 * PAGE_SIZE); | |
163561a4 | 389 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 390 | if (err) |
41d942d5 | 391 | goto err_info; |
c27a02cd YP |
392 | |
393 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
394 | if (err) { | |
453a6082 | 395 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
396 | goto err_hwq; |
397 | } | |
398 | ring->buf = ring->wqres.buf.direct.buf; | |
399 | ||
ec693d47 AV |
400 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
401 | ||
41d942d5 | 402 | *pring = ring; |
c27a02cd YP |
403 | return 0; |
404 | ||
c27a02cd YP |
405 | err_hwq: |
406 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
41d942d5 | 407 | err_info: |
c27a02cd YP |
408 | vfree(ring->rx_info); |
409 | ring->rx_info = NULL; | |
41d942d5 EE |
410 | err_ring: |
411 | kfree(ring); | |
412 | *pring = NULL; | |
413 | ||
c27a02cd YP |
414 | return err; |
415 | } | |
416 | ||
417 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
418 | { | |
c27a02cd YP |
419 | struct mlx4_en_rx_ring *ring; |
420 | int i; | |
421 | int ring_ind; | |
422 | int err; | |
423 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
424 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
425 | |
426 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 427 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
428 | |
429 | ring->prod = 0; | |
430 | ring->cons = 0; | |
431 | ring->actual_size = 0; | |
41d942d5 | 432 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
433 | |
434 | ring->stride = stride; | |
9f519f68 YP |
435 | if (ring->stride <= TXBB_SIZE) |
436 | ring->buf += TXBB_SIZE; | |
437 | ||
c27a02cd YP |
438 | ring->log_stride = ffs(ring->stride) - 1; |
439 | ring->buf_size = ring->size * ring->stride; | |
440 | ||
441 | memset(ring->buf, 0, ring->buf_size); | |
442 | mlx4_en_update_rx_prod_db(ring); | |
443 | ||
4cce66cd | 444 | /* Initialize all descriptors */ |
c27a02cd YP |
445 | for (i = 0; i < ring->size; i++) |
446 | mlx4_en_init_rx_desc(priv, ring, i); | |
447 | ||
448 | /* Initialize page allocators */ | |
449 | err = mlx4_en_init_allocator(priv, ring); | |
450 | if (err) { | |
453a6082 | 451 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
452 | if (ring->stride <= TXBB_SIZE) |
453 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
454 | ring_ind--; |
455 | goto err_allocator; | |
c27a02cd | 456 | } |
c27a02cd | 457 | } |
b58515be IM |
458 | err = mlx4_en_fill_rx_buffers(priv); |
459 | if (err) | |
c27a02cd YP |
460 | goto err_buffers; |
461 | ||
462 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 463 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 464 | |
00d7d7bc | 465 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 466 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
467 | } |
468 | ||
469 | return 0; | |
470 | ||
c27a02cd YP |
471 | err_buffers: |
472 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 473 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
474 | |
475 | ring_ind = priv->rx_ring_num - 1; | |
476 | err_allocator: | |
477 | while (ring_ind >= 0) { | |
41d942d5 EE |
478 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
479 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
480 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
481 | ring_ind--; |
482 | } | |
483 | return err; | |
484 | } | |
485 | ||
486 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
41d942d5 EE |
487 | struct mlx4_en_rx_ring **pring, |
488 | u32 size, u16 stride) | |
c27a02cd YP |
489 | { |
490 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 491 | struct mlx4_en_rx_ring *ring = *pring; |
c27a02cd | 492 | |
c27a02cd | 493 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
68355f71 | 494 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
495 | vfree(ring->rx_info); |
496 | ring->rx_info = NULL; | |
41d942d5 EE |
497 | kfree(ring); |
498 | *pring = NULL; | |
1eb8c695 | 499 | #ifdef CONFIG_RFS_ACCEL |
41d942d5 | 500 | mlx4_en_cleanup_filters(priv); |
1eb8c695 | 501 | #endif |
c27a02cd YP |
502 | } |
503 | ||
504 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
505 | struct mlx4_en_rx_ring *ring) | |
506 | { | |
c27a02cd | 507 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
508 | if (ring->stride <= TXBB_SIZE) |
509 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
510 | mlx4_en_destroy_allocator(priv, ring); |
511 | } | |
512 | ||
513 | ||
c27a02cd YP |
514 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
515 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 516 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 517 | struct sk_buff *skb, |
c27a02cd YP |
518 | int length) |
519 | { | |
90278c9f | 520 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
521 | struct mlx4_en_frag_info *frag_info; |
522 | int nr; | |
523 | dma_addr_t dma; | |
524 | ||
4cce66cd | 525 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
526 | for (nr = 0; nr < priv->num_frags; nr++) { |
527 | frag_info = &priv->frag_info[nr]; | |
528 | if (length <= frag_info->frag_prefix_size) | |
529 | break; | |
4cce66cd TLSC |
530 | if (!frags[nr].page) |
531 | goto fail; | |
c27a02cd | 532 | |
c27a02cd | 533 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
534 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
535 | DMA_FROM_DEVICE); | |
c27a02cd | 536 | |
4cce66cd | 537 | /* Save page reference in skb */ |
4cce66cd TLSC |
538 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
539 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 540 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 541 | skb->truesize += frag_info->frag_stride; |
51151a16 | 542 | frags[nr].page = NULL; |
c27a02cd YP |
543 | } |
544 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 545 | if (nr > 0) |
9e903e08 ED |
546 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
547 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
548 | return nr; |
549 | ||
550 | fail: | |
c27a02cd YP |
551 | while (nr > 0) { |
552 | nr--; | |
311761c8 | 553 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
554 | } |
555 | return 0; | |
556 | } | |
557 | ||
558 | ||
559 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
560 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 561 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
562 | unsigned int length) |
563 | { | |
c27a02cd YP |
564 | struct sk_buff *skb; |
565 | void *va; | |
566 | int used_frags; | |
567 | dma_addr_t dma; | |
568 | ||
c056b734 | 569 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 570 | if (!skb) { |
453a6082 | 571 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
572 | return NULL; |
573 | } | |
c27a02cd YP |
574 | skb_reserve(skb, NET_IP_ALIGN); |
575 | skb->len = length; | |
c27a02cd YP |
576 | |
577 | /* Get pointer to first fragment so we could copy the headers into the | |
578 | * (linear part of the) skb */ | |
70fbe079 | 579 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
580 | |
581 | if (length <= SMALL_PACKET_SIZE) { | |
582 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 583 | * sync buffers for the copy */ |
c27a02cd | 584 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 585 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 586 | DMA_FROM_DEVICE); |
c27a02cd | 587 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
588 | skb->tail += length; |
589 | } else { | |
c27a02cd | 590 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
591 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
592 | skb, length); | |
785a0982 YP |
593 | if (unlikely(!used_frags)) { |
594 | kfree_skb(skb); | |
595 | return NULL; | |
596 | } | |
c27a02cd YP |
597 | skb_shinfo(skb)->nr_frags = used_frags; |
598 | ||
599 | /* Copy headers into the skb linear buffer */ | |
600 | memcpy(skb->data, va, HEADER_COPY_SIZE); | |
601 | skb->tail += HEADER_COPY_SIZE; | |
602 | ||
603 | /* Skip headers in first fragment */ | |
604 | skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; | |
605 | ||
606 | /* Adjust size of first fragment */ | |
9e903e08 | 607 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE); |
c27a02cd YP |
608 | skb->data_len = length - HEADER_COPY_SIZE; |
609 | } | |
610 | return skb; | |
611 | } | |
612 | ||
e7c1c2c4 YP |
613 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
614 | { | |
615 | int i; | |
616 | int offset = ETH_HLEN; | |
617 | ||
618 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
619 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
620 | goto out_loopback; | |
621 | } | |
622 | /* Loopback found */ | |
623 | priv->loopback_ok = 1; | |
624 | ||
625 | out_loopback: | |
626 | dev_kfree_skb_any(skb); | |
627 | } | |
c27a02cd | 628 | |
4cce66cd TLSC |
629 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
630 | struct mlx4_en_rx_ring *ring) | |
631 | { | |
632 | int index = ring->prod & ring->size_mask; | |
633 | ||
634 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
51151a16 | 635 | if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC)) |
4cce66cd TLSC |
636 | break; |
637 | ring->prod++; | |
638 | index = ring->prod & ring->size_mask; | |
639 | } | |
640 | } | |
641 | ||
c27a02cd YP |
642 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
643 | { | |
644 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 645 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 646 | struct mlx4_cqe *cqe; |
41d942d5 | 647 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 648 | struct mlx4_en_rx_alloc *frags; |
c27a02cd YP |
649 | struct mlx4_en_rx_desc *rx_desc; |
650 | struct sk_buff *skb; | |
651 | int index; | |
652 | int nr; | |
653 | unsigned int length; | |
654 | int polled = 0; | |
655 | int ip_summed; | |
08ff3235 | 656 | int factor = priv->cqe_factor; |
ec693d47 | 657 | u64 timestamp; |
837052d0 | 658 | bool l2_tunnel; |
c27a02cd YP |
659 | |
660 | if (!priv->port_up) | |
661 | return 0; | |
662 | ||
38be0a34 EB |
663 | if (budget <= 0) |
664 | return polled; | |
665 | ||
c27a02cd YP |
666 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
667 | * descriptor offset can be deduced from the CQE index instead of | |
668 | * reading 'cqe->index' */ | |
669 | index = cq->mcq.cons_index & ring->size_mask; | |
08ff3235 | 670 | cqe = &cq->buf[(index << factor) + factor]; |
c27a02cd YP |
671 | |
672 | /* Process all completed CQEs */ | |
673 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
674 | cq->mcq.cons_index & cq->size)) { | |
675 | ||
4cce66cd | 676 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
677 | rx_desc = ring->buf + (index << ring->log_stride); |
678 | ||
679 | /* | |
680 | * make sure we read the CQE after we read the ownership bit | |
681 | */ | |
682 | rmb(); | |
683 | ||
684 | /* Drop packet on bad receive or bad checksum */ | |
685 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
686 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
687 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
688 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
689 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
690 | goto next; |
691 | } | |
692 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 693 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
694 | goto next; |
695 | } | |
696 | ||
79aeaccd YB |
697 | /* Check if we need to drop the packet if SRIOV is not enabled |
698 | * and not performing the selftest or flb disabled | |
699 | */ | |
700 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
701 | struct ethhdr *ethh; | |
702 | dma_addr_t dma; | |
79aeaccd YB |
703 | /* Get pointer to first fragment since we haven't |
704 | * skb yet and cast it to ethhdr struct | |
705 | */ | |
706 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
707 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
708 | DMA_FROM_DEVICE); | |
709 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 710 | frags[0].page_offset); |
79aeaccd | 711 | |
c07cb4b0 YB |
712 | if (is_multicast_ether_addr(ethh->h_dest)) { |
713 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
714 | struct hlist_head *bucket; |
715 | unsigned int mac_hash; | |
716 | ||
717 | /* Drop the packet, since HW loopback-ed it */ | |
718 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
719 | bucket = &priv->mac_hash[mac_hash]; | |
720 | rcu_read_lock(); | |
b67bfe0d | 721 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 YB |
722 | if (ether_addr_equal_64bits(entry->mac, |
723 | ethh->h_source)) { | |
724 | rcu_read_unlock(); | |
725 | goto next; | |
726 | } | |
727 | } | |
728 | rcu_read_unlock(); | |
729 | } | |
79aeaccd | 730 | } |
5b4c4d36 | 731 | |
c27a02cd YP |
732 | /* |
733 | * Packet is OK - process it. | |
734 | */ | |
735 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 736 | length -= ring->fcs_del; |
c27a02cd YP |
737 | ring->bytes += length; |
738 | ring->packets++; | |
837052d0 OG |
739 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
740 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 741 | |
c8c64cff | 742 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
c27a02cd YP |
743 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && |
744 | (cqe->checksum == cpu_to_be16(0xffff))) { | |
ad04378c | 745 | ring->csum_ok++; |
f1d29a3f | 746 | /* This packet is eligible for GRO if it is: |
c27a02cd YP |
747 | * - DIX Ethernet (type interpretation) |
748 | * - TCP/IP (v4) | |
749 | * - without IP options | |
9e77a2b8 AV |
750 | * - not an IP fragment |
751 | * - no LLS polling in progress | |
752 | */ | |
e6a76758 | 753 | if (!mlx4_en_cq_busy_polling(cq) && |
9e77a2b8 | 754 | (dev->features & NETIF_F_GRO)) { |
fa37a958 | 755 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); |
ebc872c7 YP |
756 | if (!gro_skb) |
757 | goto next; | |
c27a02cd | 758 | |
4cce66cd TLSC |
759 | nr = mlx4_en_complete_rx_desc(priv, |
760 | rx_desc, frags, gro_skb, | |
761 | length); | |
c27a02cd YP |
762 | if (!nr) |
763 | goto next; | |
764 | ||
fa37a958 YP |
765 | skb_shinfo(gro_skb)->nr_frags = nr; |
766 | gro_skb->len = length; | |
767 | gro_skb->data_len = length; | |
fa37a958 YP |
768 | gro_skb->ip_summed = CHECKSUM_UNNECESSARY; |
769 | ||
837052d0 OG |
770 | if (l2_tunnel) |
771 | gro_skb->encapsulation = 1; | |
ec693d47 AV |
772 | if ((cqe->vlan_my_qpn & |
773 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && | |
774 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
f1b553fb JP |
775 | u16 vid = be16_to_cpu(cqe->sl_vid); |
776 | ||
86a9bad3 | 777 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); |
f1b553fb JP |
778 | } |
779 | ||
ad86107f | 780 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
781 | skb_set_hash(gro_skb, |
782 | be32_to_cpu(cqe->immed_rss_invalid), | |
783 | PKT_HASH_TYPE_L3); | |
ad86107f | 784 | |
3b61008d | 785 | skb_record_rx_queue(gro_skb, cq->ring); |
32b333fe | 786 | skb_mark_napi_id(gro_skb, &cq->napi); |
c27a02cd | 787 | |
ec693d47 AV |
788 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
789 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
790 | mlx4_en_fill_hwtstamps(mdev, | |
791 | skb_hwtstamps(gro_skb), | |
792 | timestamp); | |
793 | } | |
794 | ||
795 | napi_gro_frags(&cq->napi); | |
c27a02cd YP |
796 | goto next; |
797 | } | |
798 | ||
f1d29a3f | 799 | /* GRO not possible, complete processing here */ |
c27a02cd | 800 | ip_summed = CHECKSUM_UNNECESSARY; |
c27a02cd YP |
801 | } else { |
802 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 803 | ring->csum_none++; |
c27a02cd YP |
804 | } |
805 | } else { | |
806 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 807 | ring->csum_none++; |
c27a02cd YP |
808 | } |
809 | ||
4cce66cd | 810 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd YP |
811 | if (!skb) { |
812 | priv->stats.rx_dropped++; | |
813 | goto next; | |
814 | } | |
815 | ||
e7c1c2c4 YP |
816 | if (unlikely(priv->validate_loopback)) { |
817 | validate_loopback(priv, skb); | |
818 | goto next; | |
819 | } | |
820 | ||
c27a02cd YP |
821 | skb->ip_summed = ip_summed; |
822 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 823 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 824 | |
837052d0 OG |
825 | if (l2_tunnel) |
826 | skb->encapsulation = 1; | |
827 | ||
ad86107f | 828 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
829 | skb_set_hash(skb, |
830 | be32_to_cpu(cqe->immed_rss_invalid), | |
831 | PKT_HASH_TYPE_L3); | |
ad86107f | 832 | |
ec693d47 AV |
833 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
834 | MLX4_CQE_VLAN_PRESENT_MASK) && | |
835 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) | |
86a9bad3 | 836 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
f1b553fb | 837 | |
ec693d47 AV |
838 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
839 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
840 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
841 | timestamp); | |
842 | } | |
843 | ||
8b80cda5 | 844 | skb_mark_napi_id(skb, &cq->napi); |
9e77a2b8 | 845 | |
e6a76758 ED |
846 | if (!mlx4_en_cq_busy_polling(cq)) |
847 | napi_gro_receive(&cq->napi, skb); | |
848 | else | |
849 | netif_receive_skb(skb); | |
c27a02cd | 850 | |
c27a02cd | 851 | next: |
4cce66cd TLSC |
852 | for (nr = 0; nr < priv->num_frags; nr++) |
853 | mlx4_en_free_frag(priv, frags, nr); | |
854 | ||
c27a02cd YP |
855 | ++cq->mcq.cons_index; |
856 | index = (cq->mcq.cons_index) & ring->size_mask; | |
08ff3235 | 857 | cqe = &cq->buf[(index << factor) + factor]; |
f1d29a3f | 858 | if (++polled == budget) |
c27a02cd | 859 | goto out; |
c27a02cd YP |
860 | } |
861 | ||
c27a02cd YP |
862 | out: |
863 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
864 | mlx4_cq_set_ci(&cq->mcq); | |
865 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
866 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 867 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
868 | mlx4_en_update_rx_prod_db(ring); |
869 | return polled; | |
870 | } | |
871 | ||
872 | ||
873 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
874 | { | |
875 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
876 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
877 | ||
878 | if (priv->port_up) | |
288379f0 | 879 | napi_schedule(&cq->napi); |
c27a02cd YP |
880 | else |
881 | mlx4_en_arm_cq(priv, cq); | |
882 | } | |
883 | ||
884 | /* Rx CQ polling - called by NAPI */ | |
885 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
886 | { | |
887 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
888 | struct net_device *dev = cq->dev; | |
889 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
890 | int done; | |
891 | ||
9e77a2b8 AV |
892 | if (!mlx4_en_cq_lock_napi(cq)) |
893 | return budget; | |
894 | ||
c27a02cd YP |
895 | done = mlx4_en_process_rx_cq(dev, cq, budget); |
896 | ||
9e77a2b8 AV |
897 | mlx4_en_cq_unlock_napi(cq); |
898 | ||
c27a02cd | 899 | /* If we used up all the quota - we're probably not done yet... */ |
2eacc23c | 900 | if (done == budget) { |
35f6f453 AV |
901 | int cpu_curr; |
902 | const struct cpumask *aff; | |
903 | ||
c27a02cd | 904 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
905 | |
906 | cpu_curr = smp_processor_id(); | |
907 | aff = irq_desc_get_irq_data(cq->irq_desc)->affinity; | |
908 | ||
909 | if (unlikely(!cpumask_test_cpu(cpu_curr, aff))) { | |
910 | /* Current cpu is not according to smp_irq_affinity - | |
911 | * probably affinity changed. need to stop this NAPI | |
912 | * poll, and restart it on the right CPU | |
913 | */ | |
2eacc23c YA |
914 | napi_complete(napi); |
915 | mlx4_en_arm_cq(priv, cq); | |
916 | return 0; | |
917 | } | |
918 | } else { | |
c27a02cd | 919 | /* Done for now */ |
288379f0 | 920 | napi_complete(napi); |
c27a02cd YP |
921 | mlx4_en_arm_cq(priv, cq); |
922 | } | |
923 | return done; | |
924 | } | |
925 | ||
51151a16 | 926 | static const int frag_sizes[] = { |
c27a02cd YP |
927 | FRAG_SZ0, |
928 | FRAG_SZ1, | |
929 | FRAG_SZ2, | |
930 | FRAG_SZ3 | |
931 | }; | |
932 | ||
933 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
934 | { | |
935 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
d5b8dff0 | 936 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN; |
c27a02cd YP |
937 | int buf_size = 0; |
938 | int i = 0; | |
939 | ||
940 | while (buf_size < eff_mtu) { | |
941 | priv->frag_info[i].frag_size = | |
942 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
943 | frag_sizes[i] : eff_mtu - buf_size; | |
944 | priv->frag_info[i].frag_prefix_size = buf_size; | |
945 | if (!i) { | |
946 | priv->frag_info[i].frag_align = NET_IP_ALIGN; | |
947 | priv->frag_info[i].frag_stride = | |
948 | ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); | |
949 | } else { | |
950 | priv->frag_info[i].frag_align = 0; | |
951 | priv->frag_info[i].frag_stride = | |
952 | ALIGN(frag_sizes[i], SMP_CACHE_BYTES); | |
953 | } | |
c27a02cd YP |
954 | buf_size += priv->frag_info[i].frag_size; |
955 | i++; | |
956 | } | |
957 | ||
958 | priv->num_frags = i; | |
959 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 960 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 961 | |
1a91de28 JP |
962 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
963 | eff_mtu, priv->num_frags); | |
c27a02cd | 964 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 ED |
965 | en_err(priv, |
966 | " frag:%d - size:%d prefix:%d align:%d stride:%d\n", | |
967 | i, | |
968 | priv->frag_info[i].frag_size, | |
969 | priv->frag_info[i].frag_prefix_size, | |
970 | priv->frag_info[i].frag_align, | |
971 | priv->frag_info[i].frag_stride); | |
c27a02cd YP |
972 | } |
973 | } | |
974 | ||
975 | /* RSS related functions */ | |
976 | ||
9f519f68 YP |
977 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
978 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
979 | enum mlx4_qp_state *state, |
980 | struct mlx4_qp *qp) | |
981 | { | |
982 | struct mlx4_en_dev *mdev = priv->mdev; | |
983 | struct mlx4_qp_context *context; | |
984 | int err = 0; | |
985 | ||
14f8dc49 JP |
986 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
987 | if (!context) | |
c27a02cd | 988 | return -ENOMEM; |
c27a02cd | 989 | |
40f2287b | 990 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 991 | if (err) { |
453a6082 | 992 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 993 | goto out; |
c27a02cd YP |
994 | } |
995 | qp->event = mlx4_en_sqp_event; | |
996 | ||
997 | memset(context, 0, sizeof *context); | |
00d7d7bc | 998 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 999 | qpn, ring->cqn, -1, context); |
9f519f68 | 1000 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1001 | |
f3a9d1f2 | 1002 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1003 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1004 | context->param3 |= cpu_to_be32(1 << 29); |
4a5f4dd8 YP |
1005 | ring->fcs_del = ETH_FCS_LEN; |
1006 | } else | |
1007 | ring->fcs_del = 0; | |
f3a9d1f2 | 1008 | |
9f519f68 | 1009 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1010 | if (err) { |
1011 | mlx4_qp_remove(mdev->dev, qp); | |
1012 | mlx4_qp_free(mdev->dev, qp); | |
1013 | } | |
9f519f68 | 1014 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1015 | out: |
1016 | kfree(context); | |
1017 | return err; | |
1018 | } | |
1019 | ||
cabdc8ee HHZ |
1020 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1021 | { | |
1022 | int err; | |
1023 | u32 qpn; | |
1024 | ||
1025 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn); | |
1026 | if (err) { | |
1027 | en_err(priv, "Failed reserving drop qpn\n"); | |
1028 | return err; | |
1029 | } | |
40f2287b | 1030 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1031 | if (err) { |
1032 | en_err(priv, "Failed allocating drop qp\n"); | |
1033 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1034 | return err; | |
1035 | } | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1041 | { | |
1042 | u32 qpn; | |
1043 | ||
1044 | qpn = priv->drop_qp.qpn; | |
1045 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1046 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1047 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1048 | } | |
1049 | ||
c27a02cd YP |
1050 | /* Allocate rx qp's and configure them according to rss map */ |
1051 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1052 | { | |
1053 | struct mlx4_en_dev *mdev = priv->mdev; | |
1054 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1055 | struct mlx4_qp_context context; | |
876f6e67 | 1056 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1057 | int rss_rings; |
c27a02cd | 1058 | void *ptr; |
876f6e67 | 1059 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1060 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1061 | int i, qpn; |
c27a02cd YP |
1062 | int err = 0; |
1063 | int good_qps = 0; | |
ad86107f YP |
1064 | static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, |
1065 | 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, | |
1066 | 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; | |
c27a02cd | 1067 | |
453a6082 | 1068 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1069 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1070 | priv->rx_ring_num, | |
1071 | &rss_map->base_qpn); | |
c27a02cd | 1072 | if (err) { |
b6b912e0 | 1073 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1074 | return err; |
1075 | } | |
1076 | ||
b6b912e0 | 1077 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1078 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1079 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1080 | &rss_map->state[i], |
1081 | &rss_map->qps[i]); | |
1082 | if (err) | |
1083 | goto rss_err; | |
1084 | ||
1085 | ++good_qps; | |
1086 | } | |
1087 | ||
1088 | /* Configure RSS indirection qp */ | |
40f2287b | 1089 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1090 | if (err) { |
453a6082 | 1091 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1092 | goto rss_err; |
c27a02cd YP |
1093 | } |
1094 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1095 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1096 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1097 | |
93d3e367 YP |
1098 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1099 | rss_rings = priv->rx_ring_num; | |
1100 | else | |
1101 | rss_rings = priv->prof->rss_rings; | |
1102 | ||
876f6e67 OG |
1103 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1104 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1105 | rss_context = ptr; |
93d3e367 | 1106 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1107 | (rss_map->base_qpn)); |
89efea25 | 1108 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1109 | if (priv->mdev->profile.udp_rss) { |
1110 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1111 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1112 | } | |
837052d0 OG |
1113 | |
1114 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1115 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1116 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1117 | } | |
1118 | ||
0533943c | 1119 | rss_context->flags = rss_mask; |
876f6e67 | 1120 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
ad86107f | 1121 | for (i = 0; i < 10; i++) |
39b2c4eb | 1122 | rss_context->rss_key[i] = cpu_to_be32(rsskey[i]); |
c27a02cd YP |
1123 | |
1124 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, | |
1125 | &rss_map->indir_qp, &rss_map->indir_state); | |
1126 | if (err) | |
1127 | goto indir_err; | |
1128 | ||
1129 | return 0; | |
1130 | ||
1131 | indir_err: | |
1132 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1133 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1134 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1135 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1136 | rss_err: |
1137 | for (i = 0; i < good_qps; i++) { | |
1138 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1139 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1140 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1141 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1142 | } | |
b6b912e0 | 1143 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1144 | return err; |
1145 | } | |
1146 | ||
1147 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1148 | { | |
1149 | struct mlx4_en_dev *mdev = priv->mdev; | |
1150 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1151 | int i; | |
1152 | ||
1153 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1154 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1155 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1156 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1157 | |
b6b912e0 | 1158 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1159 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1160 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1161 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1162 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1163 | } | |
b6b912e0 | 1164 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1165 | } |