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net: incorrect use of init_completion fixup
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
1b136de1 42#include <net/vxlan.h>
c27a02cd
YP		 43
44#include <linux/mlx4/driver.h>
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/cmd.h>
47#include <linux/mlx4/cq.h>
48
49#include "mlx4_en.h"
50#include "en_port.h"
51
d317966b 52int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 53{
bc6a4744
AV		 54 struct mlx4_en_priv *priv = netdev_priv(dev);
55 int i;
d317966b 56 unsigned int offset = 0;
bc6a4744
AV		 57
58 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 59 return -EINVAL;
60
bc6a4744
AV		 61 netdev_set_num_tc(dev, up);
62
63 /* Partition Tx queues evenly amongst UP's */
bc6a4744 64 for (i = 0; i < up; i++) {
d317966b
AV		 65 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
66 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 67 }
68
897d7846
AV		 69 return 0;
70}
71
e0d1095a 72#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 73/* must be called with local_bh_disable()d */
74static int mlx4_en_low_latency_recv(struct napi_struct *napi)
75{
76 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
77 struct net_device *dev = cq->dev;
78 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 79 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 80 int done;
81
82 if (!priv->port_up)
83 return LL_FLUSH_FAILED;
84
85 if (!mlx4_en_cq_lock_poll(cq))
86 return LL_FLUSH_BUSY;
87
88 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 89 if (likely(done))
90 rx_ring->cleaned += done;
91 else
92 rx_ring->misses++;
9e77a2b8
AV		 93
94 mlx4_en_cq_unlock_poll(cq);
95
96 return done;
97}
e0d1095a 98#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 99
1eb8c695
AV		 100#ifdef CONFIG_RFS_ACCEL
101
102struct mlx4_en_filter {
103 struct list_head next;
104 struct work_struct work;
105
75a353d4 106 u8 ip_proto;
1eb8c695
AV		 107 __be32 src_ip;
108 __be32 dst_ip;
109 __be16 src_port;
110 __be16 dst_port;
111
112 int rxq_index;
113 struct mlx4_en_priv *priv;
114 u32 flow_id; /* RFS infrastructure id */
115 int id; /* mlx4_en driver id */
116 u64 reg_id; /* Flow steering API id */
117 u8 activated; /* Used to prevent expiry before filter
118 * is attached
119 */
120 struct hlist_node filter_chain;
121};
122
123static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
124
75a353d4
EP		 125static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
126{
127 switch (ip_proto) {
128 case IPPROTO_UDP:
129 return MLX4_NET_TRANS_RULE_ID_UDP;
130 case IPPROTO_TCP:
131 return MLX4_NET_TRANS_RULE_ID_TCP;
132 default:
c3ca5205 133 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 134 }
135};
136
1eb8c695
AV		 137static void mlx4_en_filter_work(struct work_struct *work)
138{
139 struct mlx4_en_filter *filter = container_of(work,
140 struct mlx4_en_filter,
141 work);
142 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 143 struct mlx4_spec_list spec_tcp_udp = {
144 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 145 {
146 .tcp_udp = {
147 .dst_port = filter->dst_port,
148 .dst_port_msk = (__force __be16)-1,
149 .src_port = filter->src_port,
150 .src_port_msk = (__force __be16)-1,
151 },
152 },
153 };
154 struct mlx4_spec_list spec_ip = {
155 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
156 {
157 .ipv4 = {
158 .dst_ip = filter->dst_ip,
159 .dst_ip_msk = (__force __be32)-1,
160 .src_ip = filter->src_ip,
161 .src_ip_msk = (__force __be32)-1,
162 },
163 },
164 };
165 struct mlx4_spec_list spec_eth = {
166 .id = MLX4_NET_TRANS_RULE_ID_ETH,
167 };
168 struct mlx4_net_trans_rule rule = {
169 .list = LIST_HEAD_INIT(rule.list),
170 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
171 .exclusive = 1,
172 .allow_loopback = 1,
f9162539 173 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 174 .port = priv->port,
175 .priority = MLX4_DOMAIN_RFS,
176 };
177 int rc;
1eb8c695
AV		 178 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
179
c3ca5205 180 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 181 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
182 filter->ip_proto);
183 goto ignore;
184 }
1eb8c695
AV		 185 list_add_tail(&spec_eth.list, &rule.list);
186 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 187 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 188
1eb8c695 189 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 190 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 191 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
192
193 filter->activated = 0;
194
195 if (filter->reg_id) {
196 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
197 if (rc && rc != -ENOENT)
198 en_err(priv, "Error detaching flow. rc = %d\n", rc);
199 }
200
201 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
202 if (rc)
203 en_err(priv, "Error attaching flow. err = %d\n", rc);
204
75a353d4 205ignore:
1eb8c695
AV		 206 mlx4_en_filter_rfs_expire(priv);
207
208 filter->activated = 1;
209}
210
211static inline struct hlist_head *
212filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
213 __be16 src_port, __be16 dst_port)
214{
215 unsigned long l;
216 int bucket_idx;
217
218 l = (__force unsigned long)src_port |
219 ((__force unsigned long)dst_port << 2);
220 l ^= (__force unsigned long)(src_ip ^ dst_ip);
221
222 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
223
224 return &priv->filter_hash[bucket_idx];
225}
226
227static struct mlx4_en_filter *
228mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 229 __be32 dst_ip, u8 ip_proto, __be16 src_port,
230 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 231{
232 struct mlx4_en_filter *filter = NULL;
233
234 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
235 if (!filter)
236 return NULL;
237
238 filter->priv = priv;
239 filter->rxq_index = rxq_index;
240 INIT_WORK(&filter->work, mlx4_en_filter_work);
241
242 filter->src_ip = src_ip;
243 filter->dst_ip = dst_ip;
75a353d4 244 filter->ip_proto = ip_proto;
1eb8c695
AV		 245 filter->src_port = src_port;
246 filter->dst_port = dst_port;
247
248 filter->flow_id = flow_id;
249
ee64c0ee 250 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 251
252 list_add_tail(&filter->next, &priv->filters);
253 hlist_add_head(&filter->filter_chain,
254 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
255 dst_port));
256
257 return filter;
258}
259
260static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
261{
262 struct mlx4_en_priv *priv = filter->priv;
263 int rc;
264
265 list_del(&filter->next);
266
267 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
268 if (rc && rc != -ENOENT)
269 en_err(priv, "Error detaching flow. rc = %d\n", rc);
270
271 kfree(filter);
272}
273
274static inline struct mlx4_en_filter *
275mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 276 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 277{
1eb8c695
AV		 278 struct mlx4_en_filter *filter;
279 struct mlx4_en_filter *ret = NULL;
280
b67bfe0d 281 hlist_for_each_entry(filter,
1eb8c695
AV		 282 filter_hash_bucket(priv, src_ip, dst_ip,
283 src_port, dst_port),
284 filter_chain) {
285 if (filter->src_ip == src_ip &&
286 filter->dst_ip == dst_ip &&
75a353d4 287 filter->ip_proto == ip_proto &&
1eb8c695
AV		 288 filter->src_port == src_port &&
289 filter->dst_port == dst_port) {
290 ret = filter;
291 break;
292 }
293 }
294
295 return ret;
296}
297
298static int
299mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
300 u16 rxq_index, u32 flow_id)
301{
302 struct mlx4_en_priv *priv = netdev_priv(net_dev);
303 struct mlx4_en_filter *filter;
304 const struct iphdr *ip;
305 const __be16 *ports;
75a353d4 306 u8 ip_proto;
1eb8c695
AV		 307 __be32 src_ip;
308 __be32 dst_ip;
309 __be16 src_port;
310 __be16 dst_port;
311 int nhoff = skb_network_offset(skb);
312 int ret = 0;
313
314 if (skb->protocol != htons(ETH_P_IP))
315 return -EPROTONOSUPPORT;
316
317 ip = (const struct iphdr *)(skb->data + nhoff);
318 if (ip_is_fragment(ip))
319 return -EPROTONOSUPPORT;
320
75a353d4
EP		 321 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
322 return -EPROTONOSUPPORT;
1eb8c695
AV		 323 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
324
75a353d4 325 ip_proto = ip->protocol;
1eb8c695
AV		 326 src_ip = ip->saddr;
327 dst_ip = ip->daddr;
328 src_port = ports[0];
329 dst_port = ports[1];
330
1eb8c695 331 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 332 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
333 src_port, dst_port);
1eb8c695
AV		 334 if (filter) {
335 if (filter->rxq_index == rxq_index)
336 goto out;
337
338 filter->rxq_index = rxq_index;
339 } else {
340 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 341 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 342 src_port, dst_port, flow_id);
343 if (!filter) {
344 ret = -ENOMEM;
345 goto err;
346 }
347 }
348
349 queue_work(priv->mdev->workqueue, &filter->work);
350
351out:
352 ret = filter->id;
353err:
354 spin_unlock_bh(&priv->filters_lock);
355
356 return ret;
357}
358
41d942d5 359void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 360{
361 struct mlx4_en_filter *filter, *tmp;
362 LIST_HEAD(del_list);
363
364 spin_lock_bh(&priv->filters_lock);
365 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
366 list_move(&filter->next, &del_list);
367 hlist_del(&filter->filter_chain);
368 }
369 spin_unlock_bh(&priv->filters_lock);
370
371 list_for_each_entry_safe(filter, tmp, &del_list, next) {
372 cancel_work_sync(&filter->work);
373 mlx4_en_filter_free(filter);
374 }
375}
376
377static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
378{
379 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
380 LIST_HEAD(del_list);
381 int i = 0;
382
383 spin_lock_bh(&priv->filters_lock);
384 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
385 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
386 break;
387
388 if (filter->activated &&
389 !work_pending(&filter->work) &&
390 rps_may_expire_flow(priv->dev,
391 filter->rxq_index, filter->flow_id,
392 filter->id)) {
393 list_move(&filter->next, &del_list);
394 hlist_del(&filter->filter_chain);
395 } else
396 last_filter = filter;
397
398 i++;
399 }
400
401 if (last_filter && (&last_filter->next != priv->filters.next))
402 list_move(&priv->filters, &last_filter->next);
403
404 spin_unlock_bh(&priv->filters_lock);
405
406 list_for_each_entry_safe(filter, tmp, &del_list, next)
407 mlx4_en_filter_free(filter);
408}
409#endif
410
80d5c368
PM		 411static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
412 __be16 proto, u16 vid)
c27a02cd
YP		 413{
414 struct mlx4_en_priv *priv = netdev_priv(dev);
415 struct mlx4_en_dev *mdev = priv->mdev;
416 int err;
4c3eb3ca 417 int idx;
c27a02cd 418
f1b553fb 419 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 420
f1b553fb 421 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 422
423 /* Add VID to port VLAN filter */
424 mutex_lock(&mdev->state_lock);
425 if (mdev->device_up && priv->port_up) {
f1b553fb 426 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 427 if (err)
453a6082 428 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 429 }
4c3eb3ca 430 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 431 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 432 mutex_unlock(&mdev->state_lock);
4c3eb3ca 433
8e586137 434 return 0;
c27a02cd
YP		 435}
436
80d5c368
PM		 437static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
438 __be16 proto, u16 vid)
c27a02cd
YP		 439{
440 struct mlx4_en_priv *priv = netdev_priv(dev);
441 struct mlx4_en_dev *mdev = priv->mdev;
442 int err;
443
f1b553fb 444 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 445
f1b553fb 446 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 447
448 /* Remove VID from port VLAN filter */
449 mutex_lock(&mdev->state_lock);
2009d005 450 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 451
c27a02cd 452 if (mdev->device_up && priv->port_up) {
f1b553fb 453 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 454 if (err)
453a6082 455 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 456 }
457 mutex_unlock(&mdev->state_lock);
8e586137
JP		 458
459 return 0;
c27a02cd
YP		 460}
461
6bbb6d99
YB		 462static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
463{
bab6a9ea
YB		 464 int i;
465 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 466 dst_mac[i] = src_mac & 0xff;
467 src_mac >>= 8;
468 }
469 memset(&dst_mac[ETH_ALEN], 0, 2);
470}
471
837052d0
OG		 472
473static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
474 int qpn, u64 *reg_id)
475{
476 int err;
837052d0
OG		 477
478 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
479 return 0; /* do nothing */
480
b95089d0
OG		 481 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
482 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 483 if (err) {
484 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
485 return err;
486 }
487 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
488 return 0;
489}
490
491
16a10ffd
YB		 492static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
493 unsigned char *mac, int *qpn, u64 *reg_id)
494{
495 struct mlx4_en_dev *mdev = priv->mdev;
496 struct mlx4_dev *dev = mdev->dev;
497 int err;
498
499 switch (dev->caps.steering_mode) {
500 case MLX4_STEERING_MODE_B0: {
501 struct mlx4_qp qp;
502 u8 gid[16] = {0};
503
504 qp.qpn = *qpn;
505 memcpy(&gid[10], mac, ETH_ALEN);
506 gid[5] = priv->port;
507
508 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
509 break;
510 }
511 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
512 struct mlx4_spec_list spec_eth = { {NULL} };
513 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
514
515 struct mlx4_net_trans_rule rule = {
516 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
517 .exclusive = 0,
518 .allow_loopback = 1,
f9162539 519 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 520 .priority = MLX4_DOMAIN_NIC,
521 };
522
523 rule.port = priv->port;
524 rule.qpn = *qpn;
525 INIT_LIST_HEAD(&rule.list);
526
527 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
528 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
529 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
530 list_add_tail(&spec_eth.list, &rule.list);
531
532 err = mlx4_flow_attach(dev, &rule, reg_id);
533 break;
534 }
535 default:
536 return -EINVAL;
537 }
538 if (err)
539 en_warn(priv, "Failed Attaching Unicast\n");
540
541 return err;
542}
543
544static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
545 unsigned char *mac, int qpn, u64 reg_id)
546{
547 struct mlx4_en_dev *mdev = priv->mdev;
548 struct mlx4_dev *dev = mdev->dev;
549
550 switch (dev->caps.steering_mode) {
551 case MLX4_STEERING_MODE_B0: {
552 struct mlx4_qp qp;
553 u8 gid[16] = {0};
554
555 qp.qpn = qpn;
556 memcpy(&gid[10], mac, ETH_ALEN);
557 gid[5] = priv->port;
558
559 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
560 break;
561 }
562 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
563 mlx4_flow_detach(dev, reg_id);
564 break;
565 }
566 default:
567 en_err(priv, "Invalid steering mode.\n");
568 }
569}
570
571static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
572{
573 struct mlx4_en_dev *mdev = priv->mdev;
574 struct mlx4_dev *dev = mdev->dev;
575 struct mlx4_mac_entry *entry;
576 int index = 0;
577 int err = 0;
c2a3d4b4 578 u64 reg_id = 0;
16a10ffd 579 int *qpn = &priv->base_qpn;
9813337a 580 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 581
582 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
583 priv->dev->dev_addr);
584 index = mlx4_register_mac(dev, priv->port, mac);
585 if (index < 0) {
586 err = index;
587 en_err(priv, "Failed adding MAC: %pM\n",
588 priv->dev->dev_addr);
589 return err;
590 }
591
592 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
593 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
594 *qpn = base_qpn + index;
595 return 0;
596 }
597
d57febe1 598 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP);
16a10ffd
YB		 599 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
600 if (err) {
601 en_err(priv, "Failed to reserve qp for mac registration\n");
602 goto qp_err;
603 }
604
605 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
606 if (err)
607 goto steer_err;
608
9ba75fb0
WY		 609 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
610 &priv->tunnel_reg_id);
611 if (err)
837052d0
OG		 612 goto tunnel_err;
613
16a10ffd
YB		 614 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
615 if (!entry) {
616 err = -ENOMEM;
617 goto alloc_err;
618 }
619 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
b94901f3 620 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
16a10ffd
YB		 621 entry->reg_id = reg_id;
622
c07cb4b0
YB		 623 hlist_add_head_rcu(&entry->hlist,
624 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 625
c07cb4b0 626 return 0;
16a10ffd
YB		 627
628alloc_err:
837052d0
OG		 629 if (priv->tunnel_reg_id)
630 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
631tunnel_err:
16a10ffd
YB		 632 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
633
634steer_err:
635 mlx4_qp_release_range(dev, *qpn, 1);
636
637qp_err:
638 mlx4_unregister_mac(dev, priv->port, mac);
639 return err;
640}
641
642static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
643{
644 struct mlx4_en_dev *mdev = priv->mdev;
645 struct mlx4_dev *dev = mdev->dev;
16a10ffd 646 int qpn = priv->base_qpn;
83a5a6ce 647 u64 mac;
16a10ffd 648
83a5a6ce 649 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
9813337a 650 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 651 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
652 priv->dev->dev_addr);
653 mlx4_unregister_mac(dev, priv->port, mac);
654 } else {
c07cb4b0 655 struct mlx4_mac_entry *entry;
b67bfe0d 656 struct hlist_node *tmp;
c07cb4b0 657 struct hlist_head *bucket;
83a5a6ce 658 unsigned int i;
c07cb4b0 659
83a5a6ce
YB		 660 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
661 bucket = &priv->mac_hash[i];
662 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
9813337a 663 mac = mlx4_mac_to_u64(entry->mac);
83a5a6ce
YB		 664 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
665 entry->mac);
c07cb4b0
YB		 666 mlx4_en_uc_steer_release(priv, entry->mac,
667 qpn, entry->reg_id);
c07cb4b0 668
83a5a6ce 669 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB		 670 hlist_del_rcu(&entry->hlist);
671 kfree_rcu(entry, rcu);
c07cb4b0 672 }
16a10ffd 673 }
83a5a6ce 674
837052d0
OG		 675 if (priv->tunnel_reg_id) {
676 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
677 priv->tunnel_reg_id = 0;
678 }
679
83a5a6ce
YB		 680 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
681 priv->port, qpn);
682 mlx4_qp_release_range(dev, qpn, 1);
683 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 684 }
685}
686
687static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 688 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 689{
690 struct mlx4_en_dev *mdev = priv->mdev;
691 struct mlx4_dev *dev = mdev->dev;
16a10ffd 692 int err = 0;
9813337a 693 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 694
695 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 696 struct hlist_head *bucket;
697 unsigned int mac_hash;
698 struct mlx4_mac_entry *entry;
b67bfe0d 699 struct hlist_node *tmp;
9813337a 700 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 701
702 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 703 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 704 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
705 mlx4_en_uc_steer_release(priv, entry->mac,
706 qpn, entry->reg_id);
707 mlx4_unregister_mac(dev, priv->port,
708 prev_mac_u64);
709 hlist_del_rcu(&entry->hlist);
710 synchronize_rcu();
711 memcpy(entry->mac, new_mac, ETH_ALEN);
712 entry->reg_id = 0;
713 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
714 hlist_add_head_rcu(&entry->hlist,
715 &priv->mac_hash[mac_hash]);
716 mlx4_register_mac(dev, priv->port, new_mac_u64);
717 err = mlx4_en_uc_steer_add(priv, new_mac,
718 &qpn,
719 &entry->reg_id);
2a2083f7
OG		 720 if (err)
721 return err;
722 if (priv->tunnel_reg_id) {
723 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
724 priv->tunnel_reg_id = 0;
725 }
726 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
727 &priv->tunnel_reg_id);
c07cb4b0
YB		 728 return err;
729 }
730 }
731 return -EINVAL;
16a10ffd
YB		 732 }
733
734 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
735}
736
2695bab2
NO		 737static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
738 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 739{
c27a02cd
YP		 740 int err = 0;
741
c27a02cd
YP		 742 if (priv->port_up) {
743 /* Remove old MAC and insert the new one */
16a10ffd 744 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 745 new_mac, priv->current_mac);
c27a02cd 746 if (err)
453a6082 747 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 748 } else
48e551ff 749 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 750
2695bab2
NO		 751 if (!err)
752 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 753
bfa8ab47
YB		 754 return err;
755}
756
757static int mlx4_en_set_mac(struct net_device *dev, void *addr)
758{
759 struct mlx4_en_priv *priv = netdev_priv(dev);
760 struct mlx4_en_dev *mdev = priv->mdev;
761 struct sockaddr *saddr = addr;
2695bab2 762 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 763 int err;
764
765 if (!is_valid_ether_addr(saddr->sa_data))
766 return -EADDRNOTAVAIL;
767
bfa8ab47 768 mutex_lock(&mdev->state_lock);
2695bab2
NO		 769 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
770 err = mlx4_en_do_set_mac(priv, new_mac);
771 if (!err)
772 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
c27a02cd 773 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 774
775 return err;
c27a02cd
YP		 776}
777
778static void mlx4_en_clear_list(struct net_device *dev)
779{
780 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 781 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 782
6d199937
YP		 783 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
784 list_del(&mc_to_del->list);
785 kfree(mc_to_del);
786 }
c27a02cd
YP		 787}
788
789static void mlx4_en_cache_mclist(struct net_device *dev)
790{
791 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 792 struct netdev_hw_addr *ha;
6d199937 793 struct mlx4_en_mc_list *tmp;
ff6e2163 794
0e03567a 795 mlx4_en_clear_list(dev);
6d199937
YP		 796 netdev_for_each_mc_addr(ha, dev) {
797 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
798 if (!tmp) {
6d199937
YP		 799 mlx4_en_clear_list(dev);
800 return;
801 }
802 memcpy(tmp->addr, ha->addr, ETH_ALEN);
803 list_add_tail(&tmp->list, &priv->mc_list);
804 }
c27a02cd
YP		 805}
806
6d199937
YP		 807static void update_mclist_flags(struct mlx4_en_priv *priv,
808 struct list_head *dst,
809 struct list_head *src)
810{
811 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
812 bool found;
813
814 /* Find all the entries that should be removed from dst,
815 * These are the entries that are not found in src
816 */
817 list_for_each_entry(dst_tmp, dst, list) {
818 found = false;
819 list_for_each_entry(src_tmp, src, list) {
c0623e58 820 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 821 found = true;
822 break;
823 }
824 }
825 if (!found)
826 dst_tmp->action = MCLIST_REM;
827 }
828
829 /* Add entries that exist in src but not in dst
830 * mark them as need to add
831 */
832 list_for_each_entry(src_tmp, src, list) {
833 found = false;
834 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 835 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 836 dst_tmp->action = MCLIST_NONE;
837 found = true;
838 break;
839 }
840 }
841 if (!found) {
14f8dc49
JP		 842 new_mc = kmemdup(src_tmp,
843 sizeof(struct mlx4_en_mc_list),
6d199937 844 GFP_KERNEL);
14f8dc49 845 if (!new_mc)
6d199937 846 return;
14f8dc49 847
6d199937
YP		 848 new_mc->action = MCLIST_ADD;
849 list_add_tail(&new_mc->list, dst);
850 }
851 }
852}
c27a02cd 853
0eb74fdd 854static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 855{
856 struct mlx4_en_priv *priv = netdev_priv(dev);
857
858 if (!priv->port_up)
859 return;
860
0eb74fdd 861 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 862}
863
0eb74fdd
YB		 864static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
865 struct mlx4_en_dev *mdev)
c27a02cd 866{
c96d97f4 867 int err = 0;
c27a02cd 868
0eb74fdd 869 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 870 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 871 en_warn(priv, "Entering promiscuous mode\n");
872 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 873
0eb74fdd 874 /* Enable promiscouos mode */
c96d97f4 875 switch (mdev->dev->caps.steering_mode) {
592e49dd 876 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 877 err = mlx4_flow_steer_promisc_add(mdev->dev,
878 priv->port,
879 priv->base_qpn,
f9162539 880 MLX4_FS_ALL_DEFAULT);
592e49dd 881 if (err)
0eb74fdd
YB		 882 en_err(priv, "Failed enabling promiscuous mode\n");
883 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 884 break;
885
c96d97f4 886 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 887 err = mlx4_unicast_promisc_add(mdev->dev,
888 priv->base_qpn,
889 priv->port);
c96d97f4 890 if (err)
0eb74fdd
YB		 891 en_err(priv, "Failed enabling unicast promiscuous mode\n");
892
893 /* Add the default qp number as multicast
894 * promisc
895 */
896 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
897 err = mlx4_multicast_promisc_add(mdev->dev,
898 priv->base_qpn,
899 priv->port);
c96d97f4 900 if (err)
0eb74fdd
YB		 901 en_err(priv, "Failed enabling multicast promiscuous mode\n");
902 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 903 }
904 break;
c27a02cd 905
c96d97f4
HHZ		 906 case MLX4_STEERING_MODE_A0:
907 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
908 priv->port,
0eb74fdd
YB		 909 priv->base_qpn,
910 1);
1679200f 911 if (err)
0eb74fdd 912 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 913 break;
1679200f
YP		 914 }
915
0eb74fdd
YB		 916 /* Disable port multicast filter (unconditionally) */
917 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
918 0, MLX4_MCAST_DISABLE);
919 if (err)
920 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 921 }
922}
923
924static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
925 struct mlx4_en_dev *mdev)
926{
927 int err = 0;
928
929 if (netif_msg_rx_status(priv))
930 en_warn(priv, "Leaving promiscuous mode\n");
931 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
932
933 /* Disable promiscouos mode */
934 switch (mdev->dev->caps.steering_mode) {
935 case MLX4_STEERING_MODE_DEVICE_MANAGED:
936 err = mlx4_flow_steer_promisc_remove(mdev->dev,
937 priv->port,
f9162539 938 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 939 if (err)
940 en_err(priv, "Failed disabling promiscuous mode\n");
941 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
942 break;
943
944 case MLX4_STEERING_MODE_B0:
945 err = mlx4_unicast_promisc_remove(mdev->dev,
946 priv->base_qpn,
947 priv->port);
948 if (err)
949 en_err(priv, "Failed disabling unicast promiscuous mode\n");
950 /* Disable Multicast promisc */
951 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
952 err = mlx4_multicast_promisc_remove(mdev->dev,
953 priv->base_qpn,
954 priv->port);
955 if (err)
956 en_err(priv, "Failed disabling multicast promiscuous mode\n");
957 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
958 }
959 break;
960
961 case MLX4_STEERING_MODE_A0:
962 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
963 priv->port,
964 priv->base_qpn, 0);
965 if (err)
966 en_err(priv, "Failed disabling promiscuous mode\n");
967 break;
c27a02cd 968 }
0eb74fdd
YB		 969}
970
971static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
972 struct net_device *dev,
973 struct mlx4_en_dev *mdev)
974{
975 struct mlx4_en_mc_list *mclist, *tmp;
976 u64 mcast_addr = 0;
977 u8 mc_list[16] = {0};
978 int err = 0;
979
c27a02cd
YP		 980 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
981 if (dev->flags & IFF_ALLMULTI) {
982 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
983 0, MLX4_MCAST_DISABLE);
984 if (err)
453a6082 985 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 986
987 /* Add the default qp number as multicast promisc */
988 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 989 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 990 case MLX4_STEERING_MODE_DEVICE_MANAGED:
991 err = mlx4_flow_steer_promisc_add(mdev->dev,
992 priv->port,
993 priv->base_qpn,
f9162539 994 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 995 break;
996
c96d97f4
HHZ		 997 case MLX4_STEERING_MODE_B0:
998 err = mlx4_multicast_promisc_add(mdev->dev,
999 priv->base_qpn,
1000 priv->port);
1001 break;
1002
1003 case MLX4_STEERING_MODE_A0:
1004 break;
1005 }
1679200f
YP		 1006 if (err)
1007 en_err(priv, "Failed entering multicast promisc mode\n");
1008 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1009 }
c27a02cd 1010 } else {
1679200f
YP		 1011 /* Disable Multicast promisc */
1012 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1013 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1014 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1015 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1016 priv->port,
f9162539 1017 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1018 break;
1019
c96d97f4
HHZ		 1020 case MLX4_STEERING_MODE_B0:
1021 err = mlx4_multicast_promisc_remove(mdev->dev,
1022 priv->base_qpn,
1023 priv->port);
1024 break;
1025
1026 case MLX4_STEERING_MODE_A0:
1027 break;
1028 }
1679200f 1029 if (err)
25985edc 1030 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1031 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1032 }
ff6e2163 1033
c27a02cd
YP		 1034 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1035 0, MLX4_MCAST_DISABLE);
1036 if (err)
453a6082 1037 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1038
1039 /* Flush mcast filter and init it with broadcast address */
1040 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1041 1, MLX4_MCAST_CONFIG);
1042
1043 /* Update multicast list - we cache all addresses so they won't
1044 * change while HW is updated holding the command semaphor */
dbd501a8 1045 netif_addr_lock_bh(dev);
c27a02cd 1046 mlx4_en_cache_mclist(dev);
dbd501a8 1047 netif_addr_unlock_bh(dev);
6d199937 1048 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 1049 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 1050 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1051 mcast_addr, 0, MLX4_MCAST_CONFIG);
1052 }
1053 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1054 0, MLX4_MCAST_ENABLE);
1055 if (err)
453a6082 1056 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1057
1058 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1059 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1060 if (mclist->action == MCLIST_REM) {
1061 /* detach this address and delete from list */
1062 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1063 mc_list[5] = priv->port;
1064 err = mlx4_multicast_detach(mdev->dev,
1065 &priv->rss_map.indir_qp,
1066 mc_list,
0ff1fb65
HHZ		 1067 MLX4_PROT_ETH,
1068 mclist->reg_id);
6d199937
YP		 1069 if (err)
1070 en_err(priv, "Fail to detach multicast address\n");
1071
837052d0
OG		 1072 if (mclist->tunnel_reg_id) {
1073 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1074 if (err)
1075 en_err(priv, "Failed to detach multicast address\n");
1076 }
1077
6d199937
YP		 1078 /* remove from list */
1079 list_del(&mclist->list);
1080 kfree(mclist);
9c64508a 1081 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1082 /* attach the address */
1083 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1084 /* needed for B0 steering support */
6d199937
YP		 1085 mc_list[5] = priv->port;
1086 err = mlx4_multicast_attach(mdev->dev,
1087 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1088 mc_list,
1089 priv->port, 0,
1090 MLX4_PROT_ETH,
1091 &mclist->reg_id);
6d199937
YP		 1092 if (err)
1093 en_err(priv, "Fail to attach multicast address\n");
1094
837052d0
OG		 1095 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1096 &mclist->tunnel_reg_id);
1097 if (err)
1098 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1099 }
1100 }
c27a02cd 1101 }
0eb74fdd
YB		 1102}
1103
cc5387f7
YB		 1104static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1105 struct net_device *dev,
1106 struct mlx4_en_dev *mdev)
1107{
1108 struct netdev_hw_addr *ha;
1109 struct mlx4_mac_entry *entry;
b67bfe0d 1110 struct hlist_node *tmp;
cc5387f7
YB		 1111 bool found;
1112 u64 mac;
1113 int err = 0;
1114 struct hlist_head *bucket;
1115 unsigned int i;
1116 int removed = 0;
1117 u32 prev_flags;
1118
1119 /* Note that we do not need to protect our mac_hash traversal with rcu,
1120 * since all modification code is protected by mdev->state_lock
1121 */
1122
1123 /* find what to remove */
1124 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1125 bucket = &priv->mac_hash[i];
b67bfe0d 1126 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1127 found = false;
1128 netdev_for_each_uc_addr(ha, dev) {
1129 if (ether_addr_equal_64bits(entry->mac,
1130 ha->addr)) {
1131 found = true;
1132 break;
1133 }
1134 }
1135
1136 /* MAC address of the port is not in uc list */
2695bab2
NO		 1137 if (ether_addr_equal_64bits(entry->mac,
1138 priv->current_mac))
cc5387f7
YB		 1139 found = true;
1140
1141 if (!found) {
9813337a 1142 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1143 mlx4_en_uc_steer_release(priv, entry->mac,
1144 priv->base_qpn,
1145 entry->reg_id);
1146 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1147
1148 hlist_del_rcu(&entry->hlist);
1149 kfree_rcu(entry, rcu);
1150 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1151 entry->mac, priv->port);
1152 ++removed;
1153 }
1154 }
1155 }
1156
1157 /* if we didn't remove anything, there is no use in trying to add
1158 * again once we are in a forced promisc mode state
1159 */
1160 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1161 return;
1162
1163 prev_flags = priv->flags;
1164 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1165
1166 /* find what to add */
1167 netdev_for_each_uc_addr(ha, dev) {
1168 found = false;
1169 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1170 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1171 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1172 found = true;
1173 break;
1174 }
1175 }
1176
1177 if (!found) {
1178 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1179 if (!entry) {
1180 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1181 ha->addr, priv->port);
1182 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1183 break;
1184 }
9813337a 1185 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1186 memcpy(entry->mac, ha->addr, ETH_ALEN);
1187 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1188 if (err < 0) {
1189 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1190 ha->addr, priv->port, err);
1191 kfree(entry);
1192 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1193 break;
1194 }
1195 err = mlx4_en_uc_steer_add(priv, ha->addr,
1196 &priv->base_qpn,
1197 &entry->reg_id);
1198 if (err) {
1199 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1200 ha->addr, priv->port, err);
1201 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1202 kfree(entry);
1203 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1204 break;
1205 } else {
1206 unsigned int mac_hash;
1207 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1208 ha->addr, priv->port);
1209 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1210 bucket = &priv->mac_hash[mac_hash];
1211 hlist_add_head_rcu(&entry->hlist, bucket);
1212 }
1213 }
1214 }
1215
1216 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1217 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1218 priv->port);
1219 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1220 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1221 priv->port);
1222 }
1223}
1224
0eb74fdd
YB		 1225static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1226{
1227 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1228 rx_mode_task);
1229 struct mlx4_en_dev *mdev = priv->mdev;
1230 struct net_device *dev = priv->dev;
1231
1232 mutex_lock(&mdev->state_lock);
1233 if (!mdev->device_up) {
1234 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1235 goto out;
1236 }
1237 if (!priv->port_up) {
1238 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1239 goto out;
1240 }
1241
1242 if (!netif_carrier_ok(dev)) {
1243 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1244 if (priv->port_state.link_state) {
1245 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1246 netif_carrier_on(dev);
1247 en_dbg(LINK, priv, "Link Up\n");
1248 }
1249 }
1250 }
1251
cc5387f7
YB		 1252 if (dev->priv_flags & IFF_UNICAST_FLT)
1253 mlx4_en_do_uc_filter(priv, dev, mdev);
1254
0eb74fdd 1255 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1256 if ((dev->flags & IFF_PROMISC) ||
1257 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1258 mlx4_en_set_promisc_mode(priv, mdev);
1259 goto out;
1260 }
1261
1262 /* Not in promiscuous mode */
1263 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1264 mlx4_en_clear_promisc_mode(priv, mdev);
1265
1266 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1267out:
1268 mutex_unlock(&mdev->state_lock);
1269}
1270
1271#ifdef CONFIG_NET_POLL_CONTROLLER
1272static void mlx4_en_netpoll(struct net_device *dev)
1273{
1274 struct mlx4_en_priv *priv = netdev_priv(dev);
1275 struct mlx4_en_cq *cq;
c27a02cd
YP		 1276 int i;
1277
1278 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1279 cq = priv->rx_cq[i];
c98235cb 1280 napi_schedule(&cq->napi);
c27a02cd
YP		 1281 }
1282}
1283#endif
1284
1285static void mlx4_en_tx_timeout(struct net_device *dev)
1286{
1287 struct mlx4_en_priv *priv = netdev_priv(dev);
1288 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1289 int i;
c27a02cd
YP		 1290
1291 if (netif_msg_timer(priv))
453a6082 1292 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1293
b944ebec
YP		 1294 for (i = 0; i < priv->tx_ring_num; i++) {
1295 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1296 continue;
1297 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1298 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1299 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1300 }
1301
1e338db5 1302 priv->port_stats.tx_timeout++;
453a6082 1303 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1304 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1305}
1306
1307
1308static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1309{
1310 struct mlx4_en_priv *priv = netdev_priv(dev);
1311
1312 spin_lock_bh(&priv->stats_lock);
1313 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1314 spin_unlock_bh(&priv->stats_lock);
1315
1316 return &priv->ret_stats;
1317}
1318
1319static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1320{
c27a02cd
YP		 1321 struct mlx4_en_cq *cq;
1322 int i;
1323
1324 /* If we haven't received a specific coalescing setting
98a1708d 1325 * (module param), we set the moderation parameters as follows:
c27a02cd 1326 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1327 * satisfy our coalescing target.
c27a02cd
YP		 1328 * - moder_time is set to a fixed value.
1329 */
3db36fb2 1330 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1331 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1332 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1333 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1334 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1335 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1336
1337 /* Setup cq moderation params */
1338 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1339 cq = priv->rx_cq[i];
c27a02cd
YP		 1340 cq->moder_cnt = priv->rx_frames;
1341 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1342 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1343 priv->last_moder_packets[i] = 0;
1344 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1345 }
1346
1347 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1348 cq = priv->tx_cq[i];
a19a848a
YP		 1349 cq->moder_cnt = priv->tx_frames;
1350 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1351 }
1352
1353 /* Reset auto-moderation params */
1354 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1355 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1356 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1357 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1358 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1359 priv->adaptive_rx_coal = 1;
c27a02cd 1360 priv->last_moder_jiffies = 0;
c27a02cd 1361 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1362}
1363
1364static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1365{
1366 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1367 struct mlx4_en_cq *cq;
1368 unsigned long packets;
1369 unsigned long rate;
1370 unsigned long avg_pkt_size;
1371 unsigned long rx_packets;
1372 unsigned long rx_bytes;
c27a02cd
YP		 1373 unsigned long rx_pkt_diff;
1374 int moder_time;
6b4d8d9f 1375 int ring, err;
c27a02cd
YP		 1376
1377 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1378 return;
1379
6b4d8d9f
AG		 1380 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1381 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1382 rx_packets = priv->rx_ring[ring]->packets;
1383 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1384 spin_unlock_bh(&priv->stats_lock);
1385
1386 rx_pkt_diff = ((unsigned long) (rx_packets -
1387 priv->last_moder_packets[ring]));
1388 packets = rx_pkt_diff;
1389 rate = packets * HZ / period;
1390 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1391 priv->last_moder_bytes[ring])) / packets : 0;
1392
1393 /* Apply auto-moderation only when packet rate
1394 * exceeds a rate that it matters */
1395 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1396 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1397 if (rate < priv->pkt_rate_low)
1398 moder_time = priv->rx_usecs_low;
1399 else if (rate > priv->pkt_rate_high)
1400 moder_time = priv->rx_usecs_high;
1401 else
1402 moder_time = (rate - priv->pkt_rate_low) *
1403 (priv->rx_usecs_high - priv->rx_usecs_low) /
1404 (priv->pkt_rate_high - priv->pkt_rate_low) +
1405 priv->rx_usecs_low;
6b4d8d9f
AG		 1406 } else {
1407 moder_time = priv->rx_usecs_low;
c27a02cd 1408 }
c27a02cd 1409
6b4d8d9f
AG		 1410 if (moder_time != priv->last_moder_time[ring]) {
1411 priv->last_moder_time[ring] = moder_time;
41d942d5 1412 cq = priv->rx_cq[ring];
c27a02cd 1413 cq->moder_time = moder_time;
a1c6693a 1414 cq->moder_cnt = priv->rx_frames;
c27a02cd 1415 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1416 if (err)
48e551ff
YB		 1417 en_err(priv, "Failed modifying moderation for cq:%d\n",
1418 ring);
c27a02cd 1419 }
6b4d8d9f
AG		 1420 priv->last_moder_packets[ring] = rx_packets;
1421 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1422 }
1423
c27a02cd
YP		 1424 priv->last_moder_jiffies = jiffies;
1425}
1426
1427static void mlx4_en_do_get_stats(struct work_struct *work)
1428{
bf6aede7 1429 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1430 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1431 stats_task);
1432 struct mlx4_en_dev *mdev = priv->mdev;
1433 int err;
1434
c27a02cd
YP		 1435 mutex_lock(&mdev->state_lock);
1436 if (mdev->device_up) {
6123db2e
JM		 1437 if (priv->port_up) {
1438 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1439 if (err)
1440 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1441
c27a02cd 1442 mlx4_en_auto_moderation(priv);
6123db2e 1443 }
c27a02cd
YP		 1444
1445 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1446 }
d7e1a487 1447 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1448 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1449 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1450 }
c27a02cd
YP		 1451 mutex_unlock(&mdev->state_lock);
1452}
1453
b6c39bfc
AV		 1454/* mlx4_en_service_task - Run service task for tasks that needed to be done
1455 * periodically
1456 */
1457static void mlx4_en_service_task(struct work_struct *work)
1458{
1459 struct delayed_work *delay = to_delayed_work(work);
1460 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1461 service_task);
1462 struct mlx4_en_dev *mdev = priv->mdev;
1463
1464 mutex_lock(&mdev->state_lock);
1465 if (mdev->device_up) {
dc8142ea
AV		 1466 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1467 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc
AV		 1468
1469 queue_delayed_work(mdev->workqueue, &priv->service_task,
1470 SERVICE_TASK_DELAY);
1471 }
1472 mutex_unlock(&mdev->state_lock);
1473}
1474
c27a02cd
YP		 1475static void mlx4_en_linkstate(struct work_struct *work)
1476{
1477 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1478 linkstate_task);
1479 struct mlx4_en_dev *mdev = priv->mdev;
1480 int linkstate = priv->link_state;
1481
1482 mutex_lock(&mdev->state_lock);
1483 /* If observable port state changed set carrier state and
1484 * report to system log */
1485 if (priv->last_link_state != linkstate) {
1486 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1487 en_info(priv, "Link Down\n");
c27a02cd
YP		 1488 netif_carrier_off(priv->dev);
1489 } else {
e5cc44b2 1490 en_info(priv, "Link Up\n");
c27a02cd
YP		 1491 netif_carrier_on(priv->dev);
1492 }
1493 }
1494 priv->last_link_state = linkstate;
1495 mutex_unlock(&mdev->state_lock);
1496}
1497
9e311e77
YA		 1498static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1499{
1500 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1501 int numa_node = priv->mdev->dev->numa_node;
1502 int ret = 0;
1503
1504 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1505 return -ENOMEM;
1506
1507 ret = cpumask_set_cpu_local_first(ring_idx, numa_node,
1508 ring->affinity_mask);
1509 if (ret)
1510 free_cpumask_var(ring->affinity_mask);
1511
1512 return ret;
1513}
1514
1515static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1516{
1517 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1518}
c27a02cd 1519
18cc42a3 1520int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1521{
1522 struct mlx4_en_priv *priv = netdev_priv(dev);
1523 struct mlx4_en_dev *mdev = priv->mdev;
1524 struct mlx4_en_cq *cq;
1525 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1526 int rx_index = 0;
1527 int tx_index = 0;
c27a02cd
YP		 1528 int err = 0;
1529 int i;
1530 int j;
1679200f 1531 u8 mc_list[16] = {0};
c27a02cd
YP		 1532
1533 if (priv->port_up) {
453a6082 1534 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1535 return 0;
1536 }
1537
6d199937
YP		 1538 INIT_LIST_HEAD(&priv->mc_list);
1539 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1540 INIT_LIST_HEAD(&priv->ethtool_list);
1541 memset(&priv->ethtool_rules[0], 0,
1542 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1543
c27a02cd
YP		 1544 /* Calculate Rx buf size */
1545 dev->mtu = min(dev->mtu, priv->max_mtu);
1546 mlx4_en_calc_rx_buf(dev);
453a6082 1547 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1548
c27a02cd 1549 /* Configure rx cq's and rings */
38aab07c
YP		 1550 err = mlx4_en_activate_rx_rings(priv);
1551 if (err) {
453a6082 1552 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1553 return err;
1554 }
c27a02cd 1555 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1556 cq = priv->rx_cq[i];
c27a02cd 1557
9e77a2b8
AV		 1558 mlx4_en_cq_init_lock(cq);
1559
9e311e77
YA		 1560 err = mlx4_en_init_affinity_hint(priv, i);
1561 if (err) {
1562 en_err(priv, "Failed preparing IRQ affinity hint\n");
1563 goto cq_err;
1564 }
1565
76532d0c 1566 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1567 if (err) {
453a6082 1568 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1569 mlx4_en_free_affinity_hint(priv, i);
a4233304 1570 goto cq_err;
c27a02cd 1571 }
c3f2511f
IS		 1572
1573 for (j = 0; j < cq->size; j++) {
1574 struct mlx4_cqe *cqe = NULL;
1575
1576 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1577 priv->cqe_factor;
1578 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1579 }
1580
c27a02cd
YP		 1581 err = mlx4_en_set_cq_moder(priv, cq);
1582 if (err) {
1a91de28 1583 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1584 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1585 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1586 goto cq_err;
1587 }
1588 mlx4_en_arm_cq(priv, cq);
41d942d5 1589 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1590 ++rx_index;
1591 }
1592
ffe455ad
EE		 1593 /* Set qp number */
1594 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1595 err = mlx4_en_get_qp(priv);
1679200f 1596 if (err) {
ffe455ad 1597 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1598 goto cq_err;
1599 }
1600 mdev->mac_removed[priv->port] = 0;
1601
c27a02cd
YP		 1602 err = mlx4_en_config_rss_steer(priv);
1603 if (err) {
453a6082 1604 en_err(priv, "Failed configuring rss steering\n");
1679200f 1605 goto mac_err;
c27a02cd
YP		 1606 }
1607
cabdc8ee
HHZ		 1608 err = mlx4_en_create_drop_qp(priv);
1609 if (err)
1610 goto rss_err;
1611
c27a02cd
YP		 1612 /* Configure tx cq's and rings */
1613 for (i = 0; i < priv->tx_ring_num; i++) {
1614 /* Configure cq */
41d942d5 1615 cq = priv->tx_cq[i];
76532d0c 1616 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1617 if (err) {
453a6082 1618 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1619 goto tx_err;
1620 }
1621 err = mlx4_en_set_cq_moder(priv, cq);
1622 if (err) {
1a91de28 1623 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd
YP		 1624 mlx4_en_deactivate_cq(priv, cq);
1625 goto tx_err;
1626 }
453a6082 1627 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1628 cq->buf->wqe_index = cpu_to_be16(0xffff);
1629
1630 /* Configure ring */
41d942d5 1631 tx_ring = priv->tx_ring[i];
0e98b523 1632 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1633 i / priv->num_tx_rings_p_up);
c27a02cd 1634 if (err) {
453a6082 1635 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1636 mlx4_en_deactivate_cq(priv, cq);
1637 goto tx_err;
1638 }
5b263f53 1639 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1640
1641 /* Arm CQ for TX completions */
1642 mlx4_en_arm_cq(priv, cq);
1643
c27a02cd
YP		 1644 /* Set initial ownership of all Tx TXBBs to SW (1) */
1645 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1646 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1647 ++tx_index;
1648 }
1649
1650 /* Configure port */
1651 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1652 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1653 priv->prof->tx_pause,
1654 priv->prof->tx_ppp,
1655 priv->prof->rx_pause,
1656 priv->prof->rx_ppp);
c27a02cd 1657 if (err) {
48e551ff
YB		 1658 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1659 priv->port, err);
c27a02cd
YP		 1660 goto tx_err;
1661 }
1662 /* Set default qp number */
1663 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1664 if (err) {
453a6082 1665 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1666 goto tx_err;
1667 }
c27a02cd 1668
837052d0 1669 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1670 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1671 if (err) {
1672 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1673 err);
1674 goto tx_err;
1675 }
1676 }
1677
c27a02cd 1678 /* Init port */
453a6082 1679 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1680 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1681 if (err) {
453a6082 1682 en_err(priv, "Failed Initializing port\n");
1679200f 1683 goto tx_err;
c27a02cd
YP		 1684 }
1685
1679200f
YP		 1686 /* Attach rx QP to bradcast address */
1687 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1688 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1689 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1690 priv->port, 0, MLX4_PROT_ETH,
1691 &priv->broadcast_id))
1679200f
YP		 1692 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1693
b5845f98
HX		 1694 /* Must redo promiscuous mode setup. */
1695 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1696
c27a02cd 1697 /* Schedule multicast task to populate multicast list */
0eb74fdd 1698 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1699
93ece0c1
EE		 1700 mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap);
1701
a66132f3 1702#ifdef CONFIG_MLX4_EN_VXLAN
9737c6ab 1703 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1 1704 vxlan_get_rx_port(dev);
a66132f3 1705#endif
c27a02cd 1706 priv->port_up = true;
a11faac7 1707 netif_tx_start_all_queues(dev);
3484aac1
AV		 1708 netif_device_attach(dev);
1709
c27a02cd
YP		 1710 return 0;
1711
c27a02cd
YP		 1712tx_err:
1713 while (tx_index--) {
41d942d5
EE		 1714 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1715 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1716 }
cabdc8ee
HHZ		 1717 mlx4_en_destroy_drop_qp(priv);
1718rss_err:
c27a02cd 1719 mlx4_en_release_rss_steer(priv);
1679200f 1720mac_err:
16a10ffd 1721 mlx4_en_put_qp(priv);
c27a02cd 1722cq_err:
9e311e77 1723 while (rx_index--) {
41d942d5 1724 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
9e311e77
YA		 1725 mlx4_en_free_affinity_hint(priv, i);
1726 }
38aab07c 1727 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1728 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1729
1730 return err; /* need to close devices */
1731}
1732
1733
3484aac1 1734void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1735{
1736 struct mlx4_en_priv *priv = netdev_priv(dev);
1737 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1738 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1739 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1740 int i;
1679200f 1741 u8 mc_list[16] = {0};
c27a02cd
YP		 1742
1743 if (!priv->port_up) {
453a6082 1744 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1745 return;
1746 }
c27a02cd 1747
0cc5c8bf
EE		 1748 /* close port*/
1749 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1750
c27a02cd
YP		 1751 /* Synchronize with tx routine */
1752 netif_tx_lock_bh(dev);
3484aac1
AV		 1753 if (detach)
1754 netif_device_detach(dev);
3c05f5ef 1755 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1756 netif_tx_unlock_bh(dev);
1757
3484aac1
AV		 1758 netif_tx_disable(dev);
1759
7c287380 1760 /* Set port as not active */
3c05f5ef 1761 priv->port_up = false;
c27a02cd 1762
db0e7cba
AY		 1763 /* Promsicuous mode */
1764 if (mdev->dev->caps.steering_mode ==
1765 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1766 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1767 MLX4_EN_FLAG_MC_PROMISC);
1768 mlx4_flow_steer_promisc_remove(mdev->dev,
1769 priv->port,
f9162539 1770 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1771 mlx4_flow_steer_promisc_remove(mdev->dev,
1772 priv->port,
f9162539 1773 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1774 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1775 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1776
1777 /* Disable promiscouos mode */
1778 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1779 priv->port);
1780
1781 /* Disable Multicast promisc */
1782 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1783 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1784 priv->port);
1785 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1786 }
1787 }
1788
1679200f
YP		 1789 /* Detach All multicasts */
1790 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1791 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1792 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1793 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1794 list_for_each_entry(mclist, &priv->curr_list, list) {
1795 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1796 mc_list[5] = priv->port;
1797 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1798 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1799 if (mclist->tunnel_reg_id)
1800 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1801 }
1802 mlx4_en_clear_list(dev);
6d199937
YP		 1803 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1804 list_del(&mclist->list);
1805 kfree(mclist);
1806 }
1807
1679200f
YP		 1808 /* Flush multicast filter */
1809 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1810
6efb5fac
HHZ		 1811 /* Remove flow steering rules for the port*/
1812 if (mdev->dev->caps.steering_mode ==
1813 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1814 ASSERT_RTNL();
1815 list_for_each_entry_safe(flow, tmp_flow,
1816 &priv->ethtool_list, list) {
1817 mlx4_flow_detach(mdev->dev, flow->id);
1818 list_del(&flow->list);
1819 }
1820 }
1821
cabdc8ee
HHZ		 1822 mlx4_en_destroy_drop_qp(priv);
1823
c27a02cd
YP		 1824 /* Free TX Rings */
1825 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1826 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1827 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1828 }
1829 msleep(10);
1830
1831 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1832 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd
YP		 1833
1834 /* Free RSS qps */
1835 mlx4_en_release_rss_steer(priv);
1836
ffe455ad 1837 /* Unregister Mac address for the port */
16a10ffd 1838 mlx4_en_put_qp(priv);
5930e8d0 1839 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1840 mdev->mac_removed[priv->port] = 1;
ffe455ad 1841
c27a02cd
YP		 1842 /* Free RX Rings */
1843 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1844 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1845
1846 local_bh_disable();
1847 while (!mlx4_en_cq_lock_napi(cq)) {
1848 pr_info("CQ %d locked\n", i);
1849 mdelay(1);
1850 }
1851 local_bh_enable();
1852
f4a36751 1853 napi_synchronize(&cq->napi);
41d942d5 1854 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1855 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 1856
1857 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1858 }
1859}
1860
1861static void mlx4_en_restart(struct work_struct *work)
1862{
1863 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1864 watchdog_task);
1865 struct mlx4_en_dev *mdev = priv->mdev;
1866 struct net_device *dev = priv->dev;
1867
453a6082 1868 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1869
1870 mutex_lock(&mdev->state_lock);
1871 if (priv->port_up) {
3484aac1 1872 mlx4_en_stop_port(dev, 1);
1e338db5 1873 if (mlx4_en_start_port(dev))
453a6082 1874 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1875 }
1876 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1877}
1878
b477ba62 1879static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1880{
1881 struct mlx4_en_priv *priv = netdev_priv(dev);
1882 struct mlx4_en_dev *mdev = priv->mdev;
1883 int i;
c27a02cd 1884
c27a02cd 1885 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1886 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1887
1888 memset(&priv->stats, 0, sizeof(priv->stats));
1889 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1890 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1891 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
c27a02cd
YP		 1892
1893 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1894 priv->tx_ring[i]->bytes = 0;
1895 priv->tx_ring[i]->packets = 0;
1896 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1897 }
1898 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1899 priv->rx_ring[i]->bytes = 0;
1900 priv->rx_ring[i]->packets = 0;
1901 priv->rx_ring[i]->csum_ok = 0;
1902 priv->rx_ring[i]->csum_none = 0;
f8c6455b 1903 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 1904 }
b477ba62
EE		 1905}
1906
1907static int mlx4_en_open(struct net_device *dev)
1908{
1909 struct mlx4_en_priv *priv = netdev_priv(dev);
1910 struct mlx4_en_dev *mdev = priv->mdev;
1911 int err = 0;
1912
1913 mutex_lock(&mdev->state_lock);
1914
1915 if (!mdev->device_up) {
1916 en_err(priv, "Cannot open - device down/disabled\n");
1917 err = -EBUSY;
1918 goto out;
1919 }
1920
1921 /* Reset HW statistics and SW counters */
1922 mlx4_en_clear_stats(dev);
c27a02cd 1923
c27a02cd
YP		 1924 err = mlx4_en_start_port(dev);
1925 if (err)
453a6082 1926 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1927
1928out:
1929 mutex_unlock(&mdev->state_lock);
1930 return err;
1931}
1932
1933
1934static int mlx4_en_close(struct net_device *dev)
1935{
1936 struct mlx4_en_priv *priv = netdev_priv(dev);
1937 struct mlx4_en_dev *mdev = priv->mdev;
1938
453a6082 1939 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1940
1941 mutex_lock(&mdev->state_lock);
1942
3484aac1 1943 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1944 netif_carrier_off(dev);
1945
1946 mutex_unlock(&mdev->state_lock);
1947 return 0;
1948}
1949
fe0af03c 1950void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1951{
1952 int i;
1953
1eb8c695
AV		 1954#ifdef CONFIG_RFS_ACCEL
1955 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1956 priv->dev->rx_cpu_rmap = NULL;
1957#endif
1958
c27a02cd 1959 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1960 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1961 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1962 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1963 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1964 }
1965
1966 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1967 if (priv->rx_ring[i])
68355f71
TLSC		 1968 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1969 priv->prof->rx_ring_size, priv->stride);
41d942d5 1970 if (priv->rx_cq[i])
fe0af03c 1971 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1972 }
044ca2a5
YP		 1973
1974 if (priv->base_tx_qpn) {
1975 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1976 priv->base_tx_qpn = 0;
1977 }
c27a02cd
YP		 1978}
1979
18cc42a3 1980int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1981{
c27a02cd
YP		 1982 struct mlx4_en_port_profile *prof = priv->prof;
1983 int i;
163561a4 1984 int node;
87a5c389 1985
c27a02cd
YP		 1986 /* Create tx Rings */
1987 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1988 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1989 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1990 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1991 goto err;
1992
d03a68f8 1993 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
d03a68f8
IS		 1994 prof->tx_ring_size, TXBB_SIZE,
1995 node, i))
c27a02cd
YP		 1996 goto err;
1997 }
1998
1999 /* Create rx Rings */
2000 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2001 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2002 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2003 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2004 goto err;
2005
2006 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2007 prof->rx_ring_size, priv->stride,
2008 node))
c27a02cd
YP		 2009 goto err;
2010 }
2011
1eb8c695 2012#ifdef CONFIG_RFS_ACCEL
a229e488
AV		 2013 if (priv->mdev->dev->caps.comp_pool) {
2014 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
2015 if (!priv->dev->rx_cpu_rmap)
2016 goto err;
2017 }
1eb8c695
AV		 2018#endif
2019
c27a02cd
YP		 2020 return 0;
2021
2022err:
453a6082 2023 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2024 for (i = 0; i < priv->rx_ring_num; i++) {
2025 if (priv->rx_ring[i])
2026 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2027 prof->rx_ring_size,
2028 priv->stride);
2029 if (priv->rx_cq[i])
2030 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2031 }
2032 for (i = 0; i < priv->tx_ring_num; i++) {
2033 if (priv->tx_ring[i])
2034 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2035 if (priv->tx_cq[i])
2036 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2037 }
c27a02cd
YP		 2038 return -ENOMEM;
2039}
2040
2041
2042void mlx4_en_destroy_netdev(struct net_device *dev)
2043{
2044 struct mlx4_en_priv *priv = netdev_priv(dev);
2045 struct mlx4_en_dev *mdev = priv->mdev;
2046
453a6082 2047 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2048
2049 /* Unregister device - this will close the port if it was up */
2050 if (priv->registered)
2051 unregister_netdev(dev);
2052
2053 if (priv->allocated)
2054 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2055
2056 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2057 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2058 /* flush any pending task for this netdev */
2059 flush_workqueue(mdev->workqueue);
2060
2061 /* Detach the netdev so tasks would not attempt to access it */
2062 mutex_lock(&mdev->state_lock);
2063 mdev->pndev[priv->port] = NULL;
2064 mutex_unlock(&mdev->state_lock);
2065
fe0af03c 2066 mlx4_en_free_resources(priv);
564c274c 2067
bc6a4744
AV		 2068 kfree(priv->tx_ring);
2069 kfree(priv->tx_cq);
2070
c27a02cd
YP		 2071 free_netdev(dev);
2072}
2073
2074static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2075{
2076 struct mlx4_en_priv *priv = netdev_priv(dev);
2077 struct mlx4_en_dev *mdev = priv->mdev;
2078 int err = 0;
2079
453a6082 2080 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2081 dev->mtu, new_mtu);
2082
2083 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2084 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2085 return -EPERM;
2086 }
2087 dev->mtu = new_mtu;
2088
2089 if (netif_running(dev)) {
2090 mutex_lock(&mdev->state_lock);
2091 if (!mdev->device_up) {
2092 /* NIC is probably restarting - let watchdog task reset
2093 * the port */
453a6082 2094 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2095 } else {
3484aac1 2096 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2097 err = mlx4_en_start_port(dev);
2098 if (err) {
453a6082 2099 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2100 priv->port);
2101 queue_work(mdev->workqueue, &priv->watchdog_task);
2102 }
2103 }
2104 mutex_unlock(&mdev->state_lock);
2105 }
2106 return 0;
2107}
2108
100dbda8 2109static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2110{
2111 struct mlx4_en_priv *priv = netdev_priv(dev);
2112 struct mlx4_en_dev *mdev = priv->mdev;
2113 struct hwtstamp_config config;
2114
2115 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2116 return -EFAULT;
2117
2118 /* reserved for future extensions */
2119 if (config.flags)
2120 return -EINVAL;
2121
2122 /* device doesn't support time stamping */
2123 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2124 return -EINVAL;
2125
2126 /* TX HW timestamp */
2127 switch (config.tx_type) {
2128 case HWTSTAMP_TX_OFF:
2129 case HWTSTAMP_TX_ON:
2130 break;
2131 default:
2132 return -ERANGE;
2133 }
2134
2135 /* RX HW timestamp */
2136 switch (config.rx_filter) {
2137 case HWTSTAMP_FILTER_NONE:
2138 break;
2139 case HWTSTAMP_FILTER_ALL:
2140 case HWTSTAMP_FILTER_SOME:
2141 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2142 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2143 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2144 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2145 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2146 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2147 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2148 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2149 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2150 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2151 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2152 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2153 config.rx_filter = HWTSTAMP_FILTER_ALL;
2154 break;
2155 default:
2156 return -ERANGE;
2157 }
2158
7787fa66 2159 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2160 config.tx_type = HWTSTAMP_TX_OFF;
2161 config.rx_filter = HWTSTAMP_FILTER_NONE;
2162 }
2163
2164 return copy_to_user(ifr->ifr_data, &config,
2165 sizeof(config)) ? -EFAULT : 0;
2166}
2167
100dbda8
BH		 2168static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2169{
2170 struct mlx4_en_priv *priv = netdev_priv(dev);
2171
2172 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2173 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2174}
2175
ec693d47
AV		 2176static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2177{
2178 switch (cmd) {
2179 case SIOCSHWTSTAMP:
100dbda8
BH		 2180 return mlx4_en_hwtstamp_set(dev, ifr);
2181 case SIOCGHWTSTAMP:
2182 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2183 default:
2184 return -EOPNOTSUPP;
2185 }
2186}
2187
60d6fe99
AV		 2188static int mlx4_en_set_features(struct net_device *netdev,
2189 netdev_features_t features)
2190{
2191 struct mlx4_en_priv *priv = netdev_priv(netdev);
537f6f95
SM		 2192 int ret = 0;
2193
2194 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2195 en_info(priv, "Turn %s RX vlan strip offload\n",
2196 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
2197 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2198 features);
2199 if (ret)
2200 return ret;
2201 }
60d6fe99
AV		 2202
2203 if (features & NETIF_F_LOOPBACK)
2204 priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2205 else
2206 priv->ctrl_flags &=
2207 cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK);
2208
79aeaccd
YB		 2209 mlx4_en_update_loopback_state(netdev, features);
2210
60d6fe99
AV		 2211 return 0;
2212
2213}
2214
8f7ba3ca
RE		 2215static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2216{
2217 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2218 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2219 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca
RE		 2220
2221 if (!is_valid_ether_addr(mac))
2222 return -EINVAL;
2223
2224 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2225}
2226
3f7fb021
RE		 2227static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2228{
2229 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2230 struct mlx4_en_dev *mdev = en_priv->mdev;
2231
2232 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2233}
2234
e6b6a231
RE		 2235static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2236{
2237 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2238 struct mlx4_en_dev *mdev = en_priv->mdev;
2239
2240 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2241}
2242
2cccb9e4
RE		 2243static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2244{
2245 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2246 struct mlx4_en_dev *mdev = en_priv->mdev;
2247
2248 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2249}
8f7ba3ca 2250
948e306d
RE		 2251static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2252{
2253 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2254 struct mlx4_en_dev *mdev = en_priv->mdev;
2255
2256 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2257}
84c86403
HHZ		 2258
2259#define PORT_ID_BYTE_LEN 8
2260static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2261 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2262{
2263 struct mlx4_en_priv *priv = netdev_priv(dev);
2264 struct mlx4_dev *mdev = priv->mdev->dev;
2265 int i;
2266 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2267
2268 if (!phys_port_id)
2269 return -EOPNOTSUPP;
2270
2271 ppid->id_len = sizeof(phys_port_id);
2272 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2273 ppid->id[i] = phys_port_id & 0xff;
2274 phys_port_id >>= 8;
2275 }
2276 return 0;
2277}
2278
a66132f3 2279#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2280static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2281{
2282 int ret;
2283 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2284 vxlan_add_task);
2285
2286 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2287 if (ret)
2288 goto out;
2289
2290 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2291 VXLAN_STEER_BY_OUTER_MAC, 1);
2292out:
f4a1edd5 2293 if (ret) {
1b136de1 2294 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2295 return;
2296 }
2297
2298 /* set offloads */
2299 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2300 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2301 priv->dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2302 priv->dev->features |= NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2303}
2304
2305static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2306{
2307 int ret;
2308 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2309 vxlan_del_task);
f4a1edd5
OG		 2310 /* unset offloads */
2311 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2312 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL);
2313 priv->dev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;
2314 priv->dev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2315
2316 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2317 VXLAN_STEER_BY_OUTER_MAC, 0);
2318 if (ret)
2319 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2320
2321 priv->vxlan_port = 0;
2322}
2323
2324static void mlx4_en_add_vxlan_port(struct net_device *dev,
2325 sa_family_t sa_family, __be16 port)
2326{
2327 struct mlx4_en_priv *priv = netdev_priv(dev);
2328 __be16 current_port;
2329
e326f2f1 2330 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2331 return;
2332
2333 if (sa_family == AF_INET6)
2334 return;
2335
2336 current_port = priv->vxlan_port;
2337 if (current_port && current_port != port) {
2338 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2339 ntohs(current_port), ntohs(port));
2340 return;
2341 }
2342
2343 priv->vxlan_port = port;
2344 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2345}
2346
2347static void mlx4_en_del_vxlan_port(struct net_device *dev,
2348 sa_family_t sa_family, __be16 port)
2349{
2350 struct mlx4_en_priv *priv = netdev_priv(dev);
2351 __be16 current_port;
2352
2353 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
2354 return;
2355
2356 if (sa_family == AF_INET6)
2357 return;
2358
2359 current_port = priv->vxlan_port;
2360 if (current_port != port) {
2361 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2362 return;
2363 }
2364
2365 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2366}
956bdab2
JS		 2367
2368static bool mlx4_en_gso_check(struct sk_buff *skb, struct net_device *dev)
2369{
2370 return vxlan_gso_check(skb);
2371}
a66132f3 2372#endif
1b136de1 2373
3addc568
SH		 2374static const struct net_device_ops mlx4_netdev_ops = {
2375 .ndo_open = mlx4_en_open,
2376 .ndo_stop = mlx4_en_close,
2377 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2378 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2379 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2380 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2381 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2382 .ndo_validate_addr = eth_validate_addr,
3addc568 2383 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2384 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2385 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2386 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2387 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2388#ifdef CONFIG_NET_POLL_CONTROLLER
2389 .ndo_poll_controller = mlx4_en_netpoll,
2390#endif
60d6fe99 2391 .ndo_set_features = mlx4_en_set_features,
897d7846 2392 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2393#ifdef CONFIG_RFS_ACCEL
2394 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2395#endif
e0d1095a 2396#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2397 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2398#endif
84c86403 2399 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a66132f3 2400#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2401 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2402 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
956bdab2 2403 .ndo_gso_check = mlx4_en_gso_check,
a66132f3 2404#endif
3addc568
SH		 2405};
2406
8f7ba3ca
RE		 2407static const struct net_device_ops mlx4_netdev_ops_master = {
2408 .ndo_open = mlx4_en_open,
2409 .ndo_stop = mlx4_en_close,
2410 .ndo_start_xmit = mlx4_en_xmit,
2411 .ndo_select_queue = mlx4_en_select_queue,
2412 .ndo_get_stats = mlx4_en_get_stats,
2413 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2414 .ndo_set_mac_address = mlx4_en_set_mac,
2415 .ndo_validate_addr = eth_validate_addr,
2416 .ndo_change_mtu = mlx4_en_change_mtu,
2417 .ndo_tx_timeout = mlx4_en_tx_timeout,
2418 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2419 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2420 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2421 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
e6b6a231 2422 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2423 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2424 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2425#ifdef CONFIG_NET_POLL_CONTROLLER
2426 .ndo_poll_controller = mlx4_en_netpoll,
2427#endif
2428 .ndo_set_features = mlx4_en_set_features,
2429 .ndo_setup_tc = mlx4_en_setup_tc,
2430#ifdef CONFIG_RFS_ACCEL
2431 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2432#endif
84c86403 2433 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
9737c6ab
OG		 2434#ifdef CONFIG_MLX4_EN_VXLAN
2435 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2436 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
2437 .ndo_gso_check = mlx4_en_gso_check,
2438#endif
8f7ba3ca
RE		 2439};
2440
c27a02cd
YP		 2441int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2442 struct mlx4_en_port_profile *prof)
2443{
2444 struct net_device *dev;
2445 struct mlx4_en_priv *priv;
c07cb4b0 2446 int i;
c27a02cd 2447 int err;
ef96f7d4 2448 u64 mac_u64;
c27a02cd 2449
f1593d22 2450 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2451 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2452 if (dev == NULL)
c27a02cd 2453 return -ENOMEM;
c27a02cd 2454
d317966b
AV		 2455 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2456 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2457
c27a02cd 2458 SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev);
76a066f2 2459 dev->dev_port = port - 1;
c27a02cd
YP		 2460
2461 /*
2462 * Initialize driver private data
2463 */
2464
2465 priv = netdev_priv(dev);
2466 memset(priv, 0, sizeof(struct mlx4_en_priv));
207af6c5
EE		 2467 spin_lock_init(&priv->stats_lock);
2468 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
2469 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2470 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2471 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
2472 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
2473#ifdef CONFIG_MLX4_EN_VXLAN
2474 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
2475 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
2476#endif
2477#ifdef CONFIG_RFS_ACCEL
2478 INIT_LIST_HEAD(&priv->filters);
2479 spin_lock_init(&priv->filters_lock);
2480#endif
2481
c27a02cd
YP		 2482 priv->dev = dev;
2483 priv->mdev = mdev;
ebf8c9aa 2484 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2485 priv->prof = prof;
2486 priv->port = port;
2487 priv->port_up = false;
c27a02cd 2488 priv->flags = prof->flags;
0fef9d03 2489 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 2490 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2491 MLX4_WQE_CTRL_SOLICITED);
d317966b 2492 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2493 priv->tx_ring_num = prof->tx_ring_num;
fbc6daf1 2494 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 2495 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 2496
41d942d5 2497 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2498 GFP_KERNEL);
bc6a4744
AV		 2499 if (!priv->tx_ring) {
2500 err = -ENOMEM;
2501 goto out;
2502 }
41d942d5 2503 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2504 GFP_KERNEL);
bc6a4744
AV		 2505 if (!priv->tx_cq) {
2506 err = -ENOMEM;
2507 goto out;
2508 }
c27a02cd 2509 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2510 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 2511 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 2512 priv->mac_index = -1;
2513 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 2514#ifdef CONFIG_MLX4_EN_DCB
540b3a39
OG		 2515 if (!mlx4_is_slave(priv->mdev->dev)) {
2516 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
2517 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2518 } else {
2519 en_info(priv, "enabling only PFC DCB ops\n");
2520 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2521 }
2522 }
564c274c 2523#endif
c27a02cd 2524
c07cb4b0
YB		 2525 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2526 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2527
c27a02cd
YP		 2528 /* Query for default mac and max mtu */
2529 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 2530
f8c6455b
SM		 2531 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
2532 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
2533 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
2534
6bbb6d99
YB		 2535 /* Set default MAC */
2536 dev->addr_len = ETH_ALEN;
2537 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2538 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG		 2539 if (mlx4_is_slave(priv->mdev->dev)) {
2540 eth_hw_addr_random(dev);
2541 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
9813337a 2542 mac_u64 = mlx4_mac_to_u64(dev->dev_addr);
ef96f7d4
OG		 2543 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2544 } else {
2545 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2546 priv->port, dev->dev_addr);
2547 err = -EINVAL;
2548 goto out;
2549 }
c27a02cd
YP		 2550 }
2551
2695bab2 2552 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 2553
c27a02cd
YP		 2554 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2555 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2556 err = mlx4_en_alloc_resources(priv);
2557 if (err)
2558 goto out;
2559
ec693d47
AV		 2560 /* Initialize time stamping config */
2561 priv->hwtstamp_config.flags = 0;
2562 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2563 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2564
c27a02cd
YP		 2565 /* Allocate page for receive rings */
2566 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2567 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2568 if (err) {
453a6082 2569 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2570 goto out;
2571 }
2572 priv->allocated = 1;
2573
c27a02cd
YP		 2574 /*
2575 * Initialize netdev entry points
2576 */
8f7ba3ca
RE		 2577 if (mlx4_is_master(priv->mdev->dev))
2578 dev->netdev_ops = &mlx4_netdev_ops_master;
2579 else
2580 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2581 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2582 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2583 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2584
7ad24ea4 2585 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 2586
c27a02cd
YP		 2587 /*
2588 * Set driver features
2589 */
c8c64cff
MM		 2590 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2591 if (mdev->LSO_support)
2592 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2593
2594 dev->vlan_features = dev->hw_features;
2595
ad86107f 2596 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2597 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2598 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2599 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 2600 dev->hw_features |= NETIF_F_LOOPBACK |
2601 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 2602
1eb8c695 2603 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 2604 MLX4_STEERING_MODE_DEVICE_MANAGED &&
2605 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 2606 dev->hw_features |= NETIF_F_NTUPLE;
2607
cc5387f7
YB		 2608 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2609 dev->priv_flags |= IFF_UNICAST_FLT;
2610
947cbb0a
EP		 2611 /* Setting a default hash function value */
2612 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
2613 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2614 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
2615 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
2616 } else {
2617 en_warn(priv,
2618 "No RSS hash capabilities exposed, using Toeplitz\n");
2619 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2620 }
2621
c27a02cd
YP		 2622 mdev->pndev[port] = dev;
2623
2624 netif_carrier_off(dev);
4801ae70
EE		 2625 mlx4_en_set_default_moderation(priv);
2626
c27a02cd
YP		 2627 err = register_netdev(dev);
2628 if (err) {
453a6082 2629 en_err(priv, "Netdev registration failed for port %d\n", port);
c27a02cd
YP		 2630 goto out;
2631 }
4234144f 2632 priv->registered = 1;
453a6082
YP		 2633
2634 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2635 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2636
79aeaccd
YB		 2637 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2638
90822265 2639 /* Configure port */
5c8e9046 2640 mlx4_en_calc_rx_buf(dev);
90822265 2641 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2642 priv->rx_skb_size + ETH_FCS_LEN,
2643 prof->tx_pause, prof->tx_ppp,
2644 prof->rx_pause, prof->rx_ppp);
90822265 2645 if (err) {
1a91de28
JP		 2646 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
2647 priv->port, err);
90822265
YP		 2648 goto out;
2649 }
2650
837052d0 2651 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 2652 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 2653 if (err) {
2654 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
2655 err);
2656 goto out;
2657 }
2658 }
2659
90822265
YP		 2660 /* Init port */
2661 en_warn(priv, "Initializing port\n");
2662 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2663 if (err) {
2664 en_err(priv, "Failed Initializing port\n");
2665 goto out;
2666 }
c27a02cd 2667 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 2668
2669 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2670 queue_delayed_work(mdev->workqueue, &priv->service_task,
2671 SERVICE_TASK_DELAY);
2672
c27a02cd
YP		 2673 return 0;
2674
2675out:
2676 mlx4_en_destroy_netdev(dev);
2677 return err;
2678}
2679
537f6f95
SM		 2680int mlx4_en_reset_config(struct net_device *dev,
2681 struct hwtstamp_config ts_config,
2682 netdev_features_t features)
2683{
2684 struct mlx4_en_priv *priv = netdev_priv(dev);
2685 struct mlx4_en_dev *mdev = priv->mdev;
2686 int port_up = 0;
2687 int err = 0;
2688
2689 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
2690 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
2691 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX))
2692 return 0; /* Nothing to change */
2693
2694 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
2695 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
2696 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
2697 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
2698 return -EINVAL;
2699 }
2700
2701 mutex_lock(&mdev->state_lock);
2702 if (priv->port_up) {
2703 port_up = 1;
2704 mlx4_en_stop_port(dev, 1);
2705 }
2706
2707 mlx4_en_free_resources(priv);
2708
2709 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
2710 ts_config.rx_filter, !!(features & NETIF_F_HW_VLAN_CTAG_RX));
2711
2712 priv->hwtstamp_config.tx_type = ts_config.tx_type;
2713 priv->hwtstamp_config.rx_filter = ts_config.rx_filter;
2714
2715 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2716 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2717 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2718 else
2719 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
2720 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
2721 /* RX time-stamping is OFF, update the RX vlan offload
2722 * to the latest wanted state
2723 */
2724 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
2725 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2726 else
2727 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
2728 }
2729
2730 /* RX vlan offload and RX time-stamping can't co-exist !
2731 * Regardless of the caller's choice,
2732 * Turn Off RX vlan offload in case of time-stamping is ON
2733 */
2734 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
2735 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
2736 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
2737 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
2738 }
2739
2740 err = mlx4_en_alloc_resources(priv);
2741 if (err) {
2742 en_err(priv, "Failed reallocating port resources\n");
2743 goto out;
2744 }
2745 if (port_up) {
2746 err = mlx4_en_start_port(dev);
2747 if (err)
2748 en_err(priv, "Failed starting port\n");
2749 }
2750
2751out:
2752 mutex_unlock(&mdev->state_lock);
2753 netdev_features_change(dev);
2754 return err;
2755}
Linux 6.x block layer and io_uring tree(s)