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net/mlx4_en: Move statistics bitmap setting to the Ethernet driver
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_ethtool.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/ethtool.h>
36#include <linux/netdevice.h>
af22d9de 37#include <linux/mlx4/driver.h>
7202da8b 38#include <linux/mlx4/device.h>
f90a3673
HHZ		 39#include <linux/in.h>
40#include <net/ip.h>
c27a02cd
YP		 41
42#include "mlx4_en.h"
43#include "en_port.h"
44
82067281 45#define EN_ETHTOOL_QP_ATTACH (1ull << 63)
82067281
HHZ		 46#define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
47#define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
c27a02cd 48
79c54b6b
AV		 49static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
50{
51 int i;
52 int err = 0;
53
54 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 55 priv->tx_cq[i]->moder_cnt = priv->tx_frames;
56 priv->tx_cq[i]->moder_time = priv->tx_usecs;
38463e2c 57 if (priv->port_up) {
41d942d5 58 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
38463e2c
EE		 59 if (err)
60 return err;
61 }
79c54b6b
AV		 62 }
63
64 if (priv->adaptive_rx_coal)
65 return 0;
66
67 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 68 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
69 priv->rx_cq[i]->moder_time = priv->rx_usecs;
79c54b6b 70 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
38463e2c 71 if (priv->port_up) {
41d942d5 72 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
38463e2c
EE		 73 if (err)
74 return err;
75 }
79c54b6b
AV		 76 }
77
78 return err;
79}
80
c27a02cd
YP		 81static void
82mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
83{
84 struct mlx4_en_priv *priv = netdev_priv(dev);
85 struct mlx4_en_dev *mdev = priv->mdev;
86
612a94d6
RJ		 87 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
88 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
89 sizeof(drvinfo->version));
90 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
91 "%d.%d.%d",
c27a02cd
YP		 92 (u16) (mdev->dev->caps.fw_ver >> 32),
93 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
94 (u16) (mdev->dev->caps.fw_ver & 0xffff));
872bf2fb 95 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
612a94d6 96 sizeof(drvinfo->bus_info));
c27a02cd
YP		 97 drvinfo->n_stats = 0;
98 drvinfo->regdump_len = 0;
99 drvinfo->eedump_len = 0;
100}
101
0fef9d03
AV		 102static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
103 "blueflame",
104};
105
c27a02cd
YP		 106static const char main_strings[][ETH_GSTRING_LEN] = {
107 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
108 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
109 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
110 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
111 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
112 "tx_heartbeat_errors", "tx_window_errors",
113
114 /* port statistics */
fa37a958 115 "tso_packets",
9fab426d 116 "xmit_more",
c27a02cd 117 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
f8c6455b 118 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
c27a02cd
YP		 119
120 /* packet statistics */
121 "broadcast", "rx_prio_0", "rx_prio_1", "rx_prio_2", "rx_prio_3",
122 "rx_prio_4", "rx_prio_5", "rx_prio_6", "rx_prio_7", "tx_prio_0",
123 "tx_prio_1", "tx_prio_2", "tx_prio_3", "tx_prio_4", "tx_prio_5",
124 "tx_prio_6", "tx_prio_7",
125};
c27a02cd 126
e7c1c2c4 127static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
fd9071ec 128 "Interrupt Test",
e7c1c2c4
YP		 129 "Link Test",
130 "Speed Test",
131 "Register Test",
132 "Loopback Test",
133};
134
c27a02cd
YP		 135static u32 mlx4_en_get_msglevel(struct net_device *dev)
136{
137 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
138}
139
140static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
141{
142 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
143}
144
145static void mlx4_en_get_wol(struct net_device *netdev,
146 struct ethtool_wolinfo *wol)
147{
14c07b13
YP		 148 struct mlx4_en_priv *priv = netdev_priv(netdev);
149 int err = 0;
150 u64 config = 0;
559a9f1d 151 u64 mask;
14c07b13 152
559a9f1d
OD		 153 if ((priv->port < 1) || (priv->port > 2)) {
154 en_err(priv, "Failed to get WoL information\n");
155 return;
156 }
157
158 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
159 MLX4_DEV_CAP_FLAG_WOL_PORT2;
160
161 if (!(priv->mdev->dev->caps.flags & mask)) {
14c07b13
YP		 162 wol->supported = 0;
163 wol->wolopts = 0;
164 return;
165 }
166
167 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
168 if (err) {
169 en_err(priv, "Failed to get WoL information\n");
170 return;
171 }
172
173 if (config & MLX4_EN_WOL_MAGIC)
174 wol->supported = WAKE_MAGIC;
175 else
176 wol->supported = 0;
177
178 if (config & MLX4_EN_WOL_ENABLED)
179 wol->wolopts = WAKE_MAGIC;
180 else
181 wol->wolopts = 0;
182}
183
184static int mlx4_en_set_wol(struct net_device *netdev,
185 struct ethtool_wolinfo *wol)
186{
187 struct mlx4_en_priv *priv = netdev_priv(netdev);
188 u64 config = 0;
189 int err = 0;
559a9f1d
OD		 190 u64 mask;
191
192 if ((priv->port < 1) || (priv->port > 2))
193 return -EOPNOTSUPP;
194
195 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
196 MLX4_DEV_CAP_FLAG_WOL_PORT2;
14c07b13 197
559a9f1d 198 if (!(priv->mdev->dev->caps.flags & mask))
14c07b13
YP		 199 return -EOPNOTSUPP;
200
201 if (wol->supported & ~WAKE_MAGIC)
202 return -EINVAL;
203
204 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
205 if (err) {
206 en_err(priv, "Failed to get WoL info, unable to modify\n");
207 return err;
208 }
209
210 if (wol->wolopts & WAKE_MAGIC) {
211 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
212 MLX4_EN_WOL_MAGIC;
213 } else {
214 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
215 config |= MLX4_EN_WOL_DO_MODIFY;
216 }
217
218 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
219 if (err)
220 en_err(priv, "Failed to set WoL information\n");
221
222 return err;
c27a02cd
YP		 223}
224
225static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
226{
227 struct mlx4_en_priv *priv = netdev_priv(dev);
93ece0c1 228 int bit_count = hweight64(priv->stats_bitmap);
c27a02cd 229
e7c1c2c4
YP		 230 switch (sset) {
231 case ETH_SS_STATS:
93ece0c1 232 return (priv->stats_bitmap ? bit_count : NUM_ALL_STATS) +
8501841a 233 (priv->tx_ring_num * 2) +
e0d1095a 234#ifdef CONFIG_NET_RX_BUSY_POLL
8501841a
AV		 235 (priv->rx_ring_num * 5);
236#else
237 (priv->rx_ring_num * 2);
238#endif
e7c1c2c4 239 case ETH_SS_TEST:
ccf86321
OG		 240 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
241 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
0fef9d03
AV		 242 case ETH_SS_PRIV_FLAGS:
243 return ARRAY_SIZE(mlx4_en_priv_flags);
e7c1c2c4 244 default:
c27a02cd 245 return -EOPNOTSUPP;
e7c1c2c4 246 }
c27a02cd
YP		 247}
248
249static void mlx4_en_get_ethtool_stats(struct net_device *dev,
250 struct ethtool_stats *stats, uint64_t *data)
251{
252 struct mlx4_en_priv *priv = netdev_priv(dev);
253 int index = 0;
93ece0c1 254 int i, j = 0;
c27a02cd
YP		 255
256 spin_lock_bh(&priv->stats_lock);
257
93ece0c1
EE		 258 if (!(priv->stats_bitmap)) {
259 for (i = 0; i < NUM_MAIN_STATS; i++)
260 data[index++] =
261 ((unsigned long *) &priv->stats)[i];
262 for (i = 0; i < NUM_PORT_STATS; i++)
263 data[index++] =
264 ((unsigned long *) &priv->port_stats)[i];
265 for (i = 0; i < NUM_PKT_STATS; i++)
266 data[index++] =
267 ((unsigned long *) &priv->pkstats)[i];
268 } else {
269 for (i = 0; i < NUM_MAIN_STATS; i++) {
270 if ((priv->stats_bitmap >> j) & 1)
271 data[index++] =
272 ((unsigned long *) &priv->stats)[i];
273 j++;
274 }
275 for (i = 0; i < NUM_PORT_STATS; i++) {
276 if ((priv->stats_bitmap >> j) & 1)
277 data[index++] =
278 ((unsigned long *) &priv->port_stats)[i];
279 j++;
280 }
281 }
c27a02cd 282 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 283 data[index++] = priv->tx_ring[i]->packets;
284 data[index++] = priv->tx_ring[i]->bytes;
c27a02cd
YP		 285 }
286 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 287 data[index++] = priv->rx_ring[i]->packets;
288 data[index++] = priv->rx_ring[i]->bytes;
e0d1095a 289#ifdef CONFIG_NET_RX_BUSY_POLL
41d942d5
EE		 290 data[index++] = priv->rx_ring[i]->yields;
291 data[index++] = priv->rx_ring[i]->misses;
292 data[index++] = priv->rx_ring[i]->cleaned;
8501841a 293#endif
c27a02cd 294 }
c27a02cd
YP		 295 spin_unlock_bh(&priv->stats_lock);
296
297}
298
e7c1c2c4
YP		 299static void mlx4_en_self_test(struct net_device *dev,
300 struct ethtool_test *etest, u64 *buf)
301{
302 mlx4_en_ex_selftest(dev, &etest->flags, buf);
303}
304
c27a02cd
YP		 305static void mlx4_en_get_strings(struct net_device *dev,
306 uint32_t stringset, uint8_t *data)
307{
308 struct mlx4_en_priv *priv = netdev_priv(dev);
309 int index = 0;
310 int i;
311
e7c1c2c4
YP		 312 switch (stringset) {
313 case ETH_SS_TEST:
314 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
315 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
ccf86321 316 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
e7c1c2c4
YP		 317 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
318 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
319 break;
320
321 case ETH_SS_STATS:
322 /* Add main counters */
93ece0c1
EE		 323 if (!priv->stats_bitmap) {
324 for (i = 0; i < NUM_MAIN_STATS; i++)
325 strcpy(data + (index++) * ETH_GSTRING_LEN,
326 main_strings[i]);
327 for (i = 0; i < NUM_PORT_STATS; i++)
328 strcpy(data + (index++) * ETH_GSTRING_LEN,
329 main_strings[i +
330 NUM_MAIN_STATS]);
331 for (i = 0; i < NUM_PKT_STATS; i++)
332 strcpy(data + (index++) * ETH_GSTRING_LEN,
333 main_strings[i +
334 NUM_MAIN_STATS +
335 NUM_PORT_STATS]);
336 } else
337 for (i = 0; i < NUM_MAIN_STATS + NUM_PORT_STATS; i++) {
338 if ((priv->stats_bitmap >> i) & 1) {
339 strcpy(data +
340 (index++) * ETH_GSTRING_LEN,
341 main_strings[i]);
342 }
343 if (!(priv->stats_bitmap >> i))
344 break;
345 }
e7c1c2c4
YP		 346 for (i = 0; i < priv->tx_ring_num; i++) {
347 sprintf(data + (index++) * ETH_GSTRING_LEN,
348 "tx%d_packets", i);
349 sprintf(data + (index++) * ETH_GSTRING_LEN,
350 "tx%d_bytes", i);
351 }
352 for (i = 0; i < priv->rx_ring_num; i++) {
353 sprintf(data + (index++) * ETH_GSTRING_LEN,
354 "rx%d_packets", i);
355 sprintf(data + (index++) * ETH_GSTRING_LEN,
356 "rx%d_bytes", i);
e0d1095a 357#ifdef CONFIG_NET_RX_BUSY_POLL
8501841a
AV		 358 sprintf(data + (index++) * ETH_GSTRING_LEN,
359 "rx%d_napi_yield", i);
360 sprintf(data + (index++) * ETH_GSTRING_LEN,
361 "rx%d_misses", i);
362 sprintf(data + (index++) * ETH_GSTRING_LEN,
363 "rx%d_cleaned", i);
364#endif
e7c1c2c4 365 }
e7c1c2c4 366 break;
0fef9d03
AV		 367 case ETH_SS_PRIV_FLAGS:
368 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
369 strcpy(data + i * ETH_GSTRING_LEN,
370 mlx4_en_priv_flags[i]);
371 break;
372
e7c1c2c4 373 }
c27a02cd
YP		 374}
375
2c762679
SM		 376static u32 mlx4_en_autoneg_get(struct net_device *dev)
377{
378 struct mlx4_en_priv *priv = netdev_priv(dev);
379 struct mlx4_en_dev *mdev = priv->mdev;
380 u32 autoneg = AUTONEG_DISABLE;
381
382 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
383 (priv->port_state.flags & MLX4_EN_PORT_ANE))
384 autoneg = AUTONEG_ENABLE;
385
386 return autoneg;
387}
388
389static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg)
390{
391 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
392
393 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
394 | MLX4_PROT_MASK(MLX4_1000BASE_T)
395 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
396 return SUPPORTED_TP;
397 }
398
399 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
400 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
401 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
402 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
403 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
404 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
405 return SUPPORTED_FIBRE;
406 }
407
408 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
409 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
410 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
411 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
412 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
413 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
414 return SUPPORTED_Backplane;
415 }
416 return 0;
417}
418
419static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
420{
421 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
422
423 if (!eth_proto) /* link down */
424 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
425
426 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
427 | MLX4_PROT_MASK(MLX4_1000BASE_T)
428 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
429 return PORT_TP;
430 }
431
432 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
433 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
434 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
435 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
436 return PORT_FIBRE;
437 }
438
439 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
440 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
441 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
442 return PORT_DA;
443 }
444
445 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
446 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
447 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
448 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
449 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
450 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
451 return PORT_NONE;
452 }
453 return PORT_OTHER;
454}
455
456#define MLX4_LINK_MODES_SZ \
457 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
458
459enum ethtool_report {
460 SUPPORTED = 0,
461 ADVERTISED = 1,
462 SPEED = 2
463};
464
465/* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
466static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = {
467 [MLX4_100BASE_TX] = {
468 SUPPORTED_100baseT_Full,
469 ADVERTISED_100baseT_Full,
470 SPEED_100
471 },
472
473 [MLX4_1000BASE_T] = {
474 SUPPORTED_1000baseT_Full,
475 ADVERTISED_1000baseT_Full,
476 SPEED_1000
477 },
478 [MLX4_1000BASE_CX_SGMII] = {
479 SUPPORTED_1000baseKX_Full,
480 ADVERTISED_1000baseKX_Full,
481 SPEED_1000
482 },
483 [MLX4_1000BASE_KX] = {
484 SUPPORTED_1000baseKX_Full,
485 ADVERTISED_1000baseKX_Full,
486 SPEED_1000
487 },
488
489 [MLX4_10GBASE_T] = {
490 SUPPORTED_10000baseT_Full,
491 ADVERTISED_10000baseT_Full,
492 SPEED_10000
493 },
494 [MLX4_10GBASE_CX4] = {
495 SUPPORTED_10000baseKX4_Full,
496 ADVERTISED_10000baseKX4_Full,
497 SPEED_10000
498 },
499 [MLX4_10GBASE_KX4] = {
500 SUPPORTED_10000baseKX4_Full,
501 ADVERTISED_10000baseKX4_Full,
502 SPEED_10000
503 },
504 [MLX4_10GBASE_KR] = {
505 SUPPORTED_10000baseKR_Full,
506 ADVERTISED_10000baseKR_Full,
507 SPEED_10000
508 },
509 [MLX4_10GBASE_CR] = {
510 SUPPORTED_10000baseKR_Full,
511 ADVERTISED_10000baseKR_Full,
512 SPEED_10000
513 },
514 [MLX4_10GBASE_SR] = {
515 SUPPORTED_10000baseKR_Full,
516 ADVERTISED_10000baseKR_Full,
517 SPEED_10000
518 },
519
520 [MLX4_20GBASE_KR2] = {
521 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full,
522 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full,
523 SPEED_20000
524 },
525
526 [MLX4_40GBASE_CR4] = {
527 SUPPORTED_40000baseCR4_Full,
528 ADVERTISED_40000baseCR4_Full,
529 SPEED_40000
530 },
531 [MLX4_40GBASE_KR4] = {
532 SUPPORTED_40000baseKR4_Full,
533 ADVERTISED_40000baseKR4_Full,
534 SPEED_40000
535 },
536 [MLX4_40GBASE_SR4] = {
537 SUPPORTED_40000baseSR4_Full,
538 ADVERTISED_40000baseSR4_Full,
539 SPEED_40000
540 },
541
542 [MLX4_56GBASE_KR4] = {
543 SUPPORTED_56000baseKR4_Full,
544 ADVERTISED_56000baseKR4_Full,
545 SPEED_56000
546 },
547 [MLX4_56GBASE_CR4] = {
548 SUPPORTED_56000baseCR4_Full,
549 ADVERTISED_56000baseCR4_Full,
550 SPEED_56000
551 },
552 [MLX4_56GBASE_SR4] = {
553 SUPPORTED_56000baseSR4_Full,
554 ADVERTISED_56000baseSR4_Full,
555 SPEED_56000
556 },
557};
558
559static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report)
560{
561 int i;
562 u32 link_modes = 0;
563
564 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
565 if (eth_proto & MLX4_PROT_MASK(i))
566 link_modes |= ptys2ethtool_map[i][report];
567 }
568 return link_modes;
569}
570
d48b3ab4
SM		 571static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report)
572{
573 int i;
574 u32 ptys_modes = 0;
575
576 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
577 if (ptys2ethtool_map[i][report] & link_modes)
578 ptys_modes |= 1 << i;
579 }
580 return ptys_modes;
581}
582
583/* Convert actual speed (SPEED_XXX) to ptys link modes */
584static u32 speed2ptys_link_modes(u32 speed)
585{
586 int i;
587 u32 ptys_modes = 0;
588
589 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
590 if (ptys2ethtool_map[i][SPEED] == speed)
591 ptys_modes |= 1 << i;
592 }
593 return ptys_modes;
594}
595
2c762679
SM		 596static int ethtool_get_ptys_settings(struct net_device *dev,
597 struct ethtool_cmd *cmd)
598{
599 struct mlx4_en_priv *priv = netdev_priv(dev);
600 struct mlx4_ptys_reg ptys_reg;
601 u32 eth_proto;
602 int ret;
603
604 memset(&ptys_reg, 0, sizeof(ptys_reg));
605 ptys_reg.local_port = priv->port;
606 ptys_reg.proto_mask = MLX4_PTYS_EN;
607 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
608 MLX4_ACCESS_REG_QUERY, &ptys_reg);
609 if (ret) {
610 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
611 ret);
612 return ret;
613 }
614 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
615 ptys_reg.proto_mask);
616 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
617 be32_to_cpu(ptys_reg.eth_proto_cap));
618 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
619 be32_to_cpu(ptys_reg.eth_proto_admin));
620 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
621 be32_to_cpu(ptys_reg.eth_proto_oper));
622 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
623 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
624
625 cmd->supported = 0;
626 cmd->advertising = 0;
627
628 cmd->supported |= ptys_get_supported_port(&ptys_reg);
629
630 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
631 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED);
632
633 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
634 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED);
635
636 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
637 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0;
638
639 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ?
640 ADVERTISED_Asym_Pause : 0;
641
642 cmd->port = ptys_get_active_port(&ptys_reg);
643 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ?
644 XCVR_EXTERNAL : XCVR_INTERNAL;
645
646 if (mlx4_en_autoneg_get(dev)) {
647 cmd->supported |= SUPPORTED_Autoneg;
648 cmd->advertising |= ADVERTISED_Autoneg;
649 }
650
651 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
652 AUTONEG_ENABLE : AUTONEG_DISABLE;
653
654 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
655 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED);
656
657 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
658 ADVERTISED_Autoneg : 0;
659
660 cmd->phy_address = 0;
661 cmd->mdio_support = 0;
662 cmd->maxtxpkt = 0;
663 cmd->maxrxpkt = 0;
664 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
665 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
666
667 return ret;
668}
669
670static void ethtool_get_default_settings(struct net_device *dev,
671 struct ethtool_cmd *cmd)
c27a02cd 672{
7699517d
YP		 673 struct mlx4_en_priv *priv = netdev_priv(dev);
674 int trans_type;
675
c27a02cd
YP		 676 cmd->autoneg = AUTONEG_DISABLE;
677 cmd->supported = SUPPORTED_10000baseT_Full;
7699517d 678 cmd->advertising = ADVERTISED_10000baseT_Full;
2c762679 679 trans_type = priv->port_state.transceiver;
7699517d
YP		 680
681 if (trans_type > 0 && trans_type <= 0xC) {
682 cmd->port = PORT_FIBRE;
683 cmd->transceiver = XCVR_EXTERNAL;
684 cmd->supported |= SUPPORTED_FIBRE;
685 cmd->advertising |= ADVERTISED_FIBRE;
686 } else if (trans_type == 0x80 || trans_type == 0) {
687 cmd->port = PORT_TP;
688 cmd->transceiver = XCVR_INTERNAL;
689 cmd->supported |= SUPPORTED_TP;
690 cmd->advertising |= ADVERTISED_TP;
691 } else {
692 cmd->port = -1;
693 cmd->transceiver = -1;
694 }
2c762679
SM		 695}
696
697static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
698{
699 struct mlx4_en_priv *priv = netdev_priv(dev);
700 int ret = -EINVAL;
701
702 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
703 return -ENOMEM;
704
705 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
706 priv->port_state.flags & MLX4_EN_PORT_ANC,
707 priv->port_state.flags & MLX4_EN_PORT_ANE);
708
709 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
710 ret = ethtool_get_ptys_settings(dev, cmd);
711 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
712 ethtool_get_default_settings(dev, cmd);
713
714 if (netif_carrier_ok(dev)) {
715 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
716 cmd->duplex = DUPLEX_FULL;
717 } else {
718 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
719 cmd->duplex = DUPLEX_UNKNOWN;
720 }
c27a02cd
YP		 721 return 0;
722}
723
d48b3ab4
SM		 724/* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
725static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
726 __be32 proto_cap)
727{
728 __be32 proto_admin = 0;
729
730 if (!speed) { /* Speed = 0 ==> Reset Link modes */
731 proto_admin = proto_cap;
732 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
733 be32_to_cpu(proto_cap));
734 } else {
735 u32 ptys_link_modes = speed2ptys_link_modes(speed);
736
737 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
738 en_info(priv, "Setting Speed to %d\n", speed);
739 }
740 return proto_admin;
741}
742
c27a02cd
YP		 743static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
744{
d48b3ab4
SM		 745 struct mlx4_en_priv *priv = netdev_priv(dev);
746 struct mlx4_ptys_reg ptys_reg;
747 __be32 proto_admin;
748 int ret;
749
750 u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED);
751 int speed = ethtool_cmd_speed(cmd);
752
753 en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n",
754 speed, cmd->advertising, cmd->autoneg, cmd->duplex);
755
756 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
312df74c 757 (cmd->duplex == DUPLEX_HALF))
c27a02cd
YP		 758 return -EINVAL;
759
d48b3ab4
SM		 760 memset(&ptys_reg, 0, sizeof(ptys_reg));
761 ptys_reg.local_port = priv->port;
762 ptys_reg.proto_mask = MLX4_PTYS_EN;
763 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
764 MLX4_ACCESS_REG_QUERY, &ptys_reg);
765 if (ret) {
766 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
767 ret);
768 return 0;
769 }
770
5a228c03
SM		 771 proto_admin = cmd->autoneg == AUTONEG_ENABLE ?
772 cpu_to_be32(ptys_adv) :
773 speed_set_ptys_admin(priv, speed,
774 ptys_reg.eth_proto_cap);
d48b3ab4
SM		 775
776 proto_admin &= ptys_reg.eth_proto_cap;
d48b3ab4
SM		 777 if (!proto_admin) {
778 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
779 return -EINVAL; /* nothing to change due to bad input */
780 }
781
5a228c03
SM		 782 if (proto_admin == ptys_reg.eth_proto_admin)
783 return 0; /* Nothing to change */
784
d48b3ab4
SM		 785 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
786 be32_to_cpu(proto_admin));
787
788 ptys_reg.eth_proto_admin = proto_admin;
789 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
790 &ptys_reg);
791 if (ret) {
792 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
793 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
794 return ret;
795 }
796
d48b3ab4
SM		 797 mutex_lock(&priv->mdev->state_lock);
798 if (priv->port_up) {
5a228c03 799 en_warn(priv, "Port link mode changed, restarting port...\n");
d48b3ab4
SM		 800 mlx4_en_stop_port(dev, 1);
801 if (mlx4_en_start_port(dev))
802 en_err(priv, "Failed restarting port %d\n", priv->port);
803 }
804 mutex_unlock(&priv->mdev->state_lock);
c27a02cd
YP		 805 return 0;
806}
807
808static int mlx4_en_get_coalesce(struct net_device *dev,
809 struct ethtool_coalesce *coal)
810{
811 struct mlx4_en_priv *priv = netdev_priv(dev);
812
a19a848a
YP		 813 coal->tx_coalesce_usecs = priv->tx_usecs;
814 coal->tx_max_coalesced_frames = priv->tx_frames;
fbc6daf1
AV		 815 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
816
c27a02cd
YP		 817 coal->rx_coalesce_usecs = priv->rx_usecs;
818 coal->rx_max_coalesced_frames = priv->rx_frames;
819
820 coal->pkt_rate_low = priv->pkt_rate_low;
821 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
822 coal->pkt_rate_high = priv->pkt_rate_high;
823 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
824 coal->rate_sample_interval = priv->sample_interval;
825 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
fbc6daf1 826
c27a02cd
YP		 827 return 0;
828}
829
830static int mlx4_en_set_coalesce(struct net_device *dev,
831 struct ethtool_coalesce *coal)
832{
833 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd 834
fbc6daf1
AV		 835 if (!coal->tx_max_coalesced_frames_irq)
836 return -EINVAL;
837
c27a02cd
YP		 838 priv->rx_frames = (coal->rx_max_coalesced_frames ==
839 MLX4_EN_AUTO_CONF) ?
3db36fb2 840 MLX4_EN_RX_COAL_TARGET :
c27a02cd
YP		 841 coal->rx_max_coalesced_frames;
842 priv->rx_usecs = (coal->rx_coalesce_usecs ==
843 MLX4_EN_AUTO_CONF) ?
844 MLX4_EN_RX_COAL_TIME :
845 coal->rx_coalesce_usecs;
846
a19a848a
YP		 847 /* Setting TX coalescing parameters */
848 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
849 coal->tx_max_coalesced_frames != priv->tx_frames) {
850 priv->tx_usecs = coal->tx_coalesce_usecs;
851 priv->tx_frames = coal->tx_max_coalesced_frames;
a19a848a
YP		 852 }
853
c27a02cd
YP		 854 /* Set adaptive coalescing params */
855 priv->pkt_rate_low = coal->pkt_rate_low;
856 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
857 priv->pkt_rate_high = coal->pkt_rate_high;
858 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
859 priv->sample_interval = coal->rate_sample_interval;
860 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
fbc6daf1 861 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
c27a02cd 862
79c54b6b 863 return mlx4_en_moderation_update(priv);
c27a02cd
YP		 864}
865
866static int mlx4_en_set_pauseparam(struct net_device *dev,
867 struct ethtool_pauseparam *pause)
868{
869 struct mlx4_en_priv *priv = netdev_priv(dev);
870 struct mlx4_en_dev *mdev = priv->mdev;
871 int err;
872
278d436a
IV		 873 if (pause->autoneg)
874 return -EINVAL;
875
d53b93f2
YP		 876 priv->prof->tx_pause = pause->tx_pause != 0;
877 priv->prof->rx_pause = pause->rx_pause != 0;
c27a02cd
YP		 878 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
879 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 880 priv->prof->tx_pause,
881 priv->prof->tx_ppp,
882 priv->prof->rx_pause,
883 priv->prof->rx_ppp);
c27a02cd 884 if (err)
453a6082 885 en_err(priv, "Failed setting pause params\n");
c27a02cd
YP		 886
887 return err;
888}
889
890static void mlx4_en_get_pauseparam(struct net_device *dev,
891 struct ethtool_pauseparam *pause)
892{
893 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd 894
d53b93f2
YP		 895 pause->tx_pause = priv->prof->tx_pause;
896 pause->rx_pause = priv->prof->rx_pause;
c27a02cd
YP		 897}
898
18cc42a3
YP		 899static int mlx4_en_set_ringparam(struct net_device *dev,
900 struct ethtool_ringparam *param)
901{
902 struct mlx4_en_priv *priv = netdev_priv(dev);
903 struct mlx4_en_dev *mdev = priv->mdev;
904 u32 rx_size, tx_size;
905 int port_up = 0;
906 int err = 0;
907
908 if (param->rx_jumbo_pending || param->rx_mini_pending)
909 return -EINVAL;
910
911 rx_size = roundup_pow_of_two(param->rx_pending);
912 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
bd531e36 913 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
18cc42a3
YP		 914 tx_size = roundup_pow_of_two(param->tx_pending);
915 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
bd531e36 916 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
18cc42a3 917
41d942d5
EE		 918 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
919 priv->rx_ring[0]->size) &&
920 tx_size == priv->tx_ring[0]->size)
18cc42a3
YP		 921 return 0;
922
923 mutex_lock(&mdev->state_lock);
924 if (priv->port_up) {
925 port_up = 1;
3484aac1 926 mlx4_en_stop_port(dev, 1);
18cc42a3
YP		 927 }
928
fe0af03c 929 mlx4_en_free_resources(priv);
18cc42a3
YP		 930
931 priv->prof->tx_ring_size = tx_size;
932 priv->prof->rx_ring_size = rx_size;
933
934 err = mlx4_en_alloc_resources(priv);
935 if (err) {
453a6082 936 en_err(priv, "Failed reallocating port resources\n");
18cc42a3
YP		 937 goto out;
938 }
939 if (port_up) {
940 err = mlx4_en_start_port(dev);
941 if (err)
453a6082 942 en_err(priv, "Failed starting port\n");
18cc42a3
YP		 943 }
944
79c54b6b 945 err = mlx4_en_moderation_update(priv);
6b4d8d9f 946
18cc42a3
YP		 947out:
948 mutex_unlock(&mdev->state_lock);
949 return err;
950}
951
c27a02cd
YP		 952static void mlx4_en_get_ringparam(struct net_device *dev,
953 struct ethtool_ringparam *param)
954{
955 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP		 956
957 memset(param, 0, sizeof(*param));
bd531e36
YP		 958 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
959 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
bc081cec 960 param->rx_pending = priv->port_up ?
41d942d5
EE		 961 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
962 param->tx_pending = priv->tx_ring[0]->size;
c27a02cd
YP		 963}
964
93d3e367
YP		 965static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
966{
967 struct mlx4_en_priv *priv = netdev_priv(dev);
968
969 return priv->rx_ring_num;
970}
971
b9d1ab7e
ED		 972static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
973{
974 return MLX4_EN_RSS_KEY_SIZE;
975}
976
947cbb0a
EP		 977static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
978{
979 struct mlx4_en_priv *priv = netdev_priv(dev);
980
981 /* check if requested function is supported by the device */
982 if ((hfunc == ETH_RSS_HASH_TOP &&
983 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) ||
984 (hfunc == ETH_RSS_HASH_XOR &&
985 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)))
986 return -EINVAL;
987
988 priv->rss_hash_fn = hfunc;
989 if (hfunc == ETH_RSS_HASH_TOP && !(dev->features & NETIF_F_RXHASH))
990 en_warn(priv,
991 "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
992 if (hfunc == ETH_RSS_HASH_XOR && (dev->features & NETIF_F_RXHASH))
993 en_warn(priv,
994 "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
995 return 0;
996}
997
892311f6
EP		 998static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
999 u8 *hfunc)
93d3e367
YP		 1000{
1001 struct mlx4_en_priv *priv = netdev_priv(dev);
1002 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1003 int rss_rings;
1004 size_t n = priv->rx_ring_num;
1005 int err = 0;
1006
1007 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num;
d5ec899a 1008 rss_rings = 1 << ilog2(rss_rings);
93d3e367
YP		 1009
1010 while (n--) {
892311f6
EP		 1011 if (!ring_index)
1012 break;
93d3e367
YP		 1013 ring_index[n] = rss_map->qps[n % rss_rings].qpn -
1014 rss_map->base_qpn;
1015 }
b9d1ab7e 1016 if (key)
bd635c35 1017 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
892311f6 1018 if (hfunc)
947cbb0a 1019 *hfunc = priv->rss_hash_fn;
93d3e367
YP		 1020 return err;
1021}
1022
fe62d001 1023static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
892311f6 1024 const u8 *key, const u8 hfunc)
93d3e367
YP		 1025{
1026 struct mlx4_en_priv *priv = netdev_priv(dev);
1027 struct mlx4_en_dev *mdev = priv->mdev;
1028 int port_up = 0;
1029 int err = 0;
1030 int i;
1031 int rss_rings = 0;
1032
1033 /* Calculate RSS table size and make sure flows are spread evenly
1034 * between rings
1035 */
1036 for (i = 0; i < priv->rx_ring_num; i++) {
bd635c35
ED		 1037 if (!ring_index)
1038 continue;
93d3e367
YP		 1039 if (i > 0 && !ring_index[i] && !rss_rings)
1040 rss_rings = i;
1041
1042 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num)))
1043 return -EINVAL;
1044 }
1045
1046 if (!rss_rings)
1047 rss_rings = priv->rx_ring_num;
1048
1049 /* RSS table size must be an order of 2 */
1050 if (!is_power_of_2(rss_rings))
1051 return -EINVAL;
1052
947cbb0a
EP		 1053 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1054 err = mlx4_en_check_rxfh_func(dev, hfunc);
1055 if (err)
1056 return err;
1057 }
1058
93d3e367
YP		 1059 mutex_lock(&mdev->state_lock);
1060 if (priv->port_up) {
1061 port_up = 1;
3484aac1 1062 mlx4_en_stop_port(dev, 1);
93d3e367
YP		 1063 }
1064
bd635c35
ED		 1065 if (ring_index)
1066 priv->prof->rss_rings = rss_rings;
1067 if (key)
1068 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
947cbb0a 1069
93d3e367
YP		 1070 if (port_up) {
1071 err = mlx4_en_start_port(dev);
1072 if (err)
1073 en_err(priv, "Failed starting port\n");
1074 }
1075
1076 mutex_unlock(&mdev->state_lock);
1077 return err;
1078}
1079
82067281
HHZ		 1080#define all_zeros_or_all_ones(field) \
1081 ((field) == 0 || (field) == (__force typeof(field))-1)
1082
1083static int mlx4_en_validate_flow(struct net_device *dev,
1084 struct ethtool_rxnfc *cmd)
1085{
1086 struct ethtool_usrip4_spec *l3_mask;
1087 struct ethtool_tcpip4_spec *l4_mask;
1088 struct ethhdr *eth_mask;
82067281
HHZ		 1089
1090 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1091 return -EINVAL;
1092
520dfe3a
YB		 1093 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1094 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1095 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1096 return -EINVAL;
1097 }
1098
1099 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
82067281
HHZ		 1100 case TCP_V4_FLOW:
1101 case UDP_V4_FLOW:
1102 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1103 return -EINVAL;
1104 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1105 /* don't allow mask which isn't all 0 or 1 */
1106 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1107 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1108 !all_zeros_or_all_ones(l4_mask->psrc) ||
1109 !all_zeros_or_all_ones(l4_mask->pdst))
1110 return -EINVAL;
1111 break;
1112 case IP_USER_FLOW:
1113 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1114 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1115 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1116 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1117 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1118 !all_zeros_or_all_ones(l3_mask->ip4dst))
1119 return -EINVAL;
1120 break;
1121 case ETHER_FLOW:
1122 eth_mask = &cmd->fs.m_u.ether_spec;
1123 /* source mac mask must not be set */
c402b947 1124 if (!is_zero_ether_addr(eth_mask->h_source))
82067281
HHZ		 1125 return -EINVAL;
1126
1127 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
c402b947 1128 if (!is_broadcast_ether_addr(eth_mask->h_dest))
82067281
HHZ		 1129 return -EINVAL;
1130
1131 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1132 return -EINVAL;
1133 break;
1134 default:
1135 return -EINVAL;
1136 }
1137
1138 if ((cmd->fs.flow_type & FLOW_EXT)) {
1139 if (cmd->fs.m_ext.vlan_etype ||
8258bd27
HHZ		 1140 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1141 0 ||
1142 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1143 cpu_to_be16(VLAN_VID_MASK)))
82067281 1144 return -EINVAL;
8258bd27 1145
69d7126b
HHZ		 1146 if (cmd->fs.m_ext.vlan_tci) {
1147 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1148 return -EINVAL;
8258bd27 1149
69d7126b 1150 }
82067281
HHZ		 1151 }
1152
1153 return 0;
1154}
1155
f90a3673
HHZ		 1156static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1157 struct list_head *rule_list_h,
1158 struct mlx4_spec_list *spec_l2,
1159 unsigned char *mac)
1160{
1161 int err = 0;
1162 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1163
1164 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1165 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1166 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1167
8258bd27
HHZ		 1168 if ((cmd->fs.flow_type & FLOW_EXT) &&
1169 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
f90a3673 1170 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
8258bd27 1171 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
f90a3673
HHZ		 1172 }
1173
1174 list_add_tail(&spec_l2->list, rule_list_h);
1175
1176 return err;
1177}
1178
1179static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1180 struct ethtool_rxnfc *cmd,
1181 struct list_head *rule_list_h,
1182 struct mlx4_spec_list *spec_l2,
1183 __be32 ipv4_dst)
1184{
f9d96862 1185#ifdef CONFIG_INET
f90a3673
HHZ		 1186 unsigned char mac[ETH_ALEN];
1187
1188 if (!ipv4_is_multicast(ipv4_dst)) {
6bbb6d99 1189 if (cmd->fs.flow_type & FLOW_MAC_EXT)
f90a3673 1190 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
6bbb6d99
YB		 1191 else
1192 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
f90a3673
HHZ		 1193 } else {
1194 ip_eth_mc_map(ipv4_dst, mac);
1195 }
1196
1197 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
f9d96862
HHZ		 1198#else
1199 return -EINVAL;
1200#endif
f90a3673
HHZ		 1201}
1202
82067281 1203static int add_ip_rule(struct mlx4_en_priv *priv,
f90a3673
HHZ		 1204 struct ethtool_rxnfc *cmd,
1205 struct list_head *list_h)
82067281 1206{
377d9739 1207 int err;
f90a3673
HHZ		 1208 struct mlx4_spec_list *spec_l2 = NULL;
1209 struct mlx4_spec_list *spec_l3 = NULL;
82067281
HHZ		 1210 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1211
f90a3673
HHZ		 1212 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1213 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1214 if (!spec_l2 || !spec_l3) {
377d9739
HHZ		 1215 err = -ENOMEM;
1216 goto free_spec;
82067281
HHZ		 1217 }
1218
377d9739
HHZ		 1219 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1220 cmd->fs.h_u.
1221 usr_ip4_spec.ip4dst);
1222 if (err)
1223 goto free_spec;
82067281
HHZ		 1224 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1225 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1226 if (l3_mask->ip4src)
1227 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1228 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1229 if (l3_mask->ip4dst)
1230 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1231 list_add_tail(&spec_l3->list, list_h);
1232
1233 return 0;
377d9739
HHZ		 1234
1235free_spec:
1236 kfree(spec_l2);
1237 kfree(spec_l3);
1238 return err;
82067281
HHZ		 1239}
1240
1241static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1242 struct ethtool_rxnfc *cmd,
1243 struct list_head *list_h, int proto)
1244{
377d9739 1245 int err;
f90a3673
HHZ		 1246 struct mlx4_spec_list *spec_l2 = NULL;
1247 struct mlx4_spec_list *spec_l3 = NULL;
1248 struct mlx4_spec_list *spec_l4 = NULL;
82067281
HHZ		 1249 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1250
f90a3673
HHZ		 1251 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1252 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1253 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1254 if (!spec_l2 || !spec_l3 || !spec_l4) {
377d9739
HHZ		 1255 err = -ENOMEM;
1256 goto free_spec;
82067281
HHZ		 1257 }
1258
1259 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1260
1261 if (proto == TCP_V4_FLOW) {
377d9739
HHZ		 1262 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1263 spec_l2,
1264 cmd->fs.h_u.
1265 tcp_ip4_spec.ip4dst);
1266 if (err)
1267 goto free_spec;
82067281
HHZ		 1268 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1269 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1270 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1271 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1272 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1273 } else {
377d9739
HHZ		 1274 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1275 spec_l2,
1276 cmd->fs.h_u.
1277 udp_ip4_spec.ip4dst);
1278 if (err)
1279 goto free_spec;
82067281
HHZ		 1280 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1281 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1282 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1283 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1284 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1285 }
1286
1287 if (l4_mask->ip4src)
1288 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1289 if (l4_mask->ip4dst)
1290 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1291
1292 if (l4_mask->psrc)
1293 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1294 if (l4_mask->pdst)
1295 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1296
1297 list_add_tail(&spec_l3->list, list_h);
1298 list_add_tail(&spec_l4->list, list_h);
1299
1300 return 0;
377d9739
HHZ		 1301
1302free_spec:
1303 kfree(spec_l2);
1304 kfree(spec_l3);
1305 kfree(spec_l4);
1306 return err;
82067281
HHZ		 1307}
1308
1309static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1310 struct ethtool_rxnfc *cmd,
1311 struct list_head *rule_list_h)
1312{
1313 int err;
82067281 1314 struct ethhdr *eth_spec;
82067281 1315 struct mlx4_spec_list *spec_l2;
f90a3673 1316 struct mlx4_en_priv *priv = netdev_priv(dev);
82067281
HHZ		 1317
1318 err = mlx4_en_validate_flow(dev, cmd);
1319 if (err)
1320 return err;
1321
520dfe3a 1322 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
82067281 1323 case ETHER_FLOW:
f90a3673
HHZ		 1324 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1325 if (!spec_l2)
1326 return -ENOMEM;
1327
82067281 1328 eth_spec = &cmd->fs.h_u.ether_spec;
f90a3673
HHZ		 1329 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1330 &eth_spec->h_dest[0]);
82067281
HHZ		 1331 spec_l2->eth.ether_type = eth_spec->h_proto;
1332 if (eth_spec->h_proto)
1333 spec_l2->eth.ether_type_enable = 1;
1334 break;
1335 case IP_USER_FLOW:
1336 err = add_ip_rule(priv, cmd, rule_list_h);
1337 break;
1338 case TCP_V4_FLOW:
1339 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1340 break;
1341 case UDP_V4_FLOW:
1342 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1343 break;
1344 }
1345
1346 return err;
1347}
1348
1349static int mlx4_en_flow_replace(struct net_device *dev,
1350 struct ethtool_rxnfc *cmd)
1351{
1352 int err;
1353 struct mlx4_en_priv *priv = netdev_priv(dev);
1354 struct ethtool_flow_id *loc_rule;
1355 struct mlx4_spec_list *spec, *tmp_spec;
1356 u32 qpn;
1357 u64 reg_id;
1358
1359 struct mlx4_net_trans_rule rule = {
1360 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1361 .exclusive = 0,
1362 .allow_loopback = 1,
f9162539 1363 .promisc_mode = MLX4_FS_REGULAR,
82067281
HHZ		 1364 };
1365
1366 rule.port = priv->port;
1367 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1368 INIT_LIST_HEAD(&rule.list);
1369
1370 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1371 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
cabdc8ee 1372 qpn = priv->drop_qp.qpn;
82067281
HHZ		 1373 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1374 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1375 } else {
1376 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1a91de28 1377 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
82067281
HHZ		 1378 cmd->fs.ring_cookie);
1379 return -EINVAL;
1380 }
1381 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1382 if (!qpn) {
1a91de28 1383 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
82067281
HHZ		 1384 cmd->fs.ring_cookie);
1385 return -EINVAL;
1386 }
1387 }
1388 rule.qpn = qpn;
1389 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1390 if (err)
1391 goto out_free_list;
1392
1393 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1394 if (loc_rule->id) {
1395 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1396 if (err) {
1397 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1398 cmd->fs.location, loc_rule->id);
1399 goto out_free_list;
1400 }
1401 loc_rule->id = 0;
1402 memset(&loc_rule->flow_spec, 0,
1403 sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1404 list_del(&loc_rule->list);
82067281
HHZ		 1405 }
1406 err = mlx4_flow_attach(priv->mdev->dev, &rule, &reg_id);
1407 if (err) {
1a91de28 1408 en_err(priv, "Fail to attach network rule at location %d\n",
82067281
HHZ		 1409 cmd->fs.location);
1410 goto out_free_list;
1411 }
1412 loc_rule->id = reg_id;
1413 memcpy(&loc_rule->flow_spec, &cmd->fs,
1414 sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1415 list_add_tail(&loc_rule->list, &priv->ethtool_list);
82067281
HHZ		 1416
1417out_free_list:
1418 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1419 list_del(&spec->list);
1420 kfree(spec);
1421 }
1422 return err;
1423}
1424
1425static int mlx4_en_flow_detach(struct net_device *dev,
1426 struct ethtool_rxnfc *cmd)
1427{
1428 int err = 0;
1429 struct ethtool_flow_id *rule;
1430 struct mlx4_en_priv *priv = netdev_priv(dev);
1431
1432 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1433 return -EINVAL;
1434
1435 rule = &priv->ethtool_rules[cmd->fs.location];
1436 if (!rule->id) {
1437 err = -ENOENT;
1438 goto out;
1439 }
1440
1441 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1442 if (err) {
1443 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1444 cmd->fs.location, rule->id);
1445 goto out;
1446 }
1447 rule->id = 0;
1448 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1449 list_del(&rule->list);
82067281
HHZ		 1450out:
1451 return err;
1452
1453}
1454
1455static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1456 int loc)
1457{
1458 int err = 0;
1459 struct ethtool_flow_id *rule;
1460 struct mlx4_en_priv *priv = netdev_priv(dev);
1461
1462 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1463 return -EINVAL;
1464
1465 rule = &priv->ethtool_rules[loc];
1466 if (rule->id)
1467 memcpy(&cmd->fs, &rule->flow_spec,
1468 sizeof(struct ethtool_rx_flow_spec));
1469 else
1470 err = -ENOENT;
1471
1472 return err;
1473}
1474
1475static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1476{
1477
1478 int i, res = 0;
1479 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1480 if (priv->ethtool_rules[i].id)
1481 res++;
1482 }
1483 return res;
1484
1485}
1486
93d3e367
YP		 1487static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1488 u32 *rule_locs)
1489{
1490 struct mlx4_en_priv *priv = netdev_priv(dev);
82067281 1491 struct mlx4_en_dev *mdev = priv->mdev;
93d3e367 1492 int err = 0;
82067281
HHZ		 1493 int i = 0, priority = 0;
1494
1495 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1496 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1497 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
280fce1e
HHZ		 1498 (mdev->dev->caps.steering_mode !=
1499 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
82067281 1500 return -EINVAL;
93d3e367
YP		 1501
1502 switch (cmd->cmd) {
1503 case ETHTOOL_GRXRINGS:
1504 cmd->data = priv->rx_ring_num;
1505 break;
82067281
HHZ		 1506 case ETHTOOL_GRXCLSRLCNT:
1507 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1508 break;
1509 case ETHTOOL_GRXCLSRULE:
1510 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1511 break;
1512 case ETHTOOL_GRXCLSRLALL:
1513 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1514 err = mlx4_en_get_flow(dev, cmd, i);
1515 if (!err)
1516 rule_locs[priority++] = i;
1517 i++;
1518 }
1519 err = 0;
1520 break;
93d3e367
YP		 1521 default:
1522 err = -EOPNOTSUPP;
1523 break;
1524 }
1525
1526 return err;
1527}
1528
82067281
HHZ		 1529static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1530{
1531 int err = 0;
1532 struct mlx4_en_priv *priv = netdev_priv(dev);
1533 struct mlx4_en_dev *mdev = priv->mdev;
1534
280fce1e
HHZ		 1535 if (mdev->dev->caps.steering_mode !=
1536 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
82067281
HHZ		 1537 return -EINVAL;
1538
1539 switch (cmd->cmd) {
1540 case ETHTOOL_SRXCLSRLINS:
1541 err = mlx4_en_flow_replace(dev, cmd);
1542 break;
1543 case ETHTOOL_SRXCLSRLDEL:
1544 err = mlx4_en_flow_detach(dev, cmd);
1545 break;
1546 default:
1547 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1548 return -EINVAL;
1549 }
1550
1551 return err;
1552}
1553
d317966b
AV		 1554static void mlx4_en_get_channels(struct net_device *dev,
1555 struct ethtool_channels *channel)
1556{
1557 struct mlx4_en_priv *priv = netdev_priv(dev);
1558
1559 memset(channel, 0, sizeof(*channel));
1560
1561 channel->max_rx = MAX_RX_RINGS;
1562 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1563
1564 channel->rx_count = priv->rx_ring_num;
1565 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
1566}
1567
1568static int mlx4_en_set_channels(struct net_device *dev,
1569 struct ethtool_channels *channel)
1570{
1571 struct mlx4_en_priv *priv = netdev_priv(dev);
1572 struct mlx4_en_dev *mdev = priv->mdev;
da26a625 1573 int port_up = 0;
d317966b
AV		 1574 int err = 0;
1575
1576 if (channel->other_count || channel->combined_count ||
1577 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
1578 channel->rx_count > MAX_RX_RINGS ||
1579 !channel->tx_count || !channel->rx_count)
1580 return -EINVAL;
1581
1582 mutex_lock(&mdev->state_lock);
1583 if (priv->port_up) {
1584 port_up = 1;
3484aac1 1585 mlx4_en_stop_port(dev, 1);
d317966b
AV		 1586 }
1587
1588 mlx4_en_free_resources(priv);
1589
1590 priv->num_tx_rings_p_up = channel->tx_count;
1591 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
1592 priv->rx_ring_num = channel->rx_count;
1593
1594 err = mlx4_en_alloc_resources(priv);
1595 if (err) {
1596 en_err(priv, "Failed reallocating port resources\n");
1597 goto out;
1598 }
1599
1600 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
1601 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1602
f5b6345b
IS		 1603 if (dev->num_tc)
1604 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
d317966b
AV		 1605
1606 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
1607 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1608
1609 if (port_up) {
1610 err = mlx4_en_start_port(dev);
1611 if (err)
1612 en_err(priv, "Failed starting port\n");
1613 }
1614
1615 err = mlx4_en_moderation_update(priv);
1616
1617out:
1618 mutex_unlock(&mdev->state_lock);
1619 return err;
1620}
1621
ec693d47
AV		 1622static int mlx4_en_get_ts_info(struct net_device *dev,
1623 struct ethtool_ts_info *info)
1624{
1625 struct mlx4_en_priv *priv = netdev_priv(dev);
1626 struct mlx4_en_dev *mdev = priv->mdev;
1627 int ret;
1628
1629 ret = ethtool_op_get_ts_info(dev, info);
1630 if (ret)
1631 return ret;
1632
1633 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1634 info->so_timestamping |=
1635 SOF_TIMESTAMPING_TX_HARDWARE |
1636 SOF_TIMESTAMPING_RX_HARDWARE |
1637 SOF_TIMESTAMPING_RAW_HARDWARE;
1638
1639 info->tx_types =
1640 (1 << HWTSTAMP_TX_OFF) |
1641 (1 << HWTSTAMP_TX_ON);
1642
1643 info->rx_filters =
1644 (1 << HWTSTAMP_FILTER_NONE) |
1645 (1 << HWTSTAMP_FILTER_ALL);
ad7d4eae
SB		 1646
1647 if (mdev->ptp_clock)
1648 info->phc_index = ptp_clock_index(mdev->ptp_clock);
ec693d47
AV		 1649 }
1650
1651 return ret;
1652}
1653
3f6148e7 1654static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
0fef9d03
AV		 1655{
1656 struct mlx4_en_priv *priv = netdev_priv(dev);
1657 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1658 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1659 int i;
1660
1661 if (bf_enabled_new == bf_enabled_old)
1662 return 0; /* Nothing to do */
1663
1664 if (bf_enabled_new) {
1665 bool bf_supported = true;
1666
1667 for (i = 0; i < priv->tx_ring_num; i++)
1668 bf_supported &= priv->tx_ring[i]->bf_alloced;
1669
1670 if (!bf_supported) {
1671 en_err(priv, "BlueFlame is not supported\n");
1672 return -EINVAL;
1673 }
1674
1675 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1676 } else {
1677 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1678 }
1679
1680 for (i = 0; i < priv->tx_ring_num; i++)
1681 priv->tx_ring[i]->bf_enabled = bf_enabled_new;
1682
1683 en_info(priv, "BlueFlame %s\n",
1684 bf_enabled_new ? "Enabled" : "Disabled");
1685
1686 return 0;
1687}
1688
3f6148e7 1689static u32 mlx4_en_get_priv_flags(struct net_device *dev)
0fef9d03
AV		 1690{
1691 struct mlx4_en_priv *priv = netdev_priv(dev);
1692
1693 return priv->pflags;
1694}
1695
1556b874
ED		 1696static int mlx4_en_get_tunable(struct net_device *dev,
1697 const struct ethtool_tunable *tuna,
1698 void *data)
1699{
1700 const struct mlx4_en_priv *priv = netdev_priv(dev);
1701 int ret = 0;
1702
1703 switch (tuna->id) {
1704 case ETHTOOL_TX_COPYBREAK:
1705 *(u32 *)data = priv->prof->inline_thold;
1706 break;
1707 default:
1708 ret = -EINVAL;
1709 break;
1710 }
1711
1712 return ret;
1713}
1714
1715static int mlx4_en_set_tunable(struct net_device *dev,
1716 const struct ethtool_tunable *tuna,
1717 const void *data)
1718{
1719 struct mlx4_en_priv *priv = netdev_priv(dev);
1720 int val, ret = 0;
1721
1722 switch (tuna->id) {
1723 case ETHTOOL_TX_COPYBREAK:
1724 val = *(u32 *)data;
1725 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1726 ret = -EINVAL;
1727 else
1728 priv->prof->inline_thold = val;
1729 break;
1730 default:
1731 ret = -EINVAL;
1732 break;
1733 }
1734
1735 return ret;
1736}
1737
7202da8b
SM		 1738static int mlx4_en_get_module_info(struct net_device *dev,
1739 struct ethtool_modinfo *modinfo)
1740{
1741 struct mlx4_en_priv *priv = netdev_priv(dev);
1742 struct mlx4_en_dev *mdev = priv->mdev;
1743 int ret;
1744 u8 data[4];
1745
1746 /* Read first 2 bytes to get Module & REV ID */
1747 ret = mlx4_get_module_info(mdev->dev, priv->port,
1748 0/*offset*/, 2/*size*/, data);
1749 if (ret < 2)
1750 return -EIO;
1751
1752 switch (data[0] /* identifier */) {
1753 case MLX4_MODULE_ID_QSFP:
1754 modinfo->type = ETH_MODULE_SFF_8436;
1755 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1756 break;
1757 case MLX4_MODULE_ID_QSFP_PLUS:
1758 if (data[1] >= 0x3) { /* revision id */
1759 modinfo->type = ETH_MODULE_SFF_8636;
1760 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1761 } else {
1762 modinfo->type = ETH_MODULE_SFF_8436;
1763 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1764 }
1765 break;
1766 case MLX4_MODULE_ID_QSFP28:
1767 modinfo->type = ETH_MODULE_SFF_8636;
1768 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1769 break;
1770 case MLX4_MODULE_ID_SFP:
1771 modinfo->type = ETH_MODULE_SFF_8472;
1772 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1773 break;
1774 default:
1775 return -ENOSYS;
1776 }
1777
1778 return 0;
1779}
1780
1781static int mlx4_en_get_module_eeprom(struct net_device *dev,
1782 struct ethtool_eeprom *ee,
1783 u8 *data)
1784{
1785 struct mlx4_en_priv *priv = netdev_priv(dev);
1786 struct mlx4_en_dev *mdev = priv->mdev;
1787 int offset = ee->offset;
1788 int i = 0, ret;
1789
1790 if (ee->len == 0)
1791 return -EINVAL;
1792
1793 memset(data, 0, ee->len);
1794
1795 while (i < ee->len) {
1796 en_dbg(DRV, priv,
1797 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
1798 i, offset, ee->len - i);
1799
1800 ret = mlx4_get_module_info(mdev->dev, priv->port,
1801 offset, ee->len - i, data + i);
1802
1803 if (!ret) /* Done reading */
1804 return 0;
1805
1806 if (ret < 0) {
1807 en_err(priv,
1808 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
1809 i, offset, ee->len - i, ret);
1810 return 0;
1811 }
1812
1813 i += ret;
1814 offset += ret;
1815 }
1816 return 0;
1817}
0fef9d03 1818
c27a02cd
YP		 1819const struct ethtool_ops mlx4_en_ethtool_ops = {
1820 .get_drvinfo = mlx4_en_get_drvinfo,
1821 .get_settings = mlx4_en_get_settings,
1822 .set_settings = mlx4_en_set_settings,
c27a02cd 1823 .get_link = ethtool_op_get_link,
c27a02cd
YP		 1824 .get_strings = mlx4_en_get_strings,
1825 .get_sset_count = mlx4_en_get_sset_count,
1826 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
e7c1c2c4 1827 .self_test = mlx4_en_self_test,
c27a02cd 1828 .get_wol = mlx4_en_get_wol,
14c07b13 1829 .set_wol = mlx4_en_set_wol,
c27a02cd
YP		 1830 .get_msglevel = mlx4_en_get_msglevel,
1831 .set_msglevel = mlx4_en_set_msglevel,
1832 .get_coalesce = mlx4_en_get_coalesce,
1833 .set_coalesce = mlx4_en_set_coalesce,
1834 .get_pauseparam = mlx4_en_get_pauseparam,
1835 .set_pauseparam = mlx4_en_set_pauseparam,
1836 .get_ringparam = mlx4_en_get_ringparam,
18cc42a3 1837 .set_ringparam = mlx4_en_set_ringparam,
93d3e367 1838 .get_rxnfc = mlx4_en_get_rxnfc,
82067281 1839 .set_rxnfc = mlx4_en_set_rxnfc,
93d3e367 1840 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
b9d1ab7e 1841 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
fe62d001
BH		 1842 .get_rxfh = mlx4_en_get_rxfh,
1843 .set_rxfh = mlx4_en_set_rxfh,
d317966b
AV		 1844 .get_channels = mlx4_en_get_channels,
1845 .set_channels = mlx4_en_set_channels,
ec693d47 1846 .get_ts_info = mlx4_en_get_ts_info,
0fef9d03
AV		 1847 .set_priv_flags = mlx4_en_set_priv_flags,
1848 .get_priv_flags = mlx4_en_get_priv_flags,
1556b874
ED		 1849 .get_tunable = mlx4_en_get_tunable,
1850 .set_tunable = mlx4_en_set_tunable,
7202da8b
SM		 1851 .get_module_info = mlx4_en_get_module_info,
1852 .get_module_eeprom = mlx4_en_get_module_eeprom
c27a02cd
YP		 1853};
1854
1855
1856
1857
1858
Linux 6.x block layer and io_uring tree(s)