projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx4_en: Protect access to the statistics bitmap
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_ethtool.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/ethtool.h>
36#include <linux/netdevice.h>
af22d9de 37#include <linux/mlx4/driver.h>
7202da8b 38#include <linux/mlx4/device.h>
f90a3673
HHZ		 39#include <linux/in.h>
40#include <net/ip.h>
6fcd2735 41#include <linux/bitmap.h>
c27a02cd
YP		 42
43#include "mlx4_en.h"
44#include "en_port.h"
45
82067281 46#define EN_ETHTOOL_QP_ATTACH (1ull << 63)
82067281
HHZ		 47#define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48#define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
c27a02cd 49
79c54b6b
AV		 50static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
51{
52 int i;
53 int err = 0;
54
55 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 56 priv->tx_cq[i]->moder_cnt = priv->tx_frames;
57 priv->tx_cq[i]->moder_time = priv->tx_usecs;
38463e2c 58 if (priv->port_up) {
41d942d5 59 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
38463e2c
EE		 60 if (err)
61 return err;
62 }
79c54b6b
AV		 63 }
64
65 if (priv->adaptive_rx_coal)
66 return 0;
67
68 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 69 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
70 priv->rx_cq[i]->moder_time = priv->rx_usecs;
79c54b6b 71 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
38463e2c 72 if (priv->port_up) {
41d942d5 73 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
38463e2c
EE		 74 if (err)
75 return err;
76 }
79c54b6b
AV		 77 }
78
79 return err;
80}
81
c27a02cd
YP		 82static void
83mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
84{
85 struct mlx4_en_priv *priv = netdev_priv(dev);
86 struct mlx4_en_dev *mdev = priv->mdev;
87
612a94d6
RJ		 88 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
89 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
90 sizeof(drvinfo->version));
91 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
92 "%d.%d.%d",
c27a02cd
YP		 93 (u16) (mdev->dev->caps.fw_ver >> 32),
94 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
95 (u16) (mdev->dev->caps.fw_ver & 0xffff));
872bf2fb 96 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
612a94d6 97 sizeof(drvinfo->bus_info));
c27a02cd
YP		 98 drvinfo->n_stats = 0;
99 drvinfo->regdump_len = 0;
100 drvinfo->eedump_len = 0;
101}
102
0fef9d03
AV		 103static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
104 "blueflame",
105};
106
c27a02cd 107static const char main_strings[][ETH_GSTRING_LEN] = {
6fcd2735 108 /* main statistics */
c27a02cd
YP		 109 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
110 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
111 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
112 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
113 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
114 "tx_heartbeat_errors", "tx_window_errors",
115
116 /* port statistics */
fa37a958 117 "tso_packets",
9fab426d 118 "xmit_more",
c27a02cd 119 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
f8c6455b 120 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
c27a02cd
YP		 121
122 /* packet statistics */
123 "broadcast", "rx_prio_0", "rx_prio_1", "rx_prio_2", "rx_prio_3",
124 "rx_prio_4", "rx_prio_5", "rx_prio_6", "rx_prio_7", "tx_prio_0",
125 "tx_prio_1", "tx_prio_2", "tx_prio_3", "tx_prio_4", "tx_prio_5",
126 "tx_prio_6", "tx_prio_7",
127};
c27a02cd 128
e7c1c2c4 129static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
fd9071ec 130 "Interrupt Test",
e7c1c2c4
YP		 131 "Link Test",
132 "Speed Test",
133 "Register Test",
134 "Loopback Test",
135};
136
c27a02cd
YP		 137static u32 mlx4_en_get_msglevel(struct net_device *dev)
138{
139 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
140}
141
142static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
143{
144 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
145}
146
147static void mlx4_en_get_wol(struct net_device *netdev,
148 struct ethtool_wolinfo *wol)
149{
14c07b13
YP		 150 struct mlx4_en_priv *priv = netdev_priv(netdev);
151 int err = 0;
152 u64 config = 0;
559a9f1d 153 u64 mask;
14c07b13 154
559a9f1d
OD		 155 if ((priv->port < 1) || (priv->port > 2)) {
156 en_err(priv, "Failed to get WoL information\n");
157 return;
158 }
159
160 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
161 MLX4_DEV_CAP_FLAG_WOL_PORT2;
162
163 if (!(priv->mdev->dev->caps.flags & mask)) {
14c07b13
YP		 164 wol->supported = 0;
165 wol->wolopts = 0;
166 return;
167 }
168
169 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
170 if (err) {
171 en_err(priv, "Failed to get WoL information\n");
172 return;
173 }
174
175 if (config & MLX4_EN_WOL_MAGIC)
176 wol->supported = WAKE_MAGIC;
177 else
178 wol->supported = 0;
179
180 if (config & MLX4_EN_WOL_ENABLED)
181 wol->wolopts = WAKE_MAGIC;
182 else
183 wol->wolopts = 0;
184}
185
186static int mlx4_en_set_wol(struct net_device *netdev,
187 struct ethtool_wolinfo *wol)
188{
189 struct mlx4_en_priv *priv = netdev_priv(netdev);
190 u64 config = 0;
191 int err = 0;
559a9f1d
OD		 192 u64 mask;
193
194 if ((priv->port < 1) || (priv->port > 2))
195 return -EOPNOTSUPP;
196
197 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
198 MLX4_DEV_CAP_FLAG_WOL_PORT2;
14c07b13 199
559a9f1d 200 if (!(priv->mdev->dev->caps.flags & mask))
14c07b13
YP		 201 return -EOPNOTSUPP;
202
203 if (wol->supported & ~WAKE_MAGIC)
204 return -EINVAL;
205
206 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
207 if (err) {
208 en_err(priv, "Failed to get WoL info, unable to modify\n");
209 return err;
210 }
211
212 if (wol->wolopts & WAKE_MAGIC) {
213 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
214 MLX4_EN_WOL_MAGIC;
215 } else {
216 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
217 config |= MLX4_EN_WOL_DO_MODIFY;
218 }
219
220 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
221 if (err)
222 en_err(priv, "Failed to set WoL information\n");
223
224 return err;
c27a02cd
YP		 225}
226
6fcd2735
EBE		 227struct bitmap_iterator {
228 unsigned long *stats_bitmap;
229 unsigned int count;
230 unsigned int iterator;
231 bool advance_array; /* if set, force no increments */
232};
233
234static inline void bitmap_iterator_init(struct bitmap_iterator *h,
235 unsigned long *stats_bitmap,
236 int count)
237{
238 h->iterator = 0;
239 h->advance_array = !bitmap_empty(stats_bitmap, count);
240 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
241 : count;
242 h->stats_bitmap = stats_bitmap;
243}
244
245static inline int bitmap_iterator_test(struct bitmap_iterator *h)
246{
247 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
248}
249
250static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
251{
252 return h->iterator++;
253}
254
255static inline unsigned int
256bitmap_iterator_count(struct bitmap_iterator *h)
257{
258 return h->count;
259}
260
c27a02cd
YP		 261static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
262{
263 struct mlx4_en_priv *priv = netdev_priv(dev);
6fcd2735
EBE		 264 struct bitmap_iterator it;
265
3da8a36c 266 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
c27a02cd 267
e7c1c2c4
YP		 268 switch (sset) {
269 case ETH_SS_STATS:
6fcd2735 270 return bitmap_iterator_count(&it) +
8501841a 271 (priv->tx_ring_num * 2) +
e0d1095a 272#ifdef CONFIG_NET_RX_BUSY_POLL
8501841a
AV		 273 (priv->rx_ring_num * 5);
274#else
275 (priv->rx_ring_num * 2);
276#endif
e7c1c2c4 277 case ETH_SS_TEST:
ccf86321
OG		 278 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
279 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
0fef9d03
AV		 280 case ETH_SS_PRIV_FLAGS:
281 return ARRAY_SIZE(mlx4_en_priv_flags);
e7c1c2c4 282 default:
c27a02cd 283 return -EOPNOTSUPP;
e7c1c2c4 284 }
c27a02cd
YP		 285}
286
287static void mlx4_en_get_ethtool_stats(struct net_device *dev,
288 struct ethtool_stats *stats, uint64_t *data)
289{
290 struct mlx4_en_priv *priv = netdev_priv(dev);
291 int index = 0;
6fcd2735
EBE		 292 int i;
293 struct bitmap_iterator it;
294
3da8a36c 295 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
c27a02cd
YP		 296
297 spin_lock_bh(&priv->stats_lock);
298
6fcd2735
EBE		 299 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
300 if (bitmap_iterator_test(&it))
301 data[index++] = ((unsigned long *)&priv->stats)[i];
302
303 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
304 if (bitmap_iterator_test(&it))
305 data[index++] = ((unsigned long *)&priv->port_stats)[i];
306
307 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
308 if (bitmap_iterator_test(&it))
309 data[index++] = ((unsigned long *)&priv->pkstats)[i];
310
c27a02cd 311 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 312 data[index++] = priv->tx_ring[i]->packets;
313 data[index++] = priv->tx_ring[i]->bytes;
c27a02cd
YP		 314 }
315 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 316 data[index++] = priv->rx_ring[i]->packets;
317 data[index++] = priv->rx_ring[i]->bytes;
e0d1095a 318#ifdef CONFIG_NET_RX_BUSY_POLL
41d942d5
EE		 319 data[index++] = priv->rx_ring[i]->yields;
320 data[index++] = priv->rx_ring[i]->misses;
321 data[index++] = priv->rx_ring[i]->cleaned;
8501841a 322#endif
c27a02cd 323 }
c27a02cd
YP		 324 spin_unlock_bh(&priv->stats_lock);
325
326}
327
e7c1c2c4
YP		 328static void mlx4_en_self_test(struct net_device *dev,
329 struct ethtool_test *etest, u64 *buf)
330{
331 mlx4_en_ex_selftest(dev, &etest->flags, buf);
332}
333
c27a02cd
YP		 334static void mlx4_en_get_strings(struct net_device *dev,
335 uint32_t stringset, uint8_t *data)
336{
337 struct mlx4_en_priv *priv = netdev_priv(dev);
338 int index = 0;
6fcd2735
EBE		 339 int i, strings = 0;
340 struct bitmap_iterator it;
341
3da8a36c 342 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
c27a02cd 343
e7c1c2c4
YP		 344 switch (stringset) {
345 case ETH_SS_TEST:
346 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
347 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
ccf86321 348 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
e7c1c2c4
YP		 349 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
350 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
351 break;
352
353 case ETH_SS_STATS:
354 /* Add main counters */
6fcd2735
EBE		 355 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
356 bitmap_iterator_inc(&it))
357 if (bitmap_iterator_test(&it))
93ece0c1 358 strcpy(data + (index++) * ETH_GSTRING_LEN,
6fcd2735
EBE		 359 main_strings[strings]);
360
361 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
362 bitmap_iterator_inc(&it))
363 if (bitmap_iterator_test(&it))
93ece0c1 364 strcpy(data + (index++) * ETH_GSTRING_LEN,
6fcd2735
EBE		 365 main_strings[strings]);
366
367 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
368 bitmap_iterator_inc(&it))
369 if (bitmap_iterator_test(&it))
93ece0c1 370 strcpy(data + (index++) * ETH_GSTRING_LEN,
6fcd2735
EBE		 371 main_strings[strings]);
372
e7c1c2c4
YP		 373 for (i = 0; i < priv->tx_ring_num; i++) {
374 sprintf(data + (index++) * ETH_GSTRING_LEN,
375 "tx%d_packets", i);
376 sprintf(data + (index++) * ETH_GSTRING_LEN,
377 "tx%d_bytes", i);
378 }
379 for (i = 0; i < priv->rx_ring_num; i++) {
380 sprintf(data + (index++) * ETH_GSTRING_LEN,
381 "rx%d_packets", i);
382 sprintf(data + (index++) * ETH_GSTRING_LEN,
383 "rx%d_bytes", i);
e0d1095a 384#ifdef CONFIG_NET_RX_BUSY_POLL
8501841a
AV		 385 sprintf(data + (index++) * ETH_GSTRING_LEN,
386 "rx%d_napi_yield", i);
387 sprintf(data + (index++) * ETH_GSTRING_LEN,
388 "rx%d_misses", i);
389 sprintf(data + (index++) * ETH_GSTRING_LEN,
390 "rx%d_cleaned", i);
391#endif
e7c1c2c4 392 }
e7c1c2c4 393 break;
0fef9d03
AV		 394 case ETH_SS_PRIV_FLAGS:
395 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
396 strcpy(data + i * ETH_GSTRING_LEN,
397 mlx4_en_priv_flags[i]);
398 break;
399
e7c1c2c4 400 }
c27a02cd
YP		 401}
402
2c762679
SM		 403static u32 mlx4_en_autoneg_get(struct net_device *dev)
404{
405 struct mlx4_en_priv *priv = netdev_priv(dev);
406 struct mlx4_en_dev *mdev = priv->mdev;
407 u32 autoneg = AUTONEG_DISABLE;
408
409 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
410 (priv->port_state.flags & MLX4_EN_PORT_ANE))
411 autoneg = AUTONEG_ENABLE;
412
413 return autoneg;
414}
415
416static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg)
417{
418 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
419
420 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
421 | MLX4_PROT_MASK(MLX4_1000BASE_T)
422 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
423 return SUPPORTED_TP;
424 }
425
426 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
427 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
428 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
429 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
430 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
431 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
432 return SUPPORTED_FIBRE;
433 }
434
435 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
436 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
437 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
438 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
439 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
440 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
441 return SUPPORTED_Backplane;
442 }
443 return 0;
444}
445
446static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
447{
448 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
449
450 if (!eth_proto) /* link down */
451 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
452
453 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
454 | MLX4_PROT_MASK(MLX4_1000BASE_T)
455 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
456 return PORT_TP;
457 }
458
459 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
460 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
461 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
462 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
463 return PORT_FIBRE;
464 }
465
466 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
467 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
468 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
469 return PORT_DA;
470 }
471
472 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
473 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
474 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
475 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
476 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
477 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
478 return PORT_NONE;
479 }
480 return PORT_OTHER;
481}
482
483#define MLX4_LINK_MODES_SZ \
484 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
485
486enum ethtool_report {
487 SUPPORTED = 0,
488 ADVERTISED = 1,
489 SPEED = 2
490};
491
492/* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
493static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = {
494 [MLX4_100BASE_TX] = {
495 SUPPORTED_100baseT_Full,
496 ADVERTISED_100baseT_Full,
497 SPEED_100
498 },
499
500 [MLX4_1000BASE_T] = {
501 SUPPORTED_1000baseT_Full,
502 ADVERTISED_1000baseT_Full,
503 SPEED_1000
504 },
505 [MLX4_1000BASE_CX_SGMII] = {
506 SUPPORTED_1000baseKX_Full,
507 ADVERTISED_1000baseKX_Full,
508 SPEED_1000
509 },
510 [MLX4_1000BASE_KX] = {
511 SUPPORTED_1000baseKX_Full,
512 ADVERTISED_1000baseKX_Full,
513 SPEED_1000
514 },
515
516 [MLX4_10GBASE_T] = {
517 SUPPORTED_10000baseT_Full,
518 ADVERTISED_10000baseT_Full,
519 SPEED_10000
520 },
521 [MLX4_10GBASE_CX4] = {
522 SUPPORTED_10000baseKX4_Full,
523 ADVERTISED_10000baseKX4_Full,
524 SPEED_10000
525 },
526 [MLX4_10GBASE_KX4] = {
527 SUPPORTED_10000baseKX4_Full,
528 ADVERTISED_10000baseKX4_Full,
529 SPEED_10000
530 },
531 [MLX4_10GBASE_KR] = {
532 SUPPORTED_10000baseKR_Full,
533 ADVERTISED_10000baseKR_Full,
534 SPEED_10000
535 },
536 [MLX4_10GBASE_CR] = {
537 SUPPORTED_10000baseKR_Full,
538 ADVERTISED_10000baseKR_Full,
539 SPEED_10000
540 },
541 [MLX4_10GBASE_SR] = {
542 SUPPORTED_10000baseKR_Full,
543 ADVERTISED_10000baseKR_Full,
544 SPEED_10000
545 },
546
547 [MLX4_20GBASE_KR2] = {
548 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full,
549 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full,
550 SPEED_20000
551 },
552
553 [MLX4_40GBASE_CR4] = {
554 SUPPORTED_40000baseCR4_Full,
555 ADVERTISED_40000baseCR4_Full,
556 SPEED_40000
557 },
558 [MLX4_40GBASE_KR4] = {
559 SUPPORTED_40000baseKR4_Full,
560 ADVERTISED_40000baseKR4_Full,
561 SPEED_40000
562 },
563 [MLX4_40GBASE_SR4] = {
564 SUPPORTED_40000baseSR4_Full,
565 ADVERTISED_40000baseSR4_Full,
566 SPEED_40000
567 },
568
569 [MLX4_56GBASE_KR4] = {
570 SUPPORTED_56000baseKR4_Full,
571 ADVERTISED_56000baseKR4_Full,
572 SPEED_56000
573 },
574 [MLX4_56GBASE_CR4] = {
575 SUPPORTED_56000baseCR4_Full,
576 ADVERTISED_56000baseCR4_Full,
577 SPEED_56000
578 },
579 [MLX4_56GBASE_SR4] = {
580 SUPPORTED_56000baseSR4_Full,
581 ADVERTISED_56000baseSR4_Full,
582 SPEED_56000
583 },
584};
585
586static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report)
587{
588 int i;
589 u32 link_modes = 0;
590
591 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
592 if (eth_proto & MLX4_PROT_MASK(i))
593 link_modes |= ptys2ethtool_map[i][report];
594 }
595 return link_modes;
596}
597
d48b3ab4
SM		 598static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report)
599{
600 int i;
601 u32 ptys_modes = 0;
602
603 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
604 if (ptys2ethtool_map[i][report] & link_modes)
605 ptys_modes |= 1 << i;
606 }
607 return ptys_modes;
608}
609
610/* Convert actual speed (SPEED_XXX) to ptys link modes */
611static u32 speed2ptys_link_modes(u32 speed)
612{
613 int i;
614 u32 ptys_modes = 0;
615
616 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
617 if (ptys2ethtool_map[i][SPEED] == speed)
618 ptys_modes |= 1 << i;
619 }
620 return ptys_modes;
621}
622
2c762679
SM		 623static int ethtool_get_ptys_settings(struct net_device *dev,
624 struct ethtool_cmd *cmd)
625{
626 struct mlx4_en_priv *priv = netdev_priv(dev);
627 struct mlx4_ptys_reg ptys_reg;
628 u32 eth_proto;
629 int ret;
630
631 memset(&ptys_reg, 0, sizeof(ptys_reg));
632 ptys_reg.local_port = priv->port;
633 ptys_reg.proto_mask = MLX4_PTYS_EN;
634 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
635 MLX4_ACCESS_REG_QUERY, &ptys_reg);
636 if (ret) {
637 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
638 ret);
639 return ret;
640 }
641 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
642 ptys_reg.proto_mask);
643 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
644 be32_to_cpu(ptys_reg.eth_proto_cap));
645 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
646 be32_to_cpu(ptys_reg.eth_proto_admin));
647 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
648 be32_to_cpu(ptys_reg.eth_proto_oper));
649 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
650 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
651
652 cmd->supported = 0;
653 cmd->advertising = 0;
654
655 cmd->supported |= ptys_get_supported_port(&ptys_reg);
656
657 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
658 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED);
659
660 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
661 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED);
662
663 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
664 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0;
665
666 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ?
667 ADVERTISED_Asym_Pause : 0;
668
669 cmd->port = ptys_get_active_port(&ptys_reg);
670 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ?
671 XCVR_EXTERNAL : XCVR_INTERNAL;
672
673 if (mlx4_en_autoneg_get(dev)) {
674 cmd->supported |= SUPPORTED_Autoneg;
675 cmd->advertising |= ADVERTISED_Autoneg;
676 }
677
678 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
679 AUTONEG_ENABLE : AUTONEG_DISABLE;
680
681 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
682 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED);
683
684 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
685 ADVERTISED_Autoneg : 0;
686
687 cmd->phy_address = 0;
688 cmd->mdio_support = 0;
689 cmd->maxtxpkt = 0;
690 cmd->maxrxpkt = 0;
691 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
692 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
693
694 return ret;
695}
696
697static void ethtool_get_default_settings(struct net_device *dev,
698 struct ethtool_cmd *cmd)
c27a02cd 699{
7699517d
YP		 700 struct mlx4_en_priv *priv = netdev_priv(dev);
701 int trans_type;
702
c27a02cd
YP		 703 cmd->autoneg = AUTONEG_DISABLE;
704 cmd->supported = SUPPORTED_10000baseT_Full;
7699517d 705 cmd->advertising = ADVERTISED_10000baseT_Full;
2c762679 706 trans_type = priv->port_state.transceiver;
7699517d
YP		 707
708 if (trans_type > 0 && trans_type <= 0xC) {
709 cmd->port = PORT_FIBRE;
710 cmd->transceiver = XCVR_EXTERNAL;
711 cmd->supported |= SUPPORTED_FIBRE;
712 cmd->advertising |= ADVERTISED_FIBRE;
713 } else if (trans_type == 0x80 || trans_type == 0) {
714 cmd->port = PORT_TP;
715 cmd->transceiver = XCVR_INTERNAL;
716 cmd->supported |= SUPPORTED_TP;
717 cmd->advertising |= ADVERTISED_TP;
718 } else {
719 cmd->port = -1;
720 cmd->transceiver = -1;
721 }
2c762679
SM		 722}
723
724static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
725{
726 struct mlx4_en_priv *priv = netdev_priv(dev);
727 int ret = -EINVAL;
728
729 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
730 return -ENOMEM;
731
732 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
733 priv->port_state.flags & MLX4_EN_PORT_ANC,
734 priv->port_state.flags & MLX4_EN_PORT_ANE);
735
736 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
737 ret = ethtool_get_ptys_settings(dev, cmd);
738 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
739 ethtool_get_default_settings(dev, cmd);
740
741 if (netif_carrier_ok(dev)) {
742 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
743 cmd->duplex = DUPLEX_FULL;
744 } else {
745 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
746 cmd->duplex = DUPLEX_UNKNOWN;
747 }
c27a02cd
YP		 748 return 0;
749}
750
d48b3ab4
SM		 751/* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
752static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
753 __be32 proto_cap)
754{
755 __be32 proto_admin = 0;
756
757 if (!speed) { /* Speed = 0 ==> Reset Link modes */
758 proto_admin = proto_cap;
759 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
760 be32_to_cpu(proto_cap));
761 } else {
762 u32 ptys_link_modes = speed2ptys_link_modes(speed);
763
764 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
765 en_info(priv, "Setting Speed to %d\n", speed);
766 }
767 return proto_admin;
768}
769
c27a02cd
YP		 770static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
771{
d48b3ab4
SM		 772 struct mlx4_en_priv *priv = netdev_priv(dev);
773 struct mlx4_ptys_reg ptys_reg;
774 __be32 proto_admin;
775 int ret;
776
777 u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED);
778 int speed = ethtool_cmd_speed(cmd);
779
780 en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n",
781 speed, cmd->advertising, cmd->autoneg, cmd->duplex);
782
783 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
312df74c 784 (cmd->duplex == DUPLEX_HALF))
c27a02cd
YP		 785 return -EINVAL;
786
d48b3ab4
SM		 787 memset(&ptys_reg, 0, sizeof(ptys_reg));
788 ptys_reg.local_port = priv->port;
789 ptys_reg.proto_mask = MLX4_PTYS_EN;
790 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
791 MLX4_ACCESS_REG_QUERY, &ptys_reg);
792 if (ret) {
793 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
794 ret);
795 return 0;
796 }
797
5a228c03
SM		 798 proto_admin = cmd->autoneg == AUTONEG_ENABLE ?
799 cpu_to_be32(ptys_adv) :
800 speed_set_ptys_admin(priv, speed,
801 ptys_reg.eth_proto_cap);
d48b3ab4
SM		 802
803 proto_admin &= ptys_reg.eth_proto_cap;
d48b3ab4
SM		 804 if (!proto_admin) {
805 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
806 return -EINVAL; /* nothing to change due to bad input */
807 }
808
5a228c03
SM		 809 if (proto_admin == ptys_reg.eth_proto_admin)
810 return 0; /* Nothing to change */
811
d48b3ab4
SM		 812 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
813 be32_to_cpu(proto_admin));
814
815 ptys_reg.eth_proto_admin = proto_admin;
816 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
817 &ptys_reg);
818 if (ret) {
819 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
820 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
821 return ret;
822 }
823
d48b3ab4
SM		 824 mutex_lock(&priv->mdev->state_lock);
825 if (priv->port_up) {
5a228c03 826 en_warn(priv, "Port link mode changed, restarting port...\n");
d48b3ab4
SM		 827 mlx4_en_stop_port(dev, 1);
828 if (mlx4_en_start_port(dev))
829 en_err(priv, "Failed restarting port %d\n", priv->port);
830 }
831 mutex_unlock(&priv->mdev->state_lock);
c27a02cd
YP		 832 return 0;
833}
834
835static int mlx4_en_get_coalesce(struct net_device *dev,
836 struct ethtool_coalesce *coal)
837{
838 struct mlx4_en_priv *priv = netdev_priv(dev);
839
a19a848a
YP		 840 coal->tx_coalesce_usecs = priv->tx_usecs;
841 coal->tx_max_coalesced_frames = priv->tx_frames;
fbc6daf1
AV		 842 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
843
c27a02cd
YP		 844 coal->rx_coalesce_usecs = priv->rx_usecs;
845 coal->rx_max_coalesced_frames = priv->rx_frames;
846
847 coal->pkt_rate_low = priv->pkt_rate_low;
848 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
849 coal->pkt_rate_high = priv->pkt_rate_high;
850 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
851 coal->rate_sample_interval = priv->sample_interval;
852 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
fbc6daf1 853
c27a02cd
YP		 854 return 0;
855}
856
857static int mlx4_en_set_coalesce(struct net_device *dev,
858 struct ethtool_coalesce *coal)
859{
860 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd 861
fbc6daf1
AV		 862 if (!coal->tx_max_coalesced_frames_irq)
863 return -EINVAL;
864
c27a02cd
YP		 865 priv->rx_frames = (coal->rx_max_coalesced_frames ==
866 MLX4_EN_AUTO_CONF) ?
3db36fb2 867 MLX4_EN_RX_COAL_TARGET :
c27a02cd
YP		 868 coal->rx_max_coalesced_frames;
869 priv->rx_usecs = (coal->rx_coalesce_usecs ==
870 MLX4_EN_AUTO_CONF) ?
871 MLX4_EN_RX_COAL_TIME :
872 coal->rx_coalesce_usecs;
873
a19a848a
YP		 874 /* Setting TX coalescing parameters */
875 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
876 coal->tx_max_coalesced_frames != priv->tx_frames) {
877 priv->tx_usecs = coal->tx_coalesce_usecs;
878 priv->tx_frames = coal->tx_max_coalesced_frames;
a19a848a
YP		 879 }
880
c27a02cd
YP		 881 /* Set adaptive coalescing params */
882 priv->pkt_rate_low = coal->pkt_rate_low;
883 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
884 priv->pkt_rate_high = coal->pkt_rate_high;
885 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
886 priv->sample_interval = coal->rate_sample_interval;
887 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
fbc6daf1 888 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
c27a02cd 889
79c54b6b 890 return mlx4_en_moderation_update(priv);
c27a02cd
YP		 891}
892
893static int mlx4_en_set_pauseparam(struct net_device *dev,
894 struct ethtool_pauseparam *pause)
895{
896 struct mlx4_en_priv *priv = netdev_priv(dev);
897 struct mlx4_en_dev *mdev = priv->mdev;
898 int err;
899
278d436a
IV		 900 if (pause->autoneg)
901 return -EINVAL;
902
d53b93f2
YP		 903 priv->prof->tx_pause = pause->tx_pause != 0;
904 priv->prof->rx_pause = pause->rx_pause != 0;
c27a02cd
YP		 905 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
906 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 907 priv->prof->tx_pause,
908 priv->prof->tx_ppp,
909 priv->prof->rx_pause,
910 priv->prof->rx_ppp);
c27a02cd 911 if (err)
453a6082 912 en_err(priv, "Failed setting pause params\n");
c27a02cd
YP		 913
914 return err;
915}
916
917static void mlx4_en_get_pauseparam(struct net_device *dev,
918 struct ethtool_pauseparam *pause)
919{
920 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd 921
d53b93f2
YP		 922 pause->tx_pause = priv->prof->tx_pause;
923 pause->rx_pause = priv->prof->rx_pause;
c27a02cd
YP		 924}
925
18cc42a3
YP		 926static int mlx4_en_set_ringparam(struct net_device *dev,
927 struct ethtool_ringparam *param)
928{
929 struct mlx4_en_priv *priv = netdev_priv(dev);
930 struct mlx4_en_dev *mdev = priv->mdev;
931 u32 rx_size, tx_size;
932 int port_up = 0;
933 int err = 0;
934
935 if (param->rx_jumbo_pending || param->rx_mini_pending)
936 return -EINVAL;
937
938 rx_size = roundup_pow_of_two(param->rx_pending);
939 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
bd531e36 940 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
18cc42a3
YP		 941 tx_size = roundup_pow_of_two(param->tx_pending);
942 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
bd531e36 943 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
18cc42a3 944
41d942d5
EE		 945 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
946 priv->rx_ring[0]->size) &&
947 tx_size == priv->tx_ring[0]->size)
18cc42a3
YP		 948 return 0;
949
950 mutex_lock(&mdev->state_lock);
951 if (priv->port_up) {
952 port_up = 1;
3484aac1 953 mlx4_en_stop_port(dev, 1);
18cc42a3
YP		 954 }
955
fe0af03c 956 mlx4_en_free_resources(priv);
18cc42a3
YP		 957
958 priv->prof->tx_ring_size = tx_size;
959 priv->prof->rx_ring_size = rx_size;
960
961 err = mlx4_en_alloc_resources(priv);
962 if (err) {
453a6082 963 en_err(priv, "Failed reallocating port resources\n");
18cc42a3
YP		 964 goto out;
965 }
966 if (port_up) {
967 err = mlx4_en_start_port(dev);
968 if (err)
453a6082 969 en_err(priv, "Failed starting port\n");
18cc42a3
YP		 970 }
971
79c54b6b 972 err = mlx4_en_moderation_update(priv);
6b4d8d9f 973
18cc42a3
YP		 974out:
975 mutex_unlock(&mdev->state_lock);
976 return err;
977}
978
c27a02cd
YP		 979static void mlx4_en_get_ringparam(struct net_device *dev,
980 struct ethtool_ringparam *param)
981{
982 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP		 983
984 memset(param, 0, sizeof(*param));
bd531e36
YP		 985 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
986 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
bc081cec 987 param->rx_pending = priv->port_up ?
41d942d5
EE		 988 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
989 param->tx_pending = priv->tx_ring[0]->size;
c27a02cd
YP		 990}
991
93d3e367
YP		 992static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
993{
994 struct mlx4_en_priv *priv = netdev_priv(dev);
995
996 return priv->rx_ring_num;
997}
998
b9d1ab7e
ED		 999static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1000{
1001 return MLX4_EN_RSS_KEY_SIZE;
1002}
1003
947cbb0a
EP		 1004static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1005{
1006 struct mlx4_en_priv *priv = netdev_priv(dev);
1007
1008 /* check if requested function is supported by the device */
1009 if ((hfunc == ETH_RSS_HASH_TOP &&
1010 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) ||
1011 (hfunc == ETH_RSS_HASH_XOR &&
1012 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)))
1013 return -EINVAL;
1014
1015 priv->rss_hash_fn = hfunc;
1016 if (hfunc == ETH_RSS_HASH_TOP && !(dev->features & NETIF_F_RXHASH))
1017 en_warn(priv,
1018 "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1019 if (hfunc == ETH_RSS_HASH_XOR && (dev->features & NETIF_F_RXHASH))
1020 en_warn(priv,
1021 "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1022 return 0;
1023}
1024
892311f6
EP		 1025static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1026 u8 *hfunc)
93d3e367
YP		 1027{
1028 struct mlx4_en_priv *priv = netdev_priv(dev);
1029 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1030 int rss_rings;
1031 size_t n = priv->rx_ring_num;
1032 int err = 0;
1033
1034 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num;
d5ec899a 1035 rss_rings = 1 << ilog2(rss_rings);
93d3e367
YP		 1036
1037 while (n--) {
892311f6
EP		 1038 if (!ring_index)
1039 break;
93d3e367
YP		 1040 ring_index[n] = rss_map->qps[n % rss_rings].qpn -
1041 rss_map->base_qpn;
1042 }
b9d1ab7e 1043 if (key)
bd635c35 1044 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
892311f6 1045 if (hfunc)
947cbb0a 1046 *hfunc = priv->rss_hash_fn;
93d3e367
YP		 1047 return err;
1048}
1049
fe62d001 1050static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
892311f6 1051 const u8 *key, const u8 hfunc)
93d3e367
YP		 1052{
1053 struct mlx4_en_priv *priv = netdev_priv(dev);
1054 struct mlx4_en_dev *mdev = priv->mdev;
1055 int port_up = 0;
1056 int err = 0;
1057 int i;
1058 int rss_rings = 0;
1059
1060 /* Calculate RSS table size and make sure flows are spread evenly
1061 * between rings
1062 */
1063 for (i = 0; i < priv->rx_ring_num; i++) {
bd635c35
ED		 1064 if (!ring_index)
1065 continue;
93d3e367
YP		 1066 if (i > 0 && !ring_index[i] && !rss_rings)
1067 rss_rings = i;
1068
1069 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num)))
1070 return -EINVAL;
1071 }
1072
1073 if (!rss_rings)
1074 rss_rings = priv->rx_ring_num;
1075
1076 /* RSS table size must be an order of 2 */
1077 if (!is_power_of_2(rss_rings))
1078 return -EINVAL;
1079
947cbb0a
EP		 1080 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1081 err = mlx4_en_check_rxfh_func(dev, hfunc);
1082 if (err)
1083 return err;
1084 }
1085
93d3e367
YP		 1086 mutex_lock(&mdev->state_lock);
1087 if (priv->port_up) {
1088 port_up = 1;
3484aac1 1089 mlx4_en_stop_port(dev, 1);
93d3e367
YP		 1090 }
1091
bd635c35
ED		 1092 if (ring_index)
1093 priv->prof->rss_rings = rss_rings;
1094 if (key)
1095 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
947cbb0a 1096
93d3e367
YP		 1097 if (port_up) {
1098 err = mlx4_en_start_port(dev);
1099 if (err)
1100 en_err(priv, "Failed starting port\n");
1101 }
1102
1103 mutex_unlock(&mdev->state_lock);
1104 return err;
1105}
1106
82067281
HHZ		 1107#define all_zeros_or_all_ones(field) \
1108 ((field) == 0 || (field) == (__force typeof(field))-1)
1109
1110static int mlx4_en_validate_flow(struct net_device *dev,
1111 struct ethtool_rxnfc *cmd)
1112{
1113 struct ethtool_usrip4_spec *l3_mask;
1114 struct ethtool_tcpip4_spec *l4_mask;
1115 struct ethhdr *eth_mask;
82067281
HHZ		 1116
1117 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1118 return -EINVAL;
1119
520dfe3a
YB		 1120 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1121 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1122 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1123 return -EINVAL;
1124 }
1125
1126 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
82067281
HHZ		 1127 case TCP_V4_FLOW:
1128 case UDP_V4_FLOW:
1129 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1130 return -EINVAL;
1131 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1132 /* don't allow mask which isn't all 0 or 1 */
1133 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1134 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1135 !all_zeros_or_all_ones(l4_mask->psrc) ||
1136 !all_zeros_or_all_ones(l4_mask->pdst))
1137 return -EINVAL;
1138 break;
1139 case IP_USER_FLOW:
1140 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1141 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1142 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1143 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1144 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1145 !all_zeros_or_all_ones(l3_mask->ip4dst))
1146 return -EINVAL;
1147 break;
1148 case ETHER_FLOW:
1149 eth_mask = &cmd->fs.m_u.ether_spec;
1150 /* source mac mask must not be set */
c402b947 1151 if (!is_zero_ether_addr(eth_mask->h_source))
82067281
HHZ		 1152 return -EINVAL;
1153
1154 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
c402b947 1155 if (!is_broadcast_ether_addr(eth_mask->h_dest))
82067281
HHZ		 1156 return -EINVAL;
1157
1158 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1159 return -EINVAL;
1160 break;
1161 default:
1162 return -EINVAL;
1163 }
1164
1165 if ((cmd->fs.flow_type & FLOW_EXT)) {
1166 if (cmd->fs.m_ext.vlan_etype ||
8258bd27
HHZ		 1167 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1168 0 ||
1169 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1170 cpu_to_be16(VLAN_VID_MASK)))
82067281 1171 return -EINVAL;
8258bd27 1172
69d7126b
HHZ		 1173 if (cmd->fs.m_ext.vlan_tci) {
1174 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1175 return -EINVAL;
8258bd27 1176
69d7126b 1177 }
82067281
HHZ		 1178 }
1179
1180 return 0;
1181}
1182
f90a3673
HHZ		 1183static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1184 struct list_head *rule_list_h,
1185 struct mlx4_spec_list *spec_l2,
1186 unsigned char *mac)
1187{
1188 int err = 0;
1189 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1190
1191 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1192 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1193 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1194
8258bd27
HHZ		 1195 if ((cmd->fs.flow_type & FLOW_EXT) &&
1196 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
f90a3673 1197 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
8258bd27 1198 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
f90a3673
HHZ		 1199 }
1200
1201 list_add_tail(&spec_l2->list, rule_list_h);
1202
1203 return err;
1204}
1205
1206static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1207 struct ethtool_rxnfc *cmd,
1208 struct list_head *rule_list_h,
1209 struct mlx4_spec_list *spec_l2,
1210 __be32 ipv4_dst)
1211{
f9d96862 1212#ifdef CONFIG_INET
f90a3673
HHZ		 1213 unsigned char mac[ETH_ALEN];
1214
1215 if (!ipv4_is_multicast(ipv4_dst)) {
6bbb6d99 1216 if (cmd->fs.flow_type & FLOW_MAC_EXT)
f90a3673 1217 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
6bbb6d99
YB		 1218 else
1219 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
f90a3673
HHZ		 1220 } else {
1221 ip_eth_mc_map(ipv4_dst, mac);
1222 }
1223
1224 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
f9d96862
HHZ		 1225#else
1226 return -EINVAL;
1227#endif
f90a3673
HHZ		 1228}
1229
82067281 1230static int add_ip_rule(struct mlx4_en_priv *priv,
f90a3673
HHZ		 1231 struct ethtool_rxnfc *cmd,
1232 struct list_head *list_h)
82067281 1233{
377d9739 1234 int err;
f90a3673
HHZ		 1235 struct mlx4_spec_list *spec_l2 = NULL;
1236 struct mlx4_spec_list *spec_l3 = NULL;
82067281
HHZ		 1237 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1238
f90a3673
HHZ		 1239 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1240 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1241 if (!spec_l2 || !spec_l3) {
377d9739
HHZ		 1242 err = -ENOMEM;
1243 goto free_spec;
82067281
HHZ		 1244 }
1245
377d9739
HHZ		 1246 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1247 cmd->fs.h_u.
1248 usr_ip4_spec.ip4dst);
1249 if (err)
1250 goto free_spec;
82067281
HHZ		 1251 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1252 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1253 if (l3_mask->ip4src)
1254 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1255 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1256 if (l3_mask->ip4dst)
1257 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1258 list_add_tail(&spec_l3->list, list_h);
1259
1260 return 0;
377d9739
HHZ		 1261
1262free_spec:
1263 kfree(spec_l2);
1264 kfree(spec_l3);
1265 return err;
82067281
HHZ		 1266}
1267
1268static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1269 struct ethtool_rxnfc *cmd,
1270 struct list_head *list_h, int proto)
1271{
377d9739 1272 int err;
f90a3673
HHZ		 1273 struct mlx4_spec_list *spec_l2 = NULL;
1274 struct mlx4_spec_list *spec_l3 = NULL;
1275 struct mlx4_spec_list *spec_l4 = NULL;
82067281
HHZ		 1276 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1277
f90a3673
HHZ		 1278 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1279 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1280 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1281 if (!spec_l2 || !spec_l3 || !spec_l4) {
377d9739
HHZ		 1282 err = -ENOMEM;
1283 goto free_spec;
82067281
HHZ		 1284 }
1285
1286 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1287
1288 if (proto == TCP_V4_FLOW) {
377d9739
HHZ		 1289 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1290 spec_l2,
1291 cmd->fs.h_u.
1292 tcp_ip4_spec.ip4dst);
1293 if (err)
1294 goto free_spec;
82067281
HHZ		 1295 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1296 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1297 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1298 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1299 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1300 } else {
377d9739
HHZ		 1301 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1302 spec_l2,
1303 cmd->fs.h_u.
1304 udp_ip4_spec.ip4dst);
1305 if (err)
1306 goto free_spec;
82067281
HHZ		 1307 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1308 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1309 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1310 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1311 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1312 }
1313
1314 if (l4_mask->ip4src)
1315 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1316 if (l4_mask->ip4dst)
1317 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1318
1319 if (l4_mask->psrc)
1320 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1321 if (l4_mask->pdst)
1322 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1323
1324 list_add_tail(&spec_l3->list, list_h);
1325 list_add_tail(&spec_l4->list, list_h);
1326
1327 return 0;
377d9739
HHZ		 1328
1329free_spec:
1330 kfree(spec_l2);
1331 kfree(spec_l3);
1332 kfree(spec_l4);
1333 return err;
82067281
HHZ		 1334}
1335
1336static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1337 struct ethtool_rxnfc *cmd,
1338 struct list_head *rule_list_h)
1339{
1340 int err;
82067281 1341 struct ethhdr *eth_spec;
82067281 1342 struct mlx4_spec_list *spec_l2;
f90a3673 1343 struct mlx4_en_priv *priv = netdev_priv(dev);
82067281
HHZ		 1344
1345 err = mlx4_en_validate_flow(dev, cmd);
1346 if (err)
1347 return err;
1348
520dfe3a 1349 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
82067281 1350 case ETHER_FLOW:
f90a3673
HHZ		 1351 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1352 if (!spec_l2)
1353 return -ENOMEM;
1354
82067281 1355 eth_spec = &cmd->fs.h_u.ether_spec;
f90a3673
HHZ		 1356 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1357 &eth_spec->h_dest[0]);
82067281
HHZ		 1358 spec_l2->eth.ether_type = eth_spec->h_proto;
1359 if (eth_spec->h_proto)
1360 spec_l2->eth.ether_type_enable = 1;
1361 break;
1362 case IP_USER_FLOW:
1363 err = add_ip_rule(priv, cmd, rule_list_h);
1364 break;
1365 case TCP_V4_FLOW:
1366 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1367 break;
1368 case UDP_V4_FLOW:
1369 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1370 break;
1371 }
1372
1373 return err;
1374}
1375
1376static int mlx4_en_flow_replace(struct net_device *dev,
1377 struct ethtool_rxnfc *cmd)
1378{
1379 int err;
1380 struct mlx4_en_priv *priv = netdev_priv(dev);
1381 struct ethtool_flow_id *loc_rule;
1382 struct mlx4_spec_list *spec, *tmp_spec;
1383 u32 qpn;
1384 u64 reg_id;
1385
1386 struct mlx4_net_trans_rule rule = {
1387 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1388 .exclusive = 0,
1389 .allow_loopback = 1,
f9162539 1390 .promisc_mode = MLX4_FS_REGULAR,
82067281
HHZ		 1391 };
1392
1393 rule.port = priv->port;
1394 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1395 INIT_LIST_HEAD(&rule.list);
1396
1397 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1398 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
cabdc8ee 1399 qpn = priv->drop_qp.qpn;
82067281
HHZ		 1400 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1401 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1402 } else {
1403 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1a91de28 1404 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
82067281
HHZ		 1405 cmd->fs.ring_cookie);
1406 return -EINVAL;
1407 }
1408 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1409 if (!qpn) {
1a91de28 1410 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
82067281
HHZ		 1411 cmd->fs.ring_cookie);
1412 return -EINVAL;
1413 }
1414 }
1415 rule.qpn = qpn;
1416 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1417 if (err)
1418 goto out_free_list;
1419
1420 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1421 if (loc_rule->id) {
1422 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1423 if (err) {
1424 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1425 cmd->fs.location, loc_rule->id);
1426 goto out_free_list;
1427 }
1428 loc_rule->id = 0;
1429 memset(&loc_rule->flow_spec, 0,
1430 sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1431 list_del(&loc_rule->list);
82067281
HHZ		 1432 }
1433 err = mlx4_flow_attach(priv->mdev->dev, &rule, &reg_id);
1434 if (err) {
1a91de28 1435 en_err(priv, "Fail to attach network rule at location %d\n",
82067281
HHZ		 1436 cmd->fs.location);
1437 goto out_free_list;
1438 }
1439 loc_rule->id = reg_id;
1440 memcpy(&loc_rule->flow_spec, &cmd->fs,
1441 sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1442 list_add_tail(&loc_rule->list, &priv->ethtool_list);
82067281
HHZ		 1443
1444out_free_list:
1445 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1446 list_del(&spec->list);
1447 kfree(spec);
1448 }
1449 return err;
1450}
1451
1452static int mlx4_en_flow_detach(struct net_device *dev,
1453 struct ethtool_rxnfc *cmd)
1454{
1455 int err = 0;
1456 struct ethtool_flow_id *rule;
1457 struct mlx4_en_priv *priv = netdev_priv(dev);
1458
1459 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1460 return -EINVAL;
1461
1462 rule = &priv->ethtool_rules[cmd->fs.location];
1463 if (!rule->id) {
1464 err = -ENOENT;
1465 goto out;
1466 }
1467
1468 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1469 if (err) {
1470 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1471 cmd->fs.location, rule->id);
1472 goto out;
1473 }
1474 rule->id = 0;
1475 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1476 list_del(&rule->list);
82067281
HHZ		 1477out:
1478 return err;
1479
1480}
1481
1482static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1483 int loc)
1484{
1485 int err = 0;
1486 struct ethtool_flow_id *rule;
1487 struct mlx4_en_priv *priv = netdev_priv(dev);
1488
1489 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1490 return -EINVAL;
1491
1492 rule = &priv->ethtool_rules[loc];
1493 if (rule->id)
1494 memcpy(&cmd->fs, &rule->flow_spec,
1495 sizeof(struct ethtool_rx_flow_spec));
1496 else
1497 err = -ENOENT;
1498
1499 return err;
1500}
1501
1502static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1503{
1504
1505 int i, res = 0;
1506 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1507 if (priv->ethtool_rules[i].id)
1508 res++;
1509 }
1510 return res;
1511
1512}
1513
93d3e367
YP		 1514static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1515 u32 *rule_locs)
1516{
1517 struct mlx4_en_priv *priv = netdev_priv(dev);
82067281 1518 struct mlx4_en_dev *mdev = priv->mdev;
93d3e367 1519 int err = 0;
82067281
HHZ		 1520 int i = 0, priority = 0;
1521
1522 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1523 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1524 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
280fce1e
HHZ		 1525 (mdev->dev->caps.steering_mode !=
1526 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
82067281 1527 return -EINVAL;
93d3e367
YP		 1528
1529 switch (cmd->cmd) {
1530 case ETHTOOL_GRXRINGS:
1531 cmd->data = priv->rx_ring_num;
1532 break;
82067281
HHZ		 1533 case ETHTOOL_GRXCLSRLCNT:
1534 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1535 break;
1536 case ETHTOOL_GRXCLSRULE:
1537 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1538 break;
1539 case ETHTOOL_GRXCLSRLALL:
1540 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1541 err = mlx4_en_get_flow(dev, cmd, i);
1542 if (!err)
1543 rule_locs[priority++] = i;
1544 i++;
1545 }
1546 err = 0;
1547 break;
93d3e367
YP		 1548 default:
1549 err = -EOPNOTSUPP;
1550 break;
1551 }
1552
1553 return err;
1554}
1555
82067281
HHZ		 1556static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1557{
1558 int err = 0;
1559 struct mlx4_en_priv *priv = netdev_priv(dev);
1560 struct mlx4_en_dev *mdev = priv->mdev;
1561
280fce1e
HHZ		 1562 if (mdev->dev->caps.steering_mode !=
1563 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
82067281
HHZ		 1564 return -EINVAL;
1565
1566 switch (cmd->cmd) {
1567 case ETHTOOL_SRXCLSRLINS:
1568 err = mlx4_en_flow_replace(dev, cmd);
1569 break;
1570 case ETHTOOL_SRXCLSRLDEL:
1571 err = mlx4_en_flow_detach(dev, cmd);
1572 break;
1573 default:
1574 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1575 return -EINVAL;
1576 }
1577
1578 return err;
1579}
1580
d317966b
AV		 1581static void mlx4_en_get_channels(struct net_device *dev,
1582 struct ethtool_channels *channel)
1583{
1584 struct mlx4_en_priv *priv = netdev_priv(dev);
1585
1586 memset(channel, 0, sizeof(*channel));
1587
1588 channel->max_rx = MAX_RX_RINGS;
1589 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1590
1591 channel->rx_count = priv->rx_ring_num;
1592 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
1593}
1594
1595static int mlx4_en_set_channels(struct net_device *dev,
1596 struct ethtool_channels *channel)
1597{
1598 struct mlx4_en_priv *priv = netdev_priv(dev);
1599 struct mlx4_en_dev *mdev = priv->mdev;
da26a625 1600 int port_up = 0;
d317966b
AV		 1601 int err = 0;
1602
1603 if (channel->other_count || channel->combined_count ||
1604 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
1605 channel->rx_count > MAX_RX_RINGS ||
1606 !channel->tx_count || !channel->rx_count)
1607 return -EINVAL;
1608
1609 mutex_lock(&mdev->state_lock);
1610 if (priv->port_up) {
1611 port_up = 1;
3484aac1 1612 mlx4_en_stop_port(dev, 1);
d317966b
AV		 1613 }
1614
1615 mlx4_en_free_resources(priv);
1616
1617 priv->num_tx_rings_p_up = channel->tx_count;
1618 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
1619 priv->rx_ring_num = channel->rx_count;
1620
1621 err = mlx4_en_alloc_resources(priv);
1622 if (err) {
1623 en_err(priv, "Failed reallocating port resources\n");
1624 goto out;
1625 }
1626
1627 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
1628 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1629
f5b6345b
IS		 1630 if (dev->num_tc)
1631 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
d317966b
AV		 1632
1633 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
1634 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1635
1636 if (port_up) {
1637 err = mlx4_en_start_port(dev);
1638 if (err)
1639 en_err(priv, "Failed starting port\n");
1640 }
1641
1642 err = mlx4_en_moderation_update(priv);
1643
1644out:
1645 mutex_unlock(&mdev->state_lock);
1646 return err;
1647}
1648
ec693d47
AV		 1649static int mlx4_en_get_ts_info(struct net_device *dev,
1650 struct ethtool_ts_info *info)
1651{
1652 struct mlx4_en_priv *priv = netdev_priv(dev);
1653 struct mlx4_en_dev *mdev = priv->mdev;
1654 int ret;
1655
1656 ret = ethtool_op_get_ts_info(dev, info);
1657 if (ret)
1658 return ret;
1659
1660 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1661 info->so_timestamping |=
1662 SOF_TIMESTAMPING_TX_HARDWARE |
1663 SOF_TIMESTAMPING_RX_HARDWARE |
1664 SOF_TIMESTAMPING_RAW_HARDWARE;
1665
1666 info->tx_types =
1667 (1 << HWTSTAMP_TX_OFF) |
1668 (1 << HWTSTAMP_TX_ON);
1669
1670 info->rx_filters =
1671 (1 << HWTSTAMP_FILTER_NONE) |
1672 (1 << HWTSTAMP_FILTER_ALL);
ad7d4eae
SB		 1673
1674 if (mdev->ptp_clock)
1675 info->phc_index = ptp_clock_index(mdev->ptp_clock);
ec693d47
AV		 1676 }
1677
1678 return ret;
1679}
1680
3f6148e7 1681static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
0fef9d03
AV		 1682{
1683 struct mlx4_en_priv *priv = netdev_priv(dev);
1684 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1685 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1686 int i;
1687
1688 if (bf_enabled_new == bf_enabled_old)
1689 return 0; /* Nothing to do */
1690
1691 if (bf_enabled_new) {
1692 bool bf_supported = true;
1693
1694 for (i = 0; i < priv->tx_ring_num; i++)
1695 bf_supported &= priv->tx_ring[i]->bf_alloced;
1696
1697 if (!bf_supported) {
1698 en_err(priv, "BlueFlame is not supported\n");
1699 return -EINVAL;
1700 }
1701
1702 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1703 } else {
1704 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1705 }
1706
1707 for (i = 0; i < priv->tx_ring_num; i++)
1708 priv->tx_ring[i]->bf_enabled = bf_enabled_new;
1709
1710 en_info(priv, "BlueFlame %s\n",
1711 bf_enabled_new ? "Enabled" : "Disabled");
1712
1713 return 0;
1714}
1715
3f6148e7 1716static u32 mlx4_en_get_priv_flags(struct net_device *dev)
0fef9d03
AV		 1717{
1718 struct mlx4_en_priv *priv = netdev_priv(dev);
1719
1720 return priv->pflags;
1721}
1722
1556b874
ED		 1723static int mlx4_en_get_tunable(struct net_device *dev,
1724 const struct ethtool_tunable *tuna,
1725 void *data)
1726{
1727 const struct mlx4_en_priv *priv = netdev_priv(dev);
1728 int ret = 0;
1729
1730 switch (tuna->id) {
1731 case ETHTOOL_TX_COPYBREAK:
1732 *(u32 *)data = priv->prof->inline_thold;
1733 break;
1734 default:
1735 ret = -EINVAL;
1736 break;
1737 }
1738
1739 return ret;
1740}
1741
1742static int mlx4_en_set_tunable(struct net_device *dev,
1743 const struct ethtool_tunable *tuna,
1744 const void *data)
1745{
1746 struct mlx4_en_priv *priv = netdev_priv(dev);
1747 int val, ret = 0;
1748
1749 switch (tuna->id) {
1750 case ETHTOOL_TX_COPYBREAK:
1751 val = *(u32 *)data;
1752 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1753 ret = -EINVAL;
1754 else
1755 priv->prof->inline_thold = val;
1756 break;
1757 default:
1758 ret = -EINVAL;
1759 break;
1760 }
1761
1762 return ret;
1763}
1764
7202da8b
SM		 1765static int mlx4_en_get_module_info(struct net_device *dev,
1766 struct ethtool_modinfo *modinfo)
1767{
1768 struct mlx4_en_priv *priv = netdev_priv(dev);
1769 struct mlx4_en_dev *mdev = priv->mdev;
1770 int ret;
1771 u8 data[4];
1772
1773 /* Read first 2 bytes to get Module & REV ID */
1774 ret = mlx4_get_module_info(mdev->dev, priv->port,
1775 0/*offset*/, 2/*size*/, data);
1776 if (ret < 2)
1777 return -EIO;
1778
1779 switch (data[0] /* identifier */) {
1780 case MLX4_MODULE_ID_QSFP:
1781 modinfo->type = ETH_MODULE_SFF_8436;
1782 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1783 break;
1784 case MLX4_MODULE_ID_QSFP_PLUS:
1785 if (data[1] >= 0x3) { /* revision id */
1786 modinfo->type = ETH_MODULE_SFF_8636;
1787 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1788 } else {
1789 modinfo->type = ETH_MODULE_SFF_8436;
1790 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1791 }
1792 break;
1793 case MLX4_MODULE_ID_QSFP28:
1794 modinfo->type = ETH_MODULE_SFF_8636;
1795 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1796 break;
1797 case MLX4_MODULE_ID_SFP:
1798 modinfo->type = ETH_MODULE_SFF_8472;
1799 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1800 break;
1801 default:
1802 return -ENOSYS;
1803 }
1804
1805 return 0;
1806}
1807
1808static int mlx4_en_get_module_eeprom(struct net_device *dev,
1809 struct ethtool_eeprom *ee,
1810 u8 *data)
1811{
1812 struct mlx4_en_priv *priv = netdev_priv(dev);
1813 struct mlx4_en_dev *mdev = priv->mdev;
1814 int offset = ee->offset;
1815 int i = 0, ret;
1816
1817 if (ee->len == 0)
1818 return -EINVAL;
1819
1820 memset(data, 0, ee->len);
1821
1822 while (i < ee->len) {
1823 en_dbg(DRV, priv,
1824 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
1825 i, offset, ee->len - i);
1826
1827 ret = mlx4_get_module_info(mdev->dev, priv->port,
1828 offset, ee->len - i, data + i);
1829
1830 if (!ret) /* Done reading */
1831 return 0;
1832
1833 if (ret < 0) {
1834 en_err(priv,
1835 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
1836 i, offset, ee->len - i, ret);
1837 return 0;
1838 }
1839
1840 i += ret;
1841 offset += ret;
1842 }
1843 return 0;
1844}
0fef9d03 1845
c27a02cd
YP		 1846const struct ethtool_ops mlx4_en_ethtool_ops = {
1847 .get_drvinfo = mlx4_en_get_drvinfo,
1848 .get_settings = mlx4_en_get_settings,
1849 .set_settings = mlx4_en_set_settings,
c27a02cd 1850 .get_link = ethtool_op_get_link,
c27a02cd
YP		 1851 .get_strings = mlx4_en_get_strings,
1852 .get_sset_count = mlx4_en_get_sset_count,
1853 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
e7c1c2c4 1854 .self_test = mlx4_en_self_test,
c27a02cd 1855 .get_wol = mlx4_en_get_wol,
14c07b13 1856 .set_wol = mlx4_en_set_wol,
c27a02cd
YP		 1857 .get_msglevel = mlx4_en_get_msglevel,
1858 .set_msglevel = mlx4_en_set_msglevel,
1859 .get_coalesce = mlx4_en_get_coalesce,
1860 .set_coalesce = mlx4_en_set_coalesce,
1861 .get_pauseparam = mlx4_en_get_pauseparam,
1862 .set_pauseparam = mlx4_en_set_pauseparam,
1863 .get_ringparam = mlx4_en_get_ringparam,
18cc42a3 1864 .set_ringparam = mlx4_en_set_ringparam,
93d3e367 1865 .get_rxnfc = mlx4_en_get_rxnfc,
82067281 1866 .set_rxnfc = mlx4_en_set_rxnfc,
93d3e367 1867 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
b9d1ab7e 1868 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
fe62d001
BH		 1869 .get_rxfh = mlx4_en_get_rxfh,
1870 .set_rxfh = mlx4_en_set_rxfh,
d317966b
AV		 1871 .get_channels = mlx4_en_get_channels,
1872 .set_channels = mlx4_en_set_channels,
ec693d47 1873 .get_ts_info = mlx4_en_get_ts_info,
0fef9d03
AV		 1874 .set_priv_flags = mlx4_en_set_priv_flags,
1875 .get_priv_flags = mlx4_en_get_priv_flags,
1556b874
ED		 1876 .get_tunable = mlx4_en_get_tunable,
1877 .set_tunable = mlx4_en_set_tunable,
7202da8b
SM		 1878 .get_module_info = mlx4_en_get_module_info,
1879 .get_module_eeprom = mlx4_en_get_module_eeprom
c27a02cd
YP		 1880};
1881
1882
1883
1884
1885
Linux 6.x block layer and io_uring tree(s)