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net/mlx4_en: Fix errors in MAC address changing when port is down
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/sched.h>
5a0e3ad6 36#include <linux/slab.h>
ee40fa06 37#include <linux/export.h>
225c7b1f
RD		 38#include <linux/pci.h>
39#include <linux/errno.h>
40
41#include <linux/mlx4/cmd.h>
948e306d 42#include <linux/mlx4/device.h>
e8f081aa 43#include <linux/semaphore.h>
0a9a0188 44#include <rdma/ib_smi.h>
225c7b1f
RD		 45
46#include <asm/io.h>
47
48#include "mlx4.h"
e8f081aa 49#include "fw.h"
225c7b1f
RD		 50
51#define CMD_POLL_TOKEN 0xffff
e8f081aa
YP		 52#define INBOX_MASK 0xffffffffffffff00ULL
53
54#define CMD_CHAN_VER 1
55#define CMD_CHAN_IF_REV 1
225c7b1f
RD		 56
57enum {
58 /* command completed successfully: */
59 CMD_STAT_OK = 0x00,
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
899698da
JM		 80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
225c7b1f
RD		 82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
cc4ac2e7
YP		 93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
225c7b1f
RD		 96};
97
98enum {
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
104
105 HCR_OPMOD_SHIFT = 12,
106 HCR_T_BIT = 21,
107 HCR_E_BIT = 22,
108 HCR_GO_BIT = 23
109};
110
111enum {
36ce10d3 112 GO_BIT_TIMEOUT_MSECS = 10000
225c7b1f
RD		 113};
114
b01978ca
JM		 115enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
120};
121
122
225c7b1f
RD		 123struct mlx4_cmd_context {
124 struct completion done;
125 int result;
126 int next;
127 u64 out_param;
128 u16 token;
e8f081aa 129 u8 fw_status;
225c7b1f
RD		 130};
131
e8f081aa
YP		 132static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
134
ca281211
RD		 135static int mlx4_status_to_errno(u8 status)
136{
225c7b1f
RD		 137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
899698da 148 [CMD_STAT_ICM_ERROR] = -ENFILE,
225c7b1f
RD		 149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
cc4ac2e7 155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
225c7b1f
RD		 156 };
157
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
160 return -EIO;
161
162 return trans_table[status];
163}
164
72be84f1
YP		 165static u8 mlx4_errno_to_status(int errno)
166{
167 switch (errno) {
168 case -EPERM:
169 return CMD_STAT_BAD_OP;
170 case -EINVAL:
171 return CMD_STAT_BAD_PARAM;
172 case -ENXIO:
173 return CMD_STAT_BAD_SYS_STATE;
174 case -EBUSY:
175 return CMD_STAT_RESOURCE_BUSY;
176 case -ENOMEM:
177 return CMD_STAT_EXCEED_LIM;
178 case -ENFILE:
179 return CMD_STAT_ICM_ERROR;
180 default:
181 return CMD_STAT_INTERNAL_ERR;
182 }
183}
184
e8f081aa
YP		 185static int comm_pending(struct mlx4_dev *dev)
186{
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
189
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
191}
192
193static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
194{
195 struct mlx4_priv *priv = mlx4_priv(dev);
196 u32 val;
197
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
202 mmiowb();
203}
204
e8f081aa
YP		 205static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
207{
208 struct mlx4_priv *priv = mlx4_priv(dev);
209 unsigned long end;
210 int err = 0;
211 int ret_from_pending = 0;
212
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
1a91de28 215 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
e8f081aa
YP		 216 priv->cmd.comm_toggle, cmd);
217 return -EAGAIN;
218 }
219
220 /* Write command */
221 down(&priv->cmd.poll_sem);
222 mlx4_comm_cmd_post(dev, cmd, param);
223
224 end = msecs_to_jiffies(timeout) + jiffies;
225 while (comm_pending(dev) && time_before(jiffies, end))
226 cond_resched();
227 ret_from_pending = comm_pending(dev);
228 if (ret_from_pending) {
229 /* check if the slave is trying to boot in the middle of
230 * FLR process. The only non-zero result in the RESET command
231 * is MLX4_DELAY_RESET_SLAVE*/
232 if ((MLX4_COMM_CMD_RESET == cmd)) {
e8f081aa
YP		 233 err = MLX4_DELAY_RESET_SLAVE;
234 } else {
235 mlx4_warn(dev, "Communication channel timed out\n");
236 err = -ETIMEDOUT;
237 }
238 }
239
240 up(&priv->cmd.poll_sem);
241 return err;
242}
243
244static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
245 u16 param, unsigned long timeout)
246{
247 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
248 struct mlx4_cmd_context *context;
58a3de05 249 unsigned long end;
e8f081aa
YP		 250 int err = 0;
251
252 down(&cmd->event_sem);
253
254 spin_lock(&cmd->context_lock);
255 BUG_ON(cmd->free_head < 0);
256 context = &cmd->context[cmd->free_head];
257 context->token += cmd->token_mask + 1;
258 cmd->free_head = context->next;
259 spin_unlock(&cmd->context_lock);
260
261 init_completion(&context->done);
262
263 mlx4_comm_cmd_post(dev, op, param);
264
265 if (!wait_for_completion_timeout(&context->done,
266 msecs_to_jiffies(timeout))) {
674925ed
DB		 267 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
268 op);
e8f081aa
YP		 269 err = -EBUSY;
270 goto out;
271 }
272
273 err = context->result;
274 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
275 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
276 op, context->fw_status);
277 goto out;
278 }
279
280out:
58a3de05
EE		 281 /* wait for comm channel ready
282 * this is necessary for prevention the race
283 * when switching between event to polling mode
284 */
285 end = msecs_to_jiffies(timeout) + jiffies;
286 while (comm_pending(dev) && time_before(jiffies, end))
287 cond_resched();
288
e8f081aa
YP		 289 spin_lock(&cmd->context_lock);
290 context->next = cmd->free_head;
291 cmd->free_head = context - cmd->context;
292 spin_unlock(&cmd->context_lock);
293
294 up(&cmd->event_sem);
295 return err;
296}
297
ab9c17a0 298int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
e8f081aa
YP		 299 unsigned long timeout)
300{
301 if (mlx4_priv(dev)->cmd.use_events)
302 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
303 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
304}
305
225c7b1f
RD		 306static int cmd_pending(struct mlx4_dev *dev)
307{
57dbf29a
KSS		 308 u32 status;
309
310 if (pci_channel_offline(dev->pdev))
311 return -EIO;
312
313 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
225c7b1f
RD		 314
315 return (status & swab32(1 << HCR_GO_BIT)) ||
316 (mlx4_priv(dev)->cmd.toggle ==
317 !!(status & swab32(1 << HCR_T_BIT)));
318}
319
320static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
321 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
322 int event)
323{
324 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
325 u32 __iomem *hcr = cmd->hcr;
326 int ret = -EAGAIN;
327 unsigned long end;
328
329 mutex_lock(&cmd->hcr_mutex);
330
57dbf29a
KSS		 331 if (pci_channel_offline(dev->pdev)) {
332 /*
333 * Device is going through error recovery
334 * and cannot accept commands.
335 */
336 ret = -EIO;
337 goto out;
338 }
339
225c7b1f
RD		 340 end = jiffies;
341 if (event)
36ce10d3 342 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
225c7b1f
RD		 343
344 while (cmd_pending(dev)) {
57dbf29a
KSS		 345 if (pci_channel_offline(dev->pdev)) {
346 /*
347 * Device is going through error recovery
348 * and cannot accept commands.
349 */
350 ret = -EIO;
351 goto out;
352 }
353
e8f081aa
YP		 354 if (time_after_eq(jiffies, end)) {
355 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
225c7b1f 356 goto out;
e8f081aa 357 }
225c7b1f
RD		 358 cond_resched();
359 }
360
361 /*
362 * We use writel (instead of something like memcpy_toio)
363 * because writes of less than 32 bits to the HCR don't work
364 * (and some architectures such as ia64 implement memcpy_toio
365 * in terms of writeb).
366 */
367 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
368 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
369 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
370 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
371 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
372 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
373
374 /* __raw_writel may not order writes. */
375 wmb();
376
377 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
378 (cmd->toggle << HCR_T_BIT) |
379 (event ? (1 << HCR_E_BIT) : 0) |
380 (op_modifier << HCR_OPMOD_SHIFT) |
e8f081aa 381 op), hcr + 6);
2e61c646
RD		 382
383 /*
384 * Make sure that our HCR writes don't get mixed in with
385 * writes from another CPU starting a FW command.
386 */
387 mmiowb();
388
225c7b1f
RD		 389 cmd->toggle = cmd->toggle ^ 1;
390
391 ret = 0;
392
393out:
394 mutex_unlock(&cmd->hcr_mutex);
395 return ret;
396}
397
e8f081aa
YP		 398static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
399 int out_is_imm, u32 in_modifier, u8 op_modifier,
400 u16 op, unsigned long timeout)
401{
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
404 int ret;
405
f3d4c89e
RD		 406 mutex_lock(&priv->cmd.slave_cmd_mutex);
407
e8f081aa
YP		 408 vhcr->in_param = cpu_to_be64(in_param);
409 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
410 vhcr->in_modifier = cpu_to_be32(in_modifier);
411 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
412 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
413 vhcr->status = 0;
414 vhcr->flags = !!(priv->cmd.use_events) << 6;
f3d4c89e 415
e8f081aa
YP		 416 if (mlx4_is_master(dev)) {
417 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
418 if (!ret) {
419 if (out_is_imm) {
420 if (out_param)
421 *out_param =
422 be64_to_cpu(vhcr->out_param);
423 else {
1a91de28
JP		 424 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
425 op);
72be84f1 426 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 427 }
428 }
72be84f1 429 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa
YP		 430 }
431 } else {
432 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
433 MLX4_COMM_TIME + timeout);
434 if (!ret) {
435 if (out_is_imm) {
436 if (out_param)
437 *out_param =
438 be64_to_cpu(vhcr->out_param);
439 else {
1a91de28
JP		 440 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
441 op);
72be84f1 442 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 443 }
444 }
72be84f1 445 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa 446 } else
1a91de28
JP		 447 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n",
448 op);
e8f081aa 449 }
f3d4c89e
RD		 450
451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 452 return ret;
453}
454
225c7b1f
RD		 455static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
456 int out_is_imm, u32 in_modifier, u8 op_modifier,
457 u16 op, unsigned long timeout)
458{
459 struct mlx4_priv *priv = mlx4_priv(dev);
460 void __iomem *hcr = priv->cmd.hcr;
461 int err = 0;
462 unsigned long end;
e8f081aa 463 u32 stat;
225c7b1f
RD		 464
465 down(&priv->cmd.poll_sem);
466
57dbf29a
KSS		 467 if (pci_channel_offline(dev->pdev)) {
468 /*
469 * Device is going through error recovery
470 * and cannot accept commands.
471 */
472 err = -EIO;
473 goto out;
474 }
475
225c7b1f
RD		 476 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
477 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
478 if (err)
479 goto out;
480
481 end = msecs_to_jiffies(timeout) + jiffies;
57dbf29a
KSS		 482 while (cmd_pending(dev) && time_before(jiffies, end)) {
483 if (pci_channel_offline(dev->pdev)) {
484 /*
485 * Device is going through error recovery
486 * and cannot accept commands.
487 */
488 err = -EIO;
489 goto out;
490 }
491
225c7b1f 492 cond_resched();
57dbf29a 493 }
225c7b1f
RD		 494
495 if (cmd_pending(dev)) {
674925ed
DB		 496 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
497 op);
225c7b1f
RD		 498 err = -ETIMEDOUT;
499 goto out;
500 }
501
502 if (out_is_imm)
503 *out_param =
504 (u64) be32_to_cpu((__force __be32)
505 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
506 (u64) be32_to_cpu((__force __be32)
507 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
e8f081aa
YP		 508 stat = be32_to_cpu((__force __be32)
509 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
510 err = mlx4_status_to_errno(stat);
511 if (err)
512 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
513 op, stat);
225c7b1f
RD		 514
515out:
516 up(&priv->cmd.poll_sem);
517 return err;
518}
519
520void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
521{
522 struct mlx4_priv *priv = mlx4_priv(dev);
523 struct mlx4_cmd_context *context =
524 &priv->cmd.context[token & priv->cmd.token_mask];
525
526 /* previously timed out command completing at long last */
527 if (token != context->token)
528 return;
529
e8f081aa 530 context->fw_status = status;
225c7b1f
RD		 531 context->result = mlx4_status_to_errno(status);
532 context->out_param = out_param;
533
225c7b1f
RD		 534 complete(&context->done);
535}
536
537static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
538 int out_is_imm, u32 in_modifier, u8 op_modifier,
539 u16 op, unsigned long timeout)
540{
541 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
542 struct mlx4_cmd_context *context;
543 int err = 0;
544
545 down(&cmd->event_sem);
546
547 spin_lock(&cmd->context_lock);
548 BUG_ON(cmd->free_head < 0);
549 context = &cmd->context[cmd->free_head];
0981582d 550 context->token += cmd->token_mask + 1;
225c7b1f
RD		 551 cmd->free_head = context->next;
552 spin_unlock(&cmd->context_lock);
553
554 init_completion(&context->done);
555
556 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
557 in_modifier, op_modifier, op, context->token, 1);
558
e8f081aa
YP		 559 if (!wait_for_completion_timeout(&context->done,
560 msecs_to_jiffies(timeout))) {
674925ed
DB		 561 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
562 op);
225c7b1f
RD		 563 err = -EBUSY;
564 goto out;
565 }
566
567 err = context->result;
e8f081aa
YP		 568 if (err) {
569 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
570 op, context->fw_status);
225c7b1f 571 goto out;
e8f081aa 572 }
225c7b1f
RD		 573
574 if (out_is_imm)
575 *out_param = context->out_param;
576
577out:
578 spin_lock(&cmd->context_lock);
579 context->next = cmd->free_head;
580 cmd->free_head = context - cmd->context;
581 spin_unlock(&cmd->context_lock);
582
583 up(&cmd->event_sem);
584 return err;
585}
586
587int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
588 int out_is_imm, u32 in_modifier, u8 op_modifier,
f9baff50 589 u16 op, unsigned long timeout, int native)
225c7b1f 590{
57dbf29a
KSS		 591 if (pci_channel_offline(dev->pdev))
592 return -EIO;
593
e8f081aa
YP		 594 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
595 if (mlx4_priv(dev)->cmd.use_events)
596 return mlx4_cmd_wait(dev, in_param, out_param,
597 out_is_imm, in_modifier,
598 op_modifier, op, timeout);
599 else
600 return mlx4_cmd_poll(dev, in_param, out_param,
601 out_is_imm, in_modifier,
602 op_modifier, op, timeout);
603 }
604 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
605 in_modifier, op_modifier, op, timeout);
225c7b1f
RD		 606}
607EXPORT_SYMBOL_GPL(__mlx4_cmd);
608
e8f081aa
YP		 609
610static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
611{
612 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
613 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
614}
615
616static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
617 int slave, u64 slave_addr,
618 int size, int is_read)
619{
620 u64 in_param;
621 u64 out_param;
622
623 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
624 (slave & ~0x7f) | (size & 0xff)) {
1a91de28
JP		 625 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
626 slave_addr, master_addr, slave, size);
e8f081aa
YP		 627 return -EINVAL;
628 }
629
630 if (is_read) {
631 in_param = (u64) slave | slave_addr;
632 out_param = (u64) dev->caps.function | master_addr;
633 } else {
634 in_param = (u64) dev->caps.function | master_addr;
635 out_param = (u64) slave | slave_addr;
636 }
637
638 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
639 MLX4_CMD_ACCESS_MEM,
640 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
641}
642
0a9a0188
JM		 643static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
644 struct mlx4_cmd_mailbox *inbox,
645 struct mlx4_cmd_mailbox *outbox)
646{
647 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
648 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
649 int err;
650 int i;
651
652 if (index & 0x1f)
653 return -EINVAL;
654
655 in_mad->attr_mod = cpu_to_be32(index / 32);
656
657 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
658 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
659 MLX4_CMD_NATIVE);
660 if (err)
661 return err;
662
663 for (i = 0; i < 32; ++i)
664 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
665
666 return err;
667}
668
669static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
670 struct mlx4_cmd_mailbox *inbox,
671 struct mlx4_cmd_mailbox *outbox)
672{
673 int i;
674 int err;
675
676 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
677 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
678 if (err)
679 return err;
680 }
681
682 return 0;
683}
684#define PORT_CAPABILITY_LOCATION_IN_SMP 20
685#define PORT_STATE_OFFSET 32
686
687static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
688{
a0c64a17
JM		 689 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
690 return IB_PORT_ACTIVE;
691 else
692 return IB_PORT_DOWN;
0a9a0188
JM		 693}
694
695static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
696 struct mlx4_vhcr *vhcr,
697 struct mlx4_cmd_mailbox *inbox,
698 struct mlx4_cmd_mailbox *outbox,
699 struct mlx4_cmd_info *cmd)
700{
701 struct ib_smp *smp = inbox->buf;
702 u32 index;
703 u8 port;
704 u16 *table;
705 int err;
706 int vidx, pidx;
707 struct mlx4_priv *priv = mlx4_priv(dev);
708 struct ib_smp *outsmp = outbox->buf;
709 __be16 *outtab = (__be16 *)(outsmp->data);
710 __be32 slave_cap_mask;
afa8fd1d 711 __be64 slave_node_guid;
0a9a0188
JM		 712 port = vhcr->in_modifier;
713
714 if (smp->base_version == 1 &&
715 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
716 smp->class_version == 1) {
717 if (smp->method == IB_MGMT_METHOD_GET) {
718 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
719 index = be32_to_cpu(smp->attr_mod);
720 if (port < 1 || port > dev->caps.num_ports)
721 return -EINVAL;
722 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
723 if (!table)
724 return -ENOMEM;
725 /* need to get the full pkey table because the paravirtualized
726 * pkeys may be scattered among several pkey blocks.
727 */
728 err = get_full_pkey_table(dev, port, table, inbox, outbox);
729 if (!err) {
730 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
731 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
732 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
733 }
734 }
735 kfree(table);
736 return err;
737 }
738 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
739 /*get the slave specific caps:*/
740 /*do the command */
741 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
742 vhcr->in_modifier, vhcr->op_modifier,
743 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
744 /* modify the response for slaves */
745 if (!err && slave != mlx4_master_func_num(dev)) {
746 u8 *state = outsmp->data + PORT_STATE_OFFSET;
747
748 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
749 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
750 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
751 }
752 return err;
753 }
754 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
755 /* compute slave's gid block */
756 smp->attr_mod = cpu_to_be32(slave / 8);
757 /* execute cmd */
758 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
759 vhcr->in_modifier, vhcr->op_modifier,
760 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
761 if (!err) {
762 /* if needed, move slave gid to index 0 */
763 if (slave % 8)
764 memcpy(outsmp->data,
765 outsmp->data + (slave % 8) * 8, 8);
766 /* delete all other gids */
767 memset(outsmp->data + 8, 0, 56);
768 }
769 return err;
770 }
afa8fd1d
JM		 771 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
772 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
773 vhcr->in_modifier, vhcr->op_modifier,
774 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
775 if (!err) {
776 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
777 memcpy(outsmp->data + 12, &slave_node_guid, 8);
778 }
779 return err;
780 }
0a9a0188
JM		 781 }
782 }
783 if (slave != mlx4_master_func_num(dev) &&
784 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
785 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
786 smp->method == IB_MGMT_METHOD_SET))) {
1a91de28 787 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x for attr 0x%x - Rejecting\n",
0a9a0188
JM		 788 slave, smp->method, smp->mgmt_class,
789 be16_to_cpu(smp->attr_id));
790 return -EPERM;
791 }
792 /*default:*/
793 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
794 vhcr->in_modifier, vhcr->op_modifier,
795 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
796}
797
b7475794 798static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
fe6f700d
YP		 799 struct mlx4_vhcr *vhcr,
800 struct mlx4_cmd_mailbox *inbox,
801 struct mlx4_cmd_mailbox *outbox,
802 struct mlx4_cmd_info *cmd)
803{
804 return -EPERM;
805}
806
e8f081aa
YP		 807int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
808 struct mlx4_vhcr *vhcr,
809 struct mlx4_cmd_mailbox *inbox,
810 struct mlx4_cmd_mailbox *outbox,
811 struct mlx4_cmd_info *cmd)
812{
813 u64 in_param;
814 u64 out_param;
815 int err;
816
817 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
818 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
819 if (cmd->encode_slave_id) {
820 in_param &= 0xffffffffffffff00ll;
821 in_param |= slave;
822 }
823
824 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
825 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
826 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
827
828 if (cmd->out_is_imm)
829 vhcr->out_param = out_param;
830
831 return err;
832}
833
834static struct mlx4_cmd_info cmd_info[] = {
835 {
836 .opcode = MLX4_CMD_QUERY_FW,
837 .has_inbox = false,
838 .has_outbox = true,
839 .out_is_imm = false,
840 .encode_slave_id = false,
841 .verify = NULL,
b91cb3eb 842 .wrapper = mlx4_QUERY_FW_wrapper
e8f081aa
YP		 843 },
844 {
845 .opcode = MLX4_CMD_QUERY_HCA,
846 .has_inbox = false,
847 .has_outbox = true,
848 .out_is_imm = false,
849 .encode_slave_id = false,
850 .verify = NULL,
851 .wrapper = NULL
852 },
853 {
854 .opcode = MLX4_CMD_QUERY_DEV_CAP,
855 .has_inbox = false,
856 .has_outbox = true,
857 .out_is_imm = false,
858 .encode_slave_id = false,
859 .verify = NULL,
b91cb3eb 860 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
e8f081aa 861 },
c82e9aa0
EC		 862 {
863 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
864 .has_inbox = false,
865 .has_outbox = true,
866 .out_is_imm = false,
867 .encode_slave_id = false,
868 .verify = NULL,
869 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
870 },
871 {
872 .opcode = MLX4_CMD_QUERY_ADAPTER,
873 .has_inbox = false,
874 .has_outbox = true,
875 .out_is_imm = false,
876 .encode_slave_id = false,
877 .verify = NULL,
878 .wrapper = NULL
879 },
880 {
881 .opcode = MLX4_CMD_INIT_PORT,
882 .has_inbox = false,
883 .has_outbox = false,
884 .out_is_imm = false,
885 .encode_slave_id = false,
886 .verify = NULL,
887 .wrapper = mlx4_INIT_PORT_wrapper
888 },
889 {
890 .opcode = MLX4_CMD_CLOSE_PORT,
891 .has_inbox = false,
892 .has_outbox = false,
893 .out_is_imm = false,
894 .encode_slave_id = false,
895 .verify = NULL,
896 .wrapper = mlx4_CLOSE_PORT_wrapper
897 },
898 {
899 .opcode = MLX4_CMD_QUERY_PORT,
900 .has_inbox = false,
901 .has_outbox = true,
902 .out_is_imm = false,
903 .encode_slave_id = false,
904 .verify = NULL,
905 .wrapper = mlx4_QUERY_PORT_wrapper
906 },
ffe455ad
EE		 907 {
908 .opcode = MLX4_CMD_SET_PORT,
909 .has_inbox = true,
910 .has_outbox = false,
911 .out_is_imm = false,
912 .encode_slave_id = false,
913 .verify = NULL,
914 .wrapper = mlx4_SET_PORT_wrapper
915 },
c82e9aa0
EC		 916 {
917 .opcode = MLX4_CMD_MAP_EQ,
918 .has_inbox = false,
919 .has_outbox = false,
920 .out_is_imm = false,
921 .encode_slave_id = false,
922 .verify = NULL,
923 .wrapper = mlx4_MAP_EQ_wrapper
924 },
925 {
926 .opcode = MLX4_CMD_SW2HW_EQ,
927 .has_inbox = true,
928 .has_outbox = false,
929 .out_is_imm = false,
930 .encode_slave_id = true,
931 .verify = NULL,
932 .wrapper = mlx4_SW2HW_EQ_wrapper
933 },
934 {
935 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
936 .has_inbox = false,
937 .has_outbox = false,
938 .out_is_imm = false,
939 .encode_slave_id = false,
940 .verify = NULL,
941 .wrapper = NULL
942 },
943 {
944 .opcode = MLX4_CMD_NOP,
945 .has_inbox = false,
946 .has_outbox = false,
947 .out_is_imm = false,
948 .encode_slave_id = false,
949 .verify = NULL,
950 .wrapper = NULL
951 },
d18f141a
OG		 952 {
953 .opcode = MLX4_CMD_CONFIG_DEV,
954 .has_inbox = false,
955 .has_outbox = false,
956 .out_is_imm = false,
957 .encode_slave_id = false,
958 .verify = NULL,
959 .wrapper = mlx4_CMD_EPERM_wrapper
960 },
c82e9aa0
EC		 961 {
962 .opcode = MLX4_CMD_ALLOC_RES,
963 .has_inbox = false,
964 .has_outbox = false,
965 .out_is_imm = true,
966 .encode_slave_id = false,
967 .verify = NULL,
968 .wrapper = mlx4_ALLOC_RES_wrapper
969 },
970 {
971 .opcode = MLX4_CMD_FREE_RES,
972 .has_inbox = false,
973 .has_outbox = false,
974 .out_is_imm = false,
975 .encode_slave_id = false,
976 .verify = NULL,
977 .wrapper = mlx4_FREE_RES_wrapper
978 },
979 {
980 .opcode = MLX4_CMD_SW2HW_MPT,
981 .has_inbox = true,
982 .has_outbox = false,
983 .out_is_imm = false,
984 .encode_slave_id = true,
985 .verify = NULL,
986 .wrapper = mlx4_SW2HW_MPT_wrapper
987 },
988 {
989 .opcode = MLX4_CMD_QUERY_MPT,
990 .has_inbox = false,
991 .has_outbox = true,
992 .out_is_imm = false,
993 .encode_slave_id = false,
994 .verify = NULL,
995 .wrapper = mlx4_QUERY_MPT_wrapper
996 },
997 {
998 .opcode = MLX4_CMD_HW2SW_MPT,
999 .has_inbox = false,
1000 .has_outbox = false,
1001 .out_is_imm = false,
1002 .encode_slave_id = false,
1003 .verify = NULL,
1004 .wrapper = mlx4_HW2SW_MPT_wrapper
1005 },
1006 {
1007 .opcode = MLX4_CMD_READ_MTT,
1008 .has_inbox = false,
1009 .has_outbox = true,
1010 .out_is_imm = false,
1011 .encode_slave_id = false,
1012 .verify = NULL,
1013 .wrapper = NULL
1014 },
1015 {
1016 .opcode = MLX4_CMD_WRITE_MTT,
1017 .has_inbox = true,
1018 .has_outbox = false,
1019 .out_is_imm = false,
1020 .encode_slave_id = false,
1021 .verify = NULL,
1022 .wrapper = mlx4_WRITE_MTT_wrapper
1023 },
1024 {
1025 .opcode = MLX4_CMD_SYNC_TPT,
1026 .has_inbox = true,
1027 .has_outbox = false,
1028 .out_is_imm = false,
1029 .encode_slave_id = false,
1030 .verify = NULL,
1031 .wrapper = NULL
1032 },
1033 {
1034 .opcode = MLX4_CMD_HW2SW_EQ,
1035 .has_inbox = false,
1036 .has_outbox = true,
1037 .out_is_imm = false,
1038 .encode_slave_id = true,
1039 .verify = NULL,
1040 .wrapper = mlx4_HW2SW_EQ_wrapper
1041 },
1042 {
1043 .opcode = MLX4_CMD_QUERY_EQ,
1044 .has_inbox = false,
1045 .has_outbox = true,
1046 .out_is_imm = false,
1047 .encode_slave_id = true,
1048 .verify = NULL,
1049 .wrapper = mlx4_QUERY_EQ_wrapper
1050 },
1051 {
1052 .opcode = MLX4_CMD_SW2HW_CQ,
1053 .has_inbox = true,
1054 .has_outbox = false,
1055 .out_is_imm = false,
1056 .encode_slave_id = true,
1057 .verify = NULL,
1058 .wrapper = mlx4_SW2HW_CQ_wrapper
1059 },
1060 {
1061 .opcode = MLX4_CMD_HW2SW_CQ,
1062 .has_inbox = false,
1063 .has_outbox = false,
1064 .out_is_imm = false,
1065 .encode_slave_id = false,
1066 .verify = NULL,
1067 .wrapper = mlx4_HW2SW_CQ_wrapper
1068 },
1069 {
1070 .opcode = MLX4_CMD_QUERY_CQ,
1071 .has_inbox = false,
1072 .has_outbox = true,
1073 .out_is_imm = false,
1074 .encode_slave_id = false,
1075 .verify = NULL,
1076 .wrapper = mlx4_QUERY_CQ_wrapper
1077 },
1078 {
1079 .opcode = MLX4_CMD_MODIFY_CQ,
1080 .has_inbox = true,
1081 .has_outbox = false,
1082 .out_is_imm = true,
1083 .encode_slave_id = false,
1084 .verify = NULL,
1085 .wrapper = mlx4_MODIFY_CQ_wrapper
1086 },
1087 {
1088 .opcode = MLX4_CMD_SW2HW_SRQ,
1089 .has_inbox = true,
1090 .has_outbox = false,
1091 .out_is_imm = false,
1092 .encode_slave_id = true,
1093 .verify = NULL,
1094 .wrapper = mlx4_SW2HW_SRQ_wrapper
1095 },
1096 {
1097 .opcode = MLX4_CMD_HW2SW_SRQ,
1098 .has_inbox = false,
1099 .has_outbox = false,
1100 .out_is_imm = false,
1101 .encode_slave_id = false,
1102 .verify = NULL,
1103 .wrapper = mlx4_HW2SW_SRQ_wrapper
1104 },
1105 {
1106 .opcode = MLX4_CMD_QUERY_SRQ,
1107 .has_inbox = false,
1108 .has_outbox = true,
1109 .out_is_imm = false,
1110 .encode_slave_id = false,
1111 .verify = NULL,
1112 .wrapper = mlx4_QUERY_SRQ_wrapper
1113 },
1114 {
1115 .opcode = MLX4_CMD_ARM_SRQ,
1116 .has_inbox = false,
1117 .has_outbox = false,
1118 .out_is_imm = false,
1119 .encode_slave_id = false,
1120 .verify = NULL,
1121 .wrapper = mlx4_ARM_SRQ_wrapper
1122 },
1123 {
1124 .opcode = MLX4_CMD_RST2INIT_QP,
1125 .has_inbox = true,
1126 .has_outbox = false,
1127 .out_is_imm = false,
1128 .encode_slave_id = true,
1129 .verify = NULL,
1130 .wrapper = mlx4_RST2INIT_QP_wrapper
1131 },
1132 {
1133 .opcode = MLX4_CMD_INIT2INIT_QP,
1134 .has_inbox = true,
1135 .has_outbox = false,
1136 .out_is_imm = false,
1137 .encode_slave_id = false,
1138 .verify = NULL,
54679e14 1139 .wrapper = mlx4_INIT2INIT_QP_wrapper
c82e9aa0
EC		 1140 },
1141 {
1142 .opcode = MLX4_CMD_INIT2RTR_QP,
1143 .has_inbox = true,
1144 .has_outbox = false,
1145 .out_is_imm = false,
1146 .encode_slave_id = false,
1147 .verify = NULL,
1148 .wrapper = mlx4_INIT2RTR_QP_wrapper
1149 },
1150 {
1151 .opcode = MLX4_CMD_RTR2RTS_QP,
1152 .has_inbox = true,
1153 .has_outbox = false,
1154 .out_is_imm = false,
1155 .encode_slave_id = false,
1156 .verify = NULL,
54679e14 1157 .wrapper = mlx4_RTR2RTS_QP_wrapper
c82e9aa0
EC		 1158 },
1159 {
1160 .opcode = MLX4_CMD_RTS2RTS_QP,
1161 .has_inbox = true,
1162 .has_outbox = false,
1163 .out_is_imm = false,
1164 .encode_slave_id = false,
1165 .verify = NULL,
54679e14 1166 .wrapper = mlx4_RTS2RTS_QP_wrapper
c82e9aa0
EC		 1167 },
1168 {
1169 .opcode = MLX4_CMD_SQERR2RTS_QP,
1170 .has_inbox = true,
1171 .has_outbox = false,
1172 .out_is_imm = false,
1173 .encode_slave_id = false,
1174 .verify = NULL,
54679e14 1175 .wrapper = mlx4_SQERR2RTS_QP_wrapper
c82e9aa0
EC		 1176 },
1177 {
1178 .opcode = MLX4_CMD_2ERR_QP,
1179 .has_inbox = false,
1180 .has_outbox = false,
1181 .out_is_imm = false,
1182 .encode_slave_id = false,
1183 .verify = NULL,
1184 .wrapper = mlx4_GEN_QP_wrapper
1185 },
1186 {
1187 .opcode = MLX4_CMD_RTS2SQD_QP,
1188 .has_inbox = false,
1189 .has_outbox = false,
1190 .out_is_imm = false,
1191 .encode_slave_id = false,
1192 .verify = NULL,
1193 .wrapper = mlx4_GEN_QP_wrapper
1194 },
1195 {
1196 .opcode = MLX4_CMD_SQD2SQD_QP,
1197 .has_inbox = true,
1198 .has_outbox = false,
1199 .out_is_imm = false,
1200 .encode_slave_id = false,
1201 .verify = NULL,
54679e14 1202 .wrapper = mlx4_SQD2SQD_QP_wrapper
c82e9aa0
EC		 1203 },
1204 {
1205 .opcode = MLX4_CMD_SQD2RTS_QP,
1206 .has_inbox = true,
1207 .has_outbox = false,
1208 .out_is_imm = false,
1209 .encode_slave_id = false,
1210 .verify = NULL,
54679e14 1211 .wrapper = mlx4_SQD2RTS_QP_wrapper
c82e9aa0
EC		 1212 },
1213 {
1214 .opcode = MLX4_CMD_2RST_QP,
1215 .has_inbox = false,
1216 .has_outbox = false,
1217 .out_is_imm = false,
1218 .encode_slave_id = false,
1219 .verify = NULL,
1220 .wrapper = mlx4_2RST_QP_wrapper
1221 },
1222 {
1223 .opcode = MLX4_CMD_QUERY_QP,
1224 .has_inbox = false,
1225 .has_outbox = true,
1226 .out_is_imm = false,
1227 .encode_slave_id = false,
1228 .verify = NULL,
1229 .wrapper = mlx4_GEN_QP_wrapper
1230 },
1231 {
1232 .opcode = MLX4_CMD_SUSPEND_QP,
1233 .has_inbox = false,
1234 .has_outbox = false,
1235 .out_is_imm = false,
1236 .encode_slave_id = false,
1237 .verify = NULL,
1238 .wrapper = mlx4_GEN_QP_wrapper
1239 },
1240 {
1241 .opcode = MLX4_CMD_UNSUSPEND_QP,
1242 .has_inbox = false,
1243 .has_outbox = false,
1244 .out_is_imm = false,
1245 .encode_slave_id = false,
1246 .verify = NULL,
1247 .wrapper = mlx4_GEN_QP_wrapper
1248 },
b01978ca
JM		 1249 {
1250 .opcode = MLX4_CMD_UPDATE_QP,
1251 .has_inbox = false,
1252 .has_outbox = false,
1253 .out_is_imm = false,
1254 .encode_slave_id = false,
1255 .verify = NULL,
b7475794 1256 .wrapper = mlx4_CMD_EPERM_wrapper
b01978ca 1257 },
fe6f700d
YP		 1258 {
1259 .opcode = MLX4_CMD_GET_OP_REQ,
1260 .has_inbox = false,
1261 .has_outbox = false,
1262 .out_is_imm = false,
1263 .encode_slave_id = false,
1264 .verify = NULL,
b7475794 1265 .wrapper = mlx4_CMD_EPERM_wrapper,
fe6f700d 1266 },
0a9a0188
JM		 1267 {
1268 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1269 .has_inbox = false,
1270 .has_outbox = false,
1271 .out_is_imm = false,
1272 .encode_slave_id = false,
1273 .verify = NULL, /* XXX verify: only demux can do this */
1274 .wrapper = NULL
1275 },
1276 {
1277 .opcode = MLX4_CMD_MAD_IFC,
1278 .has_inbox = true,
1279 .has_outbox = true,
1280 .out_is_imm = false,
1281 .encode_slave_id = false,
1282 .verify = NULL,
1283 .wrapper = mlx4_MAD_IFC_wrapper
1284 },
c82e9aa0
EC		 1285 {
1286 .opcode = MLX4_CMD_QUERY_IF_STAT,
1287 .has_inbox = false,
1288 .has_outbox = true,
1289 .out_is_imm = false,
1290 .encode_slave_id = false,
1291 .verify = NULL,
1292 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1293 },
1294 /* Native multicast commands are not available for guests */
1295 {
1296 .opcode = MLX4_CMD_QP_ATTACH,
1297 .has_inbox = true,
1298 .has_outbox = false,
1299 .out_is_imm = false,
1300 .encode_slave_id = false,
1301 .verify = NULL,
1302 .wrapper = mlx4_QP_ATTACH_wrapper
1303 },
0ec2c0f8
EE		 1304 {
1305 .opcode = MLX4_CMD_PROMISC,
1306 .has_inbox = false,
1307 .has_outbox = false,
1308 .out_is_imm = false,
1309 .encode_slave_id = false,
1310 .verify = NULL,
1311 .wrapper = mlx4_PROMISC_wrapper
1312 },
ffe455ad
EE		 1313 /* Ethernet specific commands */
1314 {
1315 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1316 .has_inbox = true,
1317 .has_outbox = false,
1318 .out_is_imm = false,
1319 .encode_slave_id = false,
1320 .verify = NULL,
1321 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1322 },
1323 {
1324 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1325 .has_inbox = false,
1326 .has_outbox = false,
1327 .out_is_imm = false,
1328 .encode_slave_id = false,
1329 .verify = NULL,
1330 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1331 },
1332 {
1333 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1334 .has_inbox = false,
1335 .has_outbox = true,
1336 .out_is_imm = false,
1337 .encode_slave_id = false,
1338 .verify = NULL,
1339 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1340 },
c82e9aa0
EC		 1341 {
1342 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1343 .has_inbox = false,
1344 .has_outbox = false,
1345 .out_is_imm = false,
1346 .encode_slave_id = false,
1347 .verify = NULL,
1348 .wrapper = NULL
1349 },
8fcfb4db
HHZ		 1350 /* flow steering commands */
1351 {
1352 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1353 .has_inbox = true,
1354 .has_outbox = false,
1355 .out_is_imm = true,
1356 .encode_slave_id = false,
1357 .verify = NULL,
1358 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1359 },
1360 {
1361 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1362 .has_inbox = false,
1363 .has_outbox = false,
1364 .out_is_imm = false,
1365 .encode_slave_id = false,
1366 .verify = NULL,
1367 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1368 },
4de65803
MB		 1369 {
1370 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1371 .has_inbox = false,
1372 .has_outbox = false,
1373 .out_is_imm = false,
1374 .encode_slave_id = false,
1375 .verify = NULL,
b7475794 1376 .wrapper = mlx4_CMD_EPERM_wrapper
4de65803 1377 },
e8f081aa
YP		 1378};
1379
1380static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1381 struct mlx4_vhcr_cmd *in_vhcr)
1382{
1383 struct mlx4_priv *priv = mlx4_priv(dev);
1384 struct mlx4_cmd_info *cmd = NULL;
1385 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1386 struct mlx4_vhcr *vhcr;
1387 struct mlx4_cmd_mailbox *inbox = NULL;
1388 struct mlx4_cmd_mailbox *outbox = NULL;
1389 u64 in_param;
1390 u64 out_param;
1391 int ret = 0;
1392 int i;
72be84f1 1393 int err = 0;
e8f081aa
YP		 1394
1395 /* Create sw representation of Virtual HCR */
1396 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1397 if (!vhcr)
1398 return -ENOMEM;
1399
1400 /* DMA in the vHCR */
1401 if (!in_vhcr) {
1402 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1403 priv->mfunc.master.slave_state[slave].vhcr_dma,
1404 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1405 MLX4_ACCESS_MEM_ALIGN), 1);
1406 if (ret) {
1a91de28
JP		 1407 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1408 __func__, ret);
e8f081aa
YP		 1409 kfree(vhcr);
1410 return ret;
1411 }
1412 }
1413
1414 /* Fill SW VHCR fields */
1415 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1416 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1417 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1418 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1419 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1420 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1421 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1422
1423 /* Lookup command */
1424 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1425 if (vhcr->op == cmd_info[i].opcode) {
1426 cmd = &cmd_info[i];
1427 break;
1428 }
1429 }
1430 if (!cmd) {
1431 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1432 vhcr->op, slave);
72be84f1 1433 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 1434 goto out_status;
1435 }
1436
1437 /* Read inbox */
1438 if (cmd->has_inbox) {
1439 vhcr->in_param &= INBOX_MASK;
1440 inbox = mlx4_alloc_cmd_mailbox(dev);
1441 if (IS_ERR(inbox)) {
72be84f1 1442 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1443 inbox = NULL;
72be84f1 1444 goto out_status;
e8f081aa
YP		 1445 }
1446
72be84f1
YP		 1447 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1448 vhcr->in_param,
1449 MLX4_MAILBOX_SIZE, 1)) {
e8f081aa
YP		 1450 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1451 __func__, cmd->opcode);
72be84f1
YP		 1452 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1453 goto out_status;
e8f081aa
YP		 1454 }
1455 }
1456
1457 /* Apply permission and bound checks if applicable */
1458 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1a91de28
JP		 1459 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1460 vhcr->op, slave, vhcr->in_modifier);
72be84f1 1461 vhcr_cmd->status = CMD_STAT_BAD_OP;
e8f081aa
YP		 1462 goto out_status;
1463 }
1464
1465 /* Allocate outbox */
1466 if (cmd->has_outbox) {
1467 outbox = mlx4_alloc_cmd_mailbox(dev);
1468 if (IS_ERR(outbox)) {
72be84f1 1469 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1470 outbox = NULL;
72be84f1 1471 goto out_status;
e8f081aa
YP		 1472 }
1473 }
1474
1475 /* Execute the command! */
1476 if (cmd->wrapper) {
72be84f1
YP		 1477 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1478 cmd);
e8f081aa
YP		 1479 if (cmd->out_is_imm)
1480 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1481 } else {
1482 in_param = cmd->has_inbox ? (u64) inbox->dma :
1483 vhcr->in_param;
1484 out_param = cmd->has_outbox ? (u64) outbox->dma :
1485 vhcr->out_param;
72be84f1
YP		 1486 err = __mlx4_cmd(dev, in_param, &out_param,
1487 cmd->out_is_imm, vhcr->in_modifier,
1488 vhcr->op_modifier, vhcr->op,
1489 MLX4_CMD_TIME_CLASS_A,
1490 MLX4_CMD_NATIVE);
e8f081aa
YP		 1491
1492 if (cmd->out_is_imm) {
1493 vhcr->out_param = out_param;
1494 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1495 }
1496 }
1497
72be84f1 1498 if (err) {
1a91de28 1499 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
72be84f1
YP		 1500 vhcr->op, slave, vhcr->errno, err);
1501 vhcr_cmd->status = mlx4_errno_to_status(err);
1502 goto out_status;
1503 }
1504
1505
e8f081aa 1506 /* Write outbox if command completed successfully */
72be84f1 1507 if (cmd->has_outbox && !vhcr_cmd->status) {
e8f081aa
YP		 1508 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1509 vhcr->out_param,
1510 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1511 if (ret) {
72be84f1
YP		 1512 /* If we failed to write back the outbox after the
1513 *command was successfully executed, we must fail this
1514 * slave, as it is now in undefined state */
e8f081aa
YP		 1515 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1516 goto out;
1517 }
1518 }
1519
1520out_status:
1521 /* DMA back vhcr result */
1522 if (!in_vhcr) {
1523 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1524 priv->mfunc.master.slave_state[slave].vhcr_dma,
1525 ALIGN(sizeof(struct mlx4_vhcr),
1526 MLX4_ACCESS_MEM_ALIGN),
1527 MLX4_CMD_WRAPPED);
1528 if (ret)
1529 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1530 __func__);
1531 else if (vhcr->e_bit &&
1532 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1a91de28
JP		 1533 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1534 slave);
e8f081aa
YP		 1535 }
1536
1537out:
1538 kfree(vhcr);
1539 mlx4_free_cmd_mailbox(dev, inbox);
1540 mlx4_free_cmd_mailbox(dev, outbox);
1541 return ret;
1542}
1543
f094668c 1544static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
b01978ca
JM		 1545 int slave, int port)
1546{
1547 struct mlx4_vport_oper_state *vp_oper;
1548 struct mlx4_vport_state *vp_admin;
1549 struct mlx4_vf_immed_vlan_work *work;
0a6eac24 1550 struct mlx4_dev *dev = &(priv->dev);
b01978ca
JM		 1551 int err;
1552 int admin_vlan_ix = NO_INDX;
1553
1554 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1555 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1556
1557 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
0a6eac24
RE		 1558 vp_oper->state.default_qos == vp_admin->default_qos &&
1559 vp_oper->state.link_state == vp_admin->link_state)
b01978ca
JM		 1560 return 0;
1561
0a6eac24 1562 if (!(priv->mfunc.master.slave_state[slave].active &&
f0f829bf 1563 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
0a6eac24
RE		 1564 /* even if the UPDATE_QP command isn't supported, we still want
1565 * to set this VF link according to the admin directive
1566 */
1567 vp_oper->state.link_state = vp_admin->link_state;
1568 return -1;
1569 }
1570
1571 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1572 slave, port);
1a91de28
JP		 1573 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1574 vp_admin->default_vlan, vp_admin->default_qos,
1575 vp_admin->link_state);
0a6eac24 1576
b01978ca
JM		 1577 work = kzalloc(sizeof(*work), GFP_KERNEL);
1578 if (!work)
1579 return -ENOMEM;
1580
1581 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
f0f829bf
RE		 1582 if (MLX4_VGT != vp_admin->default_vlan) {
1583 err = __mlx4_register_vlan(&priv->dev, port,
1584 vp_admin->default_vlan,
1585 &admin_vlan_ix);
1586 if (err) {
1587 kfree(work);
1a91de28 1588 mlx4_warn(&priv->dev,
f0f829bf
RE		 1589 "No vlan resources slave %d, port %d\n",
1590 slave, port);
1591 return err;
1592 }
1593 } else {
1594 admin_vlan_ix = NO_INDX;
b01978ca
JM		 1595 }
1596 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1a91de28 1597 mlx4_dbg(&priv->dev,
b01978ca
JM		 1598 "alloc vlan %d idx %d slave %d port %d\n",
1599 (int)(vp_admin->default_vlan),
1600 admin_vlan_ix, slave, port);
1601 }
1602
1603 /* save original vlan ix and vlan id */
1604 work->orig_vlan_id = vp_oper->state.default_vlan;
1605 work->orig_vlan_ix = vp_oper->vlan_idx;
1606
1607 /* handle new qos */
1608 if (vp_oper->state.default_qos != vp_admin->default_qos)
1609 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1610
1611 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1612 vp_oper->vlan_idx = admin_vlan_ix;
1613
1614 vp_oper->state.default_vlan = vp_admin->default_vlan;
1615 vp_oper->state.default_qos = vp_admin->default_qos;
0a6eac24
RE		 1616 vp_oper->state.link_state = vp_admin->link_state;
1617
1618 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1619 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
b01978ca
JM		 1620
1621 /* iterate over QPs owned by this slave, using UPDATE_QP */
1622 work->port = port;
1623 work->slave = slave;
1624 work->qos = vp_oper->state.default_qos;
1625 work->vlan_id = vp_oper->state.default_vlan;
1626 work->vlan_ix = vp_oper->vlan_idx;
1627 work->priv = priv;
1628 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1629 queue_work(priv->mfunc.master.comm_wq, &work->work);
1630
1631 return 0;
1632}
1633
1634
0eb62b93
RE		 1635static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1636{
3f7fb021
RE		 1637 int port, err;
1638 struct mlx4_vport_state *vp_admin;
1639 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1640 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1641 &priv->dev, slave);
1642 int min_port = find_first_bit(actv_ports.ports,
1643 priv->dev.caps.num_ports) + 1;
1644 int max_port = min_port - 1 +
1645 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1646
1647 for (port = min_port; port <= max_port; port++) {
1648 if (!test_bit(port - 1, actv_ports.ports))
1649 continue;
3f7fb021
RE		 1650 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1651 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1652 vp_oper->state = *vp_admin;
1653 if (MLX4_VGT != vp_admin->default_vlan) {
1654 err = __mlx4_register_vlan(&priv->dev, port,
1655 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1656 if (err) {
1657 vp_oper->vlan_idx = NO_INDX;
1a91de28 1658 mlx4_warn(&priv->dev,
3f7fb021
RE		 1659 "No vlan resorces slave %d, port %d\n",
1660 slave, port);
1661 return err;
1662 }
1a91de28 1663 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
3f7fb021
RE		 1664 (int)(vp_oper->state.default_vlan),
1665 vp_oper->vlan_idx, slave, port);
1666 }
e6b6a231
RE		 1667 if (vp_admin->spoofchk) {
1668 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1669 port,
1670 vp_admin->mac);
1671 if (0 > vp_oper->mac_idx) {
1672 err = vp_oper->mac_idx;
1673 vp_oper->mac_idx = NO_INDX;
1a91de28 1674 mlx4_warn(&priv->dev,
e6b6a231
RE		 1675 "No mac resorces slave %d, port %d\n",
1676 slave, port);
1677 return err;
1678 }
1a91de28 1679 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
e6b6a231
RE		 1680 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1681 }
0eb62b93
RE		 1682 }
1683 return 0;
1684}
1685
3f7fb021
RE		 1686static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1687{
1688 int port;
1689 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1690 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1691 &priv->dev, slave);
1692 int min_port = find_first_bit(actv_ports.ports,
1693 priv->dev.caps.num_ports) + 1;
1694 int max_port = min_port - 1 +
1695 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1696
3f7fb021 1697
449fc488
MB		 1698 for (port = min_port; port <= max_port; port++) {
1699 if (!test_bit(port - 1, actv_ports.ports))
1700 continue;
3f7fb021
RE		 1701 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1702 if (NO_INDX != vp_oper->vlan_idx) {
1703 __mlx4_unregister_vlan(&priv->dev,
2009d005 1704 port, vp_oper->state.default_vlan);
3f7fb021
RE		 1705 vp_oper->vlan_idx = NO_INDX;
1706 }
e6b6a231 1707 if (NO_INDX != vp_oper->mac_idx) {
c32b7dfb 1708 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
e6b6a231
RE		 1709 vp_oper->mac_idx = NO_INDX;
1710 }
3f7fb021
RE		 1711 }
1712 return;
1713}
1714
e8f081aa
YP		 1715static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1716 u16 param, u8 toggle)
1717{
1718 struct mlx4_priv *priv = mlx4_priv(dev);
1719 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1720 u32 reply;
e8f081aa 1721 u8 is_going_down = 0;
803143fb 1722 int i;
311f813a 1723 unsigned long flags;
e8f081aa
YP		 1724
1725 slave_state[slave].comm_toggle ^= 1;
1726 reply = (u32) slave_state[slave].comm_toggle << 31;
1727 if (toggle != slave_state[slave].comm_toggle) {
1a91de28
JP		 1728 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1729 toggle, slave);
e8f081aa
YP		 1730 goto reset_slave;
1731 }
1732 if (cmd == MLX4_COMM_CMD_RESET) {
1733 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1734 slave_state[slave].active = false;
2c957ff2 1735 slave_state[slave].old_vlan_api = false;
3f7fb021 1736 mlx4_master_deactivate_admin_state(priv, slave);
803143fb
MA		 1737 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1738 slave_state[slave].event_eq[i].eqn = -1;
1739 slave_state[slave].event_eq[i].token = 0;
1740 }
e8f081aa
YP		 1741 /*check if we are in the middle of FLR process,
1742 if so return "retry" status to the slave*/
162344ed 1743 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
e8f081aa 1744 goto inform_slave_state;
e8f081aa 1745
fc06573d
JM		 1746 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1747
e8f081aa
YP		 1748 /* write the version in the event field */
1749 reply |= mlx4_comm_get_version();
1750
1751 goto reset_slave;
1752 }
1753 /*command from slave in the middle of FLR*/
1754 if (cmd != MLX4_COMM_CMD_RESET &&
1755 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1a91de28
JP		 1756 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1757 slave, cmd);
e8f081aa
YP		 1758 return;
1759 }
1760
1761 switch (cmd) {
1762 case MLX4_COMM_CMD_VHCR0:
1763 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1764 goto reset_slave;
1765 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1766 priv->mfunc.master.slave_state[slave].cookie = 0;
1767 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1768 break;
1769 case MLX4_COMM_CMD_VHCR1:
1770 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1771 goto reset_slave;
1772 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1773 break;
1774 case MLX4_COMM_CMD_VHCR2:
1775 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1776 goto reset_slave;
1777 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1778 break;
1779 case MLX4_COMM_CMD_VHCR_EN:
1780 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1781 goto reset_slave;
1782 slave_state[slave].vhcr_dma |= param;
3f7fb021
RE		 1783 if (mlx4_master_activate_admin_state(priv, slave))
1784 goto reset_slave;
e8f081aa 1785 slave_state[slave].active = true;
fc06573d 1786 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
e8f081aa
YP		 1787 break;
1788 case MLX4_COMM_CMD_VHCR_POST:
1789 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1790 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1791 goto reset_slave;
f3d4c89e
RD		 1792
1793 mutex_lock(&priv->cmd.slave_cmd_mutex);
e8f081aa 1794 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1a91de28
JP		 1795 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
1796 slave);
f3d4c89e 1797 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1798 goto reset_slave;
1799 }
f3d4c89e 1800 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1801 break;
1802 default:
1803 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1804 goto reset_slave;
1805 }
311f813a 1806 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1807 if (!slave_state[slave].is_slave_going_down)
1808 slave_state[slave].last_cmd = cmd;
1809 else
1810 is_going_down = 1;
311f813a 1811 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa 1812 if (is_going_down) {
1a91de28 1813 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
e8f081aa
YP		 1814 cmd, slave);
1815 return;
1816 }
1817 __raw_writel((__force u32) cpu_to_be32(reply),
1818 &priv->mfunc.comm[slave].slave_read);
1819 mmiowb();
1820
1821 return;
1822
1823reset_slave:
c82e9aa0
EC		 1824 /* cleanup any slave resources */
1825 mlx4_delete_all_resources_for_slave(dev, slave);
311f813a 1826 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1827 if (!slave_state[slave].is_slave_going_down)
1828 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
311f813a 1829 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1830 /*with slave in the middle of flr, no need to clean resources again.*/
1831inform_slave_state:
1832 memset(&slave_state[slave].event_eq, 0,
1833 sizeof(struct mlx4_slave_event_eq_info));
1834 __raw_writel((__force u32) cpu_to_be32(reply),
1835 &priv->mfunc.comm[slave].slave_read);
1836 wmb();
1837}
1838
1839/* master command processing */
1840void mlx4_master_comm_channel(struct work_struct *work)
1841{
1842 struct mlx4_mfunc_master_ctx *master =
1843 container_of(work,
1844 struct mlx4_mfunc_master_ctx,
1845 comm_work);
1846 struct mlx4_mfunc *mfunc =
1847 container_of(master, struct mlx4_mfunc, master);
1848 struct mlx4_priv *priv =
1849 container_of(mfunc, struct mlx4_priv, mfunc);
1850 struct mlx4_dev *dev = &priv->dev;
1851 __be32 *bit_vec;
1852 u32 comm_cmd;
1853 u32 vec;
1854 int i, j, slave;
1855 int toggle;
1856 int served = 0;
1857 int reported = 0;
1858 u32 slt;
1859
1860 bit_vec = master->comm_arm_bit_vector;
1861 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1862 vec = be32_to_cpu(bit_vec[i]);
1863 for (j = 0; j < 32; j++) {
1864 if (!(vec & (1 << j)))
1865 continue;
1866 ++reported;
1867 slave = (i * 32) + j;
1868 comm_cmd = swab32(readl(
1869 &mfunc->comm[slave].slave_write));
1870 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1871 >> 31;
1872 toggle = comm_cmd >> 31;
1873 if (toggle != slt) {
1874 if (master->slave_state[slave].comm_toggle
1875 != slt) {
1a91de28
JP		 1876 printk(KERN_INFO "slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
1877 slave, slt,
e8f081aa
YP		 1878 master->slave_state[slave].comm_toggle);
1879 master->slave_state[slave].comm_toggle =
1880 slt;
1881 }
1882 mlx4_master_do_cmd(dev, slave,
1883 comm_cmd >> 16 & 0xff,
1884 comm_cmd & 0xffff, toggle);
1885 ++served;
1886 }
1887 }
1888 }
1889
1890 if (reported && reported != served)
1a91de28 1891 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
e8f081aa
YP		 1892 reported, served);
1893
1894 if (mlx4_ARM_COMM_CHANNEL(dev))
1895 mlx4_warn(dev, "Failed to arm comm channel events\n");
1896}
1897
ab9c17a0
JM		 1898static int sync_toggles(struct mlx4_dev *dev)
1899{
1900 struct mlx4_priv *priv = mlx4_priv(dev);
1901 int wr_toggle;
1902 int rd_toggle;
1903 unsigned long end;
1904
1905 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1906 end = jiffies + msecs_to_jiffies(5000);
1907
1908 while (time_before(jiffies, end)) {
1909 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1910 if (rd_toggle == wr_toggle) {
1911 priv->cmd.comm_toggle = rd_toggle;
1912 return 0;
1913 }
1914
1915 cond_resched();
1916 }
1917
1918 /*
1919 * we could reach here if for example the previous VM using this
1920 * function misbehaved and left the channel with unsynced state. We
1921 * should fix this here and give this VM a chance to use a properly
1922 * synced channel
1923 */
1924 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1925 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1926 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1927 priv->cmd.comm_toggle = 0;
1928
1929 return 0;
1930}
1931
1932int mlx4_multi_func_init(struct mlx4_dev *dev)
1933{
1934 struct mlx4_priv *priv = mlx4_priv(dev);
1935 struct mlx4_slave_state *s_state;
803143fb 1936 int i, j, err, port;
ab9c17a0 1937
ab9c17a0
JM		 1938 if (mlx4_is_master(dev))
1939 priv->mfunc.comm =
1940 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1941 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1942 else
1943 priv->mfunc.comm =
1944 ioremap(pci_resource_start(dev->pdev, 2) +
1945 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1946 if (!priv->mfunc.comm) {
1a91de28 1947 mlx4_err(dev, "Couldn't map communication vector\n");
ab9c17a0
JM		 1948 goto err_vhcr;
1949 }
1950
1951 if (mlx4_is_master(dev)) {
1952 priv->mfunc.master.slave_state =
1953 kzalloc(dev->num_slaves *
1954 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1955 if (!priv->mfunc.master.slave_state)
1956 goto err_comm;
1957
0eb62b93
RE		 1958 priv->mfunc.master.vf_admin =
1959 kzalloc(dev->num_slaves *
1960 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1961 if (!priv->mfunc.master.vf_admin)
1962 goto err_comm_admin;
1963
1964 priv->mfunc.master.vf_oper =
1965 kzalloc(dev->num_slaves *
1966 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1967 if (!priv->mfunc.master.vf_oper)
1968 goto err_comm_oper;
1969
ab9c17a0
JM		 1970 for (i = 0; i < dev->num_slaves; ++i) {
1971 s_state = &priv->mfunc.master.slave_state[i];
1972 s_state->last_cmd = MLX4_COMM_CMD_RESET;
803143fb
MA		 1973 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1974 s_state->event_eq[j].eqn = -1;
ab9c17a0
JM		 1975 __raw_writel((__force u32) 0,
1976 &priv->mfunc.comm[i].slave_write);
1977 __raw_writel((__force u32) 0,
1978 &priv->mfunc.comm[i].slave_read);
1979 mmiowb();
1980 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1981 s_state->vlan_filter[port] =
1982 kzalloc(sizeof(struct mlx4_vlan_fltr),
1983 GFP_KERNEL);
1984 if (!s_state->vlan_filter[port]) {
1985 if (--port)
1986 kfree(s_state->vlan_filter[port]);
1987 goto err_slaves;
1988 }
1989 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
0eb62b93 1990 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
3f7fb021 1991 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
0eb62b93
RE		 1992 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1993 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
ab9c17a0
JM		 1994 }
1995 spin_lock_init(&s_state->lock);
1996 }
1997
08ff3235 1998 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
ab9c17a0
JM		 1999 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2000 INIT_WORK(&priv->mfunc.master.comm_work,
2001 mlx4_master_comm_channel);
2002 INIT_WORK(&priv->mfunc.master.slave_event_work,
2003 mlx4_gen_slave_eqe);
2004 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2005 mlx4_master_handle_slave_flr);
2006 spin_lock_init(&priv->mfunc.master.slave_state_lock);
992e8e6e 2007 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
ab9c17a0
JM		 2008 priv->mfunc.master.comm_wq =
2009 create_singlethread_workqueue("mlx4_comm");
2010 if (!priv->mfunc.master.comm_wq)
2011 goto err_slaves;
2012
2013 if (mlx4_init_resource_tracker(dev))
2014 goto err_thread;
2015
ab9c17a0
JM		 2016 err = mlx4_ARM_COMM_CHANNEL(dev);
2017 if (err) {
2018 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2019 err);
2020 goto err_resource;
2021 }
2022
2023 } else {
2024 err = sync_toggles(dev);
2025 if (err) {
2026 mlx4_err(dev, "Couldn't sync toggles\n");
2027 goto err_comm;
2028 }
ab9c17a0
JM		 2029 }
2030 return 0;
2031
2032err_resource:
b8924951 2033 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
ab9c17a0
JM		 2034err_thread:
2035 flush_workqueue(priv->mfunc.master.comm_wq);
2036 destroy_workqueue(priv->mfunc.master.comm_wq);
2037err_slaves:
2038 while (--i) {
2039 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2040 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2041 }
0eb62b93
RE		 2042 kfree(priv->mfunc.master.vf_oper);
2043err_comm_oper:
2044 kfree(priv->mfunc.master.vf_admin);
2045err_comm_admin:
ab9c17a0
JM		 2046 kfree(priv->mfunc.master.slave_state);
2047err_comm:
2048 iounmap(priv->mfunc.comm);
2049err_vhcr:
2050 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2051 priv->mfunc.vhcr,
2052 priv->mfunc.vhcr_dma);
2053 priv->mfunc.vhcr = NULL;
2054 return -ENOMEM;
2055}
2056
225c7b1f
RD		 2057int mlx4_cmd_init(struct mlx4_dev *dev)
2058{
2059 struct mlx4_priv *priv = mlx4_priv(dev);
2060
2061 mutex_init(&priv->cmd.hcr_mutex);
f3d4c89e 2062 mutex_init(&priv->cmd.slave_cmd_mutex);
225c7b1f
RD		 2063 sema_init(&priv->cmd.poll_sem, 1);
2064 priv->cmd.use_events = 0;
2065 priv->cmd.toggle = 1;
2066
e8f081aa
YP		 2067 priv->cmd.hcr = NULL;
2068 priv->mfunc.vhcr = NULL;
2069
2070 if (!mlx4_is_slave(dev)) {
2071 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2072 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2073 if (!priv->cmd.hcr) {
1a91de28 2074 mlx4_err(dev, "Couldn't map command register\n");
e8f081aa
YP		 2075 return -ENOMEM;
2076 }
225c7b1f
RD		 2077 }
2078
f3d4c89e
RD		 2079 if (mlx4_is_mfunc(dev)) {
2080 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2081 &priv->mfunc.vhcr_dma,
2082 GFP_KERNEL);
d0320f75 2083 if (!priv->mfunc.vhcr)
f3d4c89e 2084 goto err_hcr;
f3d4c89e
RD		 2085 }
2086
225c7b1f
RD		 2087 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2088 MLX4_MAILBOX_SIZE,
2089 MLX4_MAILBOX_SIZE, 0);
e8f081aa 2090 if (!priv->cmd.pool)
f3d4c89e 2091 goto err_vhcr;
225c7b1f
RD		 2092
2093 return 0;
e8f081aa 2094
f3d4c89e
RD		 2095err_vhcr:
2096 if (mlx4_is_mfunc(dev))
2097 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2098 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2099 priv->mfunc.vhcr = NULL;
2100
e8f081aa
YP		 2101err_hcr:
2102 if (!mlx4_is_slave(dev))
2103 iounmap(priv->cmd.hcr);
2104 return -ENOMEM;
225c7b1f
RD		 2105}
2106
ab9c17a0
JM		 2107void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2108{
2109 struct mlx4_priv *priv = mlx4_priv(dev);
2110 int i, port;
2111
2112 if (mlx4_is_master(dev)) {
2113 flush_workqueue(priv->mfunc.master.comm_wq);
2114 destroy_workqueue(priv->mfunc.master.comm_wq);
2115 for (i = 0; i < dev->num_slaves; i++) {
2116 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2117 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2118 }
2119 kfree(priv->mfunc.master.slave_state);
0eb62b93
RE		 2120 kfree(priv->mfunc.master.vf_admin);
2121 kfree(priv->mfunc.master.vf_oper);
ab9c17a0 2122 }
f08ad06c
EE		 2123
2124 iounmap(priv->mfunc.comm);
ab9c17a0
JM		 2125}
2126
225c7b1f
RD		 2127void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2128{
2129 struct mlx4_priv *priv = mlx4_priv(dev);
2130
2131 pci_pool_destroy(priv->cmd.pool);
e8f081aa
YP		 2132
2133 if (!mlx4_is_slave(dev))
2134 iounmap(priv->cmd.hcr);
f3d4c89e
RD		 2135 if (mlx4_is_mfunc(dev))
2136 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2137 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2138 priv->mfunc.vhcr = NULL;
225c7b1f
RD		 2139}
2140
2141/*
2142 * Switch to using events to issue FW commands (can only be called
2143 * after event queue for command events has been initialized).
2144 */
2145int mlx4_cmd_use_events(struct mlx4_dev *dev)
2146{
2147 struct mlx4_priv *priv = mlx4_priv(dev);
2148 int i;
e8f081aa 2149 int err = 0;
225c7b1f
RD		 2150
2151 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2152 sizeof (struct mlx4_cmd_context),
2153 GFP_KERNEL);
2154 if (!priv->cmd.context)
2155 return -ENOMEM;
2156
2157 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2158 priv->cmd.context[i].token = i;
2159 priv->cmd.context[i].next = i + 1;
2160 }
2161
2162 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2163 priv->cmd.free_head = 0;
2164
2165 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2166 spin_lock_init(&priv->cmd.context_lock);
2167
2168 for (priv->cmd.token_mask = 1;
2169 priv->cmd.token_mask < priv->cmd.max_cmds;
2170 priv->cmd.token_mask <<= 1)
2171 ; /* nothing */
2172 --priv->cmd.token_mask;
2173
225c7b1f 2174 down(&priv->cmd.poll_sem);
e8f081aa 2175 priv->cmd.use_events = 1;
225c7b1f 2176
e8f081aa 2177 return err;
225c7b1f
RD		 2178}
2179
2180/*
2181 * Switch back to polling (used when shutting down the device)
2182 */
2183void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2184{
2185 struct mlx4_priv *priv = mlx4_priv(dev);
2186 int i;
2187
2188 priv->cmd.use_events = 0;
2189
2190 for (i = 0; i < priv->cmd.max_cmds; ++i)
2191 down(&priv->cmd.event_sem);
2192
2193 kfree(priv->cmd.context);
2194
2195 up(&priv->cmd.poll_sem);
2196}
2197
2198struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2199{
2200 struct mlx4_cmd_mailbox *mailbox;
2201
2202 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2203 if (!mailbox)
2204 return ERR_PTR(-ENOMEM);
2205
2206 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2207 &mailbox->dma);
2208 if (!mailbox->buf) {
2209 kfree(mailbox);
2210 return ERR_PTR(-ENOMEM);
2211 }
2212
571b8b92
JM		 2213 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2214
225c7b1f
RD		 2215 return mailbox;
2216}
2217EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2218
e8f081aa
YP		 2219void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2220 struct mlx4_cmd_mailbox *mailbox)
225c7b1f
RD		 2221{
2222 if (!mailbox)
2223 return;
2224
2225 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2226 kfree(mailbox);
2227}
2228EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
e8f081aa
YP		 2229
2230u32 mlx4_comm_get_version(void)
2231{
2232 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2233}
8f7ba3ca
RE		 2234
2235static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2236{
2237 if ((vf < 0) || (vf >= dev->num_vfs)) {
2238 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2239 return -EINVAL;
2240 }
2241
2242 return vf+1;
2243}
2244
f74462ac
MB		 2245int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2246{
2247 if (slave < 1 || slave > dev->num_vfs) {
2248 mlx4_err(dev,
2249 "Bad slave number:%d (number of activated slaves: %lu)\n",
2250 slave, dev->num_slaves);
2251 return -EINVAL;
2252 }
2253 return slave - 1;
2254}
2255
2256struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2257{
2258 struct mlx4_active_ports actv_ports;
2259 int vf;
2260
2261 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2262
2263 if (slave == 0) {
2264 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2265 return actv_ports;
2266 }
2267
2268 vf = mlx4_get_vf_indx(dev, slave);
2269 if (vf < 0)
2270 return actv_ports;
2271
2272 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2273 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2274 dev->caps.num_ports));
2275
2276 return actv_ports;
2277}
2278EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2279
2280int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2281{
2282 unsigned n;
2283 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2284 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2285
2286 if (port <= 0 || port > m)
2287 return -EINVAL;
2288
2289 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2290 if (port <= n)
2291 port = n + 1;
2292
2293 return port;
2294}
2295EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2296
2297int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2298{
2299 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2300 if (test_bit(port - 1, actv_ports.ports))
2301 return port -
2302 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2303
2304 return -1;
2305}
2306EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2307
2308struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2309 int port)
2310{
2311 unsigned i;
2312 struct mlx4_slaves_pport slaves_pport;
2313
2314 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2315
2316 if (port <= 0 || port > dev->caps.num_ports)
2317 return slaves_pport;
2318
2319 for (i = 0; i < dev->num_vfs + 1; i++) {
2320 struct mlx4_active_ports actv_ports =
2321 mlx4_get_active_ports(dev, i);
2322 if (test_bit(port - 1, actv_ports.ports))
2323 set_bit(i, slaves_pport.slaves);
2324 }
2325
2326 return slaves_pport;
2327}
2328EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2329
2330struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2331 struct mlx4_dev *dev,
2332 const struct mlx4_active_ports *crit_ports)
2333{
2334 unsigned i;
2335 struct mlx4_slaves_pport slaves_pport;
2336
2337 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2338
2339 for (i = 0; i < dev->num_vfs + 1; i++) {
2340 struct mlx4_active_ports actv_ports =
2341 mlx4_get_active_ports(dev, i);
2342 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2343 dev->caps.num_ports))
2344 set_bit(i, slaves_pport.slaves);
2345 }
2346
2347 return slaves_pport;
2348}
2349EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2350
8f7ba3ca
RE		 2351int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2352{
2353 struct mlx4_priv *priv = mlx4_priv(dev);
2354 struct mlx4_vport_state *s_info;
2355 int slave;
2356
2357 if (!mlx4_is_master(dev))
2358 return -EPROTONOSUPPORT;
2359
2360 slave = mlx4_get_slave_indx(dev, vf);
2361 if (slave < 0)
2362 return -EINVAL;
2363
2364 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2365 s_info->mac = mac;
2366 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2367 vf, port, s_info->mac);
2368 return 0;
2369}
2370EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3f7fb021 2371
b01978ca 2372
3f7fb021
RE		 2373int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2374{
2375 struct mlx4_priv *priv = mlx4_priv(dev);
b01978ca 2376 struct mlx4_vport_state *vf_admin;
3f7fb021
RE		 2377 int slave;
2378
2379 if ((!mlx4_is_master(dev)) ||
2380 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2381 return -EPROTONOSUPPORT;
2382
2383 if ((vlan > 4095) || (qos > 7))
2384 return -EINVAL;
2385
2386 slave = mlx4_get_slave_indx(dev, vf);
2387 if (slave < 0)
2388 return -EINVAL;
2389
b01978ca 2390 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
b01978ca 2391
3f7fb021 2392 if ((0 == vlan) && (0 == qos))
b01978ca 2393 vf_admin->default_vlan = MLX4_VGT;
3f7fb021 2394 else
b01978ca
JM		 2395 vf_admin->default_vlan = vlan;
2396 vf_admin->default_qos = qos;
2397
0a6eac24
RE		 2398 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2399 mlx4_info(dev,
2400 "updating vf %d port %d config will take effect on next VF restart\n",
b01978ca 2401 vf, port);
3f7fb021
RE		 2402 return 0;
2403}
2404EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
e6b6a231 2405
5ea8bbfc
JM		 2406 /* mlx4_get_slave_default_vlan -
2407 * return true if VST ( default vlan)
2408 * if VST, will return vlan & qos (if not NULL)
2409 */
2410bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2411 u16 *vlan, u8 *qos)
2412{
2413 struct mlx4_vport_oper_state *vp_oper;
2414 struct mlx4_priv *priv;
2415
2416 priv = mlx4_priv(dev);
2417 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2418
2419 if (MLX4_VGT != vp_oper->state.default_vlan) {
2420 if (vlan)
2421 *vlan = vp_oper->state.default_vlan;
2422 if (qos)
2423 *qos = vp_oper->state.default_qos;
2424 return true;
2425 }
2426 return false;
2427}
2428EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2429
e6b6a231
RE		 2430int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2431{
2432 struct mlx4_priv *priv = mlx4_priv(dev);
2433 struct mlx4_vport_state *s_info;
2434 int slave;
2435
2436 if ((!mlx4_is_master(dev)) ||
2437 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2438 return -EPROTONOSUPPORT;
2439
2440 slave = mlx4_get_slave_indx(dev, vf);
2441 if (slave < 0)
2442 return -EINVAL;
2443
2444 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2445 s_info->spoofchk = setting;
2446
2447 return 0;
2448}
2449EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2cccb9e4
RE		 2450
2451int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2452{
2453 struct mlx4_priv *priv = mlx4_priv(dev);
2454 struct mlx4_vport_state *s_info;
2455 int slave;
2456
2457 if (!mlx4_is_master(dev))
2458 return -EPROTONOSUPPORT;
2459
2460 slave = mlx4_get_slave_indx(dev, vf);
2461 if (slave < 0)
2462 return -EINVAL;
2463
2464 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2465 ivf->vf = vf;
2466
2467 /* need to convert it to a func */
2468 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2469 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2470 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2471 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2472 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2473 ivf->mac[5] = ((s_info->mac) & 0xff);
2474
2475 ivf->vlan = s_info->default_vlan;
2476 ivf->qos = s_info->default_qos;
2477 ivf->tx_rate = s_info->tx_rate;
2478 ivf->spoofchk = s_info->spoofchk;
948e306d 2479 ivf->linkstate = s_info->link_state;
2cccb9e4
RE		 2480
2481 return 0;
2482}
2483EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
948e306d
RE		 2484
2485int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2486{
2487 struct mlx4_priv *priv = mlx4_priv(dev);
2488 struct mlx4_vport_state *s_info;
948e306d
RE		 2489 int slave;
2490 u8 link_stat_event;
2491
2492 slave = mlx4_get_slave_indx(dev, vf);
2493 if (slave < 0)
2494 return -EINVAL;
2495
2496 switch (link_state) {
2497 case IFLA_VF_LINK_STATE_AUTO:
2498 /* get current link state */
2499 if (!priv->sense.do_sense_port[port])
2500 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2501 else
2502 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2503 break;
2504
2505 case IFLA_VF_LINK_STATE_ENABLE:
2506 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2507 break;
2508
2509 case IFLA_VF_LINK_STATE_DISABLE:
2510 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2511 break;
2512
2513 default:
2514 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2515 link_state, slave, port);
2516 return -EINVAL;
2517 };
948e306d 2518 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
948e306d 2519 s_info->link_state = link_state;
948e306d
RE		 2520
2521 /* send event */
2522 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
0a6eac24
RE		 2523
2524 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2525 mlx4_dbg(dev,
2526 "updating vf %d port %d no link state HW enforcment\n",
2527 vf, port);
948e306d
RE		 2528 return 0;
2529}
2530EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
Linux 6.x block layer and io_uring tree(s)