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Merge branch 'fixes-for-3.12' of git://gitorious.org/linux-can/linux-can
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/sched.h>
5a0e3ad6 36#include <linux/slab.h>
ee40fa06 37#include <linux/export.h>
225c7b1f
RD		 38#include <linux/pci.h>
39#include <linux/errno.h>
40
41#include <linux/mlx4/cmd.h>
948e306d 42#include <linux/mlx4/device.h>
e8f081aa 43#include <linux/semaphore.h>
0a9a0188 44#include <rdma/ib_smi.h>
225c7b1f
RD		 45
46#include <asm/io.h>
47
48#include "mlx4.h"
e8f081aa 49#include "fw.h"
225c7b1f
RD		 50
51#define CMD_POLL_TOKEN 0xffff
e8f081aa
YP		 52#define INBOX_MASK 0xffffffffffffff00ULL
53
54#define CMD_CHAN_VER 1
55#define CMD_CHAN_IF_REV 1
225c7b1f
RD		 56
57enum {
58 /* command completed successfully: */
59 CMD_STAT_OK = 0x00,
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
899698da
JM		 80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
225c7b1f
RD		 82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
cc4ac2e7
YP		 93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
225c7b1f
RD		 96};
97
98enum {
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
104
105 HCR_OPMOD_SHIFT = 12,
106 HCR_T_BIT = 21,
107 HCR_E_BIT = 22,
108 HCR_GO_BIT = 23
109};
110
111enum {
36ce10d3 112 GO_BIT_TIMEOUT_MSECS = 10000
225c7b1f
RD		 113};
114
b01978ca
JM		 115enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
120};
121
122
225c7b1f
RD		 123struct mlx4_cmd_context {
124 struct completion done;
125 int result;
126 int next;
127 u64 out_param;
128 u16 token;
e8f081aa 129 u8 fw_status;
225c7b1f
RD		 130};
131
e8f081aa
YP		 132static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
134
ca281211
RD		 135static int mlx4_status_to_errno(u8 status)
136{
225c7b1f
RD		 137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
899698da 148 [CMD_STAT_ICM_ERROR] = -ENFILE,
225c7b1f
RD		 149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
cc4ac2e7 155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
225c7b1f
RD		 156 };
157
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
160 return -EIO;
161
162 return trans_table[status];
163}
164
72be84f1
YP		 165static u8 mlx4_errno_to_status(int errno)
166{
167 switch (errno) {
168 case -EPERM:
169 return CMD_STAT_BAD_OP;
170 case -EINVAL:
171 return CMD_STAT_BAD_PARAM;
172 case -ENXIO:
173 return CMD_STAT_BAD_SYS_STATE;
174 case -EBUSY:
175 return CMD_STAT_RESOURCE_BUSY;
176 case -ENOMEM:
177 return CMD_STAT_EXCEED_LIM;
178 case -ENFILE:
179 return CMD_STAT_ICM_ERROR;
180 default:
181 return CMD_STAT_INTERNAL_ERR;
182 }
183}
184
e8f081aa
YP		 185static int comm_pending(struct mlx4_dev *dev)
186{
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
189
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
191}
192
193static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
194{
195 struct mlx4_priv *priv = mlx4_priv(dev);
196 u32 val;
197
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
202 mmiowb();
203}
204
e8f081aa
YP		 205static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
207{
208 struct mlx4_priv *priv = mlx4_priv(dev);
209 unsigned long end;
210 int err = 0;
211 int ret_from_pending = 0;
212
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
215 mlx4_warn(dev, "Communication channel is not idle."
216 "my toggle is %d (cmd:0x%x)\n",
217 priv->cmd.comm_toggle, cmd);
218 return -EAGAIN;
219 }
220
221 /* Write command */
222 down(&priv->cmd.poll_sem);
223 mlx4_comm_cmd_post(dev, cmd, param);
224
225 end = msecs_to_jiffies(timeout) + jiffies;
226 while (comm_pending(dev) && time_before(jiffies, end))
227 cond_resched();
228 ret_from_pending = comm_pending(dev);
229 if (ret_from_pending) {
230 /* check if the slave is trying to boot in the middle of
231 * FLR process. The only non-zero result in the RESET command
232 * is MLX4_DELAY_RESET_SLAVE*/
233 if ((MLX4_COMM_CMD_RESET == cmd)) {
e8f081aa
YP		 234 err = MLX4_DELAY_RESET_SLAVE;
235 } else {
236 mlx4_warn(dev, "Communication channel timed out\n");
237 err = -ETIMEDOUT;
238 }
239 }
240
241 up(&priv->cmd.poll_sem);
242 return err;
243}
244
245static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
246 u16 param, unsigned long timeout)
247{
248 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
249 struct mlx4_cmd_context *context;
58a3de05 250 unsigned long end;
e8f081aa
YP		 251 int err = 0;
252
253 down(&cmd->event_sem);
254
255 spin_lock(&cmd->context_lock);
256 BUG_ON(cmd->free_head < 0);
257 context = &cmd->context[cmd->free_head];
258 context->token += cmd->token_mask + 1;
259 cmd->free_head = context->next;
260 spin_unlock(&cmd->context_lock);
261
262 init_completion(&context->done);
263
264 mlx4_comm_cmd_post(dev, op, param);
265
266 if (!wait_for_completion_timeout(&context->done,
267 msecs_to_jiffies(timeout))) {
674925ed
DB		 268 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
269 op);
e8f081aa
YP		 270 err = -EBUSY;
271 goto out;
272 }
273
274 err = context->result;
275 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
276 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
277 op, context->fw_status);
278 goto out;
279 }
280
281out:
58a3de05
EE		 282 /* wait for comm channel ready
283 * this is necessary for prevention the race
284 * when switching between event to polling mode
285 */
286 end = msecs_to_jiffies(timeout) + jiffies;
287 while (comm_pending(dev) && time_before(jiffies, end))
288 cond_resched();
289
e8f081aa
YP		 290 spin_lock(&cmd->context_lock);
291 context->next = cmd->free_head;
292 cmd->free_head = context - cmd->context;
293 spin_unlock(&cmd->context_lock);
294
295 up(&cmd->event_sem);
296 return err;
297}
298
ab9c17a0 299int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
e8f081aa
YP		 300 unsigned long timeout)
301{
302 if (mlx4_priv(dev)->cmd.use_events)
303 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
304 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
305}
306
225c7b1f
RD		 307static int cmd_pending(struct mlx4_dev *dev)
308{
57dbf29a
KSS		 309 u32 status;
310
311 if (pci_channel_offline(dev->pdev))
312 return -EIO;
313
314 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
225c7b1f
RD		 315
316 return (status & swab32(1 << HCR_GO_BIT)) ||
317 (mlx4_priv(dev)->cmd.toggle ==
318 !!(status & swab32(1 << HCR_T_BIT)));
319}
320
321static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
322 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
323 int event)
324{
325 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
326 u32 __iomem *hcr = cmd->hcr;
327 int ret = -EAGAIN;
328 unsigned long end;
329
330 mutex_lock(&cmd->hcr_mutex);
331
57dbf29a
KSS		 332 if (pci_channel_offline(dev->pdev)) {
333 /*
334 * Device is going through error recovery
335 * and cannot accept commands.
336 */
337 ret = -EIO;
338 goto out;
339 }
340
225c7b1f
RD		 341 end = jiffies;
342 if (event)
36ce10d3 343 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
225c7b1f
RD		 344
345 while (cmd_pending(dev)) {
57dbf29a
KSS		 346 if (pci_channel_offline(dev->pdev)) {
347 /*
348 * Device is going through error recovery
349 * and cannot accept commands.
350 */
351 ret = -EIO;
352 goto out;
353 }
354
e8f081aa
YP		 355 if (time_after_eq(jiffies, end)) {
356 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
225c7b1f 357 goto out;
e8f081aa 358 }
225c7b1f
RD		 359 cond_resched();
360 }
361
362 /*
363 * We use writel (instead of something like memcpy_toio)
364 * because writes of less than 32 bits to the HCR don't work
365 * (and some architectures such as ia64 implement memcpy_toio
366 * in terms of writeb).
367 */
368 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
369 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
370 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
371 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
372 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
373 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
374
375 /* __raw_writel may not order writes. */
376 wmb();
377
378 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
379 (cmd->toggle << HCR_T_BIT) |
380 (event ? (1 << HCR_E_BIT) : 0) |
381 (op_modifier << HCR_OPMOD_SHIFT) |
e8f081aa 382 op), hcr + 6);
2e61c646
RD		 383
384 /*
385 * Make sure that our HCR writes don't get mixed in with
386 * writes from another CPU starting a FW command.
387 */
388 mmiowb();
389
225c7b1f
RD		 390 cmd->toggle = cmd->toggle ^ 1;
391
392 ret = 0;
393
394out:
395 mutex_unlock(&cmd->hcr_mutex);
396 return ret;
397}
398
e8f081aa
YP		 399static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
400 int out_is_imm, u32 in_modifier, u8 op_modifier,
401 u16 op, unsigned long timeout)
402{
403 struct mlx4_priv *priv = mlx4_priv(dev);
404 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
405 int ret;
406
f3d4c89e
RD		 407 mutex_lock(&priv->cmd.slave_cmd_mutex);
408
e8f081aa
YP		 409 vhcr->in_param = cpu_to_be64(in_param);
410 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
411 vhcr->in_modifier = cpu_to_be32(in_modifier);
412 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
413 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
414 vhcr->status = 0;
415 vhcr->flags = !!(priv->cmd.use_events) << 6;
f3d4c89e 416
e8f081aa
YP		 417 if (mlx4_is_master(dev)) {
418 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
419 if (!ret) {
420 if (out_is_imm) {
421 if (out_param)
422 *out_param =
423 be64_to_cpu(vhcr->out_param);
424 else {
425 mlx4_err(dev, "response expected while"
426 "output mailbox is NULL for "
427 "command 0x%x\n", op);
72be84f1 428 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 429 }
430 }
72be84f1 431 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa
YP		 432 }
433 } else {
434 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
435 MLX4_COMM_TIME + timeout);
436 if (!ret) {
437 if (out_is_imm) {
438 if (out_param)
439 *out_param =
440 be64_to_cpu(vhcr->out_param);
441 else {
442 mlx4_err(dev, "response expected while"
443 "output mailbox is NULL for "
444 "command 0x%x\n", op);
72be84f1 445 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 446 }
447 }
72be84f1 448 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa
YP		 449 } else
450 mlx4_err(dev, "failed execution of VHCR_POST command"
451 "opcode 0x%x\n", op);
452 }
f3d4c89e
RD		 453
454 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 455 return ret;
456}
457
225c7b1f
RD		 458static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
459 int out_is_imm, u32 in_modifier, u8 op_modifier,
460 u16 op, unsigned long timeout)
461{
462 struct mlx4_priv *priv = mlx4_priv(dev);
463 void __iomem *hcr = priv->cmd.hcr;
464 int err = 0;
465 unsigned long end;
e8f081aa 466 u32 stat;
225c7b1f
RD		 467
468 down(&priv->cmd.poll_sem);
469
57dbf29a
KSS		 470 if (pci_channel_offline(dev->pdev)) {
471 /*
472 * Device is going through error recovery
473 * and cannot accept commands.
474 */
475 err = -EIO;
476 goto out;
477 }
478
225c7b1f
RD		 479 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
480 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
481 if (err)
482 goto out;
483
484 end = msecs_to_jiffies(timeout) + jiffies;
57dbf29a
KSS		 485 while (cmd_pending(dev) && time_before(jiffies, end)) {
486 if (pci_channel_offline(dev->pdev)) {
487 /*
488 * Device is going through error recovery
489 * and cannot accept commands.
490 */
491 err = -EIO;
492 goto out;
493 }
494
225c7b1f 495 cond_resched();
57dbf29a 496 }
225c7b1f
RD		 497
498 if (cmd_pending(dev)) {
674925ed
DB		 499 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
500 op);
225c7b1f
RD		 501 err = -ETIMEDOUT;
502 goto out;
503 }
504
505 if (out_is_imm)
506 *out_param =
507 (u64) be32_to_cpu((__force __be32)
508 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
509 (u64) be32_to_cpu((__force __be32)
510 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
e8f081aa
YP		 511 stat = be32_to_cpu((__force __be32)
512 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
513 err = mlx4_status_to_errno(stat);
514 if (err)
515 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
516 op, stat);
225c7b1f
RD		 517
518out:
519 up(&priv->cmd.poll_sem);
520 return err;
521}
522
523void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
524{
525 struct mlx4_priv *priv = mlx4_priv(dev);
526 struct mlx4_cmd_context *context =
527 &priv->cmd.context[token & priv->cmd.token_mask];
528
529 /* previously timed out command completing at long last */
530 if (token != context->token)
531 return;
532
e8f081aa 533 context->fw_status = status;
225c7b1f
RD		 534 context->result = mlx4_status_to_errno(status);
535 context->out_param = out_param;
536
225c7b1f
RD		 537 complete(&context->done);
538}
539
540static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
541 int out_is_imm, u32 in_modifier, u8 op_modifier,
542 u16 op, unsigned long timeout)
543{
544 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
545 struct mlx4_cmd_context *context;
546 int err = 0;
547
548 down(&cmd->event_sem);
549
550 spin_lock(&cmd->context_lock);
551 BUG_ON(cmd->free_head < 0);
552 context = &cmd->context[cmd->free_head];
0981582d 553 context->token += cmd->token_mask + 1;
225c7b1f
RD		 554 cmd->free_head = context->next;
555 spin_unlock(&cmd->context_lock);
556
557 init_completion(&context->done);
558
559 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
560 in_modifier, op_modifier, op, context->token, 1);
561
e8f081aa
YP		 562 if (!wait_for_completion_timeout(&context->done,
563 msecs_to_jiffies(timeout))) {
674925ed
DB		 564 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
565 op);
225c7b1f
RD		 566 err = -EBUSY;
567 goto out;
568 }
569
570 err = context->result;
e8f081aa
YP		 571 if (err) {
572 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
573 op, context->fw_status);
225c7b1f 574 goto out;
e8f081aa 575 }
225c7b1f
RD		 576
577 if (out_is_imm)
578 *out_param = context->out_param;
579
580out:
581 spin_lock(&cmd->context_lock);
582 context->next = cmd->free_head;
583 cmd->free_head = context - cmd->context;
584 spin_unlock(&cmd->context_lock);
585
586 up(&cmd->event_sem);
587 return err;
588}
589
590int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
591 int out_is_imm, u32 in_modifier, u8 op_modifier,
f9baff50 592 u16 op, unsigned long timeout, int native)
225c7b1f 593{
57dbf29a
KSS		 594 if (pci_channel_offline(dev->pdev))
595 return -EIO;
596
e8f081aa
YP		 597 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
598 if (mlx4_priv(dev)->cmd.use_events)
599 return mlx4_cmd_wait(dev, in_param, out_param,
600 out_is_imm, in_modifier,
601 op_modifier, op, timeout);
602 else
603 return mlx4_cmd_poll(dev, in_param, out_param,
604 out_is_imm, in_modifier,
605 op_modifier, op, timeout);
606 }
607 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
608 in_modifier, op_modifier, op, timeout);
225c7b1f
RD		 609}
610EXPORT_SYMBOL_GPL(__mlx4_cmd);
611
e8f081aa
YP		 612
613static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
614{
615 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
616 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
617}
618
619static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
620 int slave, u64 slave_addr,
621 int size, int is_read)
622{
623 u64 in_param;
624 u64 out_param;
625
626 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
627 (slave & ~0x7f) | (size & 0xff)) {
628 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
629 "master_addr:0x%llx slave_id:%d size:%d\n",
630 slave_addr, master_addr, slave, size);
631 return -EINVAL;
632 }
633
634 if (is_read) {
635 in_param = (u64) slave | slave_addr;
636 out_param = (u64) dev->caps.function | master_addr;
637 } else {
638 in_param = (u64) dev->caps.function | master_addr;
639 out_param = (u64) slave | slave_addr;
640 }
641
642 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
643 MLX4_CMD_ACCESS_MEM,
644 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
645}
646
0a9a0188
JM		 647static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
648 struct mlx4_cmd_mailbox *inbox,
649 struct mlx4_cmd_mailbox *outbox)
650{
651 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
652 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
653 int err;
654 int i;
655
656 if (index & 0x1f)
657 return -EINVAL;
658
659 in_mad->attr_mod = cpu_to_be32(index / 32);
660
661 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
662 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
663 MLX4_CMD_NATIVE);
664 if (err)
665 return err;
666
667 for (i = 0; i < 32; ++i)
668 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
669
670 return err;
671}
672
673static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
674 struct mlx4_cmd_mailbox *inbox,
675 struct mlx4_cmd_mailbox *outbox)
676{
677 int i;
678 int err;
679
680 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
681 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
682 if (err)
683 return err;
684 }
685
686 return 0;
687}
688#define PORT_CAPABILITY_LOCATION_IN_SMP 20
689#define PORT_STATE_OFFSET 32
690
691static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
692{
a0c64a17
JM		 693 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
694 return IB_PORT_ACTIVE;
695 else
696 return IB_PORT_DOWN;
0a9a0188
JM		 697}
698
699static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
700 struct mlx4_vhcr *vhcr,
701 struct mlx4_cmd_mailbox *inbox,
702 struct mlx4_cmd_mailbox *outbox,
703 struct mlx4_cmd_info *cmd)
704{
705 struct ib_smp *smp = inbox->buf;
706 u32 index;
707 u8 port;
708 u16 *table;
709 int err;
710 int vidx, pidx;
711 struct mlx4_priv *priv = mlx4_priv(dev);
712 struct ib_smp *outsmp = outbox->buf;
713 __be16 *outtab = (__be16 *)(outsmp->data);
714 __be32 slave_cap_mask;
afa8fd1d 715 __be64 slave_node_guid;
0a9a0188
JM		 716 port = vhcr->in_modifier;
717
718 if (smp->base_version == 1 &&
719 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
720 smp->class_version == 1) {
721 if (smp->method == IB_MGMT_METHOD_GET) {
722 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
723 index = be32_to_cpu(smp->attr_mod);
724 if (port < 1 || port > dev->caps.num_ports)
725 return -EINVAL;
726 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
727 if (!table)
728 return -ENOMEM;
729 /* need to get the full pkey table because the paravirtualized
730 * pkeys may be scattered among several pkey blocks.
731 */
732 err = get_full_pkey_table(dev, port, table, inbox, outbox);
733 if (!err) {
734 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
735 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
736 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
737 }
738 }
739 kfree(table);
740 return err;
741 }
742 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
743 /*get the slave specific caps:*/
744 /*do the command */
745 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
746 vhcr->in_modifier, vhcr->op_modifier,
747 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
748 /* modify the response for slaves */
749 if (!err && slave != mlx4_master_func_num(dev)) {
750 u8 *state = outsmp->data + PORT_STATE_OFFSET;
751
752 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
753 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
754 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
755 }
756 return err;
757 }
758 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
759 /* compute slave's gid block */
760 smp->attr_mod = cpu_to_be32(slave / 8);
761 /* execute cmd */
762 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
763 vhcr->in_modifier, vhcr->op_modifier,
764 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
765 if (!err) {
766 /* if needed, move slave gid to index 0 */
767 if (slave % 8)
768 memcpy(outsmp->data,
769 outsmp->data + (slave % 8) * 8, 8);
770 /* delete all other gids */
771 memset(outsmp->data + 8, 0, 56);
772 }
773 return err;
774 }
afa8fd1d
JM		 775 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
776 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
777 vhcr->in_modifier, vhcr->op_modifier,
778 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
779 if (!err) {
780 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
781 memcpy(outsmp->data + 12, &slave_node_guid, 8);
782 }
783 return err;
784 }
0a9a0188
JM		 785 }
786 }
787 if (slave != mlx4_master_func_num(dev) &&
788 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
789 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
790 smp->method == IB_MGMT_METHOD_SET))) {
791 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
792 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
793 slave, smp->method, smp->mgmt_class,
794 be16_to_cpu(smp->attr_id));
795 return -EPERM;
796 }
797 /*default:*/
798 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
799 vhcr->in_modifier, vhcr->op_modifier,
800 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
801}
802
f094668c 803static int MLX4_CMD_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
b01978ca
JM		 804 struct mlx4_vhcr *vhcr,
805 struct mlx4_cmd_mailbox *inbox,
806 struct mlx4_cmd_mailbox *outbox,
807 struct mlx4_cmd_info *cmd)
808{
809 return -EPERM;
810}
811
f094668c 812static int MLX4_CMD_GET_OP_REQ_wrapper(struct mlx4_dev *dev, int slave,
fe6f700d
YP		 813 struct mlx4_vhcr *vhcr,
814 struct mlx4_cmd_mailbox *inbox,
815 struct mlx4_cmd_mailbox *outbox,
816 struct mlx4_cmd_info *cmd)
817{
818 return -EPERM;
819}
820
e8f081aa
YP		 821int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
822 struct mlx4_vhcr *vhcr,
823 struct mlx4_cmd_mailbox *inbox,
824 struct mlx4_cmd_mailbox *outbox,
825 struct mlx4_cmd_info *cmd)
826{
827 u64 in_param;
828 u64 out_param;
829 int err;
830
831 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
832 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
833 if (cmd->encode_slave_id) {
834 in_param &= 0xffffffffffffff00ll;
835 in_param |= slave;
836 }
837
838 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
839 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
840 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
841
842 if (cmd->out_is_imm)
843 vhcr->out_param = out_param;
844
845 return err;
846}
847
848static struct mlx4_cmd_info cmd_info[] = {
849 {
850 .opcode = MLX4_CMD_QUERY_FW,
851 .has_inbox = false,
852 .has_outbox = true,
853 .out_is_imm = false,
854 .encode_slave_id = false,
855 .verify = NULL,
b91cb3eb 856 .wrapper = mlx4_QUERY_FW_wrapper
e8f081aa
YP		 857 },
858 {
859 .opcode = MLX4_CMD_QUERY_HCA,
860 .has_inbox = false,
861 .has_outbox = true,
862 .out_is_imm = false,
863 .encode_slave_id = false,
864 .verify = NULL,
865 .wrapper = NULL
866 },
867 {
868 .opcode = MLX4_CMD_QUERY_DEV_CAP,
869 .has_inbox = false,
870 .has_outbox = true,
871 .out_is_imm = false,
872 .encode_slave_id = false,
873 .verify = NULL,
b91cb3eb 874 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
e8f081aa 875 },
c82e9aa0
EC		 876 {
877 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
878 .has_inbox = false,
879 .has_outbox = true,
880 .out_is_imm = false,
881 .encode_slave_id = false,
882 .verify = NULL,
883 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
884 },
885 {
886 .opcode = MLX4_CMD_QUERY_ADAPTER,
887 .has_inbox = false,
888 .has_outbox = true,
889 .out_is_imm = false,
890 .encode_slave_id = false,
891 .verify = NULL,
892 .wrapper = NULL
893 },
894 {
895 .opcode = MLX4_CMD_INIT_PORT,
896 .has_inbox = false,
897 .has_outbox = false,
898 .out_is_imm = false,
899 .encode_slave_id = false,
900 .verify = NULL,
901 .wrapper = mlx4_INIT_PORT_wrapper
902 },
903 {
904 .opcode = MLX4_CMD_CLOSE_PORT,
905 .has_inbox = false,
906 .has_outbox = false,
907 .out_is_imm = false,
908 .encode_slave_id = false,
909 .verify = NULL,
910 .wrapper = mlx4_CLOSE_PORT_wrapper
911 },
912 {
913 .opcode = MLX4_CMD_QUERY_PORT,
914 .has_inbox = false,
915 .has_outbox = true,
916 .out_is_imm = false,
917 .encode_slave_id = false,
918 .verify = NULL,
919 .wrapper = mlx4_QUERY_PORT_wrapper
920 },
ffe455ad
EE		 921 {
922 .opcode = MLX4_CMD_SET_PORT,
923 .has_inbox = true,
924 .has_outbox = false,
925 .out_is_imm = false,
926 .encode_slave_id = false,
927 .verify = NULL,
928 .wrapper = mlx4_SET_PORT_wrapper
929 },
c82e9aa0
EC		 930 {
931 .opcode = MLX4_CMD_MAP_EQ,
932 .has_inbox = false,
933 .has_outbox = false,
934 .out_is_imm = false,
935 .encode_slave_id = false,
936 .verify = NULL,
937 .wrapper = mlx4_MAP_EQ_wrapper
938 },
939 {
940 .opcode = MLX4_CMD_SW2HW_EQ,
941 .has_inbox = true,
942 .has_outbox = false,
943 .out_is_imm = false,
944 .encode_slave_id = true,
945 .verify = NULL,
946 .wrapper = mlx4_SW2HW_EQ_wrapper
947 },
948 {
949 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
950 .has_inbox = false,
951 .has_outbox = false,
952 .out_is_imm = false,
953 .encode_slave_id = false,
954 .verify = NULL,
955 .wrapper = NULL
956 },
957 {
958 .opcode = MLX4_CMD_NOP,
959 .has_inbox = false,
960 .has_outbox = false,
961 .out_is_imm = false,
962 .encode_slave_id = false,
963 .verify = NULL,
964 .wrapper = NULL
965 },
966 {
967 .opcode = MLX4_CMD_ALLOC_RES,
968 .has_inbox = false,
969 .has_outbox = false,
970 .out_is_imm = true,
971 .encode_slave_id = false,
972 .verify = NULL,
973 .wrapper = mlx4_ALLOC_RES_wrapper
974 },
975 {
976 .opcode = MLX4_CMD_FREE_RES,
977 .has_inbox = false,
978 .has_outbox = false,
979 .out_is_imm = false,
980 .encode_slave_id = false,
981 .verify = NULL,
982 .wrapper = mlx4_FREE_RES_wrapper
983 },
984 {
985 .opcode = MLX4_CMD_SW2HW_MPT,
986 .has_inbox = true,
987 .has_outbox = false,
988 .out_is_imm = false,
989 .encode_slave_id = true,
990 .verify = NULL,
991 .wrapper = mlx4_SW2HW_MPT_wrapper
992 },
993 {
994 .opcode = MLX4_CMD_QUERY_MPT,
995 .has_inbox = false,
996 .has_outbox = true,
997 .out_is_imm = false,
998 .encode_slave_id = false,
999 .verify = NULL,
1000 .wrapper = mlx4_QUERY_MPT_wrapper
1001 },
1002 {
1003 .opcode = MLX4_CMD_HW2SW_MPT,
1004 .has_inbox = false,
1005 .has_outbox = false,
1006 .out_is_imm = false,
1007 .encode_slave_id = false,
1008 .verify = NULL,
1009 .wrapper = mlx4_HW2SW_MPT_wrapper
1010 },
1011 {
1012 .opcode = MLX4_CMD_READ_MTT,
1013 .has_inbox = false,
1014 .has_outbox = true,
1015 .out_is_imm = false,
1016 .encode_slave_id = false,
1017 .verify = NULL,
1018 .wrapper = NULL
1019 },
1020 {
1021 .opcode = MLX4_CMD_WRITE_MTT,
1022 .has_inbox = true,
1023 .has_outbox = false,
1024 .out_is_imm = false,
1025 .encode_slave_id = false,
1026 .verify = NULL,
1027 .wrapper = mlx4_WRITE_MTT_wrapper
1028 },
1029 {
1030 .opcode = MLX4_CMD_SYNC_TPT,
1031 .has_inbox = true,
1032 .has_outbox = false,
1033 .out_is_imm = false,
1034 .encode_slave_id = false,
1035 .verify = NULL,
1036 .wrapper = NULL
1037 },
1038 {
1039 .opcode = MLX4_CMD_HW2SW_EQ,
1040 .has_inbox = false,
1041 .has_outbox = true,
1042 .out_is_imm = false,
1043 .encode_slave_id = true,
1044 .verify = NULL,
1045 .wrapper = mlx4_HW2SW_EQ_wrapper
1046 },
1047 {
1048 .opcode = MLX4_CMD_QUERY_EQ,
1049 .has_inbox = false,
1050 .has_outbox = true,
1051 .out_is_imm = false,
1052 .encode_slave_id = true,
1053 .verify = NULL,
1054 .wrapper = mlx4_QUERY_EQ_wrapper
1055 },
1056 {
1057 .opcode = MLX4_CMD_SW2HW_CQ,
1058 .has_inbox = true,
1059 .has_outbox = false,
1060 .out_is_imm = false,
1061 .encode_slave_id = true,
1062 .verify = NULL,
1063 .wrapper = mlx4_SW2HW_CQ_wrapper
1064 },
1065 {
1066 .opcode = MLX4_CMD_HW2SW_CQ,
1067 .has_inbox = false,
1068 .has_outbox = false,
1069 .out_is_imm = false,
1070 .encode_slave_id = false,
1071 .verify = NULL,
1072 .wrapper = mlx4_HW2SW_CQ_wrapper
1073 },
1074 {
1075 .opcode = MLX4_CMD_QUERY_CQ,
1076 .has_inbox = false,
1077 .has_outbox = true,
1078 .out_is_imm = false,
1079 .encode_slave_id = false,
1080 .verify = NULL,
1081 .wrapper = mlx4_QUERY_CQ_wrapper
1082 },
1083 {
1084 .opcode = MLX4_CMD_MODIFY_CQ,
1085 .has_inbox = true,
1086 .has_outbox = false,
1087 .out_is_imm = true,
1088 .encode_slave_id = false,
1089 .verify = NULL,
1090 .wrapper = mlx4_MODIFY_CQ_wrapper
1091 },
1092 {
1093 .opcode = MLX4_CMD_SW2HW_SRQ,
1094 .has_inbox = true,
1095 .has_outbox = false,
1096 .out_is_imm = false,
1097 .encode_slave_id = true,
1098 .verify = NULL,
1099 .wrapper = mlx4_SW2HW_SRQ_wrapper
1100 },
1101 {
1102 .opcode = MLX4_CMD_HW2SW_SRQ,
1103 .has_inbox = false,
1104 .has_outbox = false,
1105 .out_is_imm = false,
1106 .encode_slave_id = false,
1107 .verify = NULL,
1108 .wrapper = mlx4_HW2SW_SRQ_wrapper
1109 },
1110 {
1111 .opcode = MLX4_CMD_QUERY_SRQ,
1112 .has_inbox = false,
1113 .has_outbox = true,
1114 .out_is_imm = false,
1115 .encode_slave_id = false,
1116 .verify = NULL,
1117 .wrapper = mlx4_QUERY_SRQ_wrapper
1118 },
1119 {
1120 .opcode = MLX4_CMD_ARM_SRQ,
1121 .has_inbox = false,
1122 .has_outbox = false,
1123 .out_is_imm = false,
1124 .encode_slave_id = false,
1125 .verify = NULL,
1126 .wrapper = mlx4_ARM_SRQ_wrapper
1127 },
1128 {
1129 .opcode = MLX4_CMD_RST2INIT_QP,
1130 .has_inbox = true,
1131 .has_outbox = false,
1132 .out_is_imm = false,
1133 .encode_slave_id = true,
1134 .verify = NULL,
1135 .wrapper = mlx4_RST2INIT_QP_wrapper
1136 },
1137 {
1138 .opcode = MLX4_CMD_INIT2INIT_QP,
1139 .has_inbox = true,
1140 .has_outbox = false,
1141 .out_is_imm = false,
1142 .encode_slave_id = false,
1143 .verify = NULL,
54679e14 1144 .wrapper = mlx4_INIT2INIT_QP_wrapper
c82e9aa0
EC		 1145 },
1146 {
1147 .opcode = MLX4_CMD_INIT2RTR_QP,
1148 .has_inbox = true,
1149 .has_outbox = false,
1150 .out_is_imm = false,
1151 .encode_slave_id = false,
1152 .verify = NULL,
1153 .wrapper = mlx4_INIT2RTR_QP_wrapper
1154 },
1155 {
1156 .opcode = MLX4_CMD_RTR2RTS_QP,
1157 .has_inbox = true,
1158 .has_outbox = false,
1159 .out_is_imm = false,
1160 .encode_slave_id = false,
1161 .verify = NULL,
54679e14 1162 .wrapper = mlx4_RTR2RTS_QP_wrapper
c82e9aa0
EC		 1163 },
1164 {
1165 .opcode = MLX4_CMD_RTS2RTS_QP,
1166 .has_inbox = true,
1167 .has_outbox = false,
1168 .out_is_imm = false,
1169 .encode_slave_id = false,
1170 .verify = NULL,
54679e14 1171 .wrapper = mlx4_RTS2RTS_QP_wrapper
c82e9aa0
EC		 1172 },
1173 {
1174 .opcode = MLX4_CMD_SQERR2RTS_QP,
1175 .has_inbox = true,
1176 .has_outbox = false,
1177 .out_is_imm = false,
1178 .encode_slave_id = false,
1179 .verify = NULL,
54679e14 1180 .wrapper = mlx4_SQERR2RTS_QP_wrapper
c82e9aa0
EC		 1181 },
1182 {
1183 .opcode = MLX4_CMD_2ERR_QP,
1184 .has_inbox = false,
1185 .has_outbox = false,
1186 .out_is_imm = false,
1187 .encode_slave_id = false,
1188 .verify = NULL,
1189 .wrapper = mlx4_GEN_QP_wrapper
1190 },
1191 {
1192 .opcode = MLX4_CMD_RTS2SQD_QP,
1193 .has_inbox = false,
1194 .has_outbox = false,
1195 .out_is_imm = false,
1196 .encode_slave_id = false,
1197 .verify = NULL,
1198 .wrapper = mlx4_GEN_QP_wrapper
1199 },
1200 {
1201 .opcode = MLX4_CMD_SQD2SQD_QP,
1202 .has_inbox = true,
1203 .has_outbox = false,
1204 .out_is_imm = false,
1205 .encode_slave_id = false,
1206 .verify = NULL,
54679e14 1207 .wrapper = mlx4_SQD2SQD_QP_wrapper
c82e9aa0
EC		 1208 },
1209 {
1210 .opcode = MLX4_CMD_SQD2RTS_QP,
1211 .has_inbox = true,
1212 .has_outbox = false,
1213 .out_is_imm = false,
1214 .encode_slave_id = false,
1215 .verify = NULL,
54679e14 1216 .wrapper = mlx4_SQD2RTS_QP_wrapper
c82e9aa0
EC		 1217 },
1218 {
1219 .opcode = MLX4_CMD_2RST_QP,
1220 .has_inbox = false,
1221 .has_outbox = false,
1222 .out_is_imm = false,
1223 .encode_slave_id = false,
1224 .verify = NULL,
1225 .wrapper = mlx4_2RST_QP_wrapper
1226 },
1227 {
1228 .opcode = MLX4_CMD_QUERY_QP,
1229 .has_inbox = false,
1230 .has_outbox = true,
1231 .out_is_imm = false,
1232 .encode_slave_id = false,
1233 .verify = NULL,
1234 .wrapper = mlx4_GEN_QP_wrapper
1235 },
1236 {
1237 .opcode = MLX4_CMD_SUSPEND_QP,
1238 .has_inbox = false,
1239 .has_outbox = false,
1240 .out_is_imm = false,
1241 .encode_slave_id = false,
1242 .verify = NULL,
1243 .wrapper = mlx4_GEN_QP_wrapper
1244 },
1245 {
1246 .opcode = MLX4_CMD_UNSUSPEND_QP,
1247 .has_inbox = false,
1248 .has_outbox = false,
1249 .out_is_imm = false,
1250 .encode_slave_id = false,
1251 .verify = NULL,
1252 .wrapper = mlx4_GEN_QP_wrapper
1253 },
b01978ca
JM		 1254 {
1255 .opcode = MLX4_CMD_UPDATE_QP,
1256 .has_inbox = false,
1257 .has_outbox = false,
1258 .out_is_imm = false,
1259 .encode_slave_id = false,
1260 .verify = NULL,
1261 .wrapper = MLX4_CMD_UPDATE_QP_wrapper
1262 },
fe6f700d
YP		 1263 {
1264 .opcode = MLX4_CMD_GET_OP_REQ,
1265 .has_inbox = false,
1266 .has_outbox = false,
1267 .out_is_imm = false,
1268 .encode_slave_id = false,
1269 .verify = NULL,
1270 .wrapper = MLX4_CMD_GET_OP_REQ_wrapper,
1271 },
0a9a0188
JM		 1272 {
1273 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1274 .has_inbox = false,
1275 .has_outbox = false,
1276 .out_is_imm = false,
1277 .encode_slave_id = false,
1278 .verify = NULL, /* XXX verify: only demux can do this */
1279 .wrapper = NULL
1280 },
1281 {
1282 .opcode = MLX4_CMD_MAD_IFC,
1283 .has_inbox = true,
1284 .has_outbox = true,
1285 .out_is_imm = false,
1286 .encode_slave_id = false,
1287 .verify = NULL,
1288 .wrapper = mlx4_MAD_IFC_wrapper
1289 },
c82e9aa0
EC		 1290 {
1291 .opcode = MLX4_CMD_QUERY_IF_STAT,
1292 .has_inbox = false,
1293 .has_outbox = true,
1294 .out_is_imm = false,
1295 .encode_slave_id = false,
1296 .verify = NULL,
1297 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1298 },
1299 /* Native multicast commands are not available for guests */
1300 {
1301 .opcode = MLX4_CMD_QP_ATTACH,
1302 .has_inbox = true,
1303 .has_outbox = false,
1304 .out_is_imm = false,
1305 .encode_slave_id = false,
1306 .verify = NULL,
1307 .wrapper = mlx4_QP_ATTACH_wrapper
1308 },
0ec2c0f8
EE		 1309 {
1310 .opcode = MLX4_CMD_PROMISC,
1311 .has_inbox = false,
1312 .has_outbox = false,
1313 .out_is_imm = false,
1314 .encode_slave_id = false,
1315 .verify = NULL,
1316 .wrapper = mlx4_PROMISC_wrapper
1317 },
ffe455ad
EE		 1318 /* Ethernet specific commands */
1319 {
1320 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1321 .has_inbox = true,
1322 .has_outbox = false,
1323 .out_is_imm = false,
1324 .encode_slave_id = false,
1325 .verify = NULL,
1326 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1327 },
1328 {
1329 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1330 .has_inbox = false,
1331 .has_outbox = false,
1332 .out_is_imm = false,
1333 .encode_slave_id = false,
1334 .verify = NULL,
1335 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1336 },
1337 {
1338 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1339 .has_inbox = false,
1340 .has_outbox = true,
1341 .out_is_imm = false,
1342 .encode_slave_id = false,
1343 .verify = NULL,
1344 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1345 },
c82e9aa0
EC		 1346 {
1347 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1348 .has_inbox = false,
1349 .has_outbox = false,
1350 .out_is_imm = false,
1351 .encode_slave_id = false,
1352 .verify = NULL,
1353 .wrapper = NULL
1354 },
8fcfb4db
HHZ		 1355 /* flow steering commands */
1356 {
1357 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1358 .has_inbox = true,
1359 .has_outbox = false,
1360 .out_is_imm = true,
1361 .encode_slave_id = false,
1362 .verify = NULL,
1363 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1364 },
1365 {
1366 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1367 .has_inbox = false,
1368 .has_outbox = false,
1369 .out_is_imm = false,
1370 .encode_slave_id = false,
1371 .verify = NULL,
1372 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1373 },
e8f081aa
YP		 1374};
1375
1376static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1377 struct mlx4_vhcr_cmd *in_vhcr)
1378{
1379 struct mlx4_priv *priv = mlx4_priv(dev);
1380 struct mlx4_cmd_info *cmd = NULL;
1381 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1382 struct mlx4_vhcr *vhcr;
1383 struct mlx4_cmd_mailbox *inbox = NULL;
1384 struct mlx4_cmd_mailbox *outbox = NULL;
1385 u64 in_param;
1386 u64 out_param;
1387 int ret = 0;
1388 int i;
72be84f1 1389 int err = 0;
e8f081aa
YP		 1390
1391 /* Create sw representation of Virtual HCR */
1392 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1393 if (!vhcr)
1394 return -ENOMEM;
1395
1396 /* DMA in the vHCR */
1397 if (!in_vhcr) {
1398 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1399 priv->mfunc.master.slave_state[slave].vhcr_dma,
1400 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1401 MLX4_ACCESS_MEM_ALIGN), 1);
1402 if (ret) {
1403 mlx4_err(dev, "%s:Failed reading vhcr"
1404 "ret: 0x%x\n", __func__, ret);
1405 kfree(vhcr);
1406 return ret;
1407 }
1408 }
1409
1410 /* Fill SW VHCR fields */
1411 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1412 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1413 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1414 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1415 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1416 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1417 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1418
1419 /* Lookup command */
1420 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1421 if (vhcr->op == cmd_info[i].opcode) {
1422 cmd = &cmd_info[i];
1423 break;
1424 }
1425 }
1426 if (!cmd) {
1427 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1428 vhcr->op, slave);
72be84f1 1429 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 1430 goto out_status;
1431 }
1432
1433 /* Read inbox */
1434 if (cmd->has_inbox) {
1435 vhcr->in_param &= INBOX_MASK;
1436 inbox = mlx4_alloc_cmd_mailbox(dev);
1437 if (IS_ERR(inbox)) {
72be84f1 1438 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1439 inbox = NULL;
72be84f1 1440 goto out_status;
e8f081aa
YP		 1441 }
1442
72be84f1
YP		 1443 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1444 vhcr->in_param,
1445 MLX4_MAILBOX_SIZE, 1)) {
e8f081aa
YP		 1446 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1447 __func__, cmd->opcode);
72be84f1
YP		 1448 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1449 goto out_status;
e8f081aa
YP		 1450 }
1451 }
1452
1453 /* Apply permission and bound checks if applicable */
1454 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1455 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1456 "checks for resource_id:%d\n", vhcr->op, slave,
1457 vhcr->in_modifier);
72be84f1 1458 vhcr_cmd->status = CMD_STAT_BAD_OP;
e8f081aa
YP		 1459 goto out_status;
1460 }
1461
1462 /* Allocate outbox */
1463 if (cmd->has_outbox) {
1464 outbox = mlx4_alloc_cmd_mailbox(dev);
1465 if (IS_ERR(outbox)) {
72be84f1 1466 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1467 outbox = NULL;
72be84f1 1468 goto out_status;
e8f081aa
YP		 1469 }
1470 }
1471
1472 /* Execute the command! */
1473 if (cmd->wrapper) {
72be84f1
YP		 1474 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1475 cmd);
e8f081aa
YP		 1476 if (cmd->out_is_imm)
1477 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1478 } else {
1479 in_param = cmd->has_inbox ? (u64) inbox->dma :
1480 vhcr->in_param;
1481 out_param = cmd->has_outbox ? (u64) outbox->dma :
1482 vhcr->out_param;
72be84f1
YP		 1483 err = __mlx4_cmd(dev, in_param, &out_param,
1484 cmd->out_is_imm, vhcr->in_modifier,
1485 vhcr->op_modifier, vhcr->op,
1486 MLX4_CMD_TIME_CLASS_A,
1487 MLX4_CMD_NATIVE);
e8f081aa
YP		 1488
1489 if (cmd->out_is_imm) {
1490 vhcr->out_param = out_param;
1491 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1492 }
1493 }
1494
72be84f1
YP		 1495 if (err) {
1496 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1497 " error:%d, status %d\n",
1498 vhcr->op, slave, vhcr->errno, err);
1499 vhcr_cmd->status = mlx4_errno_to_status(err);
1500 goto out_status;
1501 }
1502
1503
e8f081aa 1504 /* Write outbox if command completed successfully */
72be84f1 1505 if (cmd->has_outbox && !vhcr_cmd->status) {
e8f081aa
YP		 1506 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1507 vhcr->out_param,
1508 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1509 if (ret) {
72be84f1
YP		 1510 /* If we failed to write back the outbox after the
1511 *command was successfully executed, we must fail this
1512 * slave, as it is now in undefined state */
e8f081aa
YP		 1513 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1514 goto out;
1515 }
1516 }
1517
1518out_status:
1519 /* DMA back vhcr result */
1520 if (!in_vhcr) {
1521 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1522 priv->mfunc.master.slave_state[slave].vhcr_dma,
1523 ALIGN(sizeof(struct mlx4_vhcr),
1524 MLX4_ACCESS_MEM_ALIGN),
1525 MLX4_CMD_WRAPPED);
1526 if (ret)
1527 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1528 __func__);
1529 else if (vhcr->e_bit &&
1530 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1531 mlx4_warn(dev, "Failed to generate command completion "
1532 "eqe for slave %d\n", slave);
1533 }
1534
1535out:
1536 kfree(vhcr);
1537 mlx4_free_cmd_mailbox(dev, inbox);
1538 mlx4_free_cmd_mailbox(dev, outbox);
1539 return ret;
1540}
1541
0a6eac24
RE		 1542static int calculate_transition(u16 oper_vlan, u16 admin_vlan)
1543{
1544 return (2 * (oper_vlan == MLX4_VGT) + (admin_vlan == MLX4_VGT));
1545}
b01978ca 1546
f094668c 1547static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
b01978ca
JM		 1548 int slave, int port)
1549{
1550 struct mlx4_vport_oper_state *vp_oper;
1551 struct mlx4_vport_state *vp_admin;
1552 struct mlx4_vf_immed_vlan_work *work;
0a6eac24 1553 struct mlx4_dev *dev = &(priv->dev);
b01978ca
JM		 1554 int err;
1555 int admin_vlan_ix = NO_INDX;
0a6eac24 1556 enum mlx4_vlan_transition vlan_trans;
b01978ca
JM		 1557
1558 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1559 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1560
1561 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
0a6eac24
RE		 1562 vp_oper->state.default_qos == vp_admin->default_qos &&
1563 vp_oper->state.link_state == vp_admin->link_state)
b01978ca
JM		 1564 return 0;
1565
0a6eac24
RE		 1566 vlan_trans = calculate_transition(vp_oper->state.default_vlan,
1567 vp_admin->default_vlan);
1568
1569 if (!(priv->mfunc.master.slave_state[slave].active &&
1570 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP &&
1571 vlan_trans == MLX4_VLAN_TRANSITION_VST_VST)) {
1572 /* even if the UPDATE_QP command isn't supported, we still want
1573 * to set this VF link according to the admin directive
1574 */
1575 vp_oper->state.link_state = vp_admin->link_state;
1576 return -1;
1577 }
1578
1579 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1580 slave, port);
1581 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n", vp_admin->default_vlan,
1582 vp_admin->default_qos, vp_admin->link_state);
1583
b01978ca
JM		 1584 work = kzalloc(sizeof(*work), GFP_KERNEL);
1585 if (!work)
1586 return -ENOMEM;
1587
1588 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1589 err = __mlx4_register_vlan(&priv->dev, port,
1590 vp_admin->default_vlan,
1591 &admin_vlan_ix);
1592 if (err) {
9caf83c3 1593 kfree(work);
b01978ca
JM		 1594 mlx4_warn((&priv->dev),
1595 "No vlan resources slave %d, port %d\n",
1596 slave, port);
1597 return err;
1598 }
1599 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1600 mlx4_dbg((&(priv->dev)),
1601 "alloc vlan %d idx %d slave %d port %d\n",
1602 (int)(vp_admin->default_vlan),
1603 admin_vlan_ix, slave, port);
1604 }
1605
1606 /* save original vlan ix and vlan id */
1607 work->orig_vlan_id = vp_oper->state.default_vlan;
1608 work->orig_vlan_ix = vp_oper->vlan_idx;
1609
1610 /* handle new qos */
1611 if (vp_oper->state.default_qos != vp_admin->default_qos)
1612 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1613
1614 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1615 vp_oper->vlan_idx = admin_vlan_ix;
1616
1617 vp_oper->state.default_vlan = vp_admin->default_vlan;
1618 vp_oper->state.default_qos = vp_admin->default_qos;
0a6eac24
RE		 1619 vp_oper->state.link_state = vp_admin->link_state;
1620
1621 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1622 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
b01978ca
JM		 1623
1624 /* iterate over QPs owned by this slave, using UPDATE_QP */
1625 work->port = port;
1626 work->slave = slave;
1627 work->qos = vp_oper->state.default_qos;
1628 work->vlan_id = vp_oper->state.default_vlan;
1629 work->vlan_ix = vp_oper->vlan_idx;
1630 work->priv = priv;
1631 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1632 queue_work(priv->mfunc.master.comm_wq, &work->work);
1633
1634 return 0;
1635}
1636
1637
0eb62b93
RE		 1638static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1639{
3f7fb021
RE		 1640 int port, err;
1641 struct mlx4_vport_state *vp_admin;
1642 struct mlx4_vport_oper_state *vp_oper;
1643
0eb62b93 1644 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
3f7fb021
RE		 1645 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1646 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1647 vp_oper->state = *vp_admin;
1648 if (MLX4_VGT != vp_admin->default_vlan) {
1649 err = __mlx4_register_vlan(&priv->dev, port,
1650 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1651 if (err) {
1652 vp_oper->vlan_idx = NO_INDX;
1653 mlx4_warn((&priv->dev),
1654 "No vlan resorces slave %d, port %d\n",
1655 slave, port);
1656 return err;
1657 }
1658 mlx4_dbg((&(priv->dev)), "alloc vlan %d idx %d slave %d port %d\n",
1659 (int)(vp_oper->state.default_vlan),
1660 vp_oper->vlan_idx, slave, port);
1661 }
e6b6a231
RE		 1662 if (vp_admin->spoofchk) {
1663 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1664 port,
1665 vp_admin->mac);
1666 if (0 > vp_oper->mac_idx) {
1667 err = vp_oper->mac_idx;
1668 vp_oper->mac_idx = NO_INDX;
1669 mlx4_warn((&priv->dev),
1670 "No mac resorces slave %d, port %d\n",
1671 slave, port);
1672 return err;
1673 }
1674 mlx4_dbg((&(priv->dev)), "alloc mac %llx idx %d slave %d port %d\n",
1675 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1676 }
0eb62b93
RE		 1677 }
1678 return 0;
1679}
1680
3f7fb021
RE		 1681static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1682{
1683 int port;
1684 struct mlx4_vport_oper_state *vp_oper;
1685
1686 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1687 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1688 if (NO_INDX != vp_oper->vlan_idx) {
1689 __mlx4_unregister_vlan(&priv->dev,
1690 port, vp_oper->vlan_idx);
1691 vp_oper->vlan_idx = NO_INDX;
1692 }
e6b6a231
RE		 1693 if (NO_INDX != vp_oper->mac_idx) {
1694 __mlx4_unregister_mac(&priv->dev, port, vp_oper->mac_idx);
1695 vp_oper->mac_idx = NO_INDX;
1696 }
3f7fb021
RE		 1697 }
1698 return;
1699}
1700
e8f081aa
YP		 1701static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1702 u16 param, u8 toggle)
1703{
1704 struct mlx4_priv *priv = mlx4_priv(dev);
1705 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1706 u32 reply;
e8f081aa 1707 u8 is_going_down = 0;
803143fb 1708 int i;
311f813a 1709 unsigned long flags;
e8f081aa
YP		 1710
1711 slave_state[slave].comm_toggle ^= 1;
1712 reply = (u32) slave_state[slave].comm_toggle << 31;
1713 if (toggle != slave_state[slave].comm_toggle) {
1714 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1715 "STATE COMPROMISIED ***\n", toggle, slave);
1716 goto reset_slave;
1717 }
1718 if (cmd == MLX4_COMM_CMD_RESET) {
1719 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1720 slave_state[slave].active = false;
3f7fb021 1721 mlx4_master_deactivate_admin_state(priv, slave);
803143fb
MA		 1722 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1723 slave_state[slave].event_eq[i].eqn = -1;
1724 slave_state[slave].event_eq[i].token = 0;
1725 }
e8f081aa
YP		 1726 /*check if we are in the middle of FLR process,
1727 if so return "retry" status to the slave*/
162344ed 1728 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
e8f081aa 1729 goto inform_slave_state;
e8f081aa 1730
fc06573d
JM		 1731 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1732
e8f081aa
YP		 1733 /* write the version in the event field */
1734 reply |= mlx4_comm_get_version();
1735
1736 goto reset_slave;
1737 }
1738 /*command from slave in the middle of FLR*/
1739 if (cmd != MLX4_COMM_CMD_RESET &&
1740 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1741 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1742 "in the middle of FLR\n", slave, cmd);
1743 return;
1744 }
1745
1746 switch (cmd) {
1747 case MLX4_COMM_CMD_VHCR0:
1748 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1749 goto reset_slave;
1750 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1751 priv->mfunc.master.slave_state[slave].cookie = 0;
1752 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1753 break;
1754 case MLX4_COMM_CMD_VHCR1:
1755 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1756 goto reset_slave;
1757 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1758 break;
1759 case MLX4_COMM_CMD_VHCR2:
1760 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1761 goto reset_slave;
1762 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1763 break;
1764 case MLX4_COMM_CMD_VHCR_EN:
1765 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1766 goto reset_slave;
1767 slave_state[slave].vhcr_dma |= param;
3f7fb021
RE		 1768 if (mlx4_master_activate_admin_state(priv, slave))
1769 goto reset_slave;
e8f081aa 1770 slave_state[slave].active = true;
fc06573d 1771 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
e8f081aa
YP		 1772 break;
1773 case MLX4_COMM_CMD_VHCR_POST:
1774 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1775 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1776 goto reset_slave;
f3d4c89e
RD		 1777
1778 mutex_lock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1779 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1780 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
8d9eb069 1781 " resetting slave.\n", slave);
f3d4c89e 1782 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1783 goto reset_slave;
1784 }
f3d4c89e 1785 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1786 break;
1787 default:
1788 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1789 goto reset_slave;
1790 }
311f813a 1791 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1792 if (!slave_state[slave].is_slave_going_down)
1793 slave_state[slave].last_cmd = cmd;
1794 else
1795 is_going_down = 1;
311f813a 1796 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1797 if (is_going_down) {
1798 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1799 " executing from slave:%d\n",
1800 cmd, slave);
1801 return;
1802 }
1803 __raw_writel((__force u32) cpu_to_be32(reply),
1804 &priv->mfunc.comm[slave].slave_read);
1805 mmiowb();
1806
1807 return;
1808
1809reset_slave:
c82e9aa0
EC		 1810 /* cleanup any slave resources */
1811 mlx4_delete_all_resources_for_slave(dev, slave);
311f813a 1812 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1813 if (!slave_state[slave].is_slave_going_down)
1814 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
311f813a 1815 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1816 /*with slave in the middle of flr, no need to clean resources again.*/
1817inform_slave_state:
1818 memset(&slave_state[slave].event_eq, 0,
1819 sizeof(struct mlx4_slave_event_eq_info));
1820 __raw_writel((__force u32) cpu_to_be32(reply),
1821 &priv->mfunc.comm[slave].slave_read);
1822 wmb();
1823}
1824
1825/* master command processing */
1826void mlx4_master_comm_channel(struct work_struct *work)
1827{
1828 struct mlx4_mfunc_master_ctx *master =
1829 container_of(work,
1830 struct mlx4_mfunc_master_ctx,
1831 comm_work);
1832 struct mlx4_mfunc *mfunc =
1833 container_of(master, struct mlx4_mfunc, master);
1834 struct mlx4_priv *priv =
1835 container_of(mfunc, struct mlx4_priv, mfunc);
1836 struct mlx4_dev *dev = &priv->dev;
1837 __be32 *bit_vec;
1838 u32 comm_cmd;
1839 u32 vec;
1840 int i, j, slave;
1841 int toggle;
1842 int served = 0;
1843 int reported = 0;
1844 u32 slt;
1845
1846 bit_vec = master->comm_arm_bit_vector;
1847 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1848 vec = be32_to_cpu(bit_vec[i]);
1849 for (j = 0; j < 32; j++) {
1850 if (!(vec & (1 << j)))
1851 continue;
1852 ++reported;
1853 slave = (i * 32) + j;
1854 comm_cmd = swab32(readl(
1855 &mfunc->comm[slave].slave_write));
1856 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1857 >> 31;
1858 toggle = comm_cmd >> 31;
1859 if (toggle != slt) {
1860 if (master->slave_state[slave].comm_toggle
1861 != slt) {
1862 printk(KERN_INFO "slave %d out of sync."
1863 " read toggle %d, state toggle %d. "
1864 "Resynching.\n", slave, slt,
1865 master->slave_state[slave].comm_toggle);
1866 master->slave_state[slave].comm_toggle =
1867 slt;
1868 }
1869 mlx4_master_do_cmd(dev, slave,
1870 comm_cmd >> 16 & 0xff,
1871 comm_cmd & 0xffff, toggle);
1872 ++served;
1873 }
1874 }
1875 }
1876
1877 if (reported && reported != served)
1878 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1879 " but %d were served\n",
1880 reported, served);
1881
1882 if (mlx4_ARM_COMM_CHANNEL(dev))
1883 mlx4_warn(dev, "Failed to arm comm channel events\n");
1884}
1885
ab9c17a0
JM		 1886static int sync_toggles(struct mlx4_dev *dev)
1887{
1888 struct mlx4_priv *priv = mlx4_priv(dev);
1889 int wr_toggle;
1890 int rd_toggle;
1891 unsigned long end;
1892
1893 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1894 end = jiffies + msecs_to_jiffies(5000);
1895
1896 while (time_before(jiffies, end)) {
1897 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1898 if (rd_toggle == wr_toggle) {
1899 priv->cmd.comm_toggle = rd_toggle;
1900 return 0;
1901 }
1902
1903 cond_resched();
1904 }
1905
1906 /*
1907 * we could reach here if for example the previous VM using this
1908 * function misbehaved and left the channel with unsynced state. We
1909 * should fix this here and give this VM a chance to use a properly
1910 * synced channel
1911 */
1912 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1913 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1914 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1915 priv->cmd.comm_toggle = 0;
1916
1917 return 0;
1918}
1919
1920int mlx4_multi_func_init(struct mlx4_dev *dev)
1921{
1922 struct mlx4_priv *priv = mlx4_priv(dev);
1923 struct mlx4_slave_state *s_state;
803143fb 1924 int i, j, err, port;
ab9c17a0 1925
ab9c17a0
JM		 1926 if (mlx4_is_master(dev))
1927 priv->mfunc.comm =
1928 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1929 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1930 else
1931 priv->mfunc.comm =
1932 ioremap(pci_resource_start(dev->pdev, 2) +
1933 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1934 if (!priv->mfunc.comm) {
1935 mlx4_err(dev, "Couldn't map communication vector.\n");
1936 goto err_vhcr;
1937 }
1938
1939 if (mlx4_is_master(dev)) {
1940 priv->mfunc.master.slave_state =
1941 kzalloc(dev->num_slaves *
1942 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1943 if (!priv->mfunc.master.slave_state)
1944 goto err_comm;
1945
0eb62b93
RE		 1946 priv->mfunc.master.vf_admin =
1947 kzalloc(dev->num_slaves *
1948 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1949 if (!priv->mfunc.master.vf_admin)
1950 goto err_comm_admin;
1951
1952 priv->mfunc.master.vf_oper =
1953 kzalloc(dev->num_slaves *
1954 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1955 if (!priv->mfunc.master.vf_oper)
1956 goto err_comm_oper;
1957
ab9c17a0
JM		 1958 for (i = 0; i < dev->num_slaves; ++i) {
1959 s_state = &priv->mfunc.master.slave_state[i];
1960 s_state->last_cmd = MLX4_COMM_CMD_RESET;
803143fb
MA		 1961 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1962 s_state->event_eq[j].eqn = -1;
ab9c17a0
JM		 1963 __raw_writel((__force u32) 0,
1964 &priv->mfunc.comm[i].slave_write);
1965 __raw_writel((__force u32) 0,
1966 &priv->mfunc.comm[i].slave_read);
1967 mmiowb();
1968 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1969 s_state->vlan_filter[port] =
1970 kzalloc(sizeof(struct mlx4_vlan_fltr),
1971 GFP_KERNEL);
1972 if (!s_state->vlan_filter[port]) {
1973 if (--port)
1974 kfree(s_state->vlan_filter[port]);
1975 goto err_slaves;
1976 }
1977 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
0eb62b93 1978 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
3f7fb021 1979 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
0eb62b93
RE		 1980 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1981 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
ab9c17a0
JM		 1982 }
1983 spin_lock_init(&s_state->lock);
1984 }
1985
08ff3235 1986 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
ab9c17a0
JM		 1987 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1988 INIT_WORK(&priv->mfunc.master.comm_work,
1989 mlx4_master_comm_channel);
1990 INIT_WORK(&priv->mfunc.master.slave_event_work,
1991 mlx4_gen_slave_eqe);
1992 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1993 mlx4_master_handle_slave_flr);
1994 spin_lock_init(&priv->mfunc.master.slave_state_lock);
992e8e6e 1995 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
ab9c17a0
JM		 1996 priv->mfunc.master.comm_wq =
1997 create_singlethread_workqueue("mlx4_comm");
1998 if (!priv->mfunc.master.comm_wq)
1999 goto err_slaves;
2000
2001 if (mlx4_init_resource_tracker(dev))
2002 goto err_thread;
2003
ab9c17a0
JM		 2004 err = mlx4_ARM_COMM_CHANNEL(dev);
2005 if (err) {
2006 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2007 err);
2008 goto err_resource;
2009 }
2010
2011 } else {
2012 err = sync_toggles(dev);
2013 if (err) {
2014 mlx4_err(dev, "Couldn't sync toggles\n");
2015 goto err_comm;
2016 }
ab9c17a0
JM		 2017 }
2018 return 0;
2019
2020err_resource:
b8924951 2021 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
ab9c17a0
JM		 2022err_thread:
2023 flush_workqueue(priv->mfunc.master.comm_wq);
2024 destroy_workqueue(priv->mfunc.master.comm_wq);
2025err_slaves:
2026 while (--i) {
2027 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2028 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2029 }
0eb62b93
RE		 2030 kfree(priv->mfunc.master.vf_oper);
2031err_comm_oper:
2032 kfree(priv->mfunc.master.vf_admin);
2033err_comm_admin:
ab9c17a0
JM		 2034 kfree(priv->mfunc.master.slave_state);
2035err_comm:
2036 iounmap(priv->mfunc.comm);
2037err_vhcr:
2038 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2039 priv->mfunc.vhcr,
2040 priv->mfunc.vhcr_dma);
2041 priv->mfunc.vhcr = NULL;
2042 return -ENOMEM;
2043}
2044
225c7b1f
RD		 2045int mlx4_cmd_init(struct mlx4_dev *dev)
2046{
2047 struct mlx4_priv *priv = mlx4_priv(dev);
2048
2049 mutex_init(&priv->cmd.hcr_mutex);
f3d4c89e 2050 mutex_init(&priv->cmd.slave_cmd_mutex);
225c7b1f
RD		 2051 sema_init(&priv->cmd.poll_sem, 1);
2052 priv->cmd.use_events = 0;
2053 priv->cmd.toggle = 1;
2054
e8f081aa
YP		 2055 priv->cmd.hcr = NULL;
2056 priv->mfunc.vhcr = NULL;
2057
2058 if (!mlx4_is_slave(dev)) {
2059 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2060 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2061 if (!priv->cmd.hcr) {
2062 mlx4_err(dev, "Couldn't map command register.\n");
2063 return -ENOMEM;
2064 }
225c7b1f
RD		 2065 }
2066
f3d4c89e
RD		 2067 if (mlx4_is_mfunc(dev)) {
2068 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2069 &priv->mfunc.vhcr_dma,
2070 GFP_KERNEL);
d0320f75 2071 if (!priv->mfunc.vhcr)
f3d4c89e 2072 goto err_hcr;
f3d4c89e
RD		 2073 }
2074
225c7b1f
RD		 2075 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2076 MLX4_MAILBOX_SIZE,
2077 MLX4_MAILBOX_SIZE, 0);
e8f081aa 2078 if (!priv->cmd.pool)
f3d4c89e 2079 goto err_vhcr;
225c7b1f
RD		 2080
2081 return 0;
e8f081aa 2082
f3d4c89e
RD		 2083err_vhcr:
2084 if (mlx4_is_mfunc(dev))
2085 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2086 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2087 priv->mfunc.vhcr = NULL;
2088
e8f081aa
YP		 2089err_hcr:
2090 if (!mlx4_is_slave(dev))
2091 iounmap(priv->cmd.hcr);
2092 return -ENOMEM;
225c7b1f
RD		 2093}
2094
ab9c17a0
JM		 2095void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2096{
2097 struct mlx4_priv *priv = mlx4_priv(dev);
2098 int i, port;
2099
2100 if (mlx4_is_master(dev)) {
2101 flush_workqueue(priv->mfunc.master.comm_wq);
2102 destroy_workqueue(priv->mfunc.master.comm_wq);
2103 for (i = 0; i < dev->num_slaves; i++) {
2104 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2105 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2106 }
2107 kfree(priv->mfunc.master.slave_state);
0eb62b93
RE		 2108 kfree(priv->mfunc.master.vf_admin);
2109 kfree(priv->mfunc.master.vf_oper);
ab9c17a0 2110 }
f08ad06c
EE		 2111
2112 iounmap(priv->mfunc.comm);
ab9c17a0
JM		 2113}
2114
225c7b1f
RD		 2115void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2116{
2117 struct mlx4_priv *priv = mlx4_priv(dev);
2118
2119 pci_pool_destroy(priv->cmd.pool);
e8f081aa
YP		 2120
2121 if (!mlx4_is_slave(dev))
2122 iounmap(priv->cmd.hcr);
f3d4c89e
RD		 2123 if (mlx4_is_mfunc(dev))
2124 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2125 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2126 priv->mfunc.vhcr = NULL;
225c7b1f
RD		 2127}
2128
2129/*
2130 * Switch to using events to issue FW commands (can only be called
2131 * after event queue for command events has been initialized).
2132 */
2133int mlx4_cmd_use_events(struct mlx4_dev *dev)
2134{
2135 struct mlx4_priv *priv = mlx4_priv(dev);
2136 int i;
e8f081aa 2137 int err = 0;
225c7b1f
RD		 2138
2139 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2140 sizeof (struct mlx4_cmd_context),
2141 GFP_KERNEL);
2142 if (!priv->cmd.context)
2143 return -ENOMEM;
2144
2145 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2146 priv->cmd.context[i].token = i;
2147 priv->cmd.context[i].next = i + 1;
2148 }
2149
2150 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2151 priv->cmd.free_head = 0;
2152
2153 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2154 spin_lock_init(&priv->cmd.context_lock);
2155
2156 for (priv->cmd.token_mask = 1;
2157 priv->cmd.token_mask < priv->cmd.max_cmds;
2158 priv->cmd.token_mask <<= 1)
2159 ; /* nothing */
2160 --priv->cmd.token_mask;
2161
225c7b1f 2162 down(&priv->cmd.poll_sem);
e8f081aa 2163 priv->cmd.use_events = 1;
225c7b1f 2164
e8f081aa 2165 return err;
225c7b1f
RD		 2166}
2167
2168/*
2169 * Switch back to polling (used when shutting down the device)
2170 */
2171void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2172{
2173 struct mlx4_priv *priv = mlx4_priv(dev);
2174 int i;
2175
2176 priv->cmd.use_events = 0;
2177
2178 for (i = 0; i < priv->cmd.max_cmds; ++i)
2179 down(&priv->cmd.event_sem);
2180
2181 kfree(priv->cmd.context);
2182
2183 up(&priv->cmd.poll_sem);
2184}
2185
2186struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2187{
2188 struct mlx4_cmd_mailbox *mailbox;
2189
2190 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2191 if (!mailbox)
2192 return ERR_PTR(-ENOMEM);
2193
2194 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2195 &mailbox->dma);
2196 if (!mailbox->buf) {
2197 kfree(mailbox);
2198 return ERR_PTR(-ENOMEM);
2199 }
2200
2201 return mailbox;
2202}
2203EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2204
e8f081aa
YP		 2205void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2206 struct mlx4_cmd_mailbox *mailbox)
225c7b1f
RD		 2207{
2208 if (!mailbox)
2209 return;
2210
2211 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2212 kfree(mailbox);
2213}
2214EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
e8f081aa
YP		 2215
2216u32 mlx4_comm_get_version(void)
2217{
2218 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2219}
8f7ba3ca
RE		 2220
2221static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2222{
2223 if ((vf < 0) || (vf >= dev->num_vfs)) {
2224 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2225 return -EINVAL;
2226 }
2227
2228 return vf+1;
2229}
2230
2231int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2232{
2233 struct mlx4_priv *priv = mlx4_priv(dev);
2234 struct mlx4_vport_state *s_info;
2235 int slave;
2236
2237 if (!mlx4_is_master(dev))
2238 return -EPROTONOSUPPORT;
2239
2240 slave = mlx4_get_slave_indx(dev, vf);
2241 if (slave < 0)
2242 return -EINVAL;
2243
2244 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2245 s_info->mac = mac;
2246 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2247 vf, port, s_info->mac);
2248 return 0;
2249}
2250EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3f7fb021 2251
b01978ca 2252
3f7fb021
RE		 2253int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2254{
2255 struct mlx4_priv *priv = mlx4_priv(dev);
b01978ca
JM		 2256 struct mlx4_vport_oper_state *vf_oper;
2257 struct mlx4_vport_state *vf_admin;
3f7fb021
RE		 2258 int slave;
2259
2260 if ((!mlx4_is_master(dev)) ||
2261 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2262 return -EPROTONOSUPPORT;
2263
2264 if ((vlan > 4095) || (qos > 7))
2265 return -EINVAL;
2266
2267 slave = mlx4_get_slave_indx(dev, vf);
2268 if (slave < 0)
2269 return -EINVAL;
2270
b01978ca
JM		 2271 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2272 vf_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2273
3f7fb021 2274 if ((0 == vlan) && (0 == qos))
b01978ca 2275 vf_admin->default_vlan = MLX4_VGT;
3f7fb021 2276 else
b01978ca
JM		 2277 vf_admin->default_vlan = vlan;
2278 vf_admin->default_qos = qos;
2279
0a6eac24
RE		 2280 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2281 mlx4_info(dev,
2282 "updating vf %d port %d config will take effect on next VF restart\n",
b01978ca 2283 vf, port);
3f7fb021
RE		 2284 return 0;
2285}
2286EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
e6b6a231
RE		 2287
2288int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2289{
2290 struct mlx4_priv *priv = mlx4_priv(dev);
2291 struct mlx4_vport_state *s_info;
2292 int slave;
2293
2294 if ((!mlx4_is_master(dev)) ||
2295 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2296 return -EPROTONOSUPPORT;
2297
2298 slave = mlx4_get_slave_indx(dev, vf);
2299 if (slave < 0)
2300 return -EINVAL;
2301
2302 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2303 s_info->spoofchk = setting;
2304
2305 return 0;
2306}
2307EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2cccb9e4
RE		 2308
2309int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2310{
2311 struct mlx4_priv *priv = mlx4_priv(dev);
2312 struct mlx4_vport_state *s_info;
2313 int slave;
2314
2315 if (!mlx4_is_master(dev))
2316 return -EPROTONOSUPPORT;
2317
2318 slave = mlx4_get_slave_indx(dev, vf);
2319 if (slave < 0)
2320 return -EINVAL;
2321
2322 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2323 ivf->vf = vf;
2324
2325 /* need to convert it to a func */
2326 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2327 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2328 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2329 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2330 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2331 ivf->mac[5] = ((s_info->mac) & 0xff);
2332
2333 ivf->vlan = s_info->default_vlan;
2334 ivf->qos = s_info->default_qos;
2335 ivf->tx_rate = s_info->tx_rate;
2336 ivf->spoofchk = s_info->spoofchk;
948e306d 2337 ivf->linkstate = s_info->link_state;
2cccb9e4
RE		 2338
2339 return 0;
2340}
2341EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
948e306d
RE		 2342
2343int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2344{
2345 struct mlx4_priv *priv = mlx4_priv(dev);
2346 struct mlx4_vport_state *s_info;
948e306d
RE		 2347 int slave;
2348 u8 link_stat_event;
2349
2350 slave = mlx4_get_slave_indx(dev, vf);
2351 if (slave < 0)
2352 return -EINVAL;
2353
2354 switch (link_state) {
2355 case IFLA_VF_LINK_STATE_AUTO:
2356 /* get current link state */
2357 if (!priv->sense.do_sense_port[port])
2358 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2359 else
2360 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2361 break;
2362
2363 case IFLA_VF_LINK_STATE_ENABLE:
2364 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2365 break;
2366
2367 case IFLA_VF_LINK_STATE_DISABLE:
2368 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2369 break;
2370
2371 default:
2372 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2373 link_state, slave, port);
2374 return -EINVAL;
2375 };
948e306d 2376 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
948e306d 2377 s_info->link_state = link_state;
948e306d
RE		 2378
2379 /* send event */
2380 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
0a6eac24
RE		 2381
2382 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2383 mlx4_dbg(dev,
2384 "updating vf %d port %d no link state HW enforcment\n",
2385 vf, port);
948e306d
RE		 2386 return 0;
2387}
2388EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
Linux 6.x block layer and io_uring tree(s)