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hyperv: Add hash value into RNDIS Per-packet info
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/sched.h>
5a0e3ad6 36#include <linux/slab.h>
ee40fa06 37#include <linux/export.h>
225c7b1f
RD		 38#include <linux/pci.h>
39#include <linux/errno.h>
40
41#include <linux/mlx4/cmd.h>
948e306d 42#include <linux/mlx4/device.h>
e8f081aa 43#include <linux/semaphore.h>
0a9a0188 44#include <rdma/ib_smi.h>
225c7b1f
RD		 45
46#include <asm/io.h>
47
48#include "mlx4.h"
e8f081aa 49#include "fw.h"
225c7b1f
RD		 50
51#define CMD_POLL_TOKEN 0xffff
e8f081aa
YP		 52#define INBOX_MASK 0xffffffffffffff00ULL
53
54#define CMD_CHAN_VER 1
55#define CMD_CHAN_IF_REV 1
225c7b1f
RD		 56
57enum {
58 /* command completed successfully: */
59 CMD_STAT_OK = 0x00,
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
899698da
JM		 80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
225c7b1f
RD		 82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
cc4ac2e7
YP		 93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
225c7b1f
RD		 96};
97
98enum {
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
104
105 HCR_OPMOD_SHIFT = 12,
106 HCR_T_BIT = 21,
107 HCR_E_BIT = 22,
108 HCR_GO_BIT = 23
109};
110
111enum {
36ce10d3 112 GO_BIT_TIMEOUT_MSECS = 10000
225c7b1f
RD		 113};
114
b01978ca
JM		 115enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
120};
121
122
225c7b1f
RD		 123struct mlx4_cmd_context {
124 struct completion done;
125 int result;
126 int next;
127 u64 out_param;
128 u16 token;
e8f081aa 129 u8 fw_status;
225c7b1f
RD		 130};
131
e8f081aa
YP		 132static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
134
ca281211
RD		 135static int mlx4_status_to_errno(u8 status)
136{
225c7b1f
RD		 137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
899698da 148 [CMD_STAT_ICM_ERROR] = -ENFILE,
225c7b1f
RD		 149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
cc4ac2e7 155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
225c7b1f
RD		 156 };
157
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
160 return -EIO;
161
162 return trans_table[status];
163}
164
72be84f1
YP		 165static u8 mlx4_errno_to_status(int errno)
166{
167 switch (errno) {
168 case -EPERM:
169 return CMD_STAT_BAD_OP;
170 case -EINVAL:
171 return CMD_STAT_BAD_PARAM;
172 case -ENXIO:
173 return CMD_STAT_BAD_SYS_STATE;
174 case -EBUSY:
175 return CMD_STAT_RESOURCE_BUSY;
176 case -ENOMEM:
177 return CMD_STAT_EXCEED_LIM;
178 case -ENFILE:
179 return CMD_STAT_ICM_ERROR;
180 default:
181 return CMD_STAT_INTERNAL_ERR;
182 }
183}
184
e8f081aa
YP		 185static int comm_pending(struct mlx4_dev *dev)
186{
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
189
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
191}
192
193static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
194{
195 struct mlx4_priv *priv = mlx4_priv(dev);
196 u32 val;
197
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
202 mmiowb();
203}
204
e8f081aa
YP		 205static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
207{
208 struct mlx4_priv *priv = mlx4_priv(dev);
209 unsigned long end;
210 int err = 0;
211 int ret_from_pending = 0;
212
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
1a91de28 215 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
e8f081aa
YP		 216 priv->cmd.comm_toggle, cmd);
217 return -EAGAIN;
218 }
219
220 /* Write command */
221 down(&priv->cmd.poll_sem);
222 mlx4_comm_cmd_post(dev, cmd, param);
223
224 end = msecs_to_jiffies(timeout) + jiffies;
225 while (comm_pending(dev) && time_before(jiffies, end))
226 cond_resched();
227 ret_from_pending = comm_pending(dev);
228 if (ret_from_pending) {
229 /* check if the slave is trying to boot in the middle of
230 * FLR process. The only non-zero result in the RESET command
231 * is MLX4_DELAY_RESET_SLAVE*/
232 if ((MLX4_COMM_CMD_RESET == cmd)) {
e8f081aa
YP		 233 err = MLX4_DELAY_RESET_SLAVE;
234 } else {
235 mlx4_warn(dev, "Communication channel timed out\n");
236 err = -ETIMEDOUT;
237 }
238 }
239
240 up(&priv->cmd.poll_sem);
241 return err;
242}
243
244static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
245 u16 param, unsigned long timeout)
246{
247 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
248 struct mlx4_cmd_context *context;
58a3de05 249 unsigned long end;
e8f081aa
YP		 250 int err = 0;
251
252 down(&cmd->event_sem);
253
254 spin_lock(&cmd->context_lock);
255 BUG_ON(cmd->free_head < 0);
256 context = &cmd->context[cmd->free_head];
257 context->token += cmd->token_mask + 1;
258 cmd->free_head = context->next;
259 spin_unlock(&cmd->context_lock);
260
261 init_completion(&context->done);
262
263 mlx4_comm_cmd_post(dev, op, param);
264
265 if (!wait_for_completion_timeout(&context->done,
266 msecs_to_jiffies(timeout))) {
674925ed
DB		 267 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
268 op);
e8f081aa
YP		 269 err = -EBUSY;
270 goto out;
271 }
272
273 err = context->result;
274 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
275 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
276 op, context->fw_status);
277 goto out;
278 }
279
280out:
58a3de05
EE		 281 /* wait for comm channel ready
282 * this is necessary for prevention the race
283 * when switching between event to polling mode
284 */
285 end = msecs_to_jiffies(timeout) + jiffies;
286 while (comm_pending(dev) && time_before(jiffies, end))
287 cond_resched();
288
e8f081aa
YP		 289 spin_lock(&cmd->context_lock);
290 context->next = cmd->free_head;
291 cmd->free_head = context - cmd->context;
292 spin_unlock(&cmd->context_lock);
293
294 up(&cmd->event_sem);
295 return err;
296}
297
ab9c17a0 298int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
e8f081aa
YP		 299 unsigned long timeout)
300{
301 if (mlx4_priv(dev)->cmd.use_events)
302 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
303 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
304}
305
225c7b1f
RD		 306static int cmd_pending(struct mlx4_dev *dev)
307{
57dbf29a
KSS		 308 u32 status;
309
310 if (pci_channel_offline(dev->pdev))
311 return -EIO;
312
313 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
225c7b1f
RD		 314
315 return (status & swab32(1 << HCR_GO_BIT)) ||
316 (mlx4_priv(dev)->cmd.toggle ==
317 !!(status & swab32(1 << HCR_T_BIT)));
318}
319
320static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
321 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
322 int event)
323{
324 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
325 u32 __iomem *hcr = cmd->hcr;
326 int ret = -EAGAIN;
327 unsigned long end;
328
329 mutex_lock(&cmd->hcr_mutex);
330
57dbf29a
KSS		 331 if (pci_channel_offline(dev->pdev)) {
332 /*
333 * Device is going through error recovery
334 * and cannot accept commands.
335 */
336 ret = -EIO;
337 goto out;
338 }
339
225c7b1f
RD		 340 end = jiffies;
341 if (event)
36ce10d3 342 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
225c7b1f
RD		 343
344 while (cmd_pending(dev)) {
57dbf29a
KSS		 345 if (pci_channel_offline(dev->pdev)) {
346 /*
347 * Device is going through error recovery
348 * and cannot accept commands.
349 */
350 ret = -EIO;
351 goto out;
352 }
353
e8f081aa
YP		 354 if (time_after_eq(jiffies, end)) {
355 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
225c7b1f 356 goto out;
e8f081aa 357 }
225c7b1f
RD		 358 cond_resched();
359 }
360
361 /*
362 * We use writel (instead of something like memcpy_toio)
363 * because writes of less than 32 bits to the HCR don't work
364 * (and some architectures such as ia64 implement memcpy_toio
365 * in terms of writeb).
366 */
367 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
368 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
369 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
370 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
371 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
372 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
373
374 /* __raw_writel may not order writes. */
375 wmb();
376
377 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
378 (cmd->toggle << HCR_T_BIT) |
379 (event ? (1 << HCR_E_BIT) : 0) |
380 (op_modifier << HCR_OPMOD_SHIFT) |
e8f081aa 381 op), hcr + 6);
2e61c646
RD		 382
383 /*
384 * Make sure that our HCR writes don't get mixed in with
385 * writes from another CPU starting a FW command.
386 */
387 mmiowb();
388
225c7b1f
RD		 389 cmd->toggle = cmd->toggle ^ 1;
390
391 ret = 0;
392
393out:
394 mutex_unlock(&cmd->hcr_mutex);
395 return ret;
396}
397
e8f081aa
YP		 398static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
399 int out_is_imm, u32 in_modifier, u8 op_modifier,
400 u16 op, unsigned long timeout)
401{
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
404 int ret;
405
f3d4c89e
RD		 406 mutex_lock(&priv->cmd.slave_cmd_mutex);
407
e8f081aa
YP		 408 vhcr->in_param = cpu_to_be64(in_param);
409 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
410 vhcr->in_modifier = cpu_to_be32(in_modifier);
411 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
412 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
413 vhcr->status = 0;
414 vhcr->flags = !!(priv->cmd.use_events) << 6;
f3d4c89e 415
e8f081aa
YP		 416 if (mlx4_is_master(dev)) {
417 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
418 if (!ret) {
419 if (out_is_imm) {
420 if (out_param)
421 *out_param =
422 be64_to_cpu(vhcr->out_param);
423 else {
1a91de28
JP		 424 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
425 op);
72be84f1 426 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 427 }
428 }
72be84f1 429 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa
YP		 430 }
431 } else {
432 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
433 MLX4_COMM_TIME + timeout);
434 if (!ret) {
435 if (out_is_imm) {
436 if (out_param)
437 *out_param =
438 be64_to_cpu(vhcr->out_param);
439 else {
1a91de28
JP		 440 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
441 op);
72be84f1 442 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 443 }
444 }
72be84f1 445 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa 446 } else
1a91de28
JP		 447 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n",
448 op);
e8f081aa 449 }
f3d4c89e
RD		 450
451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 452 return ret;
453}
454
225c7b1f
RD		 455static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
456 int out_is_imm, u32 in_modifier, u8 op_modifier,
457 u16 op, unsigned long timeout)
458{
459 struct mlx4_priv *priv = mlx4_priv(dev);
460 void __iomem *hcr = priv->cmd.hcr;
461 int err = 0;
462 unsigned long end;
e8f081aa 463 u32 stat;
225c7b1f
RD		 464
465 down(&priv->cmd.poll_sem);
466
57dbf29a
KSS		 467 if (pci_channel_offline(dev->pdev)) {
468 /*
469 * Device is going through error recovery
470 * and cannot accept commands.
471 */
472 err = -EIO;
473 goto out;
474 }
475
c05a116f
EP		 476 if (out_is_imm && !out_param) {
477 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
478 op);
479 err = -EINVAL;
480 goto out;
481 }
482
225c7b1f
RD		 483 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
484 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
485 if (err)
486 goto out;
487
488 end = msecs_to_jiffies(timeout) + jiffies;
57dbf29a
KSS		 489 while (cmd_pending(dev) && time_before(jiffies, end)) {
490 if (pci_channel_offline(dev->pdev)) {
491 /*
492 * Device is going through error recovery
493 * and cannot accept commands.
494 */
495 err = -EIO;
496 goto out;
497 }
498
225c7b1f 499 cond_resched();
57dbf29a 500 }
225c7b1f
RD		 501
502 if (cmd_pending(dev)) {
674925ed
DB		 503 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
504 op);
225c7b1f
RD		 505 err = -ETIMEDOUT;
506 goto out;
507 }
508
509 if (out_is_imm)
510 *out_param =
511 (u64) be32_to_cpu((__force __be32)
512 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
513 (u64) be32_to_cpu((__force __be32)
514 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
e8f081aa
YP		 515 stat = be32_to_cpu((__force __be32)
516 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
517 err = mlx4_status_to_errno(stat);
518 if (err)
519 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
520 op, stat);
225c7b1f
RD		 521
522out:
523 up(&priv->cmd.poll_sem);
524 return err;
525}
526
527void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
528{
529 struct mlx4_priv *priv = mlx4_priv(dev);
530 struct mlx4_cmd_context *context =
531 &priv->cmd.context[token & priv->cmd.token_mask];
532
533 /* previously timed out command completing at long last */
534 if (token != context->token)
535 return;
536
e8f081aa 537 context->fw_status = status;
225c7b1f
RD		 538 context->result = mlx4_status_to_errno(status);
539 context->out_param = out_param;
540
225c7b1f
RD		 541 complete(&context->done);
542}
543
544static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
545 int out_is_imm, u32 in_modifier, u8 op_modifier,
546 u16 op, unsigned long timeout)
547{
548 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
549 struct mlx4_cmd_context *context;
550 int err = 0;
551
552 down(&cmd->event_sem);
553
554 spin_lock(&cmd->context_lock);
555 BUG_ON(cmd->free_head < 0);
556 context = &cmd->context[cmd->free_head];
0981582d 557 context->token += cmd->token_mask + 1;
225c7b1f
RD		 558 cmd->free_head = context->next;
559 spin_unlock(&cmd->context_lock);
560
c05a116f
EP		 561 if (out_is_imm && !out_param) {
562 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
563 op);
564 err = -EINVAL;
565 goto out;
566 }
567
225c7b1f
RD		 568 init_completion(&context->done);
569
570 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
571 in_modifier, op_modifier, op, context->token, 1);
572
e8f081aa
YP		 573 if (!wait_for_completion_timeout(&context->done,
574 msecs_to_jiffies(timeout))) {
674925ed
DB		 575 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
576 op);
225c7b1f
RD		 577 err = -EBUSY;
578 goto out;
579 }
580
581 err = context->result;
e8f081aa
YP		 582 if (err) {
583 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
584 op, context->fw_status);
225c7b1f 585 goto out;
e8f081aa 586 }
225c7b1f
RD		 587
588 if (out_is_imm)
589 *out_param = context->out_param;
590
591out:
592 spin_lock(&cmd->context_lock);
593 context->next = cmd->free_head;
594 cmd->free_head = context - cmd->context;
595 spin_unlock(&cmd->context_lock);
596
597 up(&cmd->event_sem);
598 return err;
599}
600
601int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
602 int out_is_imm, u32 in_modifier, u8 op_modifier,
f9baff50 603 u16 op, unsigned long timeout, int native)
225c7b1f 604{
57dbf29a
KSS		 605 if (pci_channel_offline(dev->pdev))
606 return -EIO;
607
e8f081aa
YP		 608 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
609 if (mlx4_priv(dev)->cmd.use_events)
610 return mlx4_cmd_wait(dev, in_param, out_param,
611 out_is_imm, in_modifier,
612 op_modifier, op, timeout);
613 else
614 return mlx4_cmd_poll(dev, in_param, out_param,
615 out_is_imm, in_modifier,
616 op_modifier, op, timeout);
617 }
618 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
619 in_modifier, op_modifier, op, timeout);
225c7b1f
RD		 620}
621EXPORT_SYMBOL_GPL(__mlx4_cmd);
622
e8f081aa
YP		 623
624static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
625{
626 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
627 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
628}
629
630static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
631 int slave, u64 slave_addr,
632 int size, int is_read)
633{
634 u64 in_param;
635 u64 out_param;
636
637 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
638 (slave & ~0x7f) | (size & 0xff)) {
1a91de28
JP		 639 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
640 slave_addr, master_addr, slave, size);
e8f081aa
YP		 641 return -EINVAL;
642 }
643
644 if (is_read) {
645 in_param = (u64) slave | slave_addr;
646 out_param = (u64) dev->caps.function | master_addr;
647 } else {
648 in_param = (u64) dev->caps.function | master_addr;
649 out_param = (u64) slave | slave_addr;
650 }
651
652 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
653 MLX4_CMD_ACCESS_MEM,
654 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
655}
656
0a9a0188
JM		 657static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
658 struct mlx4_cmd_mailbox *inbox,
659 struct mlx4_cmd_mailbox *outbox)
660{
661 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
662 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
663 int err;
664 int i;
665
666 if (index & 0x1f)
667 return -EINVAL;
668
669 in_mad->attr_mod = cpu_to_be32(index / 32);
670
671 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
672 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
673 MLX4_CMD_NATIVE);
674 if (err)
675 return err;
676
677 for (i = 0; i < 32; ++i)
678 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
679
680 return err;
681}
682
683static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
684 struct mlx4_cmd_mailbox *inbox,
685 struct mlx4_cmd_mailbox *outbox)
686{
687 int i;
688 int err;
689
690 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
691 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
692 if (err)
693 return err;
694 }
695
696 return 0;
697}
698#define PORT_CAPABILITY_LOCATION_IN_SMP 20
699#define PORT_STATE_OFFSET 32
700
701static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
702{
a0c64a17
JM		 703 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
704 return IB_PORT_ACTIVE;
705 else
706 return IB_PORT_DOWN;
0a9a0188
JM		 707}
708
709static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
710 struct mlx4_vhcr *vhcr,
711 struct mlx4_cmd_mailbox *inbox,
712 struct mlx4_cmd_mailbox *outbox,
713 struct mlx4_cmd_info *cmd)
714{
715 struct ib_smp *smp = inbox->buf;
716 u32 index;
717 u8 port;
718 u16 *table;
719 int err;
720 int vidx, pidx;
721 struct mlx4_priv *priv = mlx4_priv(dev);
722 struct ib_smp *outsmp = outbox->buf;
723 __be16 *outtab = (__be16 *)(outsmp->data);
724 __be32 slave_cap_mask;
afa8fd1d 725 __be64 slave_node_guid;
0a9a0188
JM		 726 port = vhcr->in_modifier;
727
728 if (smp->base_version == 1 &&
729 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
730 smp->class_version == 1) {
731 if (smp->method == IB_MGMT_METHOD_GET) {
732 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
733 index = be32_to_cpu(smp->attr_mod);
734 if (port < 1 || port > dev->caps.num_ports)
735 return -EINVAL;
736 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
737 if (!table)
738 return -ENOMEM;
739 /* need to get the full pkey table because the paravirtualized
740 * pkeys may be scattered among several pkey blocks.
741 */
742 err = get_full_pkey_table(dev, port, table, inbox, outbox);
743 if (!err) {
744 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
745 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
746 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
747 }
748 }
749 kfree(table);
750 return err;
751 }
752 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
753 /*get the slave specific caps:*/
754 /*do the command */
755 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
756 vhcr->in_modifier, vhcr->op_modifier,
757 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
758 /* modify the response for slaves */
759 if (!err && slave != mlx4_master_func_num(dev)) {
760 u8 *state = outsmp->data + PORT_STATE_OFFSET;
761
762 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
763 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
764 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
765 }
766 return err;
767 }
768 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
769 /* compute slave's gid block */
770 smp->attr_mod = cpu_to_be32(slave / 8);
771 /* execute cmd */
772 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
773 vhcr->in_modifier, vhcr->op_modifier,
774 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
775 if (!err) {
776 /* if needed, move slave gid to index 0 */
777 if (slave % 8)
778 memcpy(outsmp->data,
779 outsmp->data + (slave % 8) * 8, 8);
780 /* delete all other gids */
781 memset(outsmp->data + 8, 0, 56);
782 }
783 return err;
784 }
afa8fd1d
JM		 785 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
786 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
787 vhcr->in_modifier, vhcr->op_modifier,
788 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
789 if (!err) {
790 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
791 memcpy(outsmp->data + 12, &slave_node_guid, 8);
792 }
793 return err;
794 }
0a9a0188
JM		 795 }
796 }
797 if (slave != mlx4_master_func_num(dev) &&
798 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
799 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
800 smp->method == IB_MGMT_METHOD_SET))) {
1a91de28 801 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x for attr 0x%x - Rejecting\n",
0a9a0188
JM		 802 slave, smp->method, smp->mgmt_class,
803 be16_to_cpu(smp->attr_id));
804 return -EPERM;
805 }
806 /*default:*/
807 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
808 vhcr->in_modifier, vhcr->op_modifier,
809 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
810}
811
b7475794 812static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
fe6f700d
YP		 813 struct mlx4_vhcr *vhcr,
814 struct mlx4_cmd_mailbox *inbox,
815 struct mlx4_cmd_mailbox *outbox,
816 struct mlx4_cmd_info *cmd)
817{
818 return -EPERM;
819}
820
e8f081aa
YP		 821int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
822 struct mlx4_vhcr *vhcr,
823 struct mlx4_cmd_mailbox *inbox,
824 struct mlx4_cmd_mailbox *outbox,
825 struct mlx4_cmd_info *cmd)
826{
827 u64 in_param;
828 u64 out_param;
829 int err;
830
831 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
832 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
833 if (cmd->encode_slave_id) {
834 in_param &= 0xffffffffffffff00ll;
835 in_param |= slave;
836 }
837
838 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
839 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
840 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
841
842 if (cmd->out_is_imm)
843 vhcr->out_param = out_param;
844
845 return err;
846}
847
848static struct mlx4_cmd_info cmd_info[] = {
849 {
850 .opcode = MLX4_CMD_QUERY_FW,
851 .has_inbox = false,
852 .has_outbox = true,
853 .out_is_imm = false,
854 .encode_slave_id = false,
855 .verify = NULL,
b91cb3eb 856 .wrapper = mlx4_QUERY_FW_wrapper
e8f081aa
YP		 857 },
858 {
859 .opcode = MLX4_CMD_QUERY_HCA,
860 .has_inbox = false,
861 .has_outbox = true,
862 .out_is_imm = false,
863 .encode_slave_id = false,
864 .verify = NULL,
865 .wrapper = NULL
866 },
867 {
868 .opcode = MLX4_CMD_QUERY_DEV_CAP,
869 .has_inbox = false,
870 .has_outbox = true,
871 .out_is_imm = false,
872 .encode_slave_id = false,
873 .verify = NULL,
b91cb3eb 874 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
e8f081aa 875 },
c82e9aa0
EC		 876 {
877 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
878 .has_inbox = false,
879 .has_outbox = true,
880 .out_is_imm = false,
881 .encode_slave_id = false,
882 .verify = NULL,
883 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
884 },
885 {
886 .opcode = MLX4_CMD_QUERY_ADAPTER,
887 .has_inbox = false,
888 .has_outbox = true,
889 .out_is_imm = false,
890 .encode_slave_id = false,
891 .verify = NULL,
892 .wrapper = NULL
893 },
894 {
895 .opcode = MLX4_CMD_INIT_PORT,
896 .has_inbox = false,
897 .has_outbox = false,
898 .out_is_imm = false,
899 .encode_slave_id = false,
900 .verify = NULL,
901 .wrapper = mlx4_INIT_PORT_wrapper
902 },
903 {
904 .opcode = MLX4_CMD_CLOSE_PORT,
905 .has_inbox = false,
906 .has_outbox = false,
907 .out_is_imm = false,
908 .encode_slave_id = false,
909 .verify = NULL,
910 .wrapper = mlx4_CLOSE_PORT_wrapper
911 },
912 {
913 .opcode = MLX4_CMD_QUERY_PORT,
914 .has_inbox = false,
915 .has_outbox = true,
916 .out_is_imm = false,
917 .encode_slave_id = false,
918 .verify = NULL,
919 .wrapper = mlx4_QUERY_PORT_wrapper
920 },
ffe455ad
EE		 921 {
922 .opcode = MLX4_CMD_SET_PORT,
923 .has_inbox = true,
924 .has_outbox = false,
925 .out_is_imm = false,
926 .encode_slave_id = false,
927 .verify = NULL,
928 .wrapper = mlx4_SET_PORT_wrapper
929 },
c82e9aa0
EC		 930 {
931 .opcode = MLX4_CMD_MAP_EQ,
932 .has_inbox = false,
933 .has_outbox = false,
934 .out_is_imm = false,
935 .encode_slave_id = false,
936 .verify = NULL,
937 .wrapper = mlx4_MAP_EQ_wrapper
938 },
939 {
940 .opcode = MLX4_CMD_SW2HW_EQ,
941 .has_inbox = true,
942 .has_outbox = false,
943 .out_is_imm = false,
944 .encode_slave_id = true,
945 .verify = NULL,
946 .wrapper = mlx4_SW2HW_EQ_wrapper
947 },
948 {
949 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
950 .has_inbox = false,
951 .has_outbox = false,
952 .out_is_imm = false,
953 .encode_slave_id = false,
954 .verify = NULL,
955 .wrapper = NULL
956 },
957 {
958 .opcode = MLX4_CMD_NOP,
959 .has_inbox = false,
960 .has_outbox = false,
961 .out_is_imm = false,
962 .encode_slave_id = false,
963 .verify = NULL,
964 .wrapper = NULL
965 },
d18f141a
OG		 966 {
967 .opcode = MLX4_CMD_CONFIG_DEV,
968 .has_inbox = false,
969 .has_outbox = false,
970 .out_is_imm = false,
971 .encode_slave_id = false,
972 .verify = NULL,
973 .wrapper = mlx4_CMD_EPERM_wrapper
974 },
c82e9aa0
EC		 975 {
976 .opcode = MLX4_CMD_ALLOC_RES,
977 .has_inbox = false,
978 .has_outbox = false,
979 .out_is_imm = true,
980 .encode_slave_id = false,
981 .verify = NULL,
982 .wrapper = mlx4_ALLOC_RES_wrapper
983 },
984 {
985 .opcode = MLX4_CMD_FREE_RES,
986 .has_inbox = false,
987 .has_outbox = false,
988 .out_is_imm = false,
989 .encode_slave_id = false,
990 .verify = NULL,
991 .wrapper = mlx4_FREE_RES_wrapper
992 },
993 {
994 .opcode = MLX4_CMD_SW2HW_MPT,
995 .has_inbox = true,
996 .has_outbox = false,
997 .out_is_imm = false,
998 .encode_slave_id = true,
999 .verify = NULL,
1000 .wrapper = mlx4_SW2HW_MPT_wrapper
1001 },
1002 {
1003 .opcode = MLX4_CMD_QUERY_MPT,
1004 .has_inbox = false,
1005 .has_outbox = true,
1006 .out_is_imm = false,
1007 .encode_slave_id = false,
1008 .verify = NULL,
1009 .wrapper = mlx4_QUERY_MPT_wrapper
1010 },
1011 {
1012 .opcode = MLX4_CMD_HW2SW_MPT,
1013 .has_inbox = false,
1014 .has_outbox = false,
1015 .out_is_imm = false,
1016 .encode_slave_id = false,
1017 .verify = NULL,
1018 .wrapper = mlx4_HW2SW_MPT_wrapper
1019 },
1020 {
1021 .opcode = MLX4_CMD_READ_MTT,
1022 .has_inbox = false,
1023 .has_outbox = true,
1024 .out_is_imm = false,
1025 .encode_slave_id = false,
1026 .verify = NULL,
1027 .wrapper = NULL
1028 },
1029 {
1030 .opcode = MLX4_CMD_WRITE_MTT,
1031 .has_inbox = true,
1032 .has_outbox = false,
1033 .out_is_imm = false,
1034 .encode_slave_id = false,
1035 .verify = NULL,
1036 .wrapper = mlx4_WRITE_MTT_wrapper
1037 },
1038 {
1039 .opcode = MLX4_CMD_SYNC_TPT,
1040 .has_inbox = true,
1041 .has_outbox = false,
1042 .out_is_imm = false,
1043 .encode_slave_id = false,
1044 .verify = NULL,
1045 .wrapper = NULL
1046 },
1047 {
1048 .opcode = MLX4_CMD_HW2SW_EQ,
1049 .has_inbox = false,
1050 .has_outbox = true,
1051 .out_is_imm = false,
1052 .encode_slave_id = true,
1053 .verify = NULL,
1054 .wrapper = mlx4_HW2SW_EQ_wrapper
1055 },
1056 {
1057 .opcode = MLX4_CMD_QUERY_EQ,
1058 .has_inbox = false,
1059 .has_outbox = true,
1060 .out_is_imm = false,
1061 .encode_slave_id = true,
1062 .verify = NULL,
1063 .wrapper = mlx4_QUERY_EQ_wrapper
1064 },
1065 {
1066 .opcode = MLX4_CMD_SW2HW_CQ,
1067 .has_inbox = true,
1068 .has_outbox = false,
1069 .out_is_imm = false,
1070 .encode_slave_id = true,
1071 .verify = NULL,
1072 .wrapper = mlx4_SW2HW_CQ_wrapper
1073 },
1074 {
1075 .opcode = MLX4_CMD_HW2SW_CQ,
1076 .has_inbox = false,
1077 .has_outbox = false,
1078 .out_is_imm = false,
1079 .encode_slave_id = false,
1080 .verify = NULL,
1081 .wrapper = mlx4_HW2SW_CQ_wrapper
1082 },
1083 {
1084 .opcode = MLX4_CMD_QUERY_CQ,
1085 .has_inbox = false,
1086 .has_outbox = true,
1087 .out_is_imm = false,
1088 .encode_slave_id = false,
1089 .verify = NULL,
1090 .wrapper = mlx4_QUERY_CQ_wrapper
1091 },
1092 {
1093 .opcode = MLX4_CMD_MODIFY_CQ,
1094 .has_inbox = true,
1095 .has_outbox = false,
1096 .out_is_imm = true,
1097 .encode_slave_id = false,
1098 .verify = NULL,
1099 .wrapper = mlx4_MODIFY_CQ_wrapper
1100 },
1101 {
1102 .opcode = MLX4_CMD_SW2HW_SRQ,
1103 .has_inbox = true,
1104 .has_outbox = false,
1105 .out_is_imm = false,
1106 .encode_slave_id = true,
1107 .verify = NULL,
1108 .wrapper = mlx4_SW2HW_SRQ_wrapper
1109 },
1110 {
1111 .opcode = MLX4_CMD_HW2SW_SRQ,
1112 .has_inbox = false,
1113 .has_outbox = false,
1114 .out_is_imm = false,
1115 .encode_slave_id = false,
1116 .verify = NULL,
1117 .wrapper = mlx4_HW2SW_SRQ_wrapper
1118 },
1119 {
1120 .opcode = MLX4_CMD_QUERY_SRQ,
1121 .has_inbox = false,
1122 .has_outbox = true,
1123 .out_is_imm = false,
1124 .encode_slave_id = false,
1125 .verify = NULL,
1126 .wrapper = mlx4_QUERY_SRQ_wrapper
1127 },
1128 {
1129 .opcode = MLX4_CMD_ARM_SRQ,
1130 .has_inbox = false,
1131 .has_outbox = false,
1132 .out_is_imm = false,
1133 .encode_slave_id = false,
1134 .verify = NULL,
1135 .wrapper = mlx4_ARM_SRQ_wrapper
1136 },
1137 {
1138 .opcode = MLX4_CMD_RST2INIT_QP,
1139 .has_inbox = true,
1140 .has_outbox = false,
1141 .out_is_imm = false,
1142 .encode_slave_id = true,
1143 .verify = NULL,
1144 .wrapper = mlx4_RST2INIT_QP_wrapper
1145 },
1146 {
1147 .opcode = MLX4_CMD_INIT2INIT_QP,
1148 .has_inbox = true,
1149 .has_outbox = false,
1150 .out_is_imm = false,
1151 .encode_slave_id = false,
1152 .verify = NULL,
54679e14 1153 .wrapper = mlx4_INIT2INIT_QP_wrapper
c82e9aa0
EC		 1154 },
1155 {
1156 .opcode = MLX4_CMD_INIT2RTR_QP,
1157 .has_inbox = true,
1158 .has_outbox = false,
1159 .out_is_imm = false,
1160 .encode_slave_id = false,
1161 .verify = NULL,
1162 .wrapper = mlx4_INIT2RTR_QP_wrapper
1163 },
1164 {
1165 .opcode = MLX4_CMD_RTR2RTS_QP,
1166 .has_inbox = true,
1167 .has_outbox = false,
1168 .out_is_imm = false,
1169 .encode_slave_id = false,
1170 .verify = NULL,
54679e14 1171 .wrapper = mlx4_RTR2RTS_QP_wrapper
c82e9aa0
EC		 1172 },
1173 {
1174 .opcode = MLX4_CMD_RTS2RTS_QP,
1175 .has_inbox = true,
1176 .has_outbox = false,
1177 .out_is_imm = false,
1178 .encode_slave_id = false,
1179 .verify = NULL,
54679e14 1180 .wrapper = mlx4_RTS2RTS_QP_wrapper
c82e9aa0
EC		 1181 },
1182 {
1183 .opcode = MLX4_CMD_SQERR2RTS_QP,
1184 .has_inbox = true,
1185 .has_outbox = false,
1186 .out_is_imm = false,
1187 .encode_slave_id = false,
1188 .verify = NULL,
54679e14 1189 .wrapper = mlx4_SQERR2RTS_QP_wrapper
c82e9aa0
EC		 1190 },
1191 {
1192 .opcode = MLX4_CMD_2ERR_QP,
1193 .has_inbox = false,
1194 .has_outbox = false,
1195 .out_is_imm = false,
1196 .encode_slave_id = false,
1197 .verify = NULL,
1198 .wrapper = mlx4_GEN_QP_wrapper
1199 },
1200 {
1201 .opcode = MLX4_CMD_RTS2SQD_QP,
1202 .has_inbox = false,
1203 .has_outbox = false,
1204 .out_is_imm = false,
1205 .encode_slave_id = false,
1206 .verify = NULL,
1207 .wrapper = mlx4_GEN_QP_wrapper
1208 },
1209 {
1210 .opcode = MLX4_CMD_SQD2SQD_QP,
1211 .has_inbox = true,
1212 .has_outbox = false,
1213 .out_is_imm = false,
1214 .encode_slave_id = false,
1215 .verify = NULL,
54679e14 1216 .wrapper = mlx4_SQD2SQD_QP_wrapper
c82e9aa0
EC		 1217 },
1218 {
1219 .opcode = MLX4_CMD_SQD2RTS_QP,
1220 .has_inbox = true,
1221 .has_outbox = false,
1222 .out_is_imm = false,
1223 .encode_slave_id = false,
1224 .verify = NULL,
54679e14 1225 .wrapper = mlx4_SQD2RTS_QP_wrapper
c82e9aa0
EC		 1226 },
1227 {
1228 .opcode = MLX4_CMD_2RST_QP,
1229 .has_inbox = false,
1230 .has_outbox = false,
1231 .out_is_imm = false,
1232 .encode_slave_id = false,
1233 .verify = NULL,
1234 .wrapper = mlx4_2RST_QP_wrapper
1235 },
1236 {
1237 .opcode = MLX4_CMD_QUERY_QP,
1238 .has_inbox = false,
1239 .has_outbox = true,
1240 .out_is_imm = false,
1241 .encode_slave_id = false,
1242 .verify = NULL,
1243 .wrapper = mlx4_GEN_QP_wrapper
1244 },
1245 {
1246 .opcode = MLX4_CMD_SUSPEND_QP,
1247 .has_inbox = false,
1248 .has_outbox = false,
1249 .out_is_imm = false,
1250 .encode_slave_id = false,
1251 .verify = NULL,
1252 .wrapper = mlx4_GEN_QP_wrapper
1253 },
1254 {
1255 .opcode = MLX4_CMD_UNSUSPEND_QP,
1256 .has_inbox = false,
1257 .has_outbox = false,
1258 .out_is_imm = false,
1259 .encode_slave_id = false,
1260 .verify = NULL,
1261 .wrapper = mlx4_GEN_QP_wrapper
1262 },
b01978ca
JM		 1263 {
1264 .opcode = MLX4_CMD_UPDATE_QP,
1265 .has_inbox = false,
1266 .has_outbox = false,
1267 .out_is_imm = false,
1268 .encode_slave_id = false,
1269 .verify = NULL,
b7475794 1270 .wrapper = mlx4_CMD_EPERM_wrapper
b01978ca 1271 },
fe6f700d
YP		 1272 {
1273 .opcode = MLX4_CMD_GET_OP_REQ,
1274 .has_inbox = false,
1275 .has_outbox = false,
1276 .out_is_imm = false,
1277 .encode_slave_id = false,
1278 .verify = NULL,
b7475794 1279 .wrapper = mlx4_CMD_EPERM_wrapper,
fe6f700d 1280 },
0a9a0188
JM		 1281 {
1282 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1283 .has_inbox = false,
1284 .has_outbox = false,
1285 .out_is_imm = false,
1286 .encode_slave_id = false,
1287 .verify = NULL, /* XXX verify: only demux can do this */
1288 .wrapper = NULL
1289 },
1290 {
1291 .opcode = MLX4_CMD_MAD_IFC,
1292 .has_inbox = true,
1293 .has_outbox = true,
1294 .out_is_imm = false,
1295 .encode_slave_id = false,
1296 .verify = NULL,
1297 .wrapper = mlx4_MAD_IFC_wrapper
1298 },
c82e9aa0
EC		 1299 {
1300 .opcode = MLX4_CMD_QUERY_IF_STAT,
1301 .has_inbox = false,
1302 .has_outbox = true,
1303 .out_is_imm = false,
1304 .encode_slave_id = false,
1305 .verify = NULL,
1306 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1307 },
1308 /* Native multicast commands are not available for guests */
1309 {
1310 .opcode = MLX4_CMD_QP_ATTACH,
1311 .has_inbox = true,
1312 .has_outbox = false,
1313 .out_is_imm = false,
1314 .encode_slave_id = false,
1315 .verify = NULL,
1316 .wrapper = mlx4_QP_ATTACH_wrapper
1317 },
0ec2c0f8
EE		 1318 {
1319 .opcode = MLX4_CMD_PROMISC,
1320 .has_inbox = false,
1321 .has_outbox = false,
1322 .out_is_imm = false,
1323 .encode_slave_id = false,
1324 .verify = NULL,
1325 .wrapper = mlx4_PROMISC_wrapper
1326 },
ffe455ad
EE		 1327 /* Ethernet specific commands */
1328 {
1329 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1330 .has_inbox = true,
1331 .has_outbox = false,
1332 .out_is_imm = false,
1333 .encode_slave_id = false,
1334 .verify = NULL,
1335 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1336 },
1337 {
1338 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1339 .has_inbox = false,
1340 .has_outbox = false,
1341 .out_is_imm = false,
1342 .encode_slave_id = false,
1343 .verify = NULL,
1344 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1345 },
1346 {
1347 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1348 .has_inbox = false,
1349 .has_outbox = true,
1350 .out_is_imm = false,
1351 .encode_slave_id = false,
1352 .verify = NULL,
1353 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1354 },
c82e9aa0
EC		 1355 {
1356 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1357 .has_inbox = false,
1358 .has_outbox = false,
1359 .out_is_imm = false,
1360 .encode_slave_id = false,
1361 .verify = NULL,
1362 .wrapper = NULL
1363 },
8fcfb4db
HHZ		 1364 /* flow steering commands */
1365 {
1366 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1367 .has_inbox = true,
1368 .has_outbox = false,
1369 .out_is_imm = true,
1370 .encode_slave_id = false,
1371 .verify = NULL,
1372 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1373 },
1374 {
1375 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1376 .has_inbox = false,
1377 .has_outbox = false,
1378 .out_is_imm = false,
1379 .encode_slave_id = false,
1380 .verify = NULL,
1381 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1382 },
4de65803
MB		 1383 {
1384 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1385 .has_inbox = false,
1386 .has_outbox = false,
1387 .out_is_imm = false,
1388 .encode_slave_id = false,
1389 .verify = NULL,
b7475794 1390 .wrapper = mlx4_CMD_EPERM_wrapper
4de65803 1391 },
e8f081aa
YP		 1392};
1393
1394static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1395 struct mlx4_vhcr_cmd *in_vhcr)
1396{
1397 struct mlx4_priv *priv = mlx4_priv(dev);
1398 struct mlx4_cmd_info *cmd = NULL;
1399 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1400 struct mlx4_vhcr *vhcr;
1401 struct mlx4_cmd_mailbox *inbox = NULL;
1402 struct mlx4_cmd_mailbox *outbox = NULL;
1403 u64 in_param;
1404 u64 out_param;
1405 int ret = 0;
1406 int i;
72be84f1 1407 int err = 0;
e8f081aa
YP		 1408
1409 /* Create sw representation of Virtual HCR */
1410 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1411 if (!vhcr)
1412 return -ENOMEM;
1413
1414 /* DMA in the vHCR */
1415 if (!in_vhcr) {
1416 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1417 priv->mfunc.master.slave_state[slave].vhcr_dma,
1418 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1419 MLX4_ACCESS_MEM_ALIGN), 1);
1420 if (ret) {
1a91de28
JP		 1421 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1422 __func__, ret);
e8f081aa
YP		 1423 kfree(vhcr);
1424 return ret;
1425 }
1426 }
1427
1428 /* Fill SW VHCR fields */
1429 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1430 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1431 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1432 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1433 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1434 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1435 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1436
1437 /* Lookup command */
1438 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1439 if (vhcr->op == cmd_info[i].opcode) {
1440 cmd = &cmd_info[i];
1441 break;
1442 }
1443 }
1444 if (!cmd) {
1445 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1446 vhcr->op, slave);
72be84f1 1447 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 1448 goto out_status;
1449 }
1450
1451 /* Read inbox */
1452 if (cmd->has_inbox) {
1453 vhcr->in_param &= INBOX_MASK;
1454 inbox = mlx4_alloc_cmd_mailbox(dev);
1455 if (IS_ERR(inbox)) {
72be84f1 1456 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1457 inbox = NULL;
72be84f1 1458 goto out_status;
e8f081aa
YP		 1459 }
1460
72be84f1
YP		 1461 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1462 vhcr->in_param,
1463 MLX4_MAILBOX_SIZE, 1)) {
e8f081aa
YP		 1464 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1465 __func__, cmd->opcode);
72be84f1
YP		 1466 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1467 goto out_status;
e8f081aa
YP		 1468 }
1469 }
1470
1471 /* Apply permission and bound checks if applicable */
1472 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1a91de28
JP		 1473 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1474 vhcr->op, slave, vhcr->in_modifier);
72be84f1 1475 vhcr_cmd->status = CMD_STAT_BAD_OP;
e8f081aa
YP		 1476 goto out_status;
1477 }
1478
1479 /* Allocate outbox */
1480 if (cmd->has_outbox) {
1481 outbox = mlx4_alloc_cmd_mailbox(dev);
1482 if (IS_ERR(outbox)) {
72be84f1 1483 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1484 outbox = NULL;
72be84f1 1485 goto out_status;
e8f081aa
YP		 1486 }
1487 }
1488
1489 /* Execute the command! */
1490 if (cmd->wrapper) {
72be84f1
YP		 1491 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1492 cmd);
e8f081aa
YP		 1493 if (cmd->out_is_imm)
1494 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1495 } else {
1496 in_param = cmd->has_inbox ? (u64) inbox->dma :
1497 vhcr->in_param;
1498 out_param = cmd->has_outbox ? (u64) outbox->dma :
1499 vhcr->out_param;
72be84f1
YP		 1500 err = __mlx4_cmd(dev, in_param, &out_param,
1501 cmd->out_is_imm, vhcr->in_modifier,
1502 vhcr->op_modifier, vhcr->op,
1503 MLX4_CMD_TIME_CLASS_A,
1504 MLX4_CMD_NATIVE);
e8f081aa
YP		 1505
1506 if (cmd->out_is_imm) {
1507 vhcr->out_param = out_param;
1508 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1509 }
1510 }
1511
72be84f1 1512 if (err) {
1a91de28 1513 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
72be84f1
YP		 1514 vhcr->op, slave, vhcr->errno, err);
1515 vhcr_cmd->status = mlx4_errno_to_status(err);
1516 goto out_status;
1517 }
1518
1519
e8f081aa 1520 /* Write outbox if command completed successfully */
72be84f1 1521 if (cmd->has_outbox && !vhcr_cmd->status) {
e8f081aa
YP		 1522 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1523 vhcr->out_param,
1524 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1525 if (ret) {
72be84f1
YP		 1526 /* If we failed to write back the outbox after the
1527 *command was successfully executed, we must fail this
1528 * slave, as it is now in undefined state */
e8f081aa
YP		 1529 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1530 goto out;
1531 }
1532 }
1533
1534out_status:
1535 /* DMA back vhcr result */
1536 if (!in_vhcr) {
1537 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1538 priv->mfunc.master.slave_state[slave].vhcr_dma,
1539 ALIGN(sizeof(struct mlx4_vhcr),
1540 MLX4_ACCESS_MEM_ALIGN),
1541 MLX4_CMD_WRAPPED);
1542 if (ret)
1543 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1544 __func__);
1545 else if (vhcr->e_bit &&
1546 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1a91de28
JP		 1547 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1548 slave);
e8f081aa
YP		 1549 }
1550
1551out:
1552 kfree(vhcr);
1553 mlx4_free_cmd_mailbox(dev, inbox);
1554 mlx4_free_cmd_mailbox(dev, outbox);
1555 return ret;
1556}
1557
f094668c 1558static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
b01978ca
JM		 1559 int slave, int port)
1560{
1561 struct mlx4_vport_oper_state *vp_oper;
1562 struct mlx4_vport_state *vp_admin;
1563 struct mlx4_vf_immed_vlan_work *work;
0a6eac24 1564 struct mlx4_dev *dev = &(priv->dev);
b01978ca
JM		 1565 int err;
1566 int admin_vlan_ix = NO_INDX;
1567
1568 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1569 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1570
1571 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
0a6eac24
RE		 1572 vp_oper->state.default_qos == vp_admin->default_qos &&
1573 vp_oper->state.link_state == vp_admin->link_state)
b01978ca
JM		 1574 return 0;
1575
0a6eac24 1576 if (!(priv->mfunc.master.slave_state[slave].active &&
f0f829bf 1577 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
0a6eac24
RE		 1578 /* even if the UPDATE_QP command isn't supported, we still want
1579 * to set this VF link according to the admin directive
1580 */
1581 vp_oper->state.link_state = vp_admin->link_state;
1582 return -1;
1583 }
1584
1585 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1586 slave, port);
1a91de28
JP		 1587 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1588 vp_admin->default_vlan, vp_admin->default_qos,
1589 vp_admin->link_state);
0a6eac24 1590
b01978ca
JM		 1591 work = kzalloc(sizeof(*work), GFP_KERNEL);
1592 if (!work)
1593 return -ENOMEM;
1594
1595 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
f0f829bf
RE		 1596 if (MLX4_VGT != vp_admin->default_vlan) {
1597 err = __mlx4_register_vlan(&priv->dev, port,
1598 vp_admin->default_vlan,
1599 &admin_vlan_ix);
1600 if (err) {
1601 kfree(work);
1a91de28 1602 mlx4_warn(&priv->dev,
f0f829bf
RE		 1603 "No vlan resources slave %d, port %d\n",
1604 slave, port);
1605 return err;
1606 }
1607 } else {
1608 admin_vlan_ix = NO_INDX;
b01978ca
JM		 1609 }
1610 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1a91de28 1611 mlx4_dbg(&priv->dev,
b01978ca
JM		 1612 "alloc vlan %d idx %d slave %d port %d\n",
1613 (int)(vp_admin->default_vlan),
1614 admin_vlan_ix, slave, port);
1615 }
1616
1617 /* save original vlan ix and vlan id */
1618 work->orig_vlan_id = vp_oper->state.default_vlan;
1619 work->orig_vlan_ix = vp_oper->vlan_idx;
1620
1621 /* handle new qos */
1622 if (vp_oper->state.default_qos != vp_admin->default_qos)
1623 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1624
1625 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1626 vp_oper->vlan_idx = admin_vlan_ix;
1627
1628 vp_oper->state.default_vlan = vp_admin->default_vlan;
1629 vp_oper->state.default_qos = vp_admin->default_qos;
0a6eac24
RE		 1630 vp_oper->state.link_state = vp_admin->link_state;
1631
1632 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1633 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
b01978ca
JM		 1634
1635 /* iterate over QPs owned by this slave, using UPDATE_QP */
1636 work->port = port;
1637 work->slave = slave;
1638 work->qos = vp_oper->state.default_qos;
1639 work->vlan_id = vp_oper->state.default_vlan;
1640 work->vlan_ix = vp_oper->vlan_idx;
1641 work->priv = priv;
1642 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1643 queue_work(priv->mfunc.master.comm_wq, &work->work);
1644
1645 return 0;
1646}
1647
1648
0eb62b93
RE		 1649static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1650{
3f7fb021
RE		 1651 int port, err;
1652 struct mlx4_vport_state *vp_admin;
1653 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1654 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1655 &priv->dev, slave);
1656 int min_port = find_first_bit(actv_ports.ports,
1657 priv->dev.caps.num_ports) + 1;
1658 int max_port = min_port - 1 +
1659 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1660
1661 for (port = min_port; port <= max_port; port++) {
1662 if (!test_bit(port - 1, actv_ports.ports))
1663 continue;
3f7fb021
RE		 1664 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1665 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1666 vp_oper->state = *vp_admin;
1667 if (MLX4_VGT != vp_admin->default_vlan) {
1668 err = __mlx4_register_vlan(&priv->dev, port,
1669 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1670 if (err) {
1671 vp_oper->vlan_idx = NO_INDX;
1a91de28 1672 mlx4_warn(&priv->dev,
3f7fb021
RE		 1673 "No vlan resorces slave %d, port %d\n",
1674 slave, port);
1675 return err;
1676 }
1a91de28 1677 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
3f7fb021
RE		 1678 (int)(vp_oper->state.default_vlan),
1679 vp_oper->vlan_idx, slave, port);
1680 }
e6b6a231
RE		 1681 if (vp_admin->spoofchk) {
1682 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1683 port,
1684 vp_admin->mac);
1685 if (0 > vp_oper->mac_idx) {
1686 err = vp_oper->mac_idx;
1687 vp_oper->mac_idx = NO_INDX;
1a91de28 1688 mlx4_warn(&priv->dev,
e6b6a231
RE		 1689 "No mac resorces slave %d, port %d\n",
1690 slave, port);
1691 return err;
1692 }
1a91de28 1693 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
e6b6a231
RE		 1694 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1695 }
0eb62b93
RE		 1696 }
1697 return 0;
1698}
1699
3f7fb021
RE		 1700static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1701{
1702 int port;
1703 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1704 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1705 &priv->dev, slave);
1706 int min_port = find_first_bit(actv_ports.ports,
1707 priv->dev.caps.num_ports) + 1;
1708 int max_port = min_port - 1 +
1709 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1710
3f7fb021 1711
449fc488
MB		 1712 for (port = min_port; port <= max_port; port++) {
1713 if (!test_bit(port - 1, actv_ports.ports))
1714 continue;
3f7fb021
RE		 1715 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1716 if (NO_INDX != vp_oper->vlan_idx) {
1717 __mlx4_unregister_vlan(&priv->dev,
2009d005 1718 port, vp_oper->state.default_vlan);
3f7fb021
RE		 1719 vp_oper->vlan_idx = NO_INDX;
1720 }
e6b6a231 1721 if (NO_INDX != vp_oper->mac_idx) {
c32b7dfb 1722 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
e6b6a231
RE		 1723 vp_oper->mac_idx = NO_INDX;
1724 }
3f7fb021
RE		 1725 }
1726 return;
1727}
1728
e8f081aa
YP		 1729static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1730 u16 param, u8 toggle)
1731{
1732 struct mlx4_priv *priv = mlx4_priv(dev);
1733 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1734 u32 reply;
e8f081aa 1735 u8 is_going_down = 0;
803143fb 1736 int i;
311f813a 1737 unsigned long flags;
e8f081aa
YP		 1738
1739 slave_state[slave].comm_toggle ^= 1;
1740 reply = (u32) slave_state[slave].comm_toggle << 31;
1741 if (toggle != slave_state[slave].comm_toggle) {
1a91de28
JP		 1742 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1743 toggle, slave);
e8f081aa
YP		 1744 goto reset_slave;
1745 }
1746 if (cmd == MLX4_COMM_CMD_RESET) {
1747 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1748 slave_state[slave].active = false;
2c957ff2 1749 slave_state[slave].old_vlan_api = false;
3f7fb021 1750 mlx4_master_deactivate_admin_state(priv, slave);
803143fb
MA		 1751 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1752 slave_state[slave].event_eq[i].eqn = -1;
1753 slave_state[slave].event_eq[i].token = 0;
1754 }
e8f081aa
YP		 1755 /*check if we are in the middle of FLR process,
1756 if so return "retry" status to the slave*/
162344ed 1757 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
e8f081aa 1758 goto inform_slave_state;
e8f081aa 1759
fc06573d
JM		 1760 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1761
e8f081aa
YP		 1762 /* write the version in the event field */
1763 reply |= mlx4_comm_get_version();
1764
1765 goto reset_slave;
1766 }
1767 /*command from slave in the middle of FLR*/
1768 if (cmd != MLX4_COMM_CMD_RESET &&
1769 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1a91de28
JP		 1770 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1771 slave, cmd);
e8f081aa
YP		 1772 return;
1773 }
1774
1775 switch (cmd) {
1776 case MLX4_COMM_CMD_VHCR0:
1777 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1778 goto reset_slave;
1779 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1780 priv->mfunc.master.slave_state[slave].cookie = 0;
1781 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1782 break;
1783 case MLX4_COMM_CMD_VHCR1:
1784 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1785 goto reset_slave;
1786 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1787 break;
1788 case MLX4_COMM_CMD_VHCR2:
1789 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1790 goto reset_slave;
1791 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1792 break;
1793 case MLX4_COMM_CMD_VHCR_EN:
1794 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1795 goto reset_slave;
1796 slave_state[slave].vhcr_dma |= param;
3f7fb021
RE		 1797 if (mlx4_master_activate_admin_state(priv, slave))
1798 goto reset_slave;
e8f081aa 1799 slave_state[slave].active = true;
fc06573d 1800 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
e8f081aa
YP		 1801 break;
1802 case MLX4_COMM_CMD_VHCR_POST:
1803 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1804 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1805 goto reset_slave;
f3d4c89e
RD		 1806
1807 mutex_lock(&priv->cmd.slave_cmd_mutex);
e8f081aa 1808 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1a91de28
JP		 1809 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
1810 slave);
f3d4c89e 1811 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1812 goto reset_slave;
1813 }
f3d4c89e 1814 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1815 break;
1816 default:
1817 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1818 goto reset_slave;
1819 }
311f813a 1820 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1821 if (!slave_state[slave].is_slave_going_down)
1822 slave_state[slave].last_cmd = cmd;
1823 else
1824 is_going_down = 1;
311f813a 1825 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa 1826 if (is_going_down) {
1a91de28 1827 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
e8f081aa
YP		 1828 cmd, slave);
1829 return;
1830 }
1831 __raw_writel((__force u32) cpu_to_be32(reply),
1832 &priv->mfunc.comm[slave].slave_read);
1833 mmiowb();
1834
1835 return;
1836
1837reset_slave:
c82e9aa0
EC		 1838 /* cleanup any slave resources */
1839 mlx4_delete_all_resources_for_slave(dev, slave);
311f813a 1840 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1841 if (!slave_state[slave].is_slave_going_down)
1842 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
311f813a 1843 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1844 /*with slave in the middle of flr, no need to clean resources again.*/
1845inform_slave_state:
1846 memset(&slave_state[slave].event_eq, 0,
1847 sizeof(struct mlx4_slave_event_eq_info));
1848 __raw_writel((__force u32) cpu_to_be32(reply),
1849 &priv->mfunc.comm[slave].slave_read);
1850 wmb();
1851}
1852
1853/* master command processing */
1854void mlx4_master_comm_channel(struct work_struct *work)
1855{
1856 struct mlx4_mfunc_master_ctx *master =
1857 container_of(work,
1858 struct mlx4_mfunc_master_ctx,
1859 comm_work);
1860 struct mlx4_mfunc *mfunc =
1861 container_of(master, struct mlx4_mfunc, master);
1862 struct mlx4_priv *priv =
1863 container_of(mfunc, struct mlx4_priv, mfunc);
1864 struct mlx4_dev *dev = &priv->dev;
1865 __be32 *bit_vec;
1866 u32 comm_cmd;
1867 u32 vec;
1868 int i, j, slave;
1869 int toggle;
1870 int served = 0;
1871 int reported = 0;
1872 u32 slt;
1873
1874 bit_vec = master->comm_arm_bit_vector;
1875 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1876 vec = be32_to_cpu(bit_vec[i]);
1877 for (j = 0; j < 32; j++) {
1878 if (!(vec & (1 << j)))
1879 continue;
1880 ++reported;
1881 slave = (i * 32) + j;
1882 comm_cmd = swab32(readl(
1883 &mfunc->comm[slave].slave_write));
1884 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1885 >> 31;
1886 toggle = comm_cmd >> 31;
1887 if (toggle != slt) {
1888 if (master->slave_state[slave].comm_toggle
1889 != slt) {
c20862c8
AV		 1890 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
1891 slave, slt,
1892 master->slave_state[slave].comm_toggle);
e8f081aa
YP		 1893 master->slave_state[slave].comm_toggle =
1894 slt;
1895 }
1896 mlx4_master_do_cmd(dev, slave,
1897 comm_cmd >> 16 & 0xff,
1898 comm_cmd & 0xffff, toggle);
1899 ++served;
1900 }
1901 }
1902 }
1903
1904 if (reported && reported != served)
1a91de28 1905 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
e8f081aa
YP		 1906 reported, served);
1907
1908 if (mlx4_ARM_COMM_CHANNEL(dev))
1909 mlx4_warn(dev, "Failed to arm comm channel events\n");
1910}
1911
ab9c17a0
JM		 1912static int sync_toggles(struct mlx4_dev *dev)
1913{
1914 struct mlx4_priv *priv = mlx4_priv(dev);
1915 int wr_toggle;
1916 int rd_toggle;
1917 unsigned long end;
1918
1919 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1920 end = jiffies + msecs_to_jiffies(5000);
1921
1922 while (time_before(jiffies, end)) {
1923 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1924 if (rd_toggle == wr_toggle) {
1925 priv->cmd.comm_toggle = rd_toggle;
1926 return 0;
1927 }
1928
1929 cond_resched();
1930 }
1931
1932 /*
1933 * we could reach here if for example the previous VM using this
1934 * function misbehaved and left the channel with unsynced state. We
1935 * should fix this here and give this VM a chance to use a properly
1936 * synced channel
1937 */
1938 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1939 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1940 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1941 priv->cmd.comm_toggle = 0;
1942
1943 return 0;
1944}
1945
1946int mlx4_multi_func_init(struct mlx4_dev *dev)
1947{
1948 struct mlx4_priv *priv = mlx4_priv(dev);
1949 struct mlx4_slave_state *s_state;
803143fb 1950 int i, j, err, port;
ab9c17a0 1951
ab9c17a0
JM		 1952 if (mlx4_is_master(dev))
1953 priv->mfunc.comm =
1954 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1955 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1956 else
1957 priv->mfunc.comm =
1958 ioremap(pci_resource_start(dev->pdev, 2) +
1959 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1960 if (!priv->mfunc.comm) {
1a91de28 1961 mlx4_err(dev, "Couldn't map communication vector\n");
ab9c17a0
JM		 1962 goto err_vhcr;
1963 }
1964
1965 if (mlx4_is_master(dev)) {
1966 priv->mfunc.master.slave_state =
1967 kzalloc(dev->num_slaves *
1968 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1969 if (!priv->mfunc.master.slave_state)
1970 goto err_comm;
1971
0eb62b93
RE		 1972 priv->mfunc.master.vf_admin =
1973 kzalloc(dev->num_slaves *
1974 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1975 if (!priv->mfunc.master.vf_admin)
1976 goto err_comm_admin;
1977
1978 priv->mfunc.master.vf_oper =
1979 kzalloc(dev->num_slaves *
1980 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1981 if (!priv->mfunc.master.vf_oper)
1982 goto err_comm_oper;
1983
ab9c17a0
JM		 1984 for (i = 0; i < dev->num_slaves; ++i) {
1985 s_state = &priv->mfunc.master.slave_state[i];
1986 s_state->last_cmd = MLX4_COMM_CMD_RESET;
803143fb
MA		 1987 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1988 s_state->event_eq[j].eqn = -1;
ab9c17a0
JM		 1989 __raw_writel((__force u32) 0,
1990 &priv->mfunc.comm[i].slave_write);
1991 __raw_writel((__force u32) 0,
1992 &priv->mfunc.comm[i].slave_read);
1993 mmiowb();
1994 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1995 s_state->vlan_filter[port] =
1996 kzalloc(sizeof(struct mlx4_vlan_fltr),
1997 GFP_KERNEL);
1998 if (!s_state->vlan_filter[port]) {
1999 if (--port)
2000 kfree(s_state->vlan_filter[port]);
2001 goto err_slaves;
2002 }
2003 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
0eb62b93 2004 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
3f7fb021 2005 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
0eb62b93
RE		 2006 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2007 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
ab9c17a0
JM		 2008 }
2009 spin_lock_init(&s_state->lock);
2010 }
2011
08ff3235 2012 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
ab9c17a0
JM		 2013 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2014 INIT_WORK(&priv->mfunc.master.comm_work,
2015 mlx4_master_comm_channel);
2016 INIT_WORK(&priv->mfunc.master.slave_event_work,
2017 mlx4_gen_slave_eqe);
2018 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2019 mlx4_master_handle_slave_flr);
2020 spin_lock_init(&priv->mfunc.master.slave_state_lock);
992e8e6e 2021 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
ab9c17a0
JM		 2022 priv->mfunc.master.comm_wq =
2023 create_singlethread_workqueue("mlx4_comm");
2024 if (!priv->mfunc.master.comm_wq)
2025 goto err_slaves;
2026
2027 if (mlx4_init_resource_tracker(dev))
2028 goto err_thread;
2029
ab9c17a0
JM		 2030 err = mlx4_ARM_COMM_CHANNEL(dev);
2031 if (err) {
2032 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2033 err);
2034 goto err_resource;
2035 }
2036
2037 } else {
2038 err = sync_toggles(dev);
2039 if (err) {
2040 mlx4_err(dev, "Couldn't sync toggles\n");
2041 goto err_comm;
2042 }
ab9c17a0
JM		 2043 }
2044 return 0;
2045
2046err_resource:
b8924951 2047 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
ab9c17a0
JM		 2048err_thread:
2049 flush_workqueue(priv->mfunc.master.comm_wq);
2050 destroy_workqueue(priv->mfunc.master.comm_wq);
2051err_slaves:
2052 while (--i) {
2053 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2054 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2055 }
0eb62b93
RE		 2056 kfree(priv->mfunc.master.vf_oper);
2057err_comm_oper:
2058 kfree(priv->mfunc.master.vf_admin);
2059err_comm_admin:
ab9c17a0
JM		 2060 kfree(priv->mfunc.master.slave_state);
2061err_comm:
2062 iounmap(priv->mfunc.comm);
2063err_vhcr:
2064 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2065 priv->mfunc.vhcr,
2066 priv->mfunc.vhcr_dma);
2067 priv->mfunc.vhcr = NULL;
2068 return -ENOMEM;
2069}
2070
225c7b1f
RD		 2071int mlx4_cmd_init(struct mlx4_dev *dev)
2072{
2073 struct mlx4_priv *priv = mlx4_priv(dev);
2074
2075 mutex_init(&priv->cmd.hcr_mutex);
f3d4c89e 2076 mutex_init(&priv->cmd.slave_cmd_mutex);
225c7b1f
RD		 2077 sema_init(&priv->cmd.poll_sem, 1);
2078 priv->cmd.use_events = 0;
2079 priv->cmd.toggle = 1;
2080
e8f081aa
YP		 2081 priv->cmd.hcr = NULL;
2082 priv->mfunc.vhcr = NULL;
2083
2084 if (!mlx4_is_slave(dev)) {
2085 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2086 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2087 if (!priv->cmd.hcr) {
1a91de28 2088 mlx4_err(dev, "Couldn't map command register\n");
e8f081aa
YP		 2089 return -ENOMEM;
2090 }
225c7b1f
RD		 2091 }
2092
f3d4c89e
RD		 2093 if (mlx4_is_mfunc(dev)) {
2094 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2095 &priv->mfunc.vhcr_dma,
2096 GFP_KERNEL);
d0320f75 2097 if (!priv->mfunc.vhcr)
f3d4c89e 2098 goto err_hcr;
f3d4c89e
RD		 2099 }
2100
225c7b1f
RD		 2101 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2102 MLX4_MAILBOX_SIZE,
2103 MLX4_MAILBOX_SIZE, 0);
e8f081aa 2104 if (!priv->cmd.pool)
f3d4c89e 2105 goto err_vhcr;
225c7b1f
RD		 2106
2107 return 0;
e8f081aa 2108
f3d4c89e
RD		 2109err_vhcr:
2110 if (mlx4_is_mfunc(dev))
2111 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2112 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2113 priv->mfunc.vhcr = NULL;
2114
e8f081aa
YP		 2115err_hcr:
2116 if (!mlx4_is_slave(dev))
2117 iounmap(priv->cmd.hcr);
2118 return -ENOMEM;
225c7b1f
RD		 2119}
2120
ab9c17a0
JM		 2121void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2122{
2123 struct mlx4_priv *priv = mlx4_priv(dev);
2124 int i, port;
2125
2126 if (mlx4_is_master(dev)) {
2127 flush_workqueue(priv->mfunc.master.comm_wq);
2128 destroy_workqueue(priv->mfunc.master.comm_wq);
2129 for (i = 0; i < dev->num_slaves; i++) {
2130 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2131 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2132 }
2133 kfree(priv->mfunc.master.slave_state);
0eb62b93
RE		 2134 kfree(priv->mfunc.master.vf_admin);
2135 kfree(priv->mfunc.master.vf_oper);
ab9c17a0 2136 }
f08ad06c
EE		 2137
2138 iounmap(priv->mfunc.comm);
ab9c17a0
JM		 2139}
2140
225c7b1f
RD		 2141void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2142{
2143 struct mlx4_priv *priv = mlx4_priv(dev);
2144
2145 pci_pool_destroy(priv->cmd.pool);
e8f081aa
YP		 2146
2147 if (!mlx4_is_slave(dev))
2148 iounmap(priv->cmd.hcr);
f3d4c89e
RD		 2149 if (mlx4_is_mfunc(dev))
2150 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2151 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2152 priv->mfunc.vhcr = NULL;
225c7b1f
RD		 2153}
2154
2155/*
2156 * Switch to using events to issue FW commands (can only be called
2157 * after event queue for command events has been initialized).
2158 */
2159int mlx4_cmd_use_events(struct mlx4_dev *dev)
2160{
2161 struct mlx4_priv *priv = mlx4_priv(dev);
2162 int i;
e8f081aa 2163 int err = 0;
225c7b1f
RD		 2164
2165 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2166 sizeof (struct mlx4_cmd_context),
2167 GFP_KERNEL);
2168 if (!priv->cmd.context)
2169 return -ENOMEM;
2170
2171 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2172 priv->cmd.context[i].token = i;
2173 priv->cmd.context[i].next = i + 1;
2174 }
2175
2176 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2177 priv->cmd.free_head = 0;
2178
2179 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2180 spin_lock_init(&priv->cmd.context_lock);
2181
2182 for (priv->cmd.token_mask = 1;
2183 priv->cmd.token_mask < priv->cmd.max_cmds;
2184 priv->cmd.token_mask <<= 1)
2185 ; /* nothing */
2186 --priv->cmd.token_mask;
2187
225c7b1f 2188 down(&priv->cmd.poll_sem);
e8f081aa 2189 priv->cmd.use_events = 1;
225c7b1f 2190
e8f081aa 2191 return err;
225c7b1f
RD		 2192}
2193
2194/*
2195 * Switch back to polling (used when shutting down the device)
2196 */
2197void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2198{
2199 struct mlx4_priv *priv = mlx4_priv(dev);
2200 int i;
2201
2202 priv->cmd.use_events = 0;
2203
2204 for (i = 0; i < priv->cmd.max_cmds; ++i)
2205 down(&priv->cmd.event_sem);
2206
2207 kfree(priv->cmd.context);
2208
2209 up(&priv->cmd.poll_sem);
2210}
2211
2212struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2213{
2214 struct mlx4_cmd_mailbox *mailbox;
2215
2216 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2217 if (!mailbox)
2218 return ERR_PTR(-ENOMEM);
2219
2220 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2221 &mailbox->dma);
2222 if (!mailbox->buf) {
2223 kfree(mailbox);
2224 return ERR_PTR(-ENOMEM);
2225 }
2226
571b8b92
JM		 2227 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2228
225c7b1f
RD		 2229 return mailbox;
2230}
2231EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2232
e8f081aa
YP		 2233void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2234 struct mlx4_cmd_mailbox *mailbox)
225c7b1f
RD		 2235{
2236 if (!mailbox)
2237 return;
2238
2239 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2240 kfree(mailbox);
2241}
2242EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
e8f081aa
YP		 2243
2244u32 mlx4_comm_get_version(void)
2245{
2246 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2247}
8f7ba3ca
RE		 2248
2249static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2250{
2251 if ((vf < 0) || (vf >= dev->num_vfs)) {
2252 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2253 return -EINVAL;
2254 }
2255
2256 return vf+1;
2257}
2258
f74462ac
MB		 2259int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2260{
2261 if (slave < 1 || slave > dev->num_vfs) {
2262 mlx4_err(dev,
2263 "Bad slave number:%d (number of activated slaves: %lu)\n",
2264 slave, dev->num_slaves);
2265 return -EINVAL;
2266 }
2267 return slave - 1;
2268}
2269
2270struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2271{
2272 struct mlx4_active_ports actv_ports;
2273 int vf;
2274
2275 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2276
2277 if (slave == 0) {
2278 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2279 return actv_ports;
2280 }
2281
2282 vf = mlx4_get_vf_indx(dev, slave);
2283 if (vf < 0)
2284 return actv_ports;
2285
2286 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2287 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2288 dev->caps.num_ports));
2289
2290 return actv_ports;
2291}
2292EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2293
2294int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2295{
2296 unsigned n;
2297 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2298 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2299
2300 if (port <= 0 || port > m)
2301 return -EINVAL;
2302
2303 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2304 if (port <= n)
2305 port = n + 1;
2306
2307 return port;
2308}
2309EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2310
2311int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2312{
2313 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2314 if (test_bit(port - 1, actv_ports.ports))
2315 return port -
2316 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2317
2318 return -1;
2319}
2320EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2321
2322struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2323 int port)
2324{
2325 unsigned i;
2326 struct mlx4_slaves_pport slaves_pport;
2327
2328 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2329
2330 if (port <= 0 || port > dev->caps.num_ports)
2331 return slaves_pport;
2332
2333 for (i = 0; i < dev->num_vfs + 1; i++) {
2334 struct mlx4_active_ports actv_ports =
2335 mlx4_get_active_ports(dev, i);
2336 if (test_bit(port - 1, actv_ports.ports))
2337 set_bit(i, slaves_pport.slaves);
2338 }
2339
2340 return slaves_pport;
2341}
2342EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2343
2344struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2345 struct mlx4_dev *dev,
2346 const struct mlx4_active_ports *crit_ports)
2347{
2348 unsigned i;
2349 struct mlx4_slaves_pport slaves_pport;
2350
2351 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2352
2353 for (i = 0; i < dev->num_vfs + 1; i++) {
2354 struct mlx4_active_ports actv_ports =
2355 mlx4_get_active_ports(dev, i);
2356 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2357 dev->caps.num_ports))
2358 set_bit(i, slaves_pport.slaves);
2359 }
2360
2361 return slaves_pport;
2362}
2363EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2364
8f7ba3ca
RE		 2365int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2366{
2367 struct mlx4_priv *priv = mlx4_priv(dev);
2368 struct mlx4_vport_state *s_info;
2369 int slave;
2370
2371 if (!mlx4_is_master(dev))
2372 return -EPROTONOSUPPORT;
2373
2374 slave = mlx4_get_slave_indx(dev, vf);
2375 if (slave < 0)
2376 return -EINVAL;
2377
2378 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2379 s_info->mac = mac;
2380 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2381 vf, port, s_info->mac);
2382 return 0;
2383}
2384EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3f7fb021 2385
b01978ca 2386
3f7fb021
RE		 2387int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2388{
2389 struct mlx4_priv *priv = mlx4_priv(dev);
b01978ca 2390 struct mlx4_vport_state *vf_admin;
3f7fb021
RE		 2391 int slave;
2392
2393 if ((!mlx4_is_master(dev)) ||
2394 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2395 return -EPROTONOSUPPORT;
2396
2397 if ((vlan > 4095) || (qos > 7))
2398 return -EINVAL;
2399
2400 slave = mlx4_get_slave_indx(dev, vf);
2401 if (slave < 0)
2402 return -EINVAL;
2403
b01978ca 2404 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
b01978ca 2405
3f7fb021 2406 if ((0 == vlan) && (0 == qos))
b01978ca 2407 vf_admin->default_vlan = MLX4_VGT;
3f7fb021 2408 else
b01978ca
JM		 2409 vf_admin->default_vlan = vlan;
2410 vf_admin->default_qos = qos;
2411
0a6eac24
RE		 2412 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2413 mlx4_info(dev,
2414 "updating vf %d port %d config will take effect on next VF restart\n",
b01978ca 2415 vf, port);
3f7fb021
RE		 2416 return 0;
2417}
2418EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
e6b6a231 2419
5ea8bbfc
JM		 2420 /* mlx4_get_slave_default_vlan -
2421 * return true if VST ( default vlan)
2422 * if VST, will return vlan & qos (if not NULL)
2423 */
2424bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2425 u16 *vlan, u8 *qos)
2426{
2427 struct mlx4_vport_oper_state *vp_oper;
2428 struct mlx4_priv *priv;
2429
2430 priv = mlx4_priv(dev);
2431 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2432
2433 if (MLX4_VGT != vp_oper->state.default_vlan) {
2434 if (vlan)
2435 *vlan = vp_oper->state.default_vlan;
2436 if (qos)
2437 *qos = vp_oper->state.default_qos;
2438 return true;
2439 }
2440 return false;
2441}
2442EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2443
e6b6a231
RE		 2444int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2445{
2446 struct mlx4_priv *priv = mlx4_priv(dev);
2447 struct mlx4_vport_state *s_info;
2448 int slave;
2449
2450 if ((!mlx4_is_master(dev)) ||
2451 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2452 return -EPROTONOSUPPORT;
2453
2454 slave = mlx4_get_slave_indx(dev, vf);
2455 if (slave < 0)
2456 return -EINVAL;
2457
2458 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2459 s_info->spoofchk = setting;
2460
2461 return 0;
2462}
2463EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2cccb9e4
RE		 2464
2465int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2466{
2467 struct mlx4_priv *priv = mlx4_priv(dev);
2468 struct mlx4_vport_state *s_info;
2469 int slave;
2470
2471 if (!mlx4_is_master(dev))
2472 return -EPROTONOSUPPORT;
2473
2474 slave = mlx4_get_slave_indx(dev, vf);
2475 if (slave < 0)
2476 return -EINVAL;
2477
2478 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2479 ivf->vf = vf;
2480
2481 /* need to convert it to a func */
2482 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2483 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2484 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2485 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2486 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2487 ivf->mac[5] = ((s_info->mac) & 0xff);
2488
2489 ivf->vlan = s_info->default_vlan;
2490 ivf->qos = s_info->default_qos;
2491 ivf->tx_rate = s_info->tx_rate;
2492 ivf->spoofchk = s_info->spoofchk;
948e306d 2493 ivf->linkstate = s_info->link_state;
2cccb9e4
RE		 2494
2495 return 0;
2496}
2497EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
948e306d
RE		 2498
2499int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2500{
2501 struct mlx4_priv *priv = mlx4_priv(dev);
2502 struct mlx4_vport_state *s_info;
948e306d
RE		 2503 int slave;
2504 u8 link_stat_event;
2505
2506 slave = mlx4_get_slave_indx(dev, vf);
2507 if (slave < 0)
2508 return -EINVAL;
2509
2510 switch (link_state) {
2511 case IFLA_VF_LINK_STATE_AUTO:
2512 /* get current link state */
2513 if (!priv->sense.do_sense_port[port])
2514 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2515 else
2516 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2517 break;
2518
2519 case IFLA_VF_LINK_STATE_ENABLE:
2520 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2521 break;
2522
2523 case IFLA_VF_LINK_STATE_DISABLE:
2524 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2525 break;
2526
2527 default:
2528 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2529 link_state, slave, port);
2530 return -EINVAL;
2531 };
948e306d 2532 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
948e306d 2533 s_info->link_state = link_state;
948e306d
RE		 2534
2535 /* send event */
2536 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
0a6eac24
RE		 2537
2538 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2539 mlx4_dbg(dev,
2540 "updating vf %d port %d no link state HW enforcment\n",
2541 vf, port);
948e306d
RE		 2542 return 0;
2543}
2544EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
Linux 6.x block layer and io_uring tree(s)