Commit | Line | Data |
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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
0e03f563 JZ |
14 | #include <linux/clk.h> |
15 | #include <linux/cpu.h> | |
c5aff182 | 16 | #include <linux/etherdevice.h> |
0e03f563 | 17 | #include <linux/if_vlan.h> |
c5aff182 | 18 | #include <linux/inetdevice.h> |
c5aff182 | 19 | #include <linux/interrupt.h> |
c3f0dd38 | 20 | #include <linux/io.h> |
0e03f563 JZ |
21 | #include <linux/kernel.h> |
22 | #include <linux/mbus.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/netdevice.h> | |
c5aff182 | 25 | #include <linux/of.h> |
0e03f563 | 26 | #include <linux/of_address.h> |
c5aff182 TP |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_mdio.h> | |
29 | #include <linux/of_net.h> | |
a10c1c81 | 30 | #include <linux/phy/phy.h> |
c5aff182 | 31 | #include <linux/phy.h> |
503f9aa9 | 32 | #include <linux/phylink.h> |
0e03f563 JZ |
33 | #include <linux/platform_device.h> |
34 | #include <linux/skbuff.h> | |
baa11ebc | 35 | #include <net/hwbm.h> |
dc35a10f | 36 | #include "mvneta_bm.h" |
0e03f563 JZ |
37 | #include <net/ip.h> |
38 | #include <net/ipv6.h> | |
39 | #include <net/tso.h> | |
568a3fa2 | 40 | #include <net/page_pool.h> |
0db51da7 | 41 | #include <linux/bpf_trace.h> |
c5aff182 TP |
42 | |
43 | /* Registers */ | |
44 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
e5bdf689 | 45 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
dc35a10f MW |
46 | #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 |
47 | #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 | |
48 | #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 | |
49 | #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 | |
c5aff182 TP |
50 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
51 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
52 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
53 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
54 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
55 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
56 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
57 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
58 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
59 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
60 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
61 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
62 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
dc35a10f MW |
63 | #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) |
64 | #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 | |
65 | #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 | |
c5aff182 TP |
66 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
67 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
68 | #define MVNETA_PHY_ADDR 0x2000 | |
69 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
70 | #define MVNETA_MBUS_RETRY 0x2010 | |
71 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
72 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
73 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
74 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
75 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
76 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
77 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
db6ba9a5 | 78 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
c5aff182 TP |
79 | #define MVNETA_PORT_CONFIG 0x2400 |
80 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
81 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
82 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
83 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
84 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
85 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
86 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
87 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
88 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
89 | MVNETA_DEF_RXQ_ARP(q) | \ | |
90 | MVNETA_DEF_RXQ_TCP(q) | \ | |
91 | MVNETA_DEF_RXQ_UDP(q) | \ | |
92 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
93 | MVNETA_TX_UNSET_ERR_SUM | \ | |
94 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
95 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
96 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
97 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
98 | #define MVNETA_SDMA_CONFIG 0x241c | |
99 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
100 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
101 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
102 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 103 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
104 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
105 | #define MVNETA_PORT_STATUS 0x2444 | |
106 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
107 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
108 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
3f1dd4bc | 109 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 110 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 111 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
c5aff182 TP |
112 | #define MVNETA_TYPE_PRIO 0x24bc |
113 | #define MVNETA_FORCE_UNI BIT(21) | |
114 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
115 | #define MVNETA_TXQ_CMD 0x2448 | |
116 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
117 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
e483911f AL |
118 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
119 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 | |
898b2970 SS |
120 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
121 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 | 122 | #define MVNETA_ACC_MODE 0x2500 |
dc35a10f | 123 | #define MVNETA_BM_ADDRESS 0x2504 |
c5aff182 TP |
124 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
125 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
126 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
2dcf75e2 | 127 | #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) |
50bf8cb6 | 128 | #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) |
c5aff182 | 129 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
40ba35e7 | 130 | |
2dcf75e2 GC |
131 | /* Exception Interrupt Port/Queue Cause register |
132 | * | |
133 | * Their behavior depend of the mapping done using the PCPX2Q | |
134 | * registers. For a given CPU if the bit associated to a queue is not | |
135 | * set, then for the register a read from this CPU will always return | |
136 | * 0 and a write won't do anything | |
137 | */ | |
40ba35e7 | 138 | |
c5aff182 | 139 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 140 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 141 | |
142 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
143 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
144 | * bits 16..23 = RXQ FREE, one bit per queue. | |
145 | * bit 29 = OLD_REG_SUM, see old reg ? | |
146 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
147 | * bit 31 = MISC_SUM, one bit for 4 ports | |
148 | */ | |
149 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
150 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
151 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
152 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 153 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 154 | |
c5aff182 TP |
155 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
156 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 157 | |
158 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
159 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
160 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 161 | |
162 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
163 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
164 | #define MVNETA_CAUSE_PTP BIT(4) | |
165 | ||
166 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
167 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
168 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
169 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
170 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
171 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
172 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
173 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
174 | ||
175 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
176 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
177 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
178 | ||
179 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
180 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
181 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
182 | ||
c5aff182 TP |
183 | #define MVNETA_INTR_ENABLE 0x25b8 |
184 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
dc1aadf6 | 185 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
40ba35e7 | 186 | |
c5aff182 TP |
187 | #define MVNETA_RXQ_CMD 0x2680 |
188 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
189 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
190 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
191 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
192 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
193 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
194 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
22f4bf8a | 195 | #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) |
c5aff182 TP |
196 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) |
197 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 198 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 199 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
200 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
201 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
202 | #define MVNETA_GMAC_STATUS 0x2c10 | |
203 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
204 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
205 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
206 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
207 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
208 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
209 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
210 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
503f9aa9 RK |
211 | #define MVNETA_GMAC_AN_COMPLETE BIT(11) |
212 | #define MVNETA_GMAC_SYNC_OK BIT(14) | |
c5aff182 TP |
213 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c |
214 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
215 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 216 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
22f4bf8a RK |
217 | #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) |
218 | #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) | |
c5aff182 TP |
219 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
220 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 221 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
22f4bf8a RK |
222 | #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) |
223 | #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) | |
898b2970 | 224 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 225 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 226 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
da58a931 MC |
227 | #define MVNETA_GMAC_CTRL_4 0x2c90 |
228 | #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) | |
e483911f | 229 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
c5aff182 TP |
230 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
231 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
232 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
233 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
234 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
235 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
236 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
237 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
238 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
239 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
2a90f7e1 | 240 | #define MVNETA_TXQ_DEC_SENT_MASK 0xff |
c5aff182 TP |
241 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) |
242 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
243 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
244 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
245 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
246 | #define MVNETA_TX_MTU 0x3e0c | |
247 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
248 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
249 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
250 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
251 | ||
6d81f451 RK |
252 | #define MVNETA_LPI_CTRL_0 0x2cc0 |
253 | #define MVNETA_LPI_CTRL_1 0x2cc4 | |
254 | #define MVNETA_LPI_REQUEST_ENABLE BIT(0) | |
255 | #define MVNETA_LPI_CTRL_2 0x2cc8 | |
256 | #define MVNETA_LPI_STATUS 0x2ccc | |
257 | ||
c5aff182 TP |
258 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
259 | ||
260 | /* Descriptor ring Macros */ | |
261 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
262 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
263 | ||
264 | /* Various constants */ | |
265 | ||
266 | /* Coalescing */ | |
06708f81 | 267 | #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ |
c5aff182 TP |
268 | #define MVNETA_RX_COAL_PKTS 32 |
269 | #define MVNETA_RX_COAL_USEC 100 | |
270 | ||
6a20c175 | 271 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
272 | * by Marvell switches when a specific hardware mode is enabled (not |
273 | * supported by this driver) or is filled automatically by zeroes on | |
274 | * the RX side. Those two bytes being at the front of the Ethernet | |
275 | * header, they allow to have the IP header aligned on a 4 bytes | |
276 | * boundary automatically: the hardware skips those two bytes on its | |
277 | * own. | |
278 | */ | |
279 | #define MVNETA_MH_SIZE 2 | |
280 | ||
281 | #define MVNETA_VLAN_TAG_LEN 4 | |
282 | ||
9110ee07 | 283 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
c5aff182 | 284 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
dc35a10f MW |
285 | #define MVNETA_ACC_MODE_EXT1 1 |
286 | #define MVNETA_ACC_MODE_EXT2 2 | |
287 | ||
288 | #define MVNETA_MAX_DECODE_WIN 6 | |
c5aff182 TP |
289 | |
290 | /* Timeout constants */ | |
291 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
292 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
293 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
294 | ||
295 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
296 | ||
9a401dea GC |
297 | /* The RSS lookup table actually has 256 entries but we do not use |
298 | * them yet | |
299 | */ | |
300 | #define MVNETA_RSS_LU_TABLE_SIZE 1 | |
301 | ||
c5aff182 | 302 | /* Max number of Rx descriptors */ |
c307e2a8 | 303 | #define MVNETA_MAX_RXD 512 |
c5aff182 TP |
304 | |
305 | /* Max number of Tx descriptors */ | |
c307e2a8 | 306 | #define MVNETA_MAX_TXD 1024 |
c5aff182 | 307 | |
8eef5f97 EG |
308 | /* Max number of allowed TCP segments for software TSO */ |
309 | #define MVNETA_MAX_TSO_SEGS 100 | |
310 | ||
311 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
312 | ||
c5aff182 TP |
313 | /* descriptor aligned size */ |
314 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
315 | ||
8d5047cf MW |
316 | /* Number of bytes to be taken into account by HW when putting incoming data |
317 | * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet | |
318 | * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. | |
319 | */ | |
320 | #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 | |
321 | ||
c5aff182 TP |
322 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
323 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
324 | ETH_HLEN + ETH_FCS_LEN, \ | |
c66e98c9 | 325 | cache_line_size()) |
c5aff182 | 326 | |
0db51da7 LB |
327 | #define MVNETA_SKB_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ |
328 | NET_IP_ALIGN) | |
8dc9a088 | 329 | #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ |
0db51da7 | 330 | MVNETA_SKB_HEADROOM)) |
8dc9a088 LB |
331 | #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD) |
332 | #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) | |
333 | ||
2e3173a3 EG |
334 | #define IS_TSO_HEADER(txq, addr) \ |
335 | ((addr >= txq->tso_hdrs_phys) && \ | |
336 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
337 | ||
dc35a10f MW |
338 | #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ |
339 | (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) | |
c5aff182 | 340 | |
6d81f451 RK |
341 | enum { |
342 | ETHTOOL_STAT_EEE_WAKEUP, | |
17a96da6 GC |
343 | ETHTOOL_STAT_SKB_ALLOC_ERR, |
344 | ETHTOOL_STAT_REFILL_ERR, | |
6d81f451 RK |
345 | ETHTOOL_MAX_STATS, |
346 | }; | |
347 | ||
9b0cdefa RK |
348 | struct mvneta_statistic { |
349 | unsigned short offset; | |
350 | unsigned short type; | |
351 | const char name[ETH_GSTRING_LEN]; | |
352 | }; | |
353 | ||
354 | #define T_REG_32 32 | |
355 | #define T_REG_64 64 | |
6d81f451 | 356 | #define T_SW 1 |
9b0cdefa | 357 | |
0db51da7 LB |
358 | #define MVNETA_XDP_PASS BIT(0) |
359 | #define MVNETA_XDP_DROPPED BIT(1) | |
360 | #define MVNETA_XDP_TX BIT(2) | |
361 | #define MVNETA_XDP_REDIR BIT(3) | |
362 | ||
9b0cdefa RK |
363 | static const struct mvneta_statistic mvneta_statistics[] = { |
364 | { 0x3000, T_REG_64, "good_octets_received", }, | |
365 | { 0x3010, T_REG_32, "good_frames_received", }, | |
366 | { 0x3008, T_REG_32, "bad_octets_received", }, | |
367 | { 0x3014, T_REG_32, "bad_frames_received", }, | |
368 | { 0x3018, T_REG_32, "broadcast_frames_received", }, | |
369 | { 0x301c, T_REG_32, "multicast_frames_received", }, | |
370 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, | |
371 | { 0x3058, T_REG_32, "good_fc_received", }, | |
372 | { 0x305c, T_REG_32, "bad_fc_received", }, | |
373 | { 0x3060, T_REG_32, "undersize_received", }, | |
374 | { 0x3064, T_REG_32, "fragments_received", }, | |
375 | { 0x3068, T_REG_32, "oversize_received", }, | |
376 | { 0x306c, T_REG_32, "jabber_received", }, | |
377 | { 0x3070, T_REG_32, "mac_receive_error", }, | |
378 | { 0x3074, T_REG_32, "bad_crc_event", }, | |
379 | { 0x3078, T_REG_32, "collision", }, | |
380 | { 0x307c, T_REG_32, "late_collision", }, | |
381 | { 0x2484, T_REG_32, "rx_discard", }, | |
382 | { 0x2488, T_REG_32, "rx_overrun", }, | |
383 | { 0x3020, T_REG_32, "frames_64_octets", }, | |
384 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, | |
385 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, | |
386 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, | |
387 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, | |
388 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, | |
389 | { 0x3038, T_REG_64, "good_octets_sent", }, | |
390 | { 0x3040, T_REG_32, "good_frames_sent", }, | |
391 | { 0x3044, T_REG_32, "excessive_collision", }, | |
392 | { 0x3048, T_REG_32, "multicast_frames_sent", }, | |
393 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, | |
394 | { 0x3054, T_REG_32, "fc_sent", }, | |
395 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, | |
6d81f451 | 396 | { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, |
17a96da6 GC |
397 | { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, |
398 | { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, | |
9b0cdefa RK |
399 | }; |
400 | ||
74c41b04 | 401 | struct mvneta_pcpu_stats { |
c5aff182 | 402 | struct u64_stats_sync syncp; |
74c41b04 | 403 | u64 rx_packets; |
404 | u64 rx_bytes; | |
405 | u64 tx_packets; | |
406 | u64 tx_bytes; | |
c5aff182 TP |
407 | }; |
408 | ||
12bb03b4 MR |
409 | struct mvneta_pcpu_port { |
410 | /* Pointer to the shared port */ | |
411 | struct mvneta_port *pp; | |
412 | ||
413 | /* Pointer to the CPU-local NAPI struct */ | |
414 | struct napi_struct napi; | |
415 | ||
416 | /* Cause of the previous interrupt */ | |
417 | u32 cause_rx_tx; | |
418 | }; | |
419 | ||
c5aff182 | 420 | struct mvneta_port { |
dc35a10f | 421 | u8 id; |
12bb03b4 MR |
422 | struct mvneta_pcpu_port __percpu *ports; |
423 | struct mvneta_pcpu_stats __percpu *stats; | |
424 | ||
c5aff182 TP |
425 | int pkt_size; |
426 | void __iomem *base; | |
427 | struct mvneta_rx_queue *rxqs; | |
428 | struct mvneta_tx_queue *txqs; | |
c5aff182 | 429 | struct net_device *dev; |
84a3f4db SAS |
430 | struct hlist_node node_online; |
431 | struct hlist_node node_dead; | |
90b74c01 | 432 | int rxq_def; |
5888511e GC |
433 | /* Protect the access to the percpu interrupt registers, |
434 | * ensuring that the configuration remains coherent. | |
435 | */ | |
436 | spinlock_t lock; | |
120cfa50 | 437 | bool is_stopped; |
c5aff182 | 438 | |
2636ac3c MW |
439 | u32 cause_rx_tx; |
440 | struct napi_struct napi; | |
441 | ||
0db51da7 LB |
442 | struct bpf_prog *xdp_prog; |
443 | ||
c5aff182 | 444 | /* Core clock */ |
189dd626 | 445 | struct clk *clk; |
15cc4a4a JZ |
446 | /* AXI clock */ |
447 | struct clk *clk_bus; | |
c5aff182 TP |
448 | u8 mcast_count[256]; |
449 | u16 tx_ring_size; | |
450 | u16 rx_ring_size; | |
c5aff182 | 451 | |
c5aff182 | 452 | phy_interface_t phy_interface; |
503f9aa9 | 453 | struct device_node *dn; |
b65657fc | 454 | unsigned int tx_csum_limit; |
503f9aa9 | 455 | struct phylink *phylink; |
44cc27e4 | 456 | struct phylink_config phylink_config; |
a10c1c81 | 457 | struct phy *comphy; |
9b0cdefa | 458 | |
dc35a10f MW |
459 | struct mvneta_bm *bm_priv; |
460 | struct mvneta_bm_pool *pool_long; | |
461 | struct mvneta_bm_pool *pool_short; | |
462 | int bm_win_id; | |
463 | ||
6d81f451 RK |
464 | bool eee_enabled; |
465 | bool eee_active; | |
466 | bool tx_lpi_enabled; | |
467 | ||
9b0cdefa | 468 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; |
9a401dea GC |
469 | |
470 | u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; | |
2636ac3c MW |
471 | |
472 | /* Flags for special SoC configurations */ | |
473 | bool neta_armada3700; | |
8d5047cf | 474 | u16 rx_offset_correction; |
9768b45c | 475 | const struct mbus_dram_target_info *dram_target_info; |
c5aff182 TP |
476 | }; |
477 | ||
6a20c175 | 478 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
479 | * layout of the transmit and reception DMA descriptors, and their |
480 | * layout is therefore defined by the hardware design | |
481 | */ | |
6083ed44 | 482 | |
c5aff182 TP |
483 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
484 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
485 | #define MVNETA_TX_L4_UDP BIT(16) | |
486 | #define MVNETA_TX_L3_IP6 BIT(17) | |
487 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
488 | #define MVNETA_TXD_Z_PAD BIT(19) | |
489 | #define MVNETA_TXD_L_DESC BIT(20) | |
490 | #define MVNETA_TXD_F_DESC BIT(21) | |
491 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
492 | MVNETA_TXD_L_DESC | \ | |
493 | MVNETA_TXD_F_DESC) | |
494 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
495 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
496 | ||
c5aff182 | 497 | #define MVNETA_RXD_ERR_CRC 0x0 |
dc35a10f MW |
498 | #define MVNETA_RXD_BM_POOL_SHIFT 13 |
499 | #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) | |
c5aff182 TP |
500 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
501 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
502 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
503 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
504 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
505 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
562e2f46 YK |
506 | #define MVNETA_RXD_LAST_DESC BIT(26) |
507 | #define MVNETA_RXD_FIRST_DESC BIT(27) | |
508 | #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ | |
509 | MVNETA_RXD_LAST_DESC) | |
c5aff182 TP |
510 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) |
511 | ||
9ad8fef6 | 512 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
513 | struct mvneta_tx_desc { |
514 | u32 command; /* Options used by HW for packet transmitting.*/ | |
fbd1d524 | 515 | u16 reserved1; /* csum_l4 (for future use) */ |
6083ed44 TP |
516 | u16 data_size; /* Data size of transmitted packet in bytes */ |
517 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
518 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
519 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
520 | }; | |
521 | ||
522 | struct mvneta_rx_desc { | |
523 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
524 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
525 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 526 | |
c5aff182 TP |
527 | u32 buf_phys_addr; /* Physical address of the buffer */ |
528 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 529 | |
c5aff182 TP |
530 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
531 | u16 reserved3; /* prefetch_cmd, for future use */ | |
532 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 533 | |
c5aff182 TP |
534 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
535 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
536 | }; | |
9ad8fef6 TP |
537 | #else |
538 | struct mvneta_tx_desc { | |
539 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
fbd1d524 | 540 | u16 reserved1; /* csum_l4 (for future use) */ |
9ad8fef6 TP |
541 | u32 command; /* Options used by HW for packet transmitting.*/ |
542 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
543 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
544 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
545 | }; | |
546 | ||
547 | struct mvneta_rx_desc { | |
548 | u16 data_size; /* Size of received packet in bytes */ | |
549 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
550 | u32 status; /* Info about received packet */ | |
551 | ||
552 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
553 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
554 | ||
555 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
556 | u16 reserved3; /* prefetch_cmd, for future use */ | |
557 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
558 | ||
559 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
560 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
561 | }; | |
562 | #endif | |
c5aff182 | 563 | |
9e58c8b4 LB |
564 | enum mvneta_tx_buf_type { |
565 | MVNETA_TYPE_SKB, | |
566 | MVNETA_TYPE_XDP_TX, | |
567 | MVNETA_TYPE_XDP_NDO, | |
568 | }; | |
569 | ||
570 | struct mvneta_tx_buf { | |
571 | enum mvneta_tx_buf_type type; | |
572 | union { | |
573 | struct xdp_frame *xdpf; | |
574 | struct sk_buff *skb; | |
575 | }; | |
576 | }; | |
577 | ||
c5aff182 TP |
578 | struct mvneta_tx_queue { |
579 | /* Number of this TX queue, in the range 0-7 */ | |
580 | u8 id; | |
581 | ||
582 | /* Number of TX DMA descriptors in the descriptor ring */ | |
583 | int size; | |
584 | ||
585 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
586 | * descriptor ring |
587 | */ | |
c5aff182 | 588 | int count; |
2a90f7e1 | 589 | int pending; |
8eef5f97 EG |
590 | int tx_stop_threshold; |
591 | int tx_wake_threshold; | |
c5aff182 | 592 | |
9e58c8b4 LB |
593 | /* Array of transmitted buffers */ |
594 | struct mvneta_tx_buf *buf; | |
c5aff182 TP |
595 | |
596 | /* Index of last TX DMA descriptor that was inserted */ | |
597 | int txq_put_index; | |
598 | ||
599 | /* Index of the TX DMA descriptor to be cleaned up */ | |
600 | int txq_get_index; | |
601 | ||
602 | u32 done_pkts_coal; | |
603 | ||
604 | /* Virtual address of the TX DMA descriptors array */ | |
605 | struct mvneta_tx_desc *descs; | |
606 | ||
607 | /* DMA address of the TX DMA descriptors array */ | |
608 | dma_addr_t descs_phys; | |
609 | ||
610 | /* Index of the last TX DMA descriptor */ | |
611 | int last_desc; | |
612 | ||
613 | /* Index of the next TX DMA descriptor to process */ | |
614 | int next_desc_to_proc; | |
2adb719d EG |
615 | |
616 | /* DMA buffers for TSO headers */ | |
617 | char *tso_hdrs; | |
618 | ||
619 | /* DMA address of TSO headers */ | |
620 | dma_addr_t tso_hdrs_phys; | |
50bf8cb6 GC |
621 | |
622 | /* Affinity mask for CPUs*/ | |
623 | cpumask_t affinity_mask; | |
c5aff182 TP |
624 | }; |
625 | ||
626 | struct mvneta_rx_queue { | |
627 | /* rx queue number, in the range 0-7 */ | |
628 | u8 id; | |
629 | ||
630 | /* num of rx descriptors in the rx descriptor ring */ | |
631 | int size; | |
632 | ||
c5aff182 TP |
633 | u32 pkts_coal; |
634 | u32 time_coal; | |
635 | ||
568a3fa2 LB |
636 | /* page_pool */ |
637 | struct page_pool *page_pool; | |
638 | struct xdp_rxq_info xdp_rxq; | |
639 | ||
f88bee1c GC |
640 | /* Virtual address of the RX buffer */ |
641 | void **buf_virt_addr; | |
642 | ||
c5aff182 TP |
643 | /* Virtual address of the RX DMA descriptors array */ |
644 | struct mvneta_rx_desc *descs; | |
645 | ||
646 | /* DMA address of the RX DMA descriptors array */ | |
647 | dma_addr_t descs_phys; | |
648 | ||
649 | /* Index of the last RX DMA descriptor */ | |
650 | int last_desc; | |
651 | ||
652 | /* Index of the next RX DMA descriptor to process */ | |
653 | int next_desc_to_proc; | |
17a96da6 | 654 | |
562e2f46 YK |
655 | /* Index of first RX DMA descriptor to refill */ |
656 | int first_to_refill; | |
657 | u32 refill_num; | |
658 | ||
659 | /* pointer to uncomplete skb buffer */ | |
660 | struct sk_buff *skb; | |
661 | int left_size; | |
662 | ||
17a96da6 GC |
663 | /* error counters */ |
664 | u32 skb_alloc_err; | |
665 | u32 refill_err; | |
c5aff182 TP |
666 | }; |
667 | ||
84a3f4db | 668 | static enum cpuhp_state online_hpstate; |
edadb7fa EG |
669 | /* The hardware supports eight (8) rx queues, but we are only allowing |
670 | * the first one to be used. Therefore, let's just allocate one queue. | |
671 | */ | |
d8936657 | 672 | static int rxq_number = 8; |
c5aff182 TP |
673 | static int txq_number = 8; |
674 | ||
675 | static int rxq_def; | |
c5aff182 | 676 | |
f19fadfc | 677 | static int rx_copybreak __read_mostly = 256; |
678 | ||
dc35a10f MW |
679 | /* HW BM need that each port be identify by a unique ID */ |
680 | static int global_port_id; | |
681 | ||
c5aff182 TP |
682 | #define MVNETA_DRIVER_NAME "mvneta" |
683 | #define MVNETA_DRIVER_VERSION "1.0" | |
684 | ||
685 | /* Utility/helper methods */ | |
686 | ||
687 | /* Write helper method */ | |
688 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
689 | { | |
690 | writel(data, pp->base + offset); | |
691 | } | |
692 | ||
693 | /* Read helper method */ | |
694 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
695 | { | |
696 | return readl(pp->base + offset); | |
697 | } | |
698 | ||
699 | /* Increment txq get counter */ | |
700 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
701 | { | |
702 | txq->txq_get_index++; | |
703 | if (txq->txq_get_index == txq->size) | |
704 | txq->txq_get_index = 0; | |
705 | } | |
706 | ||
707 | /* Increment txq put counter */ | |
708 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
709 | { | |
710 | txq->txq_put_index++; | |
711 | if (txq->txq_put_index == txq->size) | |
712 | txq->txq_put_index = 0; | |
713 | } | |
714 | ||
715 | ||
716 | /* Clear all MIB counters */ | |
717 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
718 | { | |
719 | int i; | |
720 | u32 dummy; | |
721 | ||
722 | /* Perform dummy reads from MIB counters */ | |
723 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
724 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
e483911f AL |
725 | dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); |
726 | dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); | |
c5aff182 TP |
727 | } |
728 | ||
729 | /* Get System Network Statistics */ | |
bc1f4470 | 730 | static void |
2dc0d2b4 BX |
731 | mvneta_get_stats64(struct net_device *dev, |
732 | struct rtnl_link_stats64 *stats) | |
c5aff182 TP |
733 | { |
734 | struct mvneta_port *pp = netdev_priv(dev); | |
735 | unsigned int start; | |
74c41b04 | 736 | int cpu; |
c5aff182 | 737 | |
74c41b04 | 738 | for_each_possible_cpu(cpu) { |
739 | struct mvneta_pcpu_stats *cpu_stats; | |
740 | u64 rx_packets; | |
741 | u64 rx_bytes; | |
742 | u64 tx_packets; | |
743 | u64 tx_bytes; | |
c5aff182 | 744 | |
74c41b04 | 745 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
746 | do { | |
57a7744e | 747 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
74c41b04 | 748 | rx_packets = cpu_stats->rx_packets; |
749 | rx_bytes = cpu_stats->rx_bytes; | |
750 | tx_packets = cpu_stats->tx_packets; | |
751 | tx_bytes = cpu_stats->tx_bytes; | |
57a7744e | 752 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 753 | |
74c41b04 | 754 | stats->rx_packets += rx_packets; |
755 | stats->rx_bytes += rx_bytes; | |
756 | stats->tx_packets += tx_packets; | |
757 | stats->tx_bytes += tx_bytes; | |
758 | } | |
c5aff182 TP |
759 | |
760 | stats->rx_errors = dev->stats.rx_errors; | |
761 | stats->rx_dropped = dev->stats.rx_dropped; | |
762 | ||
763 | stats->tx_dropped = dev->stats.tx_dropped; | |
c5aff182 TP |
764 | } |
765 | ||
766 | /* Rx descriptors helper methods */ | |
767 | ||
5428213c | 768 | /* Checks whether the RX descriptor having this status is both the first |
769 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
770 | * received through a single RX descriptor, so not having each RX |
771 | * descriptor with its first and last bits set is an error | |
772 | */ | |
5428213c | 773 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 774 | { |
5428213c | 775 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
776 | MVNETA_RXD_FIRST_LAST_DESC; |
777 | } | |
778 | ||
779 | /* Add number of descriptors ready to receive new packets */ | |
780 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
781 | struct mvneta_rx_queue *rxq, | |
782 | int ndescs) | |
783 | { | |
784 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
785 | * be added at once |
786 | */ | |
c5aff182 TP |
787 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
788 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
789 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
790 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
791 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
792 | } | |
793 | ||
794 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
795 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
796 | } | |
797 | ||
798 | /* Get number of RX descriptors occupied by received packets */ | |
799 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
800 | struct mvneta_rx_queue *rxq) | |
801 | { | |
802 | u32 val; | |
803 | ||
804 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
805 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
806 | } | |
807 | ||
6a20c175 | 808 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
809 | * from mvneta_rxq_drop_pkts(). |
810 | */ | |
811 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
812 | struct mvneta_rx_queue *rxq, | |
813 | int rx_done, int rx_filled) | |
814 | { | |
815 | u32 val; | |
816 | ||
817 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
818 | val = rx_done | | |
819 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
820 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
821 | return; | |
822 | } | |
823 | ||
824 | /* Only 255 descriptors can be added at once */ | |
825 | while ((rx_done > 0) || (rx_filled > 0)) { | |
826 | if (rx_done <= 0xff) { | |
827 | val = rx_done; | |
828 | rx_done = 0; | |
829 | } else { | |
830 | val = 0xff; | |
831 | rx_done -= 0xff; | |
832 | } | |
833 | if (rx_filled <= 0xff) { | |
834 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
835 | rx_filled = 0; | |
836 | } else { | |
837 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
838 | rx_filled -= 0xff; | |
839 | } | |
840 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
841 | } | |
842 | } | |
843 | ||
844 | /* Get pointer to next RX descriptor to be processed by SW */ | |
845 | static struct mvneta_rx_desc * | |
846 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
847 | { | |
848 | int rx_desc = rxq->next_desc_to_proc; | |
849 | ||
850 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 851 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
852 | return rxq->descs + rx_desc; |
853 | } | |
854 | ||
855 | /* Change maximum receive size of the port. */ | |
856 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
857 | { | |
858 | u32 val; | |
859 | ||
860 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
861 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
862 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
863 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
864 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
865 | } | |
866 | ||
867 | ||
868 | /* Set rx queue offset */ | |
869 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
870 | struct mvneta_rx_queue *rxq, | |
871 | int offset) | |
872 | { | |
873 | u32 val; | |
874 | ||
875 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
876 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
877 | ||
878 | /* Offset is in */ | |
879 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
880 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
881 | } | |
882 | ||
883 | ||
884 | /* Tx descriptors helper methods */ | |
885 | ||
886 | /* Update HW with number of TX descriptors to be sent */ | |
887 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
888 | struct mvneta_tx_queue *txq, | |
889 | int pend_desc) | |
890 | { | |
891 | u32 val; | |
892 | ||
0d63785c SG |
893 | pend_desc += txq->pending; |
894 | ||
895 | /* Only 255 Tx descriptors can be added at once */ | |
896 | do { | |
897 | val = min(pend_desc, 255); | |
898 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
899 | pend_desc -= val; | |
900 | } while (pend_desc > 0); | |
2a90f7e1 | 901 | txq->pending = 0; |
c5aff182 TP |
902 | } |
903 | ||
904 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
905 | static struct mvneta_tx_desc * | |
906 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
907 | { | |
908 | int tx_desc = txq->next_desc_to_proc; | |
909 | ||
910 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
911 | return txq->descs + tx_desc; | |
912 | } | |
913 | ||
914 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
915 | * mapping failures in the TX path. |
916 | */ | |
c5aff182 TP |
917 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
918 | { | |
919 | if (txq->next_desc_to_proc == 0) | |
920 | txq->next_desc_to_proc = txq->last_desc - 1; | |
921 | else | |
922 | txq->next_desc_to_proc--; | |
923 | } | |
924 | ||
925 | /* Set rxq buf size */ | |
926 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
927 | struct mvneta_rx_queue *rxq, | |
928 | int buf_size) | |
929 | { | |
930 | u32 val; | |
931 | ||
932 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
933 | ||
934 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
935 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
936 | ||
937 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
938 | } | |
939 | ||
940 | /* Disable buffer management (BM) */ | |
941 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
942 | struct mvneta_rx_queue *rxq) | |
943 | { | |
944 | u32 val; | |
945 | ||
946 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
947 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
948 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
949 | } | |
950 | ||
dc35a10f MW |
951 | /* Enable buffer management (BM) */ |
952 | static void mvneta_rxq_bm_enable(struct mvneta_port *pp, | |
953 | struct mvneta_rx_queue *rxq) | |
954 | { | |
955 | u32 val; | |
956 | ||
957 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
958 | val |= MVNETA_RXQ_HW_BUF_ALLOC; | |
959 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
960 | } | |
961 | ||
962 | /* Notify HW about port's assignment of pool for bigger packets */ | |
963 | static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, | |
964 | struct mvneta_rx_queue *rxq) | |
965 | { | |
966 | u32 val; | |
967 | ||
968 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
969 | val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; | |
970 | val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); | |
971 | ||
972 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
973 | } | |
974 | ||
975 | /* Notify HW about port's assignment of pool for smaller packets */ | |
976 | static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, | |
977 | struct mvneta_rx_queue *rxq) | |
978 | { | |
979 | u32 val; | |
980 | ||
981 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
982 | val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; | |
983 | val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); | |
984 | ||
985 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
986 | } | |
987 | ||
988 | /* Set port's receive buffer size for assigned BM pool */ | |
989 | static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, | |
990 | int buf_size, | |
991 | u8 pool_id) | |
992 | { | |
993 | u32 val; | |
994 | ||
995 | if (!IS_ALIGNED(buf_size, 8)) { | |
996 | dev_warn(pp->dev->dev.parent, | |
997 | "illegal buf_size value %d, round to %d\n", | |
998 | buf_size, ALIGN(buf_size, 8)); | |
999 | buf_size = ALIGN(buf_size, 8); | |
1000 | } | |
1001 | ||
1002 | val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); | |
1003 | val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; | |
1004 | mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); | |
1005 | } | |
1006 | ||
1007 | /* Configure MBUS window in order to enable access BM internal SRAM */ | |
1008 | static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, | |
1009 | u8 target, u8 attr) | |
1010 | { | |
1011 | u32 win_enable, win_protect; | |
1012 | int i; | |
1013 | ||
1014 | win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); | |
1015 | ||
1016 | if (pp->bm_win_id < 0) { | |
1017 | /* Find first not occupied window */ | |
1018 | for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { | |
1019 | if (win_enable & (1 << i)) { | |
1020 | pp->bm_win_id = i; | |
1021 | break; | |
1022 | } | |
1023 | } | |
1024 | if (i == MVNETA_MAX_DECODE_WIN) | |
1025 | return -ENOMEM; | |
1026 | } else { | |
1027 | i = pp->bm_win_id; | |
1028 | } | |
1029 | ||
1030 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
1031 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
1032 | ||
1033 | if (i < 4) | |
1034 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
1035 | ||
1036 | mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | | |
1037 | (attr << 8) | target); | |
1038 | ||
1039 | mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); | |
1040 | ||
1041 | win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); | |
1042 | win_protect |= 3 << (2 * i); | |
1043 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); | |
1044 | ||
1045 | win_enable &= ~(1 << i); | |
1046 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
2636ac3c | 1051 | static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) |
dc35a10f | 1052 | { |
2636ac3c | 1053 | u32 wsize; |
dc35a10f MW |
1054 | u8 target, attr; |
1055 | int err; | |
1056 | ||
1057 | /* Get BM window information */ | |
1058 | err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, | |
1059 | &target, &attr); | |
1060 | if (err < 0) | |
1061 | return err; | |
1062 | ||
1063 | pp->bm_win_id = -1; | |
1064 | ||
1065 | /* Open NETA -> BM window */ | |
1066 | err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, | |
1067 | target, attr); | |
1068 | if (err < 0) { | |
1069 | netdev_info(pp->dev, "fail to configure mbus window to BM\n"); | |
1070 | return err; | |
1071 | } | |
2636ac3c MW |
1072 | return 0; |
1073 | } | |
1074 | ||
1075 | /* Assign and initialize pools for port. In case of fail | |
1076 | * buffer manager will remain disabled for current port. | |
1077 | */ | |
1078 | static int mvneta_bm_port_init(struct platform_device *pdev, | |
1079 | struct mvneta_port *pp) | |
1080 | { | |
1081 | struct device_node *dn = pdev->dev.of_node; | |
1082 | u32 long_pool_id, short_pool_id; | |
1083 | ||
1084 | if (!pp->neta_armada3700) { | |
1085 | int ret; | |
1086 | ||
1087 | ret = mvneta_bm_port_mbus_init(pp); | |
1088 | if (ret) | |
1089 | return ret; | |
1090 | } | |
dc35a10f MW |
1091 | |
1092 | if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { | |
1093 | netdev_info(pp->dev, "missing long pool id\n"); | |
1094 | return -EINVAL; | |
1095 | } | |
1096 | ||
1097 | /* Create port's long pool depending on mtu */ | |
1098 | pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, | |
1099 | MVNETA_BM_LONG, pp->id, | |
1100 | MVNETA_RX_PKT_SIZE(pp->dev->mtu)); | |
1101 | if (!pp->pool_long) { | |
1102 | netdev_info(pp->dev, "fail to obtain long pool for port\n"); | |
1103 | return -ENOMEM; | |
1104 | } | |
1105 | ||
1106 | pp->pool_long->port_map |= 1 << pp->id; | |
1107 | ||
1108 | mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, | |
1109 | pp->pool_long->id); | |
1110 | ||
1111 | /* If short pool id is not defined, assume using single pool */ | |
1112 | if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) | |
1113 | short_pool_id = long_pool_id; | |
1114 | ||
1115 | /* Create port's short pool */ | |
1116 | pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, | |
1117 | MVNETA_BM_SHORT, pp->id, | |
1118 | MVNETA_BM_SHORT_PKT_SIZE); | |
1119 | if (!pp->pool_short) { | |
1120 | netdev_info(pp->dev, "fail to obtain short pool for port\n"); | |
1121 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1122 | return -ENOMEM; | |
1123 | } | |
1124 | ||
1125 | if (short_pool_id != long_pool_id) { | |
1126 | pp->pool_short->port_map |= 1 << pp->id; | |
1127 | mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, | |
1128 | pp->pool_short->id); | |
1129 | } | |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | /* Update settings of a pool for bigger packets */ | |
1135 | static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) | |
1136 | { | |
1137 | struct mvneta_bm_pool *bm_pool = pp->pool_long; | |
baa11ebc | 1138 | struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; |
dc35a10f MW |
1139 | int num; |
1140 | ||
1141 | /* Release all buffers from long pool */ | |
1142 | mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); | |
baa11ebc | 1143 | if (hwbm_pool->buf_num) { |
dc35a10f MW |
1144 | WARN(1, "cannot free all buffers in pool %d\n", |
1145 | bm_pool->id); | |
1146 | goto bm_mtu_err; | |
1147 | } | |
1148 | ||
1149 | bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); | |
1150 | bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); | |
baa11ebc GC |
1151 | hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1152 | SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); | |
dc35a10f MW |
1153 | |
1154 | /* Fill entire long pool */ | |
6dcdd884 | 1155 | num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); |
baa11ebc | 1156 | if (num != hwbm_pool->size) { |
dc35a10f | 1157 | WARN(1, "pool %d: %d of %d allocated\n", |
baa11ebc | 1158 | bm_pool->id, num, hwbm_pool->size); |
dc35a10f MW |
1159 | goto bm_mtu_err; |
1160 | } | |
1161 | mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); | |
1162 | ||
1163 | return; | |
1164 | ||
1165 | bm_mtu_err: | |
1166 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1167 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); | |
1168 | ||
1169 | pp->bm_priv = NULL; | |
1170 | mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); | |
1171 | netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); | |
1172 | } | |
1173 | ||
c5aff182 TP |
1174 | /* Start the Ethernet port RX and TX activity */ |
1175 | static void mvneta_port_up(struct mvneta_port *pp) | |
1176 | { | |
1177 | int queue; | |
1178 | u32 q_map; | |
1179 | ||
1180 | /* Enable all initialized TXs. */ | |
c5aff182 TP |
1181 | q_map = 0; |
1182 | for (queue = 0; queue < txq_number; queue++) { | |
1183 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
f95936cc | 1184 | if (txq->descs) |
c5aff182 TP |
1185 | q_map |= (1 << queue); |
1186 | } | |
1187 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
1188 | ||
e81b5e01 | 1189 | q_map = 0; |
c5aff182 | 1190 | /* Enable all initialized RXQs. */ |
2dcf75e2 GC |
1191 | for (queue = 0; queue < rxq_number; queue++) { |
1192 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1193 | ||
f95936cc | 1194 | if (rxq->descs) |
2dcf75e2 GC |
1195 | q_map |= (1 << queue); |
1196 | } | |
1197 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
c5aff182 TP |
1198 | } |
1199 | ||
1200 | /* Stop the Ethernet port activity */ | |
1201 | static void mvneta_port_down(struct mvneta_port *pp) | |
1202 | { | |
1203 | u32 val; | |
1204 | int count; | |
1205 | ||
1206 | /* Stop Rx port activity. Check port Rx activity. */ | |
1207 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
1208 | ||
1209 | /* Issue stop command for active channels only */ | |
1210 | if (val != 0) | |
1211 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
1212 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
1213 | ||
1214 | /* Wait for all Rx activity to terminate. */ | |
1215 | count = 0; | |
1216 | do { | |
1217 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
1218 | netdev_warn(pp->dev, | |
0838abb3 | 1219 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", |
c5aff182 TP |
1220 | val); |
1221 | break; | |
1222 | } | |
1223 | mdelay(1); | |
1224 | ||
1225 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
a3703fb3 | 1226 | } while (val & MVNETA_RXQ_ENABLE_MASK); |
c5aff182 TP |
1227 | |
1228 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
1229 | * command for active channels only |
1230 | */ | |
c5aff182 TP |
1231 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
1232 | ||
1233 | if (val != 0) | |
1234 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
1235 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
1236 | ||
1237 | /* Wait for all Tx activity to terminate. */ | |
1238 | count = 0; | |
1239 | do { | |
1240 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
1241 | netdev_warn(pp->dev, | |
1242 | "TIMEOUT for TX stopped status=0x%08x\n", | |
1243 | val); | |
1244 | break; | |
1245 | } | |
1246 | mdelay(1); | |
1247 | ||
1248 | /* Check TX Command reg that all Txqs are stopped */ | |
1249 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
1250 | ||
a3703fb3 | 1251 | } while (val & MVNETA_TXQ_ENABLE_MASK); |
c5aff182 TP |
1252 | |
1253 | /* Double check to verify that TX FIFO is empty */ | |
1254 | count = 0; | |
1255 | do { | |
1256 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
1257 | netdev_warn(pp->dev, | |
0838abb3 | 1258 | "TX FIFO empty timeout status=0x%08x\n", |
c5aff182 TP |
1259 | val); |
1260 | break; | |
1261 | } | |
1262 | mdelay(1); | |
1263 | ||
1264 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
1265 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
1266 | (val & MVNETA_TX_IN_PRGRS)); | |
1267 | ||
1268 | udelay(200); | |
1269 | } | |
1270 | ||
1271 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
1272 | static void mvneta_port_enable(struct mvneta_port *pp) | |
1273 | { | |
1274 | u32 val; | |
1275 | ||
1276 | /* Enable port */ | |
1277 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1278 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
1279 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1280 | } | |
1281 | ||
1282 | /* Disable the port and wait for about 200 usec before retuning */ | |
1283 | static void mvneta_port_disable(struct mvneta_port *pp) | |
1284 | { | |
1285 | u32 val; | |
1286 | ||
1287 | /* Reset the Enable bit in the Serial Control Register */ | |
1288 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1289 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
1290 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1291 | ||
1292 | udelay(200); | |
1293 | } | |
1294 | ||
1295 | /* Multicast tables methods */ | |
1296 | ||
1297 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
1298 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
1299 | { | |
1300 | int offset; | |
1301 | u32 val; | |
1302 | ||
1303 | if (queue == -1) { | |
1304 | val = 0; | |
1305 | } else { | |
1306 | val = 0x1 | (queue << 1); | |
1307 | val |= (val << 24) | (val << 16) | (val << 8); | |
1308 | } | |
1309 | ||
1310 | for (offset = 0; offset <= 0xc; offset += 4) | |
1311 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
1312 | } | |
1313 | ||
1314 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
1315 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
1316 | { | |
1317 | int offset; | |
1318 | u32 val; | |
1319 | ||
1320 | if (queue == -1) { | |
1321 | val = 0; | |
1322 | } else { | |
1323 | val = 0x1 | (queue << 1); | |
1324 | val |= (val << 24) | (val << 16) | (val << 8); | |
1325 | } | |
1326 | ||
1327 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1328 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
1329 | ||
1330 | } | |
1331 | ||
1332 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
1333 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
1334 | { | |
1335 | int offset; | |
1336 | u32 val; | |
1337 | ||
1338 | if (queue == -1) { | |
1339 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
1340 | val = 0; | |
1341 | } else { | |
1342 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
1343 | val = 0x1 | (queue << 1); | |
1344 | val |= (val << 24) | (val << 16) | (val << 8); | |
1345 | } | |
1346 | ||
1347 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1348 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
1349 | } | |
1350 | ||
db488c10 GC |
1351 | static void mvneta_percpu_unmask_interrupt(void *arg) |
1352 | { | |
1353 | struct mvneta_port *pp = arg; | |
1354 | ||
1355 | /* All the queue are unmasked, but actually only the ones | |
1356 | * mapped to this CPU will be unmasked | |
1357 | */ | |
1358 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
1359 | MVNETA_RX_INTR_MASK_ALL | | |
1360 | MVNETA_TX_INTR_MASK_ALL | | |
1361 | MVNETA_MISCINTR_INTR_MASK); | |
1362 | } | |
1363 | ||
1364 | static void mvneta_percpu_mask_interrupt(void *arg) | |
1365 | { | |
1366 | struct mvneta_port *pp = arg; | |
1367 | ||
1368 | /* All the queue are masked, but actually only the ones | |
1369 | * mapped to this CPU will be masked | |
1370 | */ | |
1371 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1372 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
1373 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
1374 | } | |
1375 | ||
1376 | static void mvneta_percpu_clear_intr_cause(void *arg) | |
1377 | { | |
1378 | struct mvneta_port *pp = arg; | |
1379 | ||
1380 | /* All the queue are cleared, but actually only the ones | |
1381 | * mapped to this CPU will be cleared | |
1382 | */ | |
1383 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
1384 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
1385 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
1386 | } | |
1387 | ||
c5aff182 TP |
1388 | /* This method sets defaults to the NETA port: |
1389 | * Clears interrupt Cause and Mask registers. | |
1390 | * Clears all MAC tables. | |
1391 | * Sets defaults to all registers. | |
1392 | * Resets RX and TX descriptor rings. | |
1393 | * Resets PHY. | |
1394 | * This method can be called after mvneta_port_down() to return the port | |
1395 | * settings to defaults. | |
1396 | */ | |
1397 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
1398 | { | |
1399 | int cpu; | |
1400 | int queue; | |
1401 | u32 val; | |
2dcf75e2 | 1402 | int max_cpu = num_present_cpus(); |
c5aff182 TP |
1403 | |
1404 | /* Clear all Cause registers */ | |
db488c10 | 1405 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
1406 | |
1407 | /* Mask all interrupts */ | |
db488c10 | 1408 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
1409 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
1410 | ||
1411 | /* Enable MBUS Retry bit16 */ | |
1412 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
1413 | ||
50bf8cb6 GC |
1414 | /* Set CPU queue access map. CPUs are assigned to the RX and |
1415 | * TX queues modulo their number. If there is only one TX | |
1416 | * queue then it is assigned to the CPU associated to the | |
1417 | * default RX queue. | |
6a20c175 | 1418 | */ |
2dcf75e2 GC |
1419 | for_each_present_cpu(cpu) { |
1420 | int rxq_map = 0, txq_map = 0; | |
50bf8cb6 | 1421 | int rxq, txq; |
2636ac3c MW |
1422 | if (!pp->neta_armada3700) { |
1423 | for (rxq = 0; rxq < rxq_number; rxq++) | |
1424 | if ((rxq % max_cpu) == cpu) | |
1425 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
1426 | ||
1427 | for (txq = 0; txq < txq_number; txq++) | |
1428 | if ((txq % max_cpu) == cpu) | |
1429 | txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); | |
1430 | ||
1431 | /* With only one TX queue we configure a special case | |
1432 | * which will allow to get all the irq on a single | |
1433 | * CPU | |
1434 | */ | |
1435 | if (txq_number == 1) | |
1436 | txq_map = (cpu == pp->rxq_def) ? | |
1437 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2dcf75e2 | 1438 | |
2636ac3c MW |
1439 | } else { |
1440 | txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
1441 | rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; | |
1442 | } | |
2dcf75e2 GC |
1443 | |
1444 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); | |
1445 | } | |
c5aff182 TP |
1446 | |
1447 | /* Reset RX and TX DMAs */ | |
1448 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
1449 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
1450 | ||
1451 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
1452 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
1453 | for (queue = 0; queue < txq_number; queue++) { | |
1454 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
1455 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
1456 | } | |
1457 | ||
1458 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
1459 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
1460 | ||
1461 | /* Set Port Acceleration Mode */ | |
dc35a10f MW |
1462 | if (pp->bm_priv) |
1463 | /* HW buffer management + legacy parser */ | |
1464 | val = MVNETA_ACC_MODE_EXT2; | |
1465 | else | |
1466 | /* SW buffer management + legacy parser */ | |
1467 | val = MVNETA_ACC_MODE_EXT1; | |
c5aff182 TP |
1468 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
1469 | ||
dc35a10f MW |
1470 | if (pp->bm_priv) |
1471 | mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); | |
1472 | ||
c5aff182 | 1473 | /* Update val of portCfg register accordingly with all RxQueue types */ |
90b74c01 | 1474 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); |
c5aff182 TP |
1475 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
1476 | ||
1477 | val = 0; | |
1478 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
1479 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
1480 | ||
1481 | /* Build PORT_SDMA_CONFIG_REG */ | |
1482 | val = 0; | |
1483 | ||
1484 | /* Default burst size */ | |
1485 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
1486 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 1487 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1488 | |
9ad8fef6 TP |
1489 | #if defined(__BIG_ENDIAN) |
1490 | val |= MVNETA_DESC_SWAP; | |
1491 | #endif | |
c5aff182 TP |
1492 | |
1493 | /* Assign port SDMA configuration */ | |
1494 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1495 | ||
71408602 TP |
1496 | /* Disable PHY polling in hardware, since we're using the |
1497 | * kernel phylib to do this. | |
1498 | */ | |
1499 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1500 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1501 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1502 | ||
c5aff182 TP |
1503 | mvneta_set_ucast_table(pp, -1); |
1504 | mvneta_set_special_mcast_table(pp, -1); | |
1505 | mvneta_set_other_mcast_table(pp, -1); | |
1506 | ||
1507 | /* Set port interrupt enable register - default enable all */ | |
1508 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1509 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1510 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
e483911f AL |
1511 | |
1512 | mvneta_mib_counters_clear(pp); | |
c5aff182 TP |
1513 | } |
1514 | ||
1515 | /* Set max sizes for tx queues */ | |
1516 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1517 | ||
1518 | { | |
1519 | u32 val, size, mtu; | |
1520 | int queue; | |
1521 | ||
1522 | mtu = max_tx_size * 8; | |
1523 | if (mtu > MVNETA_TX_MTU_MAX) | |
1524 | mtu = MVNETA_TX_MTU_MAX; | |
1525 | ||
1526 | /* Set MTU */ | |
1527 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1528 | val &= ~MVNETA_TX_MTU_MAX; | |
1529 | val |= mtu; | |
1530 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1531 | ||
1532 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1533 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1534 | ||
1535 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1536 | if (size < mtu) { | |
1537 | size = mtu; | |
1538 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1539 | val |= size; | |
1540 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1541 | } | |
1542 | for (queue = 0; queue < txq_number; queue++) { | |
1543 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1544 | ||
1545 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1546 | if (size < mtu) { | |
1547 | size = mtu; | |
1548 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1549 | val |= size; | |
1550 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1551 | } | |
1552 | } | |
1553 | } | |
1554 | ||
1555 | /* Set unicast address */ | |
1556 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1557 | int queue) | |
1558 | { | |
1559 | unsigned int unicast_reg; | |
1560 | unsigned int tbl_offset; | |
1561 | unsigned int reg_offset; | |
1562 | ||
1563 | /* Locate the Unicast table entry */ | |
1564 | last_nibble = (0xf & last_nibble); | |
1565 | ||
1566 | /* offset from unicast tbl base */ | |
1567 | tbl_offset = (last_nibble / 4) * 4; | |
1568 | ||
1569 | /* offset within the above reg */ | |
1570 | reg_offset = last_nibble % 4; | |
1571 | ||
1572 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1573 | ||
1574 | if (queue == -1) { | |
1575 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1576 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1577 | } else { | |
1578 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1579 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1580 | } | |
1581 | ||
1582 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1583 | } | |
1584 | ||
1585 | /* Set mac address */ | |
1586 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1587 | int queue) | |
1588 | { | |
1589 | unsigned int mac_h; | |
1590 | unsigned int mac_l; | |
1591 | ||
1592 | if (queue != -1) { | |
1593 | mac_l = (addr[4] << 8) | (addr[5]); | |
1594 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1595 | (addr[2] << 8) | (addr[3] << 0); | |
1596 | ||
1597 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1598 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1599 | } | |
1600 | ||
1601 | /* Accept frames of this address */ | |
1602 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1603 | } | |
1604 | ||
6a20c175 TP |
1605 | /* Set the number of packets that will be received before RX interrupt |
1606 | * will be generated by HW. | |
c5aff182 TP |
1607 | */ |
1608 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1609 | struct mvneta_rx_queue *rxq, u32 value) | |
1610 | { | |
1611 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1612 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
c5aff182 TP |
1613 | } |
1614 | ||
6a20c175 TP |
1615 | /* Set the time delay in usec before RX interrupt will be generated by |
1616 | * HW. | |
c5aff182 TP |
1617 | */ |
1618 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1619 | struct mvneta_rx_queue *rxq, u32 value) | |
1620 | { | |
189dd626 TP |
1621 | u32 val; |
1622 | unsigned long clk_rate; | |
1623 | ||
1624 | clk_rate = clk_get_rate(pp->clk); | |
1625 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1626 | |
1627 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
c5aff182 TP |
1628 | } |
1629 | ||
1630 | /* Set threshold for TX_DONE pkts coalescing */ | |
1631 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1632 | struct mvneta_tx_queue *txq, u32 value) | |
1633 | { | |
1634 | u32 val; | |
1635 | ||
1636 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1637 | ||
1638 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1639 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1640 | ||
1641 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
c5aff182 TP |
1642 | } |
1643 | ||
c5aff182 TP |
1644 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1645 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
f88bee1c GC |
1646 | u32 phys_addr, void *virt_addr, |
1647 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 1648 | { |
f88bee1c GC |
1649 | int i; |
1650 | ||
c5aff182 | 1651 | rx_desc->buf_phys_addr = phys_addr; |
f88bee1c GC |
1652 | i = rx_desc - rxq->descs; |
1653 | rxq->buf_virt_addr[i] = virt_addr; | |
c5aff182 TP |
1654 | } |
1655 | ||
1656 | /* Decrement sent descriptors counter */ | |
1657 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1658 | struct mvneta_tx_queue *txq, | |
1659 | int sent_desc) | |
1660 | { | |
1661 | u32 val; | |
1662 | ||
1663 | /* Only 255 TX descriptors can be updated at once */ | |
1664 | while (sent_desc > 0xff) { | |
1665 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1666 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1667 | sent_desc = sent_desc - 0xff; | |
1668 | } | |
1669 | ||
1670 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1671 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1672 | } | |
1673 | ||
1674 | /* Get number of TX descriptors already sent by HW */ | |
1675 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1676 | struct mvneta_tx_queue *txq) | |
1677 | { | |
1678 | u32 val; | |
1679 | int sent_desc; | |
1680 | ||
1681 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1682 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1683 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1684 | ||
1685 | return sent_desc; | |
1686 | } | |
1687 | ||
6a20c175 | 1688 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1689 | * The number of sent descriptors is returned. |
1690 | */ | |
1691 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1692 | struct mvneta_tx_queue *txq) | |
1693 | { | |
1694 | int sent_desc; | |
1695 | ||
1696 | /* Get number of sent descriptors */ | |
1697 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1698 | ||
1699 | /* Decrement sent descriptors counter */ | |
1700 | if (sent_desc) | |
1701 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1702 | ||
1703 | return sent_desc; | |
1704 | } | |
1705 | ||
1706 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1707 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1708 | int ip_hdr_len, int l4_proto) | |
1709 | { | |
1710 | u32 command; | |
1711 | ||
1712 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1713 | * G_L4_chk, L4_type; required only for checksum |
1714 | * calculation | |
1715 | */ | |
c5aff182 TP |
1716 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1717 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1718 | ||
0a198587 | 1719 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1720 | command |= MVNETA_TXD_IP_CSUM; |
1721 | else | |
1722 | command |= MVNETA_TX_L3_IP6; | |
1723 | ||
1724 | if (l4_proto == IPPROTO_TCP) | |
1725 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1726 | else if (l4_proto == IPPROTO_UDP) | |
1727 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1728 | else | |
1729 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1730 | ||
1731 | return command; | |
1732 | } | |
1733 | ||
1734 | ||
1735 | /* Display more error info */ | |
1736 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1737 | struct mvneta_rx_desc *rx_desc) | |
1738 | { | |
1739 | u32 status = rx_desc->status; | |
1740 | ||
c5aff182 TP |
1741 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { |
1742 | case MVNETA_RXD_ERR_CRC: | |
1743 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1744 | status, rx_desc->data_size); | |
1745 | break; | |
1746 | case MVNETA_RXD_ERR_OVERRUN: | |
1747 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1748 | status, rx_desc->data_size); | |
1749 | break; | |
1750 | case MVNETA_RXD_ERR_LEN: | |
1751 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1752 | status, rx_desc->data_size); | |
1753 | break; | |
1754 | case MVNETA_RXD_ERR_RESOURCE: | |
1755 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1756 | status, rx_desc->data_size); | |
1757 | break; | |
1758 | } | |
1759 | } | |
1760 | ||
5428213c | 1761 | /* Handle RX checksum offload based on the descriptor's status */ |
1762 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1763 | struct sk_buff *skb) |
1764 | { | |
f945cec8 YK |
1765 | if ((pp->dev->features & NETIF_F_RXCSUM) && |
1766 | (status & MVNETA_RXD_L3_IP4) && | |
5428213c | 1767 | (status & MVNETA_RXD_L4_CSUM_OK)) { |
c5aff182 TP |
1768 | skb->csum = 0; |
1769 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1770 | return; | |
1771 | } | |
1772 | ||
1773 | skb->ip_summed = CHECKSUM_NONE; | |
1774 | } | |
1775 | ||
6c498974 | 1776 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1777 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1778 | * valid queue for matching the first one found in <cause>. | |
1779 | */ | |
c5aff182 TP |
1780 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1781 | u32 cause) | |
1782 | { | |
1783 | int queue = fls(cause) - 1; | |
1784 | ||
6c498974 | 1785 | return &pp->txqs[queue]; |
c5aff182 TP |
1786 | } |
1787 | ||
1788 | /* Free tx queue skbuffs */ | |
1789 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
a29b6235 MW |
1790 | struct mvneta_tx_queue *txq, int num, |
1791 | struct netdev_queue *nq) | |
c5aff182 | 1792 | { |
a29b6235 | 1793 | unsigned int bytes_compl = 0, pkts_compl = 0; |
c5aff182 TP |
1794 | int i; |
1795 | ||
1796 | for (i = 0; i < num; i++) { | |
9e58c8b4 | 1797 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; |
c5aff182 TP |
1798 | struct mvneta_tx_desc *tx_desc = txq->descs + |
1799 | txq->txq_get_index; | |
a29b6235 | 1800 | |
c5aff182 TP |
1801 | mvneta_txq_inc_get(txq); |
1802 | ||
b0a43db9 LB |
1803 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && |
1804 | buf->type != MVNETA_TYPE_XDP_TX) | |
2e3173a3 EG |
1805 | dma_unmap_single(pp->dev->dev.parent, |
1806 | tx_desc->buf_phys_addr, | |
1807 | tx_desc->data_size, DMA_TO_DEVICE); | |
b0a43db9 LB |
1808 | if (buf->type == MVNETA_TYPE_SKB && buf->skb) { |
1809 | bytes_compl += buf->skb->len; | |
1810 | pkts_compl++; | |
1811 | dev_kfree_skb_any(buf->skb); | |
1812 | } else if (buf->type == MVNETA_TYPE_XDP_TX || | |
1813 | buf->type == MVNETA_TYPE_XDP_NDO) { | |
1814 | xdp_return_frame(buf->xdpf); | |
1815 | } | |
c5aff182 | 1816 | } |
a29b6235 MW |
1817 | |
1818 | netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); | |
c5aff182 TP |
1819 | } |
1820 | ||
1821 | /* Handle end of transmission */ | |
cd713199 | 1822 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1823 | struct mvneta_tx_queue *txq) |
1824 | { | |
1825 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1826 | int tx_done; | |
1827 | ||
1828 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1829 | if (!tx_done) |
1830 | return; | |
1831 | ||
a29b6235 | 1832 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
1833 | |
1834 | txq->count -= tx_done; | |
1835 | ||
1836 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1837 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1838 | netif_tx_wake_queue(nq); |
1839 | } | |
c5aff182 TP |
1840 | } |
1841 | ||
dc35a10f | 1842 | /* Refill processing for SW buffer management */ |
7e47fd84 | 1843 | /* Allocate page per descriptor */ |
c5aff182 | 1844 | static int mvneta_rx_refill(struct mvneta_port *pp, |
f88bee1c | 1845 | struct mvneta_rx_desc *rx_desc, |
7e47fd84 GC |
1846 | struct mvneta_rx_queue *rxq, |
1847 | gfp_t gfp_mask) | |
c5aff182 TP |
1848 | { |
1849 | dma_addr_t phys_addr; | |
7e47fd84 | 1850 | struct page *page; |
c5aff182 | 1851 | |
568a3fa2 LB |
1852 | page = page_pool_alloc_pages(rxq->page_pool, |
1853 | gfp_mask | __GFP_NOWARN); | |
7e47fd84 | 1854 | if (!page) |
c5aff182 TP |
1855 | return -ENOMEM; |
1856 | ||
568a3fa2 | 1857 | phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; |
7e47fd84 | 1858 | mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); |
568a3fa2 | 1859 | |
c5aff182 TP |
1860 | return 0; |
1861 | } | |
1862 | ||
1863 | /* Handle tx checksum */ | |
1864 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1865 | { | |
1866 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1867 | int ip_hdr_len = 0; | |
817dbfa5 | 1868 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1869 | u8 l4_proto; |
1870 | ||
817dbfa5 | 1871 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1872 | struct iphdr *ip4h = ip_hdr(skb); |
1873 | ||
1874 | /* Calculate IPv4 checksum and L4 checksum */ | |
1875 | ip_hdr_len = ip4h->ihl; | |
1876 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1877 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1878 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1879 | ||
1880 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1881 | if (skb_network_header_len(skb) > 0) | |
1882 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1883 | l4_proto = ip6h->nexthdr; | |
1884 | } else | |
1885 | return MVNETA_TX_L4_CSUM_NOT; | |
1886 | ||
1887 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1888 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1889 | } |
1890 | ||
1891 | return MVNETA_TX_L4_CSUM_NOT; | |
1892 | } | |
1893 | ||
c5aff182 TP |
1894 | /* Drop packets received by the RXQ and free buffers */ |
1895 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1896 | struct mvneta_rx_queue *rxq) | |
1897 | { | |
1898 | int rx_done, i; | |
1899 | ||
1900 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
dc35a10f MW |
1901 | if (rx_done) |
1902 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1903 | ||
1904 | if (pp->bm_priv) { | |
1905 | for (i = 0; i < rx_done; i++) { | |
1906 | struct mvneta_rx_desc *rx_desc = | |
1907 | mvneta_rxq_next_desc_get(rxq); | |
1908 | u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); | |
1909 | struct mvneta_bm_pool *bm_pool; | |
1910 | ||
1911 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
1912 | /* Return dropped buffer to the pool */ | |
1913 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
1914 | rx_desc->buf_phys_addr); | |
1915 | } | |
1916 | return; | |
1917 | } | |
1918 | ||
c5aff182 TP |
1919 | for (i = 0; i < rxq->size; i++) { |
1920 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
f88bee1c | 1921 | void *data = rxq->buf_virt_addr[i]; |
562e2f46 YK |
1922 | if (!data || !(rx_desc->buf_phys_addr)) |
1923 | continue; | |
c5aff182 | 1924 | |
568a3fa2 | 1925 | page_pool_put_page(rxq->page_pool, data, false); |
c5aff182 | 1926 | } |
568a3fa2 LB |
1927 | if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) |
1928 | xdp_rxq_info_unreg(&rxq->xdp_rxq); | |
1929 | page_pool_destroy(rxq->page_pool); | |
1930 | rxq->page_pool = NULL; | |
dc35a10f | 1931 | } |
c5aff182 | 1932 | |
ff519e2a LB |
1933 | static void |
1934 | mvneta_update_stats(struct mvneta_port *pp, u32 pkts, | |
1935 | u32 len, bool tx) | |
1936 | { | |
1937 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
1938 | ||
1939 | u64_stats_update_begin(&stats->syncp); | |
1940 | if (tx) { | |
1941 | stats->tx_packets += pkts; | |
1942 | stats->tx_bytes += len; | |
1943 | } else { | |
1944 | stats->rx_packets += pkts; | |
1945 | stats->rx_bytes += len; | |
1946 | } | |
1947 | u64_stats_update_end(&stats->syncp); | |
1948 | } | |
1949 | ||
562e2f46 YK |
1950 | static inline |
1951 | int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) | |
1952 | { | |
1953 | struct mvneta_rx_desc *rx_desc; | |
1954 | int curr_desc = rxq->first_to_refill; | |
1955 | int i; | |
1956 | ||
1957 | for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { | |
1958 | rx_desc = rxq->descs + curr_desc; | |
1959 | if (!(rx_desc->buf_phys_addr)) { | |
1960 | if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { | |
1961 | pr_err("Can't refill queue %d. Done %d from %d\n", | |
1962 | rxq->id, i, rxq->refill_num); | |
1963 | rxq->refill_err++; | |
1964 | break; | |
1965 | } | |
1966 | } | |
1967 | curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); | |
1968 | } | |
1969 | rxq->refill_num -= i; | |
1970 | rxq->first_to_refill = curr_desc; | |
1971 | ||
1972 | return i; | |
1973 | } | |
1974 | ||
b0a43db9 LB |
1975 | static int |
1976 | mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, | |
1977 | struct xdp_frame *xdpf, bool dma_map) | |
1978 | { | |
1979 | struct mvneta_tx_desc *tx_desc; | |
1980 | struct mvneta_tx_buf *buf; | |
1981 | dma_addr_t dma_addr; | |
1982 | ||
1983 | if (txq->count >= txq->tx_stop_threshold) | |
1984 | return MVNETA_XDP_DROPPED; | |
1985 | ||
1986 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1987 | ||
1988 | buf = &txq->buf[txq->txq_put_index]; | |
1989 | if (dma_map) { | |
1990 | /* ndo_xdp_xmit */ | |
1991 | dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, | |
1992 | xdpf->len, DMA_TO_DEVICE); | |
1993 | if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { | |
1994 | mvneta_txq_desc_put(txq); | |
1995 | return MVNETA_XDP_DROPPED; | |
1996 | } | |
1997 | buf->type = MVNETA_TYPE_XDP_NDO; | |
1998 | } else { | |
1999 | struct page *page = virt_to_page(xdpf->data); | |
2000 | ||
2001 | dma_addr = page_pool_get_dma_addr(page) + | |
2002 | sizeof(*xdpf) + xdpf->headroom; | |
2003 | dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, | |
2004 | xdpf->len, DMA_BIDIRECTIONAL); | |
2005 | buf->type = MVNETA_TYPE_XDP_TX; | |
2006 | } | |
2007 | buf->xdpf = xdpf; | |
2008 | ||
2009 | tx_desc->command = MVNETA_TXD_FLZ_DESC; | |
2010 | tx_desc->buf_phys_addr = dma_addr; | |
2011 | tx_desc->data_size = xdpf->len; | |
2012 | ||
2013 | mvneta_update_stats(pp, 1, xdpf->len, true); | |
2014 | mvneta_txq_inc_put(txq); | |
2015 | txq->pending++; | |
2016 | txq->count++; | |
2017 | ||
2018 | return MVNETA_XDP_TX; | |
2019 | } | |
2020 | ||
2021 | static int | |
2022 | mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) | |
2023 | { | |
2024 | struct mvneta_tx_queue *txq; | |
2025 | struct netdev_queue *nq; | |
2026 | struct xdp_frame *xdpf; | |
2027 | int cpu; | |
2028 | u32 ret; | |
2029 | ||
2030 | xdpf = convert_to_xdp_frame(xdp); | |
2031 | if (unlikely(!xdpf)) | |
2032 | return MVNETA_XDP_DROPPED; | |
2033 | ||
2034 | cpu = smp_processor_id(); | |
2035 | txq = &pp->txqs[cpu % txq_number]; | |
2036 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2037 | ||
2038 | __netif_tx_lock(nq, cpu); | |
2039 | ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); | |
2040 | if (ret == MVNETA_XDP_TX) | |
2041 | mvneta_txq_pend_desc_add(pp, txq, 0); | |
2042 | __netif_tx_unlock(nq); | |
2043 | ||
2044 | return ret; | |
2045 | } | |
2046 | ||
2047 | static int | |
2048 | mvneta_xdp_xmit(struct net_device *dev, int num_frame, | |
2049 | struct xdp_frame **frames, u32 flags) | |
2050 | { | |
2051 | struct mvneta_port *pp = netdev_priv(dev); | |
2052 | int cpu = smp_processor_id(); | |
2053 | struct mvneta_tx_queue *txq; | |
2054 | struct netdev_queue *nq; | |
2055 | int i, drops = 0; | |
2056 | u32 ret; | |
2057 | ||
2058 | if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) | |
2059 | return -EINVAL; | |
2060 | ||
2061 | txq = &pp->txqs[cpu % txq_number]; | |
2062 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2063 | ||
2064 | __netif_tx_lock(nq, cpu); | |
2065 | for (i = 0; i < num_frame; i++) { | |
2066 | ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); | |
2067 | if (ret != MVNETA_XDP_TX) { | |
2068 | xdp_return_frame_rx_napi(frames[i]); | |
2069 | drops++; | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | if (unlikely(flags & XDP_XMIT_FLUSH)) | |
2074 | mvneta_txq_pend_desc_add(pp, txq, 0); | |
2075 | __netif_tx_unlock(nq); | |
2076 | ||
2077 | return num_frame - drops; | |
2078 | } | |
2079 | ||
0db51da7 LB |
2080 | static int |
2081 | mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
2082 | struct bpf_prog *prog, struct xdp_buff *xdp) | |
2083 | { | |
2084 | u32 ret, act = bpf_prog_run_xdp(prog, xdp); | |
2085 | ||
2086 | switch (act) { | |
2087 | case XDP_PASS: | |
2088 | ret = MVNETA_XDP_PASS; | |
2089 | break; | |
2090 | case XDP_REDIRECT: { | |
2091 | int err; | |
2092 | ||
2093 | err = xdp_do_redirect(pp->dev, xdp, prog); | |
2094 | if (err) { | |
2095 | ret = MVNETA_XDP_DROPPED; | |
07e13edb LB |
2096 | __page_pool_put_page(rxq->page_pool, |
2097 | virt_to_head_page(xdp->data), | |
2098 | xdp->data_end - xdp->data_hard_start, | |
2099 | true); | |
0db51da7 LB |
2100 | } else { |
2101 | ret = MVNETA_XDP_REDIR; | |
2102 | } | |
2103 | break; | |
2104 | } | |
b0a43db9 LB |
2105 | case XDP_TX: |
2106 | ret = mvneta_xdp_xmit_back(pp, xdp); | |
2107 | if (ret != MVNETA_XDP_TX) | |
07e13edb LB |
2108 | __page_pool_put_page(rxq->page_pool, |
2109 | virt_to_head_page(xdp->data), | |
2110 | xdp->data_end - xdp->data_hard_start, | |
2111 | true); | |
b0a43db9 | 2112 | break; |
0db51da7 LB |
2113 | default: |
2114 | bpf_warn_invalid_xdp_action(act); | |
2115 | /* fall through */ | |
2116 | case XDP_ABORTED: | |
2117 | trace_xdp_exception(pp->dev, prog, act); | |
2118 | /* fall through */ | |
2119 | case XDP_DROP: | |
07e13edb LB |
2120 | __page_pool_put_page(rxq->page_pool, |
2121 | virt_to_head_page(xdp->data), | |
2122 | xdp->data_end - xdp->data_hard_start, | |
2123 | true); | |
0db51da7 LB |
2124 | ret = MVNETA_XDP_DROPPED; |
2125 | break; | |
2126 | } | |
2127 | ||
2128 | return ret; | |
2129 | } | |
2130 | ||
8dc9a088 LB |
2131 | static int |
2132 | mvneta_swbm_rx_frame(struct mvneta_port *pp, | |
2133 | struct mvneta_rx_desc *rx_desc, | |
2134 | struct mvneta_rx_queue *rxq, | |
0db51da7 LB |
2135 | struct xdp_buff *xdp, |
2136 | struct bpf_prog *xdp_prog, | |
2137 | struct page *page, u32 *xdp_ret) | |
8dc9a088 LB |
2138 | { |
2139 | unsigned char *data = page_address(page); | |
2140 | int data_len = -MVNETA_MH_SIZE, len; | |
2141 | struct net_device *dev = pp->dev; | |
2142 | enum dma_data_direction dma_dir; | |
2143 | ||
2144 | if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) { | |
2145 | len = MVNETA_MAX_RX_BUF_SIZE; | |
2146 | data_len += len; | |
2147 | } else { | |
2148 | len = rx_desc->data_size; | |
2149 | data_len += len - ETH_FCS_LEN; | |
2150 | } | |
2151 | ||
2152 | dma_dir = page_pool_get_dma_dir(rxq->page_pool); | |
2153 | dma_sync_single_for_cpu(dev->dev.parent, | |
2154 | rx_desc->buf_phys_addr, | |
2155 | len, dma_dir); | |
2156 | ||
fa383f6b LB |
2157 | /* Prefetch header */ |
2158 | prefetch(data); | |
2159 | ||
0db51da7 | 2160 | xdp->data_hard_start = data; |
b37fa92e | 2161 | xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; |
0db51da7 LB |
2162 | xdp->data_end = xdp->data + data_len; |
2163 | xdp_set_data_meta_invalid(xdp); | |
2164 | ||
2165 | if (xdp_prog) { | |
2166 | u32 ret; | |
2167 | ||
2168 | ret = mvneta_run_xdp(pp, rxq, xdp_prog, xdp); | |
2169 | if (ret != MVNETA_XDP_PASS) { | |
2170 | mvneta_update_stats(pp, 1, | |
2171 | xdp->data_end - xdp->data, | |
2172 | false); | |
2173 | rx_desc->buf_phys_addr = 0; | |
2174 | *xdp_ret |= ret; | |
2175 | return ret; | |
2176 | } | |
2177 | } | |
2178 | ||
2179 | rxq->skb = build_skb(xdp->data_hard_start, PAGE_SIZE); | |
8dc9a088 LB |
2180 | if (unlikely(!rxq->skb)) { |
2181 | netdev_err(dev, | |
2182 | "Can't allocate skb on queue %d\n", | |
2183 | rxq->id); | |
2184 | dev->stats.rx_dropped++; | |
2185 | rxq->skb_alloc_err++; | |
2186 | return -ENOMEM; | |
2187 | } | |
2188 | page_pool_release_page(rxq->page_pool, page); | |
2189 | ||
0db51da7 LB |
2190 | skb_reserve(rxq->skb, |
2191 | xdp->data - xdp->data_hard_start); | |
2192 | skb_put(rxq->skb, xdp->data_end - xdp->data); | |
8dc9a088 LB |
2193 | mvneta_rx_csum(pp, rx_desc->status, rxq->skb); |
2194 | ||
2195 | rxq->left_size = rx_desc->data_size - len; | |
2196 | rx_desc->buf_phys_addr = 0; | |
2197 | ||
2198 | return 0; | |
2199 | } | |
2200 | ||
2201 | static void | |
2202 | mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, | |
2203 | struct mvneta_rx_desc *rx_desc, | |
2204 | struct mvneta_rx_queue *rxq, | |
2205 | struct page *page) | |
2206 | { | |
2207 | struct net_device *dev = pp->dev; | |
2208 | enum dma_data_direction dma_dir; | |
2209 | int data_len, len; | |
2210 | ||
2211 | if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) { | |
2212 | len = MVNETA_MAX_RX_BUF_SIZE; | |
2213 | data_len = len; | |
2214 | } else { | |
2215 | len = rxq->left_size; | |
2216 | data_len = len - ETH_FCS_LEN; | |
2217 | } | |
2218 | dma_dir = page_pool_get_dma_dir(rxq->page_pool); | |
2219 | dma_sync_single_for_cpu(dev->dev.parent, | |
2220 | rx_desc->buf_phys_addr, | |
2221 | len, dma_dir); | |
2222 | if (data_len > 0) { | |
2223 | /* refill descriptor with new buffer later */ | |
2224 | skb_add_rx_frag(rxq->skb, | |
2225 | skb_shinfo(rxq->skb)->nr_frags, | |
b37fa92e | 2226 | page, pp->rx_offset_correction, data_len, |
8dc9a088 LB |
2227 | PAGE_SIZE); |
2228 | } | |
2229 | page_pool_release_page(rxq->page_pool, page); | |
2230 | rx_desc->buf_phys_addr = 0; | |
2231 | rxq->left_size -= len; | |
2232 | } | |
2233 | ||
dc35a10f | 2234 | /* Main rx processing when using software buffer management */ |
7a86f05f | 2235 | static int mvneta_rx_swbm(struct napi_struct *napi, |
562e2f46 | 2236 | struct mvneta_port *pp, int budget, |
dc35a10f MW |
2237 | struct mvneta_rx_queue *rxq) |
2238 | { | |
8dc9a088 | 2239 | int rcvd_pkts = 0, rcvd_bytes = 0, rx_proc = 0; |
dc35a10f | 2240 | struct net_device *dev = pp->dev; |
0db51da7 LB |
2241 | struct bpf_prog *xdp_prog; |
2242 | struct xdp_buff xdp_buf; | |
8dc9a088 | 2243 | int rx_todo, refill; |
0db51da7 | 2244 | u32 xdp_ret = 0; |
dc35a10f MW |
2245 | |
2246 | /* Get number of received packets */ | |
562e2f46 | 2247 | rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); |
dc35a10f | 2248 | |
0db51da7 LB |
2249 | rcu_read_lock(); |
2250 | xdp_prog = READ_ONCE(pp->xdp_prog); | |
2251 | xdp_buf.rxq = &rxq->xdp_rxq; | |
2252 | ||
dc35a10f | 2253 | /* Fairness NAPI loop */ |
8dc9a088 | 2254 | while (rx_proc < budget && rx_proc < rx_todo) { |
dc35a10f | 2255 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); |
8dc9a088 | 2256 | u32 rx_status, index; |
7e47fd84 | 2257 | struct page *page; |
dc35a10f | 2258 | |
f88bee1c | 2259 | index = rx_desc - rxq->descs; |
7e47fd84 | 2260 | page = (struct page *)rxq->buf_virt_addr[index]; |
dc35a10f | 2261 | |
562e2f46 YK |
2262 | rx_status = rx_desc->status; |
2263 | rx_proc++; | |
2264 | rxq->refill_num++; | |
2265 | ||
2266 | if (rx_status & MVNETA_RXD_FIRST_DESC) { | |
8dc9a088 LB |
2267 | int err; |
2268 | ||
562e2f46 YK |
2269 | /* Check errors only for FIRST descriptor */ |
2270 | if (rx_status & MVNETA_RXD_ERR_SUMMARY) { | |
2271 | mvneta_rx_error(pp, rx_desc); | |
2272 | dev->stats.rx_errors++; | |
2273 | /* leave the descriptor untouched */ | |
2274 | continue; | |
2275 | } | |
dc35a10f | 2276 | |
0db51da7 LB |
2277 | err = mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, |
2278 | xdp_prog, page, &xdp_ret); | |
8dc9a088 | 2279 | if (err) |
562e2f46 | 2280 | continue; |
562e2f46 | 2281 | } else { |
562e2f46 YK |
2282 | if (unlikely(!rxq->skb)) { |
2283 | pr_debug("no skb for rx_status 0x%x\n", | |
2284 | rx_status); | |
2285 | continue; | |
2286 | } | |
8dc9a088 | 2287 | mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, page); |
562e2f46 | 2288 | } /* Middle or Last descriptor */ |
dc35a10f | 2289 | |
562e2f46 YK |
2290 | if (!(rx_status & MVNETA_RXD_LAST_DESC)) |
2291 | /* no last descriptor this time */ | |
dc35a10f | 2292 | continue; |
dc35a10f | 2293 | |
562e2f46 YK |
2294 | if (rxq->left_size) { |
2295 | pr_err("get last desc, but left_size (%d) != 0\n", | |
2296 | rxq->left_size); | |
2297 | dev_kfree_skb_any(rxq->skb); | |
2298 | rxq->left_size = 0; | |
2299 | rxq->skb = NULL; | |
2300 | continue; | |
dc35a10f | 2301 | } |
dc35a10f | 2302 | rcvd_pkts++; |
562e2f46 | 2303 | rcvd_bytes += rxq->skb->len; |
dc35a10f MW |
2304 | |
2305 | /* Linux processing */ | |
562e2f46 | 2306 | rxq->skb->protocol = eth_type_trans(rxq->skb, dev); |
dc35a10f | 2307 | |
d28118e3 | 2308 | napi_gro_receive(napi, rxq->skb); |
dc35a10f | 2309 | |
562e2f46 YK |
2310 | /* clean uncomplete skb pointer in queue */ |
2311 | rxq->skb = NULL; | |
dc35a10f | 2312 | } |
0db51da7 LB |
2313 | rcu_read_unlock(); |
2314 | ||
2315 | if (xdp_ret & MVNETA_XDP_REDIR) | |
2316 | xdp_do_flush_map(); | |
dc35a10f | 2317 | |
ff519e2a LB |
2318 | if (rcvd_pkts) |
2319 | mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); | |
dc35a10f | 2320 | |
562e2f46 YK |
2321 | /* return some buffers to hardware queue, one at a time is too slow */ |
2322 | refill = mvneta_rx_refill_queue(pp, rxq); | |
2323 | ||
dc35a10f | 2324 | /* Update rxq management counters */ |
562e2f46 | 2325 | mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); |
dc35a10f | 2326 | |
562e2f46 | 2327 | return rcvd_pkts; |
c5aff182 TP |
2328 | } |
2329 | ||
dc35a10f | 2330 | /* Main rx processing when using hardware buffer management */ |
7a86f05f AL |
2331 | static int mvneta_rx_hwbm(struct napi_struct *napi, |
2332 | struct mvneta_port *pp, int rx_todo, | |
dc35a10f | 2333 | struct mvneta_rx_queue *rxq) |
c5aff182 TP |
2334 | { |
2335 | struct net_device *dev = pp->dev; | |
a84e3289 | 2336 | int rx_done; |
dc4277dd | 2337 | u32 rcvd_pkts = 0; |
2338 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
2339 | |
2340 | /* Get number of received packets */ | |
2341 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
2342 | ||
2343 | if (rx_todo > rx_done) | |
2344 | rx_todo = rx_done; | |
2345 | ||
2346 | rx_done = 0; | |
c5aff182 TP |
2347 | |
2348 | /* Fairness NAPI loop */ | |
2349 | while (rx_done < rx_todo) { | |
2350 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
dc35a10f | 2351 | struct mvneta_bm_pool *bm_pool = NULL; |
c5aff182 | 2352 | struct sk_buff *skb; |
8ec2cd48 | 2353 | unsigned char *data; |
daf158d0 | 2354 | dma_addr_t phys_addr; |
dc35a10f | 2355 | u32 rx_status, frag_size; |
c5aff182 | 2356 | int rx_bytes, err; |
dc35a10f | 2357 | u8 pool_id; |
c5aff182 | 2358 | |
c5aff182 | 2359 | rx_done++; |
c5aff182 | 2360 | rx_status = rx_desc->status; |
f19fadfc | 2361 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
f88bee1c | 2362 | data = (u8 *)(uintptr_t)rx_desc->buf_cookie; |
daf158d0 | 2363 | phys_addr = rx_desc->buf_phys_addr; |
dc35a10f MW |
2364 | pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); |
2365 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
c5aff182 | 2366 | |
5428213c | 2367 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 2368 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
dc35a10f MW |
2369 | err_drop_frame_ret_pool: |
2370 | /* Return the buffer to the pool */ | |
2371 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2372 | rx_desc->buf_phys_addr); | |
2373 | err_drop_frame: | |
c5aff182 TP |
2374 | dev->stats.rx_errors++; |
2375 | mvneta_rx_error(pp, rx_desc); | |
8ec2cd48 | 2376 | /* leave the descriptor untouched */ |
c5aff182 TP |
2377 | continue; |
2378 | } | |
2379 | ||
f19fadfc | 2380 | if (rx_bytes <= rx_copybreak) { |
2381 | /* better copy a small frame and not unmap the DMA region */ | |
2382 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
2383 | if (unlikely(!skb)) | |
dc35a10f | 2384 | goto err_drop_frame_ret_pool; |
f19fadfc | 2385 | |
a8fef9ba | 2386 | dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, |
f19fadfc | 2387 | rx_desc->buf_phys_addr, |
2388 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
2389 | rx_bytes, | |
2390 | DMA_FROM_DEVICE); | |
59ae1d12 JB |
2391 | skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, |
2392 | rx_bytes); | |
f19fadfc | 2393 | |
2394 | skb->protocol = eth_type_trans(skb, dev); | |
2395 | mvneta_rx_csum(pp, rx_status, skb); | |
7a86f05f | 2396 | napi_gro_receive(napi, skb); |
f19fadfc | 2397 | |
2398 | rcvd_pkts++; | |
2399 | rcvd_bytes += rx_bytes; | |
2400 | ||
dc35a10f MW |
2401 | /* Return the buffer to the pool */ |
2402 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2403 | rx_desc->buf_phys_addr); | |
2404 | ||
f19fadfc | 2405 | /* leave the descriptor and buffer untouched */ |
2406 | continue; | |
2407 | } | |
2408 | ||
a84e3289 | 2409 | /* Refill processing */ |
baa11ebc | 2410 | err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); |
a84e3289 SG |
2411 | if (err) { |
2412 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
17a96da6 | 2413 | rxq->refill_err++; |
dc35a10f | 2414 | goto err_drop_frame_ret_pool; |
a84e3289 SG |
2415 | } |
2416 | ||
baa11ebc | 2417 | frag_size = bm_pool->hwbm_pool.frag_size; |
dc35a10f MW |
2418 | |
2419 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
f19fadfc | 2420 | |
26c17a17 MW |
2421 | /* After refill old buffer has to be unmapped regardless |
2422 | * the skb is successfully built or not. | |
2423 | */ | |
dc35a10f MW |
2424 | dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, |
2425 | bm_pool->buf_size, DMA_FROM_DEVICE); | |
26c17a17 MW |
2426 | if (!skb) |
2427 | goto err_drop_frame; | |
2428 | ||
dc4277dd | 2429 | rcvd_pkts++; |
2430 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
2431 | |
2432 | /* Linux processing */ | |
8ec2cd48 | 2433 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
2434 | skb_put(skb, rx_bytes); |
2435 | ||
2436 | skb->protocol = eth_type_trans(skb, dev); | |
2437 | ||
5428213c | 2438 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 | 2439 | |
7a86f05f | 2440 | napi_gro_receive(napi, skb); |
c5aff182 TP |
2441 | } |
2442 | ||
ff519e2a LB |
2443 | if (rcvd_pkts) |
2444 | mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); | |
dc4277dd | 2445 | |
c5aff182 | 2446 | /* Update rxq management counters */ |
a84e3289 | 2447 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
2448 | |
2449 | return rx_done; | |
2450 | } | |
2451 | ||
2adb719d EG |
2452 | static inline void |
2453 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
2454 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
2455 | { | |
2adb719d | 2456 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
9e58c8b4 LB |
2457 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
2458 | struct mvneta_tx_desc *tx_desc; | |
2adb719d | 2459 | |
2adb719d EG |
2460 | tx_desc = mvneta_txq_next_desc_get(txq); |
2461 | tx_desc->data_size = hdr_len; | |
2462 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
2463 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
2464 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
2465 | txq->txq_put_index * TSO_HEADER_SIZE; | |
9e58c8b4 LB |
2466 | buf->type = MVNETA_TYPE_SKB; |
2467 | buf->skb = NULL; | |
2468 | ||
2adb719d EG |
2469 | mvneta_txq_inc_put(txq); |
2470 | } | |
2471 | ||
2472 | static inline int | |
2473 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
2474 | struct sk_buff *skb, char *data, int size, | |
2475 | bool last_tcp, bool is_last) | |
2476 | { | |
9e58c8b4 | 2477 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
2adb719d EG |
2478 | struct mvneta_tx_desc *tx_desc; |
2479 | ||
2480 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2481 | tx_desc->data_size = size; | |
2482 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
2483 | size, DMA_TO_DEVICE); | |
2484 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2485 | tx_desc->buf_phys_addr))) { | |
2486 | mvneta_txq_desc_put(txq); | |
2487 | return -ENOMEM; | |
2488 | } | |
2489 | ||
2490 | tx_desc->command = 0; | |
9e58c8b4 LB |
2491 | buf->type = MVNETA_TYPE_SKB; |
2492 | buf->skb = NULL; | |
2adb719d EG |
2493 | |
2494 | if (last_tcp) { | |
2495 | /* last descriptor in the TCP packet */ | |
2496 | tx_desc->command = MVNETA_TXD_L_DESC; | |
2497 | ||
2498 | /* last descriptor in SKB */ | |
2499 | if (is_last) | |
9e58c8b4 | 2500 | buf->skb = skb; |
2adb719d EG |
2501 | } |
2502 | mvneta_txq_inc_put(txq); | |
2503 | return 0; | |
2504 | } | |
2505 | ||
2506 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
2507 | struct mvneta_tx_queue *txq) | |
2508 | { | |
2509 | int total_len, data_left; | |
2510 | int desc_count = 0; | |
2511 | struct mvneta_port *pp = netdev_priv(dev); | |
2512 | struct tso_t tso; | |
2513 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2514 | int i; | |
2515 | ||
2516 | /* Count needed descriptors */ | |
2517 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
2518 | return 0; | |
2519 | ||
2520 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
2521 | pr_info("*** Is this even possible???!?!?\n"); | |
2522 | return 0; | |
2523 | } | |
2524 | ||
2525 | /* Initialize the TSO handler, and prepare the first payload */ | |
2526 | tso_start(skb, &tso); | |
2527 | ||
2528 | total_len = skb->len - hdr_len; | |
2529 | while (total_len > 0) { | |
2530 | char *hdr; | |
2531 | ||
2532 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
2533 | total_len -= data_left; | |
2534 | desc_count++; | |
2535 | ||
2536 | /* prepare packet headers: MAC + IP + TCP */ | |
2537 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
2538 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
2539 | ||
2540 | mvneta_tso_put_hdr(skb, pp, txq); | |
2541 | ||
2542 | while (data_left > 0) { | |
2543 | int size; | |
2544 | desc_count++; | |
2545 | ||
2546 | size = min_t(int, tso.size, data_left); | |
2547 | ||
2548 | if (mvneta_tso_put_data(dev, txq, skb, | |
2549 | tso.data, size, | |
2550 | size == data_left, | |
2551 | total_len == 0)) | |
2552 | goto err_release; | |
2553 | data_left -= size; | |
2554 | ||
2555 | tso_build_data(skb, &tso, size); | |
2556 | } | |
2557 | } | |
2558 | ||
2559 | return desc_count; | |
2560 | ||
2561 | err_release: | |
2562 | /* Release all used data descriptors; header descriptors must not | |
2563 | * be DMA-unmapped. | |
2564 | */ | |
2565 | for (i = desc_count - 1; i >= 0; i--) { | |
2566 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 2567 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
2568 | dma_unmap_single(pp->dev->dev.parent, |
2569 | tx_desc->buf_phys_addr, | |
2570 | tx_desc->data_size, | |
2571 | DMA_TO_DEVICE); | |
2572 | mvneta_txq_desc_put(txq); | |
2573 | } | |
2574 | return 0; | |
2575 | } | |
2576 | ||
c5aff182 TP |
2577 | /* Handle tx fragmentation processing */ |
2578 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
2579 | struct mvneta_tx_queue *txq) | |
2580 | { | |
2581 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 2582 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 2583 | |
3d4ea02f | 2584 | for (i = 0; i < nr_frags; i++) { |
9e58c8b4 | 2585 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
c5aff182 | 2586 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
d7840976 | 2587 | void *addr = skb_frag_address(frag); |
c5aff182 TP |
2588 | |
2589 | tx_desc = mvneta_txq_next_desc_get(txq); | |
d7840976 | 2590 | tx_desc->data_size = skb_frag_size(frag); |
c5aff182 TP |
2591 | |
2592 | tx_desc->buf_phys_addr = | |
2593 | dma_map_single(pp->dev->dev.parent, addr, | |
2594 | tx_desc->data_size, DMA_TO_DEVICE); | |
2595 | ||
2596 | if (dma_mapping_error(pp->dev->dev.parent, | |
2597 | tx_desc->buf_phys_addr)) { | |
2598 | mvneta_txq_desc_put(txq); | |
2599 | goto error; | |
2600 | } | |
2601 | ||
3d4ea02f | 2602 | if (i == nr_frags - 1) { |
c5aff182 TP |
2603 | /* Last descriptor */ |
2604 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
9e58c8b4 | 2605 | buf->skb = skb; |
c5aff182 TP |
2606 | } else { |
2607 | /* Descriptor in the middle: Not First, Not Last */ | |
2608 | tx_desc->command = 0; | |
9e58c8b4 | 2609 | buf->skb = NULL; |
c5aff182 | 2610 | } |
9e58c8b4 | 2611 | buf->type = MVNETA_TYPE_SKB; |
3d4ea02f | 2612 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
2613 | } |
2614 | ||
2615 | return 0; | |
2616 | ||
2617 | error: | |
2618 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
2619 | * this packet, as well as the corresponding DMA mappings |
2620 | */ | |
c5aff182 TP |
2621 | for (i = i - 1; i >= 0; i--) { |
2622 | tx_desc = txq->descs + i; | |
2623 | dma_unmap_single(pp->dev->dev.parent, | |
2624 | tx_desc->buf_phys_addr, | |
2625 | tx_desc->data_size, | |
2626 | DMA_TO_DEVICE); | |
2627 | mvneta_txq_desc_put(txq); | |
2628 | } | |
2629 | ||
2630 | return -ENOMEM; | |
2631 | } | |
2632 | ||
2633 | /* Main tx processing */ | |
f03508ce | 2634 | static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) |
c5aff182 TP |
2635 | { |
2636 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
2637 | u16 txq_id = skb_get_queue_mapping(skb); |
2638 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
9e58c8b4 | 2639 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
c5aff182 | 2640 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 2641 | int len = skb->len; |
c5aff182 TP |
2642 | int frags = 0; |
2643 | u32 tx_cmd; | |
2644 | ||
2645 | if (!netif_running(dev)) | |
2646 | goto out; | |
2647 | ||
2adb719d EG |
2648 | if (skb_is_gso(skb)) { |
2649 | frags = mvneta_tx_tso(skb, dev, txq); | |
2650 | goto out; | |
2651 | } | |
2652 | ||
c5aff182 | 2653 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
2654 | |
2655 | /* Get a descriptor for the first part of the packet */ | |
2656 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2657 | ||
2658 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
2659 | ||
2660 | tx_desc->data_size = skb_headlen(skb); | |
2661 | ||
2662 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
2663 | tx_desc->data_size, | |
2664 | DMA_TO_DEVICE); | |
2665 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2666 | tx_desc->buf_phys_addr))) { | |
2667 | mvneta_txq_desc_put(txq); | |
2668 | frags = 0; | |
2669 | goto out; | |
2670 | } | |
2671 | ||
9e58c8b4 | 2672 | buf->type = MVNETA_TYPE_SKB; |
c5aff182 TP |
2673 | if (frags == 1) { |
2674 | /* First and Last descriptor */ | |
2675 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
2676 | tx_desc->command = tx_cmd; | |
9e58c8b4 | 2677 | buf->skb = skb; |
c5aff182 TP |
2678 | mvneta_txq_inc_put(txq); |
2679 | } else { | |
2680 | /* First but not Last */ | |
2681 | tx_cmd |= MVNETA_TXD_F_DESC; | |
9e58c8b4 | 2682 | buf->skb = NULL; |
c5aff182 TP |
2683 | mvneta_txq_inc_put(txq); |
2684 | tx_desc->command = tx_cmd; | |
2685 | /* Continue with other skb fragments */ | |
2686 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
2687 | dma_unmap_single(dev->dev.parent, | |
2688 | tx_desc->buf_phys_addr, | |
2689 | tx_desc->data_size, | |
2690 | DMA_TO_DEVICE); | |
2691 | mvneta_txq_desc_put(txq); | |
2692 | frags = 0; | |
2693 | goto out; | |
2694 | } | |
2695 | } | |
2696 | ||
c5aff182 TP |
2697 | out: |
2698 | if (frags > 0) { | |
e19d2dda EG |
2699 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
2700 | ||
a29b6235 MW |
2701 | netdev_tx_sent_queue(nq, len); |
2702 | ||
e19d2dda | 2703 | txq->count += frags; |
8eef5f97 | 2704 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 2705 | netif_tx_stop_queue(nq); |
c5aff182 | 2706 | |
6b16f9ee | 2707 | if (!netdev_xmit_more() || netif_xmit_stopped(nq) || |
2a90f7e1 SG |
2708 | txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) |
2709 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
2710 | else | |
2711 | txq->pending += frags; | |
2712 | ||
ff519e2a | 2713 | mvneta_update_stats(pp, 1, len, true); |
c5aff182 TP |
2714 | } else { |
2715 | dev->stats.tx_dropped++; | |
2716 | dev_kfree_skb_any(skb); | |
2717 | } | |
2718 | ||
c5aff182 TP |
2719 | return NETDEV_TX_OK; |
2720 | } | |
2721 | ||
2722 | ||
2723 | /* Free tx resources, when resetting a port */ | |
2724 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
2725 | struct mvneta_tx_queue *txq) | |
2726 | ||
2727 | { | |
a29b6235 | 2728 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
c5aff182 TP |
2729 | int tx_done = txq->count; |
2730 | ||
a29b6235 | 2731 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
2732 | |
2733 | /* reset txq */ | |
2734 | txq->count = 0; | |
2735 | txq->txq_put_index = 0; | |
2736 | txq->txq_get_index = 0; | |
2737 | } | |
2738 | ||
6c498974 | 2739 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
2740 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
2741 | */ | |
0713a86a | 2742 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
2743 | { |
2744 | struct mvneta_tx_queue *txq; | |
c5aff182 | 2745 | struct netdev_queue *nq; |
bd9f1ee3 | 2746 | int cpu = smp_processor_id(); |
c5aff182 | 2747 | |
6c498974 | 2748 | while (cause_tx_done) { |
c5aff182 | 2749 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
2750 | |
2751 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
bd9f1ee3 | 2752 | __netif_tx_lock(nq, cpu); |
c5aff182 | 2753 | |
0713a86a AE |
2754 | if (txq->count) |
2755 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
2756 | |
2757 | __netif_tx_unlock(nq); | |
2758 | cause_tx_done &= ~((1 << txq->id)); | |
2759 | } | |
c5aff182 TP |
2760 | } |
2761 | ||
6a20c175 | 2762 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
2763 | * according to hw spec, different than generic crc8 algorithm |
2764 | */ | |
2765 | static int mvneta_addr_crc(unsigned char *addr) | |
2766 | { | |
2767 | int crc = 0; | |
2768 | int i; | |
2769 | ||
2770 | for (i = 0; i < ETH_ALEN; i++) { | |
2771 | int j; | |
2772 | ||
2773 | crc = (crc ^ addr[i]) << 8; | |
2774 | for (j = 7; j >= 0; j--) { | |
2775 | if (crc & (0x100 << j)) | |
2776 | crc ^= 0x107 << j; | |
2777 | } | |
2778 | } | |
2779 | ||
2780 | return crc; | |
2781 | } | |
2782 | ||
2783 | /* This method controls the net device special MAC multicast support. | |
2784 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
2785 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2786 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2787 | * Table entries in the DA-Filter table. This method set the Special | |
2788 | * Multicast Table appropriate entry. | |
2789 | */ | |
2790 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
2791 | unsigned char last_byte, | |
2792 | int queue) | |
2793 | { | |
2794 | unsigned int smc_table_reg; | |
2795 | unsigned int tbl_offset; | |
2796 | unsigned int reg_offset; | |
2797 | ||
2798 | /* Register offset from SMC table base */ | |
2799 | tbl_offset = (last_byte / 4); | |
2800 | /* Entry offset within the above reg */ | |
2801 | reg_offset = last_byte % 4; | |
2802 | ||
2803 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
2804 | + tbl_offset * 4)); | |
2805 | ||
2806 | if (queue == -1) | |
2807 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2808 | else { | |
2809 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2810 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2811 | } | |
2812 | ||
2813 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
2814 | smc_table_reg); | |
2815 | } | |
2816 | ||
2817 | /* This method controls the network device Other MAC multicast support. | |
2818 | * The Other Multicast Table is used for multicast of another type. | |
2819 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
2820 | * in the DA-Filter table. | |
2821 | * The method gets the CRC-8 value from the calling routine and | |
2822 | * sets the Other Multicast Table appropriate entry according to the | |
2823 | * specified CRC-8 . | |
2824 | */ | |
2825 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
2826 | unsigned char crc8, | |
2827 | int queue) | |
2828 | { | |
2829 | unsigned int omc_table_reg; | |
2830 | unsigned int tbl_offset; | |
2831 | unsigned int reg_offset; | |
2832 | ||
2833 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
2834 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
2835 | ||
2836 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
2837 | ||
2838 | if (queue == -1) { | |
2839 | /* Clear accepts frame bit at specified Other DA table entry */ | |
2840 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2841 | } else { | |
2842 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2843 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2844 | } | |
2845 | ||
2846 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
2847 | } | |
2848 | ||
2849 | /* The network device supports multicast using two tables: | |
2850 | * 1) Special Multicast Table for MAC addresses of the form | |
2851 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2852 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2853 | * Table entries in the DA-Filter table. | |
2854 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
2855 | * is used as an index to the Other Multicast Table entries in the | |
2856 | * DA-Filter table. | |
2857 | */ | |
2858 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
2859 | int queue) | |
2860 | { | |
2861 | unsigned char crc_result = 0; | |
2862 | ||
2863 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
2864 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
2865 | return 0; | |
2866 | } | |
2867 | ||
2868 | crc_result = mvneta_addr_crc(p_addr); | |
2869 | if (queue == -1) { | |
2870 | if (pp->mcast_count[crc_result] == 0) { | |
2871 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
2872 | crc_result); | |
2873 | return -EINVAL; | |
2874 | } | |
2875 | ||
2876 | pp->mcast_count[crc_result]--; | |
2877 | if (pp->mcast_count[crc_result] != 0) { | |
2878 | netdev_info(pp->dev, | |
2879 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
2880 | pp->mcast_count[crc_result], crc_result); | |
2881 | return -EINVAL; | |
2882 | } | |
2883 | } else | |
2884 | pp->mcast_count[crc_result]++; | |
2885 | ||
2886 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
2887 | ||
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | /* Configure Fitering mode of Ethernet port */ | |
2892 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
2893 | int is_promisc) | |
2894 | { | |
2895 | u32 port_cfg_reg, val; | |
2896 | ||
2897 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
2898 | ||
2899 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
2900 | ||
2901 | /* Set / Clear UPM bit in port configuration register */ | |
2902 | if (is_promisc) { | |
2903 | /* Accept all Unicast addresses */ | |
2904 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
2905 | val |= MVNETA_FORCE_UNI; | |
2906 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
2907 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
2908 | } else { | |
2909 | /* Reject all Unicast addresses */ | |
2910 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
2911 | val &= ~MVNETA_FORCE_UNI; | |
2912 | } | |
2913 | ||
2914 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
2915 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
2916 | } | |
2917 | ||
2918 | /* register unicast and multicast addresses */ | |
2919 | static void mvneta_set_rx_mode(struct net_device *dev) | |
2920 | { | |
2921 | struct mvneta_port *pp = netdev_priv(dev); | |
2922 | struct netdev_hw_addr *ha; | |
2923 | ||
2924 | if (dev->flags & IFF_PROMISC) { | |
2925 | /* Accept all: Multicast + Unicast */ | |
2926 | mvneta_rx_unicast_promisc_set(pp, 1); | |
90b74c01 GC |
2927 | mvneta_set_ucast_table(pp, pp->rxq_def); |
2928 | mvneta_set_special_mcast_table(pp, pp->rxq_def); | |
2929 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2930 | } else { |
2931 | /* Accept single Unicast */ | |
2932 | mvneta_rx_unicast_promisc_set(pp, 0); | |
2933 | mvneta_set_ucast_table(pp, -1); | |
90b74c01 | 2934 | mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); |
c5aff182 TP |
2935 | |
2936 | if (dev->flags & IFF_ALLMULTI) { | |
2937 | /* Accept all multicast */ | |
90b74c01 GC |
2938 | mvneta_set_special_mcast_table(pp, pp->rxq_def); |
2939 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2940 | } else { |
2941 | /* Accept only initialized multicast */ | |
2942 | mvneta_set_special_mcast_table(pp, -1); | |
2943 | mvneta_set_other_mcast_table(pp, -1); | |
2944 | ||
2945 | if (!netdev_mc_empty(dev)) { | |
2946 | netdev_for_each_mc_addr(ha, dev) { | |
2947 | mvneta_mcast_addr_set(pp, ha->addr, | |
90b74c01 | 2948 | pp->rxq_def); |
c5aff182 TP |
2949 | } |
2950 | } | |
2951 | } | |
2952 | } | |
2953 | } | |
2954 | ||
2955 | /* Interrupt handling - the callback for request_irq() */ | |
2956 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2636ac3c MW |
2957 | { |
2958 | struct mvneta_port *pp = (struct mvneta_port *)dev_id; | |
2959 | ||
2960 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2961 | napi_schedule(&pp->napi); | |
2962 | ||
2963 | return IRQ_HANDLED; | |
2964 | } | |
2965 | ||
2966 | /* Interrupt handling - the callback for request_percpu_irq() */ | |
2967 | static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) | |
c5aff182 | 2968 | { |
12bb03b4 | 2969 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 2970 | |
12bb03b4 | 2971 | disable_percpu_irq(port->pp->dev->irq); |
12bb03b4 | 2972 | napi_schedule(&port->napi); |
c5aff182 TP |
2973 | |
2974 | return IRQ_HANDLED; | |
2975 | } | |
2976 | ||
503f9aa9 | 2977 | static void mvneta_link_change(struct mvneta_port *pp) |
898b2970 | 2978 | { |
898b2970 SS |
2979 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); |
2980 | ||
503f9aa9 | 2981 | phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); |
898b2970 SS |
2982 | } |
2983 | ||
c5aff182 TP |
2984 | /* NAPI handler |
2985 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
2986 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
2987 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
2988 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
2989 | * Each CPU has its own causeRxTx register | |
2990 | */ | |
2991 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
2992 | { | |
2993 | int rx_done = 0; | |
2994 | u32 cause_rx_tx; | |
2dcf75e2 | 2995 | int rx_queue; |
c5aff182 | 2996 | struct mvneta_port *pp = netdev_priv(napi->dev); |
12bb03b4 | 2997 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
2998 | |
2999 | if (!netif_running(pp->dev)) { | |
2636ac3c | 3000 | napi_complete(napi); |
c5aff182 TP |
3001 | return rx_done; |
3002 | } | |
3003 | ||
3004 | /* Read cause register */ | |
898b2970 SS |
3005 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
3006 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
3007 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
3008 | ||
3009 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
503f9aa9 RK |
3010 | |
3011 | if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 3012 | MVNETA_CAUSE_LINK_CHANGE)) |
503f9aa9 | 3013 | mvneta_link_change(pp); |
898b2970 | 3014 | } |
71f6d1b3 | 3015 | |
3016 | /* Release Tx descriptors */ | |
3017 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 3018 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 3019 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
3020 | } | |
c5aff182 | 3021 | |
6a20c175 | 3022 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
3023 | * RX packets |
3024 | */ | |
2dcf75e2 GC |
3025 | rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); |
3026 | ||
2636ac3c MW |
3027 | cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : |
3028 | port->cause_rx_tx; | |
2dcf75e2 GC |
3029 | |
3030 | if (rx_queue) { | |
3031 | rx_queue = rx_queue - 1; | |
dc35a10f | 3032 | if (pp->bm_priv) |
7a86f05f AL |
3033 | rx_done = mvneta_rx_hwbm(napi, pp, budget, |
3034 | &pp->rxqs[rx_queue]); | |
dc35a10f | 3035 | else |
7a86f05f AL |
3036 | rx_done = mvneta_rx_swbm(napi, pp, budget, |
3037 | &pp->rxqs[rx_queue]); | |
2dcf75e2 GC |
3038 | } |
3039 | ||
6ad20165 | 3040 | if (rx_done < budget) { |
c5aff182 | 3041 | cause_rx_tx = 0; |
6ad20165 | 3042 | napi_complete_done(napi, rx_done); |
2636ac3c MW |
3043 | |
3044 | if (pp->neta_armada3700) { | |
3045 | unsigned long flags; | |
3046 | ||
3047 | local_irq_save(flags); | |
3048 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
3049 | MVNETA_RX_INTR_MASK(rxq_number) | | |
3050 | MVNETA_TX_INTR_MASK(txq_number) | | |
3051 | MVNETA_MISCINTR_INTR_MASK); | |
3052 | local_irq_restore(flags); | |
3053 | } else { | |
3054 | enable_percpu_irq(pp->dev->irq, 0); | |
3055 | } | |
c5aff182 TP |
3056 | } |
3057 | ||
2636ac3c MW |
3058 | if (pp->neta_armada3700) |
3059 | pp->cause_rx_tx = cause_rx_tx; | |
3060 | else | |
3061 | port->cause_rx_tx = cause_rx_tx; | |
3062 | ||
c5aff182 TP |
3063 | return rx_done; |
3064 | } | |
3065 | ||
568a3fa2 LB |
3066 | static int mvneta_create_page_pool(struct mvneta_port *pp, |
3067 | struct mvneta_rx_queue *rxq, int size) | |
3068 | { | |
0db51da7 | 3069 | struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); |
568a3fa2 LB |
3070 | struct page_pool_params pp_params = { |
3071 | .order = 0, | |
07e13edb | 3072 | .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, |
568a3fa2 LB |
3073 | .pool_size = size, |
3074 | .nid = cpu_to_node(0), | |
3075 | .dev = pp->dev->dev.parent, | |
0db51da7 | 3076 | .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, |
07e13edb LB |
3077 | .offset = pp->rx_offset_correction, |
3078 | .max_len = MVNETA_MAX_RX_BUF_SIZE, | |
568a3fa2 LB |
3079 | }; |
3080 | int err; | |
3081 | ||
3082 | rxq->page_pool = page_pool_create(&pp_params); | |
3083 | if (IS_ERR(rxq->page_pool)) { | |
3084 | err = PTR_ERR(rxq->page_pool); | |
3085 | rxq->page_pool = NULL; | |
3086 | return err; | |
3087 | } | |
3088 | ||
3089 | err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); | |
3090 | if (err < 0) | |
3091 | goto err_free_pp; | |
3092 | ||
3093 | err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, | |
3094 | rxq->page_pool); | |
3095 | if (err) | |
3096 | goto err_unregister_rxq; | |
3097 | ||
3098 | return 0; | |
3099 | ||
3100 | err_unregister_rxq: | |
3101 | xdp_rxq_info_unreg(&rxq->xdp_rxq); | |
3102 | err_free_pp: | |
3103 | page_pool_destroy(rxq->page_pool); | |
3104 | rxq->page_pool = NULL; | |
3105 | return err; | |
3106 | } | |
3107 | ||
c5aff182 TP |
3108 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
3109 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
3110 | int num) | |
3111 | { | |
568a3fa2 LB |
3112 | int i, err; |
3113 | ||
3114 | err = mvneta_create_page_pool(pp, rxq, num); | |
3115 | if (err < 0) | |
3116 | return err; | |
c5aff182 TP |
3117 | |
3118 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 3119 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
7e47fd84 GC |
3120 | if (mvneta_rx_refill(pp, rxq->descs + i, rxq, |
3121 | GFP_KERNEL) != 0) { | |
3122 | netdev_err(pp->dev, | |
3123 | "%s:rxq %d, %d of %d buffs filled\n", | |
3124 | __func__, rxq->id, i, num); | |
c5aff182 TP |
3125 | break; |
3126 | } | |
c5aff182 TP |
3127 | } |
3128 | ||
3129 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
3130 | * get packets) |
3131 | */ | |
c5aff182 TP |
3132 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
3133 | ||
3134 | return i; | |
3135 | } | |
3136 | ||
3137 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
3138 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
3139 | { | |
3140 | int queue; | |
3141 | ||
9672850b | 3142 | /* free the skb's in the tx ring */ |
c5aff182 TP |
3143 | for (queue = 0; queue < txq_number; queue++) |
3144 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
3145 | ||
3146 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
3147 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
3148 | } | |
3149 | ||
3150 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
3151 | { | |
3152 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
3153 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
3154 | } | |
3155 | ||
3156 | /* Rx/Tx queue initialization/cleanup methods */ | |
3157 | ||
4a188a63 JZ |
3158 | static int mvneta_rxq_sw_init(struct mvneta_port *pp, |
3159 | struct mvneta_rx_queue *rxq) | |
c5aff182 TP |
3160 | { |
3161 | rxq->size = pp->rx_ring_size; | |
3162 | ||
3163 | /* Allocate memory for RX descriptors */ | |
3164 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
3165 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3166 | &rxq->descs_phys, GFP_KERNEL); | |
f95936cc | 3167 | if (!rxq->descs) |
c5aff182 | 3168 | return -ENOMEM; |
c5aff182 | 3169 | |
c5aff182 TP |
3170 | rxq->last_desc = rxq->size - 1; |
3171 | ||
4a188a63 JZ |
3172 | return 0; |
3173 | } | |
3174 | ||
3175 | static void mvneta_rxq_hw_init(struct mvneta_port *pp, | |
3176 | struct mvneta_rx_queue *rxq) | |
3177 | { | |
c5aff182 TP |
3178 | /* Set Rx descriptors queue starting address */ |
3179 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
3180 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
3181 | ||
c5aff182 TP |
3182 | /* Set coalescing pkts and time */ |
3183 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
3184 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
3185 | ||
dc35a10f | 3186 | if (!pp->bm_priv) { |
562e2f46 YK |
3187 | /* Set Offset */ |
3188 | mvneta_rxq_offset_set(pp, rxq, 0); | |
e735fd55 | 3189 | mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? |
8dc9a088 | 3190 | MVNETA_MAX_RX_BUF_SIZE : |
e735fd55 | 3191 | MVNETA_RX_BUF_SIZE(pp->pkt_size)); |
dc35a10f | 3192 | mvneta_rxq_bm_disable(pp, rxq); |
e9f64999 | 3193 | mvneta_rxq_fill(pp, rxq, rxq->size); |
dc35a10f | 3194 | } else { |
562e2f46 YK |
3195 | /* Set Offset */ |
3196 | mvneta_rxq_offset_set(pp, rxq, | |
3197 | NET_SKB_PAD - pp->rx_offset_correction); | |
3198 | ||
dc35a10f | 3199 | mvneta_rxq_bm_enable(pp, rxq); |
562e2f46 | 3200 | /* Fill RXQ with buffers from RX pool */ |
dc35a10f MW |
3201 | mvneta_rxq_long_pool_set(pp, rxq); |
3202 | mvneta_rxq_short_pool_set(pp, rxq); | |
e9f64999 | 3203 | mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); |
dc35a10f | 3204 | } |
4a188a63 JZ |
3205 | } |
3206 | ||
3207 | /* Create a specified RX queue */ | |
3208 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
3209 | struct mvneta_rx_queue *rxq) | |
3210 | ||
3211 | { | |
3212 | int ret; | |
3213 | ||
3214 | ret = mvneta_rxq_sw_init(pp, rxq); | |
3215 | if (ret < 0) | |
3216 | return ret; | |
3217 | ||
3218 | mvneta_rxq_hw_init(pp, rxq); | |
dc35a10f | 3219 | |
c5aff182 TP |
3220 | return 0; |
3221 | } | |
3222 | ||
3223 | /* Cleanup Rx queue */ | |
3224 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
3225 | struct mvneta_rx_queue *rxq) | |
3226 | { | |
3227 | mvneta_rxq_drop_pkts(pp, rxq); | |
3228 | ||
562e2f46 YK |
3229 | if (rxq->skb) |
3230 | dev_kfree_skb_any(rxq->skb); | |
3231 | ||
c5aff182 TP |
3232 | if (rxq->descs) |
3233 | dma_free_coherent(pp->dev->dev.parent, | |
3234 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3235 | rxq->descs, | |
3236 | rxq->descs_phys); | |
3237 | ||
3238 | rxq->descs = NULL; | |
3239 | rxq->last_desc = 0; | |
3240 | rxq->next_desc_to_proc = 0; | |
3241 | rxq->descs_phys = 0; | |
562e2f46 YK |
3242 | rxq->first_to_refill = 0; |
3243 | rxq->refill_num = 0; | |
3244 | rxq->skb = NULL; | |
3245 | rxq->left_size = 0; | |
c5aff182 TP |
3246 | } |
3247 | ||
4a188a63 JZ |
3248 | static int mvneta_txq_sw_init(struct mvneta_port *pp, |
3249 | struct mvneta_tx_queue *txq) | |
c5aff182 | 3250 | { |
50bf8cb6 GC |
3251 | int cpu; |
3252 | ||
c5aff182 TP |
3253 | txq->size = pp->tx_ring_size; |
3254 | ||
8eef5f97 EG |
3255 | /* A queue must always have room for at least one skb. |
3256 | * Therefore, stop the queue when the free entries reaches | |
3257 | * the maximum number of descriptors per skb. | |
3258 | */ | |
3259 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
3260 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
3261 | ||
c5aff182 TP |
3262 | /* Allocate memory for TX descriptors */ |
3263 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
3264 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3265 | &txq->descs_phys, GFP_KERNEL); | |
f95936cc | 3266 | if (!txq->descs) |
c5aff182 | 3267 | return -ENOMEM; |
c5aff182 | 3268 | |
c5aff182 TP |
3269 | txq->last_desc = txq->size - 1; |
3270 | ||
9e58c8b4 LB |
3271 | txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); |
3272 | if (!txq->buf) { | |
c5aff182 TP |
3273 | dma_free_coherent(pp->dev->dev.parent, |
3274 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3275 | txq->descs, txq->descs_phys); | |
3276 | return -ENOMEM; | |
3277 | } | |
2adb719d EG |
3278 | |
3279 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
3280 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
3281 | txq->size * TSO_HEADER_SIZE, | |
3282 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
f95936cc | 3283 | if (!txq->tso_hdrs) { |
9e58c8b4 | 3284 | kfree(txq->buf); |
2adb719d EG |
3285 | dma_free_coherent(pp->dev->dev.parent, |
3286 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3287 | txq->descs, txq->descs_phys); | |
3288 | return -ENOMEM; | |
3289 | } | |
c5aff182 | 3290 | |
50bf8cb6 GC |
3291 | /* Setup XPS mapping */ |
3292 | if (txq_number > 1) | |
3293 | cpu = txq->id % num_present_cpus(); | |
3294 | else | |
3295 | cpu = pp->rxq_def % num_present_cpus(); | |
3296 | cpumask_set_cpu(cpu, &txq->affinity_mask); | |
3297 | netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); | |
3298 | ||
c5aff182 TP |
3299 | return 0; |
3300 | } | |
3301 | ||
4a188a63 JZ |
3302 | static void mvneta_txq_hw_init(struct mvneta_port *pp, |
3303 | struct mvneta_tx_queue *txq) | |
3304 | { | |
3305 | /* Set maximum bandwidth for enabled TXQs */ | |
3306 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
3307 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
3308 | ||
3309 | /* Set Tx descriptors queue starting address */ | |
3310 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
3311 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
3312 | ||
3313 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
3314 | } | |
3315 | ||
3316 | /* Create and initialize a tx queue */ | |
3317 | static int mvneta_txq_init(struct mvneta_port *pp, | |
3318 | struct mvneta_tx_queue *txq) | |
3319 | { | |
3320 | int ret; | |
3321 | ||
3322 | ret = mvneta_txq_sw_init(pp, txq); | |
3323 | if (ret < 0) | |
3324 | return ret; | |
3325 | ||
3326 | mvneta_txq_hw_init(pp, txq); | |
3327 | ||
3328 | return 0; | |
3329 | } | |
3330 | ||
c5aff182 | 3331 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ |
4a188a63 JZ |
3332 | static void mvneta_txq_sw_deinit(struct mvneta_port *pp, |
3333 | struct mvneta_tx_queue *txq) | |
c5aff182 | 3334 | { |
a29b6235 MW |
3335 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
3336 | ||
9e58c8b4 | 3337 | kfree(txq->buf); |
c5aff182 | 3338 | |
2adb719d EG |
3339 | if (txq->tso_hdrs) |
3340 | dma_free_coherent(pp->dev->dev.parent, | |
3341 | txq->size * TSO_HEADER_SIZE, | |
3342 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
3343 | if (txq->descs) |
3344 | dma_free_coherent(pp->dev->dev.parent, | |
3345 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3346 | txq->descs, txq->descs_phys); | |
3347 | ||
a29b6235 MW |
3348 | netdev_tx_reset_queue(nq); |
3349 | ||
c5aff182 TP |
3350 | txq->descs = NULL; |
3351 | txq->last_desc = 0; | |
3352 | txq->next_desc_to_proc = 0; | |
3353 | txq->descs_phys = 0; | |
4a188a63 | 3354 | } |
c5aff182 | 3355 | |
4a188a63 JZ |
3356 | static void mvneta_txq_hw_deinit(struct mvneta_port *pp, |
3357 | struct mvneta_tx_queue *txq) | |
3358 | { | |
c5aff182 TP |
3359 | /* Set minimum bandwidth for disabled TXQs */ |
3360 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
3361 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
3362 | ||
3363 | /* Set Tx descriptors queue starting address and size */ | |
3364 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
3365 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
3366 | } | |
3367 | ||
4a188a63 JZ |
3368 | static void mvneta_txq_deinit(struct mvneta_port *pp, |
3369 | struct mvneta_tx_queue *txq) | |
3370 | { | |
3371 | mvneta_txq_sw_deinit(pp, txq); | |
3372 | mvneta_txq_hw_deinit(pp, txq); | |
3373 | } | |
3374 | ||
c5aff182 TP |
3375 | /* Cleanup all Tx queues */ |
3376 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
3377 | { | |
3378 | int queue; | |
3379 | ||
3380 | for (queue = 0; queue < txq_number; queue++) | |
3381 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
3382 | } | |
3383 | ||
3384 | /* Cleanup all Rx queues */ | |
3385 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
3386 | { | |
2dcf75e2 GC |
3387 | int queue; |
3388 | ||
ca5902a6 | 3389 | for (queue = 0; queue < rxq_number; queue++) |
2dcf75e2 | 3390 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); |
c5aff182 TP |
3391 | } |
3392 | ||
3393 | ||
3394 | /* Init all Rx queues */ | |
3395 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
3396 | { | |
2dcf75e2 GC |
3397 | int queue; |
3398 | ||
3399 | for (queue = 0; queue < rxq_number; queue++) { | |
3400 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
3401 | ||
3402 | if (err) { | |
3403 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
3404 | __func__, queue); | |
3405 | mvneta_cleanup_rxqs(pp); | |
3406 | return err; | |
3407 | } | |
c5aff182 TP |
3408 | } |
3409 | ||
3410 | return 0; | |
3411 | } | |
3412 | ||
3413 | /* Init all tx queues */ | |
3414 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
3415 | { | |
3416 | int queue; | |
3417 | ||
3418 | for (queue = 0; queue < txq_number; queue++) { | |
3419 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
3420 | if (err) { | |
3421 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
3422 | __func__, queue); | |
3423 | mvneta_cleanup_txqs(pp); | |
3424 | return err; | |
3425 | } | |
3426 | } | |
3427 | ||
3428 | return 0; | |
3429 | } | |
3430 | ||
031b922b MB |
3431 | static int mvneta_comphy_init(struct mvneta_port *pp) |
3432 | { | |
3433 | int ret; | |
3434 | ||
3435 | if (!pp->comphy) | |
3436 | return 0; | |
3437 | ||
3438 | ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, | |
3439 | pp->phy_interface); | |
3440 | if (ret) | |
3441 | return ret; | |
3442 | ||
3443 | return phy_power_on(pp->comphy); | |
3444 | } | |
3445 | ||
c5aff182 TP |
3446 | static void mvneta_start_dev(struct mvneta_port *pp) |
3447 | { | |
6b125d63 | 3448 | int cpu; |
12bb03b4 | 3449 | |
031b922b | 3450 | WARN_ON(mvneta_comphy_init(pp)); |
a10c1c81 | 3451 | |
c5aff182 TP |
3452 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
3453 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
3454 | ||
3455 | /* start the Rx/Tx activity */ | |
3456 | mvneta_port_enable(pp); | |
3457 | ||
2636ac3c MW |
3458 | if (!pp->neta_armada3700) { |
3459 | /* Enable polling on the port */ | |
3460 | for_each_online_cpu(cpu) { | |
3461 | struct mvneta_pcpu_port *port = | |
3462 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3463 | |
2636ac3c MW |
3464 | napi_enable(&port->napi); |
3465 | } | |
3466 | } else { | |
3467 | napi_enable(&pp->napi); | |
12bb03b4 | 3468 | } |
c5aff182 | 3469 | |
2dcf75e2 | 3470 | /* Unmask interrupts. It has to be done from each CPU */ |
6b125d63 GC |
3471 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); |
3472 | ||
898b2970 SS |
3473 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
3474 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 3475 | MVNETA_CAUSE_LINK_CHANGE); |
c5aff182 | 3476 | |
503f9aa9 | 3477 | phylink_start(pp->phylink); |
c5aff182 TP |
3478 | netif_tx_start_all_queues(pp->dev); |
3479 | } | |
3480 | ||
3481 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
3482 | { | |
12bb03b4 MR |
3483 | unsigned int cpu; |
3484 | ||
503f9aa9 | 3485 | phylink_stop(pp->phylink); |
c5aff182 | 3486 | |
2636ac3c MW |
3487 | if (!pp->neta_armada3700) { |
3488 | for_each_online_cpu(cpu) { | |
3489 | struct mvneta_pcpu_port *port = | |
3490 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3491 | |
2636ac3c MW |
3492 | napi_disable(&port->napi); |
3493 | } | |
3494 | } else { | |
3495 | napi_disable(&pp->napi); | |
12bb03b4 | 3496 | } |
c5aff182 TP |
3497 | |
3498 | netif_carrier_off(pp->dev); | |
3499 | ||
3500 | mvneta_port_down(pp); | |
3501 | netif_tx_stop_all_queues(pp->dev); | |
3502 | ||
3503 | /* Stop the port activity */ | |
3504 | mvneta_port_disable(pp); | |
3505 | ||
3506 | /* Clear all ethernet port interrupts */ | |
db488c10 | 3507 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
3508 | |
3509 | /* Mask all ethernet port interrupts */ | |
db488c10 | 3510 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
3511 | |
3512 | mvneta_tx_reset(pp); | |
3513 | mvneta_rx_reset(pp); | |
a10c1c81 RK |
3514 | |
3515 | WARN_ON(phy_power_off(pp->comphy)); | |
c5aff182 TP |
3516 | } |
3517 | ||
db5dd0db MW |
3518 | static void mvneta_percpu_enable(void *arg) |
3519 | { | |
3520 | struct mvneta_port *pp = arg; | |
3521 | ||
3522 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); | |
3523 | } | |
3524 | ||
3525 | static void mvneta_percpu_disable(void *arg) | |
3526 | { | |
3527 | struct mvneta_port *pp = arg; | |
3528 | ||
3529 | disable_percpu_irq(pp->dev->irq); | |
3530 | } | |
3531 | ||
c5aff182 TP |
3532 | /* Change the device mtu */ |
3533 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
3534 | { | |
3535 | struct mvneta_port *pp = netdev_priv(dev); | |
3536 | int ret; | |
3537 | ||
5777987e JW |
3538 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { |
3539 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
3540 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
3541 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
3542 | } | |
c5aff182 | 3543 | |
0db51da7 LB |
3544 | if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { |
3545 | netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); | |
3546 | return -EINVAL; | |
3547 | } | |
3548 | ||
c5aff182 TP |
3549 | dev->mtu = mtu; |
3550 | ||
b65657fc | 3551 | if (!netif_running(dev)) { |
dc35a10f MW |
3552 | if (pp->bm_priv) |
3553 | mvneta_bm_update_mtu(pp, mtu); | |
3554 | ||
b65657fc | 3555 | netdev_update_features(dev); |
c5aff182 | 3556 | return 0; |
b65657fc | 3557 | } |
c5aff182 | 3558 | |
6a20c175 | 3559 | /* The interface is running, so we have to force a |
a92dbd96 | 3560 | * reallocation of the queues |
c5aff182 TP |
3561 | */ |
3562 | mvneta_stop_dev(pp); | |
db5dd0db | 3563 | on_each_cpu(mvneta_percpu_disable, pp, true); |
c5aff182 TP |
3564 | |
3565 | mvneta_cleanup_txqs(pp); | |
3566 | mvneta_cleanup_rxqs(pp); | |
3567 | ||
dc35a10f MW |
3568 | if (pp->bm_priv) |
3569 | mvneta_bm_update_mtu(pp, mtu); | |
3570 | ||
a92dbd96 | 3571 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
c5aff182 TP |
3572 | |
3573 | ret = mvneta_setup_rxqs(pp); | |
3574 | if (ret) { | |
a92dbd96 | 3575 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
3576 | return ret; |
3577 | } | |
3578 | ||
a92dbd96 EG |
3579 | ret = mvneta_setup_txqs(pp); |
3580 | if (ret) { | |
3581 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
3582 | return ret; | |
3583 | } | |
c5aff182 | 3584 | |
db5dd0db | 3585 | on_each_cpu(mvneta_percpu_enable, pp, true); |
c5aff182 | 3586 | mvneta_start_dev(pp); |
c5aff182 | 3587 | |
b65657fc SG |
3588 | netdev_update_features(dev); |
3589 | ||
c5aff182 TP |
3590 | return 0; |
3591 | } | |
3592 | ||
b65657fc SG |
3593 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
3594 | netdev_features_t features) | |
3595 | { | |
3596 | struct mvneta_port *pp = netdev_priv(dev); | |
3597 | ||
3598 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
3599 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
3600 | netdev_info(dev, | |
3601 | "Disable IP checksum for MTU greater than %dB\n", | |
3602 | pp->tx_csum_limit); | |
3603 | } | |
3604 | ||
3605 | return features; | |
3606 | } | |
3607 | ||
8cc3e439 TP |
3608 | /* Get mac address */ |
3609 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
3610 | { | |
3611 | u32 mac_addr_l, mac_addr_h; | |
3612 | ||
3613 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
3614 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
3615 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
3616 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
3617 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
3618 | addr[3] = mac_addr_h & 0xFF; | |
3619 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
3620 | addr[5] = mac_addr_l & 0xFF; | |
3621 | } | |
3622 | ||
c5aff182 TP |
3623 | /* Handle setting mac address */ |
3624 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
3625 | { | |
3626 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
3627 | struct sockaddr *sockaddr = addr; |
3628 | int ret; | |
c5aff182 | 3629 | |
e68de360 EG |
3630 | ret = eth_prepare_mac_addr_change(dev, addr); |
3631 | if (ret < 0) | |
3632 | return ret; | |
c5aff182 TP |
3633 | /* Remove previous address table entry */ |
3634 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
3635 | ||
3636 | /* Set new addr in hw */ | |
90b74c01 | 3637 | mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); |
c5aff182 | 3638 | |
e68de360 | 3639 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
3640 | return 0; |
3641 | } | |
3642 | ||
44cc27e4 IC |
3643 | static void mvneta_validate(struct phylink_config *config, |
3644 | unsigned long *supported, | |
503f9aa9 RK |
3645 | struct phylink_link_state *state) |
3646 | { | |
44cc27e4 | 3647 | struct net_device *ndev = to_net_dev(config->dev); |
a10c1c81 | 3648 | struct mvneta_port *pp = netdev_priv(ndev); |
503f9aa9 RK |
3649 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
3650 | ||
22f4bf8a | 3651 | /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ |
503f9aa9 RK |
3652 | if (state->interface != PHY_INTERFACE_MODE_NA && |
3653 | state->interface != PHY_INTERFACE_MODE_QSGMII && | |
3654 | state->interface != PHY_INTERFACE_MODE_SGMII && | |
22f4bf8a | 3655 | !phy_interface_mode_is_8023z(state->interface) && |
503f9aa9 RK |
3656 | !phy_interface_mode_is_rgmii(state->interface)) { |
3657 | bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
3658 | return; | |
3659 | } | |
3660 | ||
3661 | /* Allow all the expected bits */ | |
3662 | phylink_set(mask, Autoneg); | |
3663 | phylink_set_port_modes(mask); | |
3664 | ||
4932a918 RK |
3665 | /* Asymmetric pause is unsupported */ |
3666 | phylink_set(mask, Pause); | |
da58a931 | 3667 | |
83e65df6 | 3668 | /* Half-duplex at speeds higher than 100Mbit is unsupported */ |
a10c1c81 RK |
3669 | if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { |
3670 | phylink_set(mask, 1000baseT_Full); | |
3671 | phylink_set(mask, 1000baseX_Full); | |
3672 | } | |
3673 | if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { | |
eda3d1b0 | 3674 | phylink_set(mask, 2500baseT_Full); |
a10c1c81 RK |
3675 | phylink_set(mask, 2500baseX_Full); |
3676 | } | |
22f4bf8a RK |
3677 | |
3678 | if (!phy_interface_mode_is_8023z(state->interface)) { | |
3679 | /* 10M and 100M are only supported in non-802.3z mode */ | |
3680 | phylink_set(mask, 10baseT_Half); | |
3681 | phylink_set(mask, 10baseT_Full); | |
3682 | phylink_set(mask, 100baseT_Half); | |
3683 | phylink_set(mask, 100baseT_Full); | |
3684 | } | |
503f9aa9 RK |
3685 | |
3686 | bitmap_and(supported, supported, mask, | |
3687 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
3688 | bitmap_and(state->advertising, state->advertising, mask, | |
3689 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
a10c1c81 RK |
3690 | |
3691 | /* We can only operate at 2500BaseX or 1000BaseX. If requested | |
3692 | * to advertise both, only report advertising at 2500BaseX. | |
3693 | */ | |
3694 | phylink_helper_basex_speed(state); | |
503f9aa9 RK |
3695 | } |
3696 | ||
d46b7e4f RK |
3697 | static void mvneta_mac_pcs_get_state(struct phylink_config *config, |
3698 | struct phylink_link_state *state) | |
c5aff182 | 3699 | { |
44cc27e4 | 3700 | struct net_device *ndev = to_net_dev(config->dev); |
c5aff182 | 3701 | struct mvneta_port *pp = netdev_priv(ndev); |
503f9aa9 | 3702 | u32 gmac_stat; |
c5aff182 | 3703 | |
503f9aa9 | 3704 | gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); |
c5aff182 | 3705 | |
503f9aa9 | 3706 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) |
a10c1c81 RK |
3707 | state->speed = |
3708 | state->interface == PHY_INTERFACE_MODE_2500BASEX ? | |
3709 | SPEED_2500 : SPEED_1000; | |
503f9aa9 RK |
3710 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) |
3711 | state->speed = SPEED_100; | |
3712 | else | |
3713 | state->speed = SPEED_10; | |
c5aff182 | 3714 | |
503f9aa9 RK |
3715 | state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); |
3716 | state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
3717 | state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
c5aff182 | 3718 | |
503f9aa9 | 3719 | state->pause = 0; |
4932a918 RK |
3720 | if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) |
3721 | state->pause |= MLO_PAUSE_RX; | |
3722 | if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) | |
3723 | state->pause |= MLO_PAUSE_TX; | |
503f9aa9 RK |
3724 | } |
3725 | ||
44cc27e4 | 3726 | static void mvneta_mac_an_restart(struct phylink_config *config) |
22f4bf8a | 3727 | { |
44cc27e4 | 3728 | struct net_device *ndev = to_net_dev(config->dev); |
22f4bf8a RK |
3729 | struct mvneta_port *pp = netdev_priv(ndev); |
3730 | u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3731 | ||
3732 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3733 | gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); | |
3734 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3735 | gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); | |
3736 | } | |
3737 | ||
44cc27e4 IC |
3738 | static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, |
3739 | const struct phylink_link_state *state) | |
503f9aa9 | 3740 | { |
44cc27e4 | 3741 | struct net_device *ndev = to_net_dev(config->dev); |
503f9aa9 | 3742 | struct mvneta_port *pp = netdev_priv(ndev); |
22f4bf8a | 3743 | u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
503f9aa9 | 3744 | u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
da58a931 | 3745 | u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); |
503f9aa9 RK |
3746 | u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); |
3747 | u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3748 | ||
22f4bf8a | 3749 | new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; |
32699954 RK |
3750 | new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | |
3751 | MVNETA_GMAC2_PORT_RESET); | |
da58a931 | 3752 | new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); |
503f9aa9 RK |
3753 | new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; |
3754 | new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
3755 | MVNETA_GMAC_INBAND_RESTART_AN | | |
3756 | MVNETA_GMAC_CONFIG_MII_SPEED | | |
3757 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3758 | MVNETA_GMAC_AN_SPEED_EN | | |
22f4bf8a RK |
3759 | MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | |
3760 | MVNETA_GMAC_CONFIG_FLOW_CTRL | | |
503f9aa9 RK |
3761 | MVNETA_GMAC_AN_FLOW_CTRL_EN | |
3762 | MVNETA_GMAC_CONFIG_FULL_DUPLEX | | |
3763 | MVNETA_GMAC_AN_DUPLEX_EN); | |
3764 | ||
32699954 RK |
3765 | /* Even though it might look weird, when we're configured in |
3766 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
3767 | */ | |
3768 | new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; | |
3769 | ||
3770 | if (state->interface == PHY_INTERFACE_MODE_QSGMII || | |
22f4bf8a RK |
3771 | state->interface == PHY_INTERFACE_MODE_SGMII || |
3772 | phy_interface_mode_is_8023z(state->interface)) | |
32699954 RK |
3773 | new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; |
3774 | ||
4932a918 RK |
3775 | if (phylink_test(state->advertising, Pause)) |
3776 | new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; | |
3777 | if (state->pause & MLO_PAUSE_TXRX_MASK) | |
3778 | new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; | |
3779 | ||
503f9aa9 RK |
3780 | if (!phylink_autoneg_inband(mode)) { |
3781 | /* Phy or fixed speed */ | |
3782 | if (state->duplex) | |
3783 | new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3784 | ||
da58a931 | 3785 | if (state->speed == SPEED_1000 || state->speed == SPEED_2500) |
503f9aa9 RK |
3786 | new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; |
3787 | else if (state->speed == SPEED_100) | |
3788 | new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
22f4bf8a | 3789 | } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { |
503f9aa9 RK |
3790 | /* SGMII mode receives the state from the PHY */ |
3791 | new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
3792 | new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
3793 | new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | | |
3794 | MVNETA_GMAC_FORCE_LINK_PASS)) | | |
3795 | MVNETA_GMAC_INBAND_AN_ENABLE | | |
3796 | MVNETA_GMAC_AN_SPEED_EN | | |
3797 | MVNETA_GMAC_AN_DUPLEX_EN; | |
22f4bf8a RK |
3798 | } else { |
3799 | /* 802.3z negotiation - only 1000base-X */ | |
3800 | new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; | |
3801 | new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
3802 | new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | | |
3803 | MVNETA_GMAC_FORCE_LINK_PASS)) | | |
3804 | MVNETA_GMAC_INBAND_AN_ENABLE | | |
3805 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3806 | /* The MAC only supports FD mode */ | |
3807 | MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
4932a918 RK |
3808 | |
3809 | if (state->pause & MLO_PAUSE_AN && state->an_enabled) | |
3810 | new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; | |
503f9aa9 | 3811 | } |
c5aff182 | 3812 | |
503f9aa9 RK |
3813 | /* Armada 370 documentation says we can only change the port mode |
3814 | * and in-band enable when the link is down, so force it down | |
3815 | * while making these changes. We also do this for GMAC_CTRL2 */ | |
22f4bf8a RK |
3816 | if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || |
3817 | (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || | |
503f9aa9 RK |
3818 | (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { |
3819 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3820 | (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | | |
3821 | MVNETA_GMAC_FORCE_LINK_DOWN); | |
fc548b99 | 3822 | } |
503f9aa9 | 3823 | |
a10c1c81 | 3824 | |
da58a931 MC |
3825 | /* When at 2.5G, the link partner can send frames with shortened |
3826 | * preambles. | |
3827 | */ | |
3828 | if (state->speed == SPEED_2500) | |
3829 | new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; | |
3830 | ||
031b922b | 3831 | if (pp->comphy && pp->phy_interface != state->interface && |
a10c1c81 RK |
3832 | (state->interface == PHY_INTERFACE_MODE_SGMII || |
3833 | state->interface == PHY_INTERFACE_MODE_1000BASEX || | |
031b922b MB |
3834 | state->interface == PHY_INTERFACE_MODE_2500BASEX)) { |
3835 | pp->phy_interface = state->interface; | |
3836 | ||
3837 | WARN_ON(phy_power_off(pp->comphy)); | |
3838 | WARN_ON(mvneta_comphy_init(pp)); | |
3839 | } | |
a10c1c81 | 3840 | |
22f4bf8a RK |
3841 | if (new_ctrl0 != gmac_ctrl0) |
3842 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); | |
503f9aa9 RK |
3843 | if (new_ctrl2 != gmac_ctrl2) |
3844 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); | |
da58a931 MC |
3845 | if (new_ctrl4 != gmac_ctrl4) |
3846 | mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); | |
503f9aa9 RK |
3847 | if (new_clk != gmac_clk) |
3848 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); | |
3849 | if (new_an != gmac_an) | |
3850 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); | |
32699954 RK |
3851 | |
3852 | if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { | |
3853 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
3854 | MVNETA_GMAC2_PORT_RESET) != 0) | |
3855 | continue; | |
3856 | } | |
fc548b99 | 3857 | } |
c5aff182 | 3858 | |
6d81f451 RK |
3859 | static void mvneta_set_eee(struct mvneta_port *pp, bool enable) |
3860 | { | |
3861 | u32 lpi_ctl1; | |
3862 | ||
3863 | lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); | |
3864 | if (enable) | |
3865 | lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; | |
3866 | else | |
3867 | lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; | |
3868 | mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); | |
3869 | } | |
3870 | ||
44cc27e4 IC |
3871 | static void mvneta_mac_link_down(struct phylink_config *config, |
3872 | unsigned int mode, phy_interface_t interface) | |
fc548b99 | 3873 | { |
44cc27e4 | 3874 | struct net_device *ndev = to_net_dev(config->dev); |
fc548b99 RK |
3875 | struct mvneta_port *pp = netdev_priv(ndev); |
3876 | u32 val; | |
3877 | ||
503f9aa9 RK |
3878 | mvneta_port_down(pp); |
3879 | ||
3880 | if (!phylink_autoneg_inband(mode)) { | |
fc548b99 RK |
3881 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
3882 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
3883 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
3884 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3885 | } | |
6d81f451 RK |
3886 | |
3887 | pp->eee_active = false; | |
3888 | mvneta_set_eee(pp, false); | |
fc548b99 RK |
3889 | } |
3890 | ||
44cc27e4 | 3891 | static void mvneta_mac_link_up(struct phylink_config *config, unsigned int mode, |
c6ab3008 | 3892 | phy_interface_t interface, |
503f9aa9 | 3893 | struct phy_device *phy) |
fc548b99 | 3894 | { |
44cc27e4 | 3895 | struct net_device *ndev = to_net_dev(config->dev); |
fc548b99 RK |
3896 | struct mvneta_port *pp = netdev_priv(ndev); |
3897 | u32 val; | |
3898 | ||
503f9aa9 | 3899 | if (!phylink_autoneg_inband(mode)) { |
fc548b99 RK |
3900 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
3901 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; | |
3902 | val |= MVNETA_GMAC_FORCE_LINK_PASS; | |
3903 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
c5aff182 TP |
3904 | } |
3905 | ||
fc548b99 | 3906 | mvneta_port_up(pp); |
6d81f451 RK |
3907 | |
3908 | if (phy && pp->eee_enabled) { | |
3909 | pp->eee_active = phy_init_eee(phy, 0) >= 0; | |
3910 | mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); | |
3911 | } | |
fc548b99 RK |
3912 | } |
3913 | ||
503f9aa9 RK |
3914 | static const struct phylink_mac_ops mvneta_phylink_ops = { |
3915 | .validate = mvneta_validate, | |
d46b7e4f | 3916 | .mac_pcs_get_state = mvneta_mac_pcs_get_state, |
22f4bf8a | 3917 | .mac_an_restart = mvneta_mac_an_restart, |
503f9aa9 RK |
3918 | .mac_config = mvneta_mac_config, |
3919 | .mac_link_down = mvneta_mac_link_down, | |
3920 | .mac_link_up = mvneta_mac_link_up, | |
3921 | }; | |
c5aff182 TP |
3922 | |
3923 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
3924 | { | |
82960fff | 3925 | struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; |
503f9aa9 | 3926 | int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); |
c5aff182 | 3927 | |
503f9aa9 RK |
3928 | if (err) |
3929 | netdev_err(pp->dev, "could not attach PHY: %d\n", err); | |
c5aff182 | 3930 | |
503f9aa9 | 3931 | phylink_ethtool_get_wol(pp->phylink, &wol); |
82960fff JZ |
3932 | device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); |
3933 | ||
503f9aa9 | 3934 | return err; |
c5aff182 TP |
3935 | } |
3936 | ||
3937 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
3938 | { | |
503f9aa9 | 3939 | phylink_disconnect_phy(pp->phylink); |
c5aff182 TP |
3940 | } |
3941 | ||
120cfa50 GC |
3942 | /* Electing a CPU must be done in an atomic way: it should be done |
3943 | * after or before the removal/insertion of a CPU and this function is | |
3944 | * not reentrant. | |
3945 | */ | |
f8642885 MR |
3946 | static void mvneta_percpu_elect(struct mvneta_port *pp) |
3947 | { | |
cad5d847 GC |
3948 | int elected_cpu = 0, max_cpu, cpu, i = 0; |
3949 | ||
3950 | /* Use the cpu associated to the rxq when it is online, in all | |
3951 | * the other cases, use the cpu 0 which can't be offline. | |
3952 | */ | |
3953 | if (cpu_online(pp->rxq_def)) | |
3954 | elected_cpu = pp->rxq_def; | |
f8642885 | 3955 | |
2dcf75e2 | 3956 | max_cpu = num_present_cpus(); |
f8642885 MR |
3957 | |
3958 | for_each_online_cpu(cpu) { | |
2dcf75e2 GC |
3959 | int rxq_map = 0, txq_map = 0; |
3960 | int rxq; | |
3961 | ||
3962 | for (rxq = 0; rxq < rxq_number; rxq++) | |
3963 | if ((rxq % max_cpu) == cpu) | |
3964 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
3965 | ||
cad5d847 | 3966 | if (cpu == elected_cpu) |
50bf8cb6 GC |
3967 | /* Map the default receive queue queue to the |
3968 | * elected CPU | |
f8642885 | 3969 | */ |
2dcf75e2 | 3970 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); |
50bf8cb6 GC |
3971 | |
3972 | /* We update the TX queue map only if we have one | |
3973 | * queue. In this case we associate the TX queue to | |
3974 | * the CPU bound to the default RX queue | |
3975 | */ | |
3976 | if (txq_number == 1) | |
cad5d847 | 3977 | txq_map = (cpu == elected_cpu) ? |
50bf8cb6 GC |
3978 | MVNETA_CPU_TXQ_ACCESS(1) : 0; |
3979 | else | |
3980 | txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & | |
3981 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
3982 | ||
2dcf75e2 GC |
3983 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); |
3984 | ||
3985 | /* Update the interrupt mask on each CPU according the | |
3986 | * new mapping | |
3987 | */ | |
3988 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
3989 | pp, true); | |
f8642885 | 3990 | i++; |
2dcf75e2 | 3991 | |
f8642885 MR |
3992 | } |
3993 | }; | |
3994 | ||
84a3f4db | 3995 | static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) |
f8642885 | 3996 | { |
84a3f4db SAS |
3997 | int other_cpu; |
3998 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
3999 | node_online); | |
f8642885 MR |
4000 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
4001 | ||
f8642885 | 4002 | |
84a3f4db SAS |
4003 | spin_lock(&pp->lock); |
4004 | /* | |
4005 | * Configuring the driver for a new CPU while the driver is | |
4006 | * stopping is racy, so just avoid it. | |
4007 | */ | |
4008 | if (pp->is_stopped) { | |
4009 | spin_unlock(&pp->lock); | |
4010 | return 0; | |
4011 | } | |
4012 | netif_tx_stop_all_queues(pp->dev); | |
f8642885 | 4013 | |
84a3f4db SAS |
4014 | /* |
4015 | * We have to synchronise on tha napi of each CPU except the one | |
4016 | * just being woken up | |
4017 | */ | |
4018 | for_each_online_cpu(other_cpu) { | |
4019 | if (other_cpu != cpu) { | |
4020 | struct mvneta_pcpu_port *other_port = | |
4021 | per_cpu_ptr(pp->ports, other_cpu); | |
4022 | ||
4023 | napi_synchronize(&other_port->napi); | |
f8642885 | 4024 | } |
84a3f4db | 4025 | } |
f8642885 | 4026 | |
84a3f4db SAS |
4027 | /* Mask all ethernet port interrupts */ |
4028 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
4029 | napi_enable(&port->napi); | |
f8642885 | 4030 | |
84a3f4db SAS |
4031 | /* |
4032 | * Enable per-CPU interrupts on the CPU that is | |
4033 | * brought up. | |
4034 | */ | |
4035 | mvneta_percpu_enable(pp); | |
2dcf75e2 | 4036 | |
84a3f4db SAS |
4037 | /* |
4038 | * Enable per-CPU interrupt on the one CPU we care | |
4039 | * about. | |
4040 | */ | |
4041 | mvneta_percpu_elect(pp); | |
2dcf75e2 | 4042 | |
84a3f4db SAS |
4043 | /* Unmask all ethernet port interrupts */ |
4044 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
4045 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
4046 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 4047 | MVNETA_CAUSE_LINK_CHANGE); |
84a3f4db SAS |
4048 | netif_tx_start_all_queues(pp->dev); |
4049 | spin_unlock(&pp->lock); | |
4050 | return 0; | |
4051 | } | |
f8642885 | 4052 | |
84a3f4db SAS |
4053 | static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) |
4054 | { | |
4055 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4056 | node_online); | |
4057 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
f8642885 | 4058 | |
84a3f4db SAS |
4059 | /* |
4060 | * Thanks to this lock we are sure that any pending cpu election is | |
4061 | * done. | |
4062 | */ | |
4063 | spin_lock(&pp->lock); | |
4064 | /* Mask all ethernet port interrupts */ | |
4065 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
4066 | spin_unlock(&pp->lock); | |
f8642885 | 4067 | |
84a3f4db SAS |
4068 | napi_synchronize(&port->napi); |
4069 | napi_disable(&port->napi); | |
4070 | /* Disable per-CPU interrupts on the CPU that is brought down. */ | |
4071 | mvneta_percpu_disable(pp); | |
4072 | return 0; | |
4073 | } | |
4074 | ||
4075 | static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) | |
4076 | { | |
4077 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4078 | node_dead); | |
4079 | ||
4080 | /* Check if a new CPU must be elected now this on is down */ | |
4081 | spin_lock(&pp->lock); | |
4082 | mvneta_percpu_elect(pp); | |
4083 | spin_unlock(&pp->lock); | |
4084 | /* Unmask all ethernet port interrupts */ | |
4085 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
4086 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
4087 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 4088 | MVNETA_CAUSE_LINK_CHANGE); |
84a3f4db SAS |
4089 | netif_tx_start_all_queues(pp->dev); |
4090 | return 0; | |
f8642885 MR |
4091 | } |
4092 | ||
c5aff182 TP |
4093 | static int mvneta_open(struct net_device *dev) |
4094 | { | |
4095 | struct mvneta_port *pp = netdev_priv(dev); | |
6b125d63 | 4096 | int ret; |
c5aff182 | 4097 | |
c5aff182 TP |
4098 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
4099 | ||
4100 | ret = mvneta_setup_rxqs(pp); | |
4101 | if (ret) | |
4102 | return ret; | |
4103 | ||
4104 | ret = mvneta_setup_txqs(pp); | |
4105 | if (ret) | |
4106 | goto err_cleanup_rxqs; | |
4107 | ||
4108 | /* Connect to port interrupt line */ | |
2636ac3c MW |
4109 | if (pp->neta_armada3700) |
4110 | ret = request_irq(pp->dev->irq, mvneta_isr, 0, | |
4111 | dev->name, pp); | |
4112 | else | |
4113 | ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, | |
4114 | dev->name, pp->ports); | |
c5aff182 TP |
4115 | if (ret) { |
4116 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
4117 | goto err_cleanup_txqs; | |
4118 | } | |
4119 | ||
2636ac3c MW |
4120 | if (!pp->neta_armada3700) { |
4121 | /* Enable per-CPU interrupt on all the CPU to handle our RX | |
4122 | * queue interrupts | |
4123 | */ | |
4124 | on_each_cpu(mvneta_percpu_enable, pp, true); | |
2dcf75e2 | 4125 | |
2636ac3c MW |
4126 | pp->is_stopped = false; |
4127 | /* Register a CPU notifier to handle the case where our CPU | |
4128 | * might be taken offline. | |
4129 | */ | |
4130 | ret = cpuhp_state_add_instance_nocalls(online_hpstate, | |
4131 | &pp->node_online); | |
4132 | if (ret) | |
4133 | goto err_free_irq; | |
84a3f4db | 4134 | |
2636ac3c MW |
4135 | ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, |
4136 | &pp->node_dead); | |
4137 | if (ret) | |
4138 | goto err_free_online_hp; | |
4139 | } | |
f8642885 | 4140 | |
c5aff182 TP |
4141 | ret = mvneta_mdio_probe(pp); |
4142 | if (ret < 0) { | |
4143 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
84a3f4db | 4144 | goto err_free_dead_hp; |
c5aff182 TP |
4145 | } |
4146 | ||
4147 | mvneta_start_dev(pp); | |
4148 | ||
4149 | return 0; | |
4150 | ||
84a3f4db | 4151 | err_free_dead_hp: |
2636ac3c MW |
4152 | if (!pp->neta_armada3700) |
4153 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
4154 | &pp->node_dead); | |
84a3f4db | 4155 | err_free_online_hp: |
2636ac3c MW |
4156 | if (!pp->neta_armada3700) |
4157 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
4158 | &pp->node_online); | |
c5aff182 | 4159 | err_free_irq: |
2636ac3c MW |
4160 | if (pp->neta_armada3700) { |
4161 | free_irq(pp->dev->irq, pp); | |
4162 | } else { | |
4163 | on_each_cpu(mvneta_percpu_disable, pp, true); | |
4164 | free_percpu_irq(pp->dev->irq, pp->ports); | |
4165 | } | |
c5aff182 TP |
4166 | err_cleanup_txqs: |
4167 | mvneta_cleanup_txqs(pp); | |
4168 | err_cleanup_rxqs: | |
4169 | mvneta_cleanup_rxqs(pp); | |
4170 | return ret; | |
4171 | } | |
4172 | ||
4173 | /* Stop the port, free port interrupt line */ | |
4174 | static int mvneta_stop(struct net_device *dev) | |
4175 | { | |
4176 | struct mvneta_port *pp = netdev_priv(dev); | |
4177 | ||
2636ac3c MW |
4178 | if (!pp->neta_armada3700) { |
4179 | /* Inform that we are stopping so we don't want to setup the | |
4180 | * driver for new CPUs in the notifiers. The code of the | |
4181 | * notifier for CPU online is protected by the same spinlock, | |
4182 | * so when we get the lock, the notifer work is done. | |
4183 | */ | |
4184 | spin_lock(&pp->lock); | |
4185 | pp->is_stopped = true; | |
4186 | spin_unlock(&pp->lock); | |
1c2722a9 | 4187 | |
2636ac3c MW |
4188 | mvneta_stop_dev(pp); |
4189 | mvneta_mdio_remove(pp); | |
84a3f4db | 4190 | |
d26aac2d DC |
4191 | cpuhp_state_remove_instance_nocalls(online_hpstate, |
4192 | &pp->node_online); | |
4193 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
4194 | &pp->node_dead); | |
2636ac3c MW |
4195 | on_each_cpu(mvneta_percpu_disable, pp, true); |
4196 | free_percpu_irq(dev->irq, pp->ports); | |
4197 | } else { | |
4198 | mvneta_stop_dev(pp); | |
4199 | mvneta_mdio_remove(pp); | |
4200 | free_irq(dev->irq, pp); | |
4201 | } | |
4202 | ||
c5aff182 TP |
4203 | mvneta_cleanup_rxqs(pp); |
4204 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
4205 | |
4206 | return 0; | |
4207 | } | |
4208 | ||
15f59456 TP |
4209 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4210 | { | |
503f9aa9 | 4211 | struct mvneta_port *pp = netdev_priv(dev); |
15f59456 | 4212 | |
503f9aa9 | 4213 | return phylink_mii_ioctl(pp->phylink, ifr, cmd); |
15f59456 TP |
4214 | } |
4215 | ||
0db51da7 LB |
4216 | static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, |
4217 | struct netlink_ext_ack *extack) | |
4218 | { | |
4219 | bool need_update, running = netif_running(dev); | |
4220 | struct mvneta_port *pp = netdev_priv(dev); | |
4221 | struct bpf_prog *old_prog; | |
4222 | ||
4223 | if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { | |
4224 | NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); | |
4225 | return -EOPNOTSUPP; | |
4226 | } | |
4227 | ||
4228 | need_update = !!pp->xdp_prog != !!prog; | |
4229 | if (running && need_update) | |
4230 | mvneta_stop(dev); | |
4231 | ||
4232 | old_prog = xchg(&pp->xdp_prog, prog); | |
4233 | if (old_prog) | |
4234 | bpf_prog_put(old_prog); | |
4235 | ||
4236 | if (running && need_update) | |
4237 | return mvneta_open(dev); | |
4238 | ||
4239 | return 0; | |
4240 | } | |
4241 | ||
4242 | static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) | |
4243 | { | |
4244 | struct mvneta_port *pp = netdev_priv(dev); | |
4245 | ||
4246 | switch (xdp->command) { | |
4247 | case XDP_SETUP_PROG: | |
4248 | return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); | |
4249 | case XDP_QUERY_PROG: | |
4250 | xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0; | |
4251 | return 0; | |
4252 | default: | |
4253 | return -EINVAL; | |
4254 | } | |
4255 | } | |
4256 | ||
c5aff182 TP |
4257 | /* Ethtool methods */ |
4258 | ||
013ad40d | 4259 | /* Set link ksettings (phy address, speed) for ethtools */ |
2dc0d2b4 BX |
4260 | static int |
4261 | mvneta_ethtool_set_link_ksettings(struct net_device *ndev, | |
4262 | const struct ethtool_link_ksettings *cmd) | |
c5aff182 | 4263 | { |
013ad40d | 4264 | struct mvneta_port *pp = netdev_priv(ndev); |
0c0744fc | 4265 | |
503f9aa9 RK |
4266 | return phylink_ethtool_ksettings_set(pp->phylink, cmd); |
4267 | } | |
0c0744fc | 4268 | |
503f9aa9 RK |
4269 | /* Get link ksettings for ethtools */ |
4270 | static int | |
4271 | mvneta_ethtool_get_link_ksettings(struct net_device *ndev, | |
4272 | struct ethtool_link_ksettings *cmd) | |
4273 | { | |
4274 | struct mvneta_port *pp = netdev_priv(ndev); | |
0c0744fc | 4275 | |
503f9aa9 RK |
4276 | return phylink_ethtool_ksettings_get(pp->phylink, cmd); |
4277 | } | |
0c0744fc | 4278 | |
503f9aa9 RK |
4279 | static int mvneta_ethtool_nway_reset(struct net_device *dev) |
4280 | { | |
4281 | struct mvneta_port *pp = netdev_priv(dev); | |
0c0744fc | 4282 | |
503f9aa9 | 4283 | return phylink_ethtool_nway_reset(pp->phylink); |
c5aff182 TP |
4284 | } |
4285 | ||
4286 | /* Set interrupt coalescing for ethtools */ | |
4287 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
4288 | struct ethtool_coalesce *c) | |
4289 | { | |
4290 | struct mvneta_port *pp = netdev_priv(dev); | |
4291 | int queue; | |
4292 | ||
4293 | for (queue = 0; queue < rxq_number; queue++) { | |
4294 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
4295 | rxq->time_coal = c->rx_coalesce_usecs; | |
4296 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
4297 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
4298 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
4299 | } | |
4300 | ||
4301 | for (queue = 0; queue < txq_number; queue++) { | |
4302 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
4303 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
4304 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
4305 | } | |
4306 | ||
4307 | return 0; | |
4308 | } | |
4309 | ||
4310 | /* get coalescing for ethtools */ | |
4311 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
4312 | struct ethtool_coalesce *c) | |
4313 | { | |
4314 | struct mvneta_port *pp = netdev_priv(dev); | |
4315 | ||
4316 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
4317 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
4318 | ||
4319 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
4320 | return 0; | |
4321 | } | |
4322 | ||
4323 | ||
4324 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
4325 | struct ethtool_drvinfo *drvinfo) | |
4326 | { | |
4327 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
4328 | sizeof(drvinfo->driver)); | |
4329 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
4330 | sizeof(drvinfo->version)); | |
4331 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
4332 | sizeof(drvinfo->bus_info)); | |
4333 | } | |
4334 | ||
4335 | ||
4336 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
4337 | struct ethtool_ringparam *ring) | |
4338 | { | |
4339 | struct mvneta_port *pp = netdev_priv(netdev); | |
4340 | ||
4341 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
4342 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
4343 | ring->rx_pending = pp->rx_ring_size; | |
4344 | ring->tx_pending = pp->tx_ring_size; | |
4345 | } | |
4346 | ||
4347 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
4348 | struct ethtool_ringparam *ring) | |
4349 | { | |
4350 | struct mvneta_port *pp = netdev_priv(dev); | |
4351 | ||
4352 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
4353 | return -EINVAL; | |
4354 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
4355 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
4356 | |
4357 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
4358 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
4359 | if (pp->tx_ring_size != ring->tx_pending) | |
4360 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
4361 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
4362 | |
4363 | if (netif_running(dev)) { | |
4364 | mvneta_stop(dev); | |
4365 | if (mvneta_open(dev)) { | |
4366 | netdev_err(dev, | |
4367 | "error on opening device after ring param change\n"); | |
4368 | return -ENOMEM; | |
4369 | } | |
4370 | } | |
4371 | ||
4372 | return 0; | |
4373 | } | |
4374 | ||
4932a918 RK |
4375 | static void mvneta_ethtool_get_pauseparam(struct net_device *dev, |
4376 | struct ethtool_pauseparam *pause) | |
4377 | { | |
4378 | struct mvneta_port *pp = netdev_priv(dev); | |
4379 | ||
4380 | phylink_ethtool_get_pauseparam(pp->phylink, pause); | |
4381 | } | |
4382 | ||
4383 | static int mvneta_ethtool_set_pauseparam(struct net_device *dev, | |
4384 | struct ethtool_pauseparam *pause) | |
4385 | { | |
4386 | struct mvneta_port *pp = netdev_priv(dev); | |
4387 | ||
4388 | return phylink_ethtool_set_pauseparam(pp->phylink, pause); | |
4389 | } | |
4390 | ||
9b0cdefa RK |
4391 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
4392 | u8 *data) | |
4393 | { | |
4394 | if (sset == ETH_SS_STATS) { | |
4395 | int i; | |
4396 | ||
4397 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
4398 | memcpy(data + i * ETH_GSTRING_LEN, | |
4399 | mvneta_statistics[i].name, ETH_GSTRING_LEN); | |
4400 | } | |
4401 | } | |
4402 | ||
4403 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) | |
4404 | { | |
4405 | const struct mvneta_statistic *s; | |
4406 | void __iomem *base = pp->base; | |
6d81f451 RK |
4407 | u32 high, low; |
4408 | u64 val; | |
9b0cdefa RK |
4409 | int i; |
4410 | ||
4411 | for (i = 0, s = mvneta_statistics; | |
4412 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); | |
4413 | s++, i++) { | |
6d81f451 RK |
4414 | val = 0; |
4415 | ||
9b0cdefa RK |
4416 | switch (s->type) { |
4417 | case T_REG_32: | |
4418 | val = readl_relaxed(base + s->offset); | |
4419 | break; | |
4420 | case T_REG_64: | |
4421 | /* Docs say to read low 32-bit then high */ | |
4422 | low = readl_relaxed(base + s->offset); | |
4423 | high = readl_relaxed(base + s->offset + 4); | |
6d81f451 RK |
4424 | val = (u64)high << 32 | low; |
4425 | break; | |
4426 | case T_SW: | |
4427 | switch (s->offset) { | |
4428 | case ETHTOOL_STAT_EEE_WAKEUP: | |
4429 | val = phylink_get_eee_err(pp->phylink); | |
4430 | break; | |
17a96da6 GC |
4431 | case ETHTOOL_STAT_SKB_ALLOC_ERR: |
4432 | val = pp->rxqs[0].skb_alloc_err; | |
4433 | break; | |
4434 | case ETHTOOL_STAT_REFILL_ERR: | |
4435 | val = pp->rxqs[0].refill_err; | |
4436 | break; | |
6d81f451 | 4437 | } |
9b0cdefa RK |
4438 | break; |
4439 | } | |
6d81f451 RK |
4440 | |
4441 | pp->ethtool_stats[i] += val; | |
9b0cdefa RK |
4442 | } |
4443 | } | |
4444 | ||
4445 | static void mvneta_ethtool_get_stats(struct net_device *dev, | |
4446 | struct ethtool_stats *stats, u64 *data) | |
4447 | { | |
4448 | struct mvneta_port *pp = netdev_priv(dev); | |
4449 | int i; | |
4450 | ||
4451 | mvneta_ethtool_update_stats(pp); | |
4452 | ||
4453 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
4454 | *data++ = pp->ethtool_stats[i]; | |
4455 | } | |
4456 | ||
4457 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) | |
4458 | { | |
4459 | if (sset == ETH_SS_STATS) | |
4460 | return ARRAY_SIZE(mvneta_statistics); | |
4461 | return -EOPNOTSUPP; | |
4462 | } | |
4463 | ||
9a401dea GC |
4464 | static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) |
4465 | { | |
4466 | return MVNETA_RSS_LU_TABLE_SIZE; | |
4467 | } | |
4468 | ||
4469 | static int mvneta_ethtool_get_rxnfc(struct net_device *dev, | |
4470 | struct ethtool_rxnfc *info, | |
4471 | u32 *rules __always_unused) | |
4472 | { | |
4473 | switch (info->cmd) { | |
4474 | case ETHTOOL_GRXRINGS: | |
4475 | info->data = rxq_number; | |
4476 | return 0; | |
4477 | case ETHTOOL_GRXFH: | |
4478 | return -EOPNOTSUPP; | |
4479 | default: | |
4480 | return -EOPNOTSUPP; | |
4481 | } | |
4482 | } | |
4483 | ||
4484 | static int mvneta_config_rss(struct mvneta_port *pp) | |
4485 | { | |
4486 | int cpu; | |
4487 | u32 val; | |
4488 | ||
4489 | netif_tx_stop_all_queues(pp->dev); | |
4490 | ||
6b125d63 | 4491 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
9a401dea | 4492 | |
0f5c6c30 JZ |
4493 | if (!pp->neta_armada3700) { |
4494 | /* We have to synchronise on the napi of each CPU */ | |
4495 | for_each_online_cpu(cpu) { | |
4496 | struct mvneta_pcpu_port *pcpu_port = | |
4497 | per_cpu_ptr(pp->ports, cpu); | |
9a401dea | 4498 | |
0f5c6c30 JZ |
4499 | napi_synchronize(&pcpu_port->napi); |
4500 | napi_disable(&pcpu_port->napi); | |
4501 | } | |
4502 | } else { | |
4503 | napi_synchronize(&pp->napi); | |
4504 | napi_disable(&pp->napi); | |
9a401dea GC |
4505 | } |
4506 | ||
4507 | pp->rxq_def = pp->indir[0]; | |
4508 | ||
4509 | /* Update unicast mapping */ | |
4510 | mvneta_set_rx_mode(pp->dev); | |
4511 | ||
4512 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
4513 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); | |
4514 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
4515 | ||
4516 | /* Update the elected CPU matching the new rxq_def */ | |
120cfa50 | 4517 | spin_lock(&pp->lock); |
9a401dea | 4518 | mvneta_percpu_elect(pp); |
120cfa50 | 4519 | spin_unlock(&pp->lock); |
9a401dea | 4520 | |
0f5c6c30 JZ |
4521 | if (!pp->neta_armada3700) { |
4522 | /* We have to synchronise on the napi of each CPU */ | |
4523 | for_each_online_cpu(cpu) { | |
4524 | struct mvneta_pcpu_port *pcpu_port = | |
4525 | per_cpu_ptr(pp->ports, cpu); | |
9a401dea | 4526 | |
0f5c6c30 JZ |
4527 | napi_enable(&pcpu_port->napi); |
4528 | } | |
4529 | } else { | |
4530 | napi_enable(&pp->napi); | |
9a401dea GC |
4531 | } |
4532 | ||
4533 | netif_tx_start_all_queues(pp->dev); | |
4534 | ||
4535 | return 0; | |
4536 | } | |
4537 | ||
4538 | static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, | |
4539 | const u8 *key, const u8 hfunc) | |
4540 | { | |
4541 | struct mvneta_port *pp = netdev_priv(dev); | |
2636ac3c MW |
4542 | |
4543 | /* Current code for Armada 3700 doesn't support RSS features yet */ | |
4544 | if (pp->neta_armada3700) | |
4545 | return -EOPNOTSUPP; | |
4546 | ||
9a401dea GC |
4547 | /* We require at least one supported parameter to be changed |
4548 | * and no change in any of the unsupported parameters | |
4549 | */ | |
4550 | if (key || | |
4551 | (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) | |
4552 | return -EOPNOTSUPP; | |
4553 | ||
4554 | if (!indir) | |
4555 | return 0; | |
4556 | ||
4557 | memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); | |
4558 | ||
4559 | return mvneta_config_rss(pp); | |
4560 | } | |
4561 | ||
4562 | static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, | |
4563 | u8 *hfunc) | |
4564 | { | |
4565 | struct mvneta_port *pp = netdev_priv(dev); | |
4566 | ||
2636ac3c MW |
4567 | /* Current code for Armada 3700 doesn't support RSS features yet */ |
4568 | if (pp->neta_armada3700) | |
4569 | return -EOPNOTSUPP; | |
4570 | ||
9a401dea GC |
4571 | if (hfunc) |
4572 | *hfunc = ETH_RSS_HASH_TOP; | |
4573 | ||
4574 | if (!indir) | |
4575 | return 0; | |
4576 | ||
4577 | memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); | |
4578 | ||
4579 | return 0; | |
4580 | } | |
4581 | ||
b60a00f9 JH |
4582 | static void mvneta_ethtool_get_wol(struct net_device *dev, |
4583 | struct ethtool_wolinfo *wol) | |
4584 | { | |
503f9aa9 | 4585 | struct mvneta_port *pp = netdev_priv(dev); |
b60a00f9 | 4586 | |
503f9aa9 | 4587 | phylink_ethtool_get_wol(pp->phylink, wol); |
b60a00f9 JH |
4588 | } |
4589 | ||
4590 | static int mvneta_ethtool_set_wol(struct net_device *dev, | |
4591 | struct ethtool_wolinfo *wol) | |
4592 | { | |
503f9aa9 | 4593 | struct mvneta_port *pp = netdev_priv(dev); |
82960fff JZ |
4594 | int ret; |
4595 | ||
503f9aa9 | 4596 | ret = phylink_ethtool_set_wol(pp->phylink, wol); |
82960fff JZ |
4597 | if (!ret) |
4598 | device_set_wakeup_enable(&dev->dev, !!wol->wolopts); | |
4599 | ||
4600 | return ret; | |
b60a00f9 JH |
4601 | } |
4602 | ||
6d81f451 RK |
4603 | static int mvneta_ethtool_get_eee(struct net_device *dev, |
4604 | struct ethtool_eee *eee) | |
4605 | { | |
4606 | struct mvneta_port *pp = netdev_priv(dev); | |
4607 | u32 lpi_ctl0; | |
4608 | ||
4609 | lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); | |
4610 | ||
4611 | eee->eee_enabled = pp->eee_enabled; | |
4612 | eee->eee_active = pp->eee_active; | |
4613 | eee->tx_lpi_enabled = pp->tx_lpi_enabled; | |
4614 | eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; | |
4615 | ||
4616 | return phylink_ethtool_get_eee(pp->phylink, eee); | |
4617 | } | |
4618 | ||
4619 | static int mvneta_ethtool_set_eee(struct net_device *dev, | |
4620 | struct ethtool_eee *eee) | |
4621 | { | |
4622 | struct mvneta_port *pp = netdev_priv(dev); | |
4623 | u32 lpi_ctl0; | |
4624 | ||
4625 | /* The Armada 37x documents do not give limits for this other than | |
4626 | * it being an 8-bit register. */ | |
e4a3e9ff | 4627 | if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) |
6d81f451 RK |
4628 | return -EINVAL; |
4629 | ||
4630 | lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); | |
4631 | lpi_ctl0 &= ~(0xff << 8); | |
4632 | lpi_ctl0 |= eee->tx_lpi_timer << 8; | |
4633 | mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); | |
4634 | ||
4635 | pp->eee_enabled = eee->eee_enabled; | |
4636 | pp->tx_lpi_enabled = eee->tx_lpi_enabled; | |
4637 | ||
4638 | mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); | |
4639 | ||
4640 | return phylink_ethtool_set_eee(pp->phylink, eee); | |
4641 | } | |
4642 | ||
c5aff182 TP |
4643 | static const struct net_device_ops mvneta_netdev_ops = { |
4644 | .ndo_open = mvneta_open, | |
4645 | .ndo_stop = mvneta_stop, | |
4646 | .ndo_start_xmit = mvneta_tx, | |
4647 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
4648 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
4649 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 4650 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 4651 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 4652 | .ndo_do_ioctl = mvneta_ioctl, |
0db51da7 | 4653 | .ndo_bpf = mvneta_xdp, |
b0a43db9 | 4654 | .ndo_xdp_xmit = mvneta_xdp_xmit, |
c5aff182 TP |
4655 | }; |
4656 | ||
4581be42 | 4657 | static const struct ethtool_ops mvneta_eth_tool_ops = { |
503f9aa9 | 4658 | .nway_reset = mvneta_ethtool_nway_reset, |
c5aff182 | 4659 | .get_link = ethtool_op_get_link, |
c5aff182 TP |
4660 | .set_coalesce = mvneta_ethtool_set_coalesce, |
4661 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
4662 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
4663 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
4664 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
4932a918 RK |
4665 | .get_pauseparam = mvneta_ethtool_get_pauseparam, |
4666 | .set_pauseparam = mvneta_ethtool_set_pauseparam, | |
9b0cdefa RK |
4667 | .get_strings = mvneta_ethtool_get_strings, |
4668 | .get_ethtool_stats = mvneta_ethtool_get_stats, | |
4669 | .get_sset_count = mvneta_ethtool_get_sset_count, | |
9a401dea GC |
4670 | .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, |
4671 | .get_rxnfc = mvneta_ethtool_get_rxnfc, | |
4672 | .get_rxfh = mvneta_ethtool_get_rxfh, | |
4673 | .set_rxfh = mvneta_ethtool_set_rxfh, | |
503f9aa9 | 4674 | .get_link_ksettings = mvneta_ethtool_get_link_ksettings, |
013ad40d | 4675 | .set_link_ksettings = mvneta_ethtool_set_link_ksettings, |
b60a00f9 JH |
4676 | .get_wol = mvneta_ethtool_get_wol, |
4677 | .set_wol = mvneta_ethtool_set_wol, | |
6d81f451 RK |
4678 | .get_eee = mvneta_ethtool_get_eee, |
4679 | .set_eee = mvneta_ethtool_set_eee, | |
c5aff182 TP |
4680 | }; |
4681 | ||
4682 | /* Initialize hw */ | |
9672850b | 4683 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
4684 | { |
4685 | int queue; | |
4686 | ||
4687 | /* Disable port */ | |
4688 | mvneta_port_disable(pp); | |
4689 | ||
4690 | /* Set port default values */ | |
4691 | mvneta_defaults_set(pp); | |
4692 | ||
5d6312ed | 4693 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); |
c5aff182 TP |
4694 | if (!pp->txqs) |
4695 | return -ENOMEM; | |
4696 | ||
4697 | /* Initialize TX descriptor rings */ | |
4698 | for (queue = 0; queue < txq_number; queue++) { | |
4699 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
4700 | txq->id = queue; | |
4701 | txq->size = pp->tx_ring_size; | |
4702 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
4703 | } | |
4704 | ||
5d6312ed | 4705 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); |
9672850b | 4706 | if (!pp->rxqs) |
c5aff182 | 4707 | return -ENOMEM; |
c5aff182 TP |
4708 | |
4709 | /* Create Rx descriptor rings */ | |
4710 | for (queue = 0; queue < rxq_number; queue++) { | |
4711 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
4712 | rxq->id = queue; | |
4713 | rxq->size = pp->rx_ring_size; | |
4714 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
4715 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
29110630 ME |
4716 | rxq->buf_virt_addr |
4717 | = devm_kmalloc_array(pp->dev->dev.parent, | |
4718 | rxq->size, | |
4719 | sizeof(*rxq->buf_virt_addr), | |
4720 | GFP_KERNEL); | |
f88bee1c GC |
4721 | if (!rxq->buf_virt_addr) |
4722 | return -ENOMEM; | |
c5aff182 TP |
4723 | } |
4724 | ||
4725 | return 0; | |
4726 | } | |
4727 | ||
c5aff182 | 4728 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
4729 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
4730 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
4731 | { |
4732 | u32 win_enable; | |
4733 | u32 win_protect; | |
4734 | int i; | |
4735 | ||
4736 | for (i = 0; i < 6; i++) { | |
4737 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
4738 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
4739 | ||
4740 | if (i < 4) | |
4741 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
4742 | } | |
4743 | ||
4744 | win_enable = 0x3f; | |
4745 | win_protect = 0; | |
4746 | ||
2636ac3c MW |
4747 | if (dram) { |
4748 | for (i = 0; i < dram->num_cs; i++) { | |
4749 | const struct mbus_dram_window *cs = dram->cs + i; | |
4750 | ||
4751 | mvreg_write(pp, MVNETA_WIN_BASE(i), | |
4752 | (cs->base & 0xffff0000) | | |
4753 | (cs->mbus_attr << 8) | | |
4754 | dram->mbus_dram_target_id); | |
c5aff182 | 4755 | |
2636ac3c MW |
4756 | mvreg_write(pp, MVNETA_WIN_SIZE(i), |
4757 | (cs->size - 1) & 0xffff0000); | |
c5aff182 | 4758 | |
2636ac3c MW |
4759 | win_enable &= ~(1 << i); |
4760 | win_protect |= 3 << (2 * i); | |
4761 | } | |
4762 | } else { | |
4763 | /* For Armada3700 open default 4GB Mbus window, leaving | |
4764 | * arbitration of target/attribute to a different layer | |
4765 | * of configuration. | |
4766 | */ | |
4767 | mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); | |
4768 | win_enable &= ~BIT(0); | |
4769 | win_protect = 3; | |
c5aff182 TP |
4770 | } |
4771 | ||
4772 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
db6ba9a5 | 4773 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
c5aff182 TP |
4774 | } |
4775 | ||
4776 | /* Power up the port */ | |
3f1dd4bc | 4777 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 4778 | { |
c5aff182 TP |
4779 | /* MAC Cause register should be cleared */ |
4780 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
4781 | ||
32699954 | 4782 | if (phy_mode == PHY_INTERFACE_MODE_QSGMII) |
3f1dd4bc | 4783 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); |
22f4bf8a | 4784 | else if (phy_mode == PHY_INTERFACE_MODE_SGMII || |
a10c1c81 | 4785 | phy_interface_mode_is_8023z(phy_mode)) |
3f1dd4bc | 4786 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); |
32699954 | 4787 | else if (!phy_interface_mode_is_rgmii(phy_mode)) |
3f1dd4bc | 4788 | return -EINVAL; |
3f1dd4bc TP |
4789 | |
4790 | return 0; | |
c5aff182 TP |
4791 | } |
4792 | ||
4793 | /* Device initialization routine */ | |
03ce758e | 4794 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 | 4795 | { |
c5aff182 | 4796 | struct device_node *dn = pdev->dev.of_node; |
dc35a10f | 4797 | struct device_node *bm_node; |
c5aff182 TP |
4798 | struct mvneta_port *pp; |
4799 | struct net_device *dev; | |
503f9aa9 | 4800 | struct phylink *phylink; |
a10c1c81 | 4801 | struct phy *comphy; |
8cc3e439 TP |
4802 | const char *dt_mac_addr; |
4803 | char hw_mac_addr[ETH_ALEN]; | |
0c65b2b9 | 4804 | phy_interface_t phy_mode; |
8cc3e439 | 4805 | const char *mac_from; |
9110ee07 | 4806 | int tx_csum_limit; |
c5aff182 | 4807 | int err; |
12bb03b4 | 4808 | int cpu; |
c5aff182 | 4809 | |
a3ddd94f RP |
4810 | dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), |
4811 | txq_number, rxq_number); | |
c5aff182 TP |
4812 | if (!dev) |
4813 | return -ENOMEM; | |
4814 | ||
4815 | dev->irq = irq_of_parse_and_map(dn, 0); | |
a3ddd94f RP |
4816 | if (dev->irq == 0) |
4817 | return -EINVAL; | |
c5aff182 | 4818 | |
0c65b2b9 AL |
4819 | err = of_get_phy_mode(dn, &phy_mode); |
4820 | if (err) { | |
c5aff182 | 4821 | dev_err(&pdev->dev, "incorrect phy-mode\n"); |
503f9aa9 RK |
4822 | goto err_free_irq; |
4823 | } | |
4824 | ||
a10c1c81 RK |
4825 | comphy = devm_of_phy_get(&pdev->dev, dn, NULL); |
4826 | if (comphy == ERR_PTR(-EPROBE_DEFER)) { | |
4827 | err = -EPROBE_DEFER; | |
4828 | goto err_free_irq; | |
4829 | } else if (IS_ERR(comphy)) { | |
4830 | comphy = NULL; | |
4831 | } | |
4832 | ||
44cc27e4 IC |
4833 | pp = netdev_priv(dev); |
4834 | spin_lock_init(&pp->lock); | |
4835 | ||
4836 | pp->phylink_config.dev = &dev->dev; | |
4837 | pp->phylink_config.type = PHYLINK_NETDEV; | |
4838 | ||
4839 | phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, | |
4840 | phy_mode, &mvneta_phylink_ops); | |
503f9aa9 RK |
4841 | if (IS_ERR(phylink)) { |
4842 | err = PTR_ERR(phylink); | |
4843 | goto err_free_irq; | |
c5aff182 TP |
4844 | } |
4845 | ||
c5aff182 TP |
4846 | dev->tx_queue_len = MVNETA_MAX_TXD; |
4847 | dev->watchdog_timeo = 5 * HZ; | |
4848 | dev->netdev_ops = &mvneta_netdev_ops; | |
4849 | ||
7ad24ea4 | 4850 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 | 4851 | |
503f9aa9 | 4852 | pp->phylink = phylink; |
a10c1c81 | 4853 | pp->comphy = comphy; |
c5aff182 | 4854 | pp->phy_interface = phy_mode; |
503f9aa9 | 4855 | pp->dn = dn; |
c5aff182 | 4856 | |
90b74c01 | 4857 | pp->rxq_def = rxq_def; |
9a401dea GC |
4858 | pp->indir[0] = rxq_def; |
4859 | ||
2636ac3c MW |
4860 | /* Get special SoC configurations */ |
4861 | if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) | |
4862 | pp->neta_armada3700 = true; | |
4863 | ||
2804ba4e JZ |
4864 | pp->clk = devm_clk_get(&pdev->dev, "core"); |
4865 | if (IS_ERR(pp->clk)) | |
4866 | pp->clk = devm_clk_get(&pdev->dev, NULL); | |
189dd626 TP |
4867 | if (IS_ERR(pp->clk)) { |
4868 | err = PTR_ERR(pp->clk); | |
503f9aa9 | 4869 | goto err_free_phylink; |
189dd626 TP |
4870 | } |
4871 | ||
4872 | clk_prepare_enable(pp->clk); | |
4873 | ||
15cc4a4a JZ |
4874 | pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); |
4875 | if (!IS_ERR(pp->clk_bus)) | |
4876 | clk_prepare_enable(pp->clk_bus); | |
4877 | ||
00c33afb | 4878 | pp->base = devm_platform_ioremap_resource(pdev, 0); |
c3f0dd38 TP |
4879 | if (IS_ERR(pp->base)) { |
4880 | err = PTR_ERR(pp->base); | |
5445eaf3 APR |
4881 | goto err_clk; |
4882 | } | |
4883 | ||
12bb03b4 MR |
4884 | /* Alloc per-cpu port structure */ |
4885 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
4886 | if (!pp->ports) { | |
4887 | err = -ENOMEM; | |
4888 | goto err_clk; | |
4889 | } | |
4890 | ||
74c41b04 | 4891 | /* Alloc per-cpu stats */ |
1c213bd2 | 4892 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 4893 | if (!pp->stats) { |
4894 | err = -ENOMEM; | |
12bb03b4 | 4895 | goto err_free_ports; |
74c41b04 | 4896 | } |
4897 | ||
8cc3e439 | 4898 | dt_mac_addr = of_get_mac_address(dn); |
a51645f7 | 4899 | if (!IS_ERR(dt_mac_addr)) { |
8cc3e439 | 4900 | mac_from = "device tree"; |
2d2924af | 4901 | ether_addr_copy(dev->dev_addr, dt_mac_addr); |
8cc3e439 TP |
4902 | } else { |
4903 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
4904 | if (is_valid_ether_addr(hw_mac_addr)) { | |
4905 | mac_from = "hardware"; | |
4906 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
4907 | } else { | |
4908 | mac_from = "random"; | |
4909 | eth_hw_addr_random(dev); | |
4910 | } | |
4911 | } | |
4912 | ||
9110ee07 MW |
4913 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
4914 | if (tx_csum_limit < 0 || | |
4915 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { | |
4916 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4917 | dev_info(&pdev->dev, | |
4918 | "Wrong TX csum limit in DT, set to %dB\n", | |
4919 | MVNETA_TX_CSUM_DEF_SIZE); | |
4920 | } | |
4921 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { | |
4922 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4923 | } else { | |
4924 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; | |
4925 | } | |
4926 | ||
4927 | pp->tx_csum_limit = tx_csum_limit; | |
b65657fc | 4928 | |
9768b45c | 4929 | pp->dram_target_info = mv_mbus_dram_info(); |
2636ac3c MW |
4930 | /* Armada3700 requires setting default configuration of Mbus |
4931 | * windows, however without using filled mbus_dram_target_info | |
4932 | * structure. | |
4933 | */ | |
9768b45c JL |
4934 | if (pp->dram_target_info || pp->neta_armada3700) |
4935 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
dc35a10f | 4936 | |
c5aff182 TP |
4937 | pp->tx_ring_size = MVNETA_MAX_TXD; |
4938 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
4939 | ||
4940 | pp->dev = dev; | |
4941 | SET_NETDEV_DEV(dev, &pdev->dev); | |
4942 | ||
dc35a10f | 4943 | pp->id = global_port_id++; |
0db51da7 | 4944 | pp->rx_offset_correction = MVNETA_SKB_HEADROOM; |
dc35a10f MW |
4945 | |
4946 | /* Obtain access to BM resources if enabled and already initialized */ | |
4947 | bm_node = of_parse_phandle(dn, "buffer-manager", 0); | |
965cbbec GC |
4948 | if (bm_node) { |
4949 | pp->bm_priv = mvneta_bm_get(bm_node); | |
4950 | if (pp->bm_priv) { | |
4951 | err = mvneta_bm_port_init(pdev, pp); | |
4952 | if (err < 0) { | |
4953 | dev_info(&pdev->dev, | |
4954 | "use SW buffer management\n"); | |
4955 | mvneta_bm_put(pp->bm_priv); | |
4956 | pp->bm_priv = NULL; | |
4957 | } | |
dc35a10f | 4958 | } |
562e2f46 YK |
4959 | /* Set RX packet offset correction for platforms, whose |
4960 | * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit | |
4961 | * platforms and 0B for 32-bit ones. | |
4962 | */ | |
4963 | pp->rx_offset_correction = max(0, | |
4964 | NET_SKB_PAD - | |
4965 | MVNETA_RX_PKT_OFFSET_CORRECTION); | |
dc35a10f | 4966 | } |
d4e4da00 | 4967 | of_node_put(bm_node); |
dc35a10f | 4968 | |
9672850b EG |
4969 | err = mvneta_init(&pdev->dev, pp); |
4970 | if (err < 0) | |
dc35a10f | 4971 | goto err_netdev; |
3f1dd4bc TP |
4972 | |
4973 | err = mvneta_port_power_up(pp, phy_mode); | |
4974 | if (err < 0) { | |
4975 | dev_err(&pdev->dev, "can't power up port\n"); | |
dc35a10f | 4976 | goto err_netdev; |
3f1dd4bc | 4977 | } |
c5aff182 | 4978 | |
2636ac3c MW |
4979 | /* Armada3700 network controller does not support per-cpu |
4980 | * operation, so only single NAPI should be initialized. | |
4981 | */ | |
4982 | if (pp->neta_armada3700) { | |
4983 | netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
4984 | } else { | |
4985 | for_each_present_cpu(cpu) { | |
4986 | struct mvneta_pcpu_port *port = | |
4987 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 4988 | |
2636ac3c MW |
4989 | netif_napi_add(dev, &port->napi, mvneta_poll, |
4990 | NAPI_POLL_WEIGHT); | |
4991 | port->pp = pp; | |
4992 | } | |
12bb03b4 | 4993 | } |
c5aff182 | 4994 | |
7772988a JZ |
4995 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
4996 | NETIF_F_TSO | NETIF_F_RXCSUM; | |
01ef26ca EG |
4997 | dev->hw_features |= dev->features; |
4998 | dev->vlan_features |= dev->features; | |
97db8afa | 4999 | dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
8eef5f97 | 5000 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 5001 | |
5777987e JW |
5002 | /* MTU range: 68 - 9676 */ |
5003 | dev->min_mtu = ETH_MIN_MTU; | |
5004 | /* 9676 == 9700 - 20 and rounding to 8 */ | |
5005 | dev->max_mtu = 9676; | |
5006 | ||
c5aff182 TP |
5007 | err = register_netdev(dev); |
5008 | if (err < 0) { | |
5009 | dev_err(&pdev->dev, "failed to register\n"); | |
d484e06e | 5010 | goto err_netdev; |
c5aff182 TP |
5011 | } |
5012 | ||
8cc3e439 TP |
5013 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
5014 | dev->dev_addr); | |
c5aff182 TP |
5015 | |
5016 | platform_set_drvdata(pdev, pp->dev); | |
5017 | ||
5018 | return 0; | |
5019 | ||
dc35a10f | 5020 | err_netdev: |
dc35a10f MW |
5021 | if (pp->bm_priv) { |
5022 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
5023 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
5024 | 1 << pp->id); | |
965cbbec | 5025 | mvneta_bm_put(pp->bm_priv); |
dc35a10f | 5026 | } |
74c41b04 | 5027 | free_percpu(pp->stats); |
12bb03b4 MR |
5028 | err_free_ports: |
5029 | free_percpu(pp->ports); | |
5445eaf3 | 5030 | err_clk: |
15cc4a4a | 5031 | clk_disable_unprepare(pp->clk_bus); |
5445eaf3 | 5032 | clk_disable_unprepare(pp->clk); |
503f9aa9 RK |
5033 | err_free_phylink: |
5034 | if (pp->phylink) | |
5035 | phylink_destroy(pp->phylink); | |
c5aff182 TP |
5036 | err_free_irq: |
5037 | irq_dispose_mapping(dev->irq); | |
c5aff182 TP |
5038 | return err; |
5039 | } | |
5040 | ||
5041 | /* Device removal routine */ | |
03ce758e | 5042 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
5043 | { |
5044 | struct net_device *dev = platform_get_drvdata(pdev); | |
5045 | struct mvneta_port *pp = netdev_priv(dev); | |
5046 | ||
5047 | unregister_netdev(dev); | |
15cc4a4a | 5048 | clk_disable_unprepare(pp->clk_bus); |
189dd626 | 5049 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 5050 | free_percpu(pp->ports); |
74c41b04 | 5051 | free_percpu(pp->stats); |
c5aff182 | 5052 | irq_dispose_mapping(dev->irq); |
503f9aa9 | 5053 | phylink_destroy(pp->phylink); |
c5aff182 | 5054 | |
dc35a10f MW |
5055 | if (pp->bm_priv) { |
5056 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
5057 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
5058 | 1 << pp->id); | |
965cbbec | 5059 | mvneta_bm_put(pp->bm_priv); |
dc35a10f MW |
5060 | } |
5061 | ||
c5aff182 TP |
5062 | return 0; |
5063 | } | |
5064 | ||
9768b45c JL |
5065 | #ifdef CONFIG_PM_SLEEP |
5066 | static int mvneta_suspend(struct device *device) | |
5067 | { | |
1799cdd2 | 5068 | int queue; |
9768b45c JL |
5069 | struct net_device *dev = dev_get_drvdata(device); |
5070 | struct mvneta_port *pp = netdev_priv(dev); | |
5071 | ||
1799cdd2 JZ |
5072 | if (!netif_running(dev)) |
5073 | goto clean_exit; | |
5074 | ||
5075 | if (!pp->neta_armada3700) { | |
5076 | spin_lock(&pp->lock); | |
5077 | pp->is_stopped = true; | |
5078 | spin_unlock(&pp->lock); | |
5079 | ||
5080 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
5081 | &pp->node_online); | |
5082 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
5083 | &pp->node_dead); | |
5084 | } | |
5085 | ||
3b8bc674 | 5086 | rtnl_lock(); |
1799cdd2 | 5087 | mvneta_stop_dev(pp); |
3b8bc674 | 5088 | rtnl_unlock(); |
1799cdd2 JZ |
5089 | |
5090 | for (queue = 0; queue < rxq_number; queue++) { | |
5091 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
5092 | ||
5093 | mvneta_rxq_drop_pkts(pp, rxq); | |
5094 | } | |
5095 | ||
5096 | for (queue = 0; queue < txq_number; queue++) { | |
5097 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
5098 | ||
5099 | mvneta_txq_hw_deinit(pp, txq); | |
5100 | } | |
5101 | ||
5102 | clean_exit: | |
9768b45c JL |
5103 | netif_device_detach(dev); |
5104 | clk_disable_unprepare(pp->clk_bus); | |
5105 | clk_disable_unprepare(pp->clk); | |
1799cdd2 | 5106 | |
9768b45c JL |
5107 | return 0; |
5108 | } | |
5109 | ||
5110 | static int mvneta_resume(struct device *device) | |
5111 | { | |
5112 | struct platform_device *pdev = to_platform_device(device); | |
5113 | struct net_device *dev = dev_get_drvdata(device); | |
5114 | struct mvneta_port *pp = netdev_priv(dev); | |
1799cdd2 | 5115 | int err, queue; |
9768b45c JL |
5116 | |
5117 | clk_prepare_enable(pp->clk); | |
5118 | if (!IS_ERR(pp->clk_bus)) | |
5119 | clk_prepare_enable(pp->clk_bus); | |
5120 | if (pp->dram_target_info || pp->neta_armada3700) | |
5121 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
5122 | if (pp->bm_priv) { | |
5123 | err = mvneta_bm_port_init(pdev, pp); | |
5124 | if (err < 0) { | |
5125 | dev_info(&pdev->dev, "use SW buffer management\n"); | |
5126 | pp->bm_priv = NULL; | |
5127 | } | |
5128 | } | |
5129 | mvneta_defaults_set(pp); | |
5130 | err = mvneta_port_power_up(pp, pp->phy_interface); | |
5131 | if (err < 0) { | |
5132 | dev_err(device, "can't power up port\n"); | |
5133 | return err; | |
5134 | } | |
5135 | ||
9768b45c | 5136 | netif_device_attach(dev); |
1799cdd2 JZ |
5137 | |
5138 | if (!netif_running(dev)) | |
5139 | return 0; | |
5140 | ||
5141 | for (queue = 0; queue < rxq_number; queue++) { | |
5142 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
5143 | ||
5144 | rxq->next_desc_to_proc = 0; | |
5145 | mvneta_rxq_hw_init(pp, rxq); | |
5146 | } | |
5147 | ||
5148 | for (queue = 0; queue < txq_number; queue++) { | |
5149 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
5150 | ||
5151 | txq->next_desc_to_proc = 0; | |
5152 | mvneta_txq_hw_init(pp, txq); | |
d6956ac8 | 5153 | } |
1799cdd2 JZ |
5154 | |
5155 | if (!pp->neta_armada3700) { | |
5156 | spin_lock(&pp->lock); | |
5157 | pp->is_stopped = false; | |
5158 | spin_unlock(&pp->lock); | |
5159 | cpuhp_state_add_instance_nocalls(online_hpstate, | |
5160 | &pp->node_online); | |
5161 | cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
5162 | &pp->node_dead); | |
5163 | } | |
5164 | ||
5165 | rtnl_lock(); | |
5166 | mvneta_start_dev(pp); | |
3b8bc674 | 5167 | rtnl_unlock(); |
1799cdd2 | 5168 | mvneta_set_rx_mode(dev); |
d6956ac8 | 5169 | |
9768b45c JL |
5170 | return 0; |
5171 | } | |
5172 | #endif | |
5173 | ||
5174 | static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); | |
5175 | ||
c5aff182 TP |
5176 | static const struct of_device_id mvneta_match[] = { |
5177 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 5178 | { .compatible = "marvell,armada-xp-neta" }, |
2636ac3c | 5179 | { .compatible = "marvell,armada-3700-neta" }, |
c5aff182 TP |
5180 | { } |
5181 | }; | |
5182 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
5183 | ||
5184 | static struct platform_driver mvneta_driver = { | |
5185 | .probe = mvneta_probe, | |
03ce758e | 5186 | .remove = mvneta_remove, |
c5aff182 TP |
5187 | .driver = { |
5188 | .name = MVNETA_DRIVER_NAME, | |
5189 | .of_match_table = mvneta_match, | |
9768b45c | 5190 | .pm = &mvneta_pm_ops, |
c5aff182 TP |
5191 | }, |
5192 | }; | |
5193 | ||
84a3f4db SAS |
5194 | static int __init mvneta_driver_init(void) |
5195 | { | |
5196 | int ret; | |
5197 | ||
5198 | ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", | |
5199 | mvneta_cpu_online, | |
5200 | mvneta_cpu_down_prepare); | |
5201 | if (ret < 0) | |
5202 | goto out; | |
5203 | online_hpstate = ret; | |
5204 | ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", | |
5205 | NULL, mvneta_cpu_dead); | |
5206 | if (ret) | |
5207 | goto err_dead; | |
5208 | ||
5209 | ret = platform_driver_register(&mvneta_driver); | |
5210 | if (ret) | |
5211 | goto err; | |
5212 | return 0; | |
5213 | ||
5214 | err: | |
5215 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
5216 | err_dead: | |
5217 | cpuhp_remove_multi_state(online_hpstate); | |
5218 | out: | |
5219 | return ret; | |
5220 | } | |
5221 | module_init(mvneta_driver_init); | |
5222 | ||
5223 | static void __exit mvneta_driver_exit(void) | |
5224 | { | |
5225 | platform_driver_unregister(&mvneta_driver); | |
5226 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
5227 | cpuhp_remove_multi_state(online_hpstate); | |
5228 | } | |
5229 | module_exit(mvneta_driver_exit); | |
c5aff182 TP |
5230 | |
5231 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
5232 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
5233 | MODULE_LICENSE("GPL"); | |
5234 | ||
d3757ba4 JP |
5235 | module_param(rxq_number, int, 0444); |
5236 | module_param(txq_number, int, 0444); | |
c5aff182 | 5237 | |
d3757ba4 JP |
5238 | module_param(rxq_def, int, 0444); |
5239 | module_param(rx_copybreak, int, 0644); |