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ixgbe: Let the Rx buffer allocation clear status bits instead of cleanup
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
8ef78adc
PWJ		 134static unsigned int allow_unsupported_sfp;
135module_param(allow_unsupported_sfp, uint, 0);
136MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
7086400d
AD		 146static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
147{
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
151}
152
153static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
154{
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
156
52f33af8 157 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
160}
161
dcd79aeb
TI		 162struct ixgbe_reg_info {
163 u32 ofs;
164 char *name;
165};
166
167static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
168
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
173
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
176
177 /* RX Registers */
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
186
187 /* TX Registers */
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
194
195 /* List Terminator */
196 {}
197};
198
199
200/*
201 * ixgbe_regdump - register printout routine
202 */
203static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
204{
205 int i = 0, j = 0;
206 char rname[16];
207 u32 regs[64];
208
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
213 break;
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
217 break;
218 case IXGBE_RDLEN(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
221 break;
222 case IXGBE_RDH(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
225 break;
226 case IXGBE_RDT(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
229 break;
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
233 break;
234 case IXGBE_RDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
237 break;
238 case IXGBE_RDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
241 break;
242 case IXGBE_TDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
245 break;
246 case IXGBE_TDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
249 break;
250 case IXGBE_TDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
253 break;
254 case IXGBE_TDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
257 break;
258 case IXGBE_TDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
261 break;
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
265 break;
266 default:
c7689578 267 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 268 IXGBE_READ_REG(hw, reginfo->ofs));
269 return;
270 }
271
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 274 pr_err("%-15s", rname);
dcd79aeb 275 for (j = 0; j < 8; j++)
c7689578
JP		 276 pr_cont(" %08x", regs[i*8+j]);
277 pr_cont("\n");
dcd79aeb
TI		 278 }
279
280}
281
282/*
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
284 */
285static void ixgbe_dump(struct ixgbe_adapter *adapter)
286{
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
290 int n = 0;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
298 u32 staterr;
299 int i = 0;
300
301 if (!netif_msg_hw(adapter))
302 return;
303
304 /* Print netdevice Info */
305 if (netdev) {
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 307 pr_info("Device Name state "
dcd79aeb 308 "trans_start last_rx\n");
c7689578
JP		 309 pr_info("%-15s %016lX %016lX %016lX\n",
310 netdev->name,
311 netdev->state,
312 netdev->trans_start,
313 netdev->last_rx);
dcd79aeb
TI		 314 }
315
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 318 pr_info(" Register Name Value\n");
dcd79aeb
TI		 319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
322 }
323
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
326 goto exit;
327
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
332 tx_buffer_info =
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
340 }
341
342 /* Print TX Rings */
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
347
348 /* Transmit Descriptor Formats
349 *
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
357 */
358
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
c7689578
JP		 361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
367
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 369 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
c7689578 372 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 373 " %04X %p %016llX %p", i,
dcd79aeb
TI		 374 le64_to_cpu(u0->a),
375 le64_to_cpu(u0->b),
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
c7689578 383 pr_cont(" NTC/U\n");
dcd79aeb 384 else if (i == tx_ring->next_to_use)
c7689578 385 pr_cont(" NTU\n");
dcd79aeb 386 else if (i == tx_ring->next_to_clean)
c7689578 387 pr_cont(" NTC\n");
dcd79aeb 388 else
c7689578 389 pr_cont("\n");
dcd79aeb
TI		 390
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
397 }
398 }
399
400 /* Print RX Rings Summary */
401rx_ring_summary:
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 403 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
c7689578
JP		 406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 408 }
409
410 /* Print RX Rings */
411 if (!netif_msg_rx_status(adapter))
412 goto exit;
413
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
415
416 /* Advanced Receive Descriptor (Read) Format
417 * 63 1 0
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
423 *
424 *
425 * Advanced Receive Descriptor (Write-Back) Format
426 *
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
c7689578 444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
447
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 450 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
c7689578 455 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 456 "%016llX ---------------- %p", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 rx_buffer_info->skb);
460 } else {
c7689578 461 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 462 "%016llX %016llX %p", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
467
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
472 rx_ring->rx_buf_len, true);
473
474 if (rx_ring->rx_buf_len
919e78a6 475 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 476 print_hex_dump(KERN_INFO, "",
477 DUMP_PREFIX_ADDRESS, 16, 1,
478 phys_to_virt(
479 rx_buffer_info->page_dma +
480 rx_buffer_info->page_offset
481 ),
482 PAGE_SIZE/2, true);
483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
e8e26350
PW		 520/*
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
d3d00239
AD		 592static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
d3d00239
AD		 595 if (tx_buffer->dma) {
596 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
597 dma_unmap_page(ring->dev,
598 tx_buffer->dma,
599 tx_buffer->length,
600 DMA_TO_DEVICE);
e5a43549 601 else
d3d00239
AD		 602 dma_unmap_single(ring->dev,
603 tx_buffer->dma,
604 tx_buffer->length,
605 DMA_TO_DEVICE);
e5a43549 606 }
d3d00239
AD		 607 tx_buffer->dma = 0;
608}
609
610void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
611 struct ixgbe_tx_buffer *tx_buffer_info)
612{
613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
614 if (tx_buffer_info->skb)
9a799d71 615 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 616 tx_buffer_info->skb = NULL;
9a799d71
AK		 617 /* tx_buffer_info must be completely set up in the transmit path */
618}
619
c84d324c
JF		 620static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
621{
622 struct ixgbe_hw *hw = &adapter->hw;
623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
624 u32 data = 0;
625 u32 xoff[8] = {0};
626 int i;
627
628 if ((hw->fc.current_mode == ixgbe_fc_full) ||
629 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
630 switch (hw->mac.type) {
631 case ixgbe_mac_82598EB:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 633 break;
634 default:
c84d324c
JF		 635 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
636 }
637 hwstats->lxoffrxc += data;
638
639 /* refill credits (no tx hang) if we received xoff */
640 if (!data)
641 return;
642
643 for (i = 0; i < adapter->num_tx_queues; i++)
644 clear_bit(__IXGBE_HANG_CHECK_ARMED,
645 &adapter->tx_ring[i]->state);
646 return;
647 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
648 return;
649
650 /* update stats for each tc, only valid with PFC enabled */
651 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
652 switch (hw->mac.type) {
653 case ixgbe_mac_82598EB:
654 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 655 break;
c84d324c
JF		 656 default:
657 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 658 }
c84d324c
JF		 659 hwstats->pxoffrxc[i] += xoff[i];
660 }
661
662 /* disarm tx queues that have received xoff frames */
663 for (i = 0; i < adapter->num_tx_queues; i++) {
664 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 665 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 666
667 if (xoff[tc])
668 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 669 }
26f23d82
YZ		 670}
671
c84d324c 672static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 673{
c84d324c
JF		 674 return ring->tx_stats.completed;
675}
676
677static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
678{
679 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 680 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 681
c84d324c
JF		 682 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
683 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
684
685 if (head != tail)
686 return (head < tail) ?
687 tail - head : (tail + ring->count - head);
688
689 return 0;
690}
691
692static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
693{
694 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
695 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
696 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
697 bool ret = false;
698
7d637bcc 699 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 700
701 /*
702 * Check for a hung queue, but be thorough. This verifies
703 * that a transmit has been completed since the previous
704 * check AND there is at least one packet pending. The
705 * ARMED bit is set to indicate a potential hang. The
706 * bit is cleared if a pause frame is received to remove
707 * false hang detection due to PFC or 802.3x frames. By
708 * requiring this to fail twice we avoid races with
709 * pfc clearing the ARMED bit and conditions where we
710 * run the check_tx_hang logic with a transmit completion
711 * pending but without time to complete it yet.
712 */
713 if ((tx_done_old == tx_done) && tx_pending) {
714 /* make sure it is true for two checks in a row */
715 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
716 &tx_ring->state);
717 } else {
718 /* update completed stats and continue */
719 tx_ring->tx_stats.tx_done_old = tx_done;
720 /* reset the countdown */
721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 722 }
723
c84d324c 724 return ret;
9a799d71
AK		 725}
726
c83c6cbd
AD		 727/**
728 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
729 * @adapter: driver private struct
730 **/
731static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
732{
733
734 /* Do the reset outside of interrupt context */
735 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
736 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
737 ixgbe_service_event_schedule(adapter);
738 }
739}
e01c31a5 740
9a799d71
AK		 741/**
742 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 743 * @q_vector: structure containing interrupt and ring information
e01c31a5 744 * @tx_ring: tx ring to clean
9a799d71 745 **/
fe49f04a 746static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 747 struct ixgbe_ring *tx_ring)
9a799d71 748{
fe49f04a 749 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 750 struct ixgbe_tx_buffer *tx_buffer;
751 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 752 unsigned int total_bytes = 0, total_packets = 0;
59224555 753 unsigned int budget = q_vector->tx.work_limit;
d3d00239 754 u16 i = tx_ring->next_to_clean;
9a799d71 755
d3d00239
AD		 756 tx_buffer = &tx_ring->tx_buffer_info[i];
757 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 758
30065e63 759 for (; budget; budget--) {
d3d00239
AD		 760 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
761
762 /* if next_to_watch is not set then there is no work pending */
763 if (!eop_desc)
764 break;
765
766 /* if DD is not set pending work has not been completed */
767 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
768 break;
8ad494b0 769
d3d00239
AD		 770 /* count the packet as being completed */
771 tx_ring->tx_stats.completed++;
772
773 /* clear next_to_watch to prevent false hangs */
774 tx_buffer->next_to_watch = NULL;
8ad494b0 775
d3d00239
AD		 776 /* prevent any other reads prior to eop_desc being verified */
777 rmb();
778
779 do {
780 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 781 tx_desc->wb.status = 0;
d3d00239
AD		 782 if (likely(tx_desc == eop_desc)) {
783 eop_desc = NULL;
784 dev_kfree_skb_any(tx_buffer->skb);
785 tx_buffer->skb = NULL;
786
787 total_bytes += tx_buffer->bytecount;
788 total_packets += tx_buffer->gso_segs;
789 }
9a799d71 790
d3d00239
AD		 791 tx_buffer++;
792 tx_desc++;
8ad494b0 793 i++;
d3d00239 794 if (unlikely(i == tx_ring->count)) {
8ad494b0 795 i = 0;
e01c31a5 796
d3d00239
AD		 797 tx_buffer = tx_ring->tx_buffer_info;
798 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 799 }
e01c31a5 800
d3d00239 801 } while (eop_desc);
12207e49
PWJ		 802 }
803
9a799d71 804 tx_ring->next_to_clean = i;
d3d00239 805 u64_stats_update_begin(&tx_ring->syncp);
b953799e 806 tx_ring->stats.bytes += total_bytes;
bd198058 807 tx_ring->stats.packets += total_packets;
d3d00239 808 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 809 q_vector->tx.total_bytes += total_bytes;
810 q_vector->tx.total_packets += total_packets;
b953799e 811
c84d324c
JF		 812 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
813 /* schedule immediate reset if we believe we hung */
814 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 815 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 816 e_err(drv, "Detected Tx Unit Hang\n"
817 " Tx Queue <%d>\n"
818 " TDH, TDT <%x>, <%x>\n"
819 " next_to_use <%x>\n"
820 " next_to_clean <%x>\n"
821 "tx_buffer_info[next_to_clean]\n"
822 " time_stamp <%lx>\n"
823 " jiffies <%lx>\n",
824 tx_ring->queue_index,
825 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
826 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 827 tx_ring->next_to_use, i,
828 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 829
830 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
831
832 e_info(probe,
833 "tx hang %d detected on queue %d, resetting adapter\n",
834 adapter->tx_timeout_count + 1, tx_ring->queue_index);
835
b953799e 836 /* schedule immediate reset if we believe we hung */
c83c6cbd 837 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 838
839 /* the adapter is about to reset, no point in enabling stuff */
59224555 840 return true;
b953799e 841 }
9a799d71 842
e092be60 843#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 844 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 845 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 846 /* Make sure that anybody stopping the queue after this
847 * sees the new next_to_clean.
848 */
849 smp_mb();
fc77dc3c 850 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 851 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 852 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 853 ++tx_ring->tx_stats.restart_queue;
30eba97a 854 }
e092be60 855 }
9a799d71 856
59224555 857 return !!budget;
9a799d71
AK		 858}
859
5dd2d332 860#ifdef CONFIG_IXGBE_DCA
bd0362dd 861static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 862 struct ixgbe_ring *rx_ring,
863 int cpu)
bd0362dd 864{
33cf09c9 865 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 866 u32 rxctrl;
33cf09c9
AD		 867 u8 reg_idx = rx_ring->reg_idx;
868
869 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
870 switch (hw->mac.type) {
871 case ixgbe_mac_82598EB:
872 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 873 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 874 break;
875 case ixgbe_mac_82599EB:
b93a2226 876 case ixgbe_mac_X540:
33cf09c9 877 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 878 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 879 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
880 break;
881 default:
882 break;
bd0362dd 883 }
33cf09c9
AD		 884 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
885 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
886 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 887 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 888}
889
890static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 891 struct ixgbe_ring *tx_ring,
892 int cpu)
bd0362dd 893{
33cf09c9 894 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 895 u32 txctrl;
33cf09c9
AD		 896 u8 reg_idx = tx_ring->reg_idx;
897
898 switch (hw->mac.type) {
899 case ixgbe_mac_82598EB:
900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
901 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 902 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
905 break;
906 case ixgbe_mac_82599EB:
b93a2226 907 case ixgbe_mac_X540:
33cf09c9
AD		 908 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
909 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 910 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 911 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
912 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 913 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
914 break;
915 default:
916 break;
917 }
918}
919
920static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
921{
922 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 923 struct ixgbe_ring *ring;
bd0362dd 924 int cpu = get_cpu();
bd0362dd 925
33cf09c9
AD		 926 if (q_vector->cpu == cpu)
927 goto out_no_update;
928
efe3d3c8
AD		 929 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
930 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 931
efe3d3c8
AD		 932 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
933 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 934
935 q_vector->cpu = cpu;
936out_no_update:
bd0362dd
JC		 937 put_cpu();
938}
939
940static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
941{
33cf09c9 942 int num_q_vectors;
bd0362dd
JC		 943 int i;
944
945 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
946 return;
947
e35ec126
AD		 948 /* always use CB2 mode, difference is masked in the CB driver */
949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
950
33cf09c9
AD		 951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
952 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
953 else
954 num_q_vectors = 1;
955
956 for (i = 0; i < num_q_vectors; i++) {
957 adapter->q_vector[i]->cpu = -1;
958 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 959 }
960}
961
962static int __ixgbe_notify_dca(struct device *dev, void *data)
963{
c60fbb00 964 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 965 unsigned long event = *(unsigned long *)data;
966
2a72c31e 967 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 968 return 0;
969
bd0362dd
JC		 970 switch (event) {
971 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 972 /* if we're already enabled, don't do it again */
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
974 break;
652f093f 975 if (dca_add_requester(dev) == 0) {
96b0e0f6 976 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 977 ixgbe_setup_dca(adapter);
978 break;
979 }
980 /* Fall Through since DCA is disabled. */
981 case DCA_PROVIDER_REMOVE:
982 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
983 dca_remove_requester(dev);
984 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
985 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
986 }
987 break;
988 }
989
652f093f 990 return 0;
bd0362dd 991}
5dd2d332 992#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 993
994static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
995 struct sk_buff *skb)
996{
997 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
998}
999
ff886dfc
AD		 1000/**
1001 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1002 * @adapter: address of board private structure
1003 * @rx_desc: advanced rx descriptor
1004 *
1005 * Returns : true if it is FCoE pkt
1006 */
1007static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1008 union ixgbe_adv_rx_desc *rx_desc)
1009{
1010 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1013 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1014 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1015 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1016}
1017
9a799d71
AK		 1018/**
1019 * ixgbe_receive_skb - Send a completed packet up the stack
1020 * @adapter: board private structure
1021 * @skb: packet to send up
177db6ff
MC		 1022 * @status: hardware indication of status of receive
1023 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1024 * @rx_desc: rx descriptor
9a799d71 1025 **/
78b6f4ce 1026static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1027 struct sk_buff *skb, u8 status,
1028 struct ixgbe_ring *ring,
1029 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1030{
78b6f4ce
HX		 1031 struct ixgbe_adapter *adapter = q_vector->adapter;
1032 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1033 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1034 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1035
f62bbb5e
JG		 1036 if (is_vlan && (tag & VLAN_VID_MASK))
1037 __vlan_hwaccel_put_tag(skb, tag);
1038
1039 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1040 napi_gro_receive(napi, skb);
1041 else
1042 netif_rx(skb);
9a799d71
AK		 1043}
1044
e59bd25d
AV		 1045/**
1046 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1047 * @adapter: address of board private structure
1048 * @status_err: hardware indication of status of receive
1049 * @skb: skb currently being received and modified
ff886dfc 1050 * @status_err: status error value of last descriptor in packet
e59bd25d 1051 **/
9a799d71 1052static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1053 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1054 struct sk_buff *skb,
1055 u32 status_err)
9a799d71 1056{
ff886dfc 1057 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1058
712744be
JB		 1059 /* Rx csum disabled */
1060 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1061 return;
e59bd25d
AV		 1062
1063 /* if IP and error */
1064 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1065 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1066 adapter->hw_csum_rx_error++;
1067 return;
1068 }
e59bd25d
AV		 1069
1070 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1071 return;
1072
1073 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1074 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1075
1076 /*
1077 * 82599 errata, UDP frames with a 0 checksum can be marked as
1078 * checksum errors.
1079 */
1080 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1081 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1082 return;
1083
e59bd25d
AV		 1084 adapter->hw_csum_rx_error++;
1085 return;
1086 }
1087
9a799d71 1088 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1089 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1090}
1091
84ea2591 1092static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1093{
1094 /*
1095 * Force memory writes to complete before letting h/w
1096 * know there are new descriptors to fetch. (Only
1097 * applicable for weak-ordered memory model archs,
1098 * such as IA-64).
1099 */
1100 wmb();
84ea2591 1101 writel(val, rx_ring->tail);
e8e26350
PW		 1102}
1103
f990b79b
AD		 1104static bool ixgbe_alloc_mapped_skb(struct ixgbe_ring *rx_ring,
1105 struct ixgbe_rx_buffer *bi)
1106{
1107 struct sk_buff *skb = bi->skb;
1108 dma_addr_t dma = bi->dma;
1109
1110 if (dma)
1111 return true;
1112
1113 if (likely(!skb)) {
1114 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1115 rx_ring->rx_buf_len);
1116 bi->skb = skb;
1117 if (!skb) {
1118 rx_ring->rx_stats.alloc_rx_buff_failed++;
1119 return false;
1120 }
1121
1122 /* initialize skb for ring */
1123 skb_record_rx_queue(skb, rx_ring->queue_index);
1124 }
1125
1126 dma = dma_map_single(rx_ring->dev, skb->data,
1127 rx_ring->rx_buf_len, DMA_FROM_DEVICE);
1128
1129 if (dma_mapping_error(rx_ring->dev, dma)) {
1130 rx_ring->rx_stats.alloc_rx_buff_failed++;
1131 return false;
1132 }
1133
1134 bi->dma = dma;
1135 return true;
1136}
1137
1138static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1139 struct ixgbe_rx_buffer *bi)
1140{
1141 struct page *page = bi->page;
1142 dma_addr_t page_dma = bi->page_dma;
1143 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
1144
1145 if (page_dma)
1146 return true;
1147
1148 if (!page) {
1149 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
1150 bi->page = page;
1151 if (unlikely(!page)) {
1152 rx_ring->rx_stats.alloc_rx_page_failed++;
1153 return false;
1154 }
1155 }
1156
1157 page_dma = dma_map_page(rx_ring->dev, page,
1158 page_offset, PAGE_SIZE / 2,
1159 DMA_FROM_DEVICE);
1160
1161 if (dma_mapping_error(rx_ring->dev, page_dma)) {
1162 rx_ring->rx_stats.alloc_rx_page_failed++;
1163 return false;
1164 }
1165
1166 bi->page_dma = page_dma;
1167 bi->page_offset = page_offset;
1168 return true;
1169}
1170
9a799d71 1171/**
f990b79b 1172 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1173 * @rx_ring: ring to place buffers on
1174 * @cleaned_count: number of buffers to replace
9a799d71 1175 **/
fc77dc3c 1176void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1177{
9a799d71 1178 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1179 struct ixgbe_rx_buffer *bi;
d5f398ed 1180 u16 i = rx_ring->next_to_use;
9a799d71 1181
f990b79b
AD		 1182 /* nothing to do or no valid netdev defined */
1183 if (!cleaned_count || !rx_ring->netdev)
fc77dc3c
AD		 1184 return;
1185
f990b79b
AD		 1186 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1187 bi = &rx_ring->rx_buffer_info[i];
1188 i -= rx_ring->count;
9a799d71 1189
f990b79b
AD		 1190 while (cleaned_count--) {
1191 if (!ixgbe_alloc_mapped_skb(rx_ring, bi))
1192 break;
d5f398ed 1193
f990b79b
AD		 1194 /* Refresh the desc even if buffer_addrs didn't change
1195 * because each write-back erases this info. */
7d637bcc 1196 if (ring_is_ps_enabled(rx_ring)) {
f990b79b 1197 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
d5f398ed 1198
f990b79b
AD		 1199 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1200 break;
d5f398ed 1201
3a581073 1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
9a799d71 1203 } else {
3a581073 1204 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1205 }
1206
f990b79b
AD		 1207 rx_desc++;
1208 bi++;
9a799d71 1209 i++;
f990b79b
AD		 1210 if (unlikely(!i)) {
1211 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, 0);
1212 bi = rx_ring->rx_buffer_info;
1213 i -= rx_ring->count;
1214 }
1215
1216 /* clear the hdr_addr for the next_to_use descriptor */
1217 rx_desc->read.hdr_addr = 0;
9a799d71 1218 }
7c6e0a43 1219
f990b79b
AD		 1220 i += rx_ring->count;
1221
9a799d71
AK		 1222 if (rx_ring->next_to_use != i) {
1223 rx_ring->next_to_use = i;
84ea2591 1224 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1225 }
1226}
1227
c267fc16 1228static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1229{
c267fc16
AD		 1230 /* HW will not DMA in data larger than the given buffer, even if it
1231 * parses the (NFS, of course) header to be larger. In that case, it
1232 * fills the header buffer and spills the rest into the page.
1233 */
1234 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1235 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1236 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1237 if (hlen > IXGBE_RX_HDR_SIZE)
1238 hlen = IXGBE_RX_HDR_SIZE;
1239 return hlen;
7c6e0a43
JB		 1240}
1241
f8212f97 1242/**
4c1975d7
AD		 1243 * ixgbe_merge_active_tail - merge active tail into lro skb
1244 * @tail: pointer to active tail in frag_list
f8212f97 1245 *
4c1975d7
AD		 1246 * This function merges the length and data of an active tail into the
1247 * skb containing the frag_list. It resets the tail's pointer to the head,
1248 * but it leaves the heads pointer to tail intact.
f8212f97 1249 **/
4c1975d7 1250static inline struct sk_buff *ixgbe_merge_active_tail(struct sk_buff *tail)
f8212f97 1251{
4c1975d7 1252 struct sk_buff *head = IXGBE_CB(tail)->head;
f8212f97 1253
4c1975d7
AD		 1254 if (!head)
1255 return tail;
1256
1257 head->len += tail->len;
1258 head->data_len += tail->len;
1259 head->truesize += tail->len;
1260
1261 IXGBE_CB(tail)->head = NULL;
1262
1263 return head;
1264}
1265
1266/**
1267 * ixgbe_add_active_tail - adds an active tail into the skb frag_list
1268 * @head: pointer to the start of the skb
1269 * @tail: pointer to active tail to add to frag_list
1270 *
1271 * This function adds an active tail to the end of the frag list. This tail
1272 * will still be receiving data so we cannot yet ad it's stats to the main
1273 * skb. That is done via ixgbe_merge_active_tail.
1274 **/
1275static inline void ixgbe_add_active_tail(struct sk_buff *head,
1276 struct sk_buff *tail)
1277{
1278 struct sk_buff *old_tail = IXGBE_CB(head)->tail;
1279
1280 if (old_tail) {
1281 ixgbe_merge_active_tail(old_tail);
1282 old_tail->next = tail;
1283 } else {
1284 skb_shinfo(head)->frag_list = tail;
f8212f97
AD		 1285 }
1286
4c1975d7
AD		 1287 IXGBE_CB(tail)->head = head;
1288 IXGBE_CB(head)->tail = tail;
1289}
1290
1291/**
1292 * ixgbe_close_active_frag_list - cleanup pointers on a frag_list skb
1293 * @head: pointer to head of an active frag list
1294 *
1295 * This function will clear the frag_tail_tracker pointer on an active
1296 * frag_list and returns true if the pointer was actually set
1297 **/
1298static inline bool ixgbe_close_active_frag_list(struct sk_buff *head)
1299{
1300 struct sk_buff *tail = IXGBE_CB(head)->tail;
1301
1302 if (!tail)
1303 return false;
1304
1305 ixgbe_merge_active_tail(tail);
1306
1307 IXGBE_CB(head)->tail = NULL;
aa80175a 1308
4c1975d7 1309 return true;
f8212f97
AD		 1310}
1311
1d2024f6
AD		 1312/**
1313 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1314 * @data: pointer to the start of the headers
1315 * @max_len: total length of section to find headers in
1316 *
1317 * This function is meant to determine the length of headers that will
1318 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1319 * motivation of doing this is to only perform one pull for IPv4 TCP
1320 * packets so that we can do basic things like calculating the gso_size
1321 * based on the average data per packet.
1322 **/
1323static unsigned int ixgbe_get_headlen(unsigned char *data,
1324 unsigned int max_len)
1325{
1326 union {
1327 unsigned char *network;
1328 /* l2 headers */
1329 struct ethhdr *eth;
1330 struct vlan_hdr *vlan;
1331 /* l3 headers */
1332 struct iphdr *ipv4;
1333 } hdr;
1334 __be16 protocol;
1335 u8 nexthdr = 0; /* default to not TCP */
1336 u8 hlen;
1337
1338 /* this should never happen, but better safe than sorry */
1339 if (max_len < ETH_HLEN)
1340 return max_len;
1341
1342 /* initialize network frame pointer */
1343 hdr.network = data;
1344
1345 /* set first protocol and move network header forward */
1346 protocol = hdr.eth->h_proto;
1347 hdr.network += ETH_HLEN;
1348
1349 /* handle any vlan tag if present */
1350 if (protocol == __constant_htons(ETH_P_8021Q)) {
1351 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1352 return max_len;
1353
1354 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1355 hdr.network += VLAN_HLEN;
1356 }
1357
1358 /* handle L3 protocols */
1359 if (protocol == __constant_htons(ETH_P_IP)) {
1360 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1361 return max_len;
1362
1363 /* access ihl as a u8 to avoid unaligned access on ia64 */
1364 hlen = (hdr.network[0] & 0x0F) << 2;
1365
1366 /* verify hlen meets minimum size requirements */
1367 if (hlen < sizeof(struct iphdr))
1368 return hdr.network - data;
1369
1370 /* record next protocol */
1371 nexthdr = hdr.ipv4->protocol;
1372 hdr.network += hlen;
1373#ifdef CONFIG_FCOE
1374 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1375 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1376 return max_len;
1377 hdr.network += FCOE_HEADER_LEN;
1378#endif
1379 } else {
1380 return hdr.network - data;
1381 }
1382
1383 /* finally sort out TCP */
1384 if (nexthdr == IPPROTO_TCP) {
1385 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1386 return max_len;
1387
1388 /* access doff as a u8 to avoid unaligned access on ia64 */
1389 hlen = (hdr.network[12] & 0xF0) >> 2;
1390
1391 /* verify hlen meets minimum size requirements */
1392 if (hlen < sizeof(struct tcphdr))
1393 return hdr.network - data;
1394
1395 hdr.network += hlen;
1396 }
1397
1398 /*
1399 * If everything has gone correctly hdr.network should be the
1400 * data section of the packet and will be the end of the header.
1401 * If not then it probably represents the end of the last recognized
1402 * header.
1403 */
1404 if ((hdr.network - data) < max_len)
1405 return hdr.network - data;
1406 else
1407 return max_len;
1408}
1409
4c1975d7
AD		 1410static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1411 union ixgbe_adv_rx_desc *rx_desc,
1412 struct sk_buff *skb)
aa80175a 1413{
4c1975d7
AD		 1414 __le32 rsc_enabled;
1415 u32 rsc_cnt;
1416
1417 if (!ring_is_rsc_enabled(rx_ring))
1418 return;
1419
1420 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1421 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1422
1423 /* If this is an RSC frame rsc_cnt should be non-zero */
1424 if (!rsc_enabled)
1425 return;
1426
1427 rsc_cnt = le32_to_cpu(rsc_enabled);
1428 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1429
1430 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1431}
43634e82 1432
1d2024f6
AD		 1433static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1434 struct sk_buff *skb)
1435{
1436 u16 hdr_len = ixgbe_get_headlen(skb->data, skb_headlen(skb));
1437
1438 /* set gso_size to avoid messing up TCP MSS */
1439 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1440 IXGBE_CB(skb)->append_cnt);
1441}
1442
1443static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1444 struct sk_buff *skb)
1445{
1446 /* if append_cnt is 0 then frame is not RSC */
1447 if (!IXGBE_CB(skb)->append_cnt)
1448 return;
1449
1450 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1451 rx_ring->rx_stats.rsc_flush++;
1452
1453 ixgbe_set_rsc_gso_size(rx_ring, skb);
1454
1455 /* gso_size is computed using append_cnt so always clear it last */
1456 IXGBE_CB(skb)->append_cnt = 0;
1457}
1458
4ff7fb12 1459static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1460 struct ixgbe_ring *rx_ring,
4ff7fb12 1461 int budget)
9a799d71 1462{
78b6f4ce 1463 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71 1464 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
4c1975d7 1465 struct ixgbe_rx_buffer *rx_buffer_info;
9a799d71 1466 struct sk_buff *skb;
d2f4fbe2 1467 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1468 const int current_node = numa_node_id();
3d8fd385
YZ		 1469#ifdef IXGBE_FCOE
1470 int ddp_bytes = 0;
1471#endif /* IXGBE_FCOE */
c267fc16
AD		 1472 u32 staterr;
1473 u16 i;
1474 u16 cleaned_count = 0;
9a799d71
AK		 1475
1476 i = rx_ring->next_to_clean;
31f05a2d 1477 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1478 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1479
1480 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1481 u32 upper_len = 0;
9a799d71 1482
3c945e5b 1483 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1484
c267fc16
AD		 1485 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1486
9a799d71 1487 skb = rx_buffer_info->skb;
9a799d71 1488 rx_buffer_info->skb = NULL;
c267fc16 1489 prefetch(skb->data);
9a799d71 1490
b811ce91
JB		 1491 /* linear means we are building an skb from multiple pages */
1492 if (!skb_is_nonlinear(skb)) {
c267fc16 1493 u16 hlen;
c267fc16
AD		 1494 if (ring_is_ps_enabled(rx_ring)) {
1495 hlen = ixgbe_get_hlen(rx_desc);
1496 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1497 } else {
1498 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1499 }
1500
1501 skb_put(skb, hlen);
4c1975d7
AD		 1502
1503 /*
1504 * Delay unmapping of the first packet. It carries the
1505 * header information, HW may still access the header
1506 * after writeback. Only unmap it when EOP is reached
1507 */
1508 if (!IXGBE_CB(skb)->head) {
1509 IXGBE_CB(skb)->delay_unmap = true;
1510 IXGBE_CB(skb)->dma = rx_buffer_info->dma;
1511 } else {
1512 skb = ixgbe_merge_active_tail(skb);
1513 dma_unmap_single(rx_ring->dev,
1514 rx_buffer_info->dma,
1515 rx_ring->rx_buf_len,
1516 DMA_FROM_DEVICE);
1517 }
1518 rx_buffer_info->dma = 0;
c267fc16
AD		 1519 } else {
1520 /* assume packet split since header is unmapped */
1521 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1522 }
1523
1524 if (upper_len) {
b6ec895e
AD		 1525 dma_unmap_page(rx_ring->dev,
1526 rx_buffer_info->page_dma,
1527 PAGE_SIZE / 2,
1528 DMA_FROM_DEVICE);
9a799d71
AK		 1529 rx_buffer_info->page_dma = 0;
1530 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1531 rx_buffer_info->page,
1532 rx_buffer_info->page_offset,
1533 upper_len);
762f4c57 1534
c267fc16
AD		 1535 if ((page_count(rx_buffer_info->page) == 1) &&
1536 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1537 get_page(rx_buffer_info->page);
c267fc16
AD		 1538 else
1539 rx_buffer_info->page = NULL;
9a799d71
AK		 1540
1541 skb->len += upper_len;
1542 skb->data_len += upper_len;
98130646 1543 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1544 }
1545
4c1975d7
AD		 1546 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1547
9a799d71
AK		 1548 i++;
1549 if (i == rx_ring->count)
1550 i = 0;
9a799d71 1551
31f05a2d 1552 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1553 prefetch(next_rxd);
9a799d71 1554 cleaned_count++;
f8212f97 1555
4c1975d7
AD		 1556 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1557 struct ixgbe_rx_buffer *next_buffer;
1558 u32 nextp;
1559
1560 if (IXGBE_CB(skb)->append_cnt) {
1561 nextp = staterr & IXGBE_RXDADV_NEXTP_MASK;
1562 nextp >>= IXGBE_RXDADV_NEXTP_SHIFT;
1563 } else {
1564 nextp = i;
1565 }
1566
f8212f97 1567 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97 1568
7d637bcc 1569 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1570 rx_buffer_info->skb = next_buffer->skb;
1571 rx_buffer_info->dma = next_buffer->dma;
1572 next_buffer->skb = skb;
1573 next_buffer->dma = 0;
1574 } else {
4c1975d7
AD		 1575 struct sk_buff *next_skb = next_buffer->skb;
1576 ixgbe_add_active_tail(skb, next_skb);
1577 IXGBE_CB(next_skb)->head = skb;
f8212f97 1578 }
5b7da515 1579 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1580 goto next_desc;
1581 }
1582
4c1975d7
AD		 1583 dma_unmap_single(rx_ring->dev,
1584 IXGBE_CB(skb)->dma,
1585 rx_ring->rx_buf_len,
1586 DMA_FROM_DEVICE);
1587 IXGBE_CB(skb)->dma = 0;
1588 IXGBE_CB(skb)->delay_unmap = false;
1589
1590 if (ixgbe_close_active_frag_list(skb) &&
1591 !IXGBE_CB(skb)->append_cnt) {
aa80175a 1592 /* if we got here without RSC the packet is invalid */
4c1975d7
AD		 1593 dev_kfree_skb_any(skb);
1594 goto next_desc;
aa80175a 1595 }
c267fc16 1596
1d2024f6 1597 ixgbe_update_rsc_stats(rx_ring, skb);
c267fc16
AD		 1598
1599 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1600 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1601 dev_kfree_skb_any(skb);
9a799d71
AK		 1602 goto next_desc;
1603 }
1604
ff886dfc 1605 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1606 if (adapter->netdev->features & NETIF_F_RXHASH)
1607 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1608
1609 /* probably a little skewed due to removing CRC */
1610 total_rx_bytes += skb->len;
1611 total_rx_packets++;
1612
fc77dc3c 1613 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1614#ifdef IXGBE_FCOE
1615 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1616 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1617 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1618 staterr);
63d635b2
AD		 1619 if (!ddp_bytes) {
1620 dev_kfree_skb_any(skb);
332d4a7d 1621 goto next_desc;
63d635b2 1622 }
3d8fd385 1623 }
332d4a7d 1624#endif /* IXGBE_FCOE */
fdaff1ce 1625 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1626
4ff7fb12 1627 budget--;
9a799d71 1628next_desc:
4ff7fb12 1629 if (!budget)
c267fc16
AD		 1630 break;
1631
9a799d71
AK		 1632 /* return some buffers to hardware, one at a time is too slow */
1633 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1634 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1635 cleaned_count = 0;
1636 }
1637
1638 /* use prefetched values */
1639 rx_desc = next_rxd;
9a799d71 1640 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1641 }
1642
9a799d71 1643 rx_ring->next_to_clean = i;
7d4987de 1644 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1645
1646 if (cleaned_count)
fc77dc3c 1647 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1648
3d8fd385
YZ		 1649#ifdef IXGBE_FCOE
1650 /* include DDPed FCoE data */
1651 if (ddp_bytes > 0) {
1652 unsigned int mss;
1653
fc77dc3c 1654 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1655 sizeof(struct fc_frame_header) -
1656 sizeof(struct fcoe_crc_eof);
1657 if (mss > 512)
1658 mss &= ~511;
1659 total_rx_bytes += ddp_bytes;
1660 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1661 }
1662#endif /* IXGBE_FCOE */
1663
c267fc16
AD		 1664 u64_stats_update_begin(&rx_ring->syncp);
1665 rx_ring->stats.packets += total_rx_packets;
1666 rx_ring->stats.bytes += total_rx_bytes;
1667 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1668 q_vector->rx.total_packets += total_rx_packets;
1669 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1670
1671 return !!budget;
9a799d71
AK		 1672}
1673
9a799d71
AK		 1674/**
1675 * ixgbe_configure_msix - Configure MSI-X hardware
1676 * @adapter: board private structure
1677 *
1678 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1679 * interrupts.
1680 **/
1681static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1682{
021230d4 1683 struct ixgbe_q_vector *q_vector;
efe3d3c8 1684 int q_vectors, v_idx;
021230d4 1685 u32 mask;
9a799d71 1686
021230d4 1687 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1688
8e34d1aa
AD		 1689 /* Populate MSIX to EITR Select */
1690 if (adapter->num_vfs > 32) {
1691 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1692 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1693 }
1694
4df10466
JB		 1695 /*
1696 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1697 * corresponding register.
1698 */
1699 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1700 struct ixgbe_ring *ring;
7a921c93 1701 q_vector = adapter->q_vector[v_idx];
021230d4 1702
efe3d3c8
AD		 1703 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1704 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1705
1706 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1707 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1708
d5bf4f67
ET		 1709 if (q_vector->tx.ring && !q_vector->rx.ring) {
1710 /* tx only vector */
1711 if (adapter->tx_itr_setting == 1)
1712 q_vector->itr = IXGBE_10K_ITR;
1713 else
1714 q_vector->itr = adapter->tx_itr_setting;
1715 } else {
1716 /* rx or rx/tx vector */
1717 if (adapter->rx_itr_setting == 1)
1718 q_vector->itr = IXGBE_20K_ITR;
1719 else
1720 q_vector->itr = adapter->rx_itr_setting;
1721 }
021230d4 1722
fe49f04a 1723 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1724 }
1725
bd508178
AD		 1726 switch (adapter->hw.mac.type) {
1727 case ixgbe_mac_82598EB:
e8e26350 1728 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1729 v_idx);
bd508178
AD		 1730 break;
1731 case ixgbe_mac_82599EB:
b93a2226 1732 case ixgbe_mac_X540:
e8e26350 1733 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1734 break;
bd508178
AD		 1735 default:
1736 break;
1737 }
021230d4
AV		 1738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1739
41fb9248 1740 /* set up to autoclear timer, and the vectors */
021230d4 1741 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1742 mask &= ~(IXGBE_EIMS_OTHER |
1743 IXGBE_EIMS_MAILBOX |
1744 IXGBE_EIMS_LSC);
1745
021230d4 1746 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1747}
1748
f494e8fa
AV		 1749enum latency_range {
1750 lowest_latency = 0,
1751 low_latency = 1,
1752 bulk_latency = 2,
1753 latency_invalid = 255
1754};
1755
1756/**
1757 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1758 * @q_vector: structure containing interrupt and ring information
1759 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1760 *
1761 * Stores a new ITR value based on packets and byte
1762 * counts during the last interrupt. The advantage of per interrupt
1763 * computation is faster updates and more accurate ITR for the current
1764 * traffic pattern. Constants in this function were computed
1765 * based on theoretical maximum wire speed and thresholds were set based
1766 * on testing data as well as attempting to minimize response time
1767 * while increasing bulk throughput.
1768 * this functionality is controlled by the InterruptThrottleRate module
1769 * parameter (see ixgbe_param.c)
1770 **/
bd198058
AD		 1771static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1772 struct ixgbe_ring_container *ring_container)
f494e8fa 1773{
f494e8fa 1774 u64 bytes_perint;
bd198058
AD		 1775 struct ixgbe_adapter *adapter = q_vector->adapter;
1776 int bytes = ring_container->total_bytes;
1777 int packets = ring_container->total_packets;
1778 u32 timepassed_us;
1779 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1780
1781 if (packets == 0)
bd198058 1782 return;
f494e8fa
AV		 1783
1784 /* simple throttlerate management
1785 * 0-20MB/s lowest (100000 ints/s)
1786 * 20-100MB/s low (20000 ints/s)
1787 * 100-1249MB/s bulk (8000 ints/s)
1788 */
1789 /* what was last interrupt timeslice? */
d5bf4f67 1790 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1791 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1792
1793 switch (itr_setting) {
1794 case lowest_latency:
1795 if (bytes_perint > adapter->eitr_low)
bd198058 1796 itr_setting = low_latency;
f494e8fa
AV		 1797 break;
1798 case low_latency:
1799 if (bytes_perint > adapter->eitr_high)
bd198058 1800 itr_setting = bulk_latency;
f494e8fa 1801 else if (bytes_perint <= adapter->eitr_low)
bd198058 1802 itr_setting = lowest_latency;
f494e8fa
AV		 1803 break;
1804 case bulk_latency:
1805 if (bytes_perint <= adapter->eitr_high)
bd198058 1806 itr_setting = low_latency;
f494e8fa
AV		 1807 break;
1808 }
1809
bd198058
AD		 1810 /* clear work counters since we have the values we need */
1811 ring_container->total_bytes = 0;
1812 ring_container->total_packets = 0;
1813
1814 /* write updated itr to ring container */
1815 ring_container->itr = itr_setting;
f494e8fa
AV		 1816}
1817
509ee935
JB		 1818/**
1819 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1820 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1821 *
1822 * This function is made to be called by ethtool and by the driver
1823 * when it needs to update EITR registers at runtime. Hardware
1824 * specific quirks/differences are taken care of here.
1825 */
fe49f04a 1826void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1827{
fe49f04a 1828 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1829 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1830 int v_idx = q_vector->v_idx;
d5bf4f67 1831 u32 itr_reg = q_vector->itr;
fe49f04a 1832
bd508178
AD		 1833 switch (adapter->hw.mac.type) {
1834 case ixgbe_mac_82598EB:
509ee935
JB		 1835 /* must write high and low 16 bits to reset counter */
1836 itr_reg |= (itr_reg << 16);
bd508178
AD		 1837 break;
1838 case ixgbe_mac_82599EB:
b93a2226 1839 case ixgbe_mac_X540:
509ee935
JB		 1840 /*
1841 * set the WDIS bit to not clear the timer bits and cause an
1842 * immediate assertion of the interrupt
1843 */
1844 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1845 break;
1846 default:
1847 break;
509ee935
JB		 1848 }
1849 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1850}
1851
bd198058 1852static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1853{
d5bf4f67 1854 u32 new_itr = q_vector->itr;
bd198058 1855 u8 current_itr;
f494e8fa 1856
bd198058
AD		 1857 ixgbe_update_itr(q_vector, &q_vector->tx);
1858 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1859
08c8833b 1860 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1861
1862 switch (current_itr) {
1863 /* counts and packets in update_itr are dependent on these numbers */
1864 case lowest_latency:
d5bf4f67 1865 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1866 break;
1867 case low_latency:
d5bf4f67 1868 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1869 break;
1870 case bulk_latency:
d5bf4f67 1871 new_itr = IXGBE_8K_ITR;
f494e8fa 1872 break;
bd198058
AD		 1873 default:
1874 break;
f494e8fa
AV		 1875 }
1876
d5bf4f67 1877 if (new_itr != q_vector->itr) {
fe49f04a 1878 /* do an exponential smoothing */
d5bf4f67
ET		 1879 new_itr = (10 * new_itr * q_vector->itr) /
1880 ((9 * new_itr) + q_vector->itr);
509ee935 1881
bd198058 1882 /* save the algorithm value here */
d5bf4f67 1883 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1884
1885 ixgbe_write_eitr(q_vector);
f494e8fa 1886 }
f494e8fa
AV		 1887}
1888
119fc60a 1889/**
f0f9778d
AD		 1890 * ixgbe_check_overtemp_subtask - check for over tempurature
1891 * @adapter: pointer to adapter
119fc60a 1892 **/
f0f9778d 1893static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1894{
119fc60a
MC		 1895 struct ixgbe_hw *hw = &adapter->hw;
1896 u32 eicr = adapter->interrupt_event;
1897
f0f9778d 1898 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1899 return;
1900
f0f9778d
AD		 1901 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1902 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1903 return;
1904
1905 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1906
7ca647bd 1907 switch (hw->device_id) {
f0f9778d
AD		 1908 case IXGBE_DEV_ID_82599_T3_LOM:
1909 /*
1910 * Since the warning interrupt is for both ports
1911 * we don't have to check if:
1912 * - This interrupt wasn't for our port.
1913 * - We may have missed the interrupt so always have to
1914 * check if we got a LSC
1915 */
1916 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1917 !(eicr & IXGBE_EICR_LSC))
1918 return;
1919
1920 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1921 u32 autoneg;
1922 bool link_up = false;
7ca647bd 1923
7ca647bd
JP		 1924 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1925
f0f9778d
AD		 1926 if (link_up)
1927 return;
1928 }
1929
1930 /* Check if this is not due to overtemp */
1931 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1932 return;
1933
1934 break;
7ca647bd
JP		 1935 default:
1936 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1937 return;
7ca647bd 1938 break;
119fc60a 1939 }
7ca647bd
JP		 1940 e_crit(drv,
1941 "Network adapter has been stopped because it has over heated. "
1942 "Restart the computer. If the problem persists, "
1943 "power off the system and replace the adapter\n");
f0f9778d
AD		 1944
1945 adapter->interrupt_event = 0;
119fc60a
MC		 1946}
1947
0befdb3e
JB		 1948static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1949{
1950 struct ixgbe_hw *hw = &adapter->hw;
1951
1952 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1953 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1954 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1955 /* write to clear the interrupt */
1956 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1957 }
1958}
cf8280ee 1959
4f51bf70
JK		 1960static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1961{
1962 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1963 return;
1964
1965 switch (adapter->hw.mac.type) {
1966 case ixgbe_mac_82599EB:
1967 /*
1968 * Need to check link state so complete overtemp check
1969 * on service task
1970 */
1971 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1972 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1973 adapter->interrupt_event = eicr;
1974 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1975 ixgbe_service_event_schedule(adapter);
1976 return;
1977 }
1978 return;
1979 case ixgbe_mac_X540:
1980 if (!(eicr & IXGBE_EICR_TS))
1981 return;
1982 break;
1983 default:
1984 return;
1985 }
1986
1987 e_crit(drv,
1988 "Network adapter has been stopped because it has over heated. "
1989 "Restart the computer. If the problem persists, "
1990 "power off the system and replace the adapter\n");
1991}
1992
e8e26350
PW		 1993static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1994{
1995 struct ixgbe_hw *hw = &adapter->hw;
1996
73c4b7cd
AD		 1997 if (eicr & IXGBE_EICR_GPI_SDP2) {
1998 /* Clear the interrupt */
1999 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2000 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2001 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2002 ixgbe_service_event_schedule(adapter);
2003 }
73c4b7cd
AD		 2004 }
2005
e8e26350
PW		 2006 if (eicr & IXGBE_EICR_GPI_SDP1) {
2007 /* Clear the interrupt */
2008 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2009 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2010 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2011 ixgbe_service_event_schedule(adapter);
2012 }
e8e26350
PW		 2013 }
2014}
2015
cf8280ee
JB		 2016static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2017{
2018 struct ixgbe_hw *hw = &adapter->hw;
2019
2020 adapter->lsc_int++;
2021 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2022 adapter->link_check_timeout = jiffies;
2023 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2024 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2025 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2026 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2027 }
2028}
2029
fe49f04a
AD		 2030static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2031 u64 qmask)
2032{
2033 u32 mask;
bd508178 2034 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2035
bd508178
AD		 2036 switch (hw->mac.type) {
2037 case ixgbe_mac_82598EB:
fe49f04a 2038 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2039 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2040 break;
2041 case ixgbe_mac_82599EB:
b93a2226 2042 case ixgbe_mac_X540:
fe49f04a 2043 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2044 if (mask)
2045 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2046 mask = (qmask >> 32);
bd508178
AD		 2047 if (mask)
2048 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2049 break;
2050 default:
2051 break;
fe49f04a
AD		 2052 }
2053 /* skip the flush */
2054}
2055
2056static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2057 u64 qmask)
fe49f04a
AD		 2058{
2059 u32 mask;
bd508178 2060 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2061
bd508178
AD		 2062 switch (hw->mac.type) {
2063 case ixgbe_mac_82598EB:
fe49f04a 2064 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2065 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2066 break;
2067 case ixgbe_mac_82599EB:
b93a2226 2068 case ixgbe_mac_X540:
fe49f04a 2069 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2070 if (mask)
2071 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2072 mask = (qmask >> 32);
bd508178
AD		 2073 if (mask)
2074 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2075 break;
2076 default:
2077 break;
fe49f04a
AD		 2078 }
2079 /* skip the flush */
2080}
2081
021230d4 2082/**
2c4af694
AD		 2083 * ixgbe_irq_enable - Enable default interrupt generation settings
2084 * @adapter: board private structure
021230d4 2085 **/
2c4af694
AD		 2086static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2087 bool flush)
9a799d71 2088{
2c4af694 2089 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2090
2c4af694
AD		 2091 /* don't reenable LSC while waiting for link */
2092 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2093 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2094
2c4af694 2095 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2096 switch (adapter->hw.mac.type) {
2097 case ixgbe_mac_82599EB:
2098 mask |= IXGBE_EIMS_GPI_SDP0;
2099 break;
2100 case ixgbe_mac_X540:
2101 mask |= IXGBE_EIMS_TS;
2102 break;
2103 default:
2104 break;
2105 }
2c4af694
AD		 2106 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2107 mask |= IXGBE_EIMS_GPI_SDP1;
2108 switch (adapter->hw.mac.type) {
2109 case ixgbe_mac_82599EB:
2c4af694
AD		 2110 mask |= IXGBE_EIMS_GPI_SDP1;
2111 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2112 case ixgbe_mac_X540:
2113 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2114 mask |= IXGBE_EIMS_MAILBOX;
2115 break;
2116 default:
2117 break;
9a799d71 2118 }
2c4af694
AD		 2119 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2120 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2121 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2122
2c4af694
AD		 2123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2124 if (queues)
2125 ixgbe_irq_enable_queues(adapter, ~0);
2126 if (flush)
2127 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2128}
2129
2c4af694 2130static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2131{
a65151ba 2132 struct ixgbe_adapter *adapter = data;
9a799d71 2133 struct ixgbe_hw *hw = &adapter->hw;
54037505 2134 u32 eicr;
91281fd3 2135
54037505
DS		 2136 /*
2137 * Workaround for Silicon errata. Use clear-by-write instead
2138 * of clear-by-read. Reading with EICS will return the
2139 * interrupt causes without clearing, which later be done
2140 * with the write to EICR.
2141 */
2142 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2143 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2144
cf8280ee
JB		 2145 if (eicr & IXGBE_EICR_LSC)
2146 ixgbe_check_lsc(adapter);
f0848276 2147
1cdd1ec8
GR		 2148 if (eicr & IXGBE_EICR_MAILBOX)
2149 ixgbe_msg_task(adapter);
efe3d3c8 2150
bd508178
AD		 2151 switch (hw->mac.type) {
2152 case ixgbe_mac_82599EB:
b93a2226 2153 case ixgbe_mac_X540:
2c4af694
AD		 2154 if (eicr & IXGBE_EICR_ECC)
2155 e_info(link, "Received unrecoverable ECC Err, please "
2156 "reboot\n");
c4cf55e5
PWJ		 2157 /* Handle Flow Director Full threshold interrupt */
2158 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2159 int reinit_count = 0;
c4cf55e5 2160 int i;
c4cf55e5 2161 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2162 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2163 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2164 &ring->state))
2165 reinit_count++;
2166 }
2167 if (reinit_count) {
2168 /* no more flow director interrupts until after init */
2169 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2170 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2171 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2172 }
2173 }
f0f9778d 2174 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2175 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2176 break;
2177 default:
2178 break;
c4cf55e5 2179 }
f0848276 2180
bd508178 2181 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 2182
7086400d 2183 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2184 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2185 ixgbe_irq_enable(adapter, false, false);
f0848276 2186
9a799d71 2187 return IRQ_HANDLED;
f0848276 2188}
91281fd3 2189
4ff7fb12 2190static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2191{
021230d4 2192 struct ixgbe_q_vector *q_vector = data;
91281fd3 2193
9b471446 2194 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2195
4ff7fb12
AD		 2196 if (q_vector->rx.ring || q_vector->tx.ring)
2197 napi_schedule(&q_vector->napi);
91281fd3 2198
9a799d71 2199 return IRQ_HANDLED;
91281fd3
AD		 2200}
2201
021230d4 2202static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2203 int r_idx)
021230d4 2204{
7a921c93 2205 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2206 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2207
2274543f 2208 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2209 rx_ring->next = q_vector->rx.ring;
2210 q_vector->rx.ring = rx_ring;
2211 q_vector->rx.count++;
021230d4
AV		 2212}
2213
2214static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2215 int t_idx)
021230d4 2216{
7a921c93 2217 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2218 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2219
2274543f 2220 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2221 tx_ring->next = q_vector->tx.ring;
2222 q_vector->tx.ring = tx_ring;
2223 q_vector->tx.count++;
bd198058 2224 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2225}
2226
9a799d71 2227/**
021230d4
AV		 2228 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2229 * @adapter: board private structure to initialize
9a799d71 2230 *
021230d4
AV		 2231 * This function maps descriptor rings to the queue-specific vectors
2232 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2233 * one vector per ring/queue, but on a constrained vector budget, we
2234 * group the rings as "efficiently" as possible. You would add new
2235 * mapping configurations in here.
9a799d71 2236 **/
4cc6df29 2237static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2238{
4cc6df29
AD		 2239 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2240 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2241 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2242 int v_start = 0;
021230d4 2243
4cc6df29 2244 /* only one q_vector if MSI-X is disabled. */
021230d4 2245 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2246 q_vectors = 1;
d0759ebb 2247
021230d4 2248 /*
4cc6df29
AD		 2249 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2250 * group them so there are multiple queues per vector.
2251 *
2252 * Re-adjusting *qpv takes care of the remainder.
021230d4 2253 */
4cc6df29
AD		 2254 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2255 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2256 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2257 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2258 }
9a799d71 2259
021230d4 2260 /*
4cc6df29
AD		 2261 * If there are not enough q_vectors for each ring to have it's own
2262 * vector then we must pair up Rx/Tx on a each vector
021230d4 2263 */
4cc6df29
AD		 2264 if ((v_start + txr_remaining) > q_vectors)
2265 v_start = 0;
2266
2267 for (; v_start < q_vectors && txr_remaining; v_start++) {
2268 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2269 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2270 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2271 }
021230d4
AV		 2272}
2273
2274/**
2275 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2276 * @adapter: board private structure
2277 *
2278 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2279 * interrupts from the kernel.
2280 **/
2281static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2282{
2283 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2284 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2285 int vector, err;
e8e9f696 2286 int ri = 0, ti = 0;
021230d4 2287
021230d4 2288 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2289 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2290 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2291
4ff7fb12 2292 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2293 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2294 "%s-%s-%d", netdev->name, "TxRx", ri++);
2295 ti++;
2296 } else if (q_vector->rx.ring) {
9fe93afd 2297 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2298 "%s-%s-%d", netdev->name, "rx", ri++);
2299 } else if (q_vector->tx.ring) {
9fe93afd 2300 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2301 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2302 } else {
2303 /* skip this unused q_vector */
2304 continue;
32aa77a4 2305 }
207867f5
AD		 2306 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2307 q_vector->name, q_vector);
9a799d71 2308 if (err) {
396e799c 2309 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2310 "Error: %d\n", err);
021230d4 2311 goto free_queue_irqs;
9a799d71 2312 }
207867f5
AD		 2313 /* If Flow Director is enabled, set interrupt affinity */
2314 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2315 /* assign the mask for this irq */
2316 irq_set_affinity_hint(entry->vector,
2317 q_vector->affinity_mask);
2318 }
9a799d71
AK		 2319 }
2320
021230d4 2321 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2322 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2323 if (err) {
396e799c 2324 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2325 goto free_queue_irqs;
9a799d71
AK		 2326 }
2327
9a799d71
AK		 2328 return 0;
2329
021230d4 2330free_queue_irqs:
207867f5
AD		 2331 while (vector) {
2332 vector--;
2333 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2334 NULL);
2335 free_irq(adapter->msix_entries[vector].vector,
2336 adapter->q_vector[vector]);
2337 }
021230d4
AV		 2338 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2339 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2340 kfree(adapter->msix_entries);
2341 adapter->msix_entries = NULL;
9a799d71
AK		 2342 return err;
2343}
2344
2345/**
021230d4 2346 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2347 * @irq: interrupt number
2348 * @data: pointer to a network interface device structure
9a799d71
AK		 2349 **/
2350static irqreturn_t ixgbe_intr(int irq, void *data)
2351{
a65151ba 2352 struct ixgbe_adapter *adapter = data;
9a799d71 2353 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2354 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2355 u32 eicr;
2356
54037505 2357 /*
6af3b9eb 2358 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2359 * before the read of EICR.
2360 */
2361 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2362
021230d4 2363 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2364 * therefore no explicit interrupt disable is necessary */
021230d4 2365 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2366 if (!eicr) {
6af3b9eb
ET		 2367 /*
2368 * shared interrupt alert!
f47cf66e 2369 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2370 * have disabled interrupts due to EIAM
2371 * finish the workaround of silicon errata on 82598. Unmask
2372 * the interrupt that we masked before the EICR read.
2373 */
2374 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2375 ixgbe_irq_enable(adapter, true, true);
9a799d71 2376 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2377 }
9a799d71 2378
cf8280ee
JB		 2379 if (eicr & IXGBE_EICR_LSC)
2380 ixgbe_check_lsc(adapter);
021230d4 2381
bd508178
AD		 2382 switch (hw->mac.type) {
2383 case ixgbe_mac_82599EB:
e8e26350 2384 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2385 /* Fall through */
2386 case ixgbe_mac_X540:
2387 if (eicr & IXGBE_EICR_ECC)
2388 e_info(link, "Received unrecoverable ECC err, please "
2389 "reboot\n");
4f51bf70 2390 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2391 break;
2392 default:
2393 break;
2394 }
e8e26350 2395
0befdb3e
JB		 2396 ixgbe_check_fan_failure(adapter, eicr);
2397
7a921c93 2398 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2399 /* would disable interrupts here but EIAM disabled it */
7a921c93 2400 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2401 }
2402
6af3b9eb
ET		 2403 /*
2404 * re-enable link(maybe) and non-queue interrupts, no flush.
2405 * ixgbe_poll will re-enable the queue interrupts
2406 */
2407
2408 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2409 ixgbe_irq_enable(adapter, false, false);
2410
9a799d71
AK		 2411 return IRQ_HANDLED;
2412}
2413
021230d4
AV		 2414static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2415{
efe3d3c8
AD		 2416 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2417 int i;
2418
2419 /* legacy and MSI only use one vector */
2420 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2421 q_vectors = 1;
2422
2423 for (i = 0; i < adapter->num_rx_queues; i++) {
2424 adapter->rx_ring[i]->q_vector = NULL;
2425 adapter->rx_ring[i]->next = NULL;
2426 }
2427 for (i = 0; i < adapter->num_tx_queues; i++) {
2428 adapter->tx_ring[i]->q_vector = NULL;
2429 adapter->tx_ring[i]->next = NULL;
2430 }
021230d4
AV		 2431
2432 for (i = 0; i < q_vectors; i++) {
7a921c93 2433 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2434 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2435 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2436 }
2437}
2438
9a799d71
AK		 2439/**
2440 * ixgbe_request_irq - initialize interrupts
2441 * @adapter: board private structure
2442 *
2443 * Attempts to configure interrupts using the best available
2444 * capabilities of the hardware and kernel.
2445 **/
021230d4 2446static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2447{
2448 struct net_device *netdev = adapter->netdev;
021230d4 2449 int err;
9a799d71 2450
4cc6df29
AD		 2451 /* map all of the rings to the q_vectors */
2452 ixgbe_map_rings_to_vectors(adapter);
2453
2454 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2455 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2456 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2457 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2458 netdev->name, adapter);
4cc6df29 2459 else
a0607fd3 2460 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2461 netdev->name, adapter);
9a799d71 2462
4cc6df29 2463 if (err) {
396e799c 2464 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2465
4cc6df29
AD		 2466 /* place q_vectors and rings back into a known good state */
2467 ixgbe_reset_q_vectors(adapter);
2468 }
2469
9a799d71
AK		 2470 return err;
2471}
2472
2473static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2474{
9a799d71 2475 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2476 int i, q_vectors;
9a799d71 2477
021230d4 2478 q_vectors = adapter->num_msix_vectors;
021230d4 2479 i = q_vectors - 1;
a65151ba 2480 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2481 i--;
4cc6df29 2482
021230d4 2483 for (; i >= 0; i--) {
894ff7cf 2484 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2485 if (!adapter->q_vector[i]->rx.ring &&
2486 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2487 continue;
2488
207867f5
AD		 2489 /* clear the affinity_mask in the IRQ descriptor */
2490 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2491 NULL);
2492
021230d4 2493 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2494 adapter->q_vector[i]);
021230d4 2495 }
021230d4 2496 } else {
a65151ba 2497 free_irq(adapter->pdev->irq, adapter);
9a799d71 2498 }
207867f5
AD		 2499
2500 /* clear q_vector state information */
2501 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2502}
2503
22d5a71b
JB		 2504/**
2505 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2506 * @adapter: board private structure
2507 **/
2508static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2509{
bd508178
AD		 2510 switch (adapter->hw.mac.type) {
2511 case ixgbe_mac_82598EB:
835462fc 2512 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2513 break;
2514 case ixgbe_mac_82599EB:
b93a2226 2515 case ixgbe_mac_X540:
835462fc
NS		 2516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2517 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2518 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2519 break;
2520 default:
2521 break;
22d5a71b
JB		 2522 }
2523 IXGBE_WRITE_FLUSH(&adapter->hw);
2524 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2525 int i;
2526 for (i = 0; i < adapter->num_msix_vectors; i++)
2527 synchronize_irq(adapter->msix_entries[i].vector);
2528 } else {
2529 synchronize_irq(adapter->pdev->irq);
2530 }
2531}
2532
9a799d71
AK		 2533/**
2534 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2535 *
2536 **/
2537static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2538{
d5bf4f67 2539 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2540
d5bf4f67
ET		 2541 /* rx/tx vector */
2542 if (adapter->rx_itr_setting == 1)
2543 q_vector->itr = IXGBE_20K_ITR;
2544 else
2545 q_vector->itr = adapter->rx_itr_setting;
2546
2547 ixgbe_write_eitr(q_vector);
9a799d71 2548
e8e26350
PW		 2549 ixgbe_set_ivar(adapter, 0, 0, 0);
2550 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2551
396e799c 2552 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2553}
2554
43e69bf0
AD		 2555/**
2556 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2557 * @adapter: board private structure
2558 * @ring: structure containing ring specific data
2559 *
2560 * Configure the Tx descriptor ring after a reset.
2561 **/
84418e3b
AD		 2562void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2563 struct ixgbe_ring *ring)
43e69bf0
AD		 2564{
2565 struct ixgbe_hw *hw = &adapter->hw;
2566 u64 tdba = ring->dma;
2f1860b8 2567 int wait_loop = 10;
b88c6de2 2568 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2569 u8 reg_idx = ring->reg_idx;
43e69bf0 2570
2f1860b8 2571 /* disable queue to avoid issues while updating state */
b88c6de2 2572 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2573 IXGBE_WRITE_FLUSH(hw);
2574
43e69bf0 2575 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2576 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2577 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2578 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2579 ring->count * sizeof(union ixgbe_adv_tx_desc));
2580 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2581 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2582 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2583
b88c6de2
AD		 2584 /*
2585 * set WTHRESH to encourage burst writeback, it should not be set
2586 * higher than 1 when ITR is 0 as it could cause false TX hangs
2587 *
2588 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2589 * to or less than the number of on chip descriptors, which is
2590 * currently 40.
2591 */
2592 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2593 txdctl |= (1 << 16); /* WTHRESH = 1 */
2594 else
2595 txdctl |= (8 << 16); /* WTHRESH = 8 */
2596
2597 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2598 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2599 32; /* PTHRESH = 32 */
2f1860b8
AD		 2600
2601 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2602 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2603 adapter->atr_sample_rate) {
2604 ring->atr_sample_rate = adapter->atr_sample_rate;
2605 ring->atr_count = 0;
2606 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2607 } else {
2608 ring->atr_sample_rate = 0;
2609 }
2f1860b8 2610
c84d324c
JF		 2611 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2612
2f1860b8 2613 /* enable queue */
2f1860b8
AD		 2614 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2615
2616 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2617 if (hw->mac.type == ixgbe_mac_82598EB &&
2618 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2619 return;
2620
2621 /* poll to verify queue is enabled */
2622 do {
032b4325 2623 usleep_range(1000, 2000);
2f1860b8
AD		 2624 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2625 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2626 if (!wait_loop)
2627 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2628}
2629
120ff942
AD		 2630static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2631{
2632 struct ixgbe_hw *hw = &adapter->hw;
2633 u32 rttdcs;
72a32f1f 2634 u32 reg;
8b1c0b24 2635 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2636
2637 if (hw->mac.type == ixgbe_mac_82598EB)
2638 return;
2639
2640 /* disable the arbiter while setting MTQC */
2641 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2642 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2643 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2644
2645 /* set transmit pool layout */
8b1c0b24 2646 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2647 case (IXGBE_FLAG_SRIOV_ENABLED):
2648 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2649 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2650 break;
8b1c0b24
JF		 2651 default:
2652 if (!tcs)
2653 reg = IXGBE_MTQC_64Q_1PB;
2654 else if (tcs <= 4)
2655 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2656 else
2657 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2658
8b1c0b24 2659 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2660
8b1c0b24
JF		 2661 /* Enable Security TX Buffer IFG for multiple pb */
2662 if (tcs) {
2663 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2664 reg |= IXGBE_SECTX_DCB;
2665 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2666 }
120ff942
AD		 2667 break;
2668 }
2669
2670 /* re-enable the arbiter */
2671 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2672 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2673}
2674
9a799d71 2675/**
3a581073 2676 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2677 * @adapter: board private structure
2678 *
2679 * Configure the Tx unit of the MAC after a reset.
2680 **/
2681static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2682{
2f1860b8
AD		 2683 struct ixgbe_hw *hw = &adapter->hw;
2684 u32 dmatxctl;
43e69bf0 2685 u32 i;
9a799d71 2686
2f1860b8
AD		 2687 ixgbe_setup_mtqc(adapter);
2688
2689 if (hw->mac.type != ixgbe_mac_82598EB) {
2690 /* DMATXCTL.EN must be before Tx queues are enabled */
2691 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2692 dmatxctl |= IXGBE_DMATXCTL_TE;
2693 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2694 }
2695
9a799d71 2696 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2697 for (i = 0; i < adapter->num_tx_queues; i++)
2698 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2699}
2700
e8e26350 2701#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2702
a6616b42 2703static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2704 struct ixgbe_ring *rx_ring)
cc41ac7c 2705{
cc41ac7c 2706 u32 srrctl;
bf29ee6c 2707 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2708
bd508178
AD		 2709 switch (adapter->hw.mac.type) {
2710 case ixgbe_mac_82598EB: {
2711 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2712 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2713 reg_idx = reg_idx & mask;
cc41ac7c 2714 }
bd508178
AD		 2715 break;
2716 case ixgbe_mac_82599EB:
b93a2226 2717 case ixgbe_mac_X540:
bd508178
AD		 2718 default:
2719 break;
2720 }
2721
bf29ee6c 2722 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2723
2724 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2725 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2726 if (adapter->num_vfs)
2727 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2728
afafd5b0
AD		 2729 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2730 IXGBE_SRRCTL_BSIZEHDR_MASK;
2731
7d637bcc 2732 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2733#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2734 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2735#else
2736 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2737#endif
cc41ac7c 2738 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2739 } else {
afafd5b0
AD		 2740 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2741 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2742 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2743 }
e8e26350 2744
bf29ee6c 2745 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2746}
9a799d71 2747
05abb126 2748static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2749{
05abb126
AD		 2750 struct ixgbe_hw *hw = &adapter->hw;
2751 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2752 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2753 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2754 u32 mrqc = 0, reta = 0;
2755 u32 rxcsum;
2756 int i, j;
8b1c0b24 2757 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2758 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2759
2760 if (tcs)
2761 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2762
05abb126
AD		 2763 /* Fill out hash function seeds */
2764 for (i = 0; i < 10; i++)
2765 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2766
2767 /* Fill out redirection table */
2768 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2769 if (j == maxq)
05abb126
AD		 2770 j = 0;
2771 /* reta = 4-byte sliding window of
2772 * 0x00..(indices-1)(indices-1)00..etc. */
2773 reta = (reta << 8) | (j * 0x11);
2774 if ((i & 3) == 3)
2775 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2776 }
0cefafad 2777
05abb126
AD		 2778 /* Disable indicating checksum in descriptor, enables RSS hash */
2779 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2780 rxcsum |= IXGBE_RXCSUM_PCSD;
2781 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2782
8b1c0b24
JF		 2783 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2784 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2785 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2786 } else {
2787 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2788 | IXGBE_FLAG_SRIOV_ENABLED);
2789
2790 switch (mask) {
2791 case (IXGBE_FLAG_RSS_ENABLED):
2792 if (!tcs)
2793 mrqc = IXGBE_MRQC_RSSEN;
2794 else if (tcs <= 4)
2795 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2796 else
2797 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2798 break;
2799 case (IXGBE_FLAG_SRIOV_ENABLED):
2800 mrqc = IXGBE_MRQC_VMDQEN;
2801 break;
2802 default:
2803 break;
2804 }
0cefafad
JB		 2805 }
2806
05abb126
AD		 2807 /* Perform hash on these packet types */
2808 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2809 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2810 | IXGBE_MRQC_RSS_FIELD_IPV6
2811 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2812
2813 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2814}
2815
bb5a9ad2
NS		 2816/**
2817 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2818 * @adapter: address of board private structure
2819 * @index: index of ring to set
bb5a9ad2 2820 **/
082757af 2821static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2822 struct ixgbe_ring *ring)
bb5a9ad2 2823{
bb5a9ad2 2824 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2825 u32 rscctrl;
edd2ea55 2826 int rx_buf_len;
bf29ee6c 2827 u8 reg_idx = ring->reg_idx;
7367096a 2828
7d637bcc 2829 if (!ring_is_rsc_enabled(ring))
7367096a 2830 return;
bb5a9ad2 2831
7367096a
AD		 2832 rx_buf_len = ring->rx_buf_len;
2833 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2834 rscctrl |= IXGBE_RSCCTL_RSCEN;
2835 /*
2836 * we must limit the number of descriptors so that the
2837 * total size of max desc * buf_len is not greater
2838 * than 65535
2839 */
7d637bcc 2840 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2841#if (MAX_SKB_FRAGS > 16)
2842 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2843#elif (MAX_SKB_FRAGS > 8)
2844 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2845#elif (MAX_SKB_FRAGS > 4)
2846 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2847#else
2848 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2849#endif
2850 } else {
919e78a6 2851 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2852 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2853 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2854 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2855 else
2856 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2857 }
7367096a 2858 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2859}
2860
9e10e045
AD		 2861/**
2862 * ixgbe_set_uta - Set unicast filter table address
2863 * @adapter: board private structure
2864 *
2865 * The unicast table address is a register array of 32-bit registers.
2866 * The table is meant to be used in a way similar to how the MTA is used
2867 * however due to certain limitations in the hardware it is necessary to
2868 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2869 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2870 **/
2871static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2872{
2873 struct ixgbe_hw *hw = &adapter->hw;
2874 int i;
2875
2876 /* The UTA table only exists on 82599 hardware and newer */
2877 if (hw->mac.type < ixgbe_mac_82599EB)
2878 return;
2879
2880 /* we only need to do this if VMDq is enabled */
2881 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2882 return;
2883
2884 for (i = 0; i < 128; i++)
2885 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2886}
2887
2888#define IXGBE_MAX_RX_DESC_POLL 10
2889static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2890 struct ixgbe_ring *ring)
2891{
2892 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2893 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2894 u32 rxdctl;
bf29ee6c 2895 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2896
2897 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2898 if (hw->mac.type == ixgbe_mac_82598EB &&
2899 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2900 return;
2901
2902 do {
032b4325 2903 usleep_range(1000, 2000);
9e10e045
AD		 2904 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2905 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2906
2907 if (!wait_loop) {
2908 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2909 "the polling period\n", reg_idx);
2910 }
2911}
2912
2d39d576
YZ		 2913void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2914 struct ixgbe_ring *ring)
2915{
2916 struct ixgbe_hw *hw = &adapter->hw;
2917 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2918 u32 rxdctl;
2919 u8 reg_idx = ring->reg_idx;
2920
2921 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2922 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2923
2924 /* write value back with RXDCTL.ENABLE bit cleared */
2925 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2926
2927 if (hw->mac.type == ixgbe_mac_82598EB &&
2928 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2929 return;
2930
2931 /* the hardware may take up to 100us to really disable the rx queue */
2932 do {
2933 udelay(10);
2934 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2935 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2936
2937 if (!wait_loop) {
2938 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2939 "the polling period\n", reg_idx);
2940 }
2941}
2942
84418e3b
AD		 2943void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2944 struct ixgbe_ring *ring)
acd37177
AD		 2945{
2946 struct ixgbe_hw *hw = &adapter->hw;
2947 u64 rdba = ring->dma;
9e10e045 2948 u32 rxdctl;
bf29ee6c 2949 u8 reg_idx = ring->reg_idx;
acd37177 2950
9e10e045
AD		 2951 /* disable queue to avoid issues while updating state */
2952 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2953 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2954
acd37177
AD		 2955 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2956 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2957 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2958 ring->count * sizeof(union ixgbe_adv_rx_desc));
2959 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2960 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2961 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2962
2963 ixgbe_configure_srrctl(adapter, ring);
2964 ixgbe_configure_rscctl(adapter, ring);
2965
e9f98072
GR		 2966 /* If operating in IOV mode set RLPML for X540 */
2967 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2968 hw->mac.type == ixgbe_mac_X540) {
2969 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2970 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2971 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2972 }
2973
9e10e045
AD		 2974 if (hw->mac.type == ixgbe_mac_82598EB) {
2975 /*
2976 * enable cache line friendly hardware writes:
2977 * PTHRESH=32 descriptors (half the internal cache),
2978 * this also removes ugly rx_no_buffer_count increment
2979 * HTHRESH=4 descriptors (to minimize latency on fetch)
2980 * WTHRESH=8 burst writeback up to two cache lines
2981 */
2982 rxdctl &= ~0x3FFFFF;
2983 rxdctl |= 0x080420;
2984 }
2985
2986 /* enable receive descriptor ring */
2987 rxdctl |= IXGBE_RXDCTL_ENABLE;
2988 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2989
2990 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2991 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2992}
2993
48654521
AD		 2994static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2995{
2996 struct ixgbe_hw *hw = &adapter->hw;
2997 int p;
2998
2999 /* PSRTYPE must be initialized in non 82598 adapters */
3000 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3001 IXGBE_PSRTYPE_UDPHDR |
3002 IXGBE_PSRTYPE_IPV4HDR |
48654521 3003 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3004 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3005
3006 if (hw->mac.type == ixgbe_mac_82598EB)
3007 return;
3008
3009 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3010 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3011
3012 for (p = 0; p < adapter->num_rx_pools; p++)
3013 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3014 psrtype);
3015}
3016
f5b4a52e
AD		 3017static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3018{
3019 struct ixgbe_hw *hw = &adapter->hw;
3020 u32 gcr_ext;
3021 u32 vt_reg_bits;
3022 u32 reg_offset, vf_shift;
3023 u32 vmdctl;
de4c7f65 3024 int i;
f5b4a52e
AD		 3025
3026 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3027 return;
3028
3029 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3030 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3031 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3032 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3033
3034 vf_shift = adapter->num_vfs % 32;
3035 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3036
3037 /* Enable only the PF's pool for Tx/Rx */
3038 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3039 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3040 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3041 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3042 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3043
3044 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3045 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3046
3047 /*
3048 * Set up VF register offsets for selected VT Mode,
3049 * i.e. 32 or 64 VFs for SR-IOV
3050 */
3051 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3052 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3053 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3054 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3055
3056 /* enable Tx loopback for VF/PF communication */
3057 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3058 /* Enable MAC Anti-Spoofing */
a1cbb15c 3059 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 3060 (adapter->num_vfs != 0),
a985b6c3 3061 adapter->num_vfs);
de4c7f65
GR		 3062 /* For VFs that have spoof checking turned off */
3063 for (i = 0; i < adapter->num_vfs; i++) {
3064 if (!adapter->vfinfo[i].spoofchk_enabled)
3065 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3066 }
f5b4a52e
AD		 3067}
3068
477de6ed 3069static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3070{
9a799d71
AK		 3071 struct ixgbe_hw *hw = &adapter->hw;
3072 struct net_device *netdev = adapter->netdev;
3073 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3074 int rx_buf_len;
477de6ed
AD		 3075 struct ixgbe_ring *rx_ring;
3076 int i;
3077 u32 mhadd, hlreg0;
48654521 3078
9a799d71 3079 /* Decide whether to use packet split mode or not */
a124339a
DS		 3080 /* On by default */
3081 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3082
1cdd1ec8 3083 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3084 if (adapter->num_vfs)
3085 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3086
3087 /* Disable packet split due to 82599 erratum #45 */
3088 if (hw->mac.type == ixgbe_mac_82599EB)
3089 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 3090
63f39bd1 3091#ifdef IXGBE_FCOE
477de6ed
AD		 3092 /* adjust max frame to be able to do baby jumbo for FCoE */
3093 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3094 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3095 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3096
477de6ed
AD		 3097#endif /* IXGBE_FCOE */
3098 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3099 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3100 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3101 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3102
3103 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3104 }
3105
919e78a6
AD		 3106 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3107 max_frame += VLAN_HLEN;
3108
3109 /* Set the RX buffer length according to the mode */
3110 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3111 rx_buf_len = IXGBE_RX_HDR_SIZE;
3112 } else {
3113 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3114 (netdev->mtu <= ETH_DATA_LEN))
3115 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3116 /*
3117 * Make best use of allocation by using all but 1K of a
3118 * power of 2 allocation that will be used for skb->head.
3119 */
3120 else if (max_frame <= IXGBE_RXBUFFER_3K)
3121 rx_buf_len = IXGBE_RXBUFFER_3K;
3122 else if (max_frame <= IXGBE_RXBUFFER_7K)
3123 rx_buf_len = IXGBE_RXBUFFER_7K;
3124 else if (max_frame <= IXGBE_RXBUFFER_15K)
3125 rx_buf_len = IXGBE_RXBUFFER_15K;
3126 else
3127 rx_buf_len = IXGBE_MAX_RXBUFFER;
3128 }
3129
477de6ed
AD		 3130 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3131 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3132 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3133 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3134
0cefafad
JB		 3135 /*
3136 * Setup the HW Rx Head and Tail Descriptor Pointers and
3137 * the Base and Length of the Rx Descriptor Ring
3138 */
9a799d71 3139 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3140 rx_ring = adapter->rx_ring[i];
a6616b42 3141 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3142
6e455b89 3143 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3144 set_ring_ps_enabled(rx_ring);
3145 else
3146 clear_ring_ps_enabled(rx_ring);
3147
3148 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3149 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3150 else
7d637bcc 3151 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3152
63f39bd1 3153#ifdef IXGBE_FCOE
e8e9f696 3154 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3155 struct ixgbe_ring_feature *f;
3156 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3157 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3158 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3159 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3160 rx_ring->rx_buf_len =
e8e9f696 3161 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3162 } else if (!ring_is_rsc_enabled(rx_ring) &&
3163 !ring_is_ps_enabled(rx_ring)) {
3164 rx_ring->rx_buf_len =
3165 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3166 }
63f39bd1 3167 }
63f39bd1 3168#endif /* IXGBE_FCOE */
477de6ed 3169 }
477de6ed
AD		 3170}
3171
7367096a
AD		 3172static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3173{
3174 struct ixgbe_hw *hw = &adapter->hw;
3175 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3176
3177 switch (hw->mac.type) {
3178 case ixgbe_mac_82598EB:
3179 /*
3180 * For VMDq support of different descriptor types or
3181 * buffer sizes through the use of multiple SRRCTL
3182 * registers, RDRXCTL.MVMEN must be set to 1
3183 *
3184 * also, the manual doesn't mention it clearly but DCA hints
3185 * will only use queue 0's tags unless this bit is set. Side
3186 * effects of setting this bit are only that SRRCTL must be
3187 * fully programmed [0..15]
3188 */
3189 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3190 break;
3191 case ixgbe_mac_82599EB:
b93a2226 3192 case ixgbe_mac_X540:
7367096a
AD		 3193 /* Disable RSC for ACK packets */
3194 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3195 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3196 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3197 /* hardware requires some bits to be set by default */
3198 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3199 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3200 break;
3201 default:
3202 /* We should do nothing since we don't know this hardware */
3203 return;
3204 }
3205
3206 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3207}
3208
477de6ed
AD		 3209/**
3210 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3211 * @adapter: board private structure
3212 *
3213 * Configure the Rx unit of the MAC after a reset.
3214 **/
3215static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3216{
3217 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3218 int i;
3219 u32 rxctrl;
477de6ed
AD		 3220
3221 /* disable receives while setting up the descriptors */
3222 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3223 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3224
3225 ixgbe_setup_psrtype(adapter);
7367096a 3226 ixgbe_setup_rdrxctl(adapter);
477de6ed 3227
9e10e045 3228 /* Program registers for the distribution of queues */
f5b4a52e 3229 ixgbe_setup_mrqc(adapter);
f5b4a52e 3230
9e10e045
AD		 3231 ixgbe_set_uta(adapter);
3232
477de6ed
AD		 3233 /* set_rx_buffer_len must be called before ring initialization */
3234 ixgbe_set_rx_buffer_len(adapter);
3235
3236 /*
3237 * Setup the HW Rx Head and Tail Descriptor Pointers and
3238 * the Base and Length of the Rx Descriptor Ring
3239 */
9e10e045
AD		 3240 for (i = 0; i < adapter->num_rx_queues; i++)
3241 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3242
9e10e045
AD		 3243 /* disable drop enable for 82598 parts */
3244 if (hw->mac.type == ixgbe_mac_82598EB)
3245 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3246
3247 /* enable all receives */
3248 rxctrl |= IXGBE_RXCTRL_RXEN;
3249 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3250}
3251
8e586137 3252static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3253{
3254 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3255 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3256 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3257
3258 /* add VID to filter table */
1ada1b1b 3259 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3260 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3261
3262 return 0;
068c89b0
DS		 3263}
3264
8e586137 3265static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3266{
3267 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3268 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3269 int pool_ndx = adapter->num_vfs;
068c89b0 3270
068c89b0 3271 /* remove VID from filter table */
1ada1b1b 3272 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3273 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3274
3275 return 0;
068c89b0
DS		 3276}
3277
5f6c0181
JB		 3278/**
3279 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3280 * @adapter: driver data
3281 */
3282static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3283{
3284 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3285 u32 vlnctrl;
3286
3287 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3288 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3289 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3290}
3291
3292/**
3293 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3294 * @adapter: driver data
3295 */
3296static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3297{
3298 struct ixgbe_hw *hw = &adapter->hw;
3299 u32 vlnctrl;
3300
3301 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3302 vlnctrl |= IXGBE_VLNCTRL_VFE;
3303 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3304 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3305}
3306
3307/**
3308 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3309 * @adapter: driver data
3310 */
3311static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3312{
3313 struct ixgbe_hw *hw = &adapter->hw;
3314 u32 vlnctrl;
5f6c0181
JB		 3315 int i, j;
3316
3317 switch (hw->mac.type) {
3318 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3319 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3320 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3321 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3322 break;
3323 case ixgbe_mac_82599EB:
b93a2226 3324 case ixgbe_mac_X540:
5f6c0181
JB		 3325 for (i = 0; i < adapter->num_rx_queues; i++) {
3326 j = adapter->rx_ring[i]->reg_idx;
3327 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3328 vlnctrl &= ~IXGBE_RXDCTL_VME;
3329 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3330 }
3331 break;
3332 default:
3333 break;
3334 }
3335}
3336
3337/**
f62bbb5e 3338 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3339 * @adapter: driver data
3340 */
f62bbb5e 3341static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3342{
3343 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3344 u32 vlnctrl;
5f6c0181
JB		 3345 int i, j;
3346
3347 switch (hw->mac.type) {
3348 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3349 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3350 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3351 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3352 break;
3353 case ixgbe_mac_82599EB:
b93a2226 3354 case ixgbe_mac_X540:
5f6c0181
JB		 3355 for (i = 0; i < adapter->num_rx_queues; i++) {
3356 j = adapter->rx_ring[i]->reg_idx;
3357 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3358 vlnctrl |= IXGBE_RXDCTL_VME;
3359 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3360 }
3361 break;
3362 default:
3363 break;
3364 }
3365}
3366
9a799d71
AK		 3367static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3368{
f62bbb5e 3369 u16 vid;
9a799d71 3370
f62bbb5e
JG		 3371 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3372
3373 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3374 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3375}
3376
2850062a
AD		 3377/**
3378 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3379 * @netdev: network interface device structure
3380 *
3381 * Writes unicast address list to the RAR table.
3382 * Returns: -ENOMEM on failure/insufficient address space
3383 * 0 on no addresses written
3384 * X on writing X addresses to the RAR table
3385 **/
3386static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3387{
3388 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3389 struct ixgbe_hw *hw = &adapter->hw;
3390 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3391 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3392 int count = 0;
3393
3394 /* return ENOMEM indicating insufficient memory for addresses */
3395 if (netdev_uc_count(netdev) > rar_entries)
3396 return -ENOMEM;
3397
3398 if (!netdev_uc_empty(netdev) && rar_entries) {
3399 struct netdev_hw_addr *ha;
3400 /* return error if we do not support writing to RAR table */
3401 if (!hw->mac.ops.set_rar)
3402 return -ENOMEM;
3403
3404 netdev_for_each_uc_addr(ha, netdev) {
3405 if (!rar_entries)
3406 break;
3407 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3408 vfn, IXGBE_RAH_AV);
3409 count++;
3410 }
3411 }
3412 /* write the addresses in reverse order to avoid write combining */
3413 for (; rar_entries > 0 ; rar_entries--)
3414 hw->mac.ops.clear_rar(hw, rar_entries);
3415
3416 return count;
3417}
3418
9a799d71 3419/**
2c5645cf 3420 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3421 * @netdev: network interface device structure
3422 *
2c5645cf
CL		 3423 * The set_rx_method entry point is called whenever the unicast/multicast
3424 * address list or the network interface flags are updated. This routine is
3425 * responsible for configuring the hardware for proper unicast, multicast and
3426 * promiscuous mode.
9a799d71 3427 **/
7f870475 3428void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3429{
3430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3431 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3432 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3433 int count;
9a799d71
AK		 3434
3435 /* Check for Promiscuous and All Multicast modes */
3436
3437 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3438
f5dc442b
AD		 3439 /* set all bits that we expect to always be set */
3440 fctrl |= IXGBE_FCTRL_BAM;
3441 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3442 fctrl |= IXGBE_FCTRL_PMCF;
3443
2850062a
AD		 3444 /* clear the bits we are changing the status of */
3445 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3446
9a799d71 3447 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3448 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3449 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3450 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3451 /* don't hardware filter vlans in promisc mode */
3452 ixgbe_vlan_filter_disable(adapter);
9a799d71 3453 } else {
746b9f02
PM		 3454 if (netdev->flags & IFF_ALLMULTI) {
3455 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3456 vmolr |= IXGBE_VMOLR_MPE;
3457 } else {
3458 /*
3459 * Write addresses to the MTA, if the attempt fails
25985edc 3460 * then we should just turn on promiscuous mode so
2850062a
AD		 3461 * that we can at least receive multicast traffic
3462 */
3463 hw->mac.ops.update_mc_addr_list(hw, netdev);
3464 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3465 }
5f6c0181 3466 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3467 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3468 /*
3469 * Write addresses to available RAR registers, if there is not
3470 * sufficient space to store all the addresses then enable
25985edc 3471 * unicast promiscuous mode
2850062a
AD		 3472 */
3473 count = ixgbe_write_uc_addr_list(netdev);
3474 if (count < 0) {
3475 fctrl |= IXGBE_FCTRL_UPE;
3476 vmolr |= IXGBE_VMOLR_ROPE;
3477 }
9a799d71
AK		 3478 }
3479
2850062a 3480 if (adapter->num_vfs) {
1cdd1ec8 3481 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3482 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3483 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3484 IXGBE_VMOLR_ROPE);
3485 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3486 }
3487
3488 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3489
3490 if (netdev->features & NETIF_F_HW_VLAN_RX)
3491 ixgbe_vlan_strip_enable(adapter);
3492 else
3493 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3494}
3495
021230d4
AV		 3496static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3497{
3498 int q_idx;
3499 struct ixgbe_q_vector *q_vector;
3500 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3501
3502 /* legacy and MSI only use one vector */
3503 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3504 q_vectors = 1;
3505
3506 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3507 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3508 napi_enable(&q_vector->napi);
021230d4
AV		 3509 }
3510}
3511
3512static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3513{
3514 int q_idx;
3515 struct ixgbe_q_vector *q_vector;
3516 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3517
3518 /* legacy and MSI only use one vector */
3519 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3520 q_vectors = 1;
3521
3522 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3523 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3524 napi_disable(&q_vector->napi);
3525 }
3526}
3527
7a6b6f51 3528#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3529/*
3530 * ixgbe_configure_dcb - Configure DCB hardware
3531 * @adapter: ixgbe adapter struct
3532 *
3533 * This is called by the driver on open to configure the DCB hardware.
3534 * This is also called by the gennetlink interface when reconfiguring
3535 * the DCB state.
3536 */
3537static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3538{
3539 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3540 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3541
67ebd791
AD		 3542 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3543 if (hw->mac.type == ixgbe_mac_82598EB)
3544 netif_set_gso_max_size(adapter->netdev, 65536);
3545 return;
3546 }
3547
3548 if (hw->mac.type == ixgbe_mac_82598EB)
3549 netif_set_gso_max_size(adapter->netdev, 32768);
3550
2f90b865 3551
2f90b865 3552 /* Enable VLAN tag insert/strip */
f62bbb5e 3553 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3554
2f90b865 3555 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3556
971060b1 3557#ifdef IXGBE_FCOE
b120818e
JF		 3558 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3559 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3560#endif
b120818e
JF		 3561
3562 /* reconfigure the hardware */
3563 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3564 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3565 DCB_TX_CONFIG);
3566 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3567 DCB_RX_CONFIG);
3568 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3569 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3570 ixgbe_dcb_hw_ets(&adapter->hw,
3571 adapter->ixgbe_ieee_ets,
3572 max_frame);
3573 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3574 adapter->ixgbe_ieee_pfc->pfc_en,
3575 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3576 }
8187cd48
JF		 3577
3578 /* Enable RSS Hash per TC */
3579 if (hw->mac.type != ixgbe_mac_82598EB) {
3580 int i;
3581 u32 reg = 0;
3582
3583 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3584 u8 msb = 0;
3585 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3586
3587 while (cnt >>= 1)
3588 msb++;
3589
3590 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3591 }
3592 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3593 }
2f90b865 3594}
9da712d2
JF		 3595#endif
3596
3597/* Additional bittime to account for IXGBE framing */
3598#define IXGBE_ETH_FRAMING 20
3599
3600/*
3601 * ixgbe_hpbthresh - calculate high water mark for flow control
3602 *
3603 * @adapter: board private structure to calculate for
3604 * @pb - packet buffer to calculate
3605 */
3606static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3607{
3608 struct ixgbe_hw *hw = &adapter->hw;
3609 struct net_device *dev = adapter->netdev;
3610 int link, tc, kb, marker;
3611 u32 dv_id, rx_pba;
3612
3613 /* Calculate max LAN frame size */
3614 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3615
3616#ifdef IXGBE_FCOE
3617 /* FCoE traffic class uses FCOE jumbo frames */
3618 if (dev->features & NETIF_F_FCOE_MTU) {
3619 int fcoe_pb = 0;
2f90b865 3620
9da712d2
JF		 3621#ifdef CONFIG_IXGBE_DCB
3622 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3623
3624#endif
3625 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3626 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3627 }
2f90b865 3628#endif
80605c65 3629
9da712d2
JF		 3630 /* Calculate delay value for device */
3631 switch (hw->mac.type) {
3632 case ixgbe_mac_X540:
3633 dv_id = IXGBE_DV_X540(link, tc);
3634 break;
3635 default:
3636 dv_id = IXGBE_DV(link, tc);
3637 break;
3638 }
3639
3640 /* Loopback switch introduces additional latency */
3641 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3642 dv_id += IXGBE_B2BT(tc);
3643
3644 /* Delay value is calculated in bit times convert to KB */
3645 kb = IXGBE_BT2KB(dv_id);
3646 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3647
3648 marker = rx_pba - kb;
3649
3650 /* It is possible that the packet buffer is not large enough
3651 * to provide required headroom. In this case throw an error
3652 * to user and a do the best we can.
3653 */
3654 if (marker < 0) {
3655 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3656 "headroom to support flow control."
3657 "Decrease MTU or number of traffic classes\n", pb);
3658 marker = tc + 1;
3659 }
3660
3661 return marker;
3662}
3663
3664/*
3665 * ixgbe_lpbthresh - calculate low water mark for for flow control
3666 *
3667 * @adapter: board private structure to calculate for
3668 * @pb - packet buffer to calculate
3669 */
3670static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3671{
3672 struct ixgbe_hw *hw = &adapter->hw;
3673 struct net_device *dev = adapter->netdev;
3674 int tc;
3675 u32 dv_id;
3676
3677 /* Calculate max LAN frame size */
3678 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3679
3680 /* Calculate delay value for device */
3681 switch (hw->mac.type) {
3682 case ixgbe_mac_X540:
3683 dv_id = IXGBE_LOW_DV_X540(tc);
3684 break;
3685 default:
3686 dv_id = IXGBE_LOW_DV(tc);
3687 break;
3688 }
3689
3690 /* Delay value is calculated in bit times convert to KB */
3691 return IXGBE_BT2KB(dv_id);
3692}
3693
3694/*
3695 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3696 */
3697static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3698{
3699 struct ixgbe_hw *hw = &adapter->hw;
3700 int num_tc = netdev_get_num_tc(adapter->netdev);
3701 int i;
3702
3703 if (!num_tc)
3704 num_tc = 1;
3705
3706 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3707
3708 for (i = 0; i < num_tc; i++) {
3709 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3710
3711 /* Low water marks must not be larger than high water marks */
3712 if (hw->fc.low_water > hw->fc.high_water[i])
3713 hw->fc.low_water = 0;
3714 }
3715}
3716
80605c65
JF		 3717static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3718{
80605c65 3719 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3720 int hdrm;
3721 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3722
3723 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3724 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3725 hdrm = 32 << adapter->fdir_pballoc;
3726 else
3727 hdrm = 0;
80605c65 3728
f7e1027f 3729 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3730 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3731}
3732
e4911d57
AD		 3733static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3734{
3735 struct ixgbe_hw *hw = &adapter->hw;
3736 struct hlist_node *node, *node2;
3737 struct ixgbe_fdir_filter *filter;
3738
3739 spin_lock(&adapter->fdir_perfect_lock);
3740
3741 if (!hlist_empty(&adapter->fdir_filter_list))
3742 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3743
3744 hlist_for_each_entry_safe(filter, node, node2,
3745 &adapter->fdir_filter_list, fdir_node) {
3746 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3747 &filter->filter,
3748 filter->sw_idx,
3749 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3750 IXGBE_FDIR_DROP_QUEUE :
3751 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3752 }
3753
3754 spin_unlock(&adapter->fdir_perfect_lock);
3755}
3756
9a799d71
AK		 3757static void ixgbe_configure(struct ixgbe_adapter *adapter)
3758{
80605c65 3759 ixgbe_configure_pb(adapter);
7a6b6f51 3760#ifdef CONFIG_IXGBE_DCB
67ebd791 3761 ixgbe_configure_dcb(adapter);
2f90b865 3762#endif
9a799d71 3763
4c1d7b4b 3764 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3765 ixgbe_restore_vlan(adapter);
3766
eacd73f7
YZ		 3767#ifdef IXGBE_FCOE
3768 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3769 ixgbe_configure_fcoe(adapter);
3770
3771#endif /* IXGBE_FCOE */
c4cf55e5 3772 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3773 ixgbe_init_fdir_signature_82599(&adapter->hw,
3774 adapter->fdir_pballoc);
e4911d57
AD		 3775 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3776 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3777 adapter->fdir_pballoc);
3778 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3779 }
4c1d7b4b 3780
933d41f1 3781 ixgbe_configure_virtualization(adapter);
c4cf55e5 3782
9a799d71
AK		 3783 ixgbe_configure_tx(adapter);
3784 ixgbe_configure_rx(adapter);
9a799d71
AK		 3785}
3786
e8e26350
PW		 3787static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3788{
3789 switch (hw->phy.type) {
3790 case ixgbe_phy_sfp_avago:
3791 case ixgbe_phy_sfp_ftl:
3792 case ixgbe_phy_sfp_intel:
3793 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3794 case ixgbe_phy_sfp_passive_tyco:
3795 case ixgbe_phy_sfp_passive_unknown:
3796 case ixgbe_phy_sfp_active_unknown:
3797 case ixgbe_phy_sfp_ftl_active:
e8e26350 3798 return true;
8917b447
AD		 3799 case ixgbe_phy_nl:
3800 if (hw->mac.type == ixgbe_mac_82598EB)
3801 return true;
e8e26350
PW		 3802 default:
3803 return false;
3804 }
3805}
3806
0ecc061d 3807/**
e8e26350
PW		 3808 * ixgbe_sfp_link_config - set up SFP+ link
3809 * @adapter: pointer to private adapter struct
3810 **/
3811static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3812{
7086400d 3813 /*
52f33af8 3814 * We are assuming the worst case scenario here, and that
7086400d
AD		 3815 * is that an SFP was inserted/removed after the reset
3816 * but before SFP detection was enabled. As such the best
3817 * solution is to just start searching as soon as we start
3818 */
3819 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3820 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3821
7086400d 3822 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3823}
3824
3825/**
3826 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3827 * @hw: pointer to private hardware struct
3828 *
3829 * Returns 0 on success, negative on failure
3830 **/
e8e26350 3831static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3832{
3833 u32 autoneg;
8620a103 3834 bool negotiation, link_up = false;
0ecc061d
PWJ		 3835 u32 ret = IXGBE_ERR_LINK_SETUP;
3836
3837 if (hw->mac.ops.check_link)
3838 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3839
3840 if (ret)
3841 goto link_cfg_out;
3842
0b0c2b31
ET		 3843 autoneg = hw->phy.autoneg_advertised;
3844 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3845 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3846 &negotiation);
0ecc061d
PWJ		 3847 if (ret)
3848 goto link_cfg_out;
3849
8620a103
MC		 3850 if (hw->mac.ops.setup_link)
3851 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3852link_cfg_out:
3853 return ret;
3854}
3855
a34bcfff 3856static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3857{
9a799d71 3858 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3859 u32 gpie = 0;
9a799d71 3860
9b471446 3861 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3862 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3863 IXGBE_GPIE_OCD;
3864 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3865 /*
3866 * use EIAM to auto-mask when MSI-X interrupt is asserted
3867 * this saves a register write for every interrupt
3868 */
3869 switch (hw->mac.type) {
3870 case ixgbe_mac_82598EB:
3871 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3872 break;
9b471446 3873 case ixgbe_mac_82599EB:
b93a2226
DS		 3874 case ixgbe_mac_X540:
3875 default:
9b471446
JB		 3876 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3877 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3878 break;
3879 }
3880 } else {
021230d4
AV		 3881 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3882 * specifically only auto mask tx and rx interrupts */
3883 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3884 }
9a799d71 3885
a34bcfff
AD		 3886 /* XXX: to interrupt immediately for EICS writes, enable this */
3887 /* gpie |= IXGBE_GPIE_EIMEN; */
3888
3889 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3890 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3891 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3892 }
3893
5fdd31f9 3894 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3895 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3896 switch (adapter->hw.mac.type) {
3897 case ixgbe_mac_82599EB:
3898 gpie |= IXGBE_SDP0_GPIEN;
3899 break;
3900 case ixgbe_mac_X540:
3901 gpie |= IXGBE_EIMS_TS;
3902 break;
3903 default:
3904 break;
3905 }
3906 }
5fdd31f9 3907
a34bcfff
AD		 3908 /* Enable fan failure interrupt */
3909 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3910 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3911
2698b208 3912 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3913 gpie |= IXGBE_SDP1_GPIEN;
3914 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3915 }
a34bcfff
AD		 3916
3917 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3918}
3919
c7ccde0f 3920static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3921{
3922 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3923 int err;
a34bcfff
AD		 3924 u32 ctrl_ext;
3925
3926 ixgbe_get_hw_control(adapter);
3927 ixgbe_setup_gpie(adapter);
e8e26350 3928
9a799d71
AK		 3929 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3930 ixgbe_configure_msix(adapter);
3931 else
3932 ixgbe_configure_msi_and_legacy(adapter);
3933
c6ecf39a
DS		 3934 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3935 if (hw->mac.ops.enable_tx_laser &&
3936 ((hw->phy.multispeed_fiber) ||
9f911707 3937 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3938 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3939 hw->mac.ops.enable_tx_laser(hw);
3940
9a799d71 3941 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3942 ixgbe_napi_enable_all(adapter);
3943
73c4b7cd
AD		 3944 if (ixgbe_is_sfp(hw)) {
3945 ixgbe_sfp_link_config(adapter);
3946 } else {
3947 err = ixgbe_non_sfp_link_config(hw);
3948 if (err)
3949 e_err(probe, "link_config FAILED %d\n", err);
3950 }
3951
021230d4
AV		 3952 /* clear any pending interrupts, may auto mask */
3953 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3954 ixgbe_irq_enable(adapter, true, true);
9a799d71 3955
bf069c97
DS		 3956 /*
3957 * If this adapter has a fan, check to see if we had a failure
3958 * before we enabled the interrupt.
3959 */
3960 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3961 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3962 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3963 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3964 }
3965
1da100bb 3966 /* enable transmits */
477de6ed 3967 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3968
9a799d71
AK		 3969 /* bring the link up in the watchdog, this could race with our first
3970 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3971 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3972 adapter->link_check_timeout = jiffies;
7086400d 3973 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3974
3975 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3976 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3977 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3978 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3979}
3980
d4f80882
AV		 3981void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3982{
3983 WARN_ON(in_interrupt());
7086400d
AD		 3984 /* put off any impending NetWatchDogTimeout */
3985 adapter->netdev->trans_start = jiffies;
3986
d4f80882 3987 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3988 usleep_range(1000, 2000);
d4f80882 3989 ixgbe_down(adapter);
5809a1ae
GR		 3990 /*
3991 * If SR-IOV enabled then wait a bit before bringing the adapter
3992 * back up to give the VFs time to respond to the reset. The
3993 * two second wait is based upon the watchdog timer cycle in
3994 * the VF driver.
3995 */
3996 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3997 msleep(2000);
d4f80882
AV		 3998 ixgbe_up(adapter);
3999 clear_bit(__IXGBE_RESETTING, &adapter->state);
4000}
4001
c7ccde0f 4002void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4003{
4004 /* hardware has been reset, we need to reload some things */
4005 ixgbe_configure(adapter);
4006
c7ccde0f 4007 ixgbe_up_complete(adapter);
9a799d71
AK		 4008}
4009
4010void ixgbe_reset(struct ixgbe_adapter *adapter)
4011{
c44ade9e 4012 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4013 int err;
4014
7086400d
AD		 4015 /* lock SFP init bit to prevent race conditions with the watchdog */
4016 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4017 usleep_range(1000, 2000);
4018
4019 /* clear all SFP and link config related flags while holding SFP_INIT */
4020 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4021 IXGBE_FLAG2_SFP_NEEDS_RESET);
4022 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4023
8ca783ab 4024 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4025 switch (err) {
4026 case 0:
4027 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4028 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4029 break;
4030 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4031 e_dev_err("master disable timed out\n");
da4dd0f7 4032 break;
794caeb2
PWJ		 4033 case IXGBE_ERR_EEPROM_VERSION:
4034 /* We are running on a pre-production device, log a warning */
849c4542 4035 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4036 "Please be aware there may be issues associated with "
849c4542
ET		 4037 "your hardware. If you are experiencing problems "
4038 "please contact your Intel or hardware "
4039 "representative who provided you with this "
4040 "hardware.\n");
794caeb2 4041 break;
da4dd0f7 4042 default:
849c4542 4043 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4044 }
9a799d71 4045
7086400d
AD		 4046 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4047
9a799d71 4048 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4049 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4050 IXGBE_RAH_AV);
9a799d71
AK		 4051}
4052
9a799d71
AK		 4053/**
4054 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4055 * @rx_ring: ring to free buffers from
4056 **/
b6ec895e 4057static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4058{
b6ec895e 4059 struct device *dev = rx_ring->dev;
9a799d71 4060 unsigned long size;
b6ec895e 4061 u16 i;
9a799d71 4062
84418e3b
AD		 4063 /* ring already cleared, nothing to do */
4064 if (!rx_ring->rx_buffer_info)
4065 return;
9a799d71 4066
84418e3b 4067 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4068 for (i = 0; i < rx_ring->count; i++) {
4069 struct ixgbe_rx_buffer *rx_buffer_info;
4070
4071 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4072 if (rx_buffer_info->dma) {
b6ec895e 4073 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4074 rx_ring->rx_buf_len,
1b507730 4075 DMA_FROM_DEVICE);
9a799d71
AK		 4076 rx_buffer_info->dma = 0;
4077 }
4078 if (rx_buffer_info->skb) {
f8212f97 4079 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4080 rx_buffer_info->skb = NULL;
4c1975d7
AD		 4081 /* We need to clean up RSC frag lists */
4082 skb = ixgbe_merge_active_tail(skb);
4083 ixgbe_close_active_frag_list(skb);
4084 if (IXGBE_CB(skb)->delay_unmap) {
4085 dma_unmap_single(dev,
4086 IXGBE_CB(skb)->dma,
4087 rx_ring->rx_buf_len,
4088 DMA_FROM_DEVICE);
4089 IXGBE_CB(skb)->dma = 0;
4090 IXGBE_CB(skb)->delay_unmap = false;
4091 }
4092 dev_kfree_skb(skb);
9a799d71
AK		 4093 }
4094 if (!rx_buffer_info->page)
4095 continue;
4f57ca6e 4096 if (rx_buffer_info->page_dma) {
b6ec895e 4097 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4098 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4099 rx_buffer_info->page_dma = 0;
4100 }
9a799d71
AK		 4101 put_page(rx_buffer_info->page);
4102 rx_buffer_info->page = NULL;
762f4c57 4103 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4104 }
4105
4106 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4107 memset(rx_ring->rx_buffer_info, 0, size);
4108
4109 /* Zero out the descriptor ring */
4110 memset(rx_ring->desc, 0, rx_ring->size);
4111
4112 rx_ring->next_to_clean = 0;
4113 rx_ring->next_to_use = 0;
9a799d71
AK		 4114}
4115
4116/**
4117 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4118 * @tx_ring: ring to be cleaned
4119 **/
b6ec895e 4120static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4121{
4122 struct ixgbe_tx_buffer *tx_buffer_info;
4123 unsigned long size;
b6ec895e 4124 u16 i;
9a799d71 4125
84418e3b
AD		 4126 /* ring already cleared, nothing to do */
4127 if (!tx_ring->tx_buffer_info)
4128 return;
9a799d71 4129
84418e3b 4130 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4131 for (i = 0; i < tx_ring->count; i++) {
4132 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4133 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4134 }
4135
4136 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4137 memset(tx_ring->tx_buffer_info, 0, size);
4138
4139 /* Zero out the descriptor ring */
4140 memset(tx_ring->desc, 0, tx_ring->size);
4141
4142 tx_ring->next_to_use = 0;
4143 tx_ring->next_to_clean = 0;
9a799d71
AK		 4144}
4145
4146/**
021230d4 4147 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4148 * @adapter: board private structure
4149 **/
021230d4 4150static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4151{
4152 int i;
4153
021230d4 4154 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4155 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4156}
4157
4158/**
021230d4 4159 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4160 * @adapter: board private structure
4161 **/
021230d4 4162static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4163{
4164 int i;
4165
021230d4 4166 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4167 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4168}
4169
e4911d57
AD		 4170static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4171{
4172 struct hlist_node *node, *node2;
4173 struct ixgbe_fdir_filter *filter;
4174
4175 spin_lock(&adapter->fdir_perfect_lock);
4176
4177 hlist_for_each_entry_safe(filter, node, node2,
4178 &adapter->fdir_filter_list, fdir_node) {
4179 hlist_del(&filter->fdir_node);
4180 kfree(filter);
4181 }
4182 adapter->fdir_filter_count = 0;
4183
4184 spin_unlock(&adapter->fdir_perfect_lock);
4185}
4186
9a799d71
AK		 4187void ixgbe_down(struct ixgbe_adapter *adapter)
4188{
4189 struct net_device *netdev = adapter->netdev;
7f821875 4190 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4191 u32 rxctrl;
bf29ee6c 4192 int i;
9a799d71
AK		 4193
4194 /* signal that we are down to the interrupt handler */
4195 set_bit(__IXGBE_DOWN, &adapter->state);
4196
4197 /* disable receives */
7f821875
JB		 4198 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4199 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4200
2d39d576
YZ		 4201 /* disable all enabled rx queues */
4202 for (i = 0; i < adapter->num_rx_queues; i++)
4203 /* this call also flushes the previous write */
4204 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4205
032b4325 4206 usleep_range(10000, 20000);
9a799d71 4207
7f821875
JB		 4208 netif_tx_stop_all_queues(netdev);
4209
7086400d 4210 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4211 netif_carrier_off(netdev);
4212 netif_tx_disable(netdev);
4213
4214 ixgbe_irq_disable(adapter);
4215
4216 ixgbe_napi_disable_all(adapter);
4217
d034acf1
AD		 4218 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4219 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4220 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4221
4222 del_timer_sync(&adapter->service_timer);
4223
34cecbbf 4224 if (adapter->num_vfs) {
8e34d1aa
AD		 4225 /* Clear EITR Select mapping */
4226 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4227
4228 /* Mark all the VFs as inactive */
4229 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4230 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4231
34cecbbf
AD		 4232 /* ping all the active vfs to let them know we are going down */
4233 ixgbe_ping_all_vfs(adapter);
4234
4235 /* Disable all VFTE/VFRE TX/RX */
4236 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4237 }
4238
7f821875
JB		 4239 /* disable transmits in the hardware now that interrupts are off */
4240 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4241 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4242 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4243 }
34cecbbf
AD		 4244
4245 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4246 switch (hw->mac.type) {
4247 case ixgbe_mac_82599EB:
b93a2226 4248 case ixgbe_mac_X540:
88512539 4249 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4250 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4251 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4252 break;
4253 default:
4254 break;
4255 }
7f821875 4256
6f4a0e45
PL		 4257 if (!pci_channel_offline(adapter->pdev))
4258 ixgbe_reset(adapter);
c6ecf39a
DS		 4259
4260 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4261 if (hw->mac.ops.disable_tx_laser &&
4262 ((hw->phy.multispeed_fiber) ||
9f911707 4263 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4264 (hw->mac.type == ixgbe_mac_82599EB))))
4265 hw->mac.ops.disable_tx_laser(hw);
4266
9a799d71
AK		 4267 ixgbe_clean_all_tx_rings(adapter);
4268 ixgbe_clean_all_rx_rings(adapter);
4269
5dd2d332 4270#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4271 /* since we reset the hardware DCA settings were cleared */
e35ec126 4272 ixgbe_setup_dca(adapter);
96b0e0f6 4273#endif
9a799d71
AK		 4274}
4275
9a799d71 4276/**
021230d4
AV		 4277 * ixgbe_poll - NAPI Rx polling callback
4278 * @napi: structure for representing this polling device
4279 * @budget: how many packets driver is allowed to clean
4280 *
4281 * This function is used for legacy and MSI, NAPI mode
9a799d71 4282 **/
021230d4 4283static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4284{
9a1a69ad 4285 struct ixgbe_q_vector *q_vector =
e8e9f696 4286 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4287 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4288 struct ixgbe_ring *ring;
4289 int per_ring_budget;
4290 bool clean_complete = true;
9a799d71 4291
5dd2d332 4292#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4293 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4294 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4295#endif
4296
4ff7fb12
AD		 4297 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4298 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4299
4ff7fb12
AD		 4300 /* attempt to distribute budget to each queue fairly, but don't allow
4301 * the budget to go below 1 because we'll exit polling */
4302 if (q_vector->rx.count > 1)
4303 per_ring_budget = max(budget/q_vector->rx.count, 1);
4304 else
4305 per_ring_budget = budget;
d2c7ddd6 4306
4ff7fb12
AD		 4307 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4308 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4309 per_ring_budget);
4310
4311 /* If all work not completed, return budget and keep polling */
4312 if (!clean_complete)
4313 return budget;
4314
4315 /* all work done, exit the polling mode */
4316 napi_complete(napi);
4317 if (adapter->rx_itr_setting & 1)
4318 ixgbe_set_itr(q_vector);
4319 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4320 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4321
4322 return 0;
9a799d71
AK		 4323}
4324
4325/**
4326 * ixgbe_tx_timeout - Respond to a Tx Hang
4327 * @netdev: network interface device structure
4328 **/
4329static void ixgbe_tx_timeout(struct net_device *netdev)
4330{
4331 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4332
4333 /* Do the reset outside of interrupt context */
c83c6cbd 4334 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4335}
4336
4df10466
JB		 4337/**
4338 * ixgbe_set_rss_queues: Allocate queues for RSS
4339 * @adapter: board private structure to initialize
4340 *
4341 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4342 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4343 *
4344 **/
bc97114d
PWJ		 4345static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4346{
4347 bool ret = false;
0cefafad 4348 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4349
4350 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4351 f->mask = 0xF;
4352 adapter->num_rx_queues = f->indices;
4353 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4354 ret = true;
4355 } else {
bc97114d 4356 ret = false;
b9804972
JB		 4357 }
4358
bc97114d
PWJ		 4359 return ret;
4360}
4361
c4cf55e5
PWJ		 4362/**
4363 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4364 * @adapter: board private structure to initialize
4365 *
4366 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4367 * to the original CPU that initiated the Tx session. This runs in addition
4368 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4369 * Rx load across CPUs using RSS.
4370 *
4371 **/
e8e9f696 4372static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4373{
4374 bool ret = false;
4375 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4376
4377 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4378 f_fdir->mask = 0;
4379
4380 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4381 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4382 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4383 adapter->num_tx_queues = f_fdir->indices;
4384 adapter->num_rx_queues = f_fdir->indices;
4385 ret = true;
4386 } else {
4387 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4388 }
4389 return ret;
4390}
4391
0331a832
YZ		 4392#ifdef IXGBE_FCOE
4393/**
4394 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4395 * @adapter: board private structure to initialize
4396 *
4397 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4398 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4399 * rx queues out of the max number of rx queues, instead, it is used as the
4400 * index of the first rx queue used by FCoE.
4401 *
4402 **/
4403static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4404{
0331a832
YZ		 4405 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4406
e5b64635
JF		 4407 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4408 return false;
4409
e901acd6 4410 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4411
e901acd6
JF		 4412 adapter->num_rx_queues = 1;
4413 adapter->num_tx_queues = 1;
e5b64635 4414
e901acd6
JF		 4415 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4416 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4417 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4418 ixgbe_set_fdir_queues(adapter);
4419 else
4420 ixgbe_set_rss_queues(adapter);
e5b64635 4421 }
03ecf91a 4422
e901acd6
JF		 4423 /* adding FCoE rx rings to the end */
4424 f->mask = adapter->num_rx_queues;
4425 adapter->num_rx_queues += f->indices;
4426 adapter->num_tx_queues += f->indices;
0331a832 4427
e5b64635
JF		 4428 return true;
4429}
4430#endif /* IXGBE_FCOE */
4431
e901acd6
JF		 4432/* Artificial max queue cap per traffic class in DCB mode */
4433#define DCB_QUEUE_CAP 8
4434
e5b64635
JF		 4435#ifdef CONFIG_IXGBE_DCB
4436static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4437{
e901acd6
JF		 4438 int per_tc_q, q, i, offset = 0;
4439 struct net_device *dev = adapter->netdev;
4440 int tcs = netdev_get_num_tc(dev);
e5b64635 4441
e901acd6
JF		 4442 if (!tcs)
4443 return false;
e5b64635 4444
e901acd6
JF		 4445 /* Map queue offset and counts onto allocated tx queues */
4446 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4447 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4448
8b1c0b24 4449 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4450 netdev_set_tc_queue(dev, i, q, offset);
4451 offset += q;
0331a832
YZ		 4452 }
4453
e901acd6
JF		 4454 adapter->num_tx_queues = q * tcs;
4455 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4456
4457#ifdef IXGBE_FCOE
e901acd6
JF		 4458 /* FCoE enabled queues require special configuration indexed
4459 * by feature specific indices and mask. Here we map FCoE
4460 * indices onto the DCB queue pairs allowing FCoE to own
4461 * configuration later.
e5b64635 4462 */
e901acd6
JF		 4463 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4464 int tc;
4465 struct ixgbe_ring_feature *f =
4466 &adapter->ring_feature[RING_F_FCOE];
4467
4468 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4469 f->indices = dev->tc_to_txq[tc].count;
4470 f->mask = dev->tc_to_txq[tc].offset;
4471 }
e5b64635
JF		 4472#endif
4473
e901acd6 4474 return true;
0331a832 4475}
e5b64635 4476#endif
0331a832 4477
1cdd1ec8
GR		 4478/**
4479 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4480 * @adapter: board private structure to initialize
4481 *
4482 * IOV doesn't actually use anything, so just NAK the
4483 * request for now and let the other queue routines
4484 * figure out what to do.
4485 */
4486static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4487{
4488 return false;
4489}
4490
4df10466 4491/*
25985edc 4492 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4493 * @adapter: board private structure to initialize
4494 *
4495 * This is the top level queue allocation routine. The order here is very
4496 * important, starting with the "most" number of features turned on at once,
4497 * and ending with the smallest set of features. This way large combinations
4498 * can be allocated if they're turned on, and smaller combinations are the
4499 * fallthrough conditions.
4500 *
4501 **/
847f53ff 4502static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4503{
1cdd1ec8
GR		 4504 /* Start with base case */
4505 adapter->num_rx_queues = 1;
4506 adapter->num_tx_queues = 1;
4507 adapter->num_rx_pools = adapter->num_rx_queues;
4508 adapter->num_rx_queues_per_pool = 1;
4509
4510 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4511 goto done;
1cdd1ec8 4512
bc97114d
PWJ		 4513#ifdef CONFIG_IXGBE_DCB
4514 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4515 goto done;
bc97114d
PWJ		 4516
4517#endif
e5b64635
JF		 4518#ifdef IXGBE_FCOE
4519 if (ixgbe_set_fcoe_queues(adapter))
4520 goto done;
4521
4522#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4523 if (ixgbe_set_fdir_queues(adapter))
4524 goto done;
4525
bc97114d 4526 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4527 goto done;
4528
4529 /* fallback to base case */
4530 adapter->num_rx_queues = 1;
4531 adapter->num_tx_queues = 1;
4532
4533done:
847f53ff 4534 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4535 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4536 return netif_set_real_num_rx_queues(adapter->netdev,
4537 adapter->num_rx_queues);
b9804972
JB		 4538}
4539
021230d4 4540static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4541 int vectors)
021230d4
AV		 4542{
4543 int err, vector_threshold;
4544
4545 /* We'll want at least 3 (vector_threshold):
4546 * 1) TxQ[0] Cleanup
4547 * 2) RxQ[0] Cleanup
4548 * 3) Other (Link Status Change, etc.)
4549 * 4) TCP Timer (optional)
4550 */
4551 vector_threshold = MIN_MSIX_COUNT;
4552
4553 /* The more we get, the more we will assign to Tx/Rx Cleanup
4554 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4555 * Right now, we simply care about how many we'll get; we'll
4556 * set them up later while requesting irq's.
4557 */
4558 while (vectors >= vector_threshold) {
4559 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4560 vectors);
021230d4
AV		 4561 if (!err) /* Success in acquiring all requested vectors. */
4562 break;
4563 else if (err < 0)
4564 vectors = 0; /* Nasty failure, quit now */
4565 else /* err == number of vectors we should try again with */
4566 vectors = err;
4567 }
4568
4569 if (vectors < vector_threshold) {
4570 /* Can't allocate enough MSI-X interrupts? Oh well.
4571 * This just means we'll go with either a single MSI
4572 * vector or fall back to legacy interrupts.
4573 */
849c4542
ET		 4574 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4575 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4576 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4577 kfree(adapter->msix_entries);
4578 adapter->msix_entries = NULL;
021230d4
AV		 4579 } else {
4580 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4581 /*
4582 * Adjust for only the vectors we'll use, which is minimum
4583 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4584 * vectors we were allocated.
4585 */
4586 adapter->num_msix_vectors = min(vectors,
e8e9f696 4587 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4588 }
4589}
4590
021230d4 4591/**
bc97114d 4592 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4593 * @adapter: board private structure to initialize
4594 *
bc97114d
PWJ		 4595 * Cache the descriptor ring offsets for RSS to the assigned rings.
4596 *
021230d4 4597 **/
bc97114d 4598static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4599{
bc97114d 4600 int i;
bc97114d 4601
9d6b758f
AD		 4602 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4603 return false;
bc97114d 4604
9d6b758f
AD		 4605 for (i = 0; i < adapter->num_rx_queues; i++)
4606 adapter->rx_ring[i]->reg_idx = i;
4607 for (i = 0; i < adapter->num_tx_queues; i++)
4608 adapter->tx_ring[i]->reg_idx = i;
4609
4610 return true;
bc97114d
PWJ		 4611}
4612
4613#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4614
4615/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4616static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4617 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4618{
4619 struct net_device *dev = adapter->netdev;
4620 struct ixgbe_hw *hw = &adapter->hw;
4621 u8 num_tcs = netdev_get_num_tc(dev);
4622
4623 *tx = 0;
4624 *rx = 0;
4625
4626 switch (hw->mac.type) {
4627 case ixgbe_mac_82598EB:
aba70d5e
JF		 4628 *tx = tc << 2;
4629 *rx = tc << 3;
e5b64635
JF		 4630 break;
4631 case ixgbe_mac_82599EB:
4632 case ixgbe_mac_X540:
4fa2e0e1 4633 if (num_tcs > 4) {
e5b64635
JF		 4634 if (tc < 3) {
4635 *tx = tc << 5;
4636 *rx = tc << 4;
4637 } else if (tc < 5) {
4638 *tx = ((tc + 2) << 4);
4639 *rx = tc << 4;
4640 } else if (tc < num_tcs) {
4641 *tx = ((tc + 8) << 3);
4642 *rx = tc << 4;
4643 }
4fa2e0e1 4644 } else {
e5b64635
JF		 4645 *rx = tc << 5;
4646 switch (tc) {
4647 case 0:
4648 *tx = 0;
4649 break;
4650 case 1:
4651 *tx = 64;
4652 break;
4653 case 2:
4654 *tx = 96;
4655 break;
4656 case 3:
4657 *tx = 112;
4658 break;
4659 default:
4660 break;
4661 }
4662 }
4663 break;
4664 default:
4665 break;
4666 }
4667}
4668
bc97114d
PWJ		 4669/**
4670 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4671 * @adapter: board private structure to initialize
4672 *
4673 * Cache the descriptor ring offsets for DCB to the assigned rings.
4674 *
4675 **/
4676static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4677{
e5b64635
JF		 4678 struct net_device *dev = adapter->netdev;
4679 int i, j, k;
4680 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4681
8b1c0b24 4682 if (!num_tcs)
bd508178 4683 return false;
f92ef202 4684
e5b64635
JF		 4685 for (i = 0, k = 0; i < num_tcs; i++) {
4686 unsigned int tx_s, rx_s;
4687 u16 count = dev->tc_to_txq[i].count;
4688
4689 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4690 for (j = 0; j < count; j++, k++) {
4691 adapter->tx_ring[k]->reg_idx = tx_s + j;
4692 adapter->rx_ring[k]->reg_idx = rx_s + j;
4693 adapter->tx_ring[k]->dcb_tc = i;
4694 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4695 }
021230d4 4696 }
e5b64635
JF		 4697
4698 return true;
bc97114d
PWJ		 4699}
4700#endif
4701
c4cf55e5
PWJ		 4702/**
4703 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4704 * @adapter: board private structure to initialize
4705 *
4706 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4707 *
4708 **/
e8e9f696 4709static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4710{
4711 int i;
4712 bool ret = false;
4713
03ecf91a
AD		 4714 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4715 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4716 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4717 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4718 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4719 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4720 ret = true;
4721 }
4722
4723 return ret;
4724}
4725
0331a832
YZ		 4726#ifdef IXGBE_FCOE
4727/**
4728 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4729 * @adapter: board private structure to initialize
4730 *
4731 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4732 *
4733 */
4734static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4735{
0331a832 4736 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4737 int i;
4738 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4739
4740 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4741 return false;
0331a832 4742
bf29ee6c 4743 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4744 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4745 ixgbe_cache_ring_fdir(adapter);
4746 else
4747 ixgbe_cache_ring_rss(adapter);
8faa2a78 4748
bf29ee6c
AD		 4749 fcoe_rx_i = f->mask;
4750 fcoe_tx_i = f->mask;
0331a832 4751 }
bf29ee6c
AD		 4752 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4753 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4754 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4755 }
4756 return true;
0331a832
YZ		 4757}
4758
4759#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4760/**
4761 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4762 * @adapter: board private structure to initialize
4763 *
4764 * SR-IOV doesn't use any descriptor rings but changes the default if
4765 * no other mapping is used.
4766 *
4767 */
4768static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4769{
4a0b9ca0
PW		 4770 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4771 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4772 if (adapter->num_vfs)
4773 return true;
4774 else
4775 return false;
4776}
4777
bc97114d
PWJ		 4778/**
4779 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4780 * @adapter: board private structure to initialize
4781 *
4782 * Once we know the feature-set enabled for the device, we'll cache
4783 * the register offset the descriptor ring is assigned to.
4784 *
4785 * Note, the order the various feature calls is important. It must start with
4786 * the "most" features enabled at the same time, then trickle down to the
4787 * least amount of features turned on at once.
4788 **/
4789static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4790{
4791 /* start with default case */
4a0b9ca0
PW		 4792 adapter->rx_ring[0]->reg_idx = 0;
4793 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4794
1cdd1ec8
GR		 4795 if (ixgbe_cache_ring_sriov(adapter))
4796 return;
4797
e5b64635
JF		 4798#ifdef CONFIG_IXGBE_DCB
4799 if (ixgbe_cache_ring_dcb(adapter))
4800 return;
4801#endif
4802
0331a832
YZ		 4803#ifdef IXGBE_FCOE
4804 if (ixgbe_cache_ring_fcoe(adapter))
4805 return;
0331a832 4806#endif /* IXGBE_FCOE */
bc97114d 4807
c4cf55e5
PWJ		 4808 if (ixgbe_cache_ring_fdir(adapter))
4809 return;
4810
bc97114d
PWJ		 4811 if (ixgbe_cache_ring_rss(adapter))
4812 return;
021230d4
AV		 4813}
4814
9a799d71
AK		 4815/**
4816 * ixgbe_alloc_queues - Allocate memory for all rings
4817 * @adapter: board private structure to initialize
4818 *
4819 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4820 * number of queues at compile-time. The polling_netdev array is
4821 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4822 **/
2f90b865 4823static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4824{
e2ddeba9 4825 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4826
e2ddeba9
ED		 4827 if (nid < 0 || !node_online(nid))
4828 nid = first_online_node;
4829
4830 for (; tx < adapter->num_tx_queues; tx++) {
4831 struct ixgbe_ring *ring;
4832
4833 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4834 if (!ring)
e2ddeba9 4835 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4836 if (!ring)
e2ddeba9 4837 goto err_allocation;
4a0b9ca0 4838 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4839 ring->queue_index = tx;
4840 ring->numa_node = nid;
b6ec895e 4841 ring->dev = &adapter->pdev->dev;
fc77dc3c 4842 ring->netdev = adapter->netdev;
4a0b9ca0 4843
e2ddeba9 4844 adapter->tx_ring[tx] = ring;
021230d4 4845 }
b9804972 4846
e2ddeba9
ED		 4847 for (; rx < adapter->num_rx_queues; rx++) {
4848 struct ixgbe_ring *ring;
4a0b9ca0 4849
e2ddeba9 4850 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4851 if (!ring)
e2ddeba9 4852 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4853 if (!ring)
e2ddeba9
ED		 4854 goto err_allocation;
4855 ring->count = adapter->rx_ring_count;
4856 ring->queue_index = rx;
4857 ring->numa_node = nid;
b6ec895e 4858 ring->dev = &adapter->pdev->dev;
fc77dc3c 4859 ring->netdev = adapter->netdev;
4a0b9ca0 4860
e2ddeba9 4861 adapter->rx_ring[rx] = ring;
021230d4
AV		 4862 }
4863
4864 ixgbe_cache_ring_register(adapter);
4865
4866 return 0;
4867
e2ddeba9
ED		 4868err_allocation:
4869 while (tx)
4870 kfree(adapter->tx_ring[--tx]);
4871
4872 while (rx)
4873 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4874 return -ENOMEM;
4875}
4876
4877/**
4878 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4879 * @adapter: board private structure to initialize
4880 *
4881 * Attempt to configure the interrupts using the best available
4882 * capabilities of the hardware and the kernel.
4883 **/
feea6a57 4884static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4885{
8be0e467 4886 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4887 int err = 0;
4888 int vector, v_budget;
4889
4890 /*
4891 * It's easy to be greedy for MSI-X vectors, but it really
4892 * doesn't do us much good if we have a lot more vectors
4893 * than CPU's. So let's be conservative and only ask for
342bde1b 4894 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4895 */
4896 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4897 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4898
4899 /*
4900 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4901 * hw.mac->max_msix_vectors vectors. With features
4902 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4903 * descriptor queues supported by our device. Thus, we cap it off in
4904 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4905 */
8be0e467 4906 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4907
4908 /* A failure in MSI-X entry allocation isn't fatal, but it does
4909 * mean we disable MSI-X capabilities of the adapter. */
4910 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4911 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4912 if (adapter->msix_entries) {
4913 for (vector = 0; vector < v_budget; vector++)
4914 adapter->msix_entries[vector].entry = vector;
021230d4 4915
7a921c93 4916 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4917
7a921c93
AD		 4918 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4919 goto out;
4920 }
26d27844 4921
7a921c93
AD		 4922 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4923 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4924 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4925 e_err(probe,
03ecf91a 4926 "ATR is not supported while multiple "
45b9f509
AD		 4927 "queues are disabled. Disabling Flow Director\n");
4928 }
c4cf55e5 4929 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4930 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4931 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4932 ixgbe_disable_sriov(adapter);
4933
847f53ff
BH		 4934 err = ixgbe_set_num_queues(adapter);
4935 if (err)
4936 return err;
021230d4 4937
021230d4
AV		 4938 err = pci_enable_msi(adapter->pdev);
4939 if (!err) {
4940 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4941 } else {
849c4542
ET		 4942 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4943 "Unable to allocate MSI interrupt, "
4944 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4945 /* reset err */
4946 err = 0;
4947 }
4948
4949out:
021230d4
AV		 4950 return err;
4951}
4952
7a921c93
AD		 4953/**
4954 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4955 * @adapter: board private structure to initialize
4956 *
4957 * We allocate one q_vector per queue interrupt. If allocation fails we
4958 * return -ENOMEM.
4959 **/
4960static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4961{
4ff7fb12 4962 int v_idx, num_q_vectors;
7a921c93 4963 struct ixgbe_q_vector *q_vector;
7a921c93 4964
4ff7fb12 4965 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4966 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4967 else
7a921c93 4968 num_q_vectors = 1;
7a921c93 4969
4ff7fb12 4970 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4971 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4972 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4973 if (!q_vector)
4974 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4975 GFP_KERNEL);
7a921c93
AD		 4976 if (!q_vector)
4977 goto err_out;
4ff7fb12 4978
7a921c93 4979 q_vector->adapter = adapter;
4ff7fb12
AD		 4980 q_vector->v_idx = v_idx;
4981
207867f5
AD		 4982 /* Allocate the affinity_hint cpumask, configure the mask */
4983 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4984 goto err_out;
4985 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 4986 netif_napi_add(adapter->netdev, &q_vector->napi,
4987 ixgbe_poll, 64);
4988 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4989 }
4990
4991 return 0;
4992
4993err_out:
4ff7fb12
AD		 4994 while (v_idx) {
4995 v_idx--;
4996 q_vector = adapter->q_vector[v_idx];
7a921c93 4997 netif_napi_del(&q_vector->napi);
207867f5 4998 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4999 kfree(q_vector);
4ff7fb12 5000 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 5001 }
5002 return -ENOMEM;
5003}
5004
5005/**
5006 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5007 * @adapter: board private structure to initialize
5008 *
5009 * This function frees the memory allocated to the q_vectors. In addition if
5010 * NAPI is enabled it will delete any references to the NAPI struct prior
5011 * to freeing the q_vector.
5012 **/
5013static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5014{
207867f5 5015 int v_idx, num_q_vectors;
7a921c93 5016
91281fd3 5017 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5018 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5019 else
7a921c93 5020 num_q_vectors = 1;
7a921c93 5021
207867f5
AD		 5022 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
5023 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
5024 adapter->q_vector[v_idx] = NULL;
91281fd3 5025 netif_napi_del(&q_vector->napi);
207867f5 5026 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 5027 kfree(q_vector);
5028 }
5029}
5030
7b25cdba 5031static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5032{
5033 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5034 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5035 pci_disable_msix(adapter->pdev);
5036 kfree(adapter->msix_entries);
5037 adapter->msix_entries = NULL;
5038 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5039 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5040 pci_disable_msi(adapter->pdev);
5041 }
021230d4
AV		 5042}
5043
5044/**
5045 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5046 * @adapter: board private structure to initialize
5047 *
5048 * We determine which interrupt scheme to use based on...
5049 * - Kernel support (MSI, MSI-X)
5050 * - which can be user-defined (via MODULE_PARAM)
5051 * - Hardware queue count (num_*_queues)
5052 * - defined by miscellaneous hardware support/features (RSS, etc.)
5053 **/
2f90b865 5054int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5055{
5056 int err;
5057
5058 /* Number of supported queues */
847f53ff
BH		 5059 err = ixgbe_set_num_queues(adapter);
5060 if (err)
5061 return err;
021230d4 5062
021230d4
AV		 5063 err = ixgbe_set_interrupt_capability(adapter);
5064 if (err) {
849c4542 5065 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5066 goto err_set_interrupt;
9a799d71
AK		 5067 }
5068
7a921c93
AD		 5069 err = ixgbe_alloc_q_vectors(adapter);
5070 if (err) {
849c4542 5071 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5072 goto err_alloc_q_vectors;
5073 }
5074
5075 err = ixgbe_alloc_queues(adapter);
5076 if (err) {
849c4542 5077 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5078 goto err_alloc_queues;
5079 }
5080
849c4542 5081 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5082 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5083 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5084
5085 set_bit(__IXGBE_DOWN, &adapter->state);
5086
9a799d71 5087 return 0;
021230d4 5088
7a921c93
AD		 5089err_alloc_queues:
5090 ixgbe_free_q_vectors(adapter);
5091err_alloc_q_vectors:
5092 ixgbe_reset_interrupt_capability(adapter);
021230d4 5093err_set_interrupt:
7a921c93
AD		 5094 return err;
5095}
5096
5097/**
5098 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5099 * @adapter: board private structure to clear interrupt scheme on
5100 *
5101 * We go through and clear interrupt specific resources and reset the structure
5102 * to pre-load conditions
5103 **/
5104void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5105{
4a0b9ca0
PW		 5106 int i;
5107
5108 for (i = 0; i < adapter->num_tx_queues; i++) {
5109 kfree(adapter->tx_ring[i]);
5110 adapter->tx_ring[i] = NULL;
5111 }
5112 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5113 struct ixgbe_ring *ring = adapter->rx_ring[i];
5114
5115 /* ixgbe_get_stats64() might access this ring, we must wait
5116 * a grace period before freeing it.
5117 */
bcec8b65 5118 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5119 adapter->rx_ring[i] = NULL;
5120 }
7a921c93 5121
b8eb3a10
DS		 5122 adapter->num_tx_queues = 0;
5123 adapter->num_rx_queues = 0;
5124
7a921c93
AD		 5125 ixgbe_free_q_vectors(adapter);
5126 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5127}
5128
5129/**
5130 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5131 * @adapter: board private structure to initialize
5132 *
5133 * ixgbe_sw_init initializes the Adapter private data structure.
5134 * Fields are initialized based on PCI device information and
5135 * OS network device settings (MTU size).
5136 **/
5137static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5138{
5139 struct ixgbe_hw *hw = &adapter->hw;
5140 struct pci_dev *pdev = adapter->pdev;
021230d4 5141 unsigned int rss;
7a6b6f51 5142#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5143 int j;
5144 struct tc_configuration *tc;
5145#endif
021230d4 5146
c44ade9e
JB		 5147 /* PCI config space info */
5148
5149 hw->vendor_id = pdev->vendor;
5150 hw->device_id = pdev->device;
5151 hw->revision_id = pdev->revision;
5152 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5153 hw->subsystem_device_id = pdev->subsystem_device;
5154
021230d4
AV		 5155 /* Set capability flags */
5156 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5157 adapter->ring_feature[RING_F_RSS].indices = rss;
5158 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5159 switch (hw->mac.type) {
5160 case ixgbe_mac_82598EB:
bf069c97
DS		 5161 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5162 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5163 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 5164 break;
b93a2226 5165 case ixgbe_mac_X540:
4f51bf70
JK		 5166 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5167 case ixgbe_mac_82599EB:
e8e26350 5168 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5169 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5170 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5171 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5172 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5173 /* Flow Director hash filters enabled */
5174 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5175 adapter->atr_sample_rate = 20;
c4cf55e5 5176 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5177 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5178 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5179#ifdef IXGBE_FCOE
0d551589
YZ		 5180 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5181 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5182 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5183#ifdef CONFIG_IXGBE_DCB
6ee16520 5184 /* Default traffic class to use for FCoE */
56075a98 5185 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5186#endif
eacd73f7 5187#endif /* IXGBE_FCOE */
bd508178
AD		 5188 break;
5189 default:
5190 break;
f8212f97 5191 }
2f90b865 5192
1fc5f038
AD		 5193 /* n-tuple support exists, always init our spinlock */
5194 spin_lock_init(&adapter->fdir_perfect_lock);
5195
7a6b6f51 5196#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5197 switch (hw->mac.type) {
5198 case ixgbe_mac_X540:
5199 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5200 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5201 break;
5202 default:
5203 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5204 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5205 break;
5206 }
5207
2f90b865
AD		 5208 /* Configure DCB traffic classes */
5209 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5210 tc = &adapter->dcb_cfg.tc_config[j];
5211 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5212 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5213 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5214 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5215 tc->dcb_pfc = pfc_disabled;
5216 }
4de2a022
JF		 5217
5218 /* Initialize default user to priority mapping, UPx->TC0 */
5219 tc = &adapter->dcb_cfg.tc_config[0];
5220 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5221 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5222
2f90b865
AD		 5223 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5224 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5225 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5226 adapter->dcb_set_bitmap = 0x00;
3032309b 5227 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5228 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5229 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5230
5231#endif
9a799d71
AK		 5232
5233 /* default flow control settings */
cd7664f6 5234 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5235 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5236#ifdef CONFIG_DCB
5237 adapter->last_lfc_mode = hw->fc.current_mode;
5238#endif
9da712d2 5239 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5240 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5241 hw->fc.send_xon = true;
71fd570b 5242 hw->fc.disable_fc_autoneg = false;
9a799d71 5243
30efa5a3 5244 /* enable itr by default in dynamic mode */
f7554a2b 5245 adapter->rx_itr_setting = 1;
f7554a2b 5246 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5247
5248 /* set defaults for eitr in MegaBytes */
5249 adapter->eitr_low = 10;
5250 adapter->eitr_high = 20;
5251
5252 /* set default ring sizes */
5253 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5254 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5255
bd198058 5256 /* set default work limits */
59224555 5257 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5258
9a799d71 5259 /* initialize eeprom parameters */
c44ade9e 5260 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5261 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5262 return -EIO;
5263 }
5264
021230d4 5265 /* enable rx csum by default */
9a799d71
AK		 5266 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5267
1a6c14a2
JB		 5268 /* get assigned NUMA node */
5269 adapter->node = dev_to_node(&pdev->dev);
5270
9a799d71
AK		 5271 set_bit(__IXGBE_DOWN, &adapter->state);
5272
5273 return 0;
5274}
5275
5276/**
5277 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5278 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5279 *
5280 * Return 0 on success, negative on failure
5281 **/
b6ec895e 5282int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5283{
b6ec895e 5284 struct device *dev = tx_ring->dev;
9a799d71
AK		 5285 int size;
5286
3a581073 5287 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5288 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5289 if (!tx_ring->tx_buffer_info)
89bf67f1 5290 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5291 if (!tx_ring->tx_buffer_info)
5292 goto err;
9a799d71
AK		 5293
5294 /* round up to nearest 4K */
12207e49 5295 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5296 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5297
b6ec895e 5298 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5299 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5300 if (!tx_ring->desc)
5301 goto err;
9a799d71 5302
3a581073
JB		 5303 tx_ring->next_to_use = 0;
5304 tx_ring->next_to_clean = 0;
9a799d71 5305 return 0;
e01c31a5
JB		 5306
5307err:
5308 vfree(tx_ring->tx_buffer_info);
5309 tx_ring->tx_buffer_info = NULL;
b6ec895e 5310 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5311 return -ENOMEM;
9a799d71
AK		 5312}
5313
69888674
AD		 5314/**
5315 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5316 * @adapter: board private structure
5317 *
5318 * If this function returns with an error, then it's possible one or
5319 * more of the rings is populated (while the rest are not). It is the
5320 * callers duty to clean those orphaned rings.
5321 *
5322 * Return 0 on success, negative on failure
5323 **/
5324static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5325{
5326 int i, err = 0;
5327
5328 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5329 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5330 if (!err)
5331 continue;
396e799c 5332 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5333 break;
5334 }
5335
5336 return err;
5337}
5338
9a799d71
AK		 5339/**
5340 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5341 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5342 *
5343 * Returns 0 on success, negative on failure
5344 **/
b6ec895e 5345int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5346{
b6ec895e 5347 struct device *dev = rx_ring->dev;
021230d4 5348 int size;
9a799d71 5349
3a581073 5350 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5351 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5352 if (!rx_ring->rx_buffer_info)
89bf67f1 5353 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5354 if (!rx_ring->rx_buffer_info)
5355 goto err;
9a799d71 5356
9a799d71 5357 /* Round up to nearest 4K */
3a581073
JB		 5358 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5359 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5360
b6ec895e 5361 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5362 &rx_ring->dma, GFP_KERNEL);
9a799d71 5363
b6ec895e
AD		 5364 if (!rx_ring->desc)
5365 goto err;
9a799d71 5366
3a581073
JB		 5367 rx_ring->next_to_clean = 0;
5368 rx_ring->next_to_use = 0;
9a799d71
AK		 5369
5370 return 0;
b6ec895e
AD		 5371err:
5372 vfree(rx_ring->rx_buffer_info);
5373 rx_ring->rx_buffer_info = NULL;
5374 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5375 return -ENOMEM;
9a799d71
AK		 5376}
5377
69888674
AD		 5378/**
5379 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5380 * @adapter: board private structure
5381 *
5382 * If this function returns with an error, then it's possible one or
5383 * more of the rings is populated (while the rest are not). It is the
5384 * callers duty to clean those orphaned rings.
5385 *
5386 * Return 0 on success, negative on failure
5387 **/
69888674
AD		 5388static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5389{
5390 int i, err = 0;
5391
5392 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5393 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5394 if (!err)
5395 continue;
396e799c 5396 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5397 break;
5398 }
5399
5400 return err;
5401}
5402
9a799d71
AK		 5403/**
5404 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5405 * @tx_ring: Tx descriptor ring for a specific queue
5406 *
5407 * Free all transmit software resources
5408 **/
b6ec895e 5409void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5410{
b6ec895e 5411 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5412
5413 vfree(tx_ring->tx_buffer_info);
5414 tx_ring->tx_buffer_info = NULL;
5415
b6ec895e
AD		 5416 /* if not set, then don't free */
5417 if (!tx_ring->desc)
5418 return;
5419
5420 dma_free_coherent(tx_ring->dev, tx_ring->size,
5421 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5422
5423 tx_ring->desc = NULL;
5424}
5425
5426/**
5427 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5428 * @adapter: board private structure
5429 *
5430 * Free all transmit software resources
5431 **/
5432static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5433{
5434 int i;
5435
5436 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5437 if (adapter->tx_ring[i]->desc)
b6ec895e 5438 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5439}
5440
5441/**
b4617240 5442 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5443 * @rx_ring: ring to clean the resources from
5444 *
5445 * Free all receive software resources
5446 **/
b6ec895e 5447void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5448{
b6ec895e 5449 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5450
5451 vfree(rx_ring->rx_buffer_info);
5452 rx_ring->rx_buffer_info = NULL;
5453
b6ec895e
AD		 5454 /* if not set, then don't free */
5455 if (!rx_ring->desc)
5456 return;
5457
5458 dma_free_coherent(rx_ring->dev, rx_ring->size,
5459 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5460
5461 rx_ring->desc = NULL;
5462}
5463
5464/**
5465 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5466 * @adapter: board private structure
5467 *
5468 * Free all receive software resources
5469 **/
5470static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5471{
5472 int i;
5473
5474 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5475 if (adapter->rx_ring[i]->desc)
b6ec895e 5476 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5477}
5478
9a799d71
AK		 5479/**
5480 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5481 * @netdev: network interface device structure
5482 * @new_mtu: new value for maximum frame size
5483 *
5484 * Returns 0 on success, negative on failure
5485 **/
5486static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5487{
5488 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5489 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5490 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5491
42c783c5 5492 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5493 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5494 hw->mac.type != ixgbe_mac_X540) {
5495 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5496 return -EINVAL;
5497 } else {
5498 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5499 return -EINVAL;
5500 }
9a799d71 5501
396e799c 5502 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5503 /* must set new MTU before calling down or up */
9a799d71
AK		 5504 netdev->mtu = new_mtu;
5505
d4f80882
AV		 5506 if (netif_running(netdev))
5507 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5508
5509 return 0;
5510}
5511
5512/**
5513 * ixgbe_open - Called when a network interface is made active
5514 * @netdev: network interface device structure
5515 *
5516 * Returns 0 on success, negative value on failure
5517 *
5518 * The open entry point is called when a network interface is made
5519 * active by the system (IFF_UP). At this point all resources needed
5520 * for transmit and receive operations are allocated, the interrupt
5521 * handler is registered with the OS, the watchdog timer is started,
5522 * and the stack is notified that the interface is ready.
5523 **/
5524static int ixgbe_open(struct net_device *netdev)
5525{
5526 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5527 int err;
4bebfaa5
AK		 5528
5529 /* disallow open during test */
5530 if (test_bit(__IXGBE_TESTING, &adapter->state))
5531 return -EBUSY;
9a799d71 5532
54386467
JB		 5533 netif_carrier_off(netdev);
5534
9a799d71
AK		 5535 /* allocate transmit descriptors */
5536 err = ixgbe_setup_all_tx_resources(adapter);
5537 if (err)
5538 goto err_setup_tx;
5539
9a799d71
AK		 5540 /* allocate receive descriptors */
5541 err = ixgbe_setup_all_rx_resources(adapter);
5542 if (err)
5543 goto err_setup_rx;
5544
5545 ixgbe_configure(adapter);
5546
021230d4 5547 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5548 if (err)
5549 goto err_req_irq;
5550
c7ccde0f 5551 ixgbe_up_complete(adapter);
9a799d71
AK		 5552
5553 return 0;
5554
9a799d71 5555err_req_irq:
9a799d71 5556err_setup_rx:
a20a1199 5557 ixgbe_free_all_rx_resources(adapter);
9a799d71 5558err_setup_tx:
a20a1199 5559 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5560 ixgbe_reset(adapter);
5561
5562 return err;
5563}
5564
5565/**
5566 * ixgbe_close - Disables a network interface
5567 * @netdev: network interface device structure
5568 *
5569 * Returns 0, this is not allowed to fail
5570 *
5571 * The close entry point is called when an interface is de-activated
5572 * by the OS. The hardware is still under the drivers control, but
5573 * needs to be disabled. A global MAC reset is issued to stop the
5574 * hardware, and all transmit and receive resources are freed.
5575 **/
5576static int ixgbe_close(struct net_device *netdev)
5577{
5578 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5579
5580 ixgbe_down(adapter);
5581 ixgbe_free_irq(adapter);
5582
e4911d57
AD		 5583 ixgbe_fdir_filter_exit(adapter);
5584
9a799d71
AK		 5585 ixgbe_free_all_tx_resources(adapter);
5586 ixgbe_free_all_rx_resources(adapter);
5587
5eba3699 5588 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5589
5590 return 0;
5591}
5592
b3c8b4ba
AD		 5593#ifdef CONFIG_PM
5594static int ixgbe_resume(struct pci_dev *pdev)
5595{
c60fbb00
AD		 5596 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5597 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5598 u32 err;
5599
5600 pci_set_power_state(pdev, PCI_D0);
5601 pci_restore_state(pdev);
656ab817
DS		 5602 /*
5603 * pci_restore_state clears dev->state_saved so call
5604 * pci_save_state to restore it.
5605 */
5606 pci_save_state(pdev);
9ce77666 5607
5608 err = pci_enable_device_mem(pdev);
b3c8b4ba 5609 if (err) {
849c4542 5610 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5611 return err;
5612 }
5613 pci_set_master(pdev);
5614
dd4d8ca6 5615 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5616
5617 err = ixgbe_init_interrupt_scheme(adapter);
5618 if (err) {
849c4542 5619 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5620 return err;
5621 }
5622
b3c8b4ba
AD		 5623 ixgbe_reset(adapter);
5624
495dce12
WJP		 5625 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5626
b3c8b4ba 5627 if (netif_running(netdev)) {
c60fbb00 5628 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5629 if (err)
5630 return err;
5631 }
5632
5633 netif_device_attach(netdev);
5634
5635 return 0;
5636}
b3c8b4ba 5637#endif /* CONFIG_PM */
9d8d05ae
RW		 5638
5639static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5640{
c60fbb00
AD		 5641 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5642 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5643 struct ixgbe_hw *hw = &adapter->hw;
5644 u32 ctrl, fctrl;
5645 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5646#ifdef CONFIG_PM
5647 int retval = 0;
5648#endif
5649
5650 netif_device_detach(netdev);
5651
5652 if (netif_running(netdev)) {
5653 ixgbe_down(adapter);
5654 ixgbe_free_irq(adapter);
5655 ixgbe_free_all_tx_resources(adapter);
5656 ixgbe_free_all_rx_resources(adapter);
5657 }
b3c8b4ba 5658
5f5ae6fc 5659 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5660#ifdef CONFIG_DCB
5661 kfree(adapter->ixgbe_ieee_pfc);
5662 kfree(adapter->ixgbe_ieee_ets);
5663#endif
5f5ae6fc 5664
b3c8b4ba
AD		 5665#ifdef CONFIG_PM
5666 retval = pci_save_state(pdev);
5667 if (retval)
5668 return retval;
4df10466 5669
b3c8b4ba 5670#endif
e8e26350
PW		 5671 if (wufc) {
5672 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5673
e8e26350
PW		 5674 /* turn on all-multi mode if wake on multicast is enabled */
5675 if (wufc & IXGBE_WUFC_MC) {
5676 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5677 fctrl |= IXGBE_FCTRL_MPE;
5678 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5679 }
5680
5681 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5682 ctrl |= IXGBE_CTRL_GIO_DIS;
5683 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5684
5685 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5686 } else {
5687 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5688 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5689 }
5690
bd508178
AD		 5691 switch (hw->mac.type) {
5692 case ixgbe_mac_82598EB:
dd4d8ca6 5693 pci_wake_from_d3(pdev, false);
bd508178
AD		 5694 break;
5695 case ixgbe_mac_82599EB:
b93a2226 5696 case ixgbe_mac_X540:
bd508178
AD		 5697 pci_wake_from_d3(pdev, !!wufc);
5698 break;
5699 default:
5700 break;
5701 }
b3c8b4ba 5702
9d8d05ae
RW		 5703 *enable_wake = !!wufc;
5704
b3c8b4ba
AD		 5705 ixgbe_release_hw_control(adapter);
5706
5707 pci_disable_device(pdev);
5708
9d8d05ae
RW		 5709 return 0;
5710}
5711
5712#ifdef CONFIG_PM
5713static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5714{
5715 int retval;
5716 bool wake;
5717
5718 retval = __ixgbe_shutdown(pdev, &wake);
5719 if (retval)
5720 return retval;
5721
5722 if (wake) {
5723 pci_prepare_to_sleep(pdev);
5724 } else {
5725 pci_wake_from_d3(pdev, false);
5726 pci_set_power_state(pdev, PCI_D3hot);
5727 }
b3c8b4ba
AD		 5728
5729 return 0;
5730}
9d8d05ae 5731#endif /* CONFIG_PM */
b3c8b4ba
AD		 5732
5733static void ixgbe_shutdown(struct pci_dev *pdev)
5734{
9d8d05ae
RW		 5735 bool wake;
5736
5737 __ixgbe_shutdown(pdev, &wake);
5738
5739 if (system_state == SYSTEM_POWER_OFF) {
5740 pci_wake_from_d3(pdev, wake);
5741 pci_set_power_state(pdev, PCI_D3hot);
5742 }
b3c8b4ba
AD		 5743}
5744
9a799d71
AK		 5745/**
5746 * ixgbe_update_stats - Update the board statistics counters.
5747 * @adapter: board private structure
5748 **/
5749void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5750{
2d86f139 5751 struct net_device *netdev = adapter->netdev;
9a799d71 5752 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5753 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5754 u64 total_mpc = 0;
5755 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5756 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5757 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5758 u64 bytes = 0, packets = 0;
7b859ebc
AH		 5759#ifdef IXGBE_FCOE
5760 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5761 unsigned int cpu;
5762 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5763#endif /* IXGBE_FCOE */
9a799d71 5764
d08935c2
DS		 5765 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5766 test_bit(__IXGBE_RESETTING, &adapter->state))
5767 return;
5768
94b982b2 5769 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5770 u64 rsc_count = 0;
94b982b2 5771 u64 rsc_flush = 0;
d51019a4
PW		 5772 for (i = 0; i < 16; i++)
5773 adapter->hw_rx_no_dma_resources +=
7ca647bd 5774 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5775 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5776 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5777 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5778 }
5779 adapter->rsc_total_count = rsc_count;
5780 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5781 }
5782
5b7da515
AD		 5783 for (i = 0; i < adapter->num_rx_queues; i++) {
5784 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5785 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5786 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5787 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5788 bytes += rx_ring->stats.bytes;
5789 packets += rx_ring->stats.packets;
5790 }
5791 adapter->non_eop_descs = non_eop_descs;
5792 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5793 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5794 netdev->stats.rx_bytes = bytes;
5795 netdev->stats.rx_packets = packets;
5796
5797 bytes = 0;
5798 packets = 0;
7ca3bc58 5799 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5800 for (i = 0; i < adapter->num_tx_queues; i++) {
5801 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5802 restart_queue += tx_ring->tx_stats.restart_queue;
5803 tx_busy += tx_ring->tx_stats.tx_busy;
5804 bytes += tx_ring->stats.bytes;
5805 packets += tx_ring->stats.packets;
5806 }
eb985f09 5807 adapter->restart_queue = restart_queue;
5b7da515
AD		 5808 adapter->tx_busy = tx_busy;
5809 netdev->stats.tx_bytes = bytes;
5810 netdev->stats.tx_packets = packets;
7ca3bc58 5811
7ca647bd 5812 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5813
5814 /* 8 register reads */
6f11eef7
AV		 5815 for (i = 0; i < 8; i++) {
5816 /* for packet buffers not used, the register should read 0 */
5817 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5818 missed_rx += mpc;
7ca647bd
JP		 5819 hwstats->mpc[i] += mpc;
5820 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5821 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5822 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5823 switch (hw->mac.type) {
5824 case ixgbe_mac_82598EB:
1a70db4b
ET		 5825 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5826 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5827 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5828 hwstats->pxonrxc[i] +=
5829 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5830 break;
5831 case ixgbe_mac_82599EB:
b93a2226 5832 case ixgbe_mac_X540:
bd508178
AD		 5833 hwstats->pxonrxc[i] +=
5834 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5835 break;
5836 default:
5837 break;
e8e26350 5838 }
6f11eef7 5839 }
1a70db4b
ET		 5840
5841 /*16 register reads */
5842 for (i = 0; i < 16; i++) {
5843 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5844 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5845 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5846 (hw->mac.type == ixgbe_mac_X540)) {
5847 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5848 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5849 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5850 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5851 }
5852 }
5853
7ca647bd 5854 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5855 /* work around hardware counting issue */
7ca647bd 5856 hwstats->gprc -= missed_rx;
6f11eef7 5857
c84d324c
JF		 5858 ixgbe_update_xoff_received(adapter);
5859
6f11eef7 5860 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5861 switch (hw->mac.type) {
5862 case ixgbe_mac_82598EB:
5863 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5864 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5865 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5866 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5867 break;
b93a2226 5868 case ixgbe_mac_X540:
58f6bcf9
ET		 5869 /* OS2BMC stats are X540 only*/
5870 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5871 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5872 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5873 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5874 case ixgbe_mac_82599EB:
7ca647bd 5875 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5876 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5877 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5878 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5879 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5880 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5881 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5882 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5883 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5884#ifdef IXGBE_FCOE
7ca647bd
JP		 5885 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5886 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5887 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5888 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5889 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5890 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5891 /* Add up per cpu counters for total ddp aloc fail */
5892 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5893 for_each_possible_cpu(cpu) {
5894 fcoe_noddp_counts_sum +=
5895 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5896 fcoe_noddp_ext_buff_counts_sum +=
5897 *per_cpu_ptr(fcoe->
5898 pcpu_noddp_ext_buff, cpu);
5899 }
5900 }
5901 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5902 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5903#endif /* IXGBE_FCOE */
bd508178
AD		 5904 break;
5905 default:
5906 break;
e8e26350 5907 }
9a799d71 5908 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5909 hwstats->bprc += bprc;
5910 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5911 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5912 hwstats->mprc -= bprc;
5913 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5914 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5915 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5916 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5917 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5918 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5919 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5920 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5921 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5922 hwstats->lxontxc += lxon;
6f11eef7 5923 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5924 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5925 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5926 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5927 /*
5928 * 82598 errata - tx of flow control packets is included in tx counters
5929 */
5930 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5931 hwstats->gptc -= xon_off_tot;
5932 hwstats->mptc -= xon_off_tot;
5933 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5934 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5935 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5936 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5937 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5938 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5939 hwstats->ptc64 -= xon_off_tot;
5940 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5941 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5942 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5943 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5944 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5945 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5946
5947 /* Fill out the OS statistics structure */
7ca647bd 5948 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5949
5950 /* Rx Errors */
7ca647bd 5951 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5952 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5953 netdev->stats.rx_length_errors = hwstats->rlec;
5954 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5955 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5956}
5957
5958/**
d034acf1
AD		 5959 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5960 * @adapter - pointer to the device adapter structure
9a799d71 5961 **/
d034acf1 5962static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5963{
cf8280ee 5964 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5965 int i;
cf8280ee 5966
d034acf1
AD		 5967 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5968 return;
5969
5970 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5971
d034acf1 5972 /* if interface is down do nothing */
fe49f04a 5973 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5974 return;
5975
5976 /* do nothing if we are not using signature filters */
5977 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5978 return;
5979
5980 adapter->fdir_overflow++;
5981
93c52dd0
AD		 5982 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5983 for (i = 0; i < adapter->num_tx_queues; i++)
5984 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5985 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5986 /* re-enable flow director interrupts */
5987 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5988 } else {
5989 e_err(probe, "failed to finish FDIR re-initialization, "
5990 "ignored adding FDIR ATR filters\n");
5991 }
93c52dd0
AD		 5992}
5993
5994/**
5995 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5996 * @adapter - pointer to the device adapter structure
5997 *
5998 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5999 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6000 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6001 * determine if a hang has occurred.
93c52dd0
AD		 6002 */
6003static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6004{
cf8280ee 6005 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6006 u64 eics = 0;
6007 int i;
cf8280ee 6008
93c52dd0
AD		 6009 /* If we're down or resetting, just bail */
6010 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6011 test_bit(__IXGBE_RESETTING, &adapter->state))
6012 return;
22d5a71b 6013
93c52dd0
AD		 6014 /* Force detection of hung controller */
6015 if (netif_carrier_ok(adapter->netdev)) {
6016 for (i = 0; i < adapter->num_tx_queues; i++)
6017 set_check_for_tx_hang(adapter->tx_ring[i]);
6018 }
22d5a71b 6019
fe49f04a
AD		 6020 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6021 /*
6022 * for legacy and MSI interrupts don't set any bits
6023 * that are enabled for EIAM, because this operation
6024 * would set *both* EIMS and EICS for any bit in EIAM
6025 */
6026 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6027 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6028 } else {
6029 /* get one bit for every active tx/rx interrupt vector */
6030 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6031 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6032 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6033 eics |= ((u64)1 << i);
6034 }
cf8280ee 6035 }
9a799d71 6036
93c52dd0 6037 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6038 ixgbe_irq_rearm_queues(adapter, eics);
6039
cf8280ee
JB		 6040}
6041
e8e26350 6042/**
93c52dd0
AD		 6043 * ixgbe_watchdog_update_link - update the link status
6044 * @adapter - pointer to the device adapter structure
6045 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6046 **/
93c52dd0 6047static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6048{
e8e26350 6049 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6050 u32 link_speed = adapter->link_speed;
6051 bool link_up = adapter->link_up;
c4cf55e5 6052 int i;
e8e26350 6053
93c52dd0
AD		 6054 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6055 return;
6056
6057 if (hw->mac.ops.check_link) {
6058 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6059 } else {
93c52dd0
AD		 6060 /* always assume link is up, if no check link function */
6061 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6062 link_up = true;
c4cf55e5 6063 }
93c52dd0
AD		 6064 if (link_up) {
6065 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6066 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6067 hw->mac.ops.fc_enable(hw, i);
6068 } else {
6069 hw->mac.ops.fc_enable(hw, 0);
6070 }
6071 }
6072
6073 if (link_up ||
6074 time_after(jiffies, (adapter->link_check_timeout +
6075 IXGBE_TRY_LINK_TIMEOUT))) {
6076 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6077 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6078 IXGBE_WRITE_FLUSH(hw);
6079 }
6080
6081 adapter->link_up = link_up;
6082 adapter->link_speed = link_speed;
e8e26350
PW		 6083}
6084
6085/**
93c52dd0
AD		 6086 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6087 * print link up message
6088 * @adapter - pointer to the device adapter structure
e8e26350 6089 **/
93c52dd0 6090static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6091{
93c52dd0 6092 struct net_device *netdev = adapter->netdev;
e8e26350 6093 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6094 u32 link_speed = adapter->link_speed;
6095 bool flow_rx, flow_tx;
e8e26350 6096
93c52dd0
AD		 6097 /* only continue if link was previously down */
6098 if (netif_carrier_ok(netdev))
a985b6c3 6099 return;
63d6e1d8 6100
93c52dd0 6101 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6102
93c52dd0
AD		 6103 switch (hw->mac.type) {
6104 case ixgbe_mac_82598EB: {
6105 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6106 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6107 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6108 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6109 }
6110 break;
6111 case ixgbe_mac_X540:
6112 case ixgbe_mac_82599EB: {
6113 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6114 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6115 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6116 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6117 }
6118 break;
6119 default:
6120 flow_tx = false;
6121 flow_rx = false;
6122 break;
e8e26350 6123 }
93c52dd0
AD		 6124 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6125 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6126 "10 Gbps" :
6127 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6128 "1 Gbps" :
6129 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6130 "100 Mbps" :
6131 "unknown speed"))),
6132 ((flow_rx && flow_tx) ? "RX/TX" :
6133 (flow_rx ? "RX" :
6134 (flow_tx ? "TX" : "None"))));
e8e26350 6135
93c52dd0 6136 netif_carrier_on(netdev);
93c52dd0 6137 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 6138}
6139
c4cf55e5 6140/**
93c52dd0
AD		 6141 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6142 * print link down message
6143 * @adapter - pointer to the adapter structure
c4cf55e5 6144 **/
93c52dd0 6145static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6146{
cf8280ee 6147 struct net_device *netdev = adapter->netdev;
c4cf55e5 6148 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6149
93c52dd0
AD		 6150 adapter->link_up = false;
6151 adapter->link_speed = 0;
cf8280ee 6152
93c52dd0
AD		 6153 /* only continue if link was up previously */
6154 if (!netif_carrier_ok(netdev))
6155 return;
264857b8 6156
93c52dd0
AD		 6157 /* poll for SFP+ cable when link is down */
6158 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6159 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6160
93c52dd0
AD		 6161 e_info(drv, "NIC Link is Down\n");
6162 netif_carrier_off(netdev);
6163}
e8e26350 6164
93c52dd0
AD		 6165/**
6166 * ixgbe_watchdog_flush_tx - flush queues on link down
6167 * @adapter - pointer to the device adapter structure
6168 **/
6169static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6170{
c4cf55e5 6171 int i;
93c52dd0 6172 int some_tx_pending = 0;
c4cf55e5 6173
93c52dd0 6174 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6175 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6176 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6177 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6178 some_tx_pending = 1;
6179 break;
6180 }
6181 }
6182
6183 if (some_tx_pending) {
6184 /* We've lost link, so the controller stops DMA,
6185 * but we've got queued Tx work that's never going
6186 * to get done, so reset controller to flush Tx.
6187 * (Do the reset outside of interrupt context).
6188 */
c83c6cbd 6189 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6190 }
c4cf55e5 6191 }
c4cf55e5
PWJ		 6192}
6193
a985b6c3
GR		 6194static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6195{
6196 u32 ssvpc;
6197
6198 /* Do not perform spoof check for 82598 */
6199 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6200 return;
6201
6202 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6203
6204 /*
6205 * ssvpc register is cleared on read, if zero then no
6206 * spoofed packets in the last interval.
6207 */
6208 if (!ssvpc)
6209 return;
6210
6211 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6212}
6213
93c52dd0
AD		 6214/**
6215 * ixgbe_watchdog_subtask - check and bring link up
6216 * @adapter - pointer to the device adapter structure
6217 **/
6218static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6219{
6220 /* if interface is down do nothing */
7edebf9a
ET		 6221 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6222 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6223 return;
6224
6225 ixgbe_watchdog_update_link(adapter);
6226
6227 if (adapter->link_up)
6228 ixgbe_watchdog_link_is_up(adapter);
6229 else
6230 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6231
a985b6c3 6232 ixgbe_spoof_check(adapter);
9a799d71 6233 ixgbe_update_stats(adapter);
93c52dd0
AD		 6234
6235 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6236}
10eec955 6237
cf8280ee 6238/**
7086400d
AD		 6239 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6240 * @adapter - the ixgbe adapter structure
cf8280ee 6241 **/
7086400d 6242static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6243{
cf8280ee 6244 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6245 s32 err;
cf8280ee 6246
7086400d
AD		 6247 /* not searching for SFP so there is nothing to do here */
6248 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6249 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6250 return;
10eec955 6251
7086400d
AD		 6252 /* someone else is in init, wait until next service event */
6253 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6254 return;
cf8280ee 6255
7086400d
AD		 6256 err = hw->phy.ops.identify_sfp(hw);
6257 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6258 goto sfp_out;
264857b8 6259
7086400d
AD		 6260 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6261 /* If no cable is present, then we need to reset
6262 * the next time we find a good cable. */
6263 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6264 }
9a799d71 6265
7086400d
AD		 6266 /* exit on error */
6267 if (err)
6268 goto sfp_out;
e8e26350 6269
7086400d
AD		 6270 /* exit if reset not needed */
6271 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6272 goto sfp_out;
9a799d71 6273
7086400d 6274 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6275
7086400d
AD		 6276 /*
6277 * A module may be identified correctly, but the EEPROM may not have
6278 * support for that module. setup_sfp() will fail in that case, so
6279 * we should not allow that module to load.
6280 */
6281 if (hw->mac.type == ixgbe_mac_82598EB)
6282 err = hw->phy.ops.reset(hw);
6283 else
6284 err = hw->mac.ops.setup_sfp(hw);
6285
6286 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6287 goto sfp_out;
6288
6289 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6290 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6291
6292sfp_out:
6293 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6294
6295 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6296 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6297 e_dev_err("failed to initialize because an unsupported "
6298 "SFP+ module type was detected.\n");
6299 e_dev_err("Reload the driver after installing a "
6300 "supported module.\n");
6301 unregister_netdev(adapter->netdev);
bc59fcda 6302 }
7086400d 6303}
bc59fcda 6304
7086400d
AD		 6305/**
6306 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6307 * @adapter - the ixgbe adapter structure
6308 **/
6309static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6310{
6311 struct ixgbe_hw *hw = &adapter->hw;
6312 u32 autoneg;
6313 bool negotiation;
6314
6315 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6316 return;
6317
6318 /* someone else is in init, wait until next service event */
6319 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6320 return;
6321
6322 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6323
6324 autoneg = hw->phy.autoneg_advertised;
6325 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6326 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6327 if (hw->mac.ops.setup_link)
6328 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6329
6330 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6331 adapter->link_check_timeout = jiffies;
6332 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6333}
6334
83c61fa9
GR		 6335#ifdef CONFIG_PCI_IOV
6336static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6337{
6338 int vf;
6339 struct ixgbe_hw *hw = &adapter->hw;
6340 struct net_device *netdev = adapter->netdev;
6341 u32 gpc;
6342 u32 ciaa, ciad;
6343
6344 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6345 if (gpc) /* If incrementing then no need for the check below */
6346 return;
6347 /*
6348 * Check to see if a bad DMA write target from an errant or
6349 * malicious VF has caused a PCIe error. If so then we can
6350 * issue a VFLR to the offending VF(s) and then resume without
6351 * requesting a full slot reset.
6352 */
6353
6354 for (vf = 0; vf < adapter->num_vfs; vf++) {
6355 ciaa = (vf << 16) | 0x80000000;
6356 /* 32 bit read so align, we really want status at offset 6 */
6357 ciaa |= PCI_COMMAND;
6358 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6359 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6360 ciaa &= 0x7FFFFFFF;
6361 /* disable debug mode asap after reading data */
6362 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6363 /* Get the upper 16 bits which will be the PCI status reg */
6364 ciad >>= 16;
6365 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6366 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6367 /* Issue VFLR */
6368 ciaa = (vf << 16) | 0x80000000;
6369 ciaa |= 0xA8;
6370 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6371 ciad = 0x00008000; /* VFLR */
6372 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6373 ciaa &= 0x7FFFFFFF;
6374 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6375 }
6376 }
6377}
6378
6379#endif
7086400d
AD		 6380/**
6381 * ixgbe_service_timer - Timer Call-back
6382 * @data: pointer to adapter cast into an unsigned long
6383 **/
6384static void ixgbe_service_timer(unsigned long data)
6385{
6386 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6387 unsigned long next_event_offset;
83c61fa9 6388 bool ready = true;
7086400d 6389
83c61fa9
GR		 6390#ifdef CONFIG_PCI_IOV
6391 ready = false;
6392
6393 /*
6394 * don't bother with SR-IOV VF DMA hang check if there are
6395 * no VFs or the link is down
6396 */
6397 if (!adapter->num_vfs ||
6398 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6399 ready = true;
6400 goto normal_timer_service;
6401 }
6402
6403 /* If we have VFs allocated then we must check for DMA hangs */
6404 ixgbe_check_for_bad_vf(adapter);
6405 next_event_offset = HZ / 50;
6406 adapter->timer_event_accumulator++;
6407
6408 if (adapter->timer_event_accumulator >= 100) {
6409 ready = true;
6410 adapter->timer_event_accumulator = 0;
6411 }
6412
6413 goto schedule_event;
6414
6415normal_timer_service:
6416#endif
7086400d
AD		 6417 /* poll faster when waiting for link */
6418 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6419 next_event_offset = HZ / 10;
6420 else
6421 next_event_offset = HZ * 2;
6422
83c61fa9
GR		 6423#ifdef CONFIG_PCI_IOV
6424schedule_event:
6425#endif
7086400d
AD		 6426 /* Reset the timer */
6427 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6428
83c61fa9
GR		 6429 if (ready)
6430 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6431}
6432
c83c6cbd
AD		 6433static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6434{
6435 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6436 return;
6437
6438 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6439
6440 /* If we're already down or resetting, just bail */
6441 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6442 test_bit(__IXGBE_RESETTING, &adapter->state))
6443 return;
6444
6445 ixgbe_dump(adapter);
6446 netdev_err(adapter->netdev, "Reset adapter\n");
6447 adapter->tx_timeout_count++;
6448
6449 ixgbe_reinit_locked(adapter);
6450}
6451
7086400d
AD		 6452/**
6453 * ixgbe_service_task - manages and runs subtasks
6454 * @work: pointer to work_struct containing our data
6455 **/
6456static void ixgbe_service_task(struct work_struct *work)
6457{
6458 struct ixgbe_adapter *adapter = container_of(work,
6459 struct ixgbe_adapter,
6460 service_task);
6461
c83c6cbd 6462 ixgbe_reset_subtask(adapter);
7086400d
AD		 6463 ixgbe_sfp_detection_subtask(adapter);
6464 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6465 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6466 ixgbe_watchdog_subtask(adapter);
d034acf1 6467 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6468 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6469
6470 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6471}
6472
897ab156
AD		 6473void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6474 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6475{
6476 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6477 u16 i = tx_ring->next_to_use;
9a799d71 6478
897ab156 6479 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6480
897ab156
AD		 6481 i++;
6482 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6483
897ab156
AD		 6484 /* set bits to identify this as an advanced context descriptor */
6485 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6486
897ab156
AD		 6487 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6488 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6489 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6490 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6491}
9a799d71 6492
897ab156
AD		 6493static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6494 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6495{
6496 int err;
6497 u32 vlan_macip_lens, type_tucmd;
6498 u32 mss_l4len_idx, l4len;
9a799d71 6499
897ab156
AD		 6500 if (!skb_is_gso(skb))
6501 return 0;
9a799d71 6502
897ab156
AD		 6503 if (skb_header_cloned(skb)) {
6504 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6505 if (err)
6506 return err;
9a799d71 6507 }
9a799d71 6508
897ab156
AD		 6509 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6510 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6511
6512 if (protocol == __constant_htons(ETH_P_IP)) {
6513 struct iphdr *iph = ip_hdr(skb);
6514 iph->tot_len = 0;
6515 iph->check = 0;
6516 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6517 iph->daddr, 0,
6518 IPPROTO_TCP,
6519 0);
6520 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6521 } else if (skb_is_gso_v6(skb)) {
6522 ipv6_hdr(skb)->payload_len = 0;
6523 tcp_hdr(skb)->check =
6524 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6525 &ipv6_hdr(skb)->daddr,
6526 0, IPPROTO_TCP, 0);
6527 }
6528
6529 l4len = tcp_hdrlen(skb);
6530 *hdr_len = skb_transport_offset(skb) + l4len;
6531
6532 /* mss_l4len_id: use 1 as index for TSO */
6533 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6534 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6535 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6536
6537 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6538 vlan_macip_lens = skb_network_header_len(skb);
6539 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6540 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6541
6542 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6543 mss_l4len_idx);
6544
6545 return 1;
6546}
6547
6548static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6549 struct sk_buff *skb, u32 tx_flags,
6550 __be16 protocol)
7ca647bd 6551{
897ab156
AD		 6552 u32 vlan_macip_lens = 0;
6553 u32 mss_l4len_idx = 0;
6554 u32 type_tucmd = 0;
7ca647bd 6555
897ab156 6556 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6557 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6558 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6559 return false;
6560 } else {
6561 u8 l4_hdr = 0;
6562 switch (protocol) {
6563 case __constant_htons(ETH_P_IP):
6564 vlan_macip_lens |= skb_network_header_len(skb);
6565 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6566 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6567 break;
897ab156
AD		 6568 case __constant_htons(ETH_P_IPV6):
6569 vlan_macip_lens |= skb_network_header_len(skb);
6570 l4_hdr = ipv6_hdr(skb)->nexthdr;
6571 break;
6572 default:
6573 if (unlikely(net_ratelimit())) {
6574 dev_warn(tx_ring->dev,
6575 "partial checksum but proto=%x!\n",
6576 skb->protocol);
6577 }
7ca647bd
JP		 6578 break;
6579 }
897ab156
AD		 6580
6581 switch (l4_hdr) {
7ca647bd 6582 case IPPROTO_TCP:
897ab156
AD		 6583 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6584 mss_l4len_idx = tcp_hdrlen(skb) <<
6585 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6586 break;
6587 case IPPROTO_SCTP:
897ab156
AD		 6588 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6589 mss_l4len_idx = sizeof(struct sctphdr) <<
6590 IXGBE_ADVTXD_L4LEN_SHIFT;
6591 break;
6592 case IPPROTO_UDP:
6593 mss_l4len_idx = sizeof(struct udphdr) <<
6594 IXGBE_ADVTXD_L4LEN_SHIFT;
6595 break;
6596 default:
6597 if (unlikely(net_ratelimit())) {
6598 dev_warn(tx_ring->dev,
6599 "partial checksum but l4 proto=%x!\n",
6600 skb->protocol);
6601 }
7ca647bd
JP		 6602 break;
6603 }
7ca647bd
JP		 6604 }
6605
897ab156
AD		 6606 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6607 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6608
897ab156
AD		 6609 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6610 type_tucmd, mss_l4len_idx);
9a799d71 6611
897ab156 6612 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6613}
6614
d3d00239 6615static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6616{
d3d00239
AD		 6617 /* set type for advanced descriptor with frame checksum insertion */
6618 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6619 IXGBE_ADVTXD_DCMD_IFCS |
6620 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6621
d3d00239 6622 /* set HW vlan bit if vlan is present */
66f32a8b 6623 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6624 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6625
d3d00239
AD		 6626 /* set segmentation enable bits for TSO/FSO */
6627#ifdef IXGBE_FCOE
6628 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6629#else
6630 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6631#endif
6632 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6633
d3d00239
AD		 6634 return cmd_type;
6635}
9a799d71 6636
d3d00239
AD		 6637static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6638{
6639 __le32 olinfo_status =
6640 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6641
d3d00239
AD		 6642 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6643 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6644 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6645 /* enble IPv4 checksum for TSO */
6646 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6647 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6648 }
6649
d3d00239
AD		 6650 /* enable L4 checksum for TSO and TX checksum offload */
6651 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6652 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6653
d3d00239
AD		 6654#ifdef IXGBE_FCOE
6655 /* use index 1 context for FCOE/FSO */
6656 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6657 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6658 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6659
d3d00239 6660#endif
7f9643fd
AD		 6661 /*
6662 * Check Context must be set if Tx switch is enabled, which it
6663 * always is for case where virtual functions are running
6664 */
6665 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6666 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6667
d3d00239
AD		 6668 return olinfo_status;
6669}
44df32c5 6670
d3d00239
AD		 6671#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6672 IXGBE_TXD_CMD_RS)
6673
6674static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6675 struct sk_buff *skb,
6676 struct ixgbe_tx_buffer *first,
6677 u32 tx_flags,
6678 const u8 hdr_len)
6679{
6680 struct device *dev = tx_ring->dev;
6681 struct ixgbe_tx_buffer *tx_buffer_info;
6682 union ixgbe_adv_tx_desc *tx_desc;
6683 dma_addr_t dma;
6684 __le32 cmd_type, olinfo_status;
6685 struct skb_frag_struct *frag;
6686 unsigned int f = 0;
6687 unsigned int data_len = skb->data_len;
6688 unsigned int size = skb_headlen(skb);
6689 u32 offset = 0;
6690 u32 paylen = skb->len - hdr_len;
6691 u16 i = tx_ring->next_to_use;
6692 u16 gso_segs;
6693
6694#ifdef IXGBE_FCOE
6695 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6696 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6697 data_len -= sizeof(struct fcoe_crc_eof);
6698 } else {
6699 size -= sizeof(struct fcoe_crc_eof) - data_len;
6700 data_len = 0;
9a799d71
AK		 6701 }
6702 }
44df32c5 6703
d3d00239
AD		 6704#endif
6705 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6706 if (dma_mapping_error(dev, dma))
6707 goto dma_error;
8ad494b0 6708
d3d00239
AD		 6709 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6710 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6711
d3d00239 6712 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6713
d3d00239
AD		 6714 for (;;) {
6715 while (size > IXGBE_MAX_DATA_PER_TXD) {
6716 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6717 tx_desc->read.cmd_type_len =
6718 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6719 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6720
d3d00239
AD		 6721 offset += IXGBE_MAX_DATA_PER_TXD;
6722 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6723
d3d00239
AD		 6724 tx_desc++;
6725 i++;
6726 if (i == tx_ring->count) {
6727 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6728 i = 0;
6729 }
6730 }
e5a43549 6731
e5a43549 6732 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6733 tx_buffer_info->length = offset + size;
6734 tx_buffer_info->tx_flags = tx_flags;
6735 tx_buffer_info->dma = dma;
9a799d71 6736
d3d00239
AD		 6737 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6738 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6739 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6740
d3d00239
AD		 6741 if (!data_len)
6742 break;
9a799d71 6743
d3d00239
AD		 6744 frag = &skb_shinfo(skb)->frags[f];
6745#ifdef IXGBE_FCOE
9e903e08 6746 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6747#else
9e903e08 6748 size = skb_frag_size(frag);
d3d00239
AD		 6749#endif
6750 data_len -= size;
6751 f++;
9a799d71 6752
d3d00239
AD		 6753 offset = 0;
6754 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6755
877749bf 6756 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6757 if (dma_mapping_error(dev, dma))
6758 goto dma_error;
9a799d71 6759
d3d00239
AD		 6760 tx_desc++;
6761 i++;
6762 if (i == tx_ring->count) {
6763 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6764 i = 0;
6765 }
6766 }
9a799d71 6767
d3d00239 6768 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6769
d3d00239
AD		 6770 i++;
6771 if (i == tx_ring->count)
6772 i = 0;
9a799d71 6773
d3d00239 6774 tx_ring->next_to_use = i;
eacd73f7 6775
d3d00239
AD		 6776 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6777 gso_segs = skb_shinfo(skb)->gso_segs;
6778#ifdef IXGBE_FCOE
6779 /* adjust for FCoE Sequence Offload */
6780 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6781 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6782 skb_shinfo(skb)->gso_size);
6783#endif /* IXGBE_FCOE */
6784 else
6785 gso_segs = 1;
9a799d71 6786
d3d00239
AD		 6787 /* multiply data chunks by size of headers */
6788 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6789 tx_buffer_info->gso_segs = gso_segs;
6790 tx_buffer_info->skb = skb;
9a799d71 6791
d3d00239
AD		 6792 /* set the timestamp */
6793 first->time_stamp = jiffies;
9a799d71
AK		 6794
6795 /*
6796 * Force memory writes to complete before letting h/w
6797 * know there are new descriptors to fetch. (Only
6798 * applicable for weak-ordered memory model archs,
6799 * such as IA-64).
6800 */
6801 wmb();
6802
d3d00239
AD		 6803 /* set next_to_watch value indicating a packet is present */
6804 first->next_to_watch = tx_desc;
6805
6806 /* notify HW of packet */
84ea2591 6807 writel(i, tx_ring->tail);
d3d00239
AD		 6808
6809 return;
6810dma_error:
6811 dev_err(dev, "TX DMA map failed\n");
6812
6813 /* clear dma mappings for failed tx_buffer_info map */
6814 for (;;) {
6815 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6816 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6817 if (tx_buffer_info == first)
6818 break;
6819 if (i == 0)
6820 i = tx_ring->count;
6821 i--;
6822 }
6823
6824 dev_kfree_skb_any(skb);
6825
6826 tx_ring->next_to_use = i;
9a799d71
AK		 6827}
6828
69830529
AD		 6829static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6830 u32 tx_flags, __be16 protocol)
6831{
6832 struct ixgbe_q_vector *q_vector = ring->q_vector;
6833 union ixgbe_atr_hash_dword input = { .dword = 0 };
6834 union ixgbe_atr_hash_dword common = { .dword = 0 };
6835 union {
6836 unsigned char *network;
6837 struct iphdr *ipv4;
6838 struct ipv6hdr *ipv6;
6839 } hdr;
ee9e0f0b 6840 struct tcphdr *th;
905e4a41 6841 __be16 vlan_id;
c4cf55e5 6842
69830529
AD		 6843 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6844 if (!q_vector)
6845 return;
6846
6847 /* do nothing if sampling is disabled */
6848 if (!ring->atr_sample_rate)
d3ead241 6849 return;
c4cf55e5 6850
69830529 6851 ring->atr_count++;
c4cf55e5 6852
69830529
AD		 6853 /* snag network header to get L4 type and address */
6854 hdr.network = skb_network_header(skb);
6855
6856 /* Currently only IPv4/IPv6 with TCP is supported */
6857 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6858 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6859 (protocol != __constant_htons(ETH_P_IP) ||
6860 hdr.ipv4->protocol != IPPROTO_TCP))
6861 return;
ee9e0f0b
AD		 6862
6863 th = tcp_hdr(skb);
c4cf55e5 6864
66f32a8b
AD		 6865 /* skip this packet since it is invalid or the socket is closing */
6866 if (!th || th->fin)
69830529
AD		 6867 return;
6868
6869 /* sample on all syn packets or once every atr sample count */
6870 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6871 return;
6872
6873 /* reset sample count */
6874 ring->atr_count = 0;
6875
6876 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6877
6878 /*
6879 * src and dst are inverted, think how the receiver sees them
6880 *
6881 * The input is broken into two sections, a non-compressed section
6882 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6883 * is XORed together and stored in the compressed dword.
6884 */
6885 input.formatted.vlan_id = vlan_id;
6886
6887 /*
6888 * since src port and flex bytes occupy the same word XOR them together
6889 * and write the value to source port portion of compressed dword
6890 */
66f32a8b 6891 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6892 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6893 else
6894 common.port.src ^= th->dest ^ protocol;
6895 common.port.dst ^= th->source;
6896
6897 if (protocol == __constant_htons(ETH_P_IP)) {
6898 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6899 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6900 } else {
6901 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6902 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6903 hdr.ipv6->saddr.s6_addr32[1] ^
6904 hdr.ipv6->saddr.s6_addr32[2] ^
6905 hdr.ipv6->saddr.s6_addr32[3] ^
6906 hdr.ipv6->daddr.s6_addr32[0] ^
6907 hdr.ipv6->daddr.s6_addr32[1] ^
6908 hdr.ipv6->daddr.s6_addr32[2] ^
6909 hdr.ipv6->daddr.s6_addr32[3];
6910 }
c4cf55e5
PWJ		 6911
6912 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6913 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6914 input, common, ring->queue_index);
c4cf55e5
PWJ		 6915}
6916
63544e9c 6917static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6918{
fc77dc3c 6919 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6920 /* Herbert's original patch had:
6921 * smp_mb__after_netif_stop_queue();
6922 * but since that doesn't exist yet, just open code it. */
6923 smp_mb();
6924
6925 /* We need to check again in a case another CPU has just
6926 * made room available. */
7d4987de 6927 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6928 return -EBUSY;
6929
6930 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6931 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6932 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6933 return 0;
6934}
6935
82d4e46e 6936static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6937{
7d4987de 6938 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6939 return 0;
fc77dc3c 6940 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6941}
6942
09a3b1f8
SH		 6943static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6944{
6945 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6946 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6947 smp_processor_id();
56075a98 6948#ifdef IXGBE_FCOE
6440752c 6949 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6950
e5b64635
JF		 6951 if (((protocol == htons(ETH_P_FCOE)) ||
6952 (protocol == htons(ETH_P_FIP))) &&
6953 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6954 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6955 txq += adapter->ring_feature[RING_F_FCOE].mask;
6956 return txq;
56075a98
JF		 6957 }
6958#endif
6959
fdd3d631
KK		 6960 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6961 while (unlikely(txq >= dev->real_num_tx_queues))
6962 txq -= dev->real_num_tx_queues;
5f715823 6963 return txq;
fdd3d631 6964 }
c4cf55e5 6965
09a3b1f8
SH		 6966 return skb_tx_hash(dev, skb);
6967}
6968
fc77dc3c 6969netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6970 struct ixgbe_adapter *adapter,
6971 struct ixgbe_ring *tx_ring)
9a799d71 6972{
d3d00239 6973 struct ixgbe_tx_buffer *first;
5f715823 6974 int tso;
d3d00239 6975 u32 tx_flags = 0;
a535c30e
AD		 6976#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6977 unsigned short f;
6978#endif
a535c30e 6979 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6980 __be16 protocol = skb->protocol;
63544e9c 6981 u8 hdr_len = 0;
5e09a105 6982
a535c30e
AD		 6983 /*
6984 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6985 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6986 * + 2 desc gap to keep tail from touching head,
6987 * + 1 desc for context descriptor,
6988 * otherwise try next time
6989 */
6990#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6991 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6992 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6993#else
6994 count += skb_shinfo(skb)->nr_frags;
6995#endif
6996 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6997 tx_ring->tx_stats.tx_busy++;
6998 return NETDEV_TX_BUSY;
6999 }
7000
7f9643fd
AD		 7001#ifdef CONFIG_PCI_IOV
7002 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7003 tx_flags |= IXGBE_TX_FLAGS_TXSW;
7004
7005#endif
66f32a8b 7006 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7007 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7008 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7009 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7010 /* else if it is a SW VLAN check the next protocol and store the tag */
7011 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7012 struct vlan_hdr *vhdr, _vhdr;
7013 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7014 if (!vhdr)
7015 goto out_drop;
7016
7017 protocol = vhdr->h_vlan_encapsulated_proto;
7018 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7019 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7020 }
7021
32701dc2 7022 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7023 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7024 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7025 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7026 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7027 tx_flags |= (skb->priority & 0x7) <<
7028 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7029 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7030 struct vlan_ethhdr *vhdr;
7031 if (skb_header_cloned(skb) &&
7032 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7033 goto out_drop;
7034 vhdr = (struct vlan_ethhdr *)skb->data;
7035 vhdr->h_vlan_TCI = htons(tx_flags >>
7036 IXGBE_TX_FLAGS_VLAN_SHIFT);
7037 } else {
7038 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7039 }
9a799d71 7040 }
eacd73f7 7041
a535c30e 7042 /* record the location of the first descriptor for this packet */
d3d00239 7043 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 7044
eacd73f7 7045#ifdef IXGBE_FCOE
66f32a8b
AD		 7046 /* setup tx offload for FCoE */
7047 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
7048 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 7049 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
7050 if (tso < 0)
7051 goto out_drop;
7052 else if (tso)
66f32a8b
AD		 7053 tx_flags |= IXGBE_TX_FLAGS_FSO |
7054 IXGBE_TX_FLAGS_FCOE;
7055 else
7056 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 7057
66f32a8b 7058 goto xmit_fcoe;
eacd73f7 7059 }
9a799d71 7060
66f32a8b
AD		 7061#endif /* IXGBE_FCOE */
7062 /* setup IPv4/IPv6 offloads */
7063 if (protocol == __constant_htons(ETH_P_IP))
7064 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 7065
66f32a8b
AD		 7066 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
7067 if (tso < 0)
897ab156 7068 goto out_drop;
66f32a8b
AD		 7069 else if (tso)
7070 tx_flags |= IXGBE_TX_FLAGS_TSO;
7071 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
7072 tx_flags |= IXGBE_TX_FLAGS_CSUM;
7073
7074 /* add the ATR filter if ATR is on */
7075 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7076 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7077
7078#ifdef IXGBE_FCOE
7079xmit_fcoe:
7080#endif /* IXGBE_FCOE */
d3d00239
AD		 7081 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
7082
7083 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7084
7085 return NETDEV_TX_OK;
897ab156
AD		 7086
7087out_drop:
7088 dev_kfree_skb_any(skb);
7089 return NETDEV_TX_OK;
9a799d71
AK		 7090}
7091
84418e3b
AD		 7092static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7093{
7094 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7095 struct ixgbe_ring *tx_ring;
7096
7097 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 7098 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7099}
7100
9a799d71
AK		 7101/**
7102 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7103 * @netdev: network interface device structure
7104 * @p: pointer to an address structure
7105 *
7106 * Returns 0 on success, negative on failure
7107 **/
7108static int ixgbe_set_mac(struct net_device *netdev, void *p)
7109{
7110 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7111 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7112 struct sockaddr *addr = p;
7113
7114 if (!is_valid_ether_addr(addr->sa_data))
7115 return -EADDRNOTAVAIL;
7116
7117 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7118 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7119
1cdd1ec8
GR		 7120 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7121 IXGBE_RAH_AV);
9a799d71
AK		 7122
7123 return 0;
7124}
7125
6b73e10d
BH		 7126static int
7127ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7128{
7129 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7130 struct ixgbe_hw *hw = &adapter->hw;
7131 u16 value;
7132 int rc;
7133
7134 if (prtad != hw->phy.mdio.prtad)
7135 return -EINVAL;
7136 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7137 if (!rc)
7138 rc = value;
7139 return rc;
7140}
7141
7142static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7143 u16 addr, u16 value)
7144{
7145 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7146 struct ixgbe_hw *hw = &adapter->hw;
7147
7148 if (prtad != hw->phy.mdio.prtad)
7149 return -EINVAL;
7150 return hw->phy.ops.write_reg(hw, addr, devad, value);
7151}
7152
7153static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7154{
7155 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7156
7157 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7158}
7159
0365e6e4
PW		 7160/**
7161 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7162 * netdev->dev_addrs
0365e6e4
PW		 7163 * @netdev: network interface device structure
7164 *
7165 * Returns non-zero on failure
7166 **/
7167static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7168{
7169 int err = 0;
7170 struct ixgbe_adapter *adapter = netdev_priv(dev);
7171 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7172
7173 if (is_valid_ether_addr(mac->san_addr)) {
7174 rtnl_lock();
7175 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7176 rtnl_unlock();
7177 }
7178 return err;
7179}
7180
7181/**
7182 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7183 * netdev->dev_addrs
0365e6e4
PW		 7184 * @netdev: network interface device structure
7185 *
7186 * Returns non-zero on failure
7187 **/
7188static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7189{
7190 int err = 0;
7191 struct ixgbe_adapter *adapter = netdev_priv(dev);
7192 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7193
7194 if (is_valid_ether_addr(mac->san_addr)) {
7195 rtnl_lock();
7196 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7197 rtnl_unlock();
7198 }
7199 return err;
7200}
7201
9a799d71
AK		 7202#ifdef CONFIG_NET_POLL_CONTROLLER
7203/*
7204 * Polling 'interrupt' - used by things like netconsole to send skbs
7205 * without having to re-enable interrupts. It's not called while
7206 * the interrupt routine is executing.
7207 */
7208static void ixgbe_netpoll(struct net_device *netdev)
7209{
7210 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7211 int i;
9a799d71 7212
1a647bd2
AD		 7213 /* if interface is down do nothing */
7214 if (test_bit(__IXGBE_DOWN, &adapter->state))
7215 return;
7216
9a799d71 7217 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7218 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7219 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7220 for (i = 0; i < num_q_vectors; i++) {
7221 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7222 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7223 }
7224 } else {
7225 ixgbe_intr(adapter->pdev->irq, netdev);
7226 }
9a799d71 7227 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7228}
7229#endif
7230
de1036b1
ED		 7231static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7232 struct rtnl_link_stats64 *stats)
7233{
7234 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7235 int i;
7236
1a51502b 7237 rcu_read_lock();
de1036b1 7238 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7239 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7240 u64 bytes, packets;
7241 unsigned int start;
7242
1a51502b
ED		 7243 if (ring) {
7244 do {
7245 start = u64_stats_fetch_begin_bh(&ring->syncp);
7246 packets = ring->stats.packets;
7247 bytes = ring->stats.bytes;
7248 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7249 stats->rx_packets += packets;
7250 stats->rx_bytes += bytes;
7251 }
de1036b1 7252 }
1ac9ad13
ED		 7253
7254 for (i = 0; i < adapter->num_tx_queues; i++) {
7255 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7256 u64 bytes, packets;
7257 unsigned int start;
7258
7259 if (ring) {
7260 do {
7261 start = u64_stats_fetch_begin_bh(&ring->syncp);
7262 packets = ring->stats.packets;
7263 bytes = ring->stats.bytes;
7264 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7265 stats->tx_packets += packets;
7266 stats->tx_bytes += bytes;
7267 }
7268 }
1a51502b 7269 rcu_read_unlock();
de1036b1
ED		 7270 /* following stats updated by ixgbe_watchdog_task() */
7271 stats->multicast = netdev->stats.multicast;
7272 stats->rx_errors = netdev->stats.rx_errors;
7273 stats->rx_length_errors = netdev->stats.rx_length_errors;
7274 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7275 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7276 return stats;
7277}
7278
8b1c0b24
JF		 7279/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7280 * #adapter: pointer to ixgbe_adapter
7281 * @tc: number of traffic classes currently enabled
7282 *
7283 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7284 * 802.1Q priority maps to a packet buffer that exists.
7285 */
7286static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7287{
7288 struct ixgbe_hw *hw = &adapter->hw;
7289 u32 reg, rsave;
7290 int i;
7291
7292 /* 82598 have a static priority to TC mapping that can not
7293 * be changed so no validation is needed.
7294 */
7295 if (hw->mac.type == ixgbe_mac_82598EB)
7296 return;
7297
7298 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7299 rsave = reg;
7300
7301 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7302 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7303
7304 /* If up2tc is out of bounds default to zero */
7305 if (up2tc > tc)
7306 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7307 }
7308
7309 if (reg != rsave)
7310 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7311
7312 return;
7313}
7314
7315
7316/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7317 * classes.
7318 *
7319 * @netdev: net device to configure
7320 * @tc: number of traffic classes to enable
7321 */
7322int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7323{
8b1c0b24
JF		 7324 struct ixgbe_adapter *adapter = netdev_priv(dev);
7325 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7326
e7589eab
JF		 7327 /* Multiple traffic classes requires multiple queues */
7328 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7329 e_err(drv, "Enable failed, needs MSI-X\n");
7330 return -EINVAL;
7331 }
8b1c0b24
JF		 7332
7333 /* Hardware supports up to 8 traffic classes */
4de2a022 7334 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7335 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7336 return -EINVAL;
7337
7338 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7339 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7340 * hardware is not flexible enough to do this dynamically.
7341 */
7342 if (netif_running(dev))
7343 ixgbe_close(dev);
7344 ixgbe_clear_interrupt_scheme(adapter);
7345
e7589eab 7346 if (tc) {
8b1c0b24 7347 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7348 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7349
7350 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7351 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7352
7353 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7354 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7355 } else {
8b1c0b24
JF		 7356 netdev_reset_tc(dev);
7357
e7589eab
JF		 7358 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7359
7360 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7361 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7362
7363 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7364 adapter->dcb_cfg.pfc_mode_enable = false;
7365 }
7366
8b1c0b24
JF		 7367 ixgbe_init_interrupt_scheme(adapter);
7368 ixgbe_validate_rtr(adapter, tc);
7369 if (netif_running(dev))
7370 ixgbe_open(dev);
7371
7372 return 0;
7373}
de1036b1 7374
082757af
DS		 7375void ixgbe_do_reset(struct net_device *netdev)
7376{
7377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7378
7379 if (netif_running(netdev))
7380 ixgbe_reinit_locked(adapter);
7381 else
7382 ixgbe_reset(adapter);
7383}
7384
c8f44aff
MM		 7385static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7386 netdev_features_t data)
082757af
DS		 7387{
7388 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7389
7390#ifdef CONFIG_DCB
7391 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7392 data &= ~NETIF_F_HW_VLAN_RX;
7393#endif
7394
7395 /* return error if RXHASH is being enabled when RSS is not supported */
7396 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7397 data &= ~NETIF_F_RXHASH;
7398
7399 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7400 if (!(data & NETIF_F_RXCSUM))
7401 data &= ~NETIF_F_LRO;
7402
7403 /* Turn off LRO if not RSC capable or invalid ITR settings */
7404 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7405 data &= ~NETIF_F_LRO;
7406 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7407 (adapter->rx_itr_setting != 1 &&
7408 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7409 data &= ~NETIF_F_LRO;
7410 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7411 }
7412
7413 return data;
7414}
7415
c8f44aff
MM		 7416static int ixgbe_set_features(struct net_device *netdev,
7417 netdev_features_t data)
082757af
DS		 7418{
7419 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7420 bool need_reset = false;
7421
7422 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7423 if (!(data & NETIF_F_RXCSUM))
7424 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7425 else
7426 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7427
7428 /* Make sure RSC matches LRO, reset if change */
7429 if (!!(data & NETIF_F_LRO) !=
7430 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7431 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7432 switch (adapter->hw.mac.type) {
7433 case ixgbe_mac_X540:
7434 case ixgbe_mac_82599EB:
7435 need_reset = true;
7436 break;
7437 default:
7438 break;
7439 }
7440 }
7441
7442 /*
7443 * Check if Flow Director n-tuple support was enabled or disabled. If
7444 * the state changed, we need to reset.
7445 */
7446 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7447 /* turn off ATR, enable perfect filters and reset */
7448 if (data & NETIF_F_NTUPLE) {
7449 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7450 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7451 need_reset = true;
7452 }
7453 } else if (!(data & NETIF_F_NTUPLE)) {
7454 /* turn off Flow Director, set ATR and reset */
7455 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7456 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7457 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7458 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7459 need_reset = true;
7460 }
7461
7462 if (need_reset)
7463 ixgbe_do_reset(netdev);
7464
7465 return 0;
7466
7467}
7468
0edc3527 7469static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7470 .ndo_open = ixgbe_open,
0edc3527 7471 .ndo_stop = ixgbe_close,
00829823 7472 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7473 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7474 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7475 .ndo_validate_addr = eth_validate_addr,
7476 .ndo_set_mac_address = ixgbe_set_mac,
7477 .ndo_change_mtu = ixgbe_change_mtu,
7478 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7479 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7480 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7481 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7482 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7483 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7484 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7485 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7486 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7487 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7488 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7489#ifdef CONFIG_NET_POLL_CONTROLLER
7490 .ndo_poll_controller = ixgbe_netpoll,
7491#endif
332d4a7d
YZ		 7492#ifdef IXGBE_FCOE
7493 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7494 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7495 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7496 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7497 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7498 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7499 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7500#endif /* IXGBE_FCOE */
082757af
DS		 7501 .ndo_set_features = ixgbe_set_features,
7502 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7503};
7504
1cdd1ec8
GR		 7505static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7506 const struct ixgbe_info *ii)
7507{
7508#ifdef CONFIG_PCI_IOV
7509 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7510
c6bda30a 7511 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7512 return;
7513
7514 /* The 82599 supports up to 64 VFs per physical function
7515 * but this implementation limits allocation to 63 so that
7516 * basic networking resources are still available to the
7517 * physical function
7518 */
7519 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7520 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7521#endif /* CONFIG_PCI_IOV */
7522}
7523
9a799d71
AK		 7524/**
7525 * ixgbe_probe - Device Initialization Routine
7526 * @pdev: PCI device information struct
7527 * @ent: entry in ixgbe_pci_tbl
7528 *
7529 * Returns 0 on success, negative on failure
7530 *
7531 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7532 * The OS initialization, configuring of the adapter private structure,
7533 * and a hardware reset occur.
7534 **/
7535static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7536 const struct pci_device_id *ent)
9a799d71
AK		 7537{
7538 struct net_device *netdev;
7539 struct ixgbe_adapter *adapter = NULL;
7540 struct ixgbe_hw *hw;
7541 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7542 static int cards_found;
7543 int i, err, pci_using_dac;
289700db 7544 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7545 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7546#ifdef IXGBE_FCOE
7547 u16 device_caps;
7548#endif
289700db 7549 u32 eec;
c23f5b6b 7550 u16 wol_cap;
9a799d71 7551
bded64a7
AG		 7552 /* Catch broken hardware that put the wrong VF device ID in
7553 * the PCIe SR-IOV capability.
7554 */
7555 if (pdev->is_virtfn) {
7556 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7557 pci_name(pdev), pdev->vendor, pdev->device);
7558 return -EINVAL;
7559 }
7560
9ce77666 7561 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7562 if (err)
7563 return err;
7564
1b507730
NN		 7565 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7566 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7567 pci_using_dac = 1;
7568 } else {
1b507730 7569 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7570 if (err) {
1b507730
NN		 7571 err = dma_set_coherent_mask(&pdev->dev,
7572 DMA_BIT_MASK(32));
9a799d71 7573 if (err) {
b8bc0421
DC		 7574 dev_err(&pdev->dev,
7575 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7576 goto err_dma;
7577 }
7578 }
7579 pci_using_dac = 0;
7580 }
7581
9ce77666 7582 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7583 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7584 if (err) {
b8bc0421
DC		 7585 dev_err(&pdev->dev,
7586 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7587 goto err_pci_reg;
7588 }
7589
19d5afd4 7590 pci_enable_pcie_error_reporting(pdev);
6fabd715 7591
9a799d71 7592 pci_set_master(pdev);
fb3b27bc 7593 pci_save_state(pdev);
9a799d71 7594
e901acd6
JF		 7595#ifdef CONFIG_IXGBE_DCB
7596 indices *= MAX_TRAFFIC_CLASS;
7597#endif
7598
c85a2618
JF		 7599 if (ii->mac == ixgbe_mac_82598EB)
7600 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7601 else
7602 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7603
e901acd6 7604#ifdef IXGBE_FCOE
c85a2618
JF		 7605 indices += min_t(unsigned int, num_possible_cpus(),
7606 IXGBE_MAX_FCOE_INDICES);
7607#endif
c85a2618 7608 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7609 if (!netdev) {
7610 err = -ENOMEM;
7611 goto err_alloc_etherdev;
7612 }
7613
9a799d71
AK		 7614 SET_NETDEV_DEV(netdev, &pdev->dev);
7615
9a799d71 7616 adapter = netdev_priv(netdev);
c60fbb00 7617 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7618
7619 adapter->netdev = netdev;
7620 adapter->pdev = pdev;
7621 hw = &adapter->hw;
7622 hw->back = adapter;
7623 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7624
05857980 7625 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7626 pci_resource_len(pdev, 0));
9a799d71
AK		 7627 if (!hw->hw_addr) {
7628 err = -EIO;
7629 goto err_ioremap;
7630 }
7631
7632 for (i = 1; i <= 5; i++) {
7633 if (pci_resource_len(pdev, i) == 0)
7634 continue;
7635 }
7636
0edc3527 7637 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7638 ixgbe_set_ethtool_ops(netdev);
9a799d71 7639 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7640 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7641
9a799d71
AK		 7642 adapter->bd_number = cards_found;
7643
9a799d71
AK		 7644 /* Setup hw api */
7645 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7646 hw->mac.type = ii->mac;
9a799d71 7647
c44ade9e
JB		 7648 /* EEPROM */
7649 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7650 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7651 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7652 if (!(eec & (1 << 8)))
7653 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7654
7655 /* PHY */
7656 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7657 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7658 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7659 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7660 hw->phy.mdio.mmds = 0;
7661 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7662 hw->phy.mdio.dev = netdev;
7663 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7664 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7665
8ca783ab 7666 ii->get_invariants(hw);
9a799d71
AK		 7667
7668 /* setup the private structure */
7669 err = ixgbe_sw_init(adapter);
7670 if (err)
7671 goto err_sw_init;
7672
e86bff0e 7673 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7674 switch (adapter->hw.mac.type) {
7675 case ixgbe_mac_82599EB:
7676 case ixgbe_mac_X540:
e86bff0e 7677 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7678 break;
7679 default:
7680 break;
7681 }
e86bff0e 7682
bf069c97
DS		 7683 /*
7684 * If there is a fan on this device and it has failed log the
7685 * failure.
7686 */
7687 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7688 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7689 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7690 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7691 }
7692
8ef78adc
PWJ		 7693 if (allow_unsupported_sfp)
7694 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7695
c44ade9e 7696 /* reset_hw fills in the perm_addr as well */
119fc60a 7697 hw->phy.reset_if_overtemp = true;
c44ade9e 7698 err = hw->mac.ops.reset_hw(hw);
119fc60a 7699 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7700 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7701 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7702 err = 0;
7703 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7704 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7705 "module type was detected.\n");
7706 e_dev_err("Reload the driver after installing a supported "
7707 "module.\n");
04f165ef
PW		 7708 goto err_sw_init;
7709 } else if (err) {
849c4542 7710 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7711 goto err_sw_init;
7712 }
7713
1cdd1ec8
GR		 7714 ixgbe_probe_vf(adapter, ii);
7715
396e799c 7716 netdev->features = NETIF_F_SG |
e8e9f696 7717 NETIF_F_IP_CSUM |
082757af 7718 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7719 NETIF_F_HW_VLAN_TX |
7720 NETIF_F_HW_VLAN_RX |
082757af
DS		 7721 NETIF_F_HW_VLAN_FILTER |
7722 NETIF_F_TSO |
7723 NETIF_F_TSO6 |
082757af
DS		 7724 NETIF_F_RXHASH |
7725 NETIF_F_RXCSUM;
9a799d71 7726
082757af 7727 netdev->hw_features = netdev->features;
ad31c402 7728
58be7666
DS		 7729 switch (adapter->hw.mac.type) {
7730 case ixgbe_mac_82599EB:
7731 case ixgbe_mac_X540:
45a5ead0 7732 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7733 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7734 NETIF_F_NTUPLE;
58be7666
DS		 7735 break;
7736 default:
7737 break;
7738 }
45a5ead0 7739
ad31c402
JK		 7740 netdev->vlan_features |= NETIF_F_TSO;
7741 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7742 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7743 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7744 netdev->vlan_features |= NETIF_F_SG;
7745
01789349
JP		 7746 netdev->priv_flags |= IFF_UNICAST_FLT;
7747
1cdd1ec8
GR		 7748 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7749 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7750 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7751
7a6b6f51 7752#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7753 netdev->dcbnl_ops = &dcbnl_ops;
7754#endif
7755
eacd73f7 7756#ifdef IXGBE_FCOE
0d551589 7757 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7758 if (hw->mac.ops.get_device_caps) {
7759 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7760 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7761 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7762 }
7763 }
5e09d7f6
YZ		 7764 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7765 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7766 netdev->vlan_features |= NETIF_F_FSO;
7767 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7768 }
eacd73f7 7769#endif /* IXGBE_FCOE */
7b872a55 7770 if (pci_using_dac) {
9a799d71 7771 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7772 netdev->vlan_features |= NETIF_F_HIGHDMA;
7773 }
9a799d71 7774
082757af
DS		 7775 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7776 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7777 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7778 netdev->features |= NETIF_F_LRO;
7779
9a799d71 7780 /* make sure the EEPROM is good */
c44ade9e 7781 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7782 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7783 err = -EIO;
7784 goto err_eeprom;
7785 }
7786
7787 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7788 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7789
c44ade9e 7790 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7791 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7792 err = -EIO;
7793 goto err_eeprom;
7794 }
7795
7086400d
AD		 7796 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7797 (unsigned long) adapter);
9a799d71 7798
7086400d
AD		 7799 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7800 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7801
021230d4
AV		 7802 err = ixgbe_init_interrupt_scheme(adapter);
7803 if (err)
7804 goto err_sw_init;
9a799d71 7805
082757af
DS		 7806 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7807 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7808 netdev->features &= ~NETIF_F_RXHASH;
082757af 7809 }
67a74ee2 7810
c23f5b6b
ET		 7811 /* WOL not supported for all but the following */
7812 adapter->wol = 0;
e8e26350 7813 switch (pdev->device) {
0b077fea 7814 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7815 /* Only these subdevice supports WOL */
7816 switch (pdev->subsystem_device) {
7817 case IXGBE_SUBDEV_ID_82599_560FLR:
7818 /* only support first port */
7819 if (hw->bus.func != 0)
7820 break;
7821 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7822 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7823 break;
7824 }
0b077fea 7825 break;
50d6c681
AD		 7826 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7827 /* All except this subdevice support WOL */
0b077fea 7828 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7829 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7830 break;
e8e26350 7831 case IXGBE_DEV_ID_82599_KX4:
9417c464 7832 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7833 break;
c23f5b6b
ET		 7834 case IXGBE_DEV_ID_X540T:
7835 /* Check eeprom to see if it is enabled */
7836 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7837 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7838
7839 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7840 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7841 (hw->bus.func == 0)))
7842 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7843 break;
7844 }
e8e26350
PW		 7845 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7846
15e5209f
ET		 7847 /* save off EEPROM version number */
7848 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7849 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7850
04f165ef
PW		 7851 /* pick up the PCI bus settings for reporting later */
7852 hw->mac.ops.get_bus_info(hw);
7853
9a799d71 7854 /* print bus type/speed/width info */
849c4542 7855 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7856 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7857 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7858 "Unknown"),
7859 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7860 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7861 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7862 "Unknown"),
7863 netdev->dev_addr);
289700db
DS		 7864
7865 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7866 if (err)
9fe93afd 7867 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7868 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7869 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7870 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7871 part_str);
e8e26350 7872 else
289700db
DS		 7873 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7874 hw->mac.type, hw->phy.type, part_str);
9a799d71 7875
e8e26350 7876 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7877 e_dev_warn("PCI-Express bandwidth available for this card is "
7878 "not sufficient for optimal performance.\n");
7879 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7880 "is required.\n");
0c254d86
AK		 7881 }
7882
9a799d71 7883 /* reset the hardware with the new settings */
794caeb2 7884 err = hw->mac.ops.start_hw(hw);
c44ade9e 7885
794caeb2
PWJ		 7886 if (err == IXGBE_ERR_EEPROM_VERSION) {
7887 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7888 e_dev_warn("This device is a pre-production adapter/LOM. "
7889 "Please be aware there may be issues associated "
7890 "with your hardware. If you are experiencing "
7891 "problems please contact your Intel or hardware "
7892 "representative who provided you with this "
7893 "hardware.\n");
794caeb2 7894 }
9a799d71
AK		 7895 strcpy(netdev->name, "eth%d");
7896 err = register_netdev(netdev);
7897 if (err)
7898 goto err_register;
7899
93d3ce8f
ET		 7900 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7901 if (hw->mac.ops.disable_tx_laser &&
7902 ((hw->phy.multispeed_fiber) ||
7903 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7904 (hw->mac.type == ixgbe_mac_82599EB))))
7905 hw->mac.ops.disable_tx_laser(hw);
7906
54386467
JB		 7907 /* carrier off reporting is important to ethtool even BEFORE open */
7908 netif_carrier_off(netdev);
7909
5dd2d332 7910#ifdef CONFIG_IXGBE_DCA
652f093f 7911 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7912 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7913 ixgbe_setup_dca(adapter);
7914 }
7915#endif
1cdd1ec8 7916 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7917 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7918 for (i = 0; i < adapter->num_vfs; i++)
7919 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7920 }
7921
2466dd9c
JK		 7922 /* firmware requires driver version to be 0xFFFFFFFF
7923 * since os does not support feature
7924 */
9612de92 7925 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7926 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7927 0xFF);
9612de92 7928
0365e6e4
PW		 7929 /* add san mac addr to netdev */
7930 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7931
ea81875a 7932 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 7933 cards_found++;
7934 return 0;
7935
7936err_register:
5eba3699 7937 ixgbe_release_hw_control(adapter);
7a921c93 7938 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7939err_sw_init:
7940err_eeprom:
1cdd1ec8
GR		 7941 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7942 ixgbe_disable_sriov(adapter);
7086400d 7943 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7944 iounmap(hw->hw_addr);
7945err_ioremap:
7946 free_netdev(netdev);
7947err_alloc_etherdev:
e8e9f696
JP		 7948 pci_release_selected_regions(pdev,
7949 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7950err_pci_reg:
7951err_dma:
7952 pci_disable_device(pdev);
7953 return err;
7954}
7955
7956/**
7957 * ixgbe_remove - Device Removal Routine
7958 * @pdev: PCI device information struct
7959 *
7960 * ixgbe_remove is called by the PCI subsystem to alert the driver
7961 * that it should release a PCI device. The could be caused by a
7962 * Hot-Plug event, or because the driver is going to be removed from
7963 * memory.
7964 **/
7965static void __devexit ixgbe_remove(struct pci_dev *pdev)
7966{
c60fbb00
AD		 7967 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7968 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7969
7970 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7971 cancel_work_sync(&adapter->service_task);
9a799d71 7972
5dd2d332 7973#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7974 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7975 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7976 dca_remove_requester(&pdev->dev);
7977 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7978 }
7979
7980#endif
332d4a7d
YZ		 7981#ifdef IXGBE_FCOE
7982 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7983 ixgbe_cleanup_fcoe(adapter);
7984
7985#endif /* IXGBE_FCOE */
0365e6e4
PW		 7986
7987 /* remove the added san mac */
7988 ixgbe_del_sanmac_netdev(netdev);
7989
c4900be0
DS		 7990 if (netdev->reg_state == NETREG_REGISTERED)
7991 unregister_netdev(netdev);
9a799d71 7992
c6bda30a
GR		 7993 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7994 if (!(ixgbe_check_vf_assignment(adapter)))
7995 ixgbe_disable_sriov(adapter);
7996 else
7997 e_dev_warn("Unloading driver while VFs are assigned "
7998 "- VFs will not be deallocated\n");
7999 }
1cdd1ec8 8000
7a921c93 8001 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8002
021230d4 8003 ixgbe_release_hw_control(adapter);
9a799d71
AK		 8004
8005 iounmap(adapter->hw.hw_addr);
9ce77666 8006 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8007 IORESOURCE_MEM));
9a799d71 8008
849c4542 8009 e_dev_info("complete\n");
021230d4 8010
9a799d71
AK		 8011 free_netdev(netdev);
8012
19d5afd4 8013 pci_disable_pcie_error_reporting(pdev);
6fabd715 8014
9a799d71
AK		 8015 pci_disable_device(pdev);
8016}
8017
8018/**
8019 * ixgbe_io_error_detected - called when PCI error is detected
8020 * @pdev: Pointer to PCI device
8021 * @state: The current pci connection state
8022 *
8023 * This function is called after a PCI bus error affecting
8024 * this device has been detected.
8025 */
8026static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8027 pci_channel_state_t state)
9a799d71 8028{
c60fbb00
AD		 8029 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8030 struct net_device *netdev = adapter->netdev;
9a799d71 8031
83c61fa9
GR		 8032#ifdef CONFIG_PCI_IOV
8033 struct pci_dev *bdev, *vfdev;
8034 u32 dw0, dw1, dw2, dw3;
8035 int vf, pos;
8036 u16 req_id, pf_func;
8037
8038 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8039 adapter->num_vfs == 0)
8040 goto skip_bad_vf_detection;
8041
8042 bdev = pdev->bus->self;
8043 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
8044 bdev = bdev->bus->self;
8045
8046 if (!bdev)
8047 goto skip_bad_vf_detection;
8048
8049 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8050 if (!pos)
8051 goto skip_bad_vf_detection;
8052
8053 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8054 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8055 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8056 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8057
8058 req_id = dw1 >> 16;
8059 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8060 if (!(req_id & 0x0080))
8061 goto skip_bad_vf_detection;
8062
8063 pf_func = req_id & 0x01;
8064 if ((pf_func & 1) == (pdev->devfn & 1)) {
8065 unsigned int device_id;
8066
8067 vf = (req_id & 0x7F) >> 1;
8068 e_dev_err("VF %d has caused a PCIe error\n", vf);
8069 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8070 "%8.8x\tdw3: %8.8x\n",
8071 dw0, dw1, dw2, dw3);
8072 switch (adapter->hw.mac.type) {
8073 case ixgbe_mac_82599EB:
8074 device_id = IXGBE_82599_VF_DEVICE_ID;
8075 break;
8076 case ixgbe_mac_X540:
8077 device_id = IXGBE_X540_VF_DEVICE_ID;
8078 break;
8079 default:
8080 device_id = 0;
8081 break;
8082 }
8083
8084 /* Find the pci device of the offending VF */
8085 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
8086 while (vfdev) {
8087 if (vfdev->devfn == (req_id & 0xFF))
8088 break;
8089 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
8090 device_id, vfdev);
8091 }
8092 /*
8093 * There's a slim chance the VF could have been hot plugged,
8094 * so if it is no longer present we don't need to issue the
8095 * VFLR. Just clean up the AER in that case.
8096 */
8097 if (vfdev) {
8098 e_dev_err("Issuing VFLR to VF %d\n", vf);
8099 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8100 }
8101
8102 pci_cleanup_aer_uncorrect_error_status(pdev);
8103 }
8104
8105 /*
8106 * Even though the error may have occurred on the other port
8107 * we still need to increment the vf error reference count for
8108 * both ports because the I/O resume function will be called
8109 * for both of them.
8110 */
8111 adapter->vferr_refcount++;
8112
8113 return PCI_ERS_RESULT_RECOVERED;
8114
8115skip_bad_vf_detection:
8116#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8117 netif_device_detach(netdev);
8118
3044b8d1
BL		 8119 if (state == pci_channel_io_perm_failure)
8120 return PCI_ERS_RESULT_DISCONNECT;
8121
9a799d71
AK		 8122 if (netif_running(netdev))
8123 ixgbe_down(adapter);
8124 pci_disable_device(pdev);
8125
b4617240 8126 /* Request a slot reset. */
9a799d71
AK		 8127 return PCI_ERS_RESULT_NEED_RESET;
8128}
8129
8130/**
8131 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8132 * @pdev: Pointer to PCI device
8133 *
8134 * Restart the card from scratch, as if from a cold-boot.
8135 */
8136static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8137{
c60fbb00 8138 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8139 pci_ers_result_t result;
8140 int err;
9a799d71 8141
9ce77666 8142 if (pci_enable_device_mem(pdev)) {
396e799c 8143 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8144 result = PCI_ERS_RESULT_DISCONNECT;
8145 } else {
8146 pci_set_master(pdev);
8147 pci_restore_state(pdev);
c0e1f68b 8148 pci_save_state(pdev);
9a799d71 8149
dd4d8ca6 8150 pci_wake_from_d3(pdev, false);
9a799d71 8151
6fabd715 8152 ixgbe_reset(adapter);
88512539 8153 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8154 result = PCI_ERS_RESULT_RECOVERED;
8155 }
8156
8157 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8158 if (err) {
849c4542
ET		 8159 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8160 "failed 0x%0x\n", err);
6fabd715
PWJ		 8161 /* non-fatal, continue */
8162 }
9a799d71 8163
6fabd715 8164 return result;
9a799d71
AK		 8165}
8166
8167/**
8168 * ixgbe_io_resume - called when traffic can start flowing again.
8169 * @pdev: Pointer to PCI device
8170 *
8171 * This callback is called when the error recovery driver tells us that
8172 * its OK to resume normal operation.
8173 */
8174static void ixgbe_io_resume(struct pci_dev *pdev)
8175{
c60fbb00
AD		 8176 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8177 struct net_device *netdev = adapter->netdev;
9a799d71 8178
83c61fa9
GR		 8179#ifdef CONFIG_PCI_IOV
8180 if (adapter->vferr_refcount) {
8181 e_info(drv, "Resuming after VF err\n");
8182 adapter->vferr_refcount--;
8183 return;
8184 }
8185
8186#endif
c7ccde0f
AD		 8187 if (netif_running(netdev))
8188 ixgbe_up(adapter);
9a799d71
AK		 8189
8190 netif_device_attach(netdev);
9a799d71
AK		 8191}
8192
8193static struct pci_error_handlers ixgbe_err_handler = {
8194 .error_detected = ixgbe_io_error_detected,
8195 .slot_reset = ixgbe_io_slot_reset,
8196 .resume = ixgbe_io_resume,
8197};
8198
8199static struct pci_driver ixgbe_driver = {
8200 .name = ixgbe_driver_name,
8201 .id_table = ixgbe_pci_tbl,
8202 .probe = ixgbe_probe,
8203 .remove = __devexit_p(ixgbe_remove),
8204#ifdef CONFIG_PM
8205 .suspend = ixgbe_suspend,
8206 .resume = ixgbe_resume,
8207#endif
8208 .shutdown = ixgbe_shutdown,
8209 .err_handler = &ixgbe_err_handler
8210};
8211
8212/**
8213 * ixgbe_init_module - Driver Registration Routine
8214 *
8215 * ixgbe_init_module is the first routine called when the driver is
8216 * loaded. All it does is register with the PCI subsystem.
8217 **/
8218static int __init ixgbe_init_module(void)
8219{
8220 int ret;
c7689578 8221 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8222 pr_info("%s\n", ixgbe_copyright);
9a799d71 8223
5dd2d332 8224#ifdef CONFIG_IXGBE_DCA
bd0362dd 8225 dca_register_notify(&dca_notifier);
bd0362dd 8226#endif
5dd2d332 8227
9a799d71
AK		 8228 ret = pci_register_driver(&ixgbe_driver);
8229 return ret;
8230}
b4617240 8231
9a799d71
AK		 8232module_init(ixgbe_init_module);
8233
8234/**
8235 * ixgbe_exit_module - Driver Exit Cleanup Routine
8236 *
8237 * ixgbe_exit_module is called just before the driver is removed
8238 * from memory.
8239 **/
8240static void __exit ixgbe_exit_module(void)
8241{
5dd2d332 8242#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8243 dca_unregister_notify(&dca_notifier);
8244#endif
9a799d71 8245 pci_unregister_driver(&ixgbe_driver);
1a51502b 8246 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8247}
bd0362dd 8248
5dd2d332 8249#ifdef CONFIG_IXGBE_DCA
bd0362dd 8250static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8251 void *p)
bd0362dd
JC		 8252{
8253 int ret_val;
8254
8255 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8256 __ixgbe_notify_dca);
bd0362dd
JC		 8257
8258 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8259}
b453368d 8260
5dd2d332 8261#endif /* CONFIG_IXGBE_DCA */
849c4542 8262
9a799d71
AK		 8263module_exit(ixgbe_exit_module);
8264
8265/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)