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igb: Fix for devices using ethtool for EEE settings
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
2a47fa45 47#include <linux/if_macvlan.h>
815cccbf 48#include <linux/if_bridge.h>
70c71606 49#include <linux/prefetch.h>
eacd73f7 50#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 51
52#include "ixgbe.h"
53#include "ixgbe_common.h"
ee5f784a 54#include "ixgbe_dcb_82599.h"
1cdd1ec8 55#include "ixgbe_sriov.h"
9a799d71
AK		 56
57char ixgbe_driver_name[] = "ixgbe";
9c8eb720 58static const char ixgbe_driver_string[] =
e8e9f696 59 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 60#ifdef IXGBE_FCOE
ea81875a
NP		 61char ixgbe_default_device_descr[] =
62 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 63#else
64static char ixgbe_default_device_descr[] =
65 "Intel(R) 10 Gigabit Network Connection";
66#endif
f341c4e0 67#define DRV_VERSION "3.19.1-k"
9c8eb720 68const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 69static const char ixgbe_copyright[] =
0391bbe3 70 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 71
72static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 73 [board_82598] = &ixgbe_82598_info,
e8e26350 74 [board_82599] = &ixgbe_82599_info,
fe15e8e1 75 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 76};
77
78/* ixgbe_pci_tbl - PCI Device ID Table
79 *
80 * Wildcard entries (PCI_ANY_ID) should come last
81 * Last entry must be all 0s
82 *
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
85 */
a3aa1884 86static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
170e8543 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
14438464
MR		 154static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
155
b8e82001
JK		 156static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
157 u32 reg, u16 *value)
158{
b8e82001
JK		 159 struct pci_dev *parent_dev;
160 struct pci_bus *parent_bus;
161
162 parent_bus = adapter->pdev->bus->parent;
163 if (!parent_bus)
164 return -1;
165
166 parent_dev = parent_bus->self;
167 if (!parent_dev)
168 return -1;
169
c0798edf 170 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 171 return -1;
172
c0798edf 173 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 174 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
175 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
176 return -1;
b8e82001
JK		 177 return 0;
178}
179
180static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
181{
182 struct ixgbe_hw *hw = &adapter->hw;
183 u16 link_status = 0;
184 int err;
185
186 hw->bus.type = ixgbe_bus_type_pci_express;
187
188 /* Get the negotiated link width and speed from PCI config space of the
189 * parent, as this device is behind a switch
190 */
191 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
192
193 /* assume caller will handle error case */
194 if (err)
195 return err;
196
197 hw->bus.width = ixgbe_convert_bus_width(link_status);
198 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
199
200 return 0;
201}
202
e027d1ae
JK		 203/**
204 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
205 * @hw: hw specific details
206 *
207 * This function is used by probe to determine whether a device's PCI-Express
208 * bandwidth details should be gathered from the parent bus instead of from the
209 * device. Used to ensure that various locations all have the correct device ID
210 * checks.
211 */
212static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
213{
214 switch (hw->device_id) {
215 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 216 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 217 return true;
218 default:
219 return false;
220 }
221}
222
223static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
224 int expected_gts)
225{
226 int max_gts = 0;
227 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
228 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
229 struct pci_dev *pdev;
230
231 /* determine whether to use the the parent device
232 */
233 if (ixgbe_pcie_from_parent(&adapter->hw))
234 pdev = adapter->pdev->bus->parent->self;
235 else
236 pdev = adapter->pdev;
237
238 if (pcie_get_minimum_link(pdev, &speed, &width) ||
239 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
240 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
241 return;
242 }
243
244 switch (speed) {
245 case PCIE_SPEED_2_5GT:
246 /* 8b/10b encoding reduces max throughput by 20% */
247 max_gts = 2 * width;
248 break;
249 case PCIE_SPEED_5_0GT:
250 /* 8b/10b encoding reduces max throughput by 20% */
251 max_gts = 4 * width;
252 break;
253 case PCIE_SPEED_8_0GT:
9f0a433c 254 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 255 max_gts = 8 * width;
256 break;
257 default:
258 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
259 return;
260 }
261
262 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
263 max_gts);
264 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
265 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
266 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
267 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
268 "Unknown"),
269 width,
270 (speed == PCIE_SPEED_2_5GT ? "20%" :
271 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 272 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 273 "Unknown"));
274
275 if (max_gts < expected_gts) {
276 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
277 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
278 expected_gts);
279 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
280 }
281}
282
7086400d
AD		 283static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
284{
285 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 286 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 287 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
288 schedule_work(&adapter->service_task);
289}
290
2a1a091c
MR		 291static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
292{
293 struct ixgbe_adapter *adapter = hw->back;
294
295 if (!hw->hw_addr)
296 return;
297 hw->hw_addr = NULL;
298 e_dev_err("Adapter removed\n");
b0483c8f 299 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 300}
301
302void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
303{
304 u32 value;
305
306 /* The following check not only optimizes a bit by not
307 * performing a read on the status register when the
308 * register just read was a status register read that
309 * returned IXGBE_FAILED_READ_REG. It also blocks any
310 * potential recursion.
311 */
312 if (reg == IXGBE_STATUS) {
313 ixgbe_remove_adapter(hw);
314 return;
315 }
316 value = ixgbe_read_reg(hw, IXGBE_STATUS);
317 if (value == IXGBE_FAILED_READ_REG)
318 ixgbe_remove_adapter(hw);
319}
320
14438464
MR		 321static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
322{
323 u16 value;
324
325 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
326 if (value == IXGBE_FAILED_READ_CFG_WORD) {
327 ixgbe_remove_adapter(hw);
328 return true;
329 }
330 return false;
331}
332
333u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
334{
335 struct ixgbe_adapter *adapter = hw->back;
336 u16 value;
337
338 if (ixgbe_removed(hw->hw_addr))
339 return IXGBE_FAILED_READ_CFG_WORD;
340 pci_read_config_word(adapter->pdev, reg, &value);
341 if (value == IXGBE_FAILED_READ_CFG_WORD &&
342 ixgbe_check_cfg_remove(hw, adapter->pdev))
343 return IXGBE_FAILED_READ_CFG_WORD;
344 return value;
345}
346
347#ifdef CONFIG_PCI_IOV
348static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
349{
350 struct ixgbe_adapter *adapter = hw->back;
351 u32 value;
352
353 if (ixgbe_removed(hw->hw_addr))
354 return IXGBE_FAILED_READ_CFG_DWORD;
355 pci_read_config_dword(adapter->pdev, reg, &value);
356 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
357 ixgbe_check_cfg_remove(hw, adapter->pdev))
358 return IXGBE_FAILED_READ_CFG_DWORD;
359 return value;
360}
361#endif /* CONFIG_PCI_IOV */
362
7086400d
AD		 363static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
364{
365 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
366
52f33af8 367 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 368 smp_mb__before_clear_bit();
369 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
370}
371
dcd79aeb
TI		 372struct ixgbe_reg_info {
373 u32 ofs;
374 char *name;
375};
376
377static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
378
379 /* General Registers */
380 {IXGBE_CTRL, "CTRL"},
381 {IXGBE_STATUS, "STATUS"},
382 {IXGBE_CTRL_EXT, "CTRL_EXT"},
383
384 /* Interrupt Registers */
385 {IXGBE_EICR, "EICR"},
386
387 /* RX Registers */
388 {IXGBE_SRRCTL(0), "SRRCTL"},
389 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
390 {IXGBE_RDLEN(0), "RDLEN"},
391 {IXGBE_RDH(0), "RDH"},
392 {IXGBE_RDT(0), "RDT"},
393 {IXGBE_RXDCTL(0), "RXDCTL"},
394 {IXGBE_RDBAL(0), "RDBAL"},
395 {IXGBE_RDBAH(0), "RDBAH"},
396
397 /* TX Registers */
398 {IXGBE_TDBAL(0), "TDBAL"},
399 {IXGBE_TDBAH(0), "TDBAH"},
400 {IXGBE_TDLEN(0), "TDLEN"},
401 {IXGBE_TDH(0), "TDH"},
402 {IXGBE_TDT(0), "TDT"},
403 {IXGBE_TXDCTL(0), "TXDCTL"},
404
405 /* List Terminator */
406 {}
407};
408
409
410/*
411 * ixgbe_regdump - register printout routine
412 */
413static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
414{
415 int i = 0, j = 0;
416 char rname[16];
417 u32 regs[64];
418
419 switch (reginfo->ofs) {
420 case IXGBE_SRRCTL(0):
421 for (i = 0; i < 64; i++)
422 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
423 break;
424 case IXGBE_DCA_RXCTRL(0):
425 for (i = 0; i < 64; i++)
426 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
427 break;
428 case IXGBE_RDLEN(0):
429 for (i = 0; i < 64; i++)
430 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
431 break;
432 case IXGBE_RDH(0):
433 for (i = 0; i < 64; i++)
434 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
435 break;
436 case IXGBE_RDT(0):
437 for (i = 0; i < 64; i++)
438 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
439 break;
440 case IXGBE_RXDCTL(0):
441 for (i = 0; i < 64; i++)
442 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
443 break;
444 case IXGBE_RDBAL(0):
445 for (i = 0; i < 64; i++)
446 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
447 break;
448 case IXGBE_RDBAH(0):
449 for (i = 0; i < 64; i++)
450 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
451 break;
452 case IXGBE_TDBAL(0):
453 for (i = 0; i < 64; i++)
454 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
455 break;
456 case IXGBE_TDBAH(0):
457 for (i = 0; i < 64; i++)
458 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
459 break;
460 case IXGBE_TDLEN(0):
461 for (i = 0; i < 64; i++)
462 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
463 break;
464 case IXGBE_TDH(0):
465 for (i = 0; i < 64; i++)
466 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
467 break;
468 case IXGBE_TDT(0):
469 for (i = 0; i < 64; i++)
470 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
471 break;
472 case IXGBE_TXDCTL(0):
473 for (i = 0; i < 64; i++)
474 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
475 break;
476 default:
c7689578 477 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 478 IXGBE_READ_REG(hw, reginfo->ofs));
479 return;
480 }
481
482 for (i = 0; i < 8; i++) {
483 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 484 pr_err("%-15s", rname);
dcd79aeb 485 for (j = 0; j < 8; j++)
c7689578
JP		 486 pr_cont(" %08x", regs[i*8+j]);
487 pr_cont("\n");
dcd79aeb
TI		 488 }
489
490}
491
492/*
493 * ixgbe_dump - Print registers, tx-rings and rx-rings
494 */
495static void ixgbe_dump(struct ixgbe_adapter *adapter)
496{
497 struct net_device *netdev = adapter->netdev;
498 struct ixgbe_hw *hw = &adapter->hw;
499 struct ixgbe_reg_info *reginfo;
500 int n = 0;
501 struct ixgbe_ring *tx_ring;
729739b7 502 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 503 union ixgbe_adv_tx_desc *tx_desc;
504 struct my_u0 { u64 a; u64 b; } *u0;
505 struct ixgbe_ring *rx_ring;
506 union ixgbe_adv_rx_desc *rx_desc;
507 struct ixgbe_rx_buffer *rx_buffer_info;
508 u32 staterr;
509 int i = 0;
510
511 if (!netif_msg_hw(adapter))
512 return;
513
514 /* Print netdevice Info */
515 if (netdev) {
516 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 517 pr_info("Device Name state "
dcd79aeb 518 "trans_start last_rx\n");
c7689578
JP		 519 pr_info("%-15s %016lX %016lX %016lX\n",
520 netdev->name,
521 netdev->state,
522 netdev->trans_start,
523 netdev->last_rx);
dcd79aeb
TI		 524 }
525
526 /* Print Registers */
527 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 528 pr_info(" Register Name Value\n");
dcd79aeb
TI		 529 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
530 reginfo->name; reginfo++) {
531 ixgbe_regdump(hw, reginfo);
532 }
533
534 /* Print TX Ring Summary */
535 if (!netdev || !netif_running(netdev))
536 goto exit;
537
538 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 539 pr_info(" %s %s %s %s\n",
540 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
541 "leng", "ntw", "timestamp");
dcd79aeb
TI		 542 for (n = 0; n < adapter->num_tx_queues; n++) {
543 tx_ring = adapter->tx_ring[n];
729739b7 544 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 545 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 546 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 547 (u64)dma_unmap_addr(tx_buffer, dma),
548 dma_unmap_len(tx_buffer, len),
549 tx_buffer->next_to_watch,
550 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 551 }
552
553 /* Print TX Rings */
554 if (!netif_msg_tx_done(adapter))
555 goto rx_ring_summary;
556
557 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
558
559 /* Transmit Descriptor Formats
560 *
39ac868a 561 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 562 * +--------------------------------------------------------------+
563 * 0 | Buffer Address [63:0] |
564 * +--------------------------------------------------------------+
39ac868a 565 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 566 * +--------------------------------------------------------------+
567 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 568 *
569 * 82598 Advanced Transmit Descriptor (Write-Back Format)
570 * +--------------------------------------------------------------+
571 * 0 | RSV [63:0] |
572 * +--------------------------------------------------------------+
573 * 8 | RSV | STA | NXTSEQ |
574 * +--------------------------------------------------------------+
575 * 63 36 35 32 31 0
576 *
577 * 82599+ Advanced Transmit Descriptor
578 * +--------------------------------------------------------------+
579 * 0 | Buffer Address [63:0] |
580 * +--------------------------------------------------------------+
581 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
582 * +--------------------------------------------------------------+
583 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
584 *
585 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
586 * +--------------------------------------------------------------+
587 * 0 | RSV [63:0] |
588 * +--------------------------------------------------------------+
589 * 8 | RSV | STA | RSV |
590 * +--------------------------------------------------------------+
591 * 63 36 35 32 31 0
dcd79aeb
TI		 592 */
593
594 for (n = 0; n < adapter->num_tx_queues; n++) {
595 tx_ring = adapter->tx_ring[n];
c7689578
JP		 596 pr_info("------------------------------------\n");
597 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
598 pr_info("------------------------------------\n");
8ad88e37
JH		 599 pr_info("%s%s %s %s %s %s\n",
600 "T [desc] [address 63:0 ] ",
601 "[PlPOIdStDDt Ln] [bi->dma ] ",
602 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 603
604 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 605 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 606 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 607 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 608 if (dma_unmap_len(tx_buffer, len) > 0) {
609 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
610 i,
611 le64_to_cpu(u0->a),
612 le64_to_cpu(u0->b),
613 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 614 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp,
617 tx_buffer->skb);
618 if (i == tx_ring->next_to_use &&
619 i == tx_ring->next_to_clean)
620 pr_cont(" NTC/U\n");
621 else if (i == tx_ring->next_to_use)
622 pr_cont(" NTU\n");
623 else if (i == tx_ring->next_to_clean)
624 pr_cont(" NTC\n");
625 else
626 pr_cont("\n");
627
628 if (netif_msg_pktdata(adapter) &&
629 tx_buffer->skb)
630 print_hex_dump(KERN_INFO, "",
631 DUMP_PREFIX_ADDRESS, 16, 1,
632 tx_buffer->skb->data,
633 dma_unmap_len(tx_buffer, len),
634 true);
635 }
dcd79aeb
TI		 636 }
637 }
638
639 /* Print RX Rings Summary */
640rx_ring_summary:
641 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 642 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 643 for (n = 0; n < adapter->num_rx_queues; n++) {
644 rx_ring = adapter->rx_ring[n];
c7689578
JP		 645 pr_info("%5d %5X %5X\n",
646 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 647 }
648
649 /* Print RX Rings */
650 if (!netif_msg_rx_status(adapter))
651 goto exit;
652
653 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
654
39ac868a
JH		 655 /* Receive Descriptor Formats
656 *
657 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 658 * 63 1 0
659 * +-----------------------------------------------------+
660 * 0 | Packet Buffer Address [63:1] |A0/NSE|
661 * +----------------------------------------------+------+
662 * 8 | Header Buffer Address [63:1] | DD |
663 * +-----------------------------------------------------+
664 *
665 *
39ac868a 666 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 667 *
668 * 63 48 47 32 31 30 21 20 16 15 4 3 0
669 * +------------------------------------------------------+
39ac868a
JH		 670 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
671 * | Packet | IP | | | | Type | Type |
672 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 673 * +------------------------------------------------------+
674 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
675 * +------------------------------------------------------+
676 * 63 48 47 32 31 20 19 0
39ac868a
JH		 677 *
678 * 82599+ Advanced Receive Descriptor (Read) Format
679 * 63 1 0
680 * +-----------------------------------------------------+
681 * 0 | Packet Buffer Address [63:1] |A0/NSE|
682 * +----------------------------------------------+------+
683 * 8 | Header Buffer Address [63:1] | DD |
684 * +-----------------------------------------------------+
685 *
686 *
687 * 82599+ Advanced Receive Descriptor (Write-Back) Format
688 *
689 * 63 48 47 32 31 30 21 20 17 16 4 3 0
690 * +------------------------------------------------------+
691 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
692 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
693 * |/ Flow Dir Flt ID | | | | | |
694 * +------------------------------------------------------+
695 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
696 * +------------------------------------------------------+
697 * 63 48 47 32 31 20 19 0
dcd79aeb 698 */
39ac868a 699
dcd79aeb
TI		 700 for (n = 0; n < adapter->num_rx_queues; n++) {
701 rx_ring = adapter->rx_ring[n];
c7689578
JP		 702 pr_info("------------------------------------\n");
703 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
704 pr_info("------------------------------------\n");
8ad88e37
JH		 705 pr_info("%s%s%s",
706 "R [desc] [ PktBuf A0] ",
707 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 708 "<-- Adv Rx Read format\n");
8ad88e37
JH		 709 pr_info("%s%s%s",
710 "RWB[desc] [PcsmIpSHl PtRs] ",
711 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 712 "<-- Adv Rx Write-Back format\n");
713
714 for (i = 0; i < rx_ring->count; i++) {
715 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 716 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 717 u0 = (struct my_u0 *)rx_desc;
718 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
719 if (staterr & IXGBE_RXD_STAT_DD) {
720 /* Descriptor Done */
c7689578 721 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 722 "%016llX ---------------- %p", i,
723 le64_to_cpu(u0->a),
724 le64_to_cpu(u0->b),
725 rx_buffer_info->skb);
726 } else {
c7689578 727 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 728 "%016llX %016llX %p", i,
729 le64_to_cpu(u0->a),
730 le64_to_cpu(u0->b),
731 (u64)rx_buffer_info->dma,
732 rx_buffer_info->skb);
733
9c50c035
ET		 734 if (netif_msg_pktdata(adapter) &&
735 rx_buffer_info->dma) {
dcd79aeb
TI		 736 print_hex_dump(KERN_INFO, "",
737 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 738 page_address(rx_buffer_info->page) +
739 rx_buffer_info->page_offset,
f800326d 740 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 741 }
742 }
743
744 if (i == rx_ring->next_to_use)
c7689578 745 pr_cont(" NTU\n");
dcd79aeb 746 else if (i == rx_ring->next_to_clean)
c7689578 747 pr_cont(" NTC\n");
dcd79aeb 748 else
c7689578 749 pr_cont("\n");
dcd79aeb
TI		 750
751 }
752 }
753
754exit:
755 return;
756}
757
5eba3699
AV		 758static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
759{
760 u32 ctrl_ext;
761
762 /* Let firmware take over control of h/w */
763 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 765 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 766}
767
768static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
769{
770 u32 ctrl_ext;
771
772 /* Let firmware know the driver has taken over */
773 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 775 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 776}
9a799d71 777
49ce9c2c 778/**
e8e26350
PW		 779 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
780 * @adapter: pointer to adapter struct
781 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
782 * @queue: queue to map the corresponding interrupt to
783 * @msix_vector: the vector to map to the corresponding queue
784 *
785 */
786static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 787 u8 queue, u8 msix_vector)
9a799d71
AK		 788{
789 u32 ivar, index;
e8e26350
PW		 790 struct ixgbe_hw *hw = &adapter->hw;
791 switch (hw->mac.type) {
792 case ixgbe_mac_82598EB:
793 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
794 if (direction == -1)
795 direction = 0;
796 index = (((direction * 64) + queue) >> 2) & 0x1F;
797 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
798 ivar &= ~(0xFF << (8 * (queue & 0x3)));
799 ivar |= (msix_vector << (8 * (queue & 0x3)));
800 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
801 break;
802 case ixgbe_mac_82599EB:
b93a2226 803 case ixgbe_mac_X540:
e8e26350
PW		 804 if (direction == -1) {
805 /* other causes */
806 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
807 index = ((queue & 1) * 8);
808 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
809 ivar &= ~(0xFF << index);
810 ivar |= (msix_vector << index);
811 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
812 break;
813 } else {
814 /* tx or rx causes */
815 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
816 index = ((16 * (queue & 1)) + (8 * direction));
817 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
818 ivar &= ~(0xFF << index);
819 ivar |= (msix_vector << index);
820 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
821 break;
822 }
823 default:
824 break;
825 }
9a799d71
AK		 826}
827
fe49f04a 828static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 829 u64 qmask)
fe49f04a
AD		 830{
831 u32 mask;
832
bd508178
AD		 833 switch (adapter->hw.mac.type) {
834 case ixgbe_mac_82598EB:
fe49f04a
AD		 835 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 837 break;
838 case ixgbe_mac_82599EB:
b93a2226 839 case ixgbe_mac_X540:
fe49f04a
AD		 840 mask = (qmask & 0xFFFFFFFF);
841 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
842 mask = (qmask >> 32);
843 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 844 break;
845 default:
846 break;
fe49f04a
AD		 847 }
848}
849
729739b7
AD		 850void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
851 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 852{
729739b7
AD		 853 if (tx_buffer->skb) {
854 dev_kfree_skb_any(tx_buffer->skb);
855 if (dma_unmap_len(tx_buffer, len))
d3d00239 856 dma_unmap_single(ring->dev,
729739b7
AD		 857 dma_unmap_addr(tx_buffer, dma),
858 dma_unmap_len(tx_buffer, len),
859 DMA_TO_DEVICE);
860 } else if (dma_unmap_len(tx_buffer, len)) {
861 dma_unmap_page(ring->dev,
862 dma_unmap_addr(tx_buffer, dma),
863 dma_unmap_len(tx_buffer, len),
864 DMA_TO_DEVICE);
e5a43549 865 }
729739b7
AD		 866 tx_buffer->next_to_watch = NULL;
867 tx_buffer->skb = NULL;
868 dma_unmap_len_set(tx_buffer, len, 0);
869 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 870}
871
943561d3 872static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 873{
874 struct ixgbe_hw *hw = &adapter->hw;
875 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 876 int i;
943561d3 877 u32 data;
c84d324c 878
943561d3
AD		 879 if ((hw->fc.current_mode != ixgbe_fc_full) &&
880 (hw->fc.current_mode != ixgbe_fc_rx_pause))
881 return;
c84d324c 882
943561d3
AD		 883 switch (hw->mac.type) {
884 case ixgbe_mac_82598EB:
885 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
886 break;
887 default:
888 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
889 }
890 hwstats->lxoffrxc += data;
c84d324c 891
943561d3
AD		 892 /* refill credits (no tx hang) if we received xoff */
893 if (!data)
c84d324c 894 return;
943561d3
AD		 895
896 for (i = 0; i < adapter->num_tx_queues; i++)
897 clear_bit(__IXGBE_HANG_CHECK_ARMED,
898 &adapter->tx_ring[i]->state);
899}
900
901static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
902{
903 struct ixgbe_hw *hw = &adapter->hw;
904 struct ixgbe_hw_stats *hwstats = &adapter->stats;
905 u32 xoff[8] = {0};
2afaa00d 906 u8 tc;
943561d3
AD		 907 int i;
908 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
909
910 if (adapter->ixgbe_ieee_pfc)
911 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
912
913 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
914 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 915 return;
943561d3 916 }
c84d324c
JF		 917
918 /* update stats for each tc, only valid with PFC enabled */
919 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 920 u32 pxoffrxc;
921
c84d324c
JF		 922 switch (hw->mac.type) {
923 case ixgbe_mac_82598EB:
2afaa00d 924 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 925 break;
c84d324c 926 default:
2afaa00d 927 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 928 }
2afaa00d
PN		 929 hwstats->pxoffrxc[i] += pxoffrxc;
930 /* Get the TC for given UP */
931 tc = netdev_get_prio_tc_map(adapter->netdev, i);
932 xoff[tc] += pxoffrxc;
c84d324c
JF		 933 }
934
935 /* disarm tx queues that have received xoff frames */
936 for (i = 0; i < adapter->num_tx_queues; i++) {
937 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 938
2afaa00d 939 tc = tx_ring->dcb_tc;
c84d324c
JF		 940 if (xoff[tc])
941 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 942 }
26f23d82
YZ		 943}
944
c84d324c 945static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 946{
7d7ce682 947 return ring->stats.packets;
c84d324c
JF		 948}
949
950static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
951{
2a47fa45
JF		 952 struct ixgbe_adapter *adapter;
953 struct ixgbe_hw *hw;
954 u32 head, tail;
955
956 if (ring->l2_accel_priv)
957 adapter = ring->l2_accel_priv->real_adapter;
958 else
959 adapter = netdev_priv(ring->netdev);
e01c31a5 960
2a47fa45
JF		 961 hw = &adapter->hw;
962 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
963 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 964
965 if (head != tail)
966 return (head < tail) ?
967 tail - head : (tail + ring->count - head);
968
969 return 0;
970}
971
972static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
973{
974 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
975 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
976 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
977 bool ret = false;
978
7d637bcc 979 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 980
981 /*
982 * Check for a hung queue, but be thorough. This verifies
983 * that a transmit has been completed since the previous
984 * check AND there is at least one packet pending. The
985 * ARMED bit is set to indicate a potential hang. The
986 * bit is cleared if a pause frame is received to remove
987 * false hang detection due to PFC or 802.3x frames. By
988 * requiring this to fail twice we avoid races with
989 * pfc clearing the ARMED bit and conditions where we
990 * run the check_tx_hang logic with a transmit completion
991 * pending but without time to complete it yet.
992 */
993 if ((tx_done_old == tx_done) && tx_pending) {
994 /* make sure it is true for two checks in a row */
995 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
996 &tx_ring->state);
997 } else {
998 /* update completed stats and continue */
999 tx_ring->tx_stats.tx_done_old = tx_done;
1000 /* reset the countdown */
1001 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 1002 }
1003
c84d324c 1004 return ret;
9a799d71
AK		 1005}
1006
c83c6cbd
AD		 1007/**
1008 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1009 * @adapter: driver private struct
1010 **/
1011static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1012{
1013
1014 /* Do the reset outside of interrupt context */
1015 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1016 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1017 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1018 ixgbe_service_event_schedule(adapter);
1019 }
1020}
e01c31a5 1021
9a799d71
AK		 1022/**
1023 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1024 * @q_vector: structure containing interrupt and ring information
e01c31a5 1025 * @tx_ring: tx ring to clean
9a799d71 1026 **/
fe49f04a 1027static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1028 struct ixgbe_ring *tx_ring)
9a799d71 1029{
fe49f04a 1030 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1031 struct ixgbe_tx_buffer *tx_buffer;
1032 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1033 unsigned int total_bytes = 0, total_packets = 0;
59224555 1034 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1035 unsigned int i = tx_ring->next_to_clean;
1036
1037 if (test_bit(__IXGBE_DOWN, &adapter->state))
1038 return true;
9a799d71 1039
d3d00239 1040 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1041 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1042 i -= tx_ring->count;
12207e49 1043
729739b7 1044 do {
d3d00239
AD		 1045 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1046
1047 /* if next_to_watch is not set then there is no work pending */
1048 if (!eop_desc)
1049 break;
1050
7f83a9e6 1051 /* prevent any other reads prior to eop_desc */
7e63bf49 1052 read_barrier_depends();
7f83a9e6 1053
d3d00239
AD		 1054 /* if DD is not set pending work has not been completed */
1055 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1056 break;
8ad494b0 1057
d3d00239
AD		 1058 /* clear next_to_watch to prevent false hangs */
1059 tx_buffer->next_to_watch = NULL;
8ad494b0 1060
091a6246
AD		 1061 /* update the statistics for this packet */
1062 total_bytes += tx_buffer->bytecount;
1063 total_packets += tx_buffer->gso_segs;
1064
fd0db0ed
AD		 1065 /* free the skb */
1066 dev_kfree_skb_any(tx_buffer->skb);
1067
729739b7
AD		 1068 /* unmap skb header data */
1069 dma_unmap_single(tx_ring->dev,
1070 dma_unmap_addr(tx_buffer, dma),
1071 dma_unmap_len(tx_buffer, len),
1072 DMA_TO_DEVICE);
1073
fd0db0ed
AD		 1074 /* clear tx_buffer data */
1075 tx_buffer->skb = NULL;
729739b7 1076 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1077
729739b7
AD		 1078 /* unmap remaining buffers */
1079 while (tx_desc != eop_desc) {
d3d00239
AD		 1080 tx_buffer++;
1081 tx_desc++;
8ad494b0 1082 i++;
729739b7
AD		 1083 if (unlikely(!i)) {
1084 i -= tx_ring->count;
d3d00239 1085 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1086 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1087 }
e01c31a5 1088
729739b7
AD		 1089 /* unmap any remaining paged data */
1090 if (dma_unmap_len(tx_buffer, len)) {
1091 dma_unmap_page(tx_ring->dev,
1092 dma_unmap_addr(tx_buffer, dma),
1093 dma_unmap_len(tx_buffer, len),
1094 DMA_TO_DEVICE);
1095 dma_unmap_len_set(tx_buffer, len, 0);
1096 }
1097 }
1098
1099 /* move us one more past the eop_desc for start of next pkt */
1100 tx_buffer++;
1101 tx_desc++;
1102 i++;
1103 if (unlikely(!i)) {
1104 i -= tx_ring->count;
1105 tx_buffer = tx_ring->tx_buffer_info;
1106 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1107 }
1108
1109 /* issue prefetch for next Tx descriptor */
1110 prefetch(tx_desc);
12207e49 1111
729739b7
AD		 1112 /* update budget accounting */
1113 budget--;
1114 } while (likely(budget));
1115
1116 i += tx_ring->count;
9a799d71 1117 tx_ring->next_to_clean = i;
d3d00239 1118 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1119 tx_ring->stats.bytes += total_bytes;
bd198058 1120 tx_ring->stats.packets += total_packets;
d3d00239 1121 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1122 q_vector->tx.total_bytes += total_bytes;
1123 q_vector->tx.total_packets += total_packets;
b953799e 1124
c84d324c
JF		 1125 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1126 /* schedule immediate reset if we believe we hung */
1127 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1128 e_err(drv, "Detected Tx Unit Hang\n"
1129 " Tx Queue <%d>\n"
1130 " TDH, TDT <%x>, <%x>\n"
1131 " next_to_use <%x>\n"
1132 " next_to_clean <%x>\n"
1133 "tx_buffer_info[next_to_clean]\n"
1134 " time_stamp <%lx>\n"
1135 " jiffies <%lx>\n",
1136 tx_ring->queue_index,
1137 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1138 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1139 tx_ring->next_to_use, i,
1140 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1141
1142 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1143
1144 e_info(probe,
1145 "tx hang %d detected on queue %d, resetting adapter\n",
1146 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1147
b953799e 1148 /* schedule immediate reset if we believe we hung */
c83c6cbd 1149 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1150
1151 /* the adapter is about to reset, no point in enabling stuff */
59224555 1152 return true;
b953799e 1153 }
9a799d71 1154
b2d96e0a
AD		 1155 netdev_tx_completed_queue(txring_txq(tx_ring),
1156 total_packets, total_bytes);
1157
e092be60 1158#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1159 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1160 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1161 /* Make sure that anybody stopping the queue after this
1162 * sees the new next_to_clean.
1163 */
1164 smp_mb();
729739b7
AD		 1165 if (__netif_subqueue_stopped(tx_ring->netdev,
1166 tx_ring->queue_index)
1167 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1168 netif_wake_subqueue(tx_ring->netdev,
1169 tx_ring->queue_index);
5b7da515 1170 ++tx_ring->tx_stats.restart_queue;
30eba97a 1171 }
e092be60 1172 }
9a799d71 1173
59224555 1174 return !!budget;
9a799d71
AK		 1175}
1176
5dd2d332 1177#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1178static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1179 struct ixgbe_ring *tx_ring,
33cf09c9 1180 int cpu)
bd0362dd 1181{
33cf09c9 1182 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1183 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1184 u16 reg_offset;
33cf09c9 1185
33cf09c9
AD		 1186 switch (hw->mac.type) {
1187 case ixgbe_mac_82598EB:
bdda1a61 1188 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1189 break;
1190 case ixgbe_mac_82599EB:
b93a2226 1191 case ixgbe_mac_X540:
bdda1a61
AD		 1192 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1193 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1194 break;
1195 default:
bdda1a61
AD		 1196 /* for unknown hardware do not write register */
1197 return;
bd0362dd 1198 }
bdda1a61
AD		 1199
1200 /*
1201 * We can enable relaxed ordering for reads, but not writes when
1202 * DCA is enabled. This is due to a known issue in some chipsets
1203 * which will cause the DCA tag to be cleared.
1204 */
1205 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1206 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1207 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1208
1209 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1210}
1211
bdda1a61
AD		 1212static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1213 struct ixgbe_ring *rx_ring,
33cf09c9 1214 int cpu)
bd0362dd 1215{
33cf09c9 1216 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1217 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1218 u8 reg_idx = rx_ring->reg_idx;
1219
33cf09c9
AD		 1220
1221 switch (hw->mac.type) {
33cf09c9 1222 case ixgbe_mac_82599EB:
b93a2226 1223 case ixgbe_mac_X540:
bdda1a61 1224 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1225 break;
1226 default:
1227 break;
1228 }
bdda1a61
AD		 1229
1230 /*
1231 * We can enable relaxed ordering for reads, but not writes when
1232 * DCA is enabled. This is due to a known issue in some chipsets
1233 * which will cause the DCA tag to be cleared.
1234 */
1235 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1236 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1237
1238 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1239}
1240
1241static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1242{
1243 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1244 struct ixgbe_ring *ring;
bd0362dd 1245 int cpu = get_cpu();
bd0362dd 1246
33cf09c9
AD		 1247 if (q_vector->cpu == cpu)
1248 goto out_no_update;
1249
a557928e 1250 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1251 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1252
a557928e 1253 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1254 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1255
1256 q_vector->cpu = cpu;
1257out_no_update:
bd0362dd
JC		 1258 put_cpu();
1259}
1260
1261static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1262{
1263 int i;
1264
1265 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1266 return;
1267
e35ec126
AD		 1268 /* always use CB2 mode, difference is masked in the CB driver */
1269 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1270
49c7ffbe 1271 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1272 adapter->q_vector[i]->cpu = -1;
1273 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1274 }
1275}
1276
1277static int __ixgbe_notify_dca(struct device *dev, void *data)
1278{
c60fbb00 1279 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1280 unsigned long event = *(unsigned long *)data;
1281
2a72c31e 1282 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1283 return 0;
1284
bd0362dd
JC		 1285 switch (event) {
1286 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1287 /* if we're already enabled, don't do it again */
1288 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1289 break;
652f093f 1290 if (dca_add_requester(dev) == 0) {
96b0e0f6 1291 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1292 ixgbe_setup_dca(adapter);
1293 break;
1294 }
1295 /* Fall Through since DCA is disabled. */
1296 case DCA_PROVIDER_REMOVE:
1297 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1298 dca_remove_requester(dev);
1299 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1301 }
1302 break;
1303 }
1304
652f093f 1305 return 0;
bd0362dd 1306}
67a74ee2 1307
bdda1a61 1308#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1309static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1310 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1311 struct sk_buff *skb)
1312{
8a0da21b
AD		 1313 if (ring->netdev->features & NETIF_F_RXHASH)
1314 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1315}
1316
f800326d 1317#ifdef IXGBE_FCOE
ff886dfc
AD		 1318/**
1319 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1320 * @ring: structure containing ring specific data
ff886dfc
AD		 1321 * @rx_desc: advanced rx descriptor
1322 *
1323 * Returns : true if it is FCoE pkt
1324 */
57efd44c 1325static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1326 union ixgbe_adv_rx_desc *rx_desc)
1327{
1328 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1329
57efd44c 1330 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1331 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1332 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1333 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1334}
1335
f800326d 1336#endif /* IXGBE_FCOE */
e59bd25d
AV		 1337/**
1338 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1339 * @ring: structure containing ring specific data
1340 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1341 * @skb: skb currently being received and modified
1342 **/
8a0da21b 1343static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1344 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1345 struct sk_buff *skb)
9a799d71 1346{
8a0da21b 1347 skb_checksum_none_assert(skb);
9a799d71 1348
712744be 1349 /* Rx csum disabled */
8a0da21b 1350 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1351 return;
e59bd25d
AV		 1352
1353 /* if IP and error */
f56e0cb1
AD		 1354 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1355 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1356 ring->rx_stats.csum_err++;
9a799d71
AK		 1357 return;
1358 }
e59bd25d 1359
f56e0cb1 1360 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1361 return;
1362
f56e0cb1 1363 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1364 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1365
1366 /*
1367 * 82599 errata, UDP frames with a 0 checksum can be marked as
1368 * checksum errors.
1369 */
8a0da21b
AD		 1370 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1371 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1372 return;
1373
8a0da21b 1374 ring->rx_stats.csum_err++;
e59bd25d
AV		 1375 return;
1376 }
1377
9a799d71 1378 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1379 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1380}
1381
84ea2591 1382static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1383{
f56e0cb1 1384 rx_ring->next_to_use = val;
f800326d
AD		 1385
1386 /* update next to alloc since we have filled the ring */
1387 rx_ring->next_to_alloc = val;
e8e26350
PW		 1388 /*
1389 * Force memory writes to complete before letting h/w
1390 * know there are new descriptors to fetch. (Only
1391 * applicable for weak-ordered memory model archs,
1392 * such as IA-64).
1393 */
1394 wmb();
84227bcd 1395 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1396}
1397
f990b79b
AD		 1398static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1399 struct ixgbe_rx_buffer *bi)
1400{
1401 struct page *page = bi->page;
f800326d 1402 dma_addr_t dma = bi->dma;
f990b79b 1403
f800326d
AD		 1404 /* since we are recycling buffers we should seldom need to alloc */
1405 if (likely(dma))
f990b79b
AD		 1406 return true;
1407
f800326d
AD		 1408 /* alloc new page for storage */
1409 if (likely(!page)) {
0614002b
MG		 1410 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1411 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1412 if (unlikely(!page)) {
1413 rx_ring->rx_stats.alloc_rx_page_failed++;
1414 return false;
1415 }
f800326d 1416 bi->page = page;
f990b79b
AD		 1417 }
1418
f800326d
AD		 1419 /* map page for use */
1420 dma = dma_map_page(rx_ring->dev, page, 0,
1421 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1422
1423 /*
1424 * if mapping failed free memory back to system since
1425 * there isn't much point in holding memory we can't use
1426 */
1427 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1428 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1429 bi->page = NULL;
f990b79b 1430
f990b79b
AD		 1431 rx_ring->rx_stats.alloc_rx_page_failed++;
1432 return false;
1433 }
1434
f800326d 1435 bi->dma = dma;
afaa9459 1436 bi->page_offset = 0;
f800326d 1437
f990b79b
AD		 1438 return true;
1439}
1440
9a799d71 1441/**
f990b79b 1442 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1443 * @rx_ring: ring to place buffers on
1444 * @cleaned_count: number of buffers to replace
9a799d71 1445 **/
fc77dc3c 1446void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1447{
9a799d71 1448 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1449 struct ixgbe_rx_buffer *bi;
d5f398ed 1450 u16 i = rx_ring->next_to_use;
9a799d71 1451
f800326d
AD		 1452 /* nothing to do */
1453 if (!cleaned_count)
fc77dc3c
AD		 1454 return;
1455
e4f74028 1456 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1457 bi = &rx_ring->rx_buffer_info[i];
1458 i -= rx_ring->count;
9a799d71 1459
f800326d
AD		 1460 do {
1461 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1462 break;
d5f398ed 1463
f800326d
AD		 1464 /*
1465 * Refresh the desc even if buffer_addrs didn't change
1466 * because each write-back erases this info.
1467 */
1468 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1469
f990b79b
AD		 1470 rx_desc++;
1471 bi++;
9a799d71 1472 i++;
f990b79b 1473 if (unlikely(!i)) {
e4f74028 1474 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1475 bi = rx_ring->rx_buffer_info;
1476 i -= rx_ring->count;
1477 }
1478
1479 /* clear the hdr_addr for the next_to_use descriptor */
1480 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1481
1482 cleaned_count--;
1483 } while (cleaned_count);
7c6e0a43 1484
f990b79b
AD		 1485 i += rx_ring->count;
1486
f56e0cb1 1487 if (rx_ring->next_to_use != i)
84ea2591 1488 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1489}
1490
1d2024f6
AD		 1491/**
1492 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1493 * @data: pointer to the start of the headers
1494 * @max_len: total length of section to find headers in
1495 *
1496 * This function is meant to determine the length of headers that will
1497 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1498 * motivation of doing this is to only perform one pull for IPv4 TCP
1499 * packets so that we can do basic things like calculating the gso_size
1500 * based on the average data per packet.
1501 **/
1502static unsigned int ixgbe_get_headlen(unsigned char *data,
1503 unsigned int max_len)
1504{
1505 union {
1506 unsigned char *network;
1507 /* l2 headers */
1508 struct ethhdr *eth;
1509 struct vlan_hdr *vlan;
1510 /* l3 headers */
1511 struct iphdr *ipv4;
a048b40e 1512 struct ipv6hdr *ipv6;
1d2024f6
AD		 1513 } hdr;
1514 __be16 protocol;
1515 u8 nexthdr = 0; /* default to not TCP */
1516 u8 hlen;
1517
1518 /* this should never happen, but better safe than sorry */
1519 if (max_len < ETH_HLEN)
1520 return max_len;
1521
1522 /* initialize network frame pointer */
1523 hdr.network = data;
1524
1525 /* set first protocol and move network header forward */
1526 protocol = hdr.eth->h_proto;
1527 hdr.network += ETH_HLEN;
1528
1529 /* handle any vlan tag if present */
1530 if (protocol == __constant_htons(ETH_P_8021Q)) {
1531 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1532 return max_len;
1533
1534 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1535 hdr.network += VLAN_HLEN;
1536 }
1537
1538 /* handle L3 protocols */
1539 if (protocol == __constant_htons(ETH_P_IP)) {
1540 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1541 return max_len;
1542
1543 /* access ihl as a u8 to avoid unaligned access on ia64 */
1544 hlen = (hdr.network[0] & 0x0F) << 2;
1545
1546 /* verify hlen meets minimum size requirements */
1547 if (hlen < sizeof(struct iphdr))
1548 return hdr.network - data;
1549
ed83da12 1550 /* record next protocol if header is present */
20967f42 1551 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1552 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1553 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1554 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1555 return max_len;
1556
1557 /* record next protocol */
1558 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1559 hlen = sizeof(struct ipv6hdr);
f800326d 1560#ifdef IXGBE_FCOE
1d2024f6
AD		 1561 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1562 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1563 return max_len;
ed83da12 1564 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1565#endif
1566 } else {
1567 return hdr.network - data;
1568 }
1569
ed83da12
AD		 1570 /* relocate pointer to start of L4 header */
1571 hdr.network += hlen;
1572
a048b40e 1573 /* finally sort out TCP/UDP */
1d2024f6
AD		 1574 if (nexthdr == IPPROTO_TCP) {
1575 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1576 return max_len;
1577
1578 /* access doff as a u8 to avoid unaligned access on ia64 */
1579 hlen = (hdr.network[12] & 0xF0) >> 2;
1580
1581 /* verify hlen meets minimum size requirements */
1582 if (hlen < sizeof(struct tcphdr))
1583 return hdr.network - data;
1584
1585 hdr.network += hlen;
a048b40e
AD		 1586 } else if (nexthdr == IPPROTO_UDP) {
1587 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1588 return max_len;
1589
1590 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1591 }
1592
1593 /*
1594 * If everything has gone correctly hdr.network should be the
1595 * data section of the packet and will be the end of the header.
1596 * If not then it probably represents the end of the last recognized
1597 * header.
1598 */
1599 if ((hdr.network - data) < max_len)
1600 return hdr.network - data;
1601 else
1602 return max_len;
1603}
1604
1d2024f6
AD		 1605static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1606 struct sk_buff *skb)
1607{
f800326d 1608 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1609
1610 /* set gso_size to avoid messing up TCP MSS */
1611 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1612 IXGBE_CB(skb)->append_cnt);
96be80ab 1613 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1614}
1615
1616static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1617 struct sk_buff *skb)
1618{
1619 /* if append_cnt is 0 then frame is not RSC */
1620 if (!IXGBE_CB(skb)->append_cnt)
1621 return;
1622
1623 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1624 rx_ring->rx_stats.rsc_flush++;
1625
1626 ixgbe_set_rsc_gso_size(rx_ring, skb);
1627
1628 /* gso_size is computed using append_cnt so always clear it last */
1629 IXGBE_CB(skb)->append_cnt = 0;
1630}
1631
8a0da21b
AD		 1632/**
1633 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1634 * @rx_ring: rx descriptor ring packet is being transacted on
1635 * @rx_desc: pointer to the EOP Rx descriptor
1636 * @skb: pointer to current skb being populated
f8212f97 1637 *
8a0da21b
AD		 1638 * This function checks the ring, descriptor, and packet information in
1639 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1640 * other fields within the skb.
f8212f97 1641 **/
8a0da21b
AD		 1642static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1643 union ixgbe_adv_rx_desc *rx_desc,
1644 struct sk_buff *skb)
f8212f97 1645{
43e95f11
JF		 1646 struct net_device *dev = rx_ring->netdev;
1647
8a0da21b
AD		 1648 ixgbe_update_rsc_stats(rx_ring, skb);
1649
1650 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1651
8a0da21b
AD		 1652 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1653
6cb562d6 1654 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1655
f646968f 1656 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1657 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1658 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1659 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1660 }
1661
8a0da21b 1662 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1663
43e95f11 1664 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1665}
1666
8a0da21b
AD		 1667static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1668 struct sk_buff *skb)
aa80175a 1669{
8a0da21b
AD		 1670 struct ixgbe_adapter *adapter = q_vector->adapter;
1671
b4640030 1672 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1673 netif_receive_skb(skb);
1674 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1675 napi_gro_receive(&q_vector->napi, skb);
1676 else
1677 netif_rx(skb);
aa80175a 1678}
43634e82 1679
f800326d
AD		 1680/**
1681 * ixgbe_is_non_eop - process handling of non-EOP buffers
1682 * @rx_ring: Rx ring being processed
1683 * @rx_desc: Rx descriptor for current buffer
1684 * @skb: Current socket buffer containing buffer in progress
1685 *
1686 * This function updates next to clean. If the buffer is an EOP buffer
1687 * this function exits returning false, otherwise it will place the
1688 * sk_buff in the next buffer to be chained and return true indicating
1689 * that this is in fact a non-EOP buffer.
1690 **/
1691static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1692 union ixgbe_adv_rx_desc *rx_desc,
1693 struct sk_buff *skb)
1694{
1695 u32 ntc = rx_ring->next_to_clean + 1;
1696
1697 /* fetch, update, and store next to clean */
1698 ntc = (ntc < rx_ring->count) ? ntc : 0;
1699 rx_ring->next_to_clean = ntc;
1700
1701 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1702
5a02cbd1
AD		 1703 /* update RSC append count if present */
1704 if (ring_is_rsc_enabled(rx_ring)) {
1705 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1706 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1707
1708 if (unlikely(rsc_enabled)) {
1709 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1710
1711 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1712 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1713
5a02cbd1
AD		 1714 /* update ntc based on RSC value */
1715 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1716 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1717 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1718 }
f800326d
AD		 1719 }
1720
5a02cbd1
AD		 1721 /* if we are the last buffer then there is nothing else to do */
1722 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1723 return false;
1724
f800326d
AD		 1725 /* place skb in next buffer to be received */
1726 rx_ring->rx_buffer_info[ntc].skb = skb;
1727 rx_ring->rx_stats.non_eop_descs++;
1728
1729 return true;
1730}
1731
19861ce2
AD		 1732/**
1733 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1734 * @rx_ring: rx descriptor ring packet is being transacted on
1735 * @skb: pointer to current skb being adjusted
1736 *
1737 * This function is an ixgbe specific version of __pskb_pull_tail. The
1738 * main difference between this version and the original function is that
1739 * this function can make several assumptions about the state of things
1740 * that allow for significant optimizations versus the standard function.
1741 * As a result we can do things like drop a frag and maintain an accurate
1742 * truesize for the skb.
1743 */
1744static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1745 struct sk_buff *skb)
1746{
1747 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1748 unsigned char *va;
1749 unsigned int pull_len;
1750
1751 /*
1752 * it is valid to use page_address instead of kmap since we are
1753 * working with pages allocated out of the lomem pool per
1754 * alloc_page(GFP_ATOMIC)
1755 */
1756 va = skb_frag_address(frag);
1757
1758 /*
1759 * we need the header to contain the greater of either ETH_HLEN or
1760 * 60 bytes if the skb->len is less than 60 for skb_pad.
1761 */
cf3fe7ac 1762 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1763
1764 /* align pull length to size of long to optimize memcpy performance */
1765 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1766
1767 /* update all of the pointers */
1768 skb_frag_size_sub(frag, pull_len);
1769 frag->page_offset += pull_len;
1770 skb->data_len -= pull_len;
1771 skb->tail += pull_len;
19861ce2
AD		 1772}
1773
42073d91
AD		 1774/**
1775 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1776 * @rx_ring: rx descriptor ring packet is being transacted on
1777 * @skb: pointer to current skb being updated
1778 *
1779 * This function provides a basic DMA sync up for the first fragment of an
1780 * skb. The reason for doing this is that the first fragment cannot be
1781 * unmapped until we have reached the end of packet descriptor for a buffer
1782 * chain.
1783 */
1784static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1785 struct sk_buff *skb)
1786{
1787 /* if the page was released unmap it, else just sync our portion */
1788 if (unlikely(IXGBE_CB(skb)->page_released)) {
1789 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1790 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1791 IXGBE_CB(skb)->page_released = false;
1792 } else {
1793 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1794
1795 dma_sync_single_range_for_cpu(rx_ring->dev,
1796 IXGBE_CB(skb)->dma,
1797 frag->page_offset,
1798 ixgbe_rx_bufsz(rx_ring),
1799 DMA_FROM_DEVICE);
1800 }
1801 IXGBE_CB(skb)->dma = 0;
1802}
1803
f800326d
AD		 1804/**
1805 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1806 * @rx_ring: rx descriptor ring packet is being transacted on
1807 * @rx_desc: pointer to the EOP Rx descriptor
1808 * @skb: pointer to current skb being fixed
1809 *
1810 * Check for corrupted packet headers caused by senders on the local L2
1811 * embedded NIC switch not setting up their Tx Descriptors right. These
1812 * should be very rare.
1813 *
1814 * Also address the case where we are pulling data in on pages only
1815 * and as such no data is present in the skb header.
1816 *
1817 * In addition if skb is not at least 60 bytes we need to pad it so that
1818 * it is large enough to qualify as a valid Ethernet frame.
1819 *
1820 * Returns true if an error was encountered and skb was freed.
1821 **/
1822static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1823 union ixgbe_adv_rx_desc *rx_desc,
1824 struct sk_buff *skb)
1825{
f800326d 1826 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1827
1828 /* verify that the packet does not have any known errors */
1829 if (unlikely(ixgbe_test_staterr(rx_desc,
1830 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1831 !(netdev->features & NETIF_F_RXALL))) {
1832 dev_kfree_skb_any(skb);
1833 return true;
1834 }
1835
19861ce2 1836 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1837 if (skb_is_nonlinear(skb))
1838 ixgbe_pull_tail(rx_ring, skb);
f800326d 1839
57efd44c
AD		 1840#ifdef IXGBE_FCOE
1841 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1842 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1843 return false;
1844
1845#endif
f800326d
AD		 1846 /* if skb_pad returns an error the skb was freed */
1847 if (unlikely(skb->len < 60)) {
1848 int pad_len = 60 - skb->len;
1849
1850 if (skb_pad(skb, pad_len))
1851 return true;
1852 __skb_put(skb, pad_len);
1853 }
1854
1855 return false;
1856}
1857
f800326d
AD		 1858/**
1859 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1860 * @rx_ring: rx descriptor ring to store buffers on
1861 * @old_buff: donor buffer to have page reused
1862 *
0549ae20 1863 * Synchronizes page for reuse by the adapter
f800326d
AD		 1864 **/
1865static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1866 struct ixgbe_rx_buffer *old_buff)
1867{
1868 struct ixgbe_rx_buffer *new_buff;
1869 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1870
1871 new_buff = &rx_ring->rx_buffer_info[nta];
1872
1873 /* update, and store next to alloc */
1874 nta++;
1875 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1876
1877 /* transfer page from old buffer to new buffer */
1878 new_buff->page = old_buff->page;
1879 new_buff->dma = old_buff->dma;
0549ae20 1880 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1881
1882 /* sync the buffer for use by the device */
1883 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1884 new_buff->page_offset,
1885 ixgbe_rx_bufsz(rx_ring),
f800326d 1886 DMA_FROM_DEVICE);
f800326d
AD		 1887}
1888
1889/**
1890 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1891 * @rx_ring: rx descriptor ring to transact packets on
1892 * @rx_buffer: buffer containing page to add
1893 * @rx_desc: descriptor containing length of buffer written by hardware
1894 * @skb: sk_buff to place the data into
1895 *
0549ae20
AD		 1896 * This function will add the data contained in rx_buffer->page to the skb.
1897 * This is done either through a direct copy if the data in the buffer is
1898 * less than the skb header size, otherwise it will just attach the page as
1899 * a frag to the skb.
1900 *
1901 * The function will then update the page offset if necessary and return
1902 * true if the buffer can be reused by the adapter.
f800326d 1903 **/
0549ae20 1904static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1905 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1906 union ixgbe_adv_rx_desc *rx_desc,
1907 struct sk_buff *skb)
f800326d 1908{
0549ae20
AD		 1909 struct page *page = rx_buffer->page;
1910 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1911#if (PAGE_SIZE < 8192)
0549ae20 1912 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1913#else
1914 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1915 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1916 ixgbe_rx_bufsz(rx_ring);
1917#endif
0549ae20 1918
cf3fe7ac
AD		 1919 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1920 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1921
1922 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1923
1924 /* we can reuse buffer as-is, just make sure it is local */
1925 if (likely(page_to_nid(page) == numa_node_id()))
1926 return true;
1927
1928 /* this page cannot be reused so discard it */
1929 put_page(page);
1930 return false;
1931 }
1932
0549ae20
AD		 1933 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1934 rx_buffer->page_offset, size, truesize);
1935
09816fbe
AD		 1936 /* avoid re-using remote pages */
1937 if (unlikely(page_to_nid(page) != numa_node_id()))
1938 return false;
1939
1940#if (PAGE_SIZE < 8192)
1941 /* if we are only owner of page we can reuse it */
1942 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1943 return false;
1944
1945 /* flip page offset to other buffer */
1946 rx_buffer->page_offset ^= truesize;
1947
09816fbe
AD		 1948 /*
1949 * since we are the only owner of the page and we need to
1950 * increment it, just set the value to 2 in order to avoid
1951 * an unecessary locked operation
1952 */
1953 atomic_set(&page->_count, 2);
1954#else
1955 /* move offset up to the next cache line */
1956 rx_buffer->page_offset += truesize;
1957
1958 if (rx_buffer->page_offset > last_offset)
1959 return false;
1960
0549ae20
AD		 1961 /* bump ref count on page before it is given to the stack */
1962 get_page(page);
09816fbe 1963#endif
0549ae20
AD		 1964
1965 return true;
f800326d
AD		 1966}
1967
18806c9e
AD		 1968static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1969 union ixgbe_adv_rx_desc *rx_desc)
1970{
1971 struct ixgbe_rx_buffer *rx_buffer;
1972 struct sk_buff *skb;
1973 struct page *page;
1974
1975 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1976 page = rx_buffer->page;
1977 prefetchw(page);
1978
1979 skb = rx_buffer->skb;
1980
1981 if (likely(!skb)) {
1982 void *page_addr = page_address(page) +
1983 rx_buffer->page_offset;
1984
1985 /* prefetch first cache line of first page */
1986 prefetch(page_addr);
1987#if L1_CACHE_BYTES < 128
1988 prefetch(page_addr + L1_CACHE_BYTES);
1989#endif
1990
1991 /* allocate a skb to store the frags */
1992 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1993 IXGBE_RX_HDR_SIZE);
1994 if (unlikely(!skb)) {
1995 rx_ring->rx_stats.alloc_rx_buff_failed++;
1996 return NULL;
1997 }
1998
1999 /*
2000 * we will be copying header into skb->data in
2001 * pskb_may_pull so it is in our interest to prefetch
2002 * it now to avoid a possible cache miss
2003 */
2004 prefetchw(skb->data);
2005
2006 /*
2007 * Delay unmapping of the first packet. It carries the
2008 * header information, HW may still access the header
2009 * after the writeback. Only unmap it when EOP is
2010 * reached
2011 */
2012 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2013 goto dma_sync;
2014
2015 IXGBE_CB(skb)->dma = rx_buffer->dma;
2016 } else {
2017 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2018 ixgbe_dma_sync_frag(rx_ring, skb);
2019
2020dma_sync:
2021 /* we are reusing so sync this buffer for CPU use */
2022 dma_sync_single_range_for_cpu(rx_ring->dev,
2023 rx_buffer->dma,
2024 rx_buffer->page_offset,
2025 ixgbe_rx_bufsz(rx_ring),
2026 DMA_FROM_DEVICE);
2027 }
2028
2029 /* pull page into skb */
2030 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2031 /* hand second half of page back to the ring */
2032 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2033 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2034 /* the page has been released from the ring */
2035 IXGBE_CB(skb)->page_released = true;
2036 } else {
2037 /* we are not reusing the buffer so unmap it */
2038 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2039 ixgbe_rx_pg_size(rx_ring),
2040 DMA_FROM_DEVICE);
2041 }
2042
2043 /* clear contents of buffer_info */
2044 rx_buffer->skb = NULL;
2045 rx_buffer->dma = 0;
2046 rx_buffer->page = NULL;
2047
2048 return skb;
f800326d
AD		 2049}
2050
2051/**
2052 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2053 * @q_vector: structure containing interrupt and ring information
2054 * @rx_ring: rx descriptor ring to transact packets on
2055 * @budget: Total limit on number of packets to process
2056 *
2057 * This function provides a "bounce buffer" approach to Rx interrupt
2058 * processing. The advantage to this is that on systems that have
2059 * expensive overhead for IOMMU access this provides a means of avoiding
2060 * it by maintaining the mapping of the page to the syste.
2061 *
5a85e737 2062 * Returns amount of work completed
f800326d 2063 **/
5a85e737 2064static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2065 struct ixgbe_ring *rx_ring,
f4de00ed 2066 const int budget)
9a799d71 2067{
d2f4fbe2 2068 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2069#ifdef IXGBE_FCOE
f800326d 2070 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2071 int ddp_bytes;
2072 unsigned int mss = 0;
3d8fd385 2073#endif /* IXGBE_FCOE */
f800326d 2074 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2075
f800326d 2076 do {
f800326d
AD		 2077 union ixgbe_adv_rx_desc *rx_desc;
2078 struct sk_buff *skb;
f800326d
AD		 2079
2080 /* return some buffers to hardware, one at a time is too slow */
2081 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2082 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2083 cleaned_count = 0;
2084 }
2085
18806c9e 2086 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2087
2088 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2089 break;
9a799d71 2090
f800326d
AD		 2091 /*
2092 * This memory barrier is needed to keep us from reading
2093 * any other fields out of the rx_desc until we know the
2094 * RXD_STAT_DD bit is set
2095 */
2096 rmb();
9a799d71 2097
18806c9e
AD		 2098 /* retrieve a buffer from the ring */
2099 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2100
18806c9e
AD		 2101 /* exit if we failed to retrieve a buffer */
2102 if (!skb)
2103 break;
9a799d71 2104
9a799d71 2105 cleaned_count++;
f8212f97 2106
f800326d
AD		 2107 /* place incomplete frames back on ring for completion */
2108 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2109 continue;
c267fc16 2110
f800326d
AD		 2111 /* verify the packet layout is correct */
2112 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2113 continue;
9a799d71 2114
d2f4fbe2
AV		 2115 /* probably a little skewed due to removing CRC */
2116 total_rx_bytes += skb->len;
d2f4fbe2 2117
8a0da21b
AD		 2118 /* populate checksum, timestamp, VLAN, and protocol */
2119 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2120
332d4a7d
YZ		 2121#ifdef IXGBE_FCOE
2122 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2123 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2124 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2125 /* include DDPed FCoE data */
2126 if (ddp_bytes > 0) {
2127 if (!mss) {
2128 mss = rx_ring->netdev->mtu -
2129 sizeof(struct fcoe_hdr) -
2130 sizeof(struct fc_frame_header) -
2131 sizeof(struct fcoe_crc_eof);
2132 if (mss > 512)
2133 mss &= ~511;
2134 }
2135 total_rx_bytes += ddp_bytes;
2136 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2137 mss);
2138 }
63d635b2
AD		 2139 if (!ddp_bytes) {
2140 dev_kfree_skb_any(skb);
f800326d 2141 continue;
63d635b2 2142 }
3d8fd385 2143 }
f800326d 2144
332d4a7d 2145#endif /* IXGBE_FCOE */
8b80cda5 2146 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2147 ixgbe_rx_skb(q_vector, skb);
9a799d71 2148
f800326d 2149 /* update budget accounting */
f4de00ed
AD		 2150 total_rx_packets++;
2151 } while (likely(total_rx_packets < budget));
9a799d71 2152
c267fc16
AD		 2153 u64_stats_update_begin(&rx_ring->syncp);
2154 rx_ring->stats.packets += total_rx_packets;
2155 rx_ring->stats.bytes += total_rx_bytes;
2156 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2157 q_vector->rx.total_packets += total_rx_packets;
2158 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2159
f800326d
AD		 2160 if (cleaned_count)
2161 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2162
5a85e737 2163 return total_rx_packets;
9a799d71
AK		 2164}
2165
e0d1095a 2166#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2167/* must be called with local_bh_disable()d */
2168static int ixgbe_low_latency_recv(struct napi_struct *napi)
2169{
2170 struct ixgbe_q_vector *q_vector =
2171 container_of(napi, struct ixgbe_q_vector, napi);
2172 struct ixgbe_adapter *adapter = q_vector->adapter;
2173 struct ixgbe_ring *ring;
2174 int found = 0;
2175
2176 if (test_bit(__IXGBE_DOWN, &adapter->state))
2177 return LL_FLUSH_FAILED;
2178
2179 if (!ixgbe_qv_lock_poll(q_vector))
2180 return LL_FLUSH_BUSY;
2181
2182 ixgbe_for_each_ring(ring, q_vector->rx) {
2183 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2184#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2185 if (found)
2186 ring->stats.cleaned += found;
2187 else
2188 ring->stats.misses++;
2189#endif
5a85e737
ET		 2190 if (found)
2191 break;
2192 }
2193
2194 ixgbe_qv_unlock_poll(q_vector);
2195
2196 return found;
2197}
e0d1095a 2198#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2199
9a799d71
AK		 2200/**
2201 * ixgbe_configure_msix - Configure MSI-X hardware
2202 * @adapter: board private structure
2203 *
2204 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2205 * interrupts.
2206 **/
2207static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2208{
021230d4 2209 struct ixgbe_q_vector *q_vector;
49c7ffbe 2210 int v_idx;
021230d4 2211 u32 mask;
9a799d71 2212
8e34d1aa
AD		 2213 /* Populate MSIX to EITR Select */
2214 if (adapter->num_vfs > 32) {
2215 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2217 }
2218
4df10466
JB		 2219 /*
2220 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2221 * corresponding register.
2222 */
49c7ffbe 2223 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2224 struct ixgbe_ring *ring;
7a921c93 2225 q_vector = adapter->q_vector[v_idx];
021230d4 2226
a557928e 2227 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2228 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2229
a557928e 2230 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2231 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2232
fe49f04a 2233 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2234 }
2235
bd508178
AD		 2236 switch (adapter->hw.mac.type) {
2237 case ixgbe_mac_82598EB:
e8e26350 2238 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2239 v_idx);
bd508178
AD		 2240 break;
2241 case ixgbe_mac_82599EB:
b93a2226 2242 case ixgbe_mac_X540:
e8e26350 2243 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2244 break;
bd508178
AD		 2245 default:
2246 break;
2247 }
021230d4
AV		 2248 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2249
41fb9248 2250 /* set up to autoclear timer, and the vectors */
021230d4 2251 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2252 mask &= ~(IXGBE_EIMS_OTHER |
2253 IXGBE_EIMS_MAILBOX |
2254 IXGBE_EIMS_LSC);
2255
021230d4 2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2257}
2258
f494e8fa
AV		 2259enum latency_range {
2260 lowest_latency = 0,
2261 low_latency = 1,
2262 bulk_latency = 2,
2263 latency_invalid = 255
2264};
2265
2266/**
2267 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2268 * @q_vector: structure containing interrupt and ring information
2269 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2270 *
2271 * Stores a new ITR value based on packets and byte
2272 * counts during the last interrupt. The advantage of per interrupt
2273 * computation is faster updates and more accurate ITR for the current
2274 * traffic pattern. Constants in this function were computed
2275 * based on theoretical maximum wire speed and thresholds were set based
2276 * on testing data as well as attempting to minimize response time
2277 * while increasing bulk throughput.
2278 * this functionality is controlled by the InterruptThrottleRate module
2279 * parameter (see ixgbe_param.c)
2280 **/
bd198058
AD		 2281static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2282 struct ixgbe_ring_container *ring_container)
f494e8fa 2283{
bd198058
AD		 2284 int bytes = ring_container->total_bytes;
2285 int packets = ring_container->total_packets;
2286 u32 timepassed_us;
621bd70e 2287 u64 bytes_perint;
bd198058 2288 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2289
2290 if (packets == 0)
bd198058 2291 return;
f494e8fa
AV		 2292
2293 /* simple throttlerate management
621bd70e
AD		 2294 * 0-10MB/s lowest (100000 ints/s)
2295 * 10-20MB/s low (20000 ints/s)
2296 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2297 */
2298 /* what was last interrupt timeslice? */
d5bf4f67 2299 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2300 if (timepassed_us == 0)
2301 return;
2302
f494e8fa
AV		 2303 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2304
2305 switch (itr_setting) {
2306 case lowest_latency:
621bd70e 2307 if (bytes_perint > 10)
bd198058 2308 itr_setting = low_latency;
f494e8fa
AV		 2309 break;
2310 case low_latency:
621bd70e 2311 if (bytes_perint > 20)
bd198058 2312 itr_setting = bulk_latency;
621bd70e 2313 else if (bytes_perint <= 10)
bd198058 2314 itr_setting = lowest_latency;
f494e8fa
AV		 2315 break;
2316 case bulk_latency:
621bd70e 2317 if (bytes_perint <= 20)
bd198058 2318 itr_setting = low_latency;
f494e8fa
AV		 2319 break;
2320 }
2321
bd198058
AD		 2322 /* clear work counters since we have the values we need */
2323 ring_container->total_bytes = 0;
2324 ring_container->total_packets = 0;
2325
2326 /* write updated itr to ring container */
2327 ring_container->itr = itr_setting;
f494e8fa
AV		 2328}
2329
509ee935
JB		 2330/**
2331 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2332 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2333 *
2334 * This function is made to be called by ethtool and by the driver
2335 * when it needs to update EITR registers at runtime. Hardware
2336 * specific quirks/differences are taken care of here.
2337 */
fe49f04a 2338void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2339{
fe49f04a 2340 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2341 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2342 int v_idx = q_vector->v_idx;
5d967eb7 2343 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2344
bd508178
AD		 2345 switch (adapter->hw.mac.type) {
2346 case ixgbe_mac_82598EB:
509ee935
JB		 2347 /* must write high and low 16 bits to reset counter */
2348 itr_reg |= (itr_reg << 16);
bd508178
AD		 2349 break;
2350 case ixgbe_mac_82599EB:
b93a2226 2351 case ixgbe_mac_X540:
509ee935
JB		 2352 /*
2353 * set the WDIS bit to not clear the timer bits and cause an
2354 * immediate assertion of the interrupt
2355 */
2356 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2357 break;
2358 default:
2359 break;
509ee935
JB		 2360 }
2361 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2362}
2363
bd198058 2364static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2365{
d5bf4f67 2366 u32 new_itr = q_vector->itr;
bd198058 2367 u8 current_itr;
f494e8fa 2368
bd198058
AD		 2369 ixgbe_update_itr(q_vector, &q_vector->tx);
2370 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2371
08c8833b 2372 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2373
2374 switch (current_itr) {
2375 /* counts and packets in update_itr are dependent on these numbers */
2376 case lowest_latency:
d5bf4f67 2377 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2378 break;
2379 case low_latency:
d5bf4f67 2380 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2381 break;
2382 case bulk_latency:
d5bf4f67 2383 new_itr = IXGBE_8K_ITR;
f494e8fa 2384 break;
bd198058
AD		 2385 default:
2386 break;
f494e8fa
AV		 2387 }
2388
d5bf4f67 2389 if (new_itr != q_vector->itr) {
fe49f04a 2390 /* do an exponential smoothing */
d5bf4f67
ET		 2391 new_itr = (10 * new_itr * q_vector->itr) /
2392 ((9 * new_itr) + q_vector->itr);
509ee935 2393
bd198058 2394 /* save the algorithm value here */
5d967eb7 2395 q_vector->itr = new_itr;
fe49f04a
AD		 2396
2397 ixgbe_write_eitr(q_vector);
f494e8fa 2398 }
f494e8fa
AV		 2399}
2400
119fc60a 2401/**
de88eeeb 2402 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2403 * @adapter: pointer to adapter
119fc60a 2404 **/
f0f9778d 2405static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2406{
119fc60a
MC		 2407 struct ixgbe_hw *hw = &adapter->hw;
2408 u32 eicr = adapter->interrupt_event;
2409
f0f9778d 2410 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2411 return;
2412
f0f9778d
AD		 2413 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2414 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2415 return;
2416
2417 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2418
7ca647bd 2419 switch (hw->device_id) {
f0f9778d
AD		 2420 case IXGBE_DEV_ID_82599_T3_LOM:
2421 /*
2422 * Since the warning interrupt is for both ports
2423 * we don't have to check if:
2424 * - This interrupt wasn't for our port.
2425 * - We may have missed the interrupt so always have to
2426 * check if we got a LSC
2427 */
2428 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2429 !(eicr & IXGBE_EICR_LSC))
2430 return;
2431
2432 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2433 u32 speed;
f0f9778d 2434 bool link_up = false;
7ca647bd 2435
3d292265 2436 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2437
f0f9778d
AD		 2438 if (link_up)
2439 return;
2440 }
2441
2442 /* Check if this is not due to overtemp */
2443 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2444 return;
2445
2446 break;
7ca647bd
JP		 2447 default:
2448 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2449 return;
7ca647bd 2450 break;
119fc60a 2451 }
7ca647bd
JP		 2452 e_crit(drv,
2453 "Network adapter has been stopped because it has over heated. "
2454 "Restart the computer. If the problem persists, "
2455 "power off the system and replace the adapter\n");
f0f9778d
AD		 2456
2457 adapter->interrupt_event = 0;
119fc60a
MC		 2458}
2459
0befdb3e
JB		 2460static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2461{
2462 struct ixgbe_hw *hw = &adapter->hw;
2463
2464 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2465 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2466 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2467 /* write to clear the interrupt */
2468 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2469 }
2470}
cf8280ee 2471
4f51bf70
JK		 2472static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2473{
2474 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2475 return;
2476
2477 switch (adapter->hw.mac.type) {
2478 case ixgbe_mac_82599EB:
2479 /*
2480 * Need to check link state so complete overtemp check
2481 * on service task
2482 */
2483 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2484 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2485 adapter->interrupt_event = eicr;
2486 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2487 ixgbe_service_event_schedule(adapter);
2488 return;
2489 }
2490 return;
2491 case ixgbe_mac_X540:
2492 if (!(eicr & IXGBE_EICR_TS))
2493 return;
2494 break;
2495 default:
2496 return;
2497 }
2498
2499 e_crit(drv,
2500 "Network adapter has been stopped because it has over heated. "
2501 "Restart the computer. If the problem persists, "
2502 "power off the system and replace the adapter\n");
2503}
2504
e8e26350
PW		 2505static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2506{
2507 struct ixgbe_hw *hw = &adapter->hw;
2508
73c4b7cd
AD		 2509 if (eicr & IXGBE_EICR_GPI_SDP2) {
2510 /* Clear the interrupt */
2511 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2512 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2513 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2514 ixgbe_service_event_schedule(adapter);
2515 }
73c4b7cd
AD		 2516 }
2517
e8e26350
PW		 2518 if (eicr & IXGBE_EICR_GPI_SDP1) {
2519 /* Clear the interrupt */
2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2523 ixgbe_service_event_schedule(adapter);
2524 }
e8e26350
PW		 2525 }
2526}
2527
cf8280ee
JB		 2528static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2529{
2530 struct ixgbe_hw *hw = &adapter->hw;
2531
2532 adapter->lsc_int++;
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2534 adapter->link_check_timeout = jiffies;
2535 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2536 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2537 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2538 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2539 }
2540}
2541
fe49f04a
AD		 2542static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2543 u64 qmask)
2544{
2545 u32 mask;
bd508178 2546 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2547
bd508178
AD		 2548 switch (hw->mac.type) {
2549 case ixgbe_mac_82598EB:
fe49f04a 2550 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2551 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2552 break;
2553 case ixgbe_mac_82599EB:
b93a2226 2554 case ixgbe_mac_X540:
fe49f04a 2555 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2556 if (mask)
2557 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2558 mask = (qmask >> 32);
bd508178
AD		 2559 if (mask)
2560 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2561 break;
2562 default:
2563 break;
fe49f04a
AD		 2564 }
2565 /* skip the flush */
2566}
2567
2568static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2569 u64 qmask)
fe49f04a
AD		 2570{
2571 u32 mask;
bd508178 2572 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2573
bd508178
AD		 2574 switch (hw->mac.type) {
2575 case ixgbe_mac_82598EB:
fe49f04a 2576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2577 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2578 break;
2579 case ixgbe_mac_82599EB:
b93a2226 2580 case ixgbe_mac_X540:
fe49f04a 2581 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2582 if (mask)
2583 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2584 mask = (qmask >> 32);
bd508178
AD		 2585 if (mask)
2586 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2587 break;
2588 default:
2589 break;
fe49f04a
AD		 2590 }
2591 /* skip the flush */
2592}
2593
021230d4 2594/**
2c4af694
AD		 2595 * ixgbe_irq_enable - Enable default interrupt generation settings
2596 * @adapter: board private structure
021230d4 2597 **/
2c4af694
AD		 2598static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2599 bool flush)
9a799d71 2600{
2c4af694 2601 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2602
2c4af694
AD		 2603 /* don't reenable LSC while waiting for link */
2604 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2605 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2606
2c4af694 2607 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2608 switch (adapter->hw.mac.type) {
2609 case ixgbe_mac_82599EB:
2610 mask |= IXGBE_EIMS_GPI_SDP0;
2611 break;
2612 case ixgbe_mac_X540:
2613 mask |= IXGBE_EIMS_TS;
2614 break;
2615 default:
2616 break;
2617 }
2c4af694
AD		 2618 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2619 mask |= IXGBE_EIMS_GPI_SDP1;
2620 switch (adapter->hw.mac.type) {
2621 case ixgbe_mac_82599EB:
2c4af694
AD		 2622 mask |= IXGBE_EIMS_GPI_SDP1;
2623 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2624 case ixgbe_mac_X540:
2625 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2626 mask |= IXGBE_EIMS_MAILBOX;
2627 break;
2628 default:
2629 break;
9a799d71 2630 }
db0677fa 2631
db0677fa
JK		 2632 if (adapter->hw.mac.type == ixgbe_mac_X540)
2633 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2634
2c4af694
AD		 2635 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2636 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2637 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2638
2c4af694
AD		 2639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2640 if (queues)
2641 ixgbe_irq_enable_queues(adapter, ~0);
2642 if (flush)
2643 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2644}
2645
2c4af694 2646static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2647{
a65151ba 2648 struct ixgbe_adapter *adapter = data;
9a799d71 2649 struct ixgbe_hw *hw = &adapter->hw;
54037505 2650 u32 eicr;
91281fd3 2651
54037505
DS		 2652 /*
2653 * Workaround for Silicon errata. Use clear-by-write instead
2654 * of clear-by-read. Reading with EICS will return the
2655 * interrupt causes without clearing, which later be done
2656 * with the write to EICR.
2657 */
2658 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2659
2660 /* The lower 16bits of the EICR register are for the queue interrupts
2661 * which should be masked here in order to not accidently clear them if
2662 * the bits are high when ixgbe_msix_other is called. There is a race
2663 * condition otherwise which results in possible performance loss
2664 * especially if the ixgbe_msix_other interrupt is triggering
2665 * consistently (as it would when PPS is turned on for the X540 device)
2666 */
2667 eicr &= 0xFFFF0000;
2668
54037505 2669 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2670
cf8280ee
JB		 2671 if (eicr & IXGBE_EICR_LSC)
2672 ixgbe_check_lsc(adapter);
f0848276 2673
1cdd1ec8
GR		 2674 if (eicr & IXGBE_EICR_MAILBOX)
2675 ixgbe_msg_task(adapter);
efe3d3c8 2676
bd508178
AD		 2677 switch (hw->mac.type) {
2678 case ixgbe_mac_82599EB:
b93a2226 2679 case ixgbe_mac_X540:
d773ce2d
DS		 2680 if (eicr & IXGBE_EICR_ECC) {
2681 e_info(link, "Received ECC Err, initiating reset\n");
2682 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2683 ixgbe_service_event_schedule(adapter);
2684 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2685 }
c4cf55e5
PWJ		 2686 /* Handle Flow Director Full threshold interrupt */
2687 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2688 int reinit_count = 0;
c4cf55e5 2689 int i;
c4cf55e5 2690 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2691 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2692 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2693 &ring->state))
2694 reinit_count++;
2695 }
2696 if (reinit_count) {
2697 /* no more flow director interrupts until after init */
2698 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2699 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2700 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2701 }
2702 }
f0f9778d 2703 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2704 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2705 break;
2706 default:
2707 break;
c4cf55e5 2708 }
f0848276 2709
bd508178 2710 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2711
db0677fa
JK		 2712 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2713 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2714
7086400d 2715 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2716 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2717 ixgbe_irq_enable(adapter, false, false);
f0848276 2718
9a799d71 2719 return IRQ_HANDLED;
f0848276 2720}
91281fd3 2721
4ff7fb12 2722static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2723{
021230d4 2724 struct ixgbe_q_vector *q_vector = data;
91281fd3 2725
9b471446 2726 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2727
4ff7fb12
AD		 2728 if (q_vector->rx.ring || q_vector->tx.ring)
2729 napi_schedule(&q_vector->napi);
91281fd3 2730
9a799d71 2731 return IRQ_HANDLED;
91281fd3
AD		 2732}
2733
eb01b975
AD		 2734/**
2735 * ixgbe_poll - NAPI Rx polling callback
2736 * @napi: structure for representing this polling device
2737 * @budget: how many packets driver is allowed to clean
2738 *
2739 * This function is used for legacy and MSI, NAPI mode
2740 **/
8af3c33f 2741int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2742{
2743 struct ixgbe_q_vector *q_vector =
2744 container_of(napi, struct ixgbe_q_vector, napi);
2745 struct ixgbe_adapter *adapter = q_vector->adapter;
2746 struct ixgbe_ring *ring;
2747 int per_ring_budget;
2748 bool clean_complete = true;
2749
2750#ifdef CONFIG_IXGBE_DCA
2751 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2752 ixgbe_update_dca(q_vector);
2753#endif
2754
2755 ixgbe_for_each_ring(ring, q_vector->tx)
2756 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2757
5a85e737
ET		 2758 if (!ixgbe_qv_lock_napi(q_vector))
2759 return budget;
2760
eb01b975
AD		 2761 /* attempt to distribute budget to each queue fairly, but don't allow
2762 * the budget to go below 1 because we'll exit polling */
2763 if (q_vector->rx.count > 1)
2764 per_ring_budget = max(budget/q_vector->rx.count, 1);
2765 else
2766 per_ring_budget = budget;
2767
2768 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2769 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2770 per_ring_budget) < per_ring_budget);
eb01b975 2771
5a85e737 2772 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2773 /* If all work not completed, return budget and keep polling */
2774 if (!clean_complete)
2775 return budget;
2776
2777 /* all work done, exit the polling mode */
2778 napi_complete(napi);
2779 if (adapter->rx_itr_setting & 1)
2780 ixgbe_set_itr(q_vector);
2781 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2782 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2783
2784 return 0;
2785}
2786
021230d4
AV		 2787/**
2788 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2789 * @adapter: board private structure
2790 *
2791 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2792 * interrupts from the kernel.
2793 **/
2794static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2795{
2796 struct net_device *netdev = adapter->netdev;
207867f5 2797 int vector, err;
e8e9f696 2798 int ri = 0, ti = 0;
021230d4 2799
49c7ffbe 2800 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2801 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2802 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2803
4ff7fb12 2804 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2805 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2806 "%s-%s-%d", netdev->name, "TxRx", ri++);
2807 ti++;
2808 } else if (q_vector->rx.ring) {
9fe93afd 2809 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2810 "%s-%s-%d", netdev->name, "rx", ri++);
2811 } else if (q_vector->tx.ring) {
9fe93afd 2812 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2813 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2814 } else {
2815 /* skip this unused q_vector */
2816 continue;
32aa77a4 2817 }
207867f5
AD		 2818 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2819 q_vector->name, q_vector);
9a799d71 2820 if (err) {
396e799c 2821 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2822 "Error: %d\n", err);
021230d4 2823 goto free_queue_irqs;
9a799d71 2824 }
207867f5
AD		 2825 /* If Flow Director is enabled, set interrupt affinity */
2826 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2827 /* assign the mask for this irq */
2828 irq_set_affinity_hint(entry->vector,
de88eeeb 2829 &q_vector->affinity_mask);
207867f5 2830 }
9a799d71
AK		 2831 }
2832
021230d4 2833 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2834 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2835 if (err) {
de88eeeb 2836 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2837 goto free_queue_irqs;
9a799d71
AK		 2838 }
2839
9a799d71
AK		 2840 return 0;
2841
021230d4 2842free_queue_irqs:
207867f5
AD		 2843 while (vector) {
2844 vector--;
2845 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2846 NULL);
2847 free_irq(adapter->msix_entries[vector].vector,
2848 adapter->q_vector[vector]);
2849 }
021230d4
AV		 2850 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2851 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2852 kfree(adapter->msix_entries);
2853 adapter->msix_entries = NULL;
9a799d71
AK		 2854 return err;
2855}
2856
2857/**
021230d4 2858 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2859 * @irq: interrupt number
2860 * @data: pointer to a network interface device structure
9a799d71
AK		 2861 **/
2862static irqreturn_t ixgbe_intr(int irq, void *data)
2863{
a65151ba 2864 struct ixgbe_adapter *adapter = data;
9a799d71 2865 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2866 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2867 u32 eicr;
2868
54037505 2869 /*
24ddd967 2870 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2871 * before the read of EICR.
2872 */
2873 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2874
021230d4 2875 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2876 * therefore no explicit interrupt disable is necessary */
021230d4 2877 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2878 if (!eicr) {
6af3b9eb
ET		 2879 /*
2880 * shared interrupt alert!
f47cf66e 2881 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2882 * have disabled interrupts due to EIAM
2883 * finish the workaround of silicon errata on 82598. Unmask
2884 * the interrupt that we masked before the EICR read.
2885 */
2886 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2887 ixgbe_irq_enable(adapter, true, true);
9a799d71 2888 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2889 }
9a799d71 2890
cf8280ee
JB		 2891 if (eicr & IXGBE_EICR_LSC)
2892 ixgbe_check_lsc(adapter);
021230d4 2893
bd508178
AD		 2894 switch (hw->mac.type) {
2895 case ixgbe_mac_82599EB:
e8e26350 2896 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2897 /* Fall through */
2898 case ixgbe_mac_X540:
d773ce2d
DS		 2899 if (eicr & IXGBE_EICR_ECC) {
2900 e_info(link, "Received ECC Err, initiating reset\n");
2901 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2902 ixgbe_service_event_schedule(adapter);
2903 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2904 }
4f51bf70 2905 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2906 break;
2907 default:
2908 break;
2909 }
e8e26350 2910
0befdb3e 2911 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2912 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2913 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2914
b9f6ed2b
AD		 2915 /* would disable interrupts here but EIAM disabled it */
2916 napi_schedule(&q_vector->napi);
9a799d71 2917
6af3b9eb
ET		 2918 /*
2919 * re-enable link(maybe) and non-queue interrupts, no flush.
2920 * ixgbe_poll will re-enable the queue interrupts
2921 */
6af3b9eb
ET		 2922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2923 ixgbe_irq_enable(adapter, false, false);
2924
9a799d71
AK		 2925 return IRQ_HANDLED;
2926}
2927
2928/**
2929 * ixgbe_request_irq - initialize interrupts
2930 * @adapter: board private structure
2931 *
2932 * Attempts to configure interrupts using the best available
2933 * capabilities of the hardware and kernel.
2934 **/
021230d4 2935static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2936{
2937 struct net_device *netdev = adapter->netdev;
021230d4 2938 int err;
9a799d71 2939
4cc6df29 2940 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2941 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2942 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2943 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2944 netdev->name, adapter);
4cc6df29 2945 else
a0607fd3 2946 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2947 netdev->name, adapter);
9a799d71 2948
de88eeeb 2949 if (err)
396e799c 2950 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2951
9a799d71
AK		 2952 return err;
2953}
2954
2955static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2956{
49c7ffbe 2957 int vector;
9a799d71 2958
49c7ffbe
AD		 2959 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2960 free_irq(adapter->pdev->irq, adapter);
2961 return;
2962 }
4cc6df29 2963
49c7ffbe
AD		 2964 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2965 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2966 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2967
49c7ffbe
AD		 2968 /* free only the irqs that were actually requested */
2969 if (!q_vector->rx.ring && !q_vector->tx.ring)
2970 continue;
207867f5 2971
49c7ffbe
AD		 2972 /* clear the affinity_mask in the IRQ descriptor */
2973 irq_set_affinity_hint(entry->vector, NULL);
2974
2975 free_irq(entry->vector, q_vector);
9a799d71 2976 }
49c7ffbe
AD		 2977
2978 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2979}
2980
22d5a71b
JB		 2981/**
2982 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2983 * @adapter: board private structure
2984 **/
2985static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2986{
bd508178
AD		 2987 switch (adapter->hw.mac.type) {
2988 case ixgbe_mac_82598EB:
835462fc 2989 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2990 break;
2991 case ixgbe_mac_82599EB:
b93a2226 2992 case ixgbe_mac_X540:
835462fc
NS		 2993 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2994 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2995 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2996 break;
2997 default:
2998 break;
22d5a71b
JB		 2999 }
3000 IXGBE_WRITE_FLUSH(&adapter->hw);
3001 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3002 int vector;
3003
3004 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3005 synchronize_irq(adapter->msix_entries[vector].vector);
3006
3007 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3008 } else {
3009 synchronize_irq(adapter->pdev->irq);
3010 }
3011}
3012
9a799d71
AK		 3013/**
3014 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3015 *
3016 **/
3017static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3018{
d5bf4f67 3019 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3020
d5bf4f67 3021 ixgbe_write_eitr(q_vector);
9a799d71 3022
e8e26350
PW		 3023 ixgbe_set_ivar(adapter, 0, 0, 0);
3024 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3025
396e799c 3026 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3027}
3028
43e69bf0
AD		 3029/**
3030 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3031 * @adapter: board private structure
3032 * @ring: structure containing ring specific data
3033 *
3034 * Configure the Tx descriptor ring after a reset.
3035 **/
84418e3b
AD		 3036void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3037 struct ixgbe_ring *ring)
43e69bf0
AD		 3038{
3039 struct ixgbe_hw *hw = &adapter->hw;
3040 u64 tdba = ring->dma;
2f1860b8 3041 int wait_loop = 10;
b88c6de2 3042 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3043 u8 reg_idx = ring->reg_idx;
43e69bf0 3044
2f1860b8 3045 /* disable queue to avoid issues while updating state */
b88c6de2 3046 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3047 IXGBE_WRITE_FLUSH(hw);
3048
43e69bf0 3049 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3050 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3051 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3052 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3053 ring->count * sizeof(union ixgbe_adv_tx_desc));
3054 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3055 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3056 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3057
b88c6de2
AD		 3058 /*
3059 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3060 * higher than 1 when:
3061 * - ITR is 0 as it could cause false TX hangs
3062 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3063 *
3064 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3065 * to or less than the number of on chip descriptors, which is
3066 * currently 40.
3067 */
67da097e
ET		 3068#if IS_ENABLED(CONFIG_BQL)
3069 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3070#else
e954b374 3071 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3072#endif
b88c6de2
AD		 3073 txdctl |= (1 << 16); /* WTHRESH = 1 */
3074 else
3075 txdctl |= (8 << 16); /* WTHRESH = 8 */
3076
e954b374
AD		 3077 /*
3078 * Setting PTHRESH to 32 both improves performance
3079 * and avoids a TX hang with DFP enabled
3080 */
b88c6de2
AD		 3081 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3082 32; /* PTHRESH = 32 */
2f1860b8
AD		 3083
3084 /* reinitialize flowdirector state */
39cb681b 3085 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3086 ring->atr_sample_rate = adapter->atr_sample_rate;
3087 ring->atr_count = 0;
3088 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3089 } else {
3090 ring->atr_sample_rate = 0;
3091 }
2f1860b8 3092
fd786b7b
AD		 3093 /* initialize XPS */
3094 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3095 struct ixgbe_q_vector *q_vector = ring->q_vector;
3096
3097 if (q_vector)
2a47fa45 3098 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3099 &q_vector->affinity_mask,
3100 ring->queue_index);
3101 }
3102
c84d324c
JF		 3103 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3104
2f1860b8 3105 /* enable queue */
2f1860b8
AD		 3106 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3107
3108 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3109 if (hw->mac.type == ixgbe_mac_82598EB &&
3110 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3111 return;
3112
3113 /* poll to verify queue is enabled */
3114 do {
032b4325 3115 usleep_range(1000, 2000);
2f1860b8
AD		 3116 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3117 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3118 if (!wait_loop)
3119 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3120}
3121
120ff942
AD		 3122static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3123{
3124 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3125 u32 rttdcs, mtqc;
8b1c0b24 3126 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3127
3128 if (hw->mac.type == ixgbe_mac_82598EB)
3129 return;
3130
3131 /* disable the arbiter while setting MTQC */
3132 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3133 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3134 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3135
3136 /* set transmit pool layout */
671c0adb
AD		 3137 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3138 mtqc = IXGBE_MTQC_VT_ENA;
3139 if (tcs > 4)
3140 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3141 else if (tcs > 1)
3142 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3143 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3144 mtqc |= IXGBE_MTQC_32VF;
3145 else
3146 mtqc |= IXGBE_MTQC_64VF;
3147 } else {
3148 if (tcs > 4)
3149 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3150 else if (tcs > 1)
3151 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3152 else
671c0adb
AD		 3153 mtqc = IXGBE_MTQC_64Q_1PB;
3154 }
120ff942 3155
671c0adb 3156 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3157
671c0adb
AD		 3158 /* Enable Security TX Buffer IFG for multiple pb */
3159 if (tcs) {
3160 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3161 sectx |= IXGBE_SECTX_DCB;
3162 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3163 }
3164
3165 /* re-enable the arbiter */
3166 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3167 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3168}
3169
9a799d71 3170/**
3a581073 3171 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3172 * @adapter: board private structure
3173 *
3174 * Configure the Tx unit of the MAC after a reset.
3175 **/
3176static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3177{
2f1860b8
AD		 3178 struct ixgbe_hw *hw = &adapter->hw;
3179 u32 dmatxctl;
43e69bf0 3180 u32 i;
9a799d71 3181
2f1860b8
AD		 3182 ixgbe_setup_mtqc(adapter);
3183
3184 if (hw->mac.type != ixgbe_mac_82598EB) {
3185 /* DMATXCTL.EN must be before Tx queues are enabled */
3186 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3187 dmatxctl |= IXGBE_DMATXCTL_TE;
3188 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3189 }
3190
9a799d71 3191 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3192 for (i = 0; i < adapter->num_tx_queues; i++)
3193 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3194}
3195
3ebe8fde
AD		 3196static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3197 struct ixgbe_ring *ring)
3198{
3199 struct ixgbe_hw *hw = &adapter->hw;
3200 u8 reg_idx = ring->reg_idx;
3201 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3202
3203 srrctl |= IXGBE_SRRCTL_DROP_EN;
3204
3205 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3206}
3207
3208static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3209 struct ixgbe_ring *ring)
3210{
3211 struct ixgbe_hw *hw = &adapter->hw;
3212 u8 reg_idx = ring->reg_idx;
3213 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3214
3215 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3216
3217 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3218}
3219
3220#ifdef CONFIG_IXGBE_DCB
3221void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3222#else
3223static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3224#endif
3225{
3226 int i;
3227 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3228
3229 if (adapter->ixgbe_ieee_pfc)
3230 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3231
3232 /*
3233 * We should set the drop enable bit if:
3234 * SR-IOV is enabled
3235 * or
3236 * Number of Rx queues > 1 and flow control is disabled
3237 *
3238 * This allows us to avoid head of line blocking for security
3239 * and performance reasons.
3240 */
3241 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3242 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3243 for (i = 0; i < adapter->num_rx_queues; i++)
3244 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3245 } else {
3246 for (i = 0; i < adapter->num_rx_queues; i++)
3247 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3248 }
3249}
3250
e8e26350 3251#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3252
a6616b42 3253static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3254 struct ixgbe_ring *rx_ring)
cc41ac7c 3255{
45e9baa5 3256 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3257 u32 srrctl;
bf29ee6c 3258 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3259
45e9baa5
AD		 3260 if (hw->mac.type == ixgbe_mac_82598EB) {
3261 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3262
45e9baa5
AD		 3263 /*
3264 * if VMDq is not active we must program one srrctl register
3265 * per RSS queue since we have enabled RDRXCTL.MVMEN
3266 */
3267 reg_idx &= mask;
3268 }
cc41ac7c 3269
45e9baa5
AD		 3270 /* configure header buffer length, needed for RSC */
3271 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3272
45e9baa5 3273 /* configure the packet buffer length */
f800326d 3274 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3275
3276 /* configure descriptor type */
f800326d 3277 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3278
45e9baa5 3279 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3280}
9a799d71 3281
05abb126 3282static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3283{
05abb126
AD		 3284 struct ixgbe_hw *hw = &adapter->hw;
3285 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3286 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3287 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3288 u32 mrqc = 0, reta = 0;
3289 u32 rxcsum;
3290 int i, j;
671c0adb
AD		 3291 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3292
671c0adb
AD		 3293 /*
3294 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3295 * make full use of any rings they may have. We will use the
3296 * PSRTYPE register to control how many rings we use within the PF.
3297 */
3298 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3299 rss_i = 2;
0cefafad 3300
05abb126
AD		 3301 /* Fill out hash function seeds */
3302 for (i = 0; i < 10; i++)
3303 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3304
3305 /* Fill out redirection table */
3306 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3307 if (j == rss_i)
05abb126
AD		 3308 j = 0;
3309 /* reta = 4-byte sliding window of
3310 * 0x00..(indices-1)(indices-1)00..etc. */
3311 reta = (reta << 8) | (j * 0x11);
3312 if ((i & 3) == 3)
3313 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3314 }
0cefafad 3315
05abb126
AD		 3316 /* Disable indicating checksum in descriptor, enables RSS hash */
3317 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3318 rxcsum |= IXGBE_RXCSUM_PCSD;
3319 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3320
671c0adb 3321 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3322 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3323 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3324 } else {
671c0adb
AD		 3325 u8 tcs = netdev_get_num_tc(adapter->netdev);
3326
3327 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3328 if (tcs > 4)
3329 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3330 else if (tcs > 1)
3331 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3332 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3333 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3334 else
671c0adb
AD		 3335 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3336 } else {
3337 if (tcs > 4)
8b1c0b24 3338 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3339 else if (tcs > 1)
3340 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3341 else
3342 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3343 }
0cefafad
JB		 3344 }
3345
05abb126 3346 /* Perform hash on these packet types */
671c0adb
AD		 3347 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3348 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3349 IXGBE_MRQC_RSS_FIELD_IPV6 |
3350 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3351
ef6afc0c
AD		 3352 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3353 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3354 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3355 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3356
05abb126 3357 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3358}
3359
bb5a9ad2
NS		 3360/**
3361 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3362 * @adapter: address of board private structure
3363 * @index: index of ring to set
bb5a9ad2 3364 **/
082757af 3365static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3366 struct ixgbe_ring *ring)
bb5a9ad2 3367{
bb5a9ad2 3368 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3369 u32 rscctrl;
bf29ee6c 3370 u8 reg_idx = ring->reg_idx;
7367096a 3371
7d637bcc 3372 if (!ring_is_rsc_enabled(ring))
7367096a 3373 return;
bb5a9ad2 3374
7367096a 3375 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3376 rscctrl |= IXGBE_RSCCTL_RSCEN;
3377 /*
3378 * we must limit the number of descriptors so that the
3379 * total size of max desc * buf_len is not greater
642c680e 3380 * than 65536
bb5a9ad2 3381 */
f800326d 3382 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3383 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3384}
3385
9e10e045
AD		 3386#define IXGBE_MAX_RX_DESC_POLL 10
3387static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3388 struct ixgbe_ring *ring)
3389{
3390 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3391 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3392 u32 rxdctl;
bf29ee6c 3393 u8 reg_idx = ring->reg_idx;
9e10e045 3394
b0483c8f
MR		 3395 if (ixgbe_removed(hw->hw_addr))
3396 return;
9e10e045
AD		 3397 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3398 if (hw->mac.type == ixgbe_mac_82598EB &&
3399 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3400 return;
3401
3402 do {
032b4325 3403 usleep_range(1000, 2000);
9e10e045
AD		 3404 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3405 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3406
3407 if (!wait_loop) {
3408 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3409 "the polling period\n", reg_idx);
3410 }
3411}
3412
2d39d576
YZ		 3413void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3414 struct ixgbe_ring *ring)
3415{
3416 struct ixgbe_hw *hw = &adapter->hw;
3417 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3418 u32 rxdctl;
3419 u8 reg_idx = ring->reg_idx;
3420
b0483c8f
MR		 3421 if (ixgbe_removed(hw->hw_addr))
3422 return;
2d39d576
YZ		 3423 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3424 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3425
3426 /* write value back with RXDCTL.ENABLE bit cleared */
3427 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3428
3429 if (hw->mac.type == ixgbe_mac_82598EB &&
3430 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3431 return;
3432
3433 /* the hardware may take up to 100us to really disable the rx queue */
3434 do {
3435 udelay(10);
3436 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3437 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3438
3439 if (!wait_loop) {
3440 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3441 "the polling period\n", reg_idx);
3442 }
3443}
3444
84418e3b
AD		 3445void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3446 struct ixgbe_ring *ring)
acd37177
AD		 3447{
3448 struct ixgbe_hw *hw = &adapter->hw;
3449 u64 rdba = ring->dma;
9e10e045 3450 u32 rxdctl;
bf29ee6c 3451 u8 reg_idx = ring->reg_idx;
acd37177 3452
9e10e045
AD		 3453 /* disable queue to avoid issues while updating state */
3454 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3455 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3456
acd37177
AD		 3457 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3458 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3459 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3460 ring->count * sizeof(union ixgbe_adv_rx_desc));
3461 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3462 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3463 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3464
3465 ixgbe_configure_srrctl(adapter, ring);
3466 ixgbe_configure_rscctl(adapter, ring);
3467
3468 if (hw->mac.type == ixgbe_mac_82598EB) {
3469 /*
3470 * enable cache line friendly hardware writes:
3471 * PTHRESH=32 descriptors (half the internal cache),
3472 * this also removes ugly rx_no_buffer_count increment
3473 * HTHRESH=4 descriptors (to minimize latency on fetch)
3474 * WTHRESH=8 burst writeback up to two cache lines
3475 */
3476 rxdctl &= ~0x3FFFFF;
3477 rxdctl |= 0x080420;
3478 }
3479
3480 /* enable receive descriptor ring */
3481 rxdctl |= IXGBE_RXDCTL_ENABLE;
3482 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3483
3484 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3485 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3486}
3487
48654521
AD		 3488static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3489{
3490 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3491 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3492 u16 pool;
48654521
AD		 3493
3494 /* PSRTYPE must be initialized in non 82598 adapters */
3495 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3496 IXGBE_PSRTYPE_UDPHDR |
3497 IXGBE_PSRTYPE_IPV4HDR |
48654521 3498 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3499 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3500
3501 if (hw->mac.type == ixgbe_mac_82598EB)
3502 return;
3503
fbe7ca7f
AD		 3504 if (rss_i > 3)
3505 psrtype |= 2 << 29;
3506 else if (rss_i > 1)
3507 psrtype |= 1 << 29;
48654521 3508
2a47fa45
JF		 3509 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3510 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3511}
3512
f5b4a52e
AD		 3513static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3514{
3515 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3516 u32 reg_offset, vf_shift;
435b19f6 3517 u32 gcr_ext, vmdctl;
de4c7f65 3518 int i;
f5b4a52e
AD		 3519
3520 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3521 return;
3522
3523 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3524 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3525 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3526 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3527 vmdctl |= IXGBE_VT_CTL_REPLEN;
3528 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3529
1d9c0bfd
AD		 3530 vf_shift = VMDQ_P(0) % 32;
3531 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3532
3533 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3534 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3535 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3536 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3537 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3538 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3539 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3540
3541 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3542 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3543
3544 /*
3545 * Set up VF register offsets for selected VT Mode,
3546 * i.e. 32 or 64 VFs for SR-IOV
3547 */
73079ea0
AD		 3548 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3549 case IXGBE_82599_VMDQ_8Q_MASK:
3550 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3551 break;
3552 case IXGBE_82599_VMDQ_4Q_MASK:
3553 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3554 break;
3555 default:
3556 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3557 break;
3558 }
3559
f5b4a52e
AD		 3560 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3561
435b19f6 3562
a985b6c3 3563 /* Enable MAC Anti-Spoofing */
435b19f6 3564 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3565 adapter->num_vfs);
de4c7f65
GR		 3566 /* For VFs that have spoof checking turned off */
3567 for (i = 0; i < adapter->num_vfs; i++) {
3568 if (!adapter->vfinfo[i].spoofchk_enabled)
3569 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3570 }
f5b4a52e
AD		 3571}
3572
477de6ed 3573static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3574{
9a799d71
AK		 3575 struct ixgbe_hw *hw = &adapter->hw;
3576 struct net_device *netdev = adapter->netdev;
3577 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3578 struct ixgbe_ring *rx_ring;
3579 int i;
3580 u32 mhadd, hlreg0;
48654521 3581
63f39bd1 3582#ifdef IXGBE_FCOE
477de6ed
AD		 3583 /* adjust max frame to be able to do baby jumbo for FCoE */
3584 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3585 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3586 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3587
477de6ed 3588#endif /* IXGBE_FCOE */
872844dd
AD		 3589
3590 /* adjust max frame to be at least the size of a standard frame */
3591 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3592 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3593
477de6ed
AD		 3594 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3595 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3596 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3597 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3598
3599 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3600 }
3601
3602 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3603 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3604 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3605 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3606
0cefafad
JB		 3607 /*
3608 * Setup the HW Rx Head and Tail Descriptor Pointers and
3609 * the Base and Length of the Rx Descriptor Ring
3610 */
9a799d71 3611 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3612 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3613 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3614 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3615 else
7d637bcc 3616 clear_ring_rsc_enabled(rx_ring);
477de6ed 3617 }
477de6ed
AD		 3618}
3619
7367096a
AD		 3620static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3621{
3622 struct ixgbe_hw *hw = &adapter->hw;
3623 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3624
3625 switch (hw->mac.type) {
3626 case ixgbe_mac_82598EB:
3627 /*
3628 * For VMDq support of different descriptor types or
3629 * buffer sizes through the use of multiple SRRCTL
3630 * registers, RDRXCTL.MVMEN must be set to 1
3631 *
3632 * also, the manual doesn't mention it clearly but DCA hints
3633 * will only use queue 0's tags unless this bit is set. Side
3634 * effects of setting this bit are only that SRRCTL must be
3635 * fully programmed [0..15]
3636 */
3637 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3638 break;
3639 case ixgbe_mac_82599EB:
b93a2226 3640 case ixgbe_mac_X540:
7367096a
AD		 3641 /* Disable RSC for ACK packets */
3642 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3643 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3644 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3645 /* hardware requires some bits to be set by default */
3646 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3647 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3648 break;
3649 default:
3650 /* We should do nothing since we don't know this hardware */
3651 return;
3652 }
3653
3654 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3655}
3656
477de6ed
AD		 3657/**
3658 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3659 * @adapter: board private structure
3660 *
3661 * Configure the Rx unit of the MAC after a reset.
3662 **/
3663static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3664{
3665 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3666 int i;
6dcc28b9 3667 u32 rxctrl, rfctl;
477de6ed
AD		 3668
3669 /* disable receives while setting up the descriptors */
3670 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3671 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3672
3673 ixgbe_setup_psrtype(adapter);
7367096a 3674 ixgbe_setup_rdrxctl(adapter);
477de6ed 3675
6dcc28b9
JK		 3676 /* RSC Setup */
3677 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3678 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3679 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3680 rfctl |= IXGBE_RFCTL_RSC_DIS;
3681 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3682
9e10e045 3683 /* Program registers for the distribution of queues */
f5b4a52e 3684 ixgbe_setup_mrqc(adapter);
f5b4a52e 3685
477de6ed
AD		 3686 /* set_rx_buffer_len must be called before ring initialization */
3687 ixgbe_set_rx_buffer_len(adapter);
3688
3689 /*
3690 * Setup the HW Rx Head and Tail Descriptor Pointers and
3691 * the Base and Length of the Rx Descriptor Ring
3692 */
9e10e045
AD		 3693 for (i = 0; i < adapter->num_rx_queues; i++)
3694 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3695
9e10e045
AD		 3696 /* disable drop enable for 82598 parts */
3697 if (hw->mac.type == ixgbe_mac_82598EB)
3698 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3699
3700 /* enable all receives */
3701 rxctrl |= IXGBE_RXCTRL_RXEN;
3702 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3703}
3704
80d5c368
PM		 3705static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3706 __be16 proto, u16 vid)
068c89b0
DS		 3707{
3708 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3709 struct ixgbe_hw *hw = &adapter->hw;
3710
3711 /* add VID to filter table */
1d9c0bfd 3712 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3713 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3714
3715 return 0;
068c89b0
DS		 3716}
3717
80d5c368
PM		 3718static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3719 __be16 proto, u16 vid)
068c89b0
DS		 3720{
3721 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3722 struct ixgbe_hw *hw = &adapter->hw;
3723
068c89b0 3724 /* remove VID from filter table */
1d9c0bfd 3725 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3726 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3727
3728 return 0;
068c89b0
DS		 3729}
3730
5f6c0181
JB		 3731/**
3732 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3733 * @adapter: driver data
3734 */
3735static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3736{
3737 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3738 u32 vlnctrl;
3739
3740 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3741 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3742 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3743}
3744
3745/**
3746 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3747 * @adapter: driver data
3748 */
3749static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3750{
3751 struct ixgbe_hw *hw = &adapter->hw;
3752 u32 vlnctrl;
3753
3754 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3755 vlnctrl |= IXGBE_VLNCTRL_VFE;
3756 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3757 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3758}
3759
3760/**
3761 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3762 * @adapter: driver data
3763 */
3764static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3765{
3766 struct ixgbe_hw *hw = &adapter->hw;
3767 u32 vlnctrl;
5f6c0181
JB		 3768 int i, j;
3769
3770 switch (hw->mac.type) {
3771 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3772 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3773 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3774 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3775 break;
3776 case ixgbe_mac_82599EB:
b93a2226 3777 case ixgbe_mac_X540:
5f6c0181 3778 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3779 struct ixgbe_ring *ring = adapter->rx_ring[i];
3780
3781 if (ring->l2_accel_priv)
3782 continue;
3783 j = ring->reg_idx;
5f6c0181
JB		 3784 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3785 vlnctrl &= ~IXGBE_RXDCTL_VME;
3786 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3787 }
3788 break;
3789 default:
3790 break;
3791 }
3792}
3793
3794/**
f62bbb5e 3795 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3796 * @adapter: driver data
3797 */
f62bbb5e 3798static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3799{
3800 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3801 u32 vlnctrl;
5f6c0181
JB		 3802 int i, j;
3803
3804 switch (hw->mac.type) {
3805 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3806 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3807 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3808 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3809 break;
3810 case ixgbe_mac_82599EB:
b93a2226 3811 case ixgbe_mac_X540:
5f6c0181 3812 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3813 struct ixgbe_ring *ring = adapter->rx_ring[i];
3814
3815 if (ring->l2_accel_priv)
3816 continue;
3817 j = ring->reg_idx;
5f6c0181
JB		 3818 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3819 vlnctrl |= IXGBE_RXDCTL_VME;
3820 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3821 }
3822 break;
3823 default:
3824 break;
3825 }
3826}
3827
9a799d71
AK		 3828static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3829{
f62bbb5e 3830 u16 vid;
9a799d71 3831
80d5c368 3832 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3833
3834 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3835 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3836}
3837
2850062a
AD		 3838/**
3839 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3840 * @netdev: network interface device structure
3841 *
3842 * Writes unicast address list to the RAR table.
3843 * Returns: -ENOMEM on failure/insufficient address space
3844 * 0 on no addresses written
3845 * X on writing X addresses to the RAR table
3846 **/
3847static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3848{
3849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3850 struct ixgbe_hw *hw = &adapter->hw;
95447461 3851 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3852 int count = 0;
3853
2a47fa45 3854 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
95447461
JF		 3855 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3856 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3857
2850062a
AD		 3858 /* return ENOMEM indicating insufficient memory for addresses */
3859 if (netdev_uc_count(netdev) > rar_entries)
3860 return -ENOMEM;
3861
95447461 3862 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3863 struct netdev_hw_addr *ha;
3864 /* return error if we do not support writing to RAR table */
3865 if (!hw->mac.ops.set_rar)
3866 return -ENOMEM;
3867
3868 netdev_for_each_uc_addr(ha, netdev) {
3869 if (!rar_entries)
3870 break;
3871 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3872 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3873 count++;
3874 }
3875 }
3876 /* write the addresses in reverse order to avoid write combining */
3877 for (; rar_entries > 0 ; rar_entries--)
3878 hw->mac.ops.clear_rar(hw, rar_entries);
3879
3880 return count;
3881}
3882
9a799d71 3883/**
2c5645cf 3884 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3885 * @netdev: network interface device structure
3886 *
2c5645cf
CL		 3887 * The set_rx_method entry point is called whenever the unicast/multicast
3888 * address list or the network interface flags are updated. This routine is
3889 * responsible for configuring the hardware for proper unicast, multicast and
3890 * promiscuous mode.
9a799d71 3891 **/
7f870475 3892void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3893{
3894 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3895 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3896 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3897 int count;
9a799d71
AK		 3898
3899 /* Check for Promiscuous and All Multicast modes */
3900
3901 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3902
f5dc442b 3903 /* set all bits that we expect to always be set */
3f2d1c0f 3904 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3905 fctrl |= IXGBE_FCTRL_BAM;
3906 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3907 fctrl |= IXGBE_FCTRL_PMCF;
3908
2850062a
AD		 3909 /* clear the bits we are changing the status of */
3910 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3911
9a799d71 3912 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3913 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3914 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3915 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3916 /* Only disable hardware filter vlans in promiscuous mode
3917 * if SR-IOV and VMDQ are disabled - otherwise ensure
3918 * that hardware VLAN filters remain enabled.
3919 */
3920 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3921 IXGBE_FLAG_SRIOV_ENABLED)))
3922 ixgbe_vlan_filter_disable(adapter);
3923 else
3924 ixgbe_vlan_filter_enable(adapter);
9a799d71 3925 } else {
746b9f02
PM		 3926 if (netdev->flags & IFF_ALLMULTI) {
3927 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3928 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3929 }
5f6c0181 3930 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3931 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3932 }
3933
3934 /*
3935 * Write addresses to available RAR registers, if there is not
3936 * sufficient space to store all the addresses then enable
3937 * unicast promiscuous mode
3938 */
3939 count = ixgbe_write_uc_addr_list(netdev);
3940 if (count < 0) {
3941 fctrl |= IXGBE_FCTRL_UPE;
3942 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3943 }
3944
cf78959c
ET		 3945 /* Write addresses to the MTA, if the attempt fails
3946 * then we should just turn on promiscuous mode so
3947 * that we can at least receive multicast traffic
3948 */
3949 hw->mac.ops.update_mc_addr_list(hw, netdev);
3950 vmolr |= IXGBE_VMOLR_ROMPE;
3951
1d9c0bfd 3952 if (adapter->num_vfs)
1cdd1ec8 3953 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3954
3955 if (hw->mac.type != ixgbe_mac_82598EB) {
3956 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3957 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3958 IXGBE_VMOLR_ROPE);
1d9c0bfd 3959 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3960 }
3961
3f2d1c0f
BG		 3962 /* This is useful for sniffing bad packets. */
3963 if (adapter->netdev->features & NETIF_F_RXALL) {
3964 /* UPE and MPE will be handled by normal PROMISC logic
3965 * in e1000e_set_rx_mode */
3966 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3967 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3968 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3969
3970 fctrl &= ~(IXGBE_FCTRL_DPF);
3971 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3972 }
3973
2850062a 3974 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3975
f646968f 3976 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3977 ixgbe_vlan_strip_enable(adapter);
3978 else
3979 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3980}
3981
021230d4
AV		 3982static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3983{
3984 int q_idx;
021230d4 3985
5a85e737
ET		 3986 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3987 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 3988 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 3989 }
021230d4
AV		 3990}
3991
3992static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3993{
3994 int q_idx;
021230d4 3995
5a85e737 3996 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 3997 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 3998 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 3999 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4000 usleep_range(1000, 20000);
5a85e737
ET		 4001 }
4002 }
021230d4
AV		 4003}
4004
7a6b6f51 4005#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4006/**
2f90b865
AD		 4007 * ixgbe_configure_dcb - Configure DCB hardware
4008 * @adapter: ixgbe adapter struct
4009 *
4010 * This is called by the driver on open to configure the DCB hardware.
4011 * This is also called by the gennetlink interface when reconfiguring
4012 * the DCB state.
4013 */
4014static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4015{
4016 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4017 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4018
67ebd791
AD		 4019 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4020 if (hw->mac.type == ixgbe_mac_82598EB)
4021 netif_set_gso_max_size(adapter->netdev, 65536);
4022 return;
4023 }
4024
4025 if (hw->mac.type == ixgbe_mac_82598EB)
4026 netif_set_gso_max_size(adapter->netdev, 32768);
4027
971060b1 4028#ifdef IXGBE_FCOE
b120818e
JF		 4029 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4030 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4031#endif
b120818e
JF		 4032
4033 /* reconfigure the hardware */
4034 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4035 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4036 DCB_TX_CONFIG);
4037 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4038 DCB_RX_CONFIG);
4039 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4040 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4041 ixgbe_dcb_hw_ets(&adapter->hw,
4042 adapter->ixgbe_ieee_ets,
4043 max_frame);
4044 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4045 adapter->ixgbe_ieee_pfc->pfc_en,
4046 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4047 }
8187cd48
JF		 4048
4049 /* Enable RSS Hash per TC */
4050 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4051 u32 msb = 0;
4052 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4053
d411a936
AD		 4054 while (rss_i) {
4055 msb++;
4056 rss_i >>= 1;
4057 }
8187cd48 4058
4ae63730
AD		 4059 /* write msb to all 8 TCs in one write */
4060 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4061 }
2f90b865 4062}
9da712d2
JF		 4063#endif
4064
4065/* Additional bittime to account for IXGBE framing */
4066#define IXGBE_ETH_FRAMING 20
4067
49ce9c2c 4068/**
9da712d2
JF		 4069 * ixgbe_hpbthresh - calculate high water mark for flow control
4070 *
4071 * @adapter: board private structure to calculate for
49ce9c2c 4072 * @pb: packet buffer to calculate
9da712d2
JF		 4073 */
4074static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4075{
4076 struct ixgbe_hw *hw = &adapter->hw;
4077 struct net_device *dev = adapter->netdev;
4078 int link, tc, kb, marker;
4079 u32 dv_id, rx_pba;
4080
4081 /* Calculate max LAN frame size */
4082 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4083
4084#ifdef IXGBE_FCOE
4085 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4086 if ((dev->features & NETIF_F_FCOE_MTU) &&
4087 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4088 (pb == ixgbe_fcoe_get_tc(adapter)))
4089 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 4090
4091#endif
9da712d2
JF		 4092 /* Calculate delay value for device */
4093 switch (hw->mac.type) {
4094 case ixgbe_mac_X540:
4095 dv_id = IXGBE_DV_X540(link, tc);
4096 break;
4097 default:
4098 dv_id = IXGBE_DV(link, tc);
4099 break;
4100 }
4101
4102 /* Loopback switch introduces additional latency */
4103 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4104 dv_id += IXGBE_B2BT(tc);
4105
4106 /* Delay value is calculated in bit times convert to KB */
4107 kb = IXGBE_BT2KB(dv_id);
4108 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4109
4110 marker = rx_pba - kb;
4111
4112 /* It is possible that the packet buffer is not large enough
4113 * to provide required headroom. In this case throw an error
4114 * to user and a do the best we can.
4115 */
4116 if (marker < 0) {
4117 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4118 "headroom to support flow control."
4119 "Decrease MTU or number of traffic classes\n", pb);
4120 marker = tc + 1;
4121 }
4122
4123 return marker;
4124}
4125
49ce9c2c 4126/**
9da712d2
JF		 4127 * ixgbe_lpbthresh - calculate low water mark for for flow control
4128 *
4129 * @adapter: board private structure to calculate for
49ce9c2c 4130 * @pb: packet buffer to calculate
9da712d2
JF		 4131 */
4132static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4133{
4134 struct ixgbe_hw *hw = &adapter->hw;
4135 struct net_device *dev = adapter->netdev;
4136 int tc;
4137 u32 dv_id;
4138
4139 /* Calculate max LAN frame size */
4140 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4141
4142 /* Calculate delay value for device */
4143 switch (hw->mac.type) {
4144 case ixgbe_mac_X540:
4145 dv_id = IXGBE_LOW_DV_X540(tc);
4146 break;
4147 default:
4148 dv_id = IXGBE_LOW_DV(tc);
4149 break;
4150 }
4151
4152 /* Delay value is calculated in bit times convert to KB */
4153 return IXGBE_BT2KB(dv_id);
4154}
4155
4156/*
4157 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4158 */
4159static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4160{
4161 struct ixgbe_hw *hw = &adapter->hw;
4162 int num_tc = netdev_get_num_tc(adapter->netdev);
4163 int i;
4164
4165 if (!num_tc)
4166 num_tc = 1;
4167
4168 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4169
4170 for (i = 0; i < num_tc; i++) {
4171 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4172
4173 /* Low water marks must not be larger than high water marks */
4174 if (hw->fc.low_water > hw->fc.high_water[i])
4175 hw->fc.low_water = 0;
4176 }
4177}
4178
80605c65
JF		 4179static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4180{
80605c65 4181 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4182 int hdrm;
4183 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4184
4185 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4186 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4187 hdrm = 32 << adapter->fdir_pballoc;
4188 else
4189 hdrm = 0;
80605c65 4190
f7e1027f 4191 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4192 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4193}
4194
e4911d57
AD		 4195static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4196{
4197 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4198 struct hlist_node *node2;
e4911d57
AD		 4199 struct ixgbe_fdir_filter *filter;
4200
4201 spin_lock(&adapter->fdir_perfect_lock);
4202
4203 if (!hlist_empty(&adapter->fdir_filter_list))
4204 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4205
b67bfe0d 4206 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4207 &adapter->fdir_filter_list, fdir_node) {
4208 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4209 &filter->filter,
4210 filter->sw_idx,
4211 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4212 IXGBE_FDIR_DROP_QUEUE :
4213 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4214 }
4215
4216 spin_unlock(&adapter->fdir_perfect_lock);
4217}
4218
2a47fa45
JF		 4219static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4220 struct ixgbe_adapter *adapter)
4221{
4222 struct ixgbe_hw *hw = &adapter->hw;
4223 u32 vmolr;
4224
4225 /* No unicast promiscuous support for VMDQ devices. */
4226 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4227 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4228
4229 /* clear the affected bit */
4230 vmolr &= ~IXGBE_VMOLR_MPE;
4231
4232 if (dev->flags & IFF_ALLMULTI) {
4233 vmolr |= IXGBE_VMOLR_MPE;
4234 } else {
4235 vmolr |= IXGBE_VMOLR_ROMPE;
4236 hw->mac.ops.update_mc_addr_list(hw, dev);
4237 }
4238 ixgbe_write_uc_addr_list(adapter->netdev);
4239 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4240}
4241
4242static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4243 u8 *addr, u16 pool)
4244{
4245 struct ixgbe_hw *hw = &adapter->hw;
4246 unsigned int entry;
4247
4248 entry = hw->mac.num_rar_entries - pool;
4249 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4250}
4251
4252static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4253{
4254 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4255 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4256 struct ixgbe_hw *hw = &adapter->hw;
4257 u16 pool = vadapter->pool;
4258 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4259 IXGBE_PSRTYPE_UDPHDR |
4260 IXGBE_PSRTYPE_IPV4HDR |
4261 IXGBE_PSRTYPE_L2HDR |
4262 IXGBE_PSRTYPE_IPV6HDR;
4263
4264 if (hw->mac.type == ixgbe_mac_82598EB)
4265 return;
4266
4267 if (rss_i > 3)
4268 psrtype |= 2 << 29;
4269 else if (rss_i > 1)
4270 psrtype |= 1 << 29;
4271
4272 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4273}
4274
4275/**
4276 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4277 * @rx_ring: ring to free buffers from
4278 **/
4279static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4280{
4281 struct device *dev = rx_ring->dev;
4282 unsigned long size;
4283 u16 i;
4284
4285 /* ring already cleared, nothing to do */
4286 if (!rx_ring->rx_buffer_info)
4287 return;
4288
4289 /* Free all the Rx ring sk_buffs */
4290 for (i = 0; i < rx_ring->count; i++) {
4291 struct ixgbe_rx_buffer *rx_buffer;
4292
4293 rx_buffer = &rx_ring->rx_buffer_info[i];
4294 if (rx_buffer->skb) {
4295 struct sk_buff *skb = rx_buffer->skb;
4296 if (IXGBE_CB(skb)->page_released) {
4297 dma_unmap_page(dev,
4298 IXGBE_CB(skb)->dma,
4299 ixgbe_rx_bufsz(rx_ring),
4300 DMA_FROM_DEVICE);
4301 IXGBE_CB(skb)->page_released = false;
4302 }
4303 dev_kfree_skb(skb);
4304 }
4305 rx_buffer->skb = NULL;
4306 if (rx_buffer->dma)
4307 dma_unmap_page(dev, rx_buffer->dma,
4308 ixgbe_rx_pg_size(rx_ring),
4309 DMA_FROM_DEVICE);
4310 rx_buffer->dma = 0;
4311 if (rx_buffer->page)
4312 __free_pages(rx_buffer->page,
4313 ixgbe_rx_pg_order(rx_ring));
4314 rx_buffer->page = NULL;
4315 }
4316
4317 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4318 memset(rx_ring->rx_buffer_info, 0, size);
4319
4320 /* Zero out the descriptor ring */
4321 memset(rx_ring->desc, 0, rx_ring->size);
4322
4323 rx_ring->next_to_alloc = 0;
4324 rx_ring->next_to_clean = 0;
4325 rx_ring->next_to_use = 0;
4326}
4327
4328static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4329 struct ixgbe_ring *rx_ring)
4330{
4331 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4332 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4333
4334 /* shutdown specific queue receive and wait for dma to settle */
4335 ixgbe_disable_rx_queue(adapter, rx_ring);
4336 usleep_range(10000, 20000);
4337 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4338 ixgbe_clean_rx_ring(rx_ring);
4339 rx_ring->l2_accel_priv = NULL;
4340}
4341
ae72c8d0
JF		 4342static int ixgbe_fwd_ring_down(struct net_device *vdev,
4343 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4344{
4345 struct ixgbe_adapter *adapter = accel->real_adapter;
4346 unsigned int rxbase = accel->rx_base_queue;
4347 unsigned int txbase = accel->tx_base_queue;
4348 int i;
4349
4350 netif_tx_stop_all_queues(vdev);
4351
4352 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4353 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4354 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4355 }
4356
4357 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4358 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4359 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4360 }
4361
4362
4363 return 0;
4364}
4365
4366static int ixgbe_fwd_ring_up(struct net_device *vdev,
4367 struct ixgbe_fwd_adapter *accel)
4368{
4369 struct ixgbe_adapter *adapter = accel->real_adapter;
4370 unsigned int rxbase, txbase, queues;
4371 int i, baseq, err = 0;
4372
4373 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4374 return 0;
4375
4376 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4377 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4378 accel->pool, adapter->num_rx_pools,
4379 baseq, baseq + adapter->num_rx_queues_per_pool,
4380 adapter->fwd_bitmask);
4381
4382 accel->netdev = vdev;
4383 accel->rx_base_queue = rxbase = baseq;
4384 accel->tx_base_queue = txbase = baseq;
4385
4386 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4387 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4388
4389 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4390 adapter->rx_ring[rxbase + i]->netdev = vdev;
4391 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4392 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4393 }
4394
4395 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4396 adapter->tx_ring[txbase + i]->netdev = vdev;
4397 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4398 }
4399
4400 queues = min_t(unsigned int,
4401 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4402 err = netif_set_real_num_tx_queues(vdev, queues);
4403 if (err)
4404 goto fwd_queue_err;
4405
2a47fa45
JF		 4406 err = netif_set_real_num_rx_queues(vdev, queues);
4407 if (err)
4408 goto fwd_queue_err;
4409
4410 if (is_valid_ether_addr(vdev->dev_addr))
4411 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4412
4413 ixgbe_fwd_psrtype(accel);
4414 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4415 return err;
4416fwd_queue_err:
4417 ixgbe_fwd_ring_down(vdev, accel);
4418 return err;
4419}
4420
4421static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4422{
4423 struct net_device *upper;
4424 struct list_head *iter;
4425 int err;
4426
4427 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4428 if (netif_is_macvlan(upper)) {
4429 struct macvlan_dev *dfwd = netdev_priv(upper);
4430 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4431
4432 if (dfwd->fwd_priv) {
4433 err = ixgbe_fwd_ring_up(upper, vadapter);
4434 if (err)
4435 continue;
4436 }
4437 }
4438 }
4439}
4440
9a799d71
AK		 4441static void ixgbe_configure(struct ixgbe_adapter *adapter)
4442{
d2f5e7f3
AS		 4443 struct ixgbe_hw *hw = &adapter->hw;
4444
80605c65 4445 ixgbe_configure_pb(adapter);
7a6b6f51 4446#ifdef CONFIG_IXGBE_DCB
67ebd791 4447 ixgbe_configure_dcb(adapter);
2f90b865 4448#endif
b35d4d42
AD		 4449 /*
4450 * We must restore virtualization before VLANs or else
4451 * the VLVF registers will not be populated
4452 */
4453 ixgbe_configure_virtualization(adapter);
9a799d71 4454
4c1d7b4b 4455 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4456 ixgbe_restore_vlan(adapter);
4457
d2f5e7f3
AS		 4458 switch (hw->mac.type) {
4459 case ixgbe_mac_82599EB:
4460 case ixgbe_mac_X540:
4461 hw->mac.ops.disable_rx_buff(hw);
4462 break;
4463 default:
4464 break;
4465 }
4466
c4cf55e5 4467 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4468 ixgbe_init_fdir_signature_82599(&adapter->hw,
4469 adapter->fdir_pballoc);
e4911d57
AD		 4470 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4471 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4472 adapter->fdir_pballoc);
4473 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4474 }
4c1d7b4b 4475
d2f5e7f3
AS		 4476 switch (hw->mac.type) {
4477 case ixgbe_mac_82599EB:
4478 case ixgbe_mac_X540:
4479 hw->mac.ops.enable_rx_buff(hw);
4480 break;
4481 default:
4482 break;
4483 }
4484
7c8ae65a
AD		 4485#ifdef IXGBE_FCOE
4486 /* configure FCoE L2 filters, redirection table, and Rx control */
4487 ixgbe_configure_fcoe(adapter);
4488
4489#endif /* IXGBE_FCOE */
9a799d71
AK		 4490 ixgbe_configure_tx(adapter);
4491 ixgbe_configure_rx(adapter);
2a47fa45 4492 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4493}
4494
e8e26350
PW		 4495static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4496{
4497 switch (hw->phy.type) {
4498 case ixgbe_phy_sfp_avago:
4499 case ixgbe_phy_sfp_ftl:
4500 case ixgbe_phy_sfp_intel:
4501 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4502 case ixgbe_phy_sfp_passive_tyco:
4503 case ixgbe_phy_sfp_passive_unknown:
4504 case ixgbe_phy_sfp_active_unknown:
4505 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4506 case ixgbe_phy_qsfp_passive_unknown:
4507 case ixgbe_phy_qsfp_active_unknown:
4508 case ixgbe_phy_qsfp_intel:
4509 case ixgbe_phy_qsfp_unknown:
e8e26350 4510 return true;
8917b447
AD		 4511 case ixgbe_phy_nl:
4512 if (hw->mac.type == ixgbe_mac_82598EB)
4513 return true;
e8e26350
PW		 4514 default:
4515 return false;
4516 }
4517}
4518
0ecc061d 4519/**
e8e26350
PW		 4520 * ixgbe_sfp_link_config - set up SFP+ link
4521 * @adapter: pointer to private adapter struct
4522 **/
4523static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4524{
7086400d 4525 /*
52f33af8 4526 * We are assuming the worst case scenario here, and that
7086400d
AD		 4527 * is that an SFP was inserted/removed after the reset
4528 * but before SFP detection was enabled. As such the best
4529 * solution is to just start searching as soon as we start
4530 */
4531 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4532 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4533
7086400d 4534 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4535}
4536
4537/**
4538 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4539 * @hw: pointer to private hardware struct
4540 *
4541 * Returns 0 on success, negative on failure
4542 **/
e8e26350 4543static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4544{
3d292265
JH		 4545 u32 speed;
4546 bool autoneg, link_up = false;
0ecc061d
PWJ		 4547 u32 ret = IXGBE_ERR_LINK_SETUP;
4548
4549 if (hw->mac.ops.check_link)
3d292265 4550 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4551
4552 if (ret)
4553 goto link_cfg_out;
4554
3d292265
JH		 4555 speed = hw->phy.autoneg_advertised;
4556 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4557 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4558 &autoneg);
0ecc061d
PWJ		 4559 if (ret)
4560 goto link_cfg_out;
4561
8620a103 4562 if (hw->mac.ops.setup_link)
fd0326f2 4563 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4564link_cfg_out:
4565 return ret;
4566}
4567
a34bcfff 4568static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4569{
9a799d71 4570 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4571 u32 gpie = 0;
9a799d71 4572
9b471446 4573 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4574 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4575 IXGBE_GPIE_OCD;
4576 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4577 /*
4578 * use EIAM to auto-mask when MSI-X interrupt is asserted
4579 * this saves a register write for every interrupt
4580 */
4581 switch (hw->mac.type) {
4582 case ixgbe_mac_82598EB:
4583 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4584 break;
9b471446 4585 case ixgbe_mac_82599EB:
b93a2226
DS		 4586 case ixgbe_mac_X540:
4587 default:
9b471446
JB		 4588 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4589 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4590 break;
4591 }
4592 } else {
021230d4
AV		 4593 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4594 * specifically only auto mask tx and rx interrupts */
4595 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4596 }
9a799d71 4597
a34bcfff
AD		 4598 /* XXX: to interrupt immediately for EICS writes, enable this */
4599 /* gpie |= IXGBE_GPIE_EIMEN; */
4600
4601 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4602 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4603
4604 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4605 case IXGBE_82599_VMDQ_8Q_MASK:
4606 gpie |= IXGBE_GPIE_VTMODE_16;
4607 break;
4608 case IXGBE_82599_VMDQ_4Q_MASK:
4609 gpie |= IXGBE_GPIE_VTMODE_32;
4610 break;
4611 default:
4612 gpie |= IXGBE_GPIE_VTMODE_64;
4613 break;
4614 }
119fc60a
MC		 4615 }
4616
5fdd31f9 4617 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4618 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4619 switch (adapter->hw.mac.type) {
4620 case ixgbe_mac_82599EB:
4621 gpie |= IXGBE_SDP0_GPIEN;
4622 break;
4623 case ixgbe_mac_X540:
4624 gpie |= IXGBE_EIMS_TS;
4625 break;
4626 default:
4627 break;
4628 }
4629 }
5fdd31f9 4630
a34bcfff
AD		 4631 /* Enable fan failure interrupt */
4632 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4633 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4634
2698b208 4635 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4636 gpie |= IXGBE_SDP1_GPIEN;
4637 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4638 }
a34bcfff
AD		 4639
4640 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4641}
4642
c7ccde0f 4643static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4644{
4645 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4646 struct net_device *upper;
4647 struct list_head *iter;
a34bcfff 4648 int err;
a34bcfff
AD		 4649 u32 ctrl_ext;
4650
4651 ixgbe_get_hw_control(adapter);
4652 ixgbe_setup_gpie(adapter);
e8e26350 4653
9a799d71
AK		 4654 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4655 ixgbe_configure_msix(adapter);
4656 else
4657 ixgbe_configure_msi_and_legacy(adapter);
4658
ec74a471
ET		 4659 /* enable the optics for 82599 SFP+ fiber */
4660 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4661 hw->mac.ops.enable_tx_laser(hw);
4662
c3049c8f 4663 smp_mb__before_clear_bit();
9a799d71 4664 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4665 ixgbe_napi_enable_all(adapter);
4666
73c4b7cd
AD		 4667 if (ixgbe_is_sfp(hw)) {
4668 ixgbe_sfp_link_config(adapter);
4669 } else {
4670 err = ixgbe_non_sfp_link_config(hw);
4671 if (err)
4672 e_err(probe, "link_config FAILED %d\n", err);
4673 }
4674
021230d4
AV		 4675 /* clear any pending interrupts, may auto mask */
4676 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4677 ixgbe_irq_enable(adapter, true, true);
9a799d71 4678
bf069c97
DS		 4679 /*
4680 * If this adapter has a fan, check to see if we had a failure
4681 * before we enabled the interrupt.
4682 */
4683 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4684 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4685 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4686 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4687 }
4688
1da100bb 4689 /* enable transmits */
477de6ed 4690 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4691
2a47fa45
JF		 4692 /* enable any upper devices */
4693 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4694 if (netif_is_macvlan(upper)) {
4695 struct macvlan_dev *vlan = netdev_priv(upper);
4696
4697 if (vlan->fwd_priv)
4698 netif_tx_start_all_queues(upper);
4699 }
4700 }
4701
9a799d71
AK		 4702 /* bring the link up in the watchdog, this could race with our first
4703 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4704 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4705 adapter->link_check_timeout = jiffies;
7086400d 4706 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4707
4708 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4709 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4710 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4711 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4712}
4713
d4f80882
AV		 4714void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4715{
4716 WARN_ON(in_interrupt());
7086400d
AD		 4717 /* put off any impending NetWatchDogTimeout */
4718 adapter->netdev->trans_start = jiffies;
4719
d4f80882 4720 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4721 usleep_range(1000, 2000);
d4f80882 4722 ixgbe_down(adapter);
5809a1ae
GR		 4723 /*
4724 * If SR-IOV enabled then wait a bit before bringing the adapter
4725 * back up to give the VFs time to respond to the reset. The
4726 * two second wait is based upon the watchdog timer cycle in
4727 * the VF driver.
4728 */
4729 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4730 msleep(2000);
d4f80882
AV		 4731 ixgbe_up(adapter);
4732 clear_bit(__IXGBE_RESETTING, &adapter->state);
4733}
4734
c7ccde0f 4735void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4736{
4737 /* hardware has been reset, we need to reload some things */
4738 ixgbe_configure(adapter);
4739
c7ccde0f 4740 ixgbe_up_complete(adapter);
9a799d71
AK		 4741}
4742
4743void ixgbe_reset(struct ixgbe_adapter *adapter)
4744{
c44ade9e 4745 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4746 int err;
4747
b0483c8f
MR		 4748 if (ixgbe_removed(hw->hw_addr))
4749 return;
7086400d
AD		 4750 /* lock SFP init bit to prevent race conditions with the watchdog */
4751 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4752 usleep_range(1000, 2000);
4753
4754 /* clear all SFP and link config related flags while holding SFP_INIT */
4755 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4756 IXGBE_FLAG2_SFP_NEEDS_RESET);
4757 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4758
8ca783ab 4759 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4760 switch (err) {
4761 case 0:
4762 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4763 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4764 break;
4765 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4766 e_dev_err("master disable timed out\n");
da4dd0f7 4767 break;
794caeb2
PWJ		 4768 case IXGBE_ERR_EEPROM_VERSION:
4769 /* We are running on a pre-production device, log a warning */
849c4542 4770 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4771 "Please be aware there may be issues associated with "
849c4542
ET		 4772 "your hardware. If you are experiencing problems "
4773 "please contact your Intel or hardware "
4774 "representative who provided you with this "
4775 "hardware.\n");
794caeb2 4776 break;
da4dd0f7 4777 default:
849c4542 4778 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4779 }
9a799d71 4780
7086400d
AD		 4781 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4782
9a799d71 4783 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4784 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4785
4786 /* update SAN MAC vmdq pool selection */
4787 if (hw->mac.san_mac_rar_index)
4788 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4789
8fecf67c 4790 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4791 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4792}
4793
9a799d71
AK		 4794/**
4795 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4796 * @tx_ring: ring to be cleaned
4797 **/
b6ec895e 4798static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4799{
4800 struct ixgbe_tx_buffer *tx_buffer_info;
4801 unsigned long size;
b6ec895e 4802 u16 i;
9a799d71 4803
84418e3b
AD		 4804 /* ring already cleared, nothing to do */
4805 if (!tx_ring->tx_buffer_info)
4806 return;
9a799d71 4807
84418e3b 4808 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4809 for (i = 0; i < tx_ring->count; i++) {
4810 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4811 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4812 }
4813
dad8a3b3
JF		 4814 netdev_tx_reset_queue(txring_txq(tx_ring));
4815
9a799d71
AK		 4816 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4817 memset(tx_ring->tx_buffer_info, 0, size);
4818
4819 /* Zero out the descriptor ring */
4820 memset(tx_ring->desc, 0, tx_ring->size);
4821
4822 tx_ring->next_to_use = 0;
4823 tx_ring->next_to_clean = 0;
9a799d71
AK		 4824}
4825
4826/**
021230d4 4827 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4828 * @adapter: board private structure
4829 **/
021230d4 4830static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4831{
4832 int i;
4833
021230d4 4834 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4835 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4836}
4837
4838/**
021230d4 4839 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4840 * @adapter: board private structure
4841 **/
021230d4 4842static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4843{
4844 int i;
4845
021230d4 4846 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4847 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4848}
4849
e4911d57
AD		 4850static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4851{
b67bfe0d 4852 struct hlist_node *node2;
e4911d57
AD		 4853 struct ixgbe_fdir_filter *filter;
4854
4855 spin_lock(&adapter->fdir_perfect_lock);
4856
b67bfe0d 4857 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4858 &adapter->fdir_filter_list, fdir_node) {
4859 hlist_del(&filter->fdir_node);
4860 kfree(filter);
4861 }
4862 adapter->fdir_filter_count = 0;
4863
4864 spin_unlock(&adapter->fdir_perfect_lock);
4865}
4866
9a799d71
AK		 4867void ixgbe_down(struct ixgbe_adapter *adapter)
4868{
4869 struct net_device *netdev = adapter->netdev;
7f821875 4870 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4871 struct net_device *upper;
4872 struct list_head *iter;
9a799d71 4873 u32 rxctrl;
bf29ee6c 4874 int i;
9a799d71
AK		 4875
4876 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4877 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4878 return; /* do nothing if already down */
9a799d71
AK		 4879
4880 /* disable receives */
7f821875
JB		 4881 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4882 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4883
2d39d576
YZ		 4884 /* disable all enabled rx queues */
4885 for (i = 0; i < adapter->num_rx_queues; i++)
4886 /* this call also flushes the previous write */
4887 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4888
032b4325 4889 usleep_range(10000, 20000);
9a799d71 4890
7f821875
JB		 4891 netif_tx_stop_all_queues(netdev);
4892
7086400d 4893 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4894 netif_carrier_off(netdev);
4895 netif_tx_disable(netdev);
4896
2a47fa45
JF		 4897 /* disable any upper devices */
4898 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4899 if (netif_is_macvlan(upper)) {
4900 struct macvlan_dev *vlan = netdev_priv(upper);
4901
4902 if (vlan->fwd_priv) {
4903 netif_tx_stop_all_queues(upper);
4904 netif_carrier_off(upper);
4905 netif_tx_disable(upper);
4906 }
4907 }
4908 }
4909
c0dfb90e
JF		 4910 ixgbe_irq_disable(adapter);
4911
4912 ixgbe_napi_disable_all(adapter);
4913
d034acf1
AD		 4914 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4915 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4916 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4917
4918 del_timer_sync(&adapter->service_timer);
4919
34cecbbf 4920 if (adapter->num_vfs) {
8e34d1aa
AD		 4921 /* Clear EITR Select mapping */
4922 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4923
4924 /* Mark all the VFs as inactive */
4925 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4926 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4927
34cecbbf
AD		 4928 /* ping all the active vfs to let them know we are going down */
4929 ixgbe_ping_all_vfs(adapter);
4930
4931 /* Disable all VFTE/VFRE TX/RX */
4932 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4933 }
4934
7f821875
JB		 4935 /* disable transmits in the hardware now that interrupts are off */
4936 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4937 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4938 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4939 }
34cecbbf
AD		 4940
4941 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4942 switch (hw->mac.type) {
4943 case ixgbe_mac_82599EB:
b93a2226 4944 case ixgbe_mac_X540:
88512539 4945 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4946 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4947 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4948 break;
4949 default:
4950 break;
4951 }
7f821875 4952
6f4a0e45
PL		 4953 if (!pci_channel_offline(adapter->pdev))
4954 ixgbe_reset(adapter);
c6ecf39a 4955
ec74a471
ET		 4956 /* power down the optics for 82599 SFP+ fiber */
4957 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4958 hw->mac.ops.disable_tx_laser(hw);
4959
9a799d71
AK		 4960 ixgbe_clean_all_tx_rings(adapter);
4961 ixgbe_clean_all_rx_rings(adapter);
4962
5dd2d332 4963#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4964 /* since we reset the hardware DCA settings were cleared */
e35ec126 4965 ixgbe_setup_dca(adapter);
96b0e0f6 4966#endif
9a799d71
AK		 4967}
4968
9a799d71
AK		 4969/**
4970 * ixgbe_tx_timeout - Respond to a Tx Hang
4971 * @netdev: network interface device structure
4972 **/
4973static void ixgbe_tx_timeout(struct net_device *netdev)
4974{
4975 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4976
4977 /* Do the reset outside of interrupt context */
c83c6cbd 4978 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4979}
4980
9a799d71
AK		 4981/**
4982 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4983 * @adapter: board private structure to initialize
4984 *
4985 * ixgbe_sw_init initializes the Adapter private data structure.
4986 * Fields are initialized based on PCI device information and
4987 * OS network device settings (MTU size).
4988 **/
9f9a12f8 4989static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4990{
4991 struct ixgbe_hw *hw = &adapter->hw;
4992 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4993 unsigned int rss, fdir;
cb6d0f5e 4994 u32 fwsm;
7a6b6f51 4995#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4996 int j;
4997 struct tc_configuration *tc;
4998#endif
021230d4 4999
c44ade9e
JB		 5000 /* PCI config space info */
5001
5002 hw->vendor_id = pdev->vendor;
5003 hw->device_id = pdev->device;
5004 hw->revision_id = pdev->revision;
5005 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5006 hw->subsystem_device_id = pdev->subsystem_device;
5007
8fc3bb6d 5008 /* Set common capability flags and settings */
3ed69d7e 5009 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5010 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5011 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5012 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5013 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5014 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5015 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5016 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5017 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5018#ifdef CONFIG_IXGBE_DCA
5019 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5020#endif
5021#ifdef IXGBE_FCOE
5022 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5023 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5024#ifdef CONFIG_IXGBE_DCB
5025 /* Default traffic class to use for FCoE */
5026 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5027#endif /* CONFIG_IXGBE_DCB */
5028#endif /* IXGBE_FCOE */
5029
5030 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5031 switch (hw->mac.type) {
5032 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5033 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5034 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5035
bf069c97
DS		 5036 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5037 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5038
49c7ffbe 5039 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5040 adapter->ring_feature[RING_F_FDIR].limit = 0;
5041 adapter->atr_sample_rate = 0;
5042 adapter->fdir_pballoc = 0;
5043#ifdef IXGBE_FCOE
5044 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5045 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5046#ifdef CONFIG_IXGBE_DCB
5047 adapter->fcoe.up = 0;
5048#endif /* IXGBE_DCB */
5049#endif /* IXGBE_FCOE */
5050 break;
5051 case ixgbe_mac_82599EB:
5052 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5053 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5054 break;
b93a2226 5055 case ixgbe_mac_X540:
cb6d0f5e
JK		 5056 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5057 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5058 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5059 break;
5060 default:
5061 break;
f8212f97 5062 }
2f90b865 5063
7c8ae65a
AD		 5064#ifdef IXGBE_FCOE
5065 /* FCoE support exists, always init the FCoE lock */
5066 spin_lock_init(&adapter->fcoe.lock);
5067
5068#endif
1fc5f038
AD		 5069 /* n-tuple support exists, always init our spinlock */
5070 spin_lock_init(&adapter->fdir_perfect_lock);
5071
7a6b6f51 5072#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5073 switch (hw->mac.type) {
5074 case ixgbe_mac_X540:
5075 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5076 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5077 break;
5078 default:
5079 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5080 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5081 break;
5082 }
5083
2f90b865
AD		 5084 /* Configure DCB traffic classes */
5085 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5086 tc = &adapter->dcb_cfg.tc_config[j];
5087 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5088 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5089 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5090 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5091 tc->dcb_pfc = pfc_disabled;
5092 }
4de2a022
JF		 5093
5094 /* Initialize default user to priority mapping, UPx->TC0 */
5095 tc = &adapter->dcb_cfg.tc_config[0];
5096 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5097 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5098
2f90b865
AD		 5099 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5100 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5101 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5102 adapter->dcb_set_bitmap = 0x00;
3032309b 5103 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5104 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5105 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5106
5107#endif
9a799d71
AK		 5108
5109 /* default flow control settings */
cd7664f6 5110 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5111 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5112 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5113 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5114 hw->fc.send_xon = true;
73d80953 5115 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5116
99d74487 5117#ifdef CONFIG_PCI_IOV
170e8543
JK		 5118 if (max_vfs > 0)
5119 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5120
99d74487 5121 /* assign number of SR-IOV VFs */
170e8543 5122 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5123 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5124 adapter->num_vfs = 0;
5125 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5126 } else {
5127 adapter->num_vfs = max_vfs;
5128 }
5129 }
5130#endif /* CONFIG_PCI_IOV */
99d74487 5131
30efa5a3 5132 /* enable itr by default in dynamic mode */
f7554a2b 5133 adapter->rx_itr_setting = 1;
f7554a2b 5134 adapter->tx_itr_setting = 1;
30efa5a3 5135
30efa5a3
JB		 5136 /* set default ring sizes */
5137 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5138 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5139
bd198058 5140 /* set default work limits */
59224555 5141 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5142
9a799d71 5143 /* initialize eeprom parameters */
c44ade9e 5144 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5145 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5146 return -EIO;
5147 }
5148
2a47fa45
JF		 5149 /* PF holds first pool slot */
5150 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5151 set_bit(__IXGBE_DOWN, &adapter->state);
5152
5153 return 0;
5154}
5155
5156/**
5157 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5158 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5159 *
5160 * Return 0 on success, negative on failure
5161 **/
b6ec895e 5162int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5163{
b6ec895e 5164 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5165 int orig_node = dev_to_node(dev);
5166 int numa_node = -1;
9a799d71
AK		 5167 int size;
5168
3a581073 5169 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5170
5171 if (tx_ring->q_vector)
5172 numa_node = tx_ring->q_vector->numa_node;
5173
5174 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5175 if (!tx_ring->tx_buffer_info)
89bf67f1 5176 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5177 if (!tx_ring->tx_buffer_info)
5178 goto err;
9a799d71 5179
827da44c
JS		 5180 u64_stats_init(&tx_ring->syncp);
5181
9a799d71 5182 /* round up to nearest 4K */
12207e49 5183 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5184 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5185
de88eeeb
AD		 5186 set_dev_node(dev, numa_node);
5187 tx_ring->desc = dma_alloc_coherent(dev,
5188 tx_ring->size,
5189 &tx_ring->dma,
5190 GFP_KERNEL);
5191 set_dev_node(dev, orig_node);
5192 if (!tx_ring->desc)
5193 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5194 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5195 if (!tx_ring->desc)
5196 goto err;
9a799d71 5197
3a581073
JB		 5198 tx_ring->next_to_use = 0;
5199 tx_ring->next_to_clean = 0;
9a799d71 5200 return 0;
e01c31a5
JB		 5201
5202err:
5203 vfree(tx_ring->tx_buffer_info);
5204 tx_ring->tx_buffer_info = NULL;
b6ec895e 5205 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5206 return -ENOMEM;
9a799d71
AK		 5207}
5208
69888674
AD		 5209/**
5210 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5211 * @adapter: board private structure
5212 *
5213 * If this function returns with an error, then it's possible one or
5214 * more of the rings is populated (while the rest are not). It is the
5215 * callers duty to clean those orphaned rings.
5216 *
5217 * Return 0 on success, negative on failure
5218 **/
5219static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5220{
5221 int i, err = 0;
5222
5223 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5224 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5225 if (!err)
5226 continue;
de3d5b94 5227
396e799c 5228 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5229 goto err_setup_tx;
69888674
AD		 5230 }
5231
de3d5b94
AD		 5232 return 0;
5233err_setup_tx:
5234 /* rewind the index freeing the rings as we go */
5235 while (i--)
5236 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5237 return err;
5238}
5239
9a799d71
AK		 5240/**
5241 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5242 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5243 *
5244 * Returns 0 on success, negative on failure
5245 **/
b6ec895e 5246int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5247{
b6ec895e 5248 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5249 int orig_node = dev_to_node(dev);
5250 int numa_node = -1;
021230d4 5251 int size;
9a799d71 5252
3a581073 5253 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5254
5255 if (rx_ring->q_vector)
5256 numa_node = rx_ring->q_vector->numa_node;
5257
5258 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5259 if (!rx_ring->rx_buffer_info)
89bf67f1 5260 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5261 if (!rx_ring->rx_buffer_info)
5262 goto err;
9a799d71 5263
827da44c
JS		 5264 u64_stats_init(&rx_ring->syncp);
5265
9a799d71 5266 /* Round up to nearest 4K */
3a581073
JB		 5267 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5268 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5269
de88eeeb
AD		 5270 set_dev_node(dev, numa_node);
5271 rx_ring->desc = dma_alloc_coherent(dev,
5272 rx_ring->size,
5273 &rx_ring->dma,
5274 GFP_KERNEL);
5275 set_dev_node(dev, orig_node);
5276 if (!rx_ring->desc)
5277 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5278 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5279 if (!rx_ring->desc)
5280 goto err;
9a799d71 5281
3a581073
JB		 5282 rx_ring->next_to_clean = 0;
5283 rx_ring->next_to_use = 0;
9a799d71
AK		 5284
5285 return 0;
b6ec895e
AD		 5286err:
5287 vfree(rx_ring->rx_buffer_info);
5288 rx_ring->rx_buffer_info = NULL;
5289 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5290 return -ENOMEM;
9a799d71
AK		 5291}
5292
69888674
AD		 5293/**
5294 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5295 * @adapter: board private structure
5296 *
5297 * If this function returns with an error, then it's possible one or
5298 * more of the rings is populated (while the rest are not). It is the
5299 * callers duty to clean those orphaned rings.
5300 *
5301 * Return 0 on success, negative on failure
5302 **/
69888674
AD		 5303static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5304{
5305 int i, err = 0;
5306
5307 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5308 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5309 if (!err)
5310 continue;
de3d5b94 5311
396e799c 5312 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5313 goto err_setup_rx;
69888674
AD		 5314 }
5315
7c8ae65a
AD		 5316#ifdef IXGBE_FCOE
5317 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5318 if (!err)
5319#endif
5320 return 0;
de3d5b94
AD		 5321err_setup_rx:
5322 /* rewind the index freeing the rings as we go */
5323 while (i--)
5324 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5325 return err;
5326}
5327
9a799d71
AK		 5328/**
5329 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5330 * @tx_ring: Tx descriptor ring for a specific queue
5331 *
5332 * Free all transmit software resources
5333 **/
b6ec895e 5334void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5335{
b6ec895e 5336 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5337
5338 vfree(tx_ring->tx_buffer_info);
5339 tx_ring->tx_buffer_info = NULL;
5340
b6ec895e
AD		 5341 /* if not set, then don't free */
5342 if (!tx_ring->desc)
5343 return;
5344
5345 dma_free_coherent(tx_ring->dev, tx_ring->size,
5346 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5347
5348 tx_ring->desc = NULL;
5349}
5350
5351/**
5352 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5353 * @adapter: board private structure
5354 *
5355 * Free all transmit software resources
5356 **/
5357static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5358{
5359 int i;
5360
5361 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5362 if (adapter->tx_ring[i]->desc)
b6ec895e 5363 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5364}
5365
5366/**
b4617240 5367 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5368 * @rx_ring: ring to clean the resources from
5369 *
5370 * Free all receive software resources
5371 **/
b6ec895e 5372void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5373{
b6ec895e 5374 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5375
5376 vfree(rx_ring->rx_buffer_info);
5377 rx_ring->rx_buffer_info = NULL;
5378
b6ec895e
AD		 5379 /* if not set, then don't free */
5380 if (!rx_ring->desc)
5381 return;
5382
5383 dma_free_coherent(rx_ring->dev, rx_ring->size,
5384 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5385
5386 rx_ring->desc = NULL;
5387}
5388
5389/**
5390 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5391 * @adapter: board private structure
5392 *
5393 * Free all receive software resources
5394 **/
5395static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5396{
5397 int i;
5398
7c8ae65a
AD		 5399#ifdef IXGBE_FCOE
5400 ixgbe_free_fcoe_ddp_resources(adapter);
5401
5402#endif
9a799d71 5403 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5404 if (adapter->rx_ring[i]->desc)
b6ec895e 5405 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5406}
5407
9a799d71
AK		 5408/**
5409 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5410 * @netdev: network interface device structure
5411 * @new_mtu: new value for maximum frame size
5412 *
5413 * Returns 0 on success, negative on failure
5414 **/
5415static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5416{
5417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5418 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5419
42c783c5 5420 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5421 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5422 return -EINVAL;
5423
5424 /*
872844dd
AD		 5425 * For 82599EB we cannot allow legacy VFs to enable their receive
5426 * paths when MTU greater than 1500 is configured. So display a
5427 * warning that legacy VFs will be disabled.
655309e9
AD		 5428 */
5429 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5430 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5431 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5432 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5433
396e799c 5434 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5435
021230d4 5436 /* must set new MTU before calling down or up */
9a799d71
AK		 5437 netdev->mtu = new_mtu;
5438
d4f80882
AV		 5439 if (netif_running(netdev))
5440 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5441
5442 return 0;
5443}
5444
5445/**
5446 * ixgbe_open - Called when a network interface is made active
5447 * @netdev: network interface device structure
5448 *
5449 * Returns 0 on success, negative value on failure
5450 *
5451 * The open entry point is called when a network interface is made
5452 * active by the system (IFF_UP). At this point all resources needed
5453 * for transmit and receive operations are allocated, the interrupt
5454 * handler is registered with the OS, the watchdog timer is started,
5455 * and the stack is notified that the interface is ready.
5456 **/
5457static int ixgbe_open(struct net_device *netdev)
5458{
5459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5460 int err, queues;
4bebfaa5
AK		 5461
5462 /* disallow open during test */
5463 if (test_bit(__IXGBE_TESTING, &adapter->state))
5464 return -EBUSY;
9a799d71 5465
54386467
JB		 5466 netif_carrier_off(netdev);
5467
9a799d71
AK		 5468 /* allocate transmit descriptors */
5469 err = ixgbe_setup_all_tx_resources(adapter);
5470 if (err)
5471 goto err_setup_tx;
5472
9a799d71
AK		 5473 /* allocate receive descriptors */
5474 err = ixgbe_setup_all_rx_resources(adapter);
5475 if (err)
5476 goto err_setup_rx;
5477
5478 ixgbe_configure(adapter);
5479
021230d4 5480 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5481 if (err)
5482 goto err_req_irq;
5483
ac802f5d 5484 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5485 if (adapter->num_rx_pools > 1)
5486 queues = adapter->num_rx_queues_per_pool;
5487 else
5488 queues = adapter->num_tx_queues;
5489
5490 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5491 if (err)
5492 goto err_set_queues;
5493
2a47fa45
JF		 5494 if (adapter->num_rx_pools > 1 &&
5495 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5496 queues = IXGBE_MAX_L2A_QUEUES;
5497 else
5498 queues = adapter->num_rx_queues;
5499 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5500 if (err)
5501 goto err_set_queues;
5502
1a71ab24 5503 ixgbe_ptp_init(adapter);
1a71ab24 5504
c7ccde0f 5505 ixgbe_up_complete(adapter);
9a799d71
AK		 5506
5507 return 0;
5508
ac802f5d
AD		 5509err_set_queues:
5510 ixgbe_free_irq(adapter);
9a799d71 5511err_req_irq:
a20a1199 5512 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5513err_setup_rx:
a20a1199 5514 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5515err_setup_tx:
9a799d71
AK		 5516 ixgbe_reset(adapter);
5517
5518 return err;
5519}
5520
5521/**
5522 * ixgbe_close - Disables a network interface
5523 * @netdev: network interface device structure
5524 *
5525 * Returns 0, this is not allowed to fail
5526 *
5527 * The close entry point is called when an interface is de-activated
5528 * by the OS. The hardware is still under the drivers control, but
5529 * needs to be disabled. A global MAC reset is issued to stop the
5530 * hardware, and all transmit and receive resources are freed.
5531 **/
5532static int ixgbe_close(struct net_device *netdev)
5533{
5534 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5535
1a71ab24 5536 ixgbe_ptp_stop(adapter);
1a71ab24 5537
9a799d71
AK		 5538 ixgbe_down(adapter);
5539 ixgbe_free_irq(adapter);
5540
e4911d57
AD		 5541 ixgbe_fdir_filter_exit(adapter);
5542
9a799d71
AK		 5543 ixgbe_free_all_tx_resources(adapter);
5544 ixgbe_free_all_rx_resources(adapter);
5545
5eba3699 5546 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5547
5548 return 0;
5549}
5550
b3c8b4ba
AD		 5551#ifdef CONFIG_PM
5552static int ixgbe_resume(struct pci_dev *pdev)
5553{
c60fbb00
AD		 5554 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5555 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5556 u32 err;
5557
0391bbe3 5558 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5559 pci_set_power_state(pdev, PCI_D0);
5560 pci_restore_state(pdev);
656ab817
DS		 5561 /*
5562 * pci_restore_state clears dev->state_saved so call
5563 * pci_save_state to restore it.
5564 */
5565 pci_save_state(pdev);
9ce77666 5566
5567 err = pci_enable_device_mem(pdev);
b3c8b4ba 5568 if (err) {
849c4542 5569 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5570 return err;
5571 }
5572 pci_set_master(pdev);
5573
dd4d8ca6 5574 pci_wake_from_d3(pdev, false);
b3c8b4ba 5575
b3c8b4ba
AD		 5576 ixgbe_reset(adapter);
5577
495dce12
WJP		 5578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5579
ac802f5d
AD		 5580 rtnl_lock();
5581 err = ixgbe_init_interrupt_scheme(adapter);
5582 if (!err && netif_running(netdev))
c60fbb00 5583 err = ixgbe_open(netdev);
ac802f5d
AD		 5584
5585 rtnl_unlock();
5586
5587 if (err)
5588 return err;
b3c8b4ba
AD		 5589
5590 netif_device_attach(netdev);
5591
5592 return 0;
5593}
b3c8b4ba 5594#endif /* CONFIG_PM */
9d8d05ae
RW		 5595
5596static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5597{
c60fbb00
AD		 5598 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5599 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5600 struct ixgbe_hw *hw = &adapter->hw;
5601 u32 ctrl, fctrl;
5602 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5603#ifdef CONFIG_PM
5604 int retval = 0;
5605#endif
5606
5607 netif_device_detach(netdev);
5608
499ab5cc 5609 rtnl_lock();
b3c8b4ba
AD		 5610 if (netif_running(netdev)) {
5611 ixgbe_down(adapter);
5612 ixgbe_free_irq(adapter);
5613 ixgbe_free_all_tx_resources(adapter);
5614 ixgbe_free_all_rx_resources(adapter);
5615 }
499ab5cc 5616 rtnl_unlock();
b3c8b4ba 5617
5f5ae6fc
AD		 5618 ixgbe_clear_interrupt_scheme(adapter);
5619
b3c8b4ba
AD		 5620#ifdef CONFIG_PM
5621 retval = pci_save_state(pdev);
5622 if (retval)
5623 return retval;
4df10466 5624
b3c8b4ba 5625#endif
f4f1040a
JK		 5626 if (hw->mac.ops.stop_link_on_d3)
5627 hw->mac.ops.stop_link_on_d3(hw);
5628
e8e26350
PW		 5629 if (wufc) {
5630 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5631
ec74a471
ET		 5632 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5633 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5634 hw->mac.ops.enable_tx_laser(hw);
5635
e8e26350
PW		 5636 /* turn on all-multi mode if wake on multicast is enabled */
5637 if (wufc & IXGBE_WUFC_MC) {
5638 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5639 fctrl |= IXGBE_FCTRL_MPE;
5640 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5641 }
5642
5643 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5644 ctrl |= IXGBE_CTRL_GIO_DIS;
5645 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5646
5647 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5648 } else {
5649 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5650 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5651 }
5652
bd508178
AD		 5653 switch (hw->mac.type) {
5654 case ixgbe_mac_82598EB:
dd4d8ca6 5655 pci_wake_from_d3(pdev, false);
bd508178
AD		 5656 break;
5657 case ixgbe_mac_82599EB:
b93a2226 5658 case ixgbe_mac_X540:
bd508178
AD		 5659 pci_wake_from_d3(pdev, !!wufc);
5660 break;
5661 default:
5662 break;
5663 }
b3c8b4ba 5664
9d8d05ae
RW		 5665 *enable_wake = !!wufc;
5666
b3c8b4ba
AD		 5667 ixgbe_release_hw_control(adapter);
5668
5669 pci_disable_device(pdev);
5670
9d8d05ae
RW		 5671 return 0;
5672}
5673
5674#ifdef CONFIG_PM
5675static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5676{
5677 int retval;
5678 bool wake;
5679
5680 retval = __ixgbe_shutdown(pdev, &wake);
5681 if (retval)
5682 return retval;
5683
5684 if (wake) {
5685 pci_prepare_to_sleep(pdev);
5686 } else {
5687 pci_wake_from_d3(pdev, false);
5688 pci_set_power_state(pdev, PCI_D3hot);
5689 }
b3c8b4ba
AD		 5690
5691 return 0;
5692}
9d8d05ae 5693#endif /* CONFIG_PM */
b3c8b4ba
AD		 5694
5695static void ixgbe_shutdown(struct pci_dev *pdev)
5696{
9d8d05ae
RW		 5697 bool wake;
5698
5699 __ixgbe_shutdown(pdev, &wake);
5700
5701 if (system_state == SYSTEM_POWER_OFF) {
5702 pci_wake_from_d3(pdev, wake);
5703 pci_set_power_state(pdev, PCI_D3hot);
5704 }
b3c8b4ba
AD		 5705}
5706
9a799d71
AK		 5707/**
5708 * ixgbe_update_stats - Update the board statistics counters.
5709 * @adapter: board private structure
5710 **/
5711void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5712{
2d86f139 5713 struct net_device *netdev = adapter->netdev;
9a799d71 5714 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5715 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5716 u64 total_mpc = 0;
5717 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5718 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5719 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5720 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5721
d08935c2
DS		 5722 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5723 test_bit(__IXGBE_RESETTING, &adapter->state))
5724 return;
5725
94b982b2 5726 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5727 u64 rsc_count = 0;
94b982b2 5728 u64 rsc_flush = 0;
94b982b2 5729 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5730 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5731 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5732 }
5733 adapter->rsc_total_count = rsc_count;
5734 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5735 }
5736
5b7da515
AD		 5737 for (i = 0; i < adapter->num_rx_queues; i++) {
5738 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5739 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5740 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5741 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5742 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5743 bytes += rx_ring->stats.bytes;
5744 packets += rx_ring->stats.packets;
5745 }
5746 adapter->non_eop_descs = non_eop_descs;
5747 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5748 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5749 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5750 netdev->stats.rx_bytes = bytes;
5751 netdev->stats.rx_packets = packets;
5752
5753 bytes = 0;
5754 packets = 0;
7ca3bc58 5755 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5756 for (i = 0; i < adapter->num_tx_queues; i++) {
5757 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5758 restart_queue += tx_ring->tx_stats.restart_queue;
5759 tx_busy += tx_ring->tx_stats.tx_busy;
5760 bytes += tx_ring->stats.bytes;
5761 packets += tx_ring->stats.packets;
5762 }
eb985f09 5763 adapter->restart_queue = restart_queue;
5b7da515
AD		 5764 adapter->tx_busy = tx_busy;
5765 netdev->stats.tx_bytes = bytes;
5766 netdev->stats.tx_packets = packets;
7ca3bc58 5767
7ca647bd 5768 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5769
5770 /* 8 register reads */
6f11eef7
AV		 5771 for (i = 0; i < 8; i++) {
5772 /* for packet buffers not used, the register should read 0 */
5773 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5774 missed_rx += mpc;
7ca647bd
JP		 5775 hwstats->mpc[i] += mpc;
5776 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5777 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5778 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5779 switch (hw->mac.type) {
5780 case ixgbe_mac_82598EB:
1a70db4b
ET		 5781 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5782 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5783 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5784 hwstats->pxonrxc[i] +=
5785 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5786 break;
5787 case ixgbe_mac_82599EB:
b93a2226 5788 case ixgbe_mac_X540:
bd508178
AD		 5789 hwstats->pxonrxc[i] +=
5790 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5791 break;
5792 default:
5793 break;
e8e26350 5794 }
6f11eef7 5795 }
1a70db4b
ET		 5796
5797 /*16 register reads */
5798 for (i = 0; i < 16; i++) {
5799 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5800 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5801 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5802 (hw->mac.type == ixgbe_mac_X540)) {
5803 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5804 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5805 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5806 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5807 }
5808 }
5809
7ca647bd 5810 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5811 /* work around hardware counting issue */
7ca647bd 5812 hwstats->gprc -= missed_rx;
6f11eef7 5813
c84d324c
JF		 5814 ixgbe_update_xoff_received(adapter);
5815
6f11eef7 5816 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5817 switch (hw->mac.type) {
5818 case ixgbe_mac_82598EB:
5819 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5820 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5821 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5822 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5823 break;
b93a2226 5824 case ixgbe_mac_X540:
58f6bcf9
ET		 5825 /* OS2BMC stats are X540 only*/
5826 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5827 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5828 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5829 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5830 case ixgbe_mac_82599EB:
a4d4f629
AD		 5831 for (i = 0; i < 16; i++)
5832 adapter->hw_rx_no_dma_resources +=
5833 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5834 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5835 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5836 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5837 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5838 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5839 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5840 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5841 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5842 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5843#ifdef IXGBE_FCOE
7ca647bd
JP		 5844 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5845 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5846 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5847 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5848 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5849 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5850 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5851 if (adapter->fcoe.ddp_pool) {
5852 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5853 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5854 unsigned int cpu;
5855 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5856 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5857 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5858 noddp += ddp_pool->noddp;
5859 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5860 }
5a1ee270
AD		 5861 hwstats->fcoe_noddp = noddp;
5862 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5863 }
6d45522c 5864#endif /* IXGBE_FCOE */
bd508178
AD		 5865 break;
5866 default:
5867 break;
e8e26350 5868 }
9a799d71 5869 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5870 hwstats->bprc += bprc;
5871 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5872 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5873 hwstats->mprc -= bprc;
5874 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5875 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5876 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5877 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5878 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5879 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5880 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5881 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5882 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5883 hwstats->lxontxc += lxon;
6f11eef7 5884 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5885 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5886 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5887 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5888 /*
5889 * 82598 errata - tx of flow control packets is included in tx counters
5890 */
5891 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5892 hwstats->gptc -= xon_off_tot;
5893 hwstats->mptc -= xon_off_tot;
5894 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5895 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5896 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5897 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5898 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5899 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5900 hwstats->ptc64 -= xon_off_tot;
5901 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5902 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5903 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5904 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5905 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5906 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5907
5908 /* Fill out the OS statistics structure */
7ca647bd 5909 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5910
5911 /* Rx Errors */
7ca647bd 5912 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5913 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5914 netdev->stats.rx_length_errors = hwstats->rlec;
5915 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5916 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5917}
5918
5919/**
d034acf1 5920 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5921 * @adapter: pointer to the device adapter structure
9a799d71 5922 **/
d034acf1 5923static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5924{
cf8280ee 5925 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5926 int i;
cf8280ee 5927
d034acf1
AD		 5928 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5929 return;
5930
5931 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5932
d034acf1 5933 /* if interface is down do nothing */
fe49f04a 5934 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5935 return;
5936
5937 /* do nothing if we are not using signature filters */
5938 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5939 return;
5940
5941 adapter->fdir_overflow++;
5942
93c52dd0
AD		 5943 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5944 for (i = 0; i < adapter->num_tx_queues; i++)
5945 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5946 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5947 /* re-enable flow director interrupts */
5948 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5949 } else {
5950 e_err(probe, "failed to finish FDIR re-initialization, "
5951 "ignored adding FDIR ATR filters\n");
5952 }
93c52dd0
AD		 5953}
5954
5955/**
5956 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5957 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5958 *
5959 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5960 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5961 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5962 * determine if a hang has occurred.
93c52dd0
AD		 5963 */
5964static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5965{
cf8280ee 5966 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5967 u64 eics = 0;
5968 int i;
cf8280ee 5969
09f40aed 5970 /* If we're down, removing or resetting, just bail */
93c52dd0 5971 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 5972 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 5973 test_bit(__IXGBE_RESETTING, &adapter->state))
5974 return;
22d5a71b 5975
93c52dd0
AD		 5976 /* Force detection of hung controller */
5977 if (netif_carrier_ok(adapter->netdev)) {
5978 for (i = 0; i < adapter->num_tx_queues; i++)
5979 set_check_for_tx_hang(adapter->tx_ring[i]);
5980 }
22d5a71b 5981
fe49f04a
AD		 5982 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5983 /*
5984 * for legacy and MSI interrupts don't set any bits
5985 * that are enabled for EIAM, because this operation
5986 * would set *both* EIMS and EICS for any bit in EIAM
5987 */
5988 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5989 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5990 } else {
5991 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5992 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5993 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5994 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5995 eics |= ((u64)1 << i);
5996 }
cf8280ee 5997 }
9a799d71 5998
93c52dd0 5999 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6000 ixgbe_irq_rearm_queues(adapter, eics);
6001
cf8280ee
JB		 6002}
6003
e8e26350 6004/**
93c52dd0 6005 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6006 * @adapter: pointer to the device adapter structure
6007 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6008 **/
93c52dd0 6009static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6010{
e8e26350 6011 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6012 u32 link_speed = adapter->link_speed;
6013 bool link_up = adapter->link_up;
041441d0 6014 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6015
93c52dd0
AD		 6016 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6017 return;
6018
6019 if (hw->mac.ops.check_link) {
6020 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6021 } else {
93c52dd0
AD		 6022 /* always assume link is up, if no check link function */
6023 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6024 link_up = true;
c4cf55e5 6025 }
041441d0
AD		 6026
6027 if (adapter->ixgbe_ieee_pfc)
6028 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6029
3ebe8fde 6030 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6031 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6032 ixgbe_set_rx_drop_en(adapter);
6033 }
93c52dd0
AD		 6034
6035 if (link_up ||
6036 time_after(jiffies, (adapter->link_check_timeout +
6037 IXGBE_TRY_LINK_TIMEOUT))) {
6038 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6039 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6040 IXGBE_WRITE_FLUSH(hw);
6041 }
6042
6043 adapter->link_up = link_up;
6044 adapter->link_speed = link_speed;
e8e26350
PW		 6045}
6046
107d3018
AD		 6047static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6048{
6049#ifdef CONFIG_IXGBE_DCB
6050 struct net_device *netdev = adapter->netdev;
6051 struct dcb_app app = {
6052 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6053 .protocol = 0,
6054 };
6055 u8 up = 0;
6056
6057 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6058 up = dcb_ieee_getapp_mask(netdev, &app);
6059
6060 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6061#endif
6062}
6063
e8e26350 6064/**
93c52dd0
AD		 6065 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6066 * print link up message
49ce9c2c 6067 * @adapter: pointer to the device adapter structure
e8e26350 6068 **/
93c52dd0 6069static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6070{
93c52dd0 6071 struct net_device *netdev = adapter->netdev;
e8e26350 6072 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6073 u32 link_speed = adapter->link_speed;
6074 bool flow_rx, flow_tx;
e8e26350 6075
93c52dd0
AD		 6076 /* only continue if link was previously down */
6077 if (netif_carrier_ok(netdev))
a985b6c3 6078 return;
63d6e1d8 6079
93c52dd0 6080 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6081
93c52dd0
AD		 6082 switch (hw->mac.type) {
6083 case ixgbe_mac_82598EB: {
6084 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6085 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6086 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6087 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6088 }
6089 break;
6090 case ixgbe_mac_X540:
6091 case ixgbe_mac_82599EB: {
6092 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6093 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6094 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6095 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6096 }
6097 break;
6098 default:
6099 flow_tx = false;
6100 flow_rx = false;
6101 break;
e8e26350 6102 }
3a6a4eda 6103
6cb562d6
JK		 6104 adapter->last_rx_ptp_check = jiffies;
6105
8fecf67c 6106 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6107 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6108
93c52dd0
AD		 6109 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6110 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6111 "10 Gbps" :
6112 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6113 "1 Gbps" :
6114 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6115 "100 Mbps" :
6116 "unknown speed"))),
6117 ((flow_rx && flow_tx) ? "RX/TX" :
6118 (flow_rx ? "RX" :
6119 (flow_tx ? "TX" : "None"))));
e8e26350 6120
93c52dd0 6121 netif_carrier_on(netdev);
93c52dd0 6122 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6123
107d3018
AD		 6124 /* update the default user priority for VFs */
6125 ixgbe_update_default_up(adapter);
6126
befa2af7
AD		 6127 /* ping all the active vfs to let them know link has changed */
6128 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6129}
6130
c4cf55e5 6131/**
93c52dd0
AD		 6132 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6133 * print link down message
49ce9c2c 6134 * @adapter: pointer to the adapter structure
c4cf55e5 6135 **/
581330ba 6136static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6137{
cf8280ee 6138 struct net_device *netdev = adapter->netdev;
c4cf55e5 6139 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6140
93c52dd0
AD		 6141 adapter->link_up = false;
6142 adapter->link_speed = 0;
cf8280ee 6143
93c52dd0
AD		 6144 /* only continue if link was up previously */
6145 if (!netif_carrier_ok(netdev))
6146 return;
264857b8 6147
93c52dd0
AD		 6148 /* poll for SFP+ cable when link is down */
6149 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6150 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6151
8fecf67c 6152 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6153 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6154
93c52dd0
AD		 6155 e_info(drv, "NIC Link is Down\n");
6156 netif_carrier_off(netdev);
befa2af7
AD		 6157
6158 /* ping all the active vfs to let them know link has changed */
6159 ixgbe_ping_all_vfs(adapter);
93c52dd0 6160}
e8e26350 6161
93c52dd0
AD		 6162/**
6163 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6164 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6165 **/
6166static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6167{
c4cf55e5 6168 int i;
93c52dd0 6169 int some_tx_pending = 0;
c4cf55e5 6170
93c52dd0 6171 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6172 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6173 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6174 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6175 some_tx_pending = 1;
6176 break;
6177 }
6178 }
6179
6180 if (some_tx_pending) {
6181 /* We've lost link, so the controller stops DMA,
6182 * but we've got queued Tx work that's never going
6183 * to get done, so reset controller to flush Tx.
6184 * (Do the reset outside of interrupt context).
6185 */
12ff3f3b 6186 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6187 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6188 }
c4cf55e5 6189 }
c4cf55e5
PWJ		 6190}
6191
a985b6c3
GR		 6192static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6193{
6194 u32 ssvpc;
6195
0584d999
GR		 6196 /* Do not perform spoof check for 82598 or if not in IOV mode */
6197 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6198 adapter->num_vfs == 0)
a985b6c3
GR		 6199 return;
6200
6201 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6202
6203 /*
6204 * ssvpc register is cleared on read, if zero then no
6205 * spoofed packets in the last interval.
6206 */
6207 if (!ssvpc)
6208 return;
6209
d6ea0754 6210 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6211}
6212
93c52dd0
AD		 6213/**
6214 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6215 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6216 **/
6217static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6218{
09f40aed 6219 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6220 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6221 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6222 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6223 return;
6224
6225 ixgbe_watchdog_update_link(adapter);
6226
6227 if (adapter->link_up)
6228 ixgbe_watchdog_link_is_up(adapter);
6229 else
6230 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6231
a985b6c3 6232 ixgbe_spoof_check(adapter);
9a799d71 6233 ixgbe_update_stats(adapter);
93c52dd0
AD		 6234
6235 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6236}
10eec955 6237
cf8280ee 6238/**
7086400d 6239 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6240 * @adapter: the ixgbe adapter structure
cf8280ee 6241 **/
7086400d 6242static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6243{
cf8280ee 6244 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6245 s32 err;
cf8280ee 6246
7086400d
AD		 6247 /* not searching for SFP so there is nothing to do here */
6248 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6249 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6250 return;
10eec955 6251
7086400d
AD		 6252 /* someone else is in init, wait until next service event */
6253 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6254 return;
cf8280ee 6255
7086400d
AD		 6256 err = hw->phy.ops.identify_sfp(hw);
6257 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6258 goto sfp_out;
264857b8 6259
7086400d
AD		 6260 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6261 /* If no cable is present, then we need to reset
6262 * the next time we find a good cable. */
6263 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6264 }
9a799d71 6265
7086400d
AD		 6266 /* exit on error */
6267 if (err)
6268 goto sfp_out;
e8e26350 6269
7086400d
AD		 6270 /* exit if reset not needed */
6271 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6272 goto sfp_out;
9a799d71 6273
7086400d 6274 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6275
7086400d
AD		 6276 /*
6277 * A module may be identified correctly, but the EEPROM may not have
6278 * support for that module. setup_sfp() will fail in that case, so
6279 * we should not allow that module to load.
6280 */
6281 if (hw->mac.type == ixgbe_mac_82598EB)
6282 err = hw->phy.ops.reset(hw);
6283 else
6284 err = hw->mac.ops.setup_sfp(hw);
6285
6286 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6287 goto sfp_out;
6288
6289 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6290 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6291
6292sfp_out:
6293 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6294
6295 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6296 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6297 e_dev_err("failed to initialize because an unsupported "
6298 "SFP+ module type was detected.\n");
6299 e_dev_err("Reload the driver after installing a "
6300 "supported module.\n");
6301 unregister_netdev(adapter->netdev);
bc59fcda 6302 }
7086400d 6303}
bc59fcda 6304
7086400d
AD		 6305/**
6306 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6307 * @adapter: the ixgbe adapter structure
7086400d
AD		 6308 **/
6309static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6310{
6311 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6312 u32 speed;
6313 bool autoneg = false;
7086400d
AD		 6314
6315 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6316 return;
6317
6318 /* someone else is in init, wait until next service event */
6319 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6320 return;
6321
6322 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6323
3d292265 6324 speed = hw->phy.autoneg_advertised;
ed33ff66 6325 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6326 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6327
6328 /* setup the highest link when no autoneg */
6329 if (!autoneg) {
6330 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6331 speed = IXGBE_LINK_SPEED_10GB_FULL;
6332 }
6333 }
6334
7086400d 6335 if (hw->mac.ops.setup_link)
fd0326f2 6336 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6337
6338 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6339 adapter->link_check_timeout = jiffies;
6340 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6341}
6342
83c61fa9
GR		 6343#ifdef CONFIG_PCI_IOV
6344static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6345{
6346 int vf;
6347 struct ixgbe_hw *hw = &adapter->hw;
6348 struct net_device *netdev = adapter->netdev;
6349 u32 gpc;
6350 u32 ciaa, ciad;
6351
6352 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6353 if (gpc) /* If incrementing then no need for the check below */
6354 return;
6355 /*
6356 * Check to see if a bad DMA write target from an errant or
6357 * malicious VF has caused a PCIe error. If so then we can
6358 * issue a VFLR to the offending VF(s) and then resume without
6359 * requesting a full slot reset.
6360 */
6361
6362 for (vf = 0; vf < adapter->num_vfs; vf++) {
6363 ciaa = (vf << 16) | 0x80000000;
6364 /* 32 bit read so align, we really want status at offset 6 */
6365 ciaa |= PCI_COMMAND;
6366 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6367 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6368 ciaa &= 0x7FFFFFFF;
6369 /* disable debug mode asap after reading data */
6370 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6371 /* Get the upper 16 bits which will be the PCI status reg */
6372 ciad >>= 16;
6373 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6374 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6375 /* Issue VFLR */
6376 ciaa = (vf << 16) | 0x80000000;
6377 ciaa |= 0xA8;
6378 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6379 ciad = 0x00008000; /* VFLR */
6380 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6381 ciaa &= 0x7FFFFFFF;
6382 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6383 }
6384 }
6385}
6386
6387#endif
7086400d
AD		 6388/**
6389 * ixgbe_service_timer - Timer Call-back
6390 * @data: pointer to adapter cast into an unsigned long
6391 **/
6392static void ixgbe_service_timer(unsigned long data)
6393{
6394 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6395 unsigned long next_event_offset;
83c61fa9 6396 bool ready = true;
7086400d 6397
6bb78cfb
AD		 6398 /* poll faster when waiting for link */
6399 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6400 next_event_offset = HZ / 10;
6401 else
6402 next_event_offset = HZ * 2;
83c61fa9 6403
6bb78cfb 6404#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6405 /*
6406 * don't bother with SR-IOV VF DMA hang check if there are
6407 * no VFs or the link is down
6408 */
6409 if (!adapter->num_vfs ||
6bb78cfb 6410 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6411 goto normal_timer_service;
83c61fa9
GR		 6412
6413 /* If we have VFs allocated then we must check for DMA hangs */
6414 ixgbe_check_for_bad_vf(adapter);
6415 next_event_offset = HZ / 50;
6416 adapter->timer_event_accumulator++;
6417
6bb78cfb 6418 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6419 adapter->timer_event_accumulator = 0;
7086400d 6420 else
6bb78cfb 6421 ready = false;
7086400d 6422
6bb78cfb 6423normal_timer_service:
83c61fa9 6424#endif
7086400d
AD		 6425 /* Reset the timer */
6426 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6427
83c61fa9
GR		 6428 if (ready)
6429 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6430}
6431
c83c6cbd
AD		 6432static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6433{
6434 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6435 return;
6436
6437 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6438
09f40aed 6439 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6440 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6441 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6442 test_bit(__IXGBE_RESETTING, &adapter->state))
6443 return;
6444
6445 ixgbe_dump(adapter);
6446 netdev_err(adapter->netdev, "Reset adapter\n");
6447 adapter->tx_timeout_count++;
6448
8f4c5c9f 6449 rtnl_lock();
c83c6cbd 6450 ixgbe_reinit_locked(adapter);
8f4c5c9f 6451 rtnl_unlock();
c83c6cbd
AD		 6452}
6453
7086400d
AD		 6454/**
6455 * ixgbe_service_task - manages and runs subtasks
6456 * @work: pointer to work_struct containing our data
6457 **/
6458static void ixgbe_service_task(struct work_struct *work)
6459{
6460 struct ixgbe_adapter *adapter = container_of(work,
6461 struct ixgbe_adapter,
6462 service_task);
b0483c8f
MR		 6463 if (ixgbe_removed(adapter->hw.hw_addr)) {
6464 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6465 rtnl_lock();
6466 ixgbe_down(adapter);
6467 rtnl_unlock();
6468 }
6469 ixgbe_service_event_complete(adapter);
6470 return;
6471 }
c83c6cbd 6472 ixgbe_reset_subtask(adapter);
7086400d
AD		 6473 ixgbe_sfp_detection_subtask(adapter);
6474 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6475 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6476 ixgbe_watchdog_subtask(adapter);
d034acf1 6477 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6478 ixgbe_check_hang_subtask(adapter);
891dc082 6479
8fecf67c 6480 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6481 ixgbe_ptp_overflow_check(adapter);
6482 ixgbe_ptp_rx_hang(adapter);
6483 }
7086400d
AD		 6484
6485 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6486}
6487
fd0db0ed
AD		 6488static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6489 struct ixgbe_tx_buffer *first,
244e27ad 6490 u8 *hdr_len)
897ab156 6491{
fd0db0ed 6492 struct sk_buff *skb = first->skb;
897ab156
AD		 6493 u32 vlan_macip_lens, type_tucmd;
6494 u32 mss_l4len_idx, l4len;
9a799d71 6495
8f4fbb9b
AD		 6496 if (skb->ip_summed != CHECKSUM_PARTIAL)
6497 return 0;
6498
897ab156
AD		 6499 if (!skb_is_gso(skb))
6500 return 0;
9a799d71 6501
897ab156 6502 if (skb_header_cloned(skb)) {
244e27ad 6503 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6504 if (err)
6505 return err;
9a799d71 6506 }
9a799d71 6507
897ab156
AD		 6508 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6509 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6510
244e27ad 6511 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 6512 struct iphdr *iph = ip_hdr(skb);
6513 iph->tot_len = 0;
6514 iph->check = 0;
6515 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6516 iph->daddr, 0,
6517 IPPROTO_TCP,
6518 0);
6519 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6520 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6521 IXGBE_TX_FLAGS_CSUM |
6522 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6523 } else if (skb_is_gso_v6(skb)) {
6524 ipv6_hdr(skb)->payload_len = 0;
6525 tcp_hdr(skb)->check =
6526 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6527 &ipv6_hdr(skb)->daddr,
6528 0, IPPROTO_TCP, 0);
244e27ad
AD		 6529 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6530 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6531 }
6532
091a6246 6533 /* compute header lengths */
897ab156
AD		 6534 l4len = tcp_hdrlen(skb);
6535 *hdr_len = skb_transport_offset(skb) + l4len;
6536
091a6246
AD		 6537 /* update gso size and bytecount with header size */
6538 first->gso_segs = skb_shinfo(skb)->gso_segs;
6539 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6540
c44f5f51 6541 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6542 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6543 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6544
6545 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6546 vlan_macip_lens = skb_network_header_len(skb);
6547 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6548 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6549
6550 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6551 mss_l4len_idx);
897ab156
AD		 6552
6553 return 1;
6554}
6555
244e27ad
AD		 6556static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6557 struct ixgbe_tx_buffer *first)
7ca647bd 6558{
fd0db0ed 6559 struct sk_buff *skb = first->skb;
897ab156
AD		 6560 u32 vlan_macip_lens = 0;
6561 u32 mss_l4len_idx = 0;
6562 u32 type_tucmd = 0;
7ca647bd 6563
897ab156 6564 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6565 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6566 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6567 return;
897ab156
AD		 6568 } else {
6569 u8 l4_hdr = 0;
244e27ad 6570 switch (first->protocol) {
897ab156
AD		 6571 case __constant_htons(ETH_P_IP):
6572 vlan_macip_lens |= skb_network_header_len(skb);
6573 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6574 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6575 break;
897ab156
AD		 6576 case __constant_htons(ETH_P_IPV6):
6577 vlan_macip_lens |= skb_network_header_len(skb);
6578 l4_hdr = ipv6_hdr(skb)->nexthdr;
6579 break;
6580 default:
6581 if (unlikely(net_ratelimit())) {
6582 dev_warn(tx_ring->dev,
6583 "partial checksum but proto=%x!\n",
244e27ad 6584 first->protocol);
897ab156 6585 }
7ca647bd
JP		 6586 break;
6587 }
897ab156
AD		 6588
6589 switch (l4_hdr) {
7ca647bd 6590 case IPPROTO_TCP:
897ab156
AD		 6591 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6592 mss_l4len_idx = tcp_hdrlen(skb) <<
6593 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6594 break;
6595 case IPPROTO_SCTP:
897ab156
AD		 6596 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6597 mss_l4len_idx = sizeof(struct sctphdr) <<
6598 IXGBE_ADVTXD_L4LEN_SHIFT;
6599 break;
6600 case IPPROTO_UDP:
6601 mss_l4len_idx = sizeof(struct udphdr) <<
6602 IXGBE_ADVTXD_L4LEN_SHIFT;
6603 break;
6604 default:
6605 if (unlikely(net_ratelimit())) {
6606 dev_warn(tx_ring->dev,
6607 "partial checksum but l4 proto=%x!\n",
244e27ad 6608 l4_hdr);
897ab156 6609 }
7ca647bd
JP		 6610 break;
6611 }
244e27ad
AD		 6612
6613 /* update TX checksum flag */
6614 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6615 }
6616
244e27ad 6617 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6618 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6619 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6620
897ab156
AD		 6621 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6622 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6623}
6624
472148c3
AD		 6625#define IXGBE_SET_FLAG(_input, _flag, _result) \
6626 ((_flag <= _result) ? \
6627 ((u32)(_input & _flag) * (_result / _flag)) : \
6628 ((u32)(_input & _flag) / (_flag / _result)))
6629
6630static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6631{
d3d00239 6632 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6633 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6634 IXGBE_ADVTXD_DCMD_DEXT |
6635 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6636
d3d00239 6637 /* set HW vlan bit if vlan is present */
472148c3
AD		 6638 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6639 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6640
d3d00239 6641 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6642 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6643 IXGBE_ADVTXD_DCMD_TSE);
6644
6645 /* set timestamp bit if present */
6646 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6647 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6648
62748b7b 6649 /* insert frame checksum */
472148c3 6650 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6651
d3d00239
AD		 6652 return cmd_type;
6653}
9a799d71 6654
729739b7
AD		 6655static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6656 u32 tx_flags, unsigned int paylen)
d3d00239 6657{
472148c3 6658 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6659
d3d00239 6660 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6661 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6662 IXGBE_TX_FLAGS_CSUM,
6663 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6664
93f5b3c1 6665 /* enble IPv4 checksum for TSO */
472148c3
AD		 6666 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6667 IXGBE_TX_FLAGS_IPV4,
6668 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6669
7f9643fd
AD		 6670 /*
6671 * Check Context must be set if Tx switch is enabled, which it
6672 * always is for case where virtual functions are running
6673 */
472148c3
AD		 6674 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6675 IXGBE_TX_FLAGS_CC,
6676 IXGBE_ADVTXD_CC);
7f9643fd 6677
472148c3 6678 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6679}
44df32c5 6680
d3d00239
AD		 6681#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6682 IXGBE_TXD_CMD_RS)
6683
6684static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6685 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6686 const u8 hdr_len)
6687{
fd0db0ed 6688 struct sk_buff *skb = first->skb;
729739b7 6689 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6690 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6691 struct skb_frag_struct *frag;
6692 dma_addr_t dma;
6693 unsigned int data_len, size;
244e27ad 6694 u32 tx_flags = first->tx_flags;
472148c3 6695 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6696 u16 i = tx_ring->next_to_use;
d3d00239 6697
729739b7
AD		 6698 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6699
ec718254
AD		 6700 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6701
6702 size = skb_headlen(skb);
6703 data_len = skb->data_len;
729739b7 6704
d3d00239
AD		 6705#ifdef IXGBE_FCOE
6706 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6707 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6708 size -= sizeof(struct fcoe_crc_eof) - data_len;
6709 data_len = 0;
729739b7
AD		 6710 } else {
6711 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6712 }
6713 }
44df32c5 6714
d3d00239 6715#endif
729739b7 6716 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6717
ec718254 6718 tx_buffer = first;
9a799d71 6719
ec718254
AD		 6720 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6721 if (dma_mapping_error(tx_ring->dev, dma))
6722 goto dma_error;
6723
6724 /* record length, and DMA address */
6725 dma_unmap_len_set(tx_buffer, len, size);
6726 dma_unmap_addr_set(tx_buffer, dma, dma);
6727
6728 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6729
729739b7 6730 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6731 tx_desc->read.cmd_type_len =
472148c3 6732 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6733
d3d00239 6734 i++;
729739b7 6735 tx_desc++;
d3d00239 6736 if (i == tx_ring->count) {
e4f74028 6737 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6738 i = 0;
6739 }
ec718254 6740 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6741
6742 dma += IXGBE_MAX_DATA_PER_TXD;
6743 size -= IXGBE_MAX_DATA_PER_TXD;
6744
6745 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6746 }
e5a43549 6747
729739b7
AD		 6748 if (likely(!data_len))
6749 break;
9a799d71 6750
472148c3 6751 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6752
729739b7
AD		 6753 i++;
6754 tx_desc++;
6755 if (i == tx_ring->count) {
6756 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6757 i = 0;
6758 }
ec718254 6759 tx_desc->read.olinfo_status = 0;
9a799d71 6760
d3d00239 6761#ifdef IXGBE_FCOE
9e903e08 6762 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6763#else
9e903e08 6764 size = skb_frag_size(frag);
d3d00239
AD		 6765#endif
6766 data_len -= size;
9a799d71 6767
729739b7
AD		 6768 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6769 DMA_TO_DEVICE);
9a799d71 6770
729739b7 6771 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6772 }
9a799d71 6773
729739b7 6774 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6775 cmd_type |= size | IXGBE_TXD_CMD;
6776 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6777
091a6246 6778 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6779
d3d00239
AD		 6780 /* set the timestamp */
6781 first->time_stamp = jiffies;
9a799d71
AK		 6782
6783 /*
729739b7
AD		 6784 * Force memory writes to complete before letting h/w know there
6785 * are new descriptors to fetch. (Only applicable for weak-ordered
6786 * memory model archs, such as IA-64).
6787 *
6788 * We also need this memory barrier to make certain all of the
6789 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6790 */
6791 wmb();
6792
d3d00239
AD		 6793 /* set next_to_watch value indicating a packet is present */
6794 first->next_to_watch = tx_desc;
6795
729739b7
AD		 6796 i++;
6797 if (i == tx_ring->count)
6798 i = 0;
6799
6800 tx_ring->next_to_use = i;
6801
d3d00239 6802 /* notify HW of packet */
84227bcd 6803 ixgbe_write_tail(tx_ring, i);
d3d00239
AD		 6804
6805 return;
6806dma_error:
729739b7 6807 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6808
6809 /* clear dma mappings for failed tx_buffer_info map */
6810 for (;;) {
729739b7
AD		 6811 tx_buffer = &tx_ring->tx_buffer_info[i];
6812 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6813 if (tx_buffer == first)
d3d00239
AD		 6814 break;
6815 if (i == 0)
6816 i = tx_ring->count;
6817 i--;
6818 }
6819
d3d00239 6820 tx_ring->next_to_use = i;
9a799d71
AK		 6821}
6822
fd0db0ed 6823static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6824 struct ixgbe_tx_buffer *first)
69830529
AD		 6825{
6826 struct ixgbe_q_vector *q_vector = ring->q_vector;
6827 union ixgbe_atr_hash_dword input = { .dword = 0 };
6828 union ixgbe_atr_hash_dword common = { .dword = 0 };
6829 union {
6830 unsigned char *network;
6831 struct iphdr *ipv4;
6832 struct ipv6hdr *ipv6;
6833 } hdr;
ee9e0f0b 6834 struct tcphdr *th;
905e4a41 6835 __be16 vlan_id;
c4cf55e5 6836
69830529
AD		 6837 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6838 if (!q_vector)
6839 return;
6840
6841 /* do nothing if sampling is disabled */
6842 if (!ring->atr_sample_rate)
d3ead241 6843 return;
c4cf55e5 6844
69830529 6845 ring->atr_count++;
c4cf55e5 6846
69830529 6847 /* snag network header to get L4 type and address */
fd0db0ed 6848 hdr.network = skb_network_header(first->skb);
69830529
AD		 6849
6850 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6851 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6852 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6853 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6854 hdr.ipv4->protocol != IPPROTO_TCP))
6855 return;
ee9e0f0b 6856
fd0db0ed 6857 th = tcp_hdr(first->skb);
c4cf55e5 6858
66f32a8b
AD		 6859 /* skip this packet since it is invalid or the socket is closing */
6860 if (!th || th->fin)
69830529
AD		 6861 return;
6862
6863 /* sample on all syn packets or once every atr sample count */
6864 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6865 return;
6866
6867 /* reset sample count */
6868 ring->atr_count = 0;
6869
244e27ad 6870 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6871
6872 /*
6873 * src and dst are inverted, think how the receiver sees them
6874 *
6875 * The input is broken into two sections, a non-compressed section
6876 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6877 * is XORed together and stored in the compressed dword.
6878 */
6879 input.formatted.vlan_id = vlan_id;
6880
6881 /*
6882 * since src port and flex bytes occupy the same word XOR them together
6883 * and write the value to source port portion of compressed dword
6884 */
244e27ad 6885 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6886 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6887 else
244e27ad 6888 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6889 common.port.dst ^= th->source;
6890
244e27ad 6891 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6892 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6893 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6894 } else {
6895 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6896 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6897 hdr.ipv6->saddr.s6_addr32[1] ^
6898 hdr.ipv6->saddr.s6_addr32[2] ^
6899 hdr.ipv6->saddr.s6_addr32[3] ^
6900 hdr.ipv6->daddr.s6_addr32[0] ^
6901 hdr.ipv6->daddr.s6_addr32[1] ^
6902 hdr.ipv6->daddr.s6_addr32[2] ^
6903 hdr.ipv6->daddr.s6_addr32[3];
6904 }
c4cf55e5
PWJ		 6905
6906 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6907 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6908 input, common, ring->queue_index);
c4cf55e5
PWJ		 6909}
6910
63544e9c 6911static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6912{
fc77dc3c 6913 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6914 /* Herbert's original patch had:
6915 * smp_mb__after_netif_stop_queue();
6916 * but since that doesn't exist yet, just open code it. */
6917 smp_mb();
6918
6919 /* We need to check again in a case another CPU has just
6920 * made room available. */
7d4987de 6921 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6922 return -EBUSY;
6923
6924 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6925 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6926 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6927 return 0;
6928}
6929
82d4e46e 6930static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6931{
7d4987de 6932 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6933 return 0;
fc77dc3c 6934 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6935}
6936
f663dd9a 6937static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 6938 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 6939{
f663dd9a
JW		 6940 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
6941#ifdef IXGBE_FCOE
97488bd1
AD		 6942 struct ixgbe_adapter *adapter;
6943 struct ixgbe_ring_feature *f;
6944 int txq;
f663dd9a
JW		 6945#endif
6946
6947 if (fwd_adapter)
6948 return skb->queue_mapping + fwd_adapter->tx_base_queue;
6949
6950#ifdef IXGBE_FCOE
5e09a105 6951
97488bd1
AD		 6952 /*
6953 * only execute the code below if protocol is FCoE
6954 * or FIP and we have FCoE enabled on the adapter
6955 */
6956 switch (vlan_get_protocol(skb)) {
6957 case __constant_htons(ETH_P_FCOE):
6958 case __constant_htons(ETH_P_FIP):
6959 adapter = netdev_priv(dev);
c087663e 6960
97488bd1
AD		 6961 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6962 break;
6963 default:
99932d4f 6964 return fallback(dev, skb);
97488bd1 6965 }
c087663e 6966
97488bd1 6967 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6968
97488bd1
AD		 6969 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6970 smp_processor_id();
56075a98 6971
97488bd1
AD		 6972 while (txq >= f->indices)
6973 txq -= f->indices;
c4cf55e5 6974
97488bd1 6975 return txq + f->offset;
f663dd9a 6976#else
99932d4f 6977 return fallback(dev, skb);
f663dd9a 6978#endif
09a3b1f8
SH		 6979}
6980
fc77dc3c 6981netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6982 struct ixgbe_adapter *adapter,
6983 struct ixgbe_ring *tx_ring)
9a799d71 6984{
d3d00239 6985 struct ixgbe_tx_buffer *first;
5f715823 6986 int tso;
d3d00239 6987 u32 tx_flags = 0;
a535c30e 6988 unsigned short f;
a535c30e 6989 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6990 __be16 protocol = skb->protocol;
63544e9c 6991 u8 hdr_len = 0;
5e09a105 6992
a535c30e
AD		 6993 /*
6994 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6995 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6996 * + 2 desc gap to keep tail from touching head,
6997 * + 1 desc for context descriptor,
6998 * otherwise try next time
6999 */
a535c30e
AD		 7000 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7001 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7002
a535c30e
AD		 7003 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7004 tx_ring->tx_stats.tx_busy++;
7005 return NETDEV_TX_BUSY;
7006 }
7007
fd0db0ed
AD		 7008 /* record the location of the first descriptor for this packet */
7009 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7010 first->skb = skb;
091a6246
AD		 7011 first->bytecount = skb->len;
7012 first->gso_segs = 1;
fd0db0ed 7013
66f32a8b 7014 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7015 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7016 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7017 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7018 /* else if it is a SW VLAN check the next protocol and store the tag */
7019 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7020 struct vlan_hdr *vhdr, _vhdr;
7021 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7022 if (!vhdr)
7023 goto out_drop;
7024
7025 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7026 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7027 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7028 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7029 }
7030
aa7bd467
JK		 7031 skb_tx_timestamp(skb);
7032
3a6a4eda
JK		 7033 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
7034 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7035 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7036
7037 /* schedule check for Tx timestamp */
7038 adapter->ptp_tx_skb = skb_get(skb);
7039 adapter->ptp_tx_start = jiffies;
7040 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7041 }
3a6a4eda 7042
9e0c5648
AD		 7043#ifdef CONFIG_PCI_IOV
7044 /*
7045 * Use the l2switch_enable flag - would be false if the DMA
7046 * Tx switch had been disabled.
7047 */
7048 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7049 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7050
7051#endif
32701dc2 7052 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7053 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7054 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7055 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7056 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7057 tx_flags |= (skb->priority & 0x7) <<
7058 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7059 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7060 struct vlan_ethhdr *vhdr;
7061 if (skb_header_cloned(skb) &&
7062 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7063 goto out_drop;
7064 vhdr = (struct vlan_ethhdr *)skb->data;
7065 vhdr->h_vlan_TCI = htons(tx_flags >>
7066 IXGBE_TX_FLAGS_VLAN_SHIFT);
7067 } else {
7068 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7069 }
9a799d71 7070 }
eacd73f7 7071
244e27ad
AD		 7072 /* record initial flags and protocol */
7073 first->tx_flags = tx_flags;
7074 first->protocol = protocol;
7075
eacd73f7 7076#ifdef IXGBE_FCOE
66f32a8b
AD		 7077 /* setup tx offload for FCoE */
7078 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 7079 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7080 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7081 if (tso < 0)
7082 goto out_drop;
9a799d71 7083
66f32a8b 7084 goto xmit_fcoe;
eacd73f7 7085 }
9a799d71 7086
66f32a8b 7087#endif /* IXGBE_FCOE */
244e27ad 7088 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7089 if (tso < 0)
897ab156 7090 goto out_drop;
244e27ad
AD		 7091 else if (!tso)
7092 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7093
7094 /* add the ATR filter if ATR is on */
7095 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7096 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7097
7098#ifdef IXGBE_FCOE
7099xmit_fcoe:
7100#endif /* IXGBE_FCOE */
244e27ad 7101 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 7102
7103 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7104
7105 return NETDEV_TX_OK;
897ab156
AD		 7106
7107out_drop:
fd0db0ed
AD		 7108 dev_kfree_skb_any(first->skb);
7109 first->skb = NULL;
7110
897ab156 7111 return NETDEV_TX_OK;
9a799d71
AK		 7112}
7113
2a47fa45
JF		 7114static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7115 struct net_device *netdev,
7116 struct ixgbe_ring *ring)
84418e3b
AD		 7117{
7118 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7119 struct ixgbe_ring *tx_ring;
7120
a50c29dd
AD		 7121 /*
7122 * The minimum packet size for olinfo paylen is 17 so pad the skb
7123 * in order to meet this minimum size requirement.
7124 */
f73332fc
SH		 7125 if (unlikely(skb->len < 17)) {
7126 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7127 return NETDEV_TX_OK;
7128 skb->len = 17;
71a49f77 7129 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7130 }
7131
2a47fa45
JF		 7132 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7133
fc77dc3c 7134 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7135}
7136
2a47fa45
JF		 7137static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7138 struct net_device *netdev)
7139{
7140 return __ixgbe_xmit_frame(skb, netdev, NULL);
7141}
7142
9a799d71
AK		 7143/**
7144 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7145 * @netdev: network interface device structure
7146 * @p: pointer to an address structure
7147 *
7148 * Returns 0 on success, negative on failure
7149 **/
7150static int ixgbe_set_mac(struct net_device *netdev, void *p)
7151{
7152 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7153 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7154 struct sockaddr *addr = p;
7155
7156 if (!is_valid_ether_addr(addr->sa_data))
7157 return -EADDRNOTAVAIL;
7158
7159 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7160 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7161
1d9c0bfd 7162 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 7163
7164 return 0;
7165}
7166
6b73e10d
BH		 7167static int
7168ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7169{
7170 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7171 struct ixgbe_hw *hw = &adapter->hw;
7172 u16 value;
7173 int rc;
7174
7175 if (prtad != hw->phy.mdio.prtad)
7176 return -EINVAL;
7177 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7178 if (!rc)
7179 rc = value;
7180 return rc;
7181}
7182
7183static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7184 u16 addr, u16 value)
7185{
7186 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7187 struct ixgbe_hw *hw = &adapter->hw;
7188
7189 if (prtad != hw->phy.mdio.prtad)
7190 return -EINVAL;
7191 return hw->phy.ops.write_reg(hw, addr, devad, value);
7192}
7193
7194static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7195{
7196 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7197
3a6a4eda 7198 switch (cmd) {
3a6a4eda 7199 case SIOCSHWTSTAMP:
93501d48
JK		 7200 return ixgbe_ptp_set_ts_config(adapter, req);
7201 case SIOCGHWTSTAMP:
7202 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7203 default:
7204 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7205 }
6b73e10d
BH		 7206}
7207
0365e6e4
PW		 7208/**
7209 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7210 * netdev->dev_addrs
0365e6e4
PW		 7211 * @netdev: network interface device structure
7212 *
7213 * Returns non-zero on failure
7214 **/
7215static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7216{
7217 int err = 0;
7218 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7219 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7220
7fa7c9dc 7221 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7222 rtnl_lock();
7fa7c9dc 7223 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7224 rtnl_unlock();
7fa7c9dc
AD		 7225
7226 /* update SAN MAC vmdq pool selection */
7227 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7228 }
7229 return err;
7230}
7231
7232/**
7233 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7234 * netdev->dev_addrs
0365e6e4
PW		 7235 * @netdev: network interface device structure
7236 *
7237 * Returns non-zero on failure
7238 **/
7239static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7240{
7241 int err = 0;
7242 struct ixgbe_adapter *adapter = netdev_priv(dev);
7243 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7244
7245 if (is_valid_ether_addr(mac->san_addr)) {
7246 rtnl_lock();
7247 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7248 rtnl_unlock();
7249 }
7250 return err;
7251}
7252
9a799d71
AK		 7253#ifdef CONFIG_NET_POLL_CONTROLLER
7254/*
7255 * Polling 'interrupt' - used by things like netconsole to send skbs
7256 * without having to re-enable interrupts. It's not called while
7257 * the interrupt routine is executing.
7258 */
7259static void ixgbe_netpoll(struct net_device *netdev)
7260{
7261 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7262 int i;
9a799d71 7263
1a647bd2
AD		 7264 /* if interface is down do nothing */
7265 if (test_bit(__IXGBE_DOWN, &adapter->state))
7266 return;
7267
9a799d71 7268 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7269 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7270 for (i = 0; i < adapter->num_q_vectors; i++)
7271 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7272 } else {
7273 ixgbe_intr(adapter->pdev->irq, netdev);
7274 }
9a799d71 7275 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7276}
9a799d71 7277
581330ba 7278#endif
de1036b1
ED		 7279static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7280 struct rtnl_link_stats64 *stats)
7281{
7282 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7283 int i;
7284
1a51502b 7285 rcu_read_lock();
de1036b1 7286 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7287 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7288 u64 bytes, packets;
7289 unsigned int start;
7290
1a51502b
ED		 7291 if (ring) {
7292 do {
7293 start = u64_stats_fetch_begin_bh(&ring->syncp);
7294 packets = ring->stats.packets;
7295 bytes = ring->stats.bytes;
7296 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7297 stats->rx_packets += packets;
7298 stats->rx_bytes += bytes;
7299 }
de1036b1 7300 }
1ac9ad13
ED		 7301
7302 for (i = 0; i < adapter->num_tx_queues; i++) {
7303 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7304 u64 bytes, packets;
7305 unsigned int start;
7306
7307 if (ring) {
7308 do {
7309 start = u64_stats_fetch_begin_bh(&ring->syncp);
7310 packets = ring->stats.packets;
7311 bytes = ring->stats.bytes;
7312 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7313 stats->tx_packets += packets;
7314 stats->tx_bytes += bytes;
7315 }
7316 }
1a51502b 7317 rcu_read_unlock();
de1036b1
ED		 7318 /* following stats updated by ixgbe_watchdog_task() */
7319 stats->multicast = netdev->stats.multicast;
7320 stats->rx_errors = netdev->stats.rx_errors;
7321 stats->rx_length_errors = netdev->stats.rx_length_errors;
7322 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7323 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7324 return stats;
7325}
7326
8af3c33f 7327#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7328/**
7329 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7330 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7331 * @tc: number of traffic classes currently enabled
7332 *
7333 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7334 * 802.1Q priority maps to a packet buffer that exists.
7335 */
7336static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7337{
7338 struct ixgbe_hw *hw = &adapter->hw;
7339 u32 reg, rsave;
7340 int i;
7341
7342 /* 82598 have a static priority to TC mapping that can not
7343 * be changed so no validation is needed.
7344 */
7345 if (hw->mac.type == ixgbe_mac_82598EB)
7346 return;
7347
7348 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7349 rsave = reg;
7350
7351 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7352 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7353
7354 /* If up2tc is out of bounds default to zero */
7355 if (up2tc > tc)
7356 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7357 }
7358
7359 if (reg != rsave)
7360 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7361
7362 return;
7363}
7364
02debdc9
AD		 7365/**
7366 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7367 * @adapter: Pointer to adapter struct
7368 *
7369 * Populate the netdev user priority to tc map
7370 */
7371static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7372{
7373 struct net_device *dev = adapter->netdev;
7374 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7375 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7376 u8 prio;
7377
7378 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7379 u8 tc = 0;
7380
7381 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7382 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7383 else if (ets)
7384 tc = ets->prio_tc[prio];
7385
7386 netdev_set_prio_tc_map(dev, prio, tc);
7387 }
7388}
7389
cca73c59 7390#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7391/**
7392 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7393 *
7394 * @netdev: net device to configure
7395 * @tc: number of traffic classes to enable
7396 */
7397int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7398{
8b1c0b24
JF		 7399 struct ixgbe_adapter *adapter = netdev_priv(dev);
7400 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7401 bool pools;
8b1c0b24 7402
8b1c0b24 7403 /* Hardware supports up to 8 traffic classes */
4de2a022 7404 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7405 (hw->mac.type == ixgbe_mac_82598EB &&
7406 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7407 return -EINVAL;
7408
2a47fa45
JF		 7409 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7410 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7411 return -EBUSY;
7412
8b1c0b24 7413 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7414 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7415 * hardware is not flexible enough to do this dynamically.
7416 */
7417 if (netif_running(dev))
7418 ixgbe_close(dev);
7419 ixgbe_clear_interrupt_scheme(adapter);
7420
cca73c59 7421#ifdef CONFIG_IXGBE_DCB
e7589eab 7422 if (tc) {
8b1c0b24 7423 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7424 ixgbe_set_prio_tc_map(adapter);
7425
e7589eab 7426 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7427
943561d3
AD		 7428 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7429 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7430 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7431 }
e7589eab 7432 } else {
8b1c0b24 7433 netdev_reset_tc(dev);
02debdc9 7434
943561d3
AD		 7435 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7436 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7437
7438 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7439
7440 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7441 adapter->dcb_cfg.pfc_mode_enable = false;
7442 }
7443
8b1c0b24 7444 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7445
7446#endif /* CONFIG_IXGBE_DCB */
7447 ixgbe_init_interrupt_scheme(adapter);
7448
8b1c0b24 7449 if (netif_running(dev))
cca73c59 7450 return ixgbe_open(dev);
8b1c0b24
JF		 7451
7452 return 0;
7453}
de1036b1 7454
da36b647
GR		 7455#ifdef CONFIG_PCI_IOV
7456void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7457{
7458 struct net_device *netdev = adapter->netdev;
7459
7460 rtnl_lock();
da36b647 7461 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7462 rtnl_unlock();
7463}
7464
7465#endif
082757af
DS		 7466void ixgbe_do_reset(struct net_device *netdev)
7467{
7468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7469
7470 if (netif_running(netdev))
7471 ixgbe_reinit_locked(adapter);
7472 else
7473 ixgbe_reset(adapter);
7474}
7475
c8f44aff 7476static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7477 netdev_features_t features)
082757af
DS		 7478{
7479 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7480
082757af 7481 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7482 if (!(features & NETIF_F_RXCSUM))
7483 features &= ~NETIF_F_LRO;
082757af 7484
567d2de2
AD		 7485 /* Turn off LRO if not RSC capable */
7486 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7487 features &= ~NETIF_F_LRO;
8e2813f5 7488
567d2de2 7489 return features;
082757af
DS		 7490}
7491
c8f44aff 7492static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7493 netdev_features_t features)
082757af
DS		 7494{
7495 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7496 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7497 bool need_reset = false;
7498
082757af 7499 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7500 if (!(features & NETIF_F_LRO)) {
7501 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7502 need_reset = true;
567d2de2
AD		 7503 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7504 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7505 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7506 if (adapter->rx_itr_setting == 1 ||
7507 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7508 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7509 need_reset = true;
7510 } else if ((changed ^ features) & NETIF_F_LRO) {
7511 e_info(probe, "rx-usecs set too low, "
7512 "disabling RSC\n");
082757af
DS		 7513 }
7514 }
7515
7516 /*
7517 * Check if Flow Director n-tuple support was enabled or disabled. If
7518 * the state changed, we need to reset.
7519 */
39cb681b
AD		 7520 switch (features & NETIF_F_NTUPLE) {
7521 case NETIF_F_NTUPLE:
567d2de2 7522 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7523 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7524 need_reset = true;
7525
567d2de2
AD		 7526 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7527 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7528 break;
7529 default:
7530 /* turn off perfect filters, enable ATR and reset */
7531 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7532 need_reset = true;
7533
7534 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7535
7536 /* We cannot enable ATR if SR-IOV is enabled */
7537 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7538 break;
7539
7540 /* We cannot enable ATR if we have 2 or more traffic classes */
7541 if (netdev_get_num_tc(netdev) > 1)
7542 break;
7543
7544 /* We cannot enable ATR if RSS is disabled */
7545 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7546 break;
7547
7548 /* A sample rate of 0 indicates ATR disabled */
7549 if (!adapter->atr_sample_rate)
7550 break;
7551
7552 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7553 break;
082757af
DS		 7554 }
7555
f646968f 7556 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7557 ixgbe_vlan_strip_enable(adapter);
7558 else
7559 ixgbe_vlan_strip_disable(adapter);
7560
3f2d1c0f
BG		 7561 if (changed & NETIF_F_RXALL)
7562 need_reset = true;
7563
567d2de2 7564 netdev->features = features;
082757af
DS		 7565 if (need_reset)
7566 ixgbe_do_reset(netdev);
7567
7568 return 0;
082757af
DS		 7569}
7570
edc7d573 7571static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7572 struct net_device *dev,
6b6e2725 7573 const unsigned char *addr,
0f4b0add
JF		 7574 u16 flags)
7575{
7576 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7577 int err;
7578
7579 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7580 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7581
b1ac1ef7
JF		 7582 /* Hardware does not support aging addresses so if a
7583 * ndm_state is given only allow permanent addresses
7584 */
7585 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7586 pr_info("%s: FDB only supports static addresses\n",
7587 ixgbe_driver_name);
7588 return -EINVAL;
7589 }
7590
46acc460 7591 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7592 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7593
7594 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7595 err = dev_uc_add_excl(dev, addr);
0f4b0add 7596 else
95447461
JF		 7597 err = -ENOMEM;
7598 } else if (is_multicast_ether_addr(addr)) {
7599 err = dev_mc_add_excl(dev, addr);
7600 } else {
7601 err = -EINVAL;
0f4b0add
JF		 7602 }
7603
7604 /* Only return duplicate errors if NLM_F_EXCL is set */
7605 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7606 err = 0;
7607
7608 return err;
7609}
7610
815cccbf
JF		 7611static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7612 struct nlmsghdr *nlh)
7613{
7614 struct ixgbe_adapter *adapter = netdev_priv(dev);
7615 struct nlattr *attr, *br_spec;
7616 int rem;
7617
7618 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7619 return -EOPNOTSUPP;
7620
7621 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7622
7623 nla_for_each_nested(attr, br_spec, rem) {
7624 __u16 mode;
7625 u32 reg = 0;
7626
7627 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7628 continue;
7629
7630 mode = nla_get_u16(attr);
9b735984 7631 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7632 reg = 0;
9b735984
GR		 7633 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7634 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7635 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7636 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7637 } else
815cccbf
JF		 7638 return -EINVAL;
7639
7640 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7641
7642 e_info(drv, "enabling bridge mode: %s\n",
7643 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7644 }
7645
7646 return 0;
7647}
7648
7649static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7650 struct net_device *dev,
7651 u32 filter_mask)
815cccbf
JF		 7652{
7653 struct ixgbe_adapter *adapter = netdev_priv(dev);
7654 u16 mode;
7655
7656 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7657 return 0;
7658
9b735984 7659 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7660 mode = BRIDGE_MODE_VEB;
7661 else
7662 mode = BRIDGE_MODE_VEPA;
7663
7664 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7665}
7666
2a47fa45
JF		 7667static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7668{
7669 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7670 struct ixgbe_adapter *adapter = netdev_priv(pdev);
51f3773b 7671 unsigned int limit;
2a47fa45
JF		 7672 int pool, err;
7673
219354d4
JF		 7674#ifdef CONFIG_RPS
7675 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7676 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7677 vdev->name);
7678 return ERR_PTR(-EINVAL);
7679 }
7680#endif
2a47fa45 7681 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7682 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7683 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7684 netdev_info(pdev,
7685 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7686 pdev->name);
7687 return ERR_PTR(-EINVAL);
7688 }
7689
7690 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7691 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7692 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7693 return ERR_PTR(-EBUSY);
7694
7695 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7696 if (!fwd_adapter)
7697 return ERR_PTR(-ENOMEM);
7698
7699 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7700 adapter->num_rx_pools++;
7701 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7702 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7703
7704 /* Enable VMDq flag so device will be set in VM mode */
7705 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7706 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7707 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7708
7709 /* Force reinit of ring allocation with VMDQ enabled */
7710 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7711 if (err)
7712 goto fwd_add_err;
7713 fwd_adapter->pool = pool;
7714 fwd_adapter->real_adapter = adapter;
7715 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7716 if (err)
7717 goto fwd_add_err;
7718 netif_tx_start_all_queues(vdev);
7719 return fwd_adapter;
7720fwd_add_err:
7721 /* unwind counter and free adapter struct */
7722 netdev_info(pdev,
7723 "%s: dfwd hardware acceleration failed\n", vdev->name);
7724 clear_bit(pool, &adapter->fwd_bitmask);
7725 adapter->num_rx_pools--;
7726 kfree(fwd_adapter);
7727 return ERR_PTR(err);
7728}
7729
7730static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7731{
7732 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7733 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7734 unsigned int limit;
2a47fa45
JF		 7735
7736 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7737 adapter->num_rx_pools--;
7738
51f3773b
JF		 7739 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7740 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7741 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7742 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7743 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7744 fwd_adapter->pool, adapter->num_rx_pools,
7745 fwd_adapter->rx_base_queue,
7746 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7747 adapter->fwd_bitmask);
7748 kfree(fwd_adapter);
7749}
7750
0edc3527 7751static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7752 .ndo_open = ixgbe_open,
0edc3527 7753 .ndo_stop = ixgbe_close,
00829823 7754 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7755 .ndo_select_queue = ixgbe_select_queue,
581330ba 7756 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7757 .ndo_validate_addr = eth_validate_addr,
7758 .ndo_set_mac_address = ixgbe_set_mac,
7759 .ndo_change_mtu = ixgbe_change_mtu,
7760 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7761 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7762 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7763 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7764 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7765 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7766 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7767 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7768 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7769 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7770#ifdef CONFIG_IXGBE_DCB
24095aa3 7771 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7772#endif
0edc3527
SH		 7773#ifdef CONFIG_NET_POLL_CONTROLLER
7774 .ndo_poll_controller = ixgbe_netpoll,
7775#endif
e0d1095a 7776#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7777 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7778#endif
332d4a7d
YZ		 7779#ifdef IXGBE_FCOE
7780 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7781 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7782 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7783 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7784 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7785 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7786 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7787#endif /* IXGBE_FCOE */
082757af
DS		 7788 .ndo_set_features = ixgbe_set_features,
7789 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7790 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7791 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7792 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7793 .ndo_dfwd_add_station = ixgbe_fwd_add,
7794 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7795};
7796
e027d1ae
JK		 7797/**
7798 * ixgbe_enumerate_functions - Get the number of ports this device has
7799 * @adapter: adapter structure
7800 *
7801 * This function enumerates the phsyical functions co-located on a single slot,
7802 * in order to determine how many ports a device has. This is most useful in
7803 * determining the required GT/s of PCIe bandwidth necessary for optimal
7804 * performance.
7805 **/
7806static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7807{
e027d1ae
JK		 7808 struct list_head *entry;
7809 int physfns = 0;
7810
f1f96579
JK		 7811 /* Some cards can not use the generic count PCIe functions method,
7812 * because they are behind a parent switch, so we hardcode these with
7813 * the correct number of functions.
e027d1ae 7814 */
f1f96579 7815 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7816 physfns = 4;
f1f96579 7817 } else {
e027d1ae
JK		 7818 list_for_each(entry, &adapter->pdev->bus_list) {
7819 struct pci_dev *pdev =
7820 list_entry(entry, struct pci_dev, bus_list);
7821 /* don't count virtual functions */
7822 if (!pdev->is_virtfn)
7823 physfns++;
7824 }
7825 }
7826
7827 return physfns;
7828}
7829
8e2813f5
JK		 7830/**
7831 * ixgbe_wol_supported - Check whether device supports WoL
7832 * @hw: hw specific details
7833 * @device_id: the device ID
7834 * @subdev_id: the subsystem device ID
7835 *
7836 * This function is used by probe and ethtool to determine
7837 * which devices have WoL support
7838 *
7839 **/
7840int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7841 u16 subdevice_id)
7842{
7843 struct ixgbe_hw *hw = &adapter->hw;
7844 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7845 int is_wol_supported = 0;
7846
7847 switch (device_id) {
7848 case IXGBE_DEV_ID_82599_SFP:
7849 /* Only these subdevices could supports WOL */
7850 switch (subdevice_id) {
87557440 7851 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7852 case IXGBE_SUBDEV_ID_82599_560FLR:
7853 /* only support first port */
7854 if (hw->bus.func != 0)
7855 break;
5700ff26 7856 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7857 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7858 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7859 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7860 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7861 is_wol_supported = 1;
7862 break;
7863 }
7864 break;
5daebbb0
DS		 7865 case IXGBE_DEV_ID_82599EN_SFP:
7866 /* Only this subdevice supports WOL */
7867 switch (subdevice_id) {
7868 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7869 is_wol_supported = 1;
7870 break;
7871 }
7872 break;
8e2813f5
JK		 7873 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7874 /* All except this subdevice support WOL */
7875 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7876 is_wol_supported = 1;
7877 break;
7878 case IXGBE_DEV_ID_82599_KX4:
7879 is_wol_supported = 1;
7880 break;
7881 case IXGBE_DEV_ID_X540T:
df376f0d 7882 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7883 /* check eeprom to see if enabled wol */
7884 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7885 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7886 (hw->bus.func == 0))) {
7887 is_wol_supported = 1;
7888 }
7889 break;
7890 }
7891
7892 return is_wol_supported;
7893}
7894
9a799d71
AK		 7895/**
7896 * ixgbe_probe - Device Initialization Routine
7897 * @pdev: PCI device information struct
7898 * @ent: entry in ixgbe_pci_tbl
7899 *
7900 * Returns 0 on success, negative on failure
7901 *
7902 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7903 * The OS initialization, configuring of the adapter private structure,
7904 * and a hardware reset occur.
7905 **/
1dd06ae8 7906static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7907{
7908 struct net_device *netdev;
7909 struct ixgbe_adapter *adapter = NULL;
7910 struct ixgbe_hw *hw;
7911 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7912 static int cards_found;
e027d1ae 7913 int i, err, pci_using_dac, expected_gts;
d3cb9869 7914 unsigned int indices = MAX_TX_QUEUES;
289700db 7915 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7916#ifdef IXGBE_FCOE
7917 u16 device_caps;
7918#endif
289700db 7919 u32 eec;
9a799d71 7920
bded64a7
AG		 7921 /* Catch broken hardware that put the wrong VF device ID in
7922 * the PCIe SR-IOV capability.
7923 */
7924 if (pdev->is_virtfn) {
7925 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7926 pci_name(pdev), pdev->vendor, pdev->device);
7927 return -EINVAL;
7928 }
7929
9ce77666 7930 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7931 if (err)
7932 return err;
7933
f5f2eda8 7934 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7935 pci_using_dac = 1;
7936 } else {
f5f2eda8 7937 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7938 if (err) {
f5f2eda8
RK		 7939 dev_err(&pdev->dev,
7940 "No usable DMA configuration, aborting\n");
7941 goto err_dma;
9a799d71
AK		 7942 }
7943 pci_using_dac = 0;
7944 }
7945
9ce77666 7946 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7947 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7948 if (err) {
b8bc0421
DC		 7949 dev_err(&pdev->dev,
7950 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7951 goto err_pci_reg;
7952 }
7953
19d5afd4 7954 pci_enable_pcie_error_reporting(pdev);
6fabd715 7955
9a799d71 7956 pci_set_master(pdev);
fb3b27bc 7957 pci_save_state(pdev);
9a799d71 7958
d3cb9869 7959 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7960#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7961 /* 8 TC w/ 4 queues per TC */
7962 indices = 4 * MAX_TRAFFIC_CLASS;
7963#else
7964 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7965#endif
d3cb9869 7966 }
e901acd6 7967
c85a2618 7968 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7969 if (!netdev) {
7970 err = -ENOMEM;
7971 goto err_alloc_etherdev;
7972 }
7973
9a799d71
AK		 7974 SET_NETDEV_DEV(netdev, &pdev->dev);
7975
9a799d71 7976 adapter = netdev_priv(netdev);
c60fbb00 7977 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7978
7979 adapter->netdev = netdev;
7980 adapter->pdev = pdev;
7981 hw = &adapter->hw;
7982 hw->back = adapter;
b3f4d599 7983 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7984
05857980 7985 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7986 pci_resource_len(pdev, 0));
2a1a091c 7987 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 7988 if (!hw->hw_addr) {
7989 err = -EIO;
7990 goto err_ioremap;
7991 }
7992
0edc3527 7993 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7994 ixgbe_set_ethtool_ops(netdev);
9a799d71 7995 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7996 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7997
9a799d71
AK		 7998 adapter->bd_number = cards_found;
7999
9a799d71
AK		 8000 /* Setup hw api */
8001 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8002 hw->mac.type = ii->mac;
9a799d71 8003
c44ade9e
JB		 8004 /* EEPROM */
8005 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8006 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8007 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8008 if (!(eec & (1 << 8)))
8009 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8010
8011 /* PHY */
8012 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8013 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8014 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8015 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8016 hw->phy.mdio.mmds = 0;
8017 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8018 hw->phy.mdio.dev = netdev;
8019 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8020 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8021
8ca783ab 8022 ii->get_invariants(hw);
9a799d71
AK		 8023
8024 /* setup the private structure */
8025 err = ixgbe_sw_init(adapter);
8026 if (err)
8027 goto err_sw_init;
8028
0b2679d6
DS		 8029 /* Cache if MNG FW is up so we don't have to read the REG later */
8030 if (hw->mac.ops.mng_fw_enabled)
8031 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
8032
e86bff0e 8033 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8034 switch (adapter->hw.mac.type) {
8035 case ixgbe_mac_82599EB:
8036 case ixgbe_mac_X540:
e86bff0e 8037 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8038 break;
8039 default:
8040 break;
8041 }
e86bff0e 8042
bf069c97
DS		 8043 /*
8044 * If there is a fan on this device and it has failed log the
8045 * failure.
8046 */
8047 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8048 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8049 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8050 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8051 }
8052
8ef78adc
PWJ		 8053 if (allow_unsupported_sfp)
8054 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8055
c44ade9e 8056 /* reset_hw fills in the perm_addr as well */
119fc60a 8057 hw->phy.reset_if_overtemp = true;
c44ade9e 8058 err = hw->mac.ops.reset_hw(hw);
119fc60a 8059 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8060 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8061 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8062 err = 0;
8063 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8064 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8065 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8066 goto err_sw_init;
8067 } else if (err) {
849c4542 8068 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8069 goto err_sw_init;
8070 }
8071
99d74487 8072#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8073 /* SR-IOV not supported on the 82598 */
8074 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8075 goto skip_sriov;
8076 /* Mailbox */
8077 ixgbe_init_mbx_params_pf(hw);
8078 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8079 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8080 ixgbe_enable_sriov(adapter);
60a1a680 8081skip_sriov:
1cdd1ec8 8082
99d74487 8083#endif
396e799c 8084 netdev->features = NETIF_F_SG |
e8e9f696 8085 NETIF_F_IP_CSUM |
082757af 8086 NETIF_F_IPV6_CSUM |
f646968f
PM		 8087 NETIF_F_HW_VLAN_CTAG_TX |
8088 NETIF_F_HW_VLAN_CTAG_RX |
8089 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8090 NETIF_F_TSO |
8091 NETIF_F_TSO6 |
082757af 8092 NETIF_F_RXHASH |
8bf1264d 8093 NETIF_F_RXCSUM;
9a799d71 8094
8bf1264d 8095 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8096
58be7666
DS		 8097 switch (adapter->hw.mac.type) {
8098 case ixgbe_mac_82599EB:
8099 case ixgbe_mac_X540:
45a5ead0 8100 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8101 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8102 NETIF_F_NTUPLE;
58be7666
DS		 8103 break;
8104 default:
8105 break;
8106 }
45a5ead0 8107
3f2d1c0f
BG		 8108 netdev->hw_features |= NETIF_F_RXALL;
8109
ad31c402
JK		 8110 netdev->vlan_features |= NETIF_F_TSO;
8111 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8112 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8113 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8114 netdev->vlan_features |= NETIF_F_SG;
8115
01789349 8116 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8117 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8118
7a6b6f51 8119#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8120 netdev->dcbnl_ops = &dcbnl_ops;
8121#endif
8122
eacd73f7 8123#ifdef IXGBE_FCOE
0d551589 8124 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8125 unsigned int fcoe_l;
8126
eacd73f7
YZ		 8127 if (hw->mac.ops.get_device_caps) {
8128 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8129 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8130 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8131 }
7c8ae65a 8132
d3cb9869
AD		 8133
8134 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8135 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8136
a58915c7
AD		 8137 netdev->features |= NETIF_F_FSO |
8138 NETIF_F_FCOE_CRC;
8139
7c8ae65a
AD		 8140 netdev->vlan_features |= NETIF_F_FSO |
8141 NETIF_F_FCOE_CRC |
8142 NETIF_F_FCOE_MTU;
5e09d7f6 8143 }
eacd73f7 8144#endif /* IXGBE_FCOE */
7b872a55 8145 if (pci_using_dac) {
9a799d71 8146 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8147 netdev->vlan_features |= NETIF_F_HIGHDMA;
8148 }
9a799d71 8149
082757af
DS		 8150 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8151 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8152 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8153 netdev->features |= NETIF_F_LRO;
8154
9a799d71 8155 /* make sure the EEPROM is good */
c44ade9e 8156 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8157 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8158 err = -EIO;
35937c05 8159 goto err_sw_init;
9a799d71
AK		 8160 }
8161
8162 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8163
aaeb6cdf 8164 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8165 e_dev_err("invalid MAC address\n");
9a799d71 8166 err = -EIO;
35937c05 8167 goto err_sw_init;
9a799d71
AK		 8168 }
8169
7086400d 8170 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8171 (unsigned long) adapter);
9a799d71 8172
7086400d
AD		 8173 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8174 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8175
021230d4
AV		 8176 err = ixgbe_init_interrupt_scheme(adapter);
8177 if (err)
8178 goto err_sw_init;
9a799d71 8179
8e2813f5 8180 /* WOL not supported for all devices */
c23f5b6b 8181 adapter->wol = 0;
8e2813f5 8182 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8183 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8184 pdev->subsystem_device);
6b92b0ba 8185 if (hw->wol_enabled)
9417c464 8186 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8187
e8e26350
PW		 8188 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8189
15e5209f
ET		 8190 /* save off EEPROM version number */
8191 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8192 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8193
04f165ef
PW		 8194 /* pick up the PCI bus settings for reporting later */
8195 hw->mac.ops.get_bus_info(hw);
e027d1ae 8196 if (ixgbe_pcie_from_parent(hw))
b8e82001 8197 ixgbe_get_parent_bus_info(adapter);
04f165ef 8198
e027d1ae
JK		 8199 /* calculate the expected PCIe bandwidth required for optimal
8200 * performance. Note that some older parts will never have enough
8201 * bandwidth due to being older generation PCIe parts. We clamp these
8202 * parts to ensure no warning is displayed if it can't be fixed.
8203 */
8204 switch (hw->mac.type) {
8205 case ixgbe_mac_82598EB:
8206 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8207 break;
8208 default:
8209 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8210 break;
0c254d86 8211 }
e027d1ae 8212 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8213
6a2aae5a
JK		 8214 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8215 if (err)
8216 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8217 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8218 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8219 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8220 part_str);
8221 else
8222 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8223 hw->mac.type, hw->phy.type, part_str);
8224
8225 e_dev_info("%pM\n", netdev->dev_addr);
8226
9a799d71 8227 /* reset the hardware with the new settings */
794caeb2 8228 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8229 if (err == IXGBE_ERR_EEPROM_VERSION) {
8230 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8231 e_dev_warn("This device is a pre-production adapter/LOM. "
8232 "Please be aware there may be issues associated "
8233 "with your hardware. If you are experiencing "
8234 "problems please contact your Intel or hardware "
8235 "representative who provided you with this "
8236 "hardware.\n");
794caeb2 8237 }
9a799d71
AK		 8238 strcpy(netdev->name, "eth%d");
8239 err = register_netdev(netdev);
8240 if (err)
8241 goto err_register;
8242
ec74a471
ET		 8243 /* power down the optics for 82599 SFP+ fiber */
8244 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8245 hw->mac.ops.disable_tx_laser(hw);
8246
54386467
JB		 8247 /* carrier off reporting is important to ethtool even BEFORE open */
8248 netif_carrier_off(netdev);
8249
5dd2d332 8250#ifdef CONFIG_IXGBE_DCA
652f093f 8251 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8252 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8253 ixgbe_setup_dca(adapter);
8254 }
8255#endif
1cdd1ec8 8256 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8257 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8258 for (i = 0; i < adapter->num_vfs; i++)
8259 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8260 }
8261
2466dd9c
JK		 8262 /* firmware requires driver version to be 0xFFFFFFFF
8263 * since os does not support feature
8264 */
9612de92 8265 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8266 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8267 0xFF);
9612de92 8268
0365e6e4
PW		 8269 /* add san mac addr to netdev */
8270 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8271
ea81875a 8272 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8273 cards_found++;
3ca8bc6d 8274
1210982b 8275#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8276 if (ixgbe_sysfs_init(adapter))
8277 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8278#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8279
00949167 8280 ixgbe_dbg_adapter_init(adapter);
00949167 8281
0b2679d6
DS		 8282 /* Need link setup for MNG FW, else wait for IXGBE_UP */
8283 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
8284 hw->mac.ops.setup_link(hw,
8285 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8286 true);
8287
9a799d71
AK		 8288 return 0;
8289
8290err_register:
5eba3699 8291 ixgbe_release_hw_control(adapter);
7a921c93 8292 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8293err_sw_init:
99d74487 8294 ixgbe_disable_sriov(adapter);
7086400d 8295 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8296 iounmap(adapter->io_addr);
9a799d71
AK		 8297err_ioremap:
8298 free_netdev(netdev);
8299err_alloc_etherdev:
e8e9f696
JP		 8300 pci_release_selected_regions(pdev,
8301 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8302err_pci_reg:
8303err_dma:
8304 pci_disable_device(pdev);
8305 return err;
8306}
8307
8308/**
8309 * ixgbe_remove - Device Removal Routine
8310 * @pdev: PCI device information struct
8311 *
8312 * ixgbe_remove is called by the PCI subsystem to alert the driver
8313 * that it should release a PCI device. The could be caused by a
8314 * Hot-Plug event, or because the driver is going to be removed from
8315 * memory.
8316 **/
9f9a12f8 8317static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8318{
c60fbb00
AD		 8319 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8320 struct net_device *netdev = adapter->netdev;
9a799d71 8321
00949167 8322 ixgbe_dbg_adapter_exit(adapter);
00949167 8323
09f40aed 8324 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8325 cancel_work_sync(&adapter->service_task);
9a799d71 8326
3a6a4eda 8327
5dd2d332 8328#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8329 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8330 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8331 dca_remove_requester(&pdev->dev);
8332 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8333 }
8334
8335#endif
1210982b 8336#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8337 ixgbe_sysfs_exit(adapter);
1210982b 8338#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8339
0365e6e4
PW		 8340 /* remove the added san mac */
8341 ixgbe_del_sanmac_netdev(netdev);
8342
c4900be0
DS		 8343 if (netdev->reg_state == NETREG_REGISTERED)
8344 unregister_netdev(netdev);
9a799d71 8345
da36b647
GR		 8346#ifdef CONFIG_PCI_IOV
8347 /*
8348 * Only disable SR-IOV on unload if the user specified the now
8349 * deprecated max_vfs module parameter.
8350 */
8351 if (max_vfs)
8352 ixgbe_disable_sriov(adapter);
8353#endif
7a921c93 8354 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8355
021230d4 8356 ixgbe_release_hw_control(adapter);
9a799d71 8357
2b1588c3
AD		 8358#ifdef CONFIG_DCB
8359 kfree(adapter->ixgbe_ieee_pfc);
8360 kfree(adapter->ixgbe_ieee_ets);
8361
8362#endif
2a1a091c 8363 iounmap(adapter->io_addr);
9ce77666 8364 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8365 IORESOURCE_MEM));
9a799d71 8366
849c4542 8367 e_dev_info("complete\n");
021230d4 8368
9a799d71
AK		 8369 free_netdev(netdev);
8370
19d5afd4 8371 pci_disable_pcie_error_reporting(pdev);
6fabd715 8372
9a799d71
AK		 8373 pci_disable_device(pdev);
8374}
8375
8376/**
8377 * ixgbe_io_error_detected - called when PCI error is detected
8378 * @pdev: Pointer to PCI device
8379 * @state: The current pci connection state
8380 *
8381 * This function is called after a PCI bus error affecting
8382 * this device has been detected.
8383 */
8384static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8385 pci_channel_state_t state)
9a799d71 8386{
c60fbb00
AD		 8387 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8388 struct net_device *netdev = adapter->netdev;
9a799d71 8389
83c61fa9 8390#ifdef CONFIG_PCI_IOV
14438464 8391 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8392 struct pci_dev *bdev, *vfdev;
8393 u32 dw0, dw1, dw2, dw3;
8394 int vf, pos;
8395 u16 req_id, pf_func;
8396
8397 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8398 adapter->num_vfs == 0)
8399 goto skip_bad_vf_detection;
8400
8401 bdev = pdev->bus->self;
62f87c0e 8402 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8403 bdev = bdev->bus->self;
8404
8405 if (!bdev)
8406 goto skip_bad_vf_detection;
8407
8408 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8409 if (!pos)
8410 goto skip_bad_vf_detection;
8411
14438464
MR		 8412 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8413 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8414 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8415 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8416 if (ixgbe_removed(hw->hw_addr))
8417 goto skip_bad_vf_detection;
83c61fa9
GR		 8418
8419 req_id = dw1 >> 16;
8420 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8421 if (!(req_id & 0x0080))
8422 goto skip_bad_vf_detection;
8423
8424 pf_func = req_id & 0x01;
8425 if ((pf_func & 1) == (pdev->devfn & 1)) {
8426 unsigned int device_id;
8427
8428 vf = (req_id & 0x7F) >> 1;
8429 e_dev_err("VF %d has caused a PCIe error\n", vf);
8430 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8431 "%8.8x\tdw3: %8.8x\n",
8432 dw0, dw1, dw2, dw3);
8433 switch (adapter->hw.mac.type) {
8434 case ixgbe_mac_82599EB:
8435 device_id = IXGBE_82599_VF_DEVICE_ID;
8436 break;
8437 case ixgbe_mac_X540:
8438 device_id = IXGBE_X540_VF_DEVICE_ID;
8439 break;
8440 default:
8441 device_id = 0;
8442 break;
8443 }
8444
8445 /* Find the pci device of the offending VF */
36e90319 8446 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8447 while (vfdev) {
8448 if (vfdev->devfn == (req_id & 0xFF))
8449 break;
36e90319 8450 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8451 device_id, vfdev);
8452 }
8453 /*
8454 * There's a slim chance the VF could have been hot plugged,
8455 * so if it is no longer present we don't need to issue the
8456 * VFLR. Just clean up the AER in that case.
8457 */
8458 if (vfdev) {
8459 e_dev_err("Issuing VFLR to VF %d\n", vf);
8460 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8461 /* Free device reference count */
8462 pci_dev_put(vfdev);
83c61fa9
GR		 8463 }
8464
8465 pci_cleanup_aer_uncorrect_error_status(pdev);
8466 }
8467
8468 /*
8469 * Even though the error may have occurred on the other port
8470 * we still need to increment the vf error reference count for
8471 * both ports because the I/O resume function will be called
8472 * for both of them.
8473 */
8474 adapter->vferr_refcount++;
8475
8476 return PCI_ERS_RESULT_RECOVERED;
8477
8478skip_bad_vf_detection:
8479#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8480 netif_device_detach(netdev);
8481
3044b8d1
BL		 8482 if (state == pci_channel_io_perm_failure)
8483 return PCI_ERS_RESULT_DISCONNECT;
8484
9a799d71
AK		 8485 if (netif_running(netdev))
8486 ixgbe_down(adapter);
8487 pci_disable_device(pdev);
8488
b4617240 8489 /* Request a slot reset. */
9a799d71
AK		 8490 return PCI_ERS_RESULT_NEED_RESET;
8491}
8492
8493/**
8494 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8495 * @pdev: Pointer to PCI device
8496 *
8497 * Restart the card from scratch, as if from a cold-boot.
8498 */
8499static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8500{
c60fbb00 8501 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8502 pci_ers_result_t result;
8503 int err;
9a799d71 8504
9ce77666 8505 if (pci_enable_device_mem(pdev)) {
396e799c 8506 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8507 result = PCI_ERS_RESULT_DISCONNECT;
8508 } else {
0391bbe3 8509 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8510 pci_set_master(pdev);
8511 pci_restore_state(pdev);
c0e1f68b 8512 pci_save_state(pdev);
9a799d71 8513
dd4d8ca6 8514 pci_wake_from_d3(pdev, false);
9a799d71 8515
6fabd715 8516 ixgbe_reset(adapter);
88512539 8517 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8518 result = PCI_ERS_RESULT_RECOVERED;
8519 }
8520
8521 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8522 if (err) {
849c4542
ET		 8523 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8524 "failed 0x%0x\n", err);
6fabd715
PWJ		 8525 /* non-fatal, continue */
8526 }
9a799d71 8527
6fabd715 8528 return result;
9a799d71
AK		 8529}
8530
8531/**
8532 * ixgbe_io_resume - called when traffic can start flowing again.
8533 * @pdev: Pointer to PCI device
8534 *
8535 * This callback is called when the error recovery driver tells us that
8536 * its OK to resume normal operation.
8537 */
8538static void ixgbe_io_resume(struct pci_dev *pdev)
8539{
c60fbb00
AD		 8540 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8541 struct net_device *netdev = adapter->netdev;
9a799d71 8542
83c61fa9
GR		 8543#ifdef CONFIG_PCI_IOV
8544 if (adapter->vferr_refcount) {
8545 e_info(drv, "Resuming after VF err\n");
8546 adapter->vferr_refcount--;
8547 return;
8548 }
8549
8550#endif
c7ccde0f
AD		 8551 if (netif_running(netdev))
8552 ixgbe_up(adapter);
9a799d71
AK		 8553
8554 netif_device_attach(netdev);
9a799d71
AK		 8555}
8556
3646f0e5 8557static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8558 .error_detected = ixgbe_io_error_detected,
8559 .slot_reset = ixgbe_io_slot_reset,
8560 .resume = ixgbe_io_resume,
8561};
8562
8563static struct pci_driver ixgbe_driver = {
8564 .name = ixgbe_driver_name,
8565 .id_table = ixgbe_pci_tbl,
8566 .probe = ixgbe_probe,
9f9a12f8 8567 .remove = ixgbe_remove,
9a799d71
AK		 8568#ifdef CONFIG_PM
8569 .suspend = ixgbe_suspend,
8570 .resume = ixgbe_resume,
8571#endif
8572 .shutdown = ixgbe_shutdown,
da36b647 8573 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8574 .err_handler = &ixgbe_err_handler
8575};
8576
8577/**
8578 * ixgbe_init_module - Driver Registration Routine
8579 *
8580 * ixgbe_init_module is the first routine called when the driver is
8581 * loaded. All it does is register with the PCI subsystem.
8582 **/
8583static int __init ixgbe_init_module(void)
8584{
8585 int ret;
c7689578 8586 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8587 pr_info("%s\n", ixgbe_copyright);
9a799d71 8588
00949167 8589 ixgbe_dbg_init();
00949167 8590
f01fc1a8
JK		 8591 ret = pci_register_driver(&ixgbe_driver);
8592 if (ret) {
f01fc1a8 8593 ixgbe_dbg_exit();
f01fc1a8
JK		 8594 return ret;
8595 }
8596
5dd2d332 8597#ifdef CONFIG_IXGBE_DCA
bd0362dd 8598 dca_register_notify(&dca_notifier);
bd0362dd 8599#endif
5dd2d332 8600
f01fc1a8 8601 return 0;
9a799d71 8602}
b4617240 8603
9a799d71
AK		 8604module_init(ixgbe_init_module);
8605
8606/**
8607 * ixgbe_exit_module - Driver Exit Cleanup Routine
8608 *
8609 * ixgbe_exit_module is called just before the driver is removed
8610 * from memory.
8611 **/
8612static void __exit ixgbe_exit_module(void)
8613{
5dd2d332 8614#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8615 dca_unregister_notify(&dca_notifier);
8616#endif
9a799d71 8617 pci_unregister_driver(&ixgbe_driver);
00949167 8618
00949167 8619 ixgbe_dbg_exit();
00949167 8620
1a51502b 8621 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8622}
bd0362dd 8623
5dd2d332 8624#ifdef CONFIG_IXGBE_DCA
bd0362dd 8625static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8626 void *p)
bd0362dd
JC		 8627{
8628 int ret_val;
8629
8630 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8631 __ixgbe_notify_dca);
bd0362dd
JC		 8632
8633 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8634}
b453368d 8635
5dd2d332 8636#endif /* CONFIG_IXGBE_DCA */
849c4542 8637
9a799d71
AK		 8638module_exit(ixgbe_exit_module);
8639
8640/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)