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ixgbe: Address issues with Tx WHTRESH value not being set correctly
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
8ef78adc
PWJ		 134static unsigned int allow_unsupported_sfp;
135module_param(allow_unsupported_sfp, uint, 0);
136MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
7086400d
AD		 146static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
147{
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
151}
152
153static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
154{
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
156
52f33af8 157 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
160}
161
dcd79aeb
TI		 162struct ixgbe_reg_info {
163 u32 ofs;
164 char *name;
165};
166
167static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
168
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
173
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
176
177 /* RX Registers */
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
186
187 /* TX Registers */
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
194
195 /* List Terminator */
196 {}
197};
198
199
200/*
201 * ixgbe_regdump - register printout routine
202 */
203static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
204{
205 int i = 0, j = 0;
206 char rname[16];
207 u32 regs[64];
208
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
213 break;
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
217 break;
218 case IXGBE_RDLEN(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
221 break;
222 case IXGBE_RDH(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
225 break;
226 case IXGBE_RDT(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
229 break;
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
233 break;
234 case IXGBE_RDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
237 break;
238 case IXGBE_RDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
241 break;
242 case IXGBE_TDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
245 break;
246 case IXGBE_TDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
249 break;
250 case IXGBE_TDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
253 break;
254 case IXGBE_TDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
257 break;
258 case IXGBE_TDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
261 break;
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
265 break;
266 default:
c7689578 267 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 268 IXGBE_READ_REG(hw, reginfo->ofs));
269 return;
270 }
271
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 274 pr_err("%-15s", rname);
dcd79aeb 275 for (j = 0; j < 8; j++)
c7689578
JP		 276 pr_cont(" %08x", regs[i*8+j]);
277 pr_cont("\n");
dcd79aeb
TI		 278 }
279
280}
281
282/*
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
284 */
285static void ixgbe_dump(struct ixgbe_adapter *adapter)
286{
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
290 int n = 0;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
298 u32 staterr;
299 int i = 0;
300
301 if (!netif_msg_hw(adapter))
302 return;
303
304 /* Print netdevice Info */
305 if (netdev) {
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 307 pr_info("Device Name state "
dcd79aeb 308 "trans_start last_rx\n");
c7689578
JP		 309 pr_info("%-15s %016lX %016lX %016lX\n",
310 netdev->name,
311 netdev->state,
312 netdev->trans_start,
313 netdev->last_rx);
dcd79aeb
TI		 314 }
315
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 318 pr_info(" Register Name Value\n");
dcd79aeb
TI		 319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
322 }
323
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
326 goto exit;
327
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
332 tx_buffer_info =
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
340 }
341
342 /* Print TX Rings */
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
347
348 /* Transmit Descriptor Formats
349 *
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
357 */
358
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
c7689578
JP		 361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
367
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 369 tx_desc = IXGBE_TX_DESC(tx_ring, i);
dcd79aeb
TI		 370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
c7689578 372 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 373 " %04X %p %016llX %p", i,
dcd79aeb
TI		 374 le64_to_cpu(u0->a),
375 le64_to_cpu(u0->b),
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
c7689578 383 pr_cont(" NTC/U\n");
dcd79aeb 384 else if (i == tx_ring->next_to_use)
c7689578 385 pr_cont(" NTU\n");
dcd79aeb 386 else if (i == tx_ring->next_to_clean)
c7689578 387 pr_cont(" NTC\n");
dcd79aeb 388 else
c7689578 389 pr_cont("\n");
dcd79aeb
TI		 390
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
397 }
398 }
399
400 /* Print RX Rings Summary */
401rx_ring_summary:
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 403 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
c7689578
JP		 406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 408 }
409
410 /* Print RX Rings */
411 if (!netif_msg_rx_status(adapter))
412 goto exit;
413
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
415
416 /* Advanced Receive Descriptor (Read) Format
417 * 63 1 0
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
423 *
424 *
425 * Advanced Receive Descriptor (Write-Back) Format
426 *
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
c7689578 444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
447
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 450 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
c7689578 455 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 456 "%016llX ---------------- %p", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 rx_buffer_info->skb);
460 } else {
c7689578 461 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 462 "%016llX %016llX %p", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
467
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
472 rx_ring->rx_buf_len, true);
473
474 if (rx_ring->rx_buf_len
919e78a6 475 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 476 print_hex_dump(KERN_INFO, "",
477 DUMP_PREFIX_ADDRESS, 16, 1,
478 phys_to_virt(
479 rx_buffer_info->page_dma +
480 rx_buffer_info->page_offset
481 ),
482 PAGE_SIZE/2, true);
483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
e8e26350
PW		 520/*
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
d3d00239
AD		 592static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
d3d00239
AD		 595 if (tx_buffer->dma) {
596 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
597 dma_unmap_page(ring->dev,
598 tx_buffer->dma,
599 tx_buffer->length,
600 DMA_TO_DEVICE);
e5a43549 601 else
d3d00239
AD		 602 dma_unmap_single(ring->dev,
603 tx_buffer->dma,
604 tx_buffer->length,
605 DMA_TO_DEVICE);
e5a43549 606 }
d3d00239
AD		 607 tx_buffer->dma = 0;
608}
609
610void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
611 struct ixgbe_tx_buffer *tx_buffer_info)
612{
613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
614 if (tx_buffer_info->skb)
9a799d71 615 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 616 tx_buffer_info->skb = NULL;
9a799d71
AK		 617 /* tx_buffer_info must be completely set up in the transmit path */
618}
619
c84d324c
JF		 620static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
621{
622 struct ixgbe_hw *hw = &adapter->hw;
623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
624 u32 data = 0;
625 u32 xoff[8] = {0};
626 int i;
627
628 if ((hw->fc.current_mode == ixgbe_fc_full) ||
629 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
630 switch (hw->mac.type) {
631 case ixgbe_mac_82598EB:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 633 break;
634 default:
c84d324c
JF		 635 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
636 }
637 hwstats->lxoffrxc += data;
638
639 /* refill credits (no tx hang) if we received xoff */
640 if (!data)
641 return;
642
643 for (i = 0; i < adapter->num_tx_queues; i++)
644 clear_bit(__IXGBE_HANG_CHECK_ARMED,
645 &adapter->tx_ring[i]->state);
646 return;
647 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
648 return;
649
650 /* update stats for each tc, only valid with PFC enabled */
651 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
652 switch (hw->mac.type) {
653 case ixgbe_mac_82598EB:
654 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 655 break;
c84d324c
JF		 656 default:
657 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 658 }
c84d324c
JF		 659 hwstats->pxoffrxc[i] += xoff[i];
660 }
661
662 /* disarm tx queues that have received xoff frames */
663 for (i = 0; i < adapter->num_tx_queues; i++) {
664 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 665 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 666
667 if (xoff[tc])
668 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 669 }
26f23d82
YZ		 670}
671
c84d324c 672static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 673{
c84d324c
JF		 674 return ring->tx_stats.completed;
675}
676
677static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
678{
679 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 680 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 681
c84d324c
JF		 682 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
683 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
684
685 if (head != tail)
686 return (head < tail) ?
687 tail - head : (tail + ring->count - head);
688
689 return 0;
690}
691
692static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
693{
694 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
695 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
696 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
697 bool ret = false;
698
7d637bcc 699 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 700
701 /*
702 * Check for a hung queue, but be thorough. This verifies
703 * that a transmit has been completed since the previous
704 * check AND there is at least one packet pending. The
705 * ARMED bit is set to indicate a potential hang. The
706 * bit is cleared if a pause frame is received to remove
707 * false hang detection due to PFC or 802.3x frames. By
708 * requiring this to fail twice we avoid races with
709 * pfc clearing the ARMED bit and conditions where we
710 * run the check_tx_hang logic with a transmit completion
711 * pending but without time to complete it yet.
712 */
713 if ((tx_done_old == tx_done) && tx_pending) {
714 /* make sure it is true for two checks in a row */
715 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
716 &tx_ring->state);
717 } else {
718 /* update completed stats and continue */
719 tx_ring->tx_stats.tx_done_old = tx_done;
720 /* reset the countdown */
721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 722 }
723
c84d324c 724 return ret;
9a799d71
AK		 725}
726
c83c6cbd
AD		 727/**
728 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
729 * @adapter: driver private struct
730 **/
731static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
732{
733
734 /* Do the reset outside of interrupt context */
735 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
736 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
737 ixgbe_service_event_schedule(adapter);
738 }
739}
e01c31a5 740
9a799d71
AK		 741/**
742 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 743 * @q_vector: structure containing interrupt and ring information
e01c31a5 744 * @tx_ring: tx ring to clean
9a799d71 745 **/
fe49f04a 746static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 747 struct ixgbe_ring *tx_ring)
9a799d71 748{
fe49f04a 749 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 750 struct ixgbe_tx_buffer *tx_buffer;
751 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 752 unsigned int total_bytes = 0, total_packets = 0;
59224555 753 unsigned int budget = q_vector->tx.work_limit;
d3d00239 754 u16 i = tx_ring->next_to_clean;
9a799d71 755
d3d00239 756 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 757 tx_desc = IXGBE_TX_DESC(tx_ring, i);
12207e49 758
30065e63 759 for (; budget; budget--) {
d3d00239
AD		 760 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
761
762 /* if next_to_watch is not set then there is no work pending */
763 if (!eop_desc)
764 break;
765
7f83a9e6
AD		 766 /* prevent any other reads prior to eop_desc */
767 rmb();
768
d3d00239
AD		 769 /* if DD is not set pending work has not been completed */
770 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
771 break;
8ad494b0 772
d3d00239
AD		 773 /* count the packet as being completed */
774 tx_ring->tx_stats.completed++;
775
776 /* clear next_to_watch to prevent false hangs */
777 tx_buffer->next_to_watch = NULL;
8ad494b0 778
d3d00239
AD		 779 do {
780 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
d3d00239
AD		 781 if (likely(tx_desc == eop_desc)) {
782 eop_desc = NULL;
783 dev_kfree_skb_any(tx_buffer->skb);
784 tx_buffer->skb = NULL;
785
786 total_bytes += tx_buffer->bytecount;
787 total_packets += tx_buffer->gso_segs;
788 }
9a799d71 789
d3d00239
AD		 790 tx_buffer++;
791 tx_desc++;
8ad494b0 792 i++;
d3d00239 793 if (unlikely(i == tx_ring->count)) {
8ad494b0 794 i = 0;
e01c31a5 795
d3d00239 796 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 797 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 798 }
e01c31a5 799
d3d00239 800 } while (eop_desc);
12207e49
PWJ		 801 }
802
9a799d71 803 tx_ring->next_to_clean = i;
d3d00239 804 u64_stats_update_begin(&tx_ring->syncp);
b953799e 805 tx_ring->stats.bytes += total_bytes;
bd198058 806 tx_ring->stats.packets += total_packets;
d3d00239 807 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 808 q_vector->tx.total_bytes += total_bytes;
809 q_vector->tx.total_packets += total_packets;
b953799e 810
c84d324c
JF		 811 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
812 /* schedule immediate reset if we believe we hung */
813 struct ixgbe_hw *hw = &adapter->hw;
e4f74028 814 tx_desc = IXGBE_TX_DESC(tx_ring, i);
c84d324c
JF		 815 e_err(drv, "Detected Tx Unit Hang\n"
816 " Tx Queue <%d>\n"
817 " TDH, TDT <%x>, <%x>\n"
818 " next_to_use <%x>\n"
819 " next_to_clean <%x>\n"
820 "tx_buffer_info[next_to_clean]\n"
821 " time_stamp <%lx>\n"
822 " jiffies <%lx>\n",
823 tx_ring->queue_index,
824 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
825 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 826 tx_ring->next_to_use, i,
827 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 828
829 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
830
831 e_info(probe,
832 "tx hang %d detected on queue %d, resetting adapter\n",
833 adapter->tx_timeout_count + 1, tx_ring->queue_index);
834
b953799e 835 /* schedule immediate reset if we believe we hung */
c83c6cbd 836 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 837
838 /* the adapter is about to reset, no point in enabling stuff */
59224555 839 return true;
b953799e 840 }
9a799d71 841
b2d96e0a
AD		 842 netdev_tx_completed_queue(txring_txq(tx_ring),
843 total_packets, total_bytes);
844
e092be60 845#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 846 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 847 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 848 /* Make sure that anybody stopping the queue after this
849 * sees the new next_to_clean.
850 */
851 smp_mb();
fc77dc3c 852 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 853 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 854 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 855 ++tx_ring->tx_stats.restart_queue;
30eba97a 856 }
e092be60 857 }
9a799d71 858
59224555 859 return !!budget;
9a799d71
AK		 860}
861
5dd2d332 862#ifdef CONFIG_IXGBE_DCA
bd0362dd 863static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 864 struct ixgbe_ring *rx_ring,
865 int cpu)
bd0362dd 866{
33cf09c9 867 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 868 u32 rxctrl;
33cf09c9
AD		 869 u8 reg_idx = rx_ring->reg_idx;
870
871 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
872 switch (hw->mac.type) {
873 case ixgbe_mac_82598EB:
874 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 875 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 876 break;
877 case ixgbe_mac_82599EB:
b93a2226 878 case ixgbe_mac_X540:
33cf09c9 879 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 880 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 881 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
882 break;
883 default:
884 break;
bd0362dd 885 }
33cf09c9
AD		 886 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
887 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
888 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 889 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 890}
891
892static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 893 struct ixgbe_ring *tx_ring,
894 int cpu)
bd0362dd 895{
33cf09c9 896 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 897 u32 txctrl;
33cf09c9
AD		 898 u8 reg_idx = tx_ring->reg_idx;
899
900 switch (hw->mac.type) {
901 case ixgbe_mac_82598EB:
902 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
903 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 904 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 905 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 906 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
907 break;
908 case ixgbe_mac_82599EB:
b93a2226 909 case ixgbe_mac_X540:
33cf09c9
AD		 910 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
911 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 912 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 913 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
914 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 915 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
916 break;
917 default:
918 break;
919 }
920}
921
922static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
923{
924 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 925 struct ixgbe_ring *ring;
bd0362dd 926 int cpu = get_cpu();
bd0362dd 927
33cf09c9
AD		 928 if (q_vector->cpu == cpu)
929 goto out_no_update;
930
efe3d3c8
AD		 931 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
932 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 933
efe3d3c8
AD		 934 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
935 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 936
937 q_vector->cpu = cpu;
938out_no_update:
bd0362dd
JC		 939 put_cpu();
940}
941
942static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
943{
33cf09c9 944 int num_q_vectors;
bd0362dd
JC		 945 int i;
946
947 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
948 return;
949
e35ec126
AD		 950 /* always use CB2 mode, difference is masked in the CB driver */
951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
952
33cf09c9
AD		 953 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
954 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
955 else
956 num_q_vectors = 1;
957
958 for (i = 0; i < num_q_vectors; i++) {
959 adapter->q_vector[i]->cpu = -1;
960 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 961 }
962}
963
964static int __ixgbe_notify_dca(struct device *dev, void *data)
965{
c60fbb00 966 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 967 unsigned long event = *(unsigned long *)data;
968
2a72c31e 969 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 970 return 0;
971
bd0362dd
JC		 972 switch (event) {
973 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 974 /* if we're already enabled, don't do it again */
975 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
976 break;
652f093f 977 if (dca_add_requester(dev) == 0) {
96b0e0f6 978 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 979 ixgbe_setup_dca(adapter);
980 break;
981 }
982 /* Fall Through since DCA is disabled. */
983 case DCA_PROVIDER_REMOVE:
984 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
985 dca_remove_requester(dev);
986 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
987 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
988 }
989 break;
990 }
991
652f093f 992 return 0;
bd0362dd 993}
5dd2d332 994#endif /* CONFIG_IXGBE_DCA */
67a74ee2 995
8a0da21b
AD		 996static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
997 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 998 struct sk_buff *skb)
999{
8a0da21b
AD		 1000 if (ring->netdev->features & NETIF_F_RXHASH)
1001 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1002}
1003
ff886dfc
AD		 1004/**
1005 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1006 * @adapter: address of board private structure
1007 * @rx_desc: advanced rx descriptor
1008 *
1009 * Returns : true if it is FCoE pkt
1010 */
1011static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1012 union ixgbe_adv_rx_desc *rx_desc)
1013{
1014 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1015
1016 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1017 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1018 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1019 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1020}
1021
e59bd25d
AV		 1022/**
1023 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1024 * @ring: structure containing ring specific data
1025 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1026 * @skb: skb currently being received and modified
1027 **/
8a0da21b 1028static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1029 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1030 struct sk_buff *skb)
9a799d71 1031{
8a0da21b 1032 skb_checksum_none_assert(skb);
9a799d71 1033
712744be 1034 /* Rx csum disabled */
8a0da21b 1035 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1036 return;
e59bd25d
AV		 1037
1038 /* if IP and error */
f56e0cb1
AD		 1039 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1040 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1041 ring->rx_stats.csum_err++;
9a799d71
AK		 1042 return;
1043 }
e59bd25d 1044
f56e0cb1 1045 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1046 return;
1047
f56e0cb1 1048 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1049 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1050
1051 /*
1052 * 82599 errata, UDP frames with a 0 checksum can be marked as
1053 * checksum errors.
1054 */
8a0da21b
AD		 1055 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1056 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1057 return;
1058
8a0da21b 1059 ring->rx_stats.csum_err++;
e59bd25d
AV		 1060 return;
1061 }
1062
9a799d71 1063 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1064 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1065}
1066
84ea2591 1067static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1068{
f56e0cb1 1069 rx_ring->next_to_use = val;
e8e26350
PW		 1070 /*
1071 * Force memory writes to complete before letting h/w
1072 * know there are new descriptors to fetch. (Only
1073 * applicable for weak-ordered memory model archs,
1074 * such as IA-64).
1075 */
1076 wmb();
84ea2591 1077 writel(val, rx_ring->tail);
e8e26350
PW		 1078}
1079
f990b79b
AD		 1080static bool ixgbe_alloc_mapped_skb(struct ixgbe_ring *rx_ring,
1081 struct ixgbe_rx_buffer *bi)
1082{
1083 struct sk_buff *skb = bi->skb;
1084 dma_addr_t dma = bi->dma;
1085
1086 if (dma)
1087 return true;
1088
1089 if (likely(!skb)) {
1090 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1091 rx_ring->rx_buf_len);
1092 bi->skb = skb;
1093 if (!skb) {
1094 rx_ring->rx_stats.alloc_rx_buff_failed++;
1095 return false;
1096 }
f990b79b
AD		 1097 }
1098
1099 dma = dma_map_single(rx_ring->dev, skb->data,
1100 rx_ring->rx_buf_len, DMA_FROM_DEVICE);
1101
1102 if (dma_mapping_error(rx_ring->dev, dma)) {
1103 rx_ring->rx_stats.alloc_rx_buff_failed++;
1104 return false;
1105 }
1106
1107 bi->dma = dma;
1108 return true;
1109}
1110
1111static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1112 struct ixgbe_rx_buffer *bi)
1113{
1114 struct page *page = bi->page;
1115 dma_addr_t page_dma = bi->page_dma;
1116 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
1117
1118 if (page_dma)
1119 return true;
1120
1121 if (!page) {
1122 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
1123 bi->page = page;
1124 if (unlikely(!page)) {
1125 rx_ring->rx_stats.alloc_rx_page_failed++;
1126 return false;
1127 }
1128 }
1129
1130 page_dma = dma_map_page(rx_ring->dev, page,
1131 page_offset, PAGE_SIZE / 2,
1132 DMA_FROM_DEVICE);
1133
1134 if (dma_mapping_error(rx_ring->dev, page_dma)) {
1135 rx_ring->rx_stats.alloc_rx_page_failed++;
1136 return false;
1137 }
1138
1139 bi->page_dma = page_dma;
1140 bi->page_offset = page_offset;
1141 return true;
1142}
1143
9a799d71 1144/**
f990b79b 1145 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1146 * @rx_ring: ring to place buffers on
1147 * @cleaned_count: number of buffers to replace
9a799d71 1148 **/
fc77dc3c 1149void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1150{
9a799d71 1151 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1152 struct ixgbe_rx_buffer *bi;
d5f398ed 1153 u16 i = rx_ring->next_to_use;
9a799d71 1154
f990b79b
AD		 1155 /* nothing to do or no valid netdev defined */
1156 if (!cleaned_count || !rx_ring->netdev)
fc77dc3c
AD		 1157 return;
1158
e4f74028 1159 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1160 bi = &rx_ring->rx_buffer_info[i];
1161 i -= rx_ring->count;
9a799d71 1162
f990b79b
AD		 1163 while (cleaned_count--) {
1164 if (!ixgbe_alloc_mapped_skb(rx_ring, bi))
1165 break;
d5f398ed 1166
f990b79b
AD		 1167 /* Refresh the desc even if buffer_addrs didn't change
1168 * because each write-back erases this info. */
7d637bcc 1169 if (ring_is_ps_enabled(rx_ring)) {
f990b79b 1170 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
d5f398ed 1171
f990b79b
AD		 1172 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1173 break;
d5f398ed 1174
3a581073 1175 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
9a799d71 1176 } else {
3a581073 1177 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1178 }
1179
f990b79b
AD		 1180 rx_desc++;
1181 bi++;
9a799d71 1182 i++;
f990b79b 1183 if (unlikely(!i)) {
e4f74028 1184 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1185 bi = rx_ring->rx_buffer_info;
1186 i -= rx_ring->count;
1187 }
1188
1189 /* clear the hdr_addr for the next_to_use descriptor */
1190 rx_desc->read.hdr_addr = 0;
9a799d71 1191 }
7c6e0a43 1192
f990b79b
AD		 1193 i += rx_ring->count;
1194
f56e0cb1 1195 if (rx_ring->next_to_use != i)
84ea2591 1196 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1197}
1198
c267fc16 1199static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1200{
c267fc16
AD		 1201 /* HW will not DMA in data larger than the given buffer, even if it
1202 * parses the (NFS, of course) header to be larger. In that case, it
1203 * fills the header buffer and spills the rest into the page.
1204 */
1205 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1206 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1207 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1208 if (hlen > IXGBE_RX_HDR_SIZE)
1209 hlen = IXGBE_RX_HDR_SIZE;
1210 return hlen;
7c6e0a43
JB		 1211}
1212
f8212f97 1213/**
4c1975d7
AD		 1214 * ixgbe_merge_active_tail - merge active tail into lro skb
1215 * @tail: pointer to active tail in frag_list
f8212f97 1216 *
4c1975d7
AD		 1217 * This function merges the length and data of an active tail into the
1218 * skb containing the frag_list. It resets the tail's pointer to the head,
1219 * but it leaves the heads pointer to tail intact.
f8212f97 1220 **/
4c1975d7 1221static inline struct sk_buff *ixgbe_merge_active_tail(struct sk_buff *tail)
f8212f97 1222{
4c1975d7 1223 struct sk_buff *head = IXGBE_CB(tail)->head;
f8212f97 1224
4c1975d7
AD		 1225 if (!head)
1226 return tail;
1227
1228 head->len += tail->len;
1229 head->data_len += tail->len;
1230 head->truesize += tail->len;
1231
1232 IXGBE_CB(tail)->head = NULL;
1233
1234 return head;
1235}
1236
1237/**
1238 * ixgbe_add_active_tail - adds an active tail into the skb frag_list
1239 * @head: pointer to the start of the skb
1240 * @tail: pointer to active tail to add to frag_list
1241 *
1242 * This function adds an active tail to the end of the frag list. This tail
1243 * will still be receiving data so we cannot yet ad it's stats to the main
1244 * skb. That is done via ixgbe_merge_active_tail.
1245 **/
1246static inline void ixgbe_add_active_tail(struct sk_buff *head,
1247 struct sk_buff *tail)
1248{
1249 struct sk_buff *old_tail = IXGBE_CB(head)->tail;
1250
1251 if (old_tail) {
1252 ixgbe_merge_active_tail(old_tail);
1253 old_tail->next = tail;
1254 } else {
1255 skb_shinfo(head)->frag_list = tail;
f8212f97
AD		 1256 }
1257
4c1975d7
AD		 1258 IXGBE_CB(tail)->head = head;
1259 IXGBE_CB(head)->tail = tail;
1260}
1261
1262/**
1263 * ixgbe_close_active_frag_list - cleanup pointers on a frag_list skb
1264 * @head: pointer to head of an active frag list
1265 *
1266 * This function will clear the frag_tail_tracker pointer on an active
1267 * frag_list and returns true if the pointer was actually set
1268 **/
1269static inline bool ixgbe_close_active_frag_list(struct sk_buff *head)
1270{
1271 struct sk_buff *tail = IXGBE_CB(head)->tail;
1272
1273 if (!tail)
1274 return false;
1275
1276 ixgbe_merge_active_tail(tail);
1277
1278 IXGBE_CB(head)->tail = NULL;
aa80175a 1279
4c1975d7 1280 return true;
f8212f97
AD		 1281}
1282
1d2024f6
AD		 1283/**
1284 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1285 * @data: pointer to the start of the headers
1286 * @max_len: total length of section to find headers in
1287 *
1288 * This function is meant to determine the length of headers that will
1289 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1290 * motivation of doing this is to only perform one pull for IPv4 TCP
1291 * packets so that we can do basic things like calculating the gso_size
1292 * based on the average data per packet.
1293 **/
1294static unsigned int ixgbe_get_headlen(unsigned char *data,
1295 unsigned int max_len)
1296{
1297 union {
1298 unsigned char *network;
1299 /* l2 headers */
1300 struct ethhdr *eth;
1301 struct vlan_hdr *vlan;
1302 /* l3 headers */
1303 struct iphdr *ipv4;
1304 } hdr;
1305 __be16 protocol;
1306 u8 nexthdr = 0; /* default to not TCP */
1307 u8 hlen;
1308
1309 /* this should never happen, but better safe than sorry */
1310 if (max_len < ETH_HLEN)
1311 return max_len;
1312
1313 /* initialize network frame pointer */
1314 hdr.network = data;
1315
1316 /* set first protocol and move network header forward */
1317 protocol = hdr.eth->h_proto;
1318 hdr.network += ETH_HLEN;
1319
1320 /* handle any vlan tag if present */
1321 if (protocol == __constant_htons(ETH_P_8021Q)) {
1322 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1323 return max_len;
1324
1325 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1326 hdr.network += VLAN_HLEN;
1327 }
1328
1329 /* handle L3 protocols */
1330 if (protocol == __constant_htons(ETH_P_IP)) {
1331 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1332 return max_len;
1333
1334 /* access ihl as a u8 to avoid unaligned access on ia64 */
1335 hlen = (hdr.network[0] & 0x0F) << 2;
1336
1337 /* verify hlen meets minimum size requirements */
1338 if (hlen < sizeof(struct iphdr))
1339 return hdr.network - data;
1340
1341 /* record next protocol */
1342 nexthdr = hdr.ipv4->protocol;
1343 hdr.network += hlen;
1344#ifdef CONFIG_FCOE
1345 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1346 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1347 return max_len;
1348 hdr.network += FCOE_HEADER_LEN;
1349#endif
1350 } else {
1351 return hdr.network - data;
1352 }
1353
1354 /* finally sort out TCP */
1355 if (nexthdr == IPPROTO_TCP) {
1356 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1357 return max_len;
1358
1359 /* access doff as a u8 to avoid unaligned access on ia64 */
1360 hlen = (hdr.network[12] & 0xF0) >> 2;
1361
1362 /* verify hlen meets minimum size requirements */
1363 if (hlen < sizeof(struct tcphdr))
1364 return hdr.network - data;
1365
1366 hdr.network += hlen;
1367 }
1368
1369 /*
1370 * If everything has gone correctly hdr.network should be the
1371 * data section of the packet and will be the end of the header.
1372 * If not then it probably represents the end of the last recognized
1373 * header.
1374 */
1375 if ((hdr.network - data) < max_len)
1376 return hdr.network - data;
1377 else
1378 return max_len;
1379}
1380
4c1975d7
AD		 1381static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1382 union ixgbe_adv_rx_desc *rx_desc,
1383 struct sk_buff *skb)
aa80175a 1384{
4c1975d7
AD		 1385 __le32 rsc_enabled;
1386 u32 rsc_cnt;
1387
1388 if (!ring_is_rsc_enabled(rx_ring))
1389 return;
1390
1391 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1392 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1393
1394 /* If this is an RSC frame rsc_cnt should be non-zero */
1395 if (!rsc_enabled)
1396 return;
1397
1398 rsc_cnt = le32_to_cpu(rsc_enabled);
1399 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1400
1401 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1402}
43634e82 1403
1d2024f6
AD		 1404static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1405 struct sk_buff *skb)
1406{
1407 u16 hdr_len = ixgbe_get_headlen(skb->data, skb_headlen(skb));
1408
1409 /* set gso_size to avoid messing up TCP MSS */
1410 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1411 IXGBE_CB(skb)->append_cnt);
1412}
1413
1414static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1415 struct sk_buff *skb)
1416{
1417 /* if append_cnt is 0 then frame is not RSC */
1418 if (!IXGBE_CB(skb)->append_cnt)
1419 return;
1420
1421 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1422 rx_ring->rx_stats.rsc_flush++;
1423
1424 ixgbe_set_rsc_gso_size(rx_ring, skb);
1425
1426 /* gso_size is computed using append_cnt so always clear it last */
1427 IXGBE_CB(skb)->append_cnt = 0;
1428}
1429
8a0da21b
AD		 1430/**
1431 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1432 * @rx_ring: rx descriptor ring packet is being transacted on
1433 * @rx_desc: pointer to the EOP Rx descriptor
1434 * @skb: pointer to current skb being populated
f8212f97 1435 *
8a0da21b
AD		 1436 * This function checks the ring, descriptor, and packet information in
1437 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1438 * other fields within the skb.
f8212f97 1439 **/
8a0da21b
AD		 1440static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1441 union ixgbe_adv_rx_desc *rx_desc,
1442 struct sk_buff *skb)
f8212f97 1443{
8a0da21b
AD		 1444 ixgbe_update_rsc_stats(rx_ring, skb);
1445
1446 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1447
8a0da21b
AD		 1448 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1449
1450 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1451 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1452 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1453 }
1454
8a0da21b 1455 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1456
8a0da21b 1457 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
f8212f97
AD		 1458}
1459
8a0da21b
AD		 1460static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1461 struct sk_buff *skb)
aa80175a 1462{
8a0da21b
AD		 1463 struct ixgbe_adapter *adapter = q_vector->adapter;
1464
1465 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1466 napi_gro_receive(&q_vector->napi, skb);
1467 else
1468 netif_rx(skb);
aa80175a 1469}
43634e82 1470
4ff7fb12 1471static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1472 struct ixgbe_ring *rx_ring,
4ff7fb12 1473 int budget)
9a799d71 1474{
9a799d71 1475 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
4c1975d7 1476 struct ixgbe_rx_buffer *rx_buffer_info;
9a799d71 1477 struct sk_buff *skb;
d2f4fbe2 1478 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1479 const int current_node = numa_node_id();
3d8fd385 1480#ifdef IXGBE_FCOE
8a0da21b 1481 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1482 int ddp_bytes = 0;
1483#endif /* IXGBE_FCOE */
c267fc16
AD		 1484 u16 i;
1485 u16 cleaned_count = 0;
9a799d71
AK		 1486
1487 i = rx_ring->next_to_clean;
e4f74028 1488 rx_desc = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1489
f56e0cb1 1490 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
7c6e0a43 1491 u32 upper_len = 0;
9a799d71 1492
3c945e5b 1493 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1494
c267fc16
AD		 1495 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1496
9a799d71 1497 skb = rx_buffer_info->skb;
9a799d71 1498 rx_buffer_info->skb = NULL;
c267fc16 1499 prefetch(skb->data);
9a799d71 1500
b811ce91
JB		 1501 /* linear means we are building an skb from multiple pages */
1502 if (!skb_is_nonlinear(skb)) {
c267fc16 1503 u16 hlen;
c267fc16
AD		 1504 if (ring_is_ps_enabled(rx_ring)) {
1505 hlen = ixgbe_get_hlen(rx_desc);
1506 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1507 } else {
1508 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1509 }
1510
1511 skb_put(skb, hlen);
4c1975d7
AD		 1512
1513 /*
1514 * Delay unmapping of the first packet. It carries the
1515 * header information, HW may still access the header
1516 * after writeback. Only unmap it when EOP is reached
1517 */
1518 if (!IXGBE_CB(skb)->head) {
1519 IXGBE_CB(skb)->delay_unmap = true;
1520 IXGBE_CB(skb)->dma = rx_buffer_info->dma;
1521 } else {
1522 skb = ixgbe_merge_active_tail(skb);
1523 dma_unmap_single(rx_ring->dev,
1524 rx_buffer_info->dma,
1525 rx_ring->rx_buf_len,
1526 DMA_FROM_DEVICE);
1527 }
1528 rx_buffer_info->dma = 0;
c267fc16
AD		 1529 } else {
1530 /* assume packet split since header is unmapped */
1531 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1532 }
1533
1534 if (upper_len) {
b6ec895e
AD		 1535 dma_unmap_page(rx_ring->dev,
1536 rx_buffer_info->page_dma,
1537 PAGE_SIZE / 2,
1538 DMA_FROM_DEVICE);
9a799d71
AK		 1539 rx_buffer_info->page_dma = 0;
1540 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1541 rx_buffer_info->page,
1542 rx_buffer_info->page_offset,
1543 upper_len);
762f4c57 1544
c267fc16
AD		 1545 if ((page_count(rx_buffer_info->page) == 1) &&
1546 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1547 get_page(rx_buffer_info->page);
c267fc16
AD		 1548 else
1549 rx_buffer_info->page = NULL;
9a799d71
AK		 1550
1551 skb->len += upper_len;
1552 skb->data_len += upper_len;
98130646 1553 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1554 }
1555
4c1975d7
AD		 1556 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1557
9a799d71
AK		 1558 i++;
1559 if (i == rx_ring->count)
1560 i = 0;
9a799d71 1561
e4f74028 1562 next_rxd = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1563 prefetch(next_rxd);
9a799d71 1564 cleaned_count++;
f8212f97 1565
f56e0cb1 1566 if ((!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) {
4c1975d7
AD		 1567 struct ixgbe_rx_buffer *next_buffer;
1568 u32 nextp;
1569
1570 if (IXGBE_CB(skb)->append_cnt) {
f56e0cb1
AD		 1571 nextp = le32_to_cpu(
1572 rx_desc->wb.upper.status_error);
4c1975d7
AD		 1573 nextp >>= IXGBE_RXDADV_NEXTP_SHIFT;
1574 } else {
1575 nextp = i;
1576 }
1577
f8212f97 1578 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97 1579
7d637bcc 1580 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1581 rx_buffer_info->skb = next_buffer->skb;
1582 rx_buffer_info->dma = next_buffer->dma;
1583 next_buffer->skb = skb;
1584 next_buffer->dma = 0;
1585 } else {
4c1975d7
AD		 1586 struct sk_buff *next_skb = next_buffer->skb;
1587 ixgbe_add_active_tail(skb, next_skb);
1588 IXGBE_CB(next_skb)->head = skb;
f8212f97 1589 }
5b7da515 1590 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1591 goto next_desc;
1592 }
1593
4c1975d7
AD		 1594 dma_unmap_single(rx_ring->dev,
1595 IXGBE_CB(skb)->dma,
1596 rx_ring->rx_buf_len,
1597 DMA_FROM_DEVICE);
1598 IXGBE_CB(skb)->dma = 0;
1599 IXGBE_CB(skb)->delay_unmap = false;
c267fc16 1600
4c1975d7
AD		 1601 if (ixgbe_close_active_frag_list(skb) &&
1602 !IXGBE_CB(skb)->append_cnt) {
aa80175a 1603 /* if we got here without RSC the packet is invalid */
4c1975d7
AD		 1604 dev_kfree_skb_any(skb);
1605 goto next_desc;
c267fc16
AD		 1606 }
1607
1608 /* ERR_MASK will only have valid bits if EOP set */
f56e0cb1
AD		 1609 if (unlikely(ixgbe_test_staterr(rx_desc,
1610 IXGBE_RXDADV_ERR_FRAME_ERR_MASK))) {
ff886dfc 1611 dev_kfree_skb_any(skb);
9a799d71
AK		 1612 goto next_desc;
1613 }
1614
d2f4fbe2
AV		 1615 /* probably a little skewed due to removing CRC */
1616 total_rx_bytes += skb->len;
1617 total_rx_packets++;
1618
8a0da21b
AD		 1619 /* populate checksum, timestamp, VLAN, and protocol */
1620 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1621
332d4a7d
YZ		 1622#ifdef IXGBE_FCOE
1623 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc 1624 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
f56e0cb1 1625 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1626 if (!ddp_bytes) {
1627 dev_kfree_skb_any(skb);
332d4a7d 1628 goto next_desc;
63d635b2 1629 }
3d8fd385 1630 }
332d4a7d 1631#endif /* IXGBE_FCOE */
8a0da21b 1632 ixgbe_rx_skb(q_vector, skb);
9a799d71 1633
4ff7fb12 1634 budget--;
9a799d71 1635next_desc:
4ff7fb12 1636 if (!budget)
c267fc16
AD		 1637 break;
1638
9a799d71
AK		 1639 /* return some buffers to hardware, one at a time is too slow */
1640 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1641 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1642 cleaned_count = 0;
1643 }
1644
1645 /* use prefetched values */
1646 rx_desc = next_rxd;
177db6ff
MC		 1647 }
1648
9a799d71 1649 rx_ring->next_to_clean = i;
7d4987de 1650 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1651
1652 if (cleaned_count)
fc77dc3c 1653 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1654
3d8fd385
YZ		 1655#ifdef IXGBE_FCOE
1656 /* include DDPed FCoE data */
1657 if (ddp_bytes > 0) {
1658 unsigned int mss;
1659
fc77dc3c 1660 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1661 sizeof(struct fc_frame_header) -
1662 sizeof(struct fcoe_crc_eof);
1663 if (mss > 512)
1664 mss &= ~511;
1665 total_rx_bytes += ddp_bytes;
1666 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1667 }
1668#endif /* IXGBE_FCOE */
1669
c267fc16
AD		 1670 u64_stats_update_begin(&rx_ring->syncp);
1671 rx_ring->stats.packets += total_rx_packets;
1672 rx_ring->stats.bytes += total_rx_bytes;
1673 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1674 q_vector->rx.total_packets += total_rx_packets;
1675 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1676
1677 return !!budget;
9a799d71
AK		 1678}
1679
9a799d71
AK		 1680/**
1681 * ixgbe_configure_msix - Configure MSI-X hardware
1682 * @adapter: board private structure
1683 *
1684 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1685 * interrupts.
1686 **/
1687static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1688{
021230d4 1689 struct ixgbe_q_vector *q_vector;
efe3d3c8 1690 int q_vectors, v_idx;
021230d4 1691 u32 mask;
9a799d71 1692
021230d4 1693 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1694
8e34d1aa
AD		 1695 /* Populate MSIX to EITR Select */
1696 if (adapter->num_vfs > 32) {
1697 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1698 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1699 }
1700
4df10466
JB		 1701 /*
1702 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1703 * corresponding register.
1704 */
1705 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1706 struct ixgbe_ring *ring;
7a921c93 1707 q_vector = adapter->q_vector[v_idx];
021230d4 1708
efe3d3c8
AD		 1709 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1710 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1711
1712 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1713 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1714
d5bf4f67
ET		 1715 if (q_vector->tx.ring && !q_vector->rx.ring) {
1716 /* tx only vector */
1717 if (adapter->tx_itr_setting == 1)
1718 q_vector->itr = IXGBE_10K_ITR;
1719 else
1720 q_vector->itr = adapter->tx_itr_setting;
1721 } else {
1722 /* rx or rx/tx vector */
1723 if (adapter->rx_itr_setting == 1)
1724 q_vector->itr = IXGBE_20K_ITR;
1725 else
1726 q_vector->itr = adapter->rx_itr_setting;
1727 }
021230d4 1728
fe49f04a 1729 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1730 }
1731
bd508178
AD		 1732 switch (adapter->hw.mac.type) {
1733 case ixgbe_mac_82598EB:
e8e26350 1734 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1735 v_idx);
bd508178
AD		 1736 break;
1737 case ixgbe_mac_82599EB:
b93a2226 1738 case ixgbe_mac_X540:
e8e26350 1739 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1740 break;
bd508178
AD		 1741 default:
1742 break;
1743 }
021230d4
AV		 1744 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1745
41fb9248 1746 /* set up to autoclear timer, and the vectors */
021230d4 1747 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1748 mask &= ~(IXGBE_EIMS_OTHER |
1749 IXGBE_EIMS_MAILBOX |
1750 IXGBE_EIMS_LSC);
1751
021230d4 1752 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1753}
1754
f494e8fa
AV		 1755enum latency_range {
1756 lowest_latency = 0,
1757 low_latency = 1,
1758 bulk_latency = 2,
1759 latency_invalid = 255
1760};
1761
1762/**
1763 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1764 * @q_vector: structure containing interrupt and ring information
1765 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1766 *
1767 * Stores a new ITR value based on packets and byte
1768 * counts during the last interrupt. The advantage of per interrupt
1769 * computation is faster updates and more accurate ITR for the current
1770 * traffic pattern. Constants in this function were computed
1771 * based on theoretical maximum wire speed and thresholds were set based
1772 * on testing data as well as attempting to minimize response time
1773 * while increasing bulk throughput.
1774 * this functionality is controlled by the InterruptThrottleRate module
1775 * parameter (see ixgbe_param.c)
1776 **/
bd198058
AD		 1777static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1778 struct ixgbe_ring_container *ring_container)
f494e8fa 1779{
f494e8fa 1780 u64 bytes_perint;
bd198058
AD		 1781 struct ixgbe_adapter *adapter = q_vector->adapter;
1782 int bytes = ring_container->total_bytes;
1783 int packets = ring_container->total_packets;
1784 u32 timepassed_us;
1785 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1786
1787 if (packets == 0)
bd198058 1788 return;
f494e8fa
AV		 1789
1790 /* simple throttlerate management
1791 * 0-20MB/s lowest (100000 ints/s)
1792 * 20-100MB/s low (20000 ints/s)
1793 * 100-1249MB/s bulk (8000 ints/s)
1794 */
1795 /* what was last interrupt timeslice? */
d5bf4f67 1796 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1797 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1798
1799 switch (itr_setting) {
1800 case lowest_latency:
1801 if (bytes_perint > adapter->eitr_low)
bd198058 1802 itr_setting = low_latency;
f494e8fa
AV		 1803 break;
1804 case low_latency:
1805 if (bytes_perint > adapter->eitr_high)
bd198058 1806 itr_setting = bulk_latency;
f494e8fa 1807 else if (bytes_perint <= adapter->eitr_low)
bd198058 1808 itr_setting = lowest_latency;
f494e8fa
AV		 1809 break;
1810 case bulk_latency:
1811 if (bytes_perint <= adapter->eitr_high)
bd198058 1812 itr_setting = low_latency;
f494e8fa
AV		 1813 break;
1814 }
1815
bd198058
AD		 1816 /* clear work counters since we have the values we need */
1817 ring_container->total_bytes = 0;
1818 ring_container->total_packets = 0;
1819
1820 /* write updated itr to ring container */
1821 ring_container->itr = itr_setting;
f494e8fa
AV		 1822}
1823
509ee935
JB		 1824/**
1825 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1826 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1827 *
1828 * This function is made to be called by ethtool and by the driver
1829 * when it needs to update EITR registers at runtime. Hardware
1830 * specific quirks/differences are taken care of here.
1831 */
fe49f04a 1832void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1833{
fe49f04a 1834 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1835 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1836 int v_idx = q_vector->v_idx;
d5bf4f67 1837 u32 itr_reg = q_vector->itr;
fe49f04a 1838
bd508178
AD		 1839 switch (adapter->hw.mac.type) {
1840 case ixgbe_mac_82598EB:
509ee935
JB		 1841 /* must write high and low 16 bits to reset counter */
1842 itr_reg |= (itr_reg << 16);
bd508178
AD		 1843 break;
1844 case ixgbe_mac_82599EB:
b93a2226 1845 case ixgbe_mac_X540:
509ee935
JB		 1846 /*
1847 * set the WDIS bit to not clear the timer bits and cause an
1848 * immediate assertion of the interrupt
1849 */
1850 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1851 break;
1852 default:
1853 break;
509ee935
JB		 1854 }
1855 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1856}
1857
bd198058 1858static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1859{
d5bf4f67 1860 u32 new_itr = q_vector->itr;
bd198058 1861 u8 current_itr;
f494e8fa 1862
bd198058
AD		 1863 ixgbe_update_itr(q_vector, &q_vector->tx);
1864 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1865
08c8833b 1866 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1867
1868 switch (current_itr) {
1869 /* counts and packets in update_itr are dependent on these numbers */
1870 case lowest_latency:
d5bf4f67 1871 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1872 break;
1873 case low_latency:
d5bf4f67 1874 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1875 break;
1876 case bulk_latency:
d5bf4f67 1877 new_itr = IXGBE_8K_ITR;
f494e8fa 1878 break;
bd198058
AD		 1879 default:
1880 break;
f494e8fa
AV		 1881 }
1882
d5bf4f67 1883 if (new_itr != q_vector->itr) {
fe49f04a 1884 /* do an exponential smoothing */
d5bf4f67
ET		 1885 new_itr = (10 * new_itr * q_vector->itr) /
1886 ((9 * new_itr) + q_vector->itr);
509ee935 1887
bd198058 1888 /* save the algorithm value here */
d5bf4f67 1889 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1890
1891 ixgbe_write_eitr(q_vector);
f494e8fa 1892 }
f494e8fa
AV		 1893}
1894
119fc60a 1895/**
f0f9778d
AD		 1896 * ixgbe_check_overtemp_subtask - check for over tempurature
1897 * @adapter: pointer to adapter
119fc60a 1898 **/
f0f9778d 1899static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1900{
119fc60a
MC		 1901 struct ixgbe_hw *hw = &adapter->hw;
1902 u32 eicr = adapter->interrupt_event;
1903
f0f9778d 1904 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1905 return;
1906
f0f9778d
AD		 1907 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1908 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1909 return;
1910
1911 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1912
7ca647bd 1913 switch (hw->device_id) {
f0f9778d
AD		 1914 case IXGBE_DEV_ID_82599_T3_LOM:
1915 /*
1916 * Since the warning interrupt is for both ports
1917 * we don't have to check if:
1918 * - This interrupt wasn't for our port.
1919 * - We may have missed the interrupt so always have to
1920 * check if we got a LSC
1921 */
1922 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1923 !(eicr & IXGBE_EICR_LSC))
1924 return;
1925
1926 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1927 u32 autoneg;
1928 bool link_up = false;
7ca647bd 1929
7ca647bd
JP		 1930 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1931
f0f9778d
AD		 1932 if (link_up)
1933 return;
1934 }
1935
1936 /* Check if this is not due to overtemp */
1937 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1938 return;
1939
1940 break;
7ca647bd
JP		 1941 default:
1942 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1943 return;
7ca647bd 1944 break;
119fc60a 1945 }
7ca647bd
JP		 1946 e_crit(drv,
1947 "Network adapter has been stopped because it has over heated. "
1948 "Restart the computer. If the problem persists, "
1949 "power off the system and replace the adapter\n");
f0f9778d
AD		 1950
1951 adapter->interrupt_event = 0;
119fc60a
MC		 1952}
1953
0befdb3e
JB		 1954static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1955{
1956 struct ixgbe_hw *hw = &adapter->hw;
1957
1958 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1959 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1960 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1961 /* write to clear the interrupt */
1962 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1963 }
1964}
cf8280ee 1965
4f51bf70
JK		 1966static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1967{
1968 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1969 return;
1970
1971 switch (adapter->hw.mac.type) {
1972 case ixgbe_mac_82599EB:
1973 /*
1974 * Need to check link state so complete overtemp check
1975 * on service task
1976 */
1977 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1978 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1979 adapter->interrupt_event = eicr;
1980 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1981 ixgbe_service_event_schedule(adapter);
1982 return;
1983 }
1984 return;
1985 case ixgbe_mac_X540:
1986 if (!(eicr & IXGBE_EICR_TS))
1987 return;
1988 break;
1989 default:
1990 return;
1991 }
1992
1993 e_crit(drv,
1994 "Network adapter has been stopped because it has over heated. "
1995 "Restart the computer. If the problem persists, "
1996 "power off the system and replace the adapter\n");
1997}
1998
e8e26350
PW		 1999static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2000{
2001 struct ixgbe_hw *hw = &adapter->hw;
2002
73c4b7cd
AD		 2003 if (eicr & IXGBE_EICR_GPI_SDP2) {
2004 /* Clear the interrupt */
2005 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2006 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2007 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2008 ixgbe_service_event_schedule(adapter);
2009 }
73c4b7cd
AD		 2010 }
2011
e8e26350
PW		 2012 if (eicr & IXGBE_EICR_GPI_SDP1) {
2013 /* Clear the interrupt */
2014 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2015 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2016 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2017 ixgbe_service_event_schedule(adapter);
2018 }
e8e26350
PW		 2019 }
2020}
2021
cf8280ee
JB		 2022static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2023{
2024 struct ixgbe_hw *hw = &adapter->hw;
2025
2026 adapter->lsc_int++;
2027 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2028 adapter->link_check_timeout = jiffies;
2029 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2030 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2031 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2032 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2033 }
2034}
2035
fe49f04a
AD		 2036static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2037 u64 qmask)
2038{
2039 u32 mask;
bd508178 2040 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2041
bd508178
AD		 2042 switch (hw->mac.type) {
2043 case ixgbe_mac_82598EB:
fe49f04a 2044 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2045 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2046 break;
2047 case ixgbe_mac_82599EB:
b93a2226 2048 case ixgbe_mac_X540:
fe49f04a 2049 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2050 if (mask)
2051 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2052 mask = (qmask >> 32);
bd508178
AD		 2053 if (mask)
2054 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2055 break;
2056 default:
2057 break;
fe49f04a
AD		 2058 }
2059 /* skip the flush */
2060}
2061
2062static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2063 u64 qmask)
fe49f04a
AD		 2064{
2065 u32 mask;
bd508178 2066 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2067
bd508178
AD		 2068 switch (hw->mac.type) {
2069 case ixgbe_mac_82598EB:
fe49f04a 2070 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2071 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2072 break;
2073 case ixgbe_mac_82599EB:
b93a2226 2074 case ixgbe_mac_X540:
fe49f04a 2075 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2076 if (mask)
2077 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2078 mask = (qmask >> 32);
bd508178
AD		 2079 if (mask)
2080 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2081 break;
2082 default:
2083 break;
fe49f04a
AD		 2084 }
2085 /* skip the flush */
2086}
2087
021230d4 2088/**
2c4af694
AD		 2089 * ixgbe_irq_enable - Enable default interrupt generation settings
2090 * @adapter: board private structure
021230d4 2091 **/
2c4af694
AD		 2092static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2093 bool flush)
9a799d71 2094{
2c4af694 2095 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2096
2c4af694
AD		 2097 /* don't reenable LSC while waiting for link */
2098 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2099 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2100
2c4af694 2101 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2102 switch (adapter->hw.mac.type) {
2103 case ixgbe_mac_82599EB:
2104 mask |= IXGBE_EIMS_GPI_SDP0;
2105 break;
2106 case ixgbe_mac_X540:
2107 mask |= IXGBE_EIMS_TS;
2108 break;
2109 default:
2110 break;
2111 }
2c4af694
AD		 2112 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2113 mask |= IXGBE_EIMS_GPI_SDP1;
2114 switch (adapter->hw.mac.type) {
2115 case ixgbe_mac_82599EB:
2c4af694
AD		 2116 mask |= IXGBE_EIMS_GPI_SDP1;
2117 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2118 case ixgbe_mac_X540:
2119 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2120 mask |= IXGBE_EIMS_MAILBOX;
2121 break;
2122 default:
2123 break;
9a799d71 2124 }
2c4af694
AD		 2125 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2126 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2127 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2128
2c4af694
AD		 2129 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2130 if (queues)
2131 ixgbe_irq_enable_queues(adapter, ~0);
2132 if (flush)
2133 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2134}
2135
2c4af694 2136static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2137{
a65151ba 2138 struct ixgbe_adapter *adapter = data;
9a799d71 2139 struct ixgbe_hw *hw = &adapter->hw;
54037505 2140 u32 eicr;
91281fd3 2141
54037505
DS		 2142 /*
2143 * Workaround for Silicon errata. Use clear-by-write instead
2144 * of clear-by-read. Reading with EICS will return the
2145 * interrupt causes without clearing, which later be done
2146 * with the write to EICR.
2147 */
2148 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2149 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2150
cf8280ee
JB		 2151 if (eicr & IXGBE_EICR_LSC)
2152 ixgbe_check_lsc(adapter);
f0848276 2153
1cdd1ec8
GR		 2154 if (eicr & IXGBE_EICR_MAILBOX)
2155 ixgbe_msg_task(adapter);
efe3d3c8 2156
bd508178
AD		 2157 switch (hw->mac.type) {
2158 case ixgbe_mac_82599EB:
b93a2226 2159 case ixgbe_mac_X540:
2c4af694
AD		 2160 if (eicr & IXGBE_EICR_ECC)
2161 e_info(link, "Received unrecoverable ECC Err, please "
2162 "reboot\n");
c4cf55e5
PWJ		 2163 /* Handle Flow Director Full threshold interrupt */
2164 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2165 int reinit_count = 0;
c4cf55e5 2166 int i;
c4cf55e5 2167 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2168 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2169 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2170 &ring->state))
2171 reinit_count++;
2172 }
2173 if (reinit_count) {
2174 /* no more flow director interrupts until after init */
2175 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2176 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2177 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2178 }
2179 }
f0f9778d 2180 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2181 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2182 break;
2183 default:
2184 break;
c4cf55e5 2185 }
f0848276 2186
bd508178 2187 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 2188
7086400d 2189 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2190 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2191 ixgbe_irq_enable(adapter, false, false);
f0848276 2192
9a799d71 2193 return IRQ_HANDLED;
f0848276 2194}
91281fd3 2195
4ff7fb12 2196static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2197{
021230d4 2198 struct ixgbe_q_vector *q_vector = data;
91281fd3 2199
9b471446 2200 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2201
4ff7fb12
AD		 2202 if (q_vector->rx.ring || q_vector->tx.ring)
2203 napi_schedule(&q_vector->napi);
91281fd3 2204
9a799d71 2205 return IRQ_HANDLED;
91281fd3
AD		 2206}
2207
021230d4 2208static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2209 int r_idx)
021230d4 2210{
7a921c93 2211 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2212 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2213
2274543f 2214 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2215 rx_ring->next = q_vector->rx.ring;
2216 q_vector->rx.ring = rx_ring;
2217 q_vector->rx.count++;
021230d4
AV		 2218}
2219
2220static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2221 int t_idx)
021230d4 2222{
7a921c93 2223 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2224 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2225
2274543f 2226 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2227 tx_ring->next = q_vector->tx.ring;
2228 q_vector->tx.ring = tx_ring;
2229 q_vector->tx.count++;
bd198058 2230 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2231}
2232
9a799d71 2233/**
021230d4
AV		 2234 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2235 * @adapter: board private structure to initialize
9a799d71 2236 *
021230d4
AV		 2237 * This function maps descriptor rings to the queue-specific vectors
2238 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2239 * one vector per ring/queue, but on a constrained vector budget, we
2240 * group the rings as "efficiently" as possible. You would add new
2241 * mapping configurations in here.
9a799d71 2242 **/
4cc6df29 2243static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2244{
4cc6df29
AD		 2245 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2246 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2247 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2248 int v_start = 0;
021230d4 2249
4cc6df29 2250 /* only one q_vector if MSI-X is disabled. */
021230d4 2251 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2252 q_vectors = 1;
d0759ebb 2253
021230d4 2254 /*
4cc6df29
AD		 2255 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2256 * group them so there are multiple queues per vector.
2257 *
2258 * Re-adjusting *qpv takes care of the remainder.
021230d4 2259 */
4cc6df29
AD		 2260 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2261 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2262 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2263 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2264 }
9a799d71 2265
021230d4 2266 /*
4cc6df29
AD		 2267 * If there are not enough q_vectors for each ring to have it's own
2268 * vector then we must pair up Rx/Tx on a each vector
021230d4 2269 */
4cc6df29
AD		 2270 if ((v_start + txr_remaining) > q_vectors)
2271 v_start = 0;
2272
2273 for (; v_start < q_vectors && txr_remaining; v_start++) {
2274 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2275 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2276 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2277 }
021230d4
AV		 2278}
2279
2280/**
2281 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2282 * @adapter: board private structure
2283 *
2284 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2285 * interrupts from the kernel.
2286 **/
2287static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2288{
2289 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2290 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2291 int vector, err;
e8e9f696 2292 int ri = 0, ti = 0;
021230d4 2293
021230d4 2294 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2295 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2296 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2297
4ff7fb12 2298 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2299 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2300 "%s-%s-%d", netdev->name, "TxRx", ri++);
2301 ti++;
2302 } else if (q_vector->rx.ring) {
9fe93afd 2303 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2304 "%s-%s-%d", netdev->name, "rx", ri++);
2305 } else if (q_vector->tx.ring) {
9fe93afd 2306 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2307 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2308 } else {
2309 /* skip this unused q_vector */
2310 continue;
32aa77a4 2311 }
207867f5
AD		 2312 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2313 q_vector->name, q_vector);
9a799d71 2314 if (err) {
396e799c 2315 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2316 "Error: %d\n", err);
021230d4 2317 goto free_queue_irqs;
9a799d71 2318 }
207867f5
AD		 2319 /* If Flow Director is enabled, set interrupt affinity */
2320 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2321 /* assign the mask for this irq */
2322 irq_set_affinity_hint(entry->vector,
2323 q_vector->affinity_mask);
2324 }
9a799d71
AK		 2325 }
2326
021230d4 2327 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2328 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2329 if (err) {
396e799c 2330 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2331 goto free_queue_irqs;
9a799d71
AK		 2332 }
2333
9a799d71
AK		 2334 return 0;
2335
021230d4 2336free_queue_irqs:
207867f5
AD		 2337 while (vector) {
2338 vector--;
2339 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2340 NULL);
2341 free_irq(adapter->msix_entries[vector].vector,
2342 adapter->q_vector[vector]);
2343 }
021230d4
AV		 2344 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2345 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2346 kfree(adapter->msix_entries);
2347 adapter->msix_entries = NULL;
9a799d71
AK		 2348 return err;
2349}
2350
2351/**
021230d4 2352 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2353 * @irq: interrupt number
2354 * @data: pointer to a network interface device structure
9a799d71
AK		 2355 **/
2356static irqreturn_t ixgbe_intr(int irq, void *data)
2357{
a65151ba 2358 struct ixgbe_adapter *adapter = data;
9a799d71 2359 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2360 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2361 u32 eicr;
2362
54037505 2363 /*
24ddd967 2364 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2365 * before the read of EICR.
2366 */
2367 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2368
021230d4 2369 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2370 * therefore no explicit interrupt disable is necessary */
021230d4 2371 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2372 if (!eicr) {
6af3b9eb
ET		 2373 /*
2374 * shared interrupt alert!
f47cf66e 2375 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2376 * have disabled interrupts due to EIAM
2377 * finish the workaround of silicon errata on 82598. Unmask
2378 * the interrupt that we masked before the EICR read.
2379 */
2380 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2381 ixgbe_irq_enable(adapter, true, true);
9a799d71 2382 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2383 }
9a799d71 2384
cf8280ee
JB		 2385 if (eicr & IXGBE_EICR_LSC)
2386 ixgbe_check_lsc(adapter);
021230d4 2387
bd508178
AD		 2388 switch (hw->mac.type) {
2389 case ixgbe_mac_82599EB:
e8e26350 2390 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2391 /* Fall through */
2392 case ixgbe_mac_X540:
2393 if (eicr & IXGBE_EICR_ECC)
2394 e_info(link, "Received unrecoverable ECC err, please "
2395 "reboot\n");
4f51bf70 2396 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2397 break;
2398 default:
2399 break;
2400 }
e8e26350 2401
0befdb3e
JB		 2402 ixgbe_check_fan_failure(adapter, eicr);
2403
7a921c93 2404 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2405 /* would disable interrupts here but EIAM disabled it */
7a921c93 2406 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2407 }
2408
6af3b9eb
ET		 2409 /*
2410 * re-enable link(maybe) and non-queue interrupts, no flush.
2411 * ixgbe_poll will re-enable the queue interrupts
2412 */
2413
2414 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2415 ixgbe_irq_enable(adapter, false, false);
2416
9a799d71
AK		 2417 return IRQ_HANDLED;
2418}
2419
021230d4
AV		 2420static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2421{
efe3d3c8
AD		 2422 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2423 int i;
2424
2425 /* legacy and MSI only use one vector */
2426 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2427 q_vectors = 1;
2428
2429 for (i = 0; i < adapter->num_rx_queues; i++) {
2430 adapter->rx_ring[i]->q_vector = NULL;
2431 adapter->rx_ring[i]->next = NULL;
2432 }
2433 for (i = 0; i < adapter->num_tx_queues; i++) {
2434 adapter->tx_ring[i]->q_vector = NULL;
2435 adapter->tx_ring[i]->next = NULL;
2436 }
021230d4
AV		 2437
2438 for (i = 0; i < q_vectors; i++) {
7a921c93 2439 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2440 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2441 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2442 }
2443}
2444
9a799d71
AK		 2445/**
2446 * ixgbe_request_irq - initialize interrupts
2447 * @adapter: board private structure
2448 *
2449 * Attempts to configure interrupts using the best available
2450 * capabilities of the hardware and kernel.
2451 **/
021230d4 2452static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2453{
2454 struct net_device *netdev = adapter->netdev;
021230d4 2455 int err;
9a799d71 2456
4cc6df29
AD		 2457 /* map all of the rings to the q_vectors */
2458 ixgbe_map_rings_to_vectors(adapter);
2459
2460 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2461 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2462 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2463 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2464 netdev->name, adapter);
4cc6df29 2465 else
a0607fd3 2466 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2467 netdev->name, adapter);
9a799d71 2468
4cc6df29 2469 if (err) {
396e799c 2470 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2471
4cc6df29
AD		 2472 /* place q_vectors and rings back into a known good state */
2473 ixgbe_reset_q_vectors(adapter);
2474 }
2475
9a799d71
AK		 2476 return err;
2477}
2478
2479static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2480{
9a799d71 2481 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2482 int i, q_vectors;
9a799d71 2483
021230d4 2484 q_vectors = adapter->num_msix_vectors;
021230d4 2485 i = q_vectors - 1;
a65151ba 2486 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2487 i--;
4cc6df29 2488
021230d4 2489 for (; i >= 0; i--) {
894ff7cf 2490 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2491 if (!adapter->q_vector[i]->rx.ring &&
2492 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2493 continue;
2494
207867f5
AD		 2495 /* clear the affinity_mask in the IRQ descriptor */
2496 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2497 NULL);
2498
021230d4 2499 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2500 adapter->q_vector[i]);
021230d4 2501 }
021230d4 2502 } else {
a65151ba 2503 free_irq(adapter->pdev->irq, adapter);
9a799d71 2504 }
207867f5
AD		 2505
2506 /* clear q_vector state information */
2507 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2508}
2509
22d5a71b
JB		 2510/**
2511 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2512 * @adapter: board private structure
2513 **/
2514static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2515{
bd508178
AD		 2516 switch (adapter->hw.mac.type) {
2517 case ixgbe_mac_82598EB:
835462fc 2518 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2519 break;
2520 case ixgbe_mac_82599EB:
b93a2226 2521 case ixgbe_mac_X540:
835462fc
NS		 2522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2525 break;
2526 default:
2527 break;
22d5a71b
JB		 2528 }
2529 IXGBE_WRITE_FLUSH(&adapter->hw);
2530 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2531 int i;
2532 for (i = 0; i < adapter->num_msix_vectors; i++)
2533 synchronize_irq(adapter->msix_entries[i].vector);
2534 } else {
2535 synchronize_irq(adapter->pdev->irq);
2536 }
2537}
2538
9a799d71
AK		 2539/**
2540 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2541 *
2542 **/
2543static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2544{
d5bf4f67 2545 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2546
d5bf4f67
ET		 2547 /* rx/tx vector */
2548 if (adapter->rx_itr_setting == 1)
2549 q_vector->itr = IXGBE_20K_ITR;
2550 else
2551 q_vector->itr = adapter->rx_itr_setting;
2552
2553 ixgbe_write_eitr(q_vector);
9a799d71 2554
e8e26350
PW		 2555 ixgbe_set_ivar(adapter, 0, 0, 0);
2556 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2557
396e799c 2558 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2559}
2560
43e69bf0
AD		 2561/**
2562 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2563 * @adapter: board private structure
2564 * @ring: structure containing ring specific data
2565 *
2566 * Configure the Tx descriptor ring after a reset.
2567 **/
84418e3b
AD		 2568void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2569 struct ixgbe_ring *ring)
43e69bf0
AD		 2570{
2571 struct ixgbe_hw *hw = &adapter->hw;
2572 u64 tdba = ring->dma;
2f1860b8 2573 int wait_loop = 10;
b88c6de2 2574 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2575 u8 reg_idx = ring->reg_idx;
43e69bf0 2576
2f1860b8 2577 /* disable queue to avoid issues while updating state */
b88c6de2 2578 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2579 IXGBE_WRITE_FLUSH(hw);
2580
43e69bf0 2581 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2582 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2583 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2584 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2585 ring->count * sizeof(union ixgbe_adv_tx_desc));
2586 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2587 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2588 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2589
b88c6de2
AD		 2590 /*
2591 * set WTHRESH to encourage burst writeback, it should not be set
2592 * higher than 1 when ITR is 0 as it could cause false TX hangs
2593 *
2594 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2595 * to or less than the number of on chip descriptors, which is
2596 * currently 40.
2597 */
e954b374 2598 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2599 txdctl |= (1 << 16); /* WTHRESH = 1 */
2600 else
2601 txdctl |= (8 << 16); /* WTHRESH = 8 */
2602
e954b374
AD		 2603 /*
2604 * Setting PTHRESH to 32 both improves performance
2605 * and avoids a TX hang with DFP enabled
2606 */
b88c6de2
AD		 2607 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2608 32; /* PTHRESH = 32 */
2f1860b8
AD		 2609
2610 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2611 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2612 adapter->atr_sample_rate) {
2613 ring->atr_sample_rate = adapter->atr_sample_rate;
2614 ring->atr_count = 0;
2615 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2616 } else {
2617 ring->atr_sample_rate = 0;
2618 }
2f1860b8 2619
c84d324c
JF		 2620 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2621
2f1860b8 2622 /* enable queue */
2f1860b8
AD		 2623 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2624
b2d96e0a
AD		 2625 netdev_tx_reset_queue(txring_txq(ring));
2626
2f1860b8
AD		 2627 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2628 if (hw->mac.type == ixgbe_mac_82598EB &&
2629 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2630 return;
2631
2632 /* poll to verify queue is enabled */
2633 do {
032b4325 2634 usleep_range(1000, 2000);
2f1860b8
AD		 2635 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2636 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2637 if (!wait_loop)
2638 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2639}
2640
120ff942
AD		 2641static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2642{
2643 struct ixgbe_hw *hw = &adapter->hw;
2644 u32 rttdcs;
72a32f1f 2645 u32 reg;
8b1c0b24 2646 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2647
2648 if (hw->mac.type == ixgbe_mac_82598EB)
2649 return;
2650
2651 /* disable the arbiter while setting MTQC */
2652 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2653 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2654 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2655
2656 /* set transmit pool layout */
8b1c0b24 2657 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2658 case (IXGBE_FLAG_SRIOV_ENABLED):
2659 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2660 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2661 break;
8b1c0b24
JF		 2662 default:
2663 if (!tcs)
2664 reg = IXGBE_MTQC_64Q_1PB;
2665 else if (tcs <= 4)
2666 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2667 else
2668 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2669
8b1c0b24 2670 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2671
8b1c0b24
JF		 2672 /* Enable Security TX Buffer IFG for multiple pb */
2673 if (tcs) {
2674 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2675 reg |= IXGBE_SECTX_DCB;
2676 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2677 }
120ff942
AD		 2678 break;
2679 }
2680
2681 /* re-enable the arbiter */
2682 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2683 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2684}
2685
9a799d71 2686/**
3a581073 2687 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2688 * @adapter: board private structure
2689 *
2690 * Configure the Tx unit of the MAC after a reset.
2691 **/
2692static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2693{
2f1860b8
AD		 2694 struct ixgbe_hw *hw = &adapter->hw;
2695 u32 dmatxctl;
43e69bf0 2696 u32 i;
9a799d71 2697
2f1860b8
AD		 2698 ixgbe_setup_mtqc(adapter);
2699
2700 if (hw->mac.type != ixgbe_mac_82598EB) {
2701 /* DMATXCTL.EN must be before Tx queues are enabled */
2702 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2703 dmatxctl |= IXGBE_DMATXCTL_TE;
2704 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2705 }
2706
9a799d71 2707 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2708 for (i = 0; i < adapter->num_tx_queues; i++)
2709 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2710}
2711
e8e26350 2712#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2713
a6616b42 2714static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2715 struct ixgbe_ring *rx_ring)
cc41ac7c 2716{
cc41ac7c 2717 u32 srrctl;
bf29ee6c 2718 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2719
bd508178
AD		 2720 switch (adapter->hw.mac.type) {
2721 case ixgbe_mac_82598EB: {
2722 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2723 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2724 reg_idx = reg_idx & mask;
cc41ac7c 2725 }
bd508178
AD		 2726 break;
2727 case ixgbe_mac_82599EB:
b93a2226 2728 case ixgbe_mac_X540:
bd508178
AD		 2729 default:
2730 break;
2731 }
2732
bf29ee6c 2733 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2734
2735 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2736 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2737 if (adapter->num_vfs)
2738 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2739
afafd5b0
AD		 2740 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2741 IXGBE_SRRCTL_BSIZEHDR_MASK;
2742
7d637bcc 2743 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2744#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2745 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2746#else
2747 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2748#endif
cc41ac7c 2749 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2750 } else {
afafd5b0
AD		 2751 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2752 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2753 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2754 }
e8e26350 2755
bf29ee6c 2756 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2757}
9a799d71 2758
05abb126 2759static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2760{
05abb126
AD		 2761 struct ixgbe_hw *hw = &adapter->hw;
2762 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2763 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2764 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2765 u32 mrqc = 0, reta = 0;
2766 u32 rxcsum;
2767 int i, j;
8b1c0b24 2768 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2769 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2770
2771 if (tcs)
2772 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2773
05abb126
AD		 2774 /* Fill out hash function seeds */
2775 for (i = 0; i < 10; i++)
2776 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2777
2778 /* Fill out redirection table */
2779 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2780 if (j == maxq)
05abb126
AD		 2781 j = 0;
2782 /* reta = 4-byte sliding window of
2783 * 0x00..(indices-1)(indices-1)00..etc. */
2784 reta = (reta << 8) | (j * 0x11);
2785 if ((i & 3) == 3)
2786 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2787 }
0cefafad 2788
05abb126
AD		 2789 /* Disable indicating checksum in descriptor, enables RSS hash */
2790 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2791 rxcsum |= IXGBE_RXCSUM_PCSD;
2792 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2793
8b1c0b24
JF		 2794 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2795 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2796 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2797 } else {
2798 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2799 | IXGBE_FLAG_SRIOV_ENABLED);
2800
2801 switch (mask) {
2802 case (IXGBE_FLAG_RSS_ENABLED):
2803 if (!tcs)
2804 mrqc = IXGBE_MRQC_RSSEN;
2805 else if (tcs <= 4)
2806 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2807 else
2808 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2809 break;
2810 case (IXGBE_FLAG_SRIOV_ENABLED):
2811 mrqc = IXGBE_MRQC_VMDQEN;
2812 break;
2813 default:
2814 break;
2815 }
0cefafad
JB		 2816 }
2817
05abb126
AD		 2818 /* Perform hash on these packet types */
2819 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2820 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2821 | IXGBE_MRQC_RSS_FIELD_IPV6
2822 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2823
2824 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2825}
2826
bb5a9ad2
NS		 2827/**
2828 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2829 * @adapter: address of board private structure
2830 * @index: index of ring to set
bb5a9ad2 2831 **/
082757af 2832static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2833 struct ixgbe_ring *ring)
bb5a9ad2 2834{
bb5a9ad2 2835 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2836 u32 rscctrl;
edd2ea55 2837 int rx_buf_len;
bf29ee6c 2838 u8 reg_idx = ring->reg_idx;
7367096a 2839
7d637bcc 2840 if (!ring_is_rsc_enabled(ring))
7367096a 2841 return;
bb5a9ad2 2842
7367096a
AD		 2843 rx_buf_len = ring->rx_buf_len;
2844 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2845 rscctrl |= IXGBE_RSCCTL_RSCEN;
2846 /*
2847 * we must limit the number of descriptors so that the
2848 * total size of max desc * buf_len is not greater
642c680e 2849 * than 65536
bb5a9ad2 2850 */
7d637bcc 2851 if (ring_is_ps_enabled(ring)) {
642c680e 2852#if (PAGE_SIZE < 8192)
bb5a9ad2 2853 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2854#elif (PAGE_SIZE < 16384)
bb5a9ad2 2855 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
642c680e 2856#elif (PAGE_SIZE < 32768)
bb5a9ad2
NS		 2857 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2858#else
2859 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2860#endif
2861 } else {
642c680e 2862 if (rx_buf_len <= IXGBE_RXBUFFER_4K)
bb5a9ad2 2863 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2864 else if (rx_buf_len <= IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2865 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2866 else
2867 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2868 }
7367096a 2869 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2870}
2871
9e10e045
AD		 2872/**
2873 * ixgbe_set_uta - Set unicast filter table address
2874 * @adapter: board private structure
2875 *
2876 * The unicast table address is a register array of 32-bit registers.
2877 * The table is meant to be used in a way similar to how the MTA is used
2878 * however due to certain limitations in the hardware it is necessary to
2879 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2880 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2881 **/
2882static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2883{
2884 struct ixgbe_hw *hw = &adapter->hw;
2885 int i;
2886
2887 /* The UTA table only exists on 82599 hardware and newer */
2888 if (hw->mac.type < ixgbe_mac_82599EB)
2889 return;
2890
2891 /* we only need to do this if VMDq is enabled */
2892 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2893 return;
2894
2895 for (i = 0; i < 128; i++)
2896 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2897}
2898
2899#define IXGBE_MAX_RX_DESC_POLL 10
2900static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2901 struct ixgbe_ring *ring)
2902{
2903 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2904 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2905 u32 rxdctl;
bf29ee6c 2906 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2907
2908 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2909 if (hw->mac.type == ixgbe_mac_82598EB &&
2910 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2911 return;
2912
2913 do {
032b4325 2914 usleep_range(1000, 2000);
9e10e045
AD		 2915 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2916 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2917
2918 if (!wait_loop) {
2919 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2920 "the polling period\n", reg_idx);
2921 }
2922}
2923
2d39d576
YZ		 2924void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2925 struct ixgbe_ring *ring)
2926{
2927 struct ixgbe_hw *hw = &adapter->hw;
2928 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2929 u32 rxdctl;
2930 u8 reg_idx = ring->reg_idx;
2931
2932 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2933 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2934
2935 /* write value back with RXDCTL.ENABLE bit cleared */
2936 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2937
2938 if (hw->mac.type == ixgbe_mac_82598EB &&
2939 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2940 return;
2941
2942 /* the hardware may take up to 100us to really disable the rx queue */
2943 do {
2944 udelay(10);
2945 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2946 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2947
2948 if (!wait_loop) {
2949 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2950 "the polling period\n", reg_idx);
2951 }
2952}
2953
84418e3b
AD		 2954void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2955 struct ixgbe_ring *ring)
acd37177
AD		 2956{
2957 struct ixgbe_hw *hw = &adapter->hw;
2958 u64 rdba = ring->dma;
9e10e045 2959 u32 rxdctl;
bf29ee6c 2960 u8 reg_idx = ring->reg_idx;
acd37177 2961
9e10e045
AD		 2962 /* disable queue to avoid issues while updating state */
2963 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2964 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2965
acd37177
AD		 2966 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2967 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2968 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2969 ring->count * sizeof(union ixgbe_adv_rx_desc));
2970 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2971 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2972 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2973
2974 ixgbe_configure_srrctl(adapter, ring);
2975 ixgbe_configure_rscctl(adapter, ring);
2976
e9f98072
GR		 2977 /* If operating in IOV mode set RLPML for X540 */
2978 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2979 hw->mac.type == ixgbe_mac_X540) {
2980 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2981 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2982 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2983 }
2984
9e10e045
AD		 2985 if (hw->mac.type == ixgbe_mac_82598EB) {
2986 /*
2987 * enable cache line friendly hardware writes:
2988 * PTHRESH=32 descriptors (half the internal cache),
2989 * this also removes ugly rx_no_buffer_count increment
2990 * HTHRESH=4 descriptors (to minimize latency on fetch)
2991 * WTHRESH=8 burst writeback up to two cache lines
2992 */
2993 rxdctl &= ~0x3FFFFF;
2994 rxdctl |= 0x080420;
2995 }
2996
2997 /* enable receive descriptor ring */
2998 rxdctl |= IXGBE_RXDCTL_ENABLE;
2999 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3000
3001 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3002 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3003}
3004
48654521
AD		 3005static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3006{
3007 struct ixgbe_hw *hw = &adapter->hw;
3008 int p;
3009
3010 /* PSRTYPE must be initialized in non 82598 adapters */
3011 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3012 IXGBE_PSRTYPE_UDPHDR |
3013 IXGBE_PSRTYPE_IPV4HDR |
48654521 3014 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3015 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3016
3017 if (hw->mac.type == ixgbe_mac_82598EB)
3018 return;
3019
3020 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3021 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3022
3023 for (p = 0; p < adapter->num_rx_pools; p++)
3024 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3025 psrtype);
3026}
3027
f5b4a52e
AD		 3028static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3029{
3030 struct ixgbe_hw *hw = &adapter->hw;
3031 u32 gcr_ext;
3032 u32 vt_reg_bits;
3033 u32 reg_offset, vf_shift;
3034 u32 vmdctl;
de4c7f65 3035 int i;
f5b4a52e
AD		 3036
3037 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3038 return;
3039
3040 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3041 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3042 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3043 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3044
3045 vf_shift = adapter->num_vfs % 32;
4cd6923d 3046 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 3047
3048 /* Enable only the PF's pool for Tx/Rx */
3049 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3050 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3051 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3052 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3053 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3054
3055 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3056 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3057
3058 /*
3059 * Set up VF register offsets for selected VT Mode,
3060 * i.e. 32 or 64 VFs for SR-IOV
3061 */
3062 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3063 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3064 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3065 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3066
3067 /* enable Tx loopback for VF/PF communication */
3068 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3069 /* Enable MAC Anti-Spoofing */
a1cbb15c 3070 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 3071 (adapter->num_vfs != 0),
a985b6c3 3072 adapter->num_vfs);
de4c7f65
GR		 3073 /* For VFs that have spoof checking turned off */
3074 for (i = 0; i < adapter->num_vfs; i++) {
3075 if (!adapter->vfinfo[i].spoofchk_enabled)
3076 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3077 }
f5b4a52e
AD		 3078}
3079
477de6ed 3080static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3081{
9a799d71
AK		 3082 struct ixgbe_hw *hw = &adapter->hw;
3083 struct net_device *netdev = adapter->netdev;
3084 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3085 int rx_buf_len;
477de6ed
AD		 3086 struct ixgbe_ring *rx_ring;
3087 int i;
3088 u32 mhadd, hlreg0;
48654521 3089
9a799d71 3090 /* Decide whether to use packet split mode or not */
a124339a
DS		 3091 /* On by default */
3092 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3093
1cdd1ec8 3094 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3095 if (adapter->num_vfs)
3096 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3097
3098 /* Disable packet split due to 82599 erratum #45 */
3099 if (hw->mac.type == ixgbe_mac_82599EB)
3100 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 3101
63f39bd1 3102#ifdef IXGBE_FCOE
477de6ed
AD		 3103 /* adjust max frame to be able to do baby jumbo for FCoE */
3104 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3105 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3106 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3107
477de6ed
AD		 3108#endif /* IXGBE_FCOE */
3109 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3110 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3111 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3112 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3113
3114 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3115 }
3116
919e78a6
AD		 3117 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3118 max_frame += VLAN_HLEN;
3119
3120 /* Set the RX buffer length according to the mode */
3121 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3122 rx_buf_len = IXGBE_RX_HDR_SIZE;
3123 } else {
3124 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3125 (netdev->mtu <= ETH_DATA_LEN))
3126 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3127 /*
3128 * Make best use of allocation by using all but 1K of a
3129 * power of 2 allocation that will be used for skb->head.
3130 */
3131 else if (max_frame <= IXGBE_RXBUFFER_3K)
3132 rx_buf_len = IXGBE_RXBUFFER_3K;
3133 else if (max_frame <= IXGBE_RXBUFFER_7K)
3134 rx_buf_len = IXGBE_RXBUFFER_7K;
3135 else if (max_frame <= IXGBE_RXBUFFER_15K)
3136 rx_buf_len = IXGBE_RXBUFFER_15K;
3137 else
3138 rx_buf_len = IXGBE_MAX_RXBUFFER;
3139 }
3140
477de6ed
AD		 3141 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3142 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3143 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3144 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3145
0cefafad
JB		 3146 /*
3147 * Setup the HW Rx Head and Tail Descriptor Pointers and
3148 * the Base and Length of the Rx Descriptor Ring
3149 */
9a799d71 3150 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3151 rx_ring = adapter->rx_ring[i];
a6616b42 3152 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3153
6e455b89 3154 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3155 set_ring_ps_enabled(rx_ring);
3156 else
3157 clear_ring_ps_enabled(rx_ring);
3158
3159 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3160 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3161 else
7d637bcc 3162 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3163
63f39bd1 3164#ifdef IXGBE_FCOE
e8e9f696 3165 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3166 struct ixgbe_ring_feature *f;
3167 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3168 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3169 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3170 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3171 rx_ring->rx_buf_len =
e8e9f696 3172 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3173 } else if (!ring_is_rsc_enabled(rx_ring) &&
3174 !ring_is_ps_enabled(rx_ring)) {
3175 rx_ring->rx_buf_len =
3176 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3177 }
63f39bd1 3178 }
63f39bd1 3179#endif /* IXGBE_FCOE */
477de6ed 3180 }
477de6ed
AD		 3181}
3182
7367096a
AD		 3183static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3184{
3185 struct ixgbe_hw *hw = &adapter->hw;
3186 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3187
3188 switch (hw->mac.type) {
3189 case ixgbe_mac_82598EB:
3190 /*
3191 * For VMDq support of different descriptor types or
3192 * buffer sizes through the use of multiple SRRCTL
3193 * registers, RDRXCTL.MVMEN must be set to 1
3194 *
3195 * also, the manual doesn't mention it clearly but DCA hints
3196 * will only use queue 0's tags unless this bit is set. Side
3197 * effects of setting this bit are only that SRRCTL must be
3198 * fully programmed [0..15]
3199 */
3200 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3201 break;
3202 case ixgbe_mac_82599EB:
b93a2226 3203 case ixgbe_mac_X540:
7367096a
AD		 3204 /* Disable RSC for ACK packets */
3205 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3206 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3207 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3208 /* hardware requires some bits to be set by default */
3209 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3210 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3211 break;
3212 default:
3213 /* We should do nothing since we don't know this hardware */
3214 return;
3215 }
3216
3217 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3218}
3219
477de6ed
AD		 3220/**
3221 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3222 * @adapter: board private structure
3223 *
3224 * Configure the Rx unit of the MAC after a reset.
3225 **/
3226static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3227{
3228 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3229 int i;
3230 u32 rxctrl;
477de6ed
AD		 3231
3232 /* disable receives while setting up the descriptors */
3233 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3234 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3235
3236 ixgbe_setup_psrtype(adapter);
7367096a 3237 ixgbe_setup_rdrxctl(adapter);
477de6ed 3238
9e10e045 3239 /* Program registers for the distribution of queues */
f5b4a52e 3240 ixgbe_setup_mrqc(adapter);
f5b4a52e 3241
9e10e045
AD		 3242 ixgbe_set_uta(adapter);
3243
477de6ed
AD		 3244 /* set_rx_buffer_len must be called before ring initialization */
3245 ixgbe_set_rx_buffer_len(adapter);
3246
3247 /*
3248 * Setup the HW Rx Head and Tail Descriptor Pointers and
3249 * the Base and Length of the Rx Descriptor Ring
3250 */
9e10e045
AD		 3251 for (i = 0; i < adapter->num_rx_queues; i++)
3252 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3253
9e10e045
AD		 3254 /* disable drop enable for 82598 parts */
3255 if (hw->mac.type == ixgbe_mac_82598EB)
3256 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3257
3258 /* enable all receives */
3259 rxctrl |= IXGBE_RXCTRL_RXEN;
3260 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3261}
3262
8e586137 3263static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3264{
3265 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3266 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3267 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3268
3269 /* add VID to filter table */
1ada1b1b 3270 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3271 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3272
3273 return 0;
068c89b0
DS		 3274}
3275
8e586137 3276static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3277{
3278 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3279 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3280 int pool_ndx = adapter->num_vfs;
068c89b0 3281
068c89b0 3282 /* remove VID from filter table */
1ada1b1b 3283 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3284 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3285
3286 return 0;
068c89b0
DS		 3287}
3288
5f6c0181
JB		 3289/**
3290 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3291 * @adapter: driver data
3292 */
3293static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3294{
3295 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3296 u32 vlnctrl;
3297
3298 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3299 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3300 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3301}
3302
3303/**
3304 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3305 * @adapter: driver data
3306 */
3307static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3308{
3309 struct ixgbe_hw *hw = &adapter->hw;
3310 u32 vlnctrl;
3311
3312 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3313 vlnctrl |= IXGBE_VLNCTRL_VFE;
3314 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3315 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3316}
3317
3318/**
3319 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3320 * @adapter: driver data
3321 */
3322static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3323{
3324 struct ixgbe_hw *hw = &adapter->hw;
3325 u32 vlnctrl;
5f6c0181
JB		 3326 int i, j;
3327
3328 switch (hw->mac.type) {
3329 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3330 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3331 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3332 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3333 break;
3334 case ixgbe_mac_82599EB:
b93a2226 3335 case ixgbe_mac_X540:
5f6c0181
JB		 3336 for (i = 0; i < adapter->num_rx_queues; i++) {
3337 j = adapter->rx_ring[i]->reg_idx;
3338 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3339 vlnctrl &= ~IXGBE_RXDCTL_VME;
3340 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3341 }
3342 break;
3343 default:
3344 break;
3345 }
3346}
3347
3348/**
f62bbb5e 3349 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3350 * @adapter: driver data
3351 */
f62bbb5e 3352static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3353{
3354 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3355 u32 vlnctrl;
5f6c0181
JB		 3356 int i, j;
3357
3358 switch (hw->mac.type) {
3359 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3360 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3361 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3362 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3363 break;
3364 case ixgbe_mac_82599EB:
b93a2226 3365 case ixgbe_mac_X540:
5f6c0181
JB		 3366 for (i = 0; i < adapter->num_rx_queues; i++) {
3367 j = adapter->rx_ring[i]->reg_idx;
3368 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3369 vlnctrl |= IXGBE_RXDCTL_VME;
3370 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3371 }
3372 break;
3373 default:
3374 break;
3375 }
3376}
3377
9a799d71
AK		 3378static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3379{
f62bbb5e 3380 u16 vid;
9a799d71 3381
f62bbb5e
JG		 3382 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3383
3384 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3385 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3386}
3387
2850062a
AD		 3388/**
3389 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3390 * @netdev: network interface device structure
3391 *
3392 * Writes unicast address list to the RAR table.
3393 * Returns: -ENOMEM on failure/insufficient address space
3394 * 0 on no addresses written
3395 * X on writing X addresses to the RAR table
3396 **/
3397static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3398{
3399 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3400 struct ixgbe_hw *hw = &adapter->hw;
3401 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3402 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3403 int count = 0;
3404
3405 /* return ENOMEM indicating insufficient memory for addresses */
3406 if (netdev_uc_count(netdev) > rar_entries)
3407 return -ENOMEM;
3408
3409 if (!netdev_uc_empty(netdev) && rar_entries) {
3410 struct netdev_hw_addr *ha;
3411 /* return error if we do not support writing to RAR table */
3412 if (!hw->mac.ops.set_rar)
3413 return -ENOMEM;
3414
3415 netdev_for_each_uc_addr(ha, netdev) {
3416 if (!rar_entries)
3417 break;
3418 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3419 vfn, IXGBE_RAH_AV);
3420 count++;
3421 }
3422 }
3423 /* write the addresses in reverse order to avoid write combining */
3424 for (; rar_entries > 0 ; rar_entries--)
3425 hw->mac.ops.clear_rar(hw, rar_entries);
3426
3427 return count;
3428}
3429
9a799d71 3430/**
2c5645cf 3431 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3432 * @netdev: network interface device structure
3433 *
2c5645cf
CL		 3434 * The set_rx_method entry point is called whenever the unicast/multicast
3435 * address list or the network interface flags are updated. This routine is
3436 * responsible for configuring the hardware for proper unicast, multicast and
3437 * promiscuous mode.
9a799d71 3438 **/
7f870475 3439void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3440{
3441 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3442 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3443 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3444 int count;
9a799d71
AK		 3445
3446 /* Check for Promiscuous and All Multicast modes */
3447
3448 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3449
f5dc442b
AD		 3450 /* set all bits that we expect to always be set */
3451 fctrl |= IXGBE_FCTRL_BAM;
3452 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3453 fctrl |= IXGBE_FCTRL_PMCF;
3454
2850062a
AD		 3455 /* clear the bits we are changing the status of */
3456 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3457
9a799d71 3458 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3459 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3460 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3461 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3462 /* don't hardware filter vlans in promisc mode */
3463 ixgbe_vlan_filter_disable(adapter);
9a799d71 3464 } else {
746b9f02
PM		 3465 if (netdev->flags & IFF_ALLMULTI) {
3466 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3467 vmolr |= IXGBE_VMOLR_MPE;
3468 } else {
3469 /*
3470 * Write addresses to the MTA, if the attempt fails
25985edc 3471 * then we should just turn on promiscuous mode so
2850062a
AD		 3472 * that we can at least receive multicast traffic
3473 */
3474 hw->mac.ops.update_mc_addr_list(hw, netdev);
3475 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3476 }
5f6c0181 3477 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3478 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3479 /*
3480 * Write addresses to available RAR registers, if there is not
3481 * sufficient space to store all the addresses then enable
25985edc 3482 * unicast promiscuous mode
2850062a
AD		 3483 */
3484 count = ixgbe_write_uc_addr_list(netdev);
3485 if (count < 0) {
3486 fctrl |= IXGBE_FCTRL_UPE;
3487 vmolr |= IXGBE_VMOLR_ROPE;
3488 }
9a799d71
AK		 3489 }
3490
2850062a 3491 if (adapter->num_vfs) {
1cdd1ec8 3492 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3493 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3494 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3495 IXGBE_VMOLR_ROPE);
3496 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3497 }
3498
3499 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3500
3501 if (netdev->features & NETIF_F_HW_VLAN_RX)
3502 ixgbe_vlan_strip_enable(adapter);
3503 else
3504 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3505}
3506
021230d4
AV		 3507static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3508{
3509 int q_idx;
3510 struct ixgbe_q_vector *q_vector;
3511 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3512
3513 /* legacy and MSI only use one vector */
3514 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3515 q_vectors = 1;
3516
3517 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3518 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3519 napi_enable(&q_vector->napi);
021230d4
AV		 3520 }
3521}
3522
3523static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3524{
3525 int q_idx;
3526 struct ixgbe_q_vector *q_vector;
3527 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3528
3529 /* legacy and MSI only use one vector */
3530 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3531 q_vectors = 1;
3532
3533 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3534 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3535 napi_disable(&q_vector->napi);
3536 }
3537}
3538
7a6b6f51 3539#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3540/*
3541 * ixgbe_configure_dcb - Configure DCB hardware
3542 * @adapter: ixgbe adapter struct
3543 *
3544 * This is called by the driver on open to configure the DCB hardware.
3545 * This is also called by the gennetlink interface when reconfiguring
3546 * the DCB state.
3547 */
3548static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3549{
3550 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3551 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3552
67ebd791
AD		 3553 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3554 if (hw->mac.type == ixgbe_mac_82598EB)
3555 netif_set_gso_max_size(adapter->netdev, 65536);
3556 return;
3557 }
3558
3559 if (hw->mac.type == ixgbe_mac_82598EB)
3560 netif_set_gso_max_size(adapter->netdev, 32768);
3561
2f90b865 3562
2f90b865 3563 /* Enable VLAN tag insert/strip */
f62bbb5e 3564 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3565
2f90b865 3566 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3567
971060b1 3568#ifdef IXGBE_FCOE
b120818e
JF		 3569 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3570 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3571#endif
b120818e
JF		 3572
3573 /* reconfigure the hardware */
3574 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3575 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3576 DCB_TX_CONFIG);
3577 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3578 DCB_RX_CONFIG);
3579 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3580 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3581 ixgbe_dcb_hw_ets(&adapter->hw,
3582 adapter->ixgbe_ieee_ets,
3583 max_frame);
3584 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3585 adapter->ixgbe_ieee_pfc->pfc_en,
3586 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3587 }
8187cd48
JF		 3588
3589 /* Enable RSS Hash per TC */
3590 if (hw->mac.type != ixgbe_mac_82598EB) {
3591 int i;
3592 u32 reg = 0;
3593
3594 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3595 u8 msb = 0;
3596 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3597
3598 while (cnt >>= 1)
3599 msb++;
3600
3601 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3602 }
3603 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3604 }
2f90b865 3605}
9da712d2
JF		 3606#endif
3607
3608/* Additional bittime to account for IXGBE framing */
3609#define IXGBE_ETH_FRAMING 20
3610
3611/*
3612 * ixgbe_hpbthresh - calculate high water mark for flow control
3613 *
3614 * @adapter: board private structure to calculate for
3615 * @pb - packet buffer to calculate
3616 */
3617static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3618{
3619 struct ixgbe_hw *hw = &adapter->hw;
3620 struct net_device *dev = adapter->netdev;
3621 int link, tc, kb, marker;
3622 u32 dv_id, rx_pba;
3623
3624 /* Calculate max LAN frame size */
3625 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3626
3627#ifdef IXGBE_FCOE
3628 /* FCoE traffic class uses FCOE jumbo frames */
3629 if (dev->features & NETIF_F_FCOE_MTU) {
3630 int fcoe_pb = 0;
2f90b865 3631
9da712d2
JF		 3632#ifdef CONFIG_IXGBE_DCB
3633 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3634
3635#endif
3636 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3637 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3638 }
2f90b865 3639#endif
80605c65 3640
9da712d2
JF		 3641 /* Calculate delay value for device */
3642 switch (hw->mac.type) {
3643 case ixgbe_mac_X540:
3644 dv_id = IXGBE_DV_X540(link, tc);
3645 break;
3646 default:
3647 dv_id = IXGBE_DV(link, tc);
3648 break;
3649 }
3650
3651 /* Loopback switch introduces additional latency */
3652 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3653 dv_id += IXGBE_B2BT(tc);
3654
3655 /* Delay value is calculated in bit times convert to KB */
3656 kb = IXGBE_BT2KB(dv_id);
3657 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3658
3659 marker = rx_pba - kb;
3660
3661 /* It is possible that the packet buffer is not large enough
3662 * to provide required headroom. In this case throw an error
3663 * to user and a do the best we can.
3664 */
3665 if (marker < 0) {
3666 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3667 "headroom to support flow control."
3668 "Decrease MTU or number of traffic classes\n", pb);
3669 marker = tc + 1;
3670 }
3671
3672 return marker;
3673}
3674
3675/*
3676 * ixgbe_lpbthresh - calculate low water mark for for flow control
3677 *
3678 * @adapter: board private structure to calculate for
3679 * @pb - packet buffer to calculate
3680 */
3681static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3682{
3683 struct ixgbe_hw *hw = &adapter->hw;
3684 struct net_device *dev = adapter->netdev;
3685 int tc;
3686 u32 dv_id;
3687
3688 /* Calculate max LAN frame size */
3689 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3690
3691 /* Calculate delay value for device */
3692 switch (hw->mac.type) {
3693 case ixgbe_mac_X540:
3694 dv_id = IXGBE_LOW_DV_X540(tc);
3695 break;
3696 default:
3697 dv_id = IXGBE_LOW_DV(tc);
3698 break;
3699 }
3700
3701 /* Delay value is calculated in bit times convert to KB */
3702 return IXGBE_BT2KB(dv_id);
3703}
3704
3705/*
3706 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3707 */
3708static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3709{
3710 struct ixgbe_hw *hw = &adapter->hw;
3711 int num_tc = netdev_get_num_tc(adapter->netdev);
3712 int i;
3713
3714 if (!num_tc)
3715 num_tc = 1;
3716
3717 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3718
3719 for (i = 0; i < num_tc; i++) {
3720 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3721
3722 /* Low water marks must not be larger than high water marks */
3723 if (hw->fc.low_water > hw->fc.high_water[i])
3724 hw->fc.low_water = 0;
3725 }
3726}
3727
80605c65
JF		 3728static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3729{
80605c65 3730 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3731 int hdrm;
3732 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3733
3734 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3735 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3736 hdrm = 32 << adapter->fdir_pballoc;
3737 else
3738 hdrm = 0;
80605c65 3739
f7e1027f 3740 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3741 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3742}
3743
e4911d57
AD		 3744static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3745{
3746 struct ixgbe_hw *hw = &adapter->hw;
3747 struct hlist_node *node, *node2;
3748 struct ixgbe_fdir_filter *filter;
3749
3750 spin_lock(&adapter->fdir_perfect_lock);
3751
3752 if (!hlist_empty(&adapter->fdir_filter_list))
3753 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3754
3755 hlist_for_each_entry_safe(filter, node, node2,
3756 &adapter->fdir_filter_list, fdir_node) {
3757 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3758 &filter->filter,
3759 filter->sw_idx,
3760 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3761 IXGBE_FDIR_DROP_QUEUE :
3762 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3763 }
3764
3765 spin_unlock(&adapter->fdir_perfect_lock);
3766}
3767
9a799d71
AK		 3768static void ixgbe_configure(struct ixgbe_adapter *adapter)
3769{
80605c65 3770 ixgbe_configure_pb(adapter);
7a6b6f51 3771#ifdef CONFIG_IXGBE_DCB
67ebd791 3772 ixgbe_configure_dcb(adapter);
2f90b865 3773#endif
9a799d71 3774
4c1d7b4b 3775 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3776 ixgbe_restore_vlan(adapter);
3777
eacd73f7
YZ		 3778#ifdef IXGBE_FCOE
3779 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3780 ixgbe_configure_fcoe(adapter);
3781
3782#endif /* IXGBE_FCOE */
c4cf55e5 3783 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3784 ixgbe_init_fdir_signature_82599(&adapter->hw,
3785 adapter->fdir_pballoc);
e4911d57
AD		 3786 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3787 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3788 adapter->fdir_pballoc);
3789 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3790 }
4c1d7b4b 3791
933d41f1 3792 ixgbe_configure_virtualization(adapter);
c4cf55e5 3793
9a799d71
AK		 3794 ixgbe_configure_tx(adapter);
3795 ixgbe_configure_rx(adapter);
9a799d71
AK		 3796}
3797
e8e26350
PW		 3798static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3799{
3800 switch (hw->phy.type) {
3801 case ixgbe_phy_sfp_avago:
3802 case ixgbe_phy_sfp_ftl:
3803 case ixgbe_phy_sfp_intel:
3804 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3805 case ixgbe_phy_sfp_passive_tyco:
3806 case ixgbe_phy_sfp_passive_unknown:
3807 case ixgbe_phy_sfp_active_unknown:
3808 case ixgbe_phy_sfp_ftl_active:
e8e26350 3809 return true;
8917b447
AD		 3810 case ixgbe_phy_nl:
3811 if (hw->mac.type == ixgbe_mac_82598EB)
3812 return true;
e8e26350
PW		 3813 default:
3814 return false;
3815 }
3816}
3817
0ecc061d 3818/**
e8e26350
PW		 3819 * ixgbe_sfp_link_config - set up SFP+ link
3820 * @adapter: pointer to private adapter struct
3821 **/
3822static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3823{
7086400d 3824 /*
52f33af8 3825 * We are assuming the worst case scenario here, and that
7086400d
AD		 3826 * is that an SFP was inserted/removed after the reset
3827 * but before SFP detection was enabled. As such the best
3828 * solution is to just start searching as soon as we start
3829 */
3830 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3831 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3832
7086400d 3833 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3834}
3835
3836/**
3837 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3838 * @hw: pointer to private hardware struct
3839 *
3840 * Returns 0 on success, negative on failure
3841 **/
e8e26350 3842static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3843{
3844 u32 autoneg;
8620a103 3845 bool negotiation, link_up = false;
0ecc061d
PWJ		 3846 u32 ret = IXGBE_ERR_LINK_SETUP;
3847
3848 if (hw->mac.ops.check_link)
3849 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3850
3851 if (ret)
3852 goto link_cfg_out;
3853
0b0c2b31
ET		 3854 autoneg = hw->phy.autoneg_advertised;
3855 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3856 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3857 &negotiation);
0ecc061d
PWJ		 3858 if (ret)
3859 goto link_cfg_out;
3860
8620a103
MC		 3861 if (hw->mac.ops.setup_link)
3862 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3863link_cfg_out:
3864 return ret;
3865}
3866
a34bcfff 3867static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3868{
9a799d71 3869 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3870 u32 gpie = 0;
9a799d71 3871
9b471446 3872 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3873 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3874 IXGBE_GPIE_OCD;
3875 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3876 /*
3877 * use EIAM to auto-mask when MSI-X interrupt is asserted
3878 * this saves a register write for every interrupt
3879 */
3880 switch (hw->mac.type) {
3881 case ixgbe_mac_82598EB:
3882 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3883 break;
9b471446 3884 case ixgbe_mac_82599EB:
b93a2226
DS		 3885 case ixgbe_mac_X540:
3886 default:
9b471446
JB		 3887 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3888 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3889 break;
3890 }
3891 } else {
021230d4
AV		 3892 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3893 * specifically only auto mask tx and rx interrupts */
3894 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3895 }
9a799d71 3896
a34bcfff
AD		 3897 /* XXX: to interrupt immediately for EICS writes, enable this */
3898 /* gpie |= IXGBE_GPIE_EIMEN; */
3899
3900 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3901 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3902 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3903 }
3904
5fdd31f9 3905 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3906 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3907 switch (adapter->hw.mac.type) {
3908 case ixgbe_mac_82599EB:
3909 gpie |= IXGBE_SDP0_GPIEN;
3910 break;
3911 case ixgbe_mac_X540:
3912 gpie |= IXGBE_EIMS_TS;
3913 break;
3914 default:
3915 break;
3916 }
3917 }
5fdd31f9 3918
a34bcfff
AD		 3919 /* Enable fan failure interrupt */
3920 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3921 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3922
2698b208 3923 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3924 gpie |= IXGBE_SDP1_GPIEN;
3925 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3926 }
a34bcfff
AD		 3927
3928 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3929}
3930
c7ccde0f 3931static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3932{
3933 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3934 int err;
a34bcfff
AD		 3935 u32 ctrl_ext;
3936
3937 ixgbe_get_hw_control(adapter);
3938 ixgbe_setup_gpie(adapter);
e8e26350 3939
9a799d71
AK		 3940 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3941 ixgbe_configure_msix(adapter);
3942 else
3943 ixgbe_configure_msi_and_legacy(adapter);
3944
c6ecf39a
DS		 3945 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3946 if (hw->mac.ops.enable_tx_laser &&
3947 ((hw->phy.multispeed_fiber) ||
9f911707 3948 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3949 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3950 hw->mac.ops.enable_tx_laser(hw);
3951
9a799d71 3952 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3953 ixgbe_napi_enable_all(adapter);
3954
73c4b7cd
AD		 3955 if (ixgbe_is_sfp(hw)) {
3956 ixgbe_sfp_link_config(adapter);
3957 } else {
3958 err = ixgbe_non_sfp_link_config(hw);
3959 if (err)
3960 e_err(probe, "link_config FAILED %d\n", err);
3961 }
3962
021230d4
AV		 3963 /* clear any pending interrupts, may auto mask */
3964 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3965 ixgbe_irq_enable(adapter, true, true);
9a799d71 3966
bf069c97
DS		 3967 /*
3968 * If this adapter has a fan, check to see if we had a failure
3969 * before we enabled the interrupt.
3970 */
3971 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3972 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3973 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3974 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3975 }
3976
1da100bb 3977 /* enable transmits */
477de6ed 3978 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3979
9a799d71
AK		 3980 /* bring the link up in the watchdog, this could race with our first
3981 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3982 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3983 adapter->link_check_timeout = jiffies;
7086400d 3984 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3985
3986 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3987 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3988 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3989 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3990}
3991
d4f80882
AV		 3992void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3993{
3994 WARN_ON(in_interrupt());
7086400d
AD		 3995 /* put off any impending NetWatchDogTimeout */
3996 adapter->netdev->trans_start = jiffies;
3997
d4f80882 3998 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3999 usleep_range(1000, 2000);
d4f80882 4000 ixgbe_down(adapter);
5809a1ae
GR		 4001 /*
4002 * If SR-IOV enabled then wait a bit before bringing the adapter
4003 * back up to give the VFs time to respond to the reset. The
4004 * two second wait is based upon the watchdog timer cycle in
4005 * the VF driver.
4006 */
4007 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4008 msleep(2000);
d4f80882
AV		 4009 ixgbe_up(adapter);
4010 clear_bit(__IXGBE_RESETTING, &adapter->state);
4011}
4012
c7ccde0f 4013void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4014{
4015 /* hardware has been reset, we need to reload some things */
4016 ixgbe_configure(adapter);
4017
c7ccde0f 4018 ixgbe_up_complete(adapter);
9a799d71
AK		 4019}
4020
4021void ixgbe_reset(struct ixgbe_adapter *adapter)
4022{
c44ade9e 4023 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4024 int err;
4025
7086400d
AD		 4026 /* lock SFP init bit to prevent race conditions with the watchdog */
4027 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4028 usleep_range(1000, 2000);
4029
4030 /* clear all SFP and link config related flags while holding SFP_INIT */
4031 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4032 IXGBE_FLAG2_SFP_NEEDS_RESET);
4033 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4034
8ca783ab 4035 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4036 switch (err) {
4037 case 0:
4038 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4039 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4040 break;
4041 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4042 e_dev_err("master disable timed out\n");
da4dd0f7 4043 break;
794caeb2
PWJ		 4044 case IXGBE_ERR_EEPROM_VERSION:
4045 /* We are running on a pre-production device, log a warning */
849c4542 4046 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4047 "Please be aware there may be issues associated with "
849c4542
ET		 4048 "your hardware. If you are experiencing problems "
4049 "please contact your Intel or hardware "
4050 "representative who provided you with this "
4051 "hardware.\n");
794caeb2 4052 break;
da4dd0f7 4053 default:
849c4542 4054 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4055 }
9a799d71 4056
7086400d
AD		 4057 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4058
9a799d71 4059 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4060 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4061 IXGBE_RAH_AV);
9a799d71
AK		 4062}
4063
9a799d71
AK		 4064/**
4065 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4066 * @rx_ring: ring to free buffers from
4067 **/
b6ec895e 4068static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4069{
b6ec895e 4070 struct device *dev = rx_ring->dev;
9a799d71 4071 unsigned long size;
b6ec895e 4072 u16 i;
9a799d71 4073
84418e3b
AD		 4074 /* ring already cleared, nothing to do */
4075 if (!rx_ring->rx_buffer_info)
4076 return;
9a799d71 4077
84418e3b 4078 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4079 for (i = 0; i < rx_ring->count; i++) {
4080 struct ixgbe_rx_buffer *rx_buffer_info;
4081
4082 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4083 if (rx_buffer_info->dma) {
b6ec895e 4084 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4085 rx_ring->rx_buf_len,
1b507730 4086 DMA_FROM_DEVICE);
9a799d71
AK		 4087 rx_buffer_info->dma = 0;
4088 }
4089 if (rx_buffer_info->skb) {
f8212f97 4090 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4091 rx_buffer_info->skb = NULL;
4c1975d7
AD		 4092 /* We need to clean up RSC frag lists */
4093 skb = ixgbe_merge_active_tail(skb);
4094 ixgbe_close_active_frag_list(skb);
4095 if (IXGBE_CB(skb)->delay_unmap) {
4096 dma_unmap_single(dev,
4097 IXGBE_CB(skb)->dma,
4098 rx_ring->rx_buf_len,
4099 DMA_FROM_DEVICE);
4100 IXGBE_CB(skb)->dma = 0;
4101 IXGBE_CB(skb)->delay_unmap = false;
4102 }
4103 dev_kfree_skb(skb);
9a799d71
AK		 4104 }
4105 if (!rx_buffer_info->page)
4106 continue;
4f57ca6e 4107 if (rx_buffer_info->page_dma) {
b6ec895e 4108 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4109 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4110 rx_buffer_info->page_dma = 0;
4111 }
9a799d71
AK		 4112 put_page(rx_buffer_info->page);
4113 rx_buffer_info->page = NULL;
762f4c57 4114 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4115 }
4116
4117 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4118 memset(rx_ring->rx_buffer_info, 0, size);
4119
4120 /* Zero out the descriptor ring */
4121 memset(rx_ring->desc, 0, rx_ring->size);
4122
4123 rx_ring->next_to_clean = 0;
4124 rx_ring->next_to_use = 0;
9a799d71
AK		 4125}
4126
4127/**
4128 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4129 * @tx_ring: ring to be cleaned
4130 **/
b6ec895e 4131static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4132{
4133 struct ixgbe_tx_buffer *tx_buffer_info;
4134 unsigned long size;
b6ec895e 4135 u16 i;
9a799d71 4136
84418e3b
AD		 4137 /* ring already cleared, nothing to do */
4138 if (!tx_ring->tx_buffer_info)
4139 return;
9a799d71 4140
84418e3b 4141 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4142 for (i = 0; i < tx_ring->count; i++) {
4143 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4144 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4145 }
4146
4147 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4148 memset(tx_ring->tx_buffer_info, 0, size);
4149
4150 /* Zero out the descriptor ring */
4151 memset(tx_ring->desc, 0, tx_ring->size);
4152
4153 tx_ring->next_to_use = 0;
4154 tx_ring->next_to_clean = 0;
9a799d71
AK		 4155}
4156
4157/**
021230d4 4158 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4159 * @adapter: board private structure
4160 **/
021230d4 4161static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4162{
4163 int i;
4164
021230d4 4165 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4166 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4167}
4168
4169/**
021230d4 4170 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4171 * @adapter: board private structure
4172 **/
021230d4 4173static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4174{
4175 int i;
4176
021230d4 4177 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4178 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4179}
4180
e4911d57
AD		 4181static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4182{
4183 struct hlist_node *node, *node2;
4184 struct ixgbe_fdir_filter *filter;
4185
4186 spin_lock(&adapter->fdir_perfect_lock);
4187
4188 hlist_for_each_entry_safe(filter, node, node2,
4189 &adapter->fdir_filter_list, fdir_node) {
4190 hlist_del(&filter->fdir_node);
4191 kfree(filter);
4192 }
4193 adapter->fdir_filter_count = 0;
4194
4195 spin_unlock(&adapter->fdir_perfect_lock);
4196}
4197
9a799d71
AK		 4198void ixgbe_down(struct ixgbe_adapter *adapter)
4199{
4200 struct net_device *netdev = adapter->netdev;
7f821875 4201 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4202 u32 rxctrl;
bf29ee6c 4203 int i;
9a799d71
AK		 4204
4205 /* signal that we are down to the interrupt handler */
4206 set_bit(__IXGBE_DOWN, &adapter->state);
4207
4208 /* disable receives */
7f821875
JB		 4209 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4210 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4211
2d39d576
YZ		 4212 /* disable all enabled rx queues */
4213 for (i = 0; i < adapter->num_rx_queues; i++)
4214 /* this call also flushes the previous write */
4215 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4216
032b4325 4217 usleep_range(10000, 20000);
9a799d71 4218
7f821875
JB		 4219 netif_tx_stop_all_queues(netdev);
4220
7086400d 4221 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4222 netif_carrier_off(netdev);
4223 netif_tx_disable(netdev);
4224
4225 ixgbe_irq_disable(adapter);
4226
4227 ixgbe_napi_disable_all(adapter);
4228
d034acf1
AD		 4229 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4230 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4231 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4232
4233 del_timer_sync(&adapter->service_timer);
4234
34cecbbf 4235 if (adapter->num_vfs) {
8e34d1aa
AD		 4236 /* Clear EITR Select mapping */
4237 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4238
4239 /* Mark all the VFs as inactive */
4240 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4241 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4242
34cecbbf
AD		 4243 /* ping all the active vfs to let them know we are going down */
4244 ixgbe_ping_all_vfs(adapter);
4245
4246 /* Disable all VFTE/VFRE TX/RX */
4247 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4248 }
4249
7f821875
JB		 4250 /* disable transmits in the hardware now that interrupts are off */
4251 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4252 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4253 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4254 }
34cecbbf
AD		 4255
4256 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4257 switch (hw->mac.type) {
4258 case ixgbe_mac_82599EB:
b93a2226 4259 case ixgbe_mac_X540:
88512539 4260 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4261 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4262 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4263 break;
4264 default:
4265 break;
4266 }
7f821875 4267
6f4a0e45
PL		 4268 if (!pci_channel_offline(adapter->pdev))
4269 ixgbe_reset(adapter);
c6ecf39a
DS		 4270
4271 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4272 if (hw->mac.ops.disable_tx_laser &&
4273 ((hw->phy.multispeed_fiber) ||
9f911707 4274 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4275 (hw->mac.type == ixgbe_mac_82599EB))))
4276 hw->mac.ops.disable_tx_laser(hw);
4277
9a799d71
AK		 4278 ixgbe_clean_all_tx_rings(adapter);
4279 ixgbe_clean_all_rx_rings(adapter);
4280
5dd2d332 4281#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4282 /* since we reset the hardware DCA settings were cleared */
e35ec126 4283 ixgbe_setup_dca(adapter);
96b0e0f6 4284#endif
9a799d71
AK		 4285}
4286
9a799d71 4287/**
021230d4
AV		 4288 * ixgbe_poll - NAPI Rx polling callback
4289 * @napi: structure for representing this polling device
4290 * @budget: how many packets driver is allowed to clean
4291 *
4292 * This function is used for legacy and MSI, NAPI mode
9a799d71 4293 **/
021230d4 4294static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4295{
9a1a69ad 4296 struct ixgbe_q_vector *q_vector =
e8e9f696 4297 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4298 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4299 struct ixgbe_ring *ring;
4300 int per_ring_budget;
4301 bool clean_complete = true;
9a799d71 4302
5dd2d332 4303#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4304 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4305 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4306#endif
4307
4ff7fb12
AD		 4308 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4309 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4310
4ff7fb12
AD		 4311 /* attempt to distribute budget to each queue fairly, but don't allow
4312 * the budget to go below 1 because we'll exit polling */
4313 if (q_vector->rx.count > 1)
4314 per_ring_budget = max(budget/q_vector->rx.count, 1);
4315 else
4316 per_ring_budget = budget;
d2c7ddd6 4317
4ff7fb12
AD		 4318 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4319 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4320 per_ring_budget);
4321
4322 /* If all work not completed, return budget and keep polling */
4323 if (!clean_complete)
4324 return budget;
4325
4326 /* all work done, exit the polling mode */
4327 napi_complete(napi);
4328 if (adapter->rx_itr_setting & 1)
4329 ixgbe_set_itr(q_vector);
4330 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4331 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4332
4333 return 0;
9a799d71
AK		 4334}
4335
4336/**
4337 * ixgbe_tx_timeout - Respond to a Tx Hang
4338 * @netdev: network interface device structure
4339 **/
4340static void ixgbe_tx_timeout(struct net_device *netdev)
4341{
4342 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4343
4344 /* Do the reset outside of interrupt context */
c83c6cbd 4345 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4346}
4347
4df10466
JB		 4348/**
4349 * ixgbe_set_rss_queues: Allocate queues for RSS
4350 * @adapter: board private structure to initialize
4351 *
4352 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4353 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4354 *
4355 **/
bc97114d
PWJ		 4356static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4357{
4358 bool ret = false;
0cefafad 4359 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4360
4361 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4362 f->mask = 0xF;
4363 adapter->num_rx_queues = f->indices;
4364 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4365 ret = true;
4366 } else {
bc97114d 4367 ret = false;
b9804972
JB		 4368 }
4369
bc97114d
PWJ		 4370 return ret;
4371}
4372
c4cf55e5
PWJ		 4373/**
4374 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4375 * @adapter: board private structure to initialize
4376 *
4377 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4378 * to the original CPU that initiated the Tx session. This runs in addition
4379 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4380 * Rx load across CPUs using RSS.
4381 *
4382 **/
e8e9f696 4383static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4384{
4385 bool ret = false;
4386 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4387
4388 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4389 f_fdir->mask = 0;
4390
24ddd967
AD		 4391 /*
4392 * Use RSS in addition to Flow Director to ensure the best
4393 * distribution of flows across cores, even when an FDIR flow
4394 * isn't matched.
4395 */
03ecf91a
AD		 4396 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4397 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4398 adapter->num_tx_queues = f_fdir->indices;
4399 adapter->num_rx_queues = f_fdir->indices;
4400 ret = true;
4401 } else {
4402 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4403 }
4404 return ret;
4405}
4406
0331a832
YZ		 4407#ifdef IXGBE_FCOE
4408/**
4409 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4410 * @adapter: board private structure to initialize
4411 *
4412 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4413 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4414 * rx queues out of the max number of rx queues, instead, it is used as the
4415 * index of the first rx queue used by FCoE.
4416 *
4417 **/
4418static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4419{
0331a832
YZ		 4420 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4421
e5b64635
JF		 4422 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4423 return false;
4424
e901acd6 4425 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4426
e901acd6
JF		 4427 adapter->num_rx_queues = 1;
4428 adapter->num_tx_queues = 1;
e5b64635 4429
e901acd6
JF		 4430 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4431 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4432 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4433 ixgbe_set_fdir_queues(adapter);
4434 else
4435 ixgbe_set_rss_queues(adapter);
e5b64635 4436 }
03ecf91a 4437
e901acd6
JF		 4438 /* adding FCoE rx rings to the end */
4439 f->mask = adapter->num_rx_queues;
4440 adapter->num_rx_queues += f->indices;
4441 adapter->num_tx_queues += f->indices;
0331a832 4442
e5b64635
JF		 4443 return true;
4444}
4445#endif /* IXGBE_FCOE */
4446
e901acd6
JF		 4447/* Artificial max queue cap per traffic class in DCB mode */
4448#define DCB_QUEUE_CAP 8
4449
e5b64635
JF		 4450#ifdef CONFIG_IXGBE_DCB
4451static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4452{
e901acd6
JF		 4453 int per_tc_q, q, i, offset = 0;
4454 struct net_device *dev = adapter->netdev;
4455 int tcs = netdev_get_num_tc(dev);
e5b64635 4456
e901acd6
JF		 4457 if (!tcs)
4458 return false;
e5b64635 4459
e901acd6
JF		 4460 /* Map queue offset and counts onto allocated tx queues */
4461 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4462 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4463
8b1c0b24 4464 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4465 netdev_set_tc_queue(dev, i, q, offset);
4466 offset += q;
0331a832
YZ		 4467 }
4468
e901acd6
JF		 4469 adapter->num_tx_queues = q * tcs;
4470 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4471
4472#ifdef IXGBE_FCOE
e901acd6
JF		 4473 /* FCoE enabled queues require special configuration indexed
4474 * by feature specific indices and mask. Here we map FCoE
4475 * indices onto the DCB queue pairs allowing FCoE to own
4476 * configuration later.
e5b64635 4477 */
e901acd6
JF		 4478 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4479 int tc;
4480 struct ixgbe_ring_feature *f =
4481 &adapter->ring_feature[RING_F_FCOE];
4482
4483 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4484 f->indices = dev->tc_to_txq[tc].count;
4485 f->mask = dev->tc_to_txq[tc].offset;
4486 }
e5b64635
JF		 4487#endif
4488
e901acd6 4489 return true;
0331a832 4490}
e5b64635 4491#endif
0331a832 4492
1cdd1ec8
GR		 4493/**
4494 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4495 * @adapter: board private structure to initialize
4496 *
4497 * IOV doesn't actually use anything, so just NAK the
4498 * request for now and let the other queue routines
4499 * figure out what to do.
4500 */
4501static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4502{
4503 return false;
4504}
4505
4df10466 4506/*
25985edc 4507 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4508 * @adapter: board private structure to initialize
4509 *
4510 * This is the top level queue allocation routine. The order here is very
4511 * important, starting with the "most" number of features turned on at once,
4512 * and ending with the smallest set of features. This way large combinations
4513 * can be allocated if they're turned on, and smaller combinations are the
4514 * fallthrough conditions.
4515 *
4516 **/
847f53ff 4517static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4518{
1cdd1ec8
GR		 4519 /* Start with base case */
4520 adapter->num_rx_queues = 1;
4521 adapter->num_tx_queues = 1;
4522 adapter->num_rx_pools = adapter->num_rx_queues;
4523 adapter->num_rx_queues_per_pool = 1;
4524
4525 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4526 goto done;
1cdd1ec8 4527
bc97114d
PWJ		 4528#ifdef CONFIG_IXGBE_DCB
4529 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4530 goto done;
bc97114d
PWJ		 4531
4532#endif
e5b64635
JF		 4533#ifdef IXGBE_FCOE
4534 if (ixgbe_set_fcoe_queues(adapter))
4535 goto done;
4536
4537#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4538 if (ixgbe_set_fdir_queues(adapter))
4539 goto done;
4540
bc97114d 4541 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4542 goto done;
4543
4544 /* fallback to base case */
4545 adapter->num_rx_queues = 1;
4546 adapter->num_tx_queues = 1;
4547
4548done:
9d837ea2
YZ		 4549 if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
4550 (adapter->netdev->reg_state == NETREG_UNREGISTERING))
4551 return 0;
4552
847f53ff 4553 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4554 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4555 return netif_set_real_num_rx_queues(adapter->netdev,
4556 adapter->num_rx_queues);
b9804972
JB		 4557}
4558
021230d4 4559static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4560 int vectors)
021230d4
AV		 4561{
4562 int err, vector_threshold;
4563
4564 /* We'll want at least 3 (vector_threshold):
4565 * 1) TxQ[0] Cleanup
4566 * 2) RxQ[0] Cleanup
4567 * 3) Other (Link Status Change, etc.)
4568 * 4) TCP Timer (optional)
4569 */
4570 vector_threshold = MIN_MSIX_COUNT;
4571
24ddd967
AD		 4572 /*
4573 * The more we get, the more we will assign to Tx/Rx Cleanup
021230d4
AV		 4574 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4575 * Right now, we simply care about how many we'll get; we'll
4576 * set them up later while requesting irq's.
4577 */
4578 while (vectors >= vector_threshold) {
4579 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4580 vectors);
021230d4
AV		 4581 if (!err) /* Success in acquiring all requested vectors. */
4582 break;
4583 else if (err < 0)
4584 vectors = 0; /* Nasty failure, quit now */
4585 else /* err == number of vectors we should try again with */
4586 vectors = err;
4587 }
4588
4589 if (vectors < vector_threshold) {
4590 /* Can't allocate enough MSI-X interrupts? Oh well.
4591 * This just means we'll go with either a single MSI
4592 * vector or fall back to legacy interrupts.
4593 */
849c4542
ET		 4594 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4595 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4596 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4597 kfree(adapter->msix_entries);
4598 adapter->msix_entries = NULL;
021230d4
AV		 4599 } else {
4600 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4601 /*
4602 * Adjust for only the vectors we'll use, which is minimum
4603 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4604 * vectors we were allocated.
4605 */
4606 adapter->num_msix_vectors = min(vectors,
e8e9f696 4607 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4608 }
4609}
4610
021230d4 4611/**
bc97114d 4612 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4613 * @adapter: board private structure to initialize
4614 *
bc97114d
PWJ		 4615 * Cache the descriptor ring offsets for RSS to the assigned rings.
4616 *
021230d4 4617 **/
bc97114d 4618static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4619{
bc97114d 4620 int i;
bc97114d 4621
9d6b758f
AD		 4622 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4623 return false;
bc97114d 4624
9d6b758f
AD		 4625 for (i = 0; i < adapter->num_rx_queues; i++)
4626 adapter->rx_ring[i]->reg_idx = i;
4627 for (i = 0; i < adapter->num_tx_queues; i++)
4628 adapter->tx_ring[i]->reg_idx = i;
4629
4630 return true;
bc97114d
PWJ		 4631}
4632
4633#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4634
4635/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4636static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4637 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4638{
4639 struct net_device *dev = adapter->netdev;
4640 struct ixgbe_hw *hw = &adapter->hw;
4641 u8 num_tcs = netdev_get_num_tc(dev);
4642
4643 *tx = 0;
4644 *rx = 0;
4645
4646 switch (hw->mac.type) {
4647 case ixgbe_mac_82598EB:
aba70d5e
JF		 4648 *tx = tc << 2;
4649 *rx = tc << 3;
e5b64635
JF		 4650 break;
4651 case ixgbe_mac_82599EB:
4652 case ixgbe_mac_X540:
4fa2e0e1 4653 if (num_tcs > 4) {
e5b64635
JF		 4654 if (tc < 3) {
4655 *tx = tc << 5;
4656 *rx = tc << 4;
4657 } else if (tc < 5) {
4658 *tx = ((tc + 2) << 4);
4659 *rx = tc << 4;
4660 } else if (tc < num_tcs) {
4661 *tx = ((tc + 8) << 3);
4662 *rx = tc << 4;
4663 }
4fa2e0e1 4664 } else {
e5b64635
JF		 4665 *rx = tc << 5;
4666 switch (tc) {
4667 case 0:
4668 *tx = 0;
4669 break;
4670 case 1:
4671 *tx = 64;
4672 break;
4673 case 2:
4674 *tx = 96;
4675 break;
4676 case 3:
4677 *tx = 112;
4678 break;
4679 default:
4680 break;
4681 }
4682 }
4683 break;
4684 default:
4685 break;
4686 }
4687}
4688
bc97114d
PWJ		 4689/**
4690 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4691 * @adapter: board private structure to initialize
4692 *
4693 * Cache the descriptor ring offsets for DCB to the assigned rings.
4694 *
4695 **/
4696static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4697{
e5b64635
JF		 4698 struct net_device *dev = adapter->netdev;
4699 int i, j, k;
4700 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4701
8b1c0b24 4702 if (!num_tcs)
bd508178 4703 return false;
f92ef202 4704
e5b64635
JF		 4705 for (i = 0, k = 0; i < num_tcs; i++) {
4706 unsigned int tx_s, rx_s;
4707 u16 count = dev->tc_to_txq[i].count;
4708
4709 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4710 for (j = 0; j < count; j++, k++) {
4711 adapter->tx_ring[k]->reg_idx = tx_s + j;
4712 adapter->rx_ring[k]->reg_idx = rx_s + j;
4713 adapter->tx_ring[k]->dcb_tc = i;
4714 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4715 }
021230d4 4716 }
e5b64635
JF		 4717
4718 return true;
bc97114d
PWJ		 4719}
4720#endif
4721
c4cf55e5
PWJ		 4722/**
4723 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4724 * @adapter: board private structure to initialize
4725 *
4726 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4727 *
4728 **/
e8e9f696 4729static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4730{
4731 int i;
4732 bool ret = false;
4733
03ecf91a
AD		 4734 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4735 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4736 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4737 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4738 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4739 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4740 ret = true;
4741 }
4742
4743 return ret;
4744}
4745
0331a832
YZ		 4746#ifdef IXGBE_FCOE
4747/**
4748 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4749 * @adapter: board private structure to initialize
4750 *
4751 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4752 *
4753 */
4754static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4755{
0331a832 4756 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4757 int i;
4758 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4759
4760 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4761 return false;
0331a832 4762
bf29ee6c 4763 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4764 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4765 ixgbe_cache_ring_fdir(adapter);
4766 else
4767 ixgbe_cache_ring_rss(adapter);
8faa2a78 4768
bf29ee6c
AD		 4769 fcoe_rx_i = f->mask;
4770 fcoe_tx_i = f->mask;
0331a832 4771 }
bf29ee6c
AD		 4772 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4773 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4774 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4775 }
4776 return true;
0331a832
YZ		 4777}
4778
4779#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4780/**
4781 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4782 * @adapter: board private structure to initialize
4783 *
4784 * SR-IOV doesn't use any descriptor rings but changes the default if
4785 * no other mapping is used.
4786 *
4787 */
4788static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4789{
4a0b9ca0
PW		 4790 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4791 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4792 if (adapter->num_vfs)
4793 return true;
4794 else
4795 return false;
4796}
4797
bc97114d
PWJ		 4798/**
4799 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4800 * @adapter: board private structure to initialize
4801 *
4802 * Once we know the feature-set enabled for the device, we'll cache
4803 * the register offset the descriptor ring is assigned to.
4804 *
4805 * Note, the order the various feature calls is important. It must start with
4806 * the "most" features enabled at the same time, then trickle down to the
4807 * least amount of features turned on at once.
4808 **/
4809static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4810{
4811 /* start with default case */
4a0b9ca0
PW		 4812 adapter->rx_ring[0]->reg_idx = 0;
4813 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4814
1cdd1ec8
GR		 4815 if (ixgbe_cache_ring_sriov(adapter))
4816 return;
4817
e5b64635
JF		 4818#ifdef CONFIG_IXGBE_DCB
4819 if (ixgbe_cache_ring_dcb(adapter))
4820 return;
4821#endif
4822
0331a832
YZ		 4823#ifdef IXGBE_FCOE
4824 if (ixgbe_cache_ring_fcoe(adapter))
4825 return;
0331a832 4826#endif /* IXGBE_FCOE */
bc97114d 4827
c4cf55e5
PWJ		 4828 if (ixgbe_cache_ring_fdir(adapter))
4829 return;
4830
bc97114d
PWJ		 4831 if (ixgbe_cache_ring_rss(adapter))
4832 return;
021230d4
AV		 4833}
4834
9a799d71
AK		 4835/**
4836 * ixgbe_alloc_queues - Allocate memory for all rings
4837 * @adapter: board private structure to initialize
4838 *
4839 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4840 * number of queues at compile-time. The polling_netdev array is
4841 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4842 **/
2f90b865 4843static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4844{
e2ddeba9 4845 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4846
e2ddeba9
ED		 4847 if (nid < 0 || !node_online(nid))
4848 nid = first_online_node;
4849
4850 for (; tx < adapter->num_tx_queues; tx++) {
4851 struct ixgbe_ring *ring;
4852
4853 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4854 if (!ring)
e2ddeba9 4855 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4856 if (!ring)
e2ddeba9 4857 goto err_allocation;
4a0b9ca0 4858 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4859 ring->queue_index = tx;
4860 ring->numa_node = nid;
b6ec895e 4861 ring->dev = &adapter->pdev->dev;
fc77dc3c 4862 ring->netdev = adapter->netdev;
4a0b9ca0 4863
e2ddeba9 4864 adapter->tx_ring[tx] = ring;
021230d4 4865 }
b9804972 4866
e2ddeba9
ED		 4867 for (; rx < adapter->num_rx_queues; rx++) {
4868 struct ixgbe_ring *ring;
4a0b9ca0 4869
e2ddeba9 4870 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4871 if (!ring)
e2ddeba9 4872 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4873 if (!ring)
e2ddeba9
ED		 4874 goto err_allocation;
4875 ring->count = adapter->rx_ring_count;
4876 ring->queue_index = rx;
4877 ring->numa_node = nid;
b6ec895e 4878 ring->dev = &adapter->pdev->dev;
fc77dc3c 4879 ring->netdev = adapter->netdev;
4a0b9ca0 4880
8a0da21b
AD		 4881 /*
4882 * 82599 errata, UDP frames with a 0 checksum can be marked as
4883 * checksum errors.
4884 */
4885 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4886 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
4887
e2ddeba9 4888 adapter->rx_ring[rx] = ring;
021230d4
AV		 4889 }
4890
4891 ixgbe_cache_ring_register(adapter);
4892
4893 return 0;
4894
e2ddeba9
ED		 4895err_allocation:
4896 while (tx)
4897 kfree(adapter->tx_ring[--tx]);
4898
4899 while (rx)
4900 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4901 return -ENOMEM;
4902}
4903
4904/**
4905 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4906 * @adapter: board private structure to initialize
4907 *
4908 * Attempt to configure the interrupts using the best available
4909 * capabilities of the hardware and the kernel.
4910 **/
feea6a57 4911static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4912{
8be0e467 4913 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4914 int err = 0;
4915 int vector, v_budget;
4916
4917 /*
4918 * It's easy to be greedy for MSI-X vectors, but it really
4919 * doesn't do us much good if we have a lot more vectors
4920 * than CPU's. So let's be conservative and only ask for
342bde1b 4921 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4922 */
4923 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4924 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4925
4926 /*
4927 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4928 * hw.mac->max_msix_vectors vectors. With features
4929 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4930 * descriptor queues supported by our device. Thus, we cap it off in
4931 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4932 */
8be0e467 4933 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4934
4935 /* A failure in MSI-X entry allocation isn't fatal, but it does
4936 * mean we disable MSI-X capabilities of the adapter. */
4937 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4938 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4939 if (adapter->msix_entries) {
4940 for (vector = 0; vector < v_budget; vector++)
4941 adapter->msix_entries[vector].entry = vector;
021230d4 4942
7a921c93 4943 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4944
7a921c93
AD		 4945 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4946 goto out;
4947 }
26d27844 4948
7a921c93
AD		 4949 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4950 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4951 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4952 e_err(probe,
03ecf91a 4953 "ATR is not supported while multiple "
45b9f509
AD		 4954 "queues are disabled. Disabling Flow Director\n");
4955 }
c4cf55e5 4956 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4957 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4958 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4959 ixgbe_disable_sriov(adapter);
4960
847f53ff
BH		 4961 err = ixgbe_set_num_queues(adapter);
4962 if (err)
4963 return err;
021230d4 4964
021230d4
AV		 4965 err = pci_enable_msi(adapter->pdev);
4966 if (!err) {
4967 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4968 } else {
849c4542
ET		 4969 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4970 "Unable to allocate MSI interrupt, "
4971 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4972 /* reset err */
4973 err = 0;
4974 }
4975
4976out:
021230d4
AV		 4977 return err;
4978}
4979
7a921c93
AD		 4980/**
4981 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4982 * @adapter: board private structure to initialize
4983 *
4984 * We allocate one q_vector per queue interrupt. If allocation fails we
4985 * return -ENOMEM.
4986 **/
4987static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4988{
4ff7fb12 4989 int v_idx, num_q_vectors;
7a921c93 4990 struct ixgbe_q_vector *q_vector;
7a921c93 4991
4ff7fb12 4992 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4993 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4994 else
7a921c93 4995 num_q_vectors = 1;
7a921c93 4996
4ff7fb12 4997 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4998 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4999 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 5000 if (!q_vector)
5001 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 5002 GFP_KERNEL);
7a921c93
AD		 5003 if (!q_vector)
5004 goto err_out;
4ff7fb12 5005
7a921c93 5006 q_vector->adapter = adapter;
4ff7fb12
AD		 5007 q_vector->v_idx = v_idx;
5008
207867f5
AD		 5009 /* Allocate the affinity_hint cpumask, configure the mask */
5010 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
5011 goto err_out;
5012 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 5013 netif_napi_add(adapter->netdev, &q_vector->napi,
5014 ixgbe_poll, 64);
5015 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 5016 }
5017
5018 return 0;
5019
5020err_out:
4ff7fb12
AD		 5021 while (v_idx) {
5022 v_idx--;
5023 q_vector = adapter->q_vector[v_idx];
7a921c93 5024 netif_napi_del(&q_vector->napi);
207867f5 5025 free_cpumask_var(q_vector->affinity_mask);
7a921c93 5026 kfree(q_vector);
4ff7fb12 5027 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 5028 }
5029 return -ENOMEM;
5030}
5031
5032/**
5033 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5034 * @adapter: board private structure to initialize
5035 *
5036 * This function frees the memory allocated to the q_vectors. In addition if
5037 * NAPI is enabled it will delete any references to the NAPI struct prior
5038 * to freeing the q_vector.
5039 **/
5040static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5041{
207867f5 5042 int v_idx, num_q_vectors;
7a921c93 5043
91281fd3 5044 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5045 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5046 else
7a921c93 5047 num_q_vectors = 1;
7a921c93 5048
207867f5
AD		 5049 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
5050 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
5051 adapter->q_vector[v_idx] = NULL;
91281fd3 5052 netif_napi_del(&q_vector->napi);
207867f5 5053 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 5054 kfree(q_vector);
5055 }
5056}
5057
7b25cdba 5058static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5059{
5060 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5061 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5062 pci_disable_msix(adapter->pdev);
5063 kfree(adapter->msix_entries);
5064 adapter->msix_entries = NULL;
5065 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5066 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5067 pci_disable_msi(adapter->pdev);
5068 }
021230d4
AV		 5069}
5070
5071/**
5072 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5073 * @adapter: board private structure to initialize
5074 *
5075 * We determine which interrupt scheme to use based on...
5076 * - Kernel support (MSI, MSI-X)
5077 * - which can be user-defined (via MODULE_PARAM)
5078 * - Hardware queue count (num_*_queues)
5079 * - defined by miscellaneous hardware support/features (RSS, etc.)
5080 **/
2f90b865 5081int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5082{
5083 int err;
5084
5085 /* Number of supported queues */
847f53ff
BH		 5086 err = ixgbe_set_num_queues(adapter);
5087 if (err)
5088 return err;
021230d4 5089
021230d4
AV		 5090 err = ixgbe_set_interrupt_capability(adapter);
5091 if (err) {
849c4542 5092 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5093 goto err_set_interrupt;
9a799d71
AK		 5094 }
5095
7a921c93
AD		 5096 err = ixgbe_alloc_q_vectors(adapter);
5097 if (err) {
849c4542 5098 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5099 goto err_alloc_q_vectors;
5100 }
5101
5102 err = ixgbe_alloc_queues(adapter);
5103 if (err) {
849c4542 5104 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5105 goto err_alloc_queues;
5106 }
5107
849c4542 5108 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5109 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5110 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5111
5112 set_bit(__IXGBE_DOWN, &adapter->state);
5113
9a799d71 5114 return 0;
021230d4 5115
7a921c93
AD		 5116err_alloc_queues:
5117 ixgbe_free_q_vectors(adapter);
5118err_alloc_q_vectors:
5119 ixgbe_reset_interrupt_capability(adapter);
021230d4 5120err_set_interrupt:
7a921c93
AD		 5121 return err;
5122}
5123
5124/**
5125 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5126 * @adapter: board private structure to clear interrupt scheme on
5127 *
5128 * We go through and clear interrupt specific resources and reset the structure
5129 * to pre-load conditions
5130 **/
5131void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5132{
4a0b9ca0
PW		 5133 int i;
5134
5135 for (i = 0; i < adapter->num_tx_queues; i++) {
5136 kfree(adapter->tx_ring[i]);
5137 adapter->tx_ring[i] = NULL;
5138 }
5139 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5140 struct ixgbe_ring *ring = adapter->rx_ring[i];
5141
5142 /* ixgbe_get_stats64() might access this ring, we must wait
5143 * a grace period before freeing it.
5144 */
bcec8b65 5145 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5146 adapter->rx_ring[i] = NULL;
5147 }
7a921c93 5148
b8eb3a10
DS		 5149 adapter->num_tx_queues = 0;
5150 adapter->num_rx_queues = 0;
5151
7a921c93
AD		 5152 ixgbe_free_q_vectors(adapter);
5153 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5154}
5155
5156/**
5157 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5158 * @adapter: board private structure to initialize
5159 *
5160 * ixgbe_sw_init initializes the Adapter private data structure.
5161 * Fields are initialized based on PCI device information and
5162 * OS network device settings (MTU size).
5163 **/
5164static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5165{
5166 struct ixgbe_hw *hw = &adapter->hw;
5167 struct pci_dev *pdev = adapter->pdev;
021230d4 5168 unsigned int rss;
7a6b6f51 5169#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5170 int j;
5171 struct tc_configuration *tc;
5172#endif
021230d4 5173
c44ade9e
JB		 5174 /* PCI config space info */
5175
5176 hw->vendor_id = pdev->vendor;
5177 hw->device_id = pdev->device;
5178 hw->revision_id = pdev->revision;
5179 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5180 hw->subsystem_device_id = pdev->subsystem_device;
5181
021230d4
AV		 5182 /* Set capability flags */
5183 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5184 adapter->ring_feature[RING_F_RSS].indices = rss;
5185 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5186 switch (hw->mac.type) {
5187 case ixgbe_mac_82598EB:
bf069c97
DS		 5188 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5189 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5190 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 5191 break;
b93a2226 5192 case ixgbe_mac_X540:
4f51bf70
JK		 5193 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5194 case ixgbe_mac_82599EB:
e8e26350 5195 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5196 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5197 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5198 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5199 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5200 /* Flow Director hash filters enabled */
5201 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5202 adapter->atr_sample_rate = 20;
c4cf55e5 5203 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5204 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5205 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5206#ifdef IXGBE_FCOE
0d551589
YZ		 5207 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5208 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5209 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5210#ifdef CONFIG_IXGBE_DCB
6ee16520 5211 /* Default traffic class to use for FCoE */
56075a98 5212 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5213#endif
eacd73f7 5214#endif /* IXGBE_FCOE */
bd508178
AD		 5215 break;
5216 default:
5217 break;
f8212f97 5218 }
2f90b865 5219
1fc5f038
AD		 5220 /* n-tuple support exists, always init our spinlock */
5221 spin_lock_init(&adapter->fdir_perfect_lock);
5222
7a6b6f51 5223#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5224 switch (hw->mac.type) {
5225 case ixgbe_mac_X540:
5226 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5227 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5228 break;
5229 default:
5230 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5231 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5232 break;
5233 }
5234
2f90b865
AD		 5235 /* Configure DCB traffic classes */
5236 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5237 tc = &adapter->dcb_cfg.tc_config[j];
5238 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5239 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5240 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5241 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5242 tc->dcb_pfc = pfc_disabled;
5243 }
4de2a022
JF		 5244
5245 /* Initialize default user to priority mapping, UPx->TC0 */
5246 tc = &adapter->dcb_cfg.tc_config[0];
5247 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5248 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5249
2f90b865
AD		 5250 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5251 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5252 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5253 adapter->dcb_set_bitmap = 0x00;
3032309b 5254 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5255 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5256 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5257
5258#endif
9a799d71
AK		 5259
5260 /* default flow control settings */
cd7664f6 5261 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5262 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5263#ifdef CONFIG_DCB
5264 adapter->last_lfc_mode = hw->fc.current_mode;
5265#endif
9da712d2 5266 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5267 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5268 hw->fc.send_xon = true;
71fd570b 5269 hw->fc.disable_fc_autoneg = false;
9a799d71 5270
30efa5a3 5271 /* enable itr by default in dynamic mode */
f7554a2b 5272 adapter->rx_itr_setting = 1;
f7554a2b 5273 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5274
5275 /* set defaults for eitr in MegaBytes */
5276 adapter->eitr_low = 10;
5277 adapter->eitr_high = 20;
5278
5279 /* set default ring sizes */
5280 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5281 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5282
bd198058 5283 /* set default work limits */
59224555 5284 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5285
9a799d71 5286 /* initialize eeprom parameters */
c44ade9e 5287 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5288 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5289 return -EIO;
5290 }
5291
1a6c14a2
JB		 5292 /* get assigned NUMA node */
5293 adapter->node = dev_to_node(&pdev->dev);
5294
9a799d71
AK		 5295 set_bit(__IXGBE_DOWN, &adapter->state);
5296
5297 return 0;
5298}
5299
5300/**
5301 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5302 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5303 *
5304 * Return 0 on success, negative on failure
5305 **/
b6ec895e 5306int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5307{
b6ec895e 5308 struct device *dev = tx_ring->dev;
9a799d71
AK		 5309 int size;
5310
3a581073 5311 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5312 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5313 if (!tx_ring->tx_buffer_info)
89bf67f1 5314 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5315 if (!tx_ring->tx_buffer_info)
5316 goto err;
9a799d71
AK		 5317
5318 /* round up to nearest 4K */
12207e49 5319 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5320 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5321
b6ec895e 5322 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5323 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5324 if (!tx_ring->desc)
5325 goto err;
9a799d71 5326
3a581073
JB		 5327 tx_ring->next_to_use = 0;
5328 tx_ring->next_to_clean = 0;
9a799d71 5329 return 0;
e01c31a5
JB		 5330
5331err:
5332 vfree(tx_ring->tx_buffer_info);
5333 tx_ring->tx_buffer_info = NULL;
b6ec895e 5334 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5335 return -ENOMEM;
9a799d71
AK		 5336}
5337
69888674
AD		 5338/**
5339 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5340 * @adapter: board private structure
5341 *
5342 * If this function returns with an error, then it's possible one or
5343 * more of the rings is populated (while the rest are not). It is the
5344 * callers duty to clean those orphaned rings.
5345 *
5346 * Return 0 on success, negative on failure
5347 **/
5348static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5349{
5350 int i, err = 0;
5351
5352 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5353 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5354 if (!err)
5355 continue;
396e799c 5356 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5357 break;
5358 }
5359
5360 return err;
5361}
5362
9a799d71
AK		 5363/**
5364 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5365 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5366 *
5367 * Returns 0 on success, negative on failure
5368 **/
b6ec895e 5369int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5370{
b6ec895e 5371 struct device *dev = rx_ring->dev;
021230d4 5372 int size;
9a799d71 5373
3a581073 5374 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5375 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5376 if (!rx_ring->rx_buffer_info)
89bf67f1 5377 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5378 if (!rx_ring->rx_buffer_info)
5379 goto err;
9a799d71 5380
9a799d71 5381 /* Round up to nearest 4K */
3a581073
JB		 5382 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5383 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5384
b6ec895e 5385 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5386 &rx_ring->dma, GFP_KERNEL);
9a799d71 5387
b6ec895e
AD		 5388 if (!rx_ring->desc)
5389 goto err;
9a799d71 5390
3a581073
JB		 5391 rx_ring->next_to_clean = 0;
5392 rx_ring->next_to_use = 0;
9a799d71
AK		 5393
5394 return 0;
b6ec895e
AD		 5395err:
5396 vfree(rx_ring->rx_buffer_info);
5397 rx_ring->rx_buffer_info = NULL;
5398 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5399 return -ENOMEM;
9a799d71
AK		 5400}
5401
69888674
AD		 5402/**
5403 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5404 * @adapter: board private structure
5405 *
5406 * If this function returns with an error, then it's possible one or
5407 * more of the rings is populated (while the rest are not). It is the
5408 * callers duty to clean those orphaned rings.
5409 *
5410 * Return 0 on success, negative on failure
5411 **/
69888674
AD		 5412static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5413{
5414 int i, err = 0;
5415
5416 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5417 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5418 if (!err)
5419 continue;
396e799c 5420 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5421 break;
5422 }
5423
5424 return err;
5425}
5426
9a799d71
AK		 5427/**
5428 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5429 * @tx_ring: Tx descriptor ring for a specific queue
5430 *
5431 * Free all transmit software resources
5432 **/
b6ec895e 5433void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5434{
b6ec895e 5435 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5436
5437 vfree(tx_ring->tx_buffer_info);
5438 tx_ring->tx_buffer_info = NULL;
5439
b6ec895e
AD		 5440 /* if not set, then don't free */
5441 if (!tx_ring->desc)
5442 return;
5443
5444 dma_free_coherent(tx_ring->dev, tx_ring->size,
5445 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5446
5447 tx_ring->desc = NULL;
5448}
5449
5450/**
5451 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5452 * @adapter: board private structure
5453 *
5454 * Free all transmit software resources
5455 **/
5456static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5457{
5458 int i;
5459
5460 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5461 if (adapter->tx_ring[i]->desc)
b6ec895e 5462 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5463}
5464
5465/**
b4617240 5466 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5467 * @rx_ring: ring to clean the resources from
5468 *
5469 * Free all receive software resources
5470 **/
b6ec895e 5471void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5472{
b6ec895e 5473 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5474
5475 vfree(rx_ring->rx_buffer_info);
5476 rx_ring->rx_buffer_info = NULL;
5477
b6ec895e
AD		 5478 /* if not set, then don't free */
5479 if (!rx_ring->desc)
5480 return;
5481
5482 dma_free_coherent(rx_ring->dev, rx_ring->size,
5483 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5484
5485 rx_ring->desc = NULL;
5486}
5487
5488/**
5489 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5490 * @adapter: board private structure
5491 *
5492 * Free all receive software resources
5493 **/
5494static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5495{
5496 int i;
5497
5498 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5499 if (adapter->rx_ring[i]->desc)
b6ec895e 5500 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5501}
5502
9a799d71
AK		 5503/**
5504 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5505 * @netdev: network interface device structure
5506 * @new_mtu: new value for maximum frame size
5507 *
5508 * Returns 0 on success, negative on failure
5509 **/
5510static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5511{
5512 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5513 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5514 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5515
42c783c5 5516 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5517 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5518 hw->mac.type != ixgbe_mac_X540) {
5519 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5520 return -EINVAL;
5521 } else {
5522 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5523 return -EINVAL;
5524 }
9a799d71 5525
396e799c 5526 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5527 /* must set new MTU before calling down or up */
9a799d71
AK		 5528 netdev->mtu = new_mtu;
5529
d4f80882
AV		 5530 if (netif_running(netdev))
5531 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5532
5533 return 0;
5534}
5535
5536/**
5537 * ixgbe_open - Called when a network interface is made active
5538 * @netdev: network interface device structure
5539 *
5540 * Returns 0 on success, negative value on failure
5541 *
5542 * The open entry point is called when a network interface is made
5543 * active by the system (IFF_UP). At this point all resources needed
5544 * for transmit and receive operations are allocated, the interrupt
5545 * handler is registered with the OS, the watchdog timer is started,
5546 * and the stack is notified that the interface is ready.
5547 **/
5548static int ixgbe_open(struct net_device *netdev)
5549{
5550 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5551 int err;
4bebfaa5
AK		 5552
5553 /* disallow open during test */
5554 if (test_bit(__IXGBE_TESTING, &adapter->state))
5555 return -EBUSY;
9a799d71 5556
54386467
JB		 5557 netif_carrier_off(netdev);
5558
9a799d71
AK		 5559 /* allocate transmit descriptors */
5560 err = ixgbe_setup_all_tx_resources(adapter);
5561 if (err)
5562 goto err_setup_tx;
5563
9a799d71
AK		 5564 /* allocate receive descriptors */
5565 err = ixgbe_setup_all_rx_resources(adapter);
5566 if (err)
5567 goto err_setup_rx;
5568
5569 ixgbe_configure(adapter);
5570
021230d4 5571 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5572 if (err)
5573 goto err_req_irq;
5574
c7ccde0f 5575 ixgbe_up_complete(adapter);
9a799d71
AK		 5576
5577 return 0;
5578
9a799d71 5579err_req_irq:
9a799d71 5580err_setup_rx:
a20a1199 5581 ixgbe_free_all_rx_resources(adapter);
9a799d71 5582err_setup_tx:
a20a1199 5583 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5584 ixgbe_reset(adapter);
5585
5586 return err;
5587}
5588
5589/**
5590 * ixgbe_close - Disables a network interface
5591 * @netdev: network interface device structure
5592 *
5593 * Returns 0, this is not allowed to fail
5594 *
5595 * The close entry point is called when an interface is de-activated
5596 * by the OS. The hardware is still under the drivers control, but
5597 * needs to be disabled. A global MAC reset is issued to stop the
5598 * hardware, and all transmit and receive resources are freed.
5599 **/
5600static int ixgbe_close(struct net_device *netdev)
5601{
5602 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5603
5604 ixgbe_down(adapter);
5605 ixgbe_free_irq(adapter);
5606
e4911d57
AD		 5607 ixgbe_fdir_filter_exit(adapter);
5608
9a799d71
AK		 5609 ixgbe_free_all_tx_resources(adapter);
5610 ixgbe_free_all_rx_resources(adapter);
5611
5eba3699 5612 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5613
5614 return 0;
5615}
5616
b3c8b4ba
AD		 5617#ifdef CONFIG_PM
5618static int ixgbe_resume(struct pci_dev *pdev)
5619{
c60fbb00
AD		 5620 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5621 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5622 u32 err;
5623
5624 pci_set_power_state(pdev, PCI_D0);
5625 pci_restore_state(pdev);
656ab817
DS		 5626 /*
5627 * pci_restore_state clears dev->state_saved so call
5628 * pci_save_state to restore it.
5629 */
5630 pci_save_state(pdev);
9ce77666 5631
5632 err = pci_enable_device_mem(pdev);
b3c8b4ba 5633 if (err) {
849c4542 5634 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5635 return err;
5636 }
5637 pci_set_master(pdev);
5638
dd4d8ca6 5639 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5640
5641 err = ixgbe_init_interrupt_scheme(adapter);
5642 if (err) {
849c4542 5643 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5644 return err;
5645 }
5646
b3c8b4ba
AD		 5647 ixgbe_reset(adapter);
5648
495dce12
WJP		 5649 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5650
b3c8b4ba 5651 if (netif_running(netdev)) {
c60fbb00 5652 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5653 if (err)
5654 return err;
5655 }
5656
5657 netif_device_attach(netdev);
5658
5659 return 0;
5660}
b3c8b4ba 5661#endif /* CONFIG_PM */
9d8d05ae
RW		 5662
5663static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5664{
c60fbb00
AD		 5665 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5666 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5667 struct ixgbe_hw *hw = &adapter->hw;
5668 u32 ctrl, fctrl;
5669 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5670#ifdef CONFIG_PM
5671 int retval = 0;
5672#endif
5673
5674 netif_device_detach(netdev);
5675
5676 if (netif_running(netdev)) {
5677 ixgbe_down(adapter);
5678 ixgbe_free_irq(adapter);
5679 ixgbe_free_all_tx_resources(adapter);
5680 ixgbe_free_all_rx_resources(adapter);
5681 }
b3c8b4ba 5682
5f5ae6fc 5683 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5684#ifdef CONFIG_DCB
5685 kfree(adapter->ixgbe_ieee_pfc);
5686 kfree(adapter->ixgbe_ieee_ets);
5687#endif
5f5ae6fc 5688
b3c8b4ba
AD		 5689#ifdef CONFIG_PM
5690 retval = pci_save_state(pdev);
5691 if (retval)
5692 return retval;
4df10466 5693
b3c8b4ba 5694#endif
e8e26350
PW		 5695 if (wufc) {
5696 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5697
e8e26350
PW		 5698 /* turn on all-multi mode if wake on multicast is enabled */
5699 if (wufc & IXGBE_WUFC_MC) {
5700 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5701 fctrl |= IXGBE_FCTRL_MPE;
5702 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5703 }
5704
5705 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5706 ctrl |= IXGBE_CTRL_GIO_DIS;
5707 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5708
5709 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5710 } else {
5711 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5712 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5713 }
5714
bd508178
AD		 5715 switch (hw->mac.type) {
5716 case ixgbe_mac_82598EB:
dd4d8ca6 5717 pci_wake_from_d3(pdev, false);
bd508178
AD		 5718 break;
5719 case ixgbe_mac_82599EB:
b93a2226 5720 case ixgbe_mac_X540:
bd508178
AD		 5721 pci_wake_from_d3(pdev, !!wufc);
5722 break;
5723 default:
5724 break;
5725 }
b3c8b4ba 5726
9d8d05ae
RW		 5727 *enable_wake = !!wufc;
5728
b3c8b4ba
AD		 5729 ixgbe_release_hw_control(adapter);
5730
5731 pci_disable_device(pdev);
5732
9d8d05ae
RW		 5733 return 0;
5734}
5735
5736#ifdef CONFIG_PM
5737static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5738{
5739 int retval;
5740 bool wake;
5741
5742 retval = __ixgbe_shutdown(pdev, &wake);
5743 if (retval)
5744 return retval;
5745
5746 if (wake) {
5747 pci_prepare_to_sleep(pdev);
5748 } else {
5749 pci_wake_from_d3(pdev, false);
5750 pci_set_power_state(pdev, PCI_D3hot);
5751 }
b3c8b4ba
AD		 5752
5753 return 0;
5754}
9d8d05ae 5755#endif /* CONFIG_PM */
b3c8b4ba
AD		 5756
5757static void ixgbe_shutdown(struct pci_dev *pdev)
5758{
9d8d05ae
RW		 5759 bool wake;
5760
5761 __ixgbe_shutdown(pdev, &wake);
5762
5763 if (system_state == SYSTEM_POWER_OFF) {
5764 pci_wake_from_d3(pdev, wake);
5765 pci_set_power_state(pdev, PCI_D3hot);
5766 }
b3c8b4ba
AD		 5767}
5768
9a799d71
AK		 5769/**
5770 * ixgbe_update_stats - Update the board statistics counters.
5771 * @adapter: board private structure
5772 **/
5773void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5774{
2d86f139 5775 struct net_device *netdev = adapter->netdev;
9a799d71 5776 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5777 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5778 u64 total_mpc = 0;
5779 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5780 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5781 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5782 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5783#ifdef IXGBE_FCOE
5784 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5785 unsigned int cpu;
5786 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5787#endif /* IXGBE_FCOE */
9a799d71 5788
d08935c2
DS		 5789 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5790 test_bit(__IXGBE_RESETTING, &adapter->state))
5791 return;
5792
94b982b2 5793 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5794 u64 rsc_count = 0;
94b982b2 5795 u64 rsc_flush = 0;
d51019a4
PW		 5796 for (i = 0; i < 16; i++)
5797 adapter->hw_rx_no_dma_resources +=
7ca647bd 5798 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5799 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5800 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5801 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5802 }
5803 adapter->rsc_total_count = rsc_count;
5804 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5805 }
5806
5b7da515
AD		 5807 for (i = 0; i < adapter->num_rx_queues; i++) {
5808 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5809 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5810 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5811 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5812 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5813 bytes += rx_ring->stats.bytes;
5814 packets += rx_ring->stats.packets;
5815 }
5816 adapter->non_eop_descs = non_eop_descs;
5817 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5818 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5819 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5820 netdev->stats.rx_bytes = bytes;
5821 netdev->stats.rx_packets = packets;
5822
5823 bytes = 0;
5824 packets = 0;
7ca3bc58 5825 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5826 for (i = 0; i < adapter->num_tx_queues; i++) {
5827 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5828 restart_queue += tx_ring->tx_stats.restart_queue;
5829 tx_busy += tx_ring->tx_stats.tx_busy;
5830 bytes += tx_ring->stats.bytes;
5831 packets += tx_ring->stats.packets;
5832 }
eb985f09 5833 adapter->restart_queue = restart_queue;
5b7da515
AD		 5834 adapter->tx_busy = tx_busy;
5835 netdev->stats.tx_bytes = bytes;
5836 netdev->stats.tx_packets = packets;
7ca3bc58 5837
7ca647bd 5838 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5839
5840 /* 8 register reads */
6f11eef7
AV		 5841 for (i = 0; i < 8; i++) {
5842 /* for packet buffers not used, the register should read 0 */
5843 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5844 missed_rx += mpc;
7ca647bd
JP		 5845 hwstats->mpc[i] += mpc;
5846 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5847 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5848 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5849 switch (hw->mac.type) {
5850 case ixgbe_mac_82598EB:
1a70db4b
ET		 5851 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5852 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5853 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5854 hwstats->pxonrxc[i] +=
5855 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5856 break;
5857 case ixgbe_mac_82599EB:
b93a2226 5858 case ixgbe_mac_X540:
bd508178
AD		 5859 hwstats->pxonrxc[i] +=
5860 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5861 break;
5862 default:
5863 break;
e8e26350 5864 }
6f11eef7 5865 }
1a70db4b
ET		 5866
5867 /*16 register reads */
5868 for (i = 0; i < 16; i++) {
5869 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5870 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5871 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5872 (hw->mac.type == ixgbe_mac_X540)) {
5873 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5874 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5875 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5876 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5877 }
5878 }
5879
7ca647bd 5880 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5881 /* work around hardware counting issue */
7ca647bd 5882 hwstats->gprc -= missed_rx;
6f11eef7 5883
c84d324c
JF		 5884 ixgbe_update_xoff_received(adapter);
5885
6f11eef7 5886 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5887 switch (hw->mac.type) {
5888 case ixgbe_mac_82598EB:
5889 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5890 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5891 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5892 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5893 break;
b93a2226 5894 case ixgbe_mac_X540:
58f6bcf9
ET		 5895 /* OS2BMC stats are X540 only*/
5896 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5897 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5898 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5899 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5900 case ixgbe_mac_82599EB:
7ca647bd 5901 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5902 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5903 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5904 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5905 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5906 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5907 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5908 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5909 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5910#ifdef IXGBE_FCOE
7ca647bd
JP		 5911 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5912 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5913 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5914 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5915 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5916 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5917 /* Add up per cpu counters for total ddp aloc fail */
5918 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5919 for_each_possible_cpu(cpu) {
5920 fcoe_noddp_counts_sum +=
5921 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5922 fcoe_noddp_ext_buff_counts_sum +=
5923 *per_cpu_ptr(fcoe->
5924 pcpu_noddp_ext_buff, cpu);
5925 }
5926 }
5927 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5928 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5929#endif /* IXGBE_FCOE */
bd508178
AD		 5930 break;
5931 default:
5932 break;
e8e26350 5933 }
9a799d71 5934 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5935 hwstats->bprc += bprc;
5936 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5937 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5938 hwstats->mprc -= bprc;
5939 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5940 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5941 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5942 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5943 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5944 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5945 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5946 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5947 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5948 hwstats->lxontxc += lxon;
6f11eef7 5949 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5950 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5951 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5952 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5953 /*
5954 * 82598 errata - tx of flow control packets is included in tx counters
5955 */
5956 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5957 hwstats->gptc -= xon_off_tot;
5958 hwstats->mptc -= xon_off_tot;
5959 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5960 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5961 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5962 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5963 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5964 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5965 hwstats->ptc64 -= xon_off_tot;
5966 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5967 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5968 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5969 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5970 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5971 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5972
5973 /* Fill out the OS statistics structure */
7ca647bd 5974 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5975
5976 /* Rx Errors */
7ca647bd 5977 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5978 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5979 netdev->stats.rx_length_errors = hwstats->rlec;
5980 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5981 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5982}
5983
5984/**
d034acf1
AD		 5985 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5986 * @adapter - pointer to the device adapter structure
9a799d71 5987 **/
d034acf1 5988static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5989{
cf8280ee 5990 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5991 int i;
cf8280ee 5992
d034acf1
AD		 5993 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5994 return;
5995
5996 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5997
d034acf1 5998 /* if interface is down do nothing */
fe49f04a 5999 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6000 return;
6001
6002 /* do nothing if we are not using signature filters */
6003 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6004 return;
6005
6006 adapter->fdir_overflow++;
6007
93c52dd0
AD		 6008 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6009 for (i = 0; i < adapter->num_tx_queues; i++)
6010 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 6011 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6012 /* re-enable flow director interrupts */
6013 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6014 } else {
6015 e_err(probe, "failed to finish FDIR re-initialization, "
6016 "ignored adding FDIR ATR filters\n");
6017 }
93c52dd0
AD		 6018}
6019
6020/**
6021 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6022 * @adapter - pointer to the device adapter structure
6023 *
6024 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6025 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6026 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6027 * determine if a hang has occurred.
93c52dd0
AD		 6028 */
6029static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6030{
cf8280ee 6031 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6032 u64 eics = 0;
6033 int i;
cf8280ee 6034
93c52dd0
AD		 6035 /* If we're down or resetting, just bail */
6036 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6037 test_bit(__IXGBE_RESETTING, &adapter->state))
6038 return;
22d5a71b 6039
93c52dd0
AD		 6040 /* Force detection of hung controller */
6041 if (netif_carrier_ok(adapter->netdev)) {
6042 for (i = 0; i < adapter->num_tx_queues; i++)
6043 set_check_for_tx_hang(adapter->tx_ring[i]);
6044 }
22d5a71b 6045
fe49f04a
AD		 6046 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6047 /*
6048 * for legacy and MSI interrupts don't set any bits
6049 * that are enabled for EIAM, because this operation
6050 * would set *both* EIMS and EICS for any bit in EIAM
6051 */
6052 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6053 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6054 } else {
6055 /* get one bit for every active tx/rx interrupt vector */
6056 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6057 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6058 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6059 eics |= ((u64)1 << i);
6060 }
cf8280ee 6061 }
9a799d71 6062
93c52dd0 6063 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6064 ixgbe_irq_rearm_queues(adapter, eics);
6065
cf8280ee
JB		 6066}
6067
e8e26350 6068/**
93c52dd0
AD		 6069 * ixgbe_watchdog_update_link - update the link status
6070 * @adapter - pointer to the device adapter structure
6071 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6072 **/
93c52dd0 6073static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6074{
e8e26350 6075 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6076 u32 link_speed = adapter->link_speed;
6077 bool link_up = adapter->link_up;
c4cf55e5 6078 int i;
e8e26350 6079
93c52dd0
AD		 6080 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6081 return;
6082
6083 if (hw->mac.ops.check_link) {
6084 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6085 } else {
93c52dd0
AD		 6086 /* always assume link is up, if no check link function */
6087 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6088 link_up = true;
c4cf55e5 6089 }
93c52dd0
AD		 6090 if (link_up) {
6091 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6092 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6093 hw->mac.ops.fc_enable(hw, i);
6094 } else {
6095 hw->mac.ops.fc_enable(hw, 0);
6096 }
6097 }
6098
6099 if (link_up ||
6100 time_after(jiffies, (adapter->link_check_timeout +
6101 IXGBE_TRY_LINK_TIMEOUT))) {
6102 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6103 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6104 IXGBE_WRITE_FLUSH(hw);
6105 }
6106
6107 adapter->link_up = link_up;
6108 adapter->link_speed = link_speed;
e8e26350
PW		 6109}
6110
6111/**
93c52dd0
AD		 6112 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6113 * print link up message
6114 * @adapter - pointer to the device adapter structure
e8e26350 6115 **/
93c52dd0 6116static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6117{
93c52dd0 6118 struct net_device *netdev = adapter->netdev;
e8e26350 6119 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6120 u32 link_speed = adapter->link_speed;
6121 bool flow_rx, flow_tx;
e8e26350 6122
93c52dd0
AD		 6123 /* only continue if link was previously down */
6124 if (netif_carrier_ok(netdev))
a985b6c3 6125 return;
63d6e1d8 6126
93c52dd0 6127 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6128
93c52dd0
AD		 6129 switch (hw->mac.type) {
6130 case ixgbe_mac_82598EB: {
6131 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6132 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6133 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6134 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6135 }
6136 break;
6137 case ixgbe_mac_X540:
6138 case ixgbe_mac_82599EB: {
6139 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6140 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6141 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6142 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6143 }
6144 break;
6145 default:
6146 flow_tx = false;
6147 flow_rx = false;
6148 break;
e8e26350 6149 }
93c52dd0
AD		 6150 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6151 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6152 "10 Gbps" :
6153 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6154 "1 Gbps" :
6155 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6156 "100 Mbps" :
6157 "unknown speed"))),
6158 ((flow_rx && flow_tx) ? "RX/TX" :
6159 (flow_rx ? "RX" :
6160 (flow_tx ? "TX" : "None"))));
e8e26350 6161
93c52dd0 6162 netif_carrier_on(netdev);
93c52dd0 6163 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 6164}
6165
c4cf55e5 6166/**
93c52dd0
AD		 6167 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6168 * print link down message
6169 * @adapter - pointer to the adapter structure
c4cf55e5 6170 **/
93c52dd0 6171static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6172{
cf8280ee 6173 struct net_device *netdev = adapter->netdev;
c4cf55e5 6174 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6175
93c52dd0
AD		 6176 adapter->link_up = false;
6177 adapter->link_speed = 0;
cf8280ee 6178
93c52dd0
AD		 6179 /* only continue if link was up previously */
6180 if (!netif_carrier_ok(netdev))
6181 return;
264857b8 6182
93c52dd0
AD		 6183 /* poll for SFP+ cable when link is down */
6184 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6185 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6186
93c52dd0
AD		 6187 e_info(drv, "NIC Link is Down\n");
6188 netif_carrier_off(netdev);
6189}
e8e26350 6190
93c52dd0
AD		 6191/**
6192 * ixgbe_watchdog_flush_tx - flush queues on link down
6193 * @adapter - pointer to the device adapter structure
6194 **/
6195static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6196{
c4cf55e5 6197 int i;
93c52dd0 6198 int some_tx_pending = 0;
c4cf55e5 6199
93c52dd0 6200 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6201 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6202 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6203 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6204 some_tx_pending = 1;
6205 break;
6206 }
6207 }
6208
6209 if (some_tx_pending) {
6210 /* We've lost link, so the controller stops DMA,
6211 * but we've got queued Tx work that's never going
6212 * to get done, so reset controller to flush Tx.
6213 * (Do the reset outside of interrupt context).
6214 */
c83c6cbd 6215 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6216 }
c4cf55e5 6217 }
c4cf55e5
PWJ		 6218}
6219
a985b6c3
GR		 6220static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6221{
6222 u32 ssvpc;
6223
6224 /* Do not perform spoof check for 82598 */
6225 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6226 return;
6227
6228 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6229
6230 /*
6231 * ssvpc register is cleared on read, if zero then no
6232 * spoofed packets in the last interval.
6233 */
6234 if (!ssvpc)
6235 return;
6236
6237 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6238}
6239
93c52dd0
AD		 6240/**
6241 * ixgbe_watchdog_subtask - check and bring link up
6242 * @adapter - pointer to the device adapter structure
6243 **/
6244static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6245{
6246 /* if interface is down do nothing */
7edebf9a
ET		 6247 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6248 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6249 return;
6250
6251 ixgbe_watchdog_update_link(adapter);
6252
6253 if (adapter->link_up)
6254 ixgbe_watchdog_link_is_up(adapter);
6255 else
6256 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6257
a985b6c3 6258 ixgbe_spoof_check(adapter);
9a799d71 6259 ixgbe_update_stats(adapter);
93c52dd0
AD		 6260
6261 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6262}
10eec955 6263
cf8280ee 6264/**
7086400d
AD		 6265 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6266 * @adapter - the ixgbe adapter structure
cf8280ee 6267 **/
7086400d 6268static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6269{
cf8280ee 6270 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6271 s32 err;
cf8280ee 6272
7086400d
AD		 6273 /* not searching for SFP so there is nothing to do here */
6274 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6275 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6276 return;
10eec955 6277
7086400d
AD		 6278 /* someone else is in init, wait until next service event */
6279 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6280 return;
cf8280ee 6281
7086400d
AD		 6282 err = hw->phy.ops.identify_sfp(hw);
6283 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6284 goto sfp_out;
264857b8 6285
7086400d
AD		 6286 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6287 /* If no cable is present, then we need to reset
6288 * the next time we find a good cable. */
6289 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6290 }
9a799d71 6291
7086400d
AD		 6292 /* exit on error */
6293 if (err)
6294 goto sfp_out;
e8e26350 6295
7086400d
AD		 6296 /* exit if reset not needed */
6297 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6298 goto sfp_out;
9a799d71 6299
7086400d 6300 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6301
7086400d
AD		 6302 /*
6303 * A module may be identified correctly, but the EEPROM may not have
6304 * support for that module. setup_sfp() will fail in that case, so
6305 * we should not allow that module to load.
6306 */
6307 if (hw->mac.type == ixgbe_mac_82598EB)
6308 err = hw->phy.ops.reset(hw);
6309 else
6310 err = hw->mac.ops.setup_sfp(hw);
6311
6312 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6313 goto sfp_out;
6314
6315 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6316 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6317
6318sfp_out:
6319 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6320
6321 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6322 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6323 e_dev_err("failed to initialize because an unsupported "
6324 "SFP+ module type was detected.\n");
6325 e_dev_err("Reload the driver after installing a "
6326 "supported module.\n");
6327 unregister_netdev(adapter->netdev);
bc59fcda 6328 }
7086400d 6329}
bc59fcda 6330
7086400d
AD		 6331/**
6332 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6333 * @adapter - the ixgbe adapter structure
6334 **/
6335static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6336{
6337 struct ixgbe_hw *hw = &adapter->hw;
6338 u32 autoneg;
6339 bool negotiation;
6340
6341 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6342 return;
6343
6344 /* someone else is in init, wait until next service event */
6345 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6346 return;
6347
6348 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6349
6350 autoneg = hw->phy.autoneg_advertised;
6351 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6352 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6353 if (hw->mac.ops.setup_link)
6354 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6355
6356 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6357 adapter->link_check_timeout = jiffies;
6358 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6359}
6360
83c61fa9
GR		 6361#ifdef CONFIG_PCI_IOV
6362static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6363{
6364 int vf;
6365 struct ixgbe_hw *hw = &adapter->hw;
6366 struct net_device *netdev = adapter->netdev;
6367 u32 gpc;
6368 u32 ciaa, ciad;
6369
6370 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6371 if (gpc) /* If incrementing then no need for the check below */
6372 return;
6373 /*
6374 * Check to see if a bad DMA write target from an errant or
6375 * malicious VF has caused a PCIe error. If so then we can
6376 * issue a VFLR to the offending VF(s) and then resume without
6377 * requesting a full slot reset.
6378 */
6379
6380 for (vf = 0; vf < adapter->num_vfs; vf++) {
6381 ciaa = (vf << 16) | 0x80000000;
6382 /* 32 bit read so align, we really want status at offset 6 */
6383 ciaa |= PCI_COMMAND;
6384 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6385 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6386 ciaa &= 0x7FFFFFFF;
6387 /* disable debug mode asap after reading data */
6388 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6389 /* Get the upper 16 bits which will be the PCI status reg */
6390 ciad >>= 16;
6391 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6392 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6393 /* Issue VFLR */
6394 ciaa = (vf << 16) | 0x80000000;
6395 ciaa |= 0xA8;
6396 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6397 ciad = 0x00008000; /* VFLR */
6398 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6399 ciaa &= 0x7FFFFFFF;
6400 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6401 }
6402 }
6403}
6404
6405#endif
7086400d
AD		 6406/**
6407 * ixgbe_service_timer - Timer Call-back
6408 * @data: pointer to adapter cast into an unsigned long
6409 **/
6410static void ixgbe_service_timer(unsigned long data)
6411{
6412 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6413 unsigned long next_event_offset;
83c61fa9 6414 bool ready = true;
7086400d 6415
83c61fa9
GR		 6416#ifdef CONFIG_PCI_IOV
6417 ready = false;
6418
6419 /*
6420 * don't bother with SR-IOV VF DMA hang check if there are
6421 * no VFs or the link is down
6422 */
6423 if (!adapter->num_vfs ||
6424 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6425 ready = true;
6426 goto normal_timer_service;
6427 }
6428
6429 /* If we have VFs allocated then we must check for DMA hangs */
6430 ixgbe_check_for_bad_vf(adapter);
6431 next_event_offset = HZ / 50;
6432 adapter->timer_event_accumulator++;
6433
6434 if (adapter->timer_event_accumulator >= 100) {
6435 ready = true;
6436 adapter->timer_event_accumulator = 0;
6437 }
6438
6439 goto schedule_event;
6440
6441normal_timer_service:
6442#endif
7086400d
AD		 6443 /* poll faster when waiting for link */
6444 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6445 next_event_offset = HZ / 10;
6446 else
6447 next_event_offset = HZ * 2;
6448
83c61fa9
GR		 6449#ifdef CONFIG_PCI_IOV
6450schedule_event:
6451#endif
7086400d
AD		 6452 /* Reset the timer */
6453 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6454
83c61fa9
GR		 6455 if (ready)
6456 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6457}
6458
c83c6cbd
AD		 6459static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6460{
6461 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6462 return;
6463
6464 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6465
6466 /* If we're already down or resetting, just bail */
6467 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6468 test_bit(__IXGBE_RESETTING, &adapter->state))
6469 return;
6470
6471 ixgbe_dump(adapter);
6472 netdev_err(adapter->netdev, "Reset adapter\n");
6473 adapter->tx_timeout_count++;
6474
6475 ixgbe_reinit_locked(adapter);
6476}
6477
7086400d
AD		 6478/**
6479 * ixgbe_service_task - manages and runs subtasks
6480 * @work: pointer to work_struct containing our data
6481 **/
6482static void ixgbe_service_task(struct work_struct *work)
6483{
6484 struct ixgbe_adapter *adapter = container_of(work,
6485 struct ixgbe_adapter,
6486 service_task);
6487
c83c6cbd 6488 ixgbe_reset_subtask(adapter);
7086400d
AD		 6489 ixgbe_sfp_detection_subtask(adapter);
6490 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6491 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6492 ixgbe_watchdog_subtask(adapter);
d034acf1 6493 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6494 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6495
6496 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6497}
6498
897ab156
AD		 6499void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6500 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6501{
6502 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6503 u16 i = tx_ring->next_to_use;
9a799d71 6504
e4f74028 6505 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
9a799d71 6506
897ab156
AD		 6507 i++;
6508 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6509
897ab156
AD		 6510 /* set bits to identify this as an advanced context descriptor */
6511 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6512
897ab156
AD		 6513 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6514 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6515 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6516 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6517}
9a799d71 6518
897ab156
AD		 6519static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6520 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6521{
6522 int err;
6523 u32 vlan_macip_lens, type_tucmd;
6524 u32 mss_l4len_idx, l4len;
9a799d71 6525
897ab156
AD		 6526 if (!skb_is_gso(skb))
6527 return 0;
9a799d71 6528
897ab156
AD		 6529 if (skb_header_cloned(skb)) {
6530 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6531 if (err)
6532 return err;
9a799d71 6533 }
9a799d71 6534
897ab156
AD		 6535 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6536 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6537
6538 if (protocol == __constant_htons(ETH_P_IP)) {
6539 struct iphdr *iph = ip_hdr(skb);
6540 iph->tot_len = 0;
6541 iph->check = 0;
6542 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6543 iph->daddr, 0,
6544 IPPROTO_TCP,
6545 0);
6546 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6547 } else if (skb_is_gso_v6(skb)) {
6548 ipv6_hdr(skb)->payload_len = 0;
6549 tcp_hdr(skb)->check =
6550 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6551 &ipv6_hdr(skb)->daddr,
6552 0, IPPROTO_TCP, 0);
6553 }
6554
6555 l4len = tcp_hdrlen(skb);
6556 *hdr_len = skb_transport_offset(skb) + l4len;
6557
6558 /* mss_l4len_id: use 1 as index for TSO */
6559 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6560 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6561 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6562
6563 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6564 vlan_macip_lens = skb_network_header_len(skb);
6565 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6566 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6567
6568 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6569 mss_l4len_idx);
6570
6571 return 1;
6572}
6573
6574static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6575 struct sk_buff *skb, u32 tx_flags,
6576 __be16 protocol)
7ca647bd 6577{
897ab156
AD		 6578 u32 vlan_macip_lens = 0;
6579 u32 mss_l4len_idx = 0;
6580 u32 type_tucmd = 0;
7ca647bd 6581
897ab156 6582 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6583 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6584 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6585 return false;
6586 } else {
6587 u8 l4_hdr = 0;
6588 switch (protocol) {
6589 case __constant_htons(ETH_P_IP):
6590 vlan_macip_lens |= skb_network_header_len(skb);
6591 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6592 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6593 break;
897ab156
AD		 6594 case __constant_htons(ETH_P_IPV6):
6595 vlan_macip_lens |= skb_network_header_len(skb);
6596 l4_hdr = ipv6_hdr(skb)->nexthdr;
6597 break;
6598 default:
6599 if (unlikely(net_ratelimit())) {
6600 dev_warn(tx_ring->dev,
6601 "partial checksum but proto=%x!\n",
6602 skb->protocol);
6603 }
7ca647bd
JP		 6604 break;
6605 }
897ab156
AD		 6606
6607 switch (l4_hdr) {
7ca647bd 6608 case IPPROTO_TCP:
897ab156
AD		 6609 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6610 mss_l4len_idx = tcp_hdrlen(skb) <<
6611 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6612 break;
6613 case IPPROTO_SCTP:
897ab156
AD		 6614 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6615 mss_l4len_idx = sizeof(struct sctphdr) <<
6616 IXGBE_ADVTXD_L4LEN_SHIFT;
6617 break;
6618 case IPPROTO_UDP:
6619 mss_l4len_idx = sizeof(struct udphdr) <<
6620 IXGBE_ADVTXD_L4LEN_SHIFT;
6621 break;
6622 default:
6623 if (unlikely(net_ratelimit())) {
6624 dev_warn(tx_ring->dev,
6625 "partial checksum but l4 proto=%x!\n",
6626 skb->protocol);
6627 }
7ca647bd
JP		 6628 break;
6629 }
7ca647bd
JP		 6630 }
6631
897ab156
AD		 6632 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6633 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6634
897ab156
AD		 6635 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6636 type_tucmd, mss_l4len_idx);
9a799d71 6637
897ab156 6638 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6639}
6640
d3d00239 6641static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6642{
d3d00239
AD		 6643 /* set type for advanced descriptor with frame checksum insertion */
6644 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6645 IXGBE_ADVTXD_DCMD_IFCS |
6646 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6647
d3d00239 6648 /* set HW vlan bit if vlan is present */
66f32a8b 6649 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6650 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6651
d3d00239
AD		 6652 /* set segmentation enable bits for TSO/FSO */
6653#ifdef IXGBE_FCOE
6654 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6655#else
6656 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6657#endif
6658 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6659
d3d00239
AD		 6660 return cmd_type;
6661}
9a799d71 6662
d3d00239
AD		 6663static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6664{
6665 __le32 olinfo_status =
6666 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6667
d3d00239
AD		 6668 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6669 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6670 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6671 /* enble IPv4 checksum for TSO */
6672 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6673 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6674 }
6675
d3d00239
AD		 6676 /* enable L4 checksum for TSO and TX checksum offload */
6677 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6678 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6679
d3d00239
AD		 6680#ifdef IXGBE_FCOE
6681 /* use index 1 context for FCOE/FSO */
6682 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6683 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6684 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6685
d3d00239 6686#endif
7f9643fd
AD		 6687 /*
6688 * Check Context must be set if Tx switch is enabled, which it
6689 * always is for case where virtual functions are running
6690 */
6691 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6692 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6693
d3d00239
AD		 6694 return olinfo_status;
6695}
44df32c5 6696
d3d00239
AD		 6697#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6698 IXGBE_TXD_CMD_RS)
6699
6700static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6701 struct sk_buff *skb,
6702 struct ixgbe_tx_buffer *first,
6703 u32 tx_flags,
6704 const u8 hdr_len)
6705{
6706 struct device *dev = tx_ring->dev;
6707 struct ixgbe_tx_buffer *tx_buffer_info;
6708 union ixgbe_adv_tx_desc *tx_desc;
6709 dma_addr_t dma;
6710 __le32 cmd_type, olinfo_status;
6711 struct skb_frag_struct *frag;
6712 unsigned int f = 0;
6713 unsigned int data_len = skb->data_len;
6714 unsigned int size = skb_headlen(skb);
6715 u32 offset = 0;
6716 u32 paylen = skb->len - hdr_len;
6717 u16 i = tx_ring->next_to_use;
6718 u16 gso_segs;
6719
6720#ifdef IXGBE_FCOE
6721 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6722 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6723 data_len -= sizeof(struct fcoe_crc_eof);
6724 } else {
6725 size -= sizeof(struct fcoe_crc_eof) - data_len;
6726 data_len = 0;
9a799d71
AK		 6727 }
6728 }
44df32c5 6729
d3d00239
AD		 6730#endif
6731 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6732 if (dma_mapping_error(dev, dma))
6733 goto dma_error;
8ad494b0 6734
d3d00239
AD		 6735 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6736 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6737
e4f74028 6738 tx_desc = IXGBE_TX_DESC(tx_ring, i);
e5a43549 6739
d3d00239
AD		 6740 for (;;) {
6741 while (size > IXGBE_MAX_DATA_PER_TXD) {
6742 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6743 tx_desc->read.cmd_type_len =
6744 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6745 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6746
d3d00239
AD		 6747 offset += IXGBE_MAX_DATA_PER_TXD;
6748 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6749
d3d00239
AD		 6750 tx_desc++;
6751 i++;
6752 if (i == tx_ring->count) {
e4f74028 6753 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6754 i = 0;
6755 }
6756 }
e5a43549 6757
e5a43549 6758 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6759 tx_buffer_info->length = offset + size;
6760 tx_buffer_info->tx_flags = tx_flags;
6761 tx_buffer_info->dma = dma;
9a799d71 6762
d3d00239
AD		 6763 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6764 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6765 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6766
d3d00239
AD		 6767 if (!data_len)
6768 break;
9a799d71 6769
d3d00239
AD		 6770 frag = &skb_shinfo(skb)->frags[f];
6771#ifdef IXGBE_FCOE
9e903e08 6772 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6773#else
9e903e08 6774 size = skb_frag_size(frag);
d3d00239
AD		 6775#endif
6776 data_len -= size;
6777 f++;
9a799d71 6778
d3d00239
AD		 6779 offset = 0;
6780 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6781
877749bf 6782 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6783 if (dma_mapping_error(dev, dma))
6784 goto dma_error;
9a799d71 6785
d3d00239
AD		 6786 tx_desc++;
6787 i++;
6788 if (i == tx_ring->count) {
e4f74028 6789 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6790 i = 0;
6791 }
6792 }
9a799d71 6793
d3d00239 6794 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6795
d3d00239
AD		 6796 i++;
6797 if (i == tx_ring->count)
6798 i = 0;
9a799d71 6799
d3d00239 6800 tx_ring->next_to_use = i;
eacd73f7 6801
d3d00239
AD		 6802 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6803 gso_segs = skb_shinfo(skb)->gso_segs;
6804#ifdef IXGBE_FCOE
6805 /* adjust for FCoE Sequence Offload */
6806 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6807 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6808 skb_shinfo(skb)->gso_size);
6809#endif /* IXGBE_FCOE */
6810 else
6811 gso_segs = 1;
9a799d71 6812
d3d00239
AD		 6813 /* multiply data chunks by size of headers */
6814 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6815 tx_buffer_info->gso_segs = gso_segs;
6816 tx_buffer_info->skb = skb;
9a799d71 6817
b2d96e0a
AD		 6818 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer_info->bytecount);
6819
d3d00239
AD		 6820 /* set the timestamp */
6821 first->time_stamp = jiffies;
9a799d71
AK		 6822
6823 /*
6824 * Force memory writes to complete before letting h/w
6825 * know there are new descriptors to fetch. (Only
6826 * applicable for weak-ordered memory model archs,
6827 * such as IA-64).
6828 */
6829 wmb();
6830
d3d00239
AD		 6831 /* set next_to_watch value indicating a packet is present */
6832 first->next_to_watch = tx_desc;
6833
6834 /* notify HW of packet */
84ea2591 6835 writel(i, tx_ring->tail);
d3d00239
AD		 6836
6837 return;
6838dma_error:
6839 dev_err(dev, "TX DMA map failed\n");
6840
6841 /* clear dma mappings for failed tx_buffer_info map */
6842 for (;;) {
6843 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6844 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6845 if (tx_buffer_info == first)
6846 break;
6847 if (i == 0)
6848 i = tx_ring->count;
6849 i--;
6850 }
6851
6852 dev_kfree_skb_any(skb);
6853
6854 tx_ring->next_to_use = i;
9a799d71
AK		 6855}
6856
69830529
AD		 6857static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6858 u32 tx_flags, __be16 protocol)
6859{
6860 struct ixgbe_q_vector *q_vector = ring->q_vector;
6861 union ixgbe_atr_hash_dword input = { .dword = 0 };
6862 union ixgbe_atr_hash_dword common = { .dword = 0 };
6863 union {
6864 unsigned char *network;
6865 struct iphdr *ipv4;
6866 struct ipv6hdr *ipv6;
6867 } hdr;
ee9e0f0b 6868 struct tcphdr *th;
905e4a41 6869 __be16 vlan_id;
c4cf55e5 6870
69830529
AD		 6871 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6872 if (!q_vector)
6873 return;
6874
6875 /* do nothing if sampling is disabled */
6876 if (!ring->atr_sample_rate)
d3ead241 6877 return;
c4cf55e5 6878
69830529 6879 ring->atr_count++;
c4cf55e5 6880
69830529
AD		 6881 /* snag network header to get L4 type and address */
6882 hdr.network = skb_network_header(skb);
6883
6884 /* Currently only IPv4/IPv6 with TCP is supported */
6885 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6886 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6887 (protocol != __constant_htons(ETH_P_IP) ||
6888 hdr.ipv4->protocol != IPPROTO_TCP))
6889 return;
ee9e0f0b
AD		 6890
6891 th = tcp_hdr(skb);
c4cf55e5 6892
66f32a8b
AD		 6893 /* skip this packet since it is invalid or the socket is closing */
6894 if (!th || th->fin)
69830529
AD		 6895 return;
6896
6897 /* sample on all syn packets or once every atr sample count */
6898 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6899 return;
6900
6901 /* reset sample count */
6902 ring->atr_count = 0;
6903
6904 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6905
6906 /*
6907 * src and dst are inverted, think how the receiver sees them
6908 *
6909 * The input is broken into two sections, a non-compressed section
6910 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6911 * is XORed together and stored in the compressed dword.
6912 */
6913 input.formatted.vlan_id = vlan_id;
6914
6915 /*
6916 * since src port and flex bytes occupy the same word XOR them together
6917 * and write the value to source port portion of compressed dword
6918 */
66f32a8b 6919 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6920 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6921 else
6922 common.port.src ^= th->dest ^ protocol;
6923 common.port.dst ^= th->source;
6924
6925 if (protocol == __constant_htons(ETH_P_IP)) {
6926 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6927 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6928 } else {
6929 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6930 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6931 hdr.ipv6->saddr.s6_addr32[1] ^
6932 hdr.ipv6->saddr.s6_addr32[2] ^
6933 hdr.ipv6->saddr.s6_addr32[3] ^
6934 hdr.ipv6->daddr.s6_addr32[0] ^
6935 hdr.ipv6->daddr.s6_addr32[1] ^
6936 hdr.ipv6->daddr.s6_addr32[2] ^
6937 hdr.ipv6->daddr.s6_addr32[3];
6938 }
c4cf55e5
PWJ		 6939
6940 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6941 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6942 input, common, ring->queue_index);
c4cf55e5
PWJ		 6943}
6944
63544e9c 6945static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6946{
fc77dc3c 6947 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6948 /* Herbert's original patch had:
6949 * smp_mb__after_netif_stop_queue();
6950 * but since that doesn't exist yet, just open code it. */
6951 smp_mb();
6952
6953 /* We need to check again in a case another CPU has just
6954 * made room available. */
7d4987de 6955 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6956 return -EBUSY;
6957
6958 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6959 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6960 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6961 return 0;
6962}
6963
82d4e46e 6964static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6965{
7d4987de 6966 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6967 return 0;
fc77dc3c 6968 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6969}
6970
09a3b1f8
SH		 6971static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6972{
6973 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6974 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6975 smp_processor_id();
56075a98 6976#ifdef IXGBE_FCOE
6440752c 6977 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6978
e5b64635
JF		 6979 if (((protocol == htons(ETH_P_FCOE)) ||
6980 (protocol == htons(ETH_P_FIP))) &&
6981 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6982 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6983 txq += adapter->ring_feature[RING_F_FCOE].mask;
6984 return txq;
56075a98
JF		 6985 }
6986#endif
6987
fdd3d631
KK		 6988 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6989 while (unlikely(txq >= dev->real_num_tx_queues))
6990 txq -= dev->real_num_tx_queues;
5f715823 6991 return txq;
fdd3d631 6992 }
c4cf55e5 6993
09a3b1f8
SH		 6994 return skb_tx_hash(dev, skb);
6995}
6996
fc77dc3c 6997netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6998 struct ixgbe_adapter *adapter,
6999 struct ixgbe_ring *tx_ring)
9a799d71 7000{
d3d00239 7001 struct ixgbe_tx_buffer *first;
5f715823 7002 int tso;
d3d00239 7003 u32 tx_flags = 0;
a535c30e
AD		 7004#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7005 unsigned short f;
7006#endif
a535c30e 7007 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7008 __be16 protocol = skb->protocol;
63544e9c 7009 u8 hdr_len = 0;
5e09a105 7010
a535c30e
AD		 7011 /*
7012 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7013 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7014 * + 2 desc gap to keep tail from touching head,
7015 * + 1 desc for context descriptor,
7016 * otherwise try next time
7017 */
7018#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7019 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7020 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7021#else
7022 count += skb_shinfo(skb)->nr_frags;
7023#endif
7024 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7025 tx_ring->tx_stats.tx_busy++;
7026 return NETDEV_TX_BUSY;
7027 }
7028
66f32a8b 7029 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7030 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7031 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7032 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7033 /* else if it is a SW VLAN check the next protocol and store the tag */
7034 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7035 struct vlan_hdr *vhdr, _vhdr;
7036 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7037 if (!vhdr)
7038 goto out_drop;
7039
7040 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7041 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7042 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7043 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7044 }
7045
9e0c5648
AD		 7046#ifdef CONFIG_PCI_IOV
7047 /*
7048 * Use the l2switch_enable flag - would be false if the DMA
7049 * Tx switch had been disabled.
7050 */
7051 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7052 tx_flags |= IXGBE_TX_FLAGS_TXSW;
7053
7054#endif
32701dc2 7055 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7056 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7057 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7058 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7059 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7060 tx_flags |= (skb->priority & 0x7) <<
7061 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7062 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7063 struct vlan_ethhdr *vhdr;
7064 if (skb_header_cloned(skb) &&
7065 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7066 goto out_drop;
7067 vhdr = (struct vlan_ethhdr *)skb->data;
7068 vhdr->h_vlan_TCI = htons(tx_flags >>
7069 IXGBE_TX_FLAGS_VLAN_SHIFT);
7070 } else {
7071 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7072 }
9a799d71 7073 }
eacd73f7 7074
a535c30e 7075 /* record the location of the first descriptor for this packet */
d3d00239 7076 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 7077
eacd73f7 7078#ifdef IXGBE_FCOE
66f32a8b
AD		 7079 /* setup tx offload for FCoE */
7080 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
7081 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 7082 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
7083 if (tso < 0)
7084 goto out_drop;
7085 else if (tso)
66f32a8b
AD		 7086 tx_flags |= IXGBE_TX_FLAGS_FSO |
7087 IXGBE_TX_FLAGS_FCOE;
7088 else
7089 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 7090
66f32a8b 7091 goto xmit_fcoe;
eacd73f7 7092 }
9a799d71 7093
66f32a8b
AD		 7094#endif /* IXGBE_FCOE */
7095 /* setup IPv4/IPv6 offloads */
7096 if (protocol == __constant_htons(ETH_P_IP))
7097 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 7098
66f32a8b
AD		 7099 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
7100 if (tso < 0)
897ab156 7101 goto out_drop;
66f32a8b
AD		 7102 else if (tso)
7103 tx_flags |= IXGBE_TX_FLAGS_TSO;
7104 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
7105 tx_flags |= IXGBE_TX_FLAGS_CSUM;
7106
7107 /* add the ATR filter if ATR is on */
7108 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7109 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7110
7111#ifdef IXGBE_FCOE
7112xmit_fcoe:
7113#endif /* IXGBE_FCOE */
d3d00239
AD		 7114 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
7115
7116 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7117
7118 return NETDEV_TX_OK;
897ab156
AD		 7119
7120out_drop:
7121 dev_kfree_skb_any(skb);
7122 return NETDEV_TX_OK;
9a799d71
AK		 7123}
7124
84418e3b
AD		 7125static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7126{
7127 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7128 struct ixgbe_ring *tx_ring;
7129
7130 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 7131 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7132}
7133
9a799d71
AK		 7134/**
7135 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7136 * @netdev: network interface device structure
7137 * @p: pointer to an address structure
7138 *
7139 * Returns 0 on success, negative on failure
7140 **/
7141static int ixgbe_set_mac(struct net_device *netdev, void *p)
7142{
7143 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7144 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7145 struct sockaddr *addr = p;
7146
7147 if (!is_valid_ether_addr(addr->sa_data))
7148 return -EADDRNOTAVAIL;
7149
7150 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7151 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7152
1cdd1ec8
GR		 7153 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7154 IXGBE_RAH_AV);
9a799d71
AK		 7155
7156 return 0;
7157}
7158
6b73e10d
BH		 7159static int
7160ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7161{
7162 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7163 struct ixgbe_hw *hw = &adapter->hw;
7164 u16 value;
7165 int rc;
7166
7167 if (prtad != hw->phy.mdio.prtad)
7168 return -EINVAL;
7169 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7170 if (!rc)
7171 rc = value;
7172 return rc;
7173}
7174
7175static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7176 u16 addr, u16 value)
7177{
7178 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7179 struct ixgbe_hw *hw = &adapter->hw;
7180
7181 if (prtad != hw->phy.mdio.prtad)
7182 return -EINVAL;
7183 return hw->phy.ops.write_reg(hw, addr, devad, value);
7184}
7185
7186static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7187{
7188 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7189
7190 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7191}
7192
0365e6e4
PW		 7193/**
7194 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7195 * netdev->dev_addrs
0365e6e4
PW		 7196 * @netdev: network interface device structure
7197 *
7198 * Returns non-zero on failure
7199 **/
7200static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7201{
7202 int err = 0;
7203 struct ixgbe_adapter *adapter = netdev_priv(dev);
7204 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7205
7206 if (is_valid_ether_addr(mac->san_addr)) {
7207 rtnl_lock();
7208 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7209 rtnl_unlock();
7210 }
7211 return err;
7212}
7213
7214/**
7215 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7216 * netdev->dev_addrs
0365e6e4
PW		 7217 * @netdev: network interface device structure
7218 *
7219 * Returns non-zero on failure
7220 **/
7221static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7222{
7223 int err = 0;
7224 struct ixgbe_adapter *adapter = netdev_priv(dev);
7225 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7226
7227 if (is_valid_ether_addr(mac->san_addr)) {
7228 rtnl_lock();
7229 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7230 rtnl_unlock();
7231 }
7232 return err;
7233}
7234
9a799d71
AK		 7235#ifdef CONFIG_NET_POLL_CONTROLLER
7236/*
7237 * Polling 'interrupt' - used by things like netconsole to send skbs
7238 * without having to re-enable interrupts. It's not called while
7239 * the interrupt routine is executing.
7240 */
7241static void ixgbe_netpoll(struct net_device *netdev)
7242{
7243 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7244 int i;
9a799d71 7245
1a647bd2
AD		 7246 /* if interface is down do nothing */
7247 if (test_bit(__IXGBE_DOWN, &adapter->state))
7248 return;
7249
9a799d71 7250 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7251 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7252 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7253 for (i = 0; i < num_q_vectors; i++) {
7254 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7255 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7256 }
7257 } else {
7258 ixgbe_intr(adapter->pdev->irq, netdev);
7259 }
9a799d71 7260 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7261}
7262#endif
7263
de1036b1
ED		 7264static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7265 struct rtnl_link_stats64 *stats)
7266{
7267 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7268 int i;
7269
1a51502b 7270 rcu_read_lock();
de1036b1 7271 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7272 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7273 u64 bytes, packets;
7274 unsigned int start;
7275
1a51502b
ED		 7276 if (ring) {
7277 do {
7278 start = u64_stats_fetch_begin_bh(&ring->syncp);
7279 packets = ring->stats.packets;
7280 bytes = ring->stats.bytes;
7281 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7282 stats->rx_packets += packets;
7283 stats->rx_bytes += bytes;
7284 }
de1036b1 7285 }
1ac9ad13
ED		 7286
7287 for (i = 0; i < adapter->num_tx_queues; i++) {
7288 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7289 u64 bytes, packets;
7290 unsigned int start;
7291
7292 if (ring) {
7293 do {
7294 start = u64_stats_fetch_begin_bh(&ring->syncp);
7295 packets = ring->stats.packets;
7296 bytes = ring->stats.bytes;
7297 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7298 stats->tx_packets += packets;
7299 stats->tx_bytes += bytes;
7300 }
7301 }
1a51502b 7302 rcu_read_unlock();
de1036b1
ED		 7303 /* following stats updated by ixgbe_watchdog_task() */
7304 stats->multicast = netdev->stats.multicast;
7305 stats->rx_errors = netdev->stats.rx_errors;
7306 stats->rx_length_errors = netdev->stats.rx_length_errors;
7307 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7308 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7309 return stats;
7310}
7311
8b1c0b24
JF		 7312/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7313 * #adapter: pointer to ixgbe_adapter
7314 * @tc: number of traffic classes currently enabled
7315 *
7316 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7317 * 802.1Q priority maps to a packet buffer that exists.
7318 */
7319static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7320{
7321 struct ixgbe_hw *hw = &adapter->hw;
7322 u32 reg, rsave;
7323 int i;
7324
7325 /* 82598 have a static priority to TC mapping that can not
7326 * be changed so no validation is needed.
7327 */
7328 if (hw->mac.type == ixgbe_mac_82598EB)
7329 return;
7330
7331 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7332 rsave = reg;
7333
7334 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7335 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7336
7337 /* If up2tc is out of bounds default to zero */
7338 if (up2tc > tc)
7339 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7340 }
7341
7342 if (reg != rsave)
7343 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7344
7345 return;
7346}
7347
7348
7349/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7350 * classes.
7351 *
7352 * @netdev: net device to configure
7353 * @tc: number of traffic classes to enable
7354 */
7355int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7356{
8b1c0b24
JF		 7357 struct ixgbe_adapter *adapter = netdev_priv(dev);
7358 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7359
e7589eab
JF		 7360 /* Multiple traffic classes requires multiple queues */
7361 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7362 e_err(drv, "Enable failed, needs MSI-X\n");
7363 return -EINVAL;
7364 }
8b1c0b24
JF		 7365
7366 /* Hardware supports up to 8 traffic classes */
4de2a022 7367 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7368 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7369 return -EINVAL;
7370
7371 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7372 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7373 * hardware is not flexible enough to do this dynamically.
7374 */
7375 if (netif_running(dev))
7376 ixgbe_close(dev);
7377 ixgbe_clear_interrupt_scheme(adapter);
7378
e7589eab 7379 if (tc) {
8b1c0b24 7380 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7381 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7382
7383 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7384 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7385
7386 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7387 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7388 } else {
8b1c0b24
JF		 7389 netdev_reset_tc(dev);
7390
e7589eab
JF		 7391 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7392
7393 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7394 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7395
7396 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7397 adapter->dcb_cfg.pfc_mode_enable = false;
7398 }
7399
8b1c0b24
JF		 7400 ixgbe_init_interrupt_scheme(adapter);
7401 ixgbe_validate_rtr(adapter, tc);
7402 if (netif_running(dev))
7403 ixgbe_open(dev);
7404
7405 return 0;
7406}
de1036b1 7407
082757af
DS		 7408void ixgbe_do_reset(struct net_device *netdev)
7409{
7410 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7411
7412 if (netif_running(netdev))
7413 ixgbe_reinit_locked(adapter);
7414 else
7415 ixgbe_reset(adapter);
7416}
7417
c8f44aff
MM		 7418static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7419 netdev_features_t data)
082757af
DS		 7420{
7421 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7422
7423#ifdef CONFIG_DCB
7424 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7425 data &= ~NETIF_F_HW_VLAN_RX;
7426#endif
7427
7428 /* return error if RXHASH is being enabled when RSS is not supported */
7429 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7430 data &= ~NETIF_F_RXHASH;
7431
7432 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7433 if (!(data & NETIF_F_RXCSUM))
7434 data &= ~NETIF_F_LRO;
7435
7436 /* Turn off LRO if not RSC capable or invalid ITR settings */
7437 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7438 data &= ~NETIF_F_LRO;
7439 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7440 (adapter->rx_itr_setting != 1 &&
7441 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7442 data &= ~NETIF_F_LRO;
7443 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7444 }
7445
7446 return data;
7447}
7448
c8f44aff
MM		 7449static int ixgbe_set_features(struct net_device *netdev,
7450 netdev_features_t data)
082757af
DS		 7451{
7452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7453 bool need_reset = false;
7454
082757af
DS		 7455 /* Make sure RSC matches LRO, reset if change */
7456 if (!!(data & NETIF_F_LRO) !=
7457 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7458 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7459 switch (adapter->hw.mac.type) {
7460 case ixgbe_mac_X540:
7461 case ixgbe_mac_82599EB:
7462 need_reset = true;
7463 break;
7464 default:
7465 break;
7466 }
7467 }
7468
7469 /*
7470 * Check if Flow Director n-tuple support was enabled or disabled. If
7471 * the state changed, we need to reset.
7472 */
7473 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7474 /* turn off ATR, enable perfect filters and reset */
7475 if (data & NETIF_F_NTUPLE) {
7476 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7477 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7478 need_reset = true;
7479 }
7480 } else if (!(data & NETIF_F_NTUPLE)) {
7481 /* turn off Flow Director, set ATR and reset */
7482 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7483 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7484 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7485 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7486 need_reset = true;
7487 }
7488
7489 if (need_reset)
7490 ixgbe_do_reset(netdev);
7491
7492 return 0;
7493
7494}
7495
0edc3527 7496static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7497 .ndo_open = ixgbe_open,
0edc3527 7498 .ndo_stop = ixgbe_close,
00829823 7499 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7500 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7501 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7502 .ndo_validate_addr = eth_validate_addr,
7503 .ndo_set_mac_address = ixgbe_set_mac,
7504 .ndo_change_mtu = ixgbe_change_mtu,
7505 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7506 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7507 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7508 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7509 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7510 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7511 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7512 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7513 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7514 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7515 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7516#ifdef CONFIG_NET_POLL_CONTROLLER
7517 .ndo_poll_controller = ixgbe_netpoll,
7518#endif
332d4a7d
YZ		 7519#ifdef IXGBE_FCOE
7520 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7521 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7522 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7523 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7524 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7525 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7526 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7527#endif /* IXGBE_FCOE */
082757af
DS		 7528 .ndo_set_features = ixgbe_set_features,
7529 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7530};
7531
1cdd1ec8
GR		 7532static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7533 const struct ixgbe_info *ii)
7534{
7535#ifdef CONFIG_PCI_IOV
7536 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7537
c6bda30a 7538 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7539 return;
7540
7541 /* The 82599 supports up to 64 VFs per physical function
7542 * but this implementation limits allocation to 63 so that
7543 * basic networking resources are still available to the
7544 * physical function
7545 */
7546 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7547 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7548#endif /* CONFIG_PCI_IOV */
7549}
7550
9a799d71
AK		 7551/**
7552 * ixgbe_probe - Device Initialization Routine
7553 * @pdev: PCI device information struct
7554 * @ent: entry in ixgbe_pci_tbl
7555 *
7556 * Returns 0 on success, negative on failure
7557 *
7558 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7559 * The OS initialization, configuring of the adapter private structure,
7560 * and a hardware reset occur.
7561 **/
7562static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7563 const struct pci_device_id *ent)
9a799d71
AK		 7564{
7565 struct net_device *netdev;
7566 struct ixgbe_adapter *adapter = NULL;
7567 struct ixgbe_hw *hw;
7568 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7569 static int cards_found;
7570 int i, err, pci_using_dac;
289700db 7571 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7572 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7573#ifdef IXGBE_FCOE
7574 u16 device_caps;
7575#endif
289700db 7576 u32 eec;
c23f5b6b 7577 u16 wol_cap;
9a799d71 7578
bded64a7
AG		 7579 /* Catch broken hardware that put the wrong VF device ID in
7580 * the PCIe SR-IOV capability.
7581 */
7582 if (pdev->is_virtfn) {
7583 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7584 pci_name(pdev), pdev->vendor, pdev->device);
7585 return -EINVAL;
7586 }
7587
9ce77666 7588 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7589 if (err)
7590 return err;
7591
1b507730
NN		 7592 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7593 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7594 pci_using_dac = 1;
7595 } else {
1b507730 7596 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7597 if (err) {
1b507730
NN		 7598 err = dma_set_coherent_mask(&pdev->dev,
7599 DMA_BIT_MASK(32));
9a799d71 7600 if (err) {
b8bc0421
DC		 7601 dev_err(&pdev->dev,
7602 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7603 goto err_dma;
7604 }
7605 }
7606 pci_using_dac = 0;
7607 }
7608
9ce77666 7609 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7610 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7611 if (err) {
b8bc0421
DC		 7612 dev_err(&pdev->dev,
7613 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7614 goto err_pci_reg;
7615 }
7616
19d5afd4 7617 pci_enable_pcie_error_reporting(pdev);
6fabd715 7618
9a799d71 7619 pci_set_master(pdev);
fb3b27bc 7620 pci_save_state(pdev);
9a799d71 7621
e901acd6
JF		 7622#ifdef CONFIG_IXGBE_DCB
7623 indices *= MAX_TRAFFIC_CLASS;
7624#endif
7625
c85a2618
JF		 7626 if (ii->mac == ixgbe_mac_82598EB)
7627 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7628 else
7629 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7630
e901acd6 7631#ifdef IXGBE_FCOE
c85a2618
JF		 7632 indices += min_t(unsigned int, num_possible_cpus(),
7633 IXGBE_MAX_FCOE_INDICES);
7634#endif
c85a2618 7635 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7636 if (!netdev) {
7637 err = -ENOMEM;
7638 goto err_alloc_etherdev;
7639 }
7640
9a799d71
AK		 7641 SET_NETDEV_DEV(netdev, &pdev->dev);
7642
9a799d71 7643 adapter = netdev_priv(netdev);
c60fbb00 7644 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7645
7646 adapter->netdev = netdev;
7647 adapter->pdev = pdev;
7648 hw = &adapter->hw;
7649 hw->back = adapter;
7650 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7651
05857980 7652 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7653 pci_resource_len(pdev, 0));
9a799d71
AK		 7654 if (!hw->hw_addr) {
7655 err = -EIO;
7656 goto err_ioremap;
7657 }
7658
7659 for (i = 1; i <= 5; i++) {
7660 if (pci_resource_len(pdev, i) == 0)
7661 continue;
7662 }
7663
0edc3527 7664 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7665 ixgbe_set_ethtool_ops(netdev);
9a799d71 7666 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7667 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7668
9a799d71
AK		 7669 adapter->bd_number = cards_found;
7670
9a799d71
AK		 7671 /* Setup hw api */
7672 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7673 hw->mac.type = ii->mac;
9a799d71 7674
c44ade9e
JB		 7675 /* EEPROM */
7676 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7677 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7678 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7679 if (!(eec & (1 << 8)))
7680 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7681
7682 /* PHY */
7683 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7684 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7685 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7686 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7687 hw->phy.mdio.mmds = 0;
7688 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7689 hw->phy.mdio.dev = netdev;
7690 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7691 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7692
8ca783ab 7693 ii->get_invariants(hw);
9a799d71
AK		 7694
7695 /* setup the private structure */
7696 err = ixgbe_sw_init(adapter);
7697 if (err)
7698 goto err_sw_init;
7699
e86bff0e 7700 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7701 switch (adapter->hw.mac.type) {
7702 case ixgbe_mac_82599EB:
7703 case ixgbe_mac_X540:
e86bff0e 7704 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7705 break;
7706 default:
7707 break;
7708 }
e86bff0e 7709
bf069c97
DS		 7710 /*
7711 * If there is a fan on this device and it has failed log the
7712 * failure.
7713 */
7714 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7715 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7716 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7717 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7718 }
7719
8ef78adc
PWJ		 7720 if (allow_unsupported_sfp)
7721 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7722
c44ade9e 7723 /* reset_hw fills in the perm_addr as well */
119fc60a 7724 hw->phy.reset_if_overtemp = true;
c44ade9e 7725 err = hw->mac.ops.reset_hw(hw);
119fc60a 7726 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7727 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7728 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7729 err = 0;
7730 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7731 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7732 "module type was detected.\n");
7733 e_dev_err("Reload the driver after installing a supported "
7734 "module.\n");
04f165ef
PW		 7735 goto err_sw_init;
7736 } else if (err) {
849c4542 7737 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7738 goto err_sw_init;
7739 }
7740
1cdd1ec8
GR		 7741 ixgbe_probe_vf(adapter, ii);
7742
396e799c 7743 netdev->features = NETIF_F_SG |
e8e9f696 7744 NETIF_F_IP_CSUM |
082757af 7745 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7746 NETIF_F_HW_VLAN_TX |
7747 NETIF_F_HW_VLAN_RX |
082757af
DS		 7748 NETIF_F_HW_VLAN_FILTER |
7749 NETIF_F_TSO |
7750 NETIF_F_TSO6 |
082757af
DS		 7751 NETIF_F_RXHASH |
7752 NETIF_F_RXCSUM;
9a799d71 7753
082757af 7754 netdev->hw_features = netdev->features;
ad31c402 7755
58be7666
DS		 7756 switch (adapter->hw.mac.type) {
7757 case ixgbe_mac_82599EB:
7758 case ixgbe_mac_X540:
45a5ead0 7759 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7760 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7761 NETIF_F_NTUPLE;
58be7666
DS		 7762 break;
7763 default:
7764 break;
7765 }
45a5ead0 7766
ad31c402
JK		 7767 netdev->vlan_features |= NETIF_F_TSO;
7768 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7769 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7770 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7771 netdev->vlan_features |= NETIF_F_SG;
7772
01789349
JP		 7773 netdev->priv_flags |= IFF_UNICAST_FLT;
7774
1cdd1ec8
GR		 7775 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7776 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7777 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7778
7a6b6f51 7779#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7780 netdev->dcbnl_ops = &dcbnl_ops;
7781#endif
7782
eacd73f7 7783#ifdef IXGBE_FCOE
0d551589 7784 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7785 if (hw->mac.ops.get_device_caps) {
7786 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7787 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7788 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7789 }
7790 }
5e09d7f6
YZ		 7791 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7792 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7793 netdev->vlan_features |= NETIF_F_FSO;
7794 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7795 }
eacd73f7 7796#endif /* IXGBE_FCOE */
7b872a55 7797 if (pci_using_dac) {
9a799d71 7798 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7799 netdev->vlan_features |= NETIF_F_HIGHDMA;
7800 }
9a799d71 7801
082757af
DS		 7802 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7803 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7804 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7805 netdev->features |= NETIF_F_LRO;
7806
9a799d71 7807 /* make sure the EEPROM is good */
c44ade9e 7808 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7809 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7810 err = -EIO;
7811 goto err_eeprom;
7812 }
7813
7814 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7815 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7816
c44ade9e 7817 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7818 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7819 err = -EIO;
7820 goto err_eeprom;
7821 }
7822
7086400d
AD		 7823 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7824 (unsigned long) adapter);
9a799d71 7825
7086400d
AD		 7826 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7827 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7828
021230d4
AV		 7829 err = ixgbe_init_interrupt_scheme(adapter);
7830 if (err)
7831 goto err_sw_init;
9a799d71 7832
082757af
DS		 7833 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7834 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7835 netdev->features &= ~NETIF_F_RXHASH;
082757af 7836 }
67a74ee2 7837
c23f5b6b
ET		 7838 /* WOL not supported for all but the following */
7839 adapter->wol = 0;
e8e26350 7840 switch (pdev->device) {
0b077fea 7841 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7842 /* Only these subdevice supports WOL */
7843 switch (pdev->subsystem_device) {
7844 case IXGBE_SUBDEV_ID_82599_560FLR:
7845 /* only support first port */
7846 if (hw->bus.func != 0)
7847 break;
7848 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7849 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7850 break;
7851 }
0b077fea 7852 break;
50d6c681
AD		 7853 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7854 /* All except this subdevice support WOL */
0b077fea 7855 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7856 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7857 break;
e8e26350 7858 case IXGBE_DEV_ID_82599_KX4:
9417c464 7859 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7860 break;
c23f5b6b
ET		 7861 case IXGBE_DEV_ID_X540T:
7862 /* Check eeprom to see if it is enabled */
7863 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7864 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7865
7866 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7867 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7868 (hw->bus.func == 0)))
7869 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7870 break;
7871 }
e8e26350
PW		 7872 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7873
15e5209f
ET		 7874 /* save off EEPROM version number */
7875 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7876 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7877
04f165ef
PW		 7878 /* pick up the PCI bus settings for reporting later */
7879 hw->mac.ops.get_bus_info(hw);
7880
9a799d71 7881 /* print bus type/speed/width info */
849c4542 7882 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7883 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7884 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7885 "Unknown"),
7886 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7887 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7888 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7889 "Unknown"),
7890 netdev->dev_addr);
289700db
DS		 7891
7892 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7893 if (err)
9fe93afd 7894 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7895 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7896 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7897 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7898 part_str);
e8e26350 7899 else
289700db
DS		 7900 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7901 hw->mac.type, hw->phy.type, part_str);
9a799d71 7902
e8e26350 7903 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7904 e_dev_warn("PCI-Express bandwidth available for this card is "
7905 "not sufficient for optimal performance.\n");
7906 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7907 "is required.\n");
0c254d86
AK		 7908 }
7909
9a799d71 7910 /* reset the hardware with the new settings */
794caeb2 7911 err = hw->mac.ops.start_hw(hw);
c44ade9e 7912
794caeb2
PWJ		 7913 if (err == IXGBE_ERR_EEPROM_VERSION) {
7914 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7915 e_dev_warn("This device is a pre-production adapter/LOM. "
7916 "Please be aware there may be issues associated "
7917 "with your hardware. If you are experiencing "
7918 "problems please contact your Intel or hardware "
7919 "representative who provided you with this "
7920 "hardware.\n");
794caeb2 7921 }
9a799d71
AK		 7922 strcpy(netdev->name, "eth%d");
7923 err = register_netdev(netdev);
7924 if (err)
7925 goto err_register;
7926
93d3ce8f
ET		 7927 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7928 if (hw->mac.ops.disable_tx_laser &&
7929 ((hw->phy.multispeed_fiber) ||
7930 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7931 (hw->mac.type == ixgbe_mac_82599EB))))
7932 hw->mac.ops.disable_tx_laser(hw);
7933
54386467
JB		 7934 /* carrier off reporting is important to ethtool even BEFORE open */
7935 netif_carrier_off(netdev);
7936
5dd2d332 7937#ifdef CONFIG_IXGBE_DCA
652f093f 7938 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7939 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7940 ixgbe_setup_dca(adapter);
7941 }
7942#endif
1cdd1ec8 7943 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7944 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7945 for (i = 0; i < adapter->num_vfs; i++)
7946 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7947 }
7948
2466dd9c
JK		 7949 /* firmware requires driver version to be 0xFFFFFFFF
7950 * since os does not support feature
7951 */
9612de92 7952 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7953 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7954 0xFF);
9612de92 7955
0365e6e4
PW		 7956 /* add san mac addr to netdev */
7957 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7958
ea81875a 7959 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 7960 cards_found++;
7961 return 0;
7962
7963err_register:
5eba3699 7964 ixgbe_release_hw_control(adapter);
7a921c93 7965 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7966err_sw_init:
7967err_eeprom:
1cdd1ec8
GR		 7968 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7969 ixgbe_disable_sriov(adapter);
7086400d 7970 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7971 iounmap(hw->hw_addr);
7972err_ioremap:
7973 free_netdev(netdev);
7974err_alloc_etherdev:
e8e9f696
JP		 7975 pci_release_selected_regions(pdev,
7976 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7977err_pci_reg:
7978err_dma:
7979 pci_disable_device(pdev);
7980 return err;
7981}
7982
7983/**
7984 * ixgbe_remove - Device Removal Routine
7985 * @pdev: PCI device information struct
7986 *
7987 * ixgbe_remove is called by the PCI subsystem to alert the driver
7988 * that it should release a PCI device. The could be caused by a
7989 * Hot-Plug event, or because the driver is going to be removed from
7990 * memory.
7991 **/
7992static void __devexit ixgbe_remove(struct pci_dev *pdev)
7993{
c60fbb00
AD		 7994 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7995 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7996
7997 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7998 cancel_work_sync(&adapter->service_task);
9a799d71 7999
5dd2d332 8000#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8001 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8002 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8003 dca_remove_requester(&pdev->dev);
8004 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8005 }
8006
8007#endif
332d4a7d
YZ		 8008#ifdef IXGBE_FCOE
8009 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
8010 ixgbe_cleanup_fcoe(adapter);
8011
8012#endif /* IXGBE_FCOE */
0365e6e4
PW		 8013
8014 /* remove the added san mac */
8015 ixgbe_del_sanmac_netdev(netdev);
8016
c4900be0
DS		 8017 if (netdev->reg_state == NETREG_REGISTERED)
8018 unregister_netdev(netdev);
9a799d71 8019
c6bda30a
GR		 8020 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8021 if (!(ixgbe_check_vf_assignment(adapter)))
8022 ixgbe_disable_sriov(adapter);
8023 else
8024 e_dev_warn("Unloading driver while VFs are assigned "
8025 "- VFs will not be deallocated\n");
8026 }
1cdd1ec8 8027
7a921c93 8028 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8029
021230d4 8030 ixgbe_release_hw_control(adapter);
9a799d71
AK		 8031
8032 iounmap(adapter->hw.hw_addr);
9ce77666 8033 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8034 IORESOURCE_MEM));
9a799d71 8035
849c4542 8036 e_dev_info("complete\n");
021230d4 8037
9a799d71
AK		 8038 free_netdev(netdev);
8039
19d5afd4 8040 pci_disable_pcie_error_reporting(pdev);
6fabd715 8041
9a799d71
AK		 8042 pci_disable_device(pdev);
8043}
8044
8045/**
8046 * ixgbe_io_error_detected - called when PCI error is detected
8047 * @pdev: Pointer to PCI device
8048 * @state: The current pci connection state
8049 *
8050 * This function is called after a PCI bus error affecting
8051 * this device has been detected.
8052 */
8053static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8054 pci_channel_state_t state)
9a799d71 8055{
c60fbb00
AD		 8056 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8057 struct net_device *netdev = adapter->netdev;
9a799d71 8058
83c61fa9
GR		 8059#ifdef CONFIG_PCI_IOV
8060 struct pci_dev *bdev, *vfdev;
8061 u32 dw0, dw1, dw2, dw3;
8062 int vf, pos;
8063 u16 req_id, pf_func;
8064
8065 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8066 adapter->num_vfs == 0)
8067 goto skip_bad_vf_detection;
8068
8069 bdev = pdev->bus->self;
8070 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
8071 bdev = bdev->bus->self;
8072
8073 if (!bdev)
8074 goto skip_bad_vf_detection;
8075
8076 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8077 if (!pos)
8078 goto skip_bad_vf_detection;
8079
8080 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8081 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8082 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8083 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8084
8085 req_id = dw1 >> 16;
8086 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8087 if (!(req_id & 0x0080))
8088 goto skip_bad_vf_detection;
8089
8090 pf_func = req_id & 0x01;
8091 if ((pf_func & 1) == (pdev->devfn & 1)) {
8092 unsigned int device_id;
8093
8094 vf = (req_id & 0x7F) >> 1;
8095 e_dev_err("VF %d has caused a PCIe error\n", vf);
8096 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8097 "%8.8x\tdw3: %8.8x\n",
8098 dw0, dw1, dw2, dw3);
8099 switch (adapter->hw.mac.type) {
8100 case ixgbe_mac_82599EB:
8101 device_id = IXGBE_82599_VF_DEVICE_ID;
8102 break;
8103 case ixgbe_mac_X540:
8104 device_id = IXGBE_X540_VF_DEVICE_ID;
8105 break;
8106 default:
8107 device_id = 0;
8108 break;
8109 }
8110
8111 /* Find the pci device of the offending VF */
8112 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
8113 while (vfdev) {
8114 if (vfdev->devfn == (req_id & 0xFF))
8115 break;
8116 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
8117 device_id, vfdev);
8118 }
8119 /*
8120 * There's a slim chance the VF could have been hot plugged,
8121 * so if it is no longer present we don't need to issue the
8122 * VFLR. Just clean up the AER in that case.
8123 */
8124 if (vfdev) {
8125 e_dev_err("Issuing VFLR to VF %d\n", vf);
8126 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8127 }
8128
8129 pci_cleanup_aer_uncorrect_error_status(pdev);
8130 }
8131
8132 /*
8133 * Even though the error may have occurred on the other port
8134 * we still need to increment the vf error reference count for
8135 * both ports because the I/O resume function will be called
8136 * for both of them.
8137 */
8138 adapter->vferr_refcount++;
8139
8140 return PCI_ERS_RESULT_RECOVERED;
8141
8142skip_bad_vf_detection:
8143#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8144 netif_device_detach(netdev);
8145
3044b8d1
BL		 8146 if (state == pci_channel_io_perm_failure)
8147 return PCI_ERS_RESULT_DISCONNECT;
8148
9a799d71
AK		 8149 if (netif_running(netdev))
8150 ixgbe_down(adapter);
8151 pci_disable_device(pdev);
8152
b4617240 8153 /* Request a slot reset. */
9a799d71
AK		 8154 return PCI_ERS_RESULT_NEED_RESET;
8155}
8156
8157/**
8158 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8159 * @pdev: Pointer to PCI device
8160 *
8161 * Restart the card from scratch, as if from a cold-boot.
8162 */
8163static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8164{
c60fbb00 8165 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8166 pci_ers_result_t result;
8167 int err;
9a799d71 8168
9ce77666 8169 if (pci_enable_device_mem(pdev)) {
396e799c 8170 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8171 result = PCI_ERS_RESULT_DISCONNECT;
8172 } else {
8173 pci_set_master(pdev);
8174 pci_restore_state(pdev);
c0e1f68b 8175 pci_save_state(pdev);
9a799d71 8176
dd4d8ca6 8177 pci_wake_from_d3(pdev, false);
9a799d71 8178
6fabd715 8179 ixgbe_reset(adapter);
88512539 8180 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8181 result = PCI_ERS_RESULT_RECOVERED;
8182 }
8183
8184 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8185 if (err) {
849c4542
ET		 8186 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8187 "failed 0x%0x\n", err);
6fabd715
PWJ		 8188 /* non-fatal, continue */
8189 }
9a799d71 8190
6fabd715 8191 return result;
9a799d71
AK		 8192}
8193
8194/**
8195 * ixgbe_io_resume - called when traffic can start flowing again.
8196 * @pdev: Pointer to PCI device
8197 *
8198 * This callback is called when the error recovery driver tells us that
8199 * its OK to resume normal operation.
8200 */
8201static void ixgbe_io_resume(struct pci_dev *pdev)
8202{
c60fbb00
AD		 8203 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8204 struct net_device *netdev = adapter->netdev;
9a799d71 8205
83c61fa9
GR		 8206#ifdef CONFIG_PCI_IOV
8207 if (adapter->vferr_refcount) {
8208 e_info(drv, "Resuming after VF err\n");
8209 adapter->vferr_refcount--;
8210 return;
8211 }
8212
8213#endif
c7ccde0f
AD		 8214 if (netif_running(netdev))
8215 ixgbe_up(adapter);
9a799d71
AK		 8216
8217 netif_device_attach(netdev);
9a799d71
AK		 8218}
8219
8220static struct pci_error_handlers ixgbe_err_handler = {
8221 .error_detected = ixgbe_io_error_detected,
8222 .slot_reset = ixgbe_io_slot_reset,
8223 .resume = ixgbe_io_resume,
8224};
8225
8226static struct pci_driver ixgbe_driver = {
8227 .name = ixgbe_driver_name,
8228 .id_table = ixgbe_pci_tbl,
8229 .probe = ixgbe_probe,
8230 .remove = __devexit_p(ixgbe_remove),
8231#ifdef CONFIG_PM
8232 .suspend = ixgbe_suspend,
8233 .resume = ixgbe_resume,
8234#endif
8235 .shutdown = ixgbe_shutdown,
8236 .err_handler = &ixgbe_err_handler
8237};
8238
8239/**
8240 * ixgbe_init_module - Driver Registration Routine
8241 *
8242 * ixgbe_init_module is the first routine called when the driver is
8243 * loaded. All it does is register with the PCI subsystem.
8244 **/
8245static int __init ixgbe_init_module(void)
8246{
8247 int ret;
c7689578 8248 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8249 pr_info("%s\n", ixgbe_copyright);
9a799d71 8250
5dd2d332 8251#ifdef CONFIG_IXGBE_DCA
bd0362dd 8252 dca_register_notify(&dca_notifier);
bd0362dd 8253#endif
5dd2d332 8254
9a799d71
AK		 8255 ret = pci_register_driver(&ixgbe_driver);
8256 return ret;
8257}
b4617240 8258
9a799d71
AK		 8259module_init(ixgbe_init_module);
8260
8261/**
8262 * ixgbe_exit_module - Driver Exit Cleanup Routine
8263 *
8264 * ixgbe_exit_module is called just before the driver is removed
8265 * from memory.
8266 **/
8267static void __exit ixgbe_exit_module(void)
8268{
5dd2d332 8269#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8270 dca_unregister_notify(&dca_notifier);
8271#endif
9a799d71 8272 pci_unregister_driver(&ixgbe_driver);
1a51502b 8273 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8274}
bd0362dd 8275
5dd2d332 8276#ifdef CONFIG_IXGBE_DCA
bd0362dd 8277static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8278 void *p)
bd0362dd
JC		 8279{
8280 int ret_val;
8281
8282 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8283 __ixgbe_notify_dca);
bd0362dd
JC		 8284
8285 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8286}
b453368d 8287
5dd2d332 8288#endif /* CONFIG_IXGBE_DCA */
849c4542 8289
9a799d71
AK		 8290module_exit(ixgbe_exit_module);
8291
8292/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)