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ixgbevf: Fix broken trunk vlan
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 58#define MAJ 3
a38a104d 59#define MIN 4
c89c7112 60#define BUILD 8
75e3d3c6 61#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 62 __stringify(BUILD) "-k"
9c8eb720 63const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 64static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 66
67static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 68 [board_82598] = &ixgbe_82598_info,
e8e26350 69 [board_82599] = &ixgbe_82599_info,
fe15e8e1 70 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 71};
72
73/* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
a3aa1884 81static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
9a799d71
AK		 108 /* required last entry */
109 {0, }
110};
111MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
112
5dd2d332 113#ifdef CONFIG_IXGBE_DCA
bd0362dd 114static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 115 void *p);
bd0362dd
JC		 116static struct notifier_block dca_notifier = {
117 .notifier_call = ixgbe_notify_dca,
118 .next = NULL,
119 .priority = 0
120};
121#endif
122
1cdd1ec8
GR		 123#ifdef CONFIG_PCI_IOV
124static unsigned int max_vfs;
125module_param(max_vfs, uint, 0);
e8e9f696
JP		 126MODULE_PARM_DESC(max_vfs,
127 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 128#endif /* CONFIG_PCI_IOV */
129
9a799d71
AK		 130MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
131MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
132MODULE_LICENSE("GPL");
133MODULE_VERSION(DRV_VERSION);
134
135#define DEFAULT_DEBUG_LEVEL_SHIFT 3
136
7086400d
AD		 137static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
138{
139 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
140 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
141 schedule_work(&adapter->service_task);
142}
143
144static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
145{
146 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
147
148 /* flush memory to make sure state is correct before next watchog */
149 smp_mb__before_clear_bit();
150 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
151}
152
dcd79aeb
TI		 153struct ixgbe_reg_info {
154 u32 ofs;
155 char *name;
156};
157
158static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
159
160 /* General Registers */
161 {IXGBE_CTRL, "CTRL"},
162 {IXGBE_STATUS, "STATUS"},
163 {IXGBE_CTRL_EXT, "CTRL_EXT"},
164
165 /* Interrupt Registers */
166 {IXGBE_EICR, "EICR"},
167
168 /* RX Registers */
169 {IXGBE_SRRCTL(0), "SRRCTL"},
170 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
171 {IXGBE_RDLEN(0), "RDLEN"},
172 {IXGBE_RDH(0), "RDH"},
173 {IXGBE_RDT(0), "RDT"},
174 {IXGBE_RXDCTL(0), "RXDCTL"},
175 {IXGBE_RDBAL(0), "RDBAL"},
176 {IXGBE_RDBAH(0), "RDBAH"},
177
178 /* TX Registers */
179 {IXGBE_TDBAL(0), "TDBAL"},
180 {IXGBE_TDBAH(0), "TDBAH"},
181 {IXGBE_TDLEN(0), "TDLEN"},
182 {IXGBE_TDH(0), "TDH"},
183 {IXGBE_TDT(0), "TDT"},
184 {IXGBE_TXDCTL(0), "TXDCTL"},
185
186 /* List Terminator */
187 {}
188};
189
190
191/*
192 * ixgbe_regdump - register printout routine
193 */
194static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
195{
196 int i = 0, j = 0;
197 char rname[16];
198 u32 regs[64];
199
200 switch (reginfo->ofs) {
201 case IXGBE_SRRCTL(0):
202 for (i = 0; i < 64; i++)
203 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
204 break;
205 case IXGBE_DCA_RXCTRL(0):
206 for (i = 0; i < 64; i++)
207 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
208 break;
209 case IXGBE_RDLEN(0):
210 for (i = 0; i < 64; i++)
211 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
212 break;
213 case IXGBE_RDH(0):
214 for (i = 0; i < 64; i++)
215 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
216 break;
217 case IXGBE_RDT(0):
218 for (i = 0; i < 64; i++)
219 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
220 break;
221 case IXGBE_RXDCTL(0):
222 for (i = 0; i < 64; i++)
223 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
224 break;
225 case IXGBE_RDBAL(0):
226 for (i = 0; i < 64; i++)
227 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
228 break;
229 case IXGBE_RDBAH(0):
230 for (i = 0; i < 64; i++)
231 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
232 break;
233 case IXGBE_TDBAL(0):
234 for (i = 0; i < 64; i++)
235 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
236 break;
237 case IXGBE_TDBAH(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
240 break;
241 case IXGBE_TDLEN(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
244 break;
245 case IXGBE_TDH(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
248 break;
249 case IXGBE_TDT(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
252 break;
253 case IXGBE_TXDCTL(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
256 break;
257 default:
c7689578 258 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 259 IXGBE_READ_REG(hw, reginfo->ofs));
260 return;
261 }
262
263 for (i = 0; i < 8; i++) {
264 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 265 pr_err("%-15s", rname);
dcd79aeb 266 for (j = 0; j < 8; j++)
c7689578
JP		 267 pr_cont(" %08x", regs[i*8+j]);
268 pr_cont("\n");
dcd79aeb
TI		 269 }
270
271}
272
273/*
274 * ixgbe_dump - Print registers, tx-rings and rx-rings
275 */
276static void ixgbe_dump(struct ixgbe_adapter *adapter)
277{
278 struct net_device *netdev = adapter->netdev;
279 struct ixgbe_hw *hw = &adapter->hw;
280 struct ixgbe_reg_info *reginfo;
281 int n = 0;
282 struct ixgbe_ring *tx_ring;
283 struct ixgbe_tx_buffer *tx_buffer_info;
284 union ixgbe_adv_tx_desc *tx_desc;
285 struct my_u0 { u64 a; u64 b; } *u0;
286 struct ixgbe_ring *rx_ring;
287 union ixgbe_adv_rx_desc *rx_desc;
288 struct ixgbe_rx_buffer *rx_buffer_info;
289 u32 staterr;
290 int i = 0;
291
292 if (!netif_msg_hw(adapter))
293 return;
294
295 /* Print netdevice Info */
296 if (netdev) {
297 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 298 pr_info("Device Name state "
dcd79aeb 299 "trans_start last_rx\n");
c7689578
JP		 300 pr_info("%-15s %016lX %016lX %016lX\n",
301 netdev->name,
302 netdev->state,
303 netdev->trans_start,
304 netdev->last_rx);
dcd79aeb
TI		 305 }
306
307 /* Print Registers */
308 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 309 pr_info(" Register Name Value\n");
dcd79aeb
TI		 310 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
311 reginfo->name; reginfo++) {
312 ixgbe_regdump(hw, reginfo);
313 }
314
315 /* Print TX Ring Summary */
316 if (!netdev || !netif_running(netdev))
317 goto exit;
318
319 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 320 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 321 for (n = 0; n < adapter->num_tx_queues; n++) {
322 tx_ring = adapter->tx_ring[n];
323 tx_buffer_info =
324 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 325 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 326 n, tx_ring->next_to_use, tx_ring->next_to_clean,
327 (u64)tx_buffer_info->dma,
328 tx_buffer_info->length,
329 tx_buffer_info->next_to_watch,
330 (u64)tx_buffer_info->time_stamp);
331 }
332
333 /* Print TX Rings */
334 if (!netif_msg_tx_done(adapter))
335 goto rx_ring_summary;
336
337 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
338
339 /* Transmit Descriptor Formats
340 *
341 * Advanced Transmit Descriptor
342 * +--------------------------------------------------------------+
343 * 0 | Buffer Address [63:0] |
344 * +--------------------------------------------------------------+
345 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
346 * +--------------------------------------------------------------+
347 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
348 */
349
350 for (n = 0; n < adapter->num_tx_queues; n++) {
351 tx_ring = adapter->tx_ring[n];
c7689578
JP		 352 pr_info("------------------------------------\n");
353 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
354 pr_info("------------------------------------\n");
355 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 356 "[PlPOIdStDDt Ln] [bi->dma ] "
357 "leng ntw timestamp bi->skb\n");
358
359 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 360 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 361 tx_buffer_info = &tx_ring->tx_buffer_info[i];
362 u0 = (struct my_u0 *)tx_desc;
c7689578 363 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 364 " %04X %p %016llX %p", i,
dcd79aeb
TI		 365 le64_to_cpu(u0->a),
366 le64_to_cpu(u0->b),
367 (u64)tx_buffer_info->dma,
368 tx_buffer_info->length,
369 tx_buffer_info->next_to_watch,
370 (u64)tx_buffer_info->time_stamp,
371 tx_buffer_info->skb);
372 if (i == tx_ring->next_to_use &&
373 i == tx_ring->next_to_clean)
c7689578 374 pr_cont(" NTC/U\n");
dcd79aeb 375 else if (i == tx_ring->next_to_use)
c7689578 376 pr_cont(" NTU\n");
dcd79aeb 377 else if (i == tx_ring->next_to_clean)
c7689578 378 pr_cont(" NTC\n");
dcd79aeb 379 else
c7689578 380 pr_cont("\n");
dcd79aeb
TI		 381
382 if (netif_msg_pktdata(adapter) &&
383 tx_buffer_info->dma != 0)
384 print_hex_dump(KERN_INFO, "",
385 DUMP_PREFIX_ADDRESS, 16, 1,
386 phys_to_virt(tx_buffer_info->dma),
387 tx_buffer_info->length, true);
388 }
389 }
390
391 /* Print RX Rings Summary */
392rx_ring_summary:
393 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 394 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 395 for (n = 0; n < adapter->num_rx_queues; n++) {
396 rx_ring = adapter->rx_ring[n];
c7689578
JP		 397 pr_info("%5d %5X %5X\n",
398 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 399 }
400
401 /* Print RX Rings */
402 if (!netif_msg_rx_status(adapter))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
406
407 /* Advanced Receive Descriptor (Read) Format
408 * 63 1 0
409 * +-----------------------------------------------------+
410 * 0 | Packet Buffer Address [63:1] |A0/NSE|
411 * +----------------------------------------------+------+
412 * 8 | Header Buffer Address [63:1] | DD |
413 * +-----------------------------------------------------+
414 *
415 *
416 * Advanced Receive Descriptor (Write-Back) Format
417 *
418 * 63 48 47 32 31 30 21 20 16 15 4 3 0
419 * +------------------------------------------------------+
420 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
421 * | Checksum Ident | | | | Type | Type |
422 * +------------------------------------------------------+
423 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
424 * +------------------------------------------------------+
425 * 63 48 47 32 31 20 19 0
426 */
427 for (n = 0; n < adapter->num_rx_queues; n++) {
428 rx_ring = adapter->rx_ring[n];
c7689578
JP		 429 pr_info("------------------------------------\n");
430 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
431 pr_info("------------------------------------\n");
432 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 433 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
434 "<-- Adv Rx Read format\n");
c7689578 435 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 436 "[vl er S cks ln] ---------------- [bi->skb] "
437 "<-- Adv Rx Write-Back format\n");
438
439 for (i = 0; i < rx_ring->count; i++) {
440 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 441 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 442 u0 = (struct my_u0 *)rx_desc;
443 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
444 if (staterr & IXGBE_RXD_STAT_DD) {
445 /* Descriptor Done */
c7689578 446 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 447 "%016llX ---------------- %p", i,
448 le64_to_cpu(u0->a),
449 le64_to_cpu(u0->b),
450 rx_buffer_info->skb);
451 } else {
c7689578 452 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 453 "%016llX %016llX %p", i,
454 le64_to_cpu(u0->a),
455 le64_to_cpu(u0->b),
456 (u64)rx_buffer_info->dma,
457 rx_buffer_info->skb);
458
459 if (netif_msg_pktdata(adapter)) {
460 print_hex_dump(KERN_INFO, "",
461 DUMP_PREFIX_ADDRESS, 16, 1,
462 phys_to_virt(rx_buffer_info->dma),
463 rx_ring->rx_buf_len, true);
464
465 if (rx_ring->rx_buf_len
919e78a6 466 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 467 print_hex_dump(KERN_INFO, "",
468 DUMP_PREFIX_ADDRESS, 16, 1,
469 phys_to_virt(
470 rx_buffer_info->page_dma +
471 rx_buffer_info->page_offset
472 ),
473 PAGE_SIZE/2, true);
474 }
475 }
476
477 if (i == rx_ring->next_to_use)
c7689578 478 pr_cont(" NTU\n");
dcd79aeb 479 else if (i == rx_ring->next_to_clean)
c7689578 480 pr_cont(" NTC\n");
dcd79aeb 481 else
c7689578 482 pr_cont("\n");
dcd79aeb
TI		 483
484 }
485 }
486
487exit:
488 return;
489}
490
5eba3699
AV		 491static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
492{
493 u32 ctrl_ext;
494
495 /* Let firmware take over control of h/w */
496 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 498 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 499}
500
501static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
502{
503 u32 ctrl_ext;
504
505 /* Let firmware know the driver has taken over */
506 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
507 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 508 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 509}
9a799d71 510
e8e26350
PW		 511/*
512 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
513 * @adapter: pointer to adapter struct
514 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
515 * @queue: queue to map the corresponding interrupt to
516 * @msix_vector: the vector to map to the corresponding queue
517 *
518 */
519static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 520 u8 queue, u8 msix_vector)
9a799d71
AK		 521{
522 u32 ivar, index;
e8e26350
PW		 523 struct ixgbe_hw *hw = &adapter->hw;
524 switch (hw->mac.type) {
525 case ixgbe_mac_82598EB:
526 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
527 if (direction == -1)
528 direction = 0;
529 index = (((direction * 64) + queue) >> 2) & 0x1F;
530 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
531 ivar &= ~(0xFF << (8 * (queue & 0x3)));
532 ivar |= (msix_vector << (8 * (queue & 0x3)));
533 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
534 break;
535 case ixgbe_mac_82599EB:
b93a2226 536 case ixgbe_mac_X540:
e8e26350
PW		 537 if (direction == -1) {
538 /* other causes */
539 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
540 index = ((queue & 1) * 8);
541 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
542 ivar &= ~(0xFF << index);
543 ivar |= (msix_vector << index);
544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
545 break;
546 } else {
547 /* tx or rx causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((16 * (queue & 1)) + (8 * direction));
550 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
554 break;
555 }
556 default:
557 break;
558 }
9a799d71
AK		 559}
560
fe49f04a 561static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 562 u64 qmask)
fe49f04a
AD		 563{
564 u32 mask;
565
bd508178
AD		 566 switch (adapter->hw.mac.type) {
567 case ixgbe_mac_82598EB:
fe49f04a
AD		 568 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 570 break;
571 case ixgbe_mac_82599EB:
b93a2226 572 case ixgbe_mac_X540:
fe49f04a
AD		 573 mask = (qmask & 0xFFFFFFFF);
574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
575 mask = (qmask >> 32);
576 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 577 break;
578 default:
579 break;
fe49f04a
AD		 580 }
581}
582
d3d00239
AD		 583static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
584 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 585{
d3d00239
AD		 586 if (tx_buffer->dma) {
587 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
588 dma_unmap_page(ring->dev,
589 tx_buffer->dma,
590 tx_buffer->length,
591 DMA_TO_DEVICE);
e5a43549 592 else
d3d00239
AD		 593 dma_unmap_single(ring->dev,
594 tx_buffer->dma,
595 tx_buffer->length,
596 DMA_TO_DEVICE);
e5a43549 597 }
d3d00239
AD		 598 tx_buffer->dma = 0;
599}
600
601void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
602 struct ixgbe_tx_buffer *tx_buffer_info)
603{
604 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
605 if (tx_buffer_info->skb)
9a799d71 606 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 607 tx_buffer_info->skb = NULL;
9a799d71
AK		 608 /* tx_buffer_info must be completely set up in the transmit path */
609}
610
c84d324c
JF		 611static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
612{
613 struct ixgbe_hw *hw = &adapter->hw;
614 struct ixgbe_hw_stats *hwstats = &adapter->stats;
615 u32 data = 0;
616 u32 xoff[8] = {0};
617 int i;
618
619 if ((hw->fc.current_mode == ixgbe_fc_full) ||
620 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
621 switch (hw->mac.type) {
622 case ixgbe_mac_82598EB:
623 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 624 break;
625 default:
c84d324c
JF		 626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
627 }
628 hwstats->lxoffrxc += data;
629
630 /* refill credits (no tx hang) if we received xoff */
631 if (!data)
632 return;
633
634 for (i = 0; i < adapter->num_tx_queues; i++)
635 clear_bit(__IXGBE_HANG_CHECK_ARMED,
636 &adapter->tx_ring[i]->state);
637 return;
638 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
639 return;
640
641 /* update stats for each tc, only valid with PFC enabled */
642 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
643 switch (hw->mac.type) {
644 case ixgbe_mac_82598EB:
645 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 646 break;
c84d324c
JF		 647 default:
648 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 649 }
c84d324c
JF		 650 hwstats->pxoffrxc[i] += xoff[i];
651 }
652
653 /* disarm tx queues that have received xoff frames */
654 for (i = 0; i < adapter->num_tx_queues; i++) {
655 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 656 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 657
658 if (xoff[tc])
659 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 660 }
26f23d82
YZ		 661}
662
c84d324c 663static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 664{
c84d324c
JF		 665 return ring->tx_stats.completed;
666}
667
668static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
669{
670 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 671 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 672
c84d324c
JF		 673 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
674 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
675
676 if (head != tail)
677 return (head < tail) ?
678 tail - head : (tail + ring->count - head);
679
680 return 0;
681}
682
683static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
684{
685 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
686 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
687 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
688 bool ret = false;
689
7d637bcc 690 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 691
692 /*
693 * Check for a hung queue, but be thorough. This verifies
694 * that a transmit has been completed since the previous
695 * check AND there is at least one packet pending. The
696 * ARMED bit is set to indicate a potential hang. The
697 * bit is cleared if a pause frame is received to remove
698 * false hang detection due to PFC or 802.3x frames. By
699 * requiring this to fail twice we avoid races with
700 * pfc clearing the ARMED bit and conditions where we
701 * run the check_tx_hang logic with a transmit completion
702 * pending but without time to complete it yet.
703 */
704 if ((tx_done_old == tx_done) && tx_pending) {
705 /* make sure it is true for two checks in a row */
706 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
707 &tx_ring->state);
708 } else {
709 /* update completed stats and continue */
710 tx_ring->tx_stats.tx_done_old = tx_done;
711 /* reset the countdown */
712 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 713 }
714
c84d324c 715 return ret;
9a799d71
AK		 716}
717
c83c6cbd
AD		 718/**
719 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
720 * @adapter: driver private struct
721 **/
722static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
723{
724
725 /* Do the reset outside of interrupt context */
726 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
727 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
728 ixgbe_service_event_schedule(adapter);
729 }
730}
e01c31a5 731
9a799d71
AK		 732/**
733 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 734 * @q_vector: structure containing interrupt and ring information
e01c31a5 735 * @tx_ring: tx ring to clean
9a799d71 736 **/
fe49f04a 737static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 738 struct ixgbe_ring *tx_ring)
9a799d71 739{
fe49f04a 740 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 741 struct ixgbe_tx_buffer *tx_buffer;
742 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 743 unsigned int total_bytes = 0, total_packets = 0;
59224555 744 unsigned int budget = q_vector->tx.work_limit;
d3d00239 745 u16 i = tx_ring->next_to_clean;
9a799d71 746
d3d00239
AD		 747 tx_buffer = &tx_ring->tx_buffer_info[i];
748 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 749
30065e63 750 for (; budget; budget--) {
d3d00239
AD		 751 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
752
753 /* if next_to_watch is not set then there is no work pending */
754 if (!eop_desc)
755 break;
756
757 /* if DD is not set pending work has not been completed */
758 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
759 break;
8ad494b0 760
d3d00239
AD		 761 /* count the packet as being completed */
762 tx_ring->tx_stats.completed++;
763
764 /* clear next_to_watch to prevent false hangs */
765 tx_buffer->next_to_watch = NULL;
8ad494b0 766
d3d00239
AD		 767 /* prevent any other reads prior to eop_desc being verified */
768 rmb();
769
770 do {
771 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 772 tx_desc->wb.status = 0;
d3d00239
AD		 773 if (likely(tx_desc == eop_desc)) {
774 eop_desc = NULL;
775 dev_kfree_skb_any(tx_buffer->skb);
776 tx_buffer->skb = NULL;
777
778 total_bytes += tx_buffer->bytecount;
779 total_packets += tx_buffer->gso_segs;
780 }
9a799d71 781
d3d00239
AD		 782 tx_buffer++;
783 tx_desc++;
8ad494b0 784 i++;
d3d00239 785 if (unlikely(i == tx_ring->count)) {
8ad494b0 786 i = 0;
e01c31a5 787
d3d00239
AD		 788 tx_buffer = tx_ring->tx_buffer_info;
789 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 790 }
e01c31a5 791
d3d00239 792 } while (eop_desc);
12207e49
PWJ		 793 }
794
9a799d71 795 tx_ring->next_to_clean = i;
d3d00239 796 u64_stats_update_begin(&tx_ring->syncp);
b953799e 797 tx_ring->stats.bytes += total_bytes;
bd198058 798 tx_ring->stats.packets += total_packets;
d3d00239 799 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 800 q_vector->tx.total_bytes += total_bytes;
801 q_vector->tx.total_packets += total_packets;
b953799e 802
c84d324c
JF		 803 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
804 /* schedule immediate reset if we believe we hung */
805 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 806 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 807 e_err(drv, "Detected Tx Unit Hang\n"
808 " Tx Queue <%d>\n"
809 " TDH, TDT <%x>, <%x>\n"
810 " next_to_use <%x>\n"
811 " next_to_clean <%x>\n"
812 "tx_buffer_info[next_to_clean]\n"
813 " time_stamp <%lx>\n"
814 " jiffies <%lx>\n",
815 tx_ring->queue_index,
816 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
817 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 818 tx_ring->next_to_use, i,
819 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 820
821 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
822
823 e_info(probe,
824 "tx hang %d detected on queue %d, resetting adapter\n",
825 adapter->tx_timeout_count + 1, tx_ring->queue_index);
826
b953799e 827 /* schedule immediate reset if we believe we hung */
c83c6cbd 828 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 829
830 /* the adapter is about to reset, no point in enabling stuff */
59224555 831 return true;
b953799e 832 }
9a799d71 833
e092be60 834#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 835 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 836 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 837 /* Make sure that anybody stopping the queue after this
838 * sees the new next_to_clean.
839 */
840 smp_mb();
fc77dc3c 841 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 842 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 843 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 844 ++tx_ring->tx_stats.restart_queue;
30eba97a 845 }
e092be60 846 }
9a799d71 847
59224555 848 return !!budget;
9a799d71
AK		 849}
850
5dd2d332 851#ifdef CONFIG_IXGBE_DCA
bd0362dd 852static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 853 struct ixgbe_ring *rx_ring,
854 int cpu)
bd0362dd 855{
33cf09c9 856 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 857 u32 rxctrl;
33cf09c9
AD		 858 u8 reg_idx = rx_ring->reg_idx;
859
860 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
861 switch (hw->mac.type) {
862 case ixgbe_mac_82598EB:
863 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 864 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 865 break;
866 case ixgbe_mac_82599EB:
b93a2226 867 case ixgbe_mac_X540:
33cf09c9 868 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 869 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 870 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
871 break;
872 default:
873 break;
bd0362dd 874 }
33cf09c9
AD		 875 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
876 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
877 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 878 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 879}
880
881static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 882 struct ixgbe_ring *tx_ring,
883 int cpu)
bd0362dd 884{
33cf09c9 885 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 886 u32 txctrl;
33cf09c9
AD		 887 u8 reg_idx = tx_ring->reg_idx;
888
889 switch (hw->mac.type) {
890 case ixgbe_mac_82598EB:
891 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
892 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 893 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 894 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 895 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
896 break;
897 case ixgbe_mac_82599EB:
b93a2226 898 case ixgbe_mac_X540:
33cf09c9
AD		 899 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
900 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 901 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 902 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
905 break;
906 default:
907 break;
908 }
909}
910
911static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
912{
913 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 914 struct ixgbe_ring *ring;
bd0362dd 915 int cpu = get_cpu();
bd0362dd 916
33cf09c9
AD		 917 if (q_vector->cpu == cpu)
918 goto out_no_update;
919
efe3d3c8
AD		 920 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
921 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 922
efe3d3c8
AD		 923 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
924 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 925
926 q_vector->cpu = cpu;
927out_no_update:
bd0362dd
JC		 928 put_cpu();
929}
930
931static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
932{
33cf09c9 933 int num_q_vectors;
bd0362dd
JC		 934 int i;
935
936 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
937 return;
938
e35ec126
AD		 939 /* always use CB2 mode, difference is masked in the CB driver */
940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
941
33cf09c9
AD		 942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
943 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
944 else
945 num_q_vectors = 1;
946
947 for (i = 0; i < num_q_vectors; i++) {
948 adapter->q_vector[i]->cpu = -1;
949 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 950 }
951}
952
953static int __ixgbe_notify_dca(struct device *dev, void *data)
954{
c60fbb00 955 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 956 unsigned long event = *(unsigned long *)data;
957
2a72c31e 958 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 959 return 0;
960
bd0362dd
JC		 961 switch (event) {
962 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 963 /* if we're already enabled, don't do it again */
964 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
965 break;
652f093f 966 if (dca_add_requester(dev) == 0) {
96b0e0f6 967 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 968 ixgbe_setup_dca(adapter);
969 break;
970 }
971 /* Fall Through since DCA is disabled. */
972 case DCA_PROVIDER_REMOVE:
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
974 dca_remove_requester(dev);
975 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
976 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
977 }
978 break;
979 }
980
652f093f 981 return 0;
bd0362dd 982}
5dd2d332 983#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 984
985static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
986 struct sk_buff *skb)
987{
988 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
989}
990
ff886dfc
AD		 991/**
992 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
993 * @adapter: address of board private structure
994 * @rx_desc: advanced rx descriptor
995 *
996 * Returns : true if it is FCoE pkt
997 */
998static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
999 union ixgbe_adv_rx_desc *rx_desc)
1000{
1001 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1002
1003 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1004 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1005 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1006 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1007}
1008
9a799d71
AK		 1009/**
1010 * ixgbe_receive_skb - Send a completed packet up the stack
1011 * @adapter: board private structure
1012 * @skb: packet to send up
177db6ff
MC		 1013 * @status: hardware indication of status of receive
1014 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1015 * @rx_desc: rx descriptor
9a799d71 1016 **/
78b6f4ce 1017static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1018 struct sk_buff *skb, u8 status,
1019 struct ixgbe_ring *ring,
1020 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1021{
78b6f4ce
HX		 1022 struct ixgbe_adapter *adapter = q_vector->adapter;
1023 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1024 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1025 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1026
f62bbb5e
JG		 1027 if (is_vlan && (tag & VLAN_VID_MASK))
1028 __vlan_hwaccel_put_tag(skb, tag);
1029
1030 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1031 napi_gro_receive(napi, skb);
1032 else
1033 netif_rx(skb);
9a799d71
AK		 1034}
1035
e59bd25d
AV		 1036/**
1037 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1038 * @adapter: address of board private structure
1039 * @status_err: hardware indication of status of receive
1040 * @skb: skb currently being received and modified
ff886dfc 1041 * @status_err: status error value of last descriptor in packet
e59bd25d 1042 **/
9a799d71 1043static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1044 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1045 struct sk_buff *skb,
1046 u32 status_err)
9a799d71 1047{
ff886dfc 1048 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1049
712744be
JB		 1050 /* Rx csum disabled */
1051 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1052 return;
e59bd25d
AV		 1053
1054 /* if IP and error */
1055 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1056 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1057 adapter->hw_csum_rx_error++;
1058 return;
1059 }
e59bd25d
AV		 1060
1061 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1062 return;
1063
1064 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1065 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1066
1067 /*
1068 * 82599 errata, UDP frames with a 0 checksum can be marked as
1069 * checksum errors.
1070 */
1071 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1072 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1073 return;
1074
e59bd25d
AV		 1075 adapter->hw_csum_rx_error++;
1076 return;
1077 }
1078
9a799d71 1079 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1080 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1081}
1082
84ea2591 1083static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1084{
1085 /*
1086 * Force memory writes to complete before letting h/w
1087 * know there are new descriptors to fetch. (Only
1088 * applicable for weak-ordered memory model archs,
1089 * such as IA-64).
1090 */
1091 wmb();
84ea2591 1092 writel(val, rx_ring->tail);
e8e26350
PW		 1093}
1094
9a799d71
AK		 1095/**
1096 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1097 * @rx_ring: ring to place buffers on
1098 * @cleaned_count: number of buffers to replace
9a799d71 1099 **/
fc77dc3c 1100void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1101{
9a799d71 1102 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1103 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1104 struct sk_buff *skb;
1105 u16 i = rx_ring->next_to_use;
9a799d71 1106
fc77dc3c
AD		 1107 /* do nothing if no valid netdev defined */
1108 if (!rx_ring->netdev)
1109 return;
1110
9a799d71 1111 while (cleaned_count--) {
31f05a2d 1112 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1113 bi = &rx_ring->rx_buffer_info[i];
1114 skb = bi->skb;
9a799d71 1115
d5f398ed 1116 if (!skb) {
fc77dc3c 1117 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1118 rx_ring->rx_buf_len);
9a799d71 1119 if (!skb) {
5b7da515 1120 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1121 goto no_buffers;
1122 }
d716a7d8
AD		 1123 /* initialize queue mapping */
1124 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1125 bi->skb = skb;
d716a7d8 1126 }
9a799d71 1127
d716a7d8 1128 if (!bi->dma) {
b6ec895e 1129 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1130 skb->data,
e8e9f696 1131 rx_ring->rx_buf_len,
1b507730 1132 DMA_FROM_DEVICE);
b6ec895e 1133 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1134 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1135 bi->dma = 0;
1136 goto no_buffers;
1137 }
9a799d71 1138 }
d5f398ed 1139
7d637bcc 1140 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1141 if (!bi->page) {
fc77dc3c 1142 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1143 if (!bi->page) {
5b7da515 1144 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1145 goto no_buffers;
1146 }
1147 }
1148
1149 if (!bi->page_dma) {
1150 /* use a half page if we're re-using */
1151 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1152 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1153 bi->page,
1154 bi->page_offset,
1155 PAGE_SIZE / 2,
1156 DMA_FROM_DEVICE);
b6ec895e 1157 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1158 bi->page_dma)) {
5b7da515 1159 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1160 bi->page_dma = 0;
1161 goto no_buffers;
1162 }
1163 }
1164
1165 /* Refresh the desc even if buffer_addrs didn't change
1166 * because each write-back erases this info. */
3a581073
JB		 1167 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1168 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1169 } else {
3a581073 1170 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1171 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1172 }
1173
1174 i++;
1175 if (i == rx_ring->count)
1176 i = 0;
9a799d71 1177 }
7c6e0a43 1178
9a799d71
AK		 1179no_buffers:
1180 if (rx_ring->next_to_use != i) {
1181 rx_ring->next_to_use = i;
84ea2591 1182 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1183 }
1184}
1185
c267fc16 1186static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1187{
c267fc16
AD		 1188 /* HW will not DMA in data larger than the given buffer, even if it
1189 * parses the (NFS, of course) header to be larger. In that case, it
1190 * fills the header buffer and spills the rest into the page.
1191 */
1192 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1193 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1194 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1195 if (hlen > IXGBE_RX_HDR_SIZE)
1196 hlen = IXGBE_RX_HDR_SIZE;
1197 return hlen;
7c6e0a43
JB		 1198}
1199
f8212f97
AD		 1200/**
1201 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1202 * @skb: pointer to the last skb in the rsc queue
1203 *
1204 * This function changes a queue full of hw rsc buffers into a completed
1205 * packet. It uses the ->prev pointers to find the first packet and then
1206 * turns it into the frag list owner.
1207 **/
aa80175a 1208static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1209{
1210 unsigned int frag_list_size = 0;
aa80175a 1211 unsigned int skb_cnt = 1;
f8212f97
AD		 1212
1213 while (skb->prev) {
1214 struct sk_buff *prev = skb->prev;
1215 frag_list_size += skb->len;
1216 skb->prev = NULL;
1217 skb = prev;
aa80175a 1218 skb_cnt++;
f8212f97
AD		 1219 }
1220
1221 skb_shinfo(skb)->frag_list = skb->next;
1222 skb->next = NULL;
1223 skb->len += frag_list_size;
1224 skb->data_len += frag_list_size;
1225 skb->truesize += frag_list_size;
aa80175a
AD		 1226 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1227
f8212f97
AD		 1228 return skb;
1229}
1230
aa80175a
AD		 1231static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1232{
1233 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1234 IXGBE_RXDADV_RSCCNT_MASK);
1235}
43634e82 1236
4ff7fb12 1237static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1238 struct ixgbe_ring *rx_ring,
4ff7fb12 1239 int budget)
9a799d71 1240{
78b6f4ce 1241 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1242 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1243 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1244 struct sk_buff *skb;
d2f4fbe2 1245 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1246 const int current_node = numa_node_id();
3d8fd385
YZ		 1247#ifdef IXGBE_FCOE
1248 int ddp_bytes = 0;
1249#endif /* IXGBE_FCOE */
c267fc16
AD		 1250 u32 staterr;
1251 u16 i;
1252 u16 cleaned_count = 0;
aa80175a 1253 bool pkt_is_rsc = false;
9a799d71
AK		 1254
1255 i = rx_ring->next_to_clean;
31f05a2d 1256 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1257 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1258
1259 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1260 u32 upper_len = 0;
9a799d71 1261
3c945e5b 1262 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1263
c267fc16
AD		 1264 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1265
9a799d71 1266 skb = rx_buffer_info->skb;
9a799d71 1267 rx_buffer_info->skb = NULL;
c267fc16 1268 prefetch(skb->data);
9a799d71 1269
c267fc16 1270 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1271 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16 1272
b811ce91
JB		 1273 /* linear means we are building an skb from multiple pages */
1274 if (!skb_is_nonlinear(skb)) {
c267fc16 1275 u16 hlen;
aa80175a 1276 if (pkt_is_rsc &&
c267fc16
AD		 1277 !(staterr & IXGBE_RXD_STAT_EOP) &&
1278 !skb->prev) {
43634e82
MC		 1279 /*
1280 * When HWRSC is enabled, delay unmapping
1281 * of the first packet. It carries the
1282 * header information, HW may still
1283 * access the header after the writeback.
1284 * Only unmap it when EOP is reached
1285 */
e8171aaa 1286 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1287 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1288 } else {
b6ec895e 1289 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1290 rx_buffer_info->dma,
1291 rx_ring->rx_buf_len,
1292 DMA_FROM_DEVICE);
e8171aaa 1293 }
4f57ca6e 1294 rx_buffer_info->dma = 0;
c267fc16
AD		 1295
1296 if (ring_is_ps_enabled(rx_ring)) {
1297 hlen = ixgbe_get_hlen(rx_desc);
1298 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1299 } else {
1300 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1301 }
1302
1303 skb_put(skb, hlen);
1304 } else {
1305 /* assume packet split since header is unmapped */
1306 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1307 }
1308
1309 if (upper_len) {
b6ec895e
AD		 1310 dma_unmap_page(rx_ring->dev,
1311 rx_buffer_info->page_dma,
1312 PAGE_SIZE / 2,
1313 DMA_FROM_DEVICE);
9a799d71
AK		 1314 rx_buffer_info->page_dma = 0;
1315 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1316 rx_buffer_info->page,
1317 rx_buffer_info->page_offset,
1318 upper_len);
762f4c57 1319
c267fc16
AD		 1320 if ((page_count(rx_buffer_info->page) == 1) &&
1321 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1322 get_page(rx_buffer_info->page);
c267fc16
AD		 1323 else
1324 rx_buffer_info->page = NULL;
9a799d71
AK		 1325
1326 skb->len += upper_len;
1327 skb->data_len += upper_len;
1328 skb->truesize += upper_len;
1329 }
1330
1331 i++;
1332 if (i == rx_ring->count)
1333 i = 0;
9a799d71 1334
31f05a2d 1335 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1336 prefetch(next_rxd);
9a799d71 1337 cleaned_count++;
f8212f97 1338
aa80175a 1339 if (pkt_is_rsc) {
f8212f97
AD		 1340 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1341 IXGBE_RXDADV_NEXTP_SHIFT;
1342 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1343 } else {
1344 next_buffer = &rx_ring->rx_buffer_info[i];
1345 }
1346
c267fc16 1347 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1348 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1349 rx_buffer_info->skb = next_buffer->skb;
1350 rx_buffer_info->dma = next_buffer->dma;
1351 next_buffer->skb = skb;
1352 next_buffer->dma = 0;
1353 } else {
1354 skb->next = next_buffer->skb;
1355 skb->next->prev = skb;
1356 }
5b7da515 1357 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1358 goto next_desc;
1359 }
1360
aa80175a
AD		 1361 if (skb->prev) {
1362 skb = ixgbe_transform_rsc_queue(skb);
1363 /* if we got here without RSC the packet is invalid */
1364 if (!pkt_is_rsc) {
1365 __pskb_trim(skb, 0);
1366 rx_buffer_info->skb = skb;
1367 goto next_desc;
1368 }
1369 }
c267fc16
AD		 1370
1371 if (ring_is_rsc_enabled(rx_ring)) {
1372 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1373 dma_unmap_single(rx_ring->dev,
1374 IXGBE_RSC_CB(skb)->dma,
1375 rx_ring->rx_buf_len,
1376 DMA_FROM_DEVICE);
1377 IXGBE_RSC_CB(skb)->dma = 0;
1378 IXGBE_RSC_CB(skb)->delay_unmap = false;
1379 }
aa80175a
AD		 1380 }
1381 if (pkt_is_rsc) {
c267fc16
AD		 1382 if (ring_is_ps_enabled(rx_ring))
1383 rx_ring->rx_stats.rsc_count +=
aa80175a 1384 skb_shinfo(skb)->nr_frags;
c267fc16 1385 else
aa80175a
AD		 1386 rx_ring->rx_stats.rsc_count +=
1387 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1388 rx_ring->rx_stats.rsc_flush++;
1389 }
1390
1391 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1392 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1393 dev_kfree_skb_any(skb);
9a799d71
AK		 1394 goto next_desc;
1395 }
1396
ff886dfc 1397 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1398 if (adapter->netdev->features & NETIF_F_RXHASH)
1399 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1400
1401 /* probably a little skewed due to removing CRC */
1402 total_rx_bytes += skb->len;
1403 total_rx_packets++;
1404
fc77dc3c 1405 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1406#ifdef IXGBE_FCOE
1407 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1408 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1409 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1410 staterr);
63d635b2
AD		 1411 if (!ddp_bytes) {
1412 dev_kfree_skb_any(skb);
332d4a7d 1413 goto next_desc;
63d635b2 1414 }
3d8fd385 1415 }
332d4a7d 1416#endif /* IXGBE_FCOE */
fdaff1ce 1417 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1418
4ff7fb12 1419 budget--;
9a799d71
AK		 1420next_desc:
1421 rx_desc->wb.upper.status_error = 0;
1422
4ff7fb12 1423 if (!budget)
c267fc16
AD		 1424 break;
1425
9a799d71
AK		 1426 /* return some buffers to hardware, one at a time is too slow */
1427 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1428 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1429 cleaned_count = 0;
1430 }
1431
1432 /* use prefetched values */
1433 rx_desc = next_rxd;
9a799d71 1434 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1435 }
1436
9a799d71 1437 rx_ring->next_to_clean = i;
7d4987de 1438 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1439
1440 if (cleaned_count)
fc77dc3c 1441 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1442
3d8fd385
YZ		 1443#ifdef IXGBE_FCOE
1444 /* include DDPed FCoE data */
1445 if (ddp_bytes > 0) {
1446 unsigned int mss;
1447
fc77dc3c 1448 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1449 sizeof(struct fc_frame_header) -
1450 sizeof(struct fcoe_crc_eof);
1451 if (mss > 512)
1452 mss &= ~511;
1453 total_rx_bytes += ddp_bytes;
1454 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1455 }
1456#endif /* IXGBE_FCOE */
1457
c267fc16
AD		 1458 u64_stats_update_begin(&rx_ring->syncp);
1459 rx_ring->stats.packets += total_rx_packets;
1460 rx_ring->stats.bytes += total_rx_bytes;
1461 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1462 q_vector->rx.total_packets += total_rx_packets;
1463 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1464
1465 return !!budget;
9a799d71
AK		 1466}
1467
9a799d71
AK		 1468/**
1469 * ixgbe_configure_msix - Configure MSI-X hardware
1470 * @adapter: board private structure
1471 *
1472 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1473 * interrupts.
1474 **/
1475static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1476{
021230d4 1477 struct ixgbe_q_vector *q_vector;
efe3d3c8 1478 int q_vectors, v_idx;
021230d4 1479 u32 mask;
9a799d71 1480
021230d4 1481 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1482
8e34d1aa
AD		 1483 /* Populate MSIX to EITR Select */
1484 if (adapter->num_vfs > 32) {
1485 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1486 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1487 }
1488
4df10466
JB		 1489 /*
1490 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1491 * corresponding register.
1492 */
1493 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1494 struct ixgbe_ring *ring;
7a921c93 1495 q_vector = adapter->q_vector[v_idx];
021230d4 1496
efe3d3c8
AD		 1497 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1498 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1499
1500 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1501 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1502
1503 if (q_vector->tx.ring && !q_vector->rx.ring)
f7554a2b
NS		 1504 /* tx only */
1505 q_vector->eitr = adapter->tx_eitr_param;
efe3d3c8 1506 else if (q_vector->rx.ring)
f7554a2b
NS		 1507 /* rx or mixed */
1508 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1509
fe49f04a 1510 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1511 }
1512
bd508178
AD		 1513 switch (adapter->hw.mac.type) {
1514 case ixgbe_mac_82598EB:
e8e26350 1515 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1516 v_idx);
bd508178
AD		 1517 break;
1518 case ixgbe_mac_82599EB:
b93a2226 1519 case ixgbe_mac_X540:
e8e26350 1520 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1521 break;
1522
1523 default:
1524 break;
1525 }
021230d4
AV		 1526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1527
41fb9248 1528 /* set up to autoclear timer, and the vectors */
021230d4 1529 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1530 if (adapter->num_vfs)
1531 mask &= ~(IXGBE_EIMS_OTHER |
1532 IXGBE_EIMS_MAILBOX |
1533 IXGBE_EIMS_LSC);
1534 else
1535 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1536 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1537}
1538
f494e8fa
AV		 1539enum latency_range {
1540 lowest_latency = 0,
1541 low_latency = 1,
1542 bulk_latency = 2,
1543 latency_invalid = 255
1544};
1545
1546/**
1547 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1548 * @q_vector: structure containing interrupt and ring information
1549 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1550 *
1551 * Stores a new ITR value based on packets and byte
1552 * counts during the last interrupt. The advantage of per interrupt
1553 * computation is faster updates and more accurate ITR for the current
1554 * traffic pattern. Constants in this function were computed
1555 * based on theoretical maximum wire speed and thresholds were set based
1556 * on testing data as well as attempting to minimize response time
1557 * while increasing bulk throughput.
1558 * this functionality is controlled by the InterruptThrottleRate module
1559 * parameter (see ixgbe_param.c)
1560 **/
bd198058
AD		 1561static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1562 struct ixgbe_ring_container *ring_container)
f494e8fa 1563{
f494e8fa 1564 u64 bytes_perint;
bd198058
AD		 1565 struct ixgbe_adapter *adapter = q_vector->adapter;
1566 int bytes = ring_container->total_bytes;
1567 int packets = ring_container->total_packets;
1568 u32 timepassed_us;
1569 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1570
1571 if (packets == 0)
bd198058 1572 return;
f494e8fa
AV		 1573
1574 /* simple throttlerate management
1575 * 0-20MB/s lowest (100000 ints/s)
1576 * 20-100MB/s low (20000 ints/s)
1577 * 100-1249MB/s bulk (8000 ints/s)
1578 */
1579 /* what was last interrupt timeslice? */
bd198058 1580 timepassed_us = 1000000/q_vector->eitr;
f494e8fa
AV		 1581 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1582
1583 switch (itr_setting) {
1584 case lowest_latency:
1585 if (bytes_perint > adapter->eitr_low)
bd198058 1586 itr_setting = low_latency;
f494e8fa
AV		 1587 break;
1588 case low_latency:
1589 if (bytes_perint > adapter->eitr_high)
bd198058 1590 itr_setting = bulk_latency;
f494e8fa 1591 else if (bytes_perint <= adapter->eitr_low)
bd198058 1592 itr_setting = lowest_latency;
f494e8fa
AV		 1593 break;
1594 case bulk_latency:
1595 if (bytes_perint <= adapter->eitr_high)
bd198058 1596 itr_setting = low_latency;
f494e8fa
AV		 1597 break;
1598 }
1599
bd198058
AD		 1600 /* clear work counters since we have the values we need */
1601 ring_container->total_bytes = 0;
1602 ring_container->total_packets = 0;
1603
1604 /* write updated itr to ring container */
1605 ring_container->itr = itr_setting;
f494e8fa
AV		 1606}
1607
509ee935
JB		 1608/**
1609 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1610 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1611 *
1612 * This function is made to be called by ethtool and by the driver
1613 * when it needs to update EITR registers at runtime. Hardware
1614 * specific quirks/differences are taken care of here.
1615 */
fe49f04a 1616void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1617{
fe49f04a 1618 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1619 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1620 int v_idx = q_vector->v_idx;
1621 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1622
bd508178
AD		 1623 switch (adapter->hw.mac.type) {
1624 case ixgbe_mac_82598EB:
509ee935
JB		 1625 /* must write high and low 16 bits to reset counter */
1626 itr_reg |= (itr_reg << 16);
bd508178
AD		 1627 break;
1628 case ixgbe_mac_82599EB:
b93a2226 1629 case ixgbe_mac_X540:
f8d1dcaf 1630 /*
b93a2226 1631 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1632 * max interrupt rate, but there is an errata where it can
1633 * not be zero with RSC
1634 */
1635 if (itr_reg == 8 &&
1636 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1637 itr_reg = 0;
1638
509ee935
JB		 1639 /*
1640 * set the WDIS bit to not clear the timer bits and cause an
1641 * immediate assertion of the interrupt
1642 */
1643 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1644 break;
1645 default:
1646 break;
509ee935
JB		 1647 }
1648 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1649}
1650
bd198058 1651static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1652{
bd198058
AD		 1653 u32 new_itr = q_vector->eitr;
1654 u8 current_itr;
f494e8fa 1655
bd198058
AD		 1656 ixgbe_update_itr(q_vector, &q_vector->tx);
1657 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1658
08c8833b 1659 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1660
1661 switch (current_itr) {
1662 /* counts and packets in update_itr are dependent on these numbers */
1663 case lowest_latency:
1664 new_itr = 100000;
1665 break;
1666 case low_latency:
1667 new_itr = 20000; /* aka hwitr = ~200 */
1668 break;
1669 case bulk_latency:
f494e8fa
AV		 1670 new_itr = 8000;
1671 break;
bd198058
AD		 1672 default:
1673 break;
f494e8fa
AV		 1674 }
1675
1676 if (new_itr != q_vector->eitr) {
fe49f04a 1677 /* do an exponential smoothing */
125601bf 1678 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 1679
bd198058 1680 /* save the algorithm value here */
509ee935 1681 q_vector->eitr = new_itr;
fe49f04a
AD		 1682
1683 ixgbe_write_eitr(q_vector);
f494e8fa 1684 }
f494e8fa
AV		 1685}
1686
119fc60a 1687/**
f0f9778d
AD		 1688 * ixgbe_check_overtemp_subtask - check for over tempurature
1689 * @adapter: pointer to adapter
119fc60a 1690 **/
f0f9778d 1691static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1692{
119fc60a
MC		 1693 struct ixgbe_hw *hw = &adapter->hw;
1694 u32 eicr = adapter->interrupt_event;
1695
f0f9778d 1696 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1697 return;
1698
f0f9778d
AD		 1699 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1700 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1701 return;
1702
1703 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1704
7ca647bd 1705 switch (hw->device_id) {
f0f9778d
AD		 1706 case IXGBE_DEV_ID_82599_T3_LOM:
1707 /*
1708 * Since the warning interrupt is for both ports
1709 * we don't have to check if:
1710 * - This interrupt wasn't for our port.
1711 * - We may have missed the interrupt so always have to
1712 * check if we got a LSC
1713 */
1714 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1715 !(eicr & IXGBE_EICR_LSC))
1716 return;
1717
1718 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1719 u32 autoneg;
1720 bool link_up = false;
7ca647bd 1721
7ca647bd
JP		 1722 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1723
f0f9778d
AD		 1724 if (link_up)
1725 return;
1726 }
1727
1728 /* Check if this is not due to overtemp */
1729 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1730 return;
1731
1732 break;
7ca647bd
JP		 1733 default:
1734 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1735 return;
7ca647bd 1736 break;
119fc60a 1737 }
7ca647bd
JP		 1738 e_crit(drv,
1739 "Network adapter has been stopped because it has over heated. "
1740 "Restart the computer. If the problem persists, "
1741 "power off the system and replace the adapter\n");
f0f9778d
AD		 1742
1743 adapter->interrupt_event = 0;
119fc60a
MC		 1744}
1745
0befdb3e
JB		 1746static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1747{
1748 struct ixgbe_hw *hw = &adapter->hw;
1749
1750 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1751 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1752 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1753 /* write to clear the interrupt */
1754 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1755 }
1756}
cf8280ee 1757
e8e26350
PW		 1758static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1759{
1760 struct ixgbe_hw *hw = &adapter->hw;
1761
73c4b7cd
AD		 1762 if (eicr & IXGBE_EICR_GPI_SDP2) {
1763 /* Clear the interrupt */
1764 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1765 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1766 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1767 ixgbe_service_event_schedule(adapter);
1768 }
73c4b7cd
AD		 1769 }
1770
e8e26350
PW		 1771 if (eicr & IXGBE_EICR_GPI_SDP1) {
1772 /* Clear the interrupt */
1773 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1774 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1775 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1776 ixgbe_service_event_schedule(adapter);
1777 }
e8e26350
PW		 1778 }
1779}
1780
cf8280ee
JB		 1781static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1782{
1783 struct ixgbe_hw *hw = &adapter->hw;
1784
1785 adapter->lsc_int++;
1786 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1787 adapter->link_check_timeout = jiffies;
1788 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1789 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1790 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1791 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1792 }
1793}
1794
fe49f04a
AD		 1795static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1796 u64 qmask)
1797{
1798 u32 mask;
bd508178 1799 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1800
bd508178
AD		 1801 switch (hw->mac.type) {
1802 case ixgbe_mac_82598EB:
fe49f04a 1803 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1804 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1805 break;
1806 case ixgbe_mac_82599EB:
b93a2226 1807 case ixgbe_mac_X540:
fe49f04a 1808 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1809 if (mask)
1810 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1811 mask = (qmask >> 32);
bd508178
AD		 1812 if (mask)
1813 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1814 break;
1815 default:
1816 break;
fe49f04a
AD		 1817 }
1818 /* skip the flush */
1819}
1820
1821static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1822 u64 qmask)
fe49f04a
AD		 1823{
1824 u32 mask;
bd508178 1825 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1826
bd508178
AD		 1827 switch (hw->mac.type) {
1828 case ixgbe_mac_82598EB:
fe49f04a 1829 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1830 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1831 break;
1832 case ixgbe_mac_82599EB:
b93a2226 1833 case ixgbe_mac_X540:
fe49f04a 1834 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1835 if (mask)
1836 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1837 mask = (qmask >> 32);
bd508178
AD		 1838 if (mask)
1839 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1840 break;
1841 default:
1842 break;
fe49f04a
AD		 1843 }
1844 /* skip the flush */
1845}
1846
021230d4 1847/**
2c4af694
AD		 1848 * ixgbe_irq_enable - Enable default interrupt generation settings
1849 * @adapter: board private structure
021230d4 1850 **/
2c4af694
AD		 1851static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1852 bool flush)
9a799d71 1853{
2c4af694 1854 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 1855
2c4af694
AD		 1856 /* don't reenable LSC while waiting for link */
1857 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1858 mask &= ~IXGBE_EIMS_LSC;
9a799d71 1859
2c4af694
AD		 1860 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1861 mask |= IXGBE_EIMS_GPI_SDP0;
1862 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1863 mask |= IXGBE_EIMS_GPI_SDP1;
1864 switch (adapter->hw.mac.type) {
1865 case ixgbe_mac_82599EB:
2c4af694
AD		 1866 mask |= IXGBE_EIMS_GPI_SDP1;
1867 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 1868 case ixgbe_mac_X540:
1869 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 1870 mask |= IXGBE_EIMS_MAILBOX;
1871 break;
1872 default:
1873 break;
9a799d71 1874 }
2c4af694
AD		 1875 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1876 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1877 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 1878
2c4af694
AD		 1879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1880 if (queues)
1881 ixgbe_irq_enable_queues(adapter, ~0);
1882 if (flush)
1883 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1884}
1885
2c4af694 1886static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 1887{
a65151ba 1888 struct ixgbe_adapter *adapter = data;
9a799d71 1889 struct ixgbe_hw *hw = &adapter->hw;
54037505 1890 u32 eicr;
91281fd3 1891
54037505
DS		 1892 /*
1893 * Workaround for Silicon errata. Use clear-by-write instead
1894 * of clear-by-read. Reading with EICS will return the
1895 * interrupt causes without clearing, which later be done
1896 * with the write to EICR.
1897 */
1898 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1899 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 1900
cf8280ee
JB		 1901 if (eicr & IXGBE_EICR_LSC)
1902 ixgbe_check_lsc(adapter);
f0848276 1903
1cdd1ec8
GR		 1904 if (eicr & IXGBE_EICR_MAILBOX)
1905 ixgbe_msg_task(adapter);
efe3d3c8 1906
bd508178
AD		 1907 switch (hw->mac.type) {
1908 case ixgbe_mac_82599EB:
b93a2226 1909 case ixgbe_mac_X540:
2c4af694
AD		 1910 if (eicr & IXGBE_EICR_ECC)
1911 e_info(link, "Received unrecoverable ECC Err, please "
1912 "reboot\n");
c4cf55e5
PWJ		 1913 /* Handle Flow Director Full threshold interrupt */
1914 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1915 int reinit_count = 0;
c4cf55e5 1916 int i;
c4cf55e5 1917 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1918 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1919 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1920 &ring->state))
1921 reinit_count++;
1922 }
1923 if (reinit_count) {
1924 /* no more flow director interrupts until after init */
1925 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 1926 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1927 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1928 }
1929 }
f0f9778d
AD		 1930 ixgbe_check_sfp_event(adapter, eicr);
1931 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1932 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1933 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1934 adapter->interrupt_event = eicr;
1935 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1936 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1937 }
1938 }
bd508178
AD		 1939 break;
1940 default:
1941 break;
c4cf55e5 1942 }
f0848276 1943
bd508178 1944 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 1945
7086400d 1946 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1947 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 1948 ixgbe_irq_enable(adapter, false, false);
f0848276 1949
9a799d71 1950 return IRQ_HANDLED;
f0848276 1951}
91281fd3 1952
4ff7fb12 1953static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 1954{
021230d4 1955 struct ixgbe_q_vector *q_vector = data;
91281fd3 1956
9b471446 1957 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1958
4ff7fb12
AD		 1959 if (q_vector->rx.ring || q_vector->tx.ring)
1960 napi_schedule(&q_vector->napi);
91281fd3 1961
9a799d71 1962 return IRQ_HANDLED;
91281fd3
AD		 1963}
1964
021230d4 1965static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 1966 int r_idx)
021230d4 1967{
7a921c93 1968 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 1969 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 1970
2274543f 1971 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 1972 rx_ring->next = q_vector->rx.ring;
1973 q_vector->rx.ring = rx_ring;
1974 q_vector->rx.count++;
021230d4
AV		 1975}
1976
1977static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 1978 int t_idx)
021230d4 1979{
7a921c93 1980 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 1981 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 1982
2274543f 1983 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 1984 tx_ring->next = q_vector->tx.ring;
1985 q_vector->tx.ring = tx_ring;
1986 q_vector->tx.count++;
bd198058 1987 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 1988}
1989
9a799d71 1990/**
021230d4
AV		 1991 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1992 * @adapter: board private structure to initialize
9a799d71 1993 *
021230d4
AV		 1994 * This function maps descriptor rings to the queue-specific vectors
1995 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1996 * one vector per ring/queue, but on a constrained vector budget, we
1997 * group the rings as "efficiently" as possible. You would add new
1998 * mapping configurations in here.
9a799d71 1999 **/
4cc6df29 2000static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2001{
4cc6df29
AD		 2002 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2003 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2004 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2005 int v_start = 0;
021230d4 2006
4cc6df29 2007 /* only one q_vector if MSI-X is disabled. */
021230d4 2008 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2009 q_vectors = 1;
d0759ebb 2010
021230d4 2011 /*
4cc6df29
AD		 2012 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2013 * group them so there are multiple queues per vector.
2014 *
2015 * Re-adjusting *qpv takes care of the remainder.
021230d4 2016 */
4cc6df29
AD		 2017 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2018 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2019 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2020 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2021 }
9a799d71 2022
021230d4 2023 /*
4cc6df29
AD		 2024 * If there are not enough q_vectors for each ring to have it's own
2025 * vector then we must pair up Rx/Tx on a each vector
021230d4 2026 */
4cc6df29
AD		 2027 if ((v_start + txr_remaining) > q_vectors)
2028 v_start = 0;
2029
2030 for (; v_start < q_vectors && txr_remaining; v_start++) {
2031 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2032 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2033 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2034 }
021230d4
AV		 2035}
2036
2037/**
2038 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2039 * @adapter: board private structure
2040 *
2041 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2042 * interrupts from the kernel.
2043 **/
2044static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2045{
2046 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2047 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2048 int vector, err;
e8e9f696 2049 int ri = 0, ti = 0;
021230d4 2050
021230d4 2051 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2052 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2053 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2054
4ff7fb12 2055 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2056 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2057 "%s-%s-%d", netdev->name, "TxRx", ri++);
2058 ti++;
2059 } else if (q_vector->rx.ring) {
9fe93afd 2060 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2061 "%s-%s-%d", netdev->name, "rx", ri++);
2062 } else if (q_vector->tx.ring) {
9fe93afd 2063 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2064 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2065 } else {
2066 /* skip this unused q_vector */
2067 continue;
32aa77a4 2068 }
207867f5
AD		 2069 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2070 q_vector->name, q_vector);
9a799d71 2071 if (err) {
396e799c 2072 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2073 "Error: %d\n", err);
021230d4 2074 goto free_queue_irqs;
9a799d71 2075 }
207867f5
AD		 2076 /* If Flow Director is enabled, set interrupt affinity */
2077 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2078 /* assign the mask for this irq */
2079 irq_set_affinity_hint(entry->vector,
2080 q_vector->affinity_mask);
2081 }
9a799d71
AK		 2082 }
2083
021230d4 2084 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2085 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2086 if (err) {
396e799c 2087 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2088 goto free_queue_irqs;
9a799d71
AK		 2089 }
2090
9a799d71
AK		 2091 return 0;
2092
021230d4 2093free_queue_irqs:
207867f5
AD		 2094 while (vector) {
2095 vector--;
2096 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2097 NULL);
2098 free_irq(adapter->msix_entries[vector].vector,
2099 adapter->q_vector[vector]);
2100 }
021230d4
AV		 2101 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2102 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2103 kfree(adapter->msix_entries);
2104 adapter->msix_entries = NULL;
9a799d71
AK		 2105 return err;
2106}
2107
2108/**
021230d4 2109 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2110 * @irq: interrupt number
2111 * @data: pointer to a network interface device structure
9a799d71
AK		 2112 **/
2113static irqreturn_t ixgbe_intr(int irq, void *data)
2114{
a65151ba 2115 struct ixgbe_adapter *adapter = data;
9a799d71 2116 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2117 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2118 u32 eicr;
2119
54037505 2120 /*
6af3b9eb 2121 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2122 * before the read of EICR.
2123 */
2124 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2125
021230d4
AV		 2126 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2127 * therefore no explict interrupt disable is necessary */
2128 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2129 if (!eicr) {
6af3b9eb
ET		 2130 /*
2131 * shared interrupt alert!
f47cf66e 2132 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2133 * have disabled interrupts due to EIAM
2134 * finish the workaround of silicon errata on 82598. Unmask
2135 * the interrupt that we masked before the EICR read.
2136 */
2137 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2138 ixgbe_irq_enable(adapter, true, true);
9a799d71 2139 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2140 }
9a799d71 2141
cf8280ee
JB		 2142 if (eicr & IXGBE_EICR_LSC)
2143 ixgbe_check_lsc(adapter);
021230d4 2144
bd508178
AD		 2145 switch (hw->mac.type) {
2146 case ixgbe_mac_82599EB:
e8e26350 2147 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2148 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2149 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2150 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2151 adapter->interrupt_event = eicr;
2152 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2153 ixgbe_service_event_schedule(adapter);
2154 }
bd508178
AD		 2155 }
2156 break;
2157 default:
2158 break;
2159 }
e8e26350 2160
0befdb3e
JB		 2161 ixgbe_check_fan_failure(adapter, eicr);
2162
7a921c93 2163 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2164 /* would disable interrupts here but EIAM disabled it */
7a921c93 2165 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2166 }
2167
6af3b9eb
ET		 2168 /*
2169 * re-enable link(maybe) and non-queue interrupts, no flush.
2170 * ixgbe_poll will re-enable the queue interrupts
2171 */
2172
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174 ixgbe_irq_enable(adapter, false, false);
2175
9a799d71
AK		 2176 return IRQ_HANDLED;
2177}
2178
021230d4
AV		 2179static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2180{
efe3d3c8
AD		 2181 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2182 int i;
2183
2184 /* legacy and MSI only use one vector */
2185 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2186 q_vectors = 1;
2187
2188 for (i = 0; i < adapter->num_rx_queues; i++) {
2189 adapter->rx_ring[i]->q_vector = NULL;
2190 adapter->rx_ring[i]->next = NULL;
2191 }
2192 for (i = 0; i < adapter->num_tx_queues; i++) {
2193 adapter->tx_ring[i]->q_vector = NULL;
2194 adapter->tx_ring[i]->next = NULL;
2195 }
021230d4
AV		 2196
2197 for (i = 0; i < q_vectors; i++) {
7a921c93 2198 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2199 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2200 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2201 }
2202}
2203
9a799d71
AK		 2204/**
2205 * ixgbe_request_irq - initialize interrupts
2206 * @adapter: board private structure
2207 *
2208 * Attempts to configure interrupts using the best available
2209 * capabilities of the hardware and kernel.
2210 **/
021230d4 2211static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2212{
2213 struct net_device *netdev = adapter->netdev;
021230d4 2214 int err;
9a799d71 2215
4cc6df29
AD		 2216 /* map all of the rings to the q_vectors */
2217 ixgbe_map_rings_to_vectors(adapter);
2218
2219 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2220 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2221 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2222 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2223 netdev->name, adapter);
4cc6df29 2224 else
a0607fd3 2225 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2226 netdev->name, adapter);
9a799d71 2227
4cc6df29 2228 if (err) {
396e799c 2229 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2230
4cc6df29
AD		 2231 /* place q_vectors and rings back into a known good state */
2232 ixgbe_reset_q_vectors(adapter);
2233 }
2234
9a799d71
AK		 2235 return err;
2236}
2237
2238static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2239{
9a799d71 2240 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2241 int i, q_vectors;
9a799d71 2242
021230d4 2243 q_vectors = adapter->num_msix_vectors;
021230d4 2244 i = q_vectors - 1;
a65151ba 2245 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2246 i--;
4cc6df29 2247
021230d4 2248 for (; i >= 0; i--) {
894ff7cf 2249 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2250 if (!adapter->q_vector[i]->rx.ring &&
2251 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2252 continue;
2253
207867f5
AD		 2254 /* clear the affinity_mask in the IRQ descriptor */
2255 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2256 NULL);
2257
021230d4 2258 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2259 adapter->q_vector[i]);
021230d4 2260 }
021230d4 2261 } else {
a65151ba 2262 free_irq(adapter->pdev->irq, adapter);
9a799d71 2263 }
207867f5
AD		 2264
2265 /* clear q_vector state information */
2266 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2267}
2268
22d5a71b
JB		 2269/**
2270 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2271 * @adapter: board private structure
2272 **/
2273static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2274{
bd508178
AD		 2275 switch (adapter->hw.mac.type) {
2276 case ixgbe_mac_82598EB:
835462fc 2277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2278 break;
2279 case ixgbe_mac_82599EB:
b93a2226 2280 case ixgbe_mac_X540:
835462fc
NS		 2281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2283 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2284 break;
2285 default:
2286 break;
22d5a71b
JB		 2287 }
2288 IXGBE_WRITE_FLUSH(&adapter->hw);
2289 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2290 int i;
2291 for (i = 0; i < adapter->num_msix_vectors; i++)
2292 synchronize_irq(adapter->msix_entries[i].vector);
2293 } else {
2294 synchronize_irq(adapter->pdev->irq);
2295 }
2296}
2297
9a799d71
AK		 2298/**
2299 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2300 *
2301 **/
2302static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2303{
9a799d71
AK		 2304 struct ixgbe_hw *hw = &adapter->hw;
2305
021230d4 2306 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2307 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2308
e8e26350
PW		 2309 ixgbe_set_ivar(adapter, 0, 0, 0);
2310 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2311
396e799c 2312 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2313}
2314
43e69bf0
AD		 2315/**
2316 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2317 * @adapter: board private structure
2318 * @ring: structure containing ring specific data
2319 *
2320 * Configure the Tx descriptor ring after a reset.
2321 **/
84418e3b
AD		 2322void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2323 struct ixgbe_ring *ring)
43e69bf0
AD		 2324{
2325 struct ixgbe_hw *hw = &adapter->hw;
2326 u64 tdba = ring->dma;
2f1860b8 2327 int wait_loop = 10;
b88c6de2 2328 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2329 u8 reg_idx = ring->reg_idx;
43e69bf0 2330
2f1860b8 2331 /* disable queue to avoid issues while updating state */
b88c6de2 2332 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2333 IXGBE_WRITE_FLUSH(hw);
2334
43e69bf0 2335 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2336 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2337 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2338 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2339 ring->count * sizeof(union ixgbe_adv_tx_desc));
2340 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2341 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2342 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2343
b88c6de2
AD		 2344 /*
2345 * set WTHRESH to encourage burst writeback, it should not be set
2346 * higher than 1 when ITR is 0 as it could cause false TX hangs
2347 *
2348 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2349 * to or less than the number of on chip descriptors, which is
2350 * currently 40.
2351 */
2352 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2353 txdctl |= (1 << 16); /* WTHRESH = 1 */
2354 else
2355 txdctl |= (8 << 16); /* WTHRESH = 8 */
2356
2357 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2358 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2359 32; /* PTHRESH = 32 */
2f1860b8
AD		 2360
2361 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2362 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2363 adapter->atr_sample_rate) {
2364 ring->atr_sample_rate = adapter->atr_sample_rate;
2365 ring->atr_count = 0;
2366 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2367 } else {
2368 ring->atr_sample_rate = 0;
2369 }
2f1860b8 2370
c84d324c
JF		 2371 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2372
2f1860b8 2373 /* enable queue */
2f1860b8
AD		 2374 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2375
2376 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2377 if (hw->mac.type == ixgbe_mac_82598EB &&
2378 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2379 return;
2380
2381 /* poll to verify queue is enabled */
2382 do {
032b4325 2383 usleep_range(1000, 2000);
2f1860b8
AD		 2384 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2385 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2386 if (!wait_loop)
2387 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2388}
2389
120ff942
AD		 2390static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2391{
2392 struct ixgbe_hw *hw = &adapter->hw;
2393 u32 rttdcs;
72a32f1f 2394 u32 reg;
8b1c0b24 2395 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2396
2397 if (hw->mac.type == ixgbe_mac_82598EB)
2398 return;
2399
2400 /* disable the arbiter while setting MTQC */
2401 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2402 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2403 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2404
2405 /* set transmit pool layout */
8b1c0b24 2406 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2407 case (IXGBE_FLAG_SRIOV_ENABLED):
2408 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2409 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2410 break;
8b1c0b24
JF		 2411 default:
2412 if (!tcs)
2413 reg = IXGBE_MTQC_64Q_1PB;
2414 else if (tcs <= 4)
2415 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2416 else
2417 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2418
8b1c0b24 2419 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2420
8b1c0b24
JF		 2421 /* Enable Security TX Buffer IFG for multiple pb */
2422 if (tcs) {
2423 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2424 reg |= IXGBE_SECTX_DCB;
2425 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2426 }
120ff942
AD		 2427 break;
2428 }
2429
2430 /* re-enable the arbiter */
2431 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2432 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2433}
2434
9a799d71 2435/**
3a581073 2436 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2437 * @adapter: board private structure
2438 *
2439 * Configure the Tx unit of the MAC after a reset.
2440 **/
2441static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2442{
2f1860b8
AD		 2443 struct ixgbe_hw *hw = &adapter->hw;
2444 u32 dmatxctl;
43e69bf0 2445 u32 i;
9a799d71 2446
2f1860b8
AD		 2447 ixgbe_setup_mtqc(adapter);
2448
2449 if (hw->mac.type != ixgbe_mac_82598EB) {
2450 /* DMATXCTL.EN must be before Tx queues are enabled */
2451 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2452 dmatxctl |= IXGBE_DMATXCTL_TE;
2453 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2454 }
2455
9a799d71 2456 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2457 for (i = 0; i < adapter->num_tx_queues; i++)
2458 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2459}
2460
e8e26350 2461#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2462
a6616b42 2463static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2464 struct ixgbe_ring *rx_ring)
cc41ac7c 2465{
cc41ac7c 2466 u32 srrctl;
bf29ee6c 2467 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2468
bd508178
AD		 2469 switch (adapter->hw.mac.type) {
2470 case ixgbe_mac_82598EB: {
2471 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2472 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2473 reg_idx = reg_idx & mask;
cc41ac7c 2474 }
bd508178
AD		 2475 break;
2476 case ixgbe_mac_82599EB:
b93a2226 2477 case ixgbe_mac_X540:
bd508178
AD		 2478 default:
2479 break;
2480 }
2481
bf29ee6c 2482 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2483
2484 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2485 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2486 if (adapter->num_vfs)
2487 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2488
afafd5b0
AD		 2489 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2490 IXGBE_SRRCTL_BSIZEHDR_MASK;
2491
7d637bcc 2492 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2493#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2494 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2495#else
2496 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2497#endif
cc41ac7c 2498 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2499 } else {
afafd5b0
AD		 2500 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2501 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2502 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2503 }
e8e26350 2504
bf29ee6c 2505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2506}
9a799d71 2507
05abb126 2508static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2509{
05abb126
AD		 2510 struct ixgbe_hw *hw = &adapter->hw;
2511 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2512 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2513 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2514 u32 mrqc = 0, reta = 0;
2515 u32 rxcsum;
2516 int i, j;
8b1c0b24 2517 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2518 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2519
2520 if (tcs)
2521 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2522
05abb126
AD		 2523 /* Fill out hash function seeds */
2524 for (i = 0; i < 10; i++)
2525 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2526
2527 /* Fill out redirection table */
2528 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2529 if (j == maxq)
05abb126
AD		 2530 j = 0;
2531 /* reta = 4-byte sliding window of
2532 * 0x00..(indices-1)(indices-1)00..etc. */
2533 reta = (reta << 8) | (j * 0x11);
2534 if ((i & 3) == 3)
2535 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2536 }
0cefafad 2537
05abb126
AD		 2538 /* Disable indicating checksum in descriptor, enables RSS hash */
2539 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2540 rxcsum |= IXGBE_RXCSUM_PCSD;
2541 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2542
8b1c0b24
JF		 2543 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2544 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2545 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2546 } else {
2547 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2548 | IXGBE_FLAG_SRIOV_ENABLED);
2549
2550 switch (mask) {
2551 case (IXGBE_FLAG_RSS_ENABLED):
2552 if (!tcs)
2553 mrqc = IXGBE_MRQC_RSSEN;
2554 else if (tcs <= 4)
2555 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2556 else
2557 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2558 break;
2559 case (IXGBE_FLAG_SRIOV_ENABLED):
2560 mrqc = IXGBE_MRQC_VMDQEN;
2561 break;
2562 default:
2563 break;
2564 }
0cefafad
JB		 2565 }
2566
05abb126
AD		 2567 /* Perform hash on these packet types */
2568 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2569 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2570 | IXGBE_MRQC_RSS_FIELD_IPV6
2571 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2572
2573 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2574}
2575
bb5a9ad2
NS		 2576/**
2577 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2578 * @adapter: address of board private structure
2579 * @index: index of ring to set
bb5a9ad2 2580 **/
082757af 2581static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2582 struct ixgbe_ring *ring)
bb5a9ad2 2583{
bb5a9ad2 2584 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2585 u32 rscctrl;
edd2ea55 2586 int rx_buf_len;
bf29ee6c 2587 u8 reg_idx = ring->reg_idx;
7367096a 2588
7d637bcc 2589 if (!ring_is_rsc_enabled(ring))
7367096a 2590 return;
bb5a9ad2 2591
7367096a
AD		 2592 rx_buf_len = ring->rx_buf_len;
2593 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2594 rscctrl |= IXGBE_RSCCTL_RSCEN;
2595 /*
2596 * we must limit the number of descriptors so that the
2597 * total size of max desc * buf_len is not greater
2598 * than 65535
2599 */
7d637bcc 2600 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2601#if (MAX_SKB_FRAGS > 16)
2602 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2603#elif (MAX_SKB_FRAGS > 8)
2604 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2605#elif (MAX_SKB_FRAGS > 4)
2606 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2607#else
2608 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2609#endif
2610 } else {
919e78a6 2611 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2612 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2613 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2614 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2615 else
2616 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2617 }
7367096a 2618 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2619}
2620
9e10e045
AD		 2621/**
2622 * ixgbe_set_uta - Set unicast filter table address
2623 * @adapter: board private structure
2624 *
2625 * The unicast table address is a register array of 32-bit registers.
2626 * The table is meant to be used in a way similar to how the MTA is used
2627 * however due to certain limitations in the hardware it is necessary to
2628 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2629 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2630 **/
2631static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2632{
2633 struct ixgbe_hw *hw = &adapter->hw;
2634 int i;
2635
2636 /* The UTA table only exists on 82599 hardware and newer */
2637 if (hw->mac.type < ixgbe_mac_82599EB)
2638 return;
2639
2640 /* we only need to do this if VMDq is enabled */
2641 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2642 return;
2643
2644 for (i = 0; i < 128; i++)
2645 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2646}
2647
2648#define IXGBE_MAX_RX_DESC_POLL 10
2649static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2650 struct ixgbe_ring *ring)
2651{
2652 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2653 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2654 u32 rxdctl;
bf29ee6c 2655 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2656
2657 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2658 if (hw->mac.type == ixgbe_mac_82598EB &&
2659 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2660 return;
2661
2662 do {
032b4325 2663 usleep_range(1000, 2000);
9e10e045
AD		 2664 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2665 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2666
2667 if (!wait_loop) {
2668 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2669 "the polling period\n", reg_idx);
2670 }
2671}
2672
2d39d576
YZ		 2673void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2674 struct ixgbe_ring *ring)
2675{
2676 struct ixgbe_hw *hw = &adapter->hw;
2677 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2678 u32 rxdctl;
2679 u8 reg_idx = ring->reg_idx;
2680
2681 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2682 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2683
2684 /* write value back with RXDCTL.ENABLE bit cleared */
2685 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2686
2687 if (hw->mac.type == ixgbe_mac_82598EB &&
2688 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2689 return;
2690
2691 /* the hardware may take up to 100us to really disable the rx queue */
2692 do {
2693 udelay(10);
2694 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2695 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2696
2697 if (!wait_loop) {
2698 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2699 "the polling period\n", reg_idx);
2700 }
2701}
2702
84418e3b
AD		 2703void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2704 struct ixgbe_ring *ring)
acd37177
AD		 2705{
2706 struct ixgbe_hw *hw = &adapter->hw;
2707 u64 rdba = ring->dma;
9e10e045 2708 u32 rxdctl;
bf29ee6c 2709 u8 reg_idx = ring->reg_idx;
acd37177 2710
9e10e045
AD		 2711 /* disable queue to avoid issues while updating state */
2712 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2713 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2714
acd37177
AD		 2715 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2716 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2717 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2718 ring->count * sizeof(union ixgbe_adv_rx_desc));
2719 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2720 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2721 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2722
2723 ixgbe_configure_srrctl(adapter, ring);
2724 ixgbe_configure_rscctl(adapter, ring);
2725
e9f98072
GR		 2726 /* If operating in IOV mode set RLPML for X540 */
2727 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2728 hw->mac.type == ixgbe_mac_X540) {
2729 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2730 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2731 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2732 }
2733
9e10e045
AD		 2734 if (hw->mac.type == ixgbe_mac_82598EB) {
2735 /*
2736 * enable cache line friendly hardware writes:
2737 * PTHRESH=32 descriptors (half the internal cache),
2738 * this also removes ugly rx_no_buffer_count increment
2739 * HTHRESH=4 descriptors (to minimize latency on fetch)
2740 * WTHRESH=8 burst writeback up to two cache lines
2741 */
2742 rxdctl &= ~0x3FFFFF;
2743 rxdctl |= 0x080420;
2744 }
2745
2746 /* enable receive descriptor ring */
2747 rxdctl |= IXGBE_RXDCTL_ENABLE;
2748 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2749
2750 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2751 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2752}
2753
48654521
AD		 2754static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2755{
2756 struct ixgbe_hw *hw = &adapter->hw;
2757 int p;
2758
2759 /* PSRTYPE must be initialized in non 82598 adapters */
2760 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2761 IXGBE_PSRTYPE_UDPHDR |
2762 IXGBE_PSRTYPE_IPV4HDR |
48654521 2763 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2764 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2765
2766 if (hw->mac.type == ixgbe_mac_82598EB)
2767 return;
2768
2769 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2770 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2771
2772 for (p = 0; p < adapter->num_rx_pools; p++)
2773 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2774 psrtype);
2775}
2776
f5b4a52e
AD		 2777static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2778{
2779 struct ixgbe_hw *hw = &adapter->hw;
2780 u32 gcr_ext;
2781 u32 vt_reg_bits;
2782 u32 reg_offset, vf_shift;
2783 u32 vmdctl;
2784
2785 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2786 return;
2787
2788 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2789 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2790 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2791 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2792
2793 vf_shift = adapter->num_vfs % 32;
2794 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2795
2796 /* Enable only the PF's pool for Tx/Rx */
2797 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2798 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2799 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2800 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2801 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2802
2803 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2804 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2805
2806 /*
2807 * Set up VF register offsets for selected VT Mode,
2808 * i.e. 32 or 64 VFs for SR-IOV
2809 */
2810 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2811 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2812 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2813 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2814
2815 /* enable Tx loopback for VF/PF communication */
2816 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2817 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 2818 hw->mac.ops.set_mac_anti_spoofing(hw,
2819 (adapter->antispoofing_enabled =
2820 (adapter->num_vfs != 0)),
a985b6c3 2821 adapter->num_vfs);
f5b4a52e
AD		 2822}
2823
477de6ed 2824static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2825{
9a799d71
AK		 2826 struct ixgbe_hw *hw = &adapter->hw;
2827 struct net_device *netdev = adapter->netdev;
2828 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2829 int rx_buf_len;
477de6ed
AD		 2830 struct ixgbe_ring *rx_ring;
2831 int i;
2832 u32 mhadd, hlreg0;
48654521 2833
9a799d71 2834 /* Decide whether to use packet split mode or not */
a124339a
DS		 2835 /* On by default */
2836 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2837
1cdd1ec8 2838 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2839 if (adapter->num_vfs)
2840 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2841
2842 /* Disable packet split due to 82599 erratum #45 */
2843 if (hw->mac.type == ixgbe_mac_82599EB)
2844 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2845
63f39bd1 2846#ifdef IXGBE_FCOE
477de6ed
AD		 2847 /* adjust max frame to be able to do baby jumbo for FCoE */
2848 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2849 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2850 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2851
477de6ed
AD		 2852#endif /* IXGBE_FCOE */
2853 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2854 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2855 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2856 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2857
2858 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2859 }
2860
919e78a6
AD		 2861 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2862 max_frame += VLAN_HLEN;
2863
2864 /* Set the RX buffer length according to the mode */
2865 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2866 rx_buf_len = IXGBE_RX_HDR_SIZE;
2867 } else {
2868 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2869 (netdev->mtu <= ETH_DATA_LEN))
2870 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2871 /*
2872 * Make best use of allocation by using all but 1K of a
2873 * power of 2 allocation that will be used for skb->head.
2874 */
2875 else if (max_frame <= IXGBE_RXBUFFER_3K)
2876 rx_buf_len = IXGBE_RXBUFFER_3K;
2877 else if (max_frame <= IXGBE_RXBUFFER_7K)
2878 rx_buf_len = IXGBE_RXBUFFER_7K;
2879 else if (max_frame <= IXGBE_RXBUFFER_15K)
2880 rx_buf_len = IXGBE_RXBUFFER_15K;
2881 else
2882 rx_buf_len = IXGBE_MAX_RXBUFFER;
2883 }
2884
477de6ed
AD		 2885 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2886 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2887 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2888 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2889
0cefafad
JB		 2890 /*
2891 * Setup the HW Rx Head and Tail Descriptor Pointers and
2892 * the Base and Length of the Rx Descriptor Ring
2893 */
9a799d71 2894 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2895 rx_ring = adapter->rx_ring[i];
a6616b42 2896 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2897
6e455b89 2898 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2899 set_ring_ps_enabled(rx_ring);
2900 else
2901 clear_ring_ps_enabled(rx_ring);
2902
2903 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2904 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2905 else
7d637bcc 2906 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2907
63f39bd1 2908#ifdef IXGBE_FCOE
e8e9f696 2909 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2910 struct ixgbe_ring_feature *f;
2911 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2912 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2913 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2914 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2915 rx_ring->rx_buf_len =
e8e9f696 2916 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2917 } else if (!ring_is_rsc_enabled(rx_ring) &&
2918 !ring_is_ps_enabled(rx_ring)) {
2919 rx_ring->rx_buf_len =
2920 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2921 }
63f39bd1 2922 }
63f39bd1 2923#endif /* IXGBE_FCOE */
477de6ed 2924 }
477de6ed
AD		 2925}
2926
7367096a
AD		 2927static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2928{
2929 struct ixgbe_hw *hw = &adapter->hw;
2930 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2931
2932 switch (hw->mac.type) {
2933 case ixgbe_mac_82598EB:
2934 /*
2935 * For VMDq support of different descriptor types or
2936 * buffer sizes through the use of multiple SRRCTL
2937 * registers, RDRXCTL.MVMEN must be set to 1
2938 *
2939 * also, the manual doesn't mention it clearly but DCA hints
2940 * will only use queue 0's tags unless this bit is set. Side
2941 * effects of setting this bit are only that SRRCTL must be
2942 * fully programmed [0..15]
2943 */
2944 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2945 break;
2946 case ixgbe_mac_82599EB:
b93a2226 2947 case ixgbe_mac_X540:
7367096a
AD		 2948 /* Disable RSC for ACK packets */
2949 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2950 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2951 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2952 /* hardware requires some bits to be set by default */
2953 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2954 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2955 break;
2956 default:
2957 /* We should do nothing since we don't know this hardware */
2958 return;
2959 }
2960
2961 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2962}
2963
477de6ed
AD		 2964/**
2965 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2966 * @adapter: board private structure
2967 *
2968 * Configure the Rx unit of the MAC after a reset.
2969 **/
2970static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2971{
2972 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 2973 int i;
2974 u32 rxctrl;
477de6ed
AD		 2975
2976 /* disable receives while setting up the descriptors */
2977 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2978 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2979
2980 ixgbe_setup_psrtype(adapter);
7367096a 2981 ixgbe_setup_rdrxctl(adapter);
477de6ed 2982
9e10e045 2983 /* Program registers for the distribution of queues */
f5b4a52e 2984 ixgbe_setup_mrqc(adapter);
f5b4a52e 2985
9e10e045
AD		 2986 ixgbe_set_uta(adapter);
2987
477de6ed
AD		 2988 /* set_rx_buffer_len must be called before ring initialization */
2989 ixgbe_set_rx_buffer_len(adapter);
2990
2991 /*
2992 * Setup the HW Rx Head and Tail Descriptor Pointers and
2993 * the Base and Length of the Rx Descriptor Ring
2994 */
9e10e045
AD		 2995 for (i = 0; i < adapter->num_rx_queues; i++)
2996 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 2997
9e10e045
AD		 2998 /* disable drop enable for 82598 parts */
2999 if (hw->mac.type == ixgbe_mac_82598EB)
3000 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3001
3002 /* enable all receives */
3003 rxctrl |= IXGBE_RXCTRL_RXEN;
3004 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3005}
3006
068c89b0
DS		 3007static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3008{
3009 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3010 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3011 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3012
3013 /* add VID to filter table */
1ada1b1b 3014 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3015 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3016}
3017
3018static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3019{
3020 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3021 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3022 int pool_ndx = adapter->num_vfs;
068c89b0 3023
068c89b0 3024 /* remove VID from filter table */
1ada1b1b 3025 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3026 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3027}
3028
5f6c0181
JB		 3029/**
3030 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3031 * @adapter: driver data
3032 */
3033static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3034{
3035 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3036 u32 vlnctrl;
3037
3038 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3039 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3040 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3041}
3042
3043/**
3044 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3045 * @adapter: driver data
3046 */
3047static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3048{
3049 struct ixgbe_hw *hw = &adapter->hw;
3050 u32 vlnctrl;
3051
3052 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3053 vlnctrl |= IXGBE_VLNCTRL_VFE;
3054 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3055 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3056}
3057
3058/**
3059 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3060 * @adapter: driver data
3061 */
3062static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3063{
3064 struct ixgbe_hw *hw = &adapter->hw;
3065 u32 vlnctrl;
5f6c0181
JB		 3066 int i, j;
3067
3068 switch (hw->mac.type) {
3069 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3070 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3071 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3072 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3073 break;
3074 case ixgbe_mac_82599EB:
b93a2226 3075 case ixgbe_mac_X540:
5f6c0181
JB		 3076 for (i = 0; i < adapter->num_rx_queues; i++) {
3077 j = adapter->rx_ring[i]->reg_idx;
3078 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3079 vlnctrl &= ~IXGBE_RXDCTL_VME;
3080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3081 }
3082 break;
3083 default:
3084 break;
3085 }
3086}
3087
3088/**
f62bbb5e 3089 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3090 * @adapter: driver data
3091 */
f62bbb5e 3092static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3093{
3094 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3095 u32 vlnctrl;
5f6c0181
JB		 3096 int i, j;
3097
3098 switch (hw->mac.type) {
3099 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3100 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3101 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3102 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3103 break;
3104 case ixgbe_mac_82599EB:
b93a2226 3105 case ixgbe_mac_X540:
5f6c0181
JB		 3106 for (i = 0; i < adapter->num_rx_queues; i++) {
3107 j = adapter->rx_ring[i]->reg_idx;
3108 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3109 vlnctrl |= IXGBE_RXDCTL_VME;
3110 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3111 }
3112 break;
3113 default:
3114 break;
3115 }
3116}
3117
9a799d71
AK		 3118static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3119{
f62bbb5e 3120 u16 vid;
9a799d71 3121
f62bbb5e
JG		 3122 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3123
3124 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3125 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3126}
3127
2850062a
AD		 3128/**
3129 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3130 * @netdev: network interface device structure
3131 *
3132 * Writes unicast address list to the RAR table.
3133 * Returns: -ENOMEM on failure/insufficient address space
3134 * 0 on no addresses written
3135 * X on writing X addresses to the RAR table
3136 **/
3137static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3138{
3139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3140 struct ixgbe_hw *hw = &adapter->hw;
3141 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3142 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3143 int count = 0;
3144
3145 /* return ENOMEM indicating insufficient memory for addresses */
3146 if (netdev_uc_count(netdev) > rar_entries)
3147 return -ENOMEM;
3148
3149 if (!netdev_uc_empty(netdev) && rar_entries) {
3150 struct netdev_hw_addr *ha;
3151 /* return error if we do not support writing to RAR table */
3152 if (!hw->mac.ops.set_rar)
3153 return -ENOMEM;
3154
3155 netdev_for_each_uc_addr(ha, netdev) {
3156 if (!rar_entries)
3157 break;
3158 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3159 vfn, IXGBE_RAH_AV);
3160 count++;
3161 }
3162 }
3163 /* write the addresses in reverse order to avoid write combining */
3164 for (; rar_entries > 0 ; rar_entries--)
3165 hw->mac.ops.clear_rar(hw, rar_entries);
3166
3167 return count;
3168}
3169
9a799d71 3170/**
2c5645cf 3171 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3172 * @netdev: network interface device structure
3173 *
2c5645cf
CL		 3174 * The set_rx_method entry point is called whenever the unicast/multicast
3175 * address list or the network interface flags are updated. This routine is
3176 * responsible for configuring the hardware for proper unicast, multicast and
3177 * promiscuous mode.
9a799d71 3178 **/
7f870475 3179void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3180{
3181 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3182 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3183 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3184 int count;
9a799d71
AK		 3185
3186 /* Check for Promiscuous and All Multicast modes */
3187
3188 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3189
f5dc442b
AD		 3190 /* set all bits that we expect to always be set */
3191 fctrl |= IXGBE_FCTRL_BAM;
3192 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3193 fctrl |= IXGBE_FCTRL_PMCF;
3194
2850062a
AD		 3195 /* clear the bits we are changing the status of */
3196 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3197
9a799d71 3198 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3199 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3200 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3201 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3202 /* don't hardware filter vlans in promisc mode */
3203 ixgbe_vlan_filter_disable(adapter);
9a799d71 3204 } else {
746b9f02
PM		 3205 if (netdev->flags & IFF_ALLMULTI) {
3206 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3207 vmolr |= IXGBE_VMOLR_MPE;
3208 } else {
3209 /*
3210 * Write addresses to the MTA, if the attempt fails
25985edc 3211 * then we should just turn on promiscuous mode so
2850062a
AD		 3212 * that we can at least receive multicast traffic
3213 */
3214 hw->mac.ops.update_mc_addr_list(hw, netdev);
3215 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3216 }
5f6c0181 3217 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3218 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3219 /*
3220 * Write addresses to available RAR registers, if there is not
3221 * sufficient space to store all the addresses then enable
25985edc 3222 * unicast promiscuous mode
2850062a
AD		 3223 */
3224 count = ixgbe_write_uc_addr_list(netdev);
3225 if (count < 0) {
3226 fctrl |= IXGBE_FCTRL_UPE;
3227 vmolr |= IXGBE_VMOLR_ROPE;
3228 }
9a799d71
AK		 3229 }
3230
2850062a 3231 if (adapter->num_vfs) {
1cdd1ec8 3232 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3233 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3234 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3235 IXGBE_VMOLR_ROPE);
3236 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3237 }
3238
3239 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3240
3241 if (netdev->features & NETIF_F_HW_VLAN_RX)
3242 ixgbe_vlan_strip_enable(adapter);
3243 else
3244 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3245}
3246
021230d4
AV		 3247static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3248{
3249 int q_idx;
3250 struct ixgbe_q_vector *q_vector;
3251 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3252
3253 /* legacy and MSI only use one vector */
3254 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3255 q_vectors = 1;
3256
3257 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3258 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3259 napi_enable(&q_vector->napi);
021230d4
AV		 3260 }
3261}
3262
3263static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3264{
3265 int q_idx;
3266 struct ixgbe_q_vector *q_vector;
3267 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3268
3269 /* legacy and MSI only use one vector */
3270 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3271 q_vectors = 1;
3272
3273 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3274 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3275 napi_disable(&q_vector->napi);
3276 }
3277}
3278
7a6b6f51 3279#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3280/*
3281 * ixgbe_configure_dcb - Configure DCB hardware
3282 * @adapter: ixgbe adapter struct
3283 *
3284 * This is called by the driver on open to configure the DCB hardware.
3285 * This is also called by the gennetlink interface when reconfiguring
3286 * the DCB state.
3287 */
3288static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3289{
3290 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3291 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3292
67ebd791
AD		 3293 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3294 if (hw->mac.type == ixgbe_mac_82598EB)
3295 netif_set_gso_max_size(adapter->netdev, 65536);
3296 return;
3297 }
3298
3299 if (hw->mac.type == ixgbe_mac_82598EB)
3300 netif_set_gso_max_size(adapter->netdev, 32768);
3301
2f90b865 3302
2f90b865 3303 /* Enable VLAN tag insert/strip */
f62bbb5e 3304 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3305
2f90b865 3306 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3307
3308 /* reconfigure the hardware */
6f70f6ac 3309 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
971060b1 3310#ifdef IXGBE_FCOE
c27931da
JF		 3311 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3312 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3313#endif
3314 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3315 DCB_TX_CONFIG);
3316 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3317 DCB_RX_CONFIG);
3318 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3319 } else {
3320 struct net_device *dev = adapter->netdev;
3321
4c09f3a0
JF		 3322 if (adapter->ixgbe_ieee_ets) {
3323 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
3324 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3325
3326 ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
3327 }
3328
3329 if (adapter->ixgbe_ieee_pfc) {
3330 struct ieee_pfc *pfc = adapter->ixgbe_ieee_pfc;
3331
3332 ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc->pfc_en);
3333 }
c27931da 3334 }
8187cd48
JF		 3335
3336 /* Enable RSS Hash per TC */
3337 if (hw->mac.type != ixgbe_mac_82598EB) {
3338 int i;
3339 u32 reg = 0;
3340
3341 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3342 u8 msb = 0;
3343 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3344
3345 while (cnt >>= 1)
3346 msb++;
3347
3348 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3349 }
3350 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3351 }
2f90b865
AD		 3352}
3353
3354#endif
80605c65
JF		 3355
3356static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3357{
80605c65 3358 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3359 int hdrm;
3360 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3361
3362 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3363 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3364 hdrm = 32 << adapter->fdir_pballoc;
3365 else
3366 hdrm = 0;
80605c65 3367
f7e1027f 3368 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
80605c65
JF		 3369}
3370
e4911d57
AD		 3371static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3372{
3373 struct ixgbe_hw *hw = &adapter->hw;
3374 struct hlist_node *node, *node2;
3375 struct ixgbe_fdir_filter *filter;
3376
3377 spin_lock(&adapter->fdir_perfect_lock);
3378
3379 if (!hlist_empty(&adapter->fdir_filter_list))
3380 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3381
3382 hlist_for_each_entry_safe(filter, node, node2,
3383 &adapter->fdir_filter_list, fdir_node) {
3384 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3385 &filter->filter,
3386 filter->sw_idx,
3387 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3388 IXGBE_FDIR_DROP_QUEUE :
3389 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3390 }
3391
3392 spin_unlock(&adapter->fdir_perfect_lock);
3393}
3394
9a799d71
AK		 3395static void ixgbe_configure(struct ixgbe_adapter *adapter)
3396{
80605c65 3397 ixgbe_configure_pb(adapter);
7a6b6f51 3398#ifdef CONFIG_IXGBE_DCB
67ebd791 3399 ixgbe_configure_dcb(adapter);
2f90b865 3400#endif
9a799d71 3401
4c1d7b4b 3402 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3403 ixgbe_restore_vlan(adapter);
3404
eacd73f7
YZ		 3405#ifdef IXGBE_FCOE
3406 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3407 ixgbe_configure_fcoe(adapter);
3408
3409#endif /* IXGBE_FCOE */
c4cf55e5 3410 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3411 ixgbe_init_fdir_signature_82599(&adapter->hw,
3412 adapter->fdir_pballoc);
e4911d57
AD		 3413 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3414 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3415 adapter->fdir_pballoc);
3416 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3417 }
4c1d7b4b 3418
933d41f1 3419 ixgbe_configure_virtualization(adapter);
c4cf55e5 3420
9a799d71
AK		 3421 ixgbe_configure_tx(adapter);
3422 ixgbe_configure_rx(adapter);
9a799d71
AK		 3423}
3424
e8e26350
PW		 3425static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3426{
3427 switch (hw->phy.type) {
3428 case ixgbe_phy_sfp_avago:
3429 case ixgbe_phy_sfp_ftl:
3430 case ixgbe_phy_sfp_intel:
3431 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3432 case ixgbe_phy_sfp_passive_tyco:
3433 case ixgbe_phy_sfp_passive_unknown:
3434 case ixgbe_phy_sfp_active_unknown:
3435 case ixgbe_phy_sfp_ftl_active:
e8e26350 3436 return true;
8917b447
AD		 3437 case ixgbe_phy_nl:
3438 if (hw->mac.type == ixgbe_mac_82598EB)
3439 return true;
e8e26350
PW		 3440 default:
3441 return false;
3442 }
3443}
3444
0ecc061d 3445/**
e8e26350
PW		 3446 * ixgbe_sfp_link_config - set up SFP+ link
3447 * @adapter: pointer to private adapter struct
3448 **/
3449static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3450{
7086400d
AD		 3451 /*
3452 * We are assuming the worst case scenerio here, and that
3453 * is that an SFP was inserted/removed after the reset
3454 * but before SFP detection was enabled. As such the best
3455 * solution is to just start searching as soon as we start
3456 */
3457 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3458 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3459
7086400d 3460 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3461}
3462
3463/**
3464 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3465 * @hw: pointer to private hardware struct
3466 *
3467 * Returns 0 on success, negative on failure
3468 **/
e8e26350 3469static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3470{
3471 u32 autoneg;
8620a103 3472 bool negotiation, link_up = false;
0ecc061d
PWJ		 3473 u32 ret = IXGBE_ERR_LINK_SETUP;
3474
3475 if (hw->mac.ops.check_link)
3476 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3477
3478 if (ret)
3479 goto link_cfg_out;
3480
0b0c2b31
ET		 3481 autoneg = hw->phy.autoneg_advertised;
3482 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3483 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3484 &negotiation);
0ecc061d
PWJ		 3485 if (ret)
3486 goto link_cfg_out;
3487
8620a103
MC		 3488 if (hw->mac.ops.setup_link)
3489 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3490link_cfg_out:
3491 return ret;
3492}
3493
a34bcfff 3494static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3495{
9a799d71 3496 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3497 u32 gpie = 0;
9a799d71 3498
9b471446 3499 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3500 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3501 IXGBE_GPIE_OCD;
3502 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3503 /*
3504 * use EIAM to auto-mask when MSI-X interrupt is asserted
3505 * this saves a register write for every interrupt
3506 */
3507 switch (hw->mac.type) {
3508 case ixgbe_mac_82598EB:
3509 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3510 break;
9b471446 3511 case ixgbe_mac_82599EB:
b93a2226
DS		 3512 case ixgbe_mac_X540:
3513 default:
9b471446
JB		 3514 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3515 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3516 break;
3517 }
3518 } else {
021230d4
AV		 3519 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3520 * specifically only auto mask tx and rx interrupts */
3521 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3522 }
9a799d71 3523
a34bcfff
AD		 3524 /* XXX: to interrupt immediately for EICS writes, enable this */
3525 /* gpie |= IXGBE_GPIE_EIMEN; */
3526
3527 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3528 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3529 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3530 }
3531
5fdd31f9
AD		 3532 /* Enable Thermal over heat sensor interrupt */
3533 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3534 gpie |= IXGBE_SDP0_GPIEN;
3535
a34bcfff
AD		 3536 /* Enable fan failure interrupt */
3537 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3538 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3539
2698b208 3540 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3541 gpie |= IXGBE_SDP1_GPIEN;
3542 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3543 }
a34bcfff
AD		 3544
3545 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3546}
3547
c7ccde0f 3548static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3549{
3550 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3551 int err;
a34bcfff
AD		 3552 u32 ctrl_ext;
3553
3554 ixgbe_get_hw_control(adapter);
3555 ixgbe_setup_gpie(adapter);
e8e26350 3556
9a799d71
AK		 3557 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3558 ixgbe_configure_msix(adapter);
3559 else
3560 ixgbe_configure_msi_and_legacy(adapter);
3561
c6ecf39a
DS		 3562 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3563 if (hw->mac.ops.enable_tx_laser &&
3564 ((hw->phy.multispeed_fiber) ||
9f911707 3565 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3566 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3567 hw->mac.ops.enable_tx_laser(hw);
3568
9a799d71 3569 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3570 ixgbe_napi_enable_all(adapter);
3571
73c4b7cd
AD		 3572 if (ixgbe_is_sfp(hw)) {
3573 ixgbe_sfp_link_config(adapter);
3574 } else {
3575 err = ixgbe_non_sfp_link_config(hw);
3576 if (err)
3577 e_err(probe, "link_config FAILED %d\n", err);
3578 }
3579
021230d4
AV		 3580 /* clear any pending interrupts, may auto mask */
3581 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3582 ixgbe_irq_enable(adapter, true, true);
9a799d71 3583
bf069c97
DS		 3584 /*
3585 * If this adapter has a fan, check to see if we had a failure
3586 * before we enabled the interrupt.
3587 */
3588 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3589 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3590 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3591 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3592 }
3593
1da100bb 3594 /* enable transmits */
477de6ed 3595 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3596
9a799d71
AK		 3597 /* bring the link up in the watchdog, this could race with our first
3598 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3599 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3600 adapter->link_check_timeout = jiffies;
7086400d 3601 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3602
3603 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3604 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3605 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3606 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3607}
3608
d4f80882
AV		 3609void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3610{
3611 WARN_ON(in_interrupt());
7086400d
AD		 3612 /* put off any impending NetWatchDogTimeout */
3613 adapter->netdev->trans_start = jiffies;
3614
d4f80882 3615 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3616 usleep_range(1000, 2000);
d4f80882 3617 ixgbe_down(adapter);
5809a1ae
GR		 3618 /*
3619 * If SR-IOV enabled then wait a bit before bringing the adapter
3620 * back up to give the VFs time to respond to the reset. The
3621 * two second wait is based upon the watchdog timer cycle in
3622 * the VF driver.
3623 */
3624 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3625 msleep(2000);
d4f80882
AV		 3626 ixgbe_up(adapter);
3627 clear_bit(__IXGBE_RESETTING, &adapter->state);
3628}
3629
c7ccde0f 3630void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3631{
3632 /* hardware has been reset, we need to reload some things */
3633 ixgbe_configure(adapter);
3634
c7ccde0f 3635 ixgbe_up_complete(adapter);
9a799d71
AK		 3636}
3637
3638void ixgbe_reset(struct ixgbe_adapter *adapter)
3639{
c44ade9e 3640 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3641 int err;
3642
7086400d
AD		 3643 /* lock SFP init bit to prevent race conditions with the watchdog */
3644 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3645 usleep_range(1000, 2000);
3646
3647 /* clear all SFP and link config related flags while holding SFP_INIT */
3648 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3649 IXGBE_FLAG2_SFP_NEEDS_RESET);
3650 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3651
8ca783ab 3652 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3653 switch (err) {
3654 case 0:
3655 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3656 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3657 break;
3658 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3659 e_dev_err("master disable timed out\n");
da4dd0f7 3660 break;
794caeb2
PWJ		 3661 case IXGBE_ERR_EEPROM_VERSION:
3662 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3663 e_dev_warn("This device is a pre-production adapter/LOM. "
3664 "Please be aware there may be issuesassociated with "
3665 "your hardware. If you are experiencing problems "
3666 "please contact your Intel or hardware "
3667 "representative who provided you with this "
3668 "hardware.\n");
794caeb2 3669 break;
da4dd0f7 3670 default:
849c4542 3671 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3672 }
9a799d71 3673
7086400d
AD		 3674 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3675
9a799d71 3676 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3677 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3678 IXGBE_RAH_AV);
9a799d71
AK		 3679}
3680
9a799d71
AK		 3681/**
3682 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3683 * @rx_ring: ring to free buffers from
3684 **/
b6ec895e 3685static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3686{
b6ec895e 3687 struct device *dev = rx_ring->dev;
9a799d71 3688 unsigned long size;
b6ec895e 3689 u16 i;
9a799d71 3690
84418e3b
AD		 3691 /* ring already cleared, nothing to do */
3692 if (!rx_ring->rx_buffer_info)
3693 return;
9a799d71 3694
84418e3b 3695 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3696 for (i = 0; i < rx_ring->count; i++) {
3697 struct ixgbe_rx_buffer *rx_buffer_info;
3698
3699 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3700 if (rx_buffer_info->dma) {
b6ec895e 3701 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3702 rx_ring->rx_buf_len,
1b507730 3703 DMA_FROM_DEVICE);
9a799d71
AK		 3704 rx_buffer_info->dma = 0;
3705 }
3706 if (rx_buffer_info->skb) {
f8212f97 3707 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3708 rx_buffer_info->skb = NULL;
f8212f97
AD		 3709 do {
3710 struct sk_buff *this = skb;
e8171aaa 3711 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3712 dma_unmap_single(dev,
1b507730 3713 IXGBE_RSC_CB(this)->dma,
e8e9f696 3714 rx_ring->rx_buf_len,
1b507730 3715 DMA_FROM_DEVICE);
fd3686a8 3716 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3717 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3718 }
f8212f97
AD		 3719 skb = skb->prev;
3720 dev_kfree_skb(this);
3721 } while (skb);
9a799d71
AK		 3722 }
3723 if (!rx_buffer_info->page)
3724 continue;
4f57ca6e 3725 if (rx_buffer_info->page_dma) {
b6ec895e 3726 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3727 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3728 rx_buffer_info->page_dma = 0;
3729 }
9a799d71
AK		 3730 put_page(rx_buffer_info->page);
3731 rx_buffer_info->page = NULL;
762f4c57 3732 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3733 }
3734
3735 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3736 memset(rx_ring->rx_buffer_info, 0, size);
3737
3738 /* Zero out the descriptor ring */
3739 memset(rx_ring->desc, 0, rx_ring->size);
3740
3741 rx_ring->next_to_clean = 0;
3742 rx_ring->next_to_use = 0;
9a799d71
AK		 3743}
3744
3745/**
3746 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3747 * @tx_ring: ring to be cleaned
3748 **/
b6ec895e 3749static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3750{
3751 struct ixgbe_tx_buffer *tx_buffer_info;
3752 unsigned long size;
b6ec895e 3753 u16 i;
9a799d71 3754
84418e3b
AD		 3755 /* ring already cleared, nothing to do */
3756 if (!tx_ring->tx_buffer_info)
3757 return;
9a799d71 3758
84418e3b 3759 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3760 for (i = 0; i < tx_ring->count; i++) {
3761 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3762 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3763 }
3764
3765 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3766 memset(tx_ring->tx_buffer_info, 0, size);
3767
3768 /* Zero out the descriptor ring */
3769 memset(tx_ring->desc, 0, tx_ring->size);
3770
3771 tx_ring->next_to_use = 0;
3772 tx_ring->next_to_clean = 0;
9a799d71
AK		 3773}
3774
3775/**
021230d4 3776 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3777 * @adapter: board private structure
3778 **/
021230d4 3779static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3780{
3781 int i;
3782
021230d4 3783 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3784 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3785}
3786
3787/**
021230d4 3788 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3789 * @adapter: board private structure
3790 **/
021230d4 3791static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3792{
3793 int i;
3794
021230d4 3795 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3796 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3797}
3798
e4911d57
AD		 3799static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3800{
3801 struct hlist_node *node, *node2;
3802 struct ixgbe_fdir_filter *filter;
3803
3804 spin_lock(&adapter->fdir_perfect_lock);
3805
3806 hlist_for_each_entry_safe(filter, node, node2,
3807 &adapter->fdir_filter_list, fdir_node) {
3808 hlist_del(&filter->fdir_node);
3809 kfree(filter);
3810 }
3811 adapter->fdir_filter_count = 0;
3812
3813 spin_unlock(&adapter->fdir_perfect_lock);
3814}
3815
9a799d71
AK		 3816void ixgbe_down(struct ixgbe_adapter *adapter)
3817{
3818 struct net_device *netdev = adapter->netdev;
7f821875 3819 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3820 u32 rxctrl;
bf29ee6c 3821 int i;
9a799d71
AK		 3822
3823 /* signal that we are down to the interrupt handler */
3824 set_bit(__IXGBE_DOWN, &adapter->state);
3825
3826 /* disable receives */
7f821875
JB		 3827 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3828 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3829
2d39d576
YZ		 3830 /* disable all enabled rx queues */
3831 for (i = 0; i < adapter->num_rx_queues; i++)
3832 /* this call also flushes the previous write */
3833 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3834
032b4325 3835 usleep_range(10000, 20000);
9a799d71 3836
7f821875
JB		 3837 netif_tx_stop_all_queues(netdev);
3838
7086400d 3839 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 3840 netif_carrier_off(netdev);
3841 netif_tx_disable(netdev);
3842
3843 ixgbe_irq_disable(adapter);
3844
3845 ixgbe_napi_disable_all(adapter);
3846
d034acf1
AD		 3847 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3848 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 3849 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3850
3851 del_timer_sync(&adapter->service_timer);
3852
34cecbbf 3853 if (adapter->num_vfs) {
8e34d1aa
AD		 3854 /* Clear EITR Select mapping */
3855 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 3856
3857 /* Mark all the VFs as inactive */
3858 for (i = 0 ; i < adapter->num_vfs; i++)
3859 adapter->vfinfo[i].clear_to_send = 0;
34cecbbf 3860
34cecbbf
AD		 3861 /* ping all the active vfs to let them know we are going down */
3862 ixgbe_ping_all_vfs(adapter);
3863
3864 /* Disable all VFTE/VFRE TX/RX */
3865 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 3866 }
3867
7f821875
JB		 3868 /* disable transmits in the hardware now that interrupts are off */
3869 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 3870 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 3871 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 3872 }
34cecbbf
AD		 3873
3874 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 3875 switch (hw->mac.type) {
3876 case ixgbe_mac_82599EB:
b93a2226 3877 case ixgbe_mac_X540:
88512539 3878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3879 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3880 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 3881 break;
3882 default:
3883 break;
3884 }
7f821875 3885
6f4a0e45
PL		 3886 if (!pci_channel_offline(adapter->pdev))
3887 ixgbe_reset(adapter);
c6ecf39a
DS		 3888
3889 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3890 if (hw->mac.ops.disable_tx_laser &&
3891 ((hw->phy.multispeed_fiber) ||
9f911707 3892 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 3893 (hw->mac.type == ixgbe_mac_82599EB))))
3894 hw->mac.ops.disable_tx_laser(hw);
3895
9a799d71
AK		 3896 ixgbe_clean_all_tx_rings(adapter);
3897 ixgbe_clean_all_rx_rings(adapter);
3898
5dd2d332 3899#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3900 /* since we reset the hardware DCA settings were cleared */
e35ec126 3901 ixgbe_setup_dca(adapter);
96b0e0f6 3902#endif
9a799d71
AK		 3903}
3904
9a799d71 3905/**
021230d4
AV		 3906 * ixgbe_poll - NAPI Rx polling callback
3907 * @napi: structure for representing this polling device
3908 * @budget: how many packets driver is allowed to clean
3909 *
3910 * This function is used for legacy and MSI, NAPI mode
9a799d71 3911 **/
021230d4 3912static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3913{
9a1a69ad 3914 struct ixgbe_q_vector *q_vector =
e8e9f696 3915 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3916 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 3917 struct ixgbe_ring *ring;
3918 int per_ring_budget;
3919 bool clean_complete = true;
9a799d71 3920
5dd2d332 3921#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 3922 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3923 ixgbe_update_dca(q_vector);
bd0362dd
JC		 3924#endif
3925
4ff7fb12
AD		 3926 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3927 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 3928
4ff7fb12
AD		 3929 /* attempt to distribute budget to each queue fairly, but don't allow
3930 * the budget to go below 1 because we'll exit polling */
3931 if (q_vector->rx.count > 1)
3932 per_ring_budget = max(budget/q_vector->rx.count, 1);
3933 else
3934 per_ring_budget = budget;
d2c7ddd6 3935
4ff7fb12
AD		 3936 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
3937 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
3938 per_ring_budget);
3939
3940 /* If all work not completed, return budget and keep polling */
3941 if (!clean_complete)
3942 return budget;
3943
3944 /* all work done, exit the polling mode */
3945 napi_complete(napi);
3946 if (adapter->rx_itr_setting & 1)
3947 ixgbe_set_itr(q_vector);
3948 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3949 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
3950
3951 return 0;
9a799d71
AK		 3952}
3953
3954/**
3955 * ixgbe_tx_timeout - Respond to a Tx Hang
3956 * @netdev: network interface device structure
3957 **/
3958static void ixgbe_tx_timeout(struct net_device *netdev)
3959{
3960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3961
3962 /* Do the reset outside of interrupt context */
c83c6cbd 3963 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 3964}
3965
4df10466
JB		 3966/**
3967 * ixgbe_set_rss_queues: Allocate queues for RSS
3968 * @adapter: board private structure to initialize
3969 *
3970 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3971 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3972 *
3973 **/
bc97114d
PWJ		 3974static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3975{
3976 bool ret = false;
0cefafad 3977 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3978
3979 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3980 f->mask = 0xF;
3981 adapter->num_rx_queues = f->indices;
3982 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3983 ret = true;
3984 } else {
bc97114d 3985 ret = false;
b9804972
JB		 3986 }
3987
bc97114d
PWJ		 3988 return ret;
3989}
3990
c4cf55e5
PWJ		 3991/**
3992 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3993 * @adapter: board private structure to initialize
3994 *
3995 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3996 * to the original CPU that initiated the Tx session. This runs in addition
3997 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3998 * Rx load across CPUs using RSS.
3999 *
4000 **/
e8e9f696 4001static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4002{
4003 bool ret = false;
4004 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4005
4006 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4007 f_fdir->mask = 0;
4008
4009 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4010 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4011 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4012 adapter->num_tx_queues = f_fdir->indices;
4013 adapter->num_rx_queues = f_fdir->indices;
4014 ret = true;
4015 } else {
4016 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4017 }
4018 return ret;
4019}
4020
0331a832
YZ		 4021#ifdef IXGBE_FCOE
4022/**
4023 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4024 * @adapter: board private structure to initialize
4025 *
4026 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4027 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4028 * rx queues out of the max number of rx queues, instead, it is used as the
4029 * index of the first rx queue used by FCoE.
4030 *
4031 **/
4032static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4033{
0331a832
YZ		 4034 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4035
e5b64635
JF		 4036 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4037 return false;
4038
e901acd6 4039 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4040
e901acd6
JF		 4041 adapter->num_rx_queues = 1;
4042 adapter->num_tx_queues = 1;
e5b64635 4043
e901acd6
JF		 4044 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4045 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4046 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4047 ixgbe_set_fdir_queues(adapter);
4048 else
4049 ixgbe_set_rss_queues(adapter);
e5b64635 4050 }
03ecf91a 4051
e901acd6
JF		 4052 /* adding FCoE rx rings to the end */
4053 f->mask = adapter->num_rx_queues;
4054 adapter->num_rx_queues += f->indices;
4055 adapter->num_tx_queues += f->indices;
0331a832 4056
e5b64635
JF		 4057 return true;
4058}
4059#endif /* IXGBE_FCOE */
4060
e901acd6
JF		 4061/* Artificial max queue cap per traffic class in DCB mode */
4062#define DCB_QUEUE_CAP 8
4063
e5b64635
JF		 4064#ifdef CONFIG_IXGBE_DCB
4065static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4066{
e901acd6
JF		 4067 int per_tc_q, q, i, offset = 0;
4068 struct net_device *dev = adapter->netdev;
4069 int tcs = netdev_get_num_tc(dev);
e5b64635 4070
e901acd6
JF		 4071 if (!tcs)
4072 return false;
e5b64635 4073
e901acd6
JF		 4074 /* Map queue offset and counts onto allocated tx queues */
4075 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4076 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4077
8b1c0b24 4078 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4079 netdev_set_prio_tc_map(dev, i, i);
4080 netdev_set_tc_queue(dev, i, q, offset);
4081 offset += q;
0331a832
YZ		 4082 }
4083
e901acd6
JF		 4084 adapter->num_tx_queues = q * tcs;
4085 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4086
4087#ifdef IXGBE_FCOE
e901acd6
JF		 4088 /* FCoE enabled queues require special configuration indexed
4089 * by feature specific indices and mask. Here we map FCoE
4090 * indices onto the DCB queue pairs allowing FCoE to own
4091 * configuration later.
e5b64635 4092 */
e901acd6
JF		 4093 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4094 int tc;
4095 struct ixgbe_ring_feature *f =
4096 &adapter->ring_feature[RING_F_FCOE];
4097
4098 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4099 f->indices = dev->tc_to_txq[tc].count;
4100 f->mask = dev->tc_to_txq[tc].offset;
4101 }
e5b64635
JF		 4102#endif
4103
e901acd6 4104 return true;
0331a832 4105}
e5b64635 4106#endif
0331a832 4107
1cdd1ec8
GR		 4108/**
4109 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4110 * @adapter: board private structure to initialize
4111 *
4112 * IOV doesn't actually use anything, so just NAK the
4113 * request for now and let the other queue routines
4114 * figure out what to do.
4115 */
4116static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4117{
4118 return false;
4119}
4120
4df10466 4121/*
25985edc 4122 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4123 * @adapter: board private structure to initialize
4124 *
4125 * This is the top level queue allocation routine. The order here is very
4126 * important, starting with the "most" number of features turned on at once,
4127 * and ending with the smallest set of features. This way large combinations
4128 * can be allocated if they're turned on, and smaller combinations are the
4129 * fallthrough conditions.
4130 *
4131 **/
847f53ff 4132static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4133{
1cdd1ec8
GR		 4134 /* Start with base case */
4135 adapter->num_rx_queues = 1;
4136 adapter->num_tx_queues = 1;
4137 adapter->num_rx_pools = adapter->num_rx_queues;
4138 adapter->num_rx_queues_per_pool = 1;
4139
4140 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4141 goto done;
1cdd1ec8 4142
bc97114d
PWJ		 4143#ifdef CONFIG_IXGBE_DCB
4144 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4145 goto done;
bc97114d
PWJ		 4146
4147#endif
e5b64635
JF		 4148#ifdef IXGBE_FCOE
4149 if (ixgbe_set_fcoe_queues(adapter))
4150 goto done;
4151
4152#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4153 if (ixgbe_set_fdir_queues(adapter))
4154 goto done;
4155
bc97114d 4156 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4157 goto done;
4158
4159 /* fallback to base case */
4160 adapter->num_rx_queues = 1;
4161 adapter->num_tx_queues = 1;
4162
4163done:
847f53ff 4164 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4165 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4166 return netif_set_real_num_rx_queues(adapter->netdev,
4167 adapter->num_rx_queues);
b9804972
JB		 4168}
4169
021230d4 4170static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4171 int vectors)
021230d4
AV		 4172{
4173 int err, vector_threshold;
4174
4175 /* We'll want at least 3 (vector_threshold):
4176 * 1) TxQ[0] Cleanup
4177 * 2) RxQ[0] Cleanup
4178 * 3) Other (Link Status Change, etc.)
4179 * 4) TCP Timer (optional)
4180 */
4181 vector_threshold = MIN_MSIX_COUNT;
4182
4183 /* The more we get, the more we will assign to Tx/Rx Cleanup
4184 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4185 * Right now, we simply care about how many we'll get; we'll
4186 * set them up later while requesting irq's.
4187 */
4188 while (vectors >= vector_threshold) {
4189 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4190 vectors);
021230d4
AV		 4191 if (!err) /* Success in acquiring all requested vectors. */
4192 break;
4193 else if (err < 0)
4194 vectors = 0; /* Nasty failure, quit now */
4195 else /* err == number of vectors we should try again with */
4196 vectors = err;
4197 }
4198
4199 if (vectors < vector_threshold) {
4200 /* Can't allocate enough MSI-X interrupts? Oh well.
4201 * This just means we'll go with either a single MSI
4202 * vector or fall back to legacy interrupts.
4203 */
849c4542
ET		 4204 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4205 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4206 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4207 kfree(adapter->msix_entries);
4208 adapter->msix_entries = NULL;
021230d4
AV		 4209 } else {
4210 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4211 /*
4212 * Adjust for only the vectors we'll use, which is minimum
4213 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4214 * vectors we were allocated.
4215 */
4216 adapter->num_msix_vectors = min(vectors,
e8e9f696 4217 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4218 }
4219}
4220
021230d4 4221/**
bc97114d 4222 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4223 * @adapter: board private structure to initialize
4224 *
bc97114d
PWJ		 4225 * Cache the descriptor ring offsets for RSS to the assigned rings.
4226 *
021230d4 4227 **/
bc97114d 4228static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4229{
bc97114d 4230 int i;
bc97114d 4231
9d6b758f
AD		 4232 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4233 return false;
bc97114d 4234
9d6b758f
AD		 4235 for (i = 0; i < adapter->num_rx_queues; i++)
4236 adapter->rx_ring[i]->reg_idx = i;
4237 for (i = 0; i < adapter->num_tx_queues; i++)
4238 adapter->tx_ring[i]->reg_idx = i;
4239
4240 return true;
bc97114d
PWJ		 4241}
4242
4243#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4244
4245/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4246static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4247 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4248{
4249 struct net_device *dev = adapter->netdev;
4250 struct ixgbe_hw *hw = &adapter->hw;
4251 u8 num_tcs = netdev_get_num_tc(dev);
4252
4253 *tx = 0;
4254 *rx = 0;
4255
4256 switch (hw->mac.type) {
4257 case ixgbe_mac_82598EB:
aba70d5e
JF		 4258 *tx = tc << 2;
4259 *rx = tc << 3;
e5b64635
JF		 4260 break;
4261 case ixgbe_mac_82599EB:
4262 case ixgbe_mac_X540:
4fa2e0e1 4263 if (num_tcs > 4) {
e5b64635
JF		 4264 if (tc < 3) {
4265 *tx = tc << 5;
4266 *rx = tc << 4;
4267 } else if (tc < 5) {
4268 *tx = ((tc + 2) << 4);
4269 *rx = tc << 4;
4270 } else if (tc < num_tcs) {
4271 *tx = ((tc + 8) << 3);
4272 *rx = tc << 4;
4273 }
4fa2e0e1 4274 } else {
e5b64635
JF		 4275 *rx = tc << 5;
4276 switch (tc) {
4277 case 0:
4278 *tx = 0;
4279 break;
4280 case 1:
4281 *tx = 64;
4282 break;
4283 case 2:
4284 *tx = 96;
4285 break;
4286 case 3:
4287 *tx = 112;
4288 break;
4289 default:
4290 break;
4291 }
4292 }
4293 break;
4294 default:
4295 break;
4296 }
4297}
4298
bc97114d
PWJ		 4299/**
4300 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4301 * @adapter: board private structure to initialize
4302 *
4303 * Cache the descriptor ring offsets for DCB to the assigned rings.
4304 *
4305 **/
4306static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4307{
e5b64635
JF		 4308 struct net_device *dev = adapter->netdev;
4309 int i, j, k;
4310 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4311
8b1c0b24 4312 if (!num_tcs)
bd508178 4313 return false;
f92ef202 4314
e5b64635
JF		 4315 for (i = 0, k = 0; i < num_tcs; i++) {
4316 unsigned int tx_s, rx_s;
4317 u16 count = dev->tc_to_txq[i].count;
4318
4319 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4320 for (j = 0; j < count; j++, k++) {
4321 adapter->tx_ring[k]->reg_idx = tx_s + j;
4322 adapter->rx_ring[k]->reg_idx = rx_s + j;
4323 adapter->tx_ring[k]->dcb_tc = i;
4324 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4325 }
021230d4 4326 }
e5b64635
JF		 4327
4328 return true;
bc97114d
PWJ		 4329}
4330#endif
4331
c4cf55e5
PWJ		 4332/**
4333 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4334 * @adapter: board private structure to initialize
4335 *
4336 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4337 *
4338 **/
e8e9f696 4339static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4340{
4341 int i;
4342 bool ret = false;
4343
03ecf91a
AD		 4344 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4345 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4346 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4347 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4348 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4349 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4350 ret = true;
4351 }
4352
4353 return ret;
4354}
4355
0331a832
YZ		 4356#ifdef IXGBE_FCOE
4357/**
4358 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4359 * @adapter: board private structure to initialize
4360 *
4361 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4362 *
4363 */
4364static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4365{
0331a832 4366 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4367 int i;
4368 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4369
4370 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4371 return false;
0331a832 4372
bf29ee6c 4373 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4374 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4375 ixgbe_cache_ring_fdir(adapter);
4376 else
4377 ixgbe_cache_ring_rss(adapter);
8faa2a78 4378
bf29ee6c
AD		 4379 fcoe_rx_i = f->mask;
4380 fcoe_tx_i = f->mask;
0331a832 4381 }
bf29ee6c
AD		 4382 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4383 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4384 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4385 }
4386 return true;
0331a832
YZ		 4387}
4388
4389#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4390/**
4391 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4392 * @adapter: board private structure to initialize
4393 *
4394 * SR-IOV doesn't use any descriptor rings but changes the default if
4395 * no other mapping is used.
4396 *
4397 */
4398static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4399{
4a0b9ca0
PW		 4400 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4401 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4402 if (adapter->num_vfs)
4403 return true;
4404 else
4405 return false;
4406}
4407
bc97114d
PWJ		 4408/**
4409 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4410 * @adapter: board private structure to initialize
4411 *
4412 * Once we know the feature-set enabled for the device, we'll cache
4413 * the register offset the descriptor ring is assigned to.
4414 *
4415 * Note, the order the various feature calls is important. It must start with
4416 * the "most" features enabled at the same time, then trickle down to the
4417 * least amount of features turned on at once.
4418 **/
4419static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4420{
4421 /* start with default case */
4a0b9ca0
PW		 4422 adapter->rx_ring[0]->reg_idx = 0;
4423 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4424
1cdd1ec8
GR		 4425 if (ixgbe_cache_ring_sriov(adapter))
4426 return;
4427
e5b64635
JF		 4428#ifdef CONFIG_IXGBE_DCB
4429 if (ixgbe_cache_ring_dcb(adapter))
4430 return;
4431#endif
4432
0331a832
YZ		 4433#ifdef IXGBE_FCOE
4434 if (ixgbe_cache_ring_fcoe(adapter))
4435 return;
0331a832 4436#endif /* IXGBE_FCOE */
bc97114d 4437
c4cf55e5
PWJ		 4438 if (ixgbe_cache_ring_fdir(adapter))
4439 return;
4440
bc97114d
PWJ		 4441 if (ixgbe_cache_ring_rss(adapter))
4442 return;
021230d4
AV		 4443}
4444
9a799d71
AK		 4445/**
4446 * ixgbe_alloc_queues - Allocate memory for all rings
4447 * @adapter: board private structure to initialize
4448 *
4449 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4450 * number of queues at compile-time. The polling_netdev array is
4451 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4452 **/
2f90b865 4453static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4454{
e2ddeba9 4455 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4456
e2ddeba9
ED		 4457 if (nid < 0 || !node_online(nid))
4458 nid = first_online_node;
4459
4460 for (; tx < adapter->num_tx_queues; tx++) {
4461 struct ixgbe_ring *ring;
4462
4463 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4464 if (!ring)
e2ddeba9 4465 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4466 if (!ring)
e2ddeba9 4467 goto err_allocation;
4a0b9ca0 4468 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4469 ring->queue_index = tx;
4470 ring->numa_node = nid;
b6ec895e 4471 ring->dev = &adapter->pdev->dev;
fc77dc3c 4472 ring->netdev = adapter->netdev;
4a0b9ca0 4473
e2ddeba9 4474 adapter->tx_ring[tx] = ring;
021230d4 4475 }
b9804972 4476
e2ddeba9
ED		 4477 for (; rx < adapter->num_rx_queues; rx++) {
4478 struct ixgbe_ring *ring;
4a0b9ca0 4479
e2ddeba9 4480 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4481 if (!ring)
e2ddeba9 4482 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4483 if (!ring)
e2ddeba9
ED		 4484 goto err_allocation;
4485 ring->count = adapter->rx_ring_count;
4486 ring->queue_index = rx;
4487 ring->numa_node = nid;
b6ec895e 4488 ring->dev = &adapter->pdev->dev;
fc77dc3c 4489 ring->netdev = adapter->netdev;
4a0b9ca0 4490
e2ddeba9 4491 adapter->rx_ring[rx] = ring;
021230d4
AV		 4492 }
4493
4494 ixgbe_cache_ring_register(adapter);
4495
4496 return 0;
4497
e2ddeba9
ED		 4498err_allocation:
4499 while (tx)
4500 kfree(adapter->tx_ring[--tx]);
4501
4502 while (rx)
4503 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4504 return -ENOMEM;
4505}
4506
4507/**
4508 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4509 * @adapter: board private structure to initialize
4510 *
4511 * Attempt to configure the interrupts using the best available
4512 * capabilities of the hardware and the kernel.
4513 **/
feea6a57 4514static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4515{
8be0e467 4516 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4517 int err = 0;
4518 int vector, v_budget;
4519
4520 /*
4521 * It's easy to be greedy for MSI-X vectors, but it really
4522 * doesn't do us much good if we have a lot more vectors
4523 * than CPU's. So let's be conservative and only ask for
342bde1b 4524 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4525 */
4526 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4527 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4528
4529 /*
4530 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4531 * hw.mac->max_msix_vectors vectors. With features
4532 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4533 * descriptor queues supported by our device. Thus, we cap it off in
4534 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4535 */
8be0e467 4536 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4537
4538 /* A failure in MSI-X entry allocation isn't fatal, but it does
4539 * mean we disable MSI-X capabilities of the adapter. */
4540 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4541 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4542 if (adapter->msix_entries) {
4543 for (vector = 0; vector < v_budget; vector++)
4544 adapter->msix_entries[vector].entry = vector;
021230d4 4545
7a921c93 4546 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4547
7a921c93
AD		 4548 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4549 goto out;
4550 }
26d27844 4551
7a921c93
AD		 4552 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4553 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4554 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4555 e_err(probe,
03ecf91a 4556 "ATR is not supported while multiple "
45b9f509
AD		 4557 "queues are disabled. Disabling Flow Director\n");
4558 }
c4cf55e5 4559 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4560 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4561 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4562 ixgbe_disable_sriov(adapter);
4563
847f53ff
BH		 4564 err = ixgbe_set_num_queues(adapter);
4565 if (err)
4566 return err;
021230d4 4567
021230d4
AV		 4568 err = pci_enable_msi(adapter->pdev);
4569 if (!err) {
4570 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4571 } else {
849c4542
ET		 4572 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4573 "Unable to allocate MSI interrupt, "
4574 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4575 /* reset err */
4576 err = 0;
4577 }
4578
4579out:
021230d4
AV		 4580 return err;
4581}
4582
7a921c93
AD		 4583/**
4584 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4585 * @adapter: board private structure to initialize
4586 *
4587 * We allocate one q_vector per queue interrupt. If allocation fails we
4588 * return -ENOMEM.
4589 **/
4590static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4591{
4ff7fb12 4592 int v_idx, num_q_vectors;
7a921c93 4593 struct ixgbe_q_vector *q_vector;
7a921c93 4594
4ff7fb12 4595 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4596 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4597 else
7a921c93 4598 num_q_vectors = 1;
7a921c93 4599
4ff7fb12 4600 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4601 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4602 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4603 if (!q_vector)
4604 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4605 GFP_KERNEL);
7a921c93
AD		 4606 if (!q_vector)
4607 goto err_out;
4ff7fb12 4608
7a921c93 4609 q_vector->adapter = adapter;
4ff7fb12
AD		 4610 q_vector->v_idx = v_idx;
4611
207867f5
AD		 4612 /* Allocate the affinity_hint cpumask, configure the mask */
4613 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4614 goto err_out;
4615 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4616
08c8833b 4617 if (q_vector->tx.count && !q_vector->rx.count)
f7554a2b
NS		 4618 q_vector->eitr = adapter->tx_eitr_param;
4619 else
4620 q_vector->eitr = adapter->rx_eitr_param;
4ff7fb12
AD		 4621
4622 netif_napi_add(adapter->netdev, &q_vector->napi,
4623 ixgbe_poll, 64);
4624 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4625 }
4626
4627 return 0;
4628
4629err_out:
4ff7fb12
AD		 4630 while (v_idx) {
4631 v_idx--;
4632 q_vector = adapter->q_vector[v_idx];
7a921c93 4633 netif_napi_del(&q_vector->napi);
207867f5 4634 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4635 kfree(q_vector);
4ff7fb12 4636 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4637 }
4638 return -ENOMEM;
4639}
4640
4641/**
4642 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4643 * @adapter: board private structure to initialize
4644 *
4645 * This function frees the memory allocated to the q_vectors. In addition if
4646 * NAPI is enabled it will delete any references to the NAPI struct prior
4647 * to freeing the q_vector.
4648 **/
4649static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4650{
207867f5 4651 int v_idx, num_q_vectors;
7a921c93 4652
91281fd3 4653 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4654 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4655 else
7a921c93 4656 num_q_vectors = 1;
7a921c93 4657
207867f5
AD		 4658 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4659 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4660 adapter->q_vector[v_idx] = NULL;
91281fd3 4661 netif_napi_del(&q_vector->napi);
207867f5 4662 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 4663 kfree(q_vector);
4664 }
4665}
4666
7b25cdba 4667static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4668{
4669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4670 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4671 pci_disable_msix(adapter->pdev);
4672 kfree(adapter->msix_entries);
4673 adapter->msix_entries = NULL;
4674 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4675 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4676 pci_disable_msi(adapter->pdev);
4677 }
021230d4
AV		 4678}
4679
4680/**
4681 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4682 * @adapter: board private structure to initialize
4683 *
4684 * We determine which interrupt scheme to use based on...
4685 * - Kernel support (MSI, MSI-X)
4686 * - which can be user-defined (via MODULE_PARAM)
4687 * - Hardware queue count (num_*_queues)
4688 * - defined by miscellaneous hardware support/features (RSS, etc.)
4689 **/
2f90b865 4690int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4691{
4692 int err;
4693
4694 /* Number of supported queues */
847f53ff
BH		 4695 err = ixgbe_set_num_queues(adapter);
4696 if (err)
4697 return err;
021230d4 4698
021230d4
AV		 4699 err = ixgbe_set_interrupt_capability(adapter);
4700 if (err) {
849c4542 4701 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4702 goto err_set_interrupt;
9a799d71
AK		 4703 }
4704
7a921c93
AD		 4705 err = ixgbe_alloc_q_vectors(adapter);
4706 if (err) {
849c4542 4707 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4708 goto err_alloc_q_vectors;
4709 }
4710
4711 err = ixgbe_alloc_queues(adapter);
4712 if (err) {
849c4542 4713 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4714 goto err_alloc_queues;
4715 }
4716
849c4542 4717 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4718 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4719 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4720
4721 set_bit(__IXGBE_DOWN, &adapter->state);
4722
9a799d71 4723 return 0;
021230d4 4724
7a921c93
AD		 4725err_alloc_queues:
4726 ixgbe_free_q_vectors(adapter);
4727err_alloc_q_vectors:
4728 ixgbe_reset_interrupt_capability(adapter);
021230d4 4729err_set_interrupt:
7a921c93
AD		 4730 return err;
4731}
4732
4733/**
4734 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4735 * @adapter: board private structure to clear interrupt scheme on
4736 *
4737 * We go through and clear interrupt specific resources and reset the structure
4738 * to pre-load conditions
4739 **/
4740void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4741{
4a0b9ca0
PW		 4742 int i;
4743
4744 for (i = 0; i < adapter->num_tx_queues; i++) {
4745 kfree(adapter->tx_ring[i]);
4746 adapter->tx_ring[i] = NULL;
4747 }
4748 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4749 struct ixgbe_ring *ring = adapter->rx_ring[i];
4750
4751 /* ixgbe_get_stats64() might access this ring, we must wait
4752 * a grace period before freeing it.
4753 */
bcec8b65 4754 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4755 adapter->rx_ring[i] = NULL;
4756 }
7a921c93 4757
b8eb3a10
DS		 4758 adapter->num_tx_queues = 0;
4759 adapter->num_rx_queues = 0;
4760
7a921c93
AD		 4761 ixgbe_free_q_vectors(adapter);
4762 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4763}
4764
4765/**
4766 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4767 * @adapter: board private structure to initialize
4768 *
4769 * ixgbe_sw_init initializes the Adapter private data structure.
4770 * Fields are initialized based on PCI device information and
4771 * OS network device settings (MTU size).
4772 **/
4773static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4774{
4775 struct ixgbe_hw *hw = &adapter->hw;
4776 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4777 struct net_device *dev = adapter->netdev;
021230d4 4778 unsigned int rss;
7a6b6f51 4779#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4780 int j;
4781 struct tc_configuration *tc;
4782#endif
16b61beb 4783 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4784
c44ade9e
JB		 4785 /* PCI config space info */
4786
4787 hw->vendor_id = pdev->vendor;
4788 hw->device_id = pdev->device;
4789 hw->revision_id = pdev->revision;
4790 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4791 hw->subsystem_device_id = pdev->subsystem_device;
4792
021230d4
AV		 4793 /* Set capability flags */
4794 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4795 adapter->ring_feature[RING_F_RSS].indices = rss;
4796 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4797 switch (hw->mac.type) {
4798 case ixgbe_mac_82598EB:
bf069c97
DS		 4799 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4800 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4801 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 4802 break;
4803 case ixgbe_mac_82599EB:
b93a2226 4804 case ixgbe_mac_X540:
e8e26350 4805 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4806 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4807 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4808 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4809 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4810 /* Flow Director hash filters enabled */
4811 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4812 adapter->atr_sample_rate = 20;
c4cf55e5 4813 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4814 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4815 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4816#ifdef IXGBE_FCOE
0d551589
YZ		 4817 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4818 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4819 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4820#ifdef CONFIG_IXGBE_DCB
6ee16520 4821 /* Default traffic class to use for FCoE */
56075a98 4822 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4823#endif
eacd73f7 4824#endif /* IXGBE_FCOE */
bd508178
AD		 4825 break;
4826 default:
4827 break;
f8212f97 4828 }
2f90b865 4829
1fc5f038
AD		 4830 /* n-tuple support exists, always init our spinlock */
4831 spin_lock_init(&adapter->fdir_perfect_lock);
4832
7a6b6f51 4833#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4834 /* Configure DCB traffic classes */
4835 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4836 tc = &adapter->dcb_cfg.tc_config[j];
4837 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4838 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4839 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4840 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4841 tc->dcb_pfc = pfc_disabled;
4842 }
4843 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4844 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4845 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4846 adapter->dcb_set_bitmap = 0x00;
3032309b 4847 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 4848 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 4849 MAX_TRAFFIC_CLASS);
2f90b865
AD		 4850
4851#endif
9a799d71
AK		 4852
4853 /* default flow control settings */
cd7664f6 4854 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4855 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4856#ifdef CONFIG_DCB
4857 adapter->last_lfc_mode = hw->fc.current_mode;
4858#endif
16b61beb
JF		 4859 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4860 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 4861 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4862 hw->fc.send_xon = true;
71fd570b 4863 hw->fc.disable_fc_autoneg = false;
9a799d71 4864
30efa5a3 4865 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4866 adapter->rx_itr_setting = 1;
4867 adapter->rx_eitr_param = 20000;
4868 adapter->tx_itr_setting = 1;
4869 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4870
4871 /* set defaults for eitr in MegaBytes */
4872 adapter->eitr_low = 10;
4873 adapter->eitr_high = 20;
4874
4875 /* set default ring sizes */
4876 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4877 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4878
bd198058 4879 /* set default work limits */
59224555 4880 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4881
9a799d71 4882 /* initialize eeprom parameters */
c44ade9e 4883 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4884 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4885 return -EIO;
4886 }
4887
021230d4 4888 /* enable rx csum by default */
9a799d71
AK		 4889 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4890
1a6c14a2
JB		 4891 /* get assigned NUMA node */
4892 adapter->node = dev_to_node(&pdev->dev);
4893
9a799d71
AK		 4894 set_bit(__IXGBE_DOWN, &adapter->state);
4895
4896 return 0;
4897}
4898
4899/**
4900 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4901 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4902 *
4903 * Return 0 on success, negative on failure
4904 **/
b6ec895e 4905int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4906{
b6ec895e 4907 struct device *dev = tx_ring->dev;
9a799d71
AK		 4908 int size;
4909
3a581073 4910 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 4911 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 4912 if (!tx_ring->tx_buffer_info)
89bf67f1 4913 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4914 if (!tx_ring->tx_buffer_info)
4915 goto err;
9a799d71
AK		 4916
4917 /* round up to nearest 4K */
12207e49 4918 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4919 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4920
b6ec895e 4921 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 4922 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4923 if (!tx_ring->desc)
4924 goto err;
9a799d71 4925
3a581073
JB		 4926 tx_ring->next_to_use = 0;
4927 tx_ring->next_to_clean = 0;
9a799d71 4928 return 0;
e01c31a5
JB		 4929
4930err:
4931 vfree(tx_ring->tx_buffer_info);
4932 tx_ring->tx_buffer_info = NULL;
b6ec895e 4933 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4934 return -ENOMEM;
9a799d71
AK		 4935}
4936
69888674
AD		 4937/**
4938 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4939 * @adapter: board private structure
4940 *
4941 * If this function returns with an error, then it's possible one or
4942 * more of the rings is populated (while the rest are not). It is the
4943 * callers duty to clean those orphaned rings.
4944 *
4945 * Return 0 on success, negative on failure
4946 **/
4947static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4948{
4949 int i, err = 0;
4950
4951 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4952 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4953 if (!err)
4954 continue;
396e799c 4955 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4956 break;
4957 }
4958
4959 return err;
4960}
4961
9a799d71
AK		 4962/**
4963 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4964 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4965 *
4966 * Returns 0 on success, negative on failure
4967 **/
b6ec895e 4968int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4969{
b6ec895e 4970 struct device *dev = rx_ring->dev;
021230d4 4971 int size;
9a799d71 4972
3a581073 4973 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 4974 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 4975 if (!rx_ring->rx_buffer_info)
89bf67f1 4976 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4977 if (!rx_ring->rx_buffer_info)
4978 goto err;
9a799d71 4979
9a799d71 4980 /* Round up to nearest 4K */
3a581073
JB		 4981 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4982 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4983
b6ec895e 4984 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 4985 &rx_ring->dma, GFP_KERNEL);
9a799d71 4986
b6ec895e
AD		 4987 if (!rx_ring->desc)
4988 goto err;
9a799d71 4989
3a581073
JB		 4990 rx_ring->next_to_clean = 0;
4991 rx_ring->next_to_use = 0;
9a799d71
AK		 4992
4993 return 0;
b6ec895e
AD		 4994err:
4995 vfree(rx_ring->rx_buffer_info);
4996 rx_ring->rx_buffer_info = NULL;
4997 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4998 return -ENOMEM;
9a799d71
AK		 4999}
5000
69888674
AD		 5001/**
5002 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5003 * @adapter: board private structure
5004 *
5005 * If this function returns with an error, then it's possible one or
5006 * more of the rings is populated (while the rest are not). It is the
5007 * callers duty to clean those orphaned rings.
5008 *
5009 * Return 0 on success, negative on failure
5010 **/
69888674
AD		 5011static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5012{
5013 int i, err = 0;
5014
5015 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5016 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5017 if (!err)
5018 continue;
396e799c 5019 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5020 break;
5021 }
5022
5023 return err;
5024}
5025
9a799d71
AK		 5026/**
5027 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5028 * @tx_ring: Tx descriptor ring for a specific queue
5029 *
5030 * Free all transmit software resources
5031 **/
b6ec895e 5032void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5033{
b6ec895e 5034 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5035
5036 vfree(tx_ring->tx_buffer_info);
5037 tx_ring->tx_buffer_info = NULL;
5038
b6ec895e
AD		 5039 /* if not set, then don't free */
5040 if (!tx_ring->desc)
5041 return;
5042
5043 dma_free_coherent(tx_ring->dev, tx_ring->size,
5044 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5045
5046 tx_ring->desc = NULL;
5047}
5048
5049/**
5050 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5051 * @adapter: board private structure
5052 *
5053 * Free all transmit software resources
5054 **/
5055static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5056{
5057 int i;
5058
5059 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5060 if (adapter->tx_ring[i]->desc)
b6ec895e 5061 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5062}
5063
5064/**
b4617240 5065 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5066 * @rx_ring: ring to clean the resources from
5067 *
5068 * Free all receive software resources
5069 **/
b6ec895e 5070void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5071{
b6ec895e 5072 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5073
5074 vfree(rx_ring->rx_buffer_info);
5075 rx_ring->rx_buffer_info = NULL;
5076
b6ec895e
AD		 5077 /* if not set, then don't free */
5078 if (!rx_ring->desc)
5079 return;
5080
5081 dma_free_coherent(rx_ring->dev, rx_ring->size,
5082 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5083
5084 rx_ring->desc = NULL;
5085}
5086
5087/**
5088 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5089 * @adapter: board private structure
5090 *
5091 * Free all receive software resources
5092 **/
5093static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5094{
5095 int i;
5096
5097 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5098 if (adapter->rx_ring[i]->desc)
b6ec895e 5099 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5100}
5101
9a799d71
AK		 5102/**
5103 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5104 * @netdev: network interface device structure
5105 * @new_mtu: new value for maximum frame size
5106 *
5107 * Returns 0 on success, negative on failure
5108 **/
5109static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5110{
5111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5112 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5113 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5114
42c783c5 5115 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5116 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5117 hw->mac.type != ixgbe_mac_X540) {
5118 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5119 return -EINVAL;
5120 } else {
5121 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5122 return -EINVAL;
5123 }
9a799d71 5124
396e799c 5125 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5126 /* must set new MTU before calling down or up */
9a799d71
AK		 5127 netdev->mtu = new_mtu;
5128
16b61beb
JF		 5129 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5130 hw->fc.low_water = FC_LOW_WATER(max_frame);
5131
d4f80882
AV		 5132 if (netif_running(netdev))
5133 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5134
5135 return 0;
5136}
5137
5138/**
5139 * ixgbe_open - Called when a network interface is made active
5140 * @netdev: network interface device structure
5141 *
5142 * Returns 0 on success, negative value on failure
5143 *
5144 * The open entry point is called when a network interface is made
5145 * active by the system (IFF_UP). At this point all resources needed
5146 * for transmit and receive operations are allocated, the interrupt
5147 * handler is registered with the OS, the watchdog timer is started,
5148 * and the stack is notified that the interface is ready.
5149 **/
5150static int ixgbe_open(struct net_device *netdev)
5151{
5152 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5153 int err;
4bebfaa5
AK		 5154
5155 /* disallow open during test */
5156 if (test_bit(__IXGBE_TESTING, &adapter->state))
5157 return -EBUSY;
9a799d71 5158
54386467
JB		 5159 netif_carrier_off(netdev);
5160
9a799d71
AK		 5161 /* allocate transmit descriptors */
5162 err = ixgbe_setup_all_tx_resources(adapter);
5163 if (err)
5164 goto err_setup_tx;
5165
9a799d71
AK		 5166 /* allocate receive descriptors */
5167 err = ixgbe_setup_all_rx_resources(adapter);
5168 if (err)
5169 goto err_setup_rx;
5170
5171 ixgbe_configure(adapter);
5172
021230d4 5173 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5174 if (err)
5175 goto err_req_irq;
5176
c7ccde0f 5177 ixgbe_up_complete(adapter);
9a799d71
AK		 5178
5179 return 0;
5180
9a799d71 5181err_req_irq:
9a799d71 5182err_setup_rx:
a20a1199 5183 ixgbe_free_all_rx_resources(adapter);
9a799d71 5184err_setup_tx:
a20a1199 5185 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5186 ixgbe_reset(adapter);
5187
5188 return err;
5189}
5190
5191/**
5192 * ixgbe_close - Disables a network interface
5193 * @netdev: network interface device structure
5194 *
5195 * Returns 0, this is not allowed to fail
5196 *
5197 * The close entry point is called when an interface is de-activated
5198 * by the OS. The hardware is still under the drivers control, but
5199 * needs to be disabled. A global MAC reset is issued to stop the
5200 * hardware, and all transmit and receive resources are freed.
5201 **/
5202static int ixgbe_close(struct net_device *netdev)
5203{
5204 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5205
5206 ixgbe_down(adapter);
5207 ixgbe_free_irq(adapter);
5208
e4911d57
AD		 5209 ixgbe_fdir_filter_exit(adapter);
5210
9a799d71
AK		 5211 ixgbe_free_all_tx_resources(adapter);
5212 ixgbe_free_all_rx_resources(adapter);
5213
5eba3699 5214 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5215
5216 return 0;
5217}
5218
b3c8b4ba
AD		 5219#ifdef CONFIG_PM
5220static int ixgbe_resume(struct pci_dev *pdev)
5221{
c60fbb00
AD		 5222 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5223 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5224 u32 err;
5225
5226 pci_set_power_state(pdev, PCI_D0);
5227 pci_restore_state(pdev);
656ab817
DS		 5228 /*
5229 * pci_restore_state clears dev->state_saved so call
5230 * pci_save_state to restore it.
5231 */
5232 pci_save_state(pdev);
9ce77666 5233
5234 err = pci_enable_device_mem(pdev);
b3c8b4ba 5235 if (err) {
849c4542 5236 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5237 return err;
5238 }
5239 pci_set_master(pdev);
5240
dd4d8ca6 5241 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5242
5243 err = ixgbe_init_interrupt_scheme(adapter);
5244 if (err) {
849c4542 5245 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5246 return err;
5247 }
5248
b3c8b4ba
AD		 5249 ixgbe_reset(adapter);
5250
495dce12
WJP		 5251 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5252
b3c8b4ba 5253 if (netif_running(netdev)) {
c60fbb00 5254 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5255 if (err)
5256 return err;
5257 }
5258
5259 netif_device_attach(netdev);
5260
5261 return 0;
5262}
b3c8b4ba 5263#endif /* CONFIG_PM */
9d8d05ae
RW		 5264
5265static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5266{
c60fbb00
AD		 5267 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5268 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5269 struct ixgbe_hw *hw = &adapter->hw;
5270 u32 ctrl, fctrl;
5271 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5272#ifdef CONFIG_PM
5273 int retval = 0;
5274#endif
5275
5276 netif_device_detach(netdev);
5277
5278 if (netif_running(netdev)) {
5279 ixgbe_down(adapter);
5280 ixgbe_free_irq(adapter);
5281 ixgbe_free_all_tx_resources(adapter);
5282 ixgbe_free_all_rx_resources(adapter);
5283 }
b3c8b4ba 5284
5f5ae6fc 5285 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5286#ifdef CONFIG_DCB
5287 kfree(adapter->ixgbe_ieee_pfc);
5288 kfree(adapter->ixgbe_ieee_ets);
5289#endif
5f5ae6fc 5290
b3c8b4ba
AD		 5291#ifdef CONFIG_PM
5292 retval = pci_save_state(pdev);
5293 if (retval)
5294 return retval;
4df10466 5295
b3c8b4ba 5296#endif
e8e26350
PW		 5297 if (wufc) {
5298 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5299
e8e26350
PW		 5300 /* turn on all-multi mode if wake on multicast is enabled */
5301 if (wufc & IXGBE_WUFC_MC) {
5302 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5303 fctrl |= IXGBE_FCTRL_MPE;
5304 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5305 }
5306
5307 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5308 ctrl |= IXGBE_CTRL_GIO_DIS;
5309 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5310
5311 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5312 } else {
5313 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5314 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5315 }
5316
bd508178
AD		 5317 switch (hw->mac.type) {
5318 case ixgbe_mac_82598EB:
dd4d8ca6 5319 pci_wake_from_d3(pdev, false);
bd508178
AD		 5320 break;
5321 case ixgbe_mac_82599EB:
b93a2226 5322 case ixgbe_mac_X540:
bd508178
AD		 5323 pci_wake_from_d3(pdev, !!wufc);
5324 break;
5325 default:
5326 break;
5327 }
b3c8b4ba 5328
9d8d05ae
RW		 5329 *enable_wake = !!wufc;
5330
b3c8b4ba
AD		 5331 ixgbe_release_hw_control(adapter);
5332
5333 pci_disable_device(pdev);
5334
9d8d05ae
RW		 5335 return 0;
5336}
5337
5338#ifdef CONFIG_PM
5339static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5340{
5341 int retval;
5342 bool wake;
5343
5344 retval = __ixgbe_shutdown(pdev, &wake);
5345 if (retval)
5346 return retval;
5347
5348 if (wake) {
5349 pci_prepare_to_sleep(pdev);
5350 } else {
5351 pci_wake_from_d3(pdev, false);
5352 pci_set_power_state(pdev, PCI_D3hot);
5353 }
b3c8b4ba
AD		 5354
5355 return 0;
5356}
9d8d05ae 5357#endif /* CONFIG_PM */
b3c8b4ba
AD		 5358
5359static void ixgbe_shutdown(struct pci_dev *pdev)
5360{
9d8d05ae
RW		 5361 bool wake;
5362
5363 __ixgbe_shutdown(pdev, &wake);
5364
5365 if (system_state == SYSTEM_POWER_OFF) {
5366 pci_wake_from_d3(pdev, wake);
5367 pci_set_power_state(pdev, PCI_D3hot);
5368 }
b3c8b4ba
AD		 5369}
5370
9a799d71
AK		 5371/**
5372 * ixgbe_update_stats - Update the board statistics counters.
5373 * @adapter: board private structure
5374 **/
5375void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5376{
2d86f139 5377 struct net_device *netdev = adapter->netdev;
9a799d71 5378 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5379 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5380 u64 total_mpc = 0;
5381 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5382 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5383 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5384 u64 bytes = 0, packets = 0;
9a799d71 5385
d08935c2
DS		 5386 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5387 test_bit(__IXGBE_RESETTING, &adapter->state))
5388 return;
5389
94b982b2 5390 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5391 u64 rsc_count = 0;
94b982b2 5392 u64 rsc_flush = 0;
d51019a4
PW		 5393 for (i = 0; i < 16; i++)
5394 adapter->hw_rx_no_dma_resources +=
7ca647bd 5395 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5396 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5397 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5398 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5399 }
5400 adapter->rsc_total_count = rsc_count;
5401 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5402 }
5403
5b7da515
AD		 5404 for (i = 0; i < adapter->num_rx_queues; i++) {
5405 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5406 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5407 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5408 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5409 bytes += rx_ring->stats.bytes;
5410 packets += rx_ring->stats.packets;
5411 }
5412 adapter->non_eop_descs = non_eop_descs;
5413 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5414 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5415 netdev->stats.rx_bytes = bytes;
5416 netdev->stats.rx_packets = packets;
5417
5418 bytes = 0;
5419 packets = 0;
7ca3bc58 5420 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5421 for (i = 0; i < adapter->num_tx_queues; i++) {
5422 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5423 restart_queue += tx_ring->tx_stats.restart_queue;
5424 tx_busy += tx_ring->tx_stats.tx_busy;
5425 bytes += tx_ring->stats.bytes;
5426 packets += tx_ring->stats.packets;
5427 }
eb985f09 5428 adapter->restart_queue = restart_queue;
5b7da515
AD		 5429 adapter->tx_busy = tx_busy;
5430 netdev->stats.tx_bytes = bytes;
5431 netdev->stats.tx_packets = packets;
7ca3bc58 5432
7ca647bd 5433 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5434
5435 /* 8 register reads */
6f11eef7
AV		 5436 for (i = 0; i < 8; i++) {
5437 /* for packet buffers not used, the register should read 0 */
5438 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5439 missed_rx += mpc;
7ca647bd
JP		 5440 hwstats->mpc[i] += mpc;
5441 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5442 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5443 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5444 switch (hw->mac.type) {
5445 case ixgbe_mac_82598EB:
1a70db4b
ET		 5446 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5447 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5448 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5449 hwstats->pxonrxc[i] +=
5450 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5451 break;
5452 case ixgbe_mac_82599EB:
b93a2226 5453 case ixgbe_mac_X540:
bd508178
AD		 5454 hwstats->pxonrxc[i] +=
5455 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5456 break;
5457 default:
5458 break;
e8e26350 5459 }
6f11eef7 5460 }
1a70db4b
ET		 5461
5462 /*16 register reads */
5463 for (i = 0; i < 16; i++) {
5464 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5465 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5466 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5467 (hw->mac.type == ixgbe_mac_X540)) {
5468 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5469 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5470 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5471 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5472 }
5473 }
5474
7ca647bd 5475 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5476 /* work around hardware counting issue */
7ca647bd 5477 hwstats->gprc -= missed_rx;
6f11eef7 5478
c84d324c
JF		 5479 ixgbe_update_xoff_received(adapter);
5480
6f11eef7 5481 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5482 switch (hw->mac.type) {
5483 case ixgbe_mac_82598EB:
5484 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5485 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5486 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5487 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5488 break;
b93a2226 5489 case ixgbe_mac_X540:
58f6bcf9
ET		 5490 /* OS2BMC stats are X540 only*/
5491 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5492 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5493 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5494 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5495 case ixgbe_mac_82599EB:
7ca647bd 5496 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5497 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5498 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5499 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5500 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5501 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5502 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5503 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5504 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5505#ifdef IXGBE_FCOE
7ca647bd
JP		 5506 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5507 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5508 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5509 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5510 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5511 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5512#endif /* IXGBE_FCOE */
bd508178
AD		 5513 break;
5514 default:
5515 break;
e8e26350 5516 }
9a799d71 5517 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5518 hwstats->bprc += bprc;
5519 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5520 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5521 hwstats->mprc -= bprc;
5522 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5523 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5524 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5525 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5526 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5527 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5528 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5529 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5530 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5531 hwstats->lxontxc += lxon;
6f11eef7 5532 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5533 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5534 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5535 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5536 /*
5537 * 82598 errata - tx of flow control packets is included in tx counters
5538 */
5539 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5540 hwstats->gptc -= xon_off_tot;
5541 hwstats->mptc -= xon_off_tot;
5542 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5543 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5544 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5545 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5546 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5547 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5548 hwstats->ptc64 -= xon_off_tot;
5549 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5550 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5551 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5552 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5553 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5554 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5555
5556 /* Fill out the OS statistics structure */
7ca647bd 5557 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5558
5559 /* Rx Errors */
7ca647bd 5560 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5561 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5562 netdev->stats.rx_length_errors = hwstats->rlec;
5563 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5564 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5565}
5566
5567/**
d034acf1
AD		 5568 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5569 * @adapter - pointer to the device adapter structure
9a799d71 5570 **/
d034acf1 5571static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5572{
cf8280ee 5573 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5574 int i;
cf8280ee 5575
d034acf1
AD		 5576 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5577 return;
5578
5579 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5580
d034acf1 5581 /* if interface is down do nothing */
fe49f04a 5582 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5583 return;
5584
5585 /* do nothing if we are not using signature filters */
5586 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5587 return;
5588
5589 adapter->fdir_overflow++;
5590
93c52dd0
AD		 5591 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5592 for (i = 0; i < adapter->num_tx_queues; i++)
5593 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5594 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5595 /* re-enable flow director interrupts */
5596 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5597 } else {
5598 e_err(probe, "failed to finish FDIR re-initialization, "
5599 "ignored adding FDIR ATR filters\n");
5600 }
93c52dd0
AD		 5601}
5602
5603/**
5604 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5605 * @adapter - pointer to the device adapter structure
5606 *
5607 * This function serves two purposes. First it strobes the interrupt lines
5608 * in order to make certain interrupts are occuring. Secondly it sets the
5609 * bits needed to check for TX hangs. As a result we should immediately
5610 * determine if a hang has occured.
5611 */
5612static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5613{
cf8280ee 5614 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5615 u64 eics = 0;
5616 int i;
cf8280ee 5617
93c52dd0
AD		 5618 /* If we're down or resetting, just bail */
5619 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5620 test_bit(__IXGBE_RESETTING, &adapter->state))
5621 return;
22d5a71b 5622
93c52dd0
AD		 5623 /* Force detection of hung controller */
5624 if (netif_carrier_ok(adapter->netdev)) {
5625 for (i = 0; i < adapter->num_tx_queues; i++)
5626 set_check_for_tx_hang(adapter->tx_ring[i]);
5627 }
22d5a71b 5628
fe49f04a
AD		 5629 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5630 /*
5631 * for legacy and MSI interrupts don't set any bits
5632 * that are enabled for EIAM, because this operation
5633 * would set *both* EIMS and EICS for any bit in EIAM
5634 */
5635 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5636 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5637 } else {
5638 /* get one bit for every active tx/rx interrupt vector */
5639 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5640 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5641 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5642 eics |= ((u64)1 << i);
5643 }
cf8280ee 5644 }
9a799d71 5645
93c52dd0 5646 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5647 ixgbe_irq_rearm_queues(adapter, eics);
5648
cf8280ee
JB		 5649}
5650
e8e26350 5651/**
93c52dd0
AD		 5652 * ixgbe_watchdog_update_link - update the link status
5653 * @adapter - pointer to the device adapter structure
5654 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5655 **/
93c52dd0 5656static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5657{
e8e26350 5658 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5659 u32 link_speed = adapter->link_speed;
5660 bool link_up = adapter->link_up;
c4cf55e5 5661 int i;
e8e26350 5662
93c52dd0
AD		 5663 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5664 return;
5665
5666 if (hw->mac.ops.check_link) {
5667 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5668 } else {
93c52dd0
AD		 5669 /* always assume link is up, if no check link function */
5670 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5671 link_up = true;
c4cf55e5 5672 }
93c52dd0
AD		 5673 if (link_up) {
5674 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5675 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5676 hw->mac.ops.fc_enable(hw, i);
5677 } else {
5678 hw->mac.ops.fc_enable(hw, 0);
5679 }
5680 }
5681
5682 if (link_up ||
5683 time_after(jiffies, (adapter->link_check_timeout +
5684 IXGBE_TRY_LINK_TIMEOUT))) {
5685 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5686 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5687 IXGBE_WRITE_FLUSH(hw);
5688 }
5689
5690 adapter->link_up = link_up;
5691 adapter->link_speed = link_speed;
e8e26350
PW		 5692}
5693
5694/**
93c52dd0
AD		 5695 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5696 * print link up message
5697 * @adapter - pointer to the device adapter structure
e8e26350 5698 **/
93c52dd0 5699static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5700{
93c52dd0 5701 struct net_device *netdev = adapter->netdev;
e8e26350 5702 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5703 u32 link_speed = adapter->link_speed;
5704 bool flow_rx, flow_tx;
e8e26350 5705
93c52dd0
AD		 5706 /* only continue if link was previously down */
5707 if (netif_carrier_ok(netdev))
a985b6c3 5708 return;
63d6e1d8 5709
93c52dd0 5710 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5711
93c52dd0
AD		 5712 switch (hw->mac.type) {
5713 case ixgbe_mac_82598EB: {
5714 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5715 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5716 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5717 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5718 }
5719 break;
5720 case ixgbe_mac_X540:
5721 case ixgbe_mac_82599EB: {
5722 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5723 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5724 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5725 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5726 }
5727 break;
5728 default:
5729 flow_tx = false;
5730 flow_rx = false;
5731 break;
e8e26350 5732 }
93c52dd0
AD		 5733 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5734 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5735 "10 Gbps" :
5736 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5737 "1 Gbps" :
5738 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5739 "100 Mbps" :
5740 "unknown speed"))),
5741 ((flow_rx && flow_tx) ? "RX/TX" :
5742 (flow_rx ? "RX" :
5743 (flow_tx ? "TX" : "None"))));
e8e26350 5744
93c52dd0 5745 netif_carrier_on(netdev);
93c52dd0 5746 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5747}
5748
c4cf55e5 5749/**
93c52dd0
AD		 5750 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5751 * print link down message
5752 * @adapter - pointer to the adapter structure
c4cf55e5 5753 **/
93c52dd0 5754static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5755{
cf8280ee 5756 struct net_device *netdev = adapter->netdev;
c4cf55e5 5757 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5758
93c52dd0
AD		 5759 adapter->link_up = false;
5760 adapter->link_speed = 0;
cf8280ee 5761
93c52dd0
AD		 5762 /* only continue if link was up previously */
5763 if (!netif_carrier_ok(netdev))
5764 return;
264857b8 5765
93c52dd0
AD		 5766 /* poll for SFP+ cable when link is down */
5767 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5768 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5769
93c52dd0
AD		 5770 e_info(drv, "NIC Link is Down\n");
5771 netif_carrier_off(netdev);
5772}
e8e26350 5773
93c52dd0
AD		 5774/**
5775 * ixgbe_watchdog_flush_tx - flush queues on link down
5776 * @adapter - pointer to the device adapter structure
5777 **/
5778static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5779{
c4cf55e5 5780 int i;
93c52dd0 5781 int some_tx_pending = 0;
c4cf55e5 5782
93c52dd0 5783 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5784 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5785 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5786 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5787 some_tx_pending = 1;
5788 break;
5789 }
5790 }
5791
5792 if (some_tx_pending) {
5793 /* We've lost link, so the controller stops DMA,
5794 * but we've got queued Tx work that's never going
5795 * to get done, so reset controller to flush Tx.
5796 * (Do the reset outside of interrupt context).
5797 */
c83c6cbd 5798 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5799 }
c4cf55e5 5800 }
c4cf55e5
PWJ		 5801}
5802
a985b6c3
GR		 5803static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5804{
5805 u32 ssvpc;
5806
5807 /* Do not perform spoof check for 82598 */
5808 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5809 return;
5810
5811 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5812
5813 /*
5814 * ssvpc register is cleared on read, if zero then no
5815 * spoofed packets in the last interval.
5816 */
5817 if (!ssvpc)
5818 return;
5819
5820 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5821}
5822
93c52dd0
AD		 5823/**
5824 * ixgbe_watchdog_subtask - check and bring link up
5825 * @adapter - pointer to the device adapter structure
5826 **/
5827static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5828{
5829 /* if interface is down do nothing */
5830 if (test_bit(__IXGBE_DOWN, &adapter->state))
5831 return;
5832
5833 ixgbe_watchdog_update_link(adapter);
5834
5835 if (adapter->link_up)
5836 ixgbe_watchdog_link_is_up(adapter);
5837 else
5838 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5839
a985b6c3 5840 ixgbe_spoof_check(adapter);
9a799d71 5841 ixgbe_update_stats(adapter);
93c52dd0
AD		 5842
5843 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5844}
10eec955 5845
cf8280ee 5846/**
7086400d
AD		 5847 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5848 * @adapter - the ixgbe adapter structure
cf8280ee 5849 **/
7086400d 5850static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5851{
cf8280ee 5852 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5853 s32 err;
cf8280ee 5854
7086400d
AD		 5855 /* not searching for SFP so there is nothing to do here */
5856 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5857 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5858 return;
10eec955 5859
7086400d
AD		 5860 /* someone else is in init, wait until next service event */
5861 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5862 return;
cf8280ee 5863
7086400d
AD		 5864 err = hw->phy.ops.identify_sfp(hw);
5865 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5866 goto sfp_out;
264857b8 5867
7086400d
AD		 5868 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5869 /* If no cable is present, then we need to reset
5870 * the next time we find a good cable. */
5871 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5872 }
9a799d71 5873
7086400d
AD		 5874 /* exit on error */
5875 if (err)
5876 goto sfp_out;
e8e26350 5877
7086400d
AD		 5878 /* exit if reset not needed */
5879 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5880 goto sfp_out;
9a799d71 5881
7086400d 5882 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5883
7086400d
AD		 5884 /*
5885 * A module may be identified correctly, but the EEPROM may not have
5886 * support for that module. setup_sfp() will fail in that case, so
5887 * we should not allow that module to load.
5888 */
5889 if (hw->mac.type == ixgbe_mac_82598EB)
5890 err = hw->phy.ops.reset(hw);
5891 else
5892 err = hw->mac.ops.setup_sfp(hw);
5893
5894 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5895 goto sfp_out;
5896
5897 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5898 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5899
5900sfp_out:
5901 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5902
5903 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5904 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5905 e_dev_err("failed to initialize because an unsupported "
5906 "SFP+ module type was detected.\n");
5907 e_dev_err("Reload the driver after installing a "
5908 "supported module.\n");
5909 unregister_netdev(adapter->netdev);
bc59fcda 5910 }
7086400d 5911}
bc59fcda 5912
7086400d
AD		 5913/**
5914 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5915 * @adapter - the ixgbe adapter structure
5916 **/
5917static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5918{
5919 struct ixgbe_hw *hw = &adapter->hw;
5920 u32 autoneg;
5921 bool negotiation;
5922
5923 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5924 return;
5925
5926 /* someone else is in init, wait until next service event */
5927 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5928 return;
5929
5930 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5931
5932 autoneg = hw->phy.autoneg_advertised;
5933 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5934 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5935 hw->mac.autotry_restart = false;
5936 if (hw->mac.ops.setup_link)
5937 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5938
5939 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5940 adapter->link_check_timeout = jiffies;
5941 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5942}
5943
5944/**
5945 * ixgbe_service_timer - Timer Call-back
5946 * @data: pointer to adapter cast into an unsigned long
5947 **/
5948static void ixgbe_service_timer(unsigned long data)
5949{
5950 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5951 unsigned long next_event_offset;
5952
5953 /* poll faster when waiting for link */
5954 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5955 next_event_offset = HZ / 10;
5956 else
5957 next_event_offset = HZ * 2;
5958
5959 /* Reset the timer */
5960 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5961
5962 ixgbe_service_event_schedule(adapter);
5963}
5964
c83c6cbd
AD		 5965static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5966{
5967 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5968 return;
5969
5970 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5971
5972 /* If we're already down or resetting, just bail */
5973 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5974 test_bit(__IXGBE_RESETTING, &adapter->state))
5975 return;
5976
5977 ixgbe_dump(adapter);
5978 netdev_err(adapter->netdev, "Reset adapter\n");
5979 adapter->tx_timeout_count++;
5980
5981 ixgbe_reinit_locked(adapter);
5982}
5983
7086400d
AD		 5984/**
5985 * ixgbe_service_task - manages and runs subtasks
5986 * @work: pointer to work_struct containing our data
5987 **/
5988static void ixgbe_service_task(struct work_struct *work)
5989{
5990 struct ixgbe_adapter *adapter = container_of(work,
5991 struct ixgbe_adapter,
5992 service_task);
5993
c83c6cbd 5994 ixgbe_reset_subtask(adapter);
7086400d
AD		 5995 ixgbe_sfp_detection_subtask(adapter);
5996 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5997 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5998 ixgbe_watchdog_subtask(adapter);
d034acf1 5999 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6000 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6001
6002 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6003}
6004
897ab156
AD		 6005void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6006 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6007{
6008 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6009 u16 i = tx_ring->next_to_use;
9a799d71 6010
897ab156 6011 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6012
897ab156
AD		 6013 i++;
6014 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6015
897ab156
AD		 6016 /* set bits to identify this as an advanced context descriptor */
6017 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6018
897ab156
AD		 6019 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6020 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6021 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6022 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6023}
9a799d71 6024
897ab156
AD		 6025static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6026 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6027{
6028 int err;
6029 u32 vlan_macip_lens, type_tucmd;
6030 u32 mss_l4len_idx, l4len;
9a799d71 6031
897ab156
AD		 6032 if (!skb_is_gso(skb))
6033 return 0;
9a799d71 6034
897ab156
AD		 6035 if (skb_header_cloned(skb)) {
6036 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6037 if (err)
6038 return err;
9a799d71 6039 }
9a799d71 6040
897ab156
AD		 6041 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6042 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6043
6044 if (protocol == __constant_htons(ETH_P_IP)) {
6045 struct iphdr *iph = ip_hdr(skb);
6046 iph->tot_len = 0;
6047 iph->check = 0;
6048 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6049 iph->daddr, 0,
6050 IPPROTO_TCP,
6051 0);
6052 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6053 } else if (skb_is_gso_v6(skb)) {
6054 ipv6_hdr(skb)->payload_len = 0;
6055 tcp_hdr(skb)->check =
6056 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6057 &ipv6_hdr(skb)->daddr,
6058 0, IPPROTO_TCP, 0);
6059 }
6060
6061 l4len = tcp_hdrlen(skb);
6062 *hdr_len = skb_transport_offset(skb) + l4len;
6063
6064 /* mss_l4len_id: use 1 as index for TSO */
6065 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6066 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6067 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6068
6069 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6070 vlan_macip_lens = skb_network_header_len(skb);
6071 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6072 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6073
6074 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6075 mss_l4len_idx);
6076
6077 return 1;
6078}
6079
6080static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6081 struct sk_buff *skb, u32 tx_flags,
6082 __be16 protocol)
7ca647bd 6083{
897ab156
AD		 6084 u32 vlan_macip_lens = 0;
6085 u32 mss_l4len_idx = 0;
6086 u32 type_tucmd = 0;
7ca647bd 6087
897ab156 6088 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6089 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6090 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6091 return false;
6092 } else {
6093 u8 l4_hdr = 0;
6094 switch (protocol) {
6095 case __constant_htons(ETH_P_IP):
6096 vlan_macip_lens |= skb_network_header_len(skb);
6097 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6098 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6099 break;
897ab156
AD		 6100 case __constant_htons(ETH_P_IPV6):
6101 vlan_macip_lens |= skb_network_header_len(skb);
6102 l4_hdr = ipv6_hdr(skb)->nexthdr;
6103 break;
6104 default:
6105 if (unlikely(net_ratelimit())) {
6106 dev_warn(tx_ring->dev,
6107 "partial checksum but proto=%x!\n",
6108 skb->protocol);
6109 }
7ca647bd
JP		 6110 break;
6111 }
897ab156
AD		 6112
6113 switch (l4_hdr) {
7ca647bd 6114 case IPPROTO_TCP:
897ab156
AD		 6115 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6116 mss_l4len_idx = tcp_hdrlen(skb) <<
6117 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6118 break;
6119 case IPPROTO_SCTP:
897ab156
AD		 6120 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6121 mss_l4len_idx = sizeof(struct sctphdr) <<
6122 IXGBE_ADVTXD_L4LEN_SHIFT;
6123 break;
6124 case IPPROTO_UDP:
6125 mss_l4len_idx = sizeof(struct udphdr) <<
6126 IXGBE_ADVTXD_L4LEN_SHIFT;
6127 break;
6128 default:
6129 if (unlikely(net_ratelimit())) {
6130 dev_warn(tx_ring->dev,
6131 "partial checksum but l4 proto=%x!\n",
6132 skb->protocol);
6133 }
7ca647bd
JP		 6134 break;
6135 }
7ca647bd
JP		 6136 }
6137
897ab156
AD		 6138 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6139 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6140
897ab156
AD		 6141 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6142 type_tucmd, mss_l4len_idx);
9a799d71 6143
897ab156 6144 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6145}
6146
d3d00239 6147static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6148{
d3d00239
AD		 6149 /* set type for advanced descriptor with frame checksum insertion */
6150 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6151 IXGBE_ADVTXD_DCMD_IFCS |
6152 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6153
d3d00239 6154 /* set HW vlan bit if vlan is present */
66f32a8b 6155 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6156 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6157
d3d00239
AD		 6158 /* set segmentation enable bits for TSO/FSO */
6159#ifdef IXGBE_FCOE
6160 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6161#else
6162 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6163#endif
6164 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6165
d3d00239
AD		 6166 return cmd_type;
6167}
9a799d71 6168
d3d00239
AD		 6169static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6170{
6171 __le32 olinfo_status =
6172 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6173
d3d00239
AD		 6174 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6175 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6176 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6177 /* enble IPv4 checksum for TSO */
6178 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6179 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6180 }
6181
d3d00239
AD		 6182 /* enable L4 checksum for TSO and TX checksum offload */
6183 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6184 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6185
d3d00239
AD		 6186#ifdef IXGBE_FCOE
6187 /* use index 1 context for FCOE/FSO */
6188 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6189 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6190 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6191
d3d00239 6192#endif
7f9643fd
AD		 6193 /*
6194 * Check Context must be set if Tx switch is enabled, which it
6195 * always is for case where virtual functions are running
6196 */
6197 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6198 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6199
d3d00239
AD		 6200 return olinfo_status;
6201}
44df32c5 6202
d3d00239
AD		 6203#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6204 IXGBE_TXD_CMD_RS)
6205
6206static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6207 struct sk_buff *skb,
6208 struct ixgbe_tx_buffer *first,
6209 u32 tx_flags,
6210 const u8 hdr_len)
6211{
6212 struct device *dev = tx_ring->dev;
6213 struct ixgbe_tx_buffer *tx_buffer_info;
6214 union ixgbe_adv_tx_desc *tx_desc;
6215 dma_addr_t dma;
6216 __le32 cmd_type, olinfo_status;
6217 struct skb_frag_struct *frag;
6218 unsigned int f = 0;
6219 unsigned int data_len = skb->data_len;
6220 unsigned int size = skb_headlen(skb);
6221 u32 offset = 0;
6222 u32 paylen = skb->len - hdr_len;
6223 u16 i = tx_ring->next_to_use;
6224 u16 gso_segs;
6225
6226#ifdef IXGBE_FCOE
6227 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6228 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6229 data_len -= sizeof(struct fcoe_crc_eof);
6230 } else {
6231 size -= sizeof(struct fcoe_crc_eof) - data_len;
6232 data_len = 0;
9a799d71
AK		 6233 }
6234 }
44df32c5 6235
d3d00239
AD		 6236#endif
6237 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6238 if (dma_mapping_error(dev, dma))
6239 goto dma_error;
8ad494b0 6240
d3d00239
AD		 6241 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6242 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6243
d3d00239 6244 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6245
d3d00239
AD		 6246 for (;;) {
6247 while (size > IXGBE_MAX_DATA_PER_TXD) {
6248 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6249 tx_desc->read.cmd_type_len =
6250 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6251 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6252
d3d00239
AD		 6253 offset += IXGBE_MAX_DATA_PER_TXD;
6254 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6255
d3d00239
AD		 6256 tx_desc++;
6257 i++;
6258 if (i == tx_ring->count) {
6259 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6260 i = 0;
6261 }
6262 }
e5a43549 6263
e5a43549 6264 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6265 tx_buffer_info->length = offset + size;
6266 tx_buffer_info->tx_flags = tx_flags;
6267 tx_buffer_info->dma = dma;
9a799d71 6268
d3d00239
AD		 6269 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6270 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6271 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6272
d3d00239
AD		 6273 if (!data_len)
6274 break;
9a799d71 6275
d3d00239
AD		 6276 frag = &skb_shinfo(skb)->frags[f];
6277#ifdef IXGBE_FCOE
6278 size = min_t(unsigned int, data_len, frag->size);
6279#else
6280 size = frag->size;
6281#endif
6282 data_len -= size;
6283 f++;
9a799d71 6284
d3d00239
AD		 6285 offset = 0;
6286 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6287
877749bf 6288 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6289 if (dma_mapping_error(dev, dma))
6290 goto dma_error;
9a799d71 6291
d3d00239
AD		 6292 tx_desc++;
6293 i++;
6294 if (i == tx_ring->count) {
6295 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6296 i = 0;
6297 }
6298 }
9a799d71 6299
d3d00239 6300 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6301
d3d00239
AD		 6302 i++;
6303 if (i == tx_ring->count)
6304 i = 0;
9a799d71 6305
d3d00239 6306 tx_ring->next_to_use = i;
eacd73f7 6307
d3d00239
AD		 6308 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6309 gso_segs = skb_shinfo(skb)->gso_segs;
6310#ifdef IXGBE_FCOE
6311 /* adjust for FCoE Sequence Offload */
6312 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6313 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6314 skb_shinfo(skb)->gso_size);
6315#endif /* IXGBE_FCOE */
6316 else
6317 gso_segs = 1;
9a799d71 6318
d3d00239
AD		 6319 /* multiply data chunks by size of headers */
6320 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6321 tx_buffer_info->gso_segs = gso_segs;
6322 tx_buffer_info->skb = skb;
9a799d71 6323
d3d00239
AD		 6324 /* set the timestamp */
6325 first->time_stamp = jiffies;
9a799d71
AK		 6326
6327 /*
6328 * Force memory writes to complete before letting h/w
6329 * know there are new descriptors to fetch. (Only
6330 * applicable for weak-ordered memory model archs,
6331 * such as IA-64).
6332 */
6333 wmb();
6334
d3d00239
AD		 6335 /* set next_to_watch value indicating a packet is present */
6336 first->next_to_watch = tx_desc;
6337
6338 /* notify HW of packet */
84ea2591 6339 writel(i, tx_ring->tail);
d3d00239
AD		 6340
6341 return;
6342dma_error:
6343 dev_err(dev, "TX DMA map failed\n");
6344
6345 /* clear dma mappings for failed tx_buffer_info map */
6346 for (;;) {
6347 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6348 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6349 if (tx_buffer_info == first)
6350 break;
6351 if (i == 0)
6352 i = tx_ring->count;
6353 i--;
6354 }
6355
6356 dev_kfree_skb_any(skb);
6357
6358 tx_ring->next_to_use = i;
9a799d71
AK		 6359}
6360
69830529
AD		 6361static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6362 u32 tx_flags, __be16 protocol)
6363{
6364 struct ixgbe_q_vector *q_vector = ring->q_vector;
6365 union ixgbe_atr_hash_dword input = { .dword = 0 };
6366 union ixgbe_atr_hash_dword common = { .dword = 0 };
6367 union {
6368 unsigned char *network;
6369 struct iphdr *ipv4;
6370 struct ipv6hdr *ipv6;
6371 } hdr;
ee9e0f0b 6372 struct tcphdr *th;
905e4a41 6373 __be16 vlan_id;
c4cf55e5 6374
69830529
AD		 6375 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6376 if (!q_vector)
6377 return;
6378
6379 /* do nothing if sampling is disabled */
6380 if (!ring->atr_sample_rate)
d3ead241 6381 return;
c4cf55e5 6382
69830529 6383 ring->atr_count++;
c4cf55e5 6384
69830529
AD		 6385 /* snag network header to get L4 type and address */
6386 hdr.network = skb_network_header(skb);
6387
6388 /* Currently only IPv4/IPv6 with TCP is supported */
6389 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6390 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6391 (protocol != __constant_htons(ETH_P_IP) ||
6392 hdr.ipv4->protocol != IPPROTO_TCP))
6393 return;
ee9e0f0b
AD		 6394
6395 th = tcp_hdr(skb);
c4cf55e5 6396
66f32a8b
AD		 6397 /* skip this packet since it is invalid or the socket is closing */
6398 if (!th || th->fin)
69830529
AD		 6399 return;
6400
6401 /* sample on all syn packets or once every atr sample count */
6402 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6403 return;
6404
6405 /* reset sample count */
6406 ring->atr_count = 0;
6407
6408 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6409
6410 /*
6411 * src and dst are inverted, think how the receiver sees them
6412 *
6413 * The input is broken into two sections, a non-compressed section
6414 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6415 * is XORed together and stored in the compressed dword.
6416 */
6417 input.formatted.vlan_id = vlan_id;
6418
6419 /*
6420 * since src port and flex bytes occupy the same word XOR them together
6421 * and write the value to source port portion of compressed dword
6422 */
66f32a8b 6423 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6424 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6425 else
6426 common.port.src ^= th->dest ^ protocol;
6427 common.port.dst ^= th->source;
6428
6429 if (protocol == __constant_htons(ETH_P_IP)) {
6430 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6431 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6432 } else {
6433 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6434 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6435 hdr.ipv6->saddr.s6_addr32[1] ^
6436 hdr.ipv6->saddr.s6_addr32[2] ^
6437 hdr.ipv6->saddr.s6_addr32[3] ^
6438 hdr.ipv6->daddr.s6_addr32[0] ^
6439 hdr.ipv6->daddr.s6_addr32[1] ^
6440 hdr.ipv6->daddr.s6_addr32[2] ^
6441 hdr.ipv6->daddr.s6_addr32[3];
6442 }
c4cf55e5
PWJ		 6443
6444 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6445 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6446 input, common, ring->queue_index);
c4cf55e5
PWJ		 6447}
6448
63544e9c 6449static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6450{
fc77dc3c 6451 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6452 /* Herbert's original patch had:
6453 * smp_mb__after_netif_stop_queue();
6454 * but since that doesn't exist yet, just open code it. */
6455 smp_mb();
6456
6457 /* We need to check again in a case another CPU has just
6458 * made room available. */
7d4987de 6459 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6460 return -EBUSY;
6461
6462 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6463 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6464 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6465 return 0;
6466}
6467
82d4e46e 6468static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6469{
7d4987de 6470 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6471 return 0;
fc77dc3c 6472 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6473}
6474
09a3b1f8
SH		 6475static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6476{
6477 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6478 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6479 smp_processor_id();
56075a98 6480#ifdef IXGBE_FCOE
6440752c 6481 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6482
e5b64635
JF		 6483 if (((protocol == htons(ETH_P_FCOE)) ||
6484 (protocol == htons(ETH_P_FIP))) &&
6485 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6486 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6487 txq += adapter->ring_feature[RING_F_FCOE].mask;
6488 return txq;
56075a98
JF		 6489 }
6490#endif
6491
fdd3d631
KK		 6492 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6493 while (unlikely(txq >= dev->real_num_tx_queues))
6494 txq -= dev->real_num_tx_queues;
5f715823 6495 return txq;
fdd3d631 6496 }
c4cf55e5 6497
09a3b1f8
SH		 6498 return skb_tx_hash(dev, skb);
6499}
6500
fc77dc3c 6501netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6502 struct ixgbe_adapter *adapter,
6503 struct ixgbe_ring *tx_ring)
9a799d71 6504{
d3d00239 6505 struct ixgbe_tx_buffer *first;
5f715823 6506 int tso;
d3d00239 6507 u32 tx_flags = 0;
a535c30e
AD		 6508#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6509 unsigned short f;
6510#endif
a535c30e 6511 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6512 __be16 protocol = skb->protocol;
63544e9c 6513 u8 hdr_len = 0;
5e09a105 6514
a535c30e
AD		 6515 /*
6516 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6517 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6518 * + 2 desc gap to keep tail from touching head,
6519 * + 1 desc for context descriptor,
6520 * otherwise try next time
6521 */
6522#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6523 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6524 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6525#else
6526 count += skb_shinfo(skb)->nr_frags;
6527#endif
6528 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6529 tx_ring->tx_stats.tx_busy++;
6530 return NETDEV_TX_BUSY;
6531 }
6532
7f9643fd
AD		 6533#ifdef CONFIG_PCI_IOV
6534 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6535 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6536
6537#endif
66f32a8b 6538 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6539 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6540 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6541 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6542 /* else if it is a SW VLAN check the next protocol and store the tag */
6543 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6544 struct vlan_hdr *vhdr, _vhdr;
6545 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6546 if (!vhdr)
6547 goto out_drop;
6548
6549 protocol = vhdr->h_vlan_encapsulated_proto;
6550 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6551 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6552 }
6553
6554 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6555 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6556 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b
AD		 6557 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6558 tx_flags |= tx_ring->dcb_tc <<
6559 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6560 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6561 struct vlan_ethhdr *vhdr;
6562 if (skb_header_cloned(skb) &&
6563 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6564 goto out_drop;
6565 vhdr = (struct vlan_ethhdr *)skb->data;
6566 vhdr->h_vlan_TCI = htons(tx_flags >>
6567 IXGBE_TX_FLAGS_VLAN_SHIFT);
6568 } else {
6569 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6570 }
9a799d71 6571 }
eacd73f7 6572
a535c30e 6573 /* record the location of the first descriptor for this packet */
d3d00239 6574 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6575
eacd73f7 6576#ifdef IXGBE_FCOE
66f32a8b
AD		 6577 /* setup tx offload for FCoE */
6578 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6579 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6580 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6581 if (tso < 0)
6582 goto out_drop;
6583 else if (tso)
66f32a8b
AD		 6584 tx_flags |= IXGBE_TX_FLAGS_FSO |
6585 IXGBE_TX_FLAGS_FCOE;
6586 else
6587 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6588
66f32a8b 6589 goto xmit_fcoe;
eacd73f7 6590 }
9a799d71 6591
66f32a8b
AD		 6592#endif /* IXGBE_FCOE */
6593 /* setup IPv4/IPv6 offloads */
6594 if (protocol == __constant_htons(ETH_P_IP))
6595 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6596
66f32a8b
AD		 6597 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6598 if (tso < 0)
897ab156 6599 goto out_drop;
66f32a8b
AD		 6600 else if (tso)
6601 tx_flags |= IXGBE_TX_FLAGS_TSO;
6602 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6603 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6604
6605 /* add the ATR filter if ATR is on */
6606 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6607 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6608
6609#ifdef IXGBE_FCOE
6610xmit_fcoe:
6611#endif /* IXGBE_FCOE */
d3d00239
AD		 6612 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6613
6614 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6615
6616 return NETDEV_TX_OK;
897ab156
AD		 6617
6618out_drop:
6619 dev_kfree_skb_any(skb);
6620 return NETDEV_TX_OK;
9a799d71
AK		 6621}
6622
84418e3b
AD		 6623static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6624{
6625 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6626 struct ixgbe_ring *tx_ring;
6627
6628 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6629 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6630}
6631
9a799d71
AK		 6632/**
6633 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6634 * @netdev: network interface device structure
6635 * @p: pointer to an address structure
6636 *
6637 * Returns 0 on success, negative on failure
6638 **/
6639static int ixgbe_set_mac(struct net_device *netdev, void *p)
6640{
6641 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6642 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6643 struct sockaddr *addr = p;
6644
6645 if (!is_valid_ether_addr(addr->sa_data))
6646 return -EADDRNOTAVAIL;
6647
6648 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6649 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6650
1cdd1ec8
GR		 6651 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6652 IXGBE_RAH_AV);
9a799d71
AK		 6653
6654 return 0;
6655}
6656
6b73e10d
BH		 6657static int
6658ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6659{
6660 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6661 struct ixgbe_hw *hw = &adapter->hw;
6662 u16 value;
6663 int rc;
6664
6665 if (prtad != hw->phy.mdio.prtad)
6666 return -EINVAL;
6667 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6668 if (!rc)
6669 rc = value;
6670 return rc;
6671}
6672
6673static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6674 u16 addr, u16 value)
6675{
6676 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6677 struct ixgbe_hw *hw = &adapter->hw;
6678
6679 if (prtad != hw->phy.mdio.prtad)
6680 return -EINVAL;
6681 return hw->phy.ops.write_reg(hw, addr, devad, value);
6682}
6683
6684static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6685{
6686 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6687
6688 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6689}
6690
0365e6e4
PW		 6691/**
6692 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6693 * netdev->dev_addrs
0365e6e4
PW		 6694 * @netdev: network interface device structure
6695 *
6696 * Returns non-zero on failure
6697 **/
6698static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6699{
6700 int err = 0;
6701 struct ixgbe_adapter *adapter = netdev_priv(dev);
6702 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6703
6704 if (is_valid_ether_addr(mac->san_addr)) {
6705 rtnl_lock();
6706 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6707 rtnl_unlock();
6708 }
6709 return err;
6710}
6711
6712/**
6713 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6714 * netdev->dev_addrs
0365e6e4
PW		 6715 * @netdev: network interface device structure
6716 *
6717 * Returns non-zero on failure
6718 **/
6719static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6720{
6721 int err = 0;
6722 struct ixgbe_adapter *adapter = netdev_priv(dev);
6723 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6724
6725 if (is_valid_ether_addr(mac->san_addr)) {
6726 rtnl_lock();
6727 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6728 rtnl_unlock();
6729 }
6730 return err;
6731}
6732
9a799d71
AK		 6733#ifdef CONFIG_NET_POLL_CONTROLLER
6734/*
6735 * Polling 'interrupt' - used by things like netconsole to send skbs
6736 * without having to re-enable interrupts. It's not called while
6737 * the interrupt routine is executing.
6738 */
6739static void ixgbe_netpoll(struct net_device *netdev)
6740{
6741 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6742 int i;
9a799d71 6743
1a647bd2
AD		 6744 /* if interface is down do nothing */
6745 if (test_bit(__IXGBE_DOWN, &adapter->state))
6746 return;
6747
9a799d71 6748 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6749 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6750 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6751 for (i = 0; i < num_q_vectors; i++) {
6752 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 6753 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 6754 }
6755 } else {
6756 ixgbe_intr(adapter->pdev->irq, netdev);
6757 }
9a799d71 6758 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6759}
6760#endif
6761
de1036b1
ED		 6762static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6763 struct rtnl_link_stats64 *stats)
6764{
6765 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6766 int i;
6767
1a51502b 6768 rcu_read_lock();
de1036b1 6769 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6770 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6771 u64 bytes, packets;
6772 unsigned int start;
6773
1a51502b
ED		 6774 if (ring) {
6775 do {
6776 start = u64_stats_fetch_begin_bh(&ring->syncp);
6777 packets = ring->stats.packets;
6778 bytes = ring->stats.bytes;
6779 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6780 stats->rx_packets += packets;
6781 stats->rx_bytes += bytes;
6782 }
de1036b1 6783 }
1ac9ad13
ED		 6784
6785 for (i = 0; i < adapter->num_tx_queues; i++) {
6786 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6787 u64 bytes, packets;
6788 unsigned int start;
6789
6790 if (ring) {
6791 do {
6792 start = u64_stats_fetch_begin_bh(&ring->syncp);
6793 packets = ring->stats.packets;
6794 bytes = ring->stats.bytes;
6795 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6796 stats->tx_packets += packets;
6797 stats->tx_bytes += bytes;
6798 }
6799 }
1a51502b 6800 rcu_read_unlock();
de1036b1
ED		 6801 /* following stats updated by ixgbe_watchdog_task() */
6802 stats->multicast = netdev->stats.multicast;
6803 stats->rx_errors = netdev->stats.rx_errors;
6804 stats->rx_length_errors = netdev->stats.rx_length_errors;
6805 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6806 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6807 return stats;
6808}
6809
8b1c0b24
JF		 6810/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6811 * #adapter: pointer to ixgbe_adapter
6812 * @tc: number of traffic classes currently enabled
6813 *
6814 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6815 * 802.1Q priority maps to a packet buffer that exists.
6816 */
6817static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6818{
6819 struct ixgbe_hw *hw = &adapter->hw;
6820 u32 reg, rsave;
6821 int i;
6822
6823 /* 82598 have a static priority to TC mapping that can not
6824 * be changed so no validation is needed.
6825 */
6826 if (hw->mac.type == ixgbe_mac_82598EB)
6827 return;
6828
6829 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6830 rsave = reg;
6831
6832 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6833 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6834
6835 /* If up2tc is out of bounds default to zero */
6836 if (up2tc > tc)
6837 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6838 }
6839
6840 if (reg != rsave)
6841 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6842
6843 return;
6844}
6845
6846
6847/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6848 * classes.
6849 *
6850 * @netdev: net device to configure
6851 * @tc: number of traffic classes to enable
6852 */
6853int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6854{
8b1c0b24
JF		 6855 struct ixgbe_adapter *adapter = netdev_priv(dev);
6856 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6857
e7589eab
JF		 6858 /* Multiple traffic classes requires multiple queues */
6859 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6860 e_err(drv, "Enable failed, needs MSI-X\n");
6861 return -EINVAL;
6862 }
8b1c0b24
JF		 6863
6864 /* Hardware supports up to 8 traffic classes */
6865 if (tc > MAX_TRAFFIC_CLASS ||
6866 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6867 return -EINVAL;
6868
6869 /* Hardware has to reinitialize queues and interrupts to
6870 * match packet buffer alignment. Unfortunantly, the
6871 * hardware is not flexible enough to do this dynamically.
6872 */
6873 if (netif_running(dev))
6874 ixgbe_close(dev);
6875 ixgbe_clear_interrupt_scheme(adapter);
6876
e7589eab 6877 if (tc) {
8b1c0b24 6878 netdev_set_num_tc(dev, tc);
e7589eab
JF		 6879 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6880
6881 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6882 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6883
6884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6885 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6886 } else {
8b1c0b24
JF		 6887 netdev_reset_tc(dev);
6888
e7589eab
JF		 6889 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6890
6891 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6892 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6893
6894 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6895 adapter->dcb_cfg.pfc_mode_enable = false;
6896 }
6897
8b1c0b24
JF		 6898 ixgbe_init_interrupt_scheme(adapter);
6899 ixgbe_validate_rtr(adapter, tc);
6900 if (netif_running(dev))
6901 ixgbe_open(dev);
6902
6903 return 0;
6904}
de1036b1 6905
082757af
DS		 6906void ixgbe_do_reset(struct net_device *netdev)
6907{
6908 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6909
6910 if (netif_running(netdev))
6911 ixgbe_reinit_locked(adapter);
6912 else
6913 ixgbe_reset(adapter);
6914}
6915
6916static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6917{
6918 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6919
6920#ifdef CONFIG_DCB
6921 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6922 data &= ~NETIF_F_HW_VLAN_RX;
6923#endif
6924
6925 /* return error if RXHASH is being enabled when RSS is not supported */
6926 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6927 data &= ~NETIF_F_RXHASH;
6928
6929 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6930 if (!(data & NETIF_F_RXCSUM))
6931 data &= ~NETIF_F_LRO;
6932
6933 /* Turn off LRO if not RSC capable or invalid ITR settings */
6934 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6935 data &= ~NETIF_F_LRO;
6936 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6937 (adapter->rx_itr_setting != 1 &&
6938 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6939 data &= ~NETIF_F_LRO;
6940 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6941 }
6942
6943 return data;
6944}
6945
6946static int ixgbe_set_features(struct net_device *netdev, u32 data)
6947{
6948 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6949 bool need_reset = false;
6950
6951 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6952 if (!(data & NETIF_F_RXCSUM))
6953 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
6954 else
6955 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
6956
6957 /* Make sure RSC matches LRO, reset if change */
6958 if (!!(data & NETIF_F_LRO) !=
6959 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6960 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
6961 switch (adapter->hw.mac.type) {
6962 case ixgbe_mac_X540:
6963 case ixgbe_mac_82599EB:
6964 need_reset = true;
6965 break;
6966 default:
6967 break;
6968 }
6969 }
6970
6971 /*
6972 * Check if Flow Director n-tuple support was enabled or disabled. If
6973 * the state changed, we need to reset.
6974 */
6975 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6976 /* turn off ATR, enable perfect filters and reset */
6977 if (data & NETIF_F_NTUPLE) {
6978 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6979 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6980 need_reset = true;
6981 }
6982 } else if (!(data & NETIF_F_NTUPLE)) {
6983 /* turn off Flow Director, set ATR and reset */
6984 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6985 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6986 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6987 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6988 need_reset = true;
6989 }
6990
6991 if (need_reset)
6992 ixgbe_do_reset(netdev);
6993
6994 return 0;
6995
6996}
6997
0edc3527 6998static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6999 .ndo_open = ixgbe_open,
0edc3527 7000 .ndo_stop = ixgbe_close,
00829823 7001 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7002 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7003 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7004 .ndo_validate_addr = eth_validate_addr,
7005 .ndo_set_mac_address = ixgbe_set_mac,
7006 .ndo_change_mtu = ixgbe_change_mtu,
7007 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7008 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7009 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7010 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7011 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7012 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7013 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7014 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7015 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7016 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7017#ifdef CONFIG_NET_POLL_CONTROLLER
7018 .ndo_poll_controller = ixgbe_netpoll,
7019#endif
332d4a7d
YZ		 7020#ifdef IXGBE_FCOE
7021 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7022 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7023 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7024 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7025 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7026 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7027#endif /* IXGBE_FCOE */
082757af
DS		 7028 .ndo_set_features = ixgbe_set_features,
7029 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7030};
7031
1cdd1ec8
GR		 7032static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7033 const struct ixgbe_info *ii)
7034{
7035#ifdef CONFIG_PCI_IOV
7036 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7037
c6bda30a 7038 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7039 return;
7040
7041 /* The 82599 supports up to 64 VFs per physical function
7042 * but this implementation limits allocation to 63 so that
7043 * basic networking resources are still available to the
7044 * physical function
7045 */
7046 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7047 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7048#endif /* CONFIG_PCI_IOV */
7049}
7050
9a799d71
AK		 7051/**
7052 * ixgbe_probe - Device Initialization Routine
7053 * @pdev: PCI device information struct
7054 * @ent: entry in ixgbe_pci_tbl
7055 *
7056 * Returns 0 on success, negative on failure
7057 *
7058 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7059 * The OS initialization, configuring of the adapter private structure,
7060 * and a hardware reset occur.
7061 **/
7062static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7063 const struct pci_device_id *ent)
9a799d71
AK		 7064{
7065 struct net_device *netdev;
7066 struct ixgbe_adapter *adapter = NULL;
7067 struct ixgbe_hw *hw;
7068 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7069 static int cards_found;
7070 int i, err, pci_using_dac;
289700db 7071 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7072 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7073#ifdef IXGBE_FCOE
7074 u16 device_caps;
7075#endif
289700db 7076 u32 eec;
c23f5b6b 7077 u16 wol_cap;
9a799d71 7078
bded64a7
AG		 7079 /* Catch broken hardware that put the wrong VF device ID in
7080 * the PCIe SR-IOV capability.
7081 */
7082 if (pdev->is_virtfn) {
7083 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7084 pci_name(pdev), pdev->vendor, pdev->device);
7085 return -EINVAL;
7086 }
7087
9ce77666 7088 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7089 if (err)
7090 return err;
7091
1b507730
NN		 7092 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7093 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7094 pci_using_dac = 1;
7095 } else {
1b507730 7096 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7097 if (err) {
1b507730
NN		 7098 err = dma_set_coherent_mask(&pdev->dev,
7099 DMA_BIT_MASK(32));
9a799d71 7100 if (err) {
b8bc0421
DC		 7101 dev_err(&pdev->dev,
7102 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7103 goto err_dma;
7104 }
7105 }
7106 pci_using_dac = 0;
7107 }
7108
9ce77666 7109 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7110 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7111 if (err) {
b8bc0421
DC		 7112 dev_err(&pdev->dev,
7113 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7114 goto err_pci_reg;
7115 }
7116
19d5afd4 7117 pci_enable_pcie_error_reporting(pdev);
6fabd715 7118
9a799d71 7119 pci_set_master(pdev);
fb3b27bc 7120 pci_save_state(pdev);
9a799d71 7121
e901acd6
JF		 7122#ifdef CONFIG_IXGBE_DCB
7123 indices *= MAX_TRAFFIC_CLASS;
7124#endif
7125
c85a2618
JF		 7126 if (ii->mac == ixgbe_mac_82598EB)
7127 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7128 else
7129 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7130
e901acd6 7131#ifdef IXGBE_FCOE
c85a2618
JF		 7132 indices += min_t(unsigned int, num_possible_cpus(),
7133 IXGBE_MAX_FCOE_INDICES);
7134#endif
c85a2618 7135 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7136 if (!netdev) {
7137 err = -ENOMEM;
7138 goto err_alloc_etherdev;
7139 }
7140
9a799d71
AK		 7141 SET_NETDEV_DEV(netdev, &pdev->dev);
7142
9a799d71 7143 adapter = netdev_priv(netdev);
c60fbb00 7144 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7145
7146 adapter->netdev = netdev;
7147 adapter->pdev = pdev;
7148 hw = &adapter->hw;
7149 hw->back = adapter;
7150 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7151
05857980 7152 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7153 pci_resource_len(pdev, 0));
9a799d71
AK		 7154 if (!hw->hw_addr) {
7155 err = -EIO;
7156 goto err_ioremap;
7157 }
7158
7159 for (i = 1; i <= 5; i++) {
7160 if (pci_resource_len(pdev, i) == 0)
7161 continue;
7162 }
7163
0edc3527 7164 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7165 ixgbe_set_ethtool_ops(netdev);
9a799d71 7166 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7167 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7168
9a799d71
AK		 7169 adapter->bd_number = cards_found;
7170
9a799d71
AK		 7171 /* Setup hw api */
7172 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7173 hw->mac.type = ii->mac;
9a799d71 7174
c44ade9e
JB		 7175 /* EEPROM */
7176 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7177 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7178 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7179 if (!(eec & (1 << 8)))
7180 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7181
7182 /* PHY */
7183 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7184 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7185 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7186 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7187 hw->phy.mdio.mmds = 0;
7188 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7189 hw->phy.mdio.dev = netdev;
7190 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7191 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7192
8ca783ab 7193 ii->get_invariants(hw);
9a799d71
AK		 7194
7195 /* setup the private structure */
7196 err = ixgbe_sw_init(adapter);
7197 if (err)
7198 goto err_sw_init;
7199
e86bff0e 7200 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7201 switch (adapter->hw.mac.type) {
7202 case ixgbe_mac_82599EB:
7203 case ixgbe_mac_X540:
e86bff0e 7204 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7205 break;
7206 default:
7207 break;
7208 }
e86bff0e 7209
bf069c97
DS		 7210 /*
7211 * If there is a fan on this device and it has failed log the
7212 * failure.
7213 */
7214 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7215 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7216 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7217 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7218 }
7219
c44ade9e 7220 /* reset_hw fills in the perm_addr as well */
119fc60a 7221 hw->phy.reset_if_overtemp = true;
c44ade9e 7222 err = hw->mac.ops.reset_hw(hw);
119fc60a 7223 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7224 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7225 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7226 err = 0;
7227 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7228 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7229 "module type was detected.\n");
7230 e_dev_err("Reload the driver after installing a supported "
7231 "module.\n");
04f165ef
PW		 7232 goto err_sw_init;
7233 } else if (err) {
849c4542 7234 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7235 goto err_sw_init;
7236 }
7237
1cdd1ec8
GR		 7238 ixgbe_probe_vf(adapter, ii);
7239
396e799c 7240 netdev->features = NETIF_F_SG |
e8e9f696 7241 NETIF_F_IP_CSUM |
082757af 7242 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7243 NETIF_F_HW_VLAN_TX |
7244 NETIF_F_HW_VLAN_RX |
082757af
DS		 7245 NETIF_F_HW_VLAN_FILTER |
7246 NETIF_F_TSO |
7247 NETIF_F_TSO6 |
082757af
DS		 7248 NETIF_F_RXHASH |
7249 NETIF_F_RXCSUM;
9a799d71 7250
082757af 7251 netdev->hw_features = netdev->features;
ad31c402 7252
58be7666
DS		 7253 switch (adapter->hw.mac.type) {
7254 case ixgbe_mac_82599EB:
7255 case ixgbe_mac_X540:
45a5ead0 7256 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7257 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7258 NETIF_F_NTUPLE;
58be7666
DS		 7259 break;
7260 default:
7261 break;
7262 }
45a5ead0 7263
ad31c402
JK		 7264 netdev->vlan_features |= NETIF_F_TSO;
7265 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7266 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7267 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7268 netdev->vlan_features |= NETIF_F_SG;
7269
01789349
JP		 7270 netdev->priv_flags |= IFF_UNICAST_FLT;
7271
1cdd1ec8
GR		 7272 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7273 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7274 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7275
7a6b6f51 7276#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7277 netdev->dcbnl_ops = &dcbnl_ops;
7278#endif
7279
eacd73f7 7280#ifdef IXGBE_FCOE
0d551589 7281 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7282 if (hw->mac.ops.get_device_caps) {
7283 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7284 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7285 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7286 }
7287 }
5e09d7f6
YZ		 7288 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7289 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7290 netdev->vlan_features |= NETIF_F_FSO;
7291 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7292 }
eacd73f7 7293#endif /* IXGBE_FCOE */
7b872a55 7294 if (pci_using_dac) {
9a799d71 7295 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7296 netdev->vlan_features |= NETIF_F_HIGHDMA;
7297 }
9a799d71 7298
082757af
DS		 7299 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7300 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7301 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7302 netdev->features |= NETIF_F_LRO;
7303
9a799d71 7304 /* make sure the EEPROM is good */
c44ade9e 7305 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7306 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7307 err = -EIO;
7308 goto err_eeprom;
7309 }
7310
7311 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7312 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7313
c44ade9e 7314 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7315 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7316 err = -EIO;
7317 goto err_eeprom;
7318 }
7319
c6ecf39a
DS		 7320 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7321 if (hw->mac.ops.disable_tx_laser &&
7322 ((hw->phy.multispeed_fiber) ||
9f911707 7323 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7324 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7325 hw->mac.ops.disable_tx_laser(hw);
7326
7086400d
AD		 7327 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7328 (unsigned long) adapter);
9a799d71 7329
7086400d
AD		 7330 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7331 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7332
021230d4
AV		 7333 err = ixgbe_init_interrupt_scheme(adapter);
7334 if (err)
7335 goto err_sw_init;
9a799d71 7336
082757af
DS		 7337 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7338 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7339 netdev->features &= ~NETIF_F_RXHASH;
082757af 7340 }
67a74ee2 7341
c23f5b6b
ET		 7342 /* WOL not supported for all but the following */
7343 adapter->wol = 0;
e8e26350 7344 switch (pdev->device) {
0b077fea
DS		 7345 case IXGBE_DEV_ID_82599_SFP:
7346 /* Only this subdevice supports WOL */
7347 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7348 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7349 break;
50d6c681
AD		 7350 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7351 /* All except this subdevice support WOL */
0b077fea 7352 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7353 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7354 break;
e8e26350 7355 case IXGBE_DEV_ID_82599_KX4:
9417c464 7356 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7357 break;
c23f5b6b
ET		 7358 case IXGBE_DEV_ID_X540T:
7359 /* Check eeprom to see if it is enabled */
7360 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7361 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7362
7363 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7364 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7365 (hw->bus.func == 0)))
7366 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7367 break;
7368 }
e8e26350
PW		 7369 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7370
04f165ef
PW		 7371 /* pick up the PCI bus settings for reporting later */
7372 hw->mac.ops.get_bus_info(hw);
7373
9a799d71 7374 /* print bus type/speed/width info */
849c4542 7375 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7376 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7377 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7378 "Unknown"),
7379 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7380 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7381 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7382 "Unknown"),
7383 netdev->dev_addr);
289700db
DS		 7384
7385 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7386 if (err)
9fe93afd 7387 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7388 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7389 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7390 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7391 part_str);
e8e26350 7392 else
289700db
DS		 7393 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7394 hw->mac.type, hw->phy.type, part_str);
9a799d71 7395
e8e26350 7396 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7397 e_dev_warn("PCI-Express bandwidth available for this card is "
7398 "not sufficient for optimal performance.\n");
7399 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7400 "is required.\n");
0c254d86
AK		 7401 }
7402
34b0368c
PWJ		 7403 /* save off EEPROM version number */
7404 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7405
9a799d71 7406 /* reset the hardware with the new settings */
794caeb2 7407 err = hw->mac.ops.start_hw(hw);
c44ade9e 7408
794caeb2
PWJ		 7409 if (err == IXGBE_ERR_EEPROM_VERSION) {
7410 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7411 e_dev_warn("This device is a pre-production adapter/LOM. "
7412 "Please be aware there may be issues associated "
7413 "with your hardware. If you are experiencing "
7414 "problems please contact your Intel or hardware "
7415 "representative who provided you with this "
7416 "hardware.\n");
794caeb2 7417 }
9a799d71
AK		 7418 strcpy(netdev->name, "eth%d");
7419 err = register_netdev(netdev);
7420 if (err)
7421 goto err_register;
7422
54386467
JB		 7423 /* carrier off reporting is important to ethtool even BEFORE open */
7424 netif_carrier_off(netdev);
7425
5dd2d332 7426#ifdef CONFIG_IXGBE_DCA
652f093f 7427 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7428 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7429 ixgbe_setup_dca(adapter);
7430 }
7431#endif
1cdd1ec8 7432 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7433 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7434 for (i = 0; i < adapter->num_vfs; i++)
7435 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7436 }
7437
9612de92
ET		 7438 /* Inform firmware of driver version */
7439 if (hw->mac.ops.set_fw_drv_ver)
a38a104d
DS		 7440 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7441 FW_CEM_UNUSED_VER);
9612de92 7442
0365e6e4
PW		 7443 /* add san mac addr to netdev */
7444 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7445
849c4542 7446 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7447 cards_found++;
7448 return 0;
7449
7450err_register:
5eba3699 7451 ixgbe_release_hw_control(adapter);
7a921c93 7452 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7453err_sw_init:
7454err_eeprom:
1cdd1ec8
GR		 7455 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7456 ixgbe_disable_sriov(adapter);
7086400d 7457 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7458 iounmap(hw->hw_addr);
7459err_ioremap:
7460 free_netdev(netdev);
7461err_alloc_etherdev:
e8e9f696
JP		 7462 pci_release_selected_regions(pdev,
7463 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7464err_pci_reg:
7465err_dma:
7466 pci_disable_device(pdev);
7467 return err;
7468}
7469
7470/**
7471 * ixgbe_remove - Device Removal Routine
7472 * @pdev: PCI device information struct
7473 *
7474 * ixgbe_remove is called by the PCI subsystem to alert the driver
7475 * that it should release a PCI device. The could be caused by a
7476 * Hot-Plug event, or because the driver is going to be removed from
7477 * memory.
7478 **/
7479static void __devexit ixgbe_remove(struct pci_dev *pdev)
7480{
c60fbb00
AD		 7481 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7482 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7483
7484 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7485 cancel_work_sync(&adapter->service_task);
9a799d71 7486
5dd2d332 7487#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7488 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7489 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7490 dca_remove_requester(&pdev->dev);
7491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7492 }
7493
7494#endif
332d4a7d
YZ		 7495#ifdef IXGBE_FCOE
7496 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7497 ixgbe_cleanup_fcoe(adapter);
7498
7499#endif /* IXGBE_FCOE */
0365e6e4
PW		 7500
7501 /* remove the added san mac */
7502 ixgbe_del_sanmac_netdev(netdev);
7503
c4900be0
DS		 7504 if (netdev->reg_state == NETREG_REGISTERED)
7505 unregister_netdev(netdev);
9a799d71 7506
c6bda30a
GR		 7507 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7508 if (!(ixgbe_check_vf_assignment(adapter)))
7509 ixgbe_disable_sriov(adapter);
7510 else
7511 e_dev_warn("Unloading driver while VFs are assigned "
7512 "- VFs will not be deallocated\n");
7513 }
1cdd1ec8 7514
7a921c93 7515 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7516
021230d4 7517 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7518
7519 iounmap(adapter->hw.hw_addr);
9ce77666 7520 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7521 IORESOURCE_MEM));
9a799d71 7522
849c4542 7523 e_dev_info("complete\n");
021230d4 7524
9a799d71
AK		 7525 free_netdev(netdev);
7526
19d5afd4 7527 pci_disable_pcie_error_reporting(pdev);
6fabd715 7528
9a799d71
AK		 7529 pci_disable_device(pdev);
7530}
7531
7532/**
7533 * ixgbe_io_error_detected - called when PCI error is detected
7534 * @pdev: Pointer to PCI device
7535 * @state: The current pci connection state
7536 *
7537 * This function is called after a PCI bus error affecting
7538 * this device has been detected.
7539 */
7540static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7541 pci_channel_state_t state)
9a799d71 7542{
c60fbb00
AD		 7543 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7544 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7545
7546 netif_device_detach(netdev);
7547
3044b8d1
BL		 7548 if (state == pci_channel_io_perm_failure)
7549 return PCI_ERS_RESULT_DISCONNECT;
7550
9a799d71
AK		 7551 if (netif_running(netdev))
7552 ixgbe_down(adapter);
7553 pci_disable_device(pdev);
7554
b4617240 7555 /* Request a slot reset. */
9a799d71
AK		 7556 return PCI_ERS_RESULT_NEED_RESET;
7557}
7558
7559/**
7560 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7561 * @pdev: Pointer to PCI device
7562 *
7563 * Restart the card from scratch, as if from a cold-boot.
7564 */
7565static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7566{
c60fbb00 7567 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7568 pci_ers_result_t result;
7569 int err;
9a799d71 7570
9ce77666 7571 if (pci_enable_device_mem(pdev)) {
396e799c 7572 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7573 result = PCI_ERS_RESULT_DISCONNECT;
7574 } else {
7575 pci_set_master(pdev);
7576 pci_restore_state(pdev);
c0e1f68b 7577 pci_save_state(pdev);
9a799d71 7578
dd4d8ca6 7579 pci_wake_from_d3(pdev, false);
9a799d71 7580
6fabd715 7581 ixgbe_reset(adapter);
88512539 7582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7583 result = PCI_ERS_RESULT_RECOVERED;
7584 }
7585
7586 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7587 if (err) {
849c4542
ET		 7588 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7589 "failed 0x%0x\n", err);
6fabd715
PWJ		 7590 /* non-fatal, continue */
7591 }
9a799d71 7592
6fabd715 7593 return result;
9a799d71
AK		 7594}
7595
7596/**
7597 * ixgbe_io_resume - called when traffic can start flowing again.
7598 * @pdev: Pointer to PCI device
7599 *
7600 * This callback is called when the error recovery driver tells us that
7601 * its OK to resume normal operation.
7602 */
7603static void ixgbe_io_resume(struct pci_dev *pdev)
7604{
c60fbb00
AD		 7605 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7606 struct net_device *netdev = adapter->netdev;
9a799d71 7607
c7ccde0f
AD		 7608 if (netif_running(netdev))
7609 ixgbe_up(adapter);
9a799d71
AK		 7610
7611 netif_device_attach(netdev);
9a799d71
AK		 7612}
7613
7614static struct pci_error_handlers ixgbe_err_handler = {
7615 .error_detected = ixgbe_io_error_detected,
7616 .slot_reset = ixgbe_io_slot_reset,
7617 .resume = ixgbe_io_resume,
7618};
7619
7620static struct pci_driver ixgbe_driver = {
7621 .name = ixgbe_driver_name,
7622 .id_table = ixgbe_pci_tbl,
7623 .probe = ixgbe_probe,
7624 .remove = __devexit_p(ixgbe_remove),
7625#ifdef CONFIG_PM
7626 .suspend = ixgbe_suspend,
7627 .resume = ixgbe_resume,
7628#endif
7629 .shutdown = ixgbe_shutdown,
7630 .err_handler = &ixgbe_err_handler
7631};
7632
7633/**
7634 * ixgbe_init_module - Driver Registration Routine
7635 *
7636 * ixgbe_init_module is the first routine called when the driver is
7637 * loaded. All it does is register with the PCI subsystem.
7638 **/
7639static int __init ixgbe_init_module(void)
7640{
7641 int ret;
c7689578 7642 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7643 pr_info("%s\n", ixgbe_copyright);
9a799d71 7644
5dd2d332 7645#ifdef CONFIG_IXGBE_DCA
bd0362dd 7646 dca_register_notify(&dca_notifier);
bd0362dd 7647#endif
5dd2d332 7648
9a799d71
AK		 7649 ret = pci_register_driver(&ixgbe_driver);
7650 return ret;
7651}
b4617240 7652
9a799d71
AK		 7653module_init(ixgbe_init_module);
7654
7655/**
7656 * ixgbe_exit_module - Driver Exit Cleanup Routine
7657 *
7658 * ixgbe_exit_module is called just before the driver is removed
7659 * from memory.
7660 **/
7661static void __exit ixgbe_exit_module(void)
7662{
5dd2d332 7663#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7664 dca_unregister_notify(&dca_notifier);
7665#endif
9a799d71 7666 pci_unregister_driver(&ixgbe_driver);
1a51502b 7667 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7668}
bd0362dd 7669
5dd2d332 7670#ifdef CONFIG_IXGBE_DCA
bd0362dd 7671static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7672 void *p)
bd0362dd
JC		 7673{
7674 int ret_val;
7675
7676 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7677 __ixgbe_notify_dca);
bd0362dd
JC		 7678
7679 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7680}
b453368d 7681
5dd2d332 7682#endif /* CONFIG_IXGBE_DCA */
849c4542 7683
9a799d71
AK		 7684module_exit(ixgbe_exit_module);
7685
7686/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)