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ixgbe: Copybreak sooner to avoid get_page/put_page and offset change overhead
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
9c50c035 399 tx_buffer->skb)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035 402 tx_buffer->skb->data,
729739b7
AD		 403 dma_unmap_len(tx_buffer, len),
404 true);
dcd79aeb
TI		 405 }
406 }
407
408 /* Print RX Rings Summary */
409rx_ring_summary:
410 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 411 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 412 for (n = 0; n < adapter->num_rx_queues; n++) {
413 rx_ring = adapter->rx_ring[n];
c7689578
JP		 414 pr_info("%5d %5X %5X\n",
415 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 416 }
417
418 /* Print RX Rings */
419 if (!netif_msg_rx_status(adapter))
420 goto exit;
421
422 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
423
424 /* Advanced Receive Descriptor (Read) Format
425 * 63 1 0
426 * +-----------------------------------------------------+
427 * 0 | Packet Buffer Address [63:1] |A0/NSE|
428 * +----------------------------------------------+------+
429 * 8 | Header Buffer Address [63:1] | DD |
430 * +-----------------------------------------------------+
431 *
432 *
433 * Advanced Receive Descriptor (Write-Back) Format
434 *
435 * 63 48 47 32 31 30 21 20 16 15 4 3 0
436 * +------------------------------------------------------+
437 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
438 * | Checksum Ident | | | | Type | Type |
439 * +------------------------------------------------------+
440 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
441 * +------------------------------------------------------+
442 * 63 48 47 32 31 20 19 0
443 */
444 for (n = 0; n < adapter->num_rx_queues; n++) {
445 rx_ring = adapter->rx_ring[n];
c7689578
JP		 446 pr_info("------------------------------------\n");
447 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
448 pr_info("------------------------------------\n");
449 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 450 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
451 "<-- Adv Rx Read format\n");
c7689578 452 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 453 "[vl er S cks ln] ---------------- [bi->skb] "
454 "<-- Adv Rx Write-Back format\n");
455
456 for (i = 0; i < rx_ring->count; i++) {
457 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 458 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 459 u0 = (struct my_u0 *)rx_desc;
460 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
461 if (staterr & IXGBE_RXD_STAT_DD) {
462 /* Descriptor Done */
c7689578 463 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 464 "%016llX ---------------- %p", i,
465 le64_to_cpu(u0->a),
466 le64_to_cpu(u0->b),
467 rx_buffer_info->skb);
468 } else {
c7689578 469 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 470 "%016llX %016llX %p", i,
471 le64_to_cpu(u0->a),
472 le64_to_cpu(u0->b),
473 (u64)rx_buffer_info->dma,
474 rx_buffer_info->skb);
475
9c50c035
ET		 476 if (netif_msg_pktdata(adapter) &&
477 rx_buffer_info->dma) {
dcd79aeb
TI		 478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 480 page_address(rx_buffer_info->page) +
481 rx_buffer_info->page_offset,
f800326d 482 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
49ce9c2c 520/**
e8e26350
PW		 521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
729739b7
AD		 592void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
729739b7
AD		 595 if (tx_buffer->skb) {
596 dev_kfree_skb_any(tx_buffer->skb);
597 if (dma_unmap_len(tx_buffer, len))
d3d00239 598 dma_unmap_single(ring->dev,
729739b7
AD		 599 dma_unmap_addr(tx_buffer, dma),
600 dma_unmap_len(tx_buffer, len),
601 DMA_TO_DEVICE);
602 } else if (dma_unmap_len(tx_buffer, len)) {
603 dma_unmap_page(ring->dev,
604 dma_unmap_addr(tx_buffer, dma),
605 dma_unmap_len(tx_buffer, len),
606 DMA_TO_DEVICE);
e5a43549 607 }
729739b7
AD		 608 tx_buffer->next_to_watch = NULL;
609 tx_buffer->skb = NULL;
610 dma_unmap_len_set(tx_buffer, len, 0);
611 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 612}
613
943561d3 614static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 615{
616 struct ixgbe_hw *hw = &adapter->hw;
617 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 618 int i;
943561d3 619 u32 data;
c84d324c 620
943561d3
AD		 621 if ((hw->fc.current_mode != ixgbe_fc_full) &&
622 (hw->fc.current_mode != ixgbe_fc_rx_pause))
623 return;
c84d324c 624
943561d3
AD		 625 switch (hw->mac.type) {
626 case ixgbe_mac_82598EB:
627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
628 break;
629 default:
630 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
631 }
632 hwstats->lxoffrxc += data;
c84d324c 633
943561d3
AD		 634 /* refill credits (no tx hang) if we received xoff */
635 if (!data)
c84d324c 636 return;
943561d3
AD		 637
638 for (i = 0; i < adapter->num_tx_queues; i++)
639 clear_bit(__IXGBE_HANG_CHECK_ARMED,
640 &adapter->tx_ring[i]->state);
641}
642
643static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
644{
645 struct ixgbe_hw *hw = &adapter->hw;
646 struct ixgbe_hw_stats *hwstats = &adapter->stats;
647 u32 xoff[8] = {0};
648 int i;
649 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
650
651 if (adapter->ixgbe_ieee_pfc)
652 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
653
654 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
655 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 656 return;
943561d3 657 }
c84d324c
JF		 658
659 /* update stats for each tc, only valid with PFC enabled */
660 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
661 switch (hw->mac.type) {
662 case ixgbe_mac_82598EB:
663 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 664 break;
c84d324c
JF		 665 default:
666 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 667 }
c84d324c
JF		 668 hwstats->pxoffrxc[i] += xoff[i];
669 }
670
671 /* disarm tx queues that have received xoff frames */
672 for (i = 0; i < adapter->num_tx_queues; i++) {
673 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 674 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 675
676 if (xoff[tc])
677 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 678 }
26f23d82
YZ		 679}
680
c84d324c 681static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 682{
7d7ce682 683 return ring->stats.packets;
c84d324c
JF		 684}
685
686static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
687{
688 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 689 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 690
c84d324c
JF		 691 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
692 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
693
694 if (head != tail)
695 return (head < tail) ?
696 tail - head : (tail + ring->count - head);
697
698 return 0;
699}
700
701static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
702{
703 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
704 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
705 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
706 bool ret = false;
707
7d637bcc 708 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 709
710 /*
711 * Check for a hung queue, but be thorough. This verifies
712 * that a transmit has been completed since the previous
713 * check AND there is at least one packet pending. The
714 * ARMED bit is set to indicate a potential hang. The
715 * bit is cleared if a pause frame is received to remove
716 * false hang detection due to PFC or 802.3x frames. By
717 * requiring this to fail twice we avoid races with
718 * pfc clearing the ARMED bit and conditions where we
719 * run the check_tx_hang logic with a transmit completion
720 * pending but without time to complete it yet.
721 */
722 if ((tx_done_old == tx_done) && tx_pending) {
723 /* make sure it is true for two checks in a row */
724 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
725 &tx_ring->state);
726 } else {
727 /* update completed stats and continue */
728 tx_ring->tx_stats.tx_done_old = tx_done;
729 /* reset the countdown */
730 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 731 }
732
c84d324c 733 return ret;
9a799d71
AK		 734}
735
c83c6cbd
AD		 736/**
737 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
738 * @adapter: driver private struct
739 **/
740static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
741{
742
743 /* Do the reset outside of interrupt context */
744 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
745 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
746 ixgbe_service_event_schedule(adapter);
747 }
748}
e01c31a5 749
9a799d71
AK		 750/**
751 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 752 * @q_vector: structure containing interrupt and ring information
e01c31a5 753 * @tx_ring: tx ring to clean
9a799d71 754 **/
fe49f04a 755static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 756 struct ixgbe_ring *tx_ring)
9a799d71 757{
fe49f04a 758 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 759 struct ixgbe_tx_buffer *tx_buffer;
760 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 761 unsigned int total_bytes = 0, total_packets = 0;
59224555 762 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 763 unsigned int i = tx_ring->next_to_clean;
764
765 if (test_bit(__IXGBE_DOWN, &adapter->state))
766 return true;
9a799d71 767
d3d00239 768 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 769 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 770 i -= tx_ring->count;
12207e49 771
729739b7 772 do {
d3d00239
AD		 773 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
774
775 /* if next_to_watch is not set then there is no work pending */
776 if (!eop_desc)
777 break;
778
7f83a9e6
AD		 779 /* prevent any other reads prior to eop_desc */
780 rmb();
781
d3d00239
AD		 782 /* if DD is not set pending work has not been completed */
783 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
784 break;
8ad494b0 785
d3d00239
AD		 786 /* clear next_to_watch to prevent false hangs */
787 tx_buffer->next_to_watch = NULL;
8ad494b0 788
091a6246
AD		 789 /* update the statistics for this packet */
790 total_bytes += tx_buffer->bytecount;
791 total_packets += tx_buffer->gso_segs;
792
3a6a4eda 793#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 794 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
795 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 796#endif
0ede4a60 797
fd0db0ed
AD		 798 /* free the skb */
799 dev_kfree_skb_any(tx_buffer->skb);
800
729739b7
AD		 801 /* unmap skb header data */
802 dma_unmap_single(tx_ring->dev,
803 dma_unmap_addr(tx_buffer, dma),
804 dma_unmap_len(tx_buffer, len),
805 DMA_TO_DEVICE);
806
fd0db0ed
AD		 807 /* clear tx_buffer data */
808 tx_buffer->skb = NULL;
729739b7 809 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 810
729739b7
AD		 811 /* unmap remaining buffers */
812 while (tx_desc != eop_desc) {
d3d00239
AD		 813 tx_buffer++;
814 tx_desc++;
8ad494b0 815 i++;
729739b7
AD		 816 if (unlikely(!i)) {
817 i -= tx_ring->count;
d3d00239 818 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 819 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 820 }
e01c31a5 821
729739b7
AD		 822 /* unmap any remaining paged data */
823 if (dma_unmap_len(tx_buffer, len)) {
824 dma_unmap_page(tx_ring->dev,
825 dma_unmap_addr(tx_buffer, dma),
826 dma_unmap_len(tx_buffer, len),
827 DMA_TO_DEVICE);
828 dma_unmap_len_set(tx_buffer, len, 0);
829 }
830 }
831
832 /* move us one more past the eop_desc for start of next pkt */
833 tx_buffer++;
834 tx_desc++;
835 i++;
836 if (unlikely(!i)) {
837 i -= tx_ring->count;
838 tx_buffer = tx_ring->tx_buffer_info;
839 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
840 }
841
842 /* issue prefetch for next Tx descriptor */
843 prefetch(tx_desc);
12207e49 844
729739b7
AD		 845 /* update budget accounting */
846 budget--;
847 } while (likely(budget));
848
849 i += tx_ring->count;
9a799d71 850 tx_ring->next_to_clean = i;
d3d00239 851 u64_stats_update_begin(&tx_ring->syncp);
b953799e 852 tx_ring->stats.bytes += total_bytes;
bd198058 853 tx_ring->stats.packets += total_packets;
d3d00239 854 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 855 q_vector->tx.total_bytes += total_bytes;
856 q_vector->tx.total_packets += total_packets;
b953799e 857
c84d324c
JF		 858 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
859 /* schedule immediate reset if we believe we hung */
860 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 861 e_err(drv, "Detected Tx Unit Hang\n"
862 " Tx Queue <%d>\n"
863 " TDH, TDT <%x>, <%x>\n"
864 " next_to_use <%x>\n"
865 " next_to_clean <%x>\n"
866 "tx_buffer_info[next_to_clean]\n"
867 " time_stamp <%lx>\n"
868 " jiffies <%lx>\n",
869 tx_ring->queue_index,
870 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
871 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 872 tx_ring->next_to_use, i,
873 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 874
875 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
876
877 e_info(probe,
878 "tx hang %d detected on queue %d, resetting adapter\n",
879 adapter->tx_timeout_count + 1, tx_ring->queue_index);
880
b953799e 881 /* schedule immediate reset if we believe we hung */
c83c6cbd 882 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 883
884 /* the adapter is about to reset, no point in enabling stuff */
59224555 885 return true;
b953799e 886 }
9a799d71 887
b2d96e0a
AD		 888 netdev_tx_completed_queue(txring_txq(tx_ring),
889 total_packets, total_bytes);
890
e092be60 891#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 892 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 893 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 894 /* Make sure that anybody stopping the queue after this
895 * sees the new next_to_clean.
896 */
897 smp_mb();
729739b7
AD		 898 if (__netif_subqueue_stopped(tx_ring->netdev,
899 tx_ring->queue_index)
900 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
901 netif_wake_subqueue(tx_ring->netdev,
902 tx_ring->queue_index);
5b7da515 903 ++tx_ring->tx_stats.restart_queue;
30eba97a 904 }
e092be60 905 }
9a799d71 906
59224555 907 return !!budget;
9a799d71
AK		 908}
909
5dd2d332 910#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 911static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
912 struct ixgbe_ring *tx_ring,
33cf09c9 913 int cpu)
bd0362dd 914{
33cf09c9 915 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 916 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
917 u16 reg_offset;
33cf09c9 918
33cf09c9
AD		 919 switch (hw->mac.type) {
920 case ixgbe_mac_82598EB:
bdda1a61 921 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 922 break;
923 case ixgbe_mac_82599EB:
b93a2226 924 case ixgbe_mac_X540:
bdda1a61
AD		 925 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
926 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 927 break;
928 default:
bdda1a61
AD		 929 /* for unknown hardware do not write register */
930 return;
bd0362dd 931 }
bdda1a61
AD		 932
933 /*
934 * We can enable relaxed ordering for reads, but not writes when
935 * DCA is enabled. This is due to a known issue in some chipsets
936 * which will cause the DCA tag to be cleared.
937 */
938 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
939 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
940 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
941
942 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 943}
944
bdda1a61
AD		 945static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
946 struct ixgbe_ring *rx_ring,
33cf09c9 947 int cpu)
bd0362dd 948{
33cf09c9 949 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 950 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
951 u8 reg_idx = rx_ring->reg_idx;
952
33cf09c9
AD		 953
954 switch (hw->mac.type) {
33cf09c9 955 case ixgbe_mac_82599EB:
b93a2226 956 case ixgbe_mac_X540:
bdda1a61 957 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 958 break;
959 default:
960 break;
961 }
bdda1a61
AD		 962
963 /*
964 * We can enable relaxed ordering for reads, but not writes when
965 * DCA is enabled. This is due to a known issue in some chipsets
966 * which will cause the DCA tag to be cleared.
967 */
968 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
969 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
970 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
971
972 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 973}
974
975static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
976{
977 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 978 struct ixgbe_ring *ring;
bd0362dd 979 int cpu = get_cpu();
bd0362dd 980
33cf09c9
AD		 981 if (q_vector->cpu == cpu)
982 goto out_no_update;
983
a557928e 984 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 985 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 986
a557928e 987 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 988 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 989
990 q_vector->cpu = cpu;
991out_no_update:
bd0362dd
JC		 992 put_cpu();
993}
994
995static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
996{
997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
e35ec126
AD		 1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
49c7ffbe 1005 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1006 adapter->q_vector[i]->cpu = -1;
1007 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1008 }
1009}
1010
1011static int __ixgbe_notify_dca(struct device *dev, void *data)
1012{
c60fbb00 1013 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1014 unsigned long event = *(unsigned long *)data;
1015
2a72c31e 1016 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1017 return 0;
1018
bd0362dd
JC		 1019 switch (event) {
1020 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1021 /* if we're already enabled, don't do it again */
1022 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1023 break;
652f093f 1024 if (dca_add_requester(dev) == 0) {
96b0e0f6 1025 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1026 ixgbe_setup_dca(adapter);
1027 break;
1028 }
1029 /* Fall Through since DCA is disabled. */
1030 case DCA_PROVIDER_REMOVE:
1031 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1032 dca_remove_requester(dev);
1033 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1035 }
1036 break;
1037 }
1038
652f093f 1039 return 0;
bd0362dd 1040}
67a74ee2 1041
bdda1a61 1042#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1043static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1044 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1045 struct sk_buff *skb)
1046{
8a0da21b
AD		 1047 if (ring->netdev->features & NETIF_F_RXHASH)
1048 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1049}
1050
f800326d 1051#ifdef IXGBE_FCOE
ff886dfc
AD		 1052/**
1053 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1054 * @ring: structure containing ring specific data
ff886dfc
AD		 1055 * @rx_desc: advanced rx descriptor
1056 *
1057 * Returns : true if it is FCoE pkt
1058 */
57efd44c 1059static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1060 union ixgbe_adv_rx_desc *rx_desc)
1061{
1062 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1063
57efd44c 1064 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1065 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1066 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1067 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1068}
1069
f800326d 1070#endif /* IXGBE_FCOE */
e59bd25d
AV		 1071/**
1072 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1073 * @ring: structure containing ring specific data
1074 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1075 * @skb: skb currently being received and modified
1076 **/
8a0da21b 1077static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1078 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1079 struct sk_buff *skb)
9a799d71 1080{
8a0da21b 1081 skb_checksum_none_assert(skb);
9a799d71 1082
712744be 1083 /* Rx csum disabled */
8a0da21b 1084 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1085 return;
e59bd25d
AV		 1086
1087 /* if IP and error */
f56e0cb1
AD		 1088 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1089 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1090 ring->rx_stats.csum_err++;
9a799d71
AK		 1091 return;
1092 }
e59bd25d 1093
f56e0cb1 1094 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1095 return;
1096
f56e0cb1 1097 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1098 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1099
1100 /*
1101 * 82599 errata, UDP frames with a 0 checksum can be marked as
1102 * checksum errors.
1103 */
8a0da21b
AD		 1104 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1105 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1106 return;
1107
8a0da21b 1108 ring->rx_stats.csum_err++;
e59bd25d
AV		 1109 return;
1110 }
1111
9a799d71 1112 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1113 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1114}
1115
84ea2591 1116static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1117{
f56e0cb1 1118 rx_ring->next_to_use = val;
f800326d
AD		 1119
1120 /* update next to alloc since we have filled the ring */
1121 rx_ring->next_to_alloc = val;
e8e26350
PW		 1122 /*
1123 * Force memory writes to complete before letting h/w
1124 * know there are new descriptors to fetch. (Only
1125 * applicable for weak-ordered memory model archs,
1126 * such as IA-64).
1127 */
1128 wmb();
84ea2591 1129 writel(val, rx_ring->tail);
e8e26350
PW		 1130}
1131
f990b79b
AD		 1132static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1133 struct ixgbe_rx_buffer *bi)
1134{
1135 struct page *page = bi->page;
f800326d 1136 dma_addr_t dma = bi->dma;
f990b79b 1137
f800326d
AD		 1138 /* since we are recycling buffers we should seldom need to alloc */
1139 if (likely(dma))
f990b79b
AD		 1140 return true;
1141
f800326d
AD		 1142 /* alloc new page for storage */
1143 if (likely(!page)) {
0614002b
MG		 1144 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1145 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1146 if (unlikely(!page)) {
1147 rx_ring->rx_stats.alloc_rx_page_failed++;
1148 return false;
1149 }
f800326d 1150 bi->page = page;
f990b79b
AD		 1151 }
1152
f800326d
AD		 1153 /* map page for use */
1154 dma = dma_map_page(rx_ring->dev, page, 0,
1155 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1156
1157 /*
1158 * if mapping failed free memory back to system since
1159 * there isn't much point in holding memory we can't use
1160 */
1161 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1162 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1163 bi->page = NULL;
f990b79b 1164
f990b79b
AD		 1165 rx_ring->rx_stats.alloc_rx_page_failed++;
1166 return false;
1167 }
1168
f800326d 1169 bi->dma = dma;
afaa9459 1170 bi->page_offset = 0;
f800326d 1171
f990b79b
AD		 1172 return true;
1173}
1174
9a799d71 1175/**
f990b79b 1176 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1177 * @rx_ring: ring to place buffers on
1178 * @cleaned_count: number of buffers to replace
9a799d71 1179 **/
fc77dc3c 1180void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1181{
9a799d71 1182 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1183 struct ixgbe_rx_buffer *bi;
d5f398ed 1184 u16 i = rx_ring->next_to_use;
9a799d71 1185
f800326d
AD		 1186 /* nothing to do */
1187 if (!cleaned_count)
fc77dc3c
AD		 1188 return;
1189
e4f74028 1190 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1191 bi = &rx_ring->rx_buffer_info[i];
1192 i -= rx_ring->count;
9a799d71 1193
f800326d
AD		 1194 do {
1195 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1196 break;
d5f398ed 1197
f800326d
AD		 1198 /*
1199 * Refresh the desc even if buffer_addrs didn't change
1200 * because each write-back erases this info.
1201 */
1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1203
f990b79b
AD		 1204 rx_desc++;
1205 bi++;
9a799d71 1206 i++;
f990b79b 1207 if (unlikely(!i)) {
e4f74028 1208 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1209 bi = rx_ring->rx_buffer_info;
1210 i -= rx_ring->count;
1211 }
1212
1213 /* clear the hdr_addr for the next_to_use descriptor */
1214 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1215
1216 cleaned_count--;
1217 } while (cleaned_count);
7c6e0a43 1218
f990b79b
AD		 1219 i += rx_ring->count;
1220
f56e0cb1 1221 if (rx_ring->next_to_use != i)
84ea2591 1222 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1223}
1224
1d2024f6
AD		 1225/**
1226 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1227 * @data: pointer to the start of the headers
1228 * @max_len: total length of section to find headers in
1229 *
1230 * This function is meant to determine the length of headers that will
1231 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1232 * motivation of doing this is to only perform one pull for IPv4 TCP
1233 * packets so that we can do basic things like calculating the gso_size
1234 * based on the average data per packet.
1235 **/
1236static unsigned int ixgbe_get_headlen(unsigned char *data,
1237 unsigned int max_len)
1238{
1239 union {
1240 unsigned char *network;
1241 /* l2 headers */
1242 struct ethhdr *eth;
1243 struct vlan_hdr *vlan;
1244 /* l3 headers */
1245 struct iphdr *ipv4;
1246 } hdr;
1247 __be16 protocol;
1248 u8 nexthdr = 0; /* default to not TCP */
1249 u8 hlen;
1250
1251 /* this should never happen, but better safe than sorry */
1252 if (max_len < ETH_HLEN)
1253 return max_len;
1254
1255 /* initialize network frame pointer */
1256 hdr.network = data;
1257
1258 /* set first protocol and move network header forward */
1259 protocol = hdr.eth->h_proto;
1260 hdr.network += ETH_HLEN;
1261
1262 /* handle any vlan tag if present */
1263 if (protocol == __constant_htons(ETH_P_8021Q)) {
1264 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1265 return max_len;
1266
1267 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1268 hdr.network += VLAN_HLEN;
1269 }
1270
1271 /* handle L3 protocols */
1272 if (protocol == __constant_htons(ETH_P_IP)) {
1273 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1274 return max_len;
1275
1276 /* access ihl as a u8 to avoid unaligned access on ia64 */
1277 hlen = (hdr.network[0] & 0x0F) << 2;
1278
1279 /* verify hlen meets minimum size requirements */
1280 if (hlen < sizeof(struct iphdr))
1281 return hdr.network - data;
1282
1283 /* record next protocol */
1284 nexthdr = hdr.ipv4->protocol;
1285 hdr.network += hlen;
f800326d 1286#ifdef IXGBE_FCOE
1d2024f6
AD		 1287 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1288 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1289 return max_len;
1290 hdr.network += FCOE_HEADER_LEN;
1291#endif
1292 } else {
1293 return hdr.network - data;
1294 }
1295
1296 /* finally sort out TCP */
1297 if (nexthdr == IPPROTO_TCP) {
1298 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1299 return max_len;
1300
1301 /* access doff as a u8 to avoid unaligned access on ia64 */
1302 hlen = (hdr.network[12] & 0xF0) >> 2;
1303
1304 /* verify hlen meets minimum size requirements */
1305 if (hlen < sizeof(struct tcphdr))
1306 return hdr.network - data;
1307
1308 hdr.network += hlen;
1309 }
1310
1311 /*
1312 * If everything has gone correctly hdr.network should be the
1313 * data section of the packet and will be the end of the header.
1314 * If not then it probably represents the end of the last recognized
1315 * header.
1316 */
1317 if ((hdr.network - data) < max_len)
1318 return hdr.network - data;
1319 else
1320 return max_len;
1321}
1322
4c1975d7
AD		 1323static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1324 union ixgbe_adv_rx_desc *rx_desc,
1325 struct sk_buff *skb)
aa80175a 1326{
4c1975d7
AD		 1327 __le32 rsc_enabled;
1328 u32 rsc_cnt;
1329
1330 if (!ring_is_rsc_enabled(rx_ring))
1331 return;
1332
1333 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1334 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1335
1336 /* If this is an RSC frame rsc_cnt should be non-zero */
1337 if (!rsc_enabled)
1338 return;
1339
1340 rsc_cnt = le32_to_cpu(rsc_enabled);
1341 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1342
1343 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1344}
43634e82 1345
1d2024f6
AD		 1346static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1347 struct sk_buff *skb)
1348{
f800326d 1349 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1350
1351 /* set gso_size to avoid messing up TCP MSS */
1352 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1353 IXGBE_CB(skb)->append_cnt);
1354}
1355
1356static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1357 struct sk_buff *skb)
1358{
1359 /* if append_cnt is 0 then frame is not RSC */
1360 if (!IXGBE_CB(skb)->append_cnt)
1361 return;
1362
1363 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1364 rx_ring->rx_stats.rsc_flush++;
1365
1366 ixgbe_set_rsc_gso_size(rx_ring, skb);
1367
1368 /* gso_size is computed using append_cnt so always clear it last */
1369 IXGBE_CB(skb)->append_cnt = 0;
1370}
1371
8a0da21b
AD		 1372/**
1373 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1374 * @rx_ring: rx descriptor ring packet is being transacted on
1375 * @rx_desc: pointer to the EOP Rx descriptor
1376 * @skb: pointer to current skb being populated
f8212f97 1377 *
8a0da21b
AD		 1378 * This function checks the ring, descriptor, and packet information in
1379 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1380 * other fields within the skb.
f8212f97 1381 **/
8a0da21b
AD		 1382static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1383 union ixgbe_adv_rx_desc *rx_desc,
1384 struct sk_buff *skb)
f8212f97 1385{
43e95f11
JF		 1386 struct net_device *dev = rx_ring->netdev;
1387
8a0da21b
AD		 1388 ixgbe_update_rsc_stats(rx_ring, skb);
1389
1390 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1391
8a0da21b
AD		 1392 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1393
3a6a4eda 1394#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1395 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1396#endif
1397
43e95f11
JF		 1398 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1399 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1400 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1401 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1402 }
1403
8a0da21b 1404 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1405
43e95f11 1406 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1407}
1408
8a0da21b
AD		 1409static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1410 struct sk_buff *skb)
aa80175a 1411{
8a0da21b
AD		 1412 struct ixgbe_adapter *adapter = q_vector->adapter;
1413
1414 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1415 napi_gro_receive(&q_vector->napi, skb);
1416 else
1417 netif_rx(skb);
aa80175a 1418}
43634e82 1419
f800326d
AD		 1420/**
1421 * ixgbe_is_non_eop - process handling of non-EOP buffers
1422 * @rx_ring: Rx ring being processed
1423 * @rx_desc: Rx descriptor for current buffer
1424 * @skb: Current socket buffer containing buffer in progress
1425 *
1426 * This function updates next to clean. If the buffer is an EOP buffer
1427 * this function exits returning false, otherwise it will place the
1428 * sk_buff in the next buffer to be chained and return true indicating
1429 * that this is in fact a non-EOP buffer.
1430 **/
1431static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1432 union ixgbe_adv_rx_desc *rx_desc,
1433 struct sk_buff *skb)
1434{
1435 u32 ntc = rx_ring->next_to_clean + 1;
1436
1437 /* fetch, update, and store next to clean */
1438 ntc = (ntc < rx_ring->count) ? ntc : 0;
1439 rx_ring->next_to_clean = ntc;
1440
1441 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1442
1443 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1444 return false;
1445
1446 /* append_cnt indicates packet is RSC, if so fetch nextp */
1447 if (IXGBE_CB(skb)->append_cnt) {
1448 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1449 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1450 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1451 }
1452
1453 /* place skb in next buffer to be received */
1454 rx_ring->rx_buffer_info[ntc].skb = skb;
1455 rx_ring->rx_stats.non_eop_descs++;
1456
1457 return true;
1458}
1459
19861ce2
AD		 1460/**
1461 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1462 * @rx_ring: rx descriptor ring packet is being transacted on
1463 * @skb: pointer to current skb being adjusted
1464 *
1465 * This function is an ixgbe specific version of __pskb_pull_tail. The
1466 * main difference between this version and the original function is that
1467 * this function can make several assumptions about the state of things
1468 * that allow for significant optimizations versus the standard function.
1469 * As a result we can do things like drop a frag and maintain an accurate
1470 * truesize for the skb.
1471 */
1472static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1473 struct sk_buff *skb)
1474{
1475 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1476 unsigned char *va;
1477 unsigned int pull_len;
1478
1479 /*
1480 * it is valid to use page_address instead of kmap since we are
1481 * working with pages allocated out of the lomem pool per
1482 * alloc_page(GFP_ATOMIC)
1483 */
1484 va = skb_frag_address(frag);
1485
1486 /*
1487 * we need the header to contain the greater of either ETH_HLEN or
1488 * 60 bytes if the skb->len is less than 60 for skb_pad.
1489 */
cf3fe7ac 1490 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1491
1492 /* align pull length to size of long to optimize memcpy performance */
1493 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1494
1495 /* update all of the pointers */
1496 skb_frag_size_sub(frag, pull_len);
1497 frag->page_offset += pull_len;
1498 skb->data_len -= pull_len;
1499 skb->tail += pull_len;
19861ce2
AD		 1500}
1501
42073d91
AD		 1502/**
1503 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1504 * @rx_ring: rx descriptor ring packet is being transacted on
1505 * @skb: pointer to current skb being updated
1506 *
1507 * This function provides a basic DMA sync up for the first fragment of an
1508 * skb. The reason for doing this is that the first fragment cannot be
1509 * unmapped until we have reached the end of packet descriptor for a buffer
1510 * chain.
1511 */
1512static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1513 struct sk_buff *skb)
1514{
1515 /* if the page was released unmap it, else just sync our portion */
1516 if (unlikely(IXGBE_CB(skb)->page_released)) {
1517 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1518 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1519 IXGBE_CB(skb)->page_released = false;
1520 } else {
1521 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1522
1523 dma_sync_single_range_for_cpu(rx_ring->dev,
1524 IXGBE_CB(skb)->dma,
1525 frag->page_offset,
1526 ixgbe_rx_bufsz(rx_ring),
1527 DMA_FROM_DEVICE);
1528 }
1529 IXGBE_CB(skb)->dma = 0;
1530}
1531
f800326d
AD		 1532/**
1533 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1534 * @rx_ring: rx descriptor ring packet is being transacted on
1535 * @rx_desc: pointer to the EOP Rx descriptor
1536 * @skb: pointer to current skb being fixed
1537 *
1538 * Check for corrupted packet headers caused by senders on the local L2
1539 * embedded NIC switch not setting up their Tx Descriptors right. These
1540 * should be very rare.
1541 *
1542 * Also address the case where we are pulling data in on pages only
1543 * and as such no data is present in the skb header.
1544 *
1545 * In addition if skb is not at least 60 bytes we need to pad it so that
1546 * it is large enough to qualify as a valid Ethernet frame.
1547 *
1548 * Returns true if an error was encountered and skb was freed.
1549 **/
1550static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1551 union ixgbe_adv_rx_desc *rx_desc,
1552 struct sk_buff *skb)
1553{
f800326d 1554 struct net_device *netdev = rx_ring->netdev;
f800326d 1555
f800326d
AD		 1556 /* verify that the packet does not have any known errors */
1557 if (unlikely(ixgbe_test_staterr(rx_desc,
1558 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1559 !(netdev->features & NETIF_F_RXALL))) {
1560 dev_kfree_skb_any(skb);
1561 return true;
1562 }
1563
19861ce2 1564 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1565 if (skb_is_nonlinear(skb))
1566 ixgbe_pull_tail(rx_ring, skb);
f800326d 1567
57efd44c
AD		 1568#ifdef IXGBE_FCOE
1569 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1570 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1571 return false;
1572
1573#endif
f800326d
AD		 1574 /* if skb_pad returns an error the skb was freed */
1575 if (unlikely(skb->len < 60)) {
1576 int pad_len = 60 - skb->len;
1577
1578 if (skb_pad(skb, pad_len))
1579 return true;
1580 __skb_put(skb, pad_len);
1581 }
1582
1583 return false;
1584}
1585
f800326d
AD		 1586/**
1587 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1588 * @rx_ring: rx descriptor ring to store buffers on
1589 * @old_buff: donor buffer to have page reused
1590 *
0549ae20 1591 * Synchronizes page for reuse by the adapter
f800326d
AD		 1592 **/
1593static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1594 struct ixgbe_rx_buffer *old_buff)
1595{
1596 struct ixgbe_rx_buffer *new_buff;
1597 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1598
1599 new_buff = &rx_ring->rx_buffer_info[nta];
1600
1601 /* update, and store next to alloc */
1602 nta++;
1603 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1604
1605 /* transfer page from old buffer to new buffer */
1606 new_buff->page = old_buff->page;
1607 new_buff->dma = old_buff->dma;
0549ae20 1608 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1609
1610 /* sync the buffer for use by the device */
1611 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1612 new_buff->page_offset,
1613 ixgbe_rx_bufsz(rx_ring),
f800326d 1614 DMA_FROM_DEVICE);
f800326d
AD		 1615}
1616
1617/**
1618 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1619 * @rx_ring: rx descriptor ring to transact packets on
1620 * @rx_buffer: buffer containing page to add
1621 * @rx_desc: descriptor containing length of buffer written by hardware
1622 * @skb: sk_buff to place the data into
1623 *
0549ae20
AD		 1624 * This function will add the data contained in rx_buffer->page to the skb.
1625 * This is done either through a direct copy if the data in the buffer is
1626 * less than the skb header size, otherwise it will just attach the page as
1627 * a frag to the skb.
1628 *
1629 * The function will then update the page offset if necessary and return
1630 * true if the buffer can be reused by the adapter.
f800326d 1631 **/
0549ae20 1632static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1633 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1634 union ixgbe_adv_rx_desc *rx_desc,
1635 struct sk_buff *skb)
f800326d 1636{
0549ae20
AD		 1637 struct page *page = rx_buffer->page;
1638 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1639#if (PAGE_SIZE < 8192)
0549ae20 1640 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1641#else
1642 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1643 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1644 ixgbe_rx_bufsz(rx_ring);
1645#endif
0549ae20 1646
cf3fe7ac
AD		 1647 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1648 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1649
1650 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1651
1652 /* we can reuse buffer as-is, just make sure it is local */
1653 if (likely(page_to_nid(page) == numa_node_id()))
1654 return true;
1655
1656 /* this page cannot be reused so discard it */
1657 put_page(page);
1658 return false;
1659 }
1660
0549ae20
AD		 1661 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1662 rx_buffer->page_offset, size, truesize);
1663
09816fbe
AD		 1664 /* avoid re-using remote pages */
1665 if (unlikely(page_to_nid(page) != numa_node_id()))
1666 return false;
1667
1668#if (PAGE_SIZE < 8192)
1669 /* if we are only owner of page we can reuse it */
1670 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1671 return false;
1672
1673 /* flip page offset to other buffer */
1674 rx_buffer->page_offset ^= truesize;
1675
09816fbe
AD		 1676 /*
1677 * since we are the only owner of the page and we need to
1678 * increment it, just set the value to 2 in order to avoid
1679 * an unecessary locked operation
1680 */
1681 atomic_set(&page->_count, 2);
1682#else
1683 /* move offset up to the next cache line */
1684 rx_buffer->page_offset += truesize;
1685
1686 if (rx_buffer->page_offset > last_offset)
1687 return false;
1688
0549ae20
AD		 1689 /* bump ref count on page before it is given to the stack */
1690 get_page(page);
09816fbe 1691#endif
0549ae20
AD		 1692
1693 return true;
f800326d
AD		 1694}
1695
1696/**
1697 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1698 * @q_vector: structure containing interrupt and ring information
1699 * @rx_ring: rx descriptor ring to transact packets on
1700 * @budget: Total limit on number of packets to process
1701 *
1702 * This function provides a "bounce buffer" approach to Rx interrupt
1703 * processing. The advantage to this is that on systems that have
1704 * expensive overhead for IOMMU access this provides a means of avoiding
1705 * it by maintaining the mapping of the page to the syste.
1706 *
1707 * Returns true if all work is completed without reaching budget
1708 **/
4ff7fb12 1709static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1710 struct ixgbe_ring *rx_ring,
4ff7fb12 1711 int budget)
9a799d71 1712{
d2f4fbe2 1713 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1714#ifdef IXGBE_FCOE
f800326d 1715 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1716 int ddp_bytes = 0;
1717#endif /* IXGBE_FCOE */
f800326d 1718 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1719
f800326d
AD		 1720 do {
1721 struct ixgbe_rx_buffer *rx_buffer;
1722 union ixgbe_adv_rx_desc *rx_desc;
1723 struct sk_buff *skb;
1724 struct page *page;
1725 u16 ntc;
1726
1727 /* return some buffers to hardware, one at a time is too slow */
1728 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1729 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1730 cleaned_count = 0;
1731 }
1732
1733 ntc = rx_ring->next_to_clean;
1734 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1735 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1736
1737 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1738 break;
9a799d71 1739
f800326d
AD		 1740 /*
1741 * This memory barrier is needed to keep us from reading
1742 * any other fields out of the rx_desc until we know the
1743 * RXD_STAT_DD bit is set
1744 */
1745 rmb();
9a799d71 1746
f800326d
AD		 1747 page = rx_buffer->page;
1748 prefetchw(page);
9a799d71 1749
f800326d 1750 skb = rx_buffer->skb;
c267fc16 1751
f800326d
AD		 1752 if (likely(!skb)) {
1753 void *page_addr = page_address(page) +
1754 rx_buffer->page_offset;
9a799d71 1755
f800326d
AD		 1756 /* prefetch first cache line of first page */
1757 prefetch(page_addr);
1758#if L1_CACHE_BYTES < 128
1759 prefetch(page_addr + L1_CACHE_BYTES);
1760#endif
1761
1762 /* allocate a skb to store the frags */
1763 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1764 IXGBE_RX_HDR_SIZE);
1765 if (unlikely(!skb)) {
1766 rx_ring->rx_stats.alloc_rx_buff_failed++;
1767 break;
c267fc16
AD		 1768 }
1769
f800326d
AD		 1770 /*
1771 * we will be copying header into skb->data in
1772 * pskb_may_pull so it is in our interest to prefetch
1773 * it now to avoid a possible cache miss
1774 */
1775 prefetchw(skb->data);
4c1975d7
AD		 1776
1777 /*
1778 * Delay unmapping of the first packet. It carries the
1779 * header information, HW may still access the header
f800326d
AD		 1780 * after the writeback. Only unmap it when EOP is
1781 * reached
4c1975d7 1782 */
42073d91
AD		 1783 if (likely(ixgbe_test_staterr(rx_desc,
1784 IXGBE_RXD_STAT_EOP)))
1785 goto dma_sync;
1786
f800326d 1787 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1788 } else {
42073d91
AD		 1789 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1790 ixgbe_dma_sync_frag(rx_ring, skb);
1791
1792dma_sync:
f800326d
AD		 1793 /* we are reusing so sync this buffer for CPU use */
1794 dma_sync_single_range_for_cpu(rx_ring->dev,
1795 rx_buffer->dma,
1796 rx_buffer->page_offset,
1797 ixgbe_rx_bufsz(rx_ring),
1798 DMA_FROM_DEVICE);
9a799d71
AK		 1799 }
1800
f800326d 1801 /* pull page into skb */
0549ae20 1802 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
f800326d
AD		 1803 /* hand second half of page back to the ring */
1804 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1805 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1806 /* the page has been released from the ring */
1807 IXGBE_CB(skb)->page_released = true;
1808 } else {
1809 /* we are not reusing the buffer so unmap it */
1810 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1811 ixgbe_rx_pg_size(rx_ring),
1812 DMA_FROM_DEVICE);
9a799d71
AK		 1813 }
1814
f800326d
AD		 1815 /* clear contents of buffer_info */
1816 rx_buffer->skb = NULL;
1817 rx_buffer->dma = 0;
1818 rx_buffer->page = NULL;
4c1975d7 1819
f800326d 1820 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1821
9a799d71 1822 cleaned_count++;
f8212f97 1823
f800326d
AD		 1824 /* place incomplete frames back on ring for completion */
1825 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1826 continue;
c267fc16 1827
f800326d
AD		 1828 /* verify the packet layout is correct */
1829 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1830 continue;
9a799d71 1831
d2f4fbe2
AV		 1832 /* probably a little skewed due to removing CRC */
1833 total_rx_bytes += skb->len;
1834 total_rx_packets++;
1835
8a0da21b
AD		 1836 /* populate checksum, timestamp, VLAN, and protocol */
1837 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1838
332d4a7d
YZ		 1839#ifdef IXGBE_FCOE
1840 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1841 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1842 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1843 if (!ddp_bytes) {
1844 dev_kfree_skb_any(skb);
f800326d 1845 continue;
63d635b2 1846 }
3d8fd385 1847 }
f800326d 1848
332d4a7d 1849#endif /* IXGBE_FCOE */
8a0da21b 1850 ixgbe_rx_skb(q_vector, skb);
9a799d71 1851
f800326d 1852 /* update budget accounting */
4ff7fb12 1853 budget--;
f800326d 1854 } while (likely(budget));
9a799d71 1855
3d8fd385
YZ		 1856#ifdef IXGBE_FCOE
1857 /* include DDPed FCoE data */
1858 if (ddp_bytes > 0) {
1859 unsigned int mss;
1860
fc77dc3c 1861 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1862 sizeof(struct fc_frame_header) -
1863 sizeof(struct fcoe_crc_eof);
1864 if (mss > 512)
1865 mss &= ~511;
1866 total_rx_bytes += ddp_bytes;
1867 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1868 }
3d8fd385 1869
f800326d 1870#endif /* IXGBE_FCOE */
c267fc16
AD		 1871 u64_stats_update_begin(&rx_ring->syncp);
1872 rx_ring->stats.packets += total_rx_packets;
1873 rx_ring->stats.bytes += total_rx_bytes;
1874 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1875 q_vector->rx.total_packets += total_rx_packets;
1876 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1877
f800326d
AD		 1878 if (cleaned_count)
1879 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1880
4ff7fb12 1881 return !!budget;
9a799d71
AK		 1882}
1883
9a799d71
AK		 1884/**
1885 * ixgbe_configure_msix - Configure MSI-X hardware
1886 * @adapter: board private structure
1887 *
1888 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1889 * interrupts.
1890 **/
1891static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1892{
021230d4 1893 struct ixgbe_q_vector *q_vector;
49c7ffbe 1894 int v_idx;
021230d4 1895 u32 mask;
9a799d71 1896
8e34d1aa
AD		 1897 /* Populate MSIX to EITR Select */
1898 if (adapter->num_vfs > 32) {
1899 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1901 }
1902
4df10466
JB		 1903 /*
1904 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1905 * corresponding register.
1906 */
49c7ffbe 1907 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1908 struct ixgbe_ring *ring;
7a921c93 1909 q_vector = adapter->q_vector[v_idx];
021230d4 1910
a557928e 1911 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1912 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1913
a557928e 1914 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1915 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1916
d5bf4f67
ET		 1917 if (q_vector->tx.ring && !q_vector->rx.ring) {
1918 /* tx only vector */
1919 if (adapter->tx_itr_setting == 1)
1920 q_vector->itr = IXGBE_10K_ITR;
1921 else
1922 q_vector->itr = adapter->tx_itr_setting;
1923 } else {
1924 /* rx or rx/tx vector */
1925 if (adapter->rx_itr_setting == 1)
1926 q_vector->itr = IXGBE_20K_ITR;
1927 else
1928 q_vector->itr = adapter->rx_itr_setting;
1929 }
021230d4 1930
fe49f04a 1931 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1932 }
1933
bd508178
AD		 1934 switch (adapter->hw.mac.type) {
1935 case ixgbe_mac_82598EB:
e8e26350 1936 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1937 v_idx);
bd508178
AD		 1938 break;
1939 case ixgbe_mac_82599EB:
b93a2226 1940 case ixgbe_mac_X540:
e8e26350 1941 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1942 break;
bd508178
AD		 1943 default:
1944 break;
1945 }
021230d4
AV		 1946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1947
41fb9248 1948 /* set up to autoclear timer, and the vectors */
021230d4 1949 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1950 mask &= ~(IXGBE_EIMS_OTHER |
1951 IXGBE_EIMS_MAILBOX |
1952 IXGBE_EIMS_LSC);
1953
021230d4 1954 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1955}
1956
f494e8fa
AV		 1957enum latency_range {
1958 lowest_latency = 0,
1959 low_latency = 1,
1960 bulk_latency = 2,
1961 latency_invalid = 255
1962};
1963
1964/**
1965 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1966 * @q_vector: structure containing interrupt and ring information
1967 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1968 *
1969 * Stores a new ITR value based on packets and byte
1970 * counts during the last interrupt. The advantage of per interrupt
1971 * computation is faster updates and more accurate ITR for the current
1972 * traffic pattern. Constants in this function were computed
1973 * based on theoretical maximum wire speed and thresholds were set based
1974 * on testing data as well as attempting to minimize response time
1975 * while increasing bulk throughput.
1976 * this functionality is controlled by the InterruptThrottleRate module
1977 * parameter (see ixgbe_param.c)
1978 **/
bd198058
AD		 1979static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1980 struct ixgbe_ring_container *ring_container)
f494e8fa 1981{
bd198058
AD		 1982 int bytes = ring_container->total_bytes;
1983 int packets = ring_container->total_packets;
1984 u32 timepassed_us;
621bd70e 1985 u64 bytes_perint;
bd198058 1986 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1987
1988 if (packets == 0)
bd198058 1989 return;
f494e8fa
AV		 1990
1991 /* simple throttlerate management
621bd70e
AD		 1992 * 0-10MB/s lowest (100000 ints/s)
1993 * 10-20MB/s low (20000 ints/s)
1994 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1995 */
1996 /* what was last interrupt timeslice? */
d5bf4f67 1997 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1998 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1999
2000 switch (itr_setting) {
2001 case lowest_latency:
621bd70e 2002 if (bytes_perint > 10)
bd198058 2003 itr_setting = low_latency;
f494e8fa
AV		 2004 break;
2005 case low_latency:
621bd70e 2006 if (bytes_perint > 20)
bd198058 2007 itr_setting = bulk_latency;
621bd70e 2008 else if (bytes_perint <= 10)
bd198058 2009 itr_setting = lowest_latency;
f494e8fa
AV		 2010 break;
2011 case bulk_latency:
621bd70e 2012 if (bytes_perint <= 20)
bd198058 2013 itr_setting = low_latency;
f494e8fa
AV		 2014 break;
2015 }
2016
bd198058
AD		 2017 /* clear work counters since we have the values we need */
2018 ring_container->total_bytes = 0;
2019 ring_container->total_packets = 0;
2020
2021 /* write updated itr to ring container */
2022 ring_container->itr = itr_setting;
f494e8fa
AV		 2023}
2024
509ee935
JB		 2025/**
2026 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2027 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2028 *
2029 * This function is made to be called by ethtool and by the driver
2030 * when it needs to update EITR registers at runtime. Hardware
2031 * specific quirks/differences are taken care of here.
2032 */
fe49f04a 2033void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2034{
fe49f04a 2035 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2036 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2037 int v_idx = q_vector->v_idx;
5d967eb7 2038 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2039
bd508178
AD		 2040 switch (adapter->hw.mac.type) {
2041 case ixgbe_mac_82598EB:
509ee935
JB		 2042 /* must write high and low 16 bits to reset counter */
2043 itr_reg |= (itr_reg << 16);
bd508178
AD		 2044 break;
2045 case ixgbe_mac_82599EB:
b93a2226 2046 case ixgbe_mac_X540:
509ee935
JB		 2047 /*
2048 * set the WDIS bit to not clear the timer bits and cause an
2049 * immediate assertion of the interrupt
2050 */
2051 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2052 break;
2053 default:
2054 break;
509ee935
JB		 2055 }
2056 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2057}
2058
bd198058 2059static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2060{
d5bf4f67 2061 u32 new_itr = q_vector->itr;
bd198058 2062 u8 current_itr;
f494e8fa 2063
bd198058
AD		 2064 ixgbe_update_itr(q_vector, &q_vector->tx);
2065 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2066
08c8833b 2067 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2068
2069 switch (current_itr) {
2070 /* counts and packets in update_itr are dependent on these numbers */
2071 case lowest_latency:
d5bf4f67 2072 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2073 break;
2074 case low_latency:
d5bf4f67 2075 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2076 break;
2077 case bulk_latency:
d5bf4f67 2078 new_itr = IXGBE_8K_ITR;
f494e8fa 2079 break;
bd198058
AD		 2080 default:
2081 break;
f494e8fa
AV		 2082 }
2083
d5bf4f67 2084 if (new_itr != q_vector->itr) {
fe49f04a 2085 /* do an exponential smoothing */
d5bf4f67
ET		 2086 new_itr = (10 * new_itr * q_vector->itr) /
2087 ((9 * new_itr) + q_vector->itr);
509ee935 2088
bd198058 2089 /* save the algorithm value here */
5d967eb7 2090 q_vector->itr = new_itr;
fe49f04a
AD		 2091
2092 ixgbe_write_eitr(q_vector);
f494e8fa 2093 }
f494e8fa
AV		 2094}
2095
119fc60a 2096/**
de88eeeb 2097 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2098 * @adapter: pointer to adapter
119fc60a 2099 **/
f0f9778d 2100static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2101{
119fc60a
MC		 2102 struct ixgbe_hw *hw = &adapter->hw;
2103 u32 eicr = adapter->interrupt_event;
2104
f0f9778d 2105 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2106 return;
2107
f0f9778d
AD		 2108 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2109 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2110 return;
2111
2112 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2113
7ca647bd 2114 switch (hw->device_id) {
f0f9778d
AD		 2115 case IXGBE_DEV_ID_82599_T3_LOM:
2116 /*
2117 * Since the warning interrupt is for both ports
2118 * we don't have to check if:
2119 * - This interrupt wasn't for our port.
2120 * - We may have missed the interrupt so always have to
2121 * check if we got a LSC
2122 */
2123 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2124 !(eicr & IXGBE_EICR_LSC))
2125 return;
2126
2127 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2128 u32 autoneg;
2129 bool link_up = false;
7ca647bd 2130
7ca647bd
JP		 2131 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2132
f0f9778d
AD		 2133 if (link_up)
2134 return;
2135 }
2136
2137 /* Check if this is not due to overtemp */
2138 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2139 return;
2140
2141 break;
7ca647bd
JP		 2142 default:
2143 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2144 return;
7ca647bd 2145 break;
119fc60a 2146 }
7ca647bd
JP		 2147 e_crit(drv,
2148 "Network adapter has been stopped because it has over heated. "
2149 "Restart the computer. If the problem persists, "
2150 "power off the system and replace the adapter\n");
f0f9778d
AD		 2151
2152 adapter->interrupt_event = 0;
119fc60a
MC		 2153}
2154
0befdb3e
JB		 2155static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2156{
2157 struct ixgbe_hw *hw = &adapter->hw;
2158
2159 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2160 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2161 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2162 /* write to clear the interrupt */
2163 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2164 }
2165}
cf8280ee 2166
4f51bf70
JK		 2167static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2168{
2169 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2170 return;
2171
2172 switch (adapter->hw.mac.type) {
2173 case ixgbe_mac_82599EB:
2174 /*
2175 * Need to check link state so complete overtemp check
2176 * on service task
2177 */
2178 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2179 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2180 adapter->interrupt_event = eicr;
2181 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2182 ixgbe_service_event_schedule(adapter);
2183 return;
2184 }
2185 return;
2186 case ixgbe_mac_X540:
2187 if (!(eicr & IXGBE_EICR_TS))
2188 return;
2189 break;
2190 default:
2191 return;
2192 }
2193
2194 e_crit(drv,
2195 "Network adapter has been stopped because it has over heated. "
2196 "Restart the computer. If the problem persists, "
2197 "power off the system and replace the adapter\n");
2198}
2199
e8e26350
PW		 2200static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2201{
2202 struct ixgbe_hw *hw = &adapter->hw;
2203
73c4b7cd
AD		 2204 if (eicr & IXGBE_EICR_GPI_SDP2) {
2205 /* Clear the interrupt */
2206 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2207 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2208 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2209 ixgbe_service_event_schedule(adapter);
2210 }
73c4b7cd
AD		 2211 }
2212
e8e26350
PW		 2213 if (eicr & IXGBE_EICR_GPI_SDP1) {
2214 /* Clear the interrupt */
2215 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2216 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2217 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2218 ixgbe_service_event_schedule(adapter);
2219 }
e8e26350
PW		 2220 }
2221}
2222
cf8280ee
JB		 2223static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2224{
2225 struct ixgbe_hw *hw = &adapter->hw;
2226
2227 adapter->lsc_int++;
2228 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2229 adapter->link_check_timeout = jiffies;
2230 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2231 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2232 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2233 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2234 }
2235}
2236
fe49f04a
AD		 2237static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2238 u64 qmask)
2239{
2240 u32 mask;
bd508178 2241 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2242
bd508178
AD		 2243 switch (hw->mac.type) {
2244 case ixgbe_mac_82598EB:
fe49f04a 2245 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2246 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2247 break;
2248 case ixgbe_mac_82599EB:
b93a2226 2249 case ixgbe_mac_X540:
fe49f04a 2250 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2251 if (mask)
2252 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2253 mask = (qmask >> 32);
bd508178
AD		 2254 if (mask)
2255 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2256 break;
2257 default:
2258 break;
fe49f04a
AD		 2259 }
2260 /* skip the flush */
2261}
2262
2263static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2264 u64 qmask)
fe49f04a
AD		 2265{
2266 u32 mask;
bd508178 2267 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2268
bd508178
AD		 2269 switch (hw->mac.type) {
2270 case ixgbe_mac_82598EB:
fe49f04a 2271 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2272 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2273 break;
2274 case ixgbe_mac_82599EB:
b93a2226 2275 case ixgbe_mac_X540:
fe49f04a 2276 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2277 if (mask)
2278 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2279 mask = (qmask >> 32);
bd508178
AD		 2280 if (mask)
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2282 break;
2283 default:
2284 break;
fe49f04a
AD		 2285 }
2286 /* skip the flush */
2287}
2288
021230d4 2289/**
2c4af694
AD		 2290 * ixgbe_irq_enable - Enable default interrupt generation settings
2291 * @adapter: board private structure
021230d4 2292 **/
2c4af694
AD		 2293static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2294 bool flush)
9a799d71 2295{
2c4af694 2296 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2297
2c4af694
AD		 2298 /* don't reenable LSC while waiting for link */
2299 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2300 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2301
2c4af694 2302 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2303 switch (adapter->hw.mac.type) {
2304 case ixgbe_mac_82599EB:
2305 mask |= IXGBE_EIMS_GPI_SDP0;
2306 break;
2307 case ixgbe_mac_X540:
2308 mask |= IXGBE_EIMS_TS;
2309 break;
2310 default:
2311 break;
2312 }
2c4af694
AD		 2313 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2314 mask |= IXGBE_EIMS_GPI_SDP1;
2315 switch (adapter->hw.mac.type) {
2316 case ixgbe_mac_82599EB:
2c4af694
AD		 2317 mask |= IXGBE_EIMS_GPI_SDP1;
2318 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2319 case ixgbe_mac_X540:
2320 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2321 mask |= IXGBE_EIMS_MAILBOX;
2322 break;
2323 default:
2324 break;
9a799d71 2325 }
2c4af694
AD		 2326 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2327 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2328 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2329
2c4af694
AD		 2330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2331 if (queues)
2332 ixgbe_irq_enable_queues(adapter, ~0);
2333 if (flush)
2334 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2335}
2336
2c4af694 2337static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2338{
a65151ba 2339 struct ixgbe_adapter *adapter = data;
9a799d71 2340 struct ixgbe_hw *hw = &adapter->hw;
54037505 2341 u32 eicr;
91281fd3 2342
54037505
DS		 2343 /*
2344 * Workaround for Silicon errata. Use clear-by-write instead
2345 * of clear-by-read. Reading with EICS will return the
2346 * interrupt causes without clearing, which later be done
2347 * with the write to EICR.
2348 */
2349 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2350 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2351
cf8280ee
JB		 2352 if (eicr & IXGBE_EICR_LSC)
2353 ixgbe_check_lsc(adapter);
f0848276 2354
1cdd1ec8
GR		 2355 if (eicr & IXGBE_EICR_MAILBOX)
2356 ixgbe_msg_task(adapter);
efe3d3c8 2357
bd508178
AD		 2358 switch (hw->mac.type) {
2359 case ixgbe_mac_82599EB:
b93a2226 2360 case ixgbe_mac_X540:
2c4af694
AD		 2361 if (eicr & IXGBE_EICR_ECC)
2362 e_info(link, "Received unrecoverable ECC Err, please "
2363 "reboot\n");
c4cf55e5
PWJ		 2364 /* Handle Flow Director Full threshold interrupt */
2365 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2366 int reinit_count = 0;
c4cf55e5 2367 int i;
c4cf55e5 2368 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2369 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2370 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2371 &ring->state))
2372 reinit_count++;
2373 }
2374 if (reinit_count) {
2375 /* no more flow director interrupts until after init */
2376 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2377 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2378 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2379 }
2380 }
f0f9778d 2381 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2382 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2383 break;
2384 default:
2385 break;
c4cf55e5 2386 }
f0848276 2387
bd508178 2388 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2389#ifdef CONFIG_IXGBE_PTP
2390 ixgbe_ptp_check_pps_event(adapter, eicr);
2391#endif
efe3d3c8 2392
7086400d 2393 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2394 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2395 ixgbe_irq_enable(adapter, false, false);
f0848276 2396
9a799d71 2397 return IRQ_HANDLED;
f0848276 2398}
91281fd3 2399
4ff7fb12 2400static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2401{
021230d4 2402 struct ixgbe_q_vector *q_vector = data;
91281fd3 2403
9b471446 2404 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2405
4ff7fb12
AD		 2406 if (q_vector->rx.ring || q_vector->tx.ring)
2407 napi_schedule(&q_vector->napi);
91281fd3 2408
9a799d71 2409 return IRQ_HANDLED;
91281fd3
AD		 2410}
2411
eb01b975
AD		 2412/**
2413 * ixgbe_poll - NAPI Rx polling callback
2414 * @napi: structure for representing this polling device
2415 * @budget: how many packets driver is allowed to clean
2416 *
2417 * This function is used for legacy and MSI, NAPI mode
2418 **/
8af3c33f 2419int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2420{
2421 struct ixgbe_q_vector *q_vector =
2422 container_of(napi, struct ixgbe_q_vector, napi);
2423 struct ixgbe_adapter *adapter = q_vector->adapter;
2424 struct ixgbe_ring *ring;
2425 int per_ring_budget;
2426 bool clean_complete = true;
2427
2428#ifdef CONFIG_IXGBE_DCA
2429 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2430 ixgbe_update_dca(q_vector);
2431#endif
2432
2433 ixgbe_for_each_ring(ring, q_vector->tx)
2434 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2435
2436 /* attempt to distribute budget to each queue fairly, but don't allow
2437 * the budget to go below 1 because we'll exit polling */
2438 if (q_vector->rx.count > 1)
2439 per_ring_budget = max(budget/q_vector->rx.count, 1);
2440 else
2441 per_ring_budget = budget;
2442
2443 ixgbe_for_each_ring(ring, q_vector->rx)
2444 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2445 per_ring_budget);
2446
2447 /* If all work not completed, return budget and keep polling */
2448 if (!clean_complete)
2449 return budget;
2450
2451 /* all work done, exit the polling mode */
2452 napi_complete(napi);
2453 if (adapter->rx_itr_setting & 1)
2454 ixgbe_set_itr(q_vector);
2455 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2456 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2457
2458 return 0;
2459}
2460
021230d4
AV		 2461/**
2462 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2463 * @adapter: board private structure
2464 *
2465 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2466 * interrupts from the kernel.
2467 **/
2468static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2469{
2470 struct net_device *netdev = adapter->netdev;
207867f5 2471 int vector, err;
e8e9f696 2472 int ri = 0, ti = 0;
021230d4 2473
49c7ffbe 2474 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2475 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2476 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2477
4ff7fb12 2478 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2479 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2480 "%s-%s-%d", netdev->name, "TxRx", ri++);
2481 ti++;
2482 } else if (q_vector->rx.ring) {
9fe93afd 2483 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2484 "%s-%s-%d", netdev->name, "rx", ri++);
2485 } else if (q_vector->tx.ring) {
9fe93afd 2486 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2487 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2488 } else {
2489 /* skip this unused q_vector */
2490 continue;
32aa77a4 2491 }
207867f5
AD		 2492 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2493 q_vector->name, q_vector);
9a799d71 2494 if (err) {
396e799c 2495 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2496 "Error: %d\n", err);
021230d4 2497 goto free_queue_irqs;
9a799d71 2498 }
207867f5
AD		 2499 /* If Flow Director is enabled, set interrupt affinity */
2500 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2501 /* assign the mask for this irq */
2502 irq_set_affinity_hint(entry->vector,
de88eeeb 2503 &q_vector->affinity_mask);
207867f5 2504 }
9a799d71
AK		 2505 }
2506
021230d4 2507 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2508 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2509 if (err) {
de88eeeb 2510 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2511 goto free_queue_irqs;
9a799d71
AK		 2512 }
2513
9a799d71
AK		 2514 return 0;
2515
021230d4 2516free_queue_irqs:
207867f5
AD		 2517 while (vector) {
2518 vector--;
2519 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2520 NULL);
2521 free_irq(adapter->msix_entries[vector].vector,
2522 adapter->q_vector[vector]);
2523 }
021230d4
AV		 2524 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2525 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2526 kfree(adapter->msix_entries);
2527 adapter->msix_entries = NULL;
9a799d71
AK		 2528 return err;
2529}
2530
2531/**
021230d4 2532 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2533 * @irq: interrupt number
2534 * @data: pointer to a network interface device structure
9a799d71
AK		 2535 **/
2536static irqreturn_t ixgbe_intr(int irq, void *data)
2537{
a65151ba 2538 struct ixgbe_adapter *adapter = data;
9a799d71 2539 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2540 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2541 u32 eicr;
2542
54037505 2543 /*
24ddd967 2544 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2545 * before the read of EICR.
2546 */
2547 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2548
021230d4 2549 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2550 * therefore no explicit interrupt disable is necessary */
021230d4 2551 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2552 if (!eicr) {
6af3b9eb
ET		 2553 /*
2554 * shared interrupt alert!
f47cf66e 2555 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2556 * have disabled interrupts due to EIAM
2557 * finish the workaround of silicon errata on 82598. Unmask
2558 * the interrupt that we masked before the EICR read.
2559 */
2560 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2561 ixgbe_irq_enable(adapter, true, true);
9a799d71 2562 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2563 }
9a799d71 2564
cf8280ee
JB		 2565 if (eicr & IXGBE_EICR_LSC)
2566 ixgbe_check_lsc(adapter);
021230d4 2567
bd508178
AD		 2568 switch (hw->mac.type) {
2569 case ixgbe_mac_82599EB:
e8e26350 2570 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2571 /* Fall through */
2572 case ixgbe_mac_X540:
2573 if (eicr & IXGBE_EICR_ECC)
2574 e_info(link, "Received unrecoverable ECC err, please "
2575 "reboot\n");
4f51bf70 2576 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2577 break;
2578 default:
2579 break;
2580 }
e8e26350 2581
0befdb3e 2582 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2583#ifdef CONFIG_IXGBE_PTP
2584 ixgbe_ptp_check_pps_event(adapter, eicr);
2585#endif
0befdb3e 2586
b9f6ed2b
AD		 2587 /* would disable interrupts here but EIAM disabled it */
2588 napi_schedule(&q_vector->napi);
9a799d71 2589
6af3b9eb
ET		 2590 /*
2591 * re-enable link(maybe) and non-queue interrupts, no flush.
2592 * ixgbe_poll will re-enable the queue interrupts
2593 */
6af3b9eb
ET		 2594 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2595 ixgbe_irq_enable(adapter, false, false);
2596
9a799d71
AK		 2597 return IRQ_HANDLED;
2598}
2599
2600/**
2601 * ixgbe_request_irq - initialize interrupts
2602 * @adapter: board private structure
2603 *
2604 * Attempts to configure interrupts using the best available
2605 * capabilities of the hardware and kernel.
2606 **/
021230d4 2607static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2608{
2609 struct net_device *netdev = adapter->netdev;
021230d4 2610 int err;
9a799d71 2611
4cc6df29 2612 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2613 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2614 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2615 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2616 netdev->name, adapter);
4cc6df29 2617 else
a0607fd3 2618 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2619 netdev->name, adapter);
9a799d71 2620
de88eeeb 2621 if (err)
396e799c 2622 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2623
9a799d71
AK		 2624 return err;
2625}
2626
2627static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2628{
49c7ffbe 2629 int vector;
9a799d71 2630
49c7ffbe
AD		 2631 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2632 free_irq(adapter->pdev->irq, adapter);
2633 return;
2634 }
4cc6df29 2635
49c7ffbe
AD		 2636 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2637 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2638 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2639
49c7ffbe
AD		 2640 /* free only the irqs that were actually requested */
2641 if (!q_vector->rx.ring && !q_vector->tx.ring)
2642 continue;
207867f5 2643
49c7ffbe
AD		 2644 /* clear the affinity_mask in the IRQ descriptor */
2645 irq_set_affinity_hint(entry->vector, NULL);
2646
2647 free_irq(entry->vector, q_vector);
9a799d71 2648 }
49c7ffbe
AD		 2649
2650 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2651}
2652
22d5a71b
JB		 2653/**
2654 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2655 * @adapter: board private structure
2656 **/
2657static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2658{
bd508178
AD		 2659 switch (adapter->hw.mac.type) {
2660 case ixgbe_mac_82598EB:
835462fc 2661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2662 break;
2663 case ixgbe_mac_82599EB:
b93a2226 2664 case ixgbe_mac_X540:
835462fc
NS		 2665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2666 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2667 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2668 break;
2669 default:
2670 break;
22d5a71b
JB		 2671 }
2672 IXGBE_WRITE_FLUSH(&adapter->hw);
2673 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2674 int vector;
2675
2676 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2677 synchronize_irq(adapter->msix_entries[vector].vector);
2678
2679 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2680 } else {
2681 synchronize_irq(adapter->pdev->irq);
2682 }
2683}
2684
9a799d71
AK		 2685/**
2686 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2687 *
2688 **/
2689static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2690{
d5bf4f67 2691 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2692
d5bf4f67
ET		 2693 /* rx/tx vector */
2694 if (adapter->rx_itr_setting == 1)
2695 q_vector->itr = IXGBE_20K_ITR;
2696 else
2697 q_vector->itr = adapter->rx_itr_setting;
2698
2699 ixgbe_write_eitr(q_vector);
9a799d71 2700
e8e26350
PW		 2701 ixgbe_set_ivar(adapter, 0, 0, 0);
2702 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2703
396e799c 2704 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2705}
2706
43e69bf0
AD		 2707/**
2708 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2709 * @adapter: board private structure
2710 * @ring: structure containing ring specific data
2711 *
2712 * Configure the Tx descriptor ring after a reset.
2713 **/
84418e3b
AD		 2714void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2715 struct ixgbe_ring *ring)
43e69bf0
AD		 2716{
2717 struct ixgbe_hw *hw = &adapter->hw;
2718 u64 tdba = ring->dma;
2f1860b8 2719 int wait_loop = 10;
b88c6de2 2720 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2721 u8 reg_idx = ring->reg_idx;
43e69bf0 2722
2f1860b8 2723 /* disable queue to avoid issues while updating state */
b88c6de2 2724 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2725 IXGBE_WRITE_FLUSH(hw);
2726
43e69bf0 2727 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2728 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2729 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2730 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2731 ring->count * sizeof(union ixgbe_adv_tx_desc));
2732 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2733 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2734 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2735
b88c6de2
AD		 2736 /*
2737 * set WTHRESH to encourage burst writeback, it should not be set
2738 * higher than 1 when ITR is 0 as it could cause false TX hangs
2739 *
2740 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2741 * to or less than the number of on chip descriptors, which is
2742 * currently 40.
2743 */
e954b374 2744 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2745 txdctl |= (1 << 16); /* WTHRESH = 1 */
2746 else
2747 txdctl |= (8 << 16); /* WTHRESH = 8 */
2748
e954b374
AD		 2749 /*
2750 * Setting PTHRESH to 32 both improves performance
2751 * and avoids a TX hang with DFP enabled
2752 */
b88c6de2
AD		 2753 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2754 32; /* PTHRESH = 32 */
2f1860b8
AD		 2755
2756 /* reinitialize flowdirector state */
39cb681b 2757 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2758 ring->atr_sample_rate = adapter->atr_sample_rate;
2759 ring->atr_count = 0;
2760 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2761 } else {
2762 ring->atr_sample_rate = 0;
2763 }
2f1860b8 2764
c84d324c
JF		 2765 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2766
2f1860b8 2767 /* enable queue */
2f1860b8
AD		 2768 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2769
2770 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2771 if (hw->mac.type == ixgbe_mac_82598EB &&
2772 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2773 return;
2774
2775 /* poll to verify queue is enabled */
2776 do {
032b4325 2777 usleep_range(1000, 2000);
2f1860b8
AD		 2778 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2779 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2780 if (!wait_loop)
2781 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2782}
2783
120ff942
AD		 2784static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2785{
2786 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2787 u32 rttdcs, mtqc;
8b1c0b24 2788 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2789
2790 if (hw->mac.type == ixgbe_mac_82598EB)
2791 return;
2792
2793 /* disable the arbiter while setting MTQC */
2794 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2795 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2796 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2797
2798 /* set transmit pool layout */
671c0adb
AD		 2799 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2800 mtqc = IXGBE_MTQC_VT_ENA;
2801 if (tcs > 4)
2802 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2803 else if (tcs > 1)
2804 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2805 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2806 mtqc |= IXGBE_MTQC_32VF;
2807 else
2808 mtqc |= IXGBE_MTQC_64VF;
2809 } else {
2810 if (tcs > 4)
2811 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2812 else if (tcs > 1)
2813 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2814 else
671c0adb
AD		 2815 mtqc = IXGBE_MTQC_64Q_1PB;
2816 }
120ff942 2817
671c0adb 2818 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2819
671c0adb
AD		 2820 /* Enable Security TX Buffer IFG for multiple pb */
2821 if (tcs) {
2822 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2823 sectx |= IXGBE_SECTX_DCB;
2824 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2825 }
2826
2827 /* re-enable the arbiter */
2828 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2829 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2830}
2831
9a799d71 2832/**
3a581073 2833 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2834 * @adapter: board private structure
2835 *
2836 * Configure the Tx unit of the MAC after a reset.
2837 **/
2838static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2839{
2f1860b8
AD		 2840 struct ixgbe_hw *hw = &adapter->hw;
2841 u32 dmatxctl;
43e69bf0 2842 u32 i;
9a799d71 2843
2f1860b8
AD		 2844 ixgbe_setup_mtqc(adapter);
2845
2846 if (hw->mac.type != ixgbe_mac_82598EB) {
2847 /* DMATXCTL.EN must be before Tx queues are enabled */
2848 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2849 dmatxctl |= IXGBE_DMATXCTL_TE;
2850 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2851 }
2852
9a799d71 2853 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2854 for (i = 0; i < adapter->num_tx_queues; i++)
2855 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2856}
2857
3ebe8fde
AD		 2858static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2859 struct ixgbe_ring *ring)
2860{
2861 struct ixgbe_hw *hw = &adapter->hw;
2862 u8 reg_idx = ring->reg_idx;
2863 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2864
2865 srrctl |= IXGBE_SRRCTL_DROP_EN;
2866
2867 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2868}
2869
2870static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2871 struct ixgbe_ring *ring)
2872{
2873 struct ixgbe_hw *hw = &adapter->hw;
2874 u8 reg_idx = ring->reg_idx;
2875 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2876
2877 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2878
2879 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2880}
2881
2882#ifdef CONFIG_IXGBE_DCB
2883void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2884#else
2885static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2886#endif
2887{
2888 int i;
2889 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2890
2891 if (adapter->ixgbe_ieee_pfc)
2892 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2893
2894 /*
2895 * We should set the drop enable bit if:
2896 * SR-IOV is enabled
2897 * or
2898 * Number of Rx queues > 1 and flow control is disabled
2899 *
2900 * This allows us to avoid head of line blocking for security
2901 * and performance reasons.
2902 */
2903 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2904 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2905 for (i = 0; i < adapter->num_rx_queues; i++)
2906 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2907 } else {
2908 for (i = 0; i < adapter->num_rx_queues; i++)
2909 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2910 }
2911}
2912
e8e26350 2913#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2914
a6616b42 2915static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2916 struct ixgbe_ring *rx_ring)
cc41ac7c 2917{
45e9baa5 2918 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2919 u32 srrctl;
bf29ee6c 2920 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2921
45e9baa5
AD		 2922 if (hw->mac.type == ixgbe_mac_82598EB) {
2923 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2924
45e9baa5
AD		 2925 /*
2926 * if VMDq is not active we must program one srrctl register
2927 * per RSS queue since we have enabled RDRXCTL.MVMEN
2928 */
2929 reg_idx &= mask;
2930 }
cc41ac7c 2931
45e9baa5
AD		 2932 /* configure header buffer length, needed for RSC */
2933 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2934
45e9baa5 2935 /* configure the packet buffer length */
f800326d 2936 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2937
2938 /* configure descriptor type */
f800326d 2939 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2940
45e9baa5 2941 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2942}
9a799d71 2943
05abb126 2944static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2945{
05abb126
AD		 2946 struct ixgbe_hw *hw = &adapter->hw;
2947 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2948 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2949 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2950 u32 mrqc = 0, reta = 0;
2951 u32 rxcsum;
2952 int i, j;
671c0adb
AD		 2953 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2954
671c0adb
AD		 2955 /*
2956 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2957 * make full use of any rings they may have. We will use the
2958 * PSRTYPE register to control how many rings we use within the PF.
2959 */
2960 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2961 rss_i = 2;
0cefafad 2962
05abb126
AD		 2963 /* Fill out hash function seeds */
2964 for (i = 0; i < 10; i++)
2965 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2966
2967 /* Fill out redirection table */
2968 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 2969 if (j == rss_i)
05abb126
AD		 2970 j = 0;
2971 /* reta = 4-byte sliding window of
2972 * 0x00..(indices-1)(indices-1)00..etc. */
2973 reta = (reta << 8) | (j * 0x11);
2974 if ((i & 3) == 3)
2975 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2976 }
0cefafad 2977
05abb126
AD		 2978 /* Disable indicating checksum in descriptor, enables RSS hash */
2979 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2980 rxcsum |= IXGBE_RXCSUM_PCSD;
2981 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2982
671c0adb 2983 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 2984 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 2985 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2986 } else {
671c0adb
AD		 2987 u8 tcs = netdev_get_num_tc(adapter->netdev);
2988
2989 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2990 if (tcs > 4)
2991 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
2992 else if (tcs > 1)
2993 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
2994 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2995 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 2996 else
671c0adb
AD		 2997 mrqc = IXGBE_MRQC_VMDQRSS64EN;
2998 } else {
2999 if (tcs > 4)
8b1c0b24 3000 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3001 else if (tcs > 1)
3002 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3003 else
3004 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3005 }
0cefafad
JB		 3006 }
3007
05abb126 3008 /* Perform hash on these packet types */
671c0adb
AD		 3009 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3010 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3011 IXGBE_MRQC_RSS_FIELD_IPV6 |
3012 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3013
ef6afc0c
AD		 3014 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3015 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3016 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3017 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3018
05abb126 3019 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3020}
3021
bb5a9ad2
NS		 3022/**
3023 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3024 * @adapter: address of board private structure
3025 * @index: index of ring to set
bb5a9ad2 3026 **/
082757af 3027static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3028 struct ixgbe_ring *ring)
bb5a9ad2 3029{
bb5a9ad2 3030 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3031 u32 rscctrl;
bf29ee6c 3032 u8 reg_idx = ring->reg_idx;
7367096a 3033
7d637bcc 3034 if (!ring_is_rsc_enabled(ring))
7367096a 3035 return;
bb5a9ad2 3036
7367096a 3037 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3038 rscctrl |= IXGBE_RSCCTL_RSCEN;
3039 /*
3040 * we must limit the number of descriptors so that the
3041 * total size of max desc * buf_len is not greater
642c680e 3042 * than 65536
bb5a9ad2 3043 */
f800326d 3044 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3045 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3046}
3047
9e10e045
AD		 3048#define IXGBE_MAX_RX_DESC_POLL 10
3049static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3050 struct ixgbe_ring *ring)
3051{
3052 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3053 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3054 u32 rxdctl;
bf29ee6c 3055 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3056
3057 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3058 if (hw->mac.type == ixgbe_mac_82598EB &&
3059 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3060 return;
3061
3062 do {
032b4325 3063 usleep_range(1000, 2000);
9e10e045
AD		 3064 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3065 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3066
3067 if (!wait_loop) {
3068 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3069 "the polling period\n", reg_idx);
3070 }
3071}
3072
2d39d576
YZ		 3073void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3074 struct ixgbe_ring *ring)
3075{
3076 struct ixgbe_hw *hw = &adapter->hw;
3077 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3078 u32 rxdctl;
3079 u8 reg_idx = ring->reg_idx;
3080
3081 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3082 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3083
3084 /* write value back with RXDCTL.ENABLE bit cleared */
3085 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3086
3087 if (hw->mac.type == ixgbe_mac_82598EB &&
3088 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3089 return;
3090
3091 /* the hardware may take up to 100us to really disable the rx queue */
3092 do {
3093 udelay(10);
3094 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3095 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3096
3097 if (!wait_loop) {
3098 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3099 "the polling period\n", reg_idx);
3100 }
3101}
3102
84418e3b
AD		 3103void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3104 struct ixgbe_ring *ring)
acd37177
AD		 3105{
3106 struct ixgbe_hw *hw = &adapter->hw;
3107 u64 rdba = ring->dma;
9e10e045 3108 u32 rxdctl;
bf29ee6c 3109 u8 reg_idx = ring->reg_idx;
acd37177 3110
9e10e045
AD		 3111 /* disable queue to avoid issues while updating state */
3112 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3113 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3114
acd37177
AD		 3115 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3116 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3117 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3118 ring->count * sizeof(union ixgbe_adv_rx_desc));
3119 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3120 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3121 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3122
3123 ixgbe_configure_srrctl(adapter, ring);
3124 ixgbe_configure_rscctl(adapter, ring);
3125
e9f98072
GR		 3126 /* If operating in IOV mode set RLPML for X540 */
3127 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3128 hw->mac.type == ixgbe_mac_X540) {
3129 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3130 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3131 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3132 }
3133
9e10e045
AD		 3134 if (hw->mac.type == ixgbe_mac_82598EB) {
3135 /*
3136 * enable cache line friendly hardware writes:
3137 * PTHRESH=32 descriptors (half the internal cache),
3138 * this also removes ugly rx_no_buffer_count increment
3139 * HTHRESH=4 descriptors (to minimize latency on fetch)
3140 * WTHRESH=8 burst writeback up to two cache lines
3141 */
3142 rxdctl &= ~0x3FFFFF;
3143 rxdctl |= 0x080420;
3144 }
3145
3146 /* enable receive descriptor ring */
3147 rxdctl |= IXGBE_RXDCTL_ENABLE;
3148 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3149
3150 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3151 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3152}
3153
48654521
AD		 3154static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3155{
3156 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3157 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3158 int p;
3159
3160 /* PSRTYPE must be initialized in non 82598 adapters */
3161 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3162 IXGBE_PSRTYPE_UDPHDR |
3163 IXGBE_PSRTYPE_IPV4HDR |
48654521 3164 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3165 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3166
3167 if (hw->mac.type == ixgbe_mac_82598EB)
3168 return;
3169
fbe7ca7f
AD		 3170 if (rss_i > 3)
3171 psrtype |= 2 << 29;
3172 else if (rss_i > 1)
3173 psrtype |= 1 << 29;
48654521
AD		 3174
3175 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3176 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3177 psrtype);
3178}
3179
f5b4a52e
AD		 3180static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3181{
3182 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3183 u32 reg_offset, vf_shift;
435b19f6 3184 u32 gcr_ext, vmdctl;
de4c7f65 3185 int i;
f5b4a52e
AD		 3186
3187 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3188 return;
3189
3190 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3191 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3192 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3193 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3194 vmdctl |= IXGBE_VT_CTL_REPLEN;
3195 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3196
1d9c0bfd
AD		 3197 vf_shift = VMDQ_P(0) % 32;
3198 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3199
3200 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3201 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3202 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3203 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3204 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3205 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3206
3207 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3208 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3209
3210 /*
3211 * Set up VF register offsets for selected VT Mode,
3212 * i.e. 32 or 64 VFs for SR-IOV
3213 */
73079ea0
AD		 3214 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3215 case IXGBE_82599_VMDQ_8Q_MASK:
3216 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3217 break;
3218 case IXGBE_82599_VMDQ_4Q_MASK:
3219 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3220 break;
3221 default:
3222 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3223 break;
3224 }
3225
f5b4a52e
AD		 3226 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3227
3228 /* enable Tx loopback for VF/PF communication */
3229 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
435b19f6 3230
a985b6c3 3231 /* Enable MAC Anti-Spoofing */
435b19f6 3232 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3233 adapter->num_vfs);
de4c7f65
GR		 3234 /* For VFs that have spoof checking turned off */
3235 for (i = 0; i < adapter->num_vfs; i++) {
3236 if (!adapter->vfinfo[i].spoofchk_enabled)
3237 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3238 }
f5b4a52e
AD		 3239}
3240
477de6ed 3241static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3242{
9a799d71
AK		 3243 struct ixgbe_hw *hw = &adapter->hw;
3244 struct net_device *netdev = adapter->netdev;
3245 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3246 struct ixgbe_ring *rx_ring;
3247 int i;
3248 u32 mhadd, hlreg0;
48654521 3249
63f39bd1 3250#ifdef IXGBE_FCOE
477de6ed
AD		 3251 /* adjust max frame to be able to do baby jumbo for FCoE */
3252 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3253 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3254 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3255
477de6ed
AD		 3256#endif /* IXGBE_FCOE */
3257 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3258 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3259 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3260 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3261
3262 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3263 }
3264
919e78a6
AD		 3265 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3266 max_frame += VLAN_HLEN;
3267
477de6ed
AD		 3268 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3269 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3270 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3271 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3272
0cefafad
JB		 3273 /*
3274 * Setup the HW Rx Head and Tail Descriptor Pointers and
3275 * the Base and Length of the Rx Descriptor Ring
3276 */
9a799d71 3277 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3278 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3279 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3280 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3281 else
7d637bcc 3282 clear_ring_rsc_enabled(rx_ring);
477de6ed 3283 }
477de6ed
AD		 3284}
3285
7367096a
AD		 3286static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3287{
3288 struct ixgbe_hw *hw = &adapter->hw;
3289 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3290
3291 switch (hw->mac.type) {
3292 case ixgbe_mac_82598EB:
3293 /*
3294 * For VMDq support of different descriptor types or
3295 * buffer sizes through the use of multiple SRRCTL
3296 * registers, RDRXCTL.MVMEN must be set to 1
3297 *
3298 * also, the manual doesn't mention it clearly but DCA hints
3299 * will only use queue 0's tags unless this bit is set. Side
3300 * effects of setting this bit are only that SRRCTL must be
3301 * fully programmed [0..15]
3302 */
3303 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3304 break;
3305 case ixgbe_mac_82599EB:
b93a2226 3306 case ixgbe_mac_X540:
7367096a
AD		 3307 /* Disable RSC for ACK packets */
3308 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3309 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3310 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3311 /* hardware requires some bits to be set by default */
3312 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3313 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3314 break;
3315 default:
3316 /* We should do nothing since we don't know this hardware */
3317 return;
3318 }
3319
3320 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3321}
3322
477de6ed
AD		 3323/**
3324 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3325 * @adapter: board private structure
3326 *
3327 * Configure the Rx unit of the MAC after a reset.
3328 **/
3329static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3330{
3331 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3332 int i;
3333 u32 rxctrl;
477de6ed
AD		 3334
3335 /* disable receives while setting up the descriptors */
3336 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3337 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3338
3339 ixgbe_setup_psrtype(adapter);
7367096a 3340 ixgbe_setup_rdrxctl(adapter);
477de6ed 3341
9e10e045 3342 /* Program registers for the distribution of queues */
f5b4a52e 3343 ixgbe_setup_mrqc(adapter);
f5b4a52e 3344
477de6ed
AD		 3345 /* set_rx_buffer_len must be called before ring initialization */
3346 ixgbe_set_rx_buffer_len(adapter);
3347
3348 /*
3349 * Setup the HW Rx Head and Tail Descriptor Pointers and
3350 * the Base and Length of the Rx Descriptor Ring
3351 */
9e10e045
AD		 3352 for (i = 0; i < adapter->num_rx_queues; i++)
3353 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3354
9e10e045
AD		 3355 /* disable drop enable for 82598 parts */
3356 if (hw->mac.type == ixgbe_mac_82598EB)
3357 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3358
3359 /* enable all receives */
3360 rxctrl |= IXGBE_RXCTRL_RXEN;
3361 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3362}
3363
8e586137 3364static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3365{
3366 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3367 struct ixgbe_hw *hw = &adapter->hw;
3368
3369 /* add VID to filter table */
1d9c0bfd 3370 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3371 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3372
3373 return 0;
068c89b0
DS		 3374}
3375
8e586137 3376static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3377{
3378 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3379 struct ixgbe_hw *hw = &adapter->hw;
3380
068c89b0 3381 /* remove VID from filter table */
1d9c0bfd 3382 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3383 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3384
3385 return 0;
068c89b0
DS		 3386}
3387
5f6c0181
JB		 3388/**
3389 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3390 * @adapter: driver data
3391 */
3392static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3393{
3394 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3395 u32 vlnctrl;
3396
3397 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3398 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3399 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3400}
3401
3402/**
3403 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3404 * @adapter: driver data
3405 */
3406static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3407{
3408 struct ixgbe_hw *hw = &adapter->hw;
3409 u32 vlnctrl;
3410
3411 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3412 vlnctrl |= IXGBE_VLNCTRL_VFE;
3413 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3414 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3415}
3416
3417/**
3418 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3419 * @adapter: driver data
3420 */
3421static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3422{
3423 struct ixgbe_hw *hw = &adapter->hw;
3424 u32 vlnctrl;
5f6c0181
JB		 3425 int i, j;
3426
3427 switch (hw->mac.type) {
3428 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3429 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3430 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3431 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3432 break;
3433 case ixgbe_mac_82599EB:
b93a2226 3434 case ixgbe_mac_X540:
5f6c0181
JB		 3435 for (i = 0; i < adapter->num_rx_queues; i++) {
3436 j = adapter->rx_ring[i]->reg_idx;
3437 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3438 vlnctrl &= ~IXGBE_RXDCTL_VME;
3439 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3440 }
3441 break;
3442 default:
3443 break;
3444 }
3445}
3446
3447/**
f62bbb5e 3448 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3449 * @adapter: driver data
3450 */
f62bbb5e 3451static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3452{
3453 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3454 u32 vlnctrl;
5f6c0181
JB		 3455 int i, j;
3456
3457 switch (hw->mac.type) {
3458 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3459 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3460 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3461 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3462 break;
3463 case ixgbe_mac_82599EB:
b93a2226 3464 case ixgbe_mac_X540:
5f6c0181
JB		 3465 for (i = 0; i < adapter->num_rx_queues; i++) {
3466 j = adapter->rx_ring[i]->reg_idx;
3467 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3468 vlnctrl |= IXGBE_RXDCTL_VME;
3469 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3470 }
3471 break;
3472 default:
3473 break;
3474 }
3475}
3476
9a799d71
AK		 3477static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3478{
f62bbb5e 3479 u16 vid;
9a799d71 3480
f62bbb5e
JG		 3481 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3482
3483 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3484 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3485}
3486
2850062a
AD		 3487/**
3488 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3489 * @netdev: network interface device structure
3490 *
3491 * Writes unicast address list to the RAR table.
3492 * Returns: -ENOMEM on failure/insufficient address space
3493 * 0 on no addresses written
3494 * X on writing X addresses to the RAR table
3495 **/
3496static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3497{
3498 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3499 struct ixgbe_hw *hw = &adapter->hw;
95447461 3500 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3501 int count = 0;
3502
95447461
JF		 3503 /* In SR-IOV mode significantly less RAR entries are available */
3504 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3505 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3506
2850062a
AD		 3507 /* return ENOMEM indicating insufficient memory for addresses */
3508 if (netdev_uc_count(netdev) > rar_entries)
3509 return -ENOMEM;
3510
95447461 3511 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3512 struct netdev_hw_addr *ha;
3513 /* return error if we do not support writing to RAR table */
3514 if (!hw->mac.ops.set_rar)
3515 return -ENOMEM;
3516
3517 netdev_for_each_uc_addr(ha, netdev) {
3518 if (!rar_entries)
3519 break;
3520 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3521 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3522 count++;
3523 }
3524 }
3525 /* write the addresses in reverse order to avoid write combining */
3526 for (; rar_entries > 0 ; rar_entries--)
3527 hw->mac.ops.clear_rar(hw, rar_entries);
3528
3529 return count;
3530}
3531
9a799d71 3532/**
2c5645cf 3533 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3534 * @netdev: network interface device structure
3535 *
2c5645cf
CL		 3536 * The set_rx_method entry point is called whenever the unicast/multicast
3537 * address list or the network interface flags are updated. This routine is
3538 * responsible for configuring the hardware for proper unicast, multicast and
3539 * promiscuous mode.
9a799d71 3540 **/
7f870475 3541void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3542{
3543 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3544 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3545 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3546 int count;
9a799d71
AK		 3547
3548 /* Check for Promiscuous and All Multicast modes */
3549
3550 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3551
f5dc442b 3552 /* set all bits that we expect to always be set */
3f2d1c0f 3553 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3554 fctrl |= IXGBE_FCTRL_BAM;
3555 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3556 fctrl |= IXGBE_FCTRL_PMCF;
3557
2850062a
AD		 3558 /* clear the bits we are changing the status of */
3559 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3560
9a799d71 3561 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3562 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3563 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3564 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3565 /* don't hardware filter vlans in promisc mode */
3566 ixgbe_vlan_filter_disable(adapter);
9a799d71 3567 } else {
746b9f02
PM		 3568 if (netdev->flags & IFF_ALLMULTI) {
3569 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3570 vmolr |= IXGBE_VMOLR_MPE;
3571 } else {
3572 /*
3573 * Write addresses to the MTA, if the attempt fails
25985edc 3574 * then we should just turn on promiscuous mode so
2850062a
AD		 3575 * that we can at least receive multicast traffic
3576 */
3577 hw->mac.ops.update_mc_addr_list(hw, netdev);
3578 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3579 }
5f6c0181 3580 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3581 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3582 }
3583
3584 /*
3585 * Write addresses to available RAR registers, if there is not
3586 * sufficient space to store all the addresses then enable
3587 * unicast promiscuous mode
3588 */
3589 count = ixgbe_write_uc_addr_list(netdev);
3590 if (count < 0) {
3591 fctrl |= IXGBE_FCTRL_UPE;
3592 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3593 }
3594
1d9c0bfd 3595 if (adapter->num_vfs)
1cdd1ec8 3596 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3597
3598 if (hw->mac.type != ixgbe_mac_82598EB) {
3599 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3600 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3601 IXGBE_VMOLR_ROPE);
1d9c0bfd 3602 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3603 }
3604
3f2d1c0f
BG		 3605 /* This is useful for sniffing bad packets. */
3606 if (adapter->netdev->features & NETIF_F_RXALL) {
3607 /* UPE and MPE will be handled by normal PROMISC logic
3608 * in e1000e_set_rx_mode */
3609 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3610 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3611 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3612
3613 fctrl &= ~(IXGBE_FCTRL_DPF);
3614 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3615 }
3616
2850062a 3617 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3618
3619 if (netdev->features & NETIF_F_HW_VLAN_RX)
3620 ixgbe_vlan_strip_enable(adapter);
3621 else
3622 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3623}
3624
021230d4
AV		 3625static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3626{
3627 int q_idx;
021230d4 3628
49c7ffbe
AD		 3629 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3630 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3631}
3632
3633static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3634{
3635 int q_idx;
021230d4 3636
49c7ffbe
AD		 3637 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3638 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3639}
3640
7a6b6f51 3641#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3642/**
2f90b865
AD		 3643 * ixgbe_configure_dcb - Configure DCB hardware
3644 * @adapter: ixgbe adapter struct
3645 *
3646 * This is called by the driver on open to configure the DCB hardware.
3647 * This is also called by the gennetlink interface when reconfiguring
3648 * the DCB state.
3649 */
3650static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3651{
3652 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3653 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3654
67ebd791
AD		 3655 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3656 if (hw->mac.type == ixgbe_mac_82598EB)
3657 netif_set_gso_max_size(adapter->netdev, 65536);
3658 return;
3659 }
3660
3661 if (hw->mac.type == ixgbe_mac_82598EB)
3662 netif_set_gso_max_size(adapter->netdev, 32768);
3663
2f90b865 3664 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3665
971060b1 3666#ifdef IXGBE_FCOE
b120818e
JF		 3667 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3668 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3669#endif
b120818e
JF		 3670
3671 /* reconfigure the hardware */
3672 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3673 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3674 DCB_TX_CONFIG);
3675 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3676 DCB_RX_CONFIG);
3677 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3678 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3679 ixgbe_dcb_hw_ets(&adapter->hw,
3680 adapter->ixgbe_ieee_ets,
3681 max_frame);
3682 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3683 adapter->ixgbe_ieee_pfc->pfc_en,
3684 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3685 }
8187cd48
JF		 3686
3687 /* Enable RSS Hash per TC */
3688 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3689 u32 msb = 0;
3690 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3691
d411a936
AD		 3692 while (rss_i) {
3693 msb++;
3694 rss_i >>= 1;
3695 }
8187cd48 3696
4ae63730
AD		 3697 /* write msb to all 8 TCs in one write */
3698 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3699 }
2f90b865 3700}
9da712d2
JF		 3701#endif
3702
3703/* Additional bittime to account for IXGBE framing */
3704#define IXGBE_ETH_FRAMING 20
3705
49ce9c2c 3706/**
9da712d2
JF		 3707 * ixgbe_hpbthresh - calculate high water mark for flow control
3708 *
3709 * @adapter: board private structure to calculate for
49ce9c2c 3710 * @pb: packet buffer to calculate
9da712d2
JF		 3711 */
3712static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3713{
3714 struct ixgbe_hw *hw = &adapter->hw;
3715 struct net_device *dev = adapter->netdev;
3716 int link, tc, kb, marker;
3717 u32 dv_id, rx_pba;
3718
3719 /* Calculate max LAN frame size */
3720 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3721
3722#ifdef IXGBE_FCOE
3723 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3724 if ((dev->features & NETIF_F_FCOE_MTU) &&
3725 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3726 (pb == ixgbe_fcoe_get_tc(adapter)))
3727 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3728
3729#endif
9da712d2
JF		 3730 /* Calculate delay value for device */
3731 switch (hw->mac.type) {
3732 case ixgbe_mac_X540:
3733 dv_id = IXGBE_DV_X540(link, tc);
3734 break;
3735 default:
3736 dv_id = IXGBE_DV(link, tc);
3737 break;
3738 }
3739
3740 /* Loopback switch introduces additional latency */
3741 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3742 dv_id += IXGBE_B2BT(tc);
3743
3744 /* Delay value is calculated in bit times convert to KB */
3745 kb = IXGBE_BT2KB(dv_id);
3746 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3747
3748 marker = rx_pba - kb;
3749
3750 /* It is possible that the packet buffer is not large enough
3751 * to provide required headroom. In this case throw an error
3752 * to user and a do the best we can.
3753 */
3754 if (marker < 0) {
3755 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3756 "headroom to support flow control."
3757 "Decrease MTU or number of traffic classes\n", pb);
3758 marker = tc + 1;
3759 }
3760
3761 return marker;
3762}
3763
49ce9c2c 3764/**
9da712d2
JF		 3765 * ixgbe_lpbthresh - calculate low water mark for for flow control
3766 *
3767 * @adapter: board private structure to calculate for
49ce9c2c 3768 * @pb: packet buffer to calculate
9da712d2
JF		 3769 */
3770static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3771{
3772 struct ixgbe_hw *hw = &adapter->hw;
3773 struct net_device *dev = adapter->netdev;
3774 int tc;
3775 u32 dv_id;
3776
3777 /* Calculate max LAN frame size */
3778 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3779
3780 /* Calculate delay value for device */
3781 switch (hw->mac.type) {
3782 case ixgbe_mac_X540:
3783 dv_id = IXGBE_LOW_DV_X540(tc);
3784 break;
3785 default:
3786 dv_id = IXGBE_LOW_DV(tc);
3787 break;
3788 }
3789
3790 /* Delay value is calculated in bit times convert to KB */
3791 return IXGBE_BT2KB(dv_id);
3792}
3793
3794/*
3795 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3796 */
3797static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3798{
3799 struct ixgbe_hw *hw = &adapter->hw;
3800 int num_tc = netdev_get_num_tc(adapter->netdev);
3801 int i;
3802
3803 if (!num_tc)
3804 num_tc = 1;
3805
3806 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3807
3808 for (i = 0; i < num_tc; i++) {
3809 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3810
3811 /* Low water marks must not be larger than high water marks */
3812 if (hw->fc.low_water > hw->fc.high_water[i])
3813 hw->fc.low_water = 0;
3814 }
3815}
3816
80605c65
JF		 3817static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3818{
80605c65 3819 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3820 int hdrm;
3821 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3822
3823 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3824 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3825 hdrm = 32 << adapter->fdir_pballoc;
3826 else
3827 hdrm = 0;
80605c65 3828
f7e1027f 3829 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3830 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3831}
3832
e4911d57
AD		 3833static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3834{
3835 struct ixgbe_hw *hw = &adapter->hw;
3836 struct hlist_node *node, *node2;
3837 struct ixgbe_fdir_filter *filter;
3838
3839 spin_lock(&adapter->fdir_perfect_lock);
3840
3841 if (!hlist_empty(&adapter->fdir_filter_list))
3842 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3843
3844 hlist_for_each_entry_safe(filter, node, node2,
3845 &adapter->fdir_filter_list, fdir_node) {
3846 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3847 &filter->filter,
3848 filter->sw_idx,
3849 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3850 IXGBE_FDIR_DROP_QUEUE :
3851 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3852 }
3853
3854 spin_unlock(&adapter->fdir_perfect_lock);
3855}
3856
9a799d71
AK		 3857static void ixgbe_configure(struct ixgbe_adapter *adapter)
3858{
d2f5e7f3
AS		 3859 struct ixgbe_hw *hw = &adapter->hw;
3860
80605c65 3861 ixgbe_configure_pb(adapter);
7a6b6f51 3862#ifdef CONFIG_IXGBE_DCB
67ebd791 3863 ixgbe_configure_dcb(adapter);
2f90b865 3864#endif
9a799d71 3865
4c1d7b4b 3866 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3867 ixgbe_restore_vlan(adapter);
3868
d2f5e7f3
AS		 3869 switch (hw->mac.type) {
3870 case ixgbe_mac_82599EB:
3871 case ixgbe_mac_X540:
3872 hw->mac.ops.disable_rx_buff(hw);
3873 break;
3874 default:
3875 break;
3876 }
3877
c4cf55e5 3878 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3879 ixgbe_init_fdir_signature_82599(&adapter->hw,
3880 adapter->fdir_pballoc);
e4911d57
AD		 3881 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3882 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3883 adapter->fdir_pballoc);
3884 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3885 }
4c1d7b4b 3886
d2f5e7f3
AS		 3887 switch (hw->mac.type) {
3888 case ixgbe_mac_82599EB:
3889 case ixgbe_mac_X540:
3890 hw->mac.ops.enable_rx_buff(hw);
3891 break;
3892 default:
3893 break;
3894 }
3895
933d41f1 3896 ixgbe_configure_virtualization(adapter);
c4cf55e5 3897
7c8ae65a
AD		 3898#ifdef IXGBE_FCOE
3899 /* configure FCoE L2 filters, redirection table, and Rx control */
3900 ixgbe_configure_fcoe(adapter);
3901
3902#endif /* IXGBE_FCOE */
9a799d71
AK		 3903 ixgbe_configure_tx(adapter);
3904 ixgbe_configure_rx(adapter);
9a799d71
AK		 3905}
3906
e8e26350
PW		 3907static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3908{
3909 switch (hw->phy.type) {
3910 case ixgbe_phy_sfp_avago:
3911 case ixgbe_phy_sfp_ftl:
3912 case ixgbe_phy_sfp_intel:
3913 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3914 case ixgbe_phy_sfp_passive_tyco:
3915 case ixgbe_phy_sfp_passive_unknown:
3916 case ixgbe_phy_sfp_active_unknown:
3917 case ixgbe_phy_sfp_ftl_active:
e8e26350 3918 return true;
8917b447
AD		 3919 case ixgbe_phy_nl:
3920 if (hw->mac.type == ixgbe_mac_82598EB)
3921 return true;
e8e26350
PW		 3922 default:
3923 return false;
3924 }
3925}
3926
0ecc061d 3927/**
e8e26350
PW		 3928 * ixgbe_sfp_link_config - set up SFP+ link
3929 * @adapter: pointer to private adapter struct
3930 **/
3931static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3932{
7086400d 3933 /*
52f33af8 3934 * We are assuming the worst case scenario here, and that
7086400d
AD		 3935 * is that an SFP was inserted/removed after the reset
3936 * but before SFP detection was enabled. As such the best
3937 * solution is to just start searching as soon as we start
3938 */
3939 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3940 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3941
7086400d 3942 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3943}
3944
3945/**
3946 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3947 * @hw: pointer to private hardware struct
3948 *
3949 * Returns 0 on success, negative on failure
3950 **/
e8e26350 3951static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3952{
3953 u32 autoneg;
8620a103 3954 bool negotiation, link_up = false;
0ecc061d
PWJ		 3955 u32 ret = IXGBE_ERR_LINK_SETUP;
3956
3957 if (hw->mac.ops.check_link)
3958 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3959
3960 if (ret)
3961 goto link_cfg_out;
3962
0b0c2b31
ET		 3963 autoneg = hw->phy.autoneg_advertised;
3964 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3965 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3966 &negotiation);
0ecc061d
PWJ		 3967 if (ret)
3968 goto link_cfg_out;
3969
8620a103
MC		 3970 if (hw->mac.ops.setup_link)
3971 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3972link_cfg_out:
3973 return ret;
3974}
3975
a34bcfff 3976static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3977{
9a799d71 3978 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3979 u32 gpie = 0;
9a799d71 3980
9b471446 3981 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3982 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3983 IXGBE_GPIE_OCD;
3984 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3985 /*
3986 * use EIAM to auto-mask when MSI-X interrupt is asserted
3987 * this saves a register write for every interrupt
3988 */
3989 switch (hw->mac.type) {
3990 case ixgbe_mac_82598EB:
3991 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3992 break;
9b471446 3993 case ixgbe_mac_82599EB:
b93a2226
DS		 3994 case ixgbe_mac_X540:
3995 default:
9b471446
JB		 3996 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3997 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3998 break;
3999 }
4000 } else {
021230d4
AV		 4001 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4002 * specifically only auto mask tx and rx interrupts */
4003 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4004 }
9a799d71 4005
a34bcfff
AD		 4006 /* XXX: to interrupt immediately for EICS writes, enable this */
4007 /* gpie |= IXGBE_GPIE_EIMEN; */
4008
4009 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4010 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4011
4012 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4013 case IXGBE_82599_VMDQ_8Q_MASK:
4014 gpie |= IXGBE_GPIE_VTMODE_16;
4015 break;
4016 case IXGBE_82599_VMDQ_4Q_MASK:
4017 gpie |= IXGBE_GPIE_VTMODE_32;
4018 break;
4019 default:
4020 gpie |= IXGBE_GPIE_VTMODE_64;
4021 break;
4022 }
119fc60a
MC		 4023 }
4024
5fdd31f9 4025 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4026 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4027 switch (adapter->hw.mac.type) {
4028 case ixgbe_mac_82599EB:
4029 gpie |= IXGBE_SDP0_GPIEN;
4030 break;
4031 case ixgbe_mac_X540:
4032 gpie |= IXGBE_EIMS_TS;
4033 break;
4034 default:
4035 break;
4036 }
4037 }
5fdd31f9 4038
a34bcfff
AD		 4039 /* Enable fan failure interrupt */
4040 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4041 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4042
2698b208 4043 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4044 gpie |= IXGBE_SDP1_GPIEN;
4045 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4046 }
a34bcfff
AD		 4047
4048 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4049}
4050
c7ccde0f 4051static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4052{
4053 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4054 int err;
a34bcfff
AD		 4055 u32 ctrl_ext;
4056
4057 ixgbe_get_hw_control(adapter);
4058 ixgbe_setup_gpie(adapter);
e8e26350 4059
9a799d71
AK		 4060 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4061 ixgbe_configure_msix(adapter);
4062 else
4063 ixgbe_configure_msi_and_legacy(adapter);
4064
c6ecf39a
DS		 4065 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4066 if (hw->mac.ops.enable_tx_laser &&
4067 ((hw->phy.multispeed_fiber) ||
9f911707 4068 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4069 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4070 hw->mac.ops.enable_tx_laser(hw);
4071
9a799d71 4072 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4073 ixgbe_napi_enable_all(adapter);
4074
73c4b7cd
AD		 4075 if (ixgbe_is_sfp(hw)) {
4076 ixgbe_sfp_link_config(adapter);
4077 } else {
4078 err = ixgbe_non_sfp_link_config(hw);
4079 if (err)
4080 e_err(probe, "link_config FAILED %d\n", err);
4081 }
4082
021230d4
AV		 4083 /* clear any pending interrupts, may auto mask */
4084 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4085 ixgbe_irq_enable(adapter, true, true);
9a799d71 4086
bf069c97
DS		 4087 /*
4088 * If this adapter has a fan, check to see if we had a failure
4089 * before we enabled the interrupt.
4090 */
4091 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4092 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4093 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4094 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4095 }
4096
1da100bb 4097 /* enable transmits */
477de6ed 4098 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4099
9a799d71
AK		 4100 /* bring the link up in the watchdog, this could race with our first
4101 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4102 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4103 adapter->link_check_timeout = jiffies;
7086400d 4104 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4105
4106 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4107 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4108 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4109 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4110}
4111
d4f80882
AV		 4112void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4113{
4114 WARN_ON(in_interrupt());
7086400d
AD		 4115 /* put off any impending NetWatchDogTimeout */
4116 adapter->netdev->trans_start = jiffies;
4117
d4f80882 4118 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4119 usleep_range(1000, 2000);
d4f80882 4120 ixgbe_down(adapter);
5809a1ae
GR		 4121 /*
4122 * If SR-IOV enabled then wait a bit before bringing the adapter
4123 * back up to give the VFs time to respond to the reset. The
4124 * two second wait is based upon the watchdog timer cycle in
4125 * the VF driver.
4126 */
4127 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4128 msleep(2000);
d4f80882
AV		 4129 ixgbe_up(adapter);
4130 clear_bit(__IXGBE_RESETTING, &adapter->state);
4131}
4132
c7ccde0f 4133void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4134{
4135 /* hardware has been reset, we need to reload some things */
4136 ixgbe_configure(adapter);
4137
c7ccde0f 4138 ixgbe_up_complete(adapter);
9a799d71
AK		 4139}
4140
4141void ixgbe_reset(struct ixgbe_adapter *adapter)
4142{
c44ade9e 4143 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4144 int err;
4145
7086400d
AD		 4146 /* lock SFP init bit to prevent race conditions with the watchdog */
4147 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4148 usleep_range(1000, 2000);
4149
4150 /* clear all SFP and link config related flags while holding SFP_INIT */
4151 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4152 IXGBE_FLAG2_SFP_NEEDS_RESET);
4153 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4154
8ca783ab 4155 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4156 switch (err) {
4157 case 0:
4158 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4159 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4160 break;
4161 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4162 e_dev_err("master disable timed out\n");
da4dd0f7 4163 break;
794caeb2
PWJ		 4164 case IXGBE_ERR_EEPROM_VERSION:
4165 /* We are running on a pre-production device, log a warning */
849c4542 4166 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4167 "Please be aware there may be issues associated with "
849c4542
ET		 4168 "your hardware. If you are experiencing problems "
4169 "please contact your Intel or hardware "
4170 "representative who provided you with this "
4171 "hardware.\n");
794caeb2 4172 break;
da4dd0f7 4173 default:
849c4542 4174 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4175 }
9a799d71 4176
7086400d
AD		 4177 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4178
9a799d71 4179 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4180 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4181
4182 /* update SAN MAC vmdq pool selection */
4183 if (hw->mac.san_mac_rar_index)
4184 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
9a799d71
AK		 4185}
4186
9a799d71
AK		 4187/**
4188 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4189 * @rx_ring: ring to free buffers from
4190 **/
b6ec895e 4191static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4192{
b6ec895e 4193 struct device *dev = rx_ring->dev;
9a799d71 4194 unsigned long size;
b6ec895e 4195 u16 i;
9a799d71 4196
84418e3b
AD		 4197 /* ring already cleared, nothing to do */
4198 if (!rx_ring->rx_buffer_info)
4199 return;
9a799d71 4200
84418e3b 4201 /* Free all the Rx ring sk_buffs */
9a799d71 4202 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4203 struct ixgbe_rx_buffer *rx_buffer;
4204
4205 rx_buffer = &rx_ring->rx_buffer_info[i];
4206 if (rx_buffer->skb) {
4207 struct sk_buff *skb = rx_buffer->skb;
4208 if (IXGBE_CB(skb)->page_released) {
4209 dma_unmap_page(dev,
4210 IXGBE_CB(skb)->dma,
4211 ixgbe_rx_bufsz(rx_ring),
4212 DMA_FROM_DEVICE);
4213 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4214 }
4215 dev_kfree_skb(skb);
9a799d71 4216 }
f800326d
AD		 4217 rx_buffer->skb = NULL;
4218 if (rx_buffer->dma)
4219 dma_unmap_page(dev, rx_buffer->dma,
4220 ixgbe_rx_pg_size(rx_ring),
4221 DMA_FROM_DEVICE);
4222 rx_buffer->dma = 0;
4223 if (rx_buffer->page)
dd411ec4
AD		 4224 __free_pages(rx_buffer->page,
4225 ixgbe_rx_pg_order(rx_ring));
f800326d 4226 rx_buffer->page = NULL;
9a799d71
AK		 4227 }
4228
4229 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4230 memset(rx_ring->rx_buffer_info, 0, size);
4231
4232 /* Zero out the descriptor ring */
4233 memset(rx_ring->desc, 0, rx_ring->size);
4234
f800326d 4235 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4236 rx_ring->next_to_clean = 0;
4237 rx_ring->next_to_use = 0;
9a799d71
AK		 4238}
4239
4240/**
4241 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4242 * @tx_ring: ring to be cleaned
4243 **/
b6ec895e 4244static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4245{
4246 struct ixgbe_tx_buffer *tx_buffer_info;
4247 unsigned long size;
b6ec895e 4248 u16 i;
9a799d71 4249
84418e3b
AD		 4250 /* ring already cleared, nothing to do */
4251 if (!tx_ring->tx_buffer_info)
4252 return;
9a799d71 4253
84418e3b 4254 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4255 for (i = 0; i < tx_ring->count; i++) {
4256 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4257 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4258 }
4259
dad8a3b3
JF		 4260 netdev_tx_reset_queue(txring_txq(tx_ring));
4261
9a799d71
AK		 4262 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4263 memset(tx_ring->tx_buffer_info, 0, size);
4264
4265 /* Zero out the descriptor ring */
4266 memset(tx_ring->desc, 0, tx_ring->size);
4267
4268 tx_ring->next_to_use = 0;
4269 tx_ring->next_to_clean = 0;
9a799d71
AK		 4270}
4271
4272/**
021230d4 4273 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4274 * @adapter: board private structure
4275 **/
021230d4 4276static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4277{
4278 int i;
4279
021230d4 4280 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4281 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4282}
4283
4284/**
021230d4 4285 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4286 * @adapter: board private structure
4287 **/
021230d4 4288static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4289{
4290 int i;
4291
021230d4 4292 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4293 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4294}
4295
e4911d57
AD		 4296static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4297{
4298 struct hlist_node *node, *node2;
4299 struct ixgbe_fdir_filter *filter;
4300
4301 spin_lock(&adapter->fdir_perfect_lock);
4302
4303 hlist_for_each_entry_safe(filter, node, node2,
4304 &adapter->fdir_filter_list, fdir_node) {
4305 hlist_del(&filter->fdir_node);
4306 kfree(filter);
4307 }
4308 adapter->fdir_filter_count = 0;
4309
4310 spin_unlock(&adapter->fdir_perfect_lock);
4311}
4312
9a799d71
AK		 4313void ixgbe_down(struct ixgbe_adapter *adapter)
4314{
4315 struct net_device *netdev = adapter->netdev;
7f821875 4316 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4317 u32 rxctrl;
bf29ee6c 4318 int i;
9a799d71
AK		 4319
4320 /* signal that we are down to the interrupt handler */
4321 set_bit(__IXGBE_DOWN, &adapter->state);
4322
4323 /* disable receives */
7f821875
JB		 4324 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4325 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4326
2d39d576
YZ		 4327 /* disable all enabled rx queues */
4328 for (i = 0; i < adapter->num_rx_queues; i++)
4329 /* this call also flushes the previous write */
4330 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4331
032b4325 4332 usleep_range(10000, 20000);
9a799d71 4333
7f821875
JB		 4334 netif_tx_stop_all_queues(netdev);
4335
7086400d 4336 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4337 netif_carrier_off(netdev);
4338 netif_tx_disable(netdev);
4339
4340 ixgbe_irq_disable(adapter);
4341
4342 ixgbe_napi_disable_all(adapter);
4343
d034acf1
AD		 4344 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4345 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4346 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4347
4348 del_timer_sync(&adapter->service_timer);
4349
34cecbbf 4350 if (adapter->num_vfs) {
8e34d1aa
AD		 4351 /* Clear EITR Select mapping */
4352 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4353
4354 /* Mark all the VFs as inactive */
4355 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4356 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4357
34cecbbf
AD		 4358 /* ping all the active vfs to let them know we are going down */
4359 ixgbe_ping_all_vfs(adapter);
4360
4361 /* Disable all VFTE/VFRE TX/RX */
4362 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4363 }
4364
7f821875
JB		 4365 /* disable transmits in the hardware now that interrupts are off */
4366 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4367 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4368 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4369 }
34cecbbf
AD		 4370
4371 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4372 switch (hw->mac.type) {
4373 case ixgbe_mac_82599EB:
b93a2226 4374 case ixgbe_mac_X540:
88512539 4375 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4376 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4377 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4378 break;
4379 default:
4380 break;
4381 }
7f821875 4382
6f4a0e45
PL		 4383 if (!pci_channel_offline(adapter->pdev))
4384 ixgbe_reset(adapter);
c6ecf39a
DS		 4385
4386 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4387 if (hw->mac.ops.disable_tx_laser &&
4388 ((hw->phy.multispeed_fiber) ||
9f911707 4389 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4390 (hw->mac.type == ixgbe_mac_82599EB))))
4391 hw->mac.ops.disable_tx_laser(hw);
4392
9a799d71
AK		 4393 ixgbe_clean_all_tx_rings(adapter);
4394 ixgbe_clean_all_rx_rings(adapter);
4395
5dd2d332 4396#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4397 /* since we reset the hardware DCA settings were cleared */
e35ec126 4398 ixgbe_setup_dca(adapter);
96b0e0f6 4399#endif
9a799d71
AK		 4400}
4401
9a799d71
AK		 4402/**
4403 * ixgbe_tx_timeout - Respond to a Tx Hang
4404 * @netdev: network interface device structure
4405 **/
4406static void ixgbe_tx_timeout(struct net_device *netdev)
4407{
4408 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4409
4410 /* Do the reset outside of interrupt context */
c83c6cbd 4411 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4412}
4413
9a799d71
AK		 4414/**
4415 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4416 * @adapter: board private structure to initialize
4417 *
4418 * ixgbe_sw_init initializes the Adapter private data structure.
4419 * Fields are initialized based on PCI device information and
4420 * OS network device settings (MTU size).
4421 **/
4422static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4423{
4424 struct ixgbe_hw *hw = &adapter->hw;
4425 struct pci_dev *pdev = adapter->pdev;
021230d4 4426 unsigned int rss;
7a6b6f51 4427#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4428 int j;
4429 struct tc_configuration *tc;
4430#endif
021230d4 4431
c44ade9e
JB		 4432 /* PCI config space info */
4433
4434 hw->vendor_id = pdev->vendor;
4435 hw->device_id = pdev->device;
4436 hw->revision_id = pdev->revision;
4437 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4438 hw->subsystem_device_id = pdev->subsystem_device;
4439
021230d4 4440 /* Set capability flags */
3ed69d7e 4441 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4442 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4443 switch (hw->mac.type) {
4444 case ixgbe_mac_82598EB:
bf069c97
DS		 4445 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4446 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4447 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4448 break;
b93a2226 4449 case ixgbe_mac_X540:
4f51bf70
JK		 4450 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4451 case ixgbe_mac_82599EB:
49c7ffbe 4452 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4453 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4454 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4455 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4456 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4457 /* Flow Director hash filters enabled */
45b9f509 4458 adapter->atr_sample_rate = 20;
c087663e 4459 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4460 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4461 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4462#ifdef IXGBE_FCOE
0d551589
YZ		 4463 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4464 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4465#ifdef CONFIG_IXGBE_DCB
6ee16520 4466 /* Default traffic class to use for FCoE */
56075a98 4467 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4468#endif
eacd73f7 4469#endif /* IXGBE_FCOE */
bd508178
AD		 4470 break;
4471 default:
4472 break;
f8212f97 4473 }
2f90b865 4474
7c8ae65a
AD		 4475#ifdef IXGBE_FCOE
4476 /* FCoE support exists, always init the FCoE lock */
4477 spin_lock_init(&adapter->fcoe.lock);
4478
4479#endif
1fc5f038
AD		 4480 /* n-tuple support exists, always init our spinlock */
4481 spin_lock_init(&adapter->fdir_perfect_lock);
4482
7a6b6f51 4483#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4484 switch (hw->mac.type) {
4485 case ixgbe_mac_X540:
4486 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4487 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4488 break;
4489 default:
4490 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4491 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4492 break;
4493 }
4494
2f90b865
AD		 4495 /* Configure DCB traffic classes */
4496 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4497 tc = &adapter->dcb_cfg.tc_config[j];
4498 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4499 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4500 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4501 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4502 tc->dcb_pfc = pfc_disabled;
4503 }
4de2a022
JF		 4504
4505 /* Initialize default user to priority mapping, UPx->TC0 */
4506 tc = &adapter->dcb_cfg.tc_config[0];
4507 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4508 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4509
2f90b865
AD		 4510 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4511 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4512 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4513 adapter->dcb_set_bitmap = 0x00;
3032309b 4514 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4515 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4516 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4517
4518#endif
9a799d71
AK		 4519
4520 /* default flow control settings */
cd7664f6 4521 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4522 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4523 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4524 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4525 hw->fc.send_xon = true;
71fd570b 4526 hw->fc.disable_fc_autoneg = false;
9a799d71 4527
99d74487
AD		 4528#ifdef CONFIG_PCI_IOV
4529 /* assign number of SR-IOV VFs */
4530 if (hw->mac.type != ixgbe_mac_82598EB)
4531 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4532
4533#endif
30efa5a3 4534 /* enable itr by default in dynamic mode */
f7554a2b 4535 adapter->rx_itr_setting = 1;
f7554a2b 4536 adapter->tx_itr_setting = 1;
30efa5a3 4537
30efa5a3
JB		 4538 /* set default ring sizes */
4539 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4540 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4541
bd198058 4542 /* set default work limits */
59224555 4543 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4544
9a799d71 4545 /* initialize eeprom parameters */
c44ade9e 4546 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4547 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4548 return -EIO;
4549 }
4550
9a799d71
AK		 4551 set_bit(__IXGBE_DOWN, &adapter->state);
4552
4553 return 0;
4554}
4555
4556/**
4557 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4558 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4559 *
4560 * Return 0 on success, negative on failure
4561 **/
b6ec895e 4562int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4563{
b6ec895e 4564 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4565 int orig_node = dev_to_node(dev);
4566 int numa_node = -1;
9a799d71
AK		 4567 int size;
4568
3a581073 4569 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4570
4571 if (tx_ring->q_vector)
4572 numa_node = tx_ring->q_vector->numa_node;
4573
4574 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4575 if (!tx_ring->tx_buffer_info)
89bf67f1 4576 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4577 if (!tx_ring->tx_buffer_info)
4578 goto err;
9a799d71
AK		 4579
4580 /* round up to nearest 4K */
12207e49 4581 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4582 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4583
de88eeeb
AD		 4584 set_dev_node(dev, numa_node);
4585 tx_ring->desc = dma_alloc_coherent(dev,
4586 tx_ring->size,
4587 &tx_ring->dma,
4588 GFP_KERNEL);
4589 set_dev_node(dev, orig_node);
4590 if (!tx_ring->desc)
4591 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4592 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4593 if (!tx_ring->desc)
4594 goto err;
9a799d71 4595
3a581073
JB		 4596 tx_ring->next_to_use = 0;
4597 tx_ring->next_to_clean = 0;
9a799d71 4598 return 0;
e01c31a5
JB		 4599
4600err:
4601 vfree(tx_ring->tx_buffer_info);
4602 tx_ring->tx_buffer_info = NULL;
b6ec895e 4603 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4604 return -ENOMEM;
9a799d71
AK		 4605}
4606
69888674
AD		 4607/**
4608 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4609 * @adapter: board private structure
4610 *
4611 * If this function returns with an error, then it's possible one or
4612 * more of the rings is populated (while the rest are not). It is the
4613 * callers duty to clean those orphaned rings.
4614 *
4615 * Return 0 on success, negative on failure
4616 **/
4617static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4618{
4619 int i, err = 0;
4620
4621 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4622 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4623 if (!err)
4624 continue;
de3d5b94 4625
396e799c 4626 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4627 goto err_setup_tx;
69888674
AD		 4628 }
4629
de3d5b94
AD		 4630 return 0;
4631err_setup_tx:
4632 /* rewind the index freeing the rings as we go */
4633 while (i--)
4634 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4635 return err;
4636}
4637
9a799d71
AK		 4638/**
4639 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4640 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4641 *
4642 * Returns 0 on success, negative on failure
4643 **/
b6ec895e 4644int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4645{
b6ec895e 4646 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4647 int orig_node = dev_to_node(dev);
4648 int numa_node = -1;
021230d4 4649 int size;
9a799d71 4650
3a581073 4651 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4652
4653 if (rx_ring->q_vector)
4654 numa_node = rx_ring->q_vector->numa_node;
4655
4656 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4657 if (!rx_ring->rx_buffer_info)
89bf67f1 4658 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4659 if (!rx_ring->rx_buffer_info)
4660 goto err;
9a799d71 4661
9a799d71 4662 /* Round up to nearest 4K */
3a581073
JB		 4663 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4664 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4665
de88eeeb
AD		 4666 set_dev_node(dev, numa_node);
4667 rx_ring->desc = dma_alloc_coherent(dev,
4668 rx_ring->size,
4669 &rx_ring->dma,
4670 GFP_KERNEL);
4671 set_dev_node(dev, orig_node);
4672 if (!rx_ring->desc)
4673 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4674 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4675 if (!rx_ring->desc)
4676 goto err;
9a799d71 4677
3a581073
JB		 4678 rx_ring->next_to_clean = 0;
4679 rx_ring->next_to_use = 0;
9a799d71
AK		 4680
4681 return 0;
b6ec895e
AD		 4682err:
4683 vfree(rx_ring->rx_buffer_info);
4684 rx_ring->rx_buffer_info = NULL;
4685 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4686 return -ENOMEM;
9a799d71
AK		 4687}
4688
69888674
AD		 4689/**
4690 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4691 * @adapter: board private structure
4692 *
4693 * If this function returns with an error, then it's possible one or
4694 * more of the rings is populated (while the rest are not). It is the
4695 * callers duty to clean those orphaned rings.
4696 *
4697 * Return 0 on success, negative on failure
4698 **/
69888674
AD		 4699static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4700{
4701 int i, err = 0;
4702
4703 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4704 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4705 if (!err)
4706 continue;
de3d5b94 4707
396e799c 4708 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4709 goto err_setup_rx;
69888674
AD		 4710 }
4711
7c8ae65a
AD		 4712#ifdef IXGBE_FCOE
4713 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4714 if (!err)
4715#endif
4716 return 0;
de3d5b94
AD		 4717err_setup_rx:
4718 /* rewind the index freeing the rings as we go */
4719 while (i--)
4720 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4721 return err;
4722}
4723
9a799d71
AK		 4724/**
4725 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4726 * @tx_ring: Tx descriptor ring for a specific queue
4727 *
4728 * Free all transmit software resources
4729 **/
b6ec895e 4730void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4731{
b6ec895e 4732 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4733
4734 vfree(tx_ring->tx_buffer_info);
4735 tx_ring->tx_buffer_info = NULL;
4736
b6ec895e
AD		 4737 /* if not set, then don't free */
4738 if (!tx_ring->desc)
4739 return;
4740
4741 dma_free_coherent(tx_ring->dev, tx_ring->size,
4742 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4743
4744 tx_ring->desc = NULL;
4745}
4746
4747/**
4748 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4749 * @adapter: board private structure
4750 *
4751 * Free all transmit software resources
4752 **/
4753static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4754{
4755 int i;
4756
4757 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4758 if (adapter->tx_ring[i]->desc)
b6ec895e 4759 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4760}
4761
4762/**
b4617240 4763 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4764 * @rx_ring: ring to clean the resources from
4765 *
4766 * Free all receive software resources
4767 **/
b6ec895e 4768void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4769{
b6ec895e 4770 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4771
4772 vfree(rx_ring->rx_buffer_info);
4773 rx_ring->rx_buffer_info = NULL;
4774
b6ec895e
AD		 4775 /* if not set, then don't free */
4776 if (!rx_ring->desc)
4777 return;
4778
4779 dma_free_coherent(rx_ring->dev, rx_ring->size,
4780 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4781
4782 rx_ring->desc = NULL;
4783}
4784
4785/**
4786 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4787 * @adapter: board private structure
4788 *
4789 * Free all receive software resources
4790 **/
4791static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4792{
4793 int i;
4794
7c8ae65a
AD		 4795#ifdef IXGBE_FCOE
4796 ixgbe_free_fcoe_ddp_resources(adapter);
4797
4798#endif
9a799d71 4799 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4800 if (adapter->rx_ring[i]->desc)
b6ec895e 4801 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4802}
4803
9a799d71
AK		 4804/**
4805 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4806 * @netdev: network interface device structure
4807 * @new_mtu: new value for maximum frame size
4808 *
4809 * Returns 0 on success, negative on failure
4810 **/
4811static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4812{
4813 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4814 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4815
42c783c5 4816 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4817 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4818 return -EINVAL;
4819
4820 /*
4821 * For 82599EB we cannot allow PF to change MTU greater than 1500
4822 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4823 * don't allocate and chain buffers correctly.
4824 */
4825 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4826 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4827 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4828 return -EINVAL;
9a799d71 4829
396e799c 4830 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4831
021230d4 4832 /* must set new MTU before calling down or up */
9a799d71
AK		 4833 netdev->mtu = new_mtu;
4834
d4f80882
AV		 4835 if (netif_running(netdev))
4836 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4837
4838 return 0;
4839}
4840
4841/**
4842 * ixgbe_open - Called when a network interface is made active
4843 * @netdev: network interface device structure
4844 *
4845 * Returns 0 on success, negative value on failure
4846 *
4847 * The open entry point is called when a network interface is made
4848 * active by the system (IFF_UP). At this point all resources needed
4849 * for transmit and receive operations are allocated, the interrupt
4850 * handler is registered with the OS, the watchdog timer is started,
4851 * and the stack is notified that the interface is ready.
4852 **/
4853static int ixgbe_open(struct net_device *netdev)
4854{
4855 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4856 int err;
4bebfaa5
AK		 4857
4858 /* disallow open during test */
4859 if (test_bit(__IXGBE_TESTING, &adapter->state))
4860 return -EBUSY;
9a799d71 4861
54386467
JB		 4862 netif_carrier_off(netdev);
4863
9a799d71
AK		 4864 /* allocate transmit descriptors */
4865 err = ixgbe_setup_all_tx_resources(adapter);
4866 if (err)
4867 goto err_setup_tx;
4868
9a799d71
AK		 4869 /* allocate receive descriptors */
4870 err = ixgbe_setup_all_rx_resources(adapter);
4871 if (err)
4872 goto err_setup_rx;
4873
4874 ixgbe_configure(adapter);
4875
021230d4 4876 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4877 if (err)
4878 goto err_req_irq;
4879
ac802f5d
AD		 4880 /* Notify the stack of the actual queue counts. */
4881 err = netif_set_real_num_tx_queues(netdev,
4882 adapter->num_rx_pools > 1 ? 1 :
4883 adapter->num_tx_queues);
4884 if (err)
4885 goto err_set_queues;
4886
4887
4888 err = netif_set_real_num_rx_queues(netdev,
4889 adapter->num_rx_pools > 1 ? 1 :
4890 adapter->num_rx_queues);
4891 if (err)
4892 goto err_set_queues;
4893
c7ccde0f 4894 ixgbe_up_complete(adapter);
9a799d71
AK		 4895
4896 return 0;
4897
ac802f5d
AD		 4898err_set_queues:
4899 ixgbe_free_irq(adapter);
9a799d71 4900err_req_irq:
a20a1199 4901 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4902err_setup_rx:
a20a1199 4903 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4904err_setup_tx:
9a799d71
AK		 4905 ixgbe_reset(adapter);
4906
4907 return err;
4908}
4909
4910/**
4911 * ixgbe_close - Disables a network interface
4912 * @netdev: network interface device structure
4913 *
4914 * Returns 0, this is not allowed to fail
4915 *
4916 * The close entry point is called when an interface is de-activated
4917 * by the OS. The hardware is still under the drivers control, but
4918 * needs to be disabled. A global MAC reset is issued to stop the
4919 * hardware, and all transmit and receive resources are freed.
4920 **/
4921static int ixgbe_close(struct net_device *netdev)
4922{
4923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4924
4925 ixgbe_down(adapter);
4926 ixgbe_free_irq(adapter);
4927
e4911d57
AD		 4928 ixgbe_fdir_filter_exit(adapter);
4929
9a799d71
AK		 4930 ixgbe_free_all_tx_resources(adapter);
4931 ixgbe_free_all_rx_resources(adapter);
4932
5eba3699 4933 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4934
4935 return 0;
4936}
4937
b3c8b4ba
AD		 4938#ifdef CONFIG_PM
4939static int ixgbe_resume(struct pci_dev *pdev)
4940{
c60fbb00
AD		 4941 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4942 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4943 u32 err;
4944
4945 pci_set_power_state(pdev, PCI_D0);
4946 pci_restore_state(pdev);
656ab817
DS		 4947 /*
4948 * pci_restore_state clears dev->state_saved so call
4949 * pci_save_state to restore it.
4950 */
4951 pci_save_state(pdev);
9ce77666 4952
4953 err = pci_enable_device_mem(pdev);
b3c8b4ba 4954 if (err) {
849c4542 4955 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4956 return err;
4957 }
4958 pci_set_master(pdev);
4959
dd4d8ca6 4960 pci_wake_from_d3(pdev, false);
b3c8b4ba 4961
b3c8b4ba
AD		 4962 ixgbe_reset(adapter);
4963
495dce12
WJP		 4964 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4965
ac802f5d
AD		 4966 rtnl_lock();
4967 err = ixgbe_init_interrupt_scheme(adapter);
4968 if (!err && netif_running(netdev))
c60fbb00 4969 err = ixgbe_open(netdev);
ac802f5d
AD		 4970
4971 rtnl_unlock();
4972
4973 if (err)
4974 return err;
b3c8b4ba
AD		 4975
4976 netif_device_attach(netdev);
4977
4978 return 0;
4979}
b3c8b4ba 4980#endif /* CONFIG_PM */
9d8d05ae
RW		 4981
4982static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4983{
c60fbb00
AD		 4984 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4985 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4986 struct ixgbe_hw *hw = &adapter->hw;
4987 u32 ctrl, fctrl;
4988 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4989#ifdef CONFIG_PM
4990 int retval = 0;
4991#endif
4992
4993 netif_device_detach(netdev);
4994
4995 if (netif_running(netdev)) {
ab6039a7 4996 rtnl_lock();
b3c8b4ba
AD		 4997 ixgbe_down(adapter);
4998 ixgbe_free_irq(adapter);
4999 ixgbe_free_all_tx_resources(adapter);
5000 ixgbe_free_all_rx_resources(adapter);
ab6039a7 5001 rtnl_unlock();
b3c8b4ba 5002 }
b3c8b4ba 5003
5f5ae6fc
AD		 5004 ixgbe_clear_interrupt_scheme(adapter);
5005
b3c8b4ba
AD		 5006#ifdef CONFIG_PM
5007 retval = pci_save_state(pdev);
5008 if (retval)
5009 return retval;
4df10466 5010
b3c8b4ba 5011#endif
e8e26350
PW		 5012 if (wufc) {
5013 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5014
c509e754
DS		 5015 /*
5016 * enable the optics for both mult-speed fiber and
5017 * 82599 SFP+ fiber as we can WoL.
5018 */
5019 if (hw->mac.ops.enable_tx_laser &&
5020 (hw->phy.multispeed_fiber ||
5021 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
5022 hw->mac.type == ixgbe_mac_82599EB)))
5023 hw->mac.ops.enable_tx_laser(hw);
5024
e8e26350
PW		 5025 /* turn on all-multi mode if wake on multicast is enabled */
5026 if (wufc & IXGBE_WUFC_MC) {
5027 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5028 fctrl |= IXGBE_FCTRL_MPE;
5029 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5030 }
5031
5032 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5033 ctrl |= IXGBE_CTRL_GIO_DIS;
5034 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5035
5036 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5037 } else {
5038 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5039 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5040 }
5041
bd508178
AD		 5042 switch (hw->mac.type) {
5043 case ixgbe_mac_82598EB:
dd4d8ca6 5044 pci_wake_from_d3(pdev, false);
bd508178
AD		 5045 break;
5046 case ixgbe_mac_82599EB:
b93a2226 5047 case ixgbe_mac_X540:
bd508178
AD		 5048 pci_wake_from_d3(pdev, !!wufc);
5049 break;
5050 default:
5051 break;
5052 }
b3c8b4ba 5053
9d8d05ae
RW		 5054 *enable_wake = !!wufc;
5055
b3c8b4ba
AD		 5056 ixgbe_release_hw_control(adapter);
5057
5058 pci_disable_device(pdev);
5059
9d8d05ae
RW		 5060 return 0;
5061}
5062
5063#ifdef CONFIG_PM
5064static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5065{
5066 int retval;
5067 bool wake;
5068
5069 retval = __ixgbe_shutdown(pdev, &wake);
5070 if (retval)
5071 return retval;
5072
5073 if (wake) {
5074 pci_prepare_to_sleep(pdev);
5075 } else {
5076 pci_wake_from_d3(pdev, false);
5077 pci_set_power_state(pdev, PCI_D3hot);
5078 }
b3c8b4ba
AD		 5079
5080 return 0;
5081}
9d8d05ae 5082#endif /* CONFIG_PM */
b3c8b4ba
AD		 5083
5084static void ixgbe_shutdown(struct pci_dev *pdev)
5085{
9d8d05ae
RW		 5086 bool wake;
5087
5088 __ixgbe_shutdown(pdev, &wake);
5089
5090 if (system_state == SYSTEM_POWER_OFF) {
5091 pci_wake_from_d3(pdev, wake);
5092 pci_set_power_state(pdev, PCI_D3hot);
5093 }
b3c8b4ba
AD		 5094}
5095
9a799d71
AK		 5096/**
5097 * ixgbe_update_stats - Update the board statistics counters.
5098 * @adapter: board private structure
5099 **/
5100void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5101{
2d86f139 5102 struct net_device *netdev = adapter->netdev;
9a799d71 5103 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5104 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5105 u64 total_mpc = 0;
5106 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5107 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5108 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5109 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5110
d08935c2
DS		 5111 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5112 test_bit(__IXGBE_RESETTING, &adapter->state))
5113 return;
5114
94b982b2 5115 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5116 u64 rsc_count = 0;
94b982b2 5117 u64 rsc_flush = 0;
94b982b2 5118 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5119 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5120 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5121 }
5122 adapter->rsc_total_count = rsc_count;
5123 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5124 }
5125
5b7da515
AD		 5126 for (i = 0; i < adapter->num_rx_queues; i++) {
5127 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5128 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5129 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5130 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5131 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5132 bytes += rx_ring->stats.bytes;
5133 packets += rx_ring->stats.packets;
5134 }
5135 adapter->non_eop_descs = non_eop_descs;
5136 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5137 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5138 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5139 netdev->stats.rx_bytes = bytes;
5140 netdev->stats.rx_packets = packets;
5141
5142 bytes = 0;
5143 packets = 0;
7ca3bc58 5144 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5145 for (i = 0; i < adapter->num_tx_queues; i++) {
5146 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5147 restart_queue += tx_ring->tx_stats.restart_queue;
5148 tx_busy += tx_ring->tx_stats.tx_busy;
5149 bytes += tx_ring->stats.bytes;
5150 packets += tx_ring->stats.packets;
5151 }
eb985f09 5152 adapter->restart_queue = restart_queue;
5b7da515
AD		 5153 adapter->tx_busy = tx_busy;
5154 netdev->stats.tx_bytes = bytes;
5155 netdev->stats.tx_packets = packets;
7ca3bc58 5156
7ca647bd 5157 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5158
5159 /* 8 register reads */
6f11eef7
AV		 5160 for (i = 0; i < 8; i++) {
5161 /* for packet buffers not used, the register should read 0 */
5162 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5163 missed_rx += mpc;
7ca647bd
JP		 5164 hwstats->mpc[i] += mpc;
5165 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5166 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5167 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5168 switch (hw->mac.type) {
5169 case ixgbe_mac_82598EB:
1a70db4b
ET		 5170 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5171 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5172 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5173 hwstats->pxonrxc[i] +=
5174 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5175 break;
5176 case ixgbe_mac_82599EB:
b93a2226 5177 case ixgbe_mac_X540:
bd508178
AD		 5178 hwstats->pxonrxc[i] +=
5179 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5180 break;
5181 default:
5182 break;
e8e26350 5183 }
6f11eef7 5184 }
1a70db4b
ET		 5185
5186 /*16 register reads */
5187 for (i = 0; i < 16; i++) {
5188 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5189 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5190 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5191 (hw->mac.type == ixgbe_mac_X540)) {
5192 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5193 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5194 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5195 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5196 }
5197 }
5198
7ca647bd 5199 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5200 /* work around hardware counting issue */
7ca647bd 5201 hwstats->gprc -= missed_rx;
6f11eef7 5202
c84d324c
JF		 5203 ixgbe_update_xoff_received(adapter);
5204
6f11eef7 5205 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5206 switch (hw->mac.type) {
5207 case ixgbe_mac_82598EB:
5208 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5209 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5210 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5211 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5212 break;
b93a2226 5213 case ixgbe_mac_X540:
58f6bcf9
ET		 5214 /* OS2BMC stats are X540 only*/
5215 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5216 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5217 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5218 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5219 case ixgbe_mac_82599EB:
a4d4f629
AD		 5220 for (i = 0; i < 16; i++)
5221 adapter->hw_rx_no_dma_resources +=
5222 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5223 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5224 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5225 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5226 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5227 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5228 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5229 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5230 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5231 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5232#ifdef IXGBE_FCOE
7ca647bd
JP		 5233 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5234 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5235 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5236 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5237 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5238 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5239 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5240 if (adapter->fcoe.ddp_pool) {
5241 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5242 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5243 unsigned int cpu;
5244 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5245 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5246 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5247 noddp += ddp_pool->noddp;
5248 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5249 }
5a1ee270
AD		 5250 hwstats->fcoe_noddp = noddp;
5251 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5252 }
6d45522c 5253#endif /* IXGBE_FCOE */
bd508178
AD		 5254 break;
5255 default:
5256 break;
e8e26350 5257 }
9a799d71 5258 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5259 hwstats->bprc += bprc;
5260 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5261 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5262 hwstats->mprc -= bprc;
5263 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5264 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5265 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5266 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5267 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5268 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5269 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5270 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5271 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5272 hwstats->lxontxc += lxon;
6f11eef7 5273 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5274 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5275 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5276 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5277 /*
5278 * 82598 errata - tx of flow control packets is included in tx counters
5279 */
5280 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5281 hwstats->gptc -= xon_off_tot;
5282 hwstats->mptc -= xon_off_tot;
5283 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5284 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5285 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5286 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5287 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5288 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5289 hwstats->ptc64 -= xon_off_tot;
5290 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5291 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5292 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5293 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5294 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5295 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5296
5297 /* Fill out the OS statistics structure */
7ca647bd 5298 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5299
5300 /* Rx Errors */
7ca647bd 5301 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5302 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5303 netdev->stats.rx_length_errors = hwstats->rlec;
5304 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5305 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5306}
5307
5308/**
d034acf1 5309 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5310 * @adapter: pointer to the device adapter structure
9a799d71 5311 **/
d034acf1 5312static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5313{
cf8280ee 5314 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5315 int i;
cf8280ee 5316
d034acf1
AD		 5317 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5318 return;
5319
5320 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5321
d034acf1 5322 /* if interface is down do nothing */
fe49f04a 5323 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5324 return;
5325
5326 /* do nothing if we are not using signature filters */
5327 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5328 return;
5329
5330 adapter->fdir_overflow++;
5331
93c52dd0
AD		 5332 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5333 for (i = 0; i < adapter->num_tx_queues; i++)
5334 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5335 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5336 /* re-enable flow director interrupts */
5337 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5338 } else {
5339 e_err(probe, "failed to finish FDIR re-initialization, "
5340 "ignored adding FDIR ATR filters\n");
5341 }
93c52dd0
AD		 5342}
5343
5344/**
5345 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5346 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5347 *
5348 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5349 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5350 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5351 * determine if a hang has occurred.
93c52dd0
AD		 5352 */
5353static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5354{
cf8280ee 5355 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5356 u64 eics = 0;
5357 int i;
cf8280ee 5358
93c52dd0
AD		 5359 /* If we're down or resetting, just bail */
5360 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5361 test_bit(__IXGBE_RESETTING, &adapter->state))
5362 return;
22d5a71b 5363
93c52dd0
AD		 5364 /* Force detection of hung controller */
5365 if (netif_carrier_ok(adapter->netdev)) {
5366 for (i = 0; i < adapter->num_tx_queues; i++)
5367 set_check_for_tx_hang(adapter->tx_ring[i]);
5368 }
22d5a71b 5369
fe49f04a
AD		 5370 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5371 /*
5372 * for legacy and MSI interrupts don't set any bits
5373 * that are enabled for EIAM, because this operation
5374 * would set *both* EIMS and EICS for any bit in EIAM
5375 */
5376 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5377 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5378 } else {
5379 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5380 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5381 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5382 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5383 eics |= ((u64)1 << i);
5384 }
cf8280ee 5385 }
9a799d71 5386
93c52dd0 5387 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5388 ixgbe_irq_rearm_queues(adapter, eics);
5389
cf8280ee
JB		 5390}
5391
e8e26350 5392/**
93c52dd0 5393 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5394 * @adapter: pointer to the device adapter structure
5395 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5396 **/
93c52dd0 5397static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5398{
e8e26350 5399 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5400 u32 link_speed = adapter->link_speed;
5401 bool link_up = adapter->link_up;
041441d0 5402 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5403
93c52dd0
AD		 5404 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5405 return;
5406
5407 if (hw->mac.ops.check_link) {
5408 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5409 } else {
93c52dd0
AD		 5410 /* always assume link is up, if no check link function */
5411 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5412 link_up = true;
c4cf55e5 5413 }
041441d0
AD		 5414
5415 if (adapter->ixgbe_ieee_pfc)
5416 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5417
3ebe8fde 5418 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5419 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5420 ixgbe_set_rx_drop_en(adapter);
5421 }
93c52dd0
AD		 5422
5423 if (link_up ||
5424 time_after(jiffies, (adapter->link_check_timeout +
5425 IXGBE_TRY_LINK_TIMEOUT))) {
5426 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5427 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5428 IXGBE_WRITE_FLUSH(hw);
5429 }
5430
5431 adapter->link_up = link_up;
5432 adapter->link_speed = link_speed;
e8e26350
PW		 5433}
5434
5435/**
93c52dd0
AD		 5436 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5437 * print link up message
49ce9c2c 5438 * @adapter: pointer to the device adapter structure
e8e26350 5439 **/
93c52dd0 5440static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5441{
93c52dd0 5442 struct net_device *netdev = adapter->netdev;
e8e26350 5443 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5444 u32 link_speed = adapter->link_speed;
5445 bool flow_rx, flow_tx;
e8e26350 5446
93c52dd0
AD		 5447 /* only continue if link was previously down */
5448 if (netif_carrier_ok(netdev))
a985b6c3 5449 return;
63d6e1d8 5450
93c52dd0 5451 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5452
93c52dd0
AD		 5453 switch (hw->mac.type) {
5454 case ixgbe_mac_82598EB: {
5455 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5456 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5457 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5458 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5459 }
5460 break;
5461 case ixgbe_mac_X540:
5462 case ixgbe_mac_82599EB: {
5463 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5464 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5465 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5466 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5467 }
5468 break;
5469 default:
5470 flow_tx = false;
5471 flow_rx = false;
5472 break;
e8e26350 5473 }
3a6a4eda
JK		 5474
5475#ifdef CONFIG_IXGBE_PTP
5476 ixgbe_ptp_start_cyclecounter(adapter);
5477#endif
5478
93c52dd0
AD		 5479 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5480 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5481 "10 Gbps" :
5482 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5483 "1 Gbps" :
5484 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5485 "100 Mbps" :
5486 "unknown speed"))),
5487 ((flow_rx && flow_tx) ? "RX/TX" :
5488 (flow_rx ? "RX" :
5489 (flow_tx ? "TX" : "None"))));
e8e26350 5490
93c52dd0 5491 netif_carrier_on(netdev);
93c52dd0 5492 ixgbe_check_vf_rate_limit(adapter);
befa2af7
AD		 5493
5494 /* ping all the active vfs to let them know link has changed */
5495 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5496}
5497
c4cf55e5 5498/**
93c52dd0
AD		 5499 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5500 * print link down message
49ce9c2c 5501 * @adapter: pointer to the adapter structure
c4cf55e5 5502 **/
581330ba 5503static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5504{
cf8280ee 5505 struct net_device *netdev = adapter->netdev;
c4cf55e5 5506 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5507
93c52dd0
AD		 5508 adapter->link_up = false;
5509 adapter->link_speed = 0;
cf8280ee 5510
93c52dd0
AD		 5511 /* only continue if link was up previously */
5512 if (!netif_carrier_ok(netdev))
5513 return;
264857b8 5514
93c52dd0
AD		 5515 /* poll for SFP+ cable when link is down */
5516 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5517 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5518
3a6a4eda
JK		 5519#ifdef CONFIG_IXGBE_PTP
5520 ixgbe_ptp_start_cyclecounter(adapter);
5521#endif
5522
93c52dd0
AD		 5523 e_info(drv, "NIC Link is Down\n");
5524 netif_carrier_off(netdev);
befa2af7
AD		 5525
5526 /* ping all the active vfs to let them know link has changed */
5527 ixgbe_ping_all_vfs(adapter);
93c52dd0 5528}
e8e26350 5529
93c52dd0
AD		 5530/**
5531 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5532 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5533 **/
5534static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5535{
c4cf55e5 5536 int i;
93c52dd0 5537 int some_tx_pending = 0;
c4cf55e5 5538
93c52dd0 5539 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5540 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5541 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5542 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5543 some_tx_pending = 1;
5544 break;
5545 }
5546 }
5547
5548 if (some_tx_pending) {
5549 /* We've lost link, so the controller stops DMA,
5550 * but we've got queued Tx work that's never going
5551 * to get done, so reset controller to flush Tx.
5552 * (Do the reset outside of interrupt context).
5553 */
c83c6cbd 5554 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5555 }
c4cf55e5 5556 }
c4cf55e5
PWJ		 5557}
5558
a985b6c3
GR		 5559static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5560{
5561 u32 ssvpc;
5562
5563 /* Do not perform spoof check for 82598 */
5564 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5565 return;
5566
5567 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5568
5569 /*
5570 * ssvpc register is cleared on read, if zero then no
5571 * spoofed packets in the last interval.
5572 */
5573 if (!ssvpc)
5574 return;
5575
5576 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5577}
5578
93c52dd0
AD		 5579/**
5580 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5581 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5582 **/
5583static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5584{
5585 /* if interface is down do nothing */
7edebf9a
ET		 5586 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5587 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5588 return;
5589
5590 ixgbe_watchdog_update_link(adapter);
5591
5592 if (adapter->link_up)
5593 ixgbe_watchdog_link_is_up(adapter);
5594 else
5595 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5596
a985b6c3 5597 ixgbe_spoof_check(adapter);
9a799d71 5598 ixgbe_update_stats(adapter);
93c52dd0
AD		 5599
5600 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5601}
10eec955 5602
cf8280ee 5603/**
7086400d 5604 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5605 * @adapter: the ixgbe adapter structure
cf8280ee 5606 **/
7086400d 5607static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5608{
cf8280ee 5609 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5610 s32 err;
cf8280ee 5611
7086400d
AD		 5612 /* not searching for SFP so there is nothing to do here */
5613 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5614 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5615 return;
10eec955 5616
7086400d
AD		 5617 /* someone else is in init, wait until next service event */
5618 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5619 return;
cf8280ee 5620
7086400d
AD		 5621 err = hw->phy.ops.identify_sfp(hw);
5622 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5623 goto sfp_out;
264857b8 5624
7086400d
AD		 5625 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5626 /* If no cable is present, then we need to reset
5627 * the next time we find a good cable. */
5628 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5629 }
9a799d71 5630
7086400d
AD		 5631 /* exit on error */
5632 if (err)
5633 goto sfp_out;
e8e26350 5634
7086400d
AD		 5635 /* exit if reset not needed */
5636 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5637 goto sfp_out;
9a799d71 5638
7086400d 5639 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5640
7086400d
AD		 5641 /*
5642 * A module may be identified correctly, but the EEPROM may not have
5643 * support for that module. setup_sfp() will fail in that case, so
5644 * we should not allow that module to load.
5645 */
5646 if (hw->mac.type == ixgbe_mac_82598EB)
5647 err = hw->phy.ops.reset(hw);
5648 else
5649 err = hw->mac.ops.setup_sfp(hw);
5650
5651 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5652 goto sfp_out;
5653
5654 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5655 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5656
5657sfp_out:
5658 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5659
5660 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5661 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5662 e_dev_err("failed to initialize because an unsupported "
5663 "SFP+ module type was detected.\n");
5664 e_dev_err("Reload the driver after installing a "
5665 "supported module.\n");
5666 unregister_netdev(adapter->netdev);
bc59fcda 5667 }
7086400d 5668}
bc59fcda 5669
7086400d
AD		 5670/**
5671 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5672 * @adapter: the ixgbe adapter structure
7086400d
AD		 5673 **/
5674static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5675{
5676 struct ixgbe_hw *hw = &adapter->hw;
5677 u32 autoneg;
5678 bool negotiation;
5679
5680 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5681 return;
5682
5683 /* someone else is in init, wait until next service event */
5684 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5685 return;
5686
5687 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5688
5689 autoneg = hw->phy.autoneg_advertised;
5690 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5691 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5692 if (hw->mac.ops.setup_link)
5693 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5694
5695 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5696 adapter->link_check_timeout = jiffies;
5697 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5698}
5699
83c61fa9
GR		 5700#ifdef CONFIG_PCI_IOV
5701static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5702{
5703 int vf;
5704 struct ixgbe_hw *hw = &adapter->hw;
5705 struct net_device *netdev = adapter->netdev;
5706 u32 gpc;
5707 u32 ciaa, ciad;
5708
5709 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5710 if (gpc) /* If incrementing then no need for the check below */
5711 return;
5712 /*
5713 * Check to see if a bad DMA write target from an errant or
5714 * malicious VF has caused a PCIe error. If so then we can
5715 * issue a VFLR to the offending VF(s) and then resume without
5716 * requesting a full slot reset.
5717 */
5718
5719 for (vf = 0; vf < adapter->num_vfs; vf++) {
5720 ciaa = (vf << 16) | 0x80000000;
5721 /* 32 bit read so align, we really want status at offset 6 */
5722 ciaa |= PCI_COMMAND;
5723 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5724 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5725 ciaa &= 0x7FFFFFFF;
5726 /* disable debug mode asap after reading data */
5727 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5728 /* Get the upper 16 bits which will be the PCI status reg */
5729 ciad >>= 16;
5730 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5731 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5732 /* Issue VFLR */
5733 ciaa = (vf << 16) | 0x80000000;
5734 ciaa |= 0xA8;
5735 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5736 ciad = 0x00008000; /* VFLR */
5737 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5738 ciaa &= 0x7FFFFFFF;
5739 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5740 }
5741 }
5742}
5743
5744#endif
7086400d
AD		 5745/**
5746 * ixgbe_service_timer - Timer Call-back
5747 * @data: pointer to adapter cast into an unsigned long
5748 **/
5749static void ixgbe_service_timer(unsigned long data)
5750{
5751 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5752 unsigned long next_event_offset;
83c61fa9 5753 bool ready = true;
7086400d 5754
6bb78cfb
AD		 5755 /* poll faster when waiting for link */
5756 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5757 next_event_offset = HZ / 10;
5758 else
5759 next_event_offset = HZ * 2;
83c61fa9 5760
6bb78cfb 5761#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5762 /*
5763 * don't bother with SR-IOV VF DMA hang check if there are
5764 * no VFs or the link is down
5765 */
5766 if (!adapter->num_vfs ||
6bb78cfb 5767 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5768 goto normal_timer_service;
83c61fa9
GR		 5769
5770 /* If we have VFs allocated then we must check for DMA hangs */
5771 ixgbe_check_for_bad_vf(adapter);
5772 next_event_offset = HZ / 50;
5773 adapter->timer_event_accumulator++;
5774
6bb78cfb 5775 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5776 adapter->timer_event_accumulator = 0;
7086400d 5777 else
6bb78cfb 5778 ready = false;
7086400d 5779
6bb78cfb 5780normal_timer_service:
83c61fa9 5781#endif
7086400d
AD		 5782 /* Reset the timer */
5783 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5784
83c61fa9
GR		 5785 if (ready)
5786 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5787}
5788
c83c6cbd
AD		 5789static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5790{
5791 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5792 return;
5793
5794 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5795
5796 /* If we're already down or resetting, just bail */
5797 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5798 test_bit(__IXGBE_RESETTING, &adapter->state))
5799 return;
5800
5801 ixgbe_dump(adapter);
5802 netdev_err(adapter->netdev, "Reset adapter\n");
5803 adapter->tx_timeout_count++;
5804
5805 ixgbe_reinit_locked(adapter);
5806}
5807
7086400d
AD		 5808/**
5809 * ixgbe_service_task - manages and runs subtasks
5810 * @work: pointer to work_struct containing our data
5811 **/
5812static void ixgbe_service_task(struct work_struct *work)
5813{
5814 struct ixgbe_adapter *adapter = container_of(work,
5815 struct ixgbe_adapter,
5816 service_task);
5817
c83c6cbd 5818 ixgbe_reset_subtask(adapter);
7086400d
AD		 5819 ixgbe_sfp_detection_subtask(adapter);
5820 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5821 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5822 ixgbe_watchdog_subtask(adapter);
d034acf1 5823 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5824 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5825#ifdef CONFIG_IXGBE_PTP
5826 ixgbe_ptp_overflow_check(adapter);
5827#endif
7086400d
AD		 5828
5829 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5830}
5831
fd0db0ed
AD		 5832static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5833 struct ixgbe_tx_buffer *first,
244e27ad 5834 u8 *hdr_len)
897ab156 5835{
fd0db0ed 5836 struct sk_buff *skb = first->skb;
897ab156
AD		 5837 u32 vlan_macip_lens, type_tucmd;
5838 u32 mss_l4len_idx, l4len;
9a799d71 5839
897ab156
AD		 5840 if (!skb_is_gso(skb))
5841 return 0;
9a799d71 5842
897ab156 5843 if (skb_header_cloned(skb)) {
244e27ad 5844 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5845 if (err)
5846 return err;
9a799d71 5847 }
9a799d71 5848
897ab156
AD		 5849 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5850 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5851
244e27ad 5852 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5853 struct iphdr *iph = ip_hdr(skb);
5854 iph->tot_len = 0;
5855 iph->check = 0;
5856 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5857 iph->daddr, 0,
5858 IPPROTO_TCP,
5859 0);
5860 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5861 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5862 IXGBE_TX_FLAGS_CSUM |
5863 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5864 } else if (skb_is_gso_v6(skb)) {
5865 ipv6_hdr(skb)->payload_len = 0;
5866 tcp_hdr(skb)->check =
5867 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5868 &ipv6_hdr(skb)->daddr,
5869 0, IPPROTO_TCP, 0);
244e27ad
AD		 5870 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5871 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5872 }
5873
091a6246 5874 /* compute header lengths */
897ab156
AD		 5875 l4len = tcp_hdrlen(skb);
5876 *hdr_len = skb_transport_offset(skb) + l4len;
5877
091a6246
AD		 5878 /* update gso size and bytecount with header size */
5879 first->gso_segs = skb_shinfo(skb)->gso_segs;
5880 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5881
897ab156
AD		 5882 /* mss_l4len_id: use 1 as index for TSO */
5883 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5884 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5885 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5886
5887 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5888 vlan_macip_lens = skb_network_header_len(skb);
5889 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5890 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5891
5892 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5893 mss_l4len_idx);
897ab156
AD		 5894
5895 return 1;
5896}
5897
244e27ad
AD		 5898static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5899 struct ixgbe_tx_buffer *first)
7ca647bd 5900{
fd0db0ed 5901 struct sk_buff *skb = first->skb;
897ab156
AD		 5902 u32 vlan_macip_lens = 0;
5903 u32 mss_l4len_idx = 0;
5904 u32 type_tucmd = 0;
7ca647bd 5905
897ab156 5906 if (skb->ip_summed != CHECKSUM_PARTIAL) {
244e27ad
AD		 5907 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5908 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5909 return;
897ab156
AD		 5910 } else {
5911 u8 l4_hdr = 0;
244e27ad 5912 switch (first->protocol) {
897ab156
AD		 5913 case __constant_htons(ETH_P_IP):
5914 vlan_macip_lens |= skb_network_header_len(skb);
5915 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5916 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5917 break;
897ab156
AD		 5918 case __constant_htons(ETH_P_IPV6):
5919 vlan_macip_lens |= skb_network_header_len(skb);
5920 l4_hdr = ipv6_hdr(skb)->nexthdr;
5921 break;
5922 default:
5923 if (unlikely(net_ratelimit())) {
5924 dev_warn(tx_ring->dev,
5925 "partial checksum but proto=%x!\n",
244e27ad 5926 first->protocol);
897ab156 5927 }
7ca647bd
JP		 5928 break;
5929 }
897ab156
AD		 5930
5931 switch (l4_hdr) {
7ca647bd 5932 case IPPROTO_TCP:
897ab156
AD		 5933 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5934 mss_l4len_idx = tcp_hdrlen(skb) <<
5935 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5936 break;
5937 case IPPROTO_SCTP:
897ab156
AD		 5938 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5939 mss_l4len_idx = sizeof(struct sctphdr) <<
5940 IXGBE_ADVTXD_L4LEN_SHIFT;
5941 break;
5942 case IPPROTO_UDP:
5943 mss_l4len_idx = sizeof(struct udphdr) <<
5944 IXGBE_ADVTXD_L4LEN_SHIFT;
5945 break;
5946 default:
5947 if (unlikely(net_ratelimit())) {
5948 dev_warn(tx_ring->dev,
5949 "partial checksum but l4 proto=%x!\n",
244e27ad 5950 l4_hdr);
897ab156 5951 }
7ca647bd
JP		 5952 break;
5953 }
244e27ad
AD		 5954
5955 /* update TX checksum flag */
5956 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5957 }
5958
244e27ad 5959 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5960 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5961 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5962
897ab156
AD		 5963 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5964 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5965}
5966
d3d00239 5967static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5968{
d3d00239
AD		 5969 /* set type for advanced descriptor with frame checksum insertion */
5970 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5971 IXGBE_ADVTXD_DCMD_IFCS |
5972 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5973
d3d00239 5974 /* set HW vlan bit if vlan is present */
66f32a8b 5975 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5976 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5977
3a6a4eda
JK		 5978#ifdef CONFIG_IXGBE_PTP
5979 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5980 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5981#endif
5982
d3d00239
AD		 5983 /* set segmentation enable bits for TSO/FSO */
5984#ifdef IXGBE_FCOE
93f5b3c1 5985 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5986#else
5987 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5988#endif
5989 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5990
d3d00239
AD		 5991 return cmd_type;
5992}
9a799d71 5993
729739b7
AD		 5994static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5995 u32 tx_flags, unsigned int paylen)
d3d00239 5996{
93f5b3c1 5997 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 5998
d3d00239
AD		 5999 /* enable L4 checksum for TSO and TX checksum offload */
6000 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6001 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6002
93f5b3c1
AD		 6003 /* enble IPv4 checksum for TSO */
6004 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6005 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6006
93f5b3c1
AD		 6007 /* use index 1 context for TSO/FSO/FCOE */
6008#ifdef IXGBE_FCOE
6009 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6010#else
6011 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 6012#endif
93f5b3c1
AD		 6013 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6014
7f9643fd
AD		 6015 /*
6016 * Check Context must be set if Tx switch is enabled, which it
6017 * always is for case where virtual functions are running
6018 */
93f5b3c1
AD		 6019#ifdef IXGBE_FCOE
6020 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6021#else
7f9643fd 6022 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 6023#endif
7f9643fd
AD		 6024 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6025
729739b7 6026 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 6027}
44df32c5 6028
d3d00239
AD		 6029#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6030 IXGBE_TXD_CMD_RS)
6031
6032static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6033 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6034 const u8 hdr_len)
6035{
729739b7 6036 dma_addr_t dma;
fd0db0ed 6037 struct sk_buff *skb = first->skb;
729739b7 6038 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6039 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6040 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6041 unsigned int data_len = skb->data_len;
6042 unsigned int size = skb_headlen(skb);
729739b7 6043 unsigned int paylen = skb->len - hdr_len;
244e27ad 6044 u32 tx_flags = first->tx_flags;
729739b7 6045 __le32 cmd_type;
d3d00239 6046 u16 i = tx_ring->next_to_use;
d3d00239 6047
729739b7
AD		 6048 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6049
6050 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6051 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6052
d3d00239
AD		 6053#ifdef IXGBE_FCOE
6054 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6055 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6056 size -= sizeof(struct fcoe_crc_eof) - data_len;
6057 data_len = 0;
729739b7
AD		 6058 } else {
6059 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6060 }
6061 }
44df32c5 6062
d3d00239 6063#endif
729739b7
AD		 6064 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6065 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6066 goto dma_error;
8ad494b0 6067
729739b7
AD		 6068 /* record length, and DMA address */
6069 dma_unmap_len_set(first, len, size);
6070 dma_unmap_addr_set(first, dma, dma);
9a799d71 6071
729739b7 6072 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6073
d3d00239 6074 for (;;) {
729739b7 6075 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6076 tx_desc->read.cmd_type_len =
6077 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6078
d3d00239 6079 i++;
729739b7 6080 tx_desc++;
d3d00239 6081 if (i == tx_ring->count) {
e4f74028 6082 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6083 i = 0;
6084 }
729739b7
AD		 6085
6086 dma += IXGBE_MAX_DATA_PER_TXD;
6087 size -= IXGBE_MAX_DATA_PER_TXD;
6088
6089 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6090 tx_desc->read.olinfo_status = 0;
d3d00239 6091 }
e5a43549 6092
729739b7
AD		 6093 if (likely(!data_len))
6094 break;
9a799d71 6095
f43f313e
BG		 6096 if (unlikely(skb->no_fcs))
6097 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239 6098 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6099
729739b7
AD		 6100 i++;
6101 tx_desc++;
6102 if (i == tx_ring->count) {
6103 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6104 i = 0;
6105 }
9a799d71 6106
d3d00239 6107#ifdef IXGBE_FCOE
9e903e08 6108 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6109#else
9e903e08 6110 size = skb_frag_size(frag);
d3d00239
AD		 6111#endif
6112 data_len -= size;
9a799d71 6113
729739b7
AD		 6114 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6115 DMA_TO_DEVICE);
6116 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6117 goto dma_error;
9a799d71 6118
729739b7
AD		 6119 tx_buffer = &tx_ring->tx_buffer_info[i];
6120 dma_unmap_len_set(tx_buffer, len, size);
6121 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6122
729739b7
AD		 6123 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6124 tx_desc->read.olinfo_status = 0;
9a799d71 6125
729739b7
AD		 6126 frag++;
6127 }
9a799d71 6128
729739b7
AD		 6129 /* write last descriptor with RS and EOP bits */
6130 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6131 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6132
091a6246 6133 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6134
d3d00239
AD		 6135 /* set the timestamp */
6136 first->time_stamp = jiffies;
9a799d71
AK		 6137
6138 /*
729739b7
AD		 6139 * Force memory writes to complete before letting h/w know there
6140 * are new descriptors to fetch. (Only applicable for weak-ordered
6141 * memory model archs, such as IA-64).
6142 *
6143 * We also need this memory barrier to make certain all of the
6144 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6145 */
6146 wmb();
6147
d3d00239
AD		 6148 /* set next_to_watch value indicating a packet is present */
6149 first->next_to_watch = tx_desc;
6150
729739b7
AD		 6151 i++;
6152 if (i == tx_ring->count)
6153 i = 0;
6154
6155 tx_ring->next_to_use = i;
6156
d3d00239 6157 /* notify HW of packet */
84ea2591 6158 writel(i, tx_ring->tail);
d3d00239
AD		 6159
6160 return;
6161dma_error:
729739b7 6162 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6163
6164 /* clear dma mappings for failed tx_buffer_info map */
6165 for (;;) {
729739b7
AD		 6166 tx_buffer = &tx_ring->tx_buffer_info[i];
6167 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6168 if (tx_buffer == first)
d3d00239
AD		 6169 break;
6170 if (i == 0)
6171 i = tx_ring->count;
6172 i--;
6173 }
6174
d3d00239 6175 tx_ring->next_to_use = i;
9a799d71
AK		 6176}
6177
fd0db0ed 6178static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6179 struct ixgbe_tx_buffer *first)
69830529
AD		 6180{
6181 struct ixgbe_q_vector *q_vector = ring->q_vector;
6182 union ixgbe_atr_hash_dword input = { .dword = 0 };
6183 union ixgbe_atr_hash_dword common = { .dword = 0 };
6184 union {
6185 unsigned char *network;
6186 struct iphdr *ipv4;
6187 struct ipv6hdr *ipv6;
6188 } hdr;
ee9e0f0b 6189 struct tcphdr *th;
905e4a41 6190 __be16 vlan_id;
c4cf55e5 6191
69830529
AD		 6192 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6193 if (!q_vector)
6194 return;
6195
6196 /* do nothing if sampling is disabled */
6197 if (!ring->atr_sample_rate)
d3ead241 6198 return;
c4cf55e5 6199
69830529 6200 ring->atr_count++;
c4cf55e5 6201
69830529 6202 /* snag network header to get L4 type and address */
fd0db0ed 6203 hdr.network = skb_network_header(first->skb);
69830529
AD		 6204
6205 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6206 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6207 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6208 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6209 hdr.ipv4->protocol != IPPROTO_TCP))
6210 return;
ee9e0f0b 6211
fd0db0ed 6212 th = tcp_hdr(first->skb);
c4cf55e5 6213
66f32a8b
AD		 6214 /* skip this packet since it is invalid or the socket is closing */
6215 if (!th || th->fin)
69830529
AD		 6216 return;
6217
6218 /* sample on all syn packets or once every atr sample count */
6219 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6220 return;
6221
6222 /* reset sample count */
6223 ring->atr_count = 0;
6224
244e27ad 6225 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6226
6227 /*
6228 * src and dst are inverted, think how the receiver sees them
6229 *
6230 * The input is broken into two sections, a non-compressed section
6231 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6232 * is XORed together and stored in the compressed dword.
6233 */
6234 input.formatted.vlan_id = vlan_id;
6235
6236 /*
6237 * since src port and flex bytes occupy the same word XOR them together
6238 * and write the value to source port portion of compressed dword
6239 */
244e27ad 6240 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6241 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6242 else
244e27ad 6243 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6244 common.port.dst ^= th->source;
6245
244e27ad 6246 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6247 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6248 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6249 } else {
6250 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6251 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6252 hdr.ipv6->saddr.s6_addr32[1] ^
6253 hdr.ipv6->saddr.s6_addr32[2] ^
6254 hdr.ipv6->saddr.s6_addr32[3] ^
6255 hdr.ipv6->daddr.s6_addr32[0] ^
6256 hdr.ipv6->daddr.s6_addr32[1] ^
6257 hdr.ipv6->daddr.s6_addr32[2] ^
6258 hdr.ipv6->daddr.s6_addr32[3];
6259 }
c4cf55e5
PWJ		 6260
6261 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6262 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6263 input, common, ring->queue_index);
c4cf55e5
PWJ		 6264}
6265
63544e9c 6266static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6267{
fc77dc3c 6268 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6269 /* Herbert's original patch had:
6270 * smp_mb__after_netif_stop_queue();
6271 * but since that doesn't exist yet, just open code it. */
6272 smp_mb();
6273
6274 /* We need to check again in a case another CPU has just
6275 * made room available. */
7d4987de 6276 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6277 return -EBUSY;
6278
6279 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6280 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6281 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6282 return 0;
6283}
6284
82d4e46e 6285static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6286{
7d4987de 6287 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6288 return 0;
fc77dc3c 6289 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6290}
6291
09a3b1f8
SH		 6292static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6293{
6294 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6295 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6296 smp_processor_id();
56075a98 6297#ifdef IXGBE_FCOE
6440752c 6298 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6299
e5b64635
JF		 6300 if (((protocol == htons(ETH_P_FCOE)) ||
6301 (protocol == htons(ETH_P_FIP))) &&
6302 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6303 struct ixgbe_ring_feature *f;
6304
6305 f = &adapter->ring_feature[RING_F_FCOE];
6306
6307 while (txq >= f->indices)
6308 txq -= f->indices;
e4b317e9 6309 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6310
e5b64635 6311 return txq;
56075a98
JF		 6312 }
6313#endif
6314
fdd3d631
KK		 6315 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6316 while (unlikely(txq >= dev->real_num_tx_queues))
6317 txq -= dev->real_num_tx_queues;
5f715823 6318 return txq;
fdd3d631 6319 }
c4cf55e5 6320
09a3b1f8
SH		 6321 return skb_tx_hash(dev, skb);
6322}
6323
fc77dc3c 6324netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6325 struct ixgbe_adapter *adapter,
6326 struct ixgbe_ring *tx_ring)
9a799d71 6327{
d3d00239 6328 struct ixgbe_tx_buffer *first;
5f715823 6329 int tso;
d3d00239 6330 u32 tx_flags = 0;
a535c30e
AD		 6331#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6332 unsigned short f;
6333#endif
a535c30e 6334 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6335 __be16 protocol = skb->protocol;
63544e9c 6336 u8 hdr_len = 0;
5e09a105 6337
a535c30e
AD		 6338 /*
6339 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6340 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6341 * + 2 desc gap to keep tail from touching head,
6342 * + 1 desc for context descriptor,
6343 * otherwise try next time
6344 */
6345#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6346 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6347 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6348#else
6349 count += skb_shinfo(skb)->nr_frags;
6350#endif
6351 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6352 tx_ring->tx_stats.tx_busy++;
6353 return NETDEV_TX_BUSY;
6354 }
6355
fd0db0ed
AD		 6356 /* record the location of the first descriptor for this packet */
6357 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6358 first->skb = skb;
091a6246
AD		 6359 first->bytecount = skb->len;
6360 first->gso_segs = 1;
fd0db0ed 6361
66f32a8b 6362 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6363 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6364 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6365 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6366 /* else if it is a SW VLAN check the next protocol and store the tag */
6367 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6368 struct vlan_hdr *vhdr, _vhdr;
6369 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6370 if (!vhdr)
6371 goto out_drop;
6372
6373 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6374 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6375 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6376 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6377 }
6378
aa7bd467
JK		 6379 skb_tx_timestamp(skb);
6380
3a6a4eda
JK		 6381#ifdef CONFIG_IXGBE_PTP
6382 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6383 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6384 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6385 }
6386#endif
6387
9e0c5648
AD		 6388#ifdef CONFIG_PCI_IOV
6389 /*
6390 * Use the l2switch_enable flag - would be false if the DMA
6391 * Tx switch had been disabled.
6392 */
6393 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6394 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6395
6396#endif
32701dc2 6397 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6398 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6399 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6400 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6401 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6402 tx_flags |= (skb->priority & 0x7) <<
6403 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6404 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6405 struct vlan_ethhdr *vhdr;
6406 if (skb_header_cloned(skb) &&
6407 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6408 goto out_drop;
6409 vhdr = (struct vlan_ethhdr *)skb->data;
6410 vhdr->h_vlan_TCI = htons(tx_flags >>
6411 IXGBE_TX_FLAGS_VLAN_SHIFT);
6412 } else {
6413 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6414 }
9a799d71 6415 }
eacd73f7 6416
244e27ad
AD		 6417 /* record initial flags and protocol */
6418 first->tx_flags = tx_flags;
6419 first->protocol = protocol;
6420
eacd73f7 6421#ifdef IXGBE_FCOE
66f32a8b
AD		 6422 /* setup tx offload for FCoE */
6423 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6424 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6425 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6426 if (tso < 0)
6427 goto out_drop;
9a799d71 6428
66f32a8b 6429 goto xmit_fcoe;
eacd73f7 6430 }
9a799d71 6431
66f32a8b 6432#endif /* IXGBE_FCOE */
244e27ad 6433 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6434 if (tso < 0)
897ab156 6435 goto out_drop;
244e27ad
AD		 6436 else if (!tso)
6437 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6438
6439 /* add the ATR filter if ATR is on */
6440 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6441 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6442
6443#ifdef IXGBE_FCOE
6444xmit_fcoe:
6445#endif /* IXGBE_FCOE */
244e27ad 6446 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6447
6448 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6449
6450 return NETDEV_TX_OK;
897ab156
AD		 6451
6452out_drop:
fd0db0ed
AD		 6453 dev_kfree_skb_any(first->skb);
6454 first->skb = NULL;
6455
897ab156 6456 return NETDEV_TX_OK;
9a799d71
AK		 6457}
6458
a50c29dd
AD		 6459static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6460 struct net_device *netdev)
84418e3b
AD		 6461{
6462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6463 struct ixgbe_ring *tx_ring;
6464
a50c29dd
AD		 6465 /*
6466 * The minimum packet size for olinfo paylen is 17 so pad the skb
6467 * in order to meet this minimum size requirement.
6468 */
f73332fc
SH		 6469 if (unlikely(skb->len < 17)) {
6470 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6471 return NETDEV_TX_OK;
6472 skb->len = 17;
6473 }
6474
84418e3b 6475 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6476 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6477}
6478
9a799d71
AK		 6479/**
6480 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6481 * @netdev: network interface device structure
6482 * @p: pointer to an address structure
6483 *
6484 * Returns 0 on success, negative on failure
6485 **/
6486static int ixgbe_set_mac(struct net_device *netdev, void *p)
6487{
6488 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6489 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6490 struct sockaddr *addr = p;
6491
6492 if (!is_valid_ether_addr(addr->sa_data))
6493 return -EADDRNOTAVAIL;
6494
6495 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6496 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6497
1d9c0bfd 6498 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6499
6500 return 0;
6501}
6502
6b73e10d
BH		 6503static int
6504ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6505{
6506 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6507 struct ixgbe_hw *hw = &adapter->hw;
6508 u16 value;
6509 int rc;
6510
6511 if (prtad != hw->phy.mdio.prtad)
6512 return -EINVAL;
6513 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6514 if (!rc)
6515 rc = value;
6516 return rc;
6517}
6518
6519static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6520 u16 addr, u16 value)
6521{
6522 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6523 struct ixgbe_hw *hw = &adapter->hw;
6524
6525 if (prtad != hw->phy.mdio.prtad)
6526 return -EINVAL;
6527 return hw->phy.ops.write_reg(hw, addr, devad, value);
6528}
6529
6530static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6531{
6532 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6533
3a6a4eda
JK		 6534 switch (cmd) {
6535#ifdef CONFIG_IXGBE_PTP
6536 case SIOCSHWTSTAMP:
6537 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6538#endif
6539 default:
6540 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6541 }
6b73e10d
BH		 6542}
6543
0365e6e4
PW		 6544/**
6545 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6546 * netdev->dev_addrs
0365e6e4
PW		 6547 * @netdev: network interface device structure
6548 *
6549 * Returns non-zero on failure
6550 **/
6551static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6552{
6553 int err = 0;
6554 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6555 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6556
7fa7c9dc 6557 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6558 rtnl_lock();
7fa7c9dc 6559 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6560 rtnl_unlock();
7fa7c9dc
AD		 6561
6562 /* update SAN MAC vmdq pool selection */
6563 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6564 }
6565 return err;
6566}
6567
6568/**
6569 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6570 * netdev->dev_addrs
0365e6e4
PW		 6571 * @netdev: network interface device structure
6572 *
6573 * Returns non-zero on failure
6574 **/
6575static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6576{
6577 int err = 0;
6578 struct ixgbe_adapter *adapter = netdev_priv(dev);
6579 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6580
6581 if (is_valid_ether_addr(mac->san_addr)) {
6582 rtnl_lock();
6583 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6584 rtnl_unlock();
6585 }
6586 return err;
6587}
6588
9a799d71
AK		 6589#ifdef CONFIG_NET_POLL_CONTROLLER
6590/*
6591 * Polling 'interrupt' - used by things like netconsole to send skbs
6592 * without having to re-enable interrupts. It's not called while
6593 * the interrupt routine is executing.
6594 */
6595static void ixgbe_netpoll(struct net_device *netdev)
6596{
6597 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6598 int i;
9a799d71 6599
1a647bd2
AD		 6600 /* if interface is down do nothing */
6601 if (test_bit(__IXGBE_DOWN, &adapter->state))
6602 return;
6603
9a799d71 6604 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6605 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6606 for (i = 0; i < adapter->num_q_vectors; i++)
6607 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6608 } else {
6609 ixgbe_intr(adapter->pdev->irq, netdev);
6610 }
9a799d71 6611 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6612}
9a799d71 6613
581330ba 6614#endif
de1036b1
ED		 6615static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6616 struct rtnl_link_stats64 *stats)
6617{
6618 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6619 int i;
6620
1a51502b 6621 rcu_read_lock();
de1036b1 6622 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6623 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6624 u64 bytes, packets;
6625 unsigned int start;
6626
1a51502b
ED		 6627 if (ring) {
6628 do {
6629 start = u64_stats_fetch_begin_bh(&ring->syncp);
6630 packets = ring->stats.packets;
6631 bytes = ring->stats.bytes;
6632 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6633 stats->rx_packets += packets;
6634 stats->rx_bytes += bytes;
6635 }
de1036b1 6636 }
1ac9ad13
ED		 6637
6638 for (i = 0; i < adapter->num_tx_queues; i++) {
6639 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6640 u64 bytes, packets;
6641 unsigned int start;
6642
6643 if (ring) {
6644 do {
6645 start = u64_stats_fetch_begin_bh(&ring->syncp);
6646 packets = ring->stats.packets;
6647 bytes = ring->stats.bytes;
6648 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6649 stats->tx_packets += packets;
6650 stats->tx_bytes += bytes;
6651 }
6652 }
1a51502b 6653 rcu_read_unlock();
de1036b1
ED		 6654 /* following stats updated by ixgbe_watchdog_task() */
6655 stats->multicast = netdev->stats.multicast;
6656 stats->rx_errors = netdev->stats.rx_errors;
6657 stats->rx_length_errors = netdev->stats.rx_length_errors;
6658 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6659 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6660 return stats;
6661}
6662
8af3c33f 6663#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6664/**
6665 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6666 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6667 * @tc: number of traffic classes currently enabled
6668 *
6669 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6670 * 802.1Q priority maps to a packet buffer that exists.
6671 */
6672static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6673{
6674 struct ixgbe_hw *hw = &adapter->hw;
6675 u32 reg, rsave;
6676 int i;
6677
6678 /* 82598 have a static priority to TC mapping that can not
6679 * be changed so no validation is needed.
6680 */
6681 if (hw->mac.type == ixgbe_mac_82598EB)
6682 return;
6683
6684 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6685 rsave = reg;
6686
6687 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6688 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6689
6690 /* If up2tc is out of bounds default to zero */
6691 if (up2tc > tc)
6692 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6693 }
6694
6695 if (reg != rsave)
6696 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6697
6698 return;
6699}
6700
02debdc9
AD		 6701/**
6702 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6703 * @adapter: Pointer to adapter struct
6704 *
6705 * Populate the netdev user priority to tc map
6706 */
6707static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6708{
6709 struct net_device *dev = adapter->netdev;
6710 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6711 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6712 u8 prio;
6713
6714 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6715 u8 tc = 0;
6716
6717 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6718 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6719 else if (ets)
6720 tc = ets->prio_tc[prio];
6721
6722 netdev_set_prio_tc_map(dev, prio, tc);
6723 }
6724}
6725
49ce9c2c
BH		 6726/**
6727 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6728 *
6729 * @netdev: net device to configure
6730 * @tc: number of traffic classes to enable
6731 */
6732int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6733{
8b1c0b24
JF		 6734 struct ixgbe_adapter *adapter = netdev_priv(dev);
6735 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6736
8b1c0b24 6737 /* Hardware supports up to 8 traffic classes */
4de2a022 6738 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6739 (hw->mac.type == ixgbe_mac_82598EB &&
6740 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6741 return -EINVAL;
6742
6743 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6744 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6745 * hardware is not flexible enough to do this dynamically.
6746 */
6747 if (netif_running(dev))
6748 ixgbe_close(dev);
6749 ixgbe_clear_interrupt_scheme(adapter);
6750
e7589eab 6751 if (tc) {
8b1c0b24 6752 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6753 ixgbe_set_prio_tc_map(adapter);
6754
e7589eab 6755 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6756
943561d3
AD		 6757 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6758 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6759 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6760 }
e7589eab 6761 } else {
8b1c0b24 6762 netdev_reset_tc(dev);
02debdc9 6763
943561d3
AD		 6764 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6765 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6766
6767 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6768
6769 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6770 adapter->dcb_cfg.pfc_mode_enable = false;
6771 }
6772
8b1c0b24
JF		 6773 ixgbe_init_interrupt_scheme(adapter);
6774 ixgbe_validate_rtr(adapter, tc);
6775 if (netif_running(dev))
6776 ixgbe_open(dev);
6777
6778 return 0;
6779}
de1036b1 6780
8af3c33f 6781#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6782void ixgbe_do_reset(struct net_device *netdev)
6783{
6784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6785
6786 if (netif_running(netdev))
6787 ixgbe_reinit_locked(adapter);
6788 else
6789 ixgbe_reset(adapter);
6790}
6791
c8f44aff 6792static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6793 netdev_features_t features)
082757af
DS		 6794{
6795 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6796
082757af 6797 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6798 if (!(features & NETIF_F_RXCSUM))
6799 features &= ~NETIF_F_LRO;
082757af 6800
567d2de2
AD		 6801 /* Turn off LRO if not RSC capable */
6802 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6803 features &= ~NETIF_F_LRO;
8e2813f5 6804
567d2de2 6805 return features;
082757af
DS		 6806}
6807
c8f44aff 6808static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6809 netdev_features_t features)
082757af
DS		 6810{
6811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6812 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6813 bool need_reset = false;
6814
082757af 6815 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6816 if (!(features & NETIF_F_LRO)) {
6817 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6818 need_reset = true;
567d2de2
AD		 6819 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6820 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6821 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6822 if (adapter->rx_itr_setting == 1 ||
6823 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6824 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6825 need_reset = true;
6826 } else if ((changed ^ features) & NETIF_F_LRO) {
6827 e_info(probe, "rx-usecs set too low, "
6828 "disabling RSC\n");
082757af
DS		 6829 }
6830 }
6831
6832 /*
6833 * Check if Flow Director n-tuple support was enabled or disabled. If
6834 * the state changed, we need to reset.
6835 */
39cb681b
AD		 6836 switch (features & NETIF_F_NTUPLE) {
6837 case NETIF_F_NTUPLE:
567d2de2 6838 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6839 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6840 need_reset = true;
6841
567d2de2
AD		 6842 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6843 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6844 break;
6845 default:
6846 /* turn off perfect filters, enable ATR and reset */
6847 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6848 need_reset = true;
6849
6850 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6851
6852 /* We cannot enable ATR if SR-IOV is enabled */
6853 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6854 break;
6855
6856 /* We cannot enable ATR if we have 2 or more traffic classes */
6857 if (netdev_get_num_tc(netdev) > 1)
6858 break;
6859
6860 /* We cannot enable ATR if RSS is disabled */
6861 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6862 break;
6863
6864 /* A sample rate of 0 indicates ATR disabled */
6865 if (!adapter->atr_sample_rate)
6866 break;
6867
6868 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6869 break;
082757af
DS		 6870 }
6871
146d4cc9
JF		 6872 if (features & NETIF_F_HW_VLAN_RX)
6873 ixgbe_vlan_strip_enable(adapter);
6874 else
6875 ixgbe_vlan_strip_disable(adapter);
6876
3f2d1c0f
BG		 6877 if (changed & NETIF_F_RXALL)
6878 need_reset = true;
6879
567d2de2 6880 netdev->features = features;
082757af
DS		 6881 if (need_reset)
6882 ixgbe_do_reset(netdev);
6883
6884 return 0;
082757af
DS		 6885}
6886
0f4b0add
JF		 6887static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6888 struct net_device *dev,
6889 unsigned char *addr,
6890 u16 flags)
6891{
6892 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6893 int err;
6894
6895 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6896 return -EOPNOTSUPP;
0f4b0add
JF		 6897
6898 if (ndm->ndm_state & NUD_PERMANENT) {
6899 pr_info("%s: FDB only supports static addresses\n",
6900 ixgbe_driver_name);
6901 return -EINVAL;
6902 }
6903
95447461
JF		 6904 if (is_unicast_ether_addr(addr)) {
6905 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6906
6907 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6908 err = dev_uc_add_excl(dev, addr);
0f4b0add 6909 else
95447461
JF		 6910 err = -ENOMEM;
6911 } else if (is_multicast_ether_addr(addr)) {
6912 err = dev_mc_add_excl(dev, addr);
6913 } else {
6914 err = -EINVAL;
0f4b0add
JF		 6915 }
6916
6917 /* Only return duplicate errors if NLM_F_EXCL is set */
6918 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6919 err = 0;
6920
6921 return err;
6922}
6923
6924static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6925 struct net_device *dev,
6926 unsigned char *addr)
6927{
6928 struct ixgbe_adapter *adapter = netdev_priv(dev);
6929 int err = -EOPNOTSUPP;
6930
6931 if (ndm->ndm_state & NUD_PERMANENT) {
6932 pr_info("%s: FDB only supports static addresses\n",
6933 ixgbe_driver_name);
6934 return -EINVAL;
6935 }
6936
6937 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6938 if (is_unicast_ether_addr(addr))
6939 err = dev_uc_del(dev, addr);
6940 else if (is_multicast_ether_addr(addr))
6941 err = dev_mc_del(dev, addr);
6942 else
6943 err = -EINVAL;
6944 }
6945
6946 return err;
6947}
6948
6949static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6950 struct netlink_callback *cb,
6951 struct net_device *dev,
6952 int idx)
6953{
6954 struct ixgbe_adapter *adapter = netdev_priv(dev);
6955
6956 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6957 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6958
6959 return idx;
6960}
6961
0edc3527 6962static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6963 .ndo_open = ixgbe_open,
0edc3527 6964 .ndo_stop = ixgbe_close,
00829823 6965 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6966 .ndo_select_queue = ixgbe_select_queue,
581330ba 6967 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6968 .ndo_validate_addr = eth_validate_addr,
6969 .ndo_set_mac_address = ixgbe_set_mac,
6970 .ndo_change_mtu = ixgbe_change_mtu,
6971 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6972 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6973 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6974 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6975 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6976 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6977 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6978 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6979 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6980 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6981#ifdef CONFIG_IXGBE_DCB
24095aa3 6982 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6983#endif
0edc3527
SH		 6984#ifdef CONFIG_NET_POLL_CONTROLLER
6985 .ndo_poll_controller = ixgbe_netpoll,
6986#endif
332d4a7d
YZ		 6987#ifdef IXGBE_FCOE
6988 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6989 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6990 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6991 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6992 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6993 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6994 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6995#endif /* IXGBE_FCOE */
082757af
DS		 6996 .ndo_set_features = ixgbe_set_features,
6997 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 6998 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6999 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7000 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 7001};
7002
8e2813f5
JK		 7003/**
7004 * ixgbe_wol_supported - Check whether device supports WoL
7005 * @hw: hw specific details
7006 * @device_id: the device ID
7007 * @subdev_id: the subsystem device ID
7008 *
7009 * This function is used by probe and ethtool to determine
7010 * which devices have WoL support
7011 *
7012 **/
7013int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7014 u16 subdevice_id)
7015{
7016 struct ixgbe_hw *hw = &adapter->hw;
7017 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7018 int is_wol_supported = 0;
7019
7020 switch (device_id) {
7021 case IXGBE_DEV_ID_82599_SFP:
7022 /* Only these subdevices could supports WOL */
7023 switch (subdevice_id) {
7024 case IXGBE_SUBDEV_ID_82599_560FLR:
7025 /* only support first port */
7026 if (hw->bus.func != 0)
7027 break;
7028 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7029 case IXGBE_SUBDEV_ID_82599_RNDC:
8e2813f5
JK		 7030 is_wol_supported = 1;
7031 break;
7032 }
7033 break;
7034 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7035 /* All except this subdevice support WOL */
7036 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7037 is_wol_supported = 1;
7038 break;
7039 case IXGBE_DEV_ID_82599_KX4:
7040 is_wol_supported = 1;
7041 break;
7042 case IXGBE_DEV_ID_X540T:
7043 /* check eeprom to see if enabled wol */
7044 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7045 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7046 (hw->bus.func == 0))) {
7047 is_wol_supported = 1;
7048 }
7049 break;
7050 }
7051
7052 return is_wol_supported;
7053}
7054
9a799d71
AK		 7055/**
7056 * ixgbe_probe - Device Initialization Routine
7057 * @pdev: PCI device information struct
7058 * @ent: entry in ixgbe_pci_tbl
7059 *
7060 * Returns 0 on success, negative on failure
7061 *
7062 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7063 * The OS initialization, configuring of the adapter private structure,
7064 * and a hardware reset occur.
7065 **/
7066static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7067 const struct pci_device_id *ent)
9a799d71
AK		 7068{
7069 struct net_device *netdev;
7070 struct ixgbe_adapter *adapter = NULL;
7071 struct ixgbe_hw *hw;
7072 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7073 static int cards_found;
7074 int i, err, pci_using_dac;
289700db 7075 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7076 unsigned int indices = num_possible_cpus();
3f4a6f00 7077 unsigned int dcb_max = 0;
eacd73f7
YZ		 7078#ifdef IXGBE_FCOE
7079 u16 device_caps;
7080#endif
289700db 7081 u32 eec;
9a799d71 7082
bded64a7
AG		 7083 /* Catch broken hardware that put the wrong VF device ID in
7084 * the PCIe SR-IOV capability.
7085 */
7086 if (pdev->is_virtfn) {
7087 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7088 pci_name(pdev), pdev->vendor, pdev->device);
7089 return -EINVAL;
7090 }
7091
9ce77666 7092 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7093 if (err)
7094 return err;
7095
1b507730
NN		 7096 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7097 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7098 pci_using_dac = 1;
7099 } else {
1b507730 7100 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7101 if (err) {
1b507730
NN		 7102 err = dma_set_coherent_mask(&pdev->dev,
7103 DMA_BIT_MASK(32));
9a799d71 7104 if (err) {
b8bc0421
DC		 7105 dev_err(&pdev->dev,
7106 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7107 goto err_dma;
7108 }
7109 }
7110 pci_using_dac = 0;
7111 }
7112
9ce77666 7113 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7114 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7115 if (err) {
b8bc0421
DC		 7116 dev_err(&pdev->dev,
7117 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7118 goto err_pci_reg;
7119 }
7120
19d5afd4 7121 pci_enable_pcie_error_reporting(pdev);
6fabd715 7122
9a799d71 7123 pci_set_master(pdev);
fb3b27bc 7124 pci_save_state(pdev);
9a799d71 7125
e901acd6 7126#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7127 if (ii->mac == ixgbe_mac_82598EB)
7128 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7129 IXGBE_MAX_RSS_INDICES);
7130 else
7131 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7132 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7133#endif
7134
c85a2618
JF		 7135 if (ii->mac == ixgbe_mac_82598EB)
7136 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7137 else
7138 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7139
e901acd6 7140#ifdef IXGBE_FCOE
c85a2618
JF		 7141 indices += min_t(unsigned int, num_possible_cpus(),
7142 IXGBE_MAX_FCOE_INDICES);
7143#endif
3f4a6f00 7144 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7145 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7146 if (!netdev) {
7147 err = -ENOMEM;
7148 goto err_alloc_etherdev;
7149 }
7150
9a799d71
AK		 7151 SET_NETDEV_DEV(netdev, &pdev->dev);
7152
9a799d71 7153 adapter = netdev_priv(netdev);
c60fbb00 7154 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7155
7156 adapter->netdev = netdev;
7157 adapter->pdev = pdev;
7158 hw = &adapter->hw;
7159 hw->back = adapter;
b3f4d599 7160 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7161
05857980 7162 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7163 pci_resource_len(pdev, 0));
9a799d71
AK		 7164 if (!hw->hw_addr) {
7165 err = -EIO;
7166 goto err_ioremap;
7167 }
7168
7169 for (i = 1; i <= 5; i++) {
7170 if (pci_resource_len(pdev, i) == 0)
7171 continue;
7172 }
7173
0edc3527 7174 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7175 ixgbe_set_ethtool_ops(netdev);
9a799d71 7176 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7177 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7178
9a799d71
AK		 7179 adapter->bd_number = cards_found;
7180
9a799d71
AK		 7181 /* Setup hw api */
7182 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7183 hw->mac.type = ii->mac;
9a799d71 7184
c44ade9e
JB		 7185 /* EEPROM */
7186 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7187 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7188 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7189 if (!(eec & (1 << 8)))
7190 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7191
7192 /* PHY */
7193 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7194 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7195 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7196 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7197 hw->phy.mdio.mmds = 0;
7198 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7199 hw->phy.mdio.dev = netdev;
7200 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7201 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7202
8ca783ab 7203 ii->get_invariants(hw);
9a799d71
AK		 7204
7205 /* setup the private structure */
7206 err = ixgbe_sw_init(adapter);
7207 if (err)
7208 goto err_sw_init;
7209
e86bff0e 7210 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7211 switch (adapter->hw.mac.type) {
7212 case ixgbe_mac_82599EB:
7213 case ixgbe_mac_X540:
e86bff0e 7214 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7215 break;
7216 default:
7217 break;
7218 }
e86bff0e 7219
bf069c97
DS		 7220 /*
7221 * If there is a fan on this device and it has failed log the
7222 * failure.
7223 */
7224 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7225 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7226 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7227 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7228 }
7229
8ef78adc
PWJ		 7230 if (allow_unsupported_sfp)
7231 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7232
c44ade9e 7233 /* reset_hw fills in the perm_addr as well */
119fc60a 7234 hw->phy.reset_if_overtemp = true;
c44ade9e 7235 err = hw->mac.ops.reset_hw(hw);
119fc60a 7236 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7237 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7238 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7239 err = 0;
7240 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7241 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7242 "module type was detected.\n");
7243 e_dev_err("Reload the driver after installing a supported "
7244 "module.\n");
04f165ef
PW		 7245 goto err_sw_init;
7246 } else if (err) {
849c4542 7247 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7248 goto err_sw_init;
7249 }
7250
99d74487
AD		 7251#ifdef CONFIG_PCI_IOV
7252 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7253
99d74487 7254#endif
396e799c 7255 netdev->features = NETIF_F_SG |
e8e9f696 7256 NETIF_F_IP_CSUM |
082757af 7257 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7258 NETIF_F_HW_VLAN_TX |
7259 NETIF_F_HW_VLAN_RX |
082757af
DS		 7260 NETIF_F_HW_VLAN_FILTER |
7261 NETIF_F_TSO |
7262 NETIF_F_TSO6 |
082757af
DS		 7263 NETIF_F_RXHASH |
7264 NETIF_F_RXCSUM;
9a799d71 7265
082757af 7266 netdev->hw_features = netdev->features;
ad31c402 7267
58be7666
DS		 7268 switch (adapter->hw.mac.type) {
7269 case ixgbe_mac_82599EB:
7270 case ixgbe_mac_X540:
45a5ead0 7271 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7272 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7273 NETIF_F_NTUPLE;
58be7666
DS		 7274 break;
7275 default:
7276 break;
7277 }
45a5ead0 7278
3f2d1c0f
BG		 7279 netdev->hw_features |= NETIF_F_RXALL;
7280
ad31c402
JK		 7281 netdev->vlan_features |= NETIF_F_TSO;
7282 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7283 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7284 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7285 netdev->vlan_features |= NETIF_F_SG;
7286
01789349 7287 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7288 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7289
7a6b6f51 7290#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7291 netdev->dcbnl_ops = &dcbnl_ops;
7292#endif
7293
eacd73f7 7294#ifdef IXGBE_FCOE
0d551589 7295 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7296 if (hw->mac.ops.get_device_caps) {
7297 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7298 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7299 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7300 }
7c8ae65a
AD		 7301
7302 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7303
a58915c7
AD		 7304 netdev->features |= NETIF_F_FSO |
7305 NETIF_F_FCOE_CRC;
7306
7c8ae65a
AD		 7307 netdev->vlan_features |= NETIF_F_FSO |
7308 NETIF_F_FCOE_CRC |
7309 NETIF_F_FCOE_MTU;
5e09d7f6 7310 }
eacd73f7 7311#endif /* IXGBE_FCOE */
7b872a55 7312 if (pci_using_dac) {
9a799d71 7313 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7314 netdev->vlan_features |= NETIF_F_HIGHDMA;
7315 }
9a799d71 7316
082757af
DS		 7317 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7318 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7319 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7320 netdev->features |= NETIF_F_LRO;
7321
9a799d71 7322 /* make sure the EEPROM is good */
c44ade9e 7323 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7324 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7325 err = -EIO;
35937c05 7326 goto err_sw_init;
9a799d71
AK		 7327 }
7328
7329 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7330 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7331
c44ade9e 7332 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7333 e_dev_err("invalid MAC address\n");
9a799d71 7334 err = -EIO;
35937c05 7335 goto err_sw_init;
9a799d71
AK		 7336 }
7337
7086400d 7338 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7339 (unsigned long) adapter);
9a799d71 7340
7086400d
AD		 7341 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7342 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7343
021230d4
AV		 7344 err = ixgbe_init_interrupt_scheme(adapter);
7345 if (err)
7346 goto err_sw_init;
9a799d71 7347
8e2813f5 7348 /* WOL not supported for all devices */
c23f5b6b 7349 adapter->wol = 0;
8e2813f5
JK		 7350 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7351 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7352 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7353
e8e26350
PW		 7354 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7355
3a6a4eda
JK		 7356#ifdef CONFIG_IXGBE_PTP
7357 ixgbe_ptp_init(adapter);
7358#endif /* CONFIG_IXGBE_PTP*/
7359
15e5209f
ET		 7360 /* save off EEPROM version number */
7361 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7362 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7363
04f165ef
PW		 7364 /* pick up the PCI bus settings for reporting later */
7365 hw->mac.ops.get_bus_info(hw);
7366
9a799d71 7367 /* print bus type/speed/width info */
849c4542 7368 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7369 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7370 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7371 "Unknown"),
7372 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7373 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7374 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7375 "Unknown"),
7376 netdev->dev_addr);
289700db
DS		 7377
7378 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7379 if (err)
9fe93afd 7380 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7381 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7382 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7383 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7384 part_str);
e8e26350 7385 else
289700db
DS		 7386 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7387 hw->mac.type, hw->phy.type, part_str);
9a799d71 7388
e8e26350 7389 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7390 e_dev_warn("PCI-Express bandwidth available for this card is "
7391 "not sufficient for optimal performance.\n");
7392 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7393 "is required.\n");
0c254d86
AK		 7394 }
7395
9a799d71 7396 /* reset the hardware with the new settings */
794caeb2 7397 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7398 if (err == IXGBE_ERR_EEPROM_VERSION) {
7399 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7400 e_dev_warn("This device is a pre-production adapter/LOM. "
7401 "Please be aware there may be issues associated "
7402 "with your hardware. If you are experiencing "
7403 "problems please contact your Intel or hardware "
7404 "representative who provided you with this "
7405 "hardware.\n");
794caeb2 7406 }
9a799d71
AK		 7407 strcpy(netdev->name, "eth%d");
7408 err = register_netdev(netdev);
7409 if (err)
7410 goto err_register;
7411
93d3ce8f
ET		 7412 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7413 if (hw->mac.ops.disable_tx_laser &&
7414 ((hw->phy.multispeed_fiber) ||
7415 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7416 (hw->mac.type == ixgbe_mac_82599EB))))
7417 hw->mac.ops.disable_tx_laser(hw);
7418
54386467
JB		 7419 /* carrier off reporting is important to ethtool even BEFORE open */
7420 netif_carrier_off(netdev);
7421
5dd2d332 7422#ifdef CONFIG_IXGBE_DCA
652f093f 7423 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7424 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7425 ixgbe_setup_dca(adapter);
7426 }
7427#endif
1cdd1ec8 7428 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7429 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7430 for (i = 0; i < adapter->num_vfs; i++)
7431 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7432 }
7433
2466dd9c
JK		 7434 /* firmware requires driver version to be 0xFFFFFFFF
7435 * since os does not support feature
7436 */
9612de92 7437 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7438 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7439 0xFF);
9612de92 7440
0365e6e4
PW		 7441 /* add san mac addr to netdev */
7442 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7443
ea81875a 7444 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7445 cards_found++;
3ca8bc6d 7446
1210982b 7447#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7448 if (ixgbe_sysfs_init(adapter))
7449 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7450#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7451
9a799d71
AK		 7452 return 0;
7453
7454err_register:
5eba3699 7455 ixgbe_release_hw_control(adapter);
7a921c93 7456 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7457err_sw_init:
99d74487 7458 ixgbe_disable_sriov(adapter);
7086400d 7459 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7460 iounmap(hw->hw_addr);
7461err_ioremap:
7462 free_netdev(netdev);
7463err_alloc_etherdev:
e8e9f696
JP		 7464 pci_release_selected_regions(pdev,
7465 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7466err_pci_reg:
7467err_dma:
7468 pci_disable_device(pdev);
7469 return err;
7470}
7471
7472/**
7473 * ixgbe_remove - Device Removal Routine
7474 * @pdev: PCI device information struct
7475 *
7476 * ixgbe_remove is called by the PCI subsystem to alert the driver
7477 * that it should release a PCI device. The could be caused by a
7478 * Hot-Plug event, or because the driver is going to be removed from
7479 * memory.
7480 **/
7481static void __devexit ixgbe_remove(struct pci_dev *pdev)
7482{
c60fbb00
AD		 7483 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7484 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7485
7486 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7487 cancel_work_sync(&adapter->service_task);
9a799d71 7488
3a6a4eda
JK		 7489#ifdef CONFIG_IXGBE_PTP
7490 ixgbe_ptp_stop(adapter);
7491#endif
7492
5dd2d332 7493#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7494 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7495 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7496 dca_remove_requester(&pdev->dev);
7497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7498 }
7499
7500#endif
1210982b 7501#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7502 ixgbe_sysfs_exit(adapter);
1210982b 7503#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7504
0365e6e4
PW		 7505 /* remove the added san mac */
7506 ixgbe_del_sanmac_netdev(netdev);
7507
c4900be0
DS		 7508 if (netdev->reg_state == NETREG_REGISTERED)
7509 unregister_netdev(netdev);
9a799d71 7510
9297127b 7511 ixgbe_disable_sriov(adapter);
1cdd1ec8 7512
7a921c93 7513 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7514
021230d4 7515 ixgbe_release_hw_control(adapter);
9a799d71 7516
2b1588c3
AD		 7517#ifdef CONFIG_DCB
7518 kfree(adapter->ixgbe_ieee_pfc);
7519 kfree(adapter->ixgbe_ieee_ets);
7520
7521#endif
9a799d71 7522 iounmap(adapter->hw.hw_addr);
9ce77666 7523 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7524 IORESOURCE_MEM));
9a799d71 7525
849c4542 7526 e_dev_info("complete\n");
021230d4 7527
9a799d71
AK		 7528 free_netdev(netdev);
7529
19d5afd4 7530 pci_disable_pcie_error_reporting(pdev);
6fabd715 7531
9a799d71
AK		 7532 pci_disable_device(pdev);
7533}
7534
7535/**
7536 * ixgbe_io_error_detected - called when PCI error is detected
7537 * @pdev: Pointer to PCI device
7538 * @state: The current pci connection state
7539 *
7540 * This function is called after a PCI bus error affecting
7541 * this device has been detected.
7542 */
7543static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7544 pci_channel_state_t state)
9a799d71 7545{
c60fbb00
AD		 7546 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7547 struct net_device *netdev = adapter->netdev;
9a799d71 7548
83c61fa9
GR		 7549#ifdef CONFIG_PCI_IOV
7550 struct pci_dev *bdev, *vfdev;
7551 u32 dw0, dw1, dw2, dw3;
7552 int vf, pos;
7553 u16 req_id, pf_func;
7554
7555 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7556 adapter->num_vfs == 0)
7557 goto skip_bad_vf_detection;
7558
7559 bdev = pdev->bus->self;
7560 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7561 bdev = bdev->bus->self;
7562
7563 if (!bdev)
7564 goto skip_bad_vf_detection;
7565
7566 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7567 if (!pos)
7568 goto skip_bad_vf_detection;
7569
7570 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7571 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7572 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7573 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7574
7575 req_id = dw1 >> 16;
7576 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7577 if (!(req_id & 0x0080))
7578 goto skip_bad_vf_detection;
7579
7580 pf_func = req_id & 0x01;
7581 if ((pf_func & 1) == (pdev->devfn & 1)) {
7582 unsigned int device_id;
7583
7584 vf = (req_id & 0x7F) >> 1;
7585 e_dev_err("VF %d has caused a PCIe error\n", vf);
7586 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7587 "%8.8x\tdw3: %8.8x\n",
7588 dw0, dw1, dw2, dw3);
7589 switch (adapter->hw.mac.type) {
7590 case ixgbe_mac_82599EB:
7591 device_id = IXGBE_82599_VF_DEVICE_ID;
7592 break;
7593 case ixgbe_mac_X540:
7594 device_id = IXGBE_X540_VF_DEVICE_ID;
7595 break;
7596 default:
7597 device_id = 0;
7598 break;
7599 }
7600
7601 /* Find the pci device of the offending VF */
36e90319 7602 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7603 while (vfdev) {
7604 if (vfdev->devfn == (req_id & 0xFF))
7605 break;
36e90319 7606 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7607 device_id, vfdev);
7608 }
7609 /*
7610 * There's a slim chance the VF could have been hot plugged,
7611 * so if it is no longer present we don't need to issue the
7612 * VFLR. Just clean up the AER in that case.
7613 */
7614 if (vfdev) {
7615 e_dev_err("Issuing VFLR to VF %d\n", vf);
7616 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7617 }
7618
7619 pci_cleanup_aer_uncorrect_error_status(pdev);
7620 }
7621
7622 /*
7623 * Even though the error may have occurred on the other port
7624 * we still need to increment the vf error reference count for
7625 * both ports because the I/O resume function will be called
7626 * for both of them.
7627 */
7628 adapter->vferr_refcount++;
7629
7630 return PCI_ERS_RESULT_RECOVERED;
7631
7632skip_bad_vf_detection:
7633#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7634 netif_device_detach(netdev);
7635
3044b8d1
BL		 7636 if (state == pci_channel_io_perm_failure)
7637 return PCI_ERS_RESULT_DISCONNECT;
7638
9a799d71
AK		 7639 if (netif_running(netdev))
7640 ixgbe_down(adapter);
7641 pci_disable_device(pdev);
7642
b4617240 7643 /* Request a slot reset. */
9a799d71
AK		 7644 return PCI_ERS_RESULT_NEED_RESET;
7645}
7646
7647/**
7648 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7649 * @pdev: Pointer to PCI device
7650 *
7651 * Restart the card from scratch, as if from a cold-boot.
7652 */
7653static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7654{
c60fbb00 7655 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7656 pci_ers_result_t result;
7657 int err;
9a799d71 7658
9ce77666 7659 if (pci_enable_device_mem(pdev)) {
396e799c 7660 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7661 result = PCI_ERS_RESULT_DISCONNECT;
7662 } else {
7663 pci_set_master(pdev);
7664 pci_restore_state(pdev);
c0e1f68b 7665 pci_save_state(pdev);
9a799d71 7666
dd4d8ca6 7667 pci_wake_from_d3(pdev, false);
9a799d71 7668
6fabd715 7669 ixgbe_reset(adapter);
88512539 7670 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7671 result = PCI_ERS_RESULT_RECOVERED;
7672 }
7673
7674 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7675 if (err) {
849c4542
ET		 7676 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7677 "failed 0x%0x\n", err);
6fabd715
PWJ		 7678 /* non-fatal, continue */
7679 }
9a799d71 7680
6fabd715 7681 return result;
9a799d71
AK		 7682}
7683
7684/**
7685 * ixgbe_io_resume - called when traffic can start flowing again.
7686 * @pdev: Pointer to PCI device
7687 *
7688 * This callback is called when the error recovery driver tells us that
7689 * its OK to resume normal operation.
7690 */
7691static void ixgbe_io_resume(struct pci_dev *pdev)
7692{
c60fbb00
AD		 7693 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7694 struct net_device *netdev = adapter->netdev;
9a799d71 7695
83c61fa9
GR		 7696#ifdef CONFIG_PCI_IOV
7697 if (adapter->vferr_refcount) {
7698 e_info(drv, "Resuming after VF err\n");
7699 adapter->vferr_refcount--;
7700 return;
7701 }
7702
7703#endif
c7ccde0f
AD		 7704 if (netif_running(netdev))
7705 ixgbe_up(adapter);
9a799d71
AK		 7706
7707 netif_device_attach(netdev);
9a799d71
AK		 7708}
7709
7710static struct pci_error_handlers ixgbe_err_handler = {
7711 .error_detected = ixgbe_io_error_detected,
7712 .slot_reset = ixgbe_io_slot_reset,
7713 .resume = ixgbe_io_resume,
7714};
7715
7716static struct pci_driver ixgbe_driver = {
7717 .name = ixgbe_driver_name,
7718 .id_table = ixgbe_pci_tbl,
7719 .probe = ixgbe_probe,
7720 .remove = __devexit_p(ixgbe_remove),
7721#ifdef CONFIG_PM
7722 .suspend = ixgbe_suspend,
7723 .resume = ixgbe_resume,
7724#endif
7725 .shutdown = ixgbe_shutdown,
7726 .err_handler = &ixgbe_err_handler
7727};
7728
7729/**
7730 * ixgbe_init_module - Driver Registration Routine
7731 *
7732 * ixgbe_init_module is the first routine called when the driver is
7733 * loaded. All it does is register with the PCI subsystem.
7734 **/
7735static int __init ixgbe_init_module(void)
7736{
7737 int ret;
c7689578 7738 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7739 pr_info("%s\n", ixgbe_copyright);
9a799d71 7740
5dd2d332 7741#ifdef CONFIG_IXGBE_DCA
bd0362dd 7742 dca_register_notify(&dca_notifier);
bd0362dd 7743#endif
5dd2d332 7744
9a799d71
AK		 7745 ret = pci_register_driver(&ixgbe_driver);
7746 return ret;
7747}
b4617240 7748
9a799d71
AK		 7749module_init(ixgbe_init_module);
7750
7751/**
7752 * ixgbe_exit_module - Driver Exit Cleanup Routine
7753 *
7754 * ixgbe_exit_module is called just before the driver is removed
7755 * from memory.
7756 **/
7757static void __exit ixgbe_exit_module(void)
7758{
5dd2d332 7759#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7760 dca_unregister_notify(&dca_notifier);
7761#endif
9a799d71 7762 pci_unregister_driver(&ixgbe_driver);
1a51502b 7763 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7764}
bd0362dd 7765
5dd2d332 7766#ifdef CONFIG_IXGBE_DCA
bd0362dd 7767static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7768 void *p)
bd0362dd
JC		 7769{
7770 int ret_val;
7771
7772 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7773 __ixgbe_notify_dca);
bd0362dd
JC		 7774
7775 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7776}
b453368d 7777
5dd2d332 7778#endif /* CONFIG_IXGBE_DCA */
849c4542 7779
9a799d71
AK		 7780module_exit(ixgbe_exit_module);
7781
7782/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)