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ixgbe: Look up MAC address in Open Firmware or IDPROM
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
9a799d71 53
c762dff2
MP		 54#ifdef CONFIG_OF
55#include <linux/of_net.h>
56#endif
57
58#ifdef CONFIG_SPARC
59#include <asm/idprom.h>
60#include <asm/prom.h>
61#endif
62
9a799d71
AK		 63#include "ixgbe.h"
64#include "ixgbe_common.h"
ee5f784a 65#include "ixgbe_dcb_82599.h"
1cdd1ec8 66#include "ixgbe_sriov.h"
9a799d71
AK		 67
68char ixgbe_driver_name[] = "ixgbe";
9c8eb720 69static const char ixgbe_driver_string[] =
e8e9f696 70 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 71#ifdef IXGBE_FCOE
ea81875a
NP		 72char ixgbe_default_device_descr[] =
73 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 74#else
75static char ixgbe_default_device_descr[] =
76 "Intel(R) 10 Gigabit Network Connection";
77#endif
f341c4e0 78#define DRV_VERSION "3.19.1-k"
9c8eb720 79const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 80static const char ixgbe_copyright[] =
0391bbe3 81 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 82
83static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 84 [board_82598] = &ixgbe_82598_info,
e8e26350 85 [board_82599] = &ixgbe_82599_info,
fe15e8e1 86 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 87};
88
89/* ixgbe_pci_tbl - PCI Device ID Table
90 *
91 * Wildcard entries (PCI_ANY_ID) should come last
92 * Last entry must be all 0s
93 *
94 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
95 * Class, Class Mask, private data (not used) }
96 */
9baa3c34 97static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 128 /* required last entry */
129 {0, }
130};
131MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
132
5dd2d332 133#ifdef CONFIG_IXGBE_DCA
bd0362dd 134static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 135 void *p);
bd0362dd
JC		 136static struct notifier_block dca_notifier = {
137 .notifier_call = ixgbe_notify_dca,
138 .next = NULL,
139 .priority = 0
140};
141#endif
142
1cdd1ec8
GR		 143#ifdef CONFIG_PCI_IOV
144static unsigned int max_vfs;
145module_param(max_vfs, uint, 0);
e8e9f696 146MODULE_PARM_DESC(max_vfs,
170e8543 147 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 148#endif /* CONFIG_PCI_IOV */
149
8ef78adc
PWJ		 150static unsigned int allow_unsupported_sfp;
151module_param(allow_unsupported_sfp, uint, 0);
152MODULE_PARM_DESC(allow_unsupported_sfp,
153 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
154
b3f4d599 155#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
156static int debug = -1;
157module_param(debug, int, 0);
158MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
159
9a799d71
AK		 160MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
161MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
162MODULE_LICENSE("GPL");
163MODULE_VERSION(DRV_VERSION);
164
14438464
MR		 165static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
166
b8e82001
JK		 167static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
168 u32 reg, u16 *value)
169{
b8e82001
JK		 170 struct pci_dev *parent_dev;
171 struct pci_bus *parent_bus;
172
173 parent_bus = adapter->pdev->bus->parent;
174 if (!parent_bus)
175 return -1;
176
177 parent_dev = parent_bus->self;
178 if (!parent_dev)
179 return -1;
180
c0798edf 181 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 182 return -1;
183
c0798edf 184 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 185 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
186 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
187 return -1;
b8e82001
JK		 188 return 0;
189}
190
191static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
192{
193 struct ixgbe_hw *hw = &adapter->hw;
194 u16 link_status = 0;
195 int err;
196
197 hw->bus.type = ixgbe_bus_type_pci_express;
198
199 /* Get the negotiated link width and speed from PCI config space of the
200 * parent, as this device is behind a switch
201 */
202 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
203
204 /* assume caller will handle error case */
205 if (err)
206 return err;
207
208 hw->bus.width = ixgbe_convert_bus_width(link_status);
209 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
210
211 return 0;
212}
213
e027d1ae
JK		 214/**
215 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
216 * @hw: hw specific details
217 *
218 * This function is used by probe to determine whether a device's PCI-Express
219 * bandwidth details should be gathered from the parent bus instead of from the
220 * device. Used to ensure that various locations all have the correct device ID
221 * checks.
222 */
223static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
224{
225 switch (hw->device_id) {
226 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 227 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 228 return true;
229 default:
230 return false;
231 }
232}
233
234static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
235 int expected_gts)
236{
237 int max_gts = 0;
238 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
239 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
240 struct pci_dev *pdev;
241
242 /* determine whether to use the the parent device
243 */
244 if (ixgbe_pcie_from_parent(&adapter->hw))
245 pdev = adapter->pdev->bus->parent->self;
246 else
247 pdev = adapter->pdev;
248
249 if (pcie_get_minimum_link(pdev, &speed, &width) ||
250 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
251 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
252 return;
253 }
254
255 switch (speed) {
256 case PCIE_SPEED_2_5GT:
257 /* 8b/10b encoding reduces max throughput by 20% */
258 max_gts = 2 * width;
259 break;
260 case PCIE_SPEED_5_0GT:
261 /* 8b/10b encoding reduces max throughput by 20% */
262 max_gts = 4 * width;
263 break;
264 case PCIE_SPEED_8_0GT:
9f0a433c 265 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 266 max_gts = 8 * width;
267 break;
268 default:
269 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
270 return;
271 }
272
273 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
274 max_gts);
275 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
276 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
277 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
278 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
279 "Unknown"),
280 width,
281 (speed == PCIE_SPEED_2_5GT ? "20%" :
282 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 283 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 284 "Unknown"));
285
286 if (max_gts < expected_gts) {
287 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
288 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
289 expected_gts);
290 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
291 }
292}
293
7086400d
AD		 294static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
295{
296 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 297 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 298 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
299 schedule_work(&adapter->service_task);
300}
301
2a1a091c
MR		 302static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
303{
304 struct ixgbe_adapter *adapter = hw->back;
305
306 if (!hw->hw_addr)
307 return;
308 hw->hw_addr = NULL;
309 e_dev_err("Adapter removed\n");
58cf663f
MR		 310 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
311 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 312}
313
f8e2472f 314static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 315{
316 u32 value;
317
318 /* The following check not only optimizes a bit by not
319 * performing a read on the status register when the
320 * register just read was a status register read that
321 * returned IXGBE_FAILED_READ_REG. It also blocks any
322 * potential recursion.
323 */
324 if (reg == IXGBE_STATUS) {
325 ixgbe_remove_adapter(hw);
326 return;
327 }
328 value = ixgbe_read_reg(hw, IXGBE_STATUS);
329 if (value == IXGBE_FAILED_READ_REG)
330 ixgbe_remove_adapter(hw);
331}
332
f8e2472f
MR		 333/**
334 * ixgbe_read_reg - Read from device register
335 * @hw: hw specific details
336 * @reg: offset of register to read
337 *
338 * Returns : value read or IXGBE_FAILED_READ_REG if removed
339 *
340 * This function is used to read device registers. It checks for device
341 * removal by confirming any read that returns all ones by checking the
342 * status register value for all ones. This function avoids reading from
343 * the hardware if a removal was previously detected in which case it
344 * returns IXGBE_FAILED_READ_REG (all ones).
345 */
346u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
347{
348 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
349 u32 value;
350
351 if (ixgbe_removed(reg_addr))
352 return IXGBE_FAILED_READ_REG;
353 value = readl(reg_addr + reg);
354 if (unlikely(value == IXGBE_FAILED_READ_REG))
355 ixgbe_check_remove(hw, reg);
356 return value;
357}
358
14438464
MR		 359static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
360{
361 u16 value;
362
363 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
364 if (value == IXGBE_FAILED_READ_CFG_WORD) {
365 ixgbe_remove_adapter(hw);
366 return true;
367 }
368 return false;
369}
370
371u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
372{
373 struct ixgbe_adapter *adapter = hw->back;
374 u16 value;
375
376 if (ixgbe_removed(hw->hw_addr))
377 return IXGBE_FAILED_READ_CFG_WORD;
378 pci_read_config_word(adapter->pdev, reg, &value);
379 if (value == IXGBE_FAILED_READ_CFG_WORD &&
380 ixgbe_check_cfg_remove(hw, adapter->pdev))
381 return IXGBE_FAILED_READ_CFG_WORD;
382 return value;
383}
384
385#ifdef CONFIG_PCI_IOV
386static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
387{
388 struct ixgbe_adapter *adapter = hw->back;
389 u32 value;
390
391 if (ixgbe_removed(hw->hw_addr))
392 return IXGBE_FAILED_READ_CFG_DWORD;
393 pci_read_config_dword(adapter->pdev, reg, &value);
394 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
395 ixgbe_check_cfg_remove(hw, adapter->pdev))
396 return IXGBE_FAILED_READ_CFG_DWORD;
397 return value;
398}
399#endif /* CONFIG_PCI_IOV */
400
ed19231c
JK		 401void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
402{
403 struct ixgbe_adapter *adapter = hw->back;
404
405 if (ixgbe_removed(hw->hw_addr))
406 return;
407 pci_write_config_word(adapter->pdev, reg, value);
408}
409
7086400d
AD		 410static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
411{
412 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
413
52f33af8 414 /* flush memory to make sure state is correct before next watchdog */
4e857c58 415 smp_mb__before_atomic();
7086400d
AD		 416 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
417}
418
dcd79aeb
TI		 419struct ixgbe_reg_info {
420 u32 ofs;
421 char *name;
422};
423
424static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
425
426 /* General Registers */
427 {IXGBE_CTRL, "CTRL"},
428 {IXGBE_STATUS, "STATUS"},
429 {IXGBE_CTRL_EXT, "CTRL_EXT"},
430
431 /* Interrupt Registers */
432 {IXGBE_EICR, "EICR"},
433
434 /* RX Registers */
435 {IXGBE_SRRCTL(0), "SRRCTL"},
436 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
437 {IXGBE_RDLEN(0), "RDLEN"},
438 {IXGBE_RDH(0), "RDH"},
439 {IXGBE_RDT(0), "RDT"},
440 {IXGBE_RXDCTL(0), "RXDCTL"},
441 {IXGBE_RDBAL(0), "RDBAL"},
442 {IXGBE_RDBAH(0), "RDBAH"},
443
444 /* TX Registers */
445 {IXGBE_TDBAL(0), "TDBAL"},
446 {IXGBE_TDBAH(0), "TDBAH"},
447 {IXGBE_TDLEN(0), "TDLEN"},
448 {IXGBE_TDH(0), "TDH"},
449 {IXGBE_TDT(0), "TDT"},
450 {IXGBE_TXDCTL(0), "TXDCTL"},
451
452 /* List Terminator */
ca8dfe25 453 { .name = NULL }
dcd79aeb
TI		 454};
455
456
457/*
458 * ixgbe_regdump - register printout routine
459 */
460static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
461{
462 int i = 0, j = 0;
463 char rname[16];
464 u32 regs[64];
465
466 switch (reginfo->ofs) {
467 case IXGBE_SRRCTL(0):
468 for (i = 0; i < 64; i++)
469 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
470 break;
471 case IXGBE_DCA_RXCTRL(0):
472 for (i = 0; i < 64; i++)
473 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
474 break;
475 case IXGBE_RDLEN(0):
476 for (i = 0; i < 64; i++)
477 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
478 break;
479 case IXGBE_RDH(0):
480 for (i = 0; i < 64; i++)
481 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
482 break;
483 case IXGBE_RDT(0):
484 for (i = 0; i < 64; i++)
485 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
486 break;
487 case IXGBE_RXDCTL(0):
488 for (i = 0; i < 64; i++)
489 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
490 break;
491 case IXGBE_RDBAL(0):
492 for (i = 0; i < 64; i++)
493 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
494 break;
495 case IXGBE_RDBAH(0):
496 for (i = 0; i < 64; i++)
497 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
498 break;
499 case IXGBE_TDBAL(0):
500 for (i = 0; i < 64; i++)
501 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
502 break;
503 case IXGBE_TDBAH(0):
504 for (i = 0; i < 64; i++)
505 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
506 break;
507 case IXGBE_TDLEN(0):
508 for (i = 0; i < 64; i++)
509 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
510 break;
511 case IXGBE_TDH(0):
512 for (i = 0; i < 64; i++)
513 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
514 break;
515 case IXGBE_TDT(0):
516 for (i = 0; i < 64; i++)
517 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
518 break;
519 case IXGBE_TXDCTL(0):
520 for (i = 0; i < 64; i++)
521 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
522 break;
523 default:
c7689578 524 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 525 IXGBE_READ_REG(hw, reginfo->ofs));
526 return;
527 }
528
529 for (i = 0; i < 8; i++) {
530 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 531 pr_err("%-15s", rname);
dcd79aeb 532 for (j = 0; j < 8; j++)
c7689578
JP		 533 pr_cont(" %08x", regs[i*8+j]);
534 pr_cont("\n");
dcd79aeb
TI		 535 }
536
537}
538
539/*
540 * ixgbe_dump - Print registers, tx-rings and rx-rings
541 */
542static void ixgbe_dump(struct ixgbe_adapter *adapter)
543{
544 struct net_device *netdev = adapter->netdev;
545 struct ixgbe_hw *hw = &adapter->hw;
546 struct ixgbe_reg_info *reginfo;
547 int n = 0;
548 struct ixgbe_ring *tx_ring;
729739b7 549 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 550 union ixgbe_adv_tx_desc *tx_desc;
551 struct my_u0 { u64 a; u64 b; } *u0;
552 struct ixgbe_ring *rx_ring;
553 union ixgbe_adv_rx_desc *rx_desc;
554 struct ixgbe_rx_buffer *rx_buffer_info;
555 u32 staterr;
556 int i = 0;
557
558 if (!netif_msg_hw(adapter))
559 return;
560
561 /* Print netdevice Info */
562 if (netdev) {
563 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 564 pr_info("Device Name state "
dcd79aeb 565 "trans_start last_rx\n");
c7689578
JP		 566 pr_info("%-15s %016lX %016lX %016lX\n",
567 netdev->name,
568 netdev->state,
569 netdev->trans_start,
570 netdev->last_rx);
dcd79aeb
TI		 571 }
572
573 /* Print Registers */
574 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 575 pr_info(" Register Name Value\n");
dcd79aeb
TI		 576 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
577 reginfo->name; reginfo++) {
578 ixgbe_regdump(hw, reginfo);
579 }
580
581 /* Print TX Ring Summary */
582 if (!netdev || !netif_running(netdev))
e90dd264 583 return;
dcd79aeb
TI		 584
585 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 586 pr_info(" %s %s %s %s\n",
587 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
588 "leng", "ntw", "timestamp");
dcd79aeb
TI		 589 for (n = 0; n < adapter->num_tx_queues; n++) {
590 tx_ring = adapter->tx_ring[n];
729739b7 591 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 592 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 593 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 594 (u64)dma_unmap_addr(tx_buffer, dma),
595 dma_unmap_len(tx_buffer, len),
596 tx_buffer->next_to_watch,
597 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 598 }
599
600 /* Print TX Rings */
601 if (!netif_msg_tx_done(adapter))
602 goto rx_ring_summary;
603
604 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
605
606 /* Transmit Descriptor Formats
607 *
39ac868a 608 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 609 * +--------------------------------------------------------------+
610 * 0 | Buffer Address [63:0] |
611 * +--------------------------------------------------------------+
39ac868a 612 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 613 * +--------------------------------------------------------------+
614 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 615 *
616 * 82598 Advanced Transmit Descriptor (Write-Back Format)
617 * +--------------------------------------------------------------+
618 * 0 | RSV [63:0] |
619 * +--------------------------------------------------------------+
620 * 8 | RSV | STA | NXTSEQ |
621 * +--------------------------------------------------------------+
622 * 63 36 35 32 31 0
623 *
624 * 82599+ Advanced Transmit Descriptor
625 * +--------------------------------------------------------------+
626 * 0 | Buffer Address [63:0] |
627 * +--------------------------------------------------------------+
628 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
629 * +--------------------------------------------------------------+
630 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
631 *
632 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
633 * +--------------------------------------------------------------+
634 * 0 | RSV [63:0] |
635 * +--------------------------------------------------------------+
636 * 8 | RSV | STA | RSV |
637 * +--------------------------------------------------------------+
638 * 63 36 35 32 31 0
dcd79aeb
TI		 639 */
640
641 for (n = 0; n < adapter->num_tx_queues; n++) {
642 tx_ring = adapter->tx_ring[n];
c7689578
JP		 643 pr_info("------------------------------------\n");
644 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
645 pr_info("------------------------------------\n");
8ad88e37
JH		 646 pr_info("%s%s %s %s %s %s\n",
647 "T [desc] [address 63:0 ] ",
648 "[PlPOIdStDDt Ln] [bi->dma ] ",
649 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 650
651 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 652 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 653 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 654 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 655 if (dma_unmap_len(tx_buffer, len) > 0) {
656 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
657 i,
658 le64_to_cpu(u0->a),
659 le64_to_cpu(u0->b),
660 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 661 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 662 tx_buffer->next_to_watch,
663 (u64)tx_buffer->time_stamp,
664 tx_buffer->skb);
665 if (i == tx_ring->next_to_use &&
666 i == tx_ring->next_to_clean)
667 pr_cont(" NTC/U\n");
668 else if (i == tx_ring->next_to_use)
669 pr_cont(" NTU\n");
670 else if (i == tx_ring->next_to_clean)
671 pr_cont(" NTC\n");
672 else
673 pr_cont("\n");
674
675 if (netif_msg_pktdata(adapter) &&
676 tx_buffer->skb)
677 print_hex_dump(KERN_INFO, "",
678 DUMP_PREFIX_ADDRESS, 16, 1,
679 tx_buffer->skb->data,
680 dma_unmap_len(tx_buffer, len),
681 true);
682 }
dcd79aeb
TI		 683 }
684 }
685
686 /* Print RX Rings Summary */
687rx_ring_summary:
688 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 689 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 690 for (n = 0; n < adapter->num_rx_queues; n++) {
691 rx_ring = adapter->rx_ring[n];
c7689578
JP		 692 pr_info("%5d %5X %5X\n",
693 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 694 }
695
696 /* Print RX Rings */
697 if (!netif_msg_rx_status(adapter))
e90dd264 698 return;
dcd79aeb
TI		 699
700 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
701
39ac868a
JH		 702 /* Receive Descriptor Formats
703 *
704 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 705 * 63 1 0
706 * +-----------------------------------------------------+
707 * 0 | Packet Buffer Address [63:1] |A0/NSE|
708 * +----------------------------------------------+------+
709 * 8 | Header Buffer Address [63:1] | DD |
710 * +-----------------------------------------------------+
711 *
712 *
39ac868a 713 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 714 *
715 * 63 48 47 32 31 30 21 20 16 15 4 3 0
716 * +------------------------------------------------------+
39ac868a
JH		 717 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
718 * | Packet | IP | | | | Type | Type |
719 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 720 * +------------------------------------------------------+
721 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
722 * +------------------------------------------------------+
723 * 63 48 47 32 31 20 19 0
39ac868a
JH		 724 *
725 * 82599+ Advanced Receive Descriptor (Read) Format
726 * 63 1 0
727 * +-----------------------------------------------------+
728 * 0 | Packet Buffer Address [63:1] |A0/NSE|
729 * +----------------------------------------------+------+
730 * 8 | Header Buffer Address [63:1] | DD |
731 * +-----------------------------------------------------+
732 *
733 *
734 * 82599+ Advanced Receive Descriptor (Write-Back) Format
735 *
736 * 63 48 47 32 31 30 21 20 17 16 4 3 0
737 * +------------------------------------------------------+
738 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
739 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
740 * |/ Flow Dir Flt ID | | | | | |
741 * +------------------------------------------------------+
742 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
743 * +------------------------------------------------------+
744 * 63 48 47 32 31 20 19 0
dcd79aeb 745 */
39ac868a 746
dcd79aeb
TI		 747 for (n = 0; n < adapter->num_rx_queues; n++) {
748 rx_ring = adapter->rx_ring[n];
c7689578
JP		 749 pr_info("------------------------------------\n");
750 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
751 pr_info("------------------------------------\n");
8ad88e37
JH		 752 pr_info("%s%s%s",
753 "R [desc] [ PktBuf A0] ",
754 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 755 "<-- Adv Rx Read format\n");
8ad88e37
JH		 756 pr_info("%s%s%s",
757 "RWB[desc] [PcsmIpSHl PtRs] ",
758 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 759 "<-- Adv Rx Write-Back format\n");
760
761 for (i = 0; i < rx_ring->count; i++) {
762 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 763 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 764 u0 = (struct my_u0 *)rx_desc;
765 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
766 if (staterr & IXGBE_RXD_STAT_DD) {
767 /* Descriptor Done */
c7689578 768 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 769 "%016llX ---------------- %p", i,
770 le64_to_cpu(u0->a),
771 le64_to_cpu(u0->b),
772 rx_buffer_info->skb);
773 } else {
c7689578 774 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 775 "%016llX %016llX %p", i,
776 le64_to_cpu(u0->a),
777 le64_to_cpu(u0->b),
778 (u64)rx_buffer_info->dma,
779 rx_buffer_info->skb);
780
9c50c035
ET		 781 if (netif_msg_pktdata(adapter) &&
782 rx_buffer_info->dma) {
dcd79aeb
TI		 783 print_hex_dump(KERN_INFO, "",
784 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 785 page_address(rx_buffer_info->page) +
786 rx_buffer_info->page_offset,
f800326d 787 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 788 }
789 }
790
791 if (i == rx_ring->next_to_use)
c7689578 792 pr_cont(" NTU\n");
dcd79aeb 793 else if (i == rx_ring->next_to_clean)
c7689578 794 pr_cont(" NTC\n");
dcd79aeb 795 else
c7689578 796 pr_cont("\n");
dcd79aeb
TI		 797
798 }
799 }
dcd79aeb
TI		 800}
801
5eba3699
AV		 802static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
803{
804 u32 ctrl_ext;
805
806 /* Let firmware take over control of h/w */
807 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 809 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 810}
811
812static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
813{
814 u32 ctrl_ext;
815
816 /* Let firmware know the driver has taken over */
817 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
818 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 819 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 820}
9a799d71 821
49ce9c2c 822/**
e8e26350
PW		 823 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
824 * @adapter: pointer to adapter struct
825 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
826 * @queue: queue to map the corresponding interrupt to
827 * @msix_vector: the vector to map to the corresponding queue
828 *
829 */
830static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 831 u8 queue, u8 msix_vector)
9a799d71
AK		 832{
833 u32 ivar, index;
e8e26350
PW		 834 struct ixgbe_hw *hw = &adapter->hw;
835 switch (hw->mac.type) {
836 case ixgbe_mac_82598EB:
837 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
838 if (direction == -1)
839 direction = 0;
840 index = (((direction * 64) + queue) >> 2) & 0x1F;
841 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
842 ivar &= ~(0xFF << (8 * (queue & 0x3)));
843 ivar |= (msix_vector << (8 * (queue & 0x3)));
844 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
845 break;
846 case ixgbe_mac_82599EB:
b93a2226 847 case ixgbe_mac_X540:
9a75a1ac
DS		 848 case ixgbe_mac_X550:
849 case ixgbe_mac_X550EM_x:
e8e26350
PW		 850 if (direction == -1) {
851 /* other causes */
852 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
853 index = ((queue & 1) * 8);
854 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
855 ivar &= ~(0xFF << index);
856 ivar |= (msix_vector << index);
857 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
858 break;
859 } else {
860 /* tx or rx causes */
861 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
862 index = ((16 * (queue & 1)) + (8 * direction));
863 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
864 ivar &= ~(0xFF << index);
865 ivar |= (msix_vector << index);
866 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
867 break;
868 }
869 default:
870 break;
871 }
9a799d71
AK		 872}
873
fe49f04a 874static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 875 u64 qmask)
fe49f04a
AD		 876{
877 u32 mask;
878
bd508178
AD		 879 switch (adapter->hw.mac.type) {
880 case ixgbe_mac_82598EB:
fe49f04a
AD		 881 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 883 break;
884 case ixgbe_mac_82599EB:
b93a2226 885 case ixgbe_mac_X540:
9a75a1ac
DS		 886 case ixgbe_mac_X550:
887 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 888 mask = (qmask & 0xFFFFFFFF);
889 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
890 mask = (qmask >> 32);
891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 892 break;
893 default:
894 break;
fe49f04a
AD		 895 }
896}
897
729739b7
AD		 898void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
899 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 900{
729739b7
AD		 901 if (tx_buffer->skb) {
902 dev_kfree_skb_any(tx_buffer->skb);
903 if (dma_unmap_len(tx_buffer, len))
d3d00239 904 dma_unmap_single(ring->dev,
729739b7
AD		 905 dma_unmap_addr(tx_buffer, dma),
906 dma_unmap_len(tx_buffer, len),
907 DMA_TO_DEVICE);
908 } else if (dma_unmap_len(tx_buffer, len)) {
909 dma_unmap_page(ring->dev,
910 dma_unmap_addr(tx_buffer, dma),
911 dma_unmap_len(tx_buffer, len),
912 DMA_TO_DEVICE);
e5a43549 913 }
729739b7
AD		 914 tx_buffer->next_to_watch = NULL;
915 tx_buffer->skb = NULL;
916 dma_unmap_len_set(tx_buffer, len, 0);
917 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 918}
919
943561d3 920static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 921{
922 struct ixgbe_hw *hw = &adapter->hw;
923 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 924 int i;
943561d3 925 u32 data;
c84d324c 926
943561d3
AD		 927 if ((hw->fc.current_mode != ixgbe_fc_full) &&
928 (hw->fc.current_mode != ixgbe_fc_rx_pause))
929 return;
c84d324c 930
943561d3
AD		 931 switch (hw->mac.type) {
932 case ixgbe_mac_82598EB:
933 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
934 break;
935 default:
936 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
937 }
938 hwstats->lxoffrxc += data;
c84d324c 939
943561d3
AD		 940 /* refill credits (no tx hang) if we received xoff */
941 if (!data)
c84d324c 942 return;
943561d3
AD		 943
944 for (i = 0; i < adapter->num_tx_queues; i++)
945 clear_bit(__IXGBE_HANG_CHECK_ARMED,
946 &adapter->tx_ring[i]->state);
947}
948
949static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
950{
951 struct ixgbe_hw *hw = &adapter->hw;
952 struct ixgbe_hw_stats *hwstats = &adapter->stats;
953 u32 xoff[8] = {0};
2afaa00d 954 u8 tc;
943561d3
AD		 955 int i;
956 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
957
958 if (adapter->ixgbe_ieee_pfc)
959 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
960
961 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
962 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 963 return;
943561d3 964 }
c84d324c
JF		 965
966 /* update stats for each tc, only valid with PFC enabled */
967 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 968 u32 pxoffrxc;
969
c84d324c
JF		 970 switch (hw->mac.type) {
971 case ixgbe_mac_82598EB:
2afaa00d 972 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 973 break;
c84d324c 974 default:
2afaa00d 975 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 976 }
2afaa00d
PN		 977 hwstats->pxoffrxc[i] += pxoffrxc;
978 /* Get the TC for given UP */
979 tc = netdev_get_prio_tc_map(adapter->netdev, i);
980 xoff[tc] += pxoffrxc;
c84d324c
JF		 981 }
982
983 /* disarm tx queues that have received xoff frames */
984 for (i = 0; i < adapter->num_tx_queues; i++) {
985 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 986
2afaa00d 987 tc = tx_ring->dcb_tc;
c84d324c
JF		 988 if (xoff[tc])
989 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 990 }
26f23d82
YZ		 991}
992
c84d324c 993static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 994{
7d7ce682 995 return ring->stats.packets;
c84d324c
JF		 996}
997
998static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
999{
2a47fa45
JF		 1000 struct ixgbe_adapter *adapter;
1001 struct ixgbe_hw *hw;
1002 u32 head, tail;
1003
1004 if (ring->l2_accel_priv)
1005 adapter = ring->l2_accel_priv->real_adapter;
1006 else
1007 adapter = netdev_priv(ring->netdev);
e01c31a5 1008
2a47fa45
JF		 1009 hw = &adapter->hw;
1010 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1011 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1012
1013 if (head != tail)
1014 return (head < tail) ?
1015 tail - head : (tail + ring->count - head);
1016
1017 return 0;
1018}
1019
1020static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1021{
1022 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1023 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1024 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1025
7d637bcc 1026 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1027
1028 /*
1029 * Check for a hung queue, but be thorough. This verifies
1030 * that a transmit has been completed since the previous
1031 * check AND there is at least one packet pending. The
1032 * ARMED bit is set to indicate a potential hang. The
1033 * bit is cleared if a pause frame is received to remove
1034 * false hang detection due to PFC or 802.3x frames. By
1035 * requiring this to fail twice we avoid races with
1036 * pfc clearing the ARMED bit and conditions where we
1037 * run the check_tx_hang logic with a transmit completion
1038 * pending but without time to complete it yet.
1039 */
e90dd264 1040 if (tx_done_old == tx_done && tx_pending)
c84d324c 1041 /* make sure it is true for two checks in a row */
e90dd264
MR		 1042 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1043 &tx_ring->state);
1044 /* update completed stats and continue */
1045 tx_ring->tx_stats.tx_done_old = tx_done;
1046 /* reset the countdown */
1047 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1048
e90dd264 1049 return false;
9a799d71
AK		 1050}
1051
c83c6cbd
AD		 1052/**
1053 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1054 * @adapter: driver private struct
1055 **/
1056static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1057{
1058
1059 /* Do the reset outside of interrupt context */
1060 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1061 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1062 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1063 ixgbe_service_event_schedule(adapter);
1064 }
1065}
e01c31a5 1066
9a799d71
AK		 1067/**
1068 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1069 * @q_vector: structure containing interrupt and ring information
e01c31a5 1070 * @tx_ring: tx ring to clean
9a799d71 1071 **/
fe49f04a 1072static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1073 struct ixgbe_ring *tx_ring)
9a799d71 1074{
fe49f04a 1075 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1076 struct ixgbe_tx_buffer *tx_buffer;
1077 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1078 unsigned int total_bytes = 0, total_packets = 0;
59224555 1079 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1080 unsigned int i = tx_ring->next_to_clean;
1081
1082 if (test_bit(__IXGBE_DOWN, &adapter->state))
1083 return true;
9a799d71 1084
d3d00239 1085 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1086 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1087 i -= tx_ring->count;
12207e49 1088
729739b7 1089 do {
d3d00239
AD		 1090 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1091
1092 /* if next_to_watch is not set then there is no work pending */
1093 if (!eop_desc)
1094 break;
1095
7f83a9e6 1096 /* prevent any other reads prior to eop_desc */
7e63bf49 1097 read_barrier_depends();
7f83a9e6 1098
d3d00239
AD		 1099 /* if DD is not set pending work has not been completed */
1100 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1101 break;
8ad494b0 1102
d3d00239
AD		 1103 /* clear next_to_watch to prevent false hangs */
1104 tx_buffer->next_to_watch = NULL;
8ad494b0 1105
091a6246
AD		 1106 /* update the statistics for this packet */
1107 total_bytes += tx_buffer->bytecount;
1108 total_packets += tx_buffer->gso_segs;
1109
fd0db0ed 1110 /* free the skb */
fe1f2a97 1111 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1112
729739b7
AD		 1113 /* unmap skb header data */
1114 dma_unmap_single(tx_ring->dev,
1115 dma_unmap_addr(tx_buffer, dma),
1116 dma_unmap_len(tx_buffer, len),
1117 DMA_TO_DEVICE);
1118
fd0db0ed
AD		 1119 /* clear tx_buffer data */
1120 tx_buffer->skb = NULL;
729739b7 1121 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1122
729739b7
AD		 1123 /* unmap remaining buffers */
1124 while (tx_desc != eop_desc) {
d3d00239
AD		 1125 tx_buffer++;
1126 tx_desc++;
8ad494b0 1127 i++;
729739b7
AD		 1128 if (unlikely(!i)) {
1129 i -= tx_ring->count;
d3d00239 1130 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1131 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1132 }
e01c31a5 1133
729739b7
AD		 1134 /* unmap any remaining paged data */
1135 if (dma_unmap_len(tx_buffer, len)) {
1136 dma_unmap_page(tx_ring->dev,
1137 dma_unmap_addr(tx_buffer, dma),
1138 dma_unmap_len(tx_buffer, len),
1139 DMA_TO_DEVICE);
1140 dma_unmap_len_set(tx_buffer, len, 0);
1141 }
1142 }
1143
1144 /* move us one more past the eop_desc for start of next pkt */
1145 tx_buffer++;
1146 tx_desc++;
1147 i++;
1148 if (unlikely(!i)) {
1149 i -= tx_ring->count;
1150 tx_buffer = tx_ring->tx_buffer_info;
1151 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1152 }
1153
1154 /* issue prefetch for next Tx descriptor */
1155 prefetch(tx_desc);
12207e49 1156
729739b7
AD		 1157 /* update budget accounting */
1158 budget--;
1159 } while (likely(budget));
1160
1161 i += tx_ring->count;
9a799d71 1162 tx_ring->next_to_clean = i;
d3d00239 1163 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1164 tx_ring->stats.bytes += total_bytes;
bd198058 1165 tx_ring->stats.packets += total_packets;
d3d00239 1166 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1167 q_vector->tx.total_bytes += total_bytes;
1168 q_vector->tx.total_packets += total_packets;
b953799e 1169
c84d324c
JF		 1170 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1171 /* schedule immediate reset if we believe we hung */
1172 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1173 e_err(drv, "Detected Tx Unit Hang\n"
1174 " Tx Queue <%d>\n"
1175 " TDH, TDT <%x>, <%x>\n"
1176 " next_to_use <%x>\n"
1177 " next_to_clean <%x>\n"
1178 "tx_buffer_info[next_to_clean]\n"
1179 " time_stamp <%lx>\n"
1180 " jiffies <%lx>\n",
1181 tx_ring->queue_index,
1182 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1183 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1184 tx_ring->next_to_use, i,
1185 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1186
1187 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1188
1189 e_info(probe,
1190 "tx hang %d detected on queue %d, resetting adapter\n",
1191 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1192
b953799e 1193 /* schedule immediate reset if we believe we hung */
c83c6cbd 1194 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1195
1196 /* the adapter is about to reset, no point in enabling stuff */
59224555 1197 return true;
b953799e 1198 }
9a799d71 1199
b2d96e0a
AD		 1200 netdev_tx_completed_queue(txring_txq(tx_ring),
1201 total_packets, total_bytes);
1202
e092be60 1203#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1204 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1205 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1206 /* Make sure that anybody stopping the queue after this
1207 * sees the new next_to_clean.
1208 */
1209 smp_mb();
729739b7
AD		 1210 if (__netif_subqueue_stopped(tx_ring->netdev,
1211 tx_ring->queue_index)
1212 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1213 netif_wake_subqueue(tx_ring->netdev,
1214 tx_ring->queue_index);
5b7da515 1215 ++tx_ring->tx_stats.restart_queue;
30eba97a 1216 }
e092be60 1217 }
9a799d71 1218
59224555 1219 return !!budget;
9a799d71
AK		 1220}
1221
5dd2d332 1222#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1223static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1224 struct ixgbe_ring *tx_ring,
33cf09c9 1225 int cpu)
bd0362dd 1226{
33cf09c9 1227 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1228 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1229 u16 reg_offset;
33cf09c9 1230
33cf09c9
AD		 1231 switch (hw->mac.type) {
1232 case ixgbe_mac_82598EB:
bdda1a61 1233 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1234 break;
1235 case ixgbe_mac_82599EB:
b93a2226 1236 case ixgbe_mac_X540:
bdda1a61
AD		 1237 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1238 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1239 break;
1240 default:
bdda1a61
AD		 1241 /* for unknown hardware do not write register */
1242 return;
bd0362dd 1243 }
bdda1a61
AD		 1244
1245 /*
1246 * We can enable relaxed ordering for reads, but not writes when
1247 * DCA is enabled. This is due to a known issue in some chipsets
1248 * which will cause the DCA tag to be cleared.
1249 */
1250 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1251 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1252 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1253
1254 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1255}
1256
bdda1a61
AD		 1257static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1258 struct ixgbe_ring *rx_ring,
33cf09c9 1259 int cpu)
bd0362dd 1260{
33cf09c9 1261 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1262 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1263 u8 reg_idx = rx_ring->reg_idx;
1264
33cf09c9
AD		 1265
1266 switch (hw->mac.type) {
33cf09c9 1267 case ixgbe_mac_82599EB:
b93a2226 1268 case ixgbe_mac_X540:
bdda1a61 1269 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1270 break;
1271 default:
1272 break;
1273 }
bdda1a61
AD		 1274
1275 /*
1276 * We can enable relaxed ordering for reads, but not writes when
1277 * DCA is enabled. This is due to a known issue in some chipsets
1278 * which will cause the DCA tag to be cleared.
1279 */
1280 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1281 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1282
1283 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1284}
1285
1286static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1287{
1288 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1289 struct ixgbe_ring *ring;
bd0362dd 1290 int cpu = get_cpu();
bd0362dd 1291
33cf09c9
AD		 1292 if (q_vector->cpu == cpu)
1293 goto out_no_update;
1294
a557928e 1295 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1296 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1297
a557928e 1298 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1299 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1300
1301 q_vector->cpu = cpu;
1302out_no_update:
bd0362dd
JC		 1303 put_cpu();
1304}
1305
1306static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1307{
1308 int i;
1309
1310 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1311 return;
1312
e35ec126
AD		 1313 /* always use CB2 mode, difference is masked in the CB driver */
1314 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1315
49c7ffbe 1316 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1317 adapter->q_vector[i]->cpu = -1;
1318 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1319 }
1320}
1321
1322static int __ixgbe_notify_dca(struct device *dev, void *data)
1323{
c60fbb00 1324 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1325 unsigned long event = *(unsigned long *)data;
1326
2a72c31e 1327 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1328 return 0;
1329
bd0362dd
JC		 1330 switch (event) {
1331 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1332 /* if we're already enabled, don't do it again */
1333 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1334 break;
652f093f 1335 if (dca_add_requester(dev) == 0) {
96b0e0f6 1336 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1337 ixgbe_setup_dca(adapter);
1338 break;
1339 }
1340 /* Fall Through since DCA is disabled. */
1341 case DCA_PROVIDER_REMOVE:
1342 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1343 dca_remove_requester(dev);
1344 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1345 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1346 }
1347 break;
1348 }
1349
652f093f 1350 return 0;
bd0362dd 1351}
67a74ee2 1352
bdda1a61 1353#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1354static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1355 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1356 struct sk_buff *skb)
1357{
8a0da21b 1358 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1359 skb_set_hash(skb,
1360 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1361 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1362}
1363
f800326d 1364#ifdef IXGBE_FCOE
ff886dfc
AD		 1365/**
1366 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1367 * @ring: structure containing ring specific data
ff886dfc
AD		 1368 * @rx_desc: advanced rx descriptor
1369 *
1370 * Returns : true if it is FCoE pkt
1371 */
57efd44c 1372static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1373 union ixgbe_adv_rx_desc *rx_desc)
1374{
1375 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1376
57efd44c 1377 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1378 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1379 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1380 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1381}
1382
f800326d 1383#endif /* IXGBE_FCOE */
e59bd25d
AV		 1384/**
1385 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1386 * @ring: structure containing ring specific data
1387 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1388 * @skb: skb currently being received and modified
1389 **/
8a0da21b 1390static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1391 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1392 struct sk_buff *skb)
9a799d71 1393{
8a0da21b 1394 skb_checksum_none_assert(skb);
9a799d71 1395
712744be 1396 /* Rx csum disabled */
8a0da21b 1397 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1398 return;
e59bd25d
AV		 1399
1400 /* if IP and error */
f56e0cb1
AD		 1401 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1402 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1403 ring->rx_stats.csum_err++;
9a799d71
AK		 1404 return;
1405 }
e59bd25d 1406
f56e0cb1 1407 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1408 return;
1409
f56e0cb1 1410 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1411 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1412
1413 /*
1414 * 82599 errata, UDP frames with a 0 checksum can be marked as
1415 * checksum errors.
1416 */
8a0da21b
AD		 1417 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1418 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1419 return;
1420
8a0da21b 1421 ring->rx_stats.csum_err++;
e59bd25d
AV		 1422 return;
1423 }
1424
9a799d71 1425 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1426 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1427}
1428
f990b79b
AD		 1429static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1430 struct ixgbe_rx_buffer *bi)
1431{
1432 struct page *page = bi->page;
18cb652a 1433 dma_addr_t dma;
f990b79b 1434
f800326d 1435 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1436 if (likely(page))
f990b79b
AD		 1437 return true;
1438
f800326d 1439 /* alloc new page for storage */
18cb652a
AD		 1440 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1441 if (unlikely(!page)) {
1442 rx_ring->rx_stats.alloc_rx_page_failed++;
1443 return false;
f990b79b
AD		 1444 }
1445
f800326d
AD		 1446 /* map page for use */
1447 dma = dma_map_page(rx_ring->dev, page, 0,
1448 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1449
1450 /*
1451 * if mapping failed free memory back to system since
1452 * there isn't much point in holding memory we can't use
1453 */
1454 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1455 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1456
f990b79b
AD		 1457 rx_ring->rx_stats.alloc_rx_page_failed++;
1458 return false;
1459 }
1460
f800326d 1461 bi->dma = dma;
18cb652a 1462 bi->page = page;
afaa9459 1463 bi->page_offset = 0;
f800326d 1464
f990b79b
AD		 1465 return true;
1466}
1467
9a799d71 1468/**
f990b79b 1469 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1470 * @rx_ring: ring to place buffers on
1471 * @cleaned_count: number of buffers to replace
9a799d71 1472 **/
fc77dc3c 1473void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1474{
9a799d71 1475 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1476 struct ixgbe_rx_buffer *bi;
d5f398ed 1477 u16 i = rx_ring->next_to_use;
9a799d71 1478
f800326d
AD		 1479 /* nothing to do */
1480 if (!cleaned_count)
fc77dc3c
AD		 1481 return;
1482
e4f74028 1483 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1484 bi = &rx_ring->rx_buffer_info[i];
1485 i -= rx_ring->count;
9a799d71 1486
f800326d
AD		 1487 do {
1488 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1489 break;
d5f398ed 1490
f800326d
AD		 1491 /*
1492 * Refresh the desc even if buffer_addrs didn't change
1493 * because each write-back erases this info.
1494 */
1495 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1496
f990b79b
AD		 1497 rx_desc++;
1498 bi++;
9a799d71 1499 i++;
f990b79b 1500 if (unlikely(!i)) {
e4f74028 1501 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1502 bi = rx_ring->rx_buffer_info;
1503 i -= rx_ring->count;
1504 }
1505
18cb652a
AD		 1506 /* clear the status bits for the next_to_use descriptor */
1507 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1508
1509 cleaned_count--;
1510 } while (cleaned_count);
7c6e0a43 1511
f990b79b
AD		 1512 i += rx_ring->count;
1513
ad435ec6
AD		 1514 if (rx_ring->next_to_use != i) {
1515 rx_ring->next_to_use = i;
1516
1517 /* update next to alloc since we have filled the ring */
1518 rx_ring->next_to_alloc = i;
1519
1520 /* Force memory writes to complete before letting h/w
1521 * know there are new descriptors to fetch. (Only
1522 * applicable for weak-ordered memory model archs,
1523 * such as IA-64).
1524 */
1525 wmb();
1526 writel(i, rx_ring->tail);
1527 }
9a799d71
AK		 1528}
1529
1d2024f6
AD		 1530static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1531 struct sk_buff *skb)
1532{
f800326d 1533 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1534
1535 /* set gso_size to avoid messing up TCP MSS */
1536 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1537 IXGBE_CB(skb)->append_cnt);
96be80ab 1538 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1539}
1540
1541static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1542 struct sk_buff *skb)
1543{
1544 /* if append_cnt is 0 then frame is not RSC */
1545 if (!IXGBE_CB(skb)->append_cnt)
1546 return;
1547
1548 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1549 rx_ring->rx_stats.rsc_flush++;
1550
1551 ixgbe_set_rsc_gso_size(rx_ring, skb);
1552
1553 /* gso_size is computed using append_cnt so always clear it last */
1554 IXGBE_CB(skb)->append_cnt = 0;
1555}
1556
8a0da21b
AD		 1557/**
1558 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1559 * @rx_ring: rx descriptor ring packet is being transacted on
1560 * @rx_desc: pointer to the EOP Rx descriptor
1561 * @skb: pointer to current skb being populated
f8212f97 1562 *
8a0da21b
AD		 1563 * This function checks the ring, descriptor, and packet information in
1564 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1565 * other fields within the skb.
f8212f97 1566 **/
8a0da21b
AD		 1567static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1568 union ixgbe_adv_rx_desc *rx_desc,
1569 struct sk_buff *skb)
f8212f97 1570{
43e95f11
JF		 1571 struct net_device *dev = rx_ring->netdev;
1572
8a0da21b
AD		 1573 ixgbe_update_rsc_stats(rx_ring, skb);
1574
1575 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1576
8a0da21b
AD		 1577 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1578
eda183c2
JK		 1579 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1580 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1581
f646968f 1582 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1583 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1584 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1585 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1586 }
1587
8a0da21b 1588 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1589
43e95f11 1590 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1591}
1592
8a0da21b
AD		 1593static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1594 struct sk_buff *skb)
aa80175a 1595{
8a0da21b
AD		 1596 struct ixgbe_adapter *adapter = q_vector->adapter;
1597
b4640030 1598 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1599 netif_receive_skb(skb);
1600 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1601 napi_gro_receive(&q_vector->napi, skb);
1602 else
1603 netif_rx(skb);
aa80175a 1604}
43634e82 1605
f800326d
AD		 1606/**
1607 * ixgbe_is_non_eop - process handling of non-EOP buffers
1608 * @rx_ring: Rx ring being processed
1609 * @rx_desc: Rx descriptor for current buffer
1610 * @skb: Current socket buffer containing buffer in progress
1611 *
1612 * This function updates next to clean. If the buffer is an EOP buffer
1613 * this function exits returning false, otherwise it will place the
1614 * sk_buff in the next buffer to be chained and return true indicating
1615 * that this is in fact a non-EOP buffer.
1616 **/
1617static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1618 union ixgbe_adv_rx_desc *rx_desc,
1619 struct sk_buff *skb)
1620{
1621 u32 ntc = rx_ring->next_to_clean + 1;
1622
1623 /* fetch, update, and store next to clean */
1624 ntc = (ntc < rx_ring->count) ? ntc : 0;
1625 rx_ring->next_to_clean = ntc;
1626
1627 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1628
5a02cbd1
AD		 1629 /* update RSC append count if present */
1630 if (ring_is_rsc_enabled(rx_ring)) {
1631 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1632 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1633
1634 if (unlikely(rsc_enabled)) {
1635 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1636
1637 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1638 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1639
5a02cbd1
AD		 1640 /* update ntc based on RSC value */
1641 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1642 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1643 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1644 }
f800326d
AD		 1645 }
1646
5a02cbd1
AD		 1647 /* if we are the last buffer then there is nothing else to do */
1648 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1649 return false;
1650
f800326d
AD		 1651 /* place skb in next buffer to be received */
1652 rx_ring->rx_buffer_info[ntc].skb = skb;
1653 rx_ring->rx_stats.non_eop_descs++;
1654
1655 return true;
1656}
1657
19861ce2
AD		 1658/**
1659 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1660 * @rx_ring: rx descriptor ring packet is being transacted on
1661 * @skb: pointer to current skb being adjusted
1662 *
1663 * This function is an ixgbe specific version of __pskb_pull_tail. The
1664 * main difference between this version and the original function is that
1665 * this function can make several assumptions about the state of things
1666 * that allow for significant optimizations versus the standard function.
1667 * As a result we can do things like drop a frag and maintain an accurate
1668 * truesize for the skb.
1669 */
1670static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1671 struct sk_buff *skb)
1672{
1673 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1674 unsigned char *va;
1675 unsigned int pull_len;
1676
1677 /*
1678 * it is valid to use page_address instead of kmap since we are
1679 * working with pages allocated out of the lomem pool per
1680 * alloc_page(GFP_ATOMIC)
1681 */
1682 va = skb_frag_address(frag);
1683
1684 /*
1685 * we need the header to contain the greater of either ETH_HLEN or
1686 * 60 bytes if the skb->len is less than 60 for skb_pad.
1687 */
8496e338 1688 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1689
1690 /* align pull length to size of long to optimize memcpy performance */
1691 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1692
1693 /* update all of the pointers */
1694 skb_frag_size_sub(frag, pull_len);
1695 frag->page_offset += pull_len;
1696 skb->data_len -= pull_len;
1697 skb->tail += pull_len;
19861ce2
AD		 1698}
1699
42073d91
AD		 1700/**
1701 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1702 * @rx_ring: rx descriptor ring packet is being transacted on
1703 * @skb: pointer to current skb being updated
1704 *
1705 * This function provides a basic DMA sync up for the first fragment of an
1706 * skb. The reason for doing this is that the first fragment cannot be
1707 * unmapped until we have reached the end of packet descriptor for a buffer
1708 * chain.
1709 */
1710static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1711 struct sk_buff *skb)
1712{
1713 /* if the page was released unmap it, else just sync our portion */
1714 if (unlikely(IXGBE_CB(skb)->page_released)) {
1715 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1716 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1717 IXGBE_CB(skb)->page_released = false;
1718 } else {
1719 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1720
1721 dma_sync_single_range_for_cpu(rx_ring->dev,
1722 IXGBE_CB(skb)->dma,
1723 frag->page_offset,
1724 ixgbe_rx_bufsz(rx_ring),
1725 DMA_FROM_DEVICE);
1726 }
1727 IXGBE_CB(skb)->dma = 0;
1728}
1729
f800326d
AD		 1730/**
1731 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1732 * @rx_ring: rx descriptor ring packet is being transacted on
1733 * @rx_desc: pointer to the EOP Rx descriptor
1734 * @skb: pointer to current skb being fixed
1735 *
1736 * Check for corrupted packet headers caused by senders on the local L2
1737 * embedded NIC switch not setting up their Tx Descriptors right. These
1738 * should be very rare.
1739 *
1740 * Also address the case where we are pulling data in on pages only
1741 * and as such no data is present in the skb header.
1742 *
1743 * In addition if skb is not at least 60 bytes we need to pad it so that
1744 * it is large enough to qualify as a valid Ethernet frame.
1745 *
1746 * Returns true if an error was encountered and skb was freed.
1747 **/
1748static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1749 union ixgbe_adv_rx_desc *rx_desc,
1750 struct sk_buff *skb)
1751{
f800326d 1752 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1753
1754 /* verify that the packet does not have any known errors */
1755 if (unlikely(ixgbe_test_staterr(rx_desc,
1756 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1757 !(netdev->features & NETIF_F_RXALL))) {
1758 dev_kfree_skb_any(skb);
1759 return true;
1760 }
1761
19861ce2 1762 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1763 if (skb_is_nonlinear(skb))
1764 ixgbe_pull_tail(rx_ring, skb);
f800326d 1765
57efd44c
AD		 1766#ifdef IXGBE_FCOE
1767 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1768 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1769 return false;
1770
1771#endif
f800326d
AD		 1772 /* if skb_pad returns an error the skb was freed */
1773 if (unlikely(skb->len < 60)) {
1774 int pad_len = 60 - skb->len;
1775
1776 if (skb_pad(skb, pad_len))
1777 return true;
1778 __skb_put(skb, pad_len);
1779 }
1780
1781 return false;
1782}
1783
f800326d
AD		 1784/**
1785 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1786 * @rx_ring: rx descriptor ring to store buffers on
1787 * @old_buff: donor buffer to have page reused
1788 *
0549ae20 1789 * Synchronizes page for reuse by the adapter
f800326d
AD		 1790 **/
1791static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1792 struct ixgbe_rx_buffer *old_buff)
1793{
1794 struct ixgbe_rx_buffer *new_buff;
1795 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1796
1797 new_buff = &rx_ring->rx_buffer_info[nta];
1798
1799 /* update, and store next to alloc */
1800 nta++;
1801 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1802
1803 /* transfer page from old buffer to new buffer */
18cb652a 1804 *new_buff = *old_buff;
f800326d
AD		 1805
1806 /* sync the buffer for use by the device */
1807 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1808 new_buff->page_offset,
1809 ixgbe_rx_bufsz(rx_ring),
f800326d 1810 DMA_FROM_DEVICE);
f800326d
AD		 1811}
1812
18cb652a
AD		 1813static inline bool ixgbe_page_is_reserved(struct page *page)
1814{
1815 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
1816}
1817
f800326d
AD		 1818/**
1819 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1820 * @rx_ring: rx descriptor ring to transact packets on
1821 * @rx_buffer: buffer containing page to add
1822 * @rx_desc: descriptor containing length of buffer written by hardware
1823 * @skb: sk_buff to place the data into
1824 *
0549ae20
AD		 1825 * This function will add the data contained in rx_buffer->page to the skb.
1826 * This is done either through a direct copy if the data in the buffer is
1827 * less than the skb header size, otherwise it will just attach the page as
1828 * a frag to the skb.
1829 *
1830 * The function will then update the page offset if necessary and return
1831 * true if the buffer can be reused by the adapter.
f800326d 1832 **/
0549ae20 1833static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1834 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1835 union ixgbe_adv_rx_desc *rx_desc,
1836 struct sk_buff *skb)
f800326d 1837{
0549ae20
AD		 1838 struct page *page = rx_buffer->page;
1839 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1840#if (PAGE_SIZE < 8192)
0549ae20 1841 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1842#else
1843 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1844 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1845 ixgbe_rx_bufsz(rx_ring);
1846#endif
0549ae20 1847
cf3fe7ac
AD		 1848 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1849 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1850
1851 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1852
18cb652a
AD		 1853 /* page is not reserved, we can reuse buffer as-is */
1854 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1855 return true;
1856
1857 /* this page cannot be reused so discard it */
18cb652a 1858 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1859 return false;
1860 }
1861
0549ae20
AD		 1862 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1863 rx_buffer->page_offset, size, truesize);
1864
09816fbe 1865 /* avoid re-using remote pages */
18cb652a 1866 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1867 return false;
1868
1869#if (PAGE_SIZE < 8192)
1870 /* if we are only owner of page we can reuse it */
1871 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1872 return false;
1873
1874 /* flip page offset to other buffer */
1875 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1876#else
1877 /* move offset up to the next cache line */
1878 rx_buffer->page_offset += truesize;
1879
1880 if (rx_buffer->page_offset > last_offset)
1881 return false;
09816fbe 1882#endif
0549ae20 1883
18cb652a
AD		 1884 /* Even if we own the page, we are not allowed to use atomic_set()
1885 * This would break get_page_unless_zero() users.
1886 */
1887 atomic_inc(&page->_count);
1888
0549ae20 1889 return true;
f800326d
AD		 1890}
1891
18806c9e
AD		 1892static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1893 union ixgbe_adv_rx_desc *rx_desc)
1894{
1895 struct ixgbe_rx_buffer *rx_buffer;
1896 struct sk_buff *skb;
1897 struct page *page;
1898
1899 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1900 page = rx_buffer->page;
1901 prefetchw(page);
1902
1903 skb = rx_buffer->skb;
1904
1905 if (likely(!skb)) {
1906 void *page_addr = page_address(page) +
1907 rx_buffer->page_offset;
1908
1909 /* prefetch first cache line of first page */
1910 prefetch(page_addr);
1911#if L1_CACHE_BYTES < 128
1912 prefetch(page_addr + L1_CACHE_BYTES);
1913#endif
1914
1915 /* allocate a skb to store the frags */
1916 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1917 IXGBE_RX_HDR_SIZE);
1918 if (unlikely(!skb)) {
1919 rx_ring->rx_stats.alloc_rx_buff_failed++;
1920 return NULL;
1921 }
1922
1923 /*
1924 * we will be copying header into skb->data in
1925 * pskb_may_pull so it is in our interest to prefetch
1926 * it now to avoid a possible cache miss
1927 */
1928 prefetchw(skb->data);
1929
1930 /*
1931 * Delay unmapping of the first packet. It carries the
1932 * header information, HW may still access the header
1933 * after the writeback. Only unmap it when EOP is
1934 * reached
1935 */
1936 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1937 goto dma_sync;
1938
1939 IXGBE_CB(skb)->dma = rx_buffer->dma;
1940 } else {
1941 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1942 ixgbe_dma_sync_frag(rx_ring, skb);
1943
1944dma_sync:
1945 /* we are reusing so sync this buffer for CPU use */
1946 dma_sync_single_range_for_cpu(rx_ring->dev,
1947 rx_buffer->dma,
1948 rx_buffer->page_offset,
1949 ixgbe_rx_bufsz(rx_ring),
1950 DMA_FROM_DEVICE);
18cb652a
AD		 1951
1952 rx_buffer->skb = NULL;
18806c9e
AD		 1953 }
1954
1955 /* pull page into skb */
1956 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1957 /* hand second half of page back to the ring */
1958 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1959 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1960 /* the page has been released from the ring */
1961 IXGBE_CB(skb)->page_released = true;
1962 } else {
1963 /* we are not reusing the buffer so unmap it */
1964 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1965 ixgbe_rx_pg_size(rx_ring),
1966 DMA_FROM_DEVICE);
1967 }
1968
1969 /* clear contents of buffer_info */
18806c9e
AD		 1970 rx_buffer->page = NULL;
1971
1972 return skb;
f800326d
AD		 1973}
1974
1975/**
1976 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1977 * @q_vector: structure containing interrupt and ring information
1978 * @rx_ring: rx descriptor ring to transact packets on
1979 * @budget: Total limit on number of packets to process
1980 *
1981 * This function provides a "bounce buffer" approach to Rx interrupt
1982 * processing. The advantage to this is that on systems that have
1983 * expensive overhead for IOMMU access this provides a means of avoiding
1984 * it by maintaining the mapping of the page to the syste.
1985 *
5a85e737 1986 * Returns amount of work completed
f800326d 1987 **/
5a85e737 1988static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1989 struct ixgbe_ring *rx_ring,
f4de00ed 1990 const int budget)
9a799d71 1991{
d2f4fbe2 1992 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1993#ifdef IXGBE_FCOE
f800326d 1994 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1995 int ddp_bytes;
1996 unsigned int mss = 0;
3d8fd385 1997#endif /* IXGBE_FCOE */
f800326d 1998 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1999
fdabfc8a 2000 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2001 union ixgbe_adv_rx_desc *rx_desc;
2002 struct sk_buff *skb;
f800326d
AD		 2003
2004 /* return some buffers to hardware, one at a time is too slow */
2005 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2006 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2007 cleaned_count = 0;
2008 }
2009
18806c9e 2010 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2011
2012 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2013 break;
9a799d71 2014
f800326d
AD		 2015 /*
2016 * This memory barrier is needed to keep us from reading
2017 * any other fields out of the rx_desc until we know the
2018 * RXD_STAT_DD bit is set
2019 */
2020 rmb();
9a799d71 2021
18806c9e
AD		 2022 /* retrieve a buffer from the ring */
2023 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2024
18806c9e
AD		 2025 /* exit if we failed to retrieve a buffer */
2026 if (!skb)
2027 break;
9a799d71 2028
9a799d71 2029 cleaned_count++;
f8212f97 2030
f800326d
AD		 2031 /* place incomplete frames back on ring for completion */
2032 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2033 continue;
c267fc16 2034
f800326d
AD		 2035 /* verify the packet layout is correct */
2036 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2037 continue;
9a799d71 2038
d2f4fbe2
AV		 2039 /* probably a little skewed due to removing CRC */
2040 total_rx_bytes += skb->len;
d2f4fbe2 2041
8a0da21b
AD		 2042 /* populate checksum, timestamp, VLAN, and protocol */
2043 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2044
332d4a7d
YZ		 2045#ifdef IXGBE_FCOE
2046 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2047 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2048 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2049 /* include DDPed FCoE data */
2050 if (ddp_bytes > 0) {
2051 if (!mss) {
2052 mss = rx_ring->netdev->mtu -
2053 sizeof(struct fcoe_hdr) -
2054 sizeof(struct fc_frame_header) -
2055 sizeof(struct fcoe_crc_eof);
2056 if (mss > 512)
2057 mss &= ~511;
2058 }
2059 total_rx_bytes += ddp_bytes;
2060 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2061 mss);
2062 }
63d635b2
AD		 2063 if (!ddp_bytes) {
2064 dev_kfree_skb_any(skb);
f800326d 2065 continue;
63d635b2 2066 }
3d8fd385 2067 }
f800326d 2068
332d4a7d 2069#endif /* IXGBE_FCOE */
8b80cda5 2070 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2071 ixgbe_rx_skb(q_vector, skb);
9a799d71 2072
f800326d 2073 /* update budget accounting */
f4de00ed 2074 total_rx_packets++;
fdabfc8a 2075 }
9a799d71 2076
c267fc16
AD		 2077 u64_stats_update_begin(&rx_ring->syncp);
2078 rx_ring->stats.packets += total_rx_packets;
2079 rx_ring->stats.bytes += total_rx_bytes;
2080 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2081 q_vector->rx.total_packets += total_rx_packets;
2082 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2083
5a85e737 2084 return total_rx_packets;
9a799d71
AK		 2085}
2086
e0d1095a 2087#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2088/* must be called with local_bh_disable()d */
2089static int ixgbe_low_latency_recv(struct napi_struct *napi)
2090{
2091 struct ixgbe_q_vector *q_vector =
2092 container_of(napi, struct ixgbe_q_vector, napi);
2093 struct ixgbe_adapter *adapter = q_vector->adapter;
2094 struct ixgbe_ring *ring;
2095 int found = 0;
2096
2097 if (test_bit(__IXGBE_DOWN, &adapter->state))
2098 return LL_FLUSH_FAILED;
2099
2100 if (!ixgbe_qv_lock_poll(q_vector))
2101 return LL_FLUSH_BUSY;
2102
2103 ixgbe_for_each_ring(ring, q_vector->rx) {
2104 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2105#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2106 if (found)
2107 ring->stats.cleaned += found;
2108 else
2109 ring->stats.misses++;
2110#endif
5a85e737
ET		 2111 if (found)
2112 break;
2113 }
2114
2115 ixgbe_qv_unlock_poll(q_vector);
2116
2117 return found;
2118}
e0d1095a 2119#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2120
9a799d71
AK		 2121/**
2122 * ixgbe_configure_msix - Configure MSI-X hardware
2123 * @adapter: board private structure
2124 *
2125 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2126 * interrupts.
2127 **/
2128static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2129{
021230d4 2130 struct ixgbe_q_vector *q_vector;
49c7ffbe 2131 int v_idx;
021230d4 2132 u32 mask;
9a799d71 2133
8e34d1aa
AD		 2134 /* Populate MSIX to EITR Select */
2135 if (adapter->num_vfs > 32) {
2136 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2137 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2138 }
2139
4df10466
JB		 2140 /*
2141 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2142 * corresponding register.
2143 */
49c7ffbe 2144 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2145 struct ixgbe_ring *ring;
7a921c93 2146 q_vector = adapter->q_vector[v_idx];
021230d4 2147
a557928e 2148 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2149 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2150
a557928e 2151 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2152 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2153
fe49f04a 2154 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2155 }
2156
bd508178
AD		 2157 switch (adapter->hw.mac.type) {
2158 case ixgbe_mac_82598EB:
e8e26350 2159 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2160 v_idx);
bd508178
AD		 2161 break;
2162 case ixgbe_mac_82599EB:
b93a2226 2163 case ixgbe_mac_X540:
9a75a1ac
DS		 2164 case ixgbe_mac_X550:
2165 case ixgbe_mac_X550EM_x:
e8e26350 2166 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2167 break;
bd508178
AD		 2168 default:
2169 break;
2170 }
021230d4
AV		 2171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2172
41fb9248 2173 /* set up to autoclear timer, and the vectors */
021230d4 2174 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2175 mask &= ~(IXGBE_EIMS_OTHER |
2176 IXGBE_EIMS_MAILBOX |
2177 IXGBE_EIMS_LSC);
2178
021230d4 2179 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2180}
2181
f494e8fa
AV		 2182enum latency_range {
2183 lowest_latency = 0,
2184 low_latency = 1,
2185 bulk_latency = 2,
2186 latency_invalid = 255
2187};
2188
2189/**
2190 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2191 * @q_vector: structure containing interrupt and ring information
2192 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2193 *
2194 * Stores a new ITR value based on packets and byte
2195 * counts during the last interrupt. The advantage of per interrupt
2196 * computation is faster updates and more accurate ITR for the current
2197 * traffic pattern. Constants in this function were computed
2198 * based on theoretical maximum wire speed and thresholds were set based
2199 * on testing data as well as attempting to minimize response time
2200 * while increasing bulk throughput.
2201 * this functionality is controlled by the InterruptThrottleRate module
2202 * parameter (see ixgbe_param.c)
2203 **/
bd198058
AD		 2204static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2205 struct ixgbe_ring_container *ring_container)
f494e8fa 2206{
bd198058
AD		 2207 int bytes = ring_container->total_bytes;
2208 int packets = ring_container->total_packets;
2209 u32 timepassed_us;
621bd70e 2210 u64 bytes_perint;
bd198058 2211 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2212
2213 if (packets == 0)
bd198058 2214 return;
f494e8fa
AV		 2215
2216 /* simple throttlerate management
621bd70e
AD		 2217 * 0-10MB/s lowest (100000 ints/s)
2218 * 10-20MB/s low (20000 ints/s)
2219 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2220 */
2221 /* what was last interrupt timeslice? */
d5bf4f67 2222 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2223 if (timepassed_us == 0)
2224 return;
2225
f494e8fa
AV		 2226 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2227
2228 switch (itr_setting) {
2229 case lowest_latency:
621bd70e 2230 if (bytes_perint > 10)
bd198058 2231 itr_setting = low_latency;
f494e8fa
AV		 2232 break;
2233 case low_latency:
621bd70e 2234 if (bytes_perint > 20)
bd198058 2235 itr_setting = bulk_latency;
621bd70e 2236 else if (bytes_perint <= 10)
bd198058 2237 itr_setting = lowest_latency;
f494e8fa
AV		 2238 break;
2239 case bulk_latency:
621bd70e 2240 if (bytes_perint <= 20)
bd198058 2241 itr_setting = low_latency;
f494e8fa
AV		 2242 break;
2243 }
2244
bd198058
AD		 2245 /* clear work counters since we have the values we need */
2246 ring_container->total_bytes = 0;
2247 ring_container->total_packets = 0;
2248
2249 /* write updated itr to ring container */
2250 ring_container->itr = itr_setting;
f494e8fa
AV		 2251}
2252
509ee935
JB		 2253/**
2254 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2255 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2256 *
2257 * This function is made to be called by ethtool and by the driver
2258 * when it needs to update EITR registers at runtime. Hardware
2259 * specific quirks/differences are taken care of here.
2260 */
fe49f04a 2261void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2262{
fe49f04a 2263 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2264 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2265 int v_idx = q_vector->v_idx;
5d967eb7 2266 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2267
bd508178
AD		 2268 switch (adapter->hw.mac.type) {
2269 case ixgbe_mac_82598EB:
509ee935
JB		 2270 /* must write high and low 16 bits to reset counter */
2271 itr_reg |= (itr_reg << 16);
bd508178
AD		 2272 break;
2273 case ixgbe_mac_82599EB:
b93a2226 2274 case ixgbe_mac_X540:
9a75a1ac
DS		 2275 case ixgbe_mac_X550:
2276 case ixgbe_mac_X550EM_x:
509ee935
JB		 2277 /*
2278 * set the WDIS bit to not clear the timer bits and cause an
2279 * immediate assertion of the interrupt
2280 */
2281 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2282 break;
2283 default:
2284 break;
509ee935
JB		 2285 }
2286 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2287}
2288
bd198058 2289static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2290{
d5bf4f67 2291 u32 new_itr = q_vector->itr;
bd198058 2292 u8 current_itr;
f494e8fa 2293
bd198058
AD		 2294 ixgbe_update_itr(q_vector, &q_vector->tx);
2295 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2296
08c8833b 2297 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2298
2299 switch (current_itr) {
2300 /* counts and packets in update_itr are dependent on these numbers */
2301 case lowest_latency:
d5bf4f67 2302 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2303 break;
2304 case low_latency:
d5bf4f67 2305 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2306 break;
2307 case bulk_latency:
d5bf4f67 2308 new_itr = IXGBE_8K_ITR;
f494e8fa 2309 break;
bd198058
AD		 2310 default:
2311 break;
f494e8fa
AV		 2312 }
2313
d5bf4f67 2314 if (new_itr != q_vector->itr) {
fe49f04a 2315 /* do an exponential smoothing */
d5bf4f67
ET		 2316 new_itr = (10 * new_itr * q_vector->itr) /
2317 ((9 * new_itr) + q_vector->itr);
509ee935 2318
bd198058 2319 /* save the algorithm value here */
5d967eb7 2320 q_vector->itr = new_itr;
fe49f04a
AD		 2321
2322 ixgbe_write_eitr(q_vector);
f494e8fa 2323 }
f494e8fa
AV		 2324}
2325
119fc60a 2326/**
de88eeeb 2327 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2328 * @adapter: pointer to adapter
119fc60a 2329 **/
f0f9778d 2330static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2331{
119fc60a
MC		 2332 struct ixgbe_hw *hw = &adapter->hw;
2333 u32 eicr = adapter->interrupt_event;
2334
f0f9778d 2335 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2336 return;
2337
f0f9778d
AD		 2338 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2339 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2340 return;
2341
2342 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2343
7ca647bd 2344 switch (hw->device_id) {
f0f9778d
AD		 2345 case IXGBE_DEV_ID_82599_T3_LOM:
2346 /*
2347 * Since the warning interrupt is for both ports
2348 * we don't have to check if:
2349 * - This interrupt wasn't for our port.
2350 * - We may have missed the interrupt so always have to
2351 * check if we got a LSC
2352 */
2353 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2354 !(eicr & IXGBE_EICR_LSC))
2355 return;
2356
2357 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2358 u32 speed;
f0f9778d 2359 bool link_up = false;
7ca647bd 2360
3d292265 2361 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2362
f0f9778d
AD		 2363 if (link_up)
2364 return;
2365 }
2366
2367 /* Check if this is not due to overtemp */
2368 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2369 return;
2370
2371 break;
7ca647bd
JP		 2372 default:
2373 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2374 return;
7ca647bd 2375 break;
119fc60a 2376 }
7ca647bd
JP		 2377 e_crit(drv,
2378 "Network adapter has been stopped because it has over heated. "
2379 "Restart the computer. If the problem persists, "
2380 "power off the system and replace the adapter\n");
f0f9778d
AD		 2381
2382 adapter->interrupt_event = 0;
119fc60a
MC		 2383}
2384
0befdb3e
JB		 2385static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2386{
2387 struct ixgbe_hw *hw = &adapter->hw;
2388
2389 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2390 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2391 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2392 /* write to clear the interrupt */
2393 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2394 }
2395}
cf8280ee 2396
4f51bf70
JK		 2397static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2398{
2399 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2400 return;
2401
2402 switch (adapter->hw.mac.type) {
2403 case ixgbe_mac_82599EB:
2404 /*
2405 * Need to check link state so complete overtemp check
2406 * on service task
2407 */
2408 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2409 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2410 adapter->interrupt_event = eicr;
2411 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2412 ixgbe_service_event_schedule(adapter);
2413 return;
2414 }
2415 return;
2416 case ixgbe_mac_X540:
2417 if (!(eicr & IXGBE_EICR_TS))
2418 return;
2419 break;
2420 default:
2421 return;
2422 }
2423
2424 e_crit(drv,
2425 "Network adapter has been stopped because it has over heated. "
2426 "Restart the computer. If the problem persists, "
2427 "power off the system and replace the adapter\n");
2428}
2429
e8e26350
PW		 2430static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2431{
2432 struct ixgbe_hw *hw = &adapter->hw;
2433
73c4b7cd
AD		 2434 if (eicr & IXGBE_EICR_GPI_SDP2) {
2435 /* Clear the interrupt */
2436 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2437 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2438 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2439 ixgbe_service_event_schedule(adapter);
2440 }
73c4b7cd
AD		 2441 }
2442
e8e26350
PW		 2443 if (eicr & IXGBE_EICR_GPI_SDP1) {
2444 /* Clear the interrupt */
2445 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2446 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2447 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2448 ixgbe_service_event_schedule(adapter);
2449 }
e8e26350
PW		 2450 }
2451}
2452
cf8280ee
JB		 2453static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2454{
2455 struct ixgbe_hw *hw = &adapter->hw;
2456
2457 adapter->lsc_int++;
2458 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2459 adapter->link_check_timeout = jiffies;
2460 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2461 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2462 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2463 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2464 }
2465}
2466
fe49f04a
AD		 2467static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2468 u64 qmask)
2469{
2470 u32 mask;
bd508178 2471 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2472
bd508178
AD		 2473 switch (hw->mac.type) {
2474 case ixgbe_mac_82598EB:
fe49f04a 2475 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2476 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2477 break;
2478 case ixgbe_mac_82599EB:
b93a2226 2479 case ixgbe_mac_X540:
9a75a1ac
DS		 2480 case ixgbe_mac_X550:
2481 case ixgbe_mac_X550EM_x:
fe49f04a 2482 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2483 if (mask)
2484 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2485 mask = (qmask >> 32);
bd508178
AD		 2486 if (mask)
2487 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2488 break;
2489 default:
2490 break;
fe49f04a
AD		 2491 }
2492 /* skip the flush */
2493}
2494
2495static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2496 u64 qmask)
fe49f04a
AD		 2497{
2498 u32 mask;
bd508178 2499 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2500
bd508178
AD		 2501 switch (hw->mac.type) {
2502 case ixgbe_mac_82598EB:
fe49f04a 2503 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2504 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2505 break;
2506 case ixgbe_mac_82599EB:
b93a2226 2507 case ixgbe_mac_X540:
9a75a1ac
DS		 2508 case ixgbe_mac_X550:
2509 case ixgbe_mac_X550EM_x:
fe49f04a 2510 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2511 if (mask)
2512 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2513 mask = (qmask >> 32);
bd508178
AD		 2514 if (mask)
2515 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2516 break;
2517 default:
2518 break;
fe49f04a
AD		 2519 }
2520 /* skip the flush */
2521}
2522
021230d4 2523/**
2c4af694
AD		 2524 * ixgbe_irq_enable - Enable default interrupt generation settings
2525 * @adapter: board private structure
021230d4 2526 **/
2c4af694
AD		 2527static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2528 bool flush)
9a799d71 2529{
2c4af694 2530 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2531
2c4af694
AD		 2532 /* don't reenable LSC while waiting for link */
2533 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2534 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2535
2c4af694 2536 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2537 switch (adapter->hw.mac.type) {
2538 case ixgbe_mac_82599EB:
2539 mask |= IXGBE_EIMS_GPI_SDP0;
2540 break;
2541 case ixgbe_mac_X540:
9a75a1ac
DS		 2542 case ixgbe_mac_X550:
2543 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2544 mask |= IXGBE_EIMS_TS;
2545 break;
2546 default:
2547 break;
2548 }
2c4af694
AD		 2549 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2550 mask |= IXGBE_EIMS_GPI_SDP1;
2551 switch (adapter->hw.mac.type) {
2552 case ixgbe_mac_82599EB:
2c4af694
AD		 2553 mask |= IXGBE_EIMS_GPI_SDP1;
2554 mask |= IXGBE_EIMS_GPI_SDP2;
9a75a1ac 2555 /* fall through */
858bc081 2556 case ixgbe_mac_X540:
9a75a1ac
DS		 2557 case ixgbe_mac_X550:
2558 case ixgbe_mac_X550EM_x:
858bc081 2559 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2560 mask |= IXGBE_EIMS_MAILBOX;
2561 break;
2562 default:
2563 break;
9a799d71 2564 }
db0677fa 2565
2c4af694
AD		 2566 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2567 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2568 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2569
2c4af694
AD		 2570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2571 if (queues)
2572 ixgbe_irq_enable_queues(adapter, ~0);
2573 if (flush)
2574 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2575}
2576
2c4af694 2577static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2578{
a65151ba 2579 struct ixgbe_adapter *adapter = data;
9a799d71 2580 struct ixgbe_hw *hw = &adapter->hw;
54037505 2581 u32 eicr;
91281fd3 2582
54037505
DS		 2583 /*
2584 * Workaround for Silicon errata. Use clear-by-write instead
2585 * of clear-by-read. Reading with EICS will return the
2586 * interrupt causes without clearing, which later be done
2587 * with the write to EICR.
2588 */
2589 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2590
2591 /* The lower 16bits of the EICR register are for the queue interrupts
2592 * which should be masked here in order to not accidently clear them if
2593 * the bits are high when ixgbe_msix_other is called. There is a race
2594 * condition otherwise which results in possible performance loss
2595 * especially if the ixgbe_msix_other interrupt is triggering
2596 * consistently (as it would when PPS is turned on for the X540 device)
2597 */
2598 eicr &= 0xFFFF0000;
2599
54037505 2600 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2601
cf8280ee
JB		 2602 if (eicr & IXGBE_EICR_LSC)
2603 ixgbe_check_lsc(adapter);
f0848276 2604
1cdd1ec8
GR		 2605 if (eicr & IXGBE_EICR_MAILBOX)
2606 ixgbe_msg_task(adapter);
efe3d3c8 2607
bd508178
AD		 2608 switch (hw->mac.type) {
2609 case ixgbe_mac_82599EB:
b93a2226 2610 case ixgbe_mac_X540:
9a75a1ac
DS		 2611 case ixgbe_mac_X550:
2612 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2613 if (eicr & IXGBE_EICR_ECC) {
2614 e_info(link, "Received ECC Err, initiating reset\n");
2615 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2616 ixgbe_service_event_schedule(adapter);
2617 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2618 }
c4cf55e5
PWJ		 2619 /* Handle Flow Director Full threshold interrupt */
2620 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2621 int reinit_count = 0;
c4cf55e5 2622 int i;
c4cf55e5 2623 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2624 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2625 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2626 &ring->state))
2627 reinit_count++;
2628 }
2629 if (reinit_count) {
2630 /* no more flow director interrupts until after init */
2631 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2632 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2633 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2634 }
2635 }
f0f9778d 2636 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2637 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2638 break;
2639 default:
2640 break;
c4cf55e5 2641 }
f0848276 2642
bd508178 2643 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2644
db0677fa
JK		 2645 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2646 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2647
7086400d 2648 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2649 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2650 ixgbe_irq_enable(adapter, false, false);
f0848276 2651
9a799d71 2652 return IRQ_HANDLED;
f0848276 2653}
91281fd3 2654
4ff7fb12 2655static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2656{
021230d4 2657 struct ixgbe_q_vector *q_vector = data;
91281fd3 2658
9b471446 2659 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2660
4ff7fb12
AD		 2661 if (q_vector->rx.ring || q_vector->tx.ring)
2662 napi_schedule(&q_vector->napi);
91281fd3 2663
9a799d71 2664 return IRQ_HANDLED;
91281fd3
AD		 2665}
2666
eb01b975
AD		 2667/**
2668 * ixgbe_poll - NAPI Rx polling callback
2669 * @napi: structure for representing this polling device
2670 * @budget: how many packets driver is allowed to clean
2671 *
2672 * This function is used for legacy and MSI, NAPI mode
2673 **/
8af3c33f 2674int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2675{
2676 struct ixgbe_q_vector *q_vector =
2677 container_of(napi, struct ixgbe_q_vector, napi);
2678 struct ixgbe_adapter *adapter = q_vector->adapter;
2679 struct ixgbe_ring *ring;
2680 int per_ring_budget;
2681 bool clean_complete = true;
2682
2683#ifdef CONFIG_IXGBE_DCA
2684 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2685 ixgbe_update_dca(q_vector);
2686#endif
2687
2688 ixgbe_for_each_ring(ring, q_vector->tx)
2689 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2690
5a85e737
ET		 2691 if (!ixgbe_qv_lock_napi(q_vector))
2692 return budget;
2693
eb01b975
AD		 2694 /* attempt to distribute budget to each queue fairly, but don't allow
2695 * the budget to go below 1 because we'll exit polling */
2696 if (q_vector->rx.count > 1)
2697 per_ring_budget = max(budget/q_vector->rx.count, 1);
2698 else
2699 per_ring_budget = budget;
2700
2701 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2702 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2703 per_ring_budget) < per_ring_budget);
eb01b975 2704
5a85e737 2705 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2706 /* If all work not completed, return budget and keep polling */
2707 if (!clean_complete)
2708 return budget;
2709
2710 /* all work done, exit the polling mode */
2711 napi_complete(napi);
2712 if (adapter->rx_itr_setting & 1)
2713 ixgbe_set_itr(q_vector);
2714 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2715 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2716
2717 return 0;
2718}
2719
021230d4
AV		 2720/**
2721 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2722 * @adapter: board private structure
2723 *
2724 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2725 * interrupts from the kernel.
2726 **/
2727static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2728{
2729 struct net_device *netdev = adapter->netdev;
207867f5 2730 int vector, err;
e8e9f696 2731 int ri = 0, ti = 0;
021230d4 2732
49c7ffbe 2733 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2734 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2735 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2736
4ff7fb12 2737 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2738 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2739 "%s-%s-%d", netdev->name, "TxRx", ri++);
2740 ti++;
2741 } else if (q_vector->rx.ring) {
9fe93afd 2742 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2743 "%s-%s-%d", netdev->name, "rx", ri++);
2744 } else if (q_vector->tx.ring) {
9fe93afd 2745 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2746 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2747 } else {
2748 /* skip this unused q_vector */
2749 continue;
32aa77a4 2750 }
207867f5
AD		 2751 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2752 q_vector->name, q_vector);
9a799d71 2753 if (err) {
396e799c 2754 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2755 "Error: %d\n", err);
021230d4 2756 goto free_queue_irqs;
9a799d71 2757 }
207867f5
AD		 2758 /* If Flow Director is enabled, set interrupt affinity */
2759 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2760 /* assign the mask for this irq */
2761 irq_set_affinity_hint(entry->vector,
de88eeeb 2762 &q_vector->affinity_mask);
207867f5 2763 }
9a799d71
AK		 2764 }
2765
021230d4 2766 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2767 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2768 if (err) {
de88eeeb 2769 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2770 goto free_queue_irqs;
9a799d71
AK		 2771 }
2772
9a799d71
AK		 2773 return 0;
2774
021230d4 2775free_queue_irqs:
207867f5
AD		 2776 while (vector) {
2777 vector--;
2778 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2779 NULL);
2780 free_irq(adapter->msix_entries[vector].vector,
2781 adapter->q_vector[vector]);
2782 }
021230d4
AV		 2783 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2784 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2785 kfree(adapter->msix_entries);
2786 adapter->msix_entries = NULL;
9a799d71
AK		 2787 return err;
2788}
2789
2790/**
021230d4 2791 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2792 * @irq: interrupt number
2793 * @data: pointer to a network interface device structure
9a799d71
AK		 2794 **/
2795static irqreturn_t ixgbe_intr(int irq, void *data)
2796{
a65151ba 2797 struct ixgbe_adapter *adapter = data;
9a799d71 2798 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2799 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2800 u32 eicr;
2801
54037505 2802 /*
24ddd967 2803 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2804 * before the read of EICR.
2805 */
2806 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2807
021230d4 2808 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2809 * therefore no explicit interrupt disable is necessary */
021230d4 2810 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2811 if (!eicr) {
6af3b9eb
ET		 2812 /*
2813 * shared interrupt alert!
f47cf66e 2814 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2815 * have disabled interrupts due to EIAM
2816 * finish the workaround of silicon errata on 82598. Unmask
2817 * the interrupt that we masked before the EICR read.
2818 */
2819 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2820 ixgbe_irq_enable(adapter, true, true);
9a799d71 2821 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2822 }
9a799d71 2823
cf8280ee
JB		 2824 if (eicr & IXGBE_EICR_LSC)
2825 ixgbe_check_lsc(adapter);
021230d4 2826
bd508178
AD		 2827 switch (hw->mac.type) {
2828 case ixgbe_mac_82599EB:
e8e26350 2829 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2830 /* Fall through */
2831 case ixgbe_mac_X540:
9a75a1ac
DS		 2832 case ixgbe_mac_X550:
2833 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2834 if (eicr & IXGBE_EICR_ECC) {
2835 e_info(link, "Received ECC Err, initiating reset\n");
2836 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2837 ixgbe_service_event_schedule(adapter);
2838 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2839 }
4f51bf70 2840 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2841 break;
2842 default:
2843 break;
2844 }
e8e26350 2845
0befdb3e 2846 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2847 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2848 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2849
b9f6ed2b
AD		 2850 /* would disable interrupts here but EIAM disabled it */
2851 napi_schedule(&q_vector->napi);
9a799d71 2852
6af3b9eb
ET		 2853 /*
2854 * re-enable link(maybe) and non-queue interrupts, no flush.
2855 * ixgbe_poll will re-enable the queue interrupts
2856 */
6af3b9eb
ET		 2857 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2858 ixgbe_irq_enable(adapter, false, false);
2859
9a799d71
AK		 2860 return IRQ_HANDLED;
2861}
2862
2863/**
2864 * ixgbe_request_irq - initialize interrupts
2865 * @adapter: board private structure
2866 *
2867 * Attempts to configure interrupts using the best available
2868 * capabilities of the hardware and kernel.
2869 **/
021230d4 2870static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2871{
2872 struct net_device *netdev = adapter->netdev;
021230d4 2873 int err;
9a799d71 2874
4cc6df29 2875 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2876 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2877 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2878 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2879 netdev->name, adapter);
4cc6df29 2880 else
a0607fd3 2881 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2882 netdev->name, adapter);
9a799d71 2883
de88eeeb 2884 if (err)
396e799c 2885 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2886
9a799d71
AK		 2887 return err;
2888}
2889
2890static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2891{
49c7ffbe 2892 int vector;
9a799d71 2893
49c7ffbe
AD		 2894 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2895 free_irq(adapter->pdev->irq, adapter);
2896 return;
2897 }
4cc6df29 2898
49c7ffbe
AD		 2899 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2900 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2901 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2902
49c7ffbe
AD		 2903 /* free only the irqs that were actually requested */
2904 if (!q_vector->rx.ring && !q_vector->tx.ring)
2905 continue;
207867f5 2906
49c7ffbe
AD		 2907 /* clear the affinity_mask in the IRQ descriptor */
2908 irq_set_affinity_hint(entry->vector, NULL);
2909
2910 free_irq(entry->vector, q_vector);
9a799d71 2911 }
49c7ffbe
AD		 2912
2913 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2914}
2915
22d5a71b
JB		 2916/**
2917 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2918 * @adapter: board private structure
2919 **/
2920static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2921{
bd508178
AD		 2922 switch (adapter->hw.mac.type) {
2923 case ixgbe_mac_82598EB:
835462fc 2924 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2925 break;
2926 case ixgbe_mac_82599EB:
b93a2226 2927 case ixgbe_mac_X540:
9a75a1ac
DS		 2928 case ixgbe_mac_X550:
2929 case ixgbe_mac_X550EM_x:
835462fc
NS		 2930 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2933 break;
2934 default:
2935 break;
22d5a71b
JB		 2936 }
2937 IXGBE_WRITE_FLUSH(&adapter->hw);
2938 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2939 int vector;
2940
2941 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2942 synchronize_irq(adapter->msix_entries[vector].vector);
2943
2944 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2945 } else {
2946 synchronize_irq(adapter->pdev->irq);
2947 }
2948}
2949
9a799d71
AK		 2950/**
2951 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2952 *
2953 **/
2954static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2955{
d5bf4f67 2956 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2957
d5bf4f67 2958 ixgbe_write_eitr(q_vector);
9a799d71 2959
e8e26350
PW		 2960 ixgbe_set_ivar(adapter, 0, 0, 0);
2961 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2962
396e799c 2963 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2964}
2965
43e69bf0
AD		 2966/**
2967 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2968 * @adapter: board private structure
2969 * @ring: structure containing ring specific data
2970 *
2971 * Configure the Tx descriptor ring after a reset.
2972 **/
84418e3b
AD		 2973void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2974 struct ixgbe_ring *ring)
43e69bf0
AD		 2975{
2976 struct ixgbe_hw *hw = &adapter->hw;
2977 u64 tdba = ring->dma;
2f1860b8 2978 int wait_loop = 10;
b88c6de2 2979 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2980 u8 reg_idx = ring->reg_idx;
43e69bf0 2981
2f1860b8 2982 /* disable queue to avoid issues while updating state */
b88c6de2 2983 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2984 IXGBE_WRITE_FLUSH(hw);
2985
43e69bf0 2986 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2987 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2988 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2989 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2990 ring->count * sizeof(union ixgbe_adv_tx_desc));
2991 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2992 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 2993 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 2994
b88c6de2
AD		 2995 /*
2996 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 2997 * higher than 1 when:
2998 * - ITR is 0 as it could cause false TX hangs
2999 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3000 *
3001 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3002 * to or less than the number of on chip descriptors, which is
3003 * currently 40.
3004 */
67da097e 3005 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3006 txdctl |= (1 << 16); /* WTHRESH = 1 */
3007 else
3008 txdctl |= (8 << 16); /* WTHRESH = 8 */
3009
e954b374
AD		 3010 /*
3011 * Setting PTHRESH to 32 both improves performance
3012 * and avoids a TX hang with DFP enabled
3013 */
b88c6de2
AD		 3014 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3015 32; /* PTHRESH = 32 */
2f1860b8
AD		 3016
3017 /* reinitialize flowdirector state */
39cb681b 3018 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3019 ring->atr_sample_rate = adapter->atr_sample_rate;
3020 ring->atr_count = 0;
3021 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3022 } else {
3023 ring->atr_sample_rate = 0;
3024 }
2f1860b8 3025
fd786b7b
AD		 3026 /* initialize XPS */
3027 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3028 struct ixgbe_q_vector *q_vector = ring->q_vector;
3029
3030 if (q_vector)
2a47fa45 3031 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3032 &q_vector->affinity_mask,
3033 ring->queue_index);
3034 }
3035
c84d324c
JF		 3036 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3037
2f1860b8 3038 /* enable queue */
2f1860b8
AD		 3039 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3040
3041 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3042 if (hw->mac.type == ixgbe_mac_82598EB &&
3043 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3044 return;
3045
3046 /* poll to verify queue is enabled */
3047 do {
032b4325 3048 usleep_range(1000, 2000);
2f1860b8
AD		 3049 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3050 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3051 if (!wait_loop)
3052 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3053}
3054
120ff942
AD		 3055static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3056{
3057 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3058 u32 rttdcs, mtqc;
8b1c0b24 3059 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3060
3061 if (hw->mac.type == ixgbe_mac_82598EB)
3062 return;
3063
3064 /* disable the arbiter while setting MTQC */
3065 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3066 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3067 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3068
3069 /* set transmit pool layout */
671c0adb
AD		 3070 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3071 mtqc = IXGBE_MTQC_VT_ENA;
3072 if (tcs > 4)
3073 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3074 else if (tcs > 1)
3075 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3076 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3077 mtqc |= IXGBE_MTQC_32VF;
3078 else
3079 mtqc |= IXGBE_MTQC_64VF;
3080 } else {
3081 if (tcs > 4)
3082 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3083 else if (tcs > 1)
3084 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3085 else
671c0adb
AD		 3086 mtqc = IXGBE_MTQC_64Q_1PB;
3087 }
120ff942 3088
671c0adb 3089 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3090
671c0adb
AD		 3091 /* Enable Security TX Buffer IFG for multiple pb */
3092 if (tcs) {
3093 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3094 sectx |= IXGBE_SECTX_DCB;
3095 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3096 }
3097
3098 /* re-enable the arbiter */
3099 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3100 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3101}
3102
9a799d71 3103/**
3a581073 3104 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3105 * @adapter: board private structure
3106 *
3107 * Configure the Tx unit of the MAC after a reset.
3108 **/
3109static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3110{
2f1860b8
AD		 3111 struct ixgbe_hw *hw = &adapter->hw;
3112 u32 dmatxctl;
43e69bf0 3113 u32 i;
9a799d71 3114
2f1860b8
AD		 3115 ixgbe_setup_mtqc(adapter);
3116
3117 if (hw->mac.type != ixgbe_mac_82598EB) {
3118 /* DMATXCTL.EN must be before Tx queues are enabled */
3119 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3120 dmatxctl |= IXGBE_DMATXCTL_TE;
3121 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3122 }
3123
9a799d71 3124 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3125 for (i = 0; i < adapter->num_tx_queues; i++)
3126 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3127}
3128
3ebe8fde
AD		 3129static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3130 struct ixgbe_ring *ring)
3131{
3132 struct ixgbe_hw *hw = &adapter->hw;
3133 u8 reg_idx = ring->reg_idx;
3134 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3135
3136 srrctl |= IXGBE_SRRCTL_DROP_EN;
3137
3138 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3139}
3140
3141static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3142 struct ixgbe_ring *ring)
3143{
3144 struct ixgbe_hw *hw = &adapter->hw;
3145 u8 reg_idx = ring->reg_idx;
3146 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3147
3148 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3149
3150 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3151}
3152
3153#ifdef CONFIG_IXGBE_DCB
3154void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3155#else
3156static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3157#endif
3158{
3159 int i;
3160 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3161
3162 if (adapter->ixgbe_ieee_pfc)
3163 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3164
3165 /*
3166 * We should set the drop enable bit if:
3167 * SR-IOV is enabled
3168 * or
3169 * Number of Rx queues > 1 and flow control is disabled
3170 *
3171 * This allows us to avoid head of line blocking for security
3172 * and performance reasons.
3173 */
3174 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3175 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3176 for (i = 0; i < adapter->num_rx_queues; i++)
3177 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3178 } else {
3179 for (i = 0; i < adapter->num_rx_queues; i++)
3180 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3181 }
3182}
3183
e8e26350 3184#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3185
a6616b42 3186static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3187 struct ixgbe_ring *rx_ring)
cc41ac7c 3188{
45e9baa5 3189 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3190 u32 srrctl;
bf29ee6c 3191 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3192
45e9baa5
AD		 3193 if (hw->mac.type == ixgbe_mac_82598EB) {
3194 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3195
45e9baa5
AD		 3196 /*
3197 * if VMDq is not active we must program one srrctl register
3198 * per RSS queue since we have enabled RDRXCTL.MVMEN
3199 */
3200 reg_idx &= mask;
3201 }
cc41ac7c 3202
45e9baa5
AD		 3203 /* configure header buffer length, needed for RSC */
3204 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3205
45e9baa5 3206 /* configure the packet buffer length */
f800326d 3207 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3208
3209 /* configure descriptor type */
f800326d 3210 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3211
45e9baa5 3212 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3213}
9a799d71 3214
d1b849b9 3215static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed)
0cefafad 3216{
05abb126 3217 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3218 u32 reta = 0;
05abb126 3219 int i, j;
671c0adb
AD		 3220 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3221
671c0adb
AD		 3222 /*
3223 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3224 * make full use of any rings they may have. We will use the
3225 * PSRTYPE register to control how many rings we use within the PF.
3226 */
3227 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3228 rss_i = 2;
0cefafad 3229
05abb126
AD		 3230 /* Fill out hash function seeds */
3231 for (i = 0; i < 10; i++)
3232 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3233
3234 /* Fill out redirection table */
3235 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3236 if (j == rss_i)
05abb126
AD		 3237 j = 0;
3238 /* reta = 4-byte sliding window of
3239 * 0x00..(indices-1)(indices-1)00..etc. */
3240 reta = (reta << 8) | (j * 0x11);
3241 if ((i & 3) == 3)
3242 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3243 }
d1b849b9
DS		 3244}
3245
3246static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3247{
3248 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3249 u32 mrqc = 0, rss_field = 0;
9913c61c 3250 u32 rss_key[10];
d1b849b9 3251 u32 rxcsum;
0cefafad 3252
05abb126
AD		 3253 /* Disable indicating checksum in descriptor, enables RSS hash */
3254 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3255 rxcsum |= IXGBE_RXCSUM_PCSD;
3256 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3257
671c0adb 3258 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3259 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3260 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3261 } else {
671c0adb
AD		 3262 u8 tcs = netdev_get_num_tc(adapter->netdev);
3263
3264 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3265 if (tcs > 4)
3266 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3267 else if (tcs > 1)
3268 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3269 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3270 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3271 else
671c0adb
AD		 3272 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3273 } else {
3274 if (tcs > 4)
8b1c0b24 3275 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3276 else if (tcs > 1)
3277 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3278 else
3279 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3280 }
0cefafad
JB		 3281 }
3282
05abb126 3283 /* Perform hash on these packet types */
d1b849b9
DS		 3284 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3285 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3286 IXGBE_MRQC_RSS_FIELD_IPV6 |
3287 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3288
ef6afc0c 3289 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3290 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3291 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3292 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3293
9913c61c
ED		 3294 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3295 ixgbe_setup_reta(adapter, rss_key);
d1b849b9 3296 mrqc |= rss_field;
05abb126 3297 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3298}
3299
bb5a9ad2
NS		 3300/**
3301 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3302 * @adapter: address of board private structure
3303 * @index: index of ring to set
bb5a9ad2 3304 **/
082757af 3305static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3306 struct ixgbe_ring *ring)
bb5a9ad2 3307{
bb5a9ad2 3308 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3309 u32 rscctrl;
bf29ee6c 3310 u8 reg_idx = ring->reg_idx;
7367096a 3311
7d637bcc 3312 if (!ring_is_rsc_enabled(ring))
7367096a 3313 return;
bb5a9ad2 3314
7367096a 3315 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3316 rscctrl |= IXGBE_RSCCTL_RSCEN;
3317 /*
3318 * we must limit the number of descriptors so that the
3319 * total size of max desc * buf_len is not greater
642c680e 3320 * than 65536
bb5a9ad2 3321 */
f800326d 3322 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3323 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3324}
3325
9e10e045
AD		 3326#define IXGBE_MAX_RX_DESC_POLL 10
3327static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3328 struct ixgbe_ring *ring)
3329{
3330 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3331 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3332 u32 rxdctl;
bf29ee6c 3333 u8 reg_idx = ring->reg_idx;
9e10e045 3334
b0483c8f
MR		 3335 if (ixgbe_removed(hw->hw_addr))
3336 return;
9e10e045
AD		 3337 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3338 if (hw->mac.type == ixgbe_mac_82598EB &&
3339 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3340 return;
3341
3342 do {
032b4325 3343 usleep_range(1000, 2000);
9e10e045
AD		 3344 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3345 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3346
3347 if (!wait_loop) {
3348 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3349 "the polling period\n", reg_idx);
3350 }
3351}
3352
2d39d576
YZ		 3353void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3354 struct ixgbe_ring *ring)
3355{
3356 struct ixgbe_hw *hw = &adapter->hw;
3357 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3358 u32 rxdctl;
3359 u8 reg_idx = ring->reg_idx;
3360
b0483c8f
MR		 3361 if (ixgbe_removed(hw->hw_addr))
3362 return;
2d39d576
YZ		 3363 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3364 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3365
3366 /* write value back with RXDCTL.ENABLE bit cleared */
3367 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3368
3369 if (hw->mac.type == ixgbe_mac_82598EB &&
3370 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3371 return;
3372
3373 /* the hardware may take up to 100us to really disable the rx queue */
3374 do {
3375 udelay(10);
3376 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3377 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3378
3379 if (!wait_loop) {
3380 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3381 "the polling period\n", reg_idx);
3382 }
3383}
3384
84418e3b
AD		 3385void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3386 struct ixgbe_ring *ring)
acd37177
AD		 3387{
3388 struct ixgbe_hw *hw = &adapter->hw;
3389 u64 rdba = ring->dma;
9e10e045 3390 u32 rxdctl;
bf29ee6c 3391 u8 reg_idx = ring->reg_idx;
acd37177 3392
9e10e045
AD		 3393 /* disable queue to avoid issues while updating state */
3394 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3395 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3396
acd37177
AD		 3397 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3398 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3399 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3400 ring->count * sizeof(union ixgbe_adv_rx_desc));
3401 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3402 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3403 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3404
3405 ixgbe_configure_srrctl(adapter, ring);
3406 ixgbe_configure_rscctl(adapter, ring);
3407
3408 if (hw->mac.type == ixgbe_mac_82598EB) {
3409 /*
3410 * enable cache line friendly hardware writes:
3411 * PTHRESH=32 descriptors (half the internal cache),
3412 * this also removes ugly rx_no_buffer_count increment
3413 * HTHRESH=4 descriptors (to minimize latency on fetch)
3414 * WTHRESH=8 burst writeback up to two cache lines
3415 */
3416 rxdctl &= ~0x3FFFFF;
3417 rxdctl |= 0x080420;
3418 }
3419
3420 /* enable receive descriptor ring */
3421 rxdctl |= IXGBE_RXDCTL_ENABLE;
3422 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3423
3424 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3425 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3426}
3427
48654521
AD		 3428static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3429{
3430 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3431 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3432 u16 pool;
48654521
AD		 3433
3434 /* PSRTYPE must be initialized in non 82598 adapters */
3435 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3436 IXGBE_PSRTYPE_UDPHDR |
3437 IXGBE_PSRTYPE_IPV4HDR |
48654521 3438 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3439 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3440
3441 if (hw->mac.type == ixgbe_mac_82598EB)
3442 return;
3443
fbe7ca7f
AD		 3444 if (rss_i > 3)
3445 psrtype |= 2 << 29;
3446 else if (rss_i > 1)
3447 psrtype |= 1 << 29;
48654521 3448
2a47fa45
JF		 3449 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3450 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3451}
3452
f5b4a52e
AD		 3453static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3454{
3455 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3456 u32 reg_offset, vf_shift;
435b19f6 3457 u32 gcr_ext, vmdctl;
de4c7f65 3458 int i;
f5b4a52e
AD		 3459
3460 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3461 return;
3462
3463 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3464 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3465 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3466 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3467 vmdctl |= IXGBE_VT_CTL_REPLEN;
3468 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3469
1d9c0bfd
AD		 3470 vf_shift = VMDQ_P(0) % 32;
3471 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3472
3473 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3474 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3475 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3476 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3477 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3478 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3479 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3480
3481 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3482 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3483
3484 /*
3485 * Set up VF register offsets for selected VT Mode,
3486 * i.e. 32 or 64 VFs for SR-IOV
3487 */
73079ea0
AD		 3488 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3489 case IXGBE_82599_VMDQ_8Q_MASK:
3490 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3491 break;
3492 case IXGBE_82599_VMDQ_4Q_MASK:
3493 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3494 break;
3495 default:
3496 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3497 break;
3498 }
3499
f5b4a52e
AD		 3500 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3501
435b19f6 3502
a985b6c3 3503 /* Enable MAC Anti-Spoofing */
435b19f6 3504 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3505 adapter->num_vfs);
de4c7f65
GR		 3506 /* For VFs that have spoof checking turned off */
3507 for (i = 0; i < adapter->num_vfs; i++) {
3508 if (!adapter->vfinfo[i].spoofchk_enabled)
3509 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3510 }
f5b4a52e
AD		 3511}
3512
477de6ed 3513static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3514{
9a799d71
AK		 3515 struct ixgbe_hw *hw = &adapter->hw;
3516 struct net_device *netdev = adapter->netdev;
3517 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3518 struct ixgbe_ring *rx_ring;
3519 int i;
3520 u32 mhadd, hlreg0;
48654521 3521
63f39bd1 3522#ifdef IXGBE_FCOE
477de6ed
AD		 3523 /* adjust max frame to be able to do baby jumbo for FCoE */
3524 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3525 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3526 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3527
477de6ed 3528#endif /* IXGBE_FCOE */
872844dd
AD		 3529
3530 /* adjust max frame to be at least the size of a standard frame */
3531 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3532 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3533
477de6ed
AD		 3534 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3535 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3536 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3537 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3538
3539 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3540 }
3541
3542 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3543 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3544 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3545 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3546
0cefafad
JB		 3547 /*
3548 * Setup the HW Rx Head and Tail Descriptor Pointers and
3549 * the Base and Length of the Rx Descriptor Ring
3550 */
9a799d71 3551 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3552 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3553 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3554 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3555 else
7d637bcc 3556 clear_ring_rsc_enabled(rx_ring);
477de6ed 3557 }
477de6ed
AD		 3558}
3559
7367096a
AD		 3560static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3561{
3562 struct ixgbe_hw *hw = &adapter->hw;
3563 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3564
3565 switch (hw->mac.type) {
9a75a1ac
DS		 3566 case ixgbe_mac_X550:
3567 case ixgbe_mac_X550EM_x:
7367096a
AD		 3568 case ixgbe_mac_82598EB:
3569 /*
3570 * For VMDq support of different descriptor types or
3571 * buffer sizes through the use of multiple SRRCTL
3572 * registers, RDRXCTL.MVMEN must be set to 1
3573 *
3574 * also, the manual doesn't mention it clearly but DCA hints
3575 * will only use queue 0's tags unless this bit is set. Side
3576 * effects of setting this bit are only that SRRCTL must be
3577 * fully programmed [0..15]
3578 */
3579 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3580 break;
3581 case ixgbe_mac_82599EB:
b93a2226 3582 case ixgbe_mac_X540:
7367096a
AD		 3583 /* Disable RSC for ACK packets */
3584 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3585 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3586 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3587 /* hardware requires some bits to be set by default */
3588 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3589 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3590 break;
3591 default:
3592 /* We should do nothing since we don't know this hardware */
3593 return;
3594 }
3595
3596 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3597}
3598
477de6ed
AD		 3599/**
3600 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3601 * @adapter: board private structure
3602 *
3603 * Configure the Rx unit of the MAC after a reset.
3604 **/
3605static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3606{
3607 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3608 int i;
6dcc28b9 3609 u32 rxctrl, rfctl;
477de6ed
AD		 3610
3611 /* disable receives while setting up the descriptors */
3612 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3613 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3614
3615 ixgbe_setup_psrtype(adapter);
7367096a 3616 ixgbe_setup_rdrxctl(adapter);
477de6ed 3617
6dcc28b9
JK		 3618 /* RSC Setup */
3619 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3620 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3621 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3622 rfctl |= IXGBE_RFCTL_RSC_DIS;
3623 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3624
9e10e045 3625 /* Program registers for the distribution of queues */
f5b4a52e 3626 ixgbe_setup_mrqc(adapter);
f5b4a52e 3627
477de6ed
AD		 3628 /* set_rx_buffer_len must be called before ring initialization */
3629 ixgbe_set_rx_buffer_len(adapter);
3630
3631 /*
3632 * Setup the HW Rx Head and Tail Descriptor Pointers and
3633 * the Base and Length of the Rx Descriptor Ring
3634 */
9e10e045
AD		 3635 for (i = 0; i < adapter->num_rx_queues; i++)
3636 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3637
9e10e045
AD		 3638 /* disable drop enable for 82598 parts */
3639 if (hw->mac.type == ixgbe_mac_82598EB)
3640 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3641
3642 /* enable all receives */
3643 rxctrl |= IXGBE_RXCTRL_RXEN;
3644 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3645}
3646
80d5c368
PM		 3647static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3648 __be16 proto, u16 vid)
068c89b0
DS		 3649{
3650 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3651 struct ixgbe_hw *hw = &adapter->hw;
3652
3653 /* add VID to filter table */
1d9c0bfd 3654 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3655 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3656
3657 return 0;
068c89b0
DS		 3658}
3659
80d5c368
PM		 3660static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3661 __be16 proto, u16 vid)
068c89b0
DS		 3662{
3663 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3664 struct ixgbe_hw *hw = &adapter->hw;
3665
068c89b0 3666 /* remove VID from filter table */
1d9c0bfd 3667 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3668 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3669
3670 return 0;
068c89b0
DS		 3671}
3672
f62bbb5e
JG		 3673/**
3674 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3675 * @adapter: driver data
3676 */
3677static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3678{
3679 struct ixgbe_hw *hw = &adapter->hw;
3680 u32 vlnctrl;
5f6c0181
JB		 3681 int i, j;
3682
3683 switch (hw->mac.type) {
3684 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3685 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3686 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3687 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3688 break;
3689 case ixgbe_mac_82599EB:
b93a2226 3690 case ixgbe_mac_X540:
9a75a1ac
DS		 3691 case ixgbe_mac_X550:
3692 case ixgbe_mac_X550EM_x:
5f6c0181 3693 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3694 struct ixgbe_ring *ring = adapter->rx_ring[i];
3695
3696 if (ring->l2_accel_priv)
3697 continue;
3698 j = ring->reg_idx;
5f6c0181
JB		 3699 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3700 vlnctrl &= ~IXGBE_RXDCTL_VME;
3701 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3702 }
3703 break;
3704 default:
3705 break;
3706 }
3707}
3708
3709/**
f62bbb5e 3710 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3711 * @adapter: driver data
3712 */
f62bbb5e 3713static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3714{
3715 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3716 u32 vlnctrl;
5f6c0181
JB		 3717 int i, j;
3718
3719 switch (hw->mac.type) {
3720 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3721 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3722 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3723 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3724 break;
3725 case ixgbe_mac_82599EB:
b93a2226 3726 case ixgbe_mac_X540:
9a75a1ac
DS		 3727 case ixgbe_mac_X550:
3728 case ixgbe_mac_X550EM_x:
5f6c0181 3729 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3730 struct ixgbe_ring *ring = adapter->rx_ring[i];
3731
3732 if (ring->l2_accel_priv)
3733 continue;
3734 j = ring->reg_idx;
5f6c0181
JB		 3735 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3736 vlnctrl |= IXGBE_RXDCTL_VME;
3737 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3738 }
3739 break;
3740 default:
3741 break;
3742 }
3743}
3744
9a799d71
AK		 3745static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3746{
f62bbb5e 3747 u16 vid;
9a799d71 3748
80d5c368 3749 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3750
3751 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3752 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3753}
3754
b335e75b
JK		 3755/**
3756 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3757 * @netdev: network interface device structure
3758 *
3759 * Writes multicast address list to the MTA hash table.
3760 * Returns: -ENOMEM on failure
3761 * 0 on no addresses written
3762 * X on writing X addresses to MTA
3763 **/
3764static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3765{
3766 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3767 struct ixgbe_hw *hw = &adapter->hw;
3768
3769 if (!netif_running(netdev))
3770 return 0;
3771
3772 if (hw->mac.ops.update_mc_addr_list)
3773 hw->mac.ops.update_mc_addr_list(hw, netdev);
3774 else
3775 return -ENOMEM;
3776
3777#ifdef CONFIG_PCI_IOV
5d7daa35 3778 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3779#endif
3780
3781 return netdev_mc_count(netdev);
3782}
3783
5d7daa35
JK		 3784#ifdef CONFIG_PCI_IOV
3785void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3786{
3787 struct ixgbe_hw *hw = &adapter->hw;
3788 int i;
3789 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3790 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3791 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3792 adapter->mac_table[i].queue,
3793 IXGBE_RAH_AV);
3794 else
3795 hw->mac.ops.clear_rar(hw, i);
3796
3797 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3798 }
3799}
3800#endif
3801
3802static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3803{
3804 struct ixgbe_hw *hw = &adapter->hw;
3805 int i;
3806 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3807 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3808 if (adapter->mac_table[i].state &
3809 IXGBE_MAC_STATE_IN_USE)
3810 hw->mac.ops.set_rar(hw, i,
3811 adapter->mac_table[i].addr,
3812 adapter->mac_table[i].queue,
3813 IXGBE_RAH_AV);
3814 else
3815 hw->mac.ops.clear_rar(hw, i);
3816
3817 adapter->mac_table[i].state &=
3818 ~(IXGBE_MAC_STATE_MODIFIED);
3819 }
3820 }
3821}
3822
3823static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3824{
3825 int i;
3826 struct ixgbe_hw *hw = &adapter->hw;
3827
3828 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3829 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3830 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3831 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3832 adapter->mac_table[i].queue = 0;
3833 }
3834 ixgbe_sync_mac_table(adapter);
3835}
3836
3837static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3838{
3839 struct ixgbe_hw *hw = &adapter->hw;
3840 int i, count = 0;
3841
3842 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3843 if (adapter->mac_table[i].state == 0)
3844 count++;
3845 }
3846 return count;
3847}
3848
3849/* this function destroys the first RAR entry */
3850static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3851 u8 *addr)
3852{
3853 struct ixgbe_hw *hw = &adapter->hw;
3854
3855 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3856 adapter->mac_table[0].queue = VMDQ_P(0);
3857 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3858 IXGBE_MAC_STATE_IN_USE);
3859 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3860 adapter->mac_table[0].queue,
3861 IXGBE_RAH_AV);
3862}
3863
3864int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3865{
3866 struct ixgbe_hw *hw = &adapter->hw;
3867 int i;
3868
3869 if (is_zero_ether_addr(addr))
3870 return -EINVAL;
3871
3872 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3873 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3874 continue;
3875 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3876 IXGBE_MAC_STATE_IN_USE);
3877 ether_addr_copy(adapter->mac_table[i].addr, addr);
3878 adapter->mac_table[i].queue = queue;
3879 ixgbe_sync_mac_table(adapter);
3880 return i;
3881 }
3882 return -ENOMEM;
3883}
3884
3885int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3886{
3887 /* search table for addr, if found, set to 0 and sync */
3888 int i;
3889 struct ixgbe_hw *hw = &adapter->hw;
3890
3891 if (is_zero_ether_addr(addr))
3892 return -EINVAL;
3893
3894 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3895 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3896 adapter->mac_table[i].queue == queue) {
3897 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3898 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3899 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3900 adapter->mac_table[i].queue = 0;
3901 ixgbe_sync_mac_table(adapter);
3902 return 0;
3903 }
3904 }
3905 return -ENOMEM;
3906}
2850062a
AD		 3907/**
3908 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3909 * @netdev: network interface device structure
3910 *
3911 * Writes unicast address list to the RAR table.
3912 * Returns: -ENOMEM on failure/insufficient address space
3913 * 0 on no addresses written
3914 * X on writing X addresses to the RAR table
3915 **/
5d7daa35 3916static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 3917{
3918 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 3919 int count = 0;
3920
3921 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 3922 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 3923 return -ENOMEM;
3924
95447461 3925 if (!netdev_uc_empty(netdev)) {
2850062a 3926 struct netdev_hw_addr *ha;
2850062a 3927 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 3928 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
3929 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 3930 count++;
3931 }
3932 }
2850062a
AD		 3933 return count;
3934}
3935
9a799d71 3936/**
2c5645cf 3937 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3938 * @netdev: network interface device structure
3939 *
2c5645cf
CL		 3940 * The set_rx_method entry point is called whenever the unicast/multicast
3941 * address list or the network interface flags are updated. This routine is
3942 * responsible for configuring the hardware for proper unicast, multicast and
3943 * promiscuous mode.
9a799d71 3944 **/
7f870475 3945void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3946{
3947 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3948 struct ixgbe_hw *hw = &adapter->hw;
2850062a 3949 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 3950 u32 vlnctrl;
2850062a 3951 int count;
9a799d71
AK		 3952
3953 /* Check for Promiscuous and All Multicast modes */
9a799d71 3954 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 3955 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 3956
f5dc442b 3957 /* set all bits that we expect to always be set */
3f2d1c0f 3958 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3959 fctrl |= IXGBE_FCTRL_BAM;
3960 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3961 fctrl |= IXGBE_FCTRL_PMCF;
3962
2850062a
AD		 3963 /* clear the bits we are changing the status of */
3964 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 3965 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 3966 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3967 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3968 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 3969 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 3970 /* Only disable hardware filter vlans in promiscuous mode
3971 * if SR-IOV and VMDQ are disabled - otherwise ensure
3972 * that hardware VLAN filters remain enabled.
3973 */
4556dc59
VY		 3974 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3975 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 3976 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 3977 } else {
746b9f02
PM		 3978 if (netdev->flags & IFF_ALLMULTI) {
3979 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3980 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3981 }
a9b8943e 3982 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 3983 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3984 }
3985
3986 /*
3987 * Write addresses to available RAR registers, if there is not
3988 * sufficient space to store all the addresses then enable
3989 * unicast promiscuous mode
3990 */
5d7daa35 3991 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 3992 if (count < 0) {
3993 fctrl |= IXGBE_FCTRL_UPE;
3994 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3995 }
3996
cf78959c
ET		 3997 /* Write addresses to the MTA, if the attempt fails
3998 * then we should just turn on promiscuous mode so
3999 * that we can at least receive multicast traffic
4000 */
b335e75b
JK		 4001 count = ixgbe_write_mc_addr_list(netdev);
4002 if (count < 0) {
4003 fctrl |= IXGBE_FCTRL_MPE;
4004 vmolr |= IXGBE_VMOLR_MPE;
4005 } else if (count) {
4006 vmolr |= IXGBE_VMOLR_ROMPE;
4007 }
1d9c0bfd
AD		 4008
4009 if (hw->mac.type != ixgbe_mac_82598EB) {
4010 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4011 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4012 IXGBE_VMOLR_ROPE);
1d9c0bfd 4013 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4014 }
4015
3f2d1c0f
BG		 4016 /* This is useful for sniffing bad packets. */
4017 if (adapter->netdev->features & NETIF_F_RXALL) {
4018 /* UPE and MPE will be handled by normal PROMISC logic
4019 * in e1000e_set_rx_mode */
4020 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4021 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4022 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4023
4024 fctrl &= ~(IXGBE_FCTRL_DPF);
4025 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4026 }
4027
a9b8943e 4028 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4029 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4030
f646968f 4031 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4032 ixgbe_vlan_strip_enable(adapter);
4033 else
4034 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4035}
4036
021230d4
AV		 4037static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4038{
4039 int q_idx;
021230d4 4040
5a85e737
ET		 4041 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4042 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4043 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4044 }
021230d4
AV		 4045}
4046
4047static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4048{
4049 int q_idx;
021230d4 4050
5a85e737 4051 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4052 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4053 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4054 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4055 usleep_range(1000, 20000);
5a85e737
ET		 4056 }
4057 }
021230d4
AV		 4058}
4059
7a6b6f51 4060#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4061/**
2f90b865
AD		 4062 * ixgbe_configure_dcb - Configure DCB hardware
4063 * @adapter: ixgbe adapter struct
4064 *
4065 * This is called by the driver on open to configure the DCB hardware.
4066 * This is also called by the gennetlink interface when reconfiguring
4067 * the DCB state.
4068 */
4069static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4070{
4071 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4072 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4073
67ebd791
AD		 4074 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4075 if (hw->mac.type == ixgbe_mac_82598EB)
4076 netif_set_gso_max_size(adapter->netdev, 65536);
4077 return;
4078 }
4079
4080 if (hw->mac.type == ixgbe_mac_82598EB)
4081 netif_set_gso_max_size(adapter->netdev, 32768);
4082
971060b1 4083#ifdef IXGBE_FCOE
b120818e
JF		 4084 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4085 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4086#endif
b120818e
JF		 4087
4088 /* reconfigure the hardware */
4089 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4090 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4091 DCB_TX_CONFIG);
4092 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4093 DCB_RX_CONFIG);
4094 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4095 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4096 ixgbe_dcb_hw_ets(&adapter->hw,
4097 adapter->ixgbe_ieee_ets,
4098 max_frame);
4099 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4100 adapter->ixgbe_ieee_pfc->pfc_en,
4101 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4102 }
8187cd48
JF		 4103
4104 /* Enable RSS Hash per TC */
4105 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4106 u32 msb = 0;
4107 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4108
d411a936
AD		 4109 while (rss_i) {
4110 msb++;
4111 rss_i >>= 1;
4112 }
8187cd48 4113
4ae63730
AD		 4114 /* write msb to all 8 TCs in one write */
4115 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4116 }
2f90b865 4117}
9da712d2
JF		 4118#endif
4119
4120/* Additional bittime to account for IXGBE framing */
4121#define IXGBE_ETH_FRAMING 20
4122
49ce9c2c 4123/**
9da712d2
JF		 4124 * ixgbe_hpbthresh - calculate high water mark for flow control
4125 *
4126 * @adapter: board private structure to calculate for
49ce9c2c 4127 * @pb: packet buffer to calculate
9da712d2
JF		 4128 */
4129static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4130{
4131 struct ixgbe_hw *hw = &adapter->hw;
4132 struct net_device *dev = adapter->netdev;
4133 int link, tc, kb, marker;
4134 u32 dv_id, rx_pba;
4135
4136 /* Calculate max LAN frame size */
4137 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4138
4139#ifdef IXGBE_FCOE
4140 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4141 if ((dev->features & NETIF_F_FCOE_MTU) &&
4142 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4143 (pb == ixgbe_fcoe_get_tc(adapter)))
4144 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4145#endif
e5776620 4146
9da712d2
JF		 4147 /* Calculate delay value for device */
4148 switch (hw->mac.type) {
4149 case ixgbe_mac_X540:
9a75a1ac
DS		 4150 case ixgbe_mac_X550:
4151 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4152 dv_id = IXGBE_DV_X540(link, tc);
4153 break;
4154 default:
4155 dv_id = IXGBE_DV(link, tc);
4156 break;
4157 }
4158
4159 /* Loopback switch introduces additional latency */
4160 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4161 dv_id += IXGBE_B2BT(tc);
4162
4163 /* Delay value is calculated in bit times convert to KB */
4164 kb = IXGBE_BT2KB(dv_id);
4165 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4166
4167 marker = rx_pba - kb;
4168
4169 /* It is possible that the packet buffer is not large enough
4170 * to provide required headroom. In this case throw an error
4171 * to user and a do the best we can.
4172 */
4173 if (marker < 0) {
4174 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4175 "headroom to support flow control."
4176 "Decrease MTU or number of traffic classes\n", pb);
4177 marker = tc + 1;
4178 }
4179
4180 return marker;
4181}
4182
49ce9c2c 4183/**
9da712d2
JF		 4184 * ixgbe_lpbthresh - calculate low water mark for for flow control
4185 *
4186 * @adapter: board private structure to calculate for
49ce9c2c 4187 * @pb: packet buffer to calculate
9da712d2 4188 */
e5776620 4189static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4190{
4191 struct ixgbe_hw *hw = &adapter->hw;
4192 struct net_device *dev = adapter->netdev;
4193 int tc;
4194 u32 dv_id;
4195
4196 /* Calculate max LAN frame size */
4197 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4198
e5776620
JK		 4199#ifdef IXGBE_FCOE
4200 /* FCoE traffic class uses FCOE jumbo frames */
4201 if ((dev->features & NETIF_F_FCOE_MTU) &&
4202 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4203 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4204 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4205#endif
4206
9da712d2
JF		 4207 /* Calculate delay value for device */
4208 switch (hw->mac.type) {
4209 case ixgbe_mac_X540:
9a75a1ac
DS		 4210 case ixgbe_mac_X550:
4211 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4212 dv_id = IXGBE_LOW_DV_X540(tc);
4213 break;
4214 default:
4215 dv_id = IXGBE_LOW_DV(tc);
4216 break;
4217 }
4218
4219 /* Delay value is calculated in bit times convert to KB */
4220 return IXGBE_BT2KB(dv_id);
4221}
4222
4223/*
4224 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4225 */
4226static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4227{
4228 struct ixgbe_hw *hw = &adapter->hw;
4229 int num_tc = netdev_get_num_tc(adapter->netdev);
4230 int i;
4231
4232 if (!num_tc)
4233 num_tc = 1;
4234
9da712d2
JF		 4235 for (i = 0; i < num_tc; i++) {
4236 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4237 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4238
4239 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4240 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4241 hw->fc.low_water[i] = 0;
9da712d2 4242 }
e5776620
JK		 4243
4244 for (; i < MAX_TRAFFIC_CLASS; i++)
4245 hw->fc.high_water[i] = 0;
9da712d2
JF		 4246}
4247
80605c65
JF		 4248static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4249{
80605c65 4250 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4251 int hdrm;
4252 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4253
4254 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4255 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4256 hdrm = 32 << adapter->fdir_pballoc;
4257 else
4258 hdrm = 0;
80605c65 4259
f7e1027f 4260 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4261 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4262}
4263
e4911d57
AD		 4264static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4265{
4266 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4267 struct hlist_node *node2;
e4911d57
AD		 4268 struct ixgbe_fdir_filter *filter;
4269
4270 spin_lock(&adapter->fdir_perfect_lock);
4271
4272 if (!hlist_empty(&adapter->fdir_filter_list))
4273 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4274
b67bfe0d 4275 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4276 &adapter->fdir_filter_list, fdir_node) {
4277 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4278 &filter->filter,
4279 filter->sw_idx,
4280 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4281 IXGBE_FDIR_DROP_QUEUE :
4282 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4283 }
4284
4285 spin_unlock(&adapter->fdir_perfect_lock);
4286}
4287
2a47fa45
JF		 4288static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4289 struct ixgbe_adapter *adapter)
4290{
4291 struct ixgbe_hw *hw = &adapter->hw;
4292 u32 vmolr;
4293
4294 /* No unicast promiscuous support for VMDQ devices. */
4295 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4296 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4297
4298 /* clear the affected bit */
4299 vmolr &= ~IXGBE_VMOLR_MPE;
4300
4301 if (dev->flags & IFF_ALLMULTI) {
4302 vmolr |= IXGBE_VMOLR_MPE;
4303 } else {
4304 vmolr |= IXGBE_VMOLR_ROMPE;
4305 hw->mac.ops.update_mc_addr_list(hw, dev);
4306 }
5d7daa35 4307 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4308 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4309}
4310
2a47fa45
JF		 4311static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4312{
4313 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4314 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4315 struct ixgbe_hw *hw = &adapter->hw;
4316 u16 pool = vadapter->pool;
4317 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4318 IXGBE_PSRTYPE_UDPHDR |
4319 IXGBE_PSRTYPE_IPV4HDR |
4320 IXGBE_PSRTYPE_L2HDR |
4321 IXGBE_PSRTYPE_IPV6HDR;
4322
4323 if (hw->mac.type == ixgbe_mac_82598EB)
4324 return;
4325
4326 if (rss_i > 3)
4327 psrtype |= 2 << 29;
4328 else if (rss_i > 1)
4329 psrtype |= 1 << 29;
4330
4331 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4332}
4333
4334/**
4335 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4336 * @rx_ring: ring to free buffers from
4337 **/
4338static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4339{
4340 struct device *dev = rx_ring->dev;
4341 unsigned long size;
4342 u16 i;
4343
4344 /* ring already cleared, nothing to do */
4345 if (!rx_ring->rx_buffer_info)
4346 return;
4347
4348 /* Free all the Rx ring sk_buffs */
4349 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4350 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4351
2a47fa45
JF		 4352 if (rx_buffer->skb) {
4353 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4354 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4355 dma_unmap_page(dev,
4356 IXGBE_CB(skb)->dma,
4357 ixgbe_rx_bufsz(rx_ring),
4358 DMA_FROM_DEVICE);
2a47fa45 4359 dev_kfree_skb(skb);
4d2fcfbc 4360 rx_buffer->skb = NULL;
2a47fa45 4361 }
18cb652a
AD		 4362
4363 if (!rx_buffer->page)
4364 continue;
4365
4366 dma_unmap_page(dev, rx_buffer->dma,
4367 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4368 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4369
2a47fa45
JF		 4370 rx_buffer->page = NULL;
4371 }
4372
4373 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4374 memset(rx_ring->rx_buffer_info, 0, size);
4375
4376 /* Zero out the descriptor ring */
4377 memset(rx_ring->desc, 0, rx_ring->size);
4378
4379 rx_ring->next_to_alloc = 0;
4380 rx_ring->next_to_clean = 0;
4381 rx_ring->next_to_use = 0;
4382}
4383
4384static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4385 struct ixgbe_ring *rx_ring)
4386{
4387 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4388 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4389
4390 /* shutdown specific queue receive and wait for dma to settle */
4391 ixgbe_disable_rx_queue(adapter, rx_ring);
4392 usleep_range(10000, 20000);
4393 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4394 ixgbe_clean_rx_ring(rx_ring);
4395 rx_ring->l2_accel_priv = NULL;
4396}
4397
ae72c8d0
JF		 4398static int ixgbe_fwd_ring_down(struct net_device *vdev,
4399 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4400{
4401 struct ixgbe_adapter *adapter = accel->real_adapter;
4402 unsigned int rxbase = accel->rx_base_queue;
4403 unsigned int txbase = accel->tx_base_queue;
4404 int i;
4405
4406 netif_tx_stop_all_queues(vdev);
4407
4408 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4409 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4410 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4411 }
4412
4413 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4414 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4415 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4416 }
4417
4418
4419 return 0;
4420}
4421
4422static int ixgbe_fwd_ring_up(struct net_device *vdev,
4423 struct ixgbe_fwd_adapter *accel)
4424{
4425 struct ixgbe_adapter *adapter = accel->real_adapter;
4426 unsigned int rxbase, txbase, queues;
4427 int i, baseq, err = 0;
4428
4429 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4430 return 0;
4431
4432 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4433 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4434 accel->pool, adapter->num_rx_pools,
4435 baseq, baseq + adapter->num_rx_queues_per_pool,
4436 adapter->fwd_bitmask);
4437
4438 accel->netdev = vdev;
4439 accel->rx_base_queue = rxbase = baseq;
4440 accel->tx_base_queue = txbase = baseq;
4441
4442 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4443 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4444
4445 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4446 adapter->rx_ring[rxbase + i]->netdev = vdev;
4447 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4448 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4449 }
4450
4451 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4452 adapter->tx_ring[txbase + i]->netdev = vdev;
4453 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4454 }
4455
4456 queues = min_t(unsigned int,
4457 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4458 err = netif_set_real_num_tx_queues(vdev, queues);
4459 if (err)
4460 goto fwd_queue_err;
4461
2a47fa45
JF		 4462 err = netif_set_real_num_rx_queues(vdev, queues);
4463 if (err)
4464 goto fwd_queue_err;
4465
4466 if (is_valid_ether_addr(vdev->dev_addr))
4467 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4468
4469 ixgbe_fwd_psrtype(accel);
4470 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4471 return err;
4472fwd_queue_err:
4473 ixgbe_fwd_ring_down(vdev, accel);
4474 return err;
4475}
4476
4477static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4478{
4479 struct net_device *upper;
4480 struct list_head *iter;
4481 int err;
4482
4483 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4484 if (netif_is_macvlan(upper)) {
4485 struct macvlan_dev *dfwd = netdev_priv(upper);
4486 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4487
4488 if (dfwd->fwd_priv) {
4489 err = ixgbe_fwd_ring_up(upper, vadapter);
4490 if (err)
4491 continue;
4492 }
4493 }
4494 }
4495}
4496
9a799d71
AK		 4497static void ixgbe_configure(struct ixgbe_adapter *adapter)
4498{
d2f5e7f3
AS		 4499 struct ixgbe_hw *hw = &adapter->hw;
4500
80605c65 4501 ixgbe_configure_pb(adapter);
7a6b6f51 4502#ifdef CONFIG_IXGBE_DCB
67ebd791 4503 ixgbe_configure_dcb(adapter);
2f90b865 4504#endif
b35d4d42
AD		 4505 /*
4506 * We must restore virtualization before VLANs or else
4507 * the VLVF registers will not be populated
4508 */
4509 ixgbe_configure_virtualization(adapter);
9a799d71 4510
4c1d7b4b 4511 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4512 ixgbe_restore_vlan(adapter);
4513
d2f5e7f3
AS		 4514 switch (hw->mac.type) {
4515 case ixgbe_mac_82599EB:
4516 case ixgbe_mac_X540:
4517 hw->mac.ops.disable_rx_buff(hw);
4518 break;
4519 default:
4520 break;
4521 }
4522
c4cf55e5 4523 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4524 ixgbe_init_fdir_signature_82599(&adapter->hw,
4525 adapter->fdir_pballoc);
e4911d57
AD		 4526 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4527 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4528 adapter->fdir_pballoc);
4529 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4530 }
4c1d7b4b 4531
d2f5e7f3
AS		 4532 switch (hw->mac.type) {
4533 case ixgbe_mac_82599EB:
4534 case ixgbe_mac_X540:
4535 hw->mac.ops.enable_rx_buff(hw);
4536 break;
4537 default:
4538 break;
4539 }
4540
7c8ae65a
AD		 4541#ifdef IXGBE_FCOE
4542 /* configure FCoE L2 filters, redirection table, and Rx control */
4543 ixgbe_configure_fcoe(adapter);
4544
4545#endif /* IXGBE_FCOE */
9a799d71
AK		 4546 ixgbe_configure_tx(adapter);
4547 ixgbe_configure_rx(adapter);
2a47fa45 4548 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4549}
4550
e8e26350
PW		 4551static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4552{
4553 switch (hw->phy.type) {
4554 case ixgbe_phy_sfp_avago:
4555 case ixgbe_phy_sfp_ftl:
4556 case ixgbe_phy_sfp_intel:
4557 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4558 case ixgbe_phy_sfp_passive_tyco:
4559 case ixgbe_phy_sfp_passive_unknown:
4560 case ixgbe_phy_sfp_active_unknown:
4561 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4562 case ixgbe_phy_qsfp_passive_unknown:
4563 case ixgbe_phy_qsfp_active_unknown:
4564 case ixgbe_phy_qsfp_intel:
4565 case ixgbe_phy_qsfp_unknown:
d9cd46cd
ET		 4566 /* ixgbe_phy_none is set when no SFP module is present */
4567 case ixgbe_phy_none:
e8e26350 4568 return true;
8917b447
AD		 4569 case ixgbe_phy_nl:
4570 if (hw->mac.type == ixgbe_mac_82598EB)
4571 return true;
e8e26350
PW		 4572 default:
4573 return false;
4574 }
4575}
4576
0ecc061d 4577/**
e8e26350
PW		 4578 * ixgbe_sfp_link_config - set up SFP+ link
4579 * @adapter: pointer to private adapter struct
4580 **/
4581static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4582{
7086400d 4583 /*
52f33af8 4584 * We are assuming the worst case scenario here, and that
7086400d
AD		 4585 * is that an SFP was inserted/removed after the reset
4586 * but before SFP detection was enabled. As such the best
4587 * solution is to just start searching as soon as we start
4588 */
4589 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4590 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4591
7086400d 4592 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4593}
4594
4595/**
4596 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4597 * @hw: pointer to private hardware struct
4598 *
4599 * Returns 0 on success, negative on failure
4600 **/
e8e26350 4601static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4602{
3d292265
JH		 4603 u32 speed;
4604 bool autoneg, link_up = false;
0ecc061d
PWJ		 4605 u32 ret = IXGBE_ERR_LINK_SETUP;
4606
4607 if (hw->mac.ops.check_link)
3d292265 4608 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4609
4610 if (ret)
e90dd264 4611 return ret;
0ecc061d 4612
3d292265
JH		 4613 speed = hw->phy.autoneg_advertised;
4614 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4615 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4616 &autoneg);
0ecc061d 4617 if (ret)
e90dd264 4618 return ret;
0ecc061d 4619
8620a103 4620 if (hw->mac.ops.setup_link)
fd0326f2 4621 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4622
0ecc061d
PWJ		 4623 return ret;
4624}
4625
a34bcfff 4626static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4627{
9a799d71 4628 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4629 u32 gpie = 0;
9a799d71 4630
9b471446 4631 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4632 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4633 IXGBE_GPIE_OCD;
4634 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4635 /*
4636 * use EIAM to auto-mask when MSI-X interrupt is asserted
4637 * this saves a register write for every interrupt
4638 */
4639 switch (hw->mac.type) {
4640 case ixgbe_mac_82598EB:
4641 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4642 break;
9b471446 4643 case ixgbe_mac_82599EB:
b93a2226 4644 case ixgbe_mac_X540:
9a75a1ac
DS		 4645 case ixgbe_mac_X550:
4646 case ixgbe_mac_X550EM_x:
b93a2226 4647 default:
9b471446
JB		 4648 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4649 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4650 break;
4651 }
4652 } else {
021230d4
AV		 4653 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4654 * specifically only auto mask tx and rx interrupts */
4655 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4656 }
9a799d71 4657
a34bcfff
AD		 4658 /* XXX: to interrupt immediately for EICS writes, enable this */
4659 /* gpie |= IXGBE_GPIE_EIMEN; */
4660
4661 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4662 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4663
4664 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4665 case IXGBE_82599_VMDQ_8Q_MASK:
4666 gpie |= IXGBE_GPIE_VTMODE_16;
4667 break;
4668 case IXGBE_82599_VMDQ_4Q_MASK:
4669 gpie |= IXGBE_GPIE_VTMODE_32;
4670 break;
4671 default:
4672 gpie |= IXGBE_GPIE_VTMODE_64;
4673 break;
4674 }
119fc60a
MC		 4675 }
4676
5fdd31f9 4677 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4678 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4679 switch (adapter->hw.mac.type) {
4680 case ixgbe_mac_82599EB:
4681 gpie |= IXGBE_SDP0_GPIEN;
4682 break;
4683 case ixgbe_mac_X540:
4684 gpie |= IXGBE_EIMS_TS;
4685 break;
4686 default:
4687 break;
4688 }
4689 }
5fdd31f9 4690
a34bcfff
AD		 4691 /* Enable fan failure interrupt */
4692 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4693 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4694
2698b208 4695 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4696 gpie |= IXGBE_SDP1_GPIEN;
4697 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4698 }
a34bcfff
AD		 4699
4700 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4701}
4702
c7ccde0f 4703static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4704{
4705 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4706 int err;
a34bcfff
AD		 4707 u32 ctrl_ext;
4708
4709 ixgbe_get_hw_control(adapter);
4710 ixgbe_setup_gpie(adapter);
e8e26350 4711
9a799d71
AK		 4712 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4713 ixgbe_configure_msix(adapter);
4714 else
4715 ixgbe_configure_msi_and_legacy(adapter);
4716
ec74a471
ET		 4717 /* enable the optics for 82599 SFP+ fiber */
4718 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4719 hw->mac.ops.enable_tx_laser(hw);
4720
4e857c58 4721 smp_mb__before_atomic();
9a799d71 4722 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4723 ixgbe_napi_enable_all(adapter);
4724
73c4b7cd
AD		 4725 if (ixgbe_is_sfp(hw)) {
4726 ixgbe_sfp_link_config(adapter);
4727 } else {
4728 err = ixgbe_non_sfp_link_config(hw);
4729 if (err)
4730 e_err(probe, "link_config FAILED %d\n", err);
4731 }
4732
021230d4
AV		 4733 /* clear any pending interrupts, may auto mask */
4734 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4735 ixgbe_irq_enable(adapter, true, true);
9a799d71 4736
bf069c97
DS		 4737 /*
4738 * If this adapter has a fan, check to see if we had a failure
4739 * before we enabled the interrupt.
4740 */
4741 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4742 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4743 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4744 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4745 }
4746
9a799d71
AK		 4747 /* bring the link up in the watchdog, this could race with our first
4748 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4749 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4750 adapter->link_check_timeout = jiffies;
7086400d 4751 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4752
4753 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4754 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4755 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4756 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4757}
4758
d4f80882
AV		 4759void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4760{
4761 WARN_ON(in_interrupt());
7086400d
AD		 4762 /* put off any impending NetWatchDogTimeout */
4763 adapter->netdev->trans_start = jiffies;
4764
d4f80882 4765 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4766 usleep_range(1000, 2000);
d4f80882 4767 ixgbe_down(adapter);
5809a1ae
GR		 4768 /*
4769 * If SR-IOV enabled then wait a bit before bringing the adapter
4770 * back up to give the VFs time to respond to the reset. The
4771 * two second wait is based upon the watchdog timer cycle in
4772 * the VF driver.
4773 */
4774 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4775 msleep(2000);
d4f80882
AV		 4776 ixgbe_up(adapter);
4777 clear_bit(__IXGBE_RESETTING, &adapter->state);
4778}
4779
c7ccde0f 4780void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4781{
4782 /* hardware has been reset, we need to reload some things */
4783 ixgbe_configure(adapter);
4784
c7ccde0f 4785 ixgbe_up_complete(adapter);
9a799d71
AK		 4786}
4787
4788void ixgbe_reset(struct ixgbe_adapter *adapter)
4789{
c44ade9e 4790 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4791 struct net_device *netdev = adapter->netdev;
8ca783ab 4792 int err;
5d7daa35 4793 u8 old_addr[ETH_ALEN];
8ca783ab 4794
b0483c8f
MR		 4795 if (ixgbe_removed(hw->hw_addr))
4796 return;
7086400d
AD		 4797 /* lock SFP init bit to prevent race conditions with the watchdog */
4798 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4799 usleep_range(1000, 2000);
4800
4801 /* clear all SFP and link config related flags while holding SFP_INIT */
4802 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4803 IXGBE_FLAG2_SFP_NEEDS_RESET);
4804 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4805
8ca783ab 4806 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4807 switch (err) {
4808 case 0:
4809 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4810 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4811 break;
4812 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4813 e_dev_err("master disable timed out\n");
da4dd0f7 4814 break;
794caeb2
PWJ		 4815 case IXGBE_ERR_EEPROM_VERSION:
4816 /* We are running on a pre-production device, log a warning */
849c4542 4817 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4818 "Please be aware there may be issues associated with "
849c4542
ET		 4819 "your hardware. If you are experiencing problems "
4820 "please contact your Intel or hardware "
4821 "representative who provided you with this "
4822 "hardware.\n");
794caeb2 4823 break;
da4dd0f7 4824 default:
849c4542 4825 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4826 }
9a799d71 4827
7086400d 4828 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 4829 /* do not flush user set addresses */
4830 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4831 ixgbe_flush_sw_mac_table(adapter);
4832 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 4833
4834 /* update SAN MAC vmdq pool selection */
4835 if (hw->mac.san_mac_rar_index)
4836 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4837
8fecf67c 4838 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4839 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4840}
4841
9a799d71
AK		 4842/**
4843 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4844 * @tx_ring: ring to be cleaned
4845 **/
b6ec895e 4846static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4847{
4848 struct ixgbe_tx_buffer *tx_buffer_info;
4849 unsigned long size;
b6ec895e 4850 u16 i;
9a799d71 4851
84418e3b
AD		 4852 /* ring already cleared, nothing to do */
4853 if (!tx_ring->tx_buffer_info)
4854 return;
9a799d71 4855
84418e3b 4856 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4857 for (i = 0; i < tx_ring->count; i++) {
4858 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4859 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4860 }
4861
dad8a3b3
JF		 4862 netdev_tx_reset_queue(txring_txq(tx_ring));
4863
9a799d71
AK		 4864 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4865 memset(tx_ring->tx_buffer_info, 0, size);
4866
4867 /* Zero out the descriptor ring */
4868 memset(tx_ring->desc, 0, tx_ring->size);
4869
4870 tx_ring->next_to_use = 0;
4871 tx_ring->next_to_clean = 0;
9a799d71
AK		 4872}
4873
4874/**
021230d4 4875 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4876 * @adapter: board private structure
4877 **/
021230d4 4878static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4879{
4880 int i;
4881
021230d4 4882 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4883 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4884}
4885
4886/**
021230d4 4887 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4888 * @adapter: board private structure
4889 **/
021230d4 4890static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4891{
4892 int i;
4893
021230d4 4894 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4895 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4896}
4897
e4911d57
AD		 4898static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4899{
b67bfe0d 4900 struct hlist_node *node2;
e4911d57
AD		 4901 struct ixgbe_fdir_filter *filter;
4902
4903 spin_lock(&adapter->fdir_perfect_lock);
4904
b67bfe0d 4905 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4906 &adapter->fdir_filter_list, fdir_node) {
4907 hlist_del(&filter->fdir_node);
4908 kfree(filter);
4909 }
4910 adapter->fdir_filter_count = 0;
4911
4912 spin_unlock(&adapter->fdir_perfect_lock);
4913}
4914
9a799d71
AK		 4915void ixgbe_down(struct ixgbe_adapter *adapter)
4916{
4917 struct net_device *netdev = adapter->netdev;
7f821875 4918 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4919 struct net_device *upper;
4920 struct list_head *iter;
9a799d71 4921 u32 rxctrl;
bf29ee6c 4922 int i;
9a799d71
AK		 4923
4924 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4925 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4926 return; /* do nothing if already down */
9a799d71
AK		 4927
4928 /* disable receives */
7f821875
JB		 4929 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4930 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4931
2d39d576
YZ		 4932 /* disable all enabled rx queues */
4933 for (i = 0; i < adapter->num_rx_queues; i++)
4934 /* this call also flushes the previous write */
4935 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4936
032b4325 4937 usleep_range(10000, 20000);
9a799d71 4938
7f821875
JB		 4939 netif_tx_stop_all_queues(netdev);
4940
7086400d 4941 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4942 netif_carrier_off(netdev);
4943 netif_tx_disable(netdev);
4944
2a47fa45
JF		 4945 /* disable any upper devices */
4946 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4947 if (netif_is_macvlan(upper)) {
4948 struct macvlan_dev *vlan = netdev_priv(upper);
4949
4950 if (vlan->fwd_priv) {
4951 netif_tx_stop_all_queues(upper);
4952 netif_carrier_off(upper);
4953 netif_tx_disable(upper);
4954 }
4955 }
4956 }
4957
c0dfb90e
JF		 4958 ixgbe_irq_disable(adapter);
4959
4960 ixgbe_napi_disable_all(adapter);
4961
d034acf1
AD		 4962 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4963 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4964 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4965
4966 del_timer_sync(&adapter->service_timer);
4967
34cecbbf 4968 if (adapter->num_vfs) {
8e34d1aa
AD		 4969 /* Clear EITR Select mapping */
4970 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4971
4972 /* Mark all the VFs as inactive */
4973 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4974 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4975
34cecbbf
AD		 4976 /* ping all the active vfs to let them know we are going down */
4977 ixgbe_ping_all_vfs(adapter);
4978
4979 /* Disable all VFTE/VFRE TX/RX */
4980 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4981 }
4982
7f821875
JB		 4983 /* disable transmits in the hardware now that interrupts are off */
4984 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4985 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4986 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4987 }
34cecbbf 4988
9a75a1ac 4989 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 4990 switch (hw->mac.type) {
4991 case ixgbe_mac_82599EB:
b93a2226 4992 case ixgbe_mac_X540:
9a75a1ac
DS		 4993 case ixgbe_mac_X550:
4994 case ixgbe_mac_X550EM_x:
88512539 4995 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4996 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4997 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4998 break;
4999 default:
5000 break;
5001 }
7f821875 5002
6f4a0e45
PL		 5003 if (!pci_channel_offline(adapter->pdev))
5004 ixgbe_reset(adapter);
c6ecf39a 5005
ec74a471
ET		 5006 /* power down the optics for 82599 SFP+ fiber */
5007 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5008 hw->mac.ops.disable_tx_laser(hw);
5009
9a799d71
AK		 5010 ixgbe_clean_all_tx_rings(adapter);
5011 ixgbe_clean_all_rx_rings(adapter);
5012
5dd2d332 5013#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5014 /* since we reset the hardware DCA settings were cleared */
e35ec126 5015 ixgbe_setup_dca(adapter);
96b0e0f6 5016#endif
9a799d71
AK		 5017}
5018
9a799d71
AK		 5019/**
5020 * ixgbe_tx_timeout - Respond to a Tx Hang
5021 * @netdev: network interface device structure
5022 **/
5023static void ixgbe_tx_timeout(struct net_device *netdev)
5024{
5025 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5026
5027 /* Do the reset outside of interrupt context */
c83c6cbd 5028 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5029}
5030
9a799d71
AK		 5031/**
5032 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5033 * @adapter: board private structure to initialize
5034 *
5035 * ixgbe_sw_init initializes the Adapter private data structure.
5036 * Fields are initialized based on PCI device information and
5037 * OS network device settings (MTU size).
5038 **/
9f9a12f8 5039static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5040{
5041 struct ixgbe_hw *hw = &adapter->hw;
5042 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5043 unsigned int rss, fdir;
cb6d0f5e 5044 u32 fwsm;
7a6b6f51 5045#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5046 int j;
5047 struct tc_configuration *tc;
5048#endif
021230d4 5049
c44ade9e
JB		 5050 /* PCI config space info */
5051
5052 hw->vendor_id = pdev->vendor;
5053 hw->device_id = pdev->device;
5054 hw->revision_id = pdev->revision;
5055 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5056 hw->subsystem_device_id = pdev->subsystem_device;
5057
8fc3bb6d 5058 /* Set common capability flags and settings */
3ed69d7e 5059 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5060 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5061 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5062 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5063 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5064 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5065 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5066 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5067 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5068#ifdef CONFIG_IXGBE_DCA
5069 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5070#endif
5071#ifdef IXGBE_FCOE
5072 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5073 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5074#ifdef CONFIG_IXGBE_DCB
5075 /* Default traffic class to use for FCoE */
5076 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5077#endif /* CONFIG_IXGBE_DCB */
5078#endif /* IXGBE_FCOE */
5079
5d7daa35
JK		 5080 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5081 hw->mac.num_rar_entries,
5082 GFP_ATOMIC);
5083
8fc3bb6d 5084 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5085 switch (hw->mac.type) {
5086 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5087 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5088 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5089
bf069c97
DS		 5090 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5091 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5092
49c7ffbe 5093 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5094 adapter->ring_feature[RING_F_FDIR].limit = 0;
5095 adapter->atr_sample_rate = 0;
5096 adapter->fdir_pballoc = 0;
5097#ifdef IXGBE_FCOE
5098 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5099 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5100#ifdef CONFIG_IXGBE_DCB
5101 adapter->fcoe.up = 0;
5102#endif /* IXGBE_DCB */
5103#endif /* IXGBE_FCOE */
5104 break;
5105 case ixgbe_mac_82599EB:
5106 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5107 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5108 break;
b93a2226 5109 case ixgbe_mac_X540:
cb6d0f5e
JK		 5110 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5111 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5112 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5113 break;
9a75a1ac
DS		 5114 case ixgbe_mac_X550EM_x:
5115 case ixgbe_mac_X550:
5116#ifdef CONFIG_IXGBE_DCA
5117 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5118#endif
5119 break;
bd508178
AD		 5120 default:
5121 break;
f8212f97 5122 }
2f90b865 5123
7c8ae65a
AD		 5124#ifdef IXGBE_FCOE
5125 /* FCoE support exists, always init the FCoE lock */
5126 spin_lock_init(&adapter->fcoe.lock);
5127
5128#endif
1fc5f038
AD		 5129 /* n-tuple support exists, always init our spinlock */
5130 spin_lock_init(&adapter->fdir_perfect_lock);
5131
7a6b6f51 5132#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5133 switch (hw->mac.type) {
5134 case ixgbe_mac_X540:
9a75a1ac
DS		 5135 case ixgbe_mac_X550:
5136 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5137 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5138 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5139 break;
5140 default:
5141 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5142 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5143 break;
5144 }
5145
2f90b865
AD		 5146 /* Configure DCB traffic classes */
5147 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5148 tc = &adapter->dcb_cfg.tc_config[j];
5149 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5150 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5151 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5152 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5153 tc->dcb_pfc = pfc_disabled;
5154 }
4de2a022
JF		 5155
5156 /* Initialize default user to priority mapping, UPx->TC0 */
5157 tc = &adapter->dcb_cfg.tc_config[0];
5158 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5159 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5160
2f90b865
AD		 5161 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5162 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5163 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5164 adapter->dcb_set_bitmap = 0x00;
3032309b 5165 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5166 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5167 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5168
5169#endif
9a799d71
AK		 5170
5171 /* default flow control settings */
cd7664f6 5172 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5173 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5174 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5175 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5176 hw->fc.send_xon = true;
73d80953 5177 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5178
99d74487 5179#ifdef CONFIG_PCI_IOV
170e8543
JK		 5180 if (max_vfs > 0)
5181 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5182
99d74487 5183 /* assign number of SR-IOV VFs */
170e8543 5184 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5185 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5186 adapter->num_vfs = 0;
5187 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5188 } else {
5189 adapter->num_vfs = max_vfs;
5190 }
5191 }
5192#endif /* CONFIG_PCI_IOV */
99d74487 5193
30efa5a3 5194 /* enable itr by default in dynamic mode */
f7554a2b 5195 adapter->rx_itr_setting = 1;
f7554a2b 5196 adapter->tx_itr_setting = 1;
30efa5a3 5197
30efa5a3
JB		 5198 /* set default ring sizes */
5199 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5200 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5201
bd198058 5202 /* set default work limits */
59224555 5203 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5204
9a799d71 5205 /* initialize eeprom parameters */
c44ade9e 5206 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5207 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5208 return -EIO;
5209 }
5210
2a47fa45
JF		 5211 /* PF holds first pool slot */
5212 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5213 set_bit(__IXGBE_DOWN, &adapter->state);
5214
5215 return 0;
5216}
5217
5218/**
5219 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5220 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5221 *
5222 * Return 0 on success, negative on failure
5223 **/
b6ec895e 5224int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5225{
b6ec895e 5226 struct device *dev = tx_ring->dev;
de88eeeb 5227 int orig_node = dev_to_node(dev);
ca8dfe25 5228 int ring_node = -1;
9a799d71
AK		 5229 int size;
5230
3a581073 5231 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5232
5233 if (tx_ring->q_vector)
ca8dfe25 5234 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5235
ca8dfe25 5236 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5237 if (!tx_ring->tx_buffer_info)
89bf67f1 5238 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5239 if (!tx_ring->tx_buffer_info)
5240 goto err;
9a799d71 5241
827da44c
JS		 5242 u64_stats_init(&tx_ring->syncp);
5243
9a799d71 5244 /* round up to nearest 4K */
12207e49 5245 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5246 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5247
ca8dfe25 5248 set_dev_node(dev, ring_node);
de88eeeb
AD		 5249 tx_ring->desc = dma_alloc_coherent(dev,
5250 tx_ring->size,
5251 &tx_ring->dma,
5252 GFP_KERNEL);
5253 set_dev_node(dev, orig_node);
5254 if (!tx_ring->desc)
5255 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5256 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5257 if (!tx_ring->desc)
5258 goto err;
9a799d71 5259
3a581073
JB		 5260 tx_ring->next_to_use = 0;
5261 tx_ring->next_to_clean = 0;
9a799d71 5262 return 0;
e01c31a5
JB		 5263
5264err:
5265 vfree(tx_ring->tx_buffer_info);
5266 tx_ring->tx_buffer_info = NULL;
b6ec895e 5267 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5268 return -ENOMEM;
9a799d71
AK		 5269}
5270
69888674
AD		 5271/**
5272 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5273 * @adapter: board private structure
5274 *
5275 * If this function returns with an error, then it's possible one or
5276 * more of the rings is populated (while the rest are not). It is the
5277 * callers duty to clean those orphaned rings.
5278 *
5279 * Return 0 on success, negative on failure
5280 **/
5281static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5282{
5283 int i, err = 0;
5284
5285 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5286 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5287 if (!err)
5288 continue;
de3d5b94 5289
396e799c 5290 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5291 goto err_setup_tx;
69888674
AD		 5292 }
5293
de3d5b94
AD		 5294 return 0;
5295err_setup_tx:
5296 /* rewind the index freeing the rings as we go */
5297 while (i--)
5298 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5299 return err;
5300}
5301
9a799d71
AK		 5302/**
5303 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5304 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5305 *
5306 * Returns 0 on success, negative on failure
5307 **/
b6ec895e 5308int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5309{
b6ec895e 5310 struct device *dev = rx_ring->dev;
de88eeeb 5311 int orig_node = dev_to_node(dev);
ca8dfe25 5312 int ring_node = -1;
021230d4 5313 int size;
9a799d71 5314
3a581073 5315 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5316
5317 if (rx_ring->q_vector)
ca8dfe25 5318 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5319
ca8dfe25 5320 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5321 if (!rx_ring->rx_buffer_info)
89bf67f1 5322 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5323 if (!rx_ring->rx_buffer_info)
5324 goto err;
9a799d71 5325
827da44c
JS		 5326 u64_stats_init(&rx_ring->syncp);
5327
9a799d71 5328 /* Round up to nearest 4K */
3a581073
JB		 5329 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5330 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5331
ca8dfe25 5332 set_dev_node(dev, ring_node);
de88eeeb
AD		 5333 rx_ring->desc = dma_alloc_coherent(dev,
5334 rx_ring->size,
5335 &rx_ring->dma,
5336 GFP_KERNEL);
5337 set_dev_node(dev, orig_node);
5338 if (!rx_ring->desc)
5339 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5340 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5341 if (!rx_ring->desc)
5342 goto err;
9a799d71 5343
3a581073
JB		 5344 rx_ring->next_to_clean = 0;
5345 rx_ring->next_to_use = 0;
9a799d71
AK		 5346
5347 return 0;
b6ec895e
AD		 5348err:
5349 vfree(rx_ring->rx_buffer_info);
5350 rx_ring->rx_buffer_info = NULL;
5351 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5352 return -ENOMEM;
9a799d71
AK		 5353}
5354
69888674
AD		 5355/**
5356 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5357 * @adapter: board private structure
5358 *
5359 * If this function returns with an error, then it's possible one or
5360 * more of the rings is populated (while the rest are not). It is the
5361 * callers duty to clean those orphaned rings.
5362 *
5363 * Return 0 on success, negative on failure
5364 **/
69888674
AD		 5365static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5366{
5367 int i, err = 0;
5368
5369 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5370 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5371 if (!err)
5372 continue;
de3d5b94 5373
396e799c 5374 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5375 goto err_setup_rx;
69888674
AD		 5376 }
5377
7c8ae65a
AD		 5378#ifdef IXGBE_FCOE
5379 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5380 if (!err)
5381#endif
5382 return 0;
de3d5b94
AD		 5383err_setup_rx:
5384 /* rewind the index freeing the rings as we go */
5385 while (i--)
5386 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5387 return err;
5388}
5389
9a799d71
AK		 5390/**
5391 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5392 * @tx_ring: Tx descriptor ring for a specific queue
5393 *
5394 * Free all transmit software resources
5395 **/
b6ec895e 5396void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5397{
b6ec895e 5398 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5399
5400 vfree(tx_ring->tx_buffer_info);
5401 tx_ring->tx_buffer_info = NULL;
5402
b6ec895e
AD		 5403 /* if not set, then don't free */
5404 if (!tx_ring->desc)
5405 return;
5406
5407 dma_free_coherent(tx_ring->dev, tx_ring->size,
5408 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5409
5410 tx_ring->desc = NULL;
5411}
5412
5413/**
5414 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5415 * @adapter: board private structure
5416 *
5417 * Free all transmit software resources
5418 **/
5419static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5420{
5421 int i;
5422
5423 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5424 if (adapter->tx_ring[i]->desc)
b6ec895e 5425 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5426}
5427
5428/**
b4617240 5429 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5430 * @rx_ring: ring to clean the resources from
5431 *
5432 * Free all receive software resources
5433 **/
b6ec895e 5434void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5435{
b6ec895e 5436 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5437
5438 vfree(rx_ring->rx_buffer_info);
5439 rx_ring->rx_buffer_info = NULL;
5440
b6ec895e
AD		 5441 /* if not set, then don't free */
5442 if (!rx_ring->desc)
5443 return;
5444
5445 dma_free_coherent(rx_ring->dev, rx_ring->size,
5446 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5447
5448 rx_ring->desc = NULL;
5449}
5450
5451/**
5452 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5453 * @adapter: board private structure
5454 *
5455 * Free all receive software resources
5456 **/
5457static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5458{
5459 int i;
5460
7c8ae65a
AD		 5461#ifdef IXGBE_FCOE
5462 ixgbe_free_fcoe_ddp_resources(adapter);
5463
5464#endif
9a799d71 5465 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5466 if (adapter->rx_ring[i]->desc)
b6ec895e 5467 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5468}
5469
9a799d71
AK		 5470/**
5471 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5472 * @netdev: network interface device structure
5473 * @new_mtu: new value for maximum frame size
5474 *
5475 * Returns 0 on success, negative on failure
5476 **/
5477static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5478{
5479 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5480 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5481
42c783c5 5482 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5483 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5484 return -EINVAL;
5485
5486 /*
872844dd
AD		 5487 * For 82599EB we cannot allow legacy VFs to enable their receive
5488 * paths when MTU greater than 1500 is configured. So display a
5489 * warning that legacy VFs will be disabled.
655309e9
AD		 5490 */
5491 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5492 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5493 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5494 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5495
396e799c 5496 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5497
021230d4 5498 /* must set new MTU before calling down or up */
9a799d71
AK		 5499 netdev->mtu = new_mtu;
5500
d4f80882
AV		 5501 if (netif_running(netdev))
5502 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5503
5504 return 0;
5505}
5506
5507/**
5508 * ixgbe_open - Called when a network interface is made active
5509 * @netdev: network interface device structure
5510 *
5511 * Returns 0 on success, negative value on failure
5512 *
5513 * The open entry point is called when a network interface is made
5514 * active by the system (IFF_UP). At this point all resources needed
5515 * for transmit and receive operations are allocated, the interrupt
5516 * handler is registered with the OS, the watchdog timer is started,
5517 * and the stack is notified that the interface is ready.
5518 **/
5519static int ixgbe_open(struct net_device *netdev)
5520{
5521 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5522 int err, queues;
4bebfaa5
AK		 5523
5524 /* disallow open during test */
5525 if (test_bit(__IXGBE_TESTING, &adapter->state))
5526 return -EBUSY;
9a799d71 5527
54386467
JB		 5528 netif_carrier_off(netdev);
5529
9a799d71
AK		 5530 /* allocate transmit descriptors */
5531 err = ixgbe_setup_all_tx_resources(adapter);
5532 if (err)
5533 goto err_setup_tx;
5534
9a799d71
AK		 5535 /* allocate receive descriptors */
5536 err = ixgbe_setup_all_rx_resources(adapter);
5537 if (err)
5538 goto err_setup_rx;
5539
5540 ixgbe_configure(adapter);
5541
021230d4 5542 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5543 if (err)
5544 goto err_req_irq;
5545
ac802f5d 5546 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5547 if (adapter->num_rx_pools > 1)
5548 queues = adapter->num_rx_queues_per_pool;
5549 else
5550 queues = adapter->num_tx_queues;
5551
5552 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5553 if (err)
5554 goto err_set_queues;
5555
2a47fa45
JF		 5556 if (adapter->num_rx_pools > 1 &&
5557 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5558 queues = IXGBE_MAX_L2A_QUEUES;
5559 else
5560 queues = adapter->num_rx_queues;
5561 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5562 if (err)
5563 goto err_set_queues;
5564
1a71ab24 5565 ixgbe_ptp_init(adapter);
1a71ab24 5566
c7ccde0f 5567 ixgbe_up_complete(adapter);
9a799d71
AK		 5568
5569 return 0;
5570
ac802f5d
AD		 5571err_set_queues:
5572 ixgbe_free_irq(adapter);
9a799d71 5573err_req_irq:
a20a1199 5574 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5575err_setup_rx:
a20a1199 5576 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5577err_setup_tx:
9a799d71
AK		 5578 ixgbe_reset(adapter);
5579
5580 return err;
5581}
5582
a0cccce2
JK		 5583static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5584{
5585 ixgbe_ptp_suspend(adapter);
5586
5587 ixgbe_down(adapter);
5588 ixgbe_free_irq(adapter);
5589
5590 ixgbe_free_all_tx_resources(adapter);
5591 ixgbe_free_all_rx_resources(adapter);
5592}
5593
9a799d71
AK		 5594/**
5595 * ixgbe_close - Disables a network interface
5596 * @netdev: network interface device structure
5597 *
5598 * Returns 0, this is not allowed to fail
5599 *
5600 * The close entry point is called when an interface is de-activated
5601 * by the OS. The hardware is still under the drivers control, but
5602 * needs to be disabled. A global MAC reset is issued to stop the
5603 * hardware, and all transmit and receive resources are freed.
5604 **/
5605static int ixgbe_close(struct net_device *netdev)
5606{
5607 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5608
1a71ab24 5609 ixgbe_ptp_stop(adapter);
1a71ab24 5610
a0cccce2 5611 ixgbe_close_suspend(adapter);
9a799d71 5612
e4911d57
AD		 5613 ixgbe_fdir_filter_exit(adapter);
5614
5eba3699 5615 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5616
5617 return 0;
5618}
5619
b3c8b4ba
AD		 5620#ifdef CONFIG_PM
5621static int ixgbe_resume(struct pci_dev *pdev)
5622{
c60fbb00
AD		 5623 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5624 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5625 u32 err;
5626
0391bbe3 5627 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5628 pci_set_power_state(pdev, PCI_D0);
5629 pci_restore_state(pdev);
656ab817
DS		 5630 /*
5631 * pci_restore_state clears dev->state_saved so call
5632 * pci_save_state to restore it.
5633 */
5634 pci_save_state(pdev);
9ce77666 5635
5636 err = pci_enable_device_mem(pdev);
b3c8b4ba 5637 if (err) {
849c4542 5638 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5639 return err;
5640 }
4e857c58 5641 smp_mb__before_atomic();
41c62843 5642 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5643 pci_set_master(pdev);
5644
dd4d8ca6 5645 pci_wake_from_d3(pdev, false);
b3c8b4ba 5646
b3c8b4ba
AD		 5647 ixgbe_reset(adapter);
5648
495dce12
WJP		 5649 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5650
ac802f5d
AD		 5651 rtnl_lock();
5652 err = ixgbe_init_interrupt_scheme(adapter);
5653 if (!err && netif_running(netdev))
c60fbb00 5654 err = ixgbe_open(netdev);
ac802f5d
AD		 5655
5656 rtnl_unlock();
5657
5658 if (err)
5659 return err;
b3c8b4ba
AD		 5660
5661 netif_device_attach(netdev);
5662
5663 return 0;
5664}
b3c8b4ba 5665#endif /* CONFIG_PM */
9d8d05ae
RW		 5666
5667static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5668{
c60fbb00
AD		 5669 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5670 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5671 struct ixgbe_hw *hw = &adapter->hw;
5672 u32 ctrl, fctrl;
5673 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5674#ifdef CONFIG_PM
5675 int retval = 0;
5676#endif
5677
5678 netif_device_detach(netdev);
5679
499ab5cc 5680 rtnl_lock();
a0cccce2
JK		 5681 if (netif_running(netdev))
5682 ixgbe_close_suspend(adapter);
499ab5cc 5683 rtnl_unlock();
b3c8b4ba 5684
5f5ae6fc
AD		 5685 ixgbe_clear_interrupt_scheme(adapter);
5686
b3c8b4ba
AD		 5687#ifdef CONFIG_PM
5688 retval = pci_save_state(pdev);
5689 if (retval)
5690 return retval;
4df10466 5691
b3c8b4ba 5692#endif
f4f1040a
JK		 5693 if (hw->mac.ops.stop_link_on_d3)
5694 hw->mac.ops.stop_link_on_d3(hw);
5695
e8e26350
PW		 5696 if (wufc) {
5697 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5698
ec74a471
ET		 5699 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5700 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5701 hw->mac.ops.enable_tx_laser(hw);
5702
e8e26350
PW		 5703 /* turn on all-multi mode if wake on multicast is enabled */
5704 if (wufc & IXGBE_WUFC_MC) {
5705 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5706 fctrl |= IXGBE_FCTRL_MPE;
5707 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5708 }
5709
5710 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5711 ctrl |= IXGBE_CTRL_GIO_DIS;
5712 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5713
5714 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5715 } else {
5716 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5717 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5718 }
5719
bd508178
AD		 5720 switch (hw->mac.type) {
5721 case ixgbe_mac_82598EB:
dd4d8ca6 5722 pci_wake_from_d3(pdev, false);
bd508178
AD		 5723 break;
5724 case ixgbe_mac_82599EB:
b93a2226 5725 case ixgbe_mac_X540:
9a75a1ac
DS		 5726 case ixgbe_mac_X550:
5727 case ixgbe_mac_X550EM_x:
bd508178
AD		 5728 pci_wake_from_d3(pdev, !!wufc);
5729 break;
5730 default:
5731 break;
5732 }
b3c8b4ba 5733
9d8d05ae
RW		 5734 *enable_wake = !!wufc;
5735
b3c8b4ba
AD		 5736 ixgbe_release_hw_control(adapter);
5737
41c62843
MR		 5738 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5739 pci_disable_device(pdev);
b3c8b4ba 5740
9d8d05ae
RW		 5741 return 0;
5742}
5743
5744#ifdef CONFIG_PM
5745static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5746{
5747 int retval;
5748 bool wake;
5749
5750 retval = __ixgbe_shutdown(pdev, &wake);
5751 if (retval)
5752 return retval;
5753
5754 if (wake) {
5755 pci_prepare_to_sleep(pdev);
5756 } else {
5757 pci_wake_from_d3(pdev, false);
5758 pci_set_power_state(pdev, PCI_D3hot);
5759 }
b3c8b4ba
AD		 5760
5761 return 0;
5762}
9d8d05ae 5763#endif /* CONFIG_PM */
b3c8b4ba
AD		 5764
5765static void ixgbe_shutdown(struct pci_dev *pdev)
5766{
9d8d05ae
RW		 5767 bool wake;
5768
5769 __ixgbe_shutdown(pdev, &wake);
5770
5771 if (system_state == SYSTEM_POWER_OFF) {
5772 pci_wake_from_d3(pdev, wake);
5773 pci_set_power_state(pdev, PCI_D3hot);
5774 }
b3c8b4ba
AD		 5775}
5776
9a799d71
AK		 5777/**
5778 * ixgbe_update_stats - Update the board statistics counters.
5779 * @adapter: board private structure
5780 **/
5781void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5782{
2d86f139 5783 struct net_device *netdev = adapter->netdev;
9a799d71 5784 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5785 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5786 u64 total_mpc = 0;
5787 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5788 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5789 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5790 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5791
d08935c2
DS		 5792 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5793 test_bit(__IXGBE_RESETTING, &adapter->state))
5794 return;
5795
94b982b2 5796 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5797 u64 rsc_count = 0;
94b982b2 5798 u64 rsc_flush = 0;
94b982b2 5799 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5800 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5801 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5802 }
5803 adapter->rsc_total_count = rsc_count;
5804 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5805 }
5806
5b7da515
AD		 5807 for (i = 0; i < adapter->num_rx_queues; i++) {
5808 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5809 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5810 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5811 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5812 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5813 bytes += rx_ring->stats.bytes;
5814 packets += rx_ring->stats.packets;
5815 }
5816 adapter->non_eop_descs = non_eop_descs;
5817 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5818 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5819 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5820 netdev->stats.rx_bytes = bytes;
5821 netdev->stats.rx_packets = packets;
5822
5823 bytes = 0;
5824 packets = 0;
7ca3bc58 5825 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5826 for (i = 0; i < adapter->num_tx_queues; i++) {
5827 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5828 restart_queue += tx_ring->tx_stats.restart_queue;
5829 tx_busy += tx_ring->tx_stats.tx_busy;
5830 bytes += tx_ring->stats.bytes;
5831 packets += tx_ring->stats.packets;
5832 }
eb985f09 5833 adapter->restart_queue = restart_queue;
5b7da515
AD		 5834 adapter->tx_busy = tx_busy;
5835 netdev->stats.tx_bytes = bytes;
5836 netdev->stats.tx_packets = packets;
7ca3bc58 5837
7ca647bd 5838 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5839
5840 /* 8 register reads */
6f11eef7
AV		 5841 for (i = 0; i < 8; i++) {
5842 /* for packet buffers not used, the register should read 0 */
5843 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5844 missed_rx += mpc;
7ca647bd
JP		 5845 hwstats->mpc[i] += mpc;
5846 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5847 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5848 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5849 switch (hw->mac.type) {
5850 case ixgbe_mac_82598EB:
1a70db4b
ET		 5851 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5852 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5853 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5854 hwstats->pxonrxc[i] +=
5855 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5856 break;
5857 case ixgbe_mac_82599EB:
b93a2226 5858 case ixgbe_mac_X540:
9a75a1ac
DS		 5859 case ixgbe_mac_X550:
5860 case ixgbe_mac_X550EM_x:
bd508178
AD		 5861 hwstats->pxonrxc[i] +=
5862 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5863 break;
5864 default:
5865 break;
e8e26350 5866 }
6f11eef7 5867 }
1a70db4b
ET		 5868
5869 /*16 register reads */
5870 for (i = 0; i < 16; i++) {
5871 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5872 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5873 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 5874 (hw->mac.type == ixgbe_mac_X540) ||
5875 (hw->mac.type == ixgbe_mac_X550) ||
5876 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 5877 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5878 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5879 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5880 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5881 }
5882 }
5883
7ca647bd 5884 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5885 /* work around hardware counting issue */
7ca647bd 5886 hwstats->gprc -= missed_rx;
6f11eef7 5887
c84d324c
JF		 5888 ixgbe_update_xoff_received(adapter);
5889
6f11eef7 5890 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5891 switch (hw->mac.type) {
5892 case ixgbe_mac_82598EB:
5893 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5894 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5895 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5896 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5897 break;
b93a2226 5898 case ixgbe_mac_X540:
9a75a1ac
DS		 5899 case ixgbe_mac_X550:
5900 case ixgbe_mac_X550EM_x:
5901 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 5902 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5903 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5904 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5905 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5906 case ixgbe_mac_82599EB:
a4d4f629
AD		 5907 for (i = 0; i < 16; i++)
5908 adapter->hw_rx_no_dma_resources +=
5909 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5910 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5911 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5912 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5913 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5914 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5915 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5916 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5917 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5918 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5919#ifdef IXGBE_FCOE
7ca647bd
JP		 5920 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5921 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5922 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5923 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5924 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5925 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5926 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5927 if (adapter->fcoe.ddp_pool) {
5928 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5929 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5930 unsigned int cpu;
5931 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5932 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5933 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5934 noddp += ddp_pool->noddp;
5935 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5936 }
5a1ee270
AD		 5937 hwstats->fcoe_noddp = noddp;
5938 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5939 }
6d45522c 5940#endif /* IXGBE_FCOE */
bd508178
AD		 5941 break;
5942 default:
5943 break;
e8e26350 5944 }
9a799d71 5945 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5946 hwstats->bprc += bprc;
5947 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5948 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5949 hwstats->mprc -= bprc;
5950 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5951 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5952 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5953 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5954 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5955 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5956 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5957 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5958 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5959 hwstats->lxontxc += lxon;
6f11eef7 5960 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5961 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5962 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5963 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5964 /*
5965 * 82598 errata - tx of flow control packets is included in tx counters
5966 */
5967 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5968 hwstats->gptc -= xon_off_tot;
5969 hwstats->mptc -= xon_off_tot;
5970 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5971 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5972 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5973 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5974 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5975 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5976 hwstats->ptc64 -= xon_off_tot;
5977 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5978 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5979 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5980 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5981 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5982 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5983
5984 /* Fill out the OS statistics structure */
7ca647bd 5985 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5986
5987 /* Rx Errors */
7ca647bd 5988 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5989 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5990 netdev->stats.rx_length_errors = hwstats->rlec;
5991 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5992 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5993}
5994
5995/**
d034acf1 5996 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5997 * @adapter: pointer to the device adapter structure
9a799d71 5998 **/
d034acf1 5999static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6000{
cf8280ee 6001 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6002 int i;
cf8280ee 6003
d034acf1
AD		 6004 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6005 return;
6006
6007 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6008
d034acf1 6009 /* if interface is down do nothing */
fe49f04a 6010 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6011 return;
6012
6013 /* do nothing if we are not using signature filters */
6014 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6015 return;
6016
6017 adapter->fdir_overflow++;
6018
93c52dd0
AD		 6019 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6020 for (i = 0; i < adapter->num_tx_queues; i++)
6021 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6022 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6023 /* re-enable flow director interrupts */
6024 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6025 } else {
6026 e_err(probe, "failed to finish FDIR re-initialization, "
6027 "ignored adding FDIR ATR filters\n");
6028 }
93c52dd0
AD		 6029}
6030
6031/**
6032 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6033 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6034 *
6035 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6036 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6037 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6038 * determine if a hang has occurred.
93c52dd0
AD		 6039 */
6040static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6041{
cf8280ee 6042 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6043 u64 eics = 0;
6044 int i;
cf8280ee 6045
09f40aed 6046 /* If we're down, removing or resetting, just bail */
93c52dd0 6047 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6048 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6049 test_bit(__IXGBE_RESETTING, &adapter->state))
6050 return;
22d5a71b 6051
93c52dd0
AD		 6052 /* Force detection of hung controller */
6053 if (netif_carrier_ok(adapter->netdev)) {
6054 for (i = 0; i < adapter->num_tx_queues; i++)
6055 set_check_for_tx_hang(adapter->tx_ring[i]);
6056 }
22d5a71b 6057
fe49f04a
AD		 6058 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6059 /*
6060 * for legacy and MSI interrupts don't set any bits
6061 * that are enabled for EIAM, because this operation
6062 * would set *both* EIMS and EICS for any bit in EIAM
6063 */
6064 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6065 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6066 } else {
6067 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6068 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6069 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6070 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6071 eics |= ((u64)1 << i);
6072 }
cf8280ee 6073 }
9a799d71 6074
93c52dd0 6075 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6076 ixgbe_irq_rearm_queues(adapter, eics);
6077
cf8280ee
JB		 6078}
6079
e8e26350 6080/**
93c52dd0 6081 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6082 * @adapter: pointer to the device adapter structure
6083 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6084 **/
93c52dd0 6085static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6086{
e8e26350 6087 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6088 u32 link_speed = adapter->link_speed;
6089 bool link_up = adapter->link_up;
041441d0 6090 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6091
93c52dd0
AD		 6092 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6093 return;
6094
6095 if (hw->mac.ops.check_link) {
6096 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6097 } else {
93c52dd0
AD		 6098 /* always assume link is up, if no check link function */
6099 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6100 link_up = true;
c4cf55e5 6101 }
041441d0
AD		 6102
6103 if (adapter->ixgbe_ieee_pfc)
6104 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6105
3ebe8fde 6106 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6107 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6108 ixgbe_set_rx_drop_en(adapter);
6109 }
93c52dd0
AD		 6110
6111 if (link_up ||
6112 time_after(jiffies, (adapter->link_check_timeout +
6113 IXGBE_TRY_LINK_TIMEOUT))) {
6114 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6115 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6116 IXGBE_WRITE_FLUSH(hw);
6117 }
6118
6119 adapter->link_up = link_up;
6120 adapter->link_speed = link_speed;
e8e26350
PW		 6121}
6122
107d3018
AD		 6123static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6124{
6125#ifdef CONFIG_IXGBE_DCB
6126 struct net_device *netdev = adapter->netdev;
6127 struct dcb_app app = {
6128 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6129 .protocol = 0,
6130 };
6131 u8 up = 0;
6132
6133 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6134 up = dcb_ieee_getapp_mask(netdev, &app);
6135
6136 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6137#endif
6138}
6139
e8e26350 6140/**
93c52dd0
AD		 6141 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6142 * print link up message
49ce9c2c 6143 * @adapter: pointer to the device adapter structure
e8e26350 6144 **/
93c52dd0 6145static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6146{
93c52dd0 6147 struct net_device *netdev = adapter->netdev;
e8e26350 6148 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6149 struct net_device *upper;
6150 struct list_head *iter;
93c52dd0
AD		 6151 u32 link_speed = adapter->link_speed;
6152 bool flow_rx, flow_tx;
e8e26350 6153
93c52dd0
AD		 6154 /* only continue if link was previously down */
6155 if (netif_carrier_ok(netdev))
a985b6c3 6156 return;
63d6e1d8 6157
93c52dd0 6158 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6159
93c52dd0
AD		 6160 switch (hw->mac.type) {
6161 case ixgbe_mac_82598EB: {
6162 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6163 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6164 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6165 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6166 }
6167 break;
6168 case ixgbe_mac_X540:
9a75a1ac
DS		 6169 case ixgbe_mac_X550:
6170 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6171 case ixgbe_mac_82599EB: {
6172 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6173 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6174 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6175 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6176 }
6177 break;
6178 default:
6179 flow_tx = false;
6180 flow_rx = false;
6181 break;
e8e26350 6182 }
3a6a4eda 6183
6cb562d6
JK		 6184 adapter->last_rx_ptp_check = jiffies;
6185
8fecf67c 6186 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6187 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6188
93c52dd0
AD		 6189 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6190 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6191 "10 Gbps" :
6192 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6193 "1 Gbps" :
6194 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6195 "100 Mbps" :
6196 "unknown speed"))),
6197 ((flow_rx && flow_tx) ? "RX/TX" :
6198 (flow_rx ? "RX" :
6199 (flow_tx ? "TX" : "None"))));
e8e26350 6200
93c52dd0 6201 netif_carrier_on(netdev);
93c52dd0 6202 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6203
cdc04dcc
ET		 6204 /* enable transmits */
6205 netif_tx_wake_all_queues(adapter->netdev);
6206
6207 /* enable any upper devices */
6208 rtnl_lock();
6209 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6210 if (netif_is_macvlan(upper)) {
6211 struct macvlan_dev *vlan = netdev_priv(upper);
6212
6213 if (vlan->fwd_priv)
6214 netif_tx_wake_all_queues(upper);
6215 }
6216 }
6217 rtnl_unlock();
6218
107d3018
AD		 6219 /* update the default user priority for VFs */
6220 ixgbe_update_default_up(adapter);
6221
befa2af7
AD		 6222 /* ping all the active vfs to let them know link has changed */
6223 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6224}
6225
c4cf55e5 6226/**
93c52dd0
AD		 6227 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6228 * print link down message
49ce9c2c 6229 * @adapter: pointer to the adapter structure
c4cf55e5 6230 **/
581330ba 6231static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6232{
cf8280ee 6233 struct net_device *netdev = adapter->netdev;
c4cf55e5 6234 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6235
93c52dd0
AD		 6236 adapter->link_up = false;
6237 adapter->link_speed = 0;
cf8280ee 6238
93c52dd0
AD		 6239 /* only continue if link was up previously */
6240 if (!netif_carrier_ok(netdev))
6241 return;
264857b8 6242
93c52dd0
AD		 6243 /* poll for SFP+ cable when link is down */
6244 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6245 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6246
8fecf67c 6247 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6248 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6249
93c52dd0
AD		 6250 e_info(drv, "NIC Link is Down\n");
6251 netif_carrier_off(netdev);
befa2af7
AD		 6252
6253 /* ping all the active vfs to let them know link has changed */
6254 ixgbe_ping_all_vfs(adapter);
93c52dd0 6255}
e8e26350 6256
07923c17
ET		 6257static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6258{
6259 int i;
6260
6261 for (i = 0; i < adapter->num_tx_queues; i++) {
6262 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6263
6264 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6265 return true;
6266 }
6267
6268 return false;
6269}
6270
6271static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6272{
6273 struct ixgbe_hw *hw = &adapter->hw;
6274 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6275 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6276
6277 int i, j;
6278
6279 if (!adapter->num_vfs)
6280 return false;
6281
9a75a1ac
DS		 6282 /* resetting the PF is only needed for MAC before X550 */
6283 if (hw->mac.type >= ixgbe_mac_X550)
6284 return false;
6285
07923c17
ET		 6286 for (i = 0; i < adapter->num_vfs; i++) {
6287 for (j = 0; j < q_per_pool; j++) {
6288 u32 h, t;
6289
6290 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6291 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6292
6293 if (h != t)
6294 return true;
6295 }
6296 }
6297
6298 return false;
6299}
6300
93c52dd0
AD		 6301/**
6302 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6303 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6304 **/
6305static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6306{
93c52dd0 6307 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6308 if (ixgbe_ring_tx_pending(adapter) ||
6309 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6310 /* We've lost link, so the controller stops DMA,
6311 * but we've got queued Tx work that's never going
6312 * to get done, so reset controller to flush Tx.
6313 * (Do the reset outside of interrupt context).
6314 */
12ff3f3b 6315 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6316 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6317 }
c4cf55e5 6318 }
c4cf55e5
PWJ		 6319}
6320
a985b6c3
GR		 6321static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6322{
6323 u32 ssvpc;
6324
0584d999
GR		 6325 /* Do not perform spoof check for 82598 or if not in IOV mode */
6326 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6327 adapter->num_vfs == 0)
a985b6c3
GR		 6328 return;
6329
6330 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6331
6332 /*
6333 * ssvpc register is cleared on read, if zero then no
6334 * spoofed packets in the last interval.
6335 */
6336 if (!ssvpc)
6337 return;
6338
d6ea0754 6339 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6340}
6341
93c52dd0
AD		 6342/**
6343 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6344 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6345 **/
6346static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6347{
09f40aed 6348 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6349 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6350 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6351 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6352 return;
6353
6354 ixgbe_watchdog_update_link(adapter);
6355
6356 if (adapter->link_up)
6357 ixgbe_watchdog_link_is_up(adapter);
6358 else
6359 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6360
a985b6c3 6361 ixgbe_spoof_check(adapter);
9a799d71 6362 ixgbe_update_stats(adapter);
93c52dd0
AD		 6363
6364 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6365}
10eec955 6366
cf8280ee 6367/**
7086400d 6368 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6369 * @adapter: the ixgbe adapter structure
cf8280ee 6370 **/
7086400d 6371static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6372{
cf8280ee 6373 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6374 s32 err;
cf8280ee 6375
7086400d
AD		 6376 /* not searching for SFP so there is nothing to do here */
6377 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6378 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6379 return;
10eec955 6380
7086400d
AD		 6381 /* someone else is in init, wait until next service event */
6382 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6383 return;
cf8280ee 6384
7086400d
AD		 6385 err = hw->phy.ops.identify_sfp(hw);
6386 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6387 goto sfp_out;
264857b8 6388
7086400d
AD		 6389 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6390 /* If no cable is present, then we need to reset
6391 * the next time we find a good cable. */
6392 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6393 }
9a799d71 6394
7086400d
AD		 6395 /* exit on error */
6396 if (err)
6397 goto sfp_out;
e8e26350 6398
7086400d
AD		 6399 /* exit if reset not needed */
6400 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6401 goto sfp_out;
9a799d71 6402
7086400d 6403 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6404
7086400d
AD		 6405 /*
6406 * A module may be identified correctly, but the EEPROM may not have
6407 * support for that module. setup_sfp() will fail in that case, so
6408 * we should not allow that module to load.
6409 */
6410 if (hw->mac.type == ixgbe_mac_82598EB)
6411 err = hw->phy.ops.reset(hw);
6412 else
6413 err = hw->mac.ops.setup_sfp(hw);
6414
6415 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6416 goto sfp_out;
6417
6418 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6419 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6420
6421sfp_out:
6422 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6423
6424 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6425 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6426 e_dev_err("failed to initialize because an unsupported "
6427 "SFP+ module type was detected.\n");
6428 e_dev_err("Reload the driver after installing a "
6429 "supported module.\n");
6430 unregister_netdev(adapter->netdev);
bc59fcda 6431 }
7086400d 6432}
bc59fcda 6433
7086400d
AD		 6434/**
6435 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6436 * @adapter: the ixgbe adapter structure
7086400d
AD		 6437 **/
6438static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6439{
6440 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6441 u32 speed;
6442 bool autoneg = false;
7086400d
AD		 6443
6444 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6445 return;
6446
6447 /* someone else is in init, wait until next service event */
6448 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6449 return;
6450
6451 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6452
3d292265 6453 speed = hw->phy.autoneg_advertised;
ed33ff66 6454 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6455 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6456
6457 /* setup the highest link when no autoneg */
6458 if (!autoneg) {
6459 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6460 speed = IXGBE_LINK_SPEED_10GB_FULL;
6461 }
6462 }
6463
7086400d 6464 if (hw->mac.ops.setup_link)
fd0326f2 6465 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6466
6467 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6468 adapter->link_check_timeout = jiffies;
6469 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6470}
6471
83c61fa9
GR		 6472#ifdef CONFIG_PCI_IOV
6473static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6474{
6475 int vf;
6476 struct ixgbe_hw *hw = &adapter->hw;
6477 struct net_device *netdev = adapter->netdev;
6478 u32 gpc;
6479 u32 ciaa, ciad;
6480
6481 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6482 if (gpc) /* If incrementing then no need for the check below */
6483 return;
6484 /*
6485 * Check to see if a bad DMA write target from an errant or
6486 * malicious VF has caused a PCIe error. If so then we can
6487 * issue a VFLR to the offending VF(s) and then resume without
6488 * requesting a full slot reset.
6489 */
6490
6491 for (vf = 0; vf < adapter->num_vfs; vf++) {
6492 ciaa = (vf << 16) | 0x80000000;
6493 /* 32 bit read so align, we really want status at offset 6 */
6494 ciaa |= PCI_COMMAND;
9a75a1ac
DS		 6495 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
6496 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_BY_MAC(hw));
83c61fa9
GR		 6497 ciaa &= 0x7FFFFFFF;
6498 /* disable debug mode asap after reading data */
9a75a1ac 6499 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
83c61fa9
GR		 6500 /* Get the upper 16 bits which will be the PCI status reg */
6501 ciad >>= 16;
6502 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6503 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6504 /* Issue VFLR */
6505 ciaa = (vf << 16) | 0x80000000;
6506 ciaa |= 0xA8;
9a75a1ac 6507 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
83c61fa9 6508 ciad = 0x00008000; /* VFLR */
9a75a1ac 6509 IXGBE_WRITE_REG(hw, IXGBE_CIAD_BY_MAC(hw), ciad);
83c61fa9 6510 ciaa &= 0x7FFFFFFF;
9a75a1ac 6511 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
83c61fa9
GR		 6512 }
6513 }
6514}
6515
6516#endif
7086400d
AD		 6517/**
6518 * ixgbe_service_timer - Timer Call-back
6519 * @data: pointer to adapter cast into an unsigned long
6520 **/
6521static void ixgbe_service_timer(unsigned long data)
6522{
6523 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6524 unsigned long next_event_offset;
83c61fa9 6525 bool ready = true;
7086400d 6526
6bb78cfb
AD		 6527 /* poll faster when waiting for link */
6528 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6529 next_event_offset = HZ / 10;
6530 else
6531 next_event_offset = HZ * 2;
83c61fa9 6532
6bb78cfb 6533#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6534 /*
6535 * don't bother with SR-IOV VF DMA hang check if there are
6536 * no VFs or the link is down
6537 */
6538 if (!adapter->num_vfs ||
6bb78cfb 6539 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6540 goto normal_timer_service;
83c61fa9
GR		 6541
6542 /* If we have VFs allocated then we must check for DMA hangs */
6543 ixgbe_check_for_bad_vf(adapter);
6544 next_event_offset = HZ / 50;
6545 adapter->timer_event_accumulator++;
6546
6bb78cfb 6547 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6548 adapter->timer_event_accumulator = 0;
7086400d 6549 else
6bb78cfb 6550 ready = false;
7086400d 6551
6bb78cfb 6552normal_timer_service:
83c61fa9 6553#endif
7086400d
AD		 6554 /* Reset the timer */
6555 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6556
83c61fa9
GR		 6557 if (ready)
6558 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6559}
6560
c83c6cbd
AD		 6561static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6562{
6563 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6564 return;
6565
6566 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6567
09f40aed 6568 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6569 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6570 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6571 test_bit(__IXGBE_RESETTING, &adapter->state))
6572 return;
6573
6574 ixgbe_dump(adapter);
6575 netdev_err(adapter->netdev, "Reset adapter\n");
6576 adapter->tx_timeout_count++;
6577
8f4c5c9f 6578 rtnl_lock();
c83c6cbd 6579 ixgbe_reinit_locked(adapter);
8f4c5c9f 6580 rtnl_unlock();
c83c6cbd
AD		 6581}
6582
7086400d
AD		 6583/**
6584 * ixgbe_service_task - manages and runs subtasks
6585 * @work: pointer to work_struct containing our data
6586 **/
6587static void ixgbe_service_task(struct work_struct *work)
6588{
6589 struct ixgbe_adapter *adapter = container_of(work,
6590 struct ixgbe_adapter,
6591 service_task);
b0483c8f
MR		 6592 if (ixgbe_removed(adapter->hw.hw_addr)) {
6593 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6594 rtnl_lock();
6595 ixgbe_down(adapter);
6596 rtnl_unlock();
6597 }
6598 ixgbe_service_event_complete(adapter);
6599 return;
6600 }
c83c6cbd 6601 ixgbe_reset_subtask(adapter);
7086400d
AD		 6602 ixgbe_sfp_detection_subtask(adapter);
6603 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6604 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6605 ixgbe_watchdog_subtask(adapter);
d034acf1 6606 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6607 ixgbe_check_hang_subtask(adapter);
891dc082 6608
8fecf67c 6609 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6610 ixgbe_ptp_overflow_check(adapter);
6611 ixgbe_ptp_rx_hang(adapter);
6612 }
7086400d
AD		 6613
6614 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6615}
6616
fd0db0ed
AD		 6617static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6618 struct ixgbe_tx_buffer *first,
244e27ad 6619 u8 *hdr_len)
897ab156 6620{
fd0db0ed 6621 struct sk_buff *skb = first->skb;
897ab156
AD		 6622 u32 vlan_macip_lens, type_tucmd;
6623 u32 mss_l4len_idx, l4len;
2049e1f6 6624 int err;
9a799d71 6625
8f4fbb9b
AD		 6626 if (skb->ip_summed != CHECKSUM_PARTIAL)
6627 return 0;
6628
897ab156
AD		 6629 if (!skb_is_gso(skb))
6630 return 0;
9a799d71 6631
2049e1f6
FR		 6632 err = skb_cow_head(skb, 0);
6633 if (err < 0)
6634 return err;
9a799d71 6635
897ab156
AD		 6636 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6637 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6638
a1108ffd 6639 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6640 struct iphdr *iph = ip_hdr(skb);
6641 iph->tot_len = 0;
6642 iph->check = 0;
6643 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6644 iph->daddr, 0,
6645 IPPROTO_TCP,
6646 0);
6647 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6648 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6649 IXGBE_TX_FLAGS_CSUM |
6650 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6651 } else if (skb_is_gso_v6(skb)) {
6652 ipv6_hdr(skb)->payload_len = 0;
6653 tcp_hdr(skb)->check =
6654 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6655 &ipv6_hdr(skb)->daddr,
6656 0, IPPROTO_TCP, 0);
244e27ad
AD		 6657 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6658 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6659 }
6660
091a6246 6661 /* compute header lengths */
897ab156
AD		 6662 l4len = tcp_hdrlen(skb);
6663 *hdr_len = skb_transport_offset(skb) + l4len;
6664
091a6246
AD		 6665 /* update gso size and bytecount with header size */
6666 first->gso_segs = skb_shinfo(skb)->gso_segs;
6667 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6668
c44f5f51 6669 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6670 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6671 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6672
6673 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6674 vlan_macip_lens = skb_network_header_len(skb);
6675 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6676 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6677
6678 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6679 mss_l4len_idx);
897ab156
AD		 6680
6681 return 1;
6682}
6683
244e27ad
AD		 6684static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6685 struct ixgbe_tx_buffer *first)
7ca647bd 6686{
fd0db0ed 6687 struct sk_buff *skb = first->skb;
897ab156
AD		 6688 u32 vlan_macip_lens = 0;
6689 u32 mss_l4len_idx = 0;
6690 u32 type_tucmd = 0;
7ca647bd 6691
897ab156 6692 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6693 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6694 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6695 return;
897ab156
AD		 6696 } else {
6697 u8 l4_hdr = 0;
244e27ad 6698 switch (first->protocol) {
a1108ffd 6699 case htons(ETH_P_IP):
897ab156
AD		 6700 vlan_macip_lens |= skb_network_header_len(skb);
6701 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6702 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6703 break;
a1108ffd 6704 case htons(ETH_P_IPV6):
897ab156
AD		 6705 vlan_macip_lens |= skb_network_header_len(skb);
6706 l4_hdr = ipv6_hdr(skb)->nexthdr;
6707 break;
6708 default:
6709 if (unlikely(net_ratelimit())) {
6710 dev_warn(tx_ring->dev,
6711 "partial checksum but proto=%x!\n",
244e27ad 6712 first->protocol);
897ab156 6713 }
7ca647bd
JP		 6714 break;
6715 }
897ab156
AD		 6716
6717 switch (l4_hdr) {
7ca647bd 6718 case IPPROTO_TCP:
897ab156
AD		 6719 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6720 mss_l4len_idx = tcp_hdrlen(skb) <<
6721 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6722 break;
6723 case IPPROTO_SCTP:
897ab156
AD		 6724 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6725 mss_l4len_idx = sizeof(struct sctphdr) <<
6726 IXGBE_ADVTXD_L4LEN_SHIFT;
6727 break;
6728 case IPPROTO_UDP:
6729 mss_l4len_idx = sizeof(struct udphdr) <<
6730 IXGBE_ADVTXD_L4LEN_SHIFT;
6731 break;
6732 default:
6733 if (unlikely(net_ratelimit())) {
6734 dev_warn(tx_ring->dev,
6735 "partial checksum but l4 proto=%x!\n",
244e27ad 6736 l4_hdr);
897ab156 6737 }
7ca647bd
JP		 6738 break;
6739 }
244e27ad
AD		 6740
6741 /* update TX checksum flag */
6742 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6743 }
6744
244e27ad 6745 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6746 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6747 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6748
897ab156
AD		 6749 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6750 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6751}
6752
472148c3
AD		 6753#define IXGBE_SET_FLAG(_input, _flag, _result) \
6754 ((_flag <= _result) ? \
6755 ((u32)(_input & _flag) * (_result / _flag)) : \
6756 ((u32)(_input & _flag) / (_flag / _result)))
6757
6758static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6759{
d3d00239 6760 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6761 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6762 IXGBE_ADVTXD_DCMD_DEXT |
6763 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6764
d3d00239 6765 /* set HW vlan bit if vlan is present */
472148c3
AD		 6766 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6767 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6768
d3d00239 6769 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6770 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6771 IXGBE_ADVTXD_DCMD_TSE);
6772
6773 /* set timestamp bit if present */
6774 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6775 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6776
62748b7b 6777 /* insert frame checksum */
472148c3 6778 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6779
d3d00239
AD		 6780 return cmd_type;
6781}
9a799d71 6782
729739b7
AD		 6783static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6784 u32 tx_flags, unsigned int paylen)
d3d00239 6785{
472148c3 6786 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6787
d3d00239 6788 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6789 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6790 IXGBE_TX_FLAGS_CSUM,
6791 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6792
93f5b3c1 6793 /* enble IPv4 checksum for TSO */
472148c3
AD		 6794 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6795 IXGBE_TX_FLAGS_IPV4,
6796 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6797
7f9643fd
AD		 6798 /*
6799 * Check Context must be set if Tx switch is enabled, which it
6800 * always is for case where virtual functions are running
6801 */
472148c3
AD		 6802 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6803 IXGBE_TX_FLAGS_CC,
6804 IXGBE_ADVTXD_CC);
7f9643fd 6805
472148c3 6806 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6807}
44df32c5 6808
2367a173
DB		 6809static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6810{
6811 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6812
6813 /* Herbert's original patch had:
6814 * smp_mb__after_netif_stop_queue();
6815 * but since that doesn't exist yet, just open code it.
6816 */
6817 smp_mb();
6818
6819 /* We need to check again in a case another CPU has just
6820 * made room available.
6821 */
6822 if (likely(ixgbe_desc_unused(tx_ring) < size))
6823 return -EBUSY;
6824
6825 /* A reprieve! - use start_queue because it doesn't call schedule */
6826 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6827 ++tx_ring->tx_stats.restart_queue;
6828 return 0;
6829}
6830
6831static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6832{
6833 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6834 return 0;
6835
6836 return __ixgbe_maybe_stop_tx(tx_ring, size);
6837}
6838
d3d00239
AD		 6839#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6840 IXGBE_TXD_CMD_RS)
6841
6842static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6843 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6844 const u8 hdr_len)
6845{
fd0db0ed 6846 struct sk_buff *skb = first->skb;
729739b7 6847 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6848 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6849 struct skb_frag_struct *frag;
6850 dma_addr_t dma;
6851 unsigned int data_len, size;
244e27ad 6852 u32 tx_flags = first->tx_flags;
472148c3 6853 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6854 u16 i = tx_ring->next_to_use;
d3d00239 6855
729739b7
AD		 6856 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6857
ec718254
AD		 6858 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6859
6860 size = skb_headlen(skb);
6861 data_len = skb->data_len;
729739b7 6862
d3d00239
AD		 6863#ifdef IXGBE_FCOE
6864 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6865 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6866 size -= sizeof(struct fcoe_crc_eof) - data_len;
6867 data_len = 0;
729739b7
AD		 6868 } else {
6869 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6870 }
6871 }
44df32c5 6872
d3d00239 6873#endif
729739b7 6874 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6875
ec718254 6876 tx_buffer = first;
9a799d71 6877
ec718254
AD		 6878 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6879 if (dma_mapping_error(tx_ring->dev, dma))
6880 goto dma_error;
6881
6882 /* record length, and DMA address */
6883 dma_unmap_len_set(tx_buffer, len, size);
6884 dma_unmap_addr_set(tx_buffer, dma, dma);
6885
6886 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6887
729739b7 6888 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6889 tx_desc->read.cmd_type_len =
472148c3 6890 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6891
d3d00239 6892 i++;
729739b7 6893 tx_desc++;
d3d00239 6894 if (i == tx_ring->count) {
e4f74028 6895 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6896 i = 0;
6897 }
ec718254 6898 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6899
6900 dma += IXGBE_MAX_DATA_PER_TXD;
6901 size -= IXGBE_MAX_DATA_PER_TXD;
6902
6903 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6904 }
e5a43549 6905
729739b7
AD		 6906 if (likely(!data_len))
6907 break;
9a799d71 6908
472148c3 6909 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6910
729739b7
AD		 6911 i++;
6912 tx_desc++;
6913 if (i == tx_ring->count) {
6914 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6915 i = 0;
6916 }
ec718254 6917 tx_desc->read.olinfo_status = 0;
9a799d71 6918
d3d00239 6919#ifdef IXGBE_FCOE
9e903e08 6920 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6921#else
9e903e08 6922 size = skb_frag_size(frag);
d3d00239
AD		 6923#endif
6924 data_len -= size;
9a799d71 6925
729739b7
AD		 6926 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6927 DMA_TO_DEVICE);
9a799d71 6928
729739b7 6929 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6930 }
9a799d71 6931
729739b7 6932 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6933 cmd_type |= size | IXGBE_TXD_CMD;
6934 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6935
091a6246 6936 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6937
d3d00239
AD		 6938 /* set the timestamp */
6939 first->time_stamp = jiffies;
9a799d71
AK		 6940
6941 /*
729739b7
AD		 6942 * Force memory writes to complete before letting h/w know there
6943 * are new descriptors to fetch. (Only applicable for weak-ordered
6944 * memory model archs, such as IA-64).
6945 *
6946 * We also need this memory barrier to make certain all of the
6947 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6948 */
6949 wmb();
6950
d3d00239
AD		 6951 /* set next_to_watch value indicating a packet is present */
6952 first->next_to_watch = tx_desc;
6953
729739b7
AD		 6954 i++;
6955 if (i == tx_ring->count)
6956 i = 0;
6957
6958 tx_ring->next_to_use = i;
6959
2367a173
DB		 6960 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6961
6962 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 6963 writel(i, tx_ring->tail);
6964
6965 /* we need this if more than one processor can write to our tail
6966 * at a time, it synchronizes IO on IA64/Altix systems
6967 */
6968 mmiowb();
9c938cdd 6969 }
2367a173 6970
d3d00239
AD		 6971 return;
6972dma_error:
729739b7 6973 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6974
6975 /* clear dma mappings for failed tx_buffer_info map */
6976 for (;;) {
729739b7
AD		 6977 tx_buffer = &tx_ring->tx_buffer_info[i];
6978 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6979 if (tx_buffer == first)
d3d00239
AD		 6980 break;
6981 if (i == 0)
6982 i = tx_ring->count;
6983 i--;
6984 }
6985
d3d00239 6986 tx_ring->next_to_use = i;
9a799d71
AK		 6987}
6988
fd0db0ed 6989static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6990 struct ixgbe_tx_buffer *first)
69830529
AD		 6991{
6992 struct ixgbe_q_vector *q_vector = ring->q_vector;
6993 union ixgbe_atr_hash_dword input = { .dword = 0 };
6994 union ixgbe_atr_hash_dword common = { .dword = 0 };
6995 union {
6996 unsigned char *network;
6997 struct iphdr *ipv4;
6998 struct ipv6hdr *ipv6;
6999 } hdr;
ee9e0f0b 7000 struct tcphdr *th;
905e4a41 7001 __be16 vlan_id;
c4cf55e5 7002
69830529
AD		 7003 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7004 if (!q_vector)
7005 return;
7006
7007 /* do nothing if sampling is disabled */
7008 if (!ring->atr_sample_rate)
d3ead241 7009 return;
c4cf55e5 7010
69830529 7011 ring->atr_count++;
c4cf55e5 7012
69830529 7013 /* snag network header to get L4 type and address */
fd0db0ed 7014 hdr.network = skb_network_header(first->skb);
69830529
AD		 7015
7016 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 7017 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 7018 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 7019 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 7020 hdr.ipv4->protocol != IPPROTO_TCP))
7021 return;
ee9e0f0b 7022
fd0db0ed 7023 th = tcp_hdr(first->skb);
c4cf55e5 7024
66f32a8b
AD		 7025 /* skip this packet since it is invalid or the socket is closing */
7026 if (!th || th->fin)
69830529
AD		 7027 return;
7028
7029 /* sample on all syn packets or once every atr sample count */
7030 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7031 return;
7032
7033 /* reset sample count */
7034 ring->atr_count = 0;
7035
244e27ad 7036 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7037
7038 /*
7039 * src and dst are inverted, think how the receiver sees them
7040 *
7041 * The input is broken into two sections, a non-compressed section
7042 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7043 * is XORed together and stored in the compressed dword.
7044 */
7045 input.formatted.vlan_id = vlan_id;
7046
7047 /*
7048 * since src port and flex bytes occupy the same word XOR them together
7049 * and write the value to source port portion of compressed dword
7050 */
244e27ad 7051 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7052 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7053 else
244e27ad 7054 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7055 common.port.dst ^= th->source;
7056
a1108ffd 7057 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7058 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7059 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7060 } else {
7061 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7062 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7063 hdr.ipv6->saddr.s6_addr32[1] ^
7064 hdr.ipv6->saddr.s6_addr32[2] ^
7065 hdr.ipv6->saddr.s6_addr32[3] ^
7066 hdr.ipv6->daddr.s6_addr32[0] ^
7067 hdr.ipv6->daddr.s6_addr32[1] ^
7068 hdr.ipv6->daddr.s6_addr32[2] ^
7069 hdr.ipv6->daddr.s6_addr32[3];
7070 }
c4cf55e5
PWJ		 7071
7072 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7073 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7074 input, common, ring->queue_index);
c4cf55e5
PWJ		 7075}
7076
f663dd9a 7077static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7078 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7079{
f663dd9a
JW		 7080 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7081#ifdef IXGBE_FCOE
97488bd1
AD		 7082 struct ixgbe_adapter *adapter;
7083 struct ixgbe_ring_feature *f;
7084 int txq;
f663dd9a
JW		 7085#endif
7086
7087 if (fwd_adapter)
7088 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7089
7090#ifdef IXGBE_FCOE
5e09a105 7091
97488bd1
AD		 7092 /*
7093 * only execute the code below if protocol is FCoE
7094 * or FIP and we have FCoE enabled on the adapter
7095 */
7096 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7097 case htons(ETH_P_FCOE):
7098 case htons(ETH_P_FIP):
97488bd1 7099 adapter = netdev_priv(dev);
c087663e 7100
97488bd1
AD		 7101 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7102 break;
7103 default:
99932d4f 7104 return fallback(dev, skb);
97488bd1 7105 }
c087663e 7106
97488bd1 7107 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7108
97488bd1
AD		 7109 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7110 smp_processor_id();
56075a98 7111
97488bd1
AD		 7112 while (txq >= f->indices)
7113 txq -= f->indices;
c4cf55e5 7114
97488bd1 7115 return txq + f->offset;
f663dd9a 7116#else
99932d4f 7117 return fallback(dev, skb);
f663dd9a 7118#endif
09a3b1f8
SH		 7119}
7120
fc77dc3c 7121netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7122 struct ixgbe_adapter *adapter,
7123 struct ixgbe_ring *tx_ring)
9a799d71 7124{
d3d00239 7125 struct ixgbe_tx_buffer *first;
5f715823 7126 int tso;
d3d00239 7127 u32 tx_flags = 0;
a535c30e 7128 unsigned short f;
a535c30e 7129 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7130 __be16 protocol = skb->protocol;
63544e9c 7131 u8 hdr_len = 0;
5e09a105 7132
a535c30e
AD		 7133 /*
7134 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7135 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7136 * + 2 desc gap to keep tail from touching head,
7137 * + 1 desc for context descriptor,
7138 * otherwise try next time
7139 */
a535c30e
AD		 7140 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7141 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7142
a535c30e
AD		 7143 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7144 tx_ring->tx_stats.tx_busy++;
7145 return NETDEV_TX_BUSY;
7146 }
7147
fd0db0ed
AD		 7148 /* record the location of the first descriptor for this packet */
7149 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7150 first->skb = skb;
091a6246
AD		 7151 first->bytecount = skb->len;
7152 first->gso_segs = 1;
fd0db0ed 7153
66f32a8b 7154 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7155 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7156 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7157 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7158 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7159 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7160 struct vlan_hdr *vhdr, _vhdr;
7161 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7162 if (!vhdr)
7163 goto out_drop;
7164
7165 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7166 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7167 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7168 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7169 }
7170
d5234933
MR		 7171 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7172 adapter->ptp_clock &&
7173 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7174 &adapter->state)) {
3a6a4eda
JK		 7175 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7176 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7177
7178 /* schedule check for Tx timestamp */
7179 adapter->ptp_tx_skb = skb_get(skb);
7180 adapter->ptp_tx_start = jiffies;
7181 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7182 }
3a6a4eda 7183
ff29a86e
JK		 7184 skb_tx_timestamp(skb);
7185
9e0c5648
AD		 7186#ifdef CONFIG_PCI_IOV
7187 /*
7188 * Use the l2switch_enable flag - would be false if the DMA
7189 * Tx switch had been disabled.
7190 */
7191 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7192 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7193
7194#endif
32701dc2 7195 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7196 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7197 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7198 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7199 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7200 tx_flags |= (skb->priority & 0x7) <<
7201 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7202 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7203 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7204
7205 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7206 goto out_drop;
7207 vhdr = (struct vlan_ethhdr *)skb->data;
7208 vhdr->h_vlan_TCI = htons(tx_flags >>
7209 IXGBE_TX_FLAGS_VLAN_SHIFT);
7210 } else {
7211 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7212 }
9a799d71 7213 }
eacd73f7 7214
244e27ad
AD		 7215 /* record initial flags and protocol */
7216 first->tx_flags = tx_flags;
7217 first->protocol = protocol;
7218
eacd73f7 7219#ifdef IXGBE_FCOE
66f32a8b 7220 /* setup tx offload for FCoE */
a1108ffd 7221 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7222 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7223 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7224 if (tso < 0)
7225 goto out_drop;
9a799d71 7226
66f32a8b 7227 goto xmit_fcoe;
eacd73f7 7228 }
9a799d71 7229
66f32a8b 7230#endif /* IXGBE_FCOE */
244e27ad 7231 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7232 if (tso < 0)
897ab156 7233 goto out_drop;
244e27ad
AD		 7234 else if (!tso)
7235 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7236
7237 /* add the ATR filter if ATR is on */
7238 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7239 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7240
7241#ifdef IXGBE_FCOE
7242xmit_fcoe:
7243#endif /* IXGBE_FCOE */
244e27ad 7244 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7245
9a799d71 7246 return NETDEV_TX_OK;
897ab156
AD		 7247
7248out_drop:
fd0db0ed
AD		 7249 dev_kfree_skb_any(first->skb);
7250 first->skb = NULL;
7251
897ab156 7252 return NETDEV_TX_OK;
9a799d71
AK		 7253}
7254
2a47fa45
JF		 7255static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7256 struct net_device *netdev,
7257 struct ixgbe_ring *ring)
84418e3b
AD		 7258{
7259 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7260 struct ixgbe_ring *tx_ring;
7261
a50c29dd
AD		 7262 /*
7263 * The minimum packet size for olinfo paylen is 17 so pad the skb
7264 * in order to meet this minimum size requirement.
7265 */
f73332fc
SH		 7266 if (unlikely(skb->len < 17)) {
7267 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7268 return NETDEV_TX_OK;
7269 skb->len = 17;
71a49f77 7270 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7271 }
7272
2a47fa45
JF		 7273 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7274
fc77dc3c 7275 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7276}
7277
2a47fa45
JF		 7278static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7279 struct net_device *netdev)
7280{
7281 return __ixgbe_xmit_frame(skb, netdev, NULL);
7282}
7283
9a799d71
AK		 7284/**
7285 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7286 * @netdev: network interface device structure
7287 * @p: pointer to an address structure
7288 *
7289 * Returns 0 on success, negative on failure
7290 **/
7291static int ixgbe_set_mac(struct net_device *netdev, void *p)
7292{
7293 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7294 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7295 struct sockaddr *addr = p;
5d7daa35 7296 int ret;
9a799d71
AK		 7297
7298 if (!is_valid_ether_addr(addr->sa_data))
7299 return -EADDRNOTAVAIL;
7300
5d7daa35 7301 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7302 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7303 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7304
5d7daa35
JK		 7305 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7306 return ret > 0 ? 0 : ret;
9a799d71
AK		 7307}
7308
6b73e10d
BH		 7309static int
7310ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7311{
7312 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7313 struct ixgbe_hw *hw = &adapter->hw;
7314 u16 value;
7315 int rc;
7316
7317 if (prtad != hw->phy.mdio.prtad)
7318 return -EINVAL;
7319 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7320 if (!rc)
7321 rc = value;
7322 return rc;
7323}
7324
7325static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7326 u16 addr, u16 value)
7327{
7328 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7329 struct ixgbe_hw *hw = &adapter->hw;
7330
7331 if (prtad != hw->phy.mdio.prtad)
7332 return -EINVAL;
7333 return hw->phy.ops.write_reg(hw, addr, devad, value);
7334}
7335
7336static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7337{
7338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7339
3a6a4eda 7340 switch (cmd) {
3a6a4eda 7341 case SIOCSHWTSTAMP:
93501d48
JK		 7342 return ixgbe_ptp_set_ts_config(adapter, req);
7343 case SIOCGHWTSTAMP:
7344 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7345 default:
7346 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7347 }
6b73e10d
BH		 7348}
7349
0365e6e4
PW		 7350/**
7351 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7352 * netdev->dev_addrs
0365e6e4
PW		 7353 * @netdev: network interface device structure
7354 *
7355 * Returns non-zero on failure
7356 **/
7357static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7358{
7359 int err = 0;
7360 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7361 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7362
7fa7c9dc 7363 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7364 rtnl_lock();
7fa7c9dc 7365 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7366 rtnl_unlock();
7fa7c9dc
AD		 7367
7368 /* update SAN MAC vmdq pool selection */
7369 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7370 }
7371 return err;
7372}
7373
7374/**
7375 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7376 * netdev->dev_addrs
0365e6e4
PW		 7377 * @netdev: network interface device structure
7378 *
7379 * Returns non-zero on failure
7380 **/
7381static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7382{
7383 int err = 0;
7384 struct ixgbe_adapter *adapter = netdev_priv(dev);
7385 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7386
7387 if (is_valid_ether_addr(mac->san_addr)) {
7388 rtnl_lock();
7389 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7390 rtnl_unlock();
7391 }
7392 return err;
7393}
7394
9a799d71
AK		 7395#ifdef CONFIG_NET_POLL_CONTROLLER
7396/*
7397 * Polling 'interrupt' - used by things like netconsole to send skbs
7398 * without having to re-enable interrupts. It's not called while
7399 * the interrupt routine is executing.
7400 */
7401static void ixgbe_netpoll(struct net_device *netdev)
7402{
7403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7404 int i;
9a799d71 7405
1a647bd2
AD		 7406 /* if interface is down do nothing */
7407 if (test_bit(__IXGBE_DOWN, &adapter->state))
7408 return;
7409
9a799d71 7410 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7411 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7412 for (i = 0; i < adapter->num_q_vectors; i++)
7413 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7414 } else {
7415 ixgbe_intr(adapter->pdev->irq, netdev);
7416 }
9a799d71 7417 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7418}
9a799d71 7419
581330ba 7420#endif
de1036b1
ED		 7421static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7422 struct rtnl_link_stats64 *stats)
7423{
7424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7425 int i;
7426
1a51502b 7427 rcu_read_lock();
de1036b1 7428 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7429 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7430 u64 bytes, packets;
7431 unsigned int start;
7432
1a51502b
ED		 7433 if (ring) {
7434 do {
57a7744e 7435 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7436 packets = ring->stats.packets;
7437 bytes = ring->stats.bytes;
57a7744e 7438 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7439 stats->rx_packets += packets;
7440 stats->rx_bytes += bytes;
7441 }
de1036b1 7442 }
1ac9ad13
ED		 7443
7444 for (i = 0; i < adapter->num_tx_queues; i++) {
7445 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7446 u64 bytes, packets;
7447 unsigned int start;
7448
7449 if (ring) {
7450 do {
57a7744e 7451 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7452 packets = ring->stats.packets;
7453 bytes = ring->stats.bytes;
57a7744e 7454 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7455 stats->tx_packets += packets;
7456 stats->tx_bytes += bytes;
7457 }
7458 }
1a51502b 7459 rcu_read_unlock();
de1036b1
ED		 7460 /* following stats updated by ixgbe_watchdog_task() */
7461 stats->multicast = netdev->stats.multicast;
7462 stats->rx_errors = netdev->stats.rx_errors;
7463 stats->rx_length_errors = netdev->stats.rx_length_errors;
7464 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7465 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7466 return stats;
7467}
7468
8af3c33f 7469#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7470/**
7471 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7472 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7473 * @tc: number of traffic classes currently enabled
7474 *
7475 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7476 * 802.1Q priority maps to a packet buffer that exists.
7477 */
7478static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7479{
7480 struct ixgbe_hw *hw = &adapter->hw;
7481 u32 reg, rsave;
7482 int i;
7483
7484 /* 82598 have a static priority to TC mapping that can not
7485 * be changed so no validation is needed.
7486 */
7487 if (hw->mac.type == ixgbe_mac_82598EB)
7488 return;
7489
7490 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7491 rsave = reg;
7492
7493 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7494 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7495
7496 /* If up2tc is out of bounds default to zero */
7497 if (up2tc > tc)
7498 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7499 }
7500
7501 if (reg != rsave)
7502 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7503
7504 return;
7505}
7506
02debdc9
AD		 7507/**
7508 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7509 * @adapter: Pointer to adapter struct
7510 *
7511 * Populate the netdev user priority to tc map
7512 */
7513static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7514{
7515 struct net_device *dev = adapter->netdev;
7516 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7517 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7518 u8 prio;
7519
7520 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7521 u8 tc = 0;
7522
7523 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7524 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7525 else if (ets)
7526 tc = ets->prio_tc[prio];
7527
7528 netdev_set_prio_tc_map(dev, prio, tc);
7529 }
7530}
7531
cca73c59 7532#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7533/**
7534 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7535 *
7536 * @netdev: net device to configure
7537 * @tc: number of traffic classes to enable
7538 */
7539int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7540{
8b1c0b24
JF		 7541 struct ixgbe_adapter *adapter = netdev_priv(dev);
7542 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7543 bool pools;
8b1c0b24 7544
8b1c0b24 7545 /* Hardware supports up to 8 traffic classes */
4de2a022 7546 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7547 (hw->mac.type == ixgbe_mac_82598EB &&
7548 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7549 return -EINVAL;
7550
2a47fa45
JF		 7551 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7552 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7553 return -EBUSY;
7554
8b1c0b24 7555 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7556 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7557 * hardware is not flexible enough to do this dynamically.
7558 */
7559 if (netif_running(dev))
7560 ixgbe_close(dev);
7561 ixgbe_clear_interrupt_scheme(adapter);
7562
cca73c59 7563#ifdef CONFIG_IXGBE_DCB
e7589eab 7564 if (tc) {
8b1c0b24 7565 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7566 ixgbe_set_prio_tc_map(adapter);
7567
e7589eab 7568 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7569
943561d3
AD		 7570 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7571 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7572 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7573 }
e7589eab 7574 } else {
8b1c0b24 7575 netdev_reset_tc(dev);
02debdc9 7576
943561d3
AD		 7577 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7578 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7579
7580 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7581
7582 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7583 adapter->dcb_cfg.pfc_mode_enable = false;
7584 }
7585
8b1c0b24 7586 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7587
7588#endif /* CONFIG_IXGBE_DCB */
7589 ixgbe_init_interrupt_scheme(adapter);
7590
8b1c0b24 7591 if (netif_running(dev))
cca73c59 7592 return ixgbe_open(dev);
8b1c0b24
JF		 7593
7594 return 0;
7595}
de1036b1 7596
da36b647
GR		 7597#ifdef CONFIG_PCI_IOV
7598void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7599{
7600 struct net_device *netdev = adapter->netdev;
7601
7602 rtnl_lock();
da36b647 7603 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7604 rtnl_unlock();
7605}
7606
7607#endif
082757af
DS		 7608void ixgbe_do_reset(struct net_device *netdev)
7609{
7610 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7611
7612 if (netif_running(netdev))
7613 ixgbe_reinit_locked(adapter);
7614 else
7615 ixgbe_reset(adapter);
7616}
7617
c8f44aff 7618static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7619 netdev_features_t features)
082757af
DS		 7620{
7621 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7622
082757af 7623 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7624 if (!(features & NETIF_F_RXCSUM))
7625 features &= ~NETIF_F_LRO;
082757af 7626
567d2de2
AD		 7627 /* Turn off LRO if not RSC capable */
7628 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7629 features &= ~NETIF_F_LRO;
8e2813f5 7630
567d2de2 7631 return features;
082757af
DS		 7632}
7633
c8f44aff 7634static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7635 netdev_features_t features)
082757af
DS		 7636{
7637 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7638 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7639 bool need_reset = false;
7640
082757af 7641 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7642 if (!(features & NETIF_F_LRO)) {
7643 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7644 need_reset = true;
567d2de2
AD		 7645 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7646 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7647 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7648 if (adapter->rx_itr_setting == 1 ||
7649 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7650 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7651 need_reset = true;
7652 } else if ((changed ^ features) & NETIF_F_LRO) {
7653 e_info(probe, "rx-usecs set too low, "
7654 "disabling RSC\n");
082757af
DS		 7655 }
7656 }
7657
7658 /*
7659 * Check if Flow Director n-tuple support was enabled or disabled. If
7660 * the state changed, we need to reset.
7661 */
39cb681b
AD		 7662 switch (features & NETIF_F_NTUPLE) {
7663 case NETIF_F_NTUPLE:
567d2de2 7664 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7665 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7666 need_reset = true;
7667
567d2de2
AD		 7668 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7669 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7670 break;
7671 default:
7672 /* turn off perfect filters, enable ATR and reset */
7673 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7674 need_reset = true;
7675
7676 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7677
7678 /* We cannot enable ATR if SR-IOV is enabled */
7679 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7680 break;
7681
7682 /* We cannot enable ATR if we have 2 or more traffic classes */
7683 if (netdev_get_num_tc(netdev) > 1)
7684 break;
7685
7686 /* We cannot enable ATR if RSS is disabled */
7687 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7688 break;
7689
7690 /* A sample rate of 0 indicates ATR disabled */
7691 if (!adapter->atr_sample_rate)
7692 break;
7693
7694 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7695 break;
082757af
DS		 7696 }
7697
f646968f 7698 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7699 ixgbe_vlan_strip_enable(adapter);
7700 else
7701 ixgbe_vlan_strip_disable(adapter);
7702
3f2d1c0f
BG		 7703 if (changed & NETIF_F_RXALL)
7704 need_reset = true;
7705
567d2de2 7706 netdev->features = features;
082757af
DS		 7707 if (need_reset)
7708 ixgbe_do_reset(netdev);
7709
7710 return 0;
082757af
DS		 7711}
7712
edc7d573 7713static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7714 struct net_device *dev,
f6f6424b 7715 const unsigned char *addr, u16 vid,
0f4b0add
JF		 7716 u16 flags)
7717{
bcfd3432 7718 /* guarantee we can provide a unique filter for the unicast address */
46acc460 7719 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 7720 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7721 return -ENOMEM;
0f4b0add
JF		 7722 }
7723
f6f6424b 7724 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 7725}
7726
815cccbf
JF		 7727static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7728 struct nlmsghdr *nlh)
7729{
7730 struct ixgbe_adapter *adapter = netdev_priv(dev);
7731 struct nlattr *attr, *br_spec;
7732 int rem;
7733
7734 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7735 return -EOPNOTSUPP;
7736
7737 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 7738 if (!br_spec)
7739 return -EINVAL;
815cccbf
JF		 7740
7741 nla_for_each_nested(attr, br_spec, rem) {
7742 __u16 mode;
7743 u32 reg = 0;
7744
7745 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7746 continue;
7747
b7c1a314
TG		 7748 if (nla_len(attr) < sizeof(mode))
7749 return -EINVAL;
7750
815cccbf 7751 mode = nla_get_u16(attr);
9b735984 7752 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7753 reg = 0;
9b735984
GR		 7754 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7755 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7756 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7757 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7758 } else
815cccbf
JF		 7759 return -EINVAL;
7760
7761 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7762
7763 e_info(drv, "enabling bridge mode: %s\n",
7764 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7765 }
7766
7767 return 0;
7768}
7769
7770static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7771 struct net_device *dev,
7772 u32 filter_mask)
815cccbf
JF		 7773{
7774 struct ixgbe_adapter *adapter = netdev_priv(dev);
7775 u16 mode;
7776
7777 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7778 return 0;
7779
9b735984 7780 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7781 mode = BRIDGE_MODE_VEB;
7782 else
7783 mode = BRIDGE_MODE_VEPA;
7784
2c3c031c 7785 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0);
815cccbf
JF		 7786}
7787
2a47fa45
JF		 7788static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7789{
7790 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7791 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 7792 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 7793 unsigned int limit;
2a47fa45
JF		 7794 int pool, err;
7795
aac2f1bf
JK		 7796 /* Hardware has a limited number of available pools. Each VF, and the
7797 * PF require a pool. Check to ensure we don't attempt to use more
7798 * then the available number of pools.
7799 */
7800 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
7801 return ERR_PTR(-EINVAL);
7802
219354d4
JF		 7803#ifdef CONFIG_RPS
7804 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7805 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7806 vdev->name);
7807 return ERR_PTR(-EINVAL);
7808 }
7809#endif
2a47fa45 7810 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7811 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7812 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7813 netdev_info(pdev,
7814 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7815 pdev->name);
7816 return ERR_PTR(-EINVAL);
7817 }
7818
7819 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7820 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7821 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7822 return ERR_PTR(-EBUSY);
7823
7824 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7825 if (!fwd_adapter)
7826 return ERR_PTR(-ENOMEM);
7827
7828 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7829 adapter->num_rx_pools++;
7830 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7831 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7832
7833 /* Enable VMDq flag so device will be set in VM mode */
7834 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7835 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7836 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7837
7838 /* Force reinit of ring allocation with VMDQ enabled */
7839 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7840 if (err)
7841 goto fwd_add_err;
7842 fwd_adapter->pool = pool;
7843 fwd_adapter->real_adapter = adapter;
7844 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7845 if (err)
7846 goto fwd_add_err;
7847 netif_tx_start_all_queues(vdev);
7848 return fwd_adapter;
7849fwd_add_err:
7850 /* unwind counter and free adapter struct */
7851 netdev_info(pdev,
7852 "%s: dfwd hardware acceleration failed\n", vdev->name);
7853 clear_bit(pool, &adapter->fwd_bitmask);
7854 adapter->num_rx_pools--;
7855 kfree(fwd_adapter);
7856 return ERR_PTR(err);
7857}
7858
7859static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7860{
7861 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7862 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7863 unsigned int limit;
2a47fa45
JF		 7864
7865 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7866 adapter->num_rx_pools--;
7867
51f3773b
JF		 7868 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7869 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7870 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7871 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7872 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7873 fwd_adapter->pool, adapter->num_rx_pools,
7874 fwd_adapter->rx_base_queue,
7875 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7876 adapter->fwd_bitmask);
7877 kfree(fwd_adapter);
7878}
7879
0edc3527 7880static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7881 .ndo_open = ixgbe_open,
0edc3527 7882 .ndo_stop = ixgbe_close,
00829823 7883 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7884 .ndo_select_queue = ixgbe_select_queue,
581330ba 7885 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7886 .ndo_validate_addr = eth_validate_addr,
7887 .ndo_set_mac_address = ixgbe_set_mac,
7888 .ndo_change_mtu = ixgbe_change_mtu,
7889 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7890 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7891 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7892 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7893 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7894 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 7895 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 7896 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7897 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7898 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7899#ifdef CONFIG_IXGBE_DCB
24095aa3 7900 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7901#endif
0edc3527
SH		 7902#ifdef CONFIG_NET_POLL_CONTROLLER
7903 .ndo_poll_controller = ixgbe_netpoll,
7904#endif
e0d1095a 7905#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7906 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7907#endif
332d4a7d
YZ		 7908#ifdef IXGBE_FCOE
7909 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7910 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7911 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7912 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7913 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7914 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7915 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7916#endif /* IXGBE_FCOE */
082757af
DS		 7917 .ndo_set_features = ixgbe_set_features,
7918 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7919 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7920 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7921 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7922 .ndo_dfwd_add_station = ixgbe_fwd_add,
7923 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7924};
7925
e027d1ae
JK		 7926/**
7927 * ixgbe_enumerate_functions - Get the number of ports this device has
7928 * @adapter: adapter structure
7929 *
7930 * This function enumerates the phsyical functions co-located on a single slot,
7931 * in order to determine how many ports a device has. This is most useful in
7932 * determining the required GT/s of PCIe bandwidth necessary for optimal
7933 * performance.
7934 **/
7935static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7936{
caafb95d 7937 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 7938 int physfns = 0;
7939
f1f96579
JK		 7940 /* Some cards can not use the generic count PCIe functions method,
7941 * because they are behind a parent switch, so we hardcode these with
7942 * the correct number of functions.
e027d1ae 7943 */
8818970d 7944 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 7945 physfns = 4;
8818970d
JK		 7946
7947 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
7948 /* don't count virtual functions */
caafb95d
JK		 7949 if (entry->is_virtfn)
7950 continue;
7951
7952 /* When the devices on the bus don't all match our device ID,
7953 * we can't reliably determine the correct number of
7954 * functions. This can occur if a function has been direct
7955 * attached to a virtual machine using VT-d, for example. In
7956 * this case, simply return -1 to indicate this.
7957 */
7958 if ((entry->vendor != pdev->vendor) ||
7959 (entry->device != pdev->device))
7960 return -1;
7961
7962 physfns++;
e027d1ae
JK		 7963 }
7964
7965 return physfns;
7966}
7967
8e2813f5
JK		 7968/**
7969 * ixgbe_wol_supported - Check whether device supports WoL
7970 * @hw: hw specific details
7971 * @device_id: the device ID
7972 * @subdev_id: the subsystem device ID
7973 *
7974 * This function is used by probe and ethtool to determine
7975 * which devices have WoL support
7976 *
7977 **/
7978int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7979 u16 subdevice_id)
7980{
7981 struct ixgbe_hw *hw = &adapter->hw;
7982 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7983 int is_wol_supported = 0;
7984
7985 switch (device_id) {
7986 case IXGBE_DEV_ID_82599_SFP:
7987 /* Only these subdevices could supports WOL */
7988 switch (subdevice_id) {
87557440 7989 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7990 case IXGBE_SUBDEV_ID_82599_560FLR:
7991 /* only support first port */
7992 if (hw->bus.func != 0)
7993 break;
5700ff26 7994 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7995 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7996 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7997 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7998 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7999 is_wol_supported = 1;
8000 break;
8001 }
8002 break;
5daebbb0
DS		 8003 case IXGBE_DEV_ID_82599EN_SFP:
8004 /* Only this subdevice supports WOL */
8005 switch (subdevice_id) {
8006 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8007 is_wol_supported = 1;
8008 break;
8009 }
8010 break;
8e2813f5
JK		 8011 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8012 /* All except this subdevice support WOL */
8013 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8014 is_wol_supported = 1;
8015 break;
8016 case IXGBE_DEV_ID_82599_KX4:
8017 is_wol_supported = 1;
8018 break;
8019 case IXGBE_DEV_ID_X540T:
df376f0d 8020 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 8021 /* check eeprom to see if enabled wol */
8022 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8023 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8024 (hw->bus.func == 0))) {
8025 is_wol_supported = 1;
8026 }
8027 break;
8028 }
8029
8030 return is_wol_supported;
8031}
8032
c762dff2
MP		 8033/**
8034 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8035 * @adapter: Pointer to adapter struct
8036 */
8037static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8038{
8039#ifdef CONFIG_OF
8040 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8041 struct ixgbe_hw *hw = &adapter->hw;
8042 const unsigned char *addr;
8043
8044 addr = of_get_mac_address(dp);
8045 if (addr) {
8046 ether_addr_copy(hw->mac.perm_addr, addr);
8047 return;
8048 }
8049#endif /* CONFIG_OF */
8050
8051#ifdef CONFIG_SPARC
8052 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8053#endif /* CONFIG_SPARC */
8054}
8055
9a799d71
AK		 8056/**
8057 * ixgbe_probe - Device Initialization Routine
8058 * @pdev: PCI device information struct
8059 * @ent: entry in ixgbe_pci_tbl
8060 *
8061 * Returns 0 on success, negative on failure
8062 *
8063 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8064 * The OS initialization, configuring of the adapter private structure,
8065 * and a hardware reset occur.
8066 **/
1dd06ae8 8067static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8068{
8069 struct net_device *netdev;
8070 struct ixgbe_adapter *adapter = NULL;
8071 struct ixgbe_hw *hw;
8072 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8073 int i, err, pci_using_dac, expected_gts;
d3cb9869 8074 unsigned int indices = MAX_TX_QUEUES;
289700db 8075 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8076 bool disable_dev = false;
eacd73f7
YZ		 8077#ifdef IXGBE_FCOE
8078 u16 device_caps;
8079#endif
289700db 8080 u32 eec;
9a799d71 8081
bded64a7
AG		 8082 /* Catch broken hardware that put the wrong VF device ID in
8083 * the PCIe SR-IOV capability.
8084 */
8085 if (pdev->is_virtfn) {
8086 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8087 pci_name(pdev), pdev->vendor, pdev->device);
8088 return -EINVAL;
8089 }
8090
9ce77666 8091 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8092 if (err)
8093 return err;
8094
f5f2eda8 8095 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8096 pci_using_dac = 1;
8097 } else {
f5f2eda8 8098 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8099 if (err) {
f5f2eda8
RK		 8100 dev_err(&pdev->dev,
8101 "No usable DMA configuration, aborting\n");
8102 goto err_dma;
9a799d71
AK		 8103 }
8104 pci_using_dac = 0;
8105 }
8106
9ce77666 8107 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8108 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8109 if (err) {
b8bc0421
DC		 8110 dev_err(&pdev->dev,
8111 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8112 goto err_pci_reg;
8113 }
8114
19d5afd4 8115 pci_enable_pcie_error_reporting(pdev);
6fabd715 8116
9a799d71 8117 pci_set_master(pdev);
fb3b27bc 8118 pci_save_state(pdev);
9a799d71 8119
d3cb9869 8120 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8121#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8122 /* 8 TC w/ 4 queues per TC */
8123 indices = 4 * MAX_TRAFFIC_CLASS;
8124#else
8125 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8126#endif
d3cb9869 8127 }
e901acd6 8128
c85a2618 8129 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8130 if (!netdev) {
8131 err = -ENOMEM;
8132 goto err_alloc_etherdev;
8133 }
8134
9a799d71
AK		 8135 SET_NETDEV_DEV(netdev, &pdev->dev);
8136
9a799d71 8137 adapter = netdev_priv(netdev);
c60fbb00 8138 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 8139
8140 adapter->netdev = netdev;
8141 adapter->pdev = pdev;
8142 hw = &adapter->hw;
8143 hw->back = adapter;
b3f4d599 8144 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8145
05857980 8146 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8147 pci_resource_len(pdev, 0));
2a1a091c 8148 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8149 if (!hw->hw_addr) {
8150 err = -EIO;
8151 goto err_ioremap;
8152 }
8153
0edc3527 8154 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8155 ixgbe_set_ethtool_ops(netdev);
9a799d71 8156 netdev->watchdog_timeo = 5 * HZ;
339de30f 8157 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8158
9a799d71
AK		 8159 /* Setup hw api */
8160 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8161 hw->mac.type = ii->mac;
9a799d71 8162
c44ade9e
JB		 8163 /* EEPROM */
8164 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8165 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8166 if (ixgbe_removed(hw->hw_addr)) {
8167 err = -EIO;
8168 goto err_ioremap;
8169 }
c44ade9e
JB		 8170 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8171 if (!(eec & (1 << 8)))
8172 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8173
8174 /* PHY */
8175 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8176 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8177 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8178 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8179 hw->phy.mdio.mmds = 0;
8180 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8181 hw->phy.mdio.dev = netdev;
8182 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8183 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8184
8ca783ab 8185 ii->get_invariants(hw);
9a799d71
AK		 8186
8187 /* setup the private structure */
8188 err = ixgbe_sw_init(adapter);
8189 if (err)
8190 goto err_sw_init;
8191
e86bff0e 8192 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8193 switch (adapter->hw.mac.type) {
8194 case ixgbe_mac_82599EB:
8195 case ixgbe_mac_X540:
9a75a1ac
DS		 8196 case ixgbe_mac_X550:
8197 case ixgbe_mac_X550EM_x:
e86bff0e 8198 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8199 break;
8200 default:
8201 break;
8202 }
e86bff0e 8203
bf069c97
DS		 8204 /*
8205 * If there is a fan on this device and it has failed log the
8206 * failure.
8207 */
8208 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8209 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8210 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8211 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8212 }
8213
8ef78adc
PWJ		 8214 if (allow_unsupported_sfp)
8215 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8216
c44ade9e 8217 /* reset_hw fills in the perm_addr as well */
119fc60a 8218 hw->phy.reset_if_overtemp = true;
c44ade9e 8219 err = hw->mac.ops.reset_hw(hw);
119fc60a 8220 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8221 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8222 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8223 err = 0;
8224 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8225 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8226 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8227 goto err_sw_init;
8228 } else if (err) {
849c4542 8229 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8230 goto err_sw_init;
8231 }
8232
99d74487 8233#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8234 /* SR-IOV not supported on the 82598 */
8235 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8236 goto skip_sriov;
8237 /* Mailbox */
8238 ixgbe_init_mbx_params_pf(hw);
8239 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8240 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8241 ixgbe_enable_sriov(adapter);
60a1a680 8242skip_sriov:
1cdd1ec8 8243
99d74487 8244#endif
396e799c 8245 netdev->features = NETIF_F_SG |
e8e9f696 8246 NETIF_F_IP_CSUM |
082757af 8247 NETIF_F_IPV6_CSUM |
f646968f
PM		 8248 NETIF_F_HW_VLAN_CTAG_TX |
8249 NETIF_F_HW_VLAN_CTAG_RX |
8250 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8251 NETIF_F_TSO |
8252 NETIF_F_TSO6 |
082757af 8253 NETIF_F_RXHASH |
8bf1264d 8254 NETIF_F_RXCSUM;
9a799d71 8255
8bf1264d 8256 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8257
58be7666
DS		 8258 switch (adapter->hw.mac.type) {
8259 case ixgbe_mac_82599EB:
8260 case ixgbe_mac_X540:
9a75a1ac
DS		 8261 case ixgbe_mac_X550:
8262 case ixgbe_mac_X550EM_x:
45a5ead0 8263 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8264 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8265 NETIF_F_NTUPLE;
58be7666
DS		 8266 break;
8267 default:
8268 break;
8269 }
45a5ead0 8270
3f2d1c0f
BG		 8271 netdev->hw_features |= NETIF_F_RXALL;
8272
ad31c402
JK		 8273 netdev->vlan_features |= NETIF_F_TSO;
8274 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8275 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8276 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8277 netdev->vlan_features |= NETIF_F_SG;
8278
01789349 8279 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8280 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8281
7a6b6f51 8282#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8283 netdev->dcbnl_ops = &dcbnl_ops;
8284#endif
8285
eacd73f7 8286#ifdef IXGBE_FCOE
0d551589 8287 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8288 unsigned int fcoe_l;
8289
eacd73f7
YZ		 8290 if (hw->mac.ops.get_device_caps) {
8291 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8292 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8293 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8294 }
7c8ae65a 8295
d3cb9869
AD		 8296
8297 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8298 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8299
a58915c7
AD		 8300 netdev->features |= NETIF_F_FSO |
8301 NETIF_F_FCOE_CRC;
8302
7c8ae65a
AD		 8303 netdev->vlan_features |= NETIF_F_FSO |
8304 NETIF_F_FCOE_CRC |
8305 NETIF_F_FCOE_MTU;
5e09d7f6 8306 }
eacd73f7 8307#endif /* IXGBE_FCOE */
7b872a55 8308 if (pci_using_dac) {
9a799d71 8309 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8310 netdev->vlan_features |= NETIF_F_HIGHDMA;
8311 }
9a799d71 8312
082757af
DS		 8313 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8314 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8315 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8316 netdev->features |= NETIF_F_LRO;
8317
9a799d71 8318 /* make sure the EEPROM is good */
c44ade9e 8319 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8320 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8321 err = -EIO;
35937c05 8322 goto err_sw_init;
9a799d71
AK		 8323 }
8324
c762dff2
MP		 8325 ixgbe_get_platform_mac_addr(adapter);
8326
9a799d71 8327 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8328
aaeb6cdf 8329 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8330 e_dev_err("invalid MAC address\n");
9a799d71 8331 err = -EIO;
35937c05 8332 goto err_sw_init;
9a799d71
AK		 8333 }
8334
5d7daa35
JK		 8335 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8336
7086400d 8337 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8338 (unsigned long) adapter);
9a799d71 8339
58cf663f
MR		 8340 if (ixgbe_removed(hw->hw_addr)) {
8341 err = -EIO;
8342 goto err_sw_init;
8343 }
7086400d 8344 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8345 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8346 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8347
021230d4
AV		 8348 err = ixgbe_init_interrupt_scheme(adapter);
8349 if (err)
8350 goto err_sw_init;
9a799d71 8351
8e2813f5 8352 /* WOL not supported for all devices */
c23f5b6b 8353 adapter->wol = 0;
8e2813f5 8354 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8355 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8356 pdev->subsystem_device);
6b92b0ba 8357 if (hw->wol_enabled)
9417c464 8358 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8359
e8e26350
PW		 8360 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8361
15e5209f
ET		 8362 /* save off EEPROM version number */
8363 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8364 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8365
04f165ef
PW		 8366 /* pick up the PCI bus settings for reporting later */
8367 hw->mac.ops.get_bus_info(hw);
e027d1ae 8368 if (ixgbe_pcie_from_parent(hw))
b8e82001 8369 ixgbe_get_parent_bus_info(adapter);
04f165ef 8370
e027d1ae
JK		 8371 /* calculate the expected PCIe bandwidth required for optimal
8372 * performance. Note that some older parts will never have enough
8373 * bandwidth due to being older generation PCIe parts. We clamp these
8374 * parts to ensure no warning is displayed if it can't be fixed.
8375 */
8376 switch (hw->mac.type) {
8377 case ixgbe_mac_82598EB:
8378 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8379 break;
8380 default:
8381 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8382 break;
0c254d86 8383 }
caafb95d
JK		 8384
8385 /* don't check link if we failed to enumerate functions */
8386 if (expected_gts > 0)
8387 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8388
339de30f 8389 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8390 if (err)
339de30f 8391 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8392 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8393 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8394 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8395 part_str);
6a2aae5a
JK		 8396 else
8397 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8398 hw->mac.type, hw->phy.type, part_str);
8399
8400 e_dev_info("%pM\n", netdev->dev_addr);
8401
9a799d71 8402 /* reset the hardware with the new settings */
794caeb2 8403 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8404 if (err == IXGBE_ERR_EEPROM_VERSION) {
8405 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8406 e_dev_warn("This device is a pre-production adapter/LOM. "
8407 "Please be aware there may be issues associated "
8408 "with your hardware. If you are experiencing "
8409 "problems please contact your Intel or hardware "
8410 "representative who provided you with this "
8411 "hardware.\n");
794caeb2 8412 }
9a799d71
AK		 8413 strcpy(netdev->name, "eth%d");
8414 err = register_netdev(netdev);
8415 if (err)
8416 goto err_register;
8417
ec74a471
ET		 8418 /* power down the optics for 82599 SFP+ fiber */
8419 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8420 hw->mac.ops.disable_tx_laser(hw);
8421
54386467
JB		 8422 /* carrier off reporting is important to ethtool even BEFORE open */
8423 netif_carrier_off(netdev);
8424
5dd2d332 8425#ifdef CONFIG_IXGBE_DCA
652f093f 8426 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8427 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8428 ixgbe_setup_dca(adapter);
8429 }
8430#endif
1cdd1ec8 8431 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8432 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8433 for (i = 0; i < adapter->num_vfs; i++)
8434 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8435 }
8436
2466dd9c
JK		 8437 /* firmware requires driver version to be 0xFFFFFFFF
8438 * since os does not support feature
8439 */
9612de92 8440 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8441 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8442 0xFF);
9612de92 8443
0365e6e4
PW		 8444 /* add san mac addr to netdev */
8445 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8446
ea81875a 8447 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8448
1210982b 8449#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8450 if (ixgbe_sysfs_init(adapter))
8451 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8452#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8453
00949167 8454 ixgbe_dbg_adapter_init(adapter);
00949167 8455
d1a35ee2
ET		 8456 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8457 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8458 hw->mac.ops.setup_link(hw,
8459 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8460 true);
8461
9a799d71
AK		 8462 return 0;
8463
8464err_register:
5eba3699 8465 ixgbe_release_hw_control(adapter);
7a921c93 8466 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8467err_sw_init:
99d74487 8468 ixgbe_disable_sriov(adapter);
7086400d 8469 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8470 iounmap(adapter->io_addr);
5d7daa35 8471 kfree(adapter->mac_table);
9a799d71 8472err_ioremap:
b5b2ffc0 8473 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8474 free_netdev(netdev);
8475err_alloc_etherdev:
e8e9f696
JP		 8476 pci_release_selected_regions(pdev,
8477 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8478err_pci_reg:
8479err_dma:
b5b2ffc0 8480 if (!adapter || disable_dev)
41c62843 8481 pci_disable_device(pdev);
9a799d71
AK		 8482 return err;
8483}
8484
8485/**
8486 * ixgbe_remove - Device Removal Routine
8487 * @pdev: PCI device information struct
8488 *
8489 * ixgbe_remove is called by the PCI subsystem to alert the driver
8490 * that it should release a PCI device. The could be caused by a
8491 * Hot-Plug event, or because the driver is going to be removed from
8492 * memory.
8493 **/
9f9a12f8 8494static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8495{
c60fbb00
AD		 8496 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8497 struct net_device *netdev = adapter->netdev;
b5b2ffc0 8498 bool disable_dev;
9a799d71 8499
00949167 8500 ixgbe_dbg_adapter_exit(adapter);
00949167 8501
09f40aed 8502 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8503 cancel_work_sync(&adapter->service_task);
9a799d71 8504
3a6a4eda 8505
5dd2d332 8506#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8507 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8508 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8509 dca_remove_requester(&pdev->dev);
8510 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8511 }
8512
8513#endif
1210982b 8514#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8515 ixgbe_sysfs_exit(adapter);
1210982b 8516#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8517
0365e6e4
PW		 8518 /* remove the added san mac */
8519 ixgbe_del_sanmac_netdev(netdev);
8520
c4900be0
DS		 8521 if (netdev->reg_state == NETREG_REGISTERED)
8522 unregister_netdev(netdev);
9a799d71 8523
da36b647
GR		 8524#ifdef CONFIG_PCI_IOV
8525 /*
8526 * Only disable SR-IOV on unload if the user specified the now
8527 * deprecated max_vfs module parameter.
8528 */
8529 if (max_vfs)
8530 ixgbe_disable_sriov(adapter);
8531#endif
7a921c93 8532 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8533
021230d4 8534 ixgbe_release_hw_control(adapter);
9a799d71 8535
2b1588c3
AD		 8536#ifdef CONFIG_DCB
8537 kfree(adapter->ixgbe_ieee_pfc);
8538 kfree(adapter->ixgbe_ieee_ets);
8539
8540#endif
2a1a091c 8541 iounmap(adapter->io_addr);
9ce77666 8542 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8543 IORESOURCE_MEM));
9a799d71 8544
849c4542 8545 e_dev_info("complete\n");
021230d4 8546
5d7daa35 8547 kfree(adapter->mac_table);
b5b2ffc0 8548 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8549 free_netdev(netdev);
8550
19d5afd4 8551 pci_disable_pcie_error_reporting(pdev);
6fabd715 8552
b5b2ffc0 8553 if (disable_dev)
41c62843 8554 pci_disable_device(pdev);
9a799d71
AK		 8555}
8556
8557/**
8558 * ixgbe_io_error_detected - called when PCI error is detected
8559 * @pdev: Pointer to PCI device
8560 * @state: The current pci connection state
8561 *
8562 * This function is called after a PCI bus error affecting
8563 * this device has been detected.
8564 */
8565static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8566 pci_channel_state_t state)
9a799d71 8567{
c60fbb00
AD		 8568 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8569 struct net_device *netdev = adapter->netdev;
9a799d71 8570
83c61fa9 8571#ifdef CONFIG_PCI_IOV
14438464 8572 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8573 struct pci_dev *bdev, *vfdev;
8574 u32 dw0, dw1, dw2, dw3;
8575 int vf, pos;
8576 u16 req_id, pf_func;
8577
8578 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8579 adapter->num_vfs == 0)
8580 goto skip_bad_vf_detection;
8581
8582 bdev = pdev->bus->self;
62f87c0e 8583 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8584 bdev = bdev->bus->self;
8585
8586 if (!bdev)
8587 goto skip_bad_vf_detection;
8588
8589 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8590 if (!pos)
8591 goto skip_bad_vf_detection;
8592
14438464
MR		 8593 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8594 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8595 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8596 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8597 if (ixgbe_removed(hw->hw_addr))
8598 goto skip_bad_vf_detection;
83c61fa9
GR		 8599
8600 req_id = dw1 >> 16;
8601 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8602 if (!(req_id & 0x0080))
8603 goto skip_bad_vf_detection;
8604
8605 pf_func = req_id & 0x01;
8606 if ((pf_func & 1) == (pdev->devfn & 1)) {
8607 unsigned int device_id;
8608
8609 vf = (req_id & 0x7F) >> 1;
8610 e_dev_err("VF %d has caused a PCIe error\n", vf);
8611 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8612 "%8.8x\tdw3: %8.8x\n",
8613 dw0, dw1, dw2, dw3);
8614 switch (adapter->hw.mac.type) {
8615 case ixgbe_mac_82599EB:
8616 device_id = IXGBE_82599_VF_DEVICE_ID;
8617 break;
8618 case ixgbe_mac_X540:
8619 device_id = IXGBE_X540_VF_DEVICE_ID;
8620 break;
9a75a1ac
DS		 8621 case ixgbe_mac_X550:
8622 device_id = IXGBE_DEV_ID_X550_VF;
8623 break;
8624 case ixgbe_mac_X550EM_x:
8625 device_id = IXGBE_DEV_ID_X550EM_X_VF;
8626 break;
83c61fa9
GR		 8627 default:
8628 device_id = 0;
8629 break;
8630 }
8631
8632 /* Find the pci device of the offending VF */
36e90319 8633 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8634 while (vfdev) {
8635 if (vfdev->devfn == (req_id & 0xFF))
8636 break;
36e90319 8637 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8638 device_id, vfdev);
8639 }
8640 /*
8641 * There's a slim chance the VF could have been hot plugged,
8642 * so if it is no longer present we don't need to issue the
8643 * VFLR. Just clean up the AER in that case.
8644 */
8645 if (vfdev) {
8646 e_dev_err("Issuing VFLR to VF %d\n", vf);
8647 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8648 /* Free device reference count */
8649 pci_dev_put(vfdev);
83c61fa9
GR		 8650 }
8651
8652 pci_cleanup_aer_uncorrect_error_status(pdev);
8653 }
8654
8655 /*
8656 * Even though the error may have occurred on the other port
8657 * we still need to increment the vf error reference count for
8658 * both ports because the I/O resume function will be called
8659 * for both of them.
8660 */
8661 adapter->vferr_refcount++;
8662
8663 return PCI_ERS_RESULT_RECOVERED;
8664
8665skip_bad_vf_detection:
8666#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8667 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8668 return PCI_ERS_RESULT_DISCONNECT;
8669
41c62843 8670 rtnl_lock();
9a799d71
AK		 8671 netif_device_detach(netdev);
8672
41c62843
MR		 8673 if (state == pci_channel_io_perm_failure) {
8674 rtnl_unlock();
3044b8d1 8675 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8676 }
3044b8d1 8677
9a799d71
AK		 8678 if (netif_running(netdev))
8679 ixgbe_down(adapter);
41c62843
MR		 8680
8681 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8682 pci_disable_device(pdev);
8683 rtnl_unlock();
9a799d71 8684
b4617240 8685 /* Request a slot reset. */
9a799d71
AK		 8686 return PCI_ERS_RESULT_NEED_RESET;
8687}
8688
8689/**
8690 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8691 * @pdev: Pointer to PCI device
8692 *
8693 * Restart the card from scratch, as if from a cold-boot.
8694 */
8695static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8696{
c60fbb00 8697 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8698 pci_ers_result_t result;
8699 int err;
9a799d71 8700
9ce77666 8701 if (pci_enable_device_mem(pdev)) {
396e799c 8702 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8703 result = PCI_ERS_RESULT_DISCONNECT;
8704 } else {
4e857c58 8705 smp_mb__before_atomic();
41c62843 8706 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8707 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8708 pci_set_master(pdev);
8709 pci_restore_state(pdev);
c0e1f68b 8710 pci_save_state(pdev);
9a799d71 8711
dd4d8ca6 8712 pci_wake_from_d3(pdev, false);
9a799d71 8713
6fabd715 8714 ixgbe_reset(adapter);
88512539 8715 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8716 result = PCI_ERS_RESULT_RECOVERED;
8717 }
8718
8719 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8720 if (err) {
849c4542
ET		 8721 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8722 "failed 0x%0x\n", err);
6fabd715
PWJ		 8723 /* non-fatal, continue */
8724 }
9a799d71 8725
6fabd715 8726 return result;
9a799d71
AK		 8727}
8728
8729/**
8730 * ixgbe_io_resume - called when traffic can start flowing again.
8731 * @pdev: Pointer to PCI device
8732 *
8733 * This callback is called when the error recovery driver tells us that
8734 * its OK to resume normal operation.
8735 */
8736static void ixgbe_io_resume(struct pci_dev *pdev)
8737{
c60fbb00
AD		 8738 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8739 struct net_device *netdev = adapter->netdev;
9a799d71 8740
83c61fa9
GR		 8741#ifdef CONFIG_PCI_IOV
8742 if (adapter->vferr_refcount) {
8743 e_info(drv, "Resuming after VF err\n");
8744 adapter->vferr_refcount--;
8745 return;
8746 }
8747
8748#endif
c7ccde0f
AD		 8749 if (netif_running(netdev))
8750 ixgbe_up(adapter);
9a799d71
AK		 8751
8752 netif_device_attach(netdev);
9a799d71
AK		 8753}
8754
3646f0e5 8755static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8756 .error_detected = ixgbe_io_error_detected,
8757 .slot_reset = ixgbe_io_slot_reset,
8758 .resume = ixgbe_io_resume,
8759};
8760
8761static struct pci_driver ixgbe_driver = {
8762 .name = ixgbe_driver_name,
8763 .id_table = ixgbe_pci_tbl,
8764 .probe = ixgbe_probe,
9f9a12f8 8765 .remove = ixgbe_remove,
9a799d71
AK		 8766#ifdef CONFIG_PM
8767 .suspend = ixgbe_suspend,
8768 .resume = ixgbe_resume,
8769#endif
8770 .shutdown = ixgbe_shutdown,
da36b647 8771 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8772 .err_handler = &ixgbe_err_handler
8773};
8774
8775/**
8776 * ixgbe_init_module - Driver Registration Routine
8777 *
8778 * ixgbe_init_module is the first routine called when the driver is
8779 * loaded. All it does is register with the PCI subsystem.
8780 **/
8781static int __init ixgbe_init_module(void)
8782{
8783 int ret;
c7689578 8784 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8785 pr_info("%s\n", ixgbe_copyright);
9a799d71 8786
00949167 8787 ixgbe_dbg_init();
00949167 8788
f01fc1a8
JK		 8789 ret = pci_register_driver(&ixgbe_driver);
8790 if (ret) {
f01fc1a8 8791 ixgbe_dbg_exit();
f01fc1a8
JK		 8792 return ret;
8793 }
8794
5dd2d332 8795#ifdef CONFIG_IXGBE_DCA
bd0362dd 8796 dca_register_notify(&dca_notifier);
bd0362dd 8797#endif
5dd2d332 8798
f01fc1a8 8799 return 0;
9a799d71 8800}
b4617240 8801
9a799d71
AK		 8802module_init(ixgbe_init_module);
8803
8804/**
8805 * ixgbe_exit_module - Driver Exit Cleanup Routine
8806 *
8807 * ixgbe_exit_module is called just before the driver is removed
8808 * from memory.
8809 **/
8810static void __exit ixgbe_exit_module(void)
8811{
5dd2d332 8812#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8813 dca_unregister_notify(&dca_notifier);
8814#endif
9a799d71 8815 pci_unregister_driver(&ixgbe_driver);
00949167 8816
00949167 8817 ixgbe_dbg_exit();
00949167 8818
1a51502b 8819 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8820}
bd0362dd 8821
5dd2d332 8822#ifdef CONFIG_IXGBE_DCA
bd0362dd 8823static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8824 void *p)
bd0362dd
JC		 8825{
8826 int ret_val;
8827
8828 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8829 __ixgbe_notify_dca);
bd0362dd
JC		 8830
8831 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8832}
b453368d 8833
5dd2d332 8834#endif /* CONFIG_IXGBE_DCA */
849c4542 8835
9a799d71
AK		 8836module_exit(ixgbe_exit_module);
8837
8838/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)