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ixgbevf: Add support for PCI error handling
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
729739b7 399 dma_unmap_len(tx_buffer, len) != 0)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
729739b7
AD		 402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
dcd79aeb
TI		 406 }
407 }
408
409 /* Print RX Rings Summary */
410rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 412 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
c7689578
JP		 415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
c7689578
JP		 447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
c7689578 453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
c7689578 464 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
c7689578 470 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
f800326d 481 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 482 }
483 }
484
485 if (i == rx_ring->next_to_use)
c7689578 486 pr_cont(" NTU\n");
dcd79aeb 487 else if (i == rx_ring->next_to_clean)
c7689578 488 pr_cont(" NTC\n");
dcd79aeb 489 else
c7689578 490 pr_cont("\n");
dcd79aeb
TI		 491
492 }
493 }
494
495exit:
496 return;
497}
498
5eba3699
AV		 499static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500{
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 507}
508
509static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510{
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 517}
9a799d71 518
49ce9c2c 519/**
e8e26350
PW		 520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 528 u8 queue, u8 msix_vector)
9a799d71
AK		 529{
530 u32 ivar, index;
e8e26350
PW		 531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
b93a2226 544 case ixgbe_mac_X540:
e8e26350
PW		 545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
9a799d71
AK		 567}
568
fe49f04a 569static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 570 u64 qmask)
fe49f04a
AD		 571{
572 u32 mask;
573
bd508178
AD		 574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
fe49f04a
AD		 576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 578 break;
579 case ixgbe_mac_82599EB:
b93a2226 580 case ixgbe_mac_X540:
fe49f04a
AD		 581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 585 break;
586 default:
587 break;
fe49f04a
AD		 588 }
589}
590
729739b7
AD		 591void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 593{
729739b7
AD		 594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
d3d00239 597 dma_unmap_single(ring->dev,
729739b7
AD		 598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
e5a43549 606 }
729739b7
AD		 607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 611}
612
943561d3 613static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 614{
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 617 int i;
943561d3 618 u32 data;
c84d324c 619
943561d3
AD		 620 if ((hw->fc.current_mode != ixgbe_fc_full) &&
621 (hw->fc.current_mode != ixgbe_fc_rx_pause))
622 return;
c84d324c 623
943561d3
AD		 624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
c84d324c 632
943561d3
AD		 633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
c84d324c 635 return;
943561d3
AD		 636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640}
641
642static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
643{
644 struct ixgbe_hw *hw = &adapter->hw;
645 struct ixgbe_hw_stats *hwstats = &adapter->stats;
646 u32 xoff[8] = {0};
647 int i;
648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
649
650 if (adapter->ixgbe_ieee_pfc)
651 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
652
653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
654 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 655 return;
943561d3 656 }
c84d324c
JF		 657
658 /* update stats for each tc, only valid with PFC enabled */
659 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
660 switch (hw->mac.type) {
661 case ixgbe_mac_82598EB:
662 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 663 break;
c84d324c
JF		 664 default:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 666 }
c84d324c
JF		 667 hwstats->pxoffrxc[i] += xoff[i];
668 }
669
670 /* disarm tx queues that have received xoff frames */
671 for (i = 0; i < adapter->num_tx_queues; i++) {
672 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 673 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 674
675 if (xoff[tc])
676 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 677 }
26f23d82
YZ		 678}
679
c84d324c 680static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 681{
7d7ce682 682 return ring->stats.packets;
c84d324c
JF		 683}
684
685static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
686{
687 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
c84d324c
JF		 690 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
691 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
692
693 if (head != tail)
694 return (head < tail) ?
695 tail - head : (tail + ring->count - head);
696
697 return 0;
698}
699
700static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
701{
702 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
703 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
704 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
705 bool ret = false;
706
7d637bcc 707 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 708
709 /*
710 * Check for a hung queue, but be thorough. This verifies
711 * that a transmit has been completed since the previous
712 * check AND there is at least one packet pending. The
713 * ARMED bit is set to indicate a potential hang. The
714 * bit is cleared if a pause frame is received to remove
715 * false hang detection due to PFC or 802.3x frames. By
716 * requiring this to fail twice we avoid races with
717 * pfc clearing the ARMED bit and conditions where we
718 * run the check_tx_hang logic with a transmit completion
719 * pending but without time to complete it yet.
720 */
721 if ((tx_done_old == tx_done) && tx_pending) {
722 /* make sure it is true for two checks in a row */
723 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
724 &tx_ring->state);
725 } else {
726 /* update completed stats and continue */
727 tx_ring->tx_stats.tx_done_old = tx_done;
728 /* reset the countdown */
729 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 730 }
731
c84d324c 732 return ret;
9a799d71
AK		 733}
734
c83c6cbd
AD		 735/**
736 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
737 * @adapter: driver private struct
738 **/
739static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
740{
741
742 /* Do the reset outside of interrupt context */
743 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
744 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
745 ixgbe_service_event_schedule(adapter);
746 }
747}
e01c31a5 748
9a799d71
AK		 749/**
750 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 751 * @q_vector: structure containing interrupt and ring information
e01c31a5 752 * @tx_ring: tx ring to clean
9a799d71 753 **/
fe49f04a 754static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 755 struct ixgbe_ring *tx_ring)
9a799d71 756{
fe49f04a 757 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 758 struct ixgbe_tx_buffer *tx_buffer;
759 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 760 unsigned int total_bytes = 0, total_packets = 0;
59224555 761 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 762 unsigned int i = tx_ring->next_to_clean;
763
764 if (test_bit(__IXGBE_DOWN, &adapter->state))
765 return true;
9a799d71 766
d3d00239 767 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 768 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 769 i -= tx_ring->count;
12207e49 770
729739b7 771 do {
d3d00239
AD		 772 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
773
774 /* if next_to_watch is not set then there is no work pending */
775 if (!eop_desc)
776 break;
777
7f83a9e6
AD		 778 /* prevent any other reads prior to eop_desc */
779 rmb();
780
d3d00239
AD		 781 /* if DD is not set pending work has not been completed */
782 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
783 break;
8ad494b0 784
d3d00239
AD		 785 /* clear next_to_watch to prevent false hangs */
786 tx_buffer->next_to_watch = NULL;
8ad494b0 787
091a6246
AD		 788 /* update the statistics for this packet */
789 total_bytes += tx_buffer->bytecount;
790 total_packets += tx_buffer->gso_segs;
791
3a6a4eda 792#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 793 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
794 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 795#endif
0ede4a60 796
fd0db0ed
AD		 797 /* free the skb */
798 dev_kfree_skb_any(tx_buffer->skb);
799
729739b7
AD		 800 /* unmap skb header data */
801 dma_unmap_single(tx_ring->dev,
802 dma_unmap_addr(tx_buffer, dma),
803 dma_unmap_len(tx_buffer, len),
804 DMA_TO_DEVICE);
805
fd0db0ed
AD		 806 /* clear tx_buffer data */
807 tx_buffer->skb = NULL;
729739b7 808 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 809
729739b7
AD		 810 /* unmap remaining buffers */
811 while (tx_desc != eop_desc) {
d3d00239
AD		 812 tx_buffer++;
813 tx_desc++;
8ad494b0 814 i++;
729739b7
AD		 815 if (unlikely(!i)) {
816 i -= tx_ring->count;
d3d00239 817 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 819 }
e01c31a5 820
729739b7
AD		 821 /* unmap any remaining paged data */
822 if (dma_unmap_len(tx_buffer, len)) {
823 dma_unmap_page(tx_ring->dev,
824 dma_unmap_addr(tx_buffer, dma),
825 dma_unmap_len(tx_buffer, len),
826 DMA_TO_DEVICE);
827 dma_unmap_len_set(tx_buffer, len, 0);
828 }
829 }
830
831 /* move us one more past the eop_desc for start of next pkt */
832 tx_buffer++;
833 tx_desc++;
834 i++;
835 if (unlikely(!i)) {
836 i -= tx_ring->count;
837 tx_buffer = tx_ring->tx_buffer_info;
838 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
839 }
840
841 /* issue prefetch for next Tx descriptor */
842 prefetch(tx_desc);
12207e49 843
729739b7
AD		 844 /* update budget accounting */
845 budget--;
846 } while (likely(budget));
847
848 i += tx_ring->count;
9a799d71 849 tx_ring->next_to_clean = i;
d3d00239 850 u64_stats_update_begin(&tx_ring->syncp);
b953799e 851 tx_ring->stats.bytes += total_bytes;
bd198058 852 tx_ring->stats.packets += total_packets;
d3d00239 853 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 854 q_vector->tx.total_bytes += total_bytes;
855 q_vector->tx.total_packets += total_packets;
b953799e 856
c84d324c
JF		 857 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
858 /* schedule immediate reset if we believe we hung */
859 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 860 e_err(drv, "Detected Tx Unit Hang\n"
861 " Tx Queue <%d>\n"
862 " TDH, TDT <%x>, <%x>\n"
863 " next_to_use <%x>\n"
864 " next_to_clean <%x>\n"
865 "tx_buffer_info[next_to_clean]\n"
866 " time_stamp <%lx>\n"
867 " jiffies <%lx>\n",
868 tx_ring->queue_index,
869 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
870 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 871 tx_ring->next_to_use, i,
872 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 873
874 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
875
876 e_info(probe,
877 "tx hang %d detected on queue %d, resetting adapter\n",
878 adapter->tx_timeout_count + 1, tx_ring->queue_index);
879
b953799e 880 /* schedule immediate reset if we believe we hung */
c83c6cbd 881 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 882
883 /* the adapter is about to reset, no point in enabling stuff */
59224555 884 return true;
b953799e 885 }
9a799d71 886
b2d96e0a
AD		 887 netdev_tx_completed_queue(txring_txq(tx_ring),
888 total_packets, total_bytes);
889
e092be60 890#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 891 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 892 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 893 /* Make sure that anybody stopping the queue after this
894 * sees the new next_to_clean.
895 */
896 smp_mb();
729739b7
AD		 897 if (__netif_subqueue_stopped(tx_ring->netdev,
898 tx_ring->queue_index)
899 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
900 netif_wake_subqueue(tx_ring->netdev,
901 tx_ring->queue_index);
5b7da515 902 ++tx_ring->tx_stats.restart_queue;
30eba97a 903 }
e092be60 904 }
9a799d71 905
59224555 906 return !!budget;
9a799d71
AK		 907}
908
5dd2d332 909#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 910static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
911 struct ixgbe_ring *tx_ring,
33cf09c9 912 int cpu)
bd0362dd 913{
33cf09c9 914 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 915 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
916 u16 reg_offset;
33cf09c9 917
33cf09c9
AD		 918 switch (hw->mac.type) {
919 case ixgbe_mac_82598EB:
bdda1a61 920 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 921 break;
922 case ixgbe_mac_82599EB:
b93a2226 923 case ixgbe_mac_X540:
bdda1a61
AD		 924 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
925 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 926 break;
927 default:
bdda1a61
AD		 928 /* for unknown hardware do not write register */
929 return;
bd0362dd 930 }
bdda1a61
AD		 931
932 /*
933 * We can enable relaxed ordering for reads, but not writes when
934 * DCA is enabled. This is due to a known issue in some chipsets
935 * which will cause the DCA tag to be cleared.
936 */
937 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
938 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
939 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
940
941 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 942}
943
bdda1a61
AD		 944static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
945 struct ixgbe_ring *rx_ring,
33cf09c9 946 int cpu)
bd0362dd 947{
33cf09c9 948 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 949 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
950 u8 reg_idx = rx_ring->reg_idx;
951
33cf09c9
AD		 952
953 switch (hw->mac.type) {
33cf09c9 954 case ixgbe_mac_82599EB:
b93a2226 955 case ixgbe_mac_X540:
bdda1a61 956 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 957 break;
958 default:
959 break;
960 }
bdda1a61
AD		 961
962 /*
963 * We can enable relaxed ordering for reads, but not writes when
964 * DCA is enabled. This is due to a known issue in some chipsets
965 * which will cause the DCA tag to be cleared.
966 */
967 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
968 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
969 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
970
971 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 972}
973
974static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975{
976 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 977 struct ixgbe_ring *ring;
bd0362dd 978 int cpu = get_cpu();
bd0362dd 979
33cf09c9
AD		 980 if (q_vector->cpu == cpu)
981 goto out_no_update;
982
a557928e 983 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 984 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 985
a557928e 986 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 987 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 988
989 q_vector->cpu = cpu;
990out_no_update:
bd0362dd
JC		 991 put_cpu();
992}
993
994static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
995{
996 int i;
997
998 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
999 return;
1000
e35ec126
AD		 1001 /* always use CB2 mode, difference is masked in the CB driver */
1002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1003
49c7ffbe 1004 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1005 adapter->q_vector[i]->cpu = -1;
1006 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1007 }
1008}
1009
1010static int __ixgbe_notify_dca(struct device *dev, void *data)
1011{
c60fbb00 1012 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1013 unsigned long event = *(unsigned long *)data;
1014
2a72c31e 1015 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1016 return 0;
1017
bd0362dd
JC		 1018 switch (event) {
1019 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1020 /* if we're already enabled, don't do it again */
1021 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1022 break;
652f093f 1023 if (dca_add_requester(dev) == 0) {
96b0e0f6 1024 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1025 ixgbe_setup_dca(adapter);
1026 break;
1027 }
1028 /* Fall Through since DCA is disabled. */
1029 case DCA_PROVIDER_REMOVE:
1030 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1031 dca_remove_requester(dev);
1032 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1034 }
1035 break;
1036 }
1037
652f093f 1038 return 0;
bd0362dd 1039}
67a74ee2 1040
bdda1a61 1041#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1042static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1043 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1044 struct sk_buff *skb)
1045{
8a0da21b
AD		 1046 if (ring->netdev->features & NETIF_F_RXHASH)
1047 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1048}
1049
f800326d 1050#ifdef IXGBE_FCOE
ff886dfc
AD		 1051/**
1052 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1053 * @ring: structure containing ring specific data
ff886dfc
AD		 1054 * @rx_desc: advanced rx descriptor
1055 *
1056 * Returns : true if it is FCoE pkt
1057 */
57efd44c 1058static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1059 union ixgbe_adv_rx_desc *rx_desc)
1060{
1061 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1062
57efd44c 1063 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1064 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1065 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1066 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1067}
1068
f800326d 1069#endif /* IXGBE_FCOE */
e59bd25d
AV		 1070/**
1071 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1072 * @ring: structure containing ring specific data
1073 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1074 * @skb: skb currently being received and modified
1075 **/
8a0da21b 1076static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1077 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1078 struct sk_buff *skb)
9a799d71 1079{
8a0da21b 1080 skb_checksum_none_assert(skb);
9a799d71 1081
712744be 1082 /* Rx csum disabled */
8a0da21b 1083 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1084 return;
e59bd25d
AV		 1085
1086 /* if IP and error */
f56e0cb1
AD		 1087 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1088 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1089 ring->rx_stats.csum_err++;
9a799d71
AK		 1090 return;
1091 }
e59bd25d 1092
f56e0cb1 1093 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1094 return;
1095
f56e0cb1 1096 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1097 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1098
1099 /*
1100 * 82599 errata, UDP frames with a 0 checksum can be marked as
1101 * checksum errors.
1102 */
8a0da21b
AD		 1103 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1104 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1105 return;
1106
8a0da21b 1107 ring->rx_stats.csum_err++;
e59bd25d
AV		 1108 return;
1109 }
1110
9a799d71 1111 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1112 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1113}
1114
84ea2591 1115static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1116{
f56e0cb1 1117 rx_ring->next_to_use = val;
f800326d
AD		 1118
1119 /* update next to alloc since we have filled the ring */
1120 rx_ring->next_to_alloc = val;
e8e26350
PW		 1121 /*
1122 * Force memory writes to complete before letting h/w
1123 * know there are new descriptors to fetch. (Only
1124 * applicable for weak-ordered memory model archs,
1125 * such as IA-64).
1126 */
1127 wmb();
84ea2591 1128 writel(val, rx_ring->tail);
e8e26350
PW		 1129}
1130
f990b79b
AD		 1131static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1132 struct ixgbe_rx_buffer *bi)
1133{
1134 struct page *page = bi->page;
f800326d 1135 dma_addr_t dma = bi->dma;
f990b79b 1136
f800326d
AD		 1137 /* since we are recycling buffers we should seldom need to alloc */
1138 if (likely(dma))
f990b79b
AD		 1139 return true;
1140
f800326d
AD		 1141 /* alloc new page for storage */
1142 if (likely(!page)) {
8633c084 1143 page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
f800326d 1144 ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1145 if (unlikely(!page)) {
1146 rx_ring->rx_stats.alloc_rx_page_failed++;
1147 return false;
1148 }
f800326d 1149 bi->page = page;
f990b79b
AD		 1150 }
1151
f800326d
AD		 1152 /* map page for use */
1153 dma = dma_map_page(rx_ring->dev, page, 0,
1154 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1155
1156 /*
1157 * if mapping failed free memory back to system since
1158 * there isn't much point in holding memory we can't use
1159 */
1160 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1161 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1162 bi->page = NULL;
f990b79b 1163
f990b79b
AD		 1164 rx_ring->rx_stats.alloc_rx_page_failed++;
1165 return false;
1166 }
1167
f800326d
AD		 1168 bi->dma = dma;
1169 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1170
f990b79b
AD		 1171 return true;
1172}
1173
9a799d71 1174/**
f990b79b 1175 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1176 * @rx_ring: ring to place buffers on
1177 * @cleaned_count: number of buffers to replace
9a799d71 1178 **/
fc77dc3c 1179void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1180{
9a799d71 1181 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1182 struct ixgbe_rx_buffer *bi;
d5f398ed 1183 u16 i = rx_ring->next_to_use;
9a799d71 1184
f800326d
AD		 1185 /* nothing to do */
1186 if (!cleaned_count)
fc77dc3c
AD		 1187 return;
1188
e4f74028 1189 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1190 bi = &rx_ring->rx_buffer_info[i];
1191 i -= rx_ring->count;
9a799d71 1192
f800326d
AD		 1193 do {
1194 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1195 break;
d5f398ed 1196
f800326d
AD		 1197 /*
1198 * Refresh the desc even if buffer_addrs didn't change
1199 * because each write-back erases this info.
1200 */
1201 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1202
f990b79b
AD		 1203 rx_desc++;
1204 bi++;
9a799d71 1205 i++;
f990b79b 1206 if (unlikely(!i)) {
e4f74028 1207 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1208 bi = rx_ring->rx_buffer_info;
1209 i -= rx_ring->count;
1210 }
1211
1212 /* clear the hdr_addr for the next_to_use descriptor */
1213 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1214
1215 cleaned_count--;
1216 } while (cleaned_count);
7c6e0a43 1217
f990b79b
AD		 1218 i += rx_ring->count;
1219
f56e0cb1 1220 if (rx_ring->next_to_use != i)
84ea2591 1221 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1222}
1223
1d2024f6
AD		 1224/**
1225 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1226 * @data: pointer to the start of the headers
1227 * @max_len: total length of section to find headers in
1228 *
1229 * This function is meant to determine the length of headers that will
1230 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1231 * motivation of doing this is to only perform one pull for IPv4 TCP
1232 * packets so that we can do basic things like calculating the gso_size
1233 * based on the average data per packet.
1234 **/
1235static unsigned int ixgbe_get_headlen(unsigned char *data,
1236 unsigned int max_len)
1237{
1238 union {
1239 unsigned char *network;
1240 /* l2 headers */
1241 struct ethhdr *eth;
1242 struct vlan_hdr *vlan;
1243 /* l3 headers */
1244 struct iphdr *ipv4;
1245 } hdr;
1246 __be16 protocol;
1247 u8 nexthdr = 0; /* default to not TCP */
1248 u8 hlen;
1249
1250 /* this should never happen, but better safe than sorry */
1251 if (max_len < ETH_HLEN)
1252 return max_len;
1253
1254 /* initialize network frame pointer */
1255 hdr.network = data;
1256
1257 /* set first protocol and move network header forward */
1258 protocol = hdr.eth->h_proto;
1259 hdr.network += ETH_HLEN;
1260
1261 /* handle any vlan tag if present */
1262 if (protocol == __constant_htons(ETH_P_8021Q)) {
1263 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1264 return max_len;
1265
1266 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1267 hdr.network += VLAN_HLEN;
1268 }
1269
1270 /* handle L3 protocols */
1271 if (protocol == __constant_htons(ETH_P_IP)) {
1272 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1273 return max_len;
1274
1275 /* access ihl as a u8 to avoid unaligned access on ia64 */
1276 hlen = (hdr.network[0] & 0x0F) << 2;
1277
1278 /* verify hlen meets minimum size requirements */
1279 if (hlen < sizeof(struct iphdr))
1280 return hdr.network - data;
1281
1282 /* record next protocol */
1283 nexthdr = hdr.ipv4->protocol;
1284 hdr.network += hlen;
f800326d 1285#ifdef IXGBE_FCOE
1d2024f6
AD		 1286 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1287 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1288 return max_len;
1289 hdr.network += FCOE_HEADER_LEN;
1290#endif
1291 } else {
1292 return hdr.network - data;
1293 }
1294
1295 /* finally sort out TCP */
1296 if (nexthdr == IPPROTO_TCP) {
1297 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1298 return max_len;
1299
1300 /* access doff as a u8 to avoid unaligned access on ia64 */
1301 hlen = (hdr.network[12] & 0xF0) >> 2;
1302
1303 /* verify hlen meets minimum size requirements */
1304 if (hlen < sizeof(struct tcphdr))
1305 return hdr.network - data;
1306
1307 hdr.network += hlen;
1308 }
1309
1310 /*
1311 * If everything has gone correctly hdr.network should be the
1312 * data section of the packet and will be the end of the header.
1313 * If not then it probably represents the end of the last recognized
1314 * header.
1315 */
1316 if ((hdr.network - data) < max_len)
1317 return hdr.network - data;
1318 else
1319 return max_len;
1320}
1321
4c1975d7
AD		 1322static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1323 union ixgbe_adv_rx_desc *rx_desc,
1324 struct sk_buff *skb)
aa80175a 1325{
4c1975d7
AD		 1326 __le32 rsc_enabled;
1327 u32 rsc_cnt;
1328
1329 if (!ring_is_rsc_enabled(rx_ring))
1330 return;
1331
1332 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1333 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1334
1335 /* If this is an RSC frame rsc_cnt should be non-zero */
1336 if (!rsc_enabled)
1337 return;
1338
1339 rsc_cnt = le32_to_cpu(rsc_enabled);
1340 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1341
1342 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1343}
43634e82 1344
1d2024f6
AD		 1345static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1346 struct sk_buff *skb)
1347{
f800326d 1348 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1349
1350 /* set gso_size to avoid messing up TCP MSS */
1351 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1352 IXGBE_CB(skb)->append_cnt);
1353}
1354
1355static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1356 struct sk_buff *skb)
1357{
1358 /* if append_cnt is 0 then frame is not RSC */
1359 if (!IXGBE_CB(skb)->append_cnt)
1360 return;
1361
1362 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1363 rx_ring->rx_stats.rsc_flush++;
1364
1365 ixgbe_set_rsc_gso_size(rx_ring, skb);
1366
1367 /* gso_size is computed using append_cnt so always clear it last */
1368 IXGBE_CB(skb)->append_cnt = 0;
1369}
1370
8a0da21b
AD		 1371/**
1372 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1373 * @rx_ring: rx descriptor ring packet is being transacted on
1374 * @rx_desc: pointer to the EOP Rx descriptor
1375 * @skb: pointer to current skb being populated
f8212f97 1376 *
8a0da21b
AD		 1377 * This function checks the ring, descriptor, and packet information in
1378 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1379 * other fields within the skb.
f8212f97 1380 **/
8a0da21b
AD		 1381static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1382 union ixgbe_adv_rx_desc *rx_desc,
1383 struct sk_buff *skb)
f8212f97 1384{
43e95f11
JF		 1385 struct net_device *dev = rx_ring->netdev;
1386
8a0da21b
AD		 1387 ixgbe_update_rsc_stats(rx_ring, skb);
1388
1389 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1390
8a0da21b
AD		 1391 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1392
3a6a4eda 1393#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1394 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1395#endif
1396
43e95f11
JF		 1397 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1398 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1399 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1400 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1401 }
1402
8a0da21b 1403 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1404
43e95f11 1405 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1406}
1407
8a0da21b
AD		 1408static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1409 struct sk_buff *skb)
aa80175a 1410{
8a0da21b
AD		 1411 struct ixgbe_adapter *adapter = q_vector->adapter;
1412
1413 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1414 napi_gro_receive(&q_vector->napi, skb);
1415 else
1416 netif_rx(skb);
aa80175a 1417}
43634e82 1418
f800326d
AD		 1419/**
1420 * ixgbe_is_non_eop - process handling of non-EOP buffers
1421 * @rx_ring: Rx ring being processed
1422 * @rx_desc: Rx descriptor for current buffer
1423 * @skb: Current socket buffer containing buffer in progress
1424 *
1425 * This function updates next to clean. If the buffer is an EOP buffer
1426 * this function exits returning false, otherwise it will place the
1427 * sk_buff in the next buffer to be chained and return true indicating
1428 * that this is in fact a non-EOP buffer.
1429 **/
1430static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1431 union ixgbe_adv_rx_desc *rx_desc,
1432 struct sk_buff *skb)
1433{
1434 u32 ntc = rx_ring->next_to_clean + 1;
1435
1436 /* fetch, update, and store next to clean */
1437 ntc = (ntc < rx_ring->count) ? ntc : 0;
1438 rx_ring->next_to_clean = ntc;
1439
1440 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1441
1442 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1443 return false;
1444
1445 /* append_cnt indicates packet is RSC, if so fetch nextp */
1446 if (IXGBE_CB(skb)->append_cnt) {
1447 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1448 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1449 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1450 }
1451
1452 /* place skb in next buffer to be received */
1453 rx_ring->rx_buffer_info[ntc].skb = skb;
1454 rx_ring->rx_stats.non_eop_descs++;
1455
1456 return true;
1457}
1458
1459/**
1460 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1461 * @rx_ring: rx descriptor ring packet is being transacted on
1462 * @rx_desc: pointer to the EOP Rx descriptor
1463 * @skb: pointer to current skb being fixed
1464 *
1465 * Check for corrupted packet headers caused by senders on the local L2
1466 * embedded NIC switch not setting up their Tx Descriptors right. These
1467 * should be very rare.
1468 *
1469 * Also address the case where we are pulling data in on pages only
1470 * and as such no data is present in the skb header.
1471 *
1472 * In addition if skb is not at least 60 bytes we need to pad it so that
1473 * it is large enough to qualify as a valid Ethernet frame.
1474 *
1475 * Returns true if an error was encountered and skb was freed.
1476 **/
1477static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1480{
1481 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1482 struct net_device *netdev = rx_ring->netdev;
1483 unsigned char *va;
1484 unsigned int pull_len;
1485
1486 /* if the page was released unmap it, else just sync our portion */
1487 if (unlikely(IXGBE_CB(skb)->page_released)) {
1488 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1489 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1490 IXGBE_CB(skb)->page_released = false;
1491 } else {
1492 dma_sync_single_range_for_cpu(rx_ring->dev,
1493 IXGBE_CB(skb)->dma,
1494 frag->page_offset,
1495 ixgbe_rx_bufsz(rx_ring),
1496 DMA_FROM_DEVICE);
1497 }
1498 IXGBE_CB(skb)->dma = 0;
1499
1500 /* verify that the packet does not have any known errors */
1501 if (unlikely(ixgbe_test_staterr(rx_desc,
1502 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1503 !(netdev->features & NETIF_F_RXALL))) {
1504 dev_kfree_skb_any(skb);
1505 return true;
1506 }
1507
1508 /*
1509 * it is valid to use page_address instead of kmap since we are
1510 * working with pages allocated out of the lomem pool per
1511 * alloc_page(GFP_ATOMIC)
1512 */
1513 va = skb_frag_address(frag);
1514
1515 /*
1516 * we need the header to contain the greater of either ETH_HLEN or
1517 * 60 bytes if the skb->len is less than 60 for skb_pad.
1518 */
1519 pull_len = skb_frag_size(frag);
1520 if (pull_len > 256)
1521 pull_len = ixgbe_get_headlen(va, pull_len);
1522
1523 /* align pull length to size of long to optimize memcpy performance */
1524 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1525
1526 /* update all of the pointers */
1527 skb_frag_size_sub(frag, pull_len);
1528 frag->page_offset += pull_len;
1529 skb->data_len -= pull_len;
1530 skb->tail += pull_len;
1531
1532 /*
1533 * if we sucked the frag empty then we should free it,
1534 * if there are other frags here something is screwed up in hardware
1535 */
1536 if (skb_frag_size(frag) == 0) {
1537 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1538 skb_shinfo(skb)->nr_frags = 0;
1539 __skb_frag_unref(frag);
1540 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1541 }
1542
57efd44c
AD		 1543#ifdef IXGBE_FCOE
1544 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1545 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1546 return false;
1547
1548#endif
f800326d
AD		 1549 /* if skb_pad returns an error the skb was freed */
1550 if (unlikely(skb->len < 60)) {
1551 int pad_len = 60 - skb->len;
1552
1553 if (skb_pad(skb, pad_len))
1554 return true;
1555 __skb_put(skb, pad_len);
1556 }
1557
1558 return false;
1559}
1560
1561/**
1562 * ixgbe_can_reuse_page - determine if we can reuse a page
1563 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1564 *
1565 * Returns true if page can be reused in another Rx buffer
1566 **/
1567static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1568{
1569 struct page *page = rx_buffer->page;
1570
1571 /* if we are only owner of page and it is local we can reuse it */
1572 return likely(page_count(page) == 1) &&
1573 likely(page_to_nid(page) == numa_node_id());
1574}
1575
1576/**
1577 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1578 * @rx_ring: rx descriptor ring to store buffers on
1579 * @old_buff: donor buffer to have page reused
1580 *
1581 * Syncronizes page for reuse by the adapter
1582 **/
1583static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1584 struct ixgbe_rx_buffer *old_buff)
1585{
1586 struct ixgbe_rx_buffer *new_buff;
1587 u16 nta = rx_ring->next_to_alloc;
1588 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1589
1590 new_buff = &rx_ring->rx_buffer_info[nta];
1591
1592 /* update, and store next to alloc */
1593 nta++;
1594 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1595
1596 /* transfer page from old buffer to new buffer */
1597 new_buff->page = old_buff->page;
1598 new_buff->dma = old_buff->dma;
1599
1600 /* flip page offset to other buffer and store to new_buff */
1601 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1602
1603 /* sync the buffer for use by the device */
1604 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1605 new_buff->page_offset, bufsz,
1606 DMA_FROM_DEVICE);
1607
1608 /* bump ref count on page before it is given to the stack */
1609 get_page(new_buff->page);
1610}
1611
1612/**
1613 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1614 * @rx_ring: rx descriptor ring to transact packets on
1615 * @rx_buffer: buffer containing page to add
1616 * @rx_desc: descriptor containing length of buffer written by hardware
1617 * @skb: sk_buff to place the data into
1618 *
1619 * This function is based on skb_add_rx_frag. I would have used that
1620 * function however it doesn't handle the truesize case correctly since we
1621 * are allocating more memory than might be used for a single receive.
1622 **/
1623static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1624 struct ixgbe_rx_buffer *rx_buffer,
1625 struct sk_buff *skb, int size)
1626{
1627 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1628 rx_buffer->page, rx_buffer->page_offset,
1629 size);
1630 skb->len += size;
1631 skb->data_len += size;
1632 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1633}
1634
1635/**
1636 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1637 * @q_vector: structure containing interrupt and ring information
1638 * @rx_ring: rx descriptor ring to transact packets on
1639 * @budget: Total limit on number of packets to process
1640 *
1641 * This function provides a "bounce buffer" approach to Rx interrupt
1642 * processing. The advantage to this is that on systems that have
1643 * expensive overhead for IOMMU access this provides a means of avoiding
1644 * it by maintaining the mapping of the page to the syste.
1645 *
1646 * Returns true if all work is completed without reaching budget
1647 **/
4ff7fb12 1648static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1649 struct ixgbe_ring *rx_ring,
4ff7fb12 1650 int budget)
9a799d71 1651{
d2f4fbe2 1652 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1653#ifdef IXGBE_FCOE
f800326d 1654 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1655 int ddp_bytes = 0;
1656#endif /* IXGBE_FCOE */
f800326d 1657 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1658
f800326d
AD		 1659 do {
1660 struct ixgbe_rx_buffer *rx_buffer;
1661 union ixgbe_adv_rx_desc *rx_desc;
1662 struct sk_buff *skb;
1663 struct page *page;
1664 u16 ntc;
1665
1666 /* return some buffers to hardware, one at a time is too slow */
1667 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1668 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1669 cleaned_count = 0;
1670 }
1671
1672 ntc = rx_ring->next_to_clean;
1673 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1674 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1675
1676 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1677 break;
9a799d71 1678
f800326d
AD		 1679 /*
1680 * This memory barrier is needed to keep us from reading
1681 * any other fields out of the rx_desc until we know the
1682 * RXD_STAT_DD bit is set
1683 */
1684 rmb();
9a799d71 1685
f800326d
AD		 1686 page = rx_buffer->page;
1687 prefetchw(page);
9a799d71 1688
f800326d 1689 skb = rx_buffer->skb;
c267fc16 1690
f800326d
AD		 1691 if (likely(!skb)) {
1692 void *page_addr = page_address(page) +
1693 rx_buffer->page_offset;
9a799d71 1694
f800326d
AD		 1695 /* prefetch first cache line of first page */
1696 prefetch(page_addr);
1697#if L1_CACHE_BYTES < 128
1698 prefetch(page_addr + L1_CACHE_BYTES);
1699#endif
1700
1701 /* allocate a skb to store the frags */
1702 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1703 IXGBE_RX_HDR_SIZE);
1704 if (unlikely(!skb)) {
1705 rx_ring->rx_stats.alloc_rx_buff_failed++;
1706 break;
c267fc16
AD		 1707 }
1708
f800326d
AD		 1709 /*
1710 * we will be copying header into skb->data in
1711 * pskb_may_pull so it is in our interest to prefetch
1712 * it now to avoid a possible cache miss
1713 */
1714 prefetchw(skb->data);
4c1975d7
AD		 1715
1716 /*
1717 * Delay unmapping of the first packet. It carries the
1718 * header information, HW may still access the header
f800326d
AD		 1719 * after the writeback. Only unmap it when EOP is
1720 * reached
4c1975d7 1721 */
f800326d 1722 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1723 } else {
f800326d
AD		 1724 /* we are reusing so sync this buffer for CPU use */
1725 dma_sync_single_range_for_cpu(rx_ring->dev,
1726 rx_buffer->dma,
1727 rx_buffer->page_offset,
1728 ixgbe_rx_bufsz(rx_ring),
1729 DMA_FROM_DEVICE);
9a799d71
AK		 1730 }
1731
f800326d
AD		 1732 /* pull page into skb */
1733 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1734 le16_to_cpu(rx_desc->wb.upper.length));
9a799d71 1735
f800326d
AD		 1736 if (ixgbe_can_reuse_page(rx_buffer)) {
1737 /* hand second half of page back to the ring */
1738 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1739 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1740 /* the page has been released from the ring */
1741 IXGBE_CB(skb)->page_released = true;
1742 } else {
1743 /* we are not reusing the buffer so unmap it */
1744 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1745 ixgbe_rx_pg_size(rx_ring),
1746 DMA_FROM_DEVICE);
9a799d71
AK		 1747 }
1748
f800326d
AD		 1749 /* clear contents of buffer_info */
1750 rx_buffer->skb = NULL;
1751 rx_buffer->dma = 0;
1752 rx_buffer->page = NULL;
4c1975d7 1753
f800326d 1754 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1755
9a799d71 1756 cleaned_count++;
f8212f97 1757
f800326d
AD		 1758 /* place incomplete frames back on ring for completion */
1759 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1760 continue;
c267fc16 1761
f800326d
AD		 1762 /* verify the packet layout is correct */
1763 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1764 continue;
9a799d71 1765
d2f4fbe2
AV		 1766 /* probably a little skewed due to removing CRC */
1767 total_rx_bytes += skb->len;
1768 total_rx_packets++;
1769
8a0da21b
AD		 1770 /* populate checksum, timestamp, VLAN, and protocol */
1771 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1772
332d4a7d
YZ		 1773#ifdef IXGBE_FCOE
1774 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1775 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1776 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1777 if (!ddp_bytes) {
1778 dev_kfree_skb_any(skb);
f800326d 1779 continue;
63d635b2 1780 }
3d8fd385 1781 }
f800326d 1782
332d4a7d 1783#endif /* IXGBE_FCOE */
8a0da21b 1784 ixgbe_rx_skb(q_vector, skb);
9a799d71 1785
f800326d 1786 /* update budget accounting */
4ff7fb12 1787 budget--;
f800326d 1788 } while (likely(budget));
9a799d71 1789
3d8fd385
YZ		 1790#ifdef IXGBE_FCOE
1791 /* include DDPed FCoE data */
1792 if (ddp_bytes > 0) {
1793 unsigned int mss;
1794
fc77dc3c 1795 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1796 sizeof(struct fc_frame_header) -
1797 sizeof(struct fcoe_crc_eof);
1798 if (mss > 512)
1799 mss &= ~511;
1800 total_rx_bytes += ddp_bytes;
1801 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1802 }
3d8fd385 1803
f800326d 1804#endif /* IXGBE_FCOE */
c267fc16
AD		 1805 u64_stats_update_begin(&rx_ring->syncp);
1806 rx_ring->stats.packets += total_rx_packets;
1807 rx_ring->stats.bytes += total_rx_bytes;
1808 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1809 q_vector->rx.total_packets += total_rx_packets;
1810 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1811
f800326d
AD		 1812 if (cleaned_count)
1813 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1814
4ff7fb12 1815 return !!budget;
9a799d71
AK		 1816}
1817
9a799d71
AK		 1818/**
1819 * ixgbe_configure_msix - Configure MSI-X hardware
1820 * @adapter: board private structure
1821 *
1822 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1823 * interrupts.
1824 **/
1825static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1826{
021230d4 1827 struct ixgbe_q_vector *q_vector;
49c7ffbe 1828 int v_idx;
021230d4 1829 u32 mask;
9a799d71 1830
8e34d1aa
AD		 1831 /* Populate MSIX to EITR Select */
1832 if (adapter->num_vfs > 32) {
1833 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1835 }
1836
4df10466
JB		 1837 /*
1838 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1839 * corresponding register.
1840 */
49c7ffbe 1841 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1842 struct ixgbe_ring *ring;
7a921c93 1843 q_vector = adapter->q_vector[v_idx];
021230d4 1844
a557928e 1845 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1846 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1847
a557928e 1848 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1849 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1850
d5bf4f67
ET		 1851 if (q_vector->tx.ring && !q_vector->rx.ring) {
1852 /* tx only vector */
1853 if (adapter->tx_itr_setting == 1)
1854 q_vector->itr = IXGBE_10K_ITR;
1855 else
1856 q_vector->itr = adapter->tx_itr_setting;
1857 } else {
1858 /* rx or rx/tx vector */
1859 if (adapter->rx_itr_setting == 1)
1860 q_vector->itr = IXGBE_20K_ITR;
1861 else
1862 q_vector->itr = adapter->rx_itr_setting;
1863 }
021230d4 1864
fe49f04a 1865 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1866 }
1867
bd508178
AD		 1868 switch (adapter->hw.mac.type) {
1869 case ixgbe_mac_82598EB:
e8e26350 1870 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1871 v_idx);
bd508178
AD		 1872 break;
1873 case ixgbe_mac_82599EB:
b93a2226 1874 case ixgbe_mac_X540:
e8e26350 1875 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1876 break;
bd508178
AD		 1877 default:
1878 break;
1879 }
021230d4
AV		 1880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1881
41fb9248 1882 /* set up to autoclear timer, and the vectors */
021230d4 1883 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1884 mask &= ~(IXGBE_EIMS_OTHER |
1885 IXGBE_EIMS_MAILBOX |
1886 IXGBE_EIMS_LSC);
1887
021230d4 1888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1889}
1890
f494e8fa
AV		 1891enum latency_range {
1892 lowest_latency = 0,
1893 low_latency = 1,
1894 bulk_latency = 2,
1895 latency_invalid = 255
1896};
1897
1898/**
1899 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1900 * @q_vector: structure containing interrupt and ring information
1901 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1902 *
1903 * Stores a new ITR value based on packets and byte
1904 * counts during the last interrupt. The advantage of per interrupt
1905 * computation is faster updates and more accurate ITR for the current
1906 * traffic pattern. Constants in this function were computed
1907 * based on theoretical maximum wire speed and thresholds were set based
1908 * on testing data as well as attempting to minimize response time
1909 * while increasing bulk throughput.
1910 * this functionality is controlled by the InterruptThrottleRate module
1911 * parameter (see ixgbe_param.c)
1912 **/
bd198058
AD		 1913static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1914 struct ixgbe_ring_container *ring_container)
f494e8fa 1915{
bd198058
AD		 1916 int bytes = ring_container->total_bytes;
1917 int packets = ring_container->total_packets;
1918 u32 timepassed_us;
621bd70e 1919 u64 bytes_perint;
bd198058 1920 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1921
1922 if (packets == 0)
bd198058 1923 return;
f494e8fa
AV		 1924
1925 /* simple throttlerate management
621bd70e
AD		 1926 * 0-10MB/s lowest (100000 ints/s)
1927 * 10-20MB/s low (20000 ints/s)
1928 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1929 */
1930 /* what was last interrupt timeslice? */
d5bf4f67 1931 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1932 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1933
1934 switch (itr_setting) {
1935 case lowest_latency:
621bd70e 1936 if (bytes_perint > 10)
bd198058 1937 itr_setting = low_latency;
f494e8fa
AV		 1938 break;
1939 case low_latency:
621bd70e 1940 if (bytes_perint > 20)
bd198058 1941 itr_setting = bulk_latency;
621bd70e 1942 else if (bytes_perint <= 10)
bd198058 1943 itr_setting = lowest_latency;
f494e8fa
AV		 1944 break;
1945 case bulk_latency:
621bd70e 1946 if (bytes_perint <= 20)
bd198058 1947 itr_setting = low_latency;
f494e8fa
AV		 1948 break;
1949 }
1950
bd198058
AD		 1951 /* clear work counters since we have the values we need */
1952 ring_container->total_bytes = 0;
1953 ring_container->total_packets = 0;
1954
1955 /* write updated itr to ring container */
1956 ring_container->itr = itr_setting;
f494e8fa
AV		 1957}
1958
509ee935
JB		 1959/**
1960 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1961 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1962 *
1963 * This function is made to be called by ethtool and by the driver
1964 * when it needs to update EITR registers at runtime. Hardware
1965 * specific quirks/differences are taken care of here.
1966 */
fe49f04a 1967void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1968{
fe49f04a 1969 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1970 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1971 int v_idx = q_vector->v_idx;
5d967eb7 1972 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1973
bd508178
AD		 1974 switch (adapter->hw.mac.type) {
1975 case ixgbe_mac_82598EB:
509ee935
JB		 1976 /* must write high and low 16 bits to reset counter */
1977 itr_reg |= (itr_reg << 16);
bd508178
AD		 1978 break;
1979 case ixgbe_mac_82599EB:
b93a2226 1980 case ixgbe_mac_X540:
509ee935
JB		 1981 /*
1982 * set the WDIS bit to not clear the timer bits and cause an
1983 * immediate assertion of the interrupt
1984 */
1985 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1986 break;
1987 default:
1988 break;
509ee935
JB		 1989 }
1990 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1991}
1992
bd198058 1993static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1994{
d5bf4f67 1995 u32 new_itr = q_vector->itr;
bd198058 1996 u8 current_itr;
f494e8fa 1997
bd198058
AD		 1998 ixgbe_update_itr(q_vector, &q_vector->tx);
1999 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2000
08c8833b 2001 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2002
2003 switch (current_itr) {
2004 /* counts and packets in update_itr are dependent on these numbers */
2005 case lowest_latency:
d5bf4f67 2006 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2007 break;
2008 case low_latency:
d5bf4f67 2009 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2010 break;
2011 case bulk_latency:
d5bf4f67 2012 new_itr = IXGBE_8K_ITR;
f494e8fa 2013 break;
bd198058
AD		 2014 default:
2015 break;
f494e8fa
AV		 2016 }
2017
d5bf4f67 2018 if (new_itr != q_vector->itr) {
fe49f04a 2019 /* do an exponential smoothing */
d5bf4f67
ET		 2020 new_itr = (10 * new_itr * q_vector->itr) /
2021 ((9 * new_itr) + q_vector->itr);
509ee935 2022
bd198058 2023 /* save the algorithm value here */
5d967eb7 2024 q_vector->itr = new_itr;
fe49f04a
AD		 2025
2026 ixgbe_write_eitr(q_vector);
f494e8fa 2027 }
f494e8fa
AV		 2028}
2029
119fc60a 2030/**
de88eeeb 2031 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2032 * @adapter: pointer to adapter
119fc60a 2033 **/
f0f9778d 2034static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2035{
119fc60a
MC		 2036 struct ixgbe_hw *hw = &adapter->hw;
2037 u32 eicr = adapter->interrupt_event;
2038
f0f9778d 2039 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2040 return;
2041
f0f9778d
AD		 2042 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2043 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2044 return;
2045
2046 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2047
7ca647bd 2048 switch (hw->device_id) {
f0f9778d
AD		 2049 case IXGBE_DEV_ID_82599_T3_LOM:
2050 /*
2051 * Since the warning interrupt is for both ports
2052 * we don't have to check if:
2053 * - This interrupt wasn't for our port.
2054 * - We may have missed the interrupt so always have to
2055 * check if we got a LSC
2056 */
2057 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2058 !(eicr & IXGBE_EICR_LSC))
2059 return;
2060
2061 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2062 u32 autoneg;
2063 bool link_up = false;
7ca647bd 2064
7ca647bd
JP		 2065 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2066
f0f9778d
AD		 2067 if (link_up)
2068 return;
2069 }
2070
2071 /* Check if this is not due to overtemp */
2072 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2073 return;
2074
2075 break;
7ca647bd
JP		 2076 default:
2077 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2078 return;
7ca647bd 2079 break;
119fc60a 2080 }
7ca647bd
JP		 2081 e_crit(drv,
2082 "Network adapter has been stopped because it has over heated. "
2083 "Restart the computer. If the problem persists, "
2084 "power off the system and replace the adapter\n");
f0f9778d
AD		 2085
2086 adapter->interrupt_event = 0;
119fc60a
MC		 2087}
2088
0befdb3e
JB		 2089static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2090{
2091 struct ixgbe_hw *hw = &adapter->hw;
2092
2093 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2094 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2095 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2096 /* write to clear the interrupt */
2097 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2098 }
2099}
cf8280ee 2100
4f51bf70
JK		 2101static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2102{
2103 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2104 return;
2105
2106 switch (adapter->hw.mac.type) {
2107 case ixgbe_mac_82599EB:
2108 /*
2109 * Need to check link state so complete overtemp check
2110 * on service task
2111 */
2112 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2113 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2114 adapter->interrupt_event = eicr;
2115 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2116 ixgbe_service_event_schedule(adapter);
2117 return;
2118 }
2119 return;
2120 case ixgbe_mac_X540:
2121 if (!(eicr & IXGBE_EICR_TS))
2122 return;
2123 break;
2124 default:
2125 return;
2126 }
2127
2128 e_crit(drv,
2129 "Network adapter has been stopped because it has over heated. "
2130 "Restart the computer. If the problem persists, "
2131 "power off the system and replace the adapter\n");
2132}
2133
e8e26350
PW		 2134static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2135{
2136 struct ixgbe_hw *hw = &adapter->hw;
2137
73c4b7cd
AD		 2138 if (eicr & IXGBE_EICR_GPI_SDP2) {
2139 /* Clear the interrupt */
2140 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2141 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2142 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2143 ixgbe_service_event_schedule(adapter);
2144 }
73c4b7cd
AD		 2145 }
2146
e8e26350
PW		 2147 if (eicr & IXGBE_EICR_GPI_SDP1) {
2148 /* Clear the interrupt */
2149 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2150 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2151 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2152 ixgbe_service_event_schedule(adapter);
2153 }
e8e26350
PW		 2154 }
2155}
2156
cf8280ee
JB		 2157static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2158{
2159 struct ixgbe_hw *hw = &adapter->hw;
2160
2161 adapter->lsc_int++;
2162 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2163 adapter->link_check_timeout = jiffies;
2164 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2165 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2166 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2167 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2168 }
2169}
2170
fe49f04a
AD		 2171static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2172 u64 qmask)
2173{
2174 u32 mask;
bd508178 2175 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2176
bd508178
AD		 2177 switch (hw->mac.type) {
2178 case ixgbe_mac_82598EB:
fe49f04a 2179 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2180 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2181 break;
2182 case ixgbe_mac_82599EB:
b93a2226 2183 case ixgbe_mac_X540:
fe49f04a 2184 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2185 if (mask)
2186 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2187 mask = (qmask >> 32);
bd508178
AD		 2188 if (mask)
2189 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2190 break;
2191 default:
2192 break;
fe49f04a
AD		 2193 }
2194 /* skip the flush */
2195}
2196
2197static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2198 u64 qmask)
fe49f04a
AD		 2199{
2200 u32 mask;
bd508178 2201 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2202
bd508178
AD		 2203 switch (hw->mac.type) {
2204 case ixgbe_mac_82598EB:
fe49f04a 2205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2206 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2207 break;
2208 case ixgbe_mac_82599EB:
b93a2226 2209 case ixgbe_mac_X540:
fe49f04a 2210 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2211 if (mask)
2212 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2213 mask = (qmask >> 32);
bd508178
AD		 2214 if (mask)
2215 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2216 break;
2217 default:
2218 break;
fe49f04a
AD		 2219 }
2220 /* skip the flush */
2221}
2222
021230d4 2223/**
2c4af694
AD		 2224 * ixgbe_irq_enable - Enable default interrupt generation settings
2225 * @adapter: board private structure
021230d4 2226 **/
2c4af694
AD		 2227static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2228 bool flush)
9a799d71 2229{
2c4af694 2230 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2231
2c4af694
AD		 2232 /* don't reenable LSC while waiting for link */
2233 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2234 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2235
2c4af694 2236 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2237 switch (adapter->hw.mac.type) {
2238 case ixgbe_mac_82599EB:
2239 mask |= IXGBE_EIMS_GPI_SDP0;
2240 break;
2241 case ixgbe_mac_X540:
2242 mask |= IXGBE_EIMS_TS;
2243 break;
2244 default:
2245 break;
2246 }
2c4af694
AD		 2247 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2248 mask |= IXGBE_EIMS_GPI_SDP1;
2249 switch (adapter->hw.mac.type) {
2250 case ixgbe_mac_82599EB:
2c4af694
AD		 2251 mask |= IXGBE_EIMS_GPI_SDP1;
2252 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2253 case ixgbe_mac_X540:
2254 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2255 mask |= IXGBE_EIMS_MAILBOX;
2256 break;
2257 default:
2258 break;
9a799d71 2259 }
2c4af694
AD		 2260 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2261 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2262 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2263
2c4af694
AD		 2264 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2265 if (queues)
2266 ixgbe_irq_enable_queues(adapter, ~0);
2267 if (flush)
2268 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2269}
2270
2c4af694 2271static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2272{
a65151ba 2273 struct ixgbe_adapter *adapter = data;
9a799d71 2274 struct ixgbe_hw *hw = &adapter->hw;
54037505 2275 u32 eicr;
91281fd3 2276
54037505
DS		 2277 /*
2278 * Workaround for Silicon errata. Use clear-by-write instead
2279 * of clear-by-read. Reading with EICS will return the
2280 * interrupt causes without clearing, which later be done
2281 * with the write to EICR.
2282 */
2283 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2284 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2285
cf8280ee
JB		 2286 if (eicr & IXGBE_EICR_LSC)
2287 ixgbe_check_lsc(adapter);
f0848276 2288
1cdd1ec8
GR		 2289 if (eicr & IXGBE_EICR_MAILBOX)
2290 ixgbe_msg_task(adapter);
efe3d3c8 2291
bd508178
AD		 2292 switch (hw->mac.type) {
2293 case ixgbe_mac_82599EB:
b93a2226 2294 case ixgbe_mac_X540:
2c4af694
AD		 2295 if (eicr & IXGBE_EICR_ECC)
2296 e_info(link, "Received unrecoverable ECC Err, please "
2297 "reboot\n");
c4cf55e5
PWJ		 2298 /* Handle Flow Director Full threshold interrupt */
2299 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2300 int reinit_count = 0;
c4cf55e5 2301 int i;
c4cf55e5 2302 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2303 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2304 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2305 &ring->state))
2306 reinit_count++;
2307 }
2308 if (reinit_count) {
2309 /* no more flow director interrupts until after init */
2310 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2311 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2312 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2313 }
2314 }
f0f9778d 2315 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2316 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2317 break;
2318 default:
2319 break;
c4cf55e5 2320 }
f0848276 2321
bd508178 2322 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2323#ifdef CONFIG_IXGBE_PTP
2324 ixgbe_ptp_check_pps_event(adapter, eicr);
2325#endif
efe3d3c8 2326
7086400d 2327 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2328 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2329 ixgbe_irq_enable(adapter, false, false);
f0848276 2330
9a799d71 2331 return IRQ_HANDLED;
f0848276 2332}
91281fd3 2333
4ff7fb12 2334static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2335{
021230d4 2336 struct ixgbe_q_vector *q_vector = data;
91281fd3 2337
9b471446 2338 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2339
4ff7fb12
AD		 2340 if (q_vector->rx.ring || q_vector->tx.ring)
2341 napi_schedule(&q_vector->napi);
91281fd3 2342
9a799d71 2343 return IRQ_HANDLED;
91281fd3
AD		 2344}
2345
eb01b975
AD		 2346/**
2347 * ixgbe_poll - NAPI Rx polling callback
2348 * @napi: structure for representing this polling device
2349 * @budget: how many packets driver is allowed to clean
2350 *
2351 * This function is used for legacy and MSI, NAPI mode
2352 **/
8af3c33f 2353int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2354{
2355 struct ixgbe_q_vector *q_vector =
2356 container_of(napi, struct ixgbe_q_vector, napi);
2357 struct ixgbe_adapter *adapter = q_vector->adapter;
2358 struct ixgbe_ring *ring;
2359 int per_ring_budget;
2360 bool clean_complete = true;
2361
2362#ifdef CONFIG_IXGBE_DCA
2363 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2364 ixgbe_update_dca(q_vector);
2365#endif
2366
2367 ixgbe_for_each_ring(ring, q_vector->tx)
2368 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2369
2370 /* attempt to distribute budget to each queue fairly, but don't allow
2371 * the budget to go below 1 because we'll exit polling */
2372 if (q_vector->rx.count > 1)
2373 per_ring_budget = max(budget/q_vector->rx.count, 1);
2374 else
2375 per_ring_budget = budget;
2376
2377 ixgbe_for_each_ring(ring, q_vector->rx)
2378 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2379 per_ring_budget);
2380
2381 /* If all work not completed, return budget and keep polling */
2382 if (!clean_complete)
2383 return budget;
2384
2385 /* all work done, exit the polling mode */
2386 napi_complete(napi);
2387 if (adapter->rx_itr_setting & 1)
2388 ixgbe_set_itr(q_vector);
2389 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2390 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2391
2392 return 0;
2393}
2394
021230d4
AV		 2395/**
2396 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2397 * @adapter: board private structure
2398 *
2399 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2400 * interrupts from the kernel.
2401 **/
2402static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2403{
2404 struct net_device *netdev = adapter->netdev;
207867f5 2405 int vector, err;
e8e9f696 2406 int ri = 0, ti = 0;
021230d4 2407
49c7ffbe 2408 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2409 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2410 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2411
4ff7fb12 2412 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2413 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2414 "%s-%s-%d", netdev->name, "TxRx", ri++);
2415 ti++;
2416 } else if (q_vector->rx.ring) {
9fe93afd 2417 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2418 "%s-%s-%d", netdev->name, "rx", ri++);
2419 } else if (q_vector->tx.ring) {
9fe93afd 2420 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2421 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2422 } else {
2423 /* skip this unused q_vector */
2424 continue;
32aa77a4 2425 }
207867f5
AD		 2426 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2427 q_vector->name, q_vector);
9a799d71 2428 if (err) {
396e799c 2429 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2430 "Error: %d\n", err);
021230d4 2431 goto free_queue_irqs;
9a799d71 2432 }
207867f5
AD		 2433 /* If Flow Director is enabled, set interrupt affinity */
2434 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2435 /* assign the mask for this irq */
2436 irq_set_affinity_hint(entry->vector,
de88eeeb 2437 &q_vector->affinity_mask);
207867f5 2438 }
9a799d71
AK		 2439 }
2440
021230d4 2441 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2442 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2443 if (err) {
de88eeeb 2444 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2445 goto free_queue_irqs;
9a799d71
AK		 2446 }
2447
9a799d71
AK		 2448 return 0;
2449
021230d4 2450free_queue_irqs:
207867f5
AD		 2451 while (vector) {
2452 vector--;
2453 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2454 NULL);
2455 free_irq(adapter->msix_entries[vector].vector,
2456 adapter->q_vector[vector]);
2457 }
021230d4
AV		 2458 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2459 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2460 kfree(adapter->msix_entries);
2461 adapter->msix_entries = NULL;
9a799d71
AK		 2462 return err;
2463}
2464
2465/**
021230d4 2466 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2467 * @irq: interrupt number
2468 * @data: pointer to a network interface device structure
9a799d71
AK		 2469 **/
2470static irqreturn_t ixgbe_intr(int irq, void *data)
2471{
a65151ba 2472 struct ixgbe_adapter *adapter = data;
9a799d71 2473 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2474 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2475 u32 eicr;
2476
54037505 2477 /*
24ddd967 2478 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2479 * before the read of EICR.
2480 */
2481 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2482
021230d4 2483 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2484 * therefore no explicit interrupt disable is necessary */
021230d4 2485 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2486 if (!eicr) {
6af3b9eb
ET		 2487 /*
2488 * shared interrupt alert!
f47cf66e 2489 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2490 * have disabled interrupts due to EIAM
2491 * finish the workaround of silicon errata on 82598. Unmask
2492 * the interrupt that we masked before the EICR read.
2493 */
2494 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2495 ixgbe_irq_enable(adapter, true, true);
9a799d71 2496 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2497 }
9a799d71 2498
cf8280ee
JB		 2499 if (eicr & IXGBE_EICR_LSC)
2500 ixgbe_check_lsc(adapter);
021230d4 2501
bd508178
AD		 2502 switch (hw->mac.type) {
2503 case ixgbe_mac_82599EB:
e8e26350 2504 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2505 /* Fall through */
2506 case ixgbe_mac_X540:
2507 if (eicr & IXGBE_EICR_ECC)
2508 e_info(link, "Received unrecoverable ECC err, please "
2509 "reboot\n");
4f51bf70 2510 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2511 break;
2512 default:
2513 break;
2514 }
e8e26350 2515
0befdb3e 2516 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2517#ifdef CONFIG_IXGBE_PTP
2518 ixgbe_ptp_check_pps_event(adapter, eicr);
2519#endif
0befdb3e 2520
b9f6ed2b
AD		 2521 /* would disable interrupts here but EIAM disabled it */
2522 napi_schedule(&q_vector->napi);
9a799d71 2523
6af3b9eb
ET		 2524 /*
2525 * re-enable link(maybe) and non-queue interrupts, no flush.
2526 * ixgbe_poll will re-enable the queue interrupts
2527 */
6af3b9eb
ET		 2528 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2529 ixgbe_irq_enable(adapter, false, false);
2530
9a799d71
AK		 2531 return IRQ_HANDLED;
2532}
2533
2534/**
2535 * ixgbe_request_irq - initialize interrupts
2536 * @adapter: board private structure
2537 *
2538 * Attempts to configure interrupts using the best available
2539 * capabilities of the hardware and kernel.
2540 **/
021230d4 2541static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2542{
2543 struct net_device *netdev = adapter->netdev;
021230d4 2544 int err;
9a799d71 2545
4cc6df29 2546 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2547 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2548 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2549 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2550 netdev->name, adapter);
4cc6df29 2551 else
a0607fd3 2552 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2553 netdev->name, adapter);
9a799d71 2554
de88eeeb 2555 if (err)
396e799c 2556 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2557
9a799d71
AK		 2558 return err;
2559}
2560
2561static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2562{
49c7ffbe 2563 int vector;
9a799d71 2564
49c7ffbe
AD		 2565 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2566 free_irq(adapter->pdev->irq, adapter);
2567 return;
2568 }
4cc6df29 2569
49c7ffbe
AD		 2570 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2571 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2572 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2573
49c7ffbe
AD		 2574 /* free only the irqs that were actually requested */
2575 if (!q_vector->rx.ring && !q_vector->tx.ring)
2576 continue;
207867f5 2577
49c7ffbe
AD		 2578 /* clear the affinity_mask in the IRQ descriptor */
2579 irq_set_affinity_hint(entry->vector, NULL);
2580
2581 free_irq(entry->vector, q_vector);
9a799d71 2582 }
49c7ffbe
AD		 2583
2584 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2585}
2586
22d5a71b
JB		 2587/**
2588 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2589 * @adapter: board private structure
2590 **/
2591static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2592{
bd508178
AD		 2593 switch (adapter->hw.mac.type) {
2594 case ixgbe_mac_82598EB:
835462fc 2595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2596 break;
2597 case ixgbe_mac_82599EB:
b93a2226 2598 case ixgbe_mac_X540:
835462fc
NS		 2599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2602 break;
2603 default:
2604 break;
22d5a71b
JB		 2605 }
2606 IXGBE_WRITE_FLUSH(&adapter->hw);
2607 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2608 int vector;
2609
2610 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2611 synchronize_irq(adapter->msix_entries[vector].vector);
2612
2613 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2614 } else {
2615 synchronize_irq(adapter->pdev->irq);
2616 }
2617}
2618
9a799d71
AK		 2619/**
2620 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2621 *
2622 **/
2623static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2624{
d5bf4f67 2625 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2626
d5bf4f67
ET		 2627 /* rx/tx vector */
2628 if (adapter->rx_itr_setting == 1)
2629 q_vector->itr = IXGBE_20K_ITR;
2630 else
2631 q_vector->itr = adapter->rx_itr_setting;
2632
2633 ixgbe_write_eitr(q_vector);
9a799d71 2634
e8e26350
PW		 2635 ixgbe_set_ivar(adapter, 0, 0, 0);
2636 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2637
396e799c 2638 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2639}
2640
43e69bf0
AD		 2641/**
2642 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2643 * @adapter: board private structure
2644 * @ring: structure containing ring specific data
2645 *
2646 * Configure the Tx descriptor ring after a reset.
2647 **/
84418e3b
AD		 2648void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2649 struct ixgbe_ring *ring)
43e69bf0
AD		 2650{
2651 struct ixgbe_hw *hw = &adapter->hw;
2652 u64 tdba = ring->dma;
2f1860b8 2653 int wait_loop = 10;
b88c6de2 2654 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2655 u8 reg_idx = ring->reg_idx;
43e69bf0 2656
2f1860b8 2657 /* disable queue to avoid issues while updating state */
b88c6de2 2658 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2659 IXGBE_WRITE_FLUSH(hw);
2660
43e69bf0 2661 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2662 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2663 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2664 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2665 ring->count * sizeof(union ixgbe_adv_tx_desc));
2666 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2667 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2668 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2669
b88c6de2
AD		 2670 /*
2671 * set WTHRESH to encourage burst writeback, it should not be set
2672 * higher than 1 when ITR is 0 as it could cause false TX hangs
2673 *
2674 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2675 * to or less than the number of on chip descriptors, which is
2676 * currently 40.
2677 */
e954b374 2678 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2679 txdctl |= (1 << 16); /* WTHRESH = 1 */
2680 else
2681 txdctl |= (8 << 16); /* WTHRESH = 8 */
2682
e954b374
AD		 2683 /*
2684 * Setting PTHRESH to 32 both improves performance
2685 * and avoids a TX hang with DFP enabled
2686 */
b88c6de2
AD		 2687 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2688 32; /* PTHRESH = 32 */
2f1860b8
AD		 2689
2690 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2691 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2692 adapter->atr_sample_rate) {
2693 ring->atr_sample_rate = adapter->atr_sample_rate;
2694 ring->atr_count = 0;
2695 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2696 } else {
2697 ring->atr_sample_rate = 0;
2698 }
2f1860b8 2699
c84d324c
JF		 2700 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2701
2f1860b8 2702 /* enable queue */
2f1860b8
AD		 2703 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2704
2705 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2706 if (hw->mac.type == ixgbe_mac_82598EB &&
2707 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2708 return;
2709
2710 /* poll to verify queue is enabled */
2711 do {
032b4325 2712 usleep_range(1000, 2000);
2f1860b8
AD		 2713 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2714 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2715 if (!wait_loop)
2716 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2717}
2718
120ff942
AD		 2719static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2720{
2721 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2722 u32 rttdcs, mtqc;
8b1c0b24 2723 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2724
2725 if (hw->mac.type == ixgbe_mac_82598EB)
2726 return;
2727
2728 /* disable the arbiter while setting MTQC */
2729 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2730 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2731 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2732
2733 /* set transmit pool layout */
671c0adb
AD		 2734 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2735 mtqc = IXGBE_MTQC_VT_ENA;
2736 if (tcs > 4)
2737 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2738 else if (tcs > 1)
2739 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2740 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2741 mtqc |= IXGBE_MTQC_32VF;
2742 else
2743 mtqc |= IXGBE_MTQC_64VF;
2744 } else {
2745 if (tcs > 4)
2746 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2747 else if (tcs > 1)
2748 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2749 else
671c0adb
AD		 2750 mtqc = IXGBE_MTQC_64Q_1PB;
2751 }
120ff942 2752
671c0adb 2753 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2754
671c0adb
AD		 2755 /* Enable Security TX Buffer IFG for multiple pb */
2756 if (tcs) {
2757 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2758 sectx |= IXGBE_SECTX_DCB;
2759 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2760 }
2761
2762 /* re-enable the arbiter */
2763 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2764 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2765}
2766
9a799d71 2767/**
3a581073 2768 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2769 * @adapter: board private structure
2770 *
2771 * Configure the Tx unit of the MAC after a reset.
2772 **/
2773static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2774{
2f1860b8
AD		 2775 struct ixgbe_hw *hw = &adapter->hw;
2776 u32 dmatxctl;
43e69bf0 2777 u32 i;
9a799d71 2778
2f1860b8
AD		 2779 ixgbe_setup_mtqc(adapter);
2780
2781 if (hw->mac.type != ixgbe_mac_82598EB) {
2782 /* DMATXCTL.EN must be before Tx queues are enabled */
2783 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2784 dmatxctl |= IXGBE_DMATXCTL_TE;
2785 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2786 }
2787
9a799d71 2788 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2789 for (i = 0; i < adapter->num_tx_queues; i++)
2790 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2791}
2792
3ebe8fde
AD		 2793static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2794 struct ixgbe_ring *ring)
2795{
2796 struct ixgbe_hw *hw = &adapter->hw;
2797 u8 reg_idx = ring->reg_idx;
2798 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2799
2800 srrctl |= IXGBE_SRRCTL_DROP_EN;
2801
2802 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2803}
2804
2805static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2806 struct ixgbe_ring *ring)
2807{
2808 struct ixgbe_hw *hw = &adapter->hw;
2809 u8 reg_idx = ring->reg_idx;
2810 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2811
2812 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2813
2814 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2815}
2816
2817#ifdef CONFIG_IXGBE_DCB
2818void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2819#else
2820static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2821#endif
2822{
2823 int i;
2824 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2825
2826 if (adapter->ixgbe_ieee_pfc)
2827 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2828
2829 /*
2830 * We should set the drop enable bit if:
2831 * SR-IOV is enabled
2832 * or
2833 * Number of Rx queues > 1 and flow control is disabled
2834 *
2835 * This allows us to avoid head of line blocking for security
2836 * and performance reasons.
2837 */
2838 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2839 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2840 for (i = 0; i < adapter->num_rx_queues; i++)
2841 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2842 } else {
2843 for (i = 0; i < adapter->num_rx_queues; i++)
2844 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2845 }
2846}
2847
e8e26350 2848#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2849
a6616b42 2850static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2851 struct ixgbe_ring *rx_ring)
cc41ac7c 2852{
45e9baa5 2853 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2854 u32 srrctl;
bf29ee6c 2855 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2856
45e9baa5
AD		 2857 if (hw->mac.type == ixgbe_mac_82598EB) {
2858 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2859
45e9baa5
AD		 2860 /*
2861 * if VMDq is not active we must program one srrctl register
2862 * per RSS queue since we have enabled RDRXCTL.MVMEN
2863 */
2864 reg_idx &= mask;
2865 }
cc41ac7c 2866
45e9baa5
AD		 2867 /* configure header buffer length, needed for RSC */
2868 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2869
45e9baa5 2870 /* configure the packet buffer length */
f800326d
AD		 2871#if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2872 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2873#else
f800326d 2874 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2875#endif
45e9baa5
AD		 2876
2877 /* configure descriptor type */
f800326d 2878 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2879
45e9baa5 2880 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2881}
9a799d71 2882
05abb126 2883static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2884{
05abb126
AD		 2885 struct ixgbe_hw *hw = &adapter->hw;
2886 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2887 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2888 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2889 u32 mrqc = 0, reta = 0;
2890 u32 rxcsum;
2891 int i, j;
671c0adb
AD		 2892 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2893
671c0adb
AD		 2894 /*
2895 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2896 * make full use of any rings they may have. We will use the
2897 * PSRTYPE register to control how many rings we use within the PF.
2898 */
2899 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2900 rss_i = 2;
0cefafad 2901
05abb126
AD		 2902 /* Fill out hash function seeds */
2903 for (i = 0; i < 10; i++)
2904 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2905
2906 /* Fill out redirection table */
2907 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 2908 if (j == rss_i)
05abb126
AD		 2909 j = 0;
2910 /* reta = 4-byte sliding window of
2911 * 0x00..(indices-1)(indices-1)00..etc. */
2912 reta = (reta << 8) | (j * 0x11);
2913 if ((i & 3) == 3)
2914 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2915 }
0cefafad 2916
05abb126
AD		 2917 /* Disable indicating checksum in descriptor, enables RSS hash */
2918 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2919 rxcsum |= IXGBE_RXCSUM_PCSD;
2920 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2921
671c0adb 2922 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 2923 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 2924 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2925 } else {
671c0adb
AD		 2926 u8 tcs = netdev_get_num_tc(adapter->netdev);
2927
2928 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2929 if (tcs > 4)
2930 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
2931 else if (tcs > 1)
2932 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
2933 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2934 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 2935 else
671c0adb
AD		 2936 mrqc = IXGBE_MRQC_VMDQRSS64EN;
2937 } else {
2938 if (tcs > 4)
8b1c0b24 2939 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 2940 else if (tcs > 1)
2941 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2942 else
2943 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2944 }
0cefafad
JB		 2945 }
2946
05abb126 2947 /* Perform hash on these packet types */
671c0adb
AD		 2948 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2949 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2950 IXGBE_MRQC_RSS_FIELD_IPV6 |
2951 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 2952
ef6afc0c
AD		 2953 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2954 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2955 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2956 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2957
05abb126 2958 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2959}
2960
bb5a9ad2
NS		 2961/**
2962 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2963 * @adapter: address of board private structure
2964 * @index: index of ring to set
bb5a9ad2 2965 **/
082757af 2966static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2967 struct ixgbe_ring *ring)
bb5a9ad2 2968{
bb5a9ad2 2969 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2970 u32 rscctrl;
bf29ee6c 2971 u8 reg_idx = ring->reg_idx;
7367096a 2972
7d637bcc 2973 if (!ring_is_rsc_enabled(ring))
7367096a 2974 return;
bb5a9ad2 2975
7367096a 2976 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2977 rscctrl |= IXGBE_RSCCTL_RSCEN;
2978 /*
2979 * we must limit the number of descriptors so that the
2980 * total size of max desc * buf_len is not greater
642c680e 2981 * than 65536
bb5a9ad2 2982 */
f800326d
AD		 2983#if (PAGE_SIZE <= 8192)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2985#elif (PAGE_SIZE <= 16384)
2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
bb5a9ad2 2987#else
f800326d 2988 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
bb5a9ad2 2989#endif
7367096a 2990 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2991}
2992
9e10e045
AD		 2993#define IXGBE_MAX_RX_DESC_POLL 10
2994static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2995 struct ixgbe_ring *ring)
2996{
2997 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2998 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2999 u32 rxdctl;
bf29ee6c 3000 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3001
3002 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3003 if (hw->mac.type == ixgbe_mac_82598EB &&
3004 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3005 return;
3006
3007 do {
032b4325 3008 usleep_range(1000, 2000);
9e10e045
AD		 3009 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3010 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3011
3012 if (!wait_loop) {
3013 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3014 "the polling period\n", reg_idx);
3015 }
3016}
3017
2d39d576
YZ		 3018void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3019 struct ixgbe_ring *ring)
3020{
3021 struct ixgbe_hw *hw = &adapter->hw;
3022 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3023 u32 rxdctl;
3024 u8 reg_idx = ring->reg_idx;
3025
3026 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3027 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3028
3029 /* write value back with RXDCTL.ENABLE bit cleared */
3030 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3031
3032 if (hw->mac.type == ixgbe_mac_82598EB &&
3033 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3034 return;
3035
3036 /* the hardware may take up to 100us to really disable the rx queue */
3037 do {
3038 udelay(10);
3039 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3040 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3041
3042 if (!wait_loop) {
3043 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3044 "the polling period\n", reg_idx);
3045 }
3046}
3047
84418e3b
AD		 3048void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3049 struct ixgbe_ring *ring)
acd37177
AD		 3050{
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 u64 rdba = ring->dma;
9e10e045 3053 u32 rxdctl;
bf29ee6c 3054 u8 reg_idx = ring->reg_idx;
acd37177 3055
9e10e045
AD		 3056 /* disable queue to avoid issues while updating state */
3057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3058 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3059
acd37177
AD		 3060 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3061 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3062 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3063 ring->count * sizeof(union ixgbe_adv_rx_desc));
3064 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3065 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3066 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3067
3068 ixgbe_configure_srrctl(adapter, ring);
3069 ixgbe_configure_rscctl(adapter, ring);
3070
e9f98072
GR		 3071 /* If operating in IOV mode set RLPML for X540 */
3072 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3073 hw->mac.type == ixgbe_mac_X540) {
3074 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3075 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3076 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3077 }
3078
9e10e045
AD		 3079 if (hw->mac.type == ixgbe_mac_82598EB) {
3080 /*
3081 * enable cache line friendly hardware writes:
3082 * PTHRESH=32 descriptors (half the internal cache),
3083 * this also removes ugly rx_no_buffer_count increment
3084 * HTHRESH=4 descriptors (to minimize latency on fetch)
3085 * WTHRESH=8 burst writeback up to two cache lines
3086 */
3087 rxdctl &= ~0x3FFFFF;
3088 rxdctl |= 0x080420;
3089 }
3090
3091 /* enable receive descriptor ring */
3092 rxdctl |= IXGBE_RXDCTL_ENABLE;
3093 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3094
3095 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3096 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3097}
3098
48654521
AD		 3099static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3100{
3101 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3102 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3103 int p;
3104
3105 /* PSRTYPE must be initialized in non 82598 adapters */
3106 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3107 IXGBE_PSRTYPE_UDPHDR |
3108 IXGBE_PSRTYPE_IPV4HDR |
48654521 3109 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3110 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3111
3112 if (hw->mac.type == ixgbe_mac_82598EB)
3113 return;
3114
fbe7ca7f
AD		 3115 if (rss_i > 3)
3116 psrtype |= 2 << 29;
3117 else if (rss_i > 1)
3118 psrtype |= 1 << 29;
48654521
AD		 3119
3120 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3121 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3122 psrtype);
3123}
3124
f5b4a52e
AD		 3125static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3126{
3127 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3128 u32 reg_offset, vf_shift;
435b19f6 3129 u32 gcr_ext, vmdctl;
de4c7f65 3130 int i;
f5b4a52e
AD		 3131
3132 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3133 return;
3134
3135 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3136 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3137 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3138 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3139 vmdctl |= IXGBE_VT_CTL_REPLEN;
3140 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3141
1d9c0bfd
AD		 3142 vf_shift = VMDQ_P(0) % 32;
3143 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3144
3145 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3146 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3147 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3148 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3149 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3150 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3151
3152 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3153 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3154
3155 /*
3156 * Set up VF register offsets for selected VT Mode,
3157 * i.e. 32 or 64 VFs for SR-IOV
3158 */
73079ea0
AD		 3159 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3160 case IXGBE_82599_VMDQ_8Q_MASK:
3161 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3162 break;
3163 case IXGBE_82599_VMDQ_4Q_MASK:
3164 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3165 break;
3166 default:
3167 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3168 break;
3169 }
3170
f5b4a52e
AD		 3171 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3172
3173 /* enable Tx loopback for VF/PF communication */
3174 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
435b19f6 3175
a985b6c3 3176 /* Enable MAC Anti-Spoofing */
435b19f6 3177 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3178 adapter->num_vfs);
de4c7f65
GR		 3179 /* For VFs that have spoof checking turned off */
3180 for (i = 0; i < adapter->num_vfs; i++) {
3181 if (!adapter->vfinfo[i].spoofchk_enabled)
3182 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3183 }
f5b4a52e
AD		 3184}
3185
477de6ed 3186static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3187{
9a799d71
AK		 3188 struct ixgbe_hw *hw = &adapter->hw;
3189 struct net_device *netdev = adapter->netdev;
3190 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3191 struct ixgbe_ring *rx_ring;
3192 int i;
3193 u32 mhadd, hlreg0;
48654521 3194
63f39bd1 3195#ifdef IXGBE_FCOE
477de6ed
AD		 3196 /* adjust max frame to be able to do baby jumbo for FCoE */
3197 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3198 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3199 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3200
477de6ed
AD		 3201#endif /* IXGBE_FCOE */
3202 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3203 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3204 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3205 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3206
3207 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3208 }
3209
919e78a6
AD		 3210 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3211 max_frame += VLAN_HLEN;
3212
477de6ed
AD		 3213 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3214 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3215 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3216 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3217
0cefafad
JB		 3218 /*
3219 * Setup the HW Rx Head and Tail Descriptor Pointers and
3220 * the Base and Length of the Rx Descriptor Ring
3221 */
9a799d71 3222 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3223 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3224 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3225 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3226 else
7d637bcc 3227 clear_ring_rsc_enabled(rx_ring);
477de6ed 3228 }
477de6ed
AD		 3229}
3230
7367096a
AD		 3231static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3232{
3233 struct ixgbe_hw *hw = &adapter->hw;
3234 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3235
3236 switch (hw->mac.type) {
3237 case ixgbe_mac_82598EB:
3238 /*
3239 * For VMDq support of different descriptor types or
3240 * buffer sizes through the use of multiple SRRCTL
3241 * registers, RDRXCTL.MVMEN must be set to 1
3242 *
3243 * also, the manual doesn't mention it clearly but DCA hints
3244 * will only use queue 0's tags unless this bit is set. Side
3245 * effects of setting this bit are only that SRRCTL must be
3246 * fully programmed [0..15]
3247 */
3248 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3249 break;
3250 case ixgbe_mac_82599EB:
b93a2226 3251 case ixgbe_mac_X540:
7367096a
AD		 3252 /* Disable RSC for ACK packets */
3253 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3254 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3255 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3256 /* hardware requires some bits to be set by default */
3257 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3258 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3259 break;
3260 default:
3261 /* We should do nothing since we don't know this hardware */
3262 return;
3263 }
3264
3265 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3266}
3267
477de6ed
AD		 3268/**
3269 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3270 * @adapter: board private structure
3271 *
3272 * Configure the Rx unit of the MAC after a reset.
3273 **/
3274static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3275{
3276 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3277 int i;
3278 u32 rxctrl;
477de6ed
AD		 3279
3280 /* disable receives while setting up the descriptors */
3281 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3282 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3283
3284 ixgbe_setup_psrtype(adapter);
7367096a 3285 ixgbe_setup_rdrxctl(adapter);
477de6ed 3286
9e10e045 3287 /* Program registers for the distribution of queues */
f5b4a52e 3288 ixgbe_setup_mrqc(adapter);
f5b4a52e 3289
477de6ed
AD		 3290 /* set_rx_buffer_len must be called before ring initialization */
3291 ixgbe_set_rx_buffer_len(adapter);
3292
3293 /*
3294 * Setup the HW Rx Head and Tail Descriptor Pointers and
3295 * the Base and Length of the Rx Descriptor Ring
3296 */
9e10e045
AD		 3297 for (i = 0; i < adapter->num_rx_queues; i++)
3298 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3299
9e10e045
AD		 3300 /* disable drop enable for 82598 parts */
3301 if (hw->mac.type == ixgbe_mac_82598EB)
3302 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3303
3304 /* enable all receives */
3305 rxctrl |= IXGBE_RXCTRL_RXEN;
3306 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3307}
3308
8e586137 3309static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3310{
3311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3312 struct ixgbe_hw *hw = &adapter->hw;
3313
3314 /* add VID to filter table */
1d9c0bfd 3315 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3316 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3317
3318 return 0;
068c89b0
DS		 3319}
3320
8e586137 3321static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3322{
3323 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3324 struct ixgbe_hw *hw = &adapter->hw;
3325
068c89b0 3326 /* remove VID from filter table */
1d9c0bfd 3327 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3328 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3329
3330 return 0;
068c89b0
DS		 3331}
3332
5f6c0181
JB		 3333/**
3334 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3335 * @adapter: driver data
3336 */
3337static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3338{
3339 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3340 u32 vlnctrl;
3341
3342 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3343 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3344 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3345}
3346
3347/**
3348 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3349 * @adapter: driver data
3350 */
3351static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3352{
3353 struct ixgbe_hw *hw = &adapter->hw;
3354 u32 vlnctrl;
3355
3356 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3357 vlnctrl |= IXGBE_VLNCTRL_VFE;
3358 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3359 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3360}
3361
3362/**
3363 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3364 * @adapter: driver data
3365 */
3366static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3367{
3368 struct ixgbe_hw *hw = &adapter->hw;
3369 u32 vlnctrl;
5f6c0181
JB		 3370 int i, j;
3371
3372 switch (hw->mac.type) {
3373 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3374 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3375 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3376 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3377 break;
3378 case ixgbe_mac_82599EB:
b93a2226 3379 case ixgbe_mac_X540:
5f6c0181
JB		 3380 for (i = 0; i < adapter->num_rx_queues; i++) {
3381 j = adapter->rx_ring[i]->reg_idx;
3382 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3383 vlnctrl &= ~IXGBE_RXDCTL_VME;
3384 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3385 }
3386 break;
3387 default:
3388 break;
3389 }
3390}
3391
3392/**
f62bbb5e 3393 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3394 * @adapter: driver data
3395 */
f62bbb5e 3396static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3397{
3398 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3399 u32 vlnctrl;
5f6c0181
JB		 3400 int i, j;
3401
3402 switch (hw->mac.type) {
3403 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3404 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3405 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3406 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3407 break;
3408 case ixgbe_mac_82599EB:
b93a2226 3409 case ixgbe_mac_X540:
5f6c0181
JB		 3410 for (i = 0; i < adapter->num_rx_queues; i++) {
3411 j = adapter->rx_ring[i]->reg_idx;
3412 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3413 vlnctrl |= IXGBE_RXDCTL_VME;
3414 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3415 }
3416 break;
3417 default:
3418 break;
3419 }
3420}
3421
9a799d71
AK		 3422static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3423{
f62bbb5e 3424 u16 vid;
9a799d71 3425
f62bbb5e
JG		 3426 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3427
3428 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3429 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3430}
3431
2850062a
AD		 3432/**
3433 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3434 * @netdev: network interface device structure
3435 *
3436 * Writes unicast address list to the RAR table.
3437 * Returns: -ENOMEM on failure/insufficient address space
3438 * 0 on no addresses written
3439 * X on writing X addresses to the RAR table
3440 **/
3441static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3442{
3443 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3444 struct ixgbe_hw *hw = &adapter->hw;
a1cbb15c 3445 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3446 int count = 0;
3447
3448 /* return ENOMEM indicating insufficient memory for addresses */
3449 if (netdev_uc_count(netdev) > rar_entries)
3450 return -ENOMEM;
3451
3452 if (!netdev_uc_empty(netdev) && rar_entries) {
3453 struct netdev_hw_addr *ha;
3454 /* return error if we do not support writing to RAR table */
3455 if (!hw->mac.ops.set_rar)
3456 return -ENOMEM;
3457
3458 netdev_for_each_uc_addr(ha, netdev) {
3459 if (!rar_entries)
3460 break;
3461 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3462 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3463 count++;
3464 }
3465 }
3466 /* write the addresses in reverse order to avoid write combining */
3467 for (; rar_entries > 0 ; rar_entries--)
3468 hw->mac.ops.clear_rar(hw, rar_entries);
3469
3470 return count;
3471}
3472
9a799d71 3473/**
2c5645cf 3474 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3475 * @netdev: network interface device structure
3476 *
2c5645cf
CL		 3477 * The set_rx_method entry point is called whenever the unicast/multicast
3478 * address list or the network interface flags are updated. This routine is
3479 * responsible for configuring the hardware for proper unicast, multicast and
3480 * promiscuous mode.
9a799d71 3481 **/
7f870475 3482void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3483{
3484 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3485 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3486 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3487 int count;
9a799d71
AK		 3488
3489 /* Check for Promiscuous and All Multicast modes */
3490
3491 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3492
f5dc442b 3493 /* set all bits that we expect to always be set */
3f2d1c0f 3494 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3495 fctrl |= IXGBE_FCTRL_BAM;
3496 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3497 fctrl |= IXGBE_FCTRL_PMCF;
3498
2850062a
AD		 3499 /* clear the bits we are changing the status of */
3500 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3501
9a799d71 3502 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3503 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3504 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3505 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3506 /* don't hardware filter vlans in promisc mode */
3507 ixgbe_vlan_filter_disable(adapter);
9a799d71 3508 } else {
746b9f02
PM		 3509 if (netdev->flags & IFF_ALLMULTI) {
3510 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3511 vmolr |= IXGBE_VMOLR_MPE;
3512 } else {
3513 /*
3514 * Write addresses to the MTA, if the attempt fails
25985edc 3515 * then we should just turn on promiscuous mode so
2850062a
AD		 3516 * that we can at least receive multicast traffic
3517 */
3518 hw->mac.ops.update_mc_addr_list(hw, netdev);
3519 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3520 }
5f6c0181 3521 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3522 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3523 }
3524
3525 /*
3526 * Write addresses to available RAR registers, if there is not
3527 * sufficient space to store all the addresses then enable
3528 * unicast promiscuous mode
3529 */
3530 count = ixgbe_write_uc_addr_list(netdev);
3531 if (count < 0) {
3532 fctrl |= IXGBE_FCTRL_UPE;
3533 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3534 }
3535
1d9c0bfd 3536 if (adapter->num_vfs)
1cdd1ec8 3537 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3538
3539 if (hw->mac.type != ixgbe_mac_82598EB) {
3540 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3541 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3542 IXGBE_VMOLR_ROPE);
1d9c0bfd 3543 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3544 }
3545
3f2d1c0f
BG		 3546 /* This is useful for sniffing bad packets. */
3547 if (adapter->netdev->features & NETIF_F_RXALL) {
3548 /* UPE and MPE will be handled by normal PROMISC logic
3549 * in e1000e_set_rx_mode */
3550 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3551 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3552 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3553
3554 fctrl &= ~(IXGBE_FCTRL_DPF);
3555 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3556 }
3557
2850062a 3558 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3559
3560 if (netdev->features & NETIF_F_HW_VLAN_RX)
3561 ixgbe_vlan_strip_enable(adapter);
3562 else
3563 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3564}
3565
021230d4
AV		 3566static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3567{
3568 int q_idx;
021230d4 3569
49c7ffbe
AD		 3570 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3571 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3572}
3573
3574static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3575{
3576 int q_idx;
021230d4 3577
49c7ffbe
AD		 3578 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3579 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3580}
3581
7a6b6f51 3582#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3583/**
2f90b865
AD		 3584 * ixgbe_configure_dcb - Configure DCB hardware
3585 * @adapter: ixgbe adapter struct
3586 *
3587 * This is called by the driver on open to configure the DCB hardware.
3588 * This is also called by the gennetlink interface when reconfiguring
3589 * the DCB state.
3590 */
3591static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3592{
3593 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3594 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3595
67ebd791
AD		 3596 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3597 if (hw->mac.type == ixgbe_mac_82598EB)
3598 netif_set_gso_max_size(adapter->netdev, 65536);
3599 return;
3600 }
3601
3602 if (hw->mac.type == ixgbe_mac_82598EB)
3603 netif_set_gso_max_size(adapter->netdev, 32768);
3604
2f90b865 3605 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3606
971060b1 3607#ifdef IXGBE_FCOE
b120818e
JF		 3608 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3609 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3610#endif
b120818e
JF		 3611
3612 /* reconfigure the hardware */
3613 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3614 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3615 DCB_TX_CONFIG);
3616 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3617 DCB_RX_CONFIG);
3618 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3619 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3620 ixgbe_dcb_hw_ets(&adapter->hw,
3621 adapter->ixgbe_ieee_ets,
3622 max_frame);
3623 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3624 adapter->ixgbe_ieee_pfc->pfc_en,
3625 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3626 }
8187cd48
JF		 3627
3628 /* Enable RSS Hash per TC */
3629 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3630 u32 msb = 0;
3631 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3632
d411a936
AD		 3633 while (rss_i) {
3634 msb++;
3635 rss_i >>= 1;
3636 }
8187cd48 3637
4ae63730
AD		 3638 /* write msb to all 8 TCs in one write */
3639 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3640 }
2f90b865 3641}
9da712d2
JF		 3642#endif
3643
3644/* Additional bittime to account for IXGBE framing */
3645#define IXGBE_ETH_FRAMING 20
3646
49ce9c2c 3647/**
9da712d2
JF		 3648 * ixgbe_hpbthresh - calculate high water mark for flow control
3649 *
3650 * @adapter: board private structure to calculate for
49ce9c2c 3651 * @pb: packet buffer to calculate
9da712d2
JF		 3652 */
3653static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3654{
3655 struct ixgbe_hw *hw = &adapter->hw;
3656 struct net_device *dev = adapter->netdev;
3657 int link, tc, kb, marker;
3658 u32 dv_id, rx_pba;
3659
3660 /* Calculate max LAN frame size */
3661 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3662
3663#ifdef IXGBE_FCOE
3664 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3665 if ((dev->features & NETIF_F_FCOE_MTU) &&
3666 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3667 (pb == ixgbe_fcoe_get_tc(adapter)))
3668 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3669
3670#endif
9da712d2
JF		 3671 /* Calculate delay value for device */
3672 switch (hw->mac.type) {
3673 case ixgbe_mac_X540:
3674 dv_id = IXGBE_DV_X540(link, tc);
3675 break;
3676 default:
3677 dv_id = IXGBE_DV(link, tc);
3678 break;
3679 }
3680
3681 /* Loopback switch introduces additional latency */
3682 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3683 dv_id += IXGBE_B2BT(tc);
3684
3685 /* Delay value is calculated in bit times convert to KB */
3686 kb = IXGBE_BT2KB(dv_id);
3687 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3688
3689 marker = rx_pba - kb;
3690
3691 /* It is possible that the packet buffer is not large enough
3692 * to provide required headroom. In this case throw an error
3693 * to user and a do the best we can.
3694 */
3695 if (marker < 0) {
3696 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3697 "headroom to support flow control."
3698 "Decrease MTU or number of traffic classes\n", pb);
3699 marker = tc + 1;
3700 }
3701
3702 return marker;
3703}
3704
49ce9c2c 3705/**
9da712d2
JF		 3706 * ixgbe_lpbthresh - calculate low water mark for for flow control
3707 *
3708 * @adapter: board private structure to calculate for
49ce9c2c 3709 * @pb: packet buffer to calculate
9da712d2
JF		 3710 */
3711static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3712{
3713 struct ixgbe_hw *hw = &adapter->hw;
3714 struct net_device *dev = adapter->netdev;
3715 int tc;
3716 u32 dv_id;
3717
3718 /* Calculate max LAN frame size */
3719 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3720
3721 /* Calculate delay value for device */
3722 switch (hw->mac.type) {
3723 case ixgbe_mac_X540:
3724 dv_id = IXGBE_LOW_DV_X540(tc);
3725 break;
3726 default:
3727 dv_id = IXGBE_LOW_DV(tc);
3728 break;
3729 }
3730
3731 /* Delay value is calculated in bit times convert to KB */
3732 return IXGBE_BT2KB(dv_id);
3733}
3734
3735/*
3736 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3737 */
3738static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3739{
3740 struct ixgbe_hw *hw = &adapter->hw;
3741 int num_tc = netdev_get_num_tc(adapter->netdev);
3742 int i;
3743
3744 if (!num_tc)
3745 num_tc = 1;
3746
3747 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3748
3749 for (i = 0; i < num_tc; i++) {
3750 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3751
3752 /* Low water marks must not be larger than high water marks */
3753 if (hw->fc.low_water > hw->fc.high_water[i])
3754 hw->fc.low_water = 0;
3755 }
3756}
3757
80605c65
JF		 3758static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3759{
80605c65 3760 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3761 int hdrm;
3762 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3763
3764 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3765 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3766 hdrm = 32 << adapter->fdir_pballoc;
3767 else
3768 hdrm = 0;
80605c65 3769
f7e1027f 3770 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3771 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3772}
3773
e4911d57
AD		 3774static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3775{
3776 struct ixgbe_hw *hw = &adapter->hw;
3777 struct hlist_node *node, *node2;
3778 struct ixgbe_fdir_filter *filter;
3779
3780 spin_lock(&adapter->fdir_perfect_lock);
3781
3782 if (!hlist_empty(&adapter->fdir_filter_list))
3783 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3784
3785 hlist_for_each_entry_safe(filter, node, node2,
3786 &adapter->fdir_filter_list, fdir_node) {
3787 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3788 &filter->filter,
3789 filter->sw_idx,
3790 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3791 IXGBE_FDIR_DROP_QUEUE :
3792 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3793 }
3794
3795 spin_unlock(&adapter->fdir_perfect_lock);
3796}
3797
9a799d71
AK		 3798static void ixgbe_configure(struct ixgbe_adapter *adapter)
3799{
d2f5e7f3
AS		 3800 struct ixgbe_hw *hw = &adapter->hw;
3801
80605c65 3802 ixgbe_configure_pb(adapter);
7a6b6f51 3803#ifdef CONFIG_IXGBE_DCB
67ebd791 3804 ixgbe_configure_dcb(adapter);
2f90b865 3805#endif
9a799d71 3806
4c1d7b4b 3807 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3808 ixgbe_restore_vlan(adapter);
3809
d2f5e7f3
AS		 3810 switch (hw->mac.type) {
3811 case ixgbe_mac_82599EB:
3812 case ixgbe_mac_X540:
3813 hw->mac.ops.disable_rx_buff(hw);
3814 break;
3815 default:
3816 break;
3817 }
3818
c4cf55e5 3819 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3820 ixgbe_init_fdir_signature_82599(&adapter->hw,
3821 adapter->fdir_pballoc);
e4911d57
AD		 3822 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3823 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3824 adapter->fdir_pballoc);
3825 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3826 }
4c1d7b4b 3827
d2f5e7f3
AS		 3828 switch (hw->mac.type) {
3829 case ixgbe_mac_82599EB:
3830 case ixgbe_mac_X540:
3831 hw->mac.ops.enable_rx_buff(hw);
3832 break;
3833 default:
3834 break;
3835 }
3836
933d41f1 3837 ixgbe_configure_virtualization(adapter);
c4cf55e5 3838
7c8ae65a
AD		 3839#ifdef IXGBE_FCOE
3840 /* configure FCoE L2 filters, redirection table, and Rx control */
3841 ixgbe_configure_fcoe(adapter);
3842
3843#endif /* IXGBE_FCOE */
9a799d71
AK		 3844 ixgbe_configure_tx(adapter);
3845 ixgbe_configure_rx(adapter);
9a799d71
AK		 3846}
3847
e8e26350
PW		 3848static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3849{
3850 switch (hw->phy.type) {
3851 case ixgbe_phy_sfp_avago:
3852 case ixgbe_phy_sfp_ftl:
3853 case ixgbe_phy_sfp_intel:
3854 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3855 case ixgbe_phy_sfp_passive_tyco:
3856 case ixgbe_phy_sfp_passive_unknown:
3857 case ixgbe_phy_sfp_active_unknown:
3858 case ixgbe_phy_sfp_ftl_active:
e8e26350 3859 return true;
8917b447
AD		 3860 case ixgbe_phy_nl:
3861 if (hw->mac.type == ixgbe_mac_82598EB)
3862 return true;
e8e26350
PW		 3863 default:
3864 return false;
3865 }
3866}
3867
0ecc061d 3868/**
e8e26350
PW		 3869 * ixgbe_sfp_link_config - set up SFP+ link
3870 * @adapter: pointer to private adapter struct
3871 **/
3872static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3873{
7086400d 3874 /*
52f33af8 3875 * We are assuming the worst case scenario here, and that
7086400d
AD		 3876 * is that an SFP was inserted/removed after the reset
3877 * but before SFP detection was enabled. As such the best
3878 * solution is to just start searching as soon as we start
3879 */
3880 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3881 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3882
7086400d 3883 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3884}
3885
3886/**
3887 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3888 * @hw: pointer to private hardware struct
3889 *
3890 * Returns 0 on success, negative on failure
3891 **/
e8e26350 3892static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3893{
3894 u32 autoneg;
8620a103 3895 bool negotiation, link_up = false;
0ecc061d
PWJ		 3896 u32 ret = IXGBE_ERR_LINK_SETUP;
3897
3898 if (hw->mac.ops.check_link)
3899 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3900
3901 if (ret)
3902 goto link_cfg_out;
3903
0b0c2b31
ET		 3904 autoneg = hw->phy.autoneg_advertised;
3905 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3906 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3907 &negotiation);
0ecc061d
PWJ		 3908 if (ret)
3909 goto link_cfg_out;
3910
8620a103
MC		 3911 if (hw->mac.ops.setup_link)
3912 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3913link_cfg_out:
3914 return ret;
3915}
3916
a34bcfff 3917static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3918{
9a799d71 3919 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3920 u32 gpie = 0;
9a799d71 3921
9b471446 3922 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3923 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3924 IXGBE_GPIE_OCD;
3925 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3926 /*
3927 * use EIAM to auto-mask when MSI-X interrupt is asserted
3928 * this saves a register write for every interrupt
3929 */
3930 switch (hw->mac.type) {
3931 case ixgbe_mac_82598EB:
3932 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3933 break;
9b471446 3934 case ixgbe_mac_82599EB:
b93a2226
DS		 3935 case ixgbe_mac_X540:
3936 default:
9b471446
JB		 3937 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3938 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3939 break;
3940 }
3941 } else {
021230d4
AV		 3942 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3943 * specifically only auto mask tx and rx interrupts */
3944 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3945 }
9a799d71 3946
a34bcfff
AD		 3947 /* XXX: to interrupt immediately for EICS writes, enable this */
3948 /* gpie |= IXGBE_GPIE_EIMEN; */
3949
3950 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3951 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 3952
3953 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3954 case IXGBE_82599_VMDQ_8Q_MASK:
3955 gpie |= IXGBE_GPIE_VTMODE_16;
3956 break;
3957 case IXGBE_82599_VMDQ_4Q_MASK:
3958 gpie |= IXGBE_GPIE_VTMODE_32;
3959 break;
3960 default:
3961 gpie |= IXGBE_GPIE_VTMODE_64;
3962 break;
3963 }
119fc60a
MC		 3964 }
3965
5fdd31f9 3966 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3967 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3968 switch (adapter->hw.mac.type) {
3969 case ixgbe_mac_82599EB:
3970 gpie |= IXGBE_SDP0_GPIEN;
3971 break;
3972 case ixgbe_mac_X540:
3973 gpie |= IXGBE_EIMS_TS;
3974 break;
3975 default:
3976 break;
3977 }
3978 }
5fdd31f9 3979
a34bcfff
AD		 3980 /* Enable fan failure interrupt */
3981 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3982 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3983
2698b208 3984 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3985 gpie |= IXGBE_SDP1_GPIEN;
3986 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3987 }
a34bcfff
AD		 3988
3989 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3990}
3991
c7ccde0f 3992static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3993{
3994 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3995 int err;
a34bcfff
AD		 3996 u32 ctrl_ext;
3997
3998 ixgbe_get_hw_control(adapter);
3999 ixgbe_setup_gpie(adapter);
e8e26350 4000
9a799d71
AK		 4001 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4002 ixgbe_configure_msix(adapter);
4003 else
4004 ixgbe_configure_msi_and_legacy(adapter);
4005
c6ecf39a
DS		 4006 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4007 if (hw->mac.ops.enable_tx_laser &&
4008 ((hw->phy.multispeed_fiber) ||
9f911707 4009 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4010 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4011 hw->mac.ops.enable_tx_laser(hw);
4012
9a799d71 4013 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4014 ixgbe_napi_enable_all(adapter);
4015
73c4b7cd
AD		 4016 if (ixgbe_is_sfp(hw)) {
4017 ixgbe_sfp_link_config(adapter);
4018 } else {
4019 err = ixgbe_non_sfp_link_config(hw);
4020 if (err)
4021 e_err(probe, "link_config FAILED %d\n", err);
4022 }
4023
021230d4
AV		 4024 /* clear any pending interrupts, may auto mask */
4025 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4026 ixgbe_irq_enable(adapter, true, true);
9a799d71 4027
bf069c97
DS		 4028 /*
4029 * If this adapter has a fan, check to see if we had a failure
4030 * before we enabled the interrupt.
4031 */
4032 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4033 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4034 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4035 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4036 }
4037
1da100bb 4038 /* enable transmits */
477de6ed 4039 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4040
9a799d71
AK		 4041 /* bring the link up in the watchdog, this could race with our first
4042 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4043 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4044 adapter->link_check_timeout = jiffies;
7086400d 4045 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4046
4047 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4048 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4049 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4050 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4051}
4052
d4f80882
AV		 4053void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4054{
4055 WARN_ON(in_interrupt());
7086400d
AD		 4056 /* put off any impending NetWatchDogTimeout */
4057 adapter->netdev->trans_start = jiffies;
4058
d4f80882 4059 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4060 usleep_range(1000, 2000);
d4f80882 4061 ixgbe_down(adapter);
5809a1ae
GR		 4062 /*
4063 * If SR-IOV enabled then wait a bit before bringing the adapter
4064 * back up to give the VFs time to respond to the reset. The
4065 * two second wait is based upon the watchdog timer cycle in
4066 * the VF driver.
4067 */
4068 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4069 msleep(2000);
d4f80882
AV		 4070 ixgbe_up(adapter);
4071 clear_bit(__IXGBE_RESETTING, &adapter->state);
4072}
4073
c7ccde0f 4074void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4075{
4076 /* hardware has been reset, we need to reload some things */
4077 ixgbe_configure(adapter);
4078
c7ccde0f 4079 ixgbe_up_complete(adapter);
9a799d71
AK		 4080}
4081
4082void ixgbe_reset(struct ixgbe_adapter *adapter)
4083{
c44ade9e 4084 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4085 int err;
4086
7086400d
AD		 4087 /* lock SFP init bit to prevent race conditions with the watchdog */
4088 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4089 usleep_range(1000, 2000);
4090
4091 /* clear all SFP and link config related flags while holding SFP_INIT */
4092 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4093 IXGBE_FLAG2_SFP_NEEDS_RESET);
4094 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4095
8ca783ab 4096 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4097 switch (err) {
4098 case 0:
4099 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4100 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4101 break;
4102 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4103 e_dev_err("master disable timed out\n");
da4dd0f7 4104 break;
794caeb2
PWJ		 4105 case IXGBE_ERR_EEPROM_VERSION:
4106 /* We are running on a pre-production device, log a warning */
849c4542 4107 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4108 "Please be aware there may be issues associated with "
849c4542
ET		 4109 "your hardware. If you are experiencing problems "
4110 "please contact your Intel or hardware "
4111 "representative who provided you with this "
4112 "hardware.\n");
794caeb2 4113 break;
da4dd0f7 4114 default:
849c4542 4115 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4116 }
9a799d71 4117
7086400d
AD		 4118 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4119
9a799d71 4120 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4121 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4122
4123 /* update SAN MAC vmdq pool selection */
4124 if (hw->mac.san_mac_rar_index)
4125 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
9a799d71
AK		 4126}
4127
f800326d
AD		 4128/**
4129 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4130 * @rx_ring: ring to setup
4131 *
4132 * On many IA platforms the L1 cache has a critical stride of 4K, this
4133 * results in each receive buffer starting in the same cache set. To help
4134 * reduce the pressure on this cache set we can interleave the offsets so
4135 * that only every other buffer will be in the same cache set.
4136 **/
4137static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4138{
4139 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4140 u16 i;
4141
4142 for (i = 0; i < rx_ring->count; i += 2) {
4143 rx_buffer[0].page_offset = 0;
4144 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4145 rx_buffer = &rx_buffer[2];
4146 }
4147}
4148
9a799d71
AK		 4149/**
4150 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4151 * @rx_ring: ring to free buffers from
4152 **/
b6ec895e 4153static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4154{
b6ec895e 4155 struct device *dev = rx_ring->dev;
9a799d71 4156 unsigned long size;
b6ec895e 4157 u16 i;
9a799d71 4158
84418e3b
AD		 4159 /* ring already cleared, nothing to do */
4160 if (!rx_ring->rx_buffer_info)
4161 return;
9a799d71 4162
84418e3b 4163 /* Free all the Rx ring sk_buffs */
9a799d71 4164 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4165 struct ixgbe_rx_buffer *rx_buffer;
4166
4167 rx_buffer = &rx_ring->rx_buffer_info[i];
4168 if (rx_buffer->skb) {
4169 struct sk_buff *skb = rx_buffer->skb;
4170 if (IXGBE_CB(skb)->page_released) {
4171 dma_unmap_page(dev,
4172 IXGBE_CB(skb)->dma,
4173 ixgbe_rx_bufsz(rx_ring),
4174 DMA_FROM_DEVICE);
4175 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4176 }
4177 dev_kfree_skb(skb);
9a799d71 4178 }
f800326d
AD		 4179 rx_buffer->skb = NULL;
4180 if (rx_buffer->dma)
4181 dma_unmap_page(dev, rx_buffer->dma,
4182 ixgbe_rx_pg_size(rx_ring),
4183 DMA_FROM_DEVICE);
4184 rx_buffer->dma = 0;
4185 if (rx_buffer->page)
dd411ec4
AD		 4186 __free_pages(rx_buffer->page,
4187 ixgbe_rx_pg_order(rx_ring));
f800326d 4188 rx_buffer->page = NULL;
9a799d71
AK		 4189 }
4190
4191 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4192 memset(rx_ring->rx_buffer_info, 0, size);
4193
f800326d
AD		 4194 ixgbe_init_rx_page_offset(rx_ring);
4195
9a799d71
AK		 4196 /* Zero out the descriptor ring */
4197 memset(rx_ring->desc, 0, rx_ring->size);
4198
f800326d 4199 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4200 rx_ring->next_to_clean = 0;
4201 rx_ring->next_to_use = 0;
9a799d71
AK		 4202}
4203
4204/**
4205 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4206 * @tx_ring: ring to be cleaned
4207 **/
b6ec895e 4208static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4209{
4210 struct ixgbe_tx_buffer *tx_buffer_info;
4211 unsigned long size;
b6ec895e 4212 u16 i;
9a799d71 4213
84418e3b
AD		 4214 /* ring already cleared, nothing to do */
4215 if (!tx_ring->tx_buffer_info)
4216 return;
9a799d71 4217
84418e3b 4218 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4219 for (i = 0; i < tx_ring->count; i++) {
4220 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4221 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4222 }
4223
dad8a3b3
JF		 4224 netdev_tx_reset_queue(txring_txq(tx_ring));
4225
9a799d71
AK		 4226 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4227 memset(tx_ring->tx_buffer_info, 0, size);
4228
4229 /* Zero out the descriptor ring */
4230 memset(tx_ring->desc, 0, tx_ring->size);
4231
4232 tx_ring->next_to_use = 0;
4233 tx_ring->next_to_clean = 0;
9a799d71
AK		 4234}
4235
4236/**
021230d4 4237 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4238 * @adapter: board private structure
4239 **/
021230d4 4240static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4241{
4242 int i;
4243
021230d4 4244 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4245 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4246}
4247
4248/**
021230d4 4249 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4250 * @adapter: board private structure
4251 **/
021230d4 4252static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4253{
4254 int i;
4255
021230d4 4256 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4257 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4258}
4259
e4911d57
AD		 4260static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4261{
4262 struct hlist_node *node, *node2;
4263 struct ixgbe_fdir_filter *filter;
4264
4265 spin_lock(&adapter->fdir_perfect_lock);
4266
4267 hlist_for_each_entry_safe(filter, node, node2,
4268 &adapter->fdir_filter_list, fdir_node) {
4269 hlist_del(&filter->fdir_node);
4270 kfree(filter);
4271 }
4272 adapter->fdir_filter_count = 0;
4273
4274 spin_unlock(&adapter->fdir_perfect_lock);
4275}
4276
9a799d71
AK		 4277void ixgbe_down(struct ixgbe_adapter *adapter)
4278{
4279 struct net_device *netdev = adapter->netdev;
7f821875 4280 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4281 u32 rxctrl;
bf29ee6c 4282 int i;
9a799d71
AK		 4283
4284 /* signal that we are down to the interrupt handler */
4285 set_bit(__IXGBE_DOWN, &adapter->state);
4286
4287 /* disable receives */
7f821875
JB		 4288 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4289 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4290
2d39d576
YZ		 4291 /* disable all enabled rx queues */
4292 for (i = 0; i < adapter->num_rx_queues; i++)
4293 /* this call also flushes the previous write */
4294 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4295
032b4325 4296 usleep_range(10000, 20000);
9a799d71 4297
7f821875
JB		 4298 netif_tx_stop_all_queues(netdev);
4299
7086400d 4300 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4301 netif_carrier_off(netdev);
4302 netif_tx_disable(netdev);
4303
4304 ixgbe_irq_disable(adapter);
4305
4306 ixgbe_napi_disable_all(adapter);
4307
d034acf1
AD		 4308 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4309 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4310 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4311
4312 del_timer_sync(&adapter->service_timer);
4313
34cecbbf 4314 if (adapter->num_vfs) {
8e34d1aa
AD		 4315 /* Clear EITR Select mapping */
4316 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4317
4318 /* Mark all the VFs as inactive */
4319 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4320 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4321
34cecbbf
AD		 4322 /* ping all the active vfs to let them know we are going down */
4323 ixgbe_ping_all_vfs(adapter);
4324
4325 /* Disable all VFTE/VFRE TX/RX */
4326 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4327 }
4328
7f821875
JB		 4329 /* disable transmits in the hardware now that interrupts are off */
4330 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4331 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4332 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4333 }
34cecbbf
AD		 4334
4335 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4336 switch (hw->mac.type) {
4337 case ixgbe_mac_82599EB:
b93a2226 4338 case ixgbe_mac_X540:
88512539 4339 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4340 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4341 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4342 break;
4343 default:
4344 break;
4345 }
7f821875 4346
6f4a0e45
PL		 4347 if (!pci_channel_offline(adapter->pdev))
4348 ixgbe_reset(adapter);
c6ecf39a
DS		 4349
4350 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4351 if (hw->mac.ops.disable_tx_laser &&
4352 ((hw->phy.multispeed_fiber) ||
9f911707 4353 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4354 (hw->mac.type == ixgbe_mac_82599EB))))
4355 hw->mac.ops.disable_tx_laser(hw);
4356
9a799d71
AK		 4357 ixgbe_clean_all_tx_rings(adapter);
4358 ixgbe_clean_all_rx_rings(adapter);
4359
5dd2d332 4360#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4361 /* since we reset the hardware DCA settings were cleared */
e35ec126 4362 ixgbe_setup_dca(adapter);
96b0e0f6 4363#endif
9a799d71
AK		 4364}
4365
9a799d71
AK		 4366/**
4367 * ixgbe_tx_timeout - Respond to a Tx Hang
4368 * @netdev: network interface device structure
4369 **/
4370static void ixgbe_tx_timeout(struct net_device *netdev)
4371{
4372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4373
4374 /* Do the reset outside of interrupt context */
c83c6cbd 4375 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4376}
4377
9a799d71
AK		 4378/**
4379 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4380 * @adapter: board private structure to initialize
4381 *
4382 * ixgbe_sw_init initializes the Adapter private data structure.
4383 * Fields are initialized based on PCI device information and
4384 * OS network device settings (MTU size).
4385 **/
4386static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4387{
4388 struct ixgbe_hw *hw = &adapter->hw;
4389 struct pci_dev *pdev = adapter->pdev;
021230d4 4390 unsigned int rss;
7a6b6f51 4391#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4392 int j;
4393 struct tc_configuration *tc;
4394#endif
021230d4 4395
c44ade9e
JB		 4396 /* PCI config space info */
4397
4398 hw->vendor_id = pdev->vendor;
4399 hw->device_id = pdev->device;
4400 hw->revision_id = pdev->revision;
4401 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4402 hw->subsystem_device_id = pdev->subsystem_device;
4403
021230d4 4404 /* Set capability flags */
3ed69d7e 4405 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4406 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4407 switch (hw->mac.type) {
4408 case ixgbe_mac_82598EB:
bf069c97
DS		 4409 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4410 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4411 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4412 break;
b93a2226 4413 case ixgbe_mac_X540:
4f51bf70
JK		 4414 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4415 case ixgbe_mac_82599EB:
49c7ffbe 4416 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4417 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4418 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4419 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4420 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4421 /* Flow Director hash filters enabled */
4422 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4423 adapter->atr_sample_rate = 20;
c087663e 4424 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4425 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4426 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4427#ifdef IXGBE_FCOE
0d551589
YZ		 4428 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4429 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4430#ifdef CONFIG_IXGBE_DCB
6ee16520 4431 /* Default traffic class to use for FCoE */
56075a98 4432 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4433#endif
eacd73f7 4434#endif /* IXGBE_FCOE */
bd508178
AD		 4435 break;
4436 default:
4437 break;
f8212f97 4438 }
2f90b865 4439
7c8ae65a
AD		 4440#ifdef IXGBE_FCOE
4441 /* FCoE support exists, always init the FCoE lock */
4442 spin_lock_init(&adapter->fcoe.lock);
4443
4444#endif
1fc5f038
AD		 4445 /* n-tuple support exists, always init our spinlock */
4446 spin_lock_init(&adapter->fdir_perfect_lock);
4447
7a6b6f51 4448#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4449 switch (hw->mac.type) {
4450 case ixgbe_mac_X540:
4451 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4452 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4453 break;
4454 default:
4455 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4456 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4457 break;
4458 }
4459
2f90b865
AD		 4460 /* Configure DCB traffic classes */
4461 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4462 tc = &adapter->dcb_cfg.tc_config[j];
4463 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4464 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4465 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4466 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4467 tc->dcb_pfc = pfc_disabled;
4468 }
4de2a022
JF		 4469
4470 /* Initialize default user to priority mapping, UPx->TC0 */
4471 tc = &adapter->dcb_cfg.tc_config[0];
4472 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4473 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4474
2f90b865
AD		 4475 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4476 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4477 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4478 adapter->dcb_set_bitmap = 0x00;
3032309b 4479 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4480 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4481 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4482
4483#endif
9a799d71
AK		 4484
4485 /* default flow control settings */
cd7664f6 4486 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4487 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4488 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4489 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4490 hw->fc.send_xon = true;
71fd570b 4491 hw->fc.disable_fc_autoneg = false;
9a799d71 4492
99d74487
AD		 4493#ifdef CONFIG_PCI_IOV
4494 /* assign number of SR-IOV VFs */
4495 if (hw->mac.type != ixgbe_mac_82598EB)
4496 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4497
4498#endif
30efa5a3 4499 /* enable itr by default in dynamic mode */
f7554a2b 4500 adapter->rx_itr_setting = 1;
f7554a2b 4501 adapter->tx_itr_setting = 1;
30efa5a3 4502
30efa5a3
JB		 4503 /* set default ring sizes */
4504 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4505 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4506
bd198058 4507 /* set default work limits */
59224555 4508 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4509
9a799d71 4510 /* initialize eeprom parameters */
c44ade9e 4511 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4512 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4513 return -EIO;
4514 }
4515
9a799d71
AK		 4516 set_bit(__IXGBE_DOWN, &adapter->state);
4517
4518 return 0;
4519}
4520
4521/**
4522 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4523 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4524 *
4525 * Return 0 on success, negative on failure
4526 **/
b6ec895e 4527int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4528{
b6ec895e 4529 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4530 int orig_node = dev_to_node(dev);
4531 int numa_node = -1;
9a799d71
AK		 4532 int size;
4533
3a581073 4534 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4535
4536 if (tx_ring->q_vector)
4537 numa_node = tx_ring->q_vector->numa_node;
4538
4539 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4540 if (!tx_ring->tx_buffer_info)
89bf67f1 4541 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4542 if (!tx_ring->tx_buffer_info)
4543 goto err;
9a799d71
AK		 4544
4545 /* round up to nearest 4K */
12207e49 4546 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4547 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4548
de88eeeb
AD		 4549 set_dev_node(dev, numa_node);
4550 tx_ring->desc = dma_alloc_coherent(dev,
4551 tx_ring->size,
4552 &tx_ring->dma,
4553 GFP_KERNEL);
4554 set_dev_node(dev, orig_node);
4555 if (!tx_ring->desc)
4556 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4557 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4558 if (!tx_ring->desc)
4559 goto err;
9a799d71 4560
3a581073
JB		 4561 tx_ring->next_to_use = 0;
4562 tx_ring->next_to_clean = 0;
9a799d71 4563 return 0;
e01c31a5
JB		 4564
4565err:
4566 vfree(tx_ring->tx_buffer_info);
4567 tx_ring->tx_buffer_info = NULL;
b6ec895e 4568 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4569 return -ENOMEM;
9a799d71
AK		 4570}
4571
69888674
AD		 4572/**
4573 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4574 * @adapter: board private structure
4575 *
4576 * If this function returns with an error, then it's possible one or
4577 * more of the rings is populated (while the rest are not). It is the
4578 * callers duty to clean those orphaned rings.
4579 *
4580 * Return 0 on success, negative on failure
4581 **/
4582static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4583{
4584 int i, err = 0;
4585
4586 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4587 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4588 if (!err)
4589 continue;
de3d5b94 4590
396e799c 4591 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4592 goto err_setup_tx;
69888674
AD		 4593 }
4594
de3d5b94
AD		 4595 return 0;
4596err_setup_tx:
4597 /* rewind the index freeing the rings as we go */
4598 while (i--)
4599 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4600 return err;
4601}
4602
9a799d71
AK		 4603/**
4604 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4605 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4606 *
4607 * Returns 0 on success, negative on failure
4608 **/
b6ec895e 4609int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4610{
b6ec895e 4611 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4612 int orig_node = dev_to_node(dev);
4613 int numa_node = -1;
021230d4 4614 int size;
9a799d71 4615
3a581073 4616 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4617
4618 if (rx_ring->q_vector)
4619 numa_node = rx_ring->q_vector->numa_node;
4620
4621 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4622 if (!rx_ring->rx_buffer_info)
89bf67f1 4623 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4624 if (!rx_ring->rx_buffer_info)
4625 goto err;
9a799d71 4626
9a799d71 4627 /* Round up to nearest 4K */
3a581073
JB		 4628 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4629 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4630
de88eeeb
AD		 4631 set_dev_node(dev, numa_node);
4632 rx_ring->desc = dma_alloc_coherent(dev,
4633 rx_ring->size,
4634 &rx_ring->dma,
4635 GFP_KERNEL);
4636 set_dev_node(dev, orig_node);
4637 if (!rx_ring->desc)
4638 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4639 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4640 if (!rx_ring->desc)
4641 goto err;
9a799d71 4642
3a581073
JB		 4643 rx_ring->next_to_clean = 0;
4644 rx_ring->next_to_use = 0;
9a799d71 4645
f800326d
AD		 4646 ixgbe_init_rx_page_offset(rx_ring);
4647
9a799d71 4648 return 0;
b6ec895e
AD		 4649err:
4650 vfree(rx_ring->rx_buffer_info);
4651 rx_ring->rx_buffer_info = NULL;
4652 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4653 return -ENOMEM;
9a799d71
AK		 4654}
4655
69888674
AD		 4656/**
4657 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4658 * @adapter: board private structure
4659 *
4660 * If this function returns with an error, then it's possible one or
4661 * more of the rings is populated (while the rest are not). It is the
4662 * callers duty to clean those orphaned rings.
4663 *
4664 * Return 0 on success, negative on failure
4665 **/
69888674
AD		 4666static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4667{
4668 int i, err = 0;
4669
4670 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4671 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4672 if (!err)
4673 continue;
de3d5b94 4674
396e799c 4675 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4676 goto err_setup_rx;
69888674
AD		 4677 }
4678
7c8ae65a
AD		 4679#ifdef IXGBE_FCOE
4680 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4681 if (!err)
4682#endif
4683 return 0;
de3d5b94
AD		 4684err_setup_rx:
4685 /* rewind the index freeing the rings as we go */
4686 while (i--)
4687 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4688 return err;
4689}
4690
9a799d71
AK		 4691/**
4692 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4693 * @tx_ring: Tx descriptor ring for a specific queue
4694 *
4695 * Free all transmit software resources
4696 **/
b6ec895e 4697void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4698{
b6ec895e 4699 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4700
4701 vfree(tx_ring->tx_buffer_info);
4702 tx_ring->tx_buffer_info = NULL;
4703
b6ec895e
AD		 4704 /* if not set, then don't free */
4705 if (!tx_ring->desc)
4706 return;
4707
4708 dma_free_coherent(tx_ring->dev, tx_ring->size,
4709 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4710
4711 tx_ring->desc = NULL;
4712}
4713
4714/**
4715 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4716 * @adapter: board private structure
4717 *
4718 * Free all transmit software resources
4719 **/
4720static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4721{
4722 int i;
4723
4724 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4725 if (adapter->tx_ring[i]->desc)
b6ec895e 4726 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4727}
4728
4729/**
b4617240 4730 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4731 * @rx_ring: ring to clean the resources from
4732 *
4733 * Free all receive software resources
4734 **/
b6ec895e 4735void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4736{
b6ec895e 4737 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4738
4739 vfree(rx_ring->rx_buffer_info);
4740 rx_ring->rx_buffer_info = NULL;
4741
b6ec895e
AD		 4742 /* if not set, then don't free */
4743 if (!rx_ring->desc)
4744 return;
4745
4746 dma_free_coherent(rx_ring->dev, rx_ring->size,
4747 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4748
4749 rx_ring->desc = NULL;
4750}
4751
4752/**
4753 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4754 * @adapter: board private structure
4755 *
4756 * Free all receive software resources
4757 **/
4758static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4759{
4760 int i;
4761
7c8ae65a
AD		 4762#ifdef IXGBE_FCOE
4763 ixgbe_free_fcoe_ddp_resources(adapter);
4764
4765#endif
9a799d71 4766 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4767 if (adapter->rx_ring[i]->desc)
b6ec895e 4768 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4769}
4770
9a799d71
AK		 4771/**
4772 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4773 * @netdev: network interface device structure
4774 * @new_mtu: new value for maximum frame size
4775 *
4776 * Returns 0 on success, negative on failure
4777 **/
4778static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4779{
4780 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4781 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4782
42c783c5 4783 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4784 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4785 return -EINVAL;
4786
4787 /*
4788 * For 82599EB we cannot allow PF to change MTU greater than 1500
4789 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4790 * don't allocate and chain buffers correctly.
4791 */
4792 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4793 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4794 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4795 return -EINVAL;
9a799d71 4796
396e799c 4797 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4798
021230d4 4799 /* must set new MTU before calling down or up */
9a799d71
AK		 4800 netdev->mtu = new_mtu;
4801
d4f80882
AV		 4802 if (netif_running(netdev))
4803 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4804
4805 return 0;
4806}
4807
4808/**
4809 * ixgbe_open - Called when a network interface is made active
4810 * @netdev: network interface device structure
4811 *
4812 * Returns 0 on success, negative value on failure
4813 *
4814 * The open entry point is called when a network interface is made
4815 * active by the system (IFF_UP). At this point all resources needed
4816 * for transmit and receive operations are allocated, the interrupt
4817 * handler is registered with the OS, the watchdog timer is started,
4818 * and the stack is notified that the interface is ready.
4819 **/
4820static int ixgbe_open(struct net_device *netdev)
4821{
4822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4823 int err;
4bebfaa5
AK		 4824
4825 /* disallow open during test */
4826 if (test_bit(__IXGBE_TESTING, &adapter->state))
4827 return -EBUSY;
9a799d71 4828
54386467
JB		 4829 netif_carrier_off(netdev);
4830
9a799d71
AK		 4831 /* allocate transmit descriptors */
4832 err = ixgbe_setup_all_tx_resources(adapter);
4833 if (err)
4834 goto err_setup_tx;
4835
9a799d71
AK		 4836 /* allocate receive descriptors */
4837 err = ixgbe_setup_all_rx_resources(adapter);
4838 if (err)
4839 goto err_setup_rx;
4840
4841 ixgbe_configure(adapter);
4842
021230d4 4843 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4844 if (err)
4845 goto err_req_irq;
4846
ac802f5d
AD		 4847 /* Notify the stack of the actual queue counts. */
4848 err = netif_set_real_num_tx_queues(netdev,
4849 adapter->num_rx_pools > 1 ? 1 :
4850 adapter->num_tx_queues);
4851 if (err)
4852 goto err_set_queues;
4853
4854
4855 err = netif_set_real_num_rx_queues(netdev,
4856 adapter->num_rx_pools > 1 ? 1 :
4857 adapter->num_rx_queues);
4858 if (err)
4859 goto err_set_queues;
4860
c7ccde0f 4861 ixgbe_up_complete(adapter);
9a799d71
AK		 4862
4863 return 0;
4864
ac802f5d
AD		 4865err_set_queues:
4866 ixgbe_free_irq(adapter);
9a799d71 4867err_req_irq:
a20a1199 4868 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4869err_setup_rx:
a20a1199 4870 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4871err_setup_tx:
9a799d71
AK		 4872 ixgbe_reset(adapter);
4873
4874 return err;
4875}
4876
4877/**
4878 * ixgbe_close - Disables a network interface
4879 * @netdev: network interface device structure
4880 *
4881 * Returns 0, this is not allowed to fail
4882 *
4883 * The close entry point is called when an interface is de-activated
4884 * by the OS. The hardware is still under the drivers control, but
4885 * needs to be disabled. A global MAC reset is issued to stop the
4886 * hardware, and all transmit and receive resources are freed.
4887 **/
4888static int ixgbe_close(struct net_device *netdev)
4889{
4890 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4891
4892 ixgbe_down(adapter);
4893 ixgbe_free_irq(adapter);
4894
e4911d57
AD		 4895 ixgbe_fdir_filter_exit(adapter);
4896
9a799d71
AK		 4897 ixgbe_free_all_tx_resources(adapter);
4898 ixgbe_free_all_rx_resources(adapter);
4899
5eba3699 4900 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4901
4902 return 0;
4903}
4904
b3c8b4ba
AD		 4905#ifdef CONFIG_PM
4906static int ixgbe_resume(struct pci_dev *pdev)
4907{
c60fbb00
AD		 4908 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4909 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4910 u32 err;
4911
4912 pci_set_power_state(pdev, PCI_D0);
4913 pci_restore_state(pdev);
656ab817
DS		 4914 /*
4915 * pci_restore_state clears dev->state_saved so call
4916 * pci_save_state to restore it.
4917 */
4918 pci_save_state(pdev);
9ce77666 4919
4920 err = pci_enable_device_mem(pdev);
b3c8b4ba 4921 if (err) {
849c4542 4922 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4923 return err;
4924 }
4925 pci_set_master(pdev);
4926
dd4d8ca6 4927 pci_wake_from_d3(pdev, false);
b3c8b4ba 4928
b3c8b4ba
AD		 4929 ixgbe_reset(adapter);
4930
495dce12
WJP		 4931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4932
ac802f5d
AD		 4933 rtnl_lock();
4934 err = ixgbe_init_interrupt_scheme(adapter);
4935 if (!err && netif_running(netdev))
c60fbb00 4936 err = ixgbe_open(netdev);
ac802f5d
AD		 4937
4938 rtnl_unlock();
4939
4940 if (err)
4941 return err;
b3c8b4ba
AD		 4942
4943 netif_device_attach(netdev);
4944
4945 return 0;
4946}
b3c8b4ba 4947#endif /* CONFIG_PM */
9d8d05ae
RW		 4948
4949static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4950{
c60fbb00
AD		 4951 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4952 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4953 struct ixgbe_hw *hw = &adapter->hw;
4954 u32 ctrl, fctrl;
4955 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4956#ifdef CONFIG_PM
4957 int retval = 0;
4958#endif
4959
4960 netif_device_detach(netdev);
4961
4962 if (netif_running(netdev)) {
ab6039a7 4963 rtnl_lock();
b3c8b4ba
AD		 4964 ixgbe_down(adapter);
4965 ixgbe_free_irq(adapter);
4966 ixgbe_free_all_tx_resources(adapter);
4967 ixgbe_free_all_rx_resources(adapter);
ab6039a7 4968 rtnl_unlock();
b3c8b4ba 4969 }
b3c8b4ba 4970
5f5ae6fc
AD		 4971 ixgbe_clear_interrupt_scheme(adapter);
4972
b3c8b4ba
AD		 4973#ifdef CONFIG_PM
4974 retval = pci_save_state(pdev);
4975 if (retval)
4976 return retval;
4df10466 4977
b3c8b4ba 4978#endif
e8e26350
PW		 4979 if (wufc) {
4980 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4981
c509e754
DS		 4982 /*
4983 * enable the optics for both mult-speed fiber and
4984 * 82599 SFP+ fiber as we can WoL.
4985 */
4986 if (hw->mac.ops.enable_tx_laser &&
4987 (hw->phy.multispeed_fiber ||
4988 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4989 hw->mac.type == ixgbe_mac_82599EB)))
4990 hw->mac.ops.enable_tx_laser(hw);
4991
e8e26350
PW		 4992 /* turn on all-multi mode if wake on multicast is enabled */
4993 if (wufc & IXGBE_WUFC_MC) {
4994 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4995 fctrl |= IXGBE_FCTRL_MPE;
4996 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4997 }
4998
4999 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5000 ctrl |= IXGBE_CTRL_GIO_DIS;
5001 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5002
5003 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5004 } else {
5005 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5006 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5007 }
5008
bd508178
AD		 5009 switch (hw->mac.type) {
5010 case ixgbe_mac_82598EB:
dd4d8ca6 5011 pci_wake_from_d3(pdev, false);
bd508178
AD		 5012 break;
5013 case ixgbe_mac_82599EB:
b93a2226 5014 case ixgbe_mac_X540:
bd508178
AD		 5015 pci_wake_from_d3(pdev, !!wufc);
5016 break;
5017 default:
5018 break;
5019 }
b3c8b4ba 5020
9d8d05ae
RW		 5021 *enable_wake = !!wufc;
5022
b3c8b4ba
AD		 5023 ixgbe_release_hw_control(adapter);
5024
5025 pci_disable_device(pdev);
5026
9d8d05ae
RW		 5027 return 0;
5028}
5029
5030#ifdef CONFIG_PM
5031static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5032{
5033 int retval;
5034 bool wake;
5035
5036 retval = __ixgbe_shutdown(pdev, &wake);
5037 if (retval)
5038 return retval;
5039
5040 if (wake) {
5041 pci_prepare_to_sleep(pdev);
5042 } else {
5043 pci_wake_from_d3(pdev, false);
5044 pci_set_power_state(pdev, PCI_D3hot);
5045 }
b3c8b4ba
AD		 5046
5047 return 0;
5048}
9d8d05ae 5049#endif /* CONFIG_PM */
b3c8b4ba
AD		 5050
5051static void ixgbe_shutdown(struct pci_dev *pdev)
5052{
9d8d05ae
RW		 5053 bool wake;
5054
5055 __ixgbe_shutdown(pdev, &wake);
5056
5057 if (system_state == SYSTEM_POWER_OFF) {
5058 pci_wake_from_d3(pdev, wake);
5059 pci_set_power_state(pdev, PCI_D3hot);
5060 }
b3c8b4ba
AD		 5061}
5062
9a799d71
AK		 5063/**
5064 * ixgbe_update_stats - Update the board statistics counters.
5065 * @adapter: board private structure
5066 **/
5067void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5068{
2d86f139 5069 struct net_device *netdev = adapter->netdev;
9a799d71 5070 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5071 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5072 u64 total_mpc = 0;
5073 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5074 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5075 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5076 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5077
d08935c2
DS		 5078 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5079 test_bit(__IXGBE_RESETTING, &adapter->state))
5080 return;
5081
94b982b2 5082 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5083 u64 rsc_count = 0;
94b982b2 5084 u64 rsc_flush = 0;
94b982b2 5085 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5086 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5087 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5088 }
5089 adapter->rsc_total_count = rsc_count;
5090 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5091 }
5092
5b7da515
AD		 5093 for (i = 0; i < adapter->num_rx_queues; i++) {
5094 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5095 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5096 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5097 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5098 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5099 bytes += rx_ring->stats.bytes;
5100 packets += rx_ring->stats.packets;
5101 }
5102 adapter->non_eop_descs = non_eop_descs;
5103 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5104 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5105 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5106 netdev->stats.rx_bytes = bytes;
5107 netdev->stats.rx_packets = packets;
5108
5109 bytes = 0;
5110 packets = 0;
7ca3bc58 5111 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5112 for (i = 0; i < adapter->num_tx_queues; i++) {
5113 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5114 restart_queue += tx_ring->tx_stats.restart_queue;
5115 tx_busy += tx_ring->tx_stats.tx_busy;
5116 bytes += tx_ring->stats.bytes;
5117 packets += tx_ring->stats.packets;
5118 }
eb985f09 5119 adapter->restart_queue = restart_queue;
5b7da515
AD		 5120 adapter->tx_busy = tx_busy;
5121 netdev->stats.tx_bytes = bytes;
5122 netdev->stats.tx_packets = packets;
7ca3bc58 5123
7ca647bd 5124 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5125
5126 /* 8 register reads */
6f11eef7
AV		 5127 for (i = 0; i < 8; i++) {
5128 /* for packet buffers not used, the register should read 0 */
5129 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5130 missed_rx += mpc;
7ca647bd
JP		 5131 hwstats->mpc[i] += mpc;
5132 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5133 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5134 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5135 switch (hw->mac.type) {
5136 case ixgbe_mac_82598EB:
1a70db4b
ET		 5137 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5138 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5139 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5140 hwstats->pxonrxc[i] +=
5141 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5142 break;
5143 case ixgbe_mac_82599EB:
b93a2226 5144 case ixgbe_mac_X540:
bd508178
AD		 5145 hwstats->pxonrxc[i] +=
5146 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5147 break;
5148 default:
5149 break;
e8e26350 5150 }
6f11eef7 5151 }
1a70db4b
ET		 5152
5153 /*16 register reads */
5154 for (i = 0; i < 16; i++) {
5155 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5156 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5157 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5158 (hw->mac.type == ixgbe_mac_X540)) {
5159 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5160 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5161 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5162 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5163 }
5164 }
5165
7ca647bd 5166 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5167 /* work around hardware counting issue */
7ca647bd 5168 hwstats->gprc -= missed_rx;
6f11eef7 5169
c84d324c
JF		 5170 ixgbe_update_xoff_received(adapter);
5171
6f11eef7 5172 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5173 switch (hw->mac.type) {
5174 case ixgbe_mac_82598EB:
5175 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5176 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5177 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5178 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5179 break;
b93a2226 5180 case ixgbe_mac_X540:
58f6bcf9
ET		 5181 /* OS2BMC stats are X540 only*/
5182 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5183 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5184 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5185 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5186 case ixgbe_mac_82599EB:
a4d4f629
AD		 5187 for (i = 0; i < 16; i++)
5188 adapter->hw_rx_no_dma_resources +=
5189 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5190 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5191 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5192 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5193 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5194 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5195 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5196 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5197 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5198 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5199#ifdef IXGBE_FCOE
7ca647bd
JP		 5200 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5201 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5202 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5203 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5204 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5205 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5206 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5207 if (adapter->fcoe.ddp_pool) {
5208 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5209 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5210 unsigned int cpu;
5211 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5212 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5213 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5214 noddp += ddp_pool->noddp;
5215 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5216 }
5a1ee270
AD		 5217 hwstats->fcoe_noddp = noddp;
5218 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5219 }
6d45522c 5220#endif /* IXGBE_FCOE */
bd508178
AD		 5221 break;
5222 default:
5223 break;
e8e26350 5224 }
9a799d71 5225 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5226 hwstats->bprc += bprc;
5227 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5228 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5229 hwstats->mprc -= bprc;
5230 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5231 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5232 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5233 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5234 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5235 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5236 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5237 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5238 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5239 hwstats->lxontxc += lxon;
6f11eef7 5240 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5241 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5242 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5243 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5244 /*
5245 * 82598 errata - tx of flow control packets is included in tx counters
5246 */
5247 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5248 hwstats->gptc -= xon_off_tot;
5249 hwstats->mptc -= xon_off_tot;
5250 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5251 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5252 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5253 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5254 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5255 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5256 hwstats->ptc64 -= xon_off_tot;
5257 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5258 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5259 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5260 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5261 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5262 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5263
5264 /* Fill out the OS statistics structure */
7ca647bd 5265 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5266
5267 /* Rx Errors */
7ca647bd 5268 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5269 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5270 netdev->stats.rx_length_errors = hwstats->rlec;
5271 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5272 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5273}
5274
5275/**
d034acf1 5276 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5277 * @adapter: pointer to the device adapter structure
9a799d71 5278 **/
d034acf1 5279static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5280{
cf8280ee 5281 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5282 int i;
cf8280ee 5283
d034acf1
AD		 5284 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5285 return;
5286
5287 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5288
d034acf1 5289 /* if interface is down do nothing */
fe49f04a 5290 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5291 return;
5292
5293 /* do nothing if we are not using signature filters */
5294 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5295 return;
5296
5297 adapter->fdir_overflow++;
5298
93c52dd0
AD		 5299 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5300 for (i = 0; i < adapter->num_tx_queues; i++)
5301 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5302 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5303 /* re-enable flow director interrupts */
5304 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5305 } else {
5306 e_err(probe, "failed to finish FDIR re-initialization, "
5307 "ignored adding FDIR ATR filters\n");
5308 }
93c52dd0
AD		 5309}
5310
5311/**
5312 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5313 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5314 *
5315 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5316 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5317 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5318 * determine if a hang has occurred.
93c52dd0
AD		 5319 */
5320static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5321{
cf8280ee 5322 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5323 u64 eics = 0;
5324 int i;
cf8280ee 5325
93c52dd0
AD		 5326 /* If we're down or resetting, just bail */
5327 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5328 test_bit(__IXGBE_RESETTING, &adapter->state))
5329 return;
22d5a71b 5330
93c52dd0
AD		 5331 /* Force detection of hung controller */
5332 if (netif_carrier_ok(adapter->netdev)) {
5333 for (i = 0; i < adapter->num_tx_queues; i++)
5334 set_check_for_tx_hang(adapter->tx_ring[i]);
5335 }
22d5a71b 5336
fe49f04a
AD		 5337 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5338 /*
5339 * for legacy and MSI interrupts don't set any bits
5340 * that are enabled for EIAM, because this operation
5341 * would set *both* EIMS and EICS for any bit in EIAM
5342 */
5343 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5344 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5345 } else {
5346 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5347 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5348 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5349 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5350 eics |= ((u64)1 << i);
5351 }
cf8280ee 5352 }
9a799d71 5353
93c52dd0 5354 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5355 ixgbe_irq_rearm_queues(adapter, eics);
5356
cf8280ee
JB		 5357}
5358
e8e26350 5359/**
93c52dd0 5360 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5361 * @adapter: pointer to the device adapter structure
5362 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5363 **/
93c52dd0 5364static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5365{
e8e26350 5366 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5367 u32 link_speed = adapter->link_speed;
5368 bool link_up = adapter->link_up;
041441d0 5369 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5370
93c52dd0
AD		 5371 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5372 return;
5373
5374 if (hw->mac.ops.check_link) {
5375 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5376 } else {
93c52dd0
AD		 5377 /* always assume link is up, if no check link function */
5378 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5379 link_up = true;
c4cf55e5 5380 }
041441d0
AD		 5381
5382 if (adapter->ixgbe_ieee_pfc)
5383 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5384
3ebe8fde 5385 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5386 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5387 ixgbe_set_rx_drop_en(adapter);
5388 }
93c52dd0
AD		 5389
5390 if (link_up ||
5391 time_after(jiffies, (adapter->link_check_timeout +
5392 IXGBE_TRY_LINK_TIMEOUT))) {
5393 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5394 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5395 IXGBE_WRITE_FLUSH(hw);
5396 }
5397
5398 adapter->link_up = link_up;
5399 adapter->link_speed = link_speed;
e8e26350
PW		 5400}
5401
5402/**
93c52dd0
AD		 5403 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5404 * print link up message
49ce9c2c 5405 * @adapter: pointer to the device adapter structure
e8e26350 5406 **/
93c52dd0 5407static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5408{
93c52dd0 5409 struct net_device *netdev = adapter->netdev;
e8e26350 5410 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5411 u32 link_speed = adapter->link_speed;
5412 bool flow_rx, flow_tx;
e8e26350 5413
93c52dd0
AD		 5414 /* only continue if link was previously down */
5415 if (netif_carrier_ok(netdev))
a985b6c3 5416 return;
63d6e1d8 5417
93c52dd0 5418 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5419
93c52dd0
AD		 5420 switch (hw->mac.type) {
5421 case ixgbe_mac_82598EB: {
5422 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5423 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5424 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5425 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5426 }
5427 break;
5428 case ixgbe_mac_X540:
5429 case ixgbe_mac_82599EB: {
5430 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5431 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5432 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5433 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5434 }
5435 break;
5436 default:
5437 flow_tx = false;
5438 flow_rx = false;
5439 break;
e8e26350 5440 }
3a6a4eda
JK		 5441
5442#ifdef CONFIG_IXGBE_PTP
5443 ixgbe_ptp_start_cyclecounter(adapter);
5444#endif
5445
93c52dd0
AD		 5446 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5447 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5448 "10 Gbps" :
5449 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5450 "1 Gbps" :
5451 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5452 "100 Mbps" :
5453 "unknown speed"))),
5454 ((flow_rx && flow_tx) ? "RX/TX" :
5455 (flow_rx ? "RX" :
5456 (flow_tx ? "TX" : "None"))));
e8e26350 5457
93c52dd0 5458 netif_carrier_on(netdev);
93c52dd0 5459 ixgbe_check_vf_rate_limit(adapter);
befa2af7
AD		 5460
5461 /* ping all the active vfs to let them know link has changed */
5462 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5463}
5464
c4cf55e5 5465/**
93c52dd0
AD		 5466 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5467 * print link down message
49ce9c2c 5468 * @adapter: pointer to the adapter structure
c4cf55e5 5469 **/
581330ba 5470static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5471{
cf8280ee 5472 struct net_device *netdev = adapter->netdev;
c4cf55e5 5473 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5474
93c52dd0
AD		 5475 adapter->link_up = false;
5476 adapter->link_speed = 0;
cf8280ee 5477
93c52dd0
AD		 5478 /* only continue if link was up previously */
5479 if (!netif_carrier_ok(netdev))
5480 return;
264857b8 5481
93c52dd0
AD		 5482 /* poll for SFP+ cable when link is down */
5483 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5484 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5485
3a6a4eda
JK		 5486#ifdef CONFIG_IXGBE_PTP
5487 ixgbe_ptp_start_cyclecounter(adapter);
5488#endif
5489
93c52dd0
AD		 5490 e_info(drv, "NIC Link is Down\n");
5491 netif_carrier_off(netdev);
befa2af7
AD		 5492
5493 /* ping all the active vfs to let them know link has changed */
5494 ixgbe_ping_all_vfs(adapter);
93c52dd0 5495}
e8e26350 5496
93c52dd0
AD		 5497/**
5498 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5499 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5500 **/
5501static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5502{
c4cf55e5 5503 int i;
93c52dd0 5504 int some_tx_pending = 0;
c4cf55e5 5505
93c52dd0 5506 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5507 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5508 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5509 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5510 some_tx_pending = 1;
5511 break;
5512 }
5513 }
5514
5515 if (some_tx_pending) {
5516 /* We've lost link, so the controller stops DMA,
5517 * but we've got queued Tx work that's never going
5518 * to get done, so reset controller to flush Tx.
5519 * (Do the reset outside of interrupt context).
5520 */
c83c6cbd 5521 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5522 }
c4cf55e5 5523 }
c4cf55e5
PWJ		 5524}
5525
a985b6c3
GR		 5526static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5527{
5528 u32 ssvpc;
5529
5530 /* Do not perform spoof check for 82598 */
5531 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5532 return;
5533
5534 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5535
5536 /*
5537 * ssvpc register is cleared on read, if zero then no
5538 * spoofed packets in the last interval.
5539 */
5540 if (!ssvpc)
5541 return;
5542
5543 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5544}
5545
93c52dd0
AD		 5546/**
5547 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5548 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5549 **/
5550static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5551{
5552 /* if interface is down do nothing */
7edebf9a
ET		 5553 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5554 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5555 return;
5556
5557 ixgbe_watchdog_update_link(adapter);
5558
5559 if (adapter->link_up)
5560 ixgbe_watchdog_link_is_up(adapter);
5561 else
5562 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5563
a985b6c3 5564 ixgbe_spoof_check(adapter);
9a799d71 5565 ixgbe_update_stats(adapter);
93c52dd0
AD		 5566
5567 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5568}
10eec955 5569
cf8280ee 5570/**
7086400d 5571 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5572 * @adapter: the ixgbe adapter structure
cf8280ee 5573 **/
7086400d 5574static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5575{
cf8280ee 5576 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5577 s32 err;
cf8280ee 5578
7086400d
AD		 5579 /* not searching for SFP so there is nothing to do here */
5580 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5581 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5582 return;
10eec955 5583
7086400d
AD		 5584 /* someone else is in init, wait until next service event */
5585 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5586 return;
cf8280ee 5587
7086400d
AD		 5588 err = hw->phy.ops.identify_sfp(hw);
5589 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5590 goto sfp_out;
264857b8 5591
7086400d
AD		 5592 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5593 /* If no cable is present, then we need to reset
5594 * the next time we find a good cable. */
5595 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5596 }
9a799d71 5597
7086400d
AD		 5598 /* exit on error */
5599 if (err)
5600 goto sfp_out;
e8e26350 5601
7086400d
AD		 5602 /* exit if reset not needed */
5603 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5604 goto sfp_out;
9a799d71 5605
7086400d 5606 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5607
7086400d
AD		 5608 /*
5609 * A module may be identified correctly, but the EEPROM may not have
5610 * support for that module. setup_sfp() will fail in that case, so
5611 * we should not allow that module to load.
5612 */
5613 if (hw->mac.type == ixgbe_mac_82598EB)
5614 err = hw->phy.ops.reset(hw);
5615 else
5616 err = hw->mac.ops.setup_sfp(hw);
5617
5618 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5619 goto sfp_out;
5620
5621 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5622 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5623
5624sfp_out:
5625 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5626
5627 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5628 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5629 e_dev_err("failed to initialize because an unsupported "
5630 "SFP+ module type was detected.\n");
5631 e_dev_err("Reload the driver after installing a "
5632 "supported module.\n");
5633 unregister_netdev(adapter->netdev);
bc59fcda 5634 }
7086400d 5635}
bc59fcda 5636
7086400d
AD		 5637/**
5638 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5639 * @adapter: the ixgbe adapter structure
7086400d
AD		 5640 **/
5641static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5642{
5643 struct ixgbe_hw *hw = &adapter->hw;
5644 u32 autoneg;
5645 bool negotiation;
5646
5647 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5648 return;
5649
5650 /* someone else is in init, wait until next service event */
5651 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5652 return;
5653
5654 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5655
5656 autoneg = hw->phy.autoneg_advertised;
5657 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5658 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5659 if (hw->mac.ops.setup_link)
5660 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5661
5662 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5663 adapter->link_check_timeout = jiffies;
5664 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5665}
5666
83c61fa9
GR		 5667#ifdef CONFIG_PCI_IOV
5668static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5669{
5670 int vf;
5671 struct ixgbe_hw *hw = &adapter->hw;
5672 struct net_device *netdev = adapter->netdev;
5673 u32 gpc;
5674 u32 ciaa, ciad;
5675
5676 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5677 if (gpc) /* If incrementing then no need for the check below */
5678 return;
5679 /*
5680 * Check to see if a bad DMA write target from an errant or
5681 * malicious VF has caused a PCIe error. If so then we can
5682 * issue a VFLR to the offending VF(s) and then resume without
5683 * requesting a full slot reset.
5684 */
5685
5686 for (vf = 0; vf < adapter->num_vfs; vf++) {
5687 ciaa = (vf << 16) | 0x80000000;
5688 /* 32 bit read so align, we really want status at offset 6 */
5689 ciaa |= PCI_COMMAND;
5690 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5691 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5692 ciaa &= 0x7FFFFFFF;
5693 /* disable debug mode asap after reading data */
5694 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5695 /* Get the upper 16 bits which will be the PCI status reg */
5696 ciad >>= 16;
5697 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5698 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5699 /* Issue VFLR */
5700 ciaa = (vf << 16) | 0x80000000;
5701 ciaa |= 0xA8;
5702 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5703 ciad = 0x00008000; /* VFLR */
5704 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5705 ciaa &= 0x7FFFFFFF;
5706 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5707 }
5708 }
5709}
5710
5711#endif
7086400d
AD		 5712/**
5713 * ixgbe_service_timer - Timer Call-back
5714 * @data: pointer to adapter cast into an unsigned long
5715 **/
5716static void ixgbe_service_timer(unsigned long data)
5717{
5718 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5719 unsigned long next_event_offset;
83c61fa9 5720 bool ready = true;
7086400d 5721
6bb78cfb
AD		 5722 /* poll faster when waiting for link */
5723 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5724 next_event_offset = HZ / 10;
5725 else
5726 next_event_offset = HZ * 2;
83c61fa9 5727
6bb78cfb 5728#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5729 /*
5730 * don't bother with SR-IOV VF DMA hang check if there are
5731 * no VFs or the link is down
5732 */
5733 if (!adapter->num_vfs ||
6bb78cfb 5734 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5735 goto normal_timer_service;
83c61fa9
GR		 5736
5737 /* If we have VFs allocated then we must check for DMA hangs */
5738 ixgbe_check_for_bad_vf(adapter);
5739 next_event_offset = HZ / 50;
5740 adapter->timer_event_accumulator++;
5741
6bb78cfb 5742 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5743 adapter->timer_event_accumulator = 0;
7086400d 5744 else
6bb78cfb 5745 ready = false;
7086400d 5746
6bb78cfb 5747normal_timer_service:
83c61fa9 5748#endif
7086400d
AD		 5749 /* Reset the timer */
5750 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5751
83c61fa9
GR		 5752 if (ready)
5753 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5754}
5755
c83c6cbd
AD		 5756static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5757{
5758 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5759 return;
5760
5761 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5762
5763 /* If we're already down or resetting, just bail */
5764 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5765 test_bit(__IXGBE_RESETTING, &adapter->state))
5766 return;
5767
5768 ixgbe_dump(adapter);
5769 netdev_err(adapter->netdev, "Reset adapter\n");
5770 adapter->tx_timeout_count++;
5771
5772 ixgbe_reinit_locked(adapter);
5773}
5774
7086400d
AD		 5775/**
5776 * ixgbe_service_task - manages and runs subtasks
5777 * @work: pointer to work_struct containing our data
5778 **/
5779static void ixgbe_service_task(struct work_struct *work)
5780{
5781 struct ixgbe_adapter *adapter = container_of(work,
5782 struct ixgbe_adapter,
5783 service_task);
5784
c83c6cbd 5785 ixgbe_reset_subtask(adapter);
7086400d
AD		 5786 ixgbe_sfp_detection_subtask(adapter);
5787 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5788 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5789 ixgbe_watchdog_subtask(adapter);
d034acf1 5790 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5791 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5792#ifdef CONFIG_IXGBE_PTP
5793 ixgbe_ptp_overflow_check(adapter);
5794#endif
7086400d
AD		 5795
5796 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5797}
5798
fd0db0ed
AD		 5799static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5800 struct ixgbe_tx_buffer *first,
244e27ad 5801 u8 *hdr_len)
897ab156 5802{
fd0db0ed 5803 struct sk_buff *skb = first->skb;
897ab156
AD		 5804 u32 vlan_macip_lens, type_tucmd;
5805 u32 mss_l4len_idx, l4len;
9a799d71 5806
897ab156
AD		 5807 if (!skb_is_gso(skb))
5808 return 0;
9a799d71 5809
897ab156 5810 if (skb_header_cloned(skb)) {
244e27ad 5811 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5812 if (err)
5813 return err;
9a799d71 5814 }
9a799d71 5815
897ab156
AD		 5816 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5817 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5818
244e27ad 5819 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5820 struct iphdr *iph = ip_hdr(skb);
5821 iph->tot_len = 0;
5822 iph->check = 0;
5823 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5824 iph->daddr, 0,
5825 IPPROTO_TCP,
5826 0);
5827 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5828 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5829 IXGBE_TX_FLAGS_CSUM |
5830 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5831 } else if (skb_is_gso_v6(skb)) {
5832 ipv6_hdr(skb)->payload_len = 0;
5833 tcp_hdr(skb)->check =
5834 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5835 &ipv6_hdr(skb)->daddr,
5836 0, IPPROTO_TCP, 0);
244e27ad
AD		 5837 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5838 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5839 }
5840
091a6246 5841 /* compute header lengths */
897ab156
AD		 5842 l4len = tcp_hdrlen(skb);
5843 *hdr_len = skb_transport_offset(skb) + l4len;
5844
091a6246
AD		 5845 /* update gso size and bytecount with header size */
5846 first->gso_segs = skb_shinfo(skb)->gso_segs;
5847 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5848
897ab156
AD		 5849 /* mss_l4len_id: use 1 as index for TSO */
5850 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5851 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5852 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5853
5854 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5855 vlan_macip_lens = skb_network_header_len(skb);
5856 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5857 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5858
5859 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5860 mss_l4len_idx);
897ab156
AD		 5861
5862 return 1;
5863}
5864
244e27ad
AD		 5865static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5866 struct ixgbe_tx_buffer *first)
7ca647bd 5867{
fd0db0ed 5868 struct sk_buff *skb = first->skb;
897ab156
AD		 5869 u32 vlan_macip_lens = 0;
5870 u32 mss_l4len_idx = 0;
5871 u32 type_tucmd = 0;
7ca647bd 5872
897ab156 5873 if (skb->ip_summed != CHECKSUM_PARTIAL) {
244e27ad
AD		 5874 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5875 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5876 return;
897ab156
AD		 5877 } else {
5878 u8 l4_hdr = 0;
244e27ad 5879 switch (first->protocol) {
897ab156
AD		 5880 case __constant_htons(ETH_P_IP):
5881 vlan_macip_lens |= skb_network_header_len(skb);
5882 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5883 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5884 break;
897ab156
AD		 5885 case __constant_htons(ETH_P_IPV6):
5886 vlan_macip_lens |= skb_network_header_len(skb);
5887 l4_hdr = ipv6_hdr(skb)->nexthdr;
5888 break;
5889 default:
5890 if (unlikely(net_ratelimit())) {
5891 dev_warn(tx_ring->dev,
5892 "partial checksum but proto=%x!\n",
244e27ad 5893 first->protocol);
897ab156 5894 }
7ca647bd
JP		 5895 break;
5896 }
897ab156
AD		 5897
5898 switch (l4_hdr) {
7ca647bd 5899 case IPPROTO_TCP:
897ab156
AD		 5900 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5901 mss_l4len_idx = tcp_hdrlen(skb) <<
5902 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5903 break;
5904 case IPPROTO_SCTP:
897ab156
AD		 5905 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5906 mss_l4len_idx = sizeof(struct sctphdr) <<
5907 IXGBE_ADVTXD_L4LEN_SHIFT;
5908 break;
5909 case IPPROTO_UDP:
5910 mss_l4len_idx = sizeof(struct udphdr) <<
5911 IXGBE_ADVTXD_L4LEN_SHIFT;
5912 break;
5913 default:
5914 if (unlikely(net_ratelimit())) {
5915 dev_warn(tx_ring->dev,
5916 "partial checksum but l4 proto=%x!\n",
244e27ad 5917 l4_hdr);
897ab156 5918 }
7ca647bd
JP		 5919 break;
5920 }
244e27ad
AD		 5921
5922 /* update TX checksum flag */
5923 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5924 }
5925
244e27ad 5926 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5927 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5928 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5929
897ab156
AD		 5930 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5931 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5932}
5933
d3d00239 5934static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5935{
d3d00239
AD		 5936 /* set type for advanced descriptor with frame checksum insertion */
5937 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5938 IXGBE_ADVTXD_DCMD_IFCS |
5939 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5940
d3d00239 5941 /* set HW vlan bit if vlan is present */
66f32a8b 5942 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5943 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5944
3a6a4eda
JK		 5945#ifdef CONFIG_IXGBE_PTP
5946 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5947 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5948#endif
5949
d3d00239
AD		 5950 /* set segmentation enable bits for TSO/FSO */
5951#ifdef IXGBE_FCOE
93f5b3c1 5952 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5953#else
5954 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5955#endif
5956 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5957
d3d00239
AD		 5958 return cmd_type;
5959}
9a799d71 5960
729739b7
AD		 5961static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5962 u32 tx_flags, unsigned int paylen)
d3d00239 5963{
93f5b3c1 5964 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 5965
d3d00239
AD		 5966 /* enable L4 checksum for TSO and TX checksum offload */
5967 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5968 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 5969
93f5b3c1
AD		 5970 /* enble IPv4 checksum for TSO */
5971 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5972 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 5973
93f5b3c1
AD		 5974 /* use index 1 context for TSO/FSO/FCOE */
5975#ifdef IXGBE_FCOE
5976 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5977#else
5978 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 5979#endif
93f5b3c1
AD		 5980 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5981
7f9643fd
AD		 5982 /*
5983 * Check Context must be set if Tx switch is enabled, which it
5984 * always is for case where virtual functions are running
5985 */
93f5b3c1
AD		 5986#ifdef IXGBE_FCOE
5987 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5988#else
7f9643fd 5989 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 5990#endif
7f9643fd
AD		 5991 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5992
729739b7 5993 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 5994}
44df32c5 5995
d3d00239
AD		 5996#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5997 IXGBE_TXD_CMD_RS)
5998
5999static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6000 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6001 const u8 hdr_len)
6002{
729739b7 6003 dma_addr_t dma;
fd0db0ed 6004 struct sk_buff *skb = first->skb;
729739b7 6005 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6006 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6007 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6008 unsigned int data_len = skb->data_len;
6009 unsigned int size = skb_headlen(skb);
729739b7 6010 unsigned int paylen = skb->len - hdr_len;
244e27ad 6011 u32 tx_flags = first->tx_flags;
729739b7 6012 __le32 cmd_type;
d3d00239 6013 u16 i = tx_ring->next_to_use;
d3d00239 6014
729739b7
AD		 6015 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6016
6017 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6018 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6019
d3d00239
AD		 6020#ifdef IXGBE_FCOE
6021 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6022 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6023 size -= sizeof(struct fcoe_crc_eof) - data_len;
6024 data_len = 0;
729739b7
AD		 6025 } else {
6026 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6027 }
6028 }
44df32c5 6029
d3d00239 6030#endif
729739b7
AD		 6031 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6032 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6033 goto dma_error;
8ad494b0 6034
729739b7
AD		 6035 /* record length, and DMA address */
6036 dma_unmap_len_set(first, len, size);
6037 dma_unmap_addr_set(first, dma, dma);
9a799d71 6038
729739b7 6039 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6040
d3d00239 6041 for (;;) {
729739b7 6042 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6043 tx_desc->read.cmd_type_len =
6044 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6045
d3d00239 6046 i++;
729739b7 6047 tx_desc++;
d3d00239 6048 if (i == tx_ring->count) {
e4f74028 6049 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6050 i = 0;
6051 }
729739b7
AD		 6052
6053 dma += IXGBE_MAX_DATA_PER_TXD;
6054 size -= IXGBE_MAX_DATA_PER_TXD;
6055
6056 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6057 tx_desc->read.olinfo_status = 0;
d3d00239 6058 }
e5a43549 6059
729739b7
AD		 6060 if (likely(!data_len))
6061 break;
9a799d71 6062
f43f313e
BG		 6063 if (unlikely(skb->no_fcs))
6064 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239 6065 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6066
729739b7
AD		 6067 i++;
6068 tx_desc++;
6069 if (i == tx_ring->count) {
6070 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6071 i = 0;
6072 }
9a799d71 6073
d3d00239 6074#ifdef IXGBE_FCOE
9e903e08 6075 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6076#else
9e903e08 6077 size = skb_frag_size(frag);
d3d00239
AD		 6078#endif
6079 data_len -= size;
9a799d71 6080
729739b7
AD		 6081 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6082 DMA_TO_DEVICE);
6083 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6084 goto dma_error;
9a799d71 6085
729739b7
AD		 6086 tx_buffer = &tx_ring->tx_buffer_info[i];
6087 dma_unmap_len_set(tx_buffer, len, size);
6088 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6089
729739b7
AD		 6090 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6091 tx_desc->read.olinfo_status = 0;
9a799d71 6092
729739b7
AD		 6093 frag++;
6094 }
9a799d71 6095
729739b7
AD		 6096 /* write last descriptor with RS and EOP bits */
6097 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6098 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6099
091a6246 6100 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6101
d3d00239
AD		 6102 /* set the timestamp */
6103 first->time_stamp = jiffies;
9a799d71
AK		 6104
6105 /*
729739b7
AD		 6106 * Force memory writes to complete before letting h/w know there
6107 * are new descriptors to fetch. (Only applicable for weak-ordered
6108 * memory model archs, such as IA-64).
6109 *
6110 * We also need this memory barrier to make certain all of the
6111 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6112 */
6113 wmb();
6114
d3d00239
AD		 6115 /* set next_to_watch value indicating a packet is present */
6116 first->next_to_watch = tx_desc;
6117
729739b7
AD		 6118 i++;
6119 if (i == tx_ring->count)
6120 i = 0;
6121
6122 tx_ring->next_to_use = i;
6123
d3d00239 6124 /* notify HW of packet */
84ea2591 6125 writel(i, tx_ring->tail);
d3d00239
AD		 6126
6127 return;
6128dma_error:
729739b7 6129 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6130
6131 /* clear dma mappings for failed tx_buffer_info map */
6132 for (;;) {
729739b7
AD		 6133 tx_buffer = &tx_ring->tx_buffer_info[i];
6134 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6135 if (tx_buffer == first)
d3d00239
AD		 6136 break;
6137 if (i == 0)
6138 i = tx_ring->count;
6139 i--;
6140 }
6141
d3d00239 6142 tx_ring->next_to_use = i;
9a799d71
AK		 6143}
6144
fd0db0ed 6145static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6146 struct ixgbe_tx_buffer *first)
69830529
AD		 6147{
6148 struct ixgbe_q_vector *q_vector = ring->q_vector;
6149 union ixgbe_atr_hash_dword input = { .dword = 0 };
6150 union ixgbe_atr_hash_dword common = { .dword = 0 };
6151 union {
6152 unsigned char *network;
6153 struct iphdr *ipv4;
6154 struct ipv6hdr *ipv6;
6155 } hdr;
ee9e0f0b 6156 struct tcphdr *th;
905e4a41 6157 __be16 vlan_id;
c4cf55e5 6158
69830529
AD		 6159 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6160 if (!q_vector)
6161 return;
6162
6163 /* do nothing if sampling is disabled */
6164 if (!ring->atr_sample_rate)
d3ead241 6165 return;
c4cf55e5 6166
69830529 6167 ring->atr_count++;
c4cf55e5 6168
69830529 6169 /* snag network header to get L4 type and address */
fd0db0ed 6170 hdr.network = skb_network_header(first->skb);
69830529
AD		 6171
6172 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6173 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6174 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6175 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6176 hdr.ipv4->protocol != IPPROTO_TCP))
6177 return;
ee9e0f0b 6178
fd0db0ed 6179 th = tcp_hdr(first->skb);
c4cf55e5 6180
66f32a8b
AD		 6181 /* skip this packet since it is invalid or the socket is closing */
6182 if (!th || th->fin)
69830529
AD		 6183 return;
6184
6185 /* sample on all syn packets or once every atr sample count */
6186 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6187 return;
6188
6189 /* reset sample count */
6190 ring->atr_count = 0;
6191
244e27ad 6192 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6193
6194 /*
6195 * src and dst are inverted, think how the receiver sees them
6196 *
6197 * The input is broken into two sections, a non-compressed section
6198 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6199 * is XORed together and stored in the compressed dword.
6200 */
6201 input.formatted.vlan_id = vlan_id;
6202
6203 /*
6204 * since src port and flex bytes occupy the same word XOR them together
6205 * and write the value to source port portion of compressed dword
6206 */
244e27ad 6207 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6208 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6209 else
244e27ad 6210 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6211 common.port.dst ^= th->source;
6212
244e27ad 6213 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6214 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6215 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6216 } else {
6217 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6218 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6219 hdr.ipv6->saddr.s6_addr32[1] ^
6220 hdr.ipv6->saddr.s6_addr32[2] ^
6221 hdr.ipv6->saddr.s6_addr32[3] ^
6222 hdr.ipv6->daddr.s6_addr32[0] ^
6223 hdr.ipv6->daddr.s6_addr32[1] ^
6224 hdr.ipv6->daddr.s6_addr32[2] ^
6225 hdr.ipv6->daddr.s6_addr32[3];
6226 }
c4cf55e5
PWJ		 6227
6228 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6229 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6230 input, common, ring->queue_index);
c4cf55e5
PWJ		 6231}
6232
63544e9c 6233static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6234{
fc77dc3c 6235 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6236 /* Herbert's original patch had:
6237 * smp_mb__after_netif_stop_queue();
6238 * but since that doesn't exist yet, just open code it. */
6239 smp_mb();
6240
6241 /* We need to check again in a case another CPU has just
6242 * made room available. */
7d4987de 6243 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6244 return -EBUSY;
6245
6246 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6247 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6248 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6249 return 0;
6250}
6251
82d4e46e 6252static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6253{
7d4987de 6254 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6255 return 0;
fc77dc3c 6256 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6257}
6258
09a3b1f8
SH		 6259static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6260{
6261 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6262 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6263 smp_processor_id();
56075a98 6264#ifdef IXGBE_FCOE
6440752c 6265 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6266
e5b64635
JF		 6267 if (((protocol == htons(ETH_P_FCOE)) ||
6268 (protocol == htons(ETH_P_FIP))) &&
6269 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6270 struct ixgbe_ring_feature *f;
6271
6272 f = &adapter->ring_feature[RING_F_FCOE];
6273
6274 while (txq >= f->indices)
6275 txq -= f->indices;
e4b317e9 6276 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6277
e5b64635 6278 return txq;
56075a98
JF		 6279 }
6280#endif
6281
fdd3d631
KK		 6282 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6283 while (unlikely(txq >= dev->real_num_tx_queues))
6284 txq -= dev->real_num_tx_queues;
5f715823 6285 return txq;
fdd3d631 6286 }
c4cf55e5 6287
09a3b1f8
SH		 6288 return skb_tx_hash(dev, skb);
6289}
6290
fc77dc3c 6291netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6292 struct ixgbe_adapter *adapter,
6293 struct ixgbe_ring *tx_ring)
9a799d71 6294{
d3d00239 6295 struct ixgbe_tx_buffer *first;
5f715823 6296 int tso;
d3d00239 6297 u32 tx_flags = 0;
a535c30e
AD		 6298#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6299 unsigned short f;
6300#endif
a535c30e 6301 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6302 __be16 protocol = skb->protocol;
63544e9c 6303 u8 hdr_len = 0;
5e09a105 6304
a535c30e
AD		 6305 /*
6306 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6307 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6308 * + 2 desc gap to keep tail from touching head,
6309 * + 1 desc for context descriptor,
6310 * otherwise try next time
6311 */
6312#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6313 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6314 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6315#else
6316 count += skb_shinfo(skb)->nr_frags;
6317#endif
6318 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6319 tx_ring->tx_stats.tx_busy++;
6320 return NETDEV_TX_BUSY;
6321 }
6322
fd0db0ed
AD		 6323 /* record the location of the first descriptor for this packet */
6324 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6325 first->skb = skb;
091a6246
AD		 6326 first->bytecount = skb->len;
6327 first->gso_segs = 1;
fd0db0ed 6328
66f32a8b 6329 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6330 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6331 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6332 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6333 /* else if it is a SW VLAN check the next protocol and store the tag */
6334 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6335 struct vlan_hdr *vhdr, _vhdr;
6336 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6337 if (!vhdr)
6338 goto out_drop;
6339
6340 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6341 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6342 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6343 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6344 }
6345
aa7bd467
JK		 6346 skb_tx_timestamp(skb);
6347
3a6a4eda
JK		 6348#ifdef CONFIG_IXGBE_PTP
6349 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6350 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6351 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6352 }
6353#endif
6354
9e0c5648
AD		 6355#ifdef CONFIG_PCI_IOV
6356 /*
6357 * Use the l2switch_enable flag - would be false if the DMA
6358 * Tx switch had been disabled.
6359 */
6360 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6361 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6362
6363#endif
32701dc2 6364 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6365 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6366 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6367 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6368 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6369 tx_flags |= (skb->priority & 0x7) <<
6370 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6371 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6372 struct vlan_ethhdr *vhdr;
6373 if (skb_header_cloned(skb) &&
6374 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6375 goto out_drop;
6376 vhdr = (struct vlan_ethhdr *)skb->data;
6377 vhdr->h_vlan_TCI = htons(tx_flags >>
6378 IXGBE_TX_FLAGS_VLAN_SHIFT);
6379 } else {
6380 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6381 }
9a799d71 6382 }
eacd73f7 6383
244e27ad
AD		 6384 /* record initial flags and protocol */
6385 first->tx_flags = tx_flags;
6386 first->protocol = protocol;
6387
eacd73f7 6388#ifdef IXGBE_FCOE
66f32a8b
AD		 6389 /* setup tx offload for FCoE */
6390 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6391 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6392 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6393 if (tso < 0)
6394 goto out_drop;
9a799d71 6395
66f32a8b 6396 goto xmit_fcoe;
eacd73f7 6397 }
9a799d71 6398
66f32a8b 6399#endif /* IXGBE_FCOE */
244e27ad 6400 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6401 if (tso < 0)
897ab156 6402 goto out_drop;
244e27ad
AD		 6403 else if (!tso)
6404 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6405
6406 /* add the ATR filter if ATR is on */
6407 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6408 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6409
6410#ifdef IXGBE_FCOE
6411xmit_fcoe:
6412#endif /* IXGBE_FCOE */
244e27ad 6413 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6414
6415 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6416
6417 return NETDEV_TX_OK;
897ab156
AD		 6418
6419out_drop:
fd0db0ed
AD		 6420 dev_kfree_skb_any(first->skb);
6421 first->skb = NULL;
6422
897ab156 6423 return NETDEV_TX_OK;
9a799d71
AK		 6424}
6425
a50c29dd
AD		 6426static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6427 struct net_device *netdev)
84418e3b
AD		 6428{
6429 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6430 struct ixgbe_ring *tx_ring;
6431
a50c29dd
AD		 6432 /*
6433 * The minimum packet size for olinfo paylen is 17 so pad the skb
6434 * in order to meet this minimum size requirement.
6435 */
f73332fc
SH		 6436 if (unlikely(skb->len < 17)) {
6437 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6438 return NETDEV_TX_OK;
6439 skb->len = 17;
6440 }
6441
84418e3b 6442 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6443 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6444}
6445
9a799d71
AK		 6446/**
6447 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6448 * @netdev: network interface device structure
6449 * @p: pointer to an address structure
6450 *
6451 * Returns 0 on success, negative on failure
6452 **/
6453static int ixgbe_set_mac(struct net_device *netdev, void *p)
6454{
6455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6456 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6457 struct sockaddr *addr = p;
6458
6459 if (!is_valid_ether_addr(addr->sa_data))
6460 return -EADDRNOTAVAIL;
6461
6462 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6463 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6464
1d9c0bfd 6465 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6466
6467 return 0;
6468}
6469
6b73e10d
BH		 6470static int
6471ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6472{
6473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6474 struct ixgbe_hw *hw = &adapter->hw;
6475 u16 value;
6476 int rc;
6477
6478 if (prtad != hw->phy.mdio.prtad)
6479 return -EINVAL;
6480 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6481 if (!rc)
6482 rc = value;
6483 return rc;
6484}
6485
6486static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6487 u16 addr, u16 value)
6488{
6489 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6490 struct ixgbe_hw *hw = &adapter->hw;
6491
6492 if (prtad != hw->phy.mdio.prtad)
6493 return -EINVAL;
6494 return hw->phy.ops.write_reg(hw, addr, devad, value);
6495}
6496
6497static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6498{
6499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6500
3a6a4eda
JK		 6501 switch (cmd) {
6502#ifdef CONFIG_IXGBE_PTP
6503 case SIOCSHWTSTAMP:
6504 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6505#endif
6506 default:
6507 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6508 }
6b73e10d
BH		 6509}
6510
0365e6e4
PW		 6511/**
6512 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6513 * netdev->dev_addrs
0365e6e4
PW		 6514 * @netdev: network interface device structure
6515 *
6516 * Returns non-zero on failure
6517 **/
6518static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6519{
6520 int err = 0;
6521 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6522 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6523
7fa7c9dc 6524 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6525 rtnl_lock();
7fa7c9dc 6526 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6527 rtnl_unlock();
7fa7c9dc
AD		 6528
6529 /* update SAN MAC vmdq pool selection */
6530 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6531 }
6532 return err;
6533}
6534
6535/**
6536 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6537 * netdev->dev_addrs
0365e6e4
PW		 6538 * @netdev: network interface device structure
6539 *
6540 * Returns non-zero on failure
6541 **/
6542static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6543{
6544 int err = 0;
6545 struct ixgbe_adapter *adapter = netdev_priv(dev);
6546 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6547
6548 if (is_valid_ether_addr(mac->san_addr)) {
6549 rtnl_lock();
6550 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6551 rtnl_unlock();
6552 }
6553 return err;
6554}
6555
9a799d71
AK		 6556#ifdef CONFIG_NET_POLL_CONTROLLER
6557/*
6558 * Polling 'interrupt' - used by things like netconsole to send skbs
6559 * without having to re-enable interrupts. It's not called while
6560 * the interrupt routine is executing.
6561 */
6562static void ixgbe_netpoll(struct net_device *netdev)
6563{
6564 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6565 int i;
9a799d71 6566
1a647bd2
AD		 6567 /* if interface is down do nothing */
6568 if (test_bit(__IXGBE_DOWN, &adapter->state))
6569 return;
6570
9a799d71 6571 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6572 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6573 for (i = 0; i < adapter->num_q_vectors; i++)
6574 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6575 } else {
6576 ixgbe_intr(adapter->pdev->irq, netdev);
6577 }
9a799d71 6578 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6579}
9a799d71 6580
581330ba 6581#endif
de1036b1
ED		 6582static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6583 struct rtnl_link_stats64 *stats)
6584{
6585 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6586 int i;
6587
1a51502b 6588 rcu_read_lock();
de1036b1 6589 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6590 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6591 u64 bytes, packets;
6592 unsigned int start;
6593
1a51502b
ED		 6594 if (ring) {
6595 do {
6596 start = u64_stats_fetch_begin_bh(&ring->syncp);
6597 packets = ring->stats.packets;
6598 bytes = ring->stats.bytes;
6599 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6600 stats->rx_packets += packets;
6601 stats->rx_bytes += bytes;
6602 }
de1036b1 6603 }
1ac9ad13
ED		 6604
6605 for (i = 0; i < adapter->num_tx_queues; i++) {
6606 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6607 u64 bytes, packets;
6608 unsigned int start;
6609
6610 if (ring) {
6611 do {
6612 start = u64_stats_fetch_begin_bh(&ring->syncp);
6613 packets = ring->stats.packets;
6614 bytes = ring->stats.bytes;
6615 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6616 stats->tx_packets += packets;
6617 stats->tx_bytes += bytes;
6618 }
6619 }
1a51502b 6620 rcu_read_unlock();
de1036b1
ED		 6621 /* following stats updated by ixgbe_watchdog_task() */
6622 stats->multicast = netdev->stats.multicast;
6623 stats->rx_errors = netdev->stats.rx_errors;
6624 stats->rx_length_errors = netdev->stats.rx_length_errors;
6625 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6626 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6627 return stats;
6628}
6629
8af3c33f 6630#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6631/**
6632 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6633 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6634 * @tc: number of traffic classes currently enabled
6635 *
6636 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6637 * 802.1Q priority maps to a packet buffer that exists.
6638 */
6639static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6640{
6641 struct ixgbe_hw *hw = &adapter->hw;
6642 u32 reg, rsave;
6643 int i;
6644
6645 /* 82598 have a static priority to TC mapping that can not
6646 * be changed so no validation is needed.
6647 */
6648 if (hw->mac.type == ixgbe_mac_82598EB)
6649 return;
6650
6651 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6652 rsave = reg;
6653
6654 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6655 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6656
6657 /* If up2tc is out of bounds default to zero */
6658 if (up2tc > tc)
6659 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6660 }
6661
6662 if (reg != rsave)
6663 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6664
6665 return;
6666}
6667
02debdc9
AD		 6668/**
6669 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6670 * @adapter: Pointer to adapter struct
6671 *
6672 * Populate the netdev user priority to tc map
6673 */
6674static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6675{
6676 struct net_device *dev = adapter->netdev;
6677 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6678 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6679 u8 prio;
6680
6681 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6682 u8 tc = 0;
6683
6684 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6685 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6686 else if (ets)
6687 tc = ets->prio_tc[prio];
6688
6689 netdev_set_prio_tc_map(dev, prio, tc);
6690 }
6691}
6692
49ce9c2c
BH		 6693/**
6694 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6695 *
6696 * @netdev: net device to configure
6697 * @tc: number of traffic classes to enable
6698 */
6699int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6700{
8b1c0b24
JF		 6701 struct ixgbe_adapter *adapter = netdev_priv(dev);
6702 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6703
e7589eab
JF		 6704 /* Multiple traffic classes requires multiple queues */
6705 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6706 e_err(drv, "Enable failed, needs MSI-X\n");
6707 return -EINVAL;
6708 }
8b1c0b24
JF		 6709
6710 /* Hardware supports up to 8 traffic classes */
4de2a022 6711 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6712 (hw->mac.type == ixgbe_mac_82598EB &&
6713 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6714 return -EINVAL;
6715
6716 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6717 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6718 * hardware is not flexible enough to do this dynamically.
6719 */
6720 if (netif_running(dev))
6721 ixgbe_close(dev);
6722 ixgbe_clear_interrupt_scheme(adapter);
6723
e7589eab 6724 if (tc) {
8b1c0b24 6725 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6726 ixgbe_set_prio_tc_map(adapter);
6727
e7589eab
JF		 6728 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6729 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6730
943561d3
AD		 6731 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6732 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6733 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6734 }
e7589eab 6735 } else {
8b1c0b24 6736 netdev_reset_tc(dev);
02debdc9 6737
943561d3
AD		 6738 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6739 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6740
6741 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6742 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6743
6744 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6745 adapter->dcb_cfg.pfc_mode_enable = false;
6746 }
6747
8b1c0b24
JF		 6748 ixgbe_init_interrupt_scheme(adapter);
6749 ixgbe_validate_rtr(adapter, tc);
6750 if (netif_running(dev))
6751 ixgbe_open(dev);
6752
6753 return 0;
6754}
de1036b1 6755
8af3c33f 6756#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6757void ixgbe_do_reset(struct net_device *netdev)
6758{
6759 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6760
6761 if (netif_running(netdev))
6762 ixgbe_reinit_locked(adapter);
6763 else
6764 ixgbe_reset(adapter);
6765}
6766
c8f44aff 6767static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6768 netdev_features_t features)
082757af
DS		 6769{
6770 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6771
082757af 6772 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6773 if (!(features & NETIF_F_RXCSUM))
6774 features &= ~NETIF_F_LRO;
082757af 6775
567d2de2
AD		 6776 /* Turn off LRO if not RSC capable */
6777 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6778 features &= ~NETIF_F_LRO;
8e2813f5 6779
567d2de2 6780 return features;
082757af
DS		 6781}
6782
c8f44aff 6783static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6784 netdev_features_t features)
082757af
DS		 6785{
6786 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6787 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6788 bool need_reset = false;
6789
082757af 6790 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6791 if (!(features & NETIF_F_LRO)) {
6792 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6793 need_reset = true;
567d2de2
AD		 6794 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6795 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6796 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6797 if (adapter->rx_itr_setting == 1 ||
6798 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6799 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6800 need_reset = true;
6801 } else if ((changed ^ features) & NETIF_F_LRO) {
6802 e_info(probe, "rx-usecs set too low, "
6803 "disabling RSC\n");
082757af
DS		 6804 }
6805 }
6806
6807 /*
6808 * Check if Flow Director n-tuple support was enabled or disabled. If
6809 * the state changed, we need to reset.
6810 */
567d2de2
AD		 6811 if (!(features & NETIF_F_NTUPLE)) {
6812 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6813 /* turn off Flow Director, set ATR and reset */
fbe7ca7f 6814 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
567d2de2
AD		 6815 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6816 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 6817 need_reset = true;
6818 }
082757af 6819 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
567d2de2
AD		 6820 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6821 /* turn off ATR, enable perfect filters and reset */
6822 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6823 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
082757af
DS		 6824 need_reset = true;
6825 }
6826
146d4cc9
JF		 6827 if (features & NETIF_F_HW_VLAN_RX)
6828 ixgbe_vlan_strip_enable(adapter);
6829 else
6830 ixgbe_vlan_strip_disable(adapter);
6831
3f2d1c0f
BG		 6832 if (changed & NETIF_F_RXALL)
6833 need_reset = true;
6834
567d2de2 6835 netdev->features = features;
082757af
DS		 6836 if (need_reset)
6837 ixgbe_do_reset(netdev);
6838
6839 return 0;
082757af
DS		 6840}
6841
0f4b0add
JF		 6842static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6843 struct net_device *dev,
6844 unsigned char *addr,
6845 u16 flags)
6846{
6847 struct ixgbe_adapter *adapter = netdev_priv(dev);
6848 int err = -EOPNOTSUPP;
6849
6850 if (ndm->ndm_state & NUD_PERMANENT) {
6851 pr_info("%s: FDB only supports static addresses\n",
6852 ixgbe_driver_name);
6853 return -EINVAL;
6854 }
6855
6856 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6857 if (is_unicast_ether_addr(addr))
6858 err = dev_uc_add_excl(dev, addr);
6859 else if (is_multicast_ether_addr(addr))
6860 err = dev_mc_add_excl(dev, addr);
6861 else
6862 err = -EINVAL;
6863 }
6864
6865 /* Only return duplicate errors if NLM_F_EXCL is set */
6866 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6867 err = 0;
6868
6869 return err;
6870}
6871
6872static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6873 struct net_device *dev,
6874 unsigned char *addr)
6875{
6876 struct ixgbe_adapter *adapter = netdev_priv(dev);
6877 int err = -EOPNOTSUPP;
6878
6879 if (ndm->ndm_state & NUD_PERMANENT) {
6880 pr_info("%s: FDB only supports static addresses\n",
6881 ixgbe_driver_name);
6882 return -EINVAL;
6883 }
6884
6885 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6886 if (is_unicast_ether_addr(addr))
6887 err = dev_uc_del(dev, addr);
6888 else if (is_multicast_ether_addr(addr))
6889 err = dev_mc_del(dev, addr);
6890 else
6891 err = -EINVAL;
6892 }
6893
6894 return err;
6895}
6896
6897static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6898 struct netlink_callback *cb,
6899 struct net_device *dev,
6900 int idx)
6901{
6902 struct ixgbe_adapter *adapter = netdev_priv(dev);
6903
6904 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6905 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6906
6907 return idx;
6908}
6909
0edc3527 6910static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6911 .ndo_open = ixgbe_open,
0edc3527 6912 .ndo_stop = ixgbe_close,
00829823 6913 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6914 .ndo_select_queue = ixgbe_select_queue,
581330ba 6915 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6916 .ndo_validate_addr = eth_validate_addr,
6917 .ndo_set_mac_address = ixgbe_set_mac,
6918 .ndo_change_mtu = ixgbe_change_mtu,
6919 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6920 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6921 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6922 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6923 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6924 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6925 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6926 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6927 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6928 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6929#ifdef CONFIG_IXGBE_DCB
24095aa3 6930 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6931#endif
0edc3527
SH		 6932#ifdef CONFIG_NET_POLL_CONTROLLER
6933 .ndo_poll_controller = ixgbe_netpoll,
6934#endif
332d4a7d
YZ		 6935#ifdef IXGBE_FCOE
6936 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6937 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6938 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6939 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6940 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6941 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6942 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6943#endif /* IXGBE_FCOE */
082757af
DS		 6944 .ndo_set_features = ixgbe_set_features,
6945 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 6946 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6947 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6948 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 6949};
6950
8e2813f5
JK		 6951/**
6952 * ixgbe_wol_supported - Check whether device supports WoL
6953 * @hw: hw specific details
6954 * @device_id: the device ID
6955 * @subdev_id: the subsystem device ID
6956 *
6957 * This function is used by probe and ethtool to determine
6958 * which devices have WoL support
6959 *
6960 **/
6961int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6962 u16 subdevice_id)
6963{
6964 struct ixgbe_hw *hw = &adapter->hw;
6965 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6966 int is_wol_supported = 0;
6967
6968 switch (device_id) {
6969 case IXGBE_DEV_ID_82599_SFP:
6970 /* Only these subdevices could supports WOL */
6971 switch (subdevice_id) {
6972 case IXGBE_SUBDEV_ID_82599_560FLR:
6973 /* only support first port */
6974 if (hw->bus.func != 0)
6975 break;
6976 case IXGBE_SUBDEV_ID_82599_SFP:
6977 is_wol_supported = 1;
6978 break;
6979 }
6980 break;
6981 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
6982 /* All except this subdevice support WOL */
6983 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
6984 is_wol_supported = 1;
6985 break;
6986 case IXGBE_DEV_ID_82599_KX4:
6987 is_wol_supported = 1;
6988 break;
6989 case IXGBE_DEV_ID_X540T:
6990 /* check eeprom to see if enabled wol */
6991 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
6992 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
6993 (hw->bus.func == 0))) {
6994 is_wol_supported = 1;
6995 }
6996 break;
6997 }
6998
6999 return is_wol_supported;
7000}
7001
9a799d71
AK		 7002/**
7003 * ixgbe_probe - Device Initialization Routine
7004 * @pdev: PCI device information struct
7005 * @ent: entry in ixgbe_pci_tbl
7006 *
7007 * Returns 0 on success, negative on failure
7008 *
7009 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7010 * The OS initialization, configuring of the adapter private structure,
7011 * and a hardware reset occur.
7012 **/
7013static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7014 const struct pci_device_id *ent)
9a799d71
AK		 7015{
7016 struct net_device *netdev;
7017 struct ixgbe_adapter *adapter = NULL;
7018 struct ixgbe_hw *hw;
7019 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7020 static int cards_found;
7021 int i, err, pci_using_dac;
289700db 7022 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7023 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7024#ifdef IXGBE_FCOE
7025 u16 device_caps;
7026#endif
289700db 7027 u32 eec;
9a799d71 7028
bded64a7
AG		 7029 /* Catch broken hardware that put the wrong VF device ID in
7030 * the PCIe SR-IOV capability.
7031 */
7032 if (pdev->is_virtfn) {
7033 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7034 pci_name(pdev), pdev->vendor, pdev->device);
7035 return -EINVAL;
7036 }
7037
9ce77666 7038 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7039 if (err)
7040 return err;
7041
1b507730
NN		 7042 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7043 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7044 pci_using_dac = 1;
7045 } else {
1b507730 7046 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7047 if (err) {
1b507730
NN		 7048 err = dma_set_coherent_mask(&pdev->dev,
7049 DMA_BIT_MASK(32));
9a799d71 7050 if (err) {
b8bc0421
DC		 7051 dev_err(&pdev->dev,
7052 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7053 goto err_dma;
7054 }
7055 }
7056 pci_using_dac = 0;
7057 }
7058
9ce77666 7059 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7060 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7061 if (err) {
b8bc0421
DC		 7062 dev_err(&pdev->dev,
7063 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7064 goto err_pci_reg;
7065 }
7066
19d5afd4 7067 pci_enable_pcie_error_reporting(pdev);
6fabd715 7068
9a799d71 7069 pci_set_master(pdev);
fb3b27bc 7070 pci_save_state(pdev);
9a799d71 7071
e901acd6
JF		 7072#ifdef CONFIG_IXGBE_DCB
7073 indices *= MAX_TRAFFIC_CLASS;
7074#endif
7075
c85a2618 7076 if (ii->mac == ixgbe_mac_82598EB)
d411a936
AD		 7077#ifdef CONFIG_IXGBE_DCB
7078 indices = min_t(unsigned int, indices, MAX_TRAFFIC_CLASS * 4);
7079#else
c85a2618 7080 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
d411a936 7081#endif
c85a2618
JF		 7082 else
7083 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7084
e901acd6 7085#ifdef IXGBE_FCOE
c85a2618
JF		 7086 indices += min_t(unsigned int, num_possible_cpus(),
7087 IXGBE_MAX_FCOE_INDICES);
7088#endif
c85a2618 7089 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7090 if (!netdev) {
7091 err = -ENOMEM;
7092 goto err_alloc_etherdev;
7093 }
7094
9a799d71
AK		 7095 SET_NETDEV_DEV(netdev, &pdev->dev);
7096
9a799d71 7097 adapter = netdev_priv(netdev);
c60fbb00 7098 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7099
7100 adapter->netdev = netdev;
7101 adapter->pdev = pdev;
7102 hw = &adapter->hw;
7103 hw->back = adapter;
b3f4d599 7104 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7105
05857980 7106 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7107 pci_resource_len(pdev, 0));
9a799d71
AK		 7108 if (!hw->hw_addr) {
7109 err = -EIO;
7110 goto err_ioremap;
7111 }
7112
7113 for (i = 1; i <= 5; i++) {
7114 if (pci_resource_len(pdev, i) == 0)
7115 continue;
7116 }
7117
0edc3527 7118 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7119 ixgbe_set_ethtool_ops(netdev);
9a799d71 7120 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7121 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7122
9a799d71
AK		 7123 adapter->bd_number = cards_found;
7124
9a799d71
AK		 7125 /* Setup hw api */
7126 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7127 hw->mac.type = ii->mac;
9a799d71 7128
c44ade9e
JB		 7129 /* EEPROM */
7130 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7131 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7132 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7133 if (!(eec & (1 << 8)))
7134 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7135
7136 /* PHY */
7137 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7138 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7139 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7140 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7141 hw->phy.mdio.mmds = 0;
7142 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7143 hw->phy.mdio.dev = netdev;
7144 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7145 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7146
8ca783ab 7147 ii->get_invariants(hw);
9a799d71
AK		 7148
7149 /* setup the private structure */
7150 err = ixgbe_sw_init(adapter);
7151 if (err)
7152 goto err_sw_init;
7153
e86bff0e 7154 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7155 switch (adapter->hw.mac.type) {
7156 case ixgbe_mac_82599EB:
7157 case ixgbe_mac_X540:
e86bff0e 7158 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7159 break;
7160 default:
7161 break;
7162 }
e86bff0e 7163
bf069c97
DS		 7164 /*
7165 * If there is a fan on this device and it has failed log the
7166 * failure.
7167 */
7168 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7169 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7170 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7171 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7172 }
7173
8ef78adc
PWJ		 7174 if (allow_unsupported_sfp)
7175 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7176
c44ade9e 7177 /* reset_hw fills in the perm_addr as well */
119fc60a 7178 hw->phy.reset_if_overtemp = true;
c44ade9e 7179 err = hw->mac.ops.reset_hw(hw);
119fc60a 7180 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7181 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7182 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7183 err = 0;
7184 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7185 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7186 "module type was detected.\n");
7187 e_dev_err("Reload the driver after installing a supported "
7188 "module.\n");
04f165ef
PW		 7189 goto err_sw_init;
7190 } else if (err) {
849c4542 7191 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7192 goto err_sw_init;
7193 }
7194
99d74487
AD		 7195#ifdef CONFIG_PCI_IOV
7196 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7197
99d74487 7198#endif
396e799c 7199 netdev->features = NETIF_F_SG |
e8e9f696 7200 NETIF_F_IP_CSUM |
082757af 7201 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7202 NETIF_F_HW_VLAN_TX |
7203 NETIF_F_HW_VLAN_RX |
082757af
DS		 7204 NETIF_F_HW_VLAN_FILTER |
7205 NETIF_F_TSO |
7206 NETIF_F_TSO6 |
082757af
DS		 7207 NETIF_F_RXHASH |
7208 NETIF_F_RXCSUM;
9a799d71 7209
082757af 7210 netdev->hw_features = netdev->features;
ad31c402 7211
58be7666
DS		 7212 switch (adapter->hw.mac.type) {
7213 case ixgbe_mac_82599EB:
7214 case ixgbe_mac_X540:
45a5ead0 7215 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7216 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7217 NETIF_F_NTUPLE;
58be7666
DS		 7218 break;
7219 default:
7220 break;
7221 }
45a5ead0 7222
3f2d1c0f
BG		 7223 netdev->hw_features |= NETIF_F_RXALL;
7224
ad31c402
JK		 7225 netdev->vlan_features |= NETIF_F_TSO;
7226 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7227 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7228 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7229 netdev->vlan_features |= NETIF_F_SG;
7230
01789349 7231 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7232 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7233
7a6b6f51 7234#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7235 netdev->dcbnl_ops = &dcbnl_ops;
7236#endif
7237
eacd73f7 7238#ifdef IXGBE_FCOE
0d551589 7239 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7240 if (hw->mac.ops.get_device_caps) {
7241 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7242 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7243 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7244 }
7c8ae65a
AD		 7245
7246 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7247
a58915c7
AD		 7248 netdev->features |= NETIF_F_FSO |
7249 NETIF_F_FCOE_CRC;
7250
7c8ae65a
AD		 7251 netdev->vlan_features |= NETIF_F_FSO |
7252 NETIF_F_FCOE_CRC |
7253 NETIF_F_FCOE_MTU;
5e09d7f6 7254 }
eacd73f7 7255#endif /* IXGBE_FCOE */
7b872a55 7256 if (pci_using_dac) {
9a799d71 7257 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7258 netdev->vlan_features |= NETIF_F_HIGHDMA;
7259 }
9a799d71 7260
082757af
DS		 7261 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7262 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7263 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7264 netdev->features |= NETIF_F_LRO;
7265
9a799d71 7266 /* make sure the EEPROM is good */
c44ade9e 7267 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7268 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7269 err = -EIO;
35937c05 7270 goto err_sw_init;
9a799d71
AK		 7271 }
7272
7273 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7274 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7275
c44ade9e 7276 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7277 e_dev_err("invalid MAC address\n");
9a799d71 7278 err = -EIO;
35937c05 7279 goto err_sw_init;
9a799d71
AK		 7280 }
7281
7086400d 7282 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7283 (unsigned long) adapter);
9a799d71 7284
7086400d
AD		 7285 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7286 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7287
021230d4
AV		 7288 err = ixgbe_init_interrupt_scheme(adapter);
7289 if (err)
7290 goto err_sw_init;
9a799d71 7291
8e2813f5 7292 /* WOL not supported for all devices */
c23f5b6b 7293 adapter->wol = 0;
8e2813f5
JK		 7294 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7295 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7296 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7297
e8e26350
PW		 7298 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7299
3a6a4eda
JK		 7300#ifdef CONFIG_IXGBE_PTP
7301 ixgbe_ptp_init(adapter);
7302#endif /* CONFIG_IXGBE_PTP*/
7303
15e5209f
ET		 7304 /* save off EEPROM version number */
7305 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7306 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7307
04f165ef
PW		 7308 /* pick up the PCI bus settings for reporting later */
7309 hw->mac.ops.get_bus_info(hw);
7310
9a799d71 7311 /* print bus type/speed/width info */
849c4542 7312 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7313 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7314 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7315 "Unknown"),
7316 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7317 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7318 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7319 "Unknown"),
7320 netdev->dev_addr);
289700db
DS		 7321
7322 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7323 if (err)
9fe93afd 7324 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7325 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7326 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7327 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7328 part_str);
e8e26350 7329 else
289700db
DS		 7330 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7331 hw->mac.type, hw->phy.type, part_str);
9a799d71 7332
e8e26350 7333 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7334 e_dev_warn("PCI-Express bandwidth available for this card is "
7335 "not sufficient for optimal performance.\n");
7336 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7337 "is required.\n");
0c254d86
AK		 7338 }
7339
9a799d71 7340 /* reset the hardware with the new settings */
794caeb2 7341 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7342 if (err == IXGBE_ERR_EEPROM_VERSION) {
7343 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7344 e_dev_warn("This device is a pre-production adapter/LOM. "
7345 "Please be aware there may be issues associated "
7346 "with your hardware. If you are experiencing "
7347 "problems please contact your Intel or hardware "
7348 "representative who provided you with this "
7349 "hardware.\n");
794caeb2 7350 }
9a799d71
AK		 7351 strcpy(netdev->name, "eth%d");
7352 err = register_netdev(netdev);
7353 if (err)
7354 goto err_register;
7355
93d3ce8f
ET		 7356 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7357 if (hw->mac.ops.disable_tx_laser &&
7358 ((hw->phy.multispeed_fiber) ||
7359 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7360 (hw->mac.type == ixgbe_mac_82599EB))))
7361 hw->mac.ops.disable_tx_laser(hw);
7362
54386467
JB		 7363 /* carrier off reporting is important to ethtool even BEFORE open */
7364 netif_carrier_off(netdev);
7365
5dd2d332 7366#ifdef CONFIG_IXGBE_DCA
652f093f 7367 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7368 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7369 ixgbe_setup_dca(adapter);
7370 }
7371#endif
1cdd1ec8 7372 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7373 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7374 for (i = 0; i < adapter->num_vfs; i++)
7375 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7376 }
7377
2466dd9c
JK		 7378 /* firmware requires driver version to be 0xFFFFFFFF
7379 * since os does not support feature
7380 */
9612de92 7381 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7382 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7383 0xFF);
9612de92 7384
0365e6e4
PW		 7385 /* add san mac addr to netdev */
7386 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7387
ea81875a 7388 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7389 cards_found++;
3ca8bc6d 7390
1210982b 7391#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7392 if (ixgbe_sysfs_init(adapter))
7393 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7394#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7395
9a799d71
AK		 7396 return 0;
7397
7398err_register:
5eba3699 7399 ixgbe_release_hw_control(adapter);
7a921c93 7400 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7401err_sw_init:
99d74487 7402 ixgbe_disable_sriov(adapter);
7086400d 7403 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7404 iounmap(hw->hw_addr);
7405err_ioremap:
7406 free_netdev(netdev);
7407err_alloc_etherdev:
e8e9f696
JP		 7408 pci_release_selected_regions(pdev,
7409 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7410err_pci_reg:
7411err_dma:
7412 pci_disable_device(pdev);
7413 return err;
7414}
7415
7416/**
7417 * ixgbe_remove - Device Removal Routine
7418 * @pdev: PCI device information struct
7419 *
7420 * ixgbe_remove is called by the PCI subsystem to alert the driver
7421 * that it should release a PCI device. The could be caused by a
7422 * Hot-Plug event, or because the driver is going to be removed from
7423 * memory.
7424 **/
7425static void __devexit ixgbe_remove(struct pci_dev *pdev)
7426{
c60fbb00
AD		 7427 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7428 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7429
7430 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7431 cancel_work_sync(&adapter->service_task);
9a799d71 7432
3a6a4eda
JK		 7433#ifdef CONFIG_IXGBE_PTP
7434 ixgbe_ptp_stop(adapter);
7435#endif
7436
5dd2d332 7437#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7438 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7439 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7440 dca_remove_requester(&pdev->dev);
7441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7442 }
7443
7444#endif
1210982b 7445#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7446 ixgbe_sysfs_exit(adapter);
1210982b 7447#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7448
0365e6e4
PW		 7449 /* remove the added san mac */
7450 ixgbe_del_sanmac_netdev(netdev);
7451
c4900be0
DS		 7452 if (netdev->reg_state == NETREG_REGISTERED)
7453 unregister_netdev(netdev);
9a799d71 7454
9297127b 7455 ixgbe_disable_sriov(adapter);
1cdd1ec8 7456
7a921c93 7457 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7458
021230d4 7459 ixgbe_release_hw_control(adapter);
9a799d71 7460
2b1588c3
AD		 7461#ifdef CONFIG_DCB
7462 kfree(adapter->ixgbe_ieee_pfc);
7463 kfree(adapter->ixgbe_ieee_ets);
7464
7465#endif
9a799d71 7466 iounmap(adapter->hw.hw_addr);
9ce77666 7467 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7468 IORESOURCE_MEM));
9a799d71 7469
849c4542 7470 e_dev_info("complete\n");
021230d4 7471
9a799d71
AK		 7472 free_netdev(netdev);
7473
19d5afd4 7474 pci_disable_pcie_error_reporting(pdev);
6fabd715 7475
9a799d71
AK		 7476 pci_disable_device(pdev);
7477}
7478
7479/**
7480 * ixgbe_io_error_detected - called when PCI error is detected
7481 * @pdev: Pointer to PCI device
7482 * @state: The current pci connection state
7483 *
7484 * This function is called after a PCI bus error affecting
7485 * this device has been detected.
7486 */
7487static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7488 pci_channel_state_t state)
9a799d71 7489{
c60fbb00
AD		 7490 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7491 struct net_device *netdev = adapter->netdev;
9a799d71 7492
83c61fa9
GR		 7493#ifdef CONFIG_PCI_IOV
7494 struct pci_dev *bdev, *vfdev;
7495 u32 dw0, dw1, dw2, dw3;
7496 int vf, pos;
7497 u16 req_id, pf_func;
7498
7499 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7500 adapter->num_vfs == 0)
7501 goto skip_bad_vf_detection;
7502
7503 bdev = pdev->bus->self;
7504 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7505 bdev = bdev->bus->self;
7506
7507 if (!bdev)
7508 goto skip_bad_vf_detection;
7509
7510 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7511 if (!pos)
7512 goto skip_bad_vf_detection;
7513
7514 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7515 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7516 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7517 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7518
7519 req_id = dw1 >> 16;
7520 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7521 if (!(req_id & 0x0080))
7522 goto skip_bad_vf_detection;
7523
7524 pf_func = req_id & 0x01;
7525 if ((pf_func & 1) == (pdev->devfn & 1)) {
7526 unsigned int device_id;
7527
7528 vf = (req_id & 0x7F) >> 1;
7529 e_dev_err("VF %d has caused a PCIe error\n", vf);
7530 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7531 "%8.8x\tdw3: %8.8x\n",
7532 dw0, dw1, dw2, dw3);
7533 switch (adapter->hw.mac.type) {
7534 case ixgbe_mac_82599EB:
7535 device_id = IXGBE_82599_VF_DEVICE_ID;
7536 break;
7537 case ixgbe_mac_X540:
7538 device_id = IXGBE_X540_VF_DEVICE_ID;
7539 break;
7540 default:
7541 device_id = 0;
7542 break;
7543 }
7544
7545 /* Find the pci device of the offending VF */
36e90319 7546 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7547 while (vfdev) {
7548 if (vfdev->devfn == (req_id & 0xFF))
7549 break;
36e90319 7550 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7551 device_id, vfdev);
7552 }
7553 /*
7554 * There's a slim chance the VF could have been hot plugged,
7555 * so if it is no longer present we don't need to issue the
7556 * VFLR. Just clean up the AER in that case.
7557 */
7558 if (vfdev) {
7559 e_dev_err("Issuing VFLR to VF %d\n", vf);
7560 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7561 }
7562
7563 pci_cleanup_aer_uncorrect_error_status(pdev);
7564 }
7565
7566 /*
7567 * Even though the error may have occurred on the other port
7568 * we still need to increment the vf error reference count for
7569 * both ports because the I/O resume function will be called
7570 * for both of them.
7571 */
7572 adapter->vferr_refcount++;
7573
7574 return PCI_ERS_RESULT_RECOVERED;
7575
7576skip_bad_vf_detection:
7577#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7578 netif_device_detach(netdev);
7579
3044b8d1
BL		 7580 if (state == pci_channel_io_perm_failure)
7581 return PCI_ERS_RESULT_DISCONNECT;
7582
9a799d71
AK		 7583 if (netif_running(netdev))
7584 ixgbe_down(adapter);
7585 pci_disable_device(pdev);
7586
b4617240 7587 /* Request a slot reset. */
9a799d71
AK		 7588 return PCI_ERS_RESULT_NEED_RESET;
7589}
7590
7591/**
7592 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7593 * @pdev: Pointer to PCI device
7594 *
7595 * Restart the card from scratch, as if from a cold-boot.
7596 */
7597static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7598{
c60fbb00 7599 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7600 pci_ers_result_t result;
7601 int err;
9a799d71 7602
9ce77666 7603 if (pci_enable_device_mem(pdev)) {
396e799c 7604 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7605 result = PCI_ERS_RESULT_DISCONNECT;
7606 } else {
7607 pci_set_master(pdev);
7608 pci_restore_state(pdev);
c0e1f68b 7609 pci_save_state(pdev);
9a799d71 7610
dd4d8ca6 7611 pci_wake_from_d3(pdev, false);
9a799d71 7612
6fabd715 7613 ixgbe_reset(adapter);
88512539 7614 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7615 result = PCI_ERS_RESULT_RECOVERED;
7616 }
7617
7618 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7619 if (err) {
849c4542
ET		 7620 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7621 "failed 0x%0x\n", err);
6fabd715
PWJ		 7622 /* non-fatal, continue */
7623 }
9a799d71 7624
6fabd715 7625 return result;
9a799d71
AK		 7626}
7627
7628/**
7629 * ixgbe_io_resume - called when traffic can start flowing again.
7630 * @pdev: Pointer to PCI device
7631 *
7632 * This callback is called when the error recovery driver tells us that
7633 * its OK to resume normal operation.
7634 */
7635static void ixgbe_io_resume(struct pci_dev *pdev)
7636{
c60fbb00
AD		 7637 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7638 struct net_device *netdev = adapter->netdev;
9a799d71 7639
83c61fa9
GR		 7640#ifdef CONFIG_PCI_IOV
7641 if (adapter->vferr_refcount) {
7642 e_info(drv, "Resuming after VF err\n");
7643 adapter->vferr_refcount--;
7644 return;
7645 }
7646
7647#endif
c7ccde0f
AD		 7648 if (netif_running(netdev))
7649 ixgbe_up(adapter);
9a799d71
AK		 7650
7651 netif_device_attach(netdev);
9a799d71
AK		 7652}
7653
7654static struct pci_error_handlers ixgbe_err_handler = {
7655 .error_detected = ixgbe_io_error_detected,
7656 .slot_reset = ixgbe_io_slot_reset,
7657 .resume = ixgbe_io_resume,
7658};
7659
7660static struct pci_driver ixgbe_driver = {
7661 .name = ixgbe_driver_name,
7662 .id_table = ixgbe_pci_tbl,
7663 .probe = ixgbe_probe,
7664 .remove = __devexit_p(ixgbe_remove),
7665#ifdef CONFIG_PM
7666 .suspend = ixgbe_suspend,
7667 .resume = ixgbe_resume,
7668#endif
7669 .shutdown = ixgbe_shutdown,
7670 .err_handler = &ixgbe_err_handler
7671};
7672
7673/**
7674 * ixgbe_init_module - Driver Registration Routine
7675 *
7676 * ixgbe_init_module is the first routine called when the driver is
7677 * loaded. All it does is register with the PCI subsystem.
7678 **/
7679static int __init ixgbe_init_module(void)
7680{
7681 int ret;
c7689578 7682 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7683 pr_info("%s\n", ixgbe_copyright);
9a799d71 7684
5dd2d332 7685#ifdef CONFIG_IXGBE_DCA
bd0362dd 7686 dca_register_notify(&dca_notifier);
bd0362dd 7687#endif
5dd2d332 7688
9a799d71
AK		 7689 ret = pci_register_driver(&ixgbe_driver);
7690 return ret;
7691}
b4617240 7692
9a799d71
AK		 7693module_init(ixgbe_init_module);
7694
7695/**
7696 * ixgbe_exit_module - Driver Exit Cleanup Routine
7697 *
7698 * ixgbe_exit_module is called just before the driver is removed
7699 * from memory.
7700 **/
7701static void __exit ixgbe_exit_module(void)
7702{
5dd2d332 7703#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7704 dca_unregister_notify(&dca_notifier);
7705#endif
9a799d71 7706 pci_unregister_driver(&ixgbe_driver);
1a51502b 7707 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7708}
bd0362dd 7709
5dd2d332 7710#ifdef CONFIG_IXGBE_DCA
bd0362dd 7711static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7712 void *p)
bd0362dd
JC		 7713{
7714 int ret_val;
7715
7716 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7717 __ixgbe_notify_dca);
bd0362dd
JC		 7718
7719 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7720}
b453368d 7721
5dd2d332 7722#endif /* CONFIG_IXGBE_DCA */
849c4542 7723
9a799d71
AK		 7724module_exit(ixgbe_exit_module);
7725
7726/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)