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bridge: convert flags in fbd entry into bitfields
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/ethtool.h>
01789349 46#include <linux/if.h>
9a799d71 47#include <linux/if_vlan.h>
2a47fa45 48#include <linux/if_macvlan.h>
815cccbf 49#include <linux/if_bridge.h>
70c71606 50#include <linux/prefetch.h>
eacd73f7 51#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 52
53#include "ixgbe.h"
54#include "ixgbe_common.h"
ee5f784a 55#include "ixgbe_dcb_82599.h"
1cdd1ec8 56#include "ixgbe_sriov.h"
9a799d71
AK		 57
58char ixgbe_driver_name[] = "ixgbe";
9c8eb720 59static const char ixgbe_driver_string[] =
e8e9f696 60 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 61#ifdef IXGBE_FCOE
ea81875a
NP		 62char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 64#else
65static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67#endif
f341c4e0 68#define DRV_VERSION "3.19.1-k"
9c8eb720 69const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 70static const char ixgbe_copyright[] =
0391bbe3 71 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 72
73static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 74 [board_82598] = &ixgbe_82598_info,
e8e26350 75 [board_82599] = &ixgbe_82599_info,
fe15e8e1 76 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 77};
78
79/* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
9baa3c34 87static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
170e8543 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
14438464
MR		 155static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
b8e82001
JK		 157static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159{
b8e82001
JK		 160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
c0798edf 171 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 172 return -1;
173
c0798edf 174 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
b8e82001
JK		 178 return 0;
179}
180
181static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182{
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202}
203
e027d1ae
JK		 204/**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214{
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 218 return true;
219 default:
220 return false;
221 }
222}
223
224static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226{
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
9f0a433c 255 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 273 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282}
283
7086400d
AD		 284static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285{
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290}
291
2a1a091c
MR		 292static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293{
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
58cf663f
MR		 300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 302}
303
f8e2472f 304static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 305{
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321}
322
f8e2472f
MR		 323/**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337{
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347}
348
14438464
MR		 349static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350{
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359}
360
361u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362{
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373}
374
375#ifdef CONFIG_PCI_IOV
376static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377{
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388}
389#endif /* CONFIG_PCI_IOV */
390
ed19231c
JK		 391void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392{
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398}
399
7086400d
AD		 400static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401{
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
52f33af8 404 /* flush memory to make sure state is correct before next watchdog */
4e857c58 405 smp_mb__before_atomic();
7086400d
AD		 406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407}
408
dcd79aeb
TI		 409struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412};
413
414static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
ca8dfe25 443 { .name = NULL }
dcd79aeb
TI		 444};
445
446
447/*
448 * ixgbe_regdump - register printout routine
449 */
450static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451{
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
c7689578 514 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 521 pr_err("%-15s", rname);
dcd79aeb 522 for (j = 0; j < 8; j++)
c7689578
JP		 523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
dcd79aeb
TI		 525 }
526
527}
528
529/*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532static void ixgbe_dump(struct ixgbe_adapter *adapter)
533{
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
729739b7 539 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 554 pr_info("Device Name state "
dcd79aeb 555 "trans_start last_rx\n");
c7689578
JP		 556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
dcd79aeb
TI		 561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 565 pr_info(" Register Name Value\n");
dcd79aeb
TI		 566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
e90dd264 573 return;
dcd79aeb
TI		 574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
dcd79aeb
TI		 579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
729739b7 581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
39ac868a 598 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
39ac868a 602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
dcd79aeb
TI		 629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
c7689578
JP		 633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
8ad88e37
JH		 636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 643 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 644 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 651 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
dcd79aeb
TI		 673 }
674 }
675
676 /* Print RX Rings Summary */
677rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 679 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
c7689578
JP		 682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
e90dd264 688 return;
dcd79aeb
TI		 689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
39ac868a
JH		 692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
39ac868a 703 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
39ac868a
JH		 707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
39ac868a
JH		 714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
dcd79aeb 735 */
39ac868a 736
dcd79aeb
TI		 737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
c7689578
JP		 739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
8ad88e37
JH		 742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 745 "<-- Adv Rx Read format\n");
8ad88e37
JH		 746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
c7689578 758 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
c7689578 764 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
9c50c035
ET		 771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
dcd79aeb
TI		 773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
f800326d 777 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 778 }
779 }
780
781 if (i == rx_ring->next_to_use)
c7689578 782 pr_cont(" NTU\n");
dcd79aeb 783 else if (i == rx_ring->next_to_clean)
c7689578 784 pr_cont(" NTC\n");
dcd79aeb 785 else
c7689578 786 pr_cont("\n");
dcd79aeb
TI		 787
788 }
789 }
dcd79aeb
TI		 790}
791
5eba3699
AV		 792static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
793{
794 u32 ctrl_ext;
795
796 /* Let firmware take over control of h/w */
797 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 799 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 800}
801
802static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
803{
804 u32 ctrl_ext;
805
806 /* Let firmware know the driver has taken over */
807 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 809 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 810}
9a799d71 811
49ce9c2c 812/**
e8e26350
PW		 813 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
814 * @adapter: pointer to adapter struct
815 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
816 * @queue: queue to map the corresponding interrupt to
817 * @msix_vector: the vector to map to the corresponding queue
818 *
819 */
820static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 821 u8 queue, u8 msix_vector)
9a799d71
AK		 822{
823 u32 ivar, index;
e8e26350
PW		 824 struct ixgbe_hw *hw = &adapter->hw;
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
828 if (direction == -1)
829 direction = 0;
830 index = (((direction * 64) + queue) >> 2) & 0x1F;
831 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
832 ivar &= ~(0xFF << (8 * (queue & 0x3)));
833 ivar |= (msix_vector << (8 * (queue & 0x3)));
834 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
835 break;
836 case ixgbe_mac_82599EB:
b93a2226 837 case ixgbe_mac_X540:
9a75a1ac
DS		 838 case ixgbe_mac_X550:
839 case ixgbe_mac_X550EM_x:
e8e26350
PW		 840 if (direction == -1) {
841 /* other causes */
842 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
843 index = ((queue & 1) * 8);
844 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
845 ivar &= ~(0xFF << index);
846 ivar |= (msix_vector << index);
847 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
848 break;
849 } else {
850 /* tx or rx causes */
851 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
852 index = ((16 * (queue & 1)) + (8 * direction));
853 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
854 ivar &= ~(0xFF << index);
855 ivar |= (msix_vector << index);
856 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
857 break;
858 }
859 default:
860 break;
861 }
9a799d71
AK		 862}
863
fe49f04a 864static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 865 u64 qmask)
fe49f04a
AD		 866{
867 u32 mask;
868
bd508178
AD		 869 switch (adapter->hw.mac.type) {
870 case ixgbe_mac_82598EB:
fe49f04a
AD		 871 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
872 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 873 break;
874 case ixgbe_mac_82599EB:
b93a2226 875 case ixgbe_mac_X540:
9a75a1ac
DS		 876 case ixgbe_mac_X550:
877 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 878 mask = (qmask & 0xFFFFFFFF);
879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
880 mask = (qmask >> 32);
881 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 882 break;
883 default:
884 break;
fe49f04a
AD		 885 }
886}
887
729739b7
AD		 888void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
889 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 890{
729739b7
AD		 891 if (tx_buffer->skb) {
892 dev_kfree_skb_any(tx_buffer->skb);
893 if (dma_unmap_len(tx_buffer, len))
d3d00239 894 dma_unmap_single(ring->dev,
729739b7
AD		 895 dma_unmap_addr(tx_buffer, dma),
896 dma_unmap_len(tx_buffer, len),
897 DMA_TO_DEVICE);
898 } else if (dma_unmap_len(tx_buffer, len)) {
899 dma_unmap_page(ring->dev,
900 dma_unmap_addr(tx_buffer, dma),
901 dma_unmap_len(tx_buffer, len),
902 DMA_TO_DEVICE);
e5a43549 903 }
729739b7
AD		 904 tx_buffer->next_to_watch = NULL;
905 tx_buffer->skb = NULL;
906 dma_unmap_len_set(tx_buffer, len, 0);
907 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 908}
909
943561d3 910static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 911{
912 struct ixgbe_hw *hw = &adapter->hw;
913 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 914 int i;
943561d3 915 u32 data;
c84d324c 916
943561d3
AD		 917 if ((hw->fc.current_mode != ixgbe_fc_full) &&
918 (hw->fc.current_mode != ixgbe_fc_rx_pause))
919 return;
c84d324c 920
943561d3
AD		 921 switch (hw->mac.type) {
922 case ixgbe_mac_82598EB:
923 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
924 break;
925 default:
926 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
927 }
928 hwstats->lxoffrxc += data;
c84d324c 929
943561d3
AD		 930 /* refill credits (no tx hang) if we received xoff */
931 if (!data)
c84d324c 932 return;
943561d3
AD		 933
934 for (i = 0; i < adapter->num_tx_queues; i++)
935 clear_bit(__IXGBE_HANG_CHECK_ARMED,
936 &adapter->tx_ring[i]->state);
937}
938
939static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
940{
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
943 u32 xoff[8] = {0};
2afaa00d 944 u8 tc;
943561d3
AD		 945 int i;
946 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
947
948 if (adapter->ixgbe_ieee_pfc)
949 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
950
951 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
952 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 953 return;
943561d3 954 }
c84d324c
JF		 955
956 /* update stats for each tc, only valid with PFC enabled */
957 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 958 u32 pxoffrxc;
959
c84d324c
JF		 960 switch (hw->mac.type) {
961 case ixgbe_mac_82598EB:
2afaa00d 962 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 963 break;
c84d324c 964 default:
2afaa00d 965 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 966 }
2afaa00d
PN		 967 hwstats->pxoffrxc[i] += pxoffrxc;
968 /* Get the TC for given UP */
969 tc = netdev_get_prio_tc_map(adapter->netdev, i);
970 xoff[tc] += pxoffrxc;
c84d324c
JF		 971 }
972
973 /* disarm tx queues that have received xoff frames */
974 for (i = 0; i < adapter->num_tx_queues; i++) {
975 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 976
2afaa00d 977 tc = tx_ring->dcb_tc;
c84d324c
JF		 978 if (xoff[tc])
979 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 980 }
26f23d82
YZ		 981}
982
c84d324c 983static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 984{
7d7ce682 985 return ring->stats.packets;
c84d324c
JF		 986}
987
988static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
989{
2a47fa45
JF		 990 struct ixgbe_adapter *adapter;
991 struct ixgbe_hw *hw;
992 u32 head, tail;
993
994 if (ring->l2_accel_priv)
995 adapter = ring->l2_accel_priv->real_adapter;
996 else
997 adapter = netdev_priv(ring->netdev);
e01c31a5 998
2a47fa45
JF		 999 hw = &adapter->hw;
1000 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1001 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1002
1003 if (head != tail)
1004 return (head < tail) ?
1005 tail - head : (tail + ring->count - head);
1006
1007 return 0;
1008}
1009
1010static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1011{
1012 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1013 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1014 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1015
7d637bcc 1016 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1017
1018 /*
1019 * Check for a hung queue, but be thorough. This verifies
1020 * that a transmit has been completed since the previous
1021 * check AND there is at least one packet pending. The
1022 * ARMED bit is set to indicate a potential hang. The
1023 * bit is cleared if a pause frame is received to remove
1024 * false hang detection due to PFC or 802.3x frames. By
1025 * requiring this to fail twice we avoid races with
1026 * pfc clearing the ARMED bit and conditions where we
1027 * run the check_tx_hang logic with a transmit completion
1028 * pending but without time to complete it yet.
1029 */
e90dd264 1030 if (tx_done_old == tx_done && tx_pending)
c84d324c 1031 /* make sure it is true for two checks in a row */
e90dd264
MR		 1032 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1033 &tx_ring->state);
1034 /* update completed stats and continue */
1035 tx_ring->tx_stats.tx_done_old = tx_done;
1036 /* reset the countdown */
1037 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1038
e90dd264 1039 return false;
9a799d71
AK		 1040}
1041
c83c6cbd
AD		 1042/**
1043 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1044 * @adapter: driver private struct
1045 **/
1046static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1047{
1048
1049 /* Do the reset outside of interrupt context */
1050 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1051 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1052 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1053 ixgbe_service_event_schedule(adapter);
1054 }
1055}
e01c31a5 1056
9a799d71
AK		 1057/**
1058 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1059 * @q_vector: structure containing interrupt and ring information
e01c31a5 1060 * @tx_ring: tx ring to clean
9a799d71 1061 **/
fe49f04a 1062static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1063 struct ixgbe_ring *tx_ring)
9a799d71 1064{
fe49f04a 1065 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1066 struct ixgbe_tx_buffer *tx_buffer;
1067 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1068 unsigned int total_bytes = 0, total_packets = 0;
59224555 1069 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1070 unsigned int i = tx_ring->next_to_clean;
1071
1072 if (test_bit(__IXGBE_DOWN, &adapter->state))
1073 return true;
9a799d71 1074
d3d00239 1075 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1076 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1077 i -= tx_ring->count;
12207e49 1078
729739b7 1079 do {
d3d00239
AD		 1080 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1081
1082 /* if next_to_watch is not set then there is no work pending */
1083 if (!eop_desc)
1084 break;
1085
7f83a9e6 1086 /* prevent any other reads prior to eop_desc */
7e63bf49 1087 read_barrier_depends();
7f83a9e6 1088
d3d00239
AD		 1089 /* if DD is not set pending work has not been completed */
1090 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1091 break;
8ad494b0 1092
d3d00239
AD		 1093 /* clear next_to_watch to prevent false hangs */
1094 tx_buffer->next_to_watch = NULL;
8ad494b0 1095
091a6246
AD		 1096 /* update the statistics for this packet */
1097 total_bytes += tx_buffer->bytecount;
1098 total_packets += tx_buffer->gso_segs;
1099
fd0db0ed 1100 /* free the skb */
fe1f2a97 1101 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1102
729739b7
AD		 1103 /* unmap skb header data */
1104 dma_unmap_single(tx_ring->dev,
1105 dma_unmap_addr(tx_buffer, dma),
1106 dma_unmap_len(tx_buffer, len),
1107 DMA_TO_DEVICE);
1108
fd0db0ed
AD		 1109 /* clear tx_buffer data */
1110 tx_buffer->skb = NULL;
729739b7 1111 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1112
729739b7
AD		 1113 /* unmap remaining buffers */
1114 while (tx_desc != eop_desc) {
d3d00239
AD		 1115 tx_buffer++;
1116 tx_desc++;
8ad494b0 1117 i++;
729739b7
AD		 1118 if (unlikely(!i)) {
1119 i -= tx_ring->count;
d3d00239 1120 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1121 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1122 }
e01c31a5 1123
729739b7
AD		 1124 /* unmap any remaining paged data */
1125 if (dma_unmap_len(tx_buffer, len)) {
1126 dma_unmap_page(tx_ring->dev,
1127 dma_unmap_addr(tx_buffer, dma),
1128 dma_unmap_len(tx_buffer, len),
1129 DMA_TO_DEVICE);
1130 dma_unmap_len_set(tx_buffer, len, 0);
1131 }
1132 }
1133
1134 /* move us one more past the eop_desc for start of next pkt */
1135 tx_buffer++;
1136 tx_desc++;
1137 i++;
1138 if (unlikely(!i)) {
1139 i -= tx_ring->count;
1140 tx_buffer = tx_ring->tx_buffer_info;
1141 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1142 }
1143
1144 /* issue prefetch for next Tx descriptor */
1145 prefetch(tx_desc);
12207e49 1146
729739b7
AD		 1147 /* update budget accounting */
1148 budget--;
1149 } while (likely(budget));
1150
1151 i += tx_ring->count;
9a799d71 1152 tx_ring->next_to_clean = i;
d3d00239 1153 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1154 tx_ring->stats.bytes += total_bytes;
bd198058 1155 tx_ring->stats.packets += total_packets;
d3d00239 1156 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1157 q_vector->tx.total_bytes += total_bytes;
1158 q_vector->tx.total_packets += total_packets;
b953799e 1159
c84d324c
JF		 1160 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1161 /* schedule immediate reset if we believe we hung */
1162 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1163 e_err(drv, "Detected Tx Unit Hang\n"
1164 " Tx Queue <%d>\n"
1165 " TDH, TDT <%x>, <%x>\n"
1166 " next_to_use <%x>\n"
1167 " next_to_clean <%x>\n"
1168 "tx_buffer_info[next_to_clean]\n"
1169 " time_stamp <%lx>\n"
1170 " jiffies <%lx>\n",
1171 tx_ring->queue_index,
1172 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1173 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1174 tx_ring->next_to_use, i,
1175 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1176
1177 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1178
1179 e_info(probe,
1180 "tx hang %d detected on queue %d, resetting adapter\n",
1181 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1182
b953799e 1183 /* schedule immediate reset if we believe we hung */
c83c6cbd 1184 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1185
1186 /* the adapter is about to reset, no point in enabling stuff */
59224555 1187 return true;
b953799e 1188 }
9a799d71 1189
b2d96e0a
AD		 1190 netdev_tx_completed_queue(txring_txq(tx_ring),
1191 total_packets, total_bytes);
1192
e092be60 1193#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1194 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1195 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1196 /* Make sure that anybody stopping the queue after this
1197 * sees the new next_to_clean.
1198 */
1199 smp_mb();
729739b7
AD		 1200 if (__netif_subqueue_stopped(tx_ring->netdev,
1201 tx_ring->queue_index)
1202 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1203 netif_wake_subqueue(tx_ring->netdev,
1204 tx_ring->queue_index);
5b7da515 1205 ++tx_ring->tx_stats.restart_queue;
30eba97a 1206 }
e092be60 1207 }
9a799d71 1208
59224555 1209 return !!budget;
9a799d71
AK		 1210}
1211
5dd2d332 1212#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1213static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1214 struct ixgbe_ring *tx_ring,
33cf09c9 1215 int cpu)
bd0362dd 1216{
33cf09c9 1217 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1218 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1219 u16 reg_offset;
33cf09c9 1220
33cf09c9
AD		 1221 switch (hw->mac.type) {
1222 case ixgbe_mac_82598EB:
bdda1a61 1223 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1224 break;
1225 case ixgbe_mac_82599EB:
b93a2226 1226 case ixgbe_mac_X540:
bdda1a61
AD		 1227 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1228 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1229 break;
1230 default:
bdda1a61
AD		 1231 /* for unknown hardware do not write register */
1232 return;
bd0362dd 1233 }
bdda1a61
AD		 1234
1235 /*
1236 * We can enable relaxed ordering for reads, but not writes when
1237 * DCA is enabled. This is due to a known issue in some chipsets
1238 * which will cause the DCA tag to be cleared.
1239 */
1240 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1241 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1242 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1243
1244 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1245}
1246
bdda1a61
AD		 1247static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1248 struct ixgbe_ring *rx_ring,
33cf09c9 1249 int cpu)
bd0362dd 1250{
33cf09c9 1251 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1252 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1253 u8 reg_idx = rx_ring->reg_idx;
1254
33cf09c9
AD		 1255
1256 switch (hw->mac.type) {
33cf09c9 1257 case ixgbe_mac_82599EB:
b93a2226 1258 case ixgbe_mac_X540:
bdda1a61 1259 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1260 break;
1261 default:
1262 break;
1263 }
bdda1a61
AD		 1264
1265 /*
1266 * We can enable relaxed ordering for reads, but not writes when
1267 * DCA is enabled. This is due to a known issue in some chipsets
1268 * which will cause the DCA tag to be cleared.
1269 */
1270 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1271 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1272
1273 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1274}
1275
1276static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1277{
1278 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1279 struct ixgbe_ring *ring;
bd0362dd 1280 int cpu = get_cpu();
bd0362dd 1281
33cf09c9
AD		 1282 if (q_vector->cpu == cpu)
1283 goto out_no_update;
1284
a557928e 1285 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1286 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1287
a557928e 1288 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1289 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1290
1291 q_vector->cpu = cpu;
1292out_no_update:
bd0362dd
JC		 1293 put_cpu();
1294}
1295
1296static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1297{
1298 int i;
1299
1300 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1301 return;
1302
e35ec126
AD		 1303 /* always use CB2 mode, difference is masked in the CB driver */
1304 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1305
49c7ffbe 1306 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1307 adapter->q_vector[i]->cpu = -1;
1308 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1309 }
1310}
1311
1312static int __ixgbe_notify_dca(struct device *dev, void *data)
1313{
c60fbb00 1314 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1315 unsigned long event = *(unsigned long *)data;
1316
2a72c31e 1317 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1318 return 0;
1319
bd0362dd
JC		 1320 switch (event) {
1321 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1322 /* if we're already enabled, don't do it again */
1323 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1324 break;
652f093f 1325 if (dca_add_requester(dev) == 0) {
96b0e0f6 1326 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1327 ixgbe_setup_dca(adapter);
1328 break;
1329 }
1330 /* Fall Through since DCA is disabled. */
1331 case DCA_PROVIDER_REMOVE:
1332 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1333 dca_remove_requester(dev);
1334 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1336 }
1337 break;
1338 }
1339
652f093f 1340 return 0;
bd0362dd 1341}
67a74ee2 1342
bdda1a61 1343#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1344static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1345 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1346 struct sk_buff *skb)
1347{
8a0da21b 1348 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1349 skb_set_hash(skb,
1350 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1351 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1352}
1353
f800326d 1354#ifdef IXGBE_FCOE
ff886dfc
AD		 1355/**
1356 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1357 * @ring: structure containing ring specific data
ff886dfc
AD		 1358 * @rx_desc: advanced rx descriptor
1359 *
1360 * Returns : true if it is FCoE pkt
1361 */
57efd44c 1362static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1363 union ixgbe_adv_rx_desc *rx_desc)
1364{
1365 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1366
57efd44c 1367 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1368 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1369 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1370 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1371}
1372
f800326d 1373#endif /* IXGBE_FCOE */
e59bd25d
AV		 1374/**
1375 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1376 * @ring: structure containing ring specific data
1377 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1378 * @skb: skb currently being received and modified
1379 **/
8a0da21b 1380static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1381 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1382 struct sk_buff *skb)
9a799d71 1383{
8a0da21b 1384 skb_checksum_none_assert(skb);
9a799d71 1385
712744be 1386 /* Rx csum disabled */
8a0da21b 1387 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1388 return;
e59bd25d
AV		 1389
1390 /* if IP and error */
f56e0cb1
AD		 1391 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1392 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1393 ring->rx_stats.csum_err++;
9a799d71
AK		 1394 return;
1395 }
e59bd25d 1396
f56e0cb1 1397 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1398 return;
1399
f56e0cb1 1400 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1401 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1402
1403 /*
1404 * 82599 errata, UDP frames with a 0 checksum can be marked as
1405 * checksum errors.
1406 */
8a0da21b
AD		 1407 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1408 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1409 return;
1410
8a0da21b 1411 ring->rx_stats.csum_err++;
e59bd25d
AV		 1412 return;
1413 }
1414
9a799d71 1415 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1416 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1417}
1418
84ea2591 1419static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1420{
f56e0cb1 1421 rx_ring->next_to_use = val;
f800326d
AD		 1422
1423 /* update next to alloc since we have filled the ring */
1424 rx_ring->next_to_alloc = val;
e8e26350
PW		 1425 /*
1426 * Force memory writes to complete before letting h/w
1427 * know there are new descriptors to fetch. (Only
1428 * applicable for weak-ordered memory model archs,
1429 * such as IA-64).
1430 */
1431 wmb();
84227bcd 1432 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1433}
1434
f990b79b
AD		 1435static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1436 struct ixgbe_rx_buffer *bi)
1437{
1438 struct page *page = bi->page;
f800326d 1439 dma_addr_t dma = bi->dma;
f990b79b 1440
f800326d
AD		 1441 /* since we are recycling buffers we should seldom need to alloc */
1442 if (likely(dma))
f990b79b
AD		 1443 return true;
1444
f800326d
AD		 1445 /* alloc new page for storage */
1446 if (likely(!page)) {
42b17f09 1447 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1448 if (unlikely(!page)) {
1449 rx_ring->rx_stats.alloc_rx_page_failed++;
1450 return false;
1451 }
f800326d 1452 bi->page = page;
f990b79b
AD		 1453 }
1454
f800326d
AD		 1455 /* map page for use */
1456 dma = dma_map_page(rx_ring->dev, page, 0,
1457 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1458
1459 /*
1460 * if mapping failed free memory back to system since
1461 * there isn't much point in holding memory we can't use
1462 */
1463 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1464 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1465 bi->page = NULL;
f990b79b 1466
f990b79b
AD		 1467 rx_ring->rx_stats.alloc_rx_page_failed++;
1468 return false;
1469 }
1470
f800326d 1471 bi->dma = dma;
afaa9459 1472 bi->page_offset = 0;
f800326d 1473
f990b79b
AD		 1474 return true;
1475}
1476
9a799d71 1477/**
f990b79b 1478 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1479 * @rx_ring: ring to place buffers on
1480 * @cleaned_count: number of buffers to replace
9a799d71 1481 **/
fc77dc3c 1482void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1483{
9a799d71 1484 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1485 struct ixgbe_rx_buffer *bi;
d5f398ed 1486 u16 i = rx_ring->next_to_use;
9a799d71 1487
f800326d
AD		 1488 /* nothing to do */
1489 if (!cleaned_count)
fc77dc3c
AD		 1490 return;
1491
e4f74028 1492 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1493 bi = &rx_ring->rx_buffer_info[i];
1494 i -= rx_ring->count;
9a799d71 1495
f800326d
AD		 1496 do {
1497 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1498 break;
d5f398ed 1499
f800326d
AD		 1500 /*
1501 * Refresh the desc even if buffer_addrs didn't change
1502 * because each write-back erases this info.
1503 */
1504 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1505
f990b79b
AD		 1506 rx_desc++;
1507 bi++;
9a799d71 1508 i++;
f990b79b 1509 if (unlikely(!i)) {
e4f74028 1510 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1511 bi = rx_ring->rx_buffer_info;
1512 i -= rx_ring->count;
1513 }
1514
1515 /* clear the hdr_addr for the next_to_use descriptor */
1516 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1517
1518 cleaned_count--;
1519 } while (cleaned_count);
7c6e0a43 1520
f990b79b
AD		 1521 i += rx_ring->count;
1522
f56e0cb1 1523 if (rx_ring->next_to_use != i)
84ea2591 1524 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1525}
1526
1d2024f6
AD		 1527static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1528 struct sk_buff *skb)
1529{
f800326d 1530 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1531
1532 /* set gso_size to avoid messing up TCP MSS */
1533 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1534 IXGBE_CB(skb)->append_cnt);
96be80ab 1535 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1536}
1537
1538static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1539 struct sk_buff *skb)
1540{
1541 /* if append_cnt is 0 then frame is not RSC */
1542 if (!IXGBE_CB(skb)->append_cnt)
1543 return;
1544
1545 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1546 rx_ring->rx_stats.rsc_flush++;
1547
1548 ixgbe_set_rsc_gso_size(rx_ring, skb);
1549
1550 /* gso_size is computed using append_cnt so always clear it last */
1551 IXGBE_CB(skb)->append_cnt = 0;
1552}
1553
8a0da21b
AD		 1554/**
1555 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1556 * @rx_ring: rx descriptor ring packet is being transacted on
1557 * @rx_desc: pointer to the EOP Rx descriptor
1558 * @skb: pointer to current skb being populated
f8212f97 1559 *
8a0da21b
AD		 1560 * This function checks the ring, descriptor, and packet information in
1561 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1562 * other fields within the skb.
f8212f97 1563 **/
8a0da21b
AD		 1564static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1565 union ixgbe_adv_rx_desc *rx_desc,
1566 struct sk_buff *skb)
f8212f97 1567{
43e95f11
JF		 1568 struct net_device *dev = rx_ring->netdev;
1569
8a0da21b
AD		 1570 ixgbe_update_rsc_stats(rx_ring, skb);
1571
1572 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1573
8a0da21b
AD		 1574 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1575
eda183c2
JK		 1576 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1577 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1578
f646968f 1579 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1580 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1581 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1582 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1583 }
1584
8a0da21b 1585 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1586
43e95f11 1587 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1588}
1589
8a0da21b
AD		 1590static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1591 struct sk_buff *skb)
aa80175a 1592{
8a0da21b
AD		 1593 struct ixgbe_adapter *adapter = q_vector->adapter;
1594
b4640030 1595 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1596 netif_receive_skb(skb);
1597 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1598 napi_gro_receive(&q_vector->napi, skb);
1599 else
1600 netif_rx(skb);
aa80175a 1601}
43634e82 1602
f800326d
AD		 1603/**
1604 * ixgbe_is_non_eop - process handling of non-EOP buffers
1605 * @rx_ring: Rx ring being processed
1606 * @rx_desc: Rx descriptor for current buffer
1607 * @skb: Current socket buffer containing buffer in progress
1608 *
1609 * This function updates next to clean. If the buffer is an EOP buffer
1610 * this function exits returning false, otherwise it will place the
1611 * sk_buff in the next buffer to be chained and return true indicating
1612 * that this is in fact a non-EOP buffer.
1613 **/
1614static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1615 union ixgbe_adv_rx_desc *rx_desc,
1616 struct sk_buff *skb)
1617{
1618 u32 ntc = rx_ring->next_to_clean + 1;
1619
1620 /* fetch, update, and store next to clean */
1621 ntc = (ntc < rx_ring->count) ? ntc : 0;
1622 rx_ring->next_to_clean = ntc;
1623
1624 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1625
5a02cbd1
AD		 1626 /* update RSC append count if present */
1627 if (ring_is_rsc_enabled(rx_ring)) {
1628 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1629 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1630
1631 if (unlikely(rsc_enabled)) {
1632 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1633
1634 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1635 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1636
5a02cbd1
AD		 1637 /* update ntc based on RSC value */
1638 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1639 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1640 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1641 }
f800326d
AD		 1642 }
1643
5a02cbd1
AD		 1644 /* if we are the last buffer then there is nothing else to do */
1645 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1646 return false;
1647
f800326d
AD		 1648 /* place skb in next buffer to be received */
1649 rx_ring->rx_buffer_info[ntc].skb = skb;
1650 rx_ring->rx_stats.non_eop_descs++;
1651
1652 return true;
1653}
1654
19861ce2
AD		 1655/**
1656 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1657 * @rx_ring: rx descriptor ring packet is being transacted on
1658 * @skb: pointer to current skb being adjusted
1659 *
1660 * This function is an ixgbe specific version of __pskb_pull_tail. The
1661 * main difference between this version and the original function is that
1662 * this function can make several assumptions about the state of things
1663 * that allow for significant optimizations versus the standard function.
1664 * As a result we can do things like drop a frag and maintain an accurate
1665 * truesize for the skb.
1666 */
1667static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1668 struct sk_buff *skb)
1669{
1670 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1671 unsigned char *va;
1672 unsigned int pull_len;
1673
1674 /*
1675 * it is valid to use page_address instead of kmap since we are
1676 * working with pages allocated out of the lomem pool per
1677 * alloc_page(GFP_ATOMIC)
1678 */
1679 va = skb_frag_address(frag);
1680
1681 /*
1682 * we need the header to contain the greater of either ETH_HLEN or
1683 * 60 bytes if the skb->len is less than 60 for skb_pad.
1684 */
8496e338 1685 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1686
1687 /* align pull length to size of long to optimize memcpy performance */
1688 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1689
1690 /* update all of the pointers */
1691 skb_frag_size_sub(frag, pull_len);
1692 frag->page_offset += pull_len;
1693 skb->data_len -= pull_len;
1694 skb->tail += pull_len;
19861ce2
AD		 1695}
1696
42073d91
AD		 1697/**
1698 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1699 * @rx_ring: rx descriptor ring packet is being transacted on
1700 * @skb: pointer to current skb being updated
1701 *
1702 * This function provides a basic DMA sync up for the first fragment of an
1703 * skb. The reason for doing this is that the first fragment cannot be
1704 * unmapped until we have reached the end of packet descriptor for a buffer
1705 * chain.
1706 */
1707static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1708 struct sk_buff *skb)
1709{
1710 /* if the page was released unmap it, else just sync our portion */
1711 if (unlikely(IXGBE_CB(skb)->page_released)) {
1712 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1713 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1714 IXGBE_CB(skb)->page_released = false;
1715 } else {
1716 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1717
1718 dma_sync_single_range_for_cpu(rx_ring->dev,
1719 IXGBE_CB(skb)->dma,
1720 frag->page_offset,
1721 ixgbe_rx_bufsz(rx_ring),
1722 DMA_FROM_DEVICE);
1723 }
1724 IXGBE_CB(skb)->dma = 0;
1725}
1726
f800326d
AD		 1727/**
1728 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1729 * @rx_ring: rx descriptor ring packet is being transacted on
1730 * @rx_desc: pointer to the EOP Rx descriptor
1731 * @skb: pointer to current skb being fixed
1732 *
1733 * Check for corrupted packet headers caused by senders on the local L2
1734 * embedded NIC switch not setting up their Tx Descriptors right. These
1735 * should be very rare.
1736 *
1737 * Also address the case where we are pulling data in on pages only
1738 * and as such no data is present in the skb header.
1739 *
1740 * In addition if skb is not at least 60 bytes we need to pad it so that
1741 * it is large enough to qualify as a valid Ethernet frame.
1742 *
1743 * Returns true if an error was encountered and skb was freed.
1744 **/
1745static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1746 union ixgbe_adv_rx_desc *rx_desc,
1747 struct sk_buff *skb)
1748{
f800326d 1749 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1750
1751 /* verify that the packet does not have any known errors */
1752 if (unlikely(ixgbe_test_staterr(rx_desc,
1753 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1754 !(netdev->features & NETIF_F_RXALL))) {
1755 dev_kfree_skb_any(skb);
1756 return true;
1757 }
1758
19861ce2 1759 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1760 if (skb_is_nonlinear(skb))
1761 ixgbe_pull_tail(rx_ring, skb);
f800326d 1762
57efd44c
AD		 1763#ifdef IXGBE_FCOE
1764 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1765 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1766 return false;
1767
1768#endif
f800326d
AD		 1769 /* if skb_pad returns an error the skb was freed */
1770 if (unlikely(skb->len < 60)) {
1771 int pad_len = 60 - skb->len;
1772
1773 if (skb_pad(skb, pad_len))
1774 return true;
1775 __skb_put(skb, pad_len);
1776 }
1777
1778 return false;
1779}
1780
f800326d
AD		 1781/**
1782 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1783 * @rx_ring: rx descriptor ring to store buffers on
1784 * @old_buff: donor buffer to have page reused
1785 *
0549ae20 1786 * Synchronizes page for reuse by the adapter
f800326d
AD		 1787 **/
1788static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1789 struct ixgbe_rx_buffer *old_buff)
1790{
1791 struct ixgbe_rx_buffer *new_buff;
1792 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1793
1794 new_buff = &rx_ring->rx_buffer_info[nta];
1795
1796 /* update, and store next to alloc */
1797 nta++;
1798 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1799
1800 /* transfer page from old buffer to new buffer */
1801 new_buff->page = old_buff->page;
1802 new_buff->dma = old_buff->dma;
0549ae20 1803 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1804
1805 /* sync the buffer for use by the device */
1806 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1807 new_buff->page_offset,
1808 ixgbe_rx_bufsz(rx_ring),
f800326d 1809 DMA_FROM_DEVICE);
f800326d
AD		 1810}
1811
1812/**
1813 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1814 * @rx_ring: rx descriptor ring to transact packets on
1815 * @rx_buffer: buffer containing page to add
1816 * @rx_desc: descriptor containing length of buffer written by hardware
1817 * @skb: sk_buff to place the data into
1818 *
0549ae20
AD		 1819 * This function will add the data contained in rx_buffer->page to the skb.
1820 * This is done either through a direct copy if the data in the buffer is
1821 * less than the skb header size, otherwise it will just attach the page as
1822 * a frag to the skb.
1823 *
1824 * The function will then update the page offset if necessary and return
1825 * true if the buffer can be reused by the adapter.
f800326d 1826 **/
0549ae20 1827static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1828 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1829 union ixgbe_adv_rx_desc *rx_desc,
1830 struct sk_buff *skb)
f800326d 1831{
0549ae20
AD		 1832 struct page *page = rx_buffer->page;
1833 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1834#if (PAGE_SIZE < 8192)
0549ae20 1835 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1836#else
1837 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1838 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1839 ixgbe_rx_bufsz(rx_ring);
1840#endif
0549ae20 1841
cf3fe7ac
AD		 1842 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1843 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1844
1845 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1846
1847 /* we can reuse buffer as-is, just make sure it is local */
1848 if (likely(page_to_nid(page) == numa_node_id()))
1849 return true;
1850
1851 /* this page cannot be reused so discard it */
1852 put_page(page);
1853 return false;
1854 }
1855
0549ae20
AD		 1856 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1857 rx_buffer->page_offset, size, truesize);
1858
09816fbe
AD		 1859 /* avoid re-using remote pages */
1860 if (unlikely(page_to_nid(page) != numa_node_id()))
1861 return false;
1862
1863#if (PAGE_SIZE < 8192)
1864 /* if we are only owner of page we can reuse it */
1865 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1866 return false;
1867
1868 /* flip page offset to other buffer */
1869 rx_buffer->page_offset ^= truesize;
1870
ec916983
ED		 1871 /* Even if we own the page, we are not allowed to use atomic_set()
1872 * This would break get_page_unless_zero() users.
09816fbe 1873 */
ec916983 1874 atomic_inc(&page->_count);
09816fbe
AD		 1875#else
1876 /* move offset up to the next cache line */
1877 rx_buffer->page_offset += truesize;
1878
1879 if (rx_buffer->page_offset > last_offset)
1880 return false;
1881
0549ae20
AD		 1882 /* bump ref count on page before it is given to the stack */
1883 get_page(page);
09816fbe 1884#endif
0549ae20
AD		 1885
1886 return true;
f800326d
AD		 1887}
1888
18806c9e
AD		 1889static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1890 union ixgbe_adv_rx_desc *rx_desc)
1891{
1892 struct ixgbe_rx_buffer *rx_buffer;
1893 struct sk_buff *skb;
1894 struct page *page;
1895
1896 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1897 page = rx_buffer->page;
1898 prefetchw(page);
1899
1900 skb = rx_buffer->skb;
1901
1902 if (likely(!skb)) {
1903 void *page_addr = page_address(page) +
1904 rx_buffer->page_offset;
1905
1906 /* prefetch first cache line of first page */
1907 prefetch(page_addr);
1908#if L1_CACHE_BYTES < 128
1909 prefetch(page_addr + L1_CACHE_BYTES);
1910#endif
1911
1912 /* allocate a skb to store the frags */
1913 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1914 IXGBE_RX_HDR_SIZE);
1915 if (unlikely(!skb)) {
1916 rx_ring->rx_stats.alloc_rx_buff_failed++;
1917 return NULL;
1918 }
1919
1920 /*
1921 * we will be copying header into skb->data in
1922 * pskb_may_pull so it is in our interest to prefetch
1923 * it now to avoid a possible cache miss
1924 */
1925 prefetchw(skb->data);
1926
1927 /*
1928 * Delay unmapping of the first packet. It carries the
1929 * header information, HW may still access the header
1930 * after the writeback. Only unmap it when EOP is
1931 * reached
1932 */
1933 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1934 goto dma_sync;
1935
1936 IXGBE_CB(skb)->dma = rx_buffer->dma;
1937 } else {
1938 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1939 ixgbe_dma_sync_frag(rx_ring, skb);
1940
1941dma_sync:
1942 /* we are reusing so sync this buffer for CPU use */
1943 dma_sync_single_range_for_cpu(rx_ring->dev,
1944 rx_buffer->dma,
1945 rx_buffer->page_offset,
1946 ixgbe_rx_bufsz(rx_ring),
1947 DMA_FROM_DEVICE);
1948 }
1949
1950 /* pull page into skb */
1951 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1952 /* hand second half of page back to the ring */
1953 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1954 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1955 /* the page has been released from the ring */
1956 IXGBE_CB(skb)->page_released = true;
1957 } else {
1958 /* we are not reusing the buffer so unmap it */
1959 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1960 ixgbe_rx_pg_size(rx_ring),
1961 DMA_FROM_DEVICE);
1962 }
1963
1964 /* clear contents of buffer_info */
1965 rx_buffer->skb = NULL;
1966 rx_buffer->dma = 0;
1967 rx_buffer->page = NULL;
1968
1969 return skb;
f800326d
AD		 1970}
1971
1972/**
1973 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1974 * @q_vector: structure containing interrupt and ring information
1975 * @rx_ring: rx descriptor ring to transact packets on
1976 * @budget: Total limit on number of packets to process
1977 *
1978 * This function provides a "bounce buffer" approach to Rx interrupt
1979 * processing. The advantage to this is that on systems that have
1980 * expensive overhead for IOMMU access this provides a means of avoiding
1981 * it by maintaining the mapping of the page to the syste.
1982 *
5a85e737 1983 * Returns amount of work completed
f800326d 1984 **/
5a85e737 1985static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1986 struct ixgbe_ring *rx_ring,
f4de00ed 1987 const int budget)
9a799d71 1988{
d2f4fbe2 1989 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1990#ifdef IXGBE_FCOE
f800326d 1991 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1992 int ddp_bytes;
1993 unsigned int mss = 0;
3d8fd385 1994#endif /* IXGBE_FCOE */
f800326d 1995 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1996
fdabfc8a 1997 while (likely(total_rx_packets < budget)) {
f800326d
AD		 1998 union ixgbe_adv_rx_desc *rx_desc;
1999 struct sk_buff *skb;
f800326d
AD		 2000
2001 /* return some buffers to hardware, one at a time is too slow */
2002 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2003 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2004 cleaned_count = 0;
2005 }
2006
18806c9e 2007 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2008
2009 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2010 break;
9a799d71 2011
f800326d
AD		 2012 /*
2013 * This memory barrier is needed to keep us from reading
2014 * any other fields out of the rx_desc until we know the
2015 * RXD_STAT_DD bit is set
2016 */
2017 rmb();
9a799d71 2018
18806c9e
AD		 2019 /* retrieve a buffer from the ring */
2020 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2021
18806c9e
AD		 2022 /* exit if we failed to retrieve a buffer */
2023 if (!skb)
2024 break;
9a799d71 2025
9a799d71 2026 cleaned_count++;
f8212f97 2027
f800326d
AD		 2028 /* place incomplete frames back on ring for completion */
2029 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2030 continue;
c267fc16 2031
f800326d
AD		 2032 /* verify the packet layout is correct */
2033 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2034 continue;
9a799d71 2035
d2f4fbe2
AV		 2036 /* probably a little skewed due to removing CRC */
2037 total_rx_bytes += skb->len;
d2f4fbe2 2038
8a0da21b
AD		 2039 /* populate checksum, timestamp, VLAN, and protocol */
2040 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2041
332d4a7d
YZ		 2042#ifdef IXGBE_FCOE
2043 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2044 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2045 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2046 /* include DDPed FCoE data */
2047 if (ddp_bytes > 0) {
2048 if (!mss) {
2049 mss = rx_ring->netdev->mtu -
2050 sizeof(struct fcoe_hdr) -
2051 sizeof(struct fc_frame_header) -
2052 sizeof(struct fcoe_crc_eof);
2053 if (mss > 512)
2054 mss &= ~511;
2055 }
2056 total_rx_bytes += ddp_bytes;
2057 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2058 mss);
2059 }
63d635b2
AD		 2060 if (!ddp_bytes) {
2061 dev_kfree_skb_any(skb);
f800326d 2062 continue;
63d635b2 2063 }
3d8fd385 2064 }
f800326d 2065
332d4a7d 2066#endif /* IXGBE_FCOE */
8b80cda5 2067 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2068 ixgbe_rx_skb(q_vector, skb);
9a799d71 2069
f800326d 2070 /* update budget accounting */
f4de00ed 2071 total_rx_packets++;
fdabfc8a 2072 }
9a799d71 2073
c267fc16
AD		 2074 u64_stats_update_begin(&rx_ring->syncp);
2075 rx_ring->stats.packets += total_rx_packets;
2076 rx_ring->stats.bytes += total_rx_bytes;
2077 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2078 q_vector->rx.total_packets += total_rx_packets;
2079 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2080
5a85e737 2081 return total_rx_packets;
9a799d71
AK		 2082}
2083
e0d1095a 2084#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2085/* must be called with local_bh_disable()d */
2086static int ixgbe_low_latency_recv(struct napi_struct *napi)
2087{
2088 struct ixgbe_q_vector *q_vector =
2089 container_of(napi, struct ixgbe_q_vector, napi);
2090 struct ixgbe_adapter *adapter = q_vector->adapter;
2091 struct ixgbe_ring *ring;
2092 int found = 0;
2093
2094 if (test_bit(__IXGBE_DOWN, &adapter->state))
2095 return LL_FLUSH_FAILED;
2096
2097 if (!ixgbe_qv_lock_poll(q_vector))
2098 return LL_FLUSH_BUSY;
2099
2100 ixgbe_for_each_ring(ring, q_vector->rx) {
2101 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2102#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2103 if (found)
2104 ring->stats.cleaned += found;
2105 else
2106 ring->stats.misses++;
2107#endif
5a85e737
ET		 2108 if (found)
2109 break;
2110 }
2111
2112 ixgbe_qv_unlock_poll(q_vector);
2113
2114 return found;
2115}
e0d1095a 2116#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2117
9a799d71
AK		 2118/**
2119 * ixgbe_configure_msix - Configure MSI-X hardware
2120 * @adapter: board private structure
2121 *
2122 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2123 * interrupts.
2124 **/
2125static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2126{
021230d4 2127 struct ixgbe_q_vector *q_vector;
49c7ffbe 2128 int v_idx;
021230d4 2129 u32 mask;
9a799d71 2130
8e34d1aa
AD		 2131 /* Populate MSIX to EITR Select */
2132 if (adapter->num_vfs > 32) {
2133 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2134 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2135 }
2136
4df10466
JB		 2137 /*
2138 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2139 * corresponding register.
2140 */
49c7ffbe 2141 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2142 struct ixgbe_ring *ring;
7a921c93 2143 q_vector = adapter->q_vector[v_idx];
021230d4 2144
a557928e 2145 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2146 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2147
a557928e 2148 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2149 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2150
fe49f04a 2151 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2152 }
2153
bd508178
AD		 2154 switch (adapter->hw.mac.type) {
2155 case ixgbe_mac_82598EB:
e8e26350 2156 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2157 v_idx);
bd508178
AD		 2158 break;
2159 case ixgbe_mac_82599EB:
b93a2226 2160 case ixgbe_mac_X540:
9a75a1ac
DS		 2161 case ixgbe_mac_X550:
2162 case ixgbe_mac_X550EM_x:
e8e26350 2163 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2164 break;
bd508178
AD		 2165 default:
2166 break;
2167 }
021230d4
AV		 2168 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2169
41fb9248 2170 /* set up to autoclear timer, and the vectors */
021230d4 2171 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2172 mask &= ~(IXGBE_EIMS_OTHER |
2173 IXGBE_EIMS_MAILBOX |
2174 IXGBE_EIMS_LSC);
2175
021230d4 2176 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2177}
2178
f494e8fa
AV		 2179enum latency_range {
2180 lowest_latency = 0,
2181 low_latency = 1,
2182 bulk_latency = 2,
2183 latency_invalid = 255
2184};
2185
2186/**
2187 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2188 * @q_vector: structure containing interrupt and ring information
2189 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2190 *
2191 * Stores a new ITR value based on packets and byte
2192 * counts during the last interrupt. The advantage of per interrupt
2193 * computation is faster updates and more accurate ITR for the current
2194 * traffic pattern. Constants in this function were computed
2195 * based on theoretical maximum wire speed and thresholds were set based
2196 * on testing data as well as attempting to minimize response time
2197 * while increasing bulk throughput.
2198 * this functionality is controlled by the InterruptThrottleRate module
2199 * parameter (see ixgbe_param.c)
2200 **/
bd198058
AD		 2201static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2202 struct ixgbe_ring_container *ring_container)
f494e8fa 2203{
bd198058
AD		 2204 int bytes = ring_container->total_bytes;
2205 int packets = ring_container->total_packets;
2206 u32 timepassed_us;
621bd70e 2207 u64 bytes_perint;
bd198058 2208 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2209
2210 if (packets == 0)
bd198058 2211 return;
f494e8fa
AV		 2212
2213 /* simple throttlerate management
621bd70e
AD		 2214 * 0-10MB/s lowest (100000 ints/s)
2215 * 10-20MB/s low (20000 ints/s)
2216 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2217 */
2218 /* what was last interrupt timeslice? */
d5bf4f67 2219 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2220 if (timepassed_us == 0)
2221 return;
2222
f494e8fa
AV		 2223 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2224
2225 switch (itr_setting) {
2226 case lowest_latency:
621bd70e 2227 if (bytes_perint > 10)
bd198058 2228 itr_setting = low_latency;
f494e8fa
AV		 2229 break;
2230 case low_latency:
621bd70e 2231 if (bytes_perint > 20)
bd198058 2232 itr_setting = bulk_latency;
621bd70e 2233 else if (bytes_perint <= 10)
bd198058 2234 itr_setting = lowest_latency;
f494e8fa
AV		 2235 break;
2236 case bulk_latency:
621bd70e 2237 if (bytes_perint <= 20)
bd198058 2238 itr_setting = low_latency;
f494e8fa
AV		 2239 break;
2240 }
2241
bd198058
AD		 2242 /* clear work counters since we have the values we need */
2243 ring_container->total_bytes = 0;
2244 ring_container->total_packets = 0;
2245
2246 /* write updated itr to ring container */
2247 ring_container->itr = itr_setting;
f494e8fa
AV		 2248}
2249
509ee935
JB		 2250/**
2251 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2252 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2253 *
2254 * This function is made to be called by ethtool and by the driver
2255 * when it needs to update EITR registers at runtime. Hardware
2256 * specific quirks/differences are taken care of here.
2257 */
fe49f04a 2258void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2259{
fe49f04a 2260 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2261 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2262 int v_idx = q_vector->v_idx;
5d967eb7 2263 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2264
bd508178
AD		 2265 switch (adapter->hw.mac.type) {
2266 case ixgbe_mac_82598EB:
509ee935
JB		 2267 /* must write high and low 16 bits to reset counter */
2268 itr_reg |= (itr_reg << 16);
bd508178
AD		 2269 break;
2270 case ixgbe_mac_82599EB:
b93a2226 2271 case ixgbe_mac_X540:
9a75a1ac
DS		 2272 case ixgbe_mac_X550:
2273 case ixgbe_mac_X550EM_x:
509ee935
JB		 2274 /*
2275 * set the WDIS bit to not clear the timer bits and cause an
2276 * immediate assertion of the interrupt
2277 */
2278 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2279 break;
2280 default:
2281 break;
509ee935
JB		 2282 }
2283 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2284}
2285
bd198058 2286static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2287{
d5bf4f67 2288 u32 new_itr = q_vector->itr;
bd198058 2289 u8 current_itr;
f494e8fa 2290
bd198058
AD		 2291 ixgbe_update_itr(q_vector, &q_vector->tx);
2292 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2293
08c8833b 2294 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2295
2296 switch (current_itr) {
2297 /* counts and packets in update_itr are dependent on these numbers */
2298 case lowest_latency:
d5bf4f67 2299 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2300 break;
2301 case low_latency:
d5bf4f67 2302 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2303 break;
2304 case bulk_latency:
d5bf4f67 2305 new_itr = IXGBE_8K_ITR;
f494e8fa 2306 break;
bd198058
AD		 2307 default:
2308 break;
f494e8fa
AV		 2309 }
2310
d5bf4f67 2311 if (new_itr != q_vector->itr) {
fe49f04a 2312 /* do an exponential smoothing */
d5bf4f67
ET		 2313 new_itr = (10 * new_itr * q_vector->itr) /
2314 ((9 * new_itr) + q_vector->itr);
509ee935 2315
bd198058 2316 /* save the algorithm value here */
5d967eb7 2317 q_vector->itr = new_itr;
fe49f04a
AD		 2318
2319 ixgbe_write_eitr(q_vector);
f494e8fa 2320 }
f494e8fa
AV		 2321}
2322
119fc60a 2323/**
de88eeeb 2324 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2325 * @adapter: pointer to adapter
119fc60a 2326 **/
f0f9778d 2327static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2328{
119fc60a
MC		 2329 struct ixgbe_hw *hw = &adapter->hw;
2330 u32 eicr = adapter->interrupt_event;
2331
f0f9778d 2332 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2333 return;
2334
f0f9778d
AD		 2335 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2336 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2337 return;
2338
2339 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2340
7ca647bd 2341 switch (hw->device_id) {
f0f9778d
AD		 2342 case IXGBE_DEV_ID_82599_T3_LOM:
2343 /*
2344 * Since the warning interrupt is for both ports
2345 * we don't have to check if:
2346 * - This interrupt wasn't for our port.
2347 * - We may have missed the interrupt so always have to
2348 * check if we got a LSC
2349 */
2350 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2351 !(eicr & IXGBE_EICR_LSC))
2352 return;
2353
2354 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2355 u32 speed;
f0f9778d 2356 bool link_up = false;
7ca647bd 2357
3d292265 2358 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2359
f0f9778d
AD		 2360 if (link_up)
2361 return;
2362 }
2363
2364 /* Check if this is not due to overtemp */
2365 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2366 return;
2367
2368 break;
7ca647bd
JP		 2369 default:
2370 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2371 return;
7ca647bd 2372 break;
119fc60a 2373 }
7ca647bd
JP		 2374 e_crit(drv,
2375 "Network adapter has been stopped because it has over heated. "
2376 "Restart the computer. If the problem persists, "
2377 "power off the system and replace the adapter\n");
f0f9778d
AD		 2378
2379 adapter->interrupt_event = 0;
119fc60a
MC		 2380}
2381
0befdb3e
JB		 2382static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2383{
2384 struct ixgbe_hw *hw = &adapter->hw;
2385
2386 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2387 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2388 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2389 /* write to clear the interrupt */
2390 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2391 }
2392}
cf8280ee 2393
4f51bf70
JK		 2394static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2395{
2396 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2397 return;
2398
2399 switch (adapter->hw.mac.type) {
2400 case ixgbe_mac_82599EB:
2401 /*
2402 * Need to check link state so complete overtemp check
2403 * on service task
2404 */
2405 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2406 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2407 adapter->interrupt_event = eicr;
2408 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2409 ixgbe_service_event_schedule(adapter);
2410 return;
2411 }
2412 return;
2413 case ixgbe_mac_X540:
2414 if (!(eicr & IXGBE_EICR_TS))
2415 return;
2416 break;
2417 default:
2418 return;
2419 }
2420
2421 e_crit(drv,
2422 "Network adapter has been stopped because it has over heated. "
2423 "Restart the computer. If the problem persists, "
2424 "power off the system and replace the adapter\n");
2425}
2426
e8e26350
PW		 2427static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2428{
2429 struct ixgbe_hw *hw = &adapter->hw;
2430
73c4b7cd
AD		 2431 if (eicr & IXGBE_EICR_GPI_SDP2) {
2432 /* Clear the interrupt */
2433 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2434 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2435 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2436 ixgbe_service_event_schedule(adapter);
2437 }
73c4b7cd
AD		 2438 }
2439
e8e26350
PW		 2440 if (eicr & IXGBE_EICR_GPI_SDP1) {
2441 /* Clear the interrupt */
2442 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2443 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2444 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2445 ixgbe_service_event_schedule(adapter);
2446 }
e8e26350
PW		 2447 }
2448}
2449
cf8280ee
JB		 2450static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2451{
2452 struct ixgbe_hw *hw = &adapter->hw;
2453
2454 adapter->lsc_int++;
2455 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2456 adapter->link_check_timeout = jiffies;
2457 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2458 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2459 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2460 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2461 }
2462}
2463
fe49f04a
AD		 2464static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2465 u64 qmask)
2466{
2467 u32 mask;
bd508178 2468 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2469
bd508178
AD		 2470 switch (hw->mac.type) {
2471 case ixgbe_mac_82598EB:
fe49f04a 2472 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2473 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2474 break;
2475 case ixgbe_mac_82599EB:
b93a2226 2476 case ixgbe_mac_X540:
9a75a1ac
DS		 2477 case ixgbe_mac_X550:
2478 case ixgbe_mac_X550EM_x:
fe49f04a 2479 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2480 if (mask)
2481 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2482 mask = (qmask >> 32);
bd508178
AD		 2483 if (mask)
2484 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2485 break;
2486 default:
2487 break;
fe49f04a
AD		 2488 }
2489 /* skip the flush */
2490}
2491
2492static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2493 u64 qmask)
fe49f04a
AD		 2494{
2495 u32 mask;
bd508178 2496 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2497
bd508178
AD		 2498 switch (hw->mac.type) {
2499 case ixgbe_mac_82598EB:
fe49f04a 2500 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2501 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2502 break;
2503 case ixgbe_mac_82599EB:
b93a2226 2504 case ixgbe_mac_X540:
9a75a1ac
DS		 2505 case ixgbe_mac_X550:
2506 case ixgbe_mac_X550EM_x:
fe49f04a 2507 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2508 if (mask)
2509 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2510 mask = (qmask >> 32);
bd508178
AD		 2511 if (mask)
2512 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2513 break;
2514 default:
2515 break;
fe49f04a
AD		 2516 }
2517 /* skip the flush */
2518}
2519
021230d4 2520/**
2c4af694
AD		 2521 * ixgbe_irq_enable - Enable default interrupt generation settings
2522 * @adapter: board private structure
021230d4 2523 **/
2c4af694
AD		 2524static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2525 bool flush)
9a799d71 2526{
2c4af694 2527 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2528
2c4af694
AD		 2529 /* don't reenable LSC while waiting for link */
2530 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2531 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2532
2c4af694 2533 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2534 switch (adapter->hw.mac.type) {
2535 case ixgbe_mac_82599EB:
2536 mask |= IXGBE_EIMS_GPI_SDP0;
2537 break;
2538 case ixgbe_mac_X540:
9a75a1ac
DS		 2539 case ixgbe_mac_X550:
2540 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2541 mask |= IXGBE_EIMS_TS;
2542 break;
2543 default:
2544 break;
2545 }
2c4af694
AD		 2546 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2547 mask |= IXGBE_EIMS_GPI_SDP1;
2548 switch (adapter->hw.mac.type) {
2549 case ixgbe_mac_82599EB:
2c4af694
AD		 2550 mask |= IXGBE_EIMS_GPI_SDP1;
2551 mask |= IXGBE_EIMS_GPI_SDP2;
9a75a1ac 2552 /* fall through */
858bc081 2553 case ixgbe_mac_X540:
9a75a1ac
DS		 2554 case ixgbe_mac_X550:
2555 case ixgbe_mac_X550EM_x:
858bc081 2556 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2557 mask |= IXGBE_EIMS_MAILBOX;
2558 break;
2559 default:
2560 break;
9a799d71 2561 }
db0677fa 2562
2c4af694
AD		 2563 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2564 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2565 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2566
2c4af694
AD		 2567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2568 if (queues)
2569 ixgbe_irq_enable_queues(adapter, ~0);
2570 if (flush)
2571 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2572}
2573
2c4af694 2574static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2575{
a65151ba 2576 struct ixgbe_adapter *adapter = data;
9a799d71 2577 struct ixgbe_hw *hw = &adapter->hw;
54037505 2578 u32 eicr;
91281fd3 2579
54037505
DS		 2580 /*
2581 * Workaround for Silicon errata. Use clear-by-write instead
2582 * of clear-by-read. Reading with EICS will return the
2583 * interrupt causes without clearing, which later be done
2584 * with the write to EICR.
2585 */
2586 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2587
2588 /* The lower 16bits of the EICR register are for the queue interrupts
2589 * which should be masked here in order to not accidently clear them if
2590 * the bits are high when ixgbe_msix_other is called. There is a race
2591 * condition otherwise which results in possible performance loss
2592 * especially if the ixgbe_msix_other interrupt is triggering
2593 * consistently (as it would when PPS is turned on for the X540 device)
2594 */
2595 eicr &= 0xFFFF0000;
2596
54037505 2597 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2598
cf8280ee
JB		 2599 if (eicr & IXGBE_EICR_LSC)
2600 ixgbe_check_lsc(adapter);
f0848276 2601
1cdd1ec8
GR		 2602 if (eicr & IXGBE_EICR_MAILBOX)
2603 ixgbe_msg_task(adapter);
efe3d3c8 2604
bd508178
AD		 2605 switch (hw->mac.type) {
2606 case ixgbe_mac_82599EB:
b93a2226 2607 case ixgbe_mac_X540:
9a75a1ac
DS		 2608 case ixgbe_mac_X550:
2609 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2610 if (eicr & IXGBE_EICR_ECC) {
2611 e_info(link, "Received ECC Err, initiating reset\n");
2612 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2613 ixgbe_service_event_schedule(adapter);
2614 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2615 }
c4cf55e5
PWJ		 2616 /* Handle Flow Director Full threshold interrupt */
2617 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2618 int reinit_count = 0;
c4cf55e5 2619 int i;
c4cf55e5 2620 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2621 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2622 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2623 &ring->state))
2624 reinit_count++;
2625 }
2626 if (reinit_count) {
2627 /* no more flow director interrupts until after init */
2628 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2629 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2630 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2631 }
2632 }
f0f9778d 2633 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2634 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2635 break;
2636 default:
2637 break;
c4cf55e5 2638 }
f0848276 2639
bd508178 2640 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2641
db0677fa
JK		 2642 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2643 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2644
7086400d 2645 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2646 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2647 ixgbe_irq_enable(adapter, false, false);
f0848276 2648
9a799d71 2649 return IRQ_HANDLED;
f0848276 2650}
91281fd3 2651
4ff7fb12 2652static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2653{
021230d4 2654 struct ixgbe_q_vector *q_vector = data;
91281fd3 2655
9b471446 2656 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2657
4ff7fb12
AD		 2658 if (q_vector->rx.ring || q_vector->tx.ring)
2659 napi_schedule(&q_vector->napi);
91281fd3 2660
9a799d71 2661 return IRQ_HANDLED;
91281fd3
AD		 2662}
2663
eb01b975
AD		 2664/**
2665 * ixgbe_poll - NAPI Rx polling callback
2666 * @napi: structure for representing this polling device
2667 * @budget: how many packets driver is allowed to clean
2668 *
2669 * This function is used for legacy and MSI, NAPI mode
2670 **/
8af3c33f 2671int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2672{
2673 struct ixgbe_q_vector *q_vector =
2674 container_of(napi, struct ixgbe_q_vector, napi);
2675 struct ixgbe_adapter *adapter = q_vector->adapter;
2676 struct ixgbe_ring *ring;
2677 int per_ring_budget;
2678 bool clean_complete = true;
2679
2680#ifdef CONFIG_IXGBE_DCA
2681 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2682 ixgbe_update_dca(q_vector);
2683#endif
2684
2685 ixgbe_for_each_ring(ring, q_vector->tx)
2686 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2687
5a85e737
ET		 2688 if (!ixgbe_qv_lock_napi(q_vector))
2689 return budget;
2690
eb01b975
AD		 2691 /* attempt to distribute budget to each queue fairly, but don't allow
2692 * the budget to go below 1 because we'll exit polling */
2693 if (q_vector->rx.count > 1)
2694 per_ring_budget = max(budget/q_vector->rx.count, 1);
2695 else
2696 per_ring_budget = budget;
2697
2698 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2699 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2700 per_ring_budget) < per_ring_budget);
eb01b975 2701
5a85e737 2702 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2703 /* If all work not completed, return budget and keep polling */
2704 if (!clean_complete)
2705 return budget;
2706
2707 /* all work done, exit the polling mode */
2708 napi_complete(napi);
2709 if (adapter->rx_itr_setting & 1)
2710 ixgbe_set_itr(q_vector);
2711 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2712 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2713
2714 return 0;
2715}
2716
021230d4
AV		 2717/**
2718 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2719 * @adapter: board private structure
2720 *
2721 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2722 * interrupts from the kernel.
2723 **/
2724static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2725{
2726 struct net_device *netdev = adapter->netdev;
207867f5 2727 int vector, err;
e8e9f696 2728 int ri = 0, ti = 0;
021230d4 2729
49c7ffbe 2730 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2731 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2732 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2733
4ff7fb12 2734 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2735 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2736 "%s-%s-%d", netdev->name, "TxRx", ri++);
2737 ti++;
2738 } else if (q_vector->rx.ring) {
9fe93afd 2739 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2740 "%s-%s-%d", netdev->name, "rx", ri++);
2741 } else if (q_vector->tx.ring) {
9fe93afd 2742 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2743 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2744 } else {
2745 /* skip this unused q_vector */
2746 continue;
32aa77a4 2747 }
207867f5
AD		 2748 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2749 q_vector->name, q_vector);
9a799d71 2750 if (err) {
396e799c 2751 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2752 "Error: %d\n", err);
021230d4 2753 goto free_queue_irqs;
9a799d71 2754 }
207867f5
AD		 2755 /* If Flow Director is enabled, set interrupt affinity */
2756 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2757 /* assign the mask for this irq */
2758 irq_set_affinity_hint(entry->vector,
de88eeeb 2759 &q_vector->affinity_mask);
207867f5 2760 }
9a799d71
AK		 2761 }
2762
021230d4 2763 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2764 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2765 if (err) {
de88eeeb 2766 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2767 goto free_queue_irqs;
9a799d71
AK		 2768 }
2769
9a799d71
AK		 2770 return 0;
2771
021230d4 2772free_queue_irqs:
207867f5
AD		 2773 while (vector) {
2774 vector--;
2775 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2776 NULL);
2777 free_irq(adapter->msix_entries[vector].vector,
2778 adapter->q_vector[vector]);
2779 }
021230d4
AV		 2780 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2781 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2782 kfree(adapter->msix_entries);
2783 adapter->msix_entries = NULL;
9a799d71
AK		 2784 return err;
2785}
2786
2787/**
021230d4 2788 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2789 * @irq: interrupt number
2790 * @data: pointer to a network interface device structure
9a799d71
AK		 2791 **/
2792static irqreturn_t ixgbe_intr(int irq, void *data)
2793{
a65151ba 2794 struct ixgbe_adapter *adapter = data;
9a799d71 2795 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2796 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2797 u32 eicr;
2798
54037505 2799 /*
24ddd967 2800 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2801 * before the read of EICR.
2802 */
2803 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2804
021230d4 2805 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2806 * therefore no explicit interrupt disable is necessary */
021230d4 2807 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2808 if (!eicr) {
6af3b9eb
ET		 2809 /*
2810 * shared interrupt alert!
f47cf66e 2811 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2812 * have disabled interrupts due to EIAM
2813 * finish the workaround of silicon errata on 82598. Unmask
2814 * the interrupt that we masked before the EICR read.
2815 */
2816 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2817 ixgbe_irq_enable(adapter, true, true);
9a799d71 2818 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2819 }
9a799d71 2820
cf8280ee
JB		 2821 if (eicr & IXGBE_EICR_LSC)
2822 ixgbe_check_lsc(adapter);
021230d4 2823
bd508178
AD		 2824 switch (hw->mac.type) {
2825 case ixgbe_mac_82599EB:
e8e26350 2826 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2827 /* Fall through */
2828 case ixgbe_mac_X540:
9a75a1ac
DS		 2829 case ixgbe_mac_X550:
2830 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2831 if (eicr & IXGBE_EICR_ECC) {
2832 e_info(link, "Received ECC Err, initiating reset\n");
2833 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2834 ixgbe_service_event_schedule(adapter);
2835 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2836 }
4f51bf70 2837 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2838 break;
2839 default:
2840 break;
2841 }
e8e26350 2842
0befdb3e 2843 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2844 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2845 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2846
b9f6ed2b
AD		 2847 /* would disable interrupts here but EIAM disabled it */
2848 napi_schedule(&q_vector->napi);
9a799d71 2849
6af3b9eb
ET		 2850 /*
2851 * re-enable link(maybe) and non-queue interrupts, no flush.
2852 * ixgbe_poll will re-enable the queue interrupts
2853 */
6af3b9eb
ET		 2854 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2855 ixgbe_irq_enable(adapter, false, false);
2856
9a799d71
AK		 2857 return IRQ_HANDLED;
2858}
2859
2860/**
2861 * ixgbe_request_irq - initialize interrupts
2862 * @adapter: board private structure
2863 *
2864 * Attempts to configure interrupts using the best available
2865 * capabilities of the hardware and kernel.
2866 **/
021230d4 2867static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2868{
2869 struct net_device *netdev = adapter->netdev;
021230d4 2870 int err;
9a799d71 2871
4cc6df29 2872 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2873 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2874 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2875 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2876 netdev->name, adapter);
4cc6df29 2877 else
a0607fd3 2878 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2879 netdev->name, adapter);
9a799d71 2880
de88eeeb 2881 if (err)
396e799c 2882 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2883
9a799d71
AK		 2884 return err;
2885}
2886
2887static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2888{
49c7ffbe 2889 int vector;
9a799d71 2890
49c7ffbe
AD		 2891 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2892 free_irq(adapter->pdev->irq, adapter);
2893 return;
2894 }
4cc6df29 2895
49c7ffbe
AD		 2896 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2897 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2898 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2899
49c7ffbe
AD		 2900 /* free only the irqs that were actually requested */
2901 if (!q_vector->rx.ring && !q_vector->tx.ring)
2902 continue;
207867f5 2903
49c7ffbe
AD		 2904 /* clear the affinity_mask in the IRQ descriptor */
2905 irq_set_affinity_hint(entry->vector, NULL);
2906
2907 free_irq(entry->vector, q_vector);
9a799d71 2908 }
49c7ffbe
AD		 2909
2910 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2911}
2912
22d5a71b
JB		 2913/**
2914 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2915 * @adapter: board private structure
2916 **/
2917static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2918{
bd508178
AD		 2919 switch (adapter->hw.mac.type) {
2920 case ixgbe_mac_82598EB:
835462fc 2921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2922 break;
2923 case ixgbe_mac_82599EB:
b93a2226 2924 case ixgbe_mac_X540:
9a75a1ac
DS		 2925 case ixgbe_mac_X550:
2926 case ixgbe_mac_X550EM_x:
835462fc
NS		 2927 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2928 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2929 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2930 break;
2931 default:
2932 break;
22d5a71b
JB		 2933 }
2934 IXGBE_WRITE_FLUSH(&adapter->hw);
2935 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2936 int vector;
2937
2938 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2939 synchronize_irq(adapter->msix_entries[vector].vector);
2940
2941 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2942 } else {
2943 synchronize_irq(adapter->pdev->irq);
2944 }
2945}
2946
9a799d71
AK		 2947/**
2948 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2949 *
2950 **/
2951static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2952{
d5bf4f67 2953 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2954
d5bf4f67 2955 ixgbe_write_eitr(q_vector);
9a799d71 2956
e8e26350
PW		 2957 ixgbe_set_ivar(adapter, 0, 0, 0);
2958 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2959
396e799c 2960 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2961}
2962
43e69bf0
AD		 2963/**
2964 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2965 * @adapter: board private structure
2966 * @ring: structure containing ring specific data
2967 *
2968 * Configure the Tx descriptor ring after a reset.
2969 **/
84418e3b
AD		 2970void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2971 struct ixgbe_ring *ring)
43e69bf0
AD		 2972{
2973 struct ixgbe_hw *hw = &adapter->hw;
2974 u64 tdba = ring->dma;
2f1860b8 2975 int wait_loop = 10;
b88c6de2 2976 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2977 u8 reg_idx = ring->reg_idx;
43e69bf0 2978
2f1860b8 2979 /* disable queue to avoid issues while updating state */
b88c6de2 2980 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2981 IXGBE_WRITE_FLUSH(hw);
2982
43e69bf0 2983 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2984 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2985 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2986 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2987 ring->count * sizeof(union ixgbe_adv_tx_desc));
2988 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2989 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 2990 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 2991
b88c6de2
AD		 2992 /*
2993 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 2994 * higher than 1 when:
2995 * - ITR is 0 as it could cause false TX hangs
2996 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 2997 *
2998 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2999 * to or less than the number of on chip descriptors, which is
3000 * currently 40.
3001 */
67da097e 3002 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3003 txdctl |= (1 << 16); /* WTHRESH = 1 */
3004 else
3005 txdctl |= (8 << 16); /* WTHRESH = 8 */
3006
e954b374
AD		 3007 /*
3008 * Setting PTHRESH to 32 both improves performance
3009 * and avoids a TX hang with DFP enabled
3010 */
b88c6de2
AD		 3011 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3012 32; /* PTHRESH = 32 */
2f1860b8
AD		 3013
3014 /* reinitialize flowdirector state */
39cb681b 3015 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3016 ring->atr_sample_rate = adapter->atr_sample_rate;
3017 ring->atr_count = 0;
3018 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3019 } else {
3020 ring->atr_sample_rate = 0;
3021 }
2f1860b8 3022
fd786b7b
AD		 3023 /* initialize XPS */
3024 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3025 struct ixgbe_q_vector *q_vector = ring->q_vector;
3026
3027 if (q_vector)
2a47fa45 3028 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3029 &q_vector->affinity_mask,
3030 ring->queue_index);
3031 }
3032
c84d324c
JF		 3033 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3034
2f1860b8 3035 /* enable queue */
2f1860b8
AD		 3036 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3037
3038 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3039 if (hw->mac.type == ixgbe_mac_82598EB &&
3040 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3041 return;
3042
3043 /* poll to verify queue is enabled */
3044 do {
032b4325 3045 usleep_range(1000, 2000);
2f1860b8
AD		 3046 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3047 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3048 if (!wait_loop)
3049 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3050}
3051
120ff942
AD		 3052static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3053{
3054 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3055 u32 rttdcs, mtqc;
8b1c0b24 3056 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3057
3058 if (hw->mac.type == ixgbe_mac_82598EB)
3059 return;
3060
3061 /* disable the arbiter while setting MTQC */
3062 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3063 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3064 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3065
3066 /* set transmit pool layout */
671c0adb
AD		 3067 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3068 mtqc = IXGBE_MTQC_VT_ENA;
3069 if (tcs > 4)
3070 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3071 else if (tcs > 1)
3072 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3073 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3074 mtqc |= IXGBE_MTQC_32VF;
3075 else
3076 mtqc |= IXGBE_MTQC_64VF;
3077 } else {
3078 if (tcs > 4)
3079 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3080 else if (tcs > 1)
3081 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3082 else
671c0adb
AD		 3083 mtqc = IXGBE_MTQC_64Q_1PB;
3084 }
120ff942 3085
671c0adb 3086 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3087
671c0adb
AD		 3088 /* Enable Security TX Buffer IFG for multiple pb */
3089 if (tcs) {
3090 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3091 sectx |= IXGBE_SECTX_DCB;
3092 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3093 }
3094
3095 /* re-enable the arbiter */
3096 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3097 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3098}
3099
9a799d71 3100/**
3a581073 3101 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3102 * @adapter: board private structure
3103 *
3104 * Configure the Tx unit of the MAC after a reset.
3105 **/
3106static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3107{
2f1860b8
AD		 3108 struct ixgbe_hw *hw = &adapter->hw;
3109 u32 dmatxctl;
43e69bf0 3110 u32 i;
9a799d71 3111
2f1860b8
AD		 3112 ixgbe_setup_mtqc(adapter);
3113
3114 if (hw->mac.type != ixgbe_mac_82598EB) {
3115 /* DMATXCTL.EN must be before Tx queues are enabled */
3116 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3117 dmatxctl |= IXGBE_DMATXCTL_TE;
3118 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3119 }
3120
9a799d71 3121 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3122 for (i = 0; i < adapter->num_tx_queues; i++)
3123 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3124}
3125
3ebe8fde
AD		 3126static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3127 struct ixgbe_ring *ring)
3128{
3129 struct ixgbe_hw *hw = &adapter->hw;
3130 u8 reg_idx = ring->reg_idx;
3131 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3132
3133 srrctl |= IXGBE_SRRCTL_DROP_EN;
3134
3135 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3136}
3137
3138static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3139 struct ixgbe_ring *ring)
3140{
3141 struct ixgbe_hw *hw = &adapter->hw;
3142 u8 reg_idx = ring->reg_idx;
3143 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3144
3145 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3146
3147 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3148}
3149
3150#ifdef CONFIG_IXGBE_DCB
3151void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3152#else
3153static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3154#endif
3155{
3156 int i;
3157 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3158
3159 if (adapter->ixgbe_ieee_pfc)
3160 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3161
3162 /*
3163 * We should set the drop enable bit if:
3164 * SR-IOV is enabled
3165 * or
3166 * Number of Rx queues > 1 and flow control is disabled
3167 *
3168 * This allows us to avoid head of line blocking for security
3169 * and performance reasons.
3170 */
3171 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3172 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3173 for (i = 0; i < adapter->num_rx_queues; i++)
3174 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3175 } else {
3176 for (i = 0; i < adapter->num_rx_queues; i++)
3177 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3178 }
3179}
3180
e8e26350 3181#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3182
a6616b42 3183static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3184 struct ixgbe_ring *rx_ring)
cc41ac7c 3185{
45e9baa5 3186 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3187 u32 srrctl;
bf29ee6c 3188 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3189
45e9baa5
AD		 3190 if (hw->mac.type == ixgbe_mac_82598EB) {
3191 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3192
45e9baa5
AD		 3193 /*
3194 * if VMDq is not active we must program one srrctl register
3195 * per RSS queue since we have enabled RDRXCTL.MVMEN
3196 */
3197 reg_idx &= mask;
3198 }
cc41ac7c 3199
45e9baa5
AD		 3200 /* configure header buffer length, needed for RSC */
3201 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3202
45e9baa5 3203 /* configure the packet buffer length */
f800326d 3204 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3205
3206 /* configure descriptor type */
f800326d 3207 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3208
45e9baa5 3209 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3210}
9a799d71 3211
d1b849b9 3212static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed)
0cefafad 3213{
05abb126 3214 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3215 u32 reta = 0;
05abb126 3216 int i, j;
671c0adb
AD		 3217 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3218
671c0adb
AD		 3219 /*
3220 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3221 * make full use of any rings they may have. We will use the
3222 * PSRTYPE register to control how many rings we use within the PF.
3223 */
3224 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3225 rss_i = 2;
0cefafad 3226
05abb126
AD		 3227 /* Fill out hash function seeds */
3228 for (i = 0; i < 10; i++)
3229 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3230
3231 /* Fill out redirection table */
3232 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3233 if (j == rss_i)
05abb126
AD		 3234 j = 0;
3235 /* reta = 4-byte sliding window of
3236 * 0x00..(indices-1)(indices-1)00..etc. */
3237 reta = (reta << 8) | (j * 0x11);
3238 if ((i & 3) == 3)
3239 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3240 }
d1b849b9
DS		 3241}
3242
3243static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3244{
3245 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3246 u32 mrqc = 0, rss_field = 0;
9913c61c 3247 u32 rss_key[10];
d1b849b9 3248 u32 rxcsum;
0cefafad 3249
05abb126
AD		 3250 /* Disable indicating checksum in descriptor, enables RSS hash */
3251 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3252 rxcsum |= IXGBE_RXCSUM_PCSD;
3253 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3254
671c0adb 3255 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3256 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3257 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3258 } else {
671c0adb
AD		 3259 u8 tcs = netdev_get_num_tc(adapter->netdev);
3260
3261 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3262 if (tcs > 4)
3263 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3264 else if (tcs > 1)
3265 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3266 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3267 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3268 else
671c0adb
AD		 3269 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3270 } else {
3271 if (tcs > 4)
8b1c0b24 3272 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3273 else if (tcs > 1)
3274 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3275 else
3276 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3277 }
0cefafad
JB		 3278 }
3279
05abb126 3280 /* Perform hash on these packet types */
d1b849b9
DS		 3281 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3282 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3283 IXGBE_MRQC_RSS_FIELD_IPV6 |
3284 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3285
ef6afc0c 3286 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3287 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3288 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3289 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3290
9913c61c
ED		 3291 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3292 ixgbe_setup_reta(adapter, rss_key);
d1b849b9 3293 mrqc |= rss_field;
05abb126 3294 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3295}
3296
bb5a9ad2
NS		 3297/**
3298 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3299 * @adapter: address of board private structure
3300 * @index: index of ring to set
bb5a9ad2 3301 **/
082757af 3302static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3303 struct ixgbe_ring *ring)
bb5a9ad2 3304{
bb5a9ad2 3305 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3306 u32 rscctrl;
bf29ee6c 3307 u8 reg_idx = ring->reg_idx;
7367096a 3308
7d637bcc 3309 if (!ring_is_rsc_enabled(ring))
7367096a 3310 return;
bb5a9ad2 3311
7367096a 3312 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3313 rscctrl |= IXGBE_RSCCTL_RSCEN;
3314 /*
3315 * we must limit the number of descriptors so that the
3316 * total size of max desc * buf_len is not greater
642c680e 3317 * than 65536
bb5a9ad2 3318 */
f800326d 3319 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3320 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3321}
3322
9e10e045
AD		 3323#define IXGBE_MAX_RX_DESC_POLL 10
3324static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3325 struct ixgbe_ring *ring)
3326{
3327 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3328 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3329 u32 rxdctl;
bf29ee6c 3330 u8 reg_idx = ring->reg_idx;
9e10e045 3331
b0483c8f
MR		 3332 if (ixgbe_removed(hw->hw_addr))
3333 return;
9e10e045
AD		 3334 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3335 if (hw->mac.type == ixgbe_mac_82598EB &&
3336 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3337 return;
3338
3339 do {
032b4325 3340 usleep_range(1000, 2000);
9e10e045
AD		 3341 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3342 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3343
3344 if (!wait_loop) {
3345 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3346 "the polling period\n", reg_idx);
3347 }
3348}
3349
2d39d576
YZ		 3350void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3351 struct ixgbe_ring *ring)
3352{
3353 struct ixgbe_hw *hw = &adapter->hw;
3354 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3355 u32 rxdctl;
3356 u8 reg_idx = ring->reg_idx;
3357
b0483c8f
MR		 3358 if (ixgbe_removed(hw->hw_addr))
3359 return;
2d39d576
YZ		 3360 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3361 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3362
3363 /* write value back with RXDCTL.ENABLE bit cleared */
3364 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3365
3366 if (hw->mac.type == ixgbe_mac_82598EB &&
3367 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3368 return;
3369
3370 /* the hardware may take up to 100us to really disable the rx queue */
3371 do {
3372 udelay(10);
3373 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3374 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3375
3376 if (!wait_loop) {
3377 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3378 "the polling period\n", reg_idx);
3379 }
3380}
3381
84418e3b
AD		 3382void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3383 struct ixgbe_ring *ring)
acd37177
AD		 3384{
3385 struct ixgbe_hw *hw = &adapter->hw;
3386 u64 rdba = ring->dma;
9e10e045 3387 u32 rxdctl;
bf29ee6c 3388 u8 reg_idx = ring->reg_idx;
acd37177 3389
9e10e045
AD		 3390 /* disable queue to avoid issues while updating state */
3391 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3392 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3393
acd37177
AD		 3394 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3395 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3396 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3397 ring->count * sizeof(union ixgbe_adv_rx_desc));
3398 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3399 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3400 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3401
3402 ixgbe_configure_srrctl(adapter, ring);
3403 ixgbe_configure_rscctl(adapter, ring);
3404
3405 if (hw->mac.type == ixgbe_mac_82598EB) {
3406 /*
3407 * enable cache line friendly hardware writes:
3408 * PTHRESH=32 descriptors (half the internal cache),
3409 * this also removes ugly rx_no_buffer_count increment
3410 * HTHRESH=4 descriptors (to minimize latency on fetch)
3411 * WTHRESH=8 burst writeback up to two cache lines
3412 */
3413 rxdctl &= ~0x3FFFFF;
3414 rxdctl |= 0x080420;
3415 }
3416
3417 /* enable receive descriptor ring */
3418 rxdctl |= IXGBE_RXDCTL_ENABLE;
3419 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3420
3421 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3422 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3423}
3424
48654521
AD		 3425static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3426{
3427 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3428 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3429 u16 pool;
48654521
AD		 3430
3431 /* PSRTYPE must be initialized in non 82598 adapters */
3432 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3433 IXGBE_PSRTYPE_UDPHDR |
3434 IXGBE_PSRTYPE_IPV4HDR |
48654521 3435 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3436 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3437
3438 if (hw->mac.type == ixgbe_mac_82598EB)
3439 return;
3440
fbe7ca7f
AD		 3441 if (rss_i > 3)
3442 psrtype |= 2 << 29;
3443 else if (rss_i > 1)
3444 psrtype |= 1 << 29;
48654521 3445
2a47fa45
JF		 3446 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3447 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3448}
3449
f5b4a52e
AD		 3450static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3451{
3452 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3453 u32 reg_offset, vf_shift;
435b19f6 3454 u32 gcr_ext, vmdctl;
de4c7f65 3455 int i;
f5b4a52e
AD		 3456
3457 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3458 return;
3459
3460 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3461 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3462 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3463 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3464 vmdctl |= IXGBE_VT_CTL_REPLEN;
3465 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3466
1d9c0bfd
AD		 3467 vf_shift = VMDQ_P(0) % 32;
3468 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3469
3470 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3471 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3472 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3473 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3474 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3475 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3476 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3477
3478 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3479 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3480
3481 /*
3482 * Set up VF register offsets for selected VT Mode,
3483 * i.e. 32 or 64 VFs for SR-IOV
3484 */
73079ea0
AD		 3485 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3486 case IXGBE_82599_VMDQ_8Q_MASK:
3487 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3488 break;
3489 case IXGBE_82599_VMDQ_4Q_MASK:
3490 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3491 break;
3492 default:
3493 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3494 break;
3495 }
3496
f5b4a52e
AD		 3497 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3498
435b19f6 3499
a985b6c3 3500 /* Enable MAC Anti-Spoofing */
435b19f6 3501 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3502 adapter->num_vfs);
de4c7f65
GR		 3503 /* For VFs that have spoof checking turned off */
3504 for (i = 0; i < adapter->num_vfs; i++) {
3505 if (!adapter->vfinfo[i].spoofchk_enabled)
3506 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3507 }
f5b4a52e
AD		 3508}
3509
477de6ed 3510static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3511{
9a799d71
AK		 3512 struct ixgbe_hw *hw = &adapter->hw;
3513 struct net_device *netdev = adapter->netdev;
3514 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3515 struct ixgbe_ring *rx_ring;
3516 int i;
3517 u32 mhadd, hlreg0;
48654521 3518
63f39bd1 3519#ifdef IXGBE_FCOE
477de6ed
AD		 3520 /* adjust max frame to be able to do baby jumbo for FCoE */
3521 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3522 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3523 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3524
477de6ed 3525#endif /* IXGBE_FCOE */
872844dd
AD		 3526
3527 /* adjust max frame to be at least the size of a standard frame */
3528 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3529 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3530
477de6ed
AD		 3531 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3532 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3533 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3534 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3535
3536 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3537 }
3538
3539 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3540 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3541 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3542 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3543
0cefafad
JB		 3544 /*
3545 * Setup the HW Rx Head and Tail Descriptor Pointers and
3546 * the Base and Length of the Rx Descriptor Ring
3547 */
9a799d71 3548 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3549 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3550 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3551 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3552 else
7d637bcc 3553 clear_ring_rsc_enabled(rx_ring);
477de6ed 3554 }
477de6ed
AD		 3555}
3556
7367096a
AD		 3557static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3558{
3559 struct ixgbe_hw *hw = &adapter->hw;
3560 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3561
3562 switch (hw->mac.type) {
9a75a1ac
DS		 3563 case ixgbe_mac_X550:
3564 case ixgbe_mac_X550EM_x:
7367096a
AD		 3565 case ixgbe_mac_82598EB:
3566 /*
3567 * For VMDq support of different descriptor types or
3568 * buffer sizes through the use of multiple SRRCTL
3569 * registers, RDRXCTL.MVMEN must be set to 1
3570 *
3571 * also, the manual doesn't mention it clearly but DCA hints
3572 * will only use queue 0's tags unless this bit is set. Side
3573 * effects of setting this bit are only that SRRCTL must be
3574 * fully programmed [0..15]
3575 */
3576 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3577 break;
3578 case ixgbe_mac_82599EB:
b93a2226 3579 case ixgbe_mac_X540:
7367096a
AD		 3580 /* Disable RSC for ACK packets */
3581 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3582 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3583 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3584 /* hardware requires some bits to be set by default */
3585 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3586 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3587 break;
3588 default:
3589 /* We should do nothing since we don't know this hardware */
3590 return;
3591 }
3592
3593 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3594}
3595
477de6ed
AD		 3596/**
3597 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3598 * @adapter: board private structure
3599 *
3600 * Configure the Rx unit of the MAC after a reset.
3601 **/
3602static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3603{
3604 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3605 int i;
6dcc28b9 3606 u32 rxctrl, rfctl;
477de6ed
AD		 3607
3608 /* disable receives while setting up the descriptors */
3609 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3610 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3611
3612 ixgbe_setup_psrtype(adapter);
7367096a 3613 ixgbe_setup_rdrxctl(adapter);
477de6ed 3614
6dcc28b9
JK		 3615 /* RSC Setup */
3616 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3617 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3618 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3619 rfctl |= IXGBE_RFCTL_RSC_DIS;
3620 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3621
9e10e045 3622 /* Program registers for the distribution of queues */
f5b4a52e 3623 ixgbe_setup_mrqc(adapter);
f5b4a52e 3624
477de6ed
AD		 3625 /* set_rx_buffer_len must be called before ring initialization */
3626 ixgbe_set_rx_buffer_len(adapter);
3627
3628 /*
3629 * Setup the HW Rx Head and Tail Descriptor Pointers and
3630 * the Base and Length of the Rx Descriptor Ring
3631 */
9e10e045
AD		 3632 for (i = 0; i < adapter->num_rx_queues; i++)
3633 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3634
9e10e045
AD		 3635 /* disable drop enable for 82598 parts */
3636 if (hw->mac.type == ixgbe_mac_82598EB)
3637 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3638
3639 /* enable all receives */
3640 rxctrl |= IXGBE_RXCTRL_RXEN;
3641 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3642}
3643
80d5c368
PM		 3644static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3645 __be16 proto, u16 vid)
068c89b0
DS		 3646{
3647 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3648 struct ixgbe_hw *hw = &adapter->hw;
3649
3650 /* add VID to filter table */
1d9c0bfd 3651 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3652 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3653
3654 return 0;
068c89b0
DS		 3655}
3656
80d5c368
PM		 3657static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3658 __be16 proto, u16 vid)
068c89b0
DS		 3659{
3660 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3661 struct ixgbe_hw *hw = &adapter->hw;
3662
068c89b0 3663 /* remove VID from filter table */
1d9c0bfd 3664 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3665 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3666
3667 return 0;
068c89b0
DS		 3668}
3669
f62bbb5e
JG		 3670/**
3671 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3672 * @adapter: driver data
3673 */
3674static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3675{
3676 struct ixgbe_hw *hw = &adapter->hw;
3677 u32 vlnctrl;
5f6c0181
JB		 3678 int i, j;
3679
3680 switch (hw->mac.type) {
3681 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3682 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3683 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3684 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3685 break;
3686 case ixgbe_mac_82599EB:
b93a2226 3687 case ixgbe_mac_X540:
9a75a1ac
DS		 3688 case ixgbe_mac_X550:
3689 case ixgbe_mac_X550EM_x:
5f6c0181 3690 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3691 struct ixgbe_ring *ring = adapter->rx_ring[i];
3692
3693 if (ring->l2_accel_priv)
3694 continue;
3695 j = ring->reg_idx;
5f6c0181
JB		 3696 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3697 vlnctrl &= ~IXGBE_RXDCTL_VME;
3698 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3699 }
3700 break;
3701 default:
3702 break;
3703 }
3704}
3705
3706/**
f62bbb5e 3707 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3708 * @adapter: driver data
3709 */
f62bbb5e 3710static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3711{
3712 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3713 u32 vlnctrl;
5f6c0181
JB		 3714 int i, j;
3715
3716 switch (hw->mac.type) {
3717 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3718 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3719 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3720 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3721 break;
3722 case ixgbe_mac_82599EB:
b93a2226 3723 case ixgbe_mac_X540:
9a75a1ac
DS		 3724 case ixgbe_mac_X550:
3725 case ixgbe_mac_X550EM_x:
5f6c0181 3726 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3727 struct ixgbe_ring *ring = adapter->rx_ring[i];
3728
3729 if (ring->l2_accel_priv)
3730 continue;
3731 j = ring->reg_idx;
5f6c0181
JB		 3732 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3733 vlnctrl |= IXGBE_RXDCTL_VME;
3734 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3735 }
3736 break;
3737 default:
3738 break;
3739 }
3740}
3741
9a799d71
AK		 3742static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3743{
f62bbb5e 3744 u16 vid;
9a799d71 3745
80d5c368 3746 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3747
3748 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3749 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3750}
3751
b335e75b
JK		 3752/**
3753 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3754 * @netdev: network interface device structure
3755 *
3756 * Writes multicast address list to the MTA hash table.
3757 * Returns: -ENOMEM on failure
3758 * 0 on no addresses written
3759 * X on writing X addresses to MTA
3760 **/
3761static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3762{
3763 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3764 struct ixgbe_hw *hw = &adapter->hw;
3765
3766 if (!netif_running(netdev))
3767 return 0;
3768
3769 if (hw->mac.ops.update_mc_addr_list)
3770 hw->mac.ops.update_mc_addr_list(hw, netdev);
3771 else
3772 return -ENOMEM;
3773
3774#ifdef CONFIG_PCI_IOV
5d7daa35 3775 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3776#endif
3777
3778 return netdev_mc_count(netdev);
3779}
3780
5d7daa35
JK		 3781#ifdef CONFIG_PCI_IOV
3782void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3783{
3784 struct ixgbe_hw *hw = &adapter->hw;
3785 int i;
3786 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3787 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3788 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3789 adapter->mac_table[i].queue,
3790 IXGBE_RAH_AV);
3791 else
3792 hw->mac.ops.clear_rar(hw, i);
3793
3794 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3795 }
3796}
3797#endif
3798
3799static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3800{
3801 struct ixgbe_hw *hw = &adapter->hw;
3802 int i;
3803 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3804 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3805 if (adapter->mac_table[i].state &
3806 IXGBE_MAC_STATE_IN_USE)
3807 hw->mac.ops.set_rar(hw, i,
3808 adapter->mac_table[i].addr,
3809 adapter->mac_table[i].queue,
3810 IXGBE_RAH_AV);
3811 else
3812 hw->mac.ops.clear_rar(hw, i);
3813
3814 adapter->mac_table[i].state &=
3815 ~(IXGBE_MAC_STATE_MODIFIED);
3816 }
3817 }
3818}
3819
3820static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3821{
3822 int i;
3823 struct ixgbe_hw *hw = &adapter->hw;
3824
3825 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3826 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3827 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3828 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3829 adapter->mac_table[i].queue = 0;
3830 }
3831 ixgbe_sync_mac_table(adapter);
3832}
3833
3834static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3835{
3836 struct ixgbe_hw *hw = &adapter->hw;
3837 int i, count = 0;
3838
3839 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3840 if (adapter->mac_table[i].state == 0)
3841 count++;
3842 }
3843 return count;
3844}
3845
3846/* this function destroys the first RAR entry */
3847static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3848 u8 *addr)
3849{
3850 struct ixgbe_hw *hw = &adapter->hw;
3851
3852 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3853 adapter->mac_table[0].queue = VMDQ_P(0);
3854 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3855 IXGBE_MAC_STATE_IN_USE);
3856 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3857 adapter->mac_table[0].queue,
3858 IXGBE_RAH_AV);
3859}
3860
3861int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3862{
3863 struct ixgbe_hw *hw = &adapter->hw;
3864 int i;
3865
3866 if (is_zero_ether_addr(addr))
3867 return -EINVAL;
3868
3869 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3870 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3871 continue;
3872 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3873 IXGBE_MAC_STATE_IN_USE);
3874 ether_addr_copy(adapter->mac_table[i].addr, addr);
3875 adapter->mac_table[i].queue = queue;
3876 ixgbe_sync_mac_table(adapter);
3877 return i;
3878 }
3879 return -ENOMEM;
3880}
3881
3882int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3883{
3884 /* search table for addr, if found, set to 0 and sync */
3885 int i;
3886 struct ixgbe_hw *hw = &adapter->hw;
3887
3888 if (is_zero_ether_addr(addr))
3889 return -EINVAL;
3890
3891 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3892 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3893 adapter->mac_table[i].queue == queue) {
3894 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3895 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3896 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3897 adapter->mac_table[i].queue = 0;
3898 ixgbe_sync_mac_table(adapter);
3899 return 0;
3900 }
3901 }
3902 return -ENOMEM;
3903}
2850062a
AD		 3904/**
3905 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3906 * @netdev: network interface device structure
3907 *
3908 * Writes unicast address list to the RAR table.
3909 * Returns: -ENOMEM on failure/insufficient address space
3910 * 0 on no addresses written
3911 * X on writing X addresses to the RAR table
3912 **/
5d7daa35 3913static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 3914{
3915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 3916 int count = 0;
3917
3918 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 3919 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 3920 return -ENOMEM;
3921
95447461 3922 if (!netdev_uc_empty(netdev)) {
2850062a 3923 struct netdev_hw_addr *ha;
2850062a 3924 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 3925 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
3926 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 3927 count++;
3928 }
3929 }
2850062a
AD		 3930 return count;
3931}
3932
9a799d71 3933/**
2c5645cf 3934 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3935 * @netdev: network interface device structure
3936 *
2c5645cf
CL		 3937 * The set_rx_method entry point is called whenever the unicast/multicast
3938 * address list or the network interface flags are updated. This routine is
3939 * responsible for configuring the hardware for proper unicast, multicast and
3940 * promiscuous mode.
9a799d71 3941 **/
7f870475 3942void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3943{
3944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3945 struct ixgbe_hw *hw = &adapter->hw;
2850062a 3946 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 3947 u32 vlnctrl;
2850062a 3948 int count;
9a799d71
AK		 3949
3950 /* Check for Promiscuous and All Multicast modes */
9a799d71 3951 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 3952 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 3953
f5dc442b 3954 /* set all bits that we expect to always be set */
3f2d1c0f 3955 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3956 fctrl |= IXGBE_FCTRL_BAM;
3957 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3958 fctrl |= IXGBE_FCTRL_PMCF;
3959
2850062a
AD		 3960 /* clear the bits we are changing the status of */
3961 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 3962 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 3963 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3964 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3965 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 3966 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 3967 /* Only disable hardware filter vlans in promiscuous mode
3968 * if SR-IOV and VMDQ are disabled - otherwise ensure
3969 * that hardware VLAN filters remain enabled.
3970 */
4556dc59
VY		 3971 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3972 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 3973 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 3974 } else {
746b9f02
PM		 3975 if (netdev->flags & IFF_ALLMULTI) {
3976 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3977 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3978 }
a9b8943e 3979 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 3980 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3981 }
3982
3983 /*
3984 * Write addresses to available RAR registers, if there is not
3985 * sufficient space to store all the addresses then enable
3986 * unicast promiscuous mode
3987 */
5d7daa35 3988 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 3989 if (count < 0) {
3990 fctrl |= IXGBE_FCTRL_UPE;
3991 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3992 }
3993
cf78959c
ET		 3994 /* Write addresses to the MTA, if the attempt fails
3995 * then we should just turn on promiscuous mode so
3996 * that we can at least receive multicast traffic
3997 */
b335e75b
JK		 3998 count = ixgbe_write_mc_addr_list(netdev);
3999 if (count < 0) {
4000 fctrl |= IXGBE_FCTRL_MPE;
4001 vmolr |= IXGBE_VMOLR_MPE;
4002 } else if (count) {
4003 vmolr |= IXGBE_VMOLR_ROMPE;
4004 }
1d9c0bfd
AD		 4005
4006 if (hw->mac.type != ixgbe_mac_82598EB) {
4007 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4008 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4009 IXGBE_VMOLR_ROPE);
1d9c0bfd 4010 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4011 }
4012
3f2d1c0f
BG		 4013 /* This is useful for sniffing bad packets. */
4014 if (adapter->netdev->features & NETIF_F_RXALL) {
4015 /* UPE and MPE will be handled by normal PROMISC logic
4016 * in e1000e_set_rx_mode */
4017 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4018 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4019 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4020
4021 fctrl &= ~(IXGBE_FCTRL_DPF);
4022 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4023 }
4024
a9b8943e 4025 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4026 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4027
f646968f 4028 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4029 ixgbe_vlan_strip_enable(adapter);
4030 else
4031 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4032}
4033
021230d4
AV		 4034static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4035{
4036 int q_idx;
021230d4 4037
5a85e737
ET		 4038 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4039 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4040 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4041 }
021230d4
AV		 4042}
4043
4044static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4045{
4046 int q_idx;
021230d4 4047
5a85e737 4048 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4049 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4050 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4051 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4052 usleep_range(1000, 20000);
5a85e737
ET		 4053 }
4054 }
021230d4
AV		 4055}
4056
7a6b6f51 4057#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4058/**
2f90b865
AD		 4059 * ixgbe_configure_dcb - Configure DCB hardware
4060 * @adapter: ixgbe adapter struct
4061 *
4062 * This is called by the driver on open to configure the DCB hardware.
4063 * This is also called by the gennetlink interface when reconfiguring
4064 * the DCB state.
4065 */
4066static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4067{
4068 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4069 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4070
67ebd791
AD		 4071 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4072 if (hw->mac.type == ixgbe_mac_82598EB)
4073 netif_set_gso_max_size(adapter->netdev, 65536);
4074 return;
4075 }
4076
4077 if (hw->mac.type == ixgbe_mac_82598EB)
4078 netif_set_gso_max_size(adapter->netdev, 32768);
4079
971060b1 4080#ifdef IXGBE_FCOE
b120818e
JF		 4081 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4082 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4083#endif
b120818e
JF		 4084
4085 /* reconfigure the hardware */
4086 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4087 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4088 DCB_TX_CONFIG);
4089 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4090 DCB_RX_CONFIG);
4091 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4092 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4093 ixgbe_dcb_hw_ets(&adapter->hw,
4094 adapter->ixgbe_ieee_ets,
4095 max_frame);
4096 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4097 adapter->ixgbe_ieee_pfc->pfc_en,
4098 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4099 }
8187cd48
JF		 4100
4101 /* Enable RSS Hash per TC */
4102 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4103 u32 msb = 0;
4104 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4105
d411a936
AD		 4106 while (rss_i) {
4107 msb++;
4108 rss_i >>= 1;
4109 }
8187cd48 4110
4ae63730
AD		 4111 /* write msb to all 8 TCs in one write */
4112 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4113 }
2f90b865 4114}
9da712d2
JF		 4115#endif
4116
4117/* Additional bittime to account for IXGBE framing */
4118#define IXGBE_ETH_FRAMING 20
4119
49ce9c2c 4120/**
9da712d2
JF		 4121 * ixgbe_hpbthresh - calculate high water mark for flow control
4122 *
4123 * @adapter: board private structure to calculate for
49ce9c2c 4124 * @pb: packet buffer to calculate
9da712d2
JF		 4125 */
4126static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4127{
4128 struct ixgbe_hw *hw = &adapter->hw;
4129 struct net_device *dev = adapter->netdev;
4130 int link, tc, kb, marker;
4131 u32 dv_id, rx_pba;
4132
4133 /* Calculate max LAN frame size */
4134 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4135
4136#ifdef IXGBE_FCOE
4137 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4138 if ((dev->features & NETIF_F_FCOE_MTU) &&
4139 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4140 (pb == ixgbe_fcoe_get_tc(adapter)))
4141 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4142#endif
e5776620 4143
9da712d2
JF		 4144 /* Calculate delay value for device */
4145 switch (hw->mac.type) {
4146 case ixgbe_mac_X540:
9a75a1ac
DS		 4147 case ixgbe_mac_X550:
4148 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4149 dv_id = IXGBE_DV_X540(link, tc);
4150 break;
4151 default:
4152 dv_id = IXGBE_DV(link, tc);
4153 break;
4154 }
4155
4156 /* Loopback switch introduces additional latency */
4157 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4158 dv_id += IXGBE_B2BT(tc);
4159
4160 /* Delay value is calculated in bit times convert to KB */
4161 kb = IXGBE_BT2KB(dv_id);
4162 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4163
4164 marker = rx_pba - kb;
4165
4166 /* It is possible that the packet buffer is not large enough
4167 * to provide required headroom. In this case throw an error
4168 * to user and a do the best we can.
4169 */
4170 if (marker < 0) {
4171 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4172 "headroom to support flow control."
4173 "Decrease MTU or number of traffic classes\n", pb);
4174 marker = tc + 1;
4175 }
4176
4177 return marker;
4178}
4179
49ce9c2c 4180/**
9da712d2
JF		 4181 * ixgbe_lpbthresh - calculate low water mark for for flow control
4182 *
4183 * @adapter: board private structure to calculate for
49ce9c2c 4184 * @pb: packet buffer to calculate
9da712d2 4185 */
e5776620 4186static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4187{
4188 struct ixgbe_hw *hw = &adapter->hw;
4189 struct net_device *dev = adapter->netdev;
4190 int tc;
4191 u32 dv_id;
4192
4193 /* Calculate max LAN frame size */
4194 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4195
e5776620
JK		 4196#ifdef IXGBE_FCOE
4197 /* FCoE traffic class uses FCOE jumbo frames */
4198 if ((dev->features & NETIF_F_FCOE_MTU) &&
4199 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4200 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4201 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4202#endif
4203
9da712d2
JF		 4204 /* Calculate delay value for device */
4205 switch (hw->mac.type) {
4206 case ixgbe_mac_X540:
9a75a1ac
DS		 4207 case ixgbe_mac_X550:
4208 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4209 dv_id = IXGBE_LOW_DV_X540(tc);
4210 break;
4211 default:
4212 dv_id = IXGBE_LOW_DV(tc);
4213 break;
4214 }
4215
4216 /* Delay value is calculated in bit times convert to KB */
4217 return IXGBE_BT2KB(dv_id);
4218}
4219
4220/*
4221 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4222 */
4223static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4224{
4225 struct ixgbe_hw *hw = &adapter->hw;
4226 int num_tc = netdev_get_num_tc(adapter->netdev);
4227 int i;
4228
4229 if (!num_tc)
4230 num_tc = 1;
4231
9da712d2
JF		 4232 for (i = 0; i < num_tc; i++) {
4233 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4234 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4235
4236 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4237 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4238 hw->fc.low_water[i] = 0;
9da712d2 4239 }
e5776620
JK		 4240
4241 for (; i < MAX_TRAFFIC_CLASS; i++)
4242 hw->fc.high_water[i] = 0;
9da712d2
JF		 4243}
4244
80605c65
JF		 4245static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4246{
80605c65 4247 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4248 int hdrm;
4249 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4250
4251 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4252 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4253 hdrm = 32 << adapter->fdir_pballoc;
4254 else
4255 hdrm = 0;
80605c65 4256
f7e1027f 4257 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4258 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4259}
4260
e4911d57
AD		 4261static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4262{
4263 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4264 struct hlist_node *node2;
e4911d57
AD		 4265 struct ixgbe_fdir_filter *filter;
4266
4267 spin_lock(&adapter->fdir_perfect_lock);
4268
4269 if (!hlist_empty(&adapter->fdir_filter_list))
4270 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4271
b67bfe0d 4272 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4273 &adapter->fdir_filter_list, fdir_node) {
4274 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4275 &filter->filter,
4276 filter->sw_idx,
4277 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4278 IXGBE_FDIR_DROP_QUEUE :
4279 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4280 }
4281
4282 spin_unlock(&adapter->fdir_perfect_lock);
4283}
4284
2a47fa45
JF		 4285static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4286 struct ixgbe_adapter *adapter)
4287{
4288 struct ixgbe_hw *hw = &adapter->hw;
4289 u32 vmolr;
4290
4291 /* No unicast promiscuous support for VMDQ devices. */
4292 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4293 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4294
4295 /* clear the affected bit */
4296 vmolr &= ~IXGBE_VMOLR_MPE;
4297
4298 if (dev->flags & IFF_ALLMULTI) {
4299 vmolr |= IXGBE_VMOLR_MPE;
4300 } else {
4301 vmolr |= IXGBE_VMOLR_ROMPE;
4302 hw->mac.ops.update_mc_addr_list(hw, dev);
4303 }
5d7daa35 4304 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4305 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4306}
4307
2a47fa45
JF		 4308static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4309{
4310 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4311 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4312 struct ixgbe_hw *hw = &adapter->hw;
4313 u16 pool = vadapter->pool;
4314 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4315 IXGBE_PSRTYPE_UDPHDR |
4316 IXGBE_PSRTYPE_IPV4HDR |
4317 IXGBE_PSRTYPE_L2HDR |
4318 IXGBE_PSRTYPE_IPV6HDR;
4319
4320 if (hw->mac.type == ixgbe_mac_82598EB)
4321 return;
4322
4323 if (rss_i > 3)
4324 psrtype |= 2 << 29;
4325 else if (rss_i > 1)
4326 psrtype |= 1 << 29;
4327
4328 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4329}
4330
4331/**
4332 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4333 * @rx_ring: ring to free buffers from
4334 **/
4335static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4336{
4337 struct device *dev = rx_ring->dev;
4338 unsigned long size;
4339 u16 i;
4340
4341 /* ring already cleared, nothing to do */
4342 if (!rx_ring->rx_buffer_info)
4343 return;
4344
4345 /* Free all the Rx ring sk_buffs */
4346 for (i = 0; i < rx_ring->count; i++) {
4347 struct ixgbe_rx_buffer *rx_buffer;
4348
4349 rx_buffer = &rx_ring->rx_buffer_info[i];
4350 if (rx_buffer->skb) {
4351 struct sk_buff *skb = rx_buffer->skb;
4352 if (IXGBE_CB(skb)->page_released) {
4353 dma_unmap_page(dev,
4354 IXGBE_CB(skb)->dma,
4355 ixgbe_rx_bufsz(rx_ring),
4356 DMA_FROM_DEVICE);
4357 IXGBE_CB(skb)->page_released = false;
4358 }
4359 dev_kfree_skb(skb);
4d2fcfbc 4360 rx_buffer->skb = NULL;
2a47fa45 4361 }
2a47fa45
JF		 4362 if (rx_buffer->dma)
4363 dma_unmap_page(dev, rx_buffer->dma,
4364 ixgbe_rx_pg_size(rx_ring),
4365 DMA_FROM_DEVICE);
4366 rx_buffer->dma = 0;
4367 if (rx_buffer->page)
4368 __free_pages(rx_buffer->page,
4369 ixgbe_rx_pg_order(rx_ring));
4370 rx_buffer->page = NULL;
4371 }
4372
4373 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4374 memset(rx_ring->rx_buffer_info, 0, size);
4375
4376 /* Zero out the descriptor ring */
4377 memset(rx_ring->desc, 0, rx_ring->size);
4378
4379 rx_ring->next_to_alloc = 0;
4380 rx_ring->next_to_clean = 0;
4381 rx_ring->next_to_use = 0;
4382}
4383
4384static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4385 struct ixgbe_ring *rx_ring)
4386{
4387 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4388 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4389
4390 /* shutdown specific queue receive and wait for dma to settle */
4391 ixgbe_disable_rx_queue(adapter, rx_ring);
4392 usleep_range(10000, 20000);
4393 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4394 ixgbe_clean_rx_ring(rx_ring);
4395 rx_ring->l2_accel_priv = NULL;
4396}
4397
ae72c8d0
JF		 4398static int ixgbe_fwd_ring_down(struct net_device *vdev,
4399 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4400{
4401 struct ixgbe_adapter *adapter = accel->real_adapter;
4402 unsigned int rxbase = accel->rx_base_queue;
4403 unsigned int txbase = accel->tx_base_queue;
4404 int i;
4405
4406 netif_tx_stop_all_queues(vdev);
4407
4408 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4409 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4410 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4411 }
4412
4413 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4414 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4415 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4416 }
4417
4418
4419 return 0;
4420}
4421
4422static int ixgbe_fwd_ring_up(struct net_device *vdev,
4423 struct ixgbe_fwd_adapter *accel)
4424{
4425 struct ixgbe_adapter *adapter = accel->real_adapter;
4426 unsigned int rxbase, txbase, queues;
4427 int i, baseq, err = 0;
4428
4429 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4430 return 0;
4431
4432 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4433 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4434 accel->pool, adapter->num_rx_pools,
4435 baseq, baseq + adapter->num_rx_queues_per_pool,
4436 adapter->fwd_bitmask);
4437
4438 accel->netdev = vdev;
4439 accel->rx_base_queue = rxbase = baseq;
4440 accel->tx_base_queue = txbase = baseq;
4441
4442 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4443 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4444
4445 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4446 adapter->rx_ring[rxbase + i]->netdev = vdev;
4447 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4448 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4449 }
4450
4451 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4452 adapter->tx_ring[txbase + i]->netdev = vdev;
4453 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4454 }
4455
4456 queues = min_t(unsigned int,
4457 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4458 err = netif_set_real_num_tx_queues(vdev, queues);
4459 if (err)
4460 goto fwd_queue_err;
4461
2a47fa45
JF		 4462 err = netif_set_real_num_rx_queues(vdev, queues);
4463 if (err)
4464 goto fwd_queue_err;
4465
4466 if (is_valid_ether_addr(vdev->dev_addr))
4467 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4468
4469 ixgbe_fwd_psrtype(accel);
4470 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4471 return err;
4472fwd_queue_err:
4473 ixgbe_fwd_ring_down(vdev, accel);
4474 return err;
4475}
4476
4477static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4478{
4479 struct net_device *upper;
4480 struct list_head *iter;
4481 int err;
4482
4483 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4484 if (netif_is_macvlan(upper)) {
4485 struct macvlan_dev *dfwd = netdev_priv(upper);
4486 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4487
4488 if (dfwd->fwd_priv) {
4489 err = ixgbe_fwd_ring_up(upper, vadapter);
4490 if (err)
4491 continue;
4492 }
4493 }
4494 }
4495}
4496
9a799d71
AK		 4497static void ixgbe_configure(struct ixgbe_adapter *adapter)
4498{
d2f5e7f3
AS		 4499 struct ixgbe_hw *hw = &adapter->hw;
4500
80605c65 4501 ixgbe_configure_pb(adapter);
7a6b6f51 4502#ifdef CONFIG_IXGBE_DCB
67ebd791 4503 ixgbe_configure_dcb(adapter);
2f90b865 4504#endif
b35d4d42
AD		 4505 /*
4506 * We must restore virtualization before VLANs or else
4507 * the VLVF registers will not be populated
4508 */
4509 ixgbe_configure_virtualization(adapter);
9a799d71 4510
4c1d7b4b 4511 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4512 ixgbe_restore_vlan(adapter);
4513
d2f5e7f3
AS		 4514 switch (hw->mac.type) {
4515 case ixgbe_mac_82599EB:
4516 case ixgbe_mac_X540:
4517 hw->mac.ops.disable_rx_buff(hw);
4518 break;
4519 default:
4520 break;
4521 }
4522
c4cf55e5 4523 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4524 ixgbe_init_fdir_signature_82599(&adapter->hw,
4525 adapter->fdir_pballoc);
e4911d57
AD		 4526 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4527 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4528 adapter->fdir_pballoc);
4529 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4530 }
4c1d7b4b 4531
d2f5e7f3
AS		 4532 switch (hw->mac.type) {
4533 case ixgbe_mac_82599EB:
4534 case ixgbe_mac_X540:
4535 hw->mac.ops.enable_rx_buff(hw);
4536 break;
4537 default:
4538 break;
4539 }
4540
7c8ae65a
AD		 4541#ifdef IXGBE_FCOE
4542 /* configure FCoE L2 filters, redirection table, and Rx control */
4543 ixgbe_configure_fcoe(adapter);
4544
4545#endif /* IXGBE_FCOE */
9a799d71
AK		 4546 ixgbe_configure_tx(adapter);
4547 ixgbe_configure_rx(adapter);
2a47fa45 4548 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4549}
4550
e8e26350
PW		 4551static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4552{
4553 switch (hw->phy.type) {
4554 case ixgbe_phy_sfp_avago:
4555 case ixgbe_phy_sfp_ftl:
4556 case ixgbe_phy_sfp_intel:
4557 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4558 case ixgbe_phy_sfp_passive_tyco:
4559 case ixgbe_phy_sfp_passive_unknown:
4560 case ixgbe_phy_sfp_active_unknown:
4561 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4562 case ixgbe_phy_qsfp_passive_unknown:
4563 case ixgbe_phy_qsfp_active_unknown:
4564 case ixgbe_phy_qsfp_intel:
4565 case ixgbe_phy_qsfp_unknown:
d9cd46cd
ET		 4566 /* ixgbe_phy_none is set when no SFP module is present */
4567 case ixgbe_phy_none:
e8e26350 4568 return true;
8917b447
AD		 4569 case ixgbe_phy_nl:
4570 if (hw->mac.type == ixgbe_mac_82598EB)
4571 return true;
e8e26350
PW		 4572 default:
4573 return false;
4574 }
4575}
4576
0ecc061d 4577/**
e8e26350
PW		 4578 * ixgbe_sfp_link_config - set up SFP+ link
4579 * @adapter: pointer to private adapter struct
4580 **/
4581static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4582{
7086400d 4583 /*
52f33af8 4584 * We are assuming the worst case scenario here, and that
7086400d
AD		 4585 * is that an SFP was inserted/removed after the reset
4586 * but before SFP detection was enabled. As such the best
4587 * solution is to just start searching as soon as we start
4588 */
4589 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4590 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4591
7086400d 4592 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4593}
4594
4595/**
4596 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4597 * @hw: pointer to private hardware struct
4598 *
4599 * Returns 0 on success, negative on failure
4600 **/
e8e26350 4601static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4602{
3d292265
JH		 4603 u32 speed;
4604 bool autoneg, link_up = false;
0ecc061d
PWJ		 4605 u32 ret = IXGBE_ERR_LINK_SETUP;
4606
4607 if (hw->mac.ops.check_link)
3d292265 4608 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4609
4610 if (ret)
e90dd264 4611 return ret;
0ecc061d 4612
3d292265
JH		 4613 speed = hw->phy.autoneg_advertised;
4614 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4615 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4616 &autoneg);
0ecc061d 4617 if (ret)
e90dd264 4618 return ret;
0ecc061d 4619
8620a103 4620 if (hw->mac.ops.setup_link)
fd0326f2 4621 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4622
0ecc061d
PWJ		 4623 return ret;
4624}
4625
a34bcfff 4626static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4627{
9a799d71 4628 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4629 u32 gpie = 0;
9a799d71 4630
9b471446 4631 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4632 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4633 IXGBE_GPIE_OCD;
4634 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4635 /*
4636 * use EIAM to auto-mask when MSI-X interrupt is asserted
4637 * this saves a register write for every interrupt
4638 */
4639 switch (hw->mac.type) {
4640 case ixgbe_mac_82598EB:
4641 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4642 break;
9b471446 4643 case ixgbe_mac_82599EB:
b93a2226 4644 case ixgbe_mac_X540:
9a75a1ac
DS		 4645 case ixgbe_mac_X550:
4646 case ixgbe_mac_X550EM_x:
b93a2226 4647 default:
9b471446
JB		 4648 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4649 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4650 break;
4651 }
4652 } else {
021230d4
AV		 4653 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4654 * specifically only auto mask tx and rx interrupts */
4655 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4656 }
9a799d71 4657
a34bcfff
AD		 4658 /* XXX: to interrupt immediately for EICS writes, enable this */
4659 /* gpie |= IXGBE_GPIE_EIMEN; */
4660
4661 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4662 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4663
4664 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4665 case IXGBE_82599_VMDQ_8Q_MASK:
4666 gpie |= IXGBE_GPIE_VTMODE_16;
4667 break;
4668 case IXGBE_82599_VMDQ_4Q_MASK:
4669 gpie |= IXGBE_GPIE_VTMODE_32;
4670 break;
4671 default:
4672 gpie |= IXGBE_GPIE_VTMODE_64;
4673 break;
4674 }
119fc60a
MC		 4675 }
4676
5fdd31f9 4677 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4678 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4679 switch (adapter->hw.mac.type) {
4680 case ixgbe_mac_82599EB:
4681 gpie |= IXGBE_SDP0_GPIEN;
4682 break;
4683 case ixgbe_mac_X540:
4684 gpie |= IXGBE_EIMS_TS;
4685 break;
4686 default:
4687 break;
4688 }
4689 }
5fdd31f9 4690
a34bcfff
AD		 4691 /* Enable fan failure interrupt */
4692 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4693 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4694
2698b208 4695 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4696 gpie |= IXGBE_SDP1_GPIEN;
4697 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4698 }
a34bcfff
AD		 4699
4700 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4701}
4702
c7ccde0f 4703static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4704{
4705 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4706 int err;
a34bcfff
AD		 4707 u32 ctrl_ext;
4708
4709 ixgbe_get_hw_control(adapter);
4710 ixgbe_setup_gpie(adapter);
e8e26350 4711
9a799d71
AK		 4712 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4713 ixgbe_configure_msix(adapter);
4714 else
4715 ixgbe_configure_msi_and_legacy(adapter);
4716
ec74a471
ET		 4717 /* enable the optics for 82599 SFP+ fiber */
4718 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4719 hw->mac.ops.enable_tx_laser(hw);
4720
4e857c58 4721 smp_mb__before_atomic();
9a799d71 4722 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4723 ixgbe_napi_enable_all(adapter);
4724
73c4b7cd
AD		 4725 if (ixgbe_is_sfp(hw)) {
4726 ixgbe_sfp_link_config(adapter);
4727 } else {
4728 err = ixgbe_non_sfp_link_config(hw);
4729 if (err)
4730 e_err(probe, "link_config FAILED %d\n", err);
4731 }
4732
021230d4
AV		 4733 /* clear any pending interrupts, may auto mask */
4734 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4735 ixgbe_irq_enable(adapter, true, true);
9a799d71 4736
bf069c97
DS		 4737 /*
4738 * If this adapter has a fan, check to see if we had a failure
4739 * before we enabled the interrupt.
4740 */
4741 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4742 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4743 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4744 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4745 }
4746
9a799d71
AK		 4747 /* bring the link up in the watchdog, this could race with our first
4748 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4749 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4750 adapter->link_check_timeout = jiffies;
7086400d 4751 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4752
4753 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4754 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4755 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4756 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4757}
4758
d4f80882
AV		 4759void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4760{
4761 WARN_ON(in_interrupt());
7086400d
AD		 4762 /* put off any impending NetWatchDogTimeout */
4763 adapter->netdev->trans_start = jiffies;
4764
d4f80882 4765 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4766 usleep_range(1000, 2000);
d4f80882 4767 ixgbe_down(adapter);
5809a1ae
GR		 4768 /*
4769 * If SR-IOV enabled then wait a bit before bringing the adapter
4770 * back up to give the VFs time to respond to the reset. The
4771 * two second wait is based upon the watchdog timer cycle in
4772 * the VF driver.
4773 */
4774 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4775 msleep(2000);
d4f80882
AV		 4776 ixgbe_up(adapter);
4777 clear_bit(__IXGBE_RESETTING, &adapter->state);
4778}
4779
c7ccde0f 4780void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4781{
4782 /* hardware has been reset, we need to reload some things */
4783 ixgbe_configure(adapter);
4784
c7ccde0f 4785 ixgbe_up_complete(adapter);
9a799d71
AK		 4786}
4787
4788void ixgbe_reset(struct ixgbe_adapter *adapter)
4789{
c44ade9e 4790 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4791 struct net_device *netdev = adapter->netdev;
8ca783ab 4792 int err;
5d7daa35 4793 u8 old_addr[ETH_ALEN];
8ca783ab 4794
b0483c8f
MR		 4795 if (ixgbe_removed(hw->hw_addr))
4796 return;
7086400d
AD		 4797 /* lock SFP init bit to prevent race conditions with the watchdog */
4798 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4799 usleep_range(1000, 2000);
4800
4801 /* clear all SFP and link config related flags while holding SFP_INIT */
4802 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4803 IXGBE_FLAG2_SFP_NEEDS_RESET);
4804 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4805
8ca783ab 4806 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4807 switch (err) {
4808 case 0:
4809 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4810 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4811 break;
4812 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4813 e_dev_err("master disable timed out\n");
da4dd0f7 4814 break;
794caeb2
PWJ		 4815 case IXGBE_ERR_EEPROM_VERSION:
4816 /* We are running on a pre-production device, log a warning */
849c4542 4817 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4818 "Please be aware there may be issues associated with "
849c4542
ET		 4819 "your hardware. If you are experiencing problems "
4820 "please contact your Intel or hardware "
4821 "representative who provided you with this "
4822 "hardware.\n");
794caeb2 4823 break;
da4dd0f7 4824 default:
849c4542 4825 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4826 }
9a799d71 4827
7086400d 4828 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 4829 /* do not flush user set addresses */
4830 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4831 ixgbe_flush_sw_mac_table(adapter);
4832 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 4833
4834 /* update SAN MAC vmdq pool selection */
4835 if (hw->mac.san_mac_rar_index)
4836 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4837
8fecf67c 4838 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4839 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4840}
4841
9a799d71
AK		 4842/**
4843 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4844 * @tx_ring: ring to be cleaned
4845 **/
b6ec895e 4846static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4847{
4848 struct ixgbe_tx_buffer *tx_buffer_info;
4849 unsigned long size;
b6ec895e 4850 u16 i;
9a799d71 4851
84418e3b
AD		 4852 /* ring already cleared, nothing to do */
4853 if (!tx_ring->tx_buffer_info)
4854 return;
9a799d71 4855
84418e3b 4856 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4857 for (i = 0; i < tx_ring->count; i++) {
4858 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4859 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4860 }
4861
dad8a3b3
JF		 4862 netdev_tx_reset_queue(txring_txq(tx_ring));
4863
9a799d71
AK		 4864 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4865 memset(tx_ring->tx_buffer_info, 0, size);
4866
4867 /* Zero out the descriptor ring */
4868 memset(tx_ring->desc, 0, tx_ring->size);
4869
4870 tx_ring->next_to_use = 0;
4871 tx_ring->next_to_clean = 0;
9a799d71
AK		 4872}
4873
4874/**
021230d4 4875 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4876 * @adapter: board private structure
4877 **/
021230d4 4878static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4879{
4880 int i;
4881
021230d4 4882 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4883 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4884}
4885
4886/**
021230d4 4887 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4888 * @adapter: board private structure
4889 **/
021230d4 4890static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4891{
4892 int i;
4893
021230d4 4894 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4895 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4896}
4897
e4911d57
AD		 4898static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4899{
b67bfe0d 4900 struct hlist_node *node2;
e4911d57
AD		 4901 struct ixgbe_fdir_filter *filter;
4902
4903 spin_lock(&adapter->fdir_perfect_lock);
4904
b67bfe0d 4905 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4906 &adapter->fdir_filter_list, fdir_node) {
4907 hlist_del(&filter->fdir_node);
4908 kfree(filter);
4909 }
4910 adapter->fdir_filter_count = 0;
4911
4912 spin_unlock(&adapter->fdir_perfect_lock);
4913}
4914
9a799d71
AK		 4915void ixgbe_down(struct ixgbe_adapter *adapter)
4916{
4917 struct net_device *netdev = adapter->netdev;
7f821875 4918 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4919 struct net_device *upper;
4920 struct list_head *iter;
9a799d71 4921 u32 rxctrl;
bf29ee6c 4922 int i;
9a799d71
AK		 4923
4924 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4925 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4926 return; /* do nothing if already down */
9a799d71
AK		 4927
4928 /* disable receives */
7f821875
JB		 4929 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4930 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4931
2d39d576
YZ		 4932 /* disable all enabled rx queues */
4933 for (i = 0; i < adapter->num_rx_queues; i++)
4934 /* this call also flushes the previous write */
4935 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4936
032b4325 4937 usleep_range(10000, 20000);
9a799d71 4938
7f821875
JB		 4939 netif_tx_stop_all_queues(netdev);
4940
7086400d 4941 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4942 netif_carrier_off(netdev);
4943 netif_tx_disable(netdev);
4944
2a47fa45
JF		 4945 /* disable any upper devices */
4946 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4947 if (netif_is_macvlan(upper)) {
4948 struct macvlan_dev *vlan = netdev_priv(upper);
4949
4950 if (vlan->fwd_priv) {
4951 netif_tx_stop_all_queues(upper);
4952 netif_carrier_off(upper);
4953 netif_tx_disable(upper);
4954 }
4955 }
4956 }
4957
c0dfb90e
JF		 4958 ixgbe_irq_disable(adapter);
4959
4960 ixgbe_napi_disable_all(adapter);
4961
d034acf1
AD		 4962 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4963 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4964 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4965
4966 del_timer_sync(&adapter->service_timer);
4967
34cecbbf 4968 if (adapter->num_vfs) {
8e34d1aa
AD		 4969 /* Clear EITR Select mapping */
4970 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4971
4972 /* Mark all the VFs as inactive */
4973 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4974 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4975
34cecbbf
AD		 4976 /* ping all the active vfs to let them know we are going down */
4977 ixgbe_ping_all_vfs(adapter);
4978
4979 /* Disable all VFTE/VFRE TX/RX */
4980 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4981 }
4982
7f821875
JB		 4983 /* disable transmits in the hardware now that interrupts are off */
4984 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4985 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4986 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4987 }
34cecbbf 4988
9a75a1ac 4989 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 4990 switch (hw->mac.type) {
4991 case ixgbe_mac_82599EB:
b93a2226 4992 case ixgbe_mac_X540:
9a75a1ac
DS		 4993 case ixgbe_mac_X550:
4994 case ixgbe_mac_X550EM_x:
88512539 4995 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4996 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4997 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4998 break;
4999 default:
5000 break;
5001 }
7f821875 5002
6f4a0e45
PL		 5003 if (!pci_channel_offline(adapter->pdev))
5004 ixgbe_reset(adapter);
c6ecf39a 5005
ec74a471
ET		 5006 /* power down the optics for 82599 SFP+ fiber */
5007 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5008 hw->mac.ops.disable_tx_laser(hw);
5009
9a799d71
AK		 5010 ixgbe_clean_all_tx_rings(adapter);
5011 ixgbe_clean_all_rx_rings(adapter);
5012
5dd2d332 5013#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5014 /* since we reset the hardware DCA settings were cleared */
e35ec126 5015 ixgbe_setup_dca(adapter);
96b0e0f6 5016#endif
9a799d71
AK		 5017}
5018
9a799d71
AK		 5019/**
5020 * ixgbe_tx_timeout - Respond to a Tx Hang
5021 * @netdev: network interface device structure
5022 **/
5023static void ixgbe_tx_timeout(struct net_device *netdev)
5024{
5025 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5026
5027 /* Do the reset outside of interrupt context */
c83c6cbd 5028 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5029}
5030
9a799d71
AK		 5031/**
5032 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5033 * @adapter: board private structure to initialize
5034 *
5035 * ixgbe_sw_init initializes the Adapter private data structure.
5036 * Fields are initialized based on PCI device information and
5037 * OS network device settings (MTU size).
5038 **/
9f9a12f8 5039static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5040{
5041 struct ixgbe_hw *hw = &adapter->hw;
5042 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5043 unsigned int rss, fdir;
cb6d0f5e 5044 u32 fwsm;
7a6b6f51 5045#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5046 int j;
5047 struct tc_configuration *tc;
5048#endif
021230d4 5049
c44ade9e
JB		 5050 /* PCI config space info */
5051
5052 hw->vendor_id = pdev->vendor;
5053 hw->device_id = pdev->device;
5054 hw->revision_id = pdev->revision;
5055 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5056 hw->subsystem_device_id = pdev->subsystem_device;
5057
8fc3bb6d 5058 /* Set common capability flags and settings */
3ed69d7e 5059 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5060 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5061 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5062 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5063 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5064 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5065 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5066 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5067 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5068#ifdef CONFIG_IXGBE_DCA
5069 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5070#endif
5071#ifdef IXGBE_FCOE
5072 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5073 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5074#ifdef CONFIG_IXGBE_DCB
5075 /* Default traffic class to use for FCoE */
5076 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5077#endif /* CONFIG_IXGBE_DCB */
5078#endif /* IXGBE_FCOE */
5079
5d7daa35
JK		 5080 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5081 hw->mac.num_rar_entries,
5082 GFP_ATOMIC);
5083
8fc3bb6d 5084 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5085 switch (hw->mac.type) {
5086 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5087 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5088 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5089
bf069c97
DS		 5090 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5091 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5092
49c7ffbe 5093 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5094 adapter->ring_feature[RING_F_FDIR].limit = 0;
5095 adapter->atr_sample_rate = 0;
5096 adapter->fdir_pballoc = 0;
5097#ifdef IXGBE_FCOE
5098 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5099 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5100#ifdef CONFIG_IXGBE_DCB
5101 adapter->fcoe.up = 0;
5102#endif /* IXGBE_DCB */
5103#endif /* IXGBE_FCOE */
5104 break;
5105 case ixgbe_mac_82599EB:
5106 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5107 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5108 break;
b93a2226 5109 case ixgbe_mac_X540:
cb6d0f5e
JK		 5110 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5111 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5112 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5113 break;
9a75a1ac
DS		 5114 case ixgbe_mac_X550EM_x:
5115 case ixgbe_mac_X550:
5116#ifdef CONFIG_IXGBE_DCA
5117 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5118#endif
5119 break;
bd508178
AD		 5120 default:
5121 break;
f8212f97 5122 }
2f90b865 5123
7c8ae65a
AD		 5124#ifdef IXGBE_FCOE
5125 /* FCoE support exists, always init the FCoE lock */
5126 spin_lock_init(&adapter->fcoe.lock);
5127
5128#endif
1fc5f038
AD		 5129 /* n-tuple support exists, always init our spinlock */
5130 spin_lock_init(&adapter->fdir_perfect_lock);
5131
7a6b6f51 5132#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5133 switch (hw->mac.type) {
5134 case ixgbe_mac_X540:
9a75a1ac
DS		 5135 case ixgbe_mac_X550:
5136 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5137 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5138 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5139 break;
5140 default:
5141 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5142 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5143 break;
5144 }
5145
2f90b865
AD		 5146 /* Configure DCB traffic classes */
5147 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5148 tc = &adapter->dcb_cfg.tc_config[j];
5149 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5150 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5151 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5152 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5153 tc->dcb_pfc = pfc_disabled;
5154 }
4de2a022
JF		 5155
5156 /* Initialize default user to priority mapping, UPx->TC0 */
5157 tc = &adapter->dcb_cfg.tc_config[0];
5158 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5159 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5160
2f90b865
AD		 5161 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5162 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5163 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5164 adapter->dcb_set_bitmap = 0x00;
3032309b 5165 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5166 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5167 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5168
5169#endif
9a799d71
AK		 5170
5171 /* default flow control settings */
cd7664f6 5172 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5173 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5174 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5175 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5176 hw->fc.send_xon = true;
73d80953 5177 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5178
99d74487 5179#ifdef CONFIG_PCI_IOV
170e8543
JK		 5180 if (max_vfs > 0)
5181 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5182
99d74487 5183 /* assign number of SR-IOV VFs */
170e8543 5184 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5185 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5186 adapter->num_vfs = 0;
5187 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5188 } else {
5189 adapter->num_vfs = max_vfs;
5190 }
5191 }
5192#endif /* CONFIG_PCI_IOV */
99d74487 5193
30efa5a3 5194 /* enable itr by default in dynamic mode */
f7554a2b 5195 adapter->rx_itr_setting = 1;
f7554a2b 5196 adapter->tx_itr_setting = 1;
30efa5a3 5197
30efa5a3
JB		 5198 /* set default ring sizes */
5199 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5200 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5201
bd198058 5202 /* set default work limits */
59224555 5203 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5204
9a799d71 5205 /* initialize eeprom parameters */
c44ade9e 5206 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5207 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5208 return -EIO;
5209 }
5210
2a47fa45
JF		 5211 /* PF holds first pool slot */
5212 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5213 set_bit(__IXGBE_DOWN, &adapter->state);
5214
5215 return 0;
5216}
5217
5218/**
5219 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5220 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5221 *
5222 * Return 0 on success, negative on failure
5223 **/
b6ec895e 5224int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5225{
b6ec895e 5226 struct device *dev = tx_ring->dev;
de88eeeb 5227 int orig_node = dev_to_node(dev);
ca8dfe25 5228 int ring_node = -1;
9a799d71
AK		 5229 int size;
5230
3a581073 5231 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5232
5233 if (tx_ring->q_vector)
ca8dfe25 5234 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5235
ca8dfe25 5236 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5237 if (!tx_ring->tx_buffer_info)
89bf67f1 5238 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5239 if (!tx_ring->tx_buffer_info)
5240 goto err;
9a799d71 5241
827da44c
JS		 5242 u64_stats_init(&tx_ring->syncp);
5243
9a799d71 5244 /* round up to nearest 4K */
12207e49 5245 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5246 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5247
ca8dfe25 5248 set_dev_node(dev, ring_node);
de88eeeb
AD		 5249 tx_ring->desc = dma_alloc_coherent(dev,
5250 tx_ring->size,
5251 &tx_ring->dma,
5252 GFP_KERNEL);
5253 set_dev_node(dev, orig_node);
5254 if (!tx_ring->desc)
5255 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5256 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5257 if (!tx_ring->desc)
5258 goto err;
9a799d71 5259
3a581073
JB		 5260 tx_ring->next_to_use = 0;
5261 tx_ring->next_to_clean = 0;
9a799d71 5262 return 0;
e01c31a5
JB		 5263
5264err:
5265 vfree(tx_ring->tx_buffer_info);
5266 tx_ring->tx_buffer_info = NULL;
b6ec895e 5267 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5268 return -ENOMEM;
9a799d71
AK		 5269}
5270
69888674
AD		 5271/**
5272 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5273 * @adapter: board private structure
5274 *
5275 * If this function returns with an error, then it's possible one or
5276 * more of the rings is populated (while the rest are not). It is the
5277 * callers duty to clean those orphaned rings.
5278 *
5279 * Return 0 on success, negative on failure
5280 **/
5281static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5282{
5283 int i, err = 0;
5284
5285 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5286 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5287 if (!err)
5288 continue;
de3d5b94 5289
396e799c 5290 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5291 goto err_setup_tx;
69888674
AD		 5292 }
5293
de3d5b94
AD		 5294 return 0;
5295err_setup_tx:
5296 /* rewind the index freeing the rings as we go */
5297 while (i--)
5298 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5299 return err;
5300}
5301
9a799d71
AK		 5302/**
5303 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5304 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5305 *
5306 * Returns 0 on success, negative on failure
5307 **/
b6ec895e 5308int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5309{
b6ec895e 5310 struct device *dev = rx_ring->dev;
de88eeeb 5311 int orig_node = dev_to_node(dev);
ca8dfe25 5312 int ring_node = -1;
021230d4 5313 int size;
9a799d71 5314
3a581073 5315 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5316
5317 if (rx_ring->q_vector)
ca8dfe25 5318 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5319
ca8dfe25 5320 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5321 if (!rx_ring->rx_buffer_info)
89bf67f1 5322 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5323 if (!rx_ring->rx_buffer_info)
5324 goto err;
9a799d71 5325
827da44c
JS		 5326 u64_stats_init(&rx_ring->syncp);
5327
9a799d71 5328 /* Round up to nearest 4K */
3a581073
JB		 5329 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5330 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5331
ca8dfe25 5332 set_dev_node(dev, ring_node);
de88eeeb
AD		 5333 rx_ring->desc = dma_alloc_coherent(dev,
5334 rx_ring->size,
5335 &rx_ring->dma,
5336 GFP_KERNEL);
5337 set_dev_node(dev, orig_node);
5338 if (!rx_ring->desc)
5339 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5340 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5341 if (!rx_ring->desc)
5342 goto err;
9a799d71 5343
3a581073
JB		 5344 rx_ring->next_to_clean = 0;
5345 rx_ring->next_to_use = 0;
9a799d71
AK		 5346
5347 return 0;
b6ec895e
AD		 5348err:
5349 vfree(rx_ring->rx_buffer_info);
5350 rx_ring->rx_buffer_info = NULL;
5351 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5352 return -ENOMEM;
9a799d71
AK		 5353}
5354
69888674
AD		 5355/**
5356 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5357 * @adapter: board private structure
5358 *
5359 * If this function returns with an error, then it's possible one or
5360 * more of the rings is populated (while the rest are not). It is the
5361 * callers duty to clean those orphaned rings.
5362 *
5363 * Return 0 on success, negative on failure
5364 **/
69888674
AD		 5365static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5366{
5367 int i, err = 0;
5368
5369 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5370 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5371 if (!err)
5372 continue;
de3d5b94 5373
396e799c 5374 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5375 goto err_setup_rx;
69888674
AD		 5376 }
5377
7c8ae65a
AD		 5378#ifdef IXGBE_FCOE
5379 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5380 if (!err)
5381#endif
5382 return 0;
de3d5b94
AD		 5383err_setup_rx:
5384 /* rewind the index freeing the rings as we go */
5385 while (i--)
5386 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5387 return err;
5388}
5389
9a799d71
AK		 5390/**
5391 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5392 * @tx_ring: Tx descriptor ring for a specific queue
5393 *
5394 * Free all transmit software resources
5395 **/
b6ec895e 5396void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5397{
b6ec895e 5398 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5399
5400 vfree(tx_ring->tx_buffer_info);
5401 tx_ring->tx_buffer_info = NULL;
5402
b6ec895e
AD		 5403 /* if not set, then don't free */
5404 if (!tx_ring->desc)
5405 return;
5406
5407 dma_free_coherent(tx_ring->dev, tx_ring->size,
5408 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5409
5410 tx_ring->desc = NULL;
5411}
5412
5413/**
5414 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5415 * @adapter: board private structure
5416 *
5417 * Free all transmit software resources
5418 **/
5419static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5420{
5421 int i;
5422
5423 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5424 if (adapter->tx_ring[i]->desc)
b6ec895e 5425 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5426}
5427
5428/**
b4617240 5429 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5430 * @rx_ring: ring to clean the resources from
5431 *
5432 * Free all receive software resources
5433 **/
b6ec895e 5434void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5435{
b6ec895e 5436 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5437
5438 vfree(rx_ring->rx_buffer_info);
5439 rx_ring->rx_buffer_info = NULL;
5440
b6ec895e
AD		 5441 /* if not set, then don't free */
5442 if (!rx_ring->desc)
5443 return;
5444
5445 dma_free_coherent(rx_ring->dev, rx_ring->size,
5446 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5447
5448 rx_ring->desc = NULL;
5449}
5450
5451/**
5452 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5453 * @adapter: board private structure
5454 *
5455 * Free all receive software resources
5456 **/
5457static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5458{
5459 int i;
5460
7c8ae65a
AD		 5461#ifdef IXGBE_FCOE
5462 ixgbe_free_fcoe_ddp_resources(adapter);
5463
5464#endif
9a799d71 5465 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5466 if (adapter->rx_ring[i]->desc)
b6ec895e 5467 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5468}
5469
9a799d71
AK		 5470/**
5471 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5472 * @netdev: network interface device structure
5473 * @new_mtu: new value for maximum frame size
5474 *
5475 * Returns 0 on success, negative on failure
5476 **/
5477static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5478{
5479 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5480 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5481
42c783c5 5482 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5483 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5484 return -EINVAL;
5485
5486 /*
872844dd
AD		 5487 * For 82599EB we cannot allow legacy VFs to enable their receive
5488 * paths when MTU greater than 1500 is configured. So display a
5489 * warning that legacy VFs will be disabled.
655309e9
AD		 5490 */
5491 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5492 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5493 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5494 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5495
396e799c 5496 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5497
021230d4 5498 /* must set new MTU before calling down or up */
9a799d71
AK		 5499 netdev->mtu = new_mtu;
5500
d4f80882
AV		 5501 if (netif_running(netdev))
5502 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5503
5504 return 0;
5505}
5506
5507/**
5508 * ixgbe_open - Called when a network interface is made active
5509 * @netdev: network interface device structure
5510 *
5511 * Returns 0 on success, negative value on failure
5512 *
5513 * The open entry point is called when a network interface is made
5514 * active by the system (IFF_UP). At this point all resources needed
5515 * for transmit and receive operations are allocated, the interrupt
5516 * handler is registered with the OS, the watchdog timer is started,
5517 * and the stack is notified that the interface is ready.
5518 **/
5519static int ixgbe_open(struct net_device *netdev)
5520{
5521 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5522 int err, queues;
4bebfaa5
AK		 5523
5524 /* disallow open during test */
5525 if (test_bit(__IXGBE_TESTING, &adapter->state))
5526 return -EBUSY;
9a799d71 5527
54386467
JB		 5528 netif_carrier_off(netdev);
5529
9a799d71
AK		 5530 /* allocate transmit descriptors */
5531 err = ixgbe_setup_all_tx_resources(adapter);
5532 if (err)
5533 goto err_setup_tx;
5534
9a799d71
AK		 5535 /* allocate receive descriptors */
5536 err = ixgbe_setup_all_rx_resources(adapter);
5537 if (err)
5538 goto err_setup_rx;
5539
5540 ixgbe_configure(adapter);
5541
021230d4 5542 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5543 if (err)
5544 goto err_req_irq;
5545
ac802f5d 5546 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5547 if (adapter->num_rx_pools > 1)
5548 queues = adapter->num_rx_queues_per_pool;
5549 else
5550 queues = adapter->num_tx_queues;
5551
5552 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5553 if (err)
5554 goto err_set_queues;
5555
2a47fa45
JF		 5556 if (adapter->num_rx_pools > 1 &&
5557 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5558 queues = IXGBE_MAX_L2A_QUEUES;
5559 else
5560 queues = adapter->num_rx_queues;
5561 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5562 if (err)
5563 goto err_set_queues;
5564
1a71ab24 5565 ixgbe_ptp_init(adapter);
1a71ab24 5566
c7ccde0f 5567 ixgbe_up_complete(adapter);
9a799d71
AK		 5568
5569 return 0;
5570
ac802f5d
AD		 5571err_set_queues:
5572 ixgbe_free_irq(adapter);
9a799d71 5573err_req_irq:
a20a1199 5574 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5575err_setup_rx:
a20a1199 5576 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5577err_setup_tx:
9a799d71
AK		 5578 ixgbe_reset(adapter);
5579
5580 return err;
5581}
5582
a0cccce2
JK		 5583static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5584{
5585 ixgbe_ptp_suspend(adapter);
5586
5587 ixgbe_down(adapter);
5588 ixgbe_free_irq(adapter);
5589
5590 ixgbe_free_all_tx_resources(adapter);
5591 ixgbe_free_all_rx_resources(adapter);
5592}
5593
9a799d71
AK		 5594/**
5595 * ixgbe_close - Disables a network interface
5596 * @netdev: network interface device structure
5597 *
5598 * Returns 0, this is not allowed to fail
5599 *
5600 * The close entry point is called when an interface is de-activated
5601 * by the OS. The hardware is still under the drivers control, but
5602 * needs to be disabled. A global MAC reset is issued to stop the
5603 * hardware, and all transmit and receive resources are freed.
5604 **/
5605static int ixgbe_close(struct net_device *netdev)
5606{
5607 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5608
1a71ab24 5609 ixgbe_ptp_stop(adapter);
1a71ab24 5610
a0cccce2 5611 ixgbe_close_suspend(adapter);
9a799d71 5612
e4911d57
AD		 5613 ixgbe_fdir_filter_exit(adapter);
5614
5eba3699 5615 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5616
5617 return 0;
5618}
5619
b3c8b4ba
AD		 5620#ifdef CONFIG_PM
5621static int ixgbe_resume(struct pci_dev *pdev)
5622{
c60fbb00
AD		 5623 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5624 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5625 u32 err;
5626
0391bbe3 5627 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5628 pci_set_power_state(pdev, PCI_D0);
5629 pci_restore_state(pdev);
656ab817
DS		 5630 /*
5631 * pci_restore_state clears dev->state_saved so call
5632 * pci_save_state to restore it.
5633 */
5634 pci_save_state(pdev);
9ce77666 5635
5636 err = pci_enable_device_mem(pdev);
b3c8b4ba 5637 if (err) {
849c4542 5638 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5639 return err;
5640 }
4e857c58 5641 smp_mb__before_atomic();
41c62843 5642 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5643 pci_set_master(pdev);
5644
dd4d8ca6 5645 pci_wake_from_d3(pdev, false);
b3c8b4ba 5646
b3c8b4ba
AD		 5647 ixgbe_reset(adapter);
5648
495dce12
WJP		 5649 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5650
ac802f5d
AD		 5651 rtnl_lock();
5652 err = ixgbe_init_interrupt_scheme(adapter);
5653 if (!err && netif_running(netdev))
c60fbb00 5654 err = ixgbe_open(netdev);
ac802f5d
AD		 5655
5656 rtnl_unlock();
5657
5658 if (err)
5659 return err;
b3c8b4ba
AD		 5660
5661 netif_device_attach(netdev);
5662
5663 return 0;
5664}
b3c8b4ba 5665#endif /* CONFIG_PM */
9d8d05ae
RW		 5666
5667static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5668{
c60fbb00
AD		 5669 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5670 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5671 struct ixgbe_hw *hw = &adapter->hw;
5672 u32 ctrl, fctrl;
5673 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5674#ifdef CONFIG_PM
5675 int retval = 0;
5676#endif
5677
5678 netif_device_detach(netdev);
5679
499ab5cc 5680 rtnl_lock();
a0cccce2
JK		 5681 if (netif_running(netdev))
5682 ixgbe_close_suspend(adapter);
499ab5cc 5683 rtnl_unlock();
b3c8b4ba 5684
5f5ae6fc
AD		 5685 ixgbe_clear_interrupt_scheme(adapter);
5686
b3c8b4ba
AD		 5687#ifdef CONFIG_PM
5688 retval = pci_save_state(pdev);
5689 if (retval)
5690 return retval;
4df10466 5691
b3c8b4ba 5692#endif
f4f1040a
JK		 5693 if (hw->mac.ops.stop_link_on_d3)
5694 hw->mac.ops.stop_link_on_d3(hw);
5695
e8e26350
PW		 5696 if (wufc) {
5697 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5698
ec74a471
ET		 5699 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5700 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5701 hw->mac.ops.enable_tx_laser(hw);
5702
e8e26350
PW		 5703 /* turn on all-multi mode if wake on multicast is enabled */
5704 if (wufc & IXGBE_WUFC_MC) {
5705 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5706 fctrl |= IXGBE_FCTRL_MPE;
5707 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5708 }
5709
5710 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5711 ctrl |= IXGBE_CTRL_GIO_DIS;
5712 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5713
5714 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5715 } else {
5716 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5717 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5718 }
5719
bd508178
AD		 5720 switch (hw->mac.type) {
5721 case ixgbe_mac_82598EB:
dd4d8ca6 5722 pci_wake_from_d3(pdev, false);
bd508178
AD		 5723 break;
5724 case ixgbe_mac_82599EB:
b93a2226 5725 case ixgbe_mac_X540:
9a75a1ac
DS		 5726 case ixgbe_mac_X550:
5727 case ixgbe_mac_X550EM_x:
bd508178
AD		 5728 pci_wake_from_d3(pdev, !!wufc);
5729 break;
5730 default:
5731 break;
5732 }
b3c8b4ba 5733
9d8d05ae
RW		 5734 *enable_wake = !!wufc;
5735
b3c8b4ba
AD		 5736 ixgbe_release_hw_control(adapter);
5737
41c62843
MR		 5738 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5739 pci_disable_device(pdev);
b3c8b4ba 5740
9d8d05ae
RW		 5741 return 0;
5742}
5743
5744#ifdef CONFIG_PM
5745static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5746{
5747 int retval;
5748 bool wake;
5749
5750 retval = __ixgbe_shutdown(pdev, &wake);
5751 if (retval)
5752 return retval;
5753
5754 if (wake) {
5755 pci_prepare_to_sleep(pdev);
5756 } else {
5757 pci_wake_from_d3(pdev, false);
5758 pci_set_power_state(pdev, PCI_D3hot);
5759 }
b3c8b4ba
AD		 5760
5761 return 0;
5762}
9d8d05ae 5763#endif /* CONFIG_PM */
b3c8b4ba
AD		 5764
5765static void ixgbe_shutdown(struct pci_dev *pdev)
5766{
9d8d05ae
RW		 5767 bool wake;
5768
5769 __ixgbe_shutdown(pdev, &wake);
5770
5771 if (system_state == SYSTEM_POWER_OFF) {
5772 pci_wake_from_d3(pdev, wake);
5773 pci_set_power_state(pdev, PCI_D3hot);
5774 }
b3c8b4ba
AD		 5775}
5776
9a799d71
AK		 5777/**
5778 * ixgbe_update_stats - Update the board statistics counters.
5779 * @adapter: board private structure
5780 **/
5781void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5782{
2d86f139 5783 struct net_device *netdev = adapter->netdev;
9a799d71 5784 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5785 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5786 u64 total_mpc = 0;
5787 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5788 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5789 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5790 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5791
d08935c2
DS		 5792 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5793 test_bit(__IXGBE_RESETTING, &adapter->state))
5794 return;
5795
94b982b2 5796 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5797 u64 rsc_count = 0;
94b982b2 5798 u64 rsc_flush = 0;
94b982b2 5799 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5800 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5801 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5802 }
5803 adapter->rsc_total_count = rsc_count;
5804 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5805 }
5806
5b7da515
AD		 5807 for (i = 0; i < adapter->num_rx_queues; i++) {
5808 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5809 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5810 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5811 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5812 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5813 bytes += rx_ring->stats.bytes;
5814 packets += rx_ring->stats.packets;
5815 }
5816 adapter->non_eop_descs = non_eop_descs;
5817 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5818 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5819 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5820 netdev->stats.rx_bytes = bytes;
5821 netdev->stats.rx_packets = packets;
5822
5823 bytes = 0;
5824 packets = 0;
7ca3bc58 5825 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5826 for (i = 0; i < adapter->num_tx_queues; i++) {
5827 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5828 restart_queue += tx_ring->tx_stats.restart_queue;
5829 tx_busy += tx_ring->tx_stats.tx_busy;
5830 bytes += tx_ring->stats.bytes;
5831 packets += tx_ring->stats.packets;
5832 }
eb985f09 5833 adapter->restart_queue = restart_queue;
5b7da515
AD		 5834 adapter->tx_busy = tx_busy;
5835 netdev->stats.tx_bytes = bytes;
5836 netdev->stats.tx_packets = packets;
7ca3bc58 5837
7ca647bd 5838 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5839
5840 /* 8 register reads */
6f11eef7
AV		 5841 for (i = 0; i < 8; i++) {
5842 /* for packet buffers not used, the register should read 0 */
5843 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5844 missed_rx += mpc;
7ca647bd
JP		 5845 hwstats->mpc[i] += mpc;
5846 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5847 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5848 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5849 switch (hw->mac.type) {
5850 case ixgbe_mac_82598EB:
1a70db4b
ET		 5851 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5852 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5853 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5854 hwstats->pxonrxc[i] +=
5855 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5856 break;
5857 case ixgbe_mac_82599EB:
b93a2226 5858 case ixgbe_mac_X540:
9a75a1ac
DS		 5859 case ixgbe_mac_X550:
5860 case ixgbe_mac_X550EM_x:
bd508178
AD		 5861 hwstats->pxonrxc[i] +=
5862 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5863 break;
5864 default:
5865 break;
e8e26350 5866 }
6f11eef7 5867 }
1a70db4b
ET		 5868
5869 /*16 register reads */
5870 for (i = 0; i < 16; i++) {
5871 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5872 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5873 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 5874 (hw->mac.type == ixgbe_mac_X540) ||
5875 (hw->mac.type == ixgbe_mac_X550) ||
5876 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 5877 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5878 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5879 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5880 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5881 }
5882 }
5883
7ca647bd 5884 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5885 /* work around hardware counting issue */
7ca647bd 5886 hwstats->gprc -= missed_rx;
6f11eef7 5887
c84d324c
JF		 5888 ixgbe_update_xoff_received(adapter);
5889
6f11eef7 5890 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5891 switch (hw->mac.type) {
5892 case ixgbe_mac_82598EB:
5893 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5894 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5895 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5896 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5897 break;
b93a2226 5898 case ixgbe_mac_X540:
9a75a1ac
DS		 5899 case ixgbe_mac_X550:
5900 case ixgbe_mac_X550EM_x:
5901 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 5902 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5903 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5904 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5905 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5906 case ixgbe_mac_82599EB:
a4d4f629
AD		 5907 for (i = 0; i < 16; i++)
5908 adapter->hw_rx_no_dma_resources +=
5909 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5910 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5911 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5912 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5913 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5914 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5915 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5916 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5917 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5918 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5919#ifdef IXGBE_FCOE
7ca647bd
JP		 5920 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5921 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5922 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5923 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5924 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5925 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5926 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5927 if (adapter->fcoe.ddp_pool) {
5928 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5929 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5930 unsigned int cpu;
5931 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5932 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5933 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5934 noddp += ddp_pool->noddp;
5935 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5936 }
5a1ee270
AD		 5937 hwstats->fcoe_noddp = noddp;
5938 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5939 }
6d45522c 5940#endif /* IXGBE_FCOE */
bd508178
AD		 5941 break;
5942 default:
5943 break;
e8e26350 5944 }
9a799d71 5945 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5946 hwstats->bprc += bprc;
5947 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5948 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5949 hwstats->mprc -= bprc;
5950 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5951 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5952 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5953 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5954 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5955 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5956 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5957 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5958 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5959 hwstats->lxontxc += lxon;
6f11eef7 5960 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5961 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5962 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5963 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5964 /*
5965 * 82598 errata - tx of flow control packets is included in tx counters
5966 */
5967 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5968 hwstats->gptc -= xon_off_tot;
5969 hwstats->mptc -= xon_off_tot;
5970 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5971 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5972 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5973 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5974 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5975 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5976 hwstats->ptc64 -= xon_off_tot;
5977 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5978 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5979 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5980 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5981 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5982 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5983
5984 /* Fill out the OS statistics structure */
7ca647bd 5985 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5986
5987 /* Rx Errors */
7ca647bd 5988 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5989 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5990 netdev->stats.rx_length_errors = hwstats->rlec;
5991 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5992 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5993}
5994
5995/**
d034acf1 5996 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5997 * @adapter: pointer to the device adapter structure
9a799d71 5998 **/
d034acf1 5999static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6000{
cf8280ee 6001 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6002 int i;
cf8280ee 6003
d034acf1
AD		 6004 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6005 return;
6006
6007 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6008
d034acf1 6009 /* if interface is down do nothing */
fe49f04a 6010 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6011 return;
6012
6013 /* do nothing if we are not using signature filters */
6014 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6015 return;
6016
6017 adapter->fdir_overflow++;
6018
93c52dd0
AD		 6019 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6020 for (i = 0; i < adapter->num_tx_queues; i++)
6021 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6022 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6023 /* re-enable flow director interrupts */
6024 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6025 } else {
6026 e_err(probe, "failed to finish FDIR re-initialization, "
6027 "ignored adding FDIR ATR filters\n");
6028 }
93c52dd0
AD		 6029}
6030
6031/**
6032 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6033 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6034 *
6035 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6036 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6037 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6038 * determine if a hang has occurred.
93c52dd0
AD		 6039 */
6040static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6041{
cf8280ee 6042 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6043 u64 eics = 0;
6044 int i;
cf8280ee 6045
09f40aed 6046 /* If we're down, removing or resetting, just bail */
93c52dd0 6047 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6048 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6049 test_bit(__IXGBE_RESETTING, &adapter->state))
6050 return;
22d5a71b 6051
93c52dd0
AD		 6052 /* Force detection of hung controller */
6053 if (netif_carrier_ok(adapter->netdev)) {
6054 for (i = 0; i < adapter->num_tx_queues; i++)
6055 set_check_for_tx_hang(adapter->tx_ring[i]);
6056 }
22d5a71b 6057
fe49f04a
AD		 6058 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6059 /*
6060 * for legacy and MSI interrupts don't set any bits
6061 * that are enabled for EIAM, because this operation
6062 * would set *both* EIMS and EICS for any bit in EIAM
6063 */
6064 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6065 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6066 } else {
6067 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6068 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6069 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6070 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6071 eics |= ((u64)1 << i);
6072 }
cf8280ee 6073 }
9a799d71 6074
93c52dd0 6075 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6076 ixgbe_irq_rearm_queues(adapter, eics);
6077
cf8280ee
JB		 6078}
6079
e8e26350 6080/**
93c52dd0 6081 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6082 * @adapter: pointer to the device adapter structure
6083 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6084 **/
93c52dd0 6085static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6086{
e8e26350 6087 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6088 u32 link_speed = adapter->link_speed;
6089 bool link_up = adapter->link_up;
041441d0 6090 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6091
93c52dd0
AD		 6092 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6093 return;
6094
6095 if (hw->mac.ops.check_link) {
6096 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6097 } else {
93c52dd0
AD		 6098 /* always assume link is up, if no check link function */
6099 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6100 link_up = true;
c4cf55e5 6101 }
041441d0
AD		 6102
6103 if (adapter->ixgbe_ieee_pfc)
6104 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6105
3ebe8fde 6106 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6107 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6108 ixgbe_set_rx_drop_en(adapter);
6109 }
93c52dd0
AD		 6110
6111 if (link_up ||
6112 time_after(jiffies, (adapter->link_check_timeout +
6113 IXGBE_TRY_LINK_TIMEOUT))) {
6114 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6115 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6116 IXGBE_WRITE_FLUSH(hw);
6117 }
6118
6119 adapter->link_up = link_up;
6120 adapter->link_speed = link_speed;
e8e26350
PW		 6121}
6122
107d3018
AD		 6123static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6124{
6125#ifdef CONFIG_IXGBE_DCB
6126 struct net_device *netdev = adapter->netdev;
6127 struct dcb_app app = {
6128 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6129 .protocol = 0,
6130 };
6131 u8 up = 0;
6132
6133 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6134 up = dcb_ieee_getapp_mask(netdev, &app);
6135
6136 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6137#endif
6138}
6139
e8e26350 6140/**
93c52dd0
AD		 6141 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6142 * print link up message
49ce9c2c 6143 * @adapter: pointer to the device adapter structure
e8e26350 6144 **/
93c52dd0 6145static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6146{
93c52dd0 6147 struct net_device *netdev = adapter->netdev;
e8e26350 6148 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6149 struct net_device *upper;
6150 struct list_head *iter;
93c52dd0
AD		 6151 u32 link_speed = adapter->link_speed;
6152 bool flow_rx, flow_tx;
e8e26350 6153
93c52dd0
AD		 6154 /* only continue if link was previously down */
6155 if (netif_carrier_ok(netdev))
a985b6c3 6156 return;
63d6e1d8 6157
93c52dd0 6158 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6159
93c52dd0
AD		 6160 switch (hw->mac.type) {
6161 case ixgbe_mac_82598EB: {
6162 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6163 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6164 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6165 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6166 }
6167 break;
6168 case ixgbe_mac_X540:
9a75a1ac
DS		 6169 case ixgbe_mac_X550:
6170 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6171 case ixgbe_mac_82599EB: {
6172 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6173 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6174 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6175 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6176 }
6177 break;
6178 default:
6179 flow_tx = false;
6180 flow_rx = false;
6181 break;
e8e26350 6182 }
3a6a4eda 6183
6cb562d6
JK		 6184 adapter->last_rx_ptp_check = jiffies;
6185
8fecf67c 6186 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6187 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6188
93c52dd0
AD		 6189 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6190 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6191 "10 Gbps" :
6192 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6193 "1 Gbps" :
6194 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6195 "100 Mbps" :
6196 "unknown speed"))),
6197 ((flow_rx && flow_tx) ? "RX/TX" :
6198 (flow_rx ? "RX" :
6199 (flow_tx ? "TX" : "None"))));
e8e26350 6200
93c52dd0 6201 netif_carrier_on(netdev);
93c52dd0 6202 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6203
cdc04dcc
ET		 6204 /* enable transmits */
6205 netif_tx_wake_all_queues(adapter->netdev);
6206
6207 /* enable any upper devices */
6208 rtnl_lock();
6209 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6210 if (netif_is_macvlan(upper)) {
6211 struct macvlan_dev *vlan = netdev_priv(upper);
6212
6213 if (vlan->fwd_priv)
6214 netif_tx_wake_all_queues(upper);
6215 }
6216 }
6217 rtnl_unlock();
6218
107d3018
AD		 6219 /* update the default user priority for VFs */
6220 ixgbe_update_default_up(adapter);
6221
befa2af7
AD		 6222 /* ping all the active vfs to let them know link has changed */
6223 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6224}
6225
c4cf55e5 6226/**
93c52dd0
AD		 6227 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6228 * print link down message
49ce9c2c 6229 * @adapter: pointer to the adapter structure
c4cf55e5 6230 **/
581330ba 6231static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6232{
cf8280ee 6233 struct net_device *netdev = adapter->netdev;
c4cf55e5 6234 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6235
93c52dd0
AD		 6236 adapter->link_up = false;
6237 adapter->link_speed = 0;
cf8280ee 6238
93c52dd0
AD		 6239 /* only continue if link was up previously */
6240 if (!netif_carrier_ok(netdev))
6241 return;
264857b8 6242
93c52dd0
AD		 6243 /* poll for SFP+ cable when link is down */
6244 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6245 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6246
8fecf67c 6247 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6248 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6249
93c52dd0
AD		 6250 e_info(drv, "NIC Link is Down\n");
6251 netif_carrier_off(netdev);
befa2af7
AD		 6252
6253 /* ping all the active vfs to let them know link has changed */
6254 ixgbe_ping_all_vfs(adapter);
93c52dd0 6255}
e8e26350 6256
07923c17
ET		 6257static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6258{
6259 int i;
6260
6261 for (i = 0; i < adapter->num_tx_queues; i++) {
6262 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6263
6264 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6265 return true;
6266 }
6267
6268 return false;
6269}
6270
6271static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6272{
6273 struct ixgbe_hw *hw = &adapter->hw;
6274 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6275 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6276
6277 int i, j;
6278
6279 if (!adapter->num_vfs)
6280 return false;
6281
9a75a1ac
DS		 6282 /* resetting the PF is only needed for MAC before X550 */
6283 if (hw->mac.type >= ixgbe_mac_X550)
6284 return false;
6285
07923c17
ET		 6286 for (i = 0; i < adapter->num_vfs; i++) {
6287 for (j = 0; j < q_per_pool; j++) {
6288 u32 h, t;
6289
6290 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6291 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6292
6293 if (h != t)
6294 return true;
6295 }
6296 }
6297
6298 return false;
6299}
6300
93c52dd0
AD		 6301/**
6302 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6303 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6304 **/
6305static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6306{
93c52dd0 6307 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6308 if (ixgbe_ring_tx_pending(adapter) ||
6309 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6310 /* We've lost link, so the controller stops DMA,
6311 * but we've got queued Tx work that's never going
6312 * to get done, so reset controller to flush Tx.
6313 * (Do the reset outside of interrupt context).
6314 */
12ff3f3b 6315 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6316 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6317 }
c4cf55e5 6318 }
c4cf55e5
PWJ		 6319}
6320
a985b6c3
GR		 6321static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6322{
6323 u32 ssvpc;
6324
0584d999
GR		 6325 /* Do not perform spoof check for 82598 or if not in IOV mode */
6326 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6327 adapter->num_vfs == 0)
a985b6c3
GR		 6328 return;
6329
6330 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6331
6332 /*
6333 * ssvpc register is cleared on read, if zero then no
6334 * spoofed packets in the last interval.
6335 */
6336 if (!ssvpc)
6337 return;
6338
d6ea0754 6339 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6340}
6341
93c52dd0
AD		 6342/**
6343 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6344 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6345 **/
6346static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6347{
09f40aed 6348 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6349 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6350 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6351 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6352 return;
6353
6354 ixgbe_watchdog_update_link(adapter);
6355
6356 if (adapter->link_up)
6357 ixgbe_watchdog_link_is_up(adapter);
6358 else
6359 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6360
a985b6c3 6361 ixgbe_spoof_check(adapter);
9a799d71 6362 ixgbe_update_stats(adapter);
93c52dd0
AD		 6363
6364 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6365}
10eec955 6366
cf8280ee 6367/**
7086400d 6368 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6369 * @adapter: the ixgbe adapter structure
cf8280ee 6370 **/
7086400d 6371static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6372{
cf8280ee 6373 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6374 s32 err;
cf8280ee 6375
7086400d
AD		 6376 /* not searching for SFP so there is nothing to do here */
6377 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6378 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6379 return;
10eec955 6380
7086400d
AD		 6381 /* someone else is in init, wait until next service event */
6382 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6383 return;
cf8280ee 6384
7086400d
AD		 6385 err = hw->phy.ops.identify_sfp(hw);
6386 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6387 goto sfp_out;
264857b8 6388
7086400d
AD		 6389 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6390 /* If no cable is present, then we need to reset
6391 * the next time we find a good cable. */
6392 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6393 }
9a799d71 6394
7086400d
AD		 6395 /* exit on error */
6396 if (err)
6397 goto sfp_out;
e8e26350 6398
7086400d
AD		 6399 /* exit if reset not needed */
6400 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6401 goto sfp_out;
9a799d71 6402
7086400d 6403 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6404
7086400d
AD		 6405 /*
6406 * A module may be identified correctly, but the EEPROM may not have
6407 * support for that module. setup_sfp() will fail in that case, so
6408 * we should not allow that module to load.
6409 */
6410 if (hw->mac.type == ixgbe_mac_82598EB)
6411 err = hw->phy.ops.reset(hw);
6412 else
6413 err = hw->mac.ops.setup_sfp(hw);
6414
6415 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6416 goto sfp_out;
6417
6418 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6419 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6420
6421sfp_out:
6422 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6423
6424 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6425 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6426 e_dev_err("failed to initialize because an unsupported "
6427 "SFP+ module type was detected.\n");
6428 e_dev_err("Reload the driver after installing a "
6429 "supported module.\n");
6430 unregister_netdev(adapter->netdev);
bc59fcda 6431 }
7086400d 6432}
bc59fcda 6433
7086400d
AD		 6434/**
6435 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6436 * @adapter: the ixgbe adapter structure
7086400d
AD		 6437 **/
6438static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6439{
6440 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6441 u32 speed;
6442 bool autoneg = false;
7086400d
AD		 6443
6444 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6445 return;
6446
6447 /* someone else is in init, wait until next service event */
6448 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6449 return;
6450
6451 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6452
3d292265 6453 speed = hw->phy.autoneg_advertised;
ed33ff66 6454 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6455 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6456
6457 /* setup the highest link when no autoneg */
6458 if (!autoneg) {
6459 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6460 speed = IXGBE_LINK_SPEED_10GB_FULL;
6461 }
6462 }
6463
7086400d 6464 if (hw->mac.ops.setup_link)
fd0326f2 6465 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6466
6467 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6468 adapter->link_check_timeout = jiffies;
6469 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6470}
6471
83c61fa9
GR		 6472#ifdef CONFIG_PCI_IOV
6473static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6474{
6475 int vf;
6476 struct ixgbe_hw *hw = &adapter->hw;
6477 struct net_device *netdev = adapter->netdev;
6478 u32 gpc;
6479 u32 ciaa, ciad;
6480
6481 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6482 if (gpc) /* If incrementing then no need for the check below */
6483 return;
6484 /*
6485 * Check to see if a bad DMA write target from an errant or
6486 * malicious VF has caused a PCIe error. If so then we can
6487 * issue a VFLR to the offending VF(s) and then resume without
6488 * requesting a full slot reset.
6489 */
6490
6491 for (vf = 0; vf < adapter->num_vfs; vf++) {
6492 ciaa = (vf << 16) | 0x80000000;
6493 /* 32 bit read so align, we really want status at offset 6 */
6494 ciaa |= PCI_COMMAND;
9a75a1ac
DS		 6495 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
6496 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_BY_MAC(hw));
83c61fa9
GR		 6497 ciaa &= 0x7FFFFFFF;
6498 /* disable debug mode asap after reading data */
9a75a1ac 6499 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
83c61fa9
GR		 6500 /* Get the upper 16 bits which will be the PCI status reg */
6501 ciad >>= 16;
6502 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6503 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6504 /* Issue VFLR */
6505 ciaa = (vf << 16) | 0x80000000;
6506 ciaa |= 0xA8;
9a75a1ac 6507 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
83c61fa9 6508 ciad = 0x00008000; /* VFLR */
9a75a1ac 6509 IXGBE_WRITE_REG(hw, IXGBE_CIAD_BY_MAC(hw), ciad);
83c61fa9 6510 ciaa &= 0x7FFFFFFF;
9a75a1ac 6511 IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
83c61fa9
GR		 6512 }
6513 }
6514}
6515
6516#endif
7086400d
AD		 6517/**
6518 * ixgbe_service_timer - Timer Call-back
6519 * @data: pointer to adapter cast into an unsigned long
6520 **/
6521static void ixgbe_service_timer(unsigned long data)
6522{
6523 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6524 unsigned long next_event_offset;
83c61fa9 6525 bool ready = true;
7086400d 6526
6bb78cfb
AD		 6527 /* poll faster when waiting for link */
6528 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6529 next_event_offset = HZ / 10;
6530 else
6531 next_event_offset = HZ * 2;
83c61fa9 6532
6bb78cfb 6533#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6534 /*
6535 * don't bother with SR-IOV VF DMA hang check if there are
6536 * no VFs or the link is down
6537 */
6538 if (!adapter->num_vfs ||
6bb78cfb 6539 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6540 goto normal_timer_service;
83c61fa9
GR		 6541
6542 /* If we have VFs allocated then we must check for DMA hangs */
6543 ixgbe_check_for_bad_vf(adapter);
6544 next_event_offset = HZ / 50;
6545 adapter->timer_event_accumulator++;
6546
6bb78cfb 6547 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6548 adapter->timer_event_accumulator = 0;
7086400d 6549 else
6bb78cfb 6550 ready = false;
7086400d 6551
6bb78cfb 6552normal_timer_service:
83c61fa9 6553#endif
7086400d
AD		 6554 /* Reset the timer */
6555 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6556
83c61fa9
GR		 6557 if (ready)
6558 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6559}
6560
c83c6cbd
AD		 6561static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6562{
6563 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6564 return;
6565
6566 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6567
09f40aed 6568 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6569 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6570 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6571 test_bit(__IXGBE_RESETTING, &adapter->state))
6572 return;
6573
6574 ixgbe_dump(adapter);
6575 netdev_err(adapter->netdev, "Reset adapter\n");
6576 adapter->tx_timeout_count++;
6577
8f4c5c9f 6578 rtnl_lock();
c83c6cbd 6579 ixgbe_reinit_locked(adapter);
8f4c5c9f 6580 rtnl_unlock();
c83c6cbd
AD		 6581}
6582
7086400d
AD		 6583/**
6584 * ixgbe_service_task - manages and runs subtasks
6585 * @work: pointer to work_struct containing our data
6586 **/
6587static void ixgbe_service_task(struct work_struct *work)
6588{
6589 struct ixgbe_adapter *adapter = container_of(work,
6590 struct ixgbe_adapter,
6591 service_task);
b0483c8f
MR		 6592 if (ixgbe_removed(adapter->hw.hw_addr)) {
6593 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6594 rtnl_lock();
6595 ixgbe_down(adapter);
6596 rtnl_unlock();
6597 }
6598 ixgbe_service_event_complete(adapter);
6599 return;
6600 }
c83c6cbd 6601 ixgbe_reset_subtask(adapter);
7086400d
AD		 6602 ixgbe_sfp_detection_subtask(adapter);
6603 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6604 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6605 ixgbe_watchdog_subtask(adapter);
d034acf1 6606 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6607 ixgbe_check_hang_subtask(adapter);
891dc082 6608
8fecf67c 6609 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6610 ixgbe_ptp_overflow_check(adapter);
6611 ixgbe_ptp_rx_hang(adapter);
6612 }
7086400d
AD		 6613
6614 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6615}
6616
fd0db0ed
AD		 6617static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6618 struct ixgbe_tx_buffer *first,
244e27ad 6619 u8 *hdr_len)
897ab156 6620{
fd0db0ed 6621 struct sk_buff *skb = first->skb;
897ab156
AD		 6622 u32 vlan_macip_lens, type_tucmd;
6623 u32 mss_l4len_idx, l4len;
2049e1f6 6624 int err;
9a799d71 6625
8f4fbb9b
AD		 6626 if (skb->ip_summed != CHECKSUM_PARTIAL)
6627 return 0;
6628
897ab156
AD		 6629 if (!skb_is_gso(skb))
6630 return 0;
9a799d71 6631
2049e1f6
FR		 6632 err = skb_cow_head(skb, 0);
6633 if (err < 0)
6634 return err;
9a799d71 6635
897ab156
AD		 6636 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6637 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6638
a1108ffd 6639 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6640 struct iphdr *iph = ip_hdr(skb);
6641 iph->tot_len = 0;
6642 iph->check = 0;
6643 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6644 iph->daddr, 0,
6645 IPPROTO_TCP,
6646 0);
6647 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6648 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6649 IXGBE_TX_FLAGS_CSUM |
6650 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6651 } else if (skb_is_gso_v6(skb)) {
6652 ipv6_hdr(skb)->payload_len = 0;
6653 tcp_hdr(skb)->check =
6654 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6655 &ipv6_hdr(skb)->daddr,
6656 0, IPPROTO_TCP, 0);
244e27ad
AD		 6657 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6658 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6659 }
6660
091a6246 6661 /* compute header lengths */
897ab156
AD		 6662 l4len = tcp_hdrlen(skb);
6663 *hdr_len = skb_transport_offset(skb) + l4len;
6664
091a6246
AD		 6665 /* update gso size and bytecount with header size */
6666 first->gso_segs = skb_shinfo(skb)->gso_segs;
6667 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6668
c44f5f51 6669 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6670 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6671 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6672
6673 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6674 vlan_macip_lens = skb_network_header_len(skb);
6675 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6676 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6677
6678 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6679 mss_l4len_idx);
897ab156
AD		 6680
6681 return 1;
6682}
6683
244e27ad
AD		 6684static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6685 struct ixgbe_tx_buffer *first)
7ca647bd 6686{
fd0db0ed 6687 struct sk_buff *skb = first->skb;
897ab156
AD		 6688 u32 vlan_macip_lens = 0;
6689 u32 mss_l4len_idx = 0;
6690 u32 type_tucmd = 0;
7ca647bd 6691
897ab156 6692 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6693 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6694 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6695 return;
897ab156
AD		 6696 } else {
6697 u8 l4_hdr = 0;
244e27ad 6698 switch (first->protocol) {
a1108ffd 6699 case htons(ETH_P_IP):
897ab156
AD		 6700 vlan_macip_lens |= skb_network_header_len(skb);
6701 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6702 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6703 break;
a1108ffd 6704 case htons(ETH_P_IPV6):
897ab156
AD		 6705 vlan_macip_lens |= skb_network_header_len(skb);
6706 l4_hdr = ipv6_hdr(skb)->nexthdr;
6707 break;
6708 default:
6709 if (unlikely(net_ratelimit())) {
6710 dev_warn(tx_ring->dev,
6711 "partial checksum but proto=%x!\n",
244e27ad 6712 first->protocol);
897ab156 6713 }
7ca647bd
JP		 6714 break;
6715 }
897ab156
AD		 6716
6717 switch (l4_hdr) {
7ca647bd 6718 case IPPROTO_TCP:
897ab156
AD		 6719 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6720 mss_l4len_idx = tcp_hdrlen(skb) <<
6721 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6722 break;
6723 case IPPROTO_SCTP:
897ab156
AD		 6724 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6725 mss_l4len_idx = sizeof(struct sctphdr) <<
6726 IXGBE_ADVTXD_L4LEN_SHIFT;
6727 break;
6728 case IPPROTO_UDP:
6729 mss_l4len_idx = sizeof(struct udphdr) <<
6730 IXGBE_ADVTXD_L4LEN_SHIFT;
6731 break;
6732 default:
6733 if (unlikely(net_ratelimit())) {
6734 dev_warn(tx_ring->dev,
6735 "partial checksum but l4 proto=%x!\n",
244e27ad 6736 l4_hdr);
897ab156 6737 }
7ca647bd
JP		 6738 break;
6739 }
244e27ad
AD		 6740
6741 /* update TX checksum flag */
6742 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6743 }
6744
244e27ad 6745 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6746 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6747 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6748
897ab156
AD		 6749 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6750 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6751}
6752
472148c3
AD		 6753#define IXGBE_SET_FLAG(_input, _flag, _result) \
6754 ((_flag <= _result) ? \
6755 ((u32)(_input & _flag) * (_result / _flag)) : \
6756 ((u32)(_input & _flag) / (_flag / _result)))
6757
6758static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6759{
d3d00239 6760 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6761 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6762 IXGBE_ADVTXD_DCMD_DEXT |
6763 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6764
d3d00239 6765 /* set HW vlan bit if vlan is present */
472148c3
AD		 6766 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6767 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6768
d3d00239 6769 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6770 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6771 IXGBE_ADVTXD_DCMD_TSE);
6772
6773 /* set timestamp bit if present */
6774 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6775 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6776
62748b7b 6777 /* insert frame checksum */
472148c3 6778 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6779
d3d00239
AD		 6780 return cmd_type;
6781}
9a799d71 6782
729739b7
AD		 6783static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6784 u32 tx_flags, unsigned int paylen)
d3d00239 6785{
472148c3 6786 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6787
d3d00239 6788 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6789 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6790 IXGBE_TX_FLAGS_CSUM,
6791 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6792
93f5b3c1 6793 /* enble IPv4 checksum for TSO */
472148c3
AD		 6794 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6795 IXGBE_TX_FLAGS_IPV4,
6796 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6797
7f9643fd
AD		 6798 /*
6799 * Check Context must be set if Tx switch is enabled, which it
6800 * always is for case where virtual functions are running
6801 */
472148c3
AD		 6802 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6803 IXGBE_TX_FLAGS_CC,
6804 IXGBE_ADVTXD_CC);
7f9643fd 6805
472148c3 6806 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6807}
44df32c5 6808
2367a173
DB		 6809static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6810{
6811 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6812
6813 /* Herbert's original patch had:
6814 * smp_mb__after_netif_stop_queue();
6815 * but since that doesn't exist yet, just open code it.
6816 */
6817 smp_mb();
6818
6819 /* We need to check again in a case another CPU has just
6820 * made room available.
6821 */
6822 if (likely(ixgbe_desc_unused(tx_ring) < size))
6823 return -EBUSY;
6824
6825 /* A reprieve! - use start_queue because it doesn't call schedule */
6826 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6827 ++tx_ring->tx_stats.restart_queue;
6828 return 0;
6829}
6830
6831static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6832{
6833 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6834 return 0;
6835
6836 return __ixgbe_maybe_stop_tx(tx_ring, size);
6837}
6838
d3d00239
AD		 6839#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6840 IXGBE_TXD_CMD_RS)
6841
6842static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6843 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6844 const u8 hdr_len)
6845{
fd0db0ed 6846 struct sk_buff *skb = first->skb;
729739b7 6847 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6848 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6849 struct skb_frag_struct *frag;
6850 dma_addr_t dma;
6851 unsigned int data_len, size;
244e27ad 6852 u32 tx_flags = first->tx_flags;
472148c3 6853 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6854 u16 i = tx_ring->next_to_use;
d3d00239 6855
729739b7
AD		 6856 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6857
ec718254
AD		 6858 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6859
6860 size = skb_headlen(skb);
6861 data_len = skb->data_len;
729739b7 6862
d3d00239
AD		 6863#ifdef IXGBE_FCOE
6864 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6865 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6866 size -= sizeof(struct fcoe_crc_eof) - data_len;
6867 data_len = 0;
729739b7
AD		 6868 } else {
6869 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6870 }
6871 }
44df32c5 6872
d3d00239 6873#endif
729739b7 6874 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6875
ec718254 6876 tx_buffer = first;
9a799d71 6877
ec718254
AD		 6878 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6879 if (dma_mapping_error(tx_ring->dev, dma))
6880 goto dma_error;
6881
6882 /* record length, and DMA address */
6883 dma_unmap_len_set(tx_buffer, len, size);
6884 dma_unmap_addr_set(tx_buffer, dma, dma);
6885
6886 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6887
729739b7 6888 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6889 tx_desc->read.cmd_type_len =
472148c3 6890 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6891
d3d00239 6892 i++;
729739b7 6893 tx_desc++;
d3d00239 6894 if (i == tx_ring->count) {
e4f74028 6895 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6896 i = 0;
6897 }
ec718254 6898 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6899
6900 dma += IXGBE_MAX_DATA_PER_TXD;
6901 size -= IXGBE_MAX_DATA_PER_TXD;
6902
6903 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6904 }
e5a43549 6905
729739b7
AD		 6906 if (likely(!data_len))
6907 break;
9a799d71 6908
472148c3 6909 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6910
729739b7
AD		 6911 i++;
6912 tx_desc++;
6913 if (i == tx_ring->count) {
6914 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6915 i = 0;
6916 }
ec718254 6917 tx_desc->read.olinfo_status = 0;
9a799d71 6918
d3d00239 6919#ifdef IXGBE_FCOE
9e903e08 6920 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6921#else
9e903e08 6922 size = skb_frag_size(frag);
d3d00239
AD		 6923#endif
6924 data_len -= size;
9a799d71 6925
729739b7
AD		 6926 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6927 DMA_TO_DEVICE);
9a799d71 6928
729739b7 6929 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6930 }
9a799d71 6931
729739b7 6932 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6933 cmd_type |= size | IXGBE_TXD_CMD;
6934 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6935
091a6246 6936 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6937
d3d00239
AD		 6938 /* set the timestamp */
6939 first->time_stamp = jiffies;
9a799d71
AK		 6940
6941 /*
729739b7
AD		 6942 * Force memory writes to complete before letting h/w know there
6943 * are new descriptors to fetch. (Only applicable for weak-ordered
6944 * memory model archs, such as IA-64).
6945 *
6946 * We also need this memory barrier to make certain all of the
6947 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6948 */
6949 wmb();
6950
d3d00239
AD		 6951 /* set next_to_watch value indicating a packet is present */
6952 first->next_to_watch = tx_desc;
6953
729739b7
AD		 6954 i++;
6955 if (i == tx_ring->count)
6956 i = 0;
6957
6958 tx_ring->next_to_use = i;
6959
2367a173
DB		 6960 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6961
6962 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
9c938cdd
DB		 6963 /* notify HW of packet */
6964 ixgbe_write_tail(tx_ring, i);
6965 }
2367a173 6966
d3d00239
AD		 6967 return;
6968dma_error:
729739b7 6969 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6970
6971 /* clear dma mappings for failed tx_buffer_info map */
6972 for (;;) {
729739b7
AD		 6973 tx_buffer = &tx_ring->tx_buffer_info[i];
6974 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6975 if (tx_buffer == first)
d3d00239
AD		 6976 break;
6977 if (i == 0)
6978 i = tx_ring->count;
6979 i--;
6980 }
6981
d3d00239 6982 tx_ring->next_to_use = i;
9a799d71
AK		 6983}
6984
fd0db0ed 6985static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6986 struct ixgbe_tx_buffer *first)
69830529
AD		 6987{
6988 struct ixgbe_q_vector *q_vector = ring->q_vector;
6989 union ixgbe_atr_hash_dword input = { .dword = 0 };
6990 union ixgbe_atr_hash_dword common = { .dword = 0 };
6991 union {
6992 unsigned char *network;
6993 struct iphdr *ipv4;
6994 struct ipv6hdr *ipv6;
6995 } hdr;
ee9e0f0b 6996 struct tcphdr *th;
905e4a41 6997 __be16 vlan_id;
c4cf55e5 6998
69830529
AD		 6999 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7000 if (!q_vector)
7001 return;
7002
7003 /* do nothing if sampling is disabled */
7004 if (!ring->atr_sample_rate)
d3ead241 7005 return;
c4cf55e5 7006
69830529 7007 ring->atr_count++;
c4cf55e5 7008
69830529 7009 /* snag network header to get L4 type and address */
fd0db0ed 7010 hdr.network = skb_network_header(first->skb);
69830529
AD		 7011
7012 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 7013 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 7014 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 7015 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 7016 hdr.ipv4->protocol != IPPROTO_TCP))
7017 return;
ee9e0f0b 7018
fd0db0ed 7019 th = tcp_hdr(first->skb);
c4cf55e5 7020
66f32a8b
AD		 7021 /* skip this packet since it is invalid or the socket is closing */
7022 if (!th || th->fin)
69830529
AD		 7023 return;
7024
7025 /* sample on all syn packets or once every atr sample count */
7026 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7027 return;
7028
7029 /* reset sample count */
7030 ring->atr_count = 0;
7031
244e27ad 7032 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7033
7034 /*
7035 * src and dst are inverted, think how the receiver sees them
7036 *
7037 * The input is broken into two sections, a non-compressed section
7038 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7039 * is XORed together and stored in the compressed dword.
7040 */
7041 input.formatted.vlan_id = vlan_id;
7042
7043 /*
7044 * since src port and flex bytes occupy the same word XOR them together
7045 * and write the value to source port portion of compressed dword
7046 */
244e27ad 7047 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7048 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7049 else
244e27ad 7050 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7051 common.port.dst ^= th->source;
7052
a1108ffd 7053 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7054 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7055 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7056 } else {
7057 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7058 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7059 hdr.ipv6->saddr.s6_addr32[1] ^
7060 hdr.ipv6->saddr.s6_addr32[2] ^
7061 hdr.ipv6->saddr.s6_addr32[3] ^
7062 hdr.ipv6->daddr.s6_addr32[0] ^
7063 hdr.ipv6->daddr.s6_addr32[1] ^
7064 hdr.ipv6->daddr.s6_addr32[2] ^
7065 hdr.ipv6->daddr.s6_addr32[3];
7066 }
c4cf55e5
PWJ		 7067
7068 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7069 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7070 input, common, ring->queue_index);
c4cf55e5
PWJ		 7071}
7072
f663dd9a 7073static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7074 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7075{
f663dd9a
JW		 7076 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7077#ifdef IXGBE_FCOE
97488bd1
AD		 7078 struct ixgbe_adapter *adapter;
7079 struct ixgbe_ring_feature *f;
7080 int txq;
f663dd9a
JW		 7081#endif
7082
7083 if (fwd_adapter)
7084 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7085
7086#ifdef IXGBE_FCOE
5e09a105 7087
97488bd1
AD		 7088 /*
7089 * only execute the code below if protocol is FCoE
7090 * or FIP and we have FCoE enabled on the adapter
7091 */
7092 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7093 case htons(ETH_P_FCOE):
7094 case htons(ETH_P_FIP):
97488bd1 7095 adapter = netdev_priv(dev);
c087663e 7096
97488bd1
AD		 7097 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7098 break;
7099 default:
99932d4f 7100 return fallback(dev, skb);
97488bd1 7101 }
c087663e 7102
97488bd1 7103 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7104
97488bd1
AD		 7105 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7106 smp_processor_id();
56075a98 7107
97488bd1
AD		 7108 while (txq >= f->indices)
7109 txq -= f->indices;
c4cf55e5 7110
97488bd1 7111 return txq + f->offset;
f663dd9a 7112#else
99932d4f 7113 return fallback(dev, skb);
f663dd9a 7114#endif
09a3b1f8
SH		 7115}
7116
fc77dc3c 7117netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7118 struct ixgbe_adapter *adapter,
7119 struct ixgbe_ring *tx_ring)
9a799d71 7120{
d3d00239 7121 struct ixgbe_tx_buffer *first;
5f715823 7122 int tso;
d3d00239 7123 u32 tx_flags = 0;
a535c30e 7124 unsigned short f;
a535c30e 7125 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7126 __be16 protocol = skb->protocol;
63544e9c 7127 u8 hdr_len = 0;
5e09a105 7128
a535c30e
AD		 7129 /*
7130 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7131 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7132 * + 2 desc gap to keep tail from touching head,
7133 * + 1 desc for context descriptor,
7134 * otherwise try next time
7135 */
a535c30e
AD		 7136 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7137 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7138
a535c30e
AD		 7139 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7140 tx_ring->tx_stats.tx_busy++;
7141 return NETDEV_TX_BUSY;
7142 }
7143
fd0db0ed
AD		 7144 /* record the location of the first descriptor for this packet */
7145 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7146 first->skb = skb;
091a6246
AD		 7147 first->bytecount = skb->len;
7148 first->gso_segs = 1;
fd0db0ed 7149
66f32a8b 7150 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7151 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7152 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7153 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7154 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7155 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7156 struct vlan_hdr *vhdr, _vhdr;
7157 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7158 if (!vhdr)
7159 goto out_drop;
7160
7161 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7162 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7163 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7164 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7165 }
7166
d5234933
MR		 7167 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7168 adapter->ptp_clock &&
7169 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7170 &adapter->state)) {
3a6a4eda
JK		 7171 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7172 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7173
7174 /* schedule check for Tx timestamp */
7175 adapter->ptp_tx_skb = skb_get(skb);
7176 adapter->ptp_tx_start = jiffies;
7177 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7178 }
3a6a4eda 7179
ff29a86e
JK		 7180 skb_tx_timestamp(skb);
7181
9e0c5648
AD		 7182#ifdef CONFIG_PCI_IOV
7183 /*
7184 * Use the l2switch_enable flag - would be false if the DMA
7185 * Tx switch had been disabled.
7186 */
7187 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7188 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7189
7190#endif
32701dc2 7191 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7192 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7193 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7194 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7195 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7196 tx_flags |= (skb->priority & 0x7) <<
7197 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7198 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7199 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7200
7201 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7202 goto out_drop;
7203 vhdr = (struct vlan_ethhdr *)skb->data;
7204 vhdr->h_vlan_TCI = htons(tx_flags >>
7205 IXGBE_TX_FLAGS_VLAN_SHIFT);
7206 } else {
7207 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7208 }
9a799d71 7209 }
eacd73f7 7210
244e27ad
AD		 7211 /* record initial flags and protocol */
7212 first->tx_flags = tx_flags;
7213 first->protocol = protocol;
7214
eacd73f7 7215#ifdef IXGBE_FCOE
66f32a8b 7216 /* setup tx offload for FCoE */
a1108ffd 7217 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7218 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7219 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7220 if (tso < 0)
7221 goto out_drop;
9a799d71 7222
66f32a8b 7223 goto xmit_fcoe;
eacd73f7 7224 }
9a799d71 7225
66f32a8b 7226#endif /* IXGBE_FCOE */
244e27ad 7227 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7228 if (tso < 0)
897ab156 7229 goto out_drop;
244e27ad
AD		 7230 else if (!tso)
7231 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7232
7233 /* add the ATR filter if ATR is on */
7234 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7235 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7236
7237#ifdef IXGBE_FCOE
7238xmit_fcoe:
7239#endif /* IXGBE_FCOE */
244e27ad 7240 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7241
9a799d71 7242 return NETDEV_TX_OK;
897ab156
AD		 7243
7244out_drop:
fd0db0ed
AD		 7245 dev_kfree_skb_any(first->skb);
7246 first->skb = NULL;
7247
897ab156 7248 return NETDEV_TX_OK;
9a799d71
AK		 7249}
7250
2a47fa45
JF		 7251static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7252 struct net_device *netdev,
7253 struct ixgbe_ring *ring)
84418e3b
AD		 7254{
7255 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7256 struct ixgbe_ring *tx_ring;
7257
a50c29dd
AD		 7258 /*
7259 * The minimum packet size for olinfo paylen is 17 so pad the skb
7260 * in order to meet this minimum size requirement.
7261 */
f73332fc
SH		 7262 if (unlikely(skb->len < 17)) {
7263 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7264 return NETDEV_TX_OK;
7265 skb->len = 17;
71a49f77 7266 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7267 }
7268
2a47fa45
JF		 7269 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7270
fc77dc3c 7271 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7272}
7273
2a47fa45
JF		 7274static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7275 struct net_device *netdev)
7276{
7277 return __ixgbe_xmit_frame(skb, netdev, NULL);
7278}
7279
9a799d71
AK		 7280/**
7281 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7282 * @netdev: network interface device structure
7283 * @p: pointer to an address structure
7284 *
7285 * Returns 0 on success, negative on failure
7286 **/
7287static int ixgbe_set_mac(struct net_device *netdev, void *p)
7288{
7289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7290 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7291 struct sockaddr *addr = p;
5d7daa35 7292 int ret;
9a799d71
AK		 7293
7294 if (!is_valid_ether_addr(addr->sa_data))
7295 return -EADDRNOTAVAIL;
7296
5d7daa35 7297 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7298 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7299 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7300
5d7daa35
JK		 7301 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7302 return ret > 0 ? 0 : ret;
9a799d71
AK		 7303}
7304
6b73e10d
BH		 7305static int
7306ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7307{
7308 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7309 struct ixgbe_hw *hw = &adapter->hw;
7310 u16 value;
7311 int rc;
7312
7313 if (prtad != hw->phy.mdio.prtad)
7314 return -EINVAL;
7315 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7316 if (!rc)
7317 rc = value;
7318 return rc;
7319}
7320
7321static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7322 u16 addr, u16 value)
7323{
7324 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7325 struct ixgbe_hw *hw = &adapter->hw;
7326
7327 if (prtad != hw->phy.mdio.prtad)
7328 return -EINVAL;
7329 return hw->phy.ops.write_reg(hw, addr, devad, value);
7330}
7331
7332static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7333{
7334 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7335
3a6a4eda 7336 switch (cmd) {
3a6a4eda 7337 case SIOCSHWTSTAMP:
93501d48
JK		 7338 return ixgbe_ptp_set_ts_config(adapter, req);
7339 case SIOCGHWTSTAMP:
7340 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7341 default:
7342 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7343 }
6b73e10d
BH		 7344}
7345
0365e6e4
PW		 7346/**
7347 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7348 * netdev->dev_addrs
0365e6e4
PW		 7349 * @netdev: network interface device structure
7350 *
7351 * Returns non-zero on failure
7352 **/
7353static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7354{
7355 int err = 0;
7356 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7357 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7358
7fa7c9dc 7359 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7360 rtnl_lock();
7fa7c9dc 7361 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7362 rtnl_unlock();
7fa7c9dc
AD		 7363
7364 /* update SAN MAC vmdq pool selection */
7365 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7366 }
7367 return err;
7368}
7369
7370/**
7371 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7372 * netdev->dev_addrs
0365e6e4
PW		 7373 * @netdev: network interface device structure
7374 *
7375 * Returns non-zero on failure
7376 **/
7377static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7378{
7379 int err = 0;
7380 struct ixgbe_adapter *adapter = netdev_priv(dev);
7381 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7382
7383 if (is_valid_ether_addr(mac->san_addr)) {
7384 rtnl_lock();
7385 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7386 rtnl_unlock();
7387 }
7388 return err;
7389}
7390
9a799d71
AK		 7391#ifdef CONFIG_NET_POLL_CONTROLLER
7392/*
7393 * Polling 'interrupt' - used by things like netconsole to send skbs
7394 * without having to re-enable interrupts. It's not called while
7395 * the interrupt routine is executing.
7396 */
7397static void ixgbe_netpoll(struct net_device *netdev)
7398{
7399 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7400 int i;
9a799d71 7401
1a647bd2
AD		 7402 /* if interface is down do nothing */
7403 if (test_bit(__IXGBE_DOWN, &adapter->state))
7404 return;
7405
9a799d71 7406 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7407 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7408 for (i = 0; i < adapter->num_q_vectors; i++)
7409 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7410 } else {
7411 ixgbe_intr(adapter->pdev->irq, netdev);
7412 }
9a799d71 7413 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7414}
9a799d71 7415
581330ba 7416#endif
de1036b1
ED		 7417static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7418 struct rtnl_link_stats64 *stats)
7419{
7420 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7421 int i;
7422
1a51502b 7423 rcu_read_lock();
de1036b1 7424 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7425 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7426 u64 bytes, packets;
7427 unsigned int start;
7428
1a51502b
ED		 7429 if (ring) {
7430 do {
57a7744e 7431 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7432 packets = ring->stats.packets;
7433 bytes = ring->stats.bytes;
57a7744e 7434 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7435 stats->rx_packets += packets;
7436 stats->rx_bytes += bytes;
7437 }
de1036b1 7438 }
1ac9ad13
ED		 7439
7440 for (i = 0; i < adapter->num_tx_queues; i++) {
7441 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7442 u64 bytes, packets;
7443 unsigned int start;
7444
7445 if (ring) {
7446 do {
57a7744e 7447 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7448 packets = ring->stats.packets;
7449 bytes = ring->stats.bytes;
57a7744e 7450 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7451 stats->tx_packets += packets;
7452 stats->tx_bytes += bytes;
7453 }
7454 }
1a51502b 7455 rcu_read_unlock();
de1036b1
ED		 7456 /* following stats updated by ixgbe_watchdog_task() */
7457 stats->multicast = netdev->stats.multicast;
7458 stats->rx_errors = netdev->stats.rx_errors;
7459 stats->rx_length_errors = netdev->stats.rx_length_errors;
7460 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7461 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7462 return stats;
7463}
7464
8af3c33f 7465#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7466/**
7467 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7468 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7469 * @tc: number of traffic classes currently enabled
7470 *
7471 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7472 * 802.1Q priority maps to a packet buffer that exists.
7473 */
7474static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7475{
7476 struct ixgbe_hw *hw = &adapter->hw;
7477 u32 reg, rsave;
7478 int i;
7479
7480 /* 82598 have a static priority to TC mapping that can not
7481 * be changed so no validation is needed.
7482 */
7483 if (hw->mac.type == ixgbe_mac_82598EB)
7484 return;
7485
7486 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7487 rsave = reg;
7488
7489 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7490 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7491
7492 /* If up2tc is out of bounds default to zero */
7493 if (up2tc > tc)
7494 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7495 }
7496
7497 if (reg != rsave)
7498 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7499
7500 return;
7501}
7502
02debdc9
AD		 7503/**
7504 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7505 * @adapter: Pointer to adapter struct
7506 *
7507 * Populate the netdev user priority to tc map
7508 */
7509static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7510{
7511 struct net_device *dev = adapter->netdev;
7512 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7513 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7514 u8 prio;
7515
7516 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7517 u8 tc = 0;
7518
7519 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7520 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7521 else if (ets)
7522 tc = ets->prio_tc[prio];
7523
7524 netdev_set_prio_tc_map(dev, prio, tc);
7525 }
7526}
7527
cca73c59 7528#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7529/**
7530 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7531 *
7532 * @netdev: net device to configure
7533 * @tc: number of traffic classes to enable
7534 */
7535int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7536{
8b1c0b24
JF		 7537 struct ixgbe_adapter *adapter = netdev_priv(dev);
7538 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7539 bool pools;
8b1c0b24 7540
8b1c0b24 7541 /* Hardware supports up to 8 traffic classes */
4de2a022 7542 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7543 (hw->mac.type == ixgbe_mac_82598EB &&
7544 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7545 return -EINVAL;
7546
2a47fa45
JF		 7547 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7548 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7549 return -EBUSY;
7550
8b1c0b24 7551 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7552 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7553 * hardware is not flexible enough to do this dynamically.
7554 */
7555 if (netif_running(dev))
7556 ixgbe_close(dev);
7557 ixgbe_clear_interrupt_scheme(adapter);
7558
cca73c59 7559#ifdef CONFIG_IXGBE_DCB
e7589eab 7560 if (tc) {
8b1c0b24 7561 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7562 ixgbe_set_prio_tc_map(adapter);
7563
e7589eab 7564 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7565
943561d3
AD		 7566 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7567 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7568 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7569 }
e7589eab 7570 } else {
8b1c0b24 7571 netdev_reset_tc(dev);
02debdc9 7572
943561d3
AD		 7573 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7574 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7575
7576 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7577
7578 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7579 adapter->dcb_cfg.pfc_mode_enable = false;
7580 }
7581
8b1c0b24 7582 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7583
7584#endif /* CONFIG_IXGBE_DCB */
7585 ixgbe_init_interrupt_scheme(adapter);
7586
8b1c0b24 7587 if (netif_running(dev))
cca73c59 7588 return ixgbe_open(dev);
8b1c0b24
JF		 7589
7590 return 0;
7591}
de1036b1 7592
da36b647
GR		 7593#ifdef CONFIG_PCI_IOV
7594void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7595{
7596 struct net_device *netdev = adapter->netdev;
7597
7598 rtnl_lock();
da36b647 7599 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7600 rtnl_unlock();
7601}
7602
7603#endif
082757af
DS		 7604void ixgbe_do_reset(struct net_device *netdev)
7605{
7606 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7607
7608 if (netif_running(netdev))
7609 ixgbe_reinit_locked(adapter);
7610 else
7611 ixgbe_reset(adapter);
7612}
7613
c8f44aff 7614static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7615 netdev_features_t features)
082757af
DS		 7616{
7617 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7618
082757af 7619 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7620 if (!(features & NETIF_F_RXCSUM))
7621 features &= ~NETIF_F_LRO;
082757af 7622
567d2de2
AD		 7623 /* Turn off LRO if not RSC capable */
7624 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7625 features &= ~NETIF_F_LRO;
8e2813f5 7626
567d2de2 7627 return features;
082757af
DS		 7628}
7629
c8f44aff 7630static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7631 netdev_features_t features)
082757af
DS		 7632{
7633 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7634 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7635 bool need_reset = false;
7636
082757af 7637 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7638 if (!(features & NETIF_F_LRO)) {
7639 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7640 need_reset = true;
567d2de2
AD		 7641 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7642 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7643 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7644 if (adapter->rx_itr_setting == 1 ||
7645 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7646 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7647 need_reset = true;
7648 } else if ((changed ^ features) & NETIF_F_LRO) {
7649 e_info(probe, "rx-usecs set too low, "
7650 "disabling RSC\n");
082757af
DS		 7651 }
7652 }
7653
7654 /*
7655 * Check if Flow Director n-tuple support was enabled or disabled. If
7656 * the state changed, we need to reset.
7657 */
39cb681b
AD		 7658 switch (features & NETIF_F_NTUPLE) {
7659 case NETIF_F_NTUPLE:
567d2de2 7660 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7661 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7662 need_reset = true;
7663
567d2de2
AD		 7664 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7665 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7666 break;
7667 default:
7668 /* turn off perfect filters, enable ATR and reset */
7669 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7670 need_reset = true;
7671
7672 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7673
7674 /* We cannot enable ATR if SR-IOV is enabled */
7675 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7676 break;
7677
7678 /* We cannot enable ATR if we have 2 or more traffic classes */
7679 if (netdev_get_num_tc(netdev) > 1)
7680 break;
7681
7682 /* We cannot enable ATR if RSS is disabled */
7683 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7684 break;
7685
7686 /* A sample rate of 0 indicates ATR disabled */
7687 if (!adapter->atr_sample_rate)
7688 break;
7689
7690 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7691 break;
082757af
DS		 7692 }
7693
f646968f 7694 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7695 ixgbe_vlan_strip_enable(adapter);
7696 else
7697 ixgbe_vlan_strip_disable(adapter);
7698
3f2d1c0f
BG		 7699 if (changed & NETIF_F_RXALL)
7700 need_reset = true;
7701
567d2de2 7702 netdev->features = features;
082757af
DS		 7703 if (need_reset)
7704 ixgbe_do_reset(netdev);
7705
7706 return 0;
082757af
DS		 7707}
7708
edc7d573 7709static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7710 struct net_device *dev,
6b6e2725 7711 const unsigned char *addr,
0f4b0add
JF		 7712 u16 flags)
7713{
bcfd3432 7714 /* guarantee we can provide a unique filter for the unicast address */
46acc460 7715 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 7716 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7717 return -ENOMEM;
0f4b0add
JF		 7718 }
7719
bcfd3432 7720 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add
JF		 7721}
7722
815cccbf
JF		 7723static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7724 struct nlmsghdr *nlh)
7725{
7726 struct ixgbe_adapter *adapter = netdev_priv(dev);
7727 struct nlattr *attr, *br_spec;
7728 int rem;
7729
7730 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7731 return -EOPNOTSUPP;
7732
7733 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 7734 if (!br_spec)
7735 return -EINVAL;
815cccbf
JF		 7736
7737 nla_for_each_nested(attr, br_spec, rem) {
7738 __u16 mode;
7739 u32 reg = 0;
7740
7741 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7742 continue;
7743
b7c1a314
TG		 7744 if (nla_len(attr) < sizeof(mode))
7745 return -EINVAL;
7746
815cccbf 7747 mode = nla_get_u16(attr);
9b735984 7748 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7749 reg = 0;
9b735984
GR		 7750 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7751 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7752 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7753 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7754 } else
815cccbf
JF		 7755 return -EINVAL;
7756
7757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7758
7759 e_info(drv, "enabling bridge mode: %s\n",
7760 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7761 }
7762
7763 return 0;
7764}
7765
7766static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7767 struct net_device *dev,
7768 u32 filter_mask)
815cccbf
JF		 7769{
7770 struct ixgbe_adapter *adapter = netdev_priv(dev);
7771 u16 mode;
7772
7773 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7774 return 0;
7775
9b735984 7776 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7777 mode = BRIDGE_MODE_VEB;
7778 else
7779 mode = BRIDGE_MODE_VEPA;
7780
7781 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7782}
7783
2a47fa45
JF		 7784static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7785{
7786 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7787 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 7788 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 7789 unsigned int limit;
2a47fa45
JF		 7790 int pool, err;
7791
aac2f1bf
JK		 7792 /* Hardware has a limited number of available pools. Each VF, and the
7793 * PF require a pool. Check to ensure we don't attempt to use more
7794 * then the available number of pools.
7795 */
7796 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
7797 return ERR_PTR(-EINVAL);
7798
219354d4
JF		 7799#ifdef CONFIG_RPS
7800 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7801 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7802 vdev->name);
7803 return ERR_PTR(-EINVAL);
7804 }
7805#endif
2a47fa45 7806 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7807 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7808 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7809 netdev_info(pdev,
7810 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7811 pdev->name);
7812 return ERR_PTR(-EINVAL);
7813 }
7814
7815 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7816 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7817 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7818 return ERR_PTR(-EBUSY);
7819
7820 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7821 if (!fwd_adapter)
7822 return ERR_PTR(-ENOMEM);
7823
7824 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7825 adapter->num_rx_pools++;
7826 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7827 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7828
7829 /* Enable VMDq flag so device will be set in VM mode */
7830 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7831 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7832 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7833
7834 /* Force reinit of ring allocation with VMDQ enabled */
7835 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7836 if (err)
7837 goto fwd_add_err;
7838 fwd_adapter->pool = pool;
7839 fwd_adapter->real_adapter = adapter;
7840 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7841 if (err)
7842 goto fwd_add_err;
7843 netif_tx_start_all_queues(vdev);
7844 return fwd_adapter;
7845fwd_add_err:
7846 /* unwind counter and free adapter struct */
7847 netdev_info(pdev,
7848 "%s: dfwd hardware acceleration failed\n", vdev->name);
7849 clear_bit(pool, &adapter->fwd_bitmask);
7850 adapter->num_rx_pools--;
7851 kfree(fwd_adapter);
7852 return ERR_PTR(err);
7853}
7854
7855static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7856{
7857 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7858 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7859 unsigned int limit;
2a47fa45
JF		 7860
7861 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7862 adapter->num_rx_pools--;
7863
51f3773b
JF		 7864 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7865 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7866 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7867 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7868 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7869 fwd_adapter->pool, adapter->num_rx_pools,
7870 fwd_adapter->rx_base_queue,
7871 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7872 adapter->fwd_bitmask);
7873 kfree(fwd_adapter);
7874}
7875
0edc3527 7876static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7877 .ndo_open = ixgbe_open,
0edc3527 7878 .ndo_stop = ixgbe_close,
00829823 7879 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7880 .ndo_select_queue = ixgbe_select_queue,
581330ba 7881 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7882 .ndo_validate_addr = eth_validate_addr,
7883 .ndo_set_mac_address = ixgbe_set_mac,
7884 .ndo_change_mtu = ixgbe_change_mtu,
7885 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7886 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7887 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7888 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7889 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7890 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 7891 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 7892 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7893 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7894 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7895#ifdef CONFIG_IXGBE_DCB
24095aa3 7896 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7897#endif
0edc3527
SH		 7898#ifdef CONFIG_NET_POLL_CONTROLLER
7899 .ndo_poll_controller = ixgbe_netpoll,
7900#endif
e0d1095a 7901#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7902 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7903#endif
332d4a7d
YZ		 7904#ifdef IXGBE_FCOE
7905 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7906 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7907 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7908 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7909 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7910 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7911 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7912#endif /* IXGBE_FCOE */
082757af
DS		 7913 .ndo_set_features = ixgbe_set_features,
7914 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7915 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7916 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7917 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7918 .ndo_dfwd_add_station = ixgbe_fwd_add,
7919 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7920};
7921
e027d1ae
JK		 7922/**
7923 * ixgbe_enumerate_functions - Get the number of ports this device has
7924 * @adapter: adapter structure
7925 *
7926 * This function enumerates the phsyical functions co-located on a single slot,
7927 * in order to determine how many ports a device has. This is most useful in
7928 * determining the required GT/s of PCIe bandwidth necessary for optimal
7929 * performance.
7930 **/
7931static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7932{
caafb95d 7933 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 7934 int physfns = 0;
7935
f1f96579
JK		 7936 /* Some cards can not use the generic count PCIe functions method,
7937 * because they are behind a parent switch, so we hardcode these with
7938 * the correct number of functions.
e027d1ae 7939 */
8818970d 7940 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 7941 physfns = 4;
8818970d
JK		 7942
7943 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
7944 /* don't count virtual functions */
caafb95d
JK		 7945 if (entry->is_virtfn)
7946 continue;
7947
7948 /* When the devices on the bus don't all match our device ID,
7949 * we can't reliably determine the correct number of
7950 * functions. This can occur if a function has been direct
7951 * attached to a virtual machine using VT-d, for example. In
7952 * this case, simply return -1 to indicate this.
7953 */
7954 if ((entry->vendor != pdev->vendor) ||
7955 (entry->device != pdev->device))
7956 return -1;
7957
7958 physfns++;
e027d1ae
JK		 7959 }
7960
7961 return physfns;
7962}
7963
8e2813f5
JK		 7964/**
7965 * ixgbe_wol_supported - Check whether device supports WoL
7966 * @hw: hw specific details
7967 * @device_id: the device ID
7968 * @subdev_id: the subsystem device ID
7969 *
7970 * This function is used by probe and ethtool to determine
7971 * which devices have WoL support
7972 *
7973 **/
7974int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7975 u16 subdevice_id)
7976{
7977 struct ixgbe_hw *hw = &adapter->hw;
7978 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7979 int is_wol_supported = 0;
7980
7981 switch (device_id) {
7982 case IXGBE_DEV_ID_82599_SFP:
7983 /* Only these subdevices could supports WOL */
7984 switch (subdevice_id) {
87557440 7985 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7986 case IXGBE_SUBDEV_ID_82599_560FLR:
7987 /* only support first port */
7988 if (hw->bus.func != 0)
7989 break;
5700ff26 7990 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7991 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7992 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7993 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7994 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7995 is_wol_supported = 1;
7996 break;
7997 }
7998 break;
5daebbb0
DS		 7999 case IXGBE_DEV_ID_82599EN_SFP:
8000 /* Only this subdevice supports WOL */
8001 switch (subdevice_id) {
8002 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8003 is_wol_supported = 1;
8004 break;
8005 }
8006 break;
8e2813f5
JK		 8007 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8008 /* All except this subdevice support WOL */
8009 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8010 is_wol_supported = 1;
8011 break;
8012 case IXGBE_DEV_ID_82599_KX4:
8013 is_wol_supported = 1;
8014 break;
8015 case IXGBE_DEV_ID_X540T:
df376f0d 8016 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 8017 /* check eeprom to see if enabled wol */
8018 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8019 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8020 (hw->bus.func == 0))) {
8021 is_wol_supported = 1;
8022 }
8023 break;
8024 }
8025
8026 return is_wol_supported;
8027}
8028
9a799d71
AK		 8029/**
8030 * ixgbe_probe - Device Initialization Routine
8031 * @pdev: PCI device information struct
8032 * @ent: entry in ixgbe_pci_tbl
8033 *
8034 * Returns 0 on success, negative on failure
8035 *
8036 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8037 * The OS initialization, configuring of the adapter private structure,
8038 * and a hardware reset occur.
8039 **/
1dd06ae8 8040static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8041{
8042 struct net_device *netdev;
8043 struct ixgbe_adapter *adapter = NULL;
8044 struct ixgbe_hw *hw;
8045 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8046 int i, err, pci_using_dac, expected_gts;
d3cb9869 8047 unsigned int indices = MAX_TX_QUEUES;
289700db 8048 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8049 bool disable_dev = false;
eacd73f7
YZ		 8050#ifdef IXGBE_FCOE
8051 u16 device_caps;
8052#endif
289700db 8053 u32 eec;
9a799d71 8054
bded64a7
AG		 8055 /* Catch broken hardware that put the wrong VF device ID in
8056 * the PCIe SR-IOV capability.
8057 */
8058 if (pdev->is_virtfn) {
8059 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8060 pci_name(pdev), pdev->vendor, pdev->device);
8061 return -EINVAL;
8062 }
8063
9ce77666 8064 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8065 if (err)
8066 return err;
8067
f5f2eda8 8068 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8069 pci_using_dac = 1;
8070 } else {
f5f2eda8 8071 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8072 if (err) {
f5f2eda8
RK		 8073 dev_err(&pdev->dev,
8074 "No usable DMA configuration, aborting\n");
8075 goto err_dma;
9a799d71
AK		 8076 }
8077 pci_using_dac = 0;
8078 }
8079
9ce77666 8080 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8081 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8082 if (err) {
b8bc0421
DC		 8083 dev_err(&pdev->dev,
8084 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8085 goto err_pci_reg;
8086 }
8087
19d5afd4 8088 pci_enable_pcie_error_reporting(pdev);
6fabd715 8089
9a799d71 8090 pci_set_master(pdev);
fb3b27bc 8091 pci_save_state(pdev);
9a799d71 8092
d3cb9869 8093 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8094#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8095 /* 8 TC w/ 4 queues per TC */
8096 indices = 4 * MAX_TRAFFIC_CLASS;
8097#else
8098 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8099#endif
d3cb9869 8100 }
e901acd6 8101
c85a2618 8102 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8103 if (!netdev) {
8104 err = -ENOMEM;
8105 goto err_alloc_etherdev;
8106 }
8107
9a799d71
AK		 8108 SET_NETDEV_DEV(netdev, &pdev->dev);
8109
9a799d71 8110 adapter = netdev_priv(netdev);
c60fbb00 8111 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 8112
8113 adapter->netdev = netdev;
8114 adapter->pdev = pdev;
8115 hw = &adapter->hw;
8116 hw->back = adapter;
b3f4d599 8117 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8118
05857980 8119 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8120 pci_resource_len(pdev, 0));
2a1a091c 8121 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8122 if (!hw->hw_addr) {
8123 err = -EIO;
8124 goto err_ioremap;
8125 }
8126
0edc3527 8127 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8128 ixgbe_set_ethtool_ops(netdev);
9a799d71 8129 netdev->watchdog_timeo = 5 * HZ;
339de30f 8130 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8131
9a799d71
AK		 8132 /* Setup hw api */
8133 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8134 hw->mac.type = ii->mac;
9a799d71 8135
c44ade9e
JB		 8136 /* EEPROM */
8137 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8138 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8139 if (ixgbe_removed(hw->hw_addr)) {
8140 err = -EIO;
8141 goto err_ioremap;
8142 }
c44ade9e
JB		 8143 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8144 if (!(eec & (1 << 8)))
8145 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8146
8147 /* PHY */
8148 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8149 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8150 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8151 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8152 hw->phy.mdio.mmds = 0;
8153 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8154 hw->phy.mdio.dev = netdev;
8155 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8156 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8157
8ca783ab 8158 ii->get_invariants(hw);
9a799d71
AK		 8159
8160 /* setup the private structure */
8161 err = ixgbe_sw_init(adapter);
8162 if (err)
8163 goto err_sw_init;
8164
e86bff0e 8165 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8166 switch (adapter->hw.mac.type) {
8167 case ixgbe_mac_82599EB:
8168 case ixgbe_mac_X540:
9a75a1ac
DS		 8169 case ixgbe_mac_X550:
8170 case ixgbe_mac_X550EM_x:
e86bff0e 8171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8172 break;
8173 default:
8174 break;
8175 }
e86bff0e 8176
bf069c97
DS		 8177 /*
8178 * If there is a fan on this device and it has failed log the
8179 * failure.
8180 */
8181 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8182 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8183 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8184 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8185 }
8186
8ef78adc
PWJ		 8187 if (allow_unsupported_sfp)
8188 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8189
c44ade9e 8190 /* reset_hw fills in the perm_addr as well */
119fc60a 8191 hw->phy.reset_if_overtemp = true;
c44ade9e 8192 err = hw->mac.ops.reset_hw(hw);
119fc60a 8193 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8194 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8195 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8196 err = 0;
8197 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8198 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8199 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8200 goto err_sw_init;
8201 } else if (err) {
849c4542 8202 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8203 goto err_sw_init;
8204 }
8205
99d74487 8206#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8207 /* SR-IOV not supported on the 82598 */
8208 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8209 goto skip_sriov;
8210 /* Mailbox */
8211 ixgbe_init_mbx_params_pf(hw);
8212 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8213 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8214 ixgbe_enable_sriov(adapter);
60a1a680 8215skip_sriov:
1cdd1ec8 8216
99d74487 8217#endif
396e799c 8218 netdev->features = NETIF_F_SG |
e8e9f696 8219 NETIF_F_IP_CSUM |
082757af 8220 NETIF_F_IPV6_CSUM |
f646968f
PM		 8221 NETIF_F_HW_VLAN_CTAG_TX |
8222 NETIF_F_HW_VLAN_CTAG_RX |
8223 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8224 NETIF_F_TSO |
8225 NETIF_F_TSO6 |
082757af 8226 NETIF_F_RXHASH |
8bf1264d 8227 NETIF_F_RXCSUM;
9a799d71 8228
8bf1264d 8229 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8230
58be7666
DS		 8231 switch (adapter->hw.mac.type) {
8232 case ixgbe_mac_82599EB:
8233 case ixgbe_mac_X540:
9a75a1ac
DS		 8234 case ixgbe_mac_X550:
8235 case ixgbe_mac_X550EM_x:
45a5ead0 8236 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8237 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8238 NETIF_F_NTUPLE;
58be7666
DS		 8239 break;
8240 default:
8241 break;
8242 }
45a5ead0 8243
3f2d1c0f
BG		 8244 netdev->hw_features |= NETIF_F_RXALL;
8245
ad31c402
JK		 8246 netdev->vlan_features |= NETIF_F_TSO;
8247 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8248 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8249 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8250 netdev->vlan_features |= NETIF_F_SG;
8251
01789349 8252 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8253 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8254
7a6b6f51 8255#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8256 netdev->dcbnl_ops = &dcbnl_ops;
8257#endif
8258
eacd73f7 8259#ifdef IXGBE_FCOE
0d551589 8260 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8261 unsigned int fcoe_l;
8262
eacd73f7
YZ		 8263 if (hw->mac.ops.get_device_caps) {
8264 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8265 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8266 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8267 }
7c8ae65a 8268
d3cb9869
AD		 8269
8270 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8271 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8272
a58915c7
AD		 8273 netdev->features |= NETIF_F_FSO |
8274 NETIF_F_FCOE_CRC;
8275
7c8ae65a
AD		 8276 netdev->vlan_features |= NETIF_F_FSO |
8277 NETIF_F_FCOE_CRC |
8278 NETIF_F_FCOE_MTU;
5e09d7f6 8279 }
eacd73f7 8280#endif /* IXGBE_FCOE */
7b872a55 8281 if (pci_using_dac) {
9a799d71 8282 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8283 netdev->vlan_features |= NETIF_F_HIGHDMA;
8284 }
9a799d71 8285
082757af
DS		 8286 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8287 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8288 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8289 netdev->features |= NETIF_F_LRO;
8290
9a799d71 8291 /* make sure the EEPROM is good */
c44ade9e 8292 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8293 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8294 err = -EIO;
35937c05 8295 goto err_sw_init;
9a799d71
AK		 8296 }
8297
8298 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8299
aaeb6cdf 8300 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8301 e_dev_err("invalid MAC address\n");
9a799d71 8302 err = -EIO;
35937c05 8303 goto err_sw_init;
9a799d71
AK		 8304 }
8305
5d7daa35
JK		 8306 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8307
7086400d 8308 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8309 (unsigned long) adapter);
9a799d71 8310
58cf663f
MR		 8311 if (ixgbe_removed(hw->hw_addr)) {
8312 err = -EIO;
8313 goto err_sw_init;
8314 }
7086400d 8315 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8316 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8317 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8318
021230d4
AV		 8319 err = ixgbe_init_interrupt_scheme(adapter);
8320 if (err)
8321 goto err_sw_init;
9a799d71 8322
8e2813f5 8323 /* WOL not supported for all devices */
c23f5b6b 8324 adapter->wol = 0;
8e2813f5 8325 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8326 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8327 pdev->subsystem_device);
6b92b0ba 8328 if (hw->wol_enabled)
9417c464 8329 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8330
e8e26350
PW		 8331 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8332
15e5209f
ET		 8333 /* save off EEPROM version number */
8334 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8335 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8336
04f165ef
PW		 8337 /* pick up the PCI bus settings for reporting later */
8338 hw->mac.ops.get_bus_info(hw);
e027d1ae 8339 if (ixgbe_pcie_from_parent(hw))
b8e82001 8340 ixgbe_get_parent_bus_info(adapter);
04f165ef 8341
e027d1ae
JK		 8342 /* calculate the expected PCIe bandwidth required for optimal
8343 * performance. Note that some older parts will never have enough
8344 * bandwidth due to being older generation PCIe parts. We clamp these
8345 * parts to ensure no warning is displayed if it can't be fixed.
8346 */
8347 switch (hw->mac.type) {
8348 case ixgbe_mac_82598EB:
8349 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8350 break;
8351 default:
8352 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8353 break;
0c254d86 8354 }
caafb95d
JK		 8355
8356 /* don't check link if we failed to enumerate functions */
8357 if (expected_gts > 0)
8358 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8359
339de30f 8360 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8361 if (err)
339de30f 8362 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8363 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8364 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8365 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8366 part_str);
6a2aae5a
JK		 8367 else
8368 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8369 hw->mac.type, hw->phy.type, part_str);
8370
8371 e_dev_info("%pM\n", netdev->dev_addr);
8372
9a799d71 8373 /* reset the hardware with the new settings */
794caeb2 8374 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8375 if (err == IXGBE_ERR_EEPROM_VERSION) {
8376 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8377 e_dev_warn("This device is a pre-production adapter/LOM. "
8378 "Please be aware there may be issues associated "
8379 "with your hardware. If you are experiencing "
8380 "problems please contact your Intel or hardware "
8381 "representative who provided you with this "
8382 "hardware.\n");
794caeb2 8383 }
9a799d71
AK		 8384 strcpy(netdev->name, "eth%d");
8385 err = register_netdev(netdev);
8386 if (err)
8387 goto err_register;
8388
ec74a471
ET		 8389 /* power down the optics for 82599 SFP+ fiber */
8390 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8391 hw->mac.ops.disable_tx_laser(hw);
8392
54386467
JB		 8393 /* carrier off reporting is important to ethtool even BEFORE open */
8394 netif_carrier_off(netdev);
8395
5dd2d332 8396#ifdef CONFIG_IXGBE_DCA
652f093f 8397 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8398 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8399 ixgbe_setup_dca(adapter);
8400 }
8401#endif
1cdd1ec8 8402 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8403 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8404 for (i = 0; i < adapter->num_vfs; i++)
8405 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8406 }
8407
2466dd9c
JK		 8408 /* firmware requires driver version to be 0xFFFFFFFF
8409 * since os does not support feature
8410 */
9612de92 8411 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8412 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8413 0xFF);
9612de92 8414
0365e6e4
PW		 8415 /* add san mac addr to netdev */
8416 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8417
ea81875a 8418 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8419
1210982b 8420#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8421 if (ixgbe_sysfs_init(adapter))
8422 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8423#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8424
00949167 8425 ixgbe_dbg_adapter_init(adapter);
00949167 8426
d1a35ee2
ET		 8427 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8428 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8429 hw->mac.ops.setup_link(hw,
8430 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8431 true);
8432
9a799d71
AK		 8433 return 0;
8434
8435err_register:
5eba3699 8436 ixgbe_release_hw_control(adapter);
7a921c93 8437 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8438err_sw_init:
99d74487 8439 ixgbe_disable_sriov(adapter);
7086400d 8440 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8441 iounmap(adapter->io_addr);
5d7daa35 8442 kfree(adapter->mac_table);
9a799d71 8443err_ioremap:
b5b2ffc0 8444 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8445 free_netdev(netdev);
8446err_alloc_etherdev:
e8e9f696
JP		 8447 pci_release_selected_regions(pdev,
8448 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8449err_pci_reg:
8450err_dma:
b5b2ffc0 8451 if (!adapter || disable_dev)
41c62843 8452 pci_disable_device(pdev);
9a799d71
AK		 8453 return err;
8454}
8455
8456/**
8457 * ixgbe_remove - Device Removal Routine
8458 * @pdev: PCI device information struct
8459 *
8460 * ixgbe_remove is called by the PCI subsystem to alert the driver
8461 * that it should release a PCI device. The could be caused by a
8462 * Hot-Plug event, or because the driver is going to be removed from
8463 * memory.
8464 **/
9f9a12f8 8465static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8466{
c60fbb00
AD		 8467 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8468 struct net_device *netdev = adapter->netdev;
b5b2ffc0 8469 bool disable_dev;
9a799d71 8470
00949167 8471 ixgbe_dbg_adapter_exit(adapter);
00949167 8472
09f40aed 8473 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8474 cancel_work_sync(&adapter->service_task);
9a799d71 8475
3a6a4eda 8476
5dd2d332 8477#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8478 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8479 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8480 dca_remove_requester(&pdev->dev);
8481 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8482 }
8483
8484#endif
1210982b 8485#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8486 ixgbe_sysfs_exit(adapter);
1210982b 8487#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8488
0365e6e4
PW		 8489 /* remove the added san mac */
8490 ixgbe_del_sanmac_netdev(netdev);
8491
c4900be0
DS		 8492 if (netdev->reg_state == NETREG_REGISTERED)
8493 unregister_netdev(netdev);
9a799d71 8494
da36b647
GR		 8495#ifdef CONFIG_PCI_IOV
8496 /*
8497 * Only disable SR-IOV on unload if the user specified the now
8498 * deprecated max_vfs module parameter.
8499 */
8500 if (max_vfs)
8501 ixgbe_disable_sriov(adapter);
8502#endif
7a921c93 8503 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8504
021230d4 8505 ixgbe_release_hw_control(adapter);
9a799d71 8506
2b1588c3
AD		 8507#ifdef CONFIG_DCB
8508 kfree(adapter->ixgbe_ieee_pfc);
8509 kfree(adapter->ixgbe_ieee_ets);
8510
8511#endif
2a1a091c 8512 iounmap(adapter->io_addr);
9ce77666 8513 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8514 IORESOURCE_MEM));
9a799d71 8515
849c4542 8516 e_dev_info("complete\n");
021230d4 8517
5d7daa35 8518 kfree(adapter->mac_table);
b5b2ffc0 8519 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8520 free_netdev(netdev);
8521
19d5afd4 8522 pci_disable_pcie_error_reporting(pdev);
6fabd715 8523
b5b2ffc0 8524 if (disable_dev)
41c62843 8525 pci_disable_device(pdev);
9a799d71
AK		 8526}
8527
8528/**
8529 * ixgbe_io_error_detected - called when PCI error is detected
8530 * @pdev: Pointer to PCI device
8531 * @state: The current pci connection state
8532 *
8533 * This function is called after a PCI bus error affecting
8534 * this device has been detected.
8535 */
8536static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8537 pci_channel_state_t state)
9a799d71 8538{
c60fbb00
AD		 8539 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8540 struct net_device *netdev = adapter->netdev;
9a799d71 8541
83c61fa9 8542#ifdef CONFIG_PCI_IOV
14438464 8543 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8544 struct pci_dev *bdev, *vfdev;
8545 u32 dw0, dw1, dw2, dw3;
8546 int vf, pos;
8547 u16 req_id, pf_func;
8548
8549 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8550 adapter->num_vfs == 0)
8551 goto skip_bad_vf_detection;
8552
8553 bdev = pdev->bus->self;
62f87c0e 8554 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8555 bdev = bdev->bus->self;
8556
8557 if (!bdev)
8558 goto skip_bad_vf_detection;
8559
8560 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8561 if (!pos)
8562 goto skip_bad_vf_detection;
8563
14438464
MR		 8564 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8565 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8566 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8567 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8568 if (ixgbe_removed(hw->hw_addr))
8569 goto skip_bad_vf_detection;
83c61fa9
GR		 8570
8571 req_id = dw1 >> 16;
8572 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8573 if (!(req_id & 0x0080))
8574 goto skip_bad_vf_detection;
8575
8576 pf_func = req_id & 0x01;
8577 if ((pf_func & 1) == (pdev->devfn & 1)) {
8578 unsigned int device_id;
8579
8580 vf = (req_id & 0x7F) >> 1;
8581 e_dev_err("VF %d has caused a PCIe error\n", vf);
8582 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8583 "%8.8x\tdw3: %8.8x\n",
8584 dw0, dw1, dw2, dw3);
8585 switch (adapter->hw.mac.type) {
8586 case ixgbe_mac_82599EB:
8587 device_id = IXGBE_82599_VF_DEVICE_ID;
8588 break;
8589 case ixgbe_mac_X540:
8590 device_id = IXGBE_X540_VF_DEVICE_ID;
8591 break;
9a75a1ac
DS		 8592 case ixgbe_mac_X550:
8593 device_id = IXGBE_DEV_ID_X550_VF;
8594 break;
8595 case ixgbe_mac_X550EM_x:
8596 device_id = IXGBE_DEV_ID_X550EM_X_VF;
8597 break;
83c61fa9
GR		 8598 default:
8599 device_id = 0;
8600 break;
8601 }
8602
8603 /* Find the pci device of the offending VF */
36e90319 8604 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8605 while (vfdev) {
8606 if (vfdev->devfn == (req_id & 0xFF))
8607 break;
36e90319 8608 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8609 device_id, vfdev);
8610 }
8611 /*
8612 * There's a slim chance the VF could have been hot plugged,
8613 * so if it is no longer present we don't need to issue the
8614 * VFLR. Just clean up the AER in that case.
8615 */
8616 if (vfdev) {
8617 e_dev_err("Issuing VFLR to VF %d\n", vf);
8618 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8619 /* Free device reference count */
8620 pci_dev_put(vfdev);
83c61fa9
GR		 8621 }
8622
8623 pci_cleanup_aer_uncorrect_error_status(pdev);
8624 }
8625
8626 /*
8627 * Even though the error may have occurred on the other port
8628 * we still need to increment the vf error reference count for
8629 * both ports because the I/O resume function will be called
8630 * for both of them.
8631 */
8632 adapter->vferr_refcount++;
8633
8634 return PCI_ERS_RESULT_RECOVERED;
8635
8636skip_bad_vf_detection:
8637#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8638 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8639 return PCI_ERS_RESULT_DISCONNECT;
8640
41c62843 8641 rtnl_lock();
9a799d71
AK		 8642 netif_device_detach(netdev);
8643
41c62843
MR		 8644 if (state == pci_channel_io_perm_failure) {
8645 rtnl_unlock();
3044b8d1 8646 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8647 }
3044b8d1 8648
9a799d71
AK		 8649 if (netif_running(netdev))
8650 ixgbe_down(adapter);
41c62843
MR		 8651
8652 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8653 pci_disable_device(pdev);
8654 rtnl_unlock();
9a799d71 8655
b4617240 8656 /* Request a slot reset. */
9a799d71
AK		 8657 return PCI_ERS_RESULT_NEED_RESET;
8658}
8659
8660/**
8661 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8662 * @pdev: Pointer to PCI device
8663 *
8664 * Restart the card from scratch, as if from a cold-boot.
8665 */
8666static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8667{
c60fbb00 8668 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8669 pci_ers_result_t result;
8670 int err;
9a799d71 8671
9ce77666 8672 if (pci_enable_device_mem(pdev)) {
396e799c 8673 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8674 result = PCI_ERS_RESULT_DISCONNECT;
8675 } else {
4e857c58 8676 smp_mb__before_atomic();
41c62843 8677 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8678 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8679 pci_set_master(pdev);
8680 pci_restore_state(pdev);
c0e1f68b 8681 pci_save_state(pdev);
9a799d71 8682
dd4d8ca6 8683 pci_wake_from_d3(pdev, false);
9a799d71 8684
6fabd715 8685 ixgbe_reset(adapter);
88512539 8686 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8687 result = PCI_ERS_RESULT_RECOVERED;
8688 }
8689
8690 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8691 if (err) {
849c4542
ET		 8692 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8693 "failed 0x%0x\n", err);
6fabd715
PWJ		 8694 /* non-fatal, continue */
8695 }
9a799d71 8696
6fabd715 8697 return result;
9a799d71
AK		 8698}
8699
8700/**
8701 * ixgbe_io_resume - called when traffic can start flowing again.
8702 * @pdev: Pointer to PCI device
8703 *
8704 * This callback is called when the error recovery driver tells us that
8705 * its OK to resume normal operation.
8706 */
8707static void ixgbe_io_resume(struct pci_dev *pdev)
8708{
c60fbb00
AD		 8709 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8710 struct net_device *netdev = adapter->netdev;
9a799d71 8711
83c61fa9
GR		 8712#ifdef CONFIG_PCI_IOV
8713 if (adapter->vferr_refcount) {
8714 e_info(drv, "Resuming after VF err\n");
8715 adapter->vferr_refcount--;
8716 return;
8717 }
8718
8719#endif
c7ccde0f
AD		 8720 if (netif_running(netdev))
8721 ixgbe_up(adapter);
9a799d71
AK		 8722
8723 netif_device_attach(netdev);
9a799d71
AK		 8724}
8725
3646f0e5 8726static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8727 .error_detected = ixgbe_io_error_detected,
8728 .slot_reset = ixgbe_io_slot_reset,
8729 .resume = ixgbe_io_resume,
8730};
8731
8732static struct pci_driver ixgbe_driver = {
8733 .name = ixgbe_driver_name,
8734 .id_table = ixgbe_pci_tbl,
8735 .probe = ixgbe_probe,
9f9a12f8 8736 .remove = ixgbe_remove,
9a799d71
AK		 8737#ifdef CONFIG_PM
8738 .suspend = ixgbe_suspend,
8739 .resume = ixgbe_resume,
8740#endif
8741 .shutdown = ixgbe_shutdown,
da36b647 8742 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8743 .err_handler = &ixgbe_err_handler
8744};
8745
8746/**
8747 * ixgbe_init_module - Driver Registration Routine
8748 *
8749 * ixgbe_init_module is the first routine called when the driver is
8750 * loaded. All it does is register with the PCI subsystem.
8751 **/
8752static int __init ixgbe_init_module(void)
8753{
8754 int ret;
c7689578 8755 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8756 pr_info("%s\n", ixgbe_copyright);
9a799d71 8757
00949167 8758 ixgbe_dbg_init();
00949167 8759
f01fc1a8
JK		 8760 ret = pci_register_driver(&ixgbe_driver);
8761 if (ret) {
f01fc1a8 8762 ixgbe_dbg_exit();
f01fc1a8
JK		 8763 return ret;
8764 }
8765
5dd2d332 8766#ifdef CONFIG_IXGBE_DCA
bd0362dd 8767 dca_register_notify(&dca_notifier);
bd0362dd 8768#endif
5dd2d332 8769
f01fc1a8 8770 return 0;
9a799d71 8771}
b4617240 8772
9a799d71
AK		 8773module_init(ixgbe_init_module);
8774
8775/**
8776 * ixgbe_exit_module - Driver Exit Cleanup Routine
8777 *
8778 * ixgbe_exit_module is called just before the driver is removed
8779 * from memory.
8780 **/
8781static void __exit ixgbe_exit_module(void)
8782{
5dd2d332 8783#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8784 dca_unregister_notify(&dca_notifier);
8785#endif
9a799d71 8786 pci_unregister_driver(&ixgbe_driver);
00949167 8787
00949167 8788 ixgbe_dbg_exit();
00949167 8789
1a51502b 8790 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8791}
bd0362dd 8792
5dd2d332 8793#ifdef CONFIG_IXGBE_DCA
bd0362dd 8794static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8795 void *p)
bd0362dd
JC		 8796{
8797 int ret_val;
8798
8799 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8800 __ixgbe_notify_dca);
bd0362dd
JC		 8801
8802 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8803}
b453368d 8804
5dd2d332 8805#endif /* CONFIG_IXGBE_DCA */
849c4542 8806
9a799d71
AK		 8807module_exit(ixgbe_exit_module);
8808
8809/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)