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e1000e: make function tables const
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 58#define MAJ 3
a38a104d 59#define MIN 4
c89c7112 60#define BUILD 8
75e3d3c6 61#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 62 __stringify(BUILD) "-k"
9c8eb720 63const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 64static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 66
67static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 68 [board_82598] = &ixgbe_82598_info,
e8e26350 69 [board_82599] = &ixgbe_82599_info,
fe15e8e1 70 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 71};
72
73/* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
a3aa1884 81static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
9a799d71
AK		 108 /* required last entry */
109 {0, }
110};
111MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
112
5dd2d332 113#ifdef CONFIG_IXGBE_DCA
bd0362dd 114static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 115 void *p);
bd0362dd
JC		 116static struct notifier_block dca_notifier = {
117 .notifier_call = ixgbe_notify_dca,
118 .next = NULL,
119 .priority = 0
120};
121#endif
122
1cdd1ec8
GR		 123#ifdef CONFIG_PCI_IOV
124static unsigned int max_vfs;
125module_param(max_vfs, uint, 0);
e8e9f696
JP		 126MODULE_PARM_DESC(max_vfs,
127 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 128#endif /* CONFIG_PCI_IOV */
129
9a799d71
AK		 130MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
131MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
132MODULE_LICENSE("GPL");
133MODULE_VERSION(DRV_VERSION);
134
135#define DEFAULT_DEBUG_LEVEL_SHIFT 3
136
7086400d
AD		 137static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
138{
139 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
140 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
141 schedule_work(&adapter->service_task);
142}
143
144static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
145{
146 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
147
148 /* flush memory to make sure state is correct before next watchog */
149 smp_mb__before_clear_bit();
150 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
151}
152
dcd79aeb
TI		 153struct ixgbe_reg_info {
154 u32 ofs;
155 char *name;
156};
157
158static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
159
160 /* General Registers */
161 {IXGBE_CTRL, "CTRL"},
162 {IXGBE_STATUS, "STATUS"},
163 {IXGBE_CTRL_EXT, "CTRL_EXT"},
164
165 /* Interrupt Registers */
166 {IXGBE_EICR, "EICR"},
167
168 /* RX Registers */
169 {IXGBE_SRRCTL(0), "SRRCTL"},
170 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
171 {IXGBE_RDLEN(0), "RDLEN"},
172 {IXGBE_RDH(0), "RDH"},
173 {IXGBE_RDT(0), "RDT"},
174 {IXGBE_RXDCTL(0), "RXDCTL"},
175 {IXGBE_RDBAL(0), "RDBAL"},
176 {IXGBE_RDBAH(0), "RDBAH"},
177
178 /* TX Registers */
179 {IXGBE_TDBAL(0), "TDBAL"},
180 {IXGBE_TDBAH(0), "TDBAH"},
181 {IXGBE_TDLEN(0), "TDLEN"},
182 {IXGBE_TDH(0), "TDH"},
183 {IXGBE_TDT(0), "TDT"},
184 {IXGBE_TXDCTL(0), "TXDCTL"},
185
186 /* List Terminator */
187 {}
188};
189
190
191/*
192 * ixgbe_regdump - register printout routine
193 */
194static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
195{
196 int i = 0, j = 0;
197 char rname[16];
198 u32 regs[64];
199
200 switch (reginfo->ofs) {
201 case IXGBE_SRRCTL(0):
202 for (i = 0; i < 64; i++)
203 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
204 break;
205 case IXGBE_DCA_RXCTRL(0):
206 for (i = 0; i < 64; i++)
207 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
208 break;
209 case IXGBE_RDLEN(0):
210 for (i = 0; i < 64; i++)
211 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
212 break;
213 case IXGBE_RDH(0):
214 for (i = 0; i < 64; i++)
215 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
216 break;
217 case IXGBE_RDT(0):
218 for (i = 0; i < 64; i++)
219 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
220 break;
221 case IXGBE_RXDCTL(0):
222 for (i = 0; i < 64; i++)
223 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
224 break;
225 case IXGBE_RDBAL(0):
226 for (i = 0; i < 64; i++)
227 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
228 break;
229 case IXGBE_RDBAH(0):
230 for (i = 0; i < 64; i++)
231 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
232 break;
233 case IXGBE_TDBAL(0):
234 for (i = 0; i < 64; i++)
235 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
236 break;
237 case IXGBE_TDBAH(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
240 break;
241 case IXGBE_TDLEN(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
244 break;
245 case IXGBE_TDH(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
248 break;
249 case IXGBE_TDT(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
252 break;
253 case IXGBE_TXDCTL(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
256 break;
257 default:
c7689578 258 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 259 IXGBE_READ_REG(hw, reginfo->ofs));
260 return;
261 }
262
263 for (i = 0; i < 8; i++) {
264 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 265 pr_err("%-15s", rname);
dcd79aeb 266 for (j = 0; j < 8; j++)
c7689578
JP		 267 pr_cont(" %08x", regs[i*8+j]);
268 pr_cont("\n");
dcd79aeb
TI		 269 }
270
271}
272
273/*
274 * ixgbe_dump - Print registers, tx-rings and rx-rings
275 */
276static void ixgbe_dump(struct ixgbe_adapter *adapter)
277{
278 struct net_device *netdev = adapter->netdev;
279 struct ixgbe_hw *hw = &adapter->hw;
280 struct ixgbe_reg_info *reginfo;
281 int n = 0;
282 struct ixgbe_ring *tx_ring;
283 struct ixgbe_tx_buffer *tx_buffer_info;
284 union ixgbe_adv_tx_desc *tx_desc;
285 struct my_u0 { u64 a; u64 b; } *u0;
286 struct ixgbe_ring *rx_ring;
287 union ixgbe_adv_rx_desc *rx_desc;
288 struct ixgbe_rx_buffer *rx_buffer_info;
289 u32 staterr;
290 int i = 0;
291
292 if (!netif_msg_hw(adapter))
293 return;
294
295 /* Print netdevice Info */
296 if (netdev) {
297 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 298 pr_info("Device Name state "
dcd79aeb 299 "trans_start last_rx\n");
c7689578
JP		 300 pr_info("%-15s %016lX %016lX %016lX\n",
301 netdev->name,
302 netdev->state,
303 netdev->trans_start,
304 netdev->last_rx);
dcd79aeb
TI		 305 }
306
307 /* Print Registers */
308 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 309 pr_info(" Register Name Value\n");
dcd79aeb
TI		 310 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
311 reginfo->name; reginfo++) {
312 ixgbe_regdump(hw, reginfo);
313 }
314
315 /* Print TX Ring Summary */
316 if (!netdev || !netif_running(netdev))
317 goto exit;
318
319 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 320 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 321 for (n = 0; n < adapter->num_tx_queues; n++) {
322 tx_ring = adapter->tx_ring[n];
323 tx_buffer_info =
324 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 325 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 326 n, tx_ring->next_to_use, tx_ring->next_to_clean,
327 (u64)tx_buffer_info->dma,
328 tx_buffer_info->length,
329 tx_buffer_info->next_to_watch,
330 (u64)tx_buffer_info->time_stamp);
331 }
332
333 /* Print TX Rings */
334 if (!netif_msg_tx_done(adapter))
335 goto rx_ring_summary;
336
337 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
338
339 /* Transmit Descriptor Formats
340 *
341 * Advanced Transmit Descriptor
342 * +--------------------------------------------------------------+
343 * 0 | Buffer Address [63:0] |
344 * +--------------------------------------------------------------+
345 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
346 * +--------------------------------------------------------------+
347 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
348 */
349
350 for (n = 0; n < adapter->num_tx_queues; n++) {
351 tx_ring = adapter->tx_ring[n];
c7689578
JP		 352 pr_info("------------------------------------\n");
353 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
354 pr_info("------------------------------------\n");
355 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 356 "[PlPOIdStDDt Ln] [bi->dma ] "
357 "leng ntw timestamp bi->skb\n");
358
359 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 360 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 361 tx_buffer_info = &tx_ring->tx_buffer_info[i];
362 u0 = (struct my_u0 *)tx_desc;
c7689578 363 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 364 " %04X %p %016llX %p", i,
dcd79aeb
TI		 365 le64_to_cpu(u0->a),
366 le64_to_cpu(u0->b),
367 (u64)tx_buffer_info->dma,
368 tx_buffer_info->length,
369 tx_buffer_info->next_to_watch,
370 (u64)tx_buffer_info->time_stamp,
371 tx_buffer_info->skb);
372 if (i == tx_ring->next_to_use &&
373 i == tx_ring->next_to_clean)
c7689578 374 pr_cont(" NTC/U\n");
dcd79aeb 375 else if (i == tx_ring->next_to_use)
c7689578 376 pr_cont(" NTU\n");
dcd79aeb 377 else if (i == tx_ring->next_to_clean)
c7689578 378 pr_cont(" NTC\n");
dcd79aeb 379 else
c7689578 380 pr_cont("\n");
dcd79aeb
TI		 381
382 if (netif_msg_pktdata(adapter) &&
383 tx_buffer_info->dma != 0)
384 print_hex_dump(KERN_INFO, "",
385 DUMP_PREFIX_ADDRESS, 16, 1,
386 phys_to_virt(tx_buffer_info->dma),
387 tx_buffer_info->length, true);
388 }
389 }
390
391 /* Print RX Rings Summary */
392rx_ring_summary:
393 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 394 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 395 for (n = 0; n < adapter->num_rx_queues; n++) {
396 rx_ring = adapter->rx_ring[n];
c7689578
JP		 397 pr_info("%5d %5X %5X\n",
398 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 399 }
400
401 /* Print RX Rings */
402 if (!netif_msg_rx_status(adapter))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
406
407 /* Advanced Receive Descriptor (Read) Format
408 * 63 1 0
409 * +-----------------------------------------------------+
410 * 0 | Packet Buffer Address [63:1] |A0/NSE|
411 * +----------------------------------------------+------+
412 * 8 | Header Buffer Address [63:1] | DD |
413 * +-----------------------------------------------------+
414 *
415 *
416 * Advanced Receive Descriptor (Write-Back) Format
417 *
418 * 63 48 47 32 31 30 21 20 16 15 4 3 0
419 * +------------------------------------------------------+
420 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
421 * | Checksum Ident | | | | Type | Type |
422 * +------------------------------------------------------+
423 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
424 * +------------------------------------------------------+
425 * 63 48 47 32 31 20 19 0
426 */
427 for (n = 0; n < adapter->num_rx_queues; n++) {
428 rx_ring = adapter->rx_ring[n];
c7689578
JP		 429 pr_info("------------------------------------\n");
430 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
431 pr_info("------------------------------------\n");
432 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 433 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
434 "<-- Adv Rx Read format\n");
c7689578 435 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 436 "[vl er S cks ln] ---------------- [bi->skb] "
437 "<-- Adv Rx Write-Back format\n");
438
439 for (i = 0; i < rx_ring->count; i++) {
440 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 441 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 442 u0 = (struct my_u0 *)rx_desc;
443 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
444 if (staterr & IXGBE_RXD_STAT_DD) {
445 /* Descriptor Done */
c7689578 446 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 447 "%016llX ---------------- %p", i,
448 le64_to_cpu(u0->a),
449 le64_to_cpu(u0->b),
450 rx_buffer_info->skb);
451 } else {
c7689578 452 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 453 "%016llX %016llX %p", i,
454 le64_to_cpu(u0->a),
455 le64_to_cpu(u0->b),
456 (u64)rx_buffer_info->dma,
457 rx_buffer_info->skb);
458
459 if (netif_msg_pktdata(adapter)) {
460 print_hex_dump(KERN_INFO, "",
461 DUMP_PREFIX_ADDRESS, 16, 1,
462 phys_to_virt(rx_buffer_info->dma),
463 rx_ring->rx_buf_len, true);
464
465 if (rx_ring->rx_buf_len
919e78a6 466 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 467 print_hex_dump(KERN_INFO, "",
468 DUMP_PREFIX_ADDRESS, 16, 1,
469 phys_to_virt(
470 rx_buffer_info->page_dma +
471 rx_buffer_info->page_offset
472 ),
473 PAGE_SIZE/2, true);
474 }
475 }
476
477 if (i == rx_ring->next_to_use)
c7689578 478 pr_cont(" NTU\n");
dcd79aeb 479 else if (i == rx_ring->next_to_clean)
c7689578 480 pr_cont(" NTC\n");
dcd79aeb 481 else
c7689578 482 pr_cont("\n");
dcd79aeb
TI		 483
484 }
485 }
486
487exit:
488 return;
489}
490
5eba3699
AV		 491static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
492{
493 u32 ctrl_ext;
494
495 /* Let firmware take over control of h/w */
496 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 498 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 499}
500
501static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
502{
503 u32 ctrl_ext;
504
505 /* Let firmware know the driver has taken over */
506 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
507 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 508 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 509}
9a799d71 510
e8e26350
PW		 511/*
512 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
513 * @adapter: pointer to adapter struct
514 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
515 * @queue: queue to map the corresponding interrupt to
516 * @msix_vector: the vector to map to the corresponding queue
517 *
518 */
519static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 520 u8 queue, u8 msix_vector)
9a799d71
AK		 521{
522 u32 ivar, index;
e8e26350
PW		 523 struct ixgbe_hw *hw = &adapter->hw;
524 switch (hw->mac.type) {
525 case ixgbe_mac_82598EB:
526 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
527 if (direction == -1)
528 direction = 0;
529 index = (((direction * 64) + queue) >> 2) & 0x1F;
530 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
531 ivar &= ~(0xFF << (8 * (queue & 0x3)));
532 ivar |= (msix_vector << (8 * (queue & 0x3)));
533 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
534 break;
535 case ixgbe_mac_82599EB:
b93a2226 536 case ixgbe_mac_X540:
e8e26350
PW		 537 if (direction == -1) {
538 /* other causes */
539 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
540 index = ((queue & 1) * 8);
541 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
542 ivar &= ~(0xFF << index);
543 ivar |= (msix_vector << index);
544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
545 break;
546 } else {
547 /* tx or rx causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((16 * (queue & 1)) + (8 * direction));
550 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
554 break;
555 }
556 default:
557 break;
558 }
9a799d71
AK		 559}
560
fe49f04a 561static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 562 u64 qmask)
fe49f04a
AD		 563{
564 u32 mask;
565
bd508178
AD		 566 switch (adapter->hw.mac.type) {
567 case ixgbe_mac_82598EB:
fe49f04a
AD		 568 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 570 break;
571 case ixgbe_mac_82599EB:
b93a2226 572 case ixgbe_mac_X540:
fe49f04a
AD		 573 mask = (qmask & 0xFFFFFFFF);
574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
575 mask = (qmask >> 32);
576 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 577 break;
578 default:
579 break;
fe49f04a
AD		 580 }
581}
582
d3d00239
AD		 583static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
584 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 585{
d3d00239
AD		 586 if (tx_buffer->dma) {
587 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
588 dma_unmap_page(ring->dev,
589 tx_buffer->dma,
590 tx_buffer->length,
591 DMA_TO_DEVICE);
e5a43549 592 else
d3d00239
AD		 593 dma_unmap_single(ring->dev,
594 tx_buffer->dma,
595 tx_buffer->length,
596 DMA_TO_DEVICE);
e5a43549 597 }
d3d00239
AD		 598 tx_buffer->dma = 0;
599}
600
601void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
602 struct ixgbe_tx_buffer *tx_buffer_info)
603{
604 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
605 if (tx_buffer_info->skb)
9a799d71 606 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 607 tx_buffer_info->skb = NULL;
9a799d71
AK		 608 /* tx_buffer_info must be completely set up in the transmit path */
609}
610
c84d324c
JF		 611static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
612{
613 struct ixgbe_hw *hw = &adapter->hw;
614 struct ixgbe_hw_stats *hwstats = &adapter->stats;
615 u32 data = 0;
616 u32 xoff[8] = {0};
617 int i;
618
619 if ((hw->fc.current_mode == ixgbe_fc_full) ||
620 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
621 switch (hw->mac.type) {
622 case ixgbe_mac_82598EB:
623 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 624 break;
625 default:
c84d324c
JF		 626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
627 }
628 hwstats->lxoffrxc += data;
629
630 /* refill credits (no tx hang) if we received xoff */
631 if (!data)
632 return;
633
634 for (i = 0; i < adapter->num_tx_queues; i++)
635 clear_bit(__IXGBE_HANG_CHECK_ARMED,
636 &adapter->tx_ring[i]->state);
637 return;
638 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
639 return;
640
641 /* update stats for each tc, only valid with PFC enabled */
642 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
643 switch (hw->mac.type) {
644 case ixgbe_mac_82598EB:
645 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 646 break;
c84d324c
JF		 647 default:
648 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 649 }
c84d324c
JF		 650 hwstats->pxoffrxc[i] += xoff[i];
651 }
652
653 /* disarm tx queues that have received xoff frames */
654 for (i = 0; i < adapter->num_tx_queues; i++) {
655 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 656 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 657
658 if (xoff[tc])
659 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 660 }
26f23d82
YZ		 661}
662
c84d324c 663static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 664{
c84d324c
JF		 665 return ring->tx_stats.completed;
666}
667
668static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
669{
670 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 671 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 672
c84d324c
JF		 673 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
674 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
675
676 if (head != tail)
677 return (head < tail) ?
678 tail - head : (tail + ring->count - head);
679
680 return 0;
681}
682
683static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
684{
685 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
686 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
687 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
688 bool ret = false;
689
7d637bcc 690 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 691
692 /*
693 * Check for a hung queue, but be thorough. This verifies
694 * that a transmit has been completed since the previous
695 * check AND there is at least one packet pending. The
696 * ARMED bit is set to indicate a potential hang. The
697 * bit is cleared if a pause frame is received to remove
698 * false hang detection due to PFC or 802.3x frames. By
699 * requiring this to fail twice we avoid races with
700 * pfc clearing the ARMED bit and conditions where we
701 * run the check_tx_hang logic with a transmit completion
702 * pending but without time to complete it yet.
703 */
704 if ((tx_done_old == tx_done) && tx_pending) {
705 /* make sure it is true for two checks in a row */
706 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
707 &tx_ring->state);
708 } else {
709 /* update completed stats and continue */
710 tx_ring->tx_stats.tx_done_old = tx_done;
711 /* reset the countdown */
712 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 713 }
714
c84d324c 715 return ret;
9a799d71
AK		 716}
717
c83c6cbd
AD		 718/**
719 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
720 * @adapter: driver private struct
721 **/
722static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
723{
724
725 /* Do the reset outside of interrupt context */
726 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
727 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
728 ixgbe_service_event_schedule(adapter);
729 }
730}
e01c31a5 731
9a799d71
AK		 732/**
733 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 734 * @q_vector: structure containing interrupt and ring information
e01c31a5 735 * @tx_ring: tx ring to clean
9a799d71 736 **/
fe49f04a 737static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 738 struct ixgbe_ring *tx_ring)
9a799d71 739{
fe49f04a 740 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 741 struct ixgbe_tx_buffer *tx_buffer;
742 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 743 unsigned int total_bytes = 0, total_packets = 0;
59224555 744 unsigned int budget = q_vector->tx.work_limit;
d3d00239 745 u16 i = tx_ring->next_to_clean;
9a799d71 746
d3d00239
AD		 747 tx_buffer = &tx_ring->tx_buffer_info[i];
748 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 749
30065e63 750 for (; budget; budget--) {
d3d00239
AD		 751 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
752
753 /* if next_to_watch is not set then there is no work pending */
754 if (!eop_desc)
755 break;
756
757 /* if DD is not set pending work has not been completed */
758 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
759 break;
8ad494b0 760
d3d00239
AD		 761 /* count the packet as being completed */
762 tx_ring->tx_stats.completed++;
763
764 /* clear next_to_watch to prevent false hangs */
765 tx_buffer->next_to_watch = NULL;
8ad494b0 766
d3d00239
AD		 767 /* prevent any other reads prior to eop_desc being verified */
768 rmb();
769
770 do {
771 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 772 tx_desc->wb.status = 0;
d3d00239
AD		 773 if (likely(tx_desc == eop_desc)) {
774 eop_desc = NULL;
775 dev_kfree_skb_any(tx_buffer->skb);
776 tx_buffer->skb = NULL;
777
778 total_bytes += tx_buffer->bytecount;
779 total_packets += tx_buffer->gso_segs;
780 }
9a799d71 781
d3d00239
AD		 782 tx_buffer++;
783 tx_desc++;
8ad494b0 784 i++;
d3d00239 785 if (unlikely(i == tx_ring->count)) {
8ad494b0 786 i = 0;
e01c31a5 787
d3d00239
AD		 788 tx_buffer = tx_ring->tx_buffer_info;
789 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 790 }
e01c31a5 791
d3d00239 792 } while (eop_desc);
12207e49
PWJ		 793 }
794
9a799d71 795 tx_ring->next_to_clean = i;
d3d00239 796 u64_stats_update_begin(&tx_ring->syncp);
b953799e 797 tx_ring->stats.bytes += total_bytes;
bd198058 798 tx_ring->stats.packets += total_packets;
d3d00239 799 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 800 q_vector->tx.total_bytes += total_bytes;
801 q_vector->tx.total_packets += total_packets;
b953799e 802
c84d324c
JF		 803 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
804 /* schedule immediate reset if we believe we hung */
805 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 806 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 807 e_err(drv, "Detected Tx Unit Hang\n"
808 " Tx Queue <%d>\n"
809 " TDH, TDT <%x>, <%x>\n"
810 " next_to_use <%x>\n"
811 " next_to_clean <%x>\n"
812 "tx_buffer_info[next_to_clean]\n"
813 " time_stamp <%lx>\n"
814 " jiffies <%lx>\n",
815 tx_ring->queue_index,
816 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
817 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 818 tx_ring->next_to_use, i,
819 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 820
821 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
822
823 e_info(probe,
824 "tx hang %d detected on queue %d, resetting adapter\n",
825 adapter->tx_timeout_count + 1, tx_ring->queue_index);
826
b953799e 827 /* schedule immediate reset if we believe we hung */
c83c6cbd 828 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 829
830 /* the adapter is about to reset, no point in enabling stuff */
59224555 831 return true;
b953799e 832 }
9a799d71 833
e092be60 834#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 835 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 836 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 837 /* Make sure that anybody stopping the queue after this
838 * sees the new next_to_clean.
839 */
840 smp_mb();
fc77dc3c 841 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 842 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 843 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 844 ++tx_ring->tx_stats.restart_queue;
30eba97a 845 }
e092be60 846 }
9a799d71 847
59224555 848 return !!budget;
9a799d71
AK		 849}
850
5dd2d332 851#ifdef CONFIG_IXGBE_DCA
bd0362dd 852static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 853 struct ixgbe_ring *rx_ring,
854 int cpu)
bd0362dd 855{
33cf09c9 856 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 857 u32 rxctrl;
33cf09c9
AD		 858 u8 reg_idx = rx_ring->reg_idx;
859
860 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
861 switch (hw->mac.type) {
862 case ixgbe_mac_82598EB:
863 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 864 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 865 break;
866 case ixgbe_mac_82599EB:
b93a2226 867 case ixgbe_mac_X540:
33cf09c9 868 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 869 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 870 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
871 break;
872 default:
873 break;
bd0362dd 874 }
33cf09c9
AD		 875 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
876 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
877 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 878 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 879}
880
881static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 882 struct ixgbe_ring *tx_ring,
883 int cpu)
bd0362dd 884{
33cf09c9 885 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 886 u32 txctrl;
33cf09c9
AD		 887 u8 reg_idx = tx_ring->reg_idx;
888
889 switch (hw->mac.type) {
890 case ixgbe_mac_82598EB:
891 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
892 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 893 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 894 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 895 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
896 break;
897 case ixgbe_mac_82599EB:
b93a2226 898 case ixgbe_mac_X540:
33cf09c9
AD		 899 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
900 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 901 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 902 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
905 break;
906 default:
907 break;
908 }
909}
910
911static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
912{
913 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 914 struct ixgbe_ring *ring;
bd0362dd 915 int cpu = get_cpu();
bd0362dd 916
33cf09c9
AD		 917 if (q_vector->cpu == cpu)
918 goto out_no_update;
919
efe3d3c8
AD		 920 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
921 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 922
efe3d3c8
AD		 923 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
924 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 925
926 q_vector->cpu = cpu;
927out_no_update:
bd0362dd
JC		 928 put_cpu();
929}
930
931static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
932{
33cf09c9 933 int num_q_vectors;
bd0362dd
JC		 934 int i;
935
936 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
937 return;
938
e35ec126
AD		 939 /* always use CB2 mode, difference is masked in the CB driver */
940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
941
33cf09c9
AD		 942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
943 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
944 else
945 num_q_vectors = 1;
946
947 for (i = 0; i < num_q_vectors; i++) {
948 adapter->q_vector[i]->cpu = -1;
949 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 950 }
951}
952
953static int __ixgbe_notify_dca(struct device *dev, void *data)
954{
c60fbb00 955 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 956 unsigned long event = *(unsigned long *)data;
957
2a72c31e 958 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 959 return 0;
960
bd0362dd
JC		 961 switch (event) {
962 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 963 /* if we're already enabled, don't do it again */
964 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
965 break;
652f093f 966 if (dca_add_requester(dev) == 0) {
96b0e0f6 967 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 968 ixgbe_setup_dca(adapter);
969 break;
970 }
971 /* Fall Through since DCA is disabled. */
972 case DCA_PROVIDER_REMOVE:
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
974 dca_remove_requester(dev);
975 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
976 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
977 }
978 break;
979 }
980
652f093f 981 return 0;
bd0362dd 982}
5dd2d332 983#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 984
985static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
986 struct sk_buff *skb)
987{
988 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
989}
990
ff886dfc
AD		 991/**
992 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
993 * @adapter: address of board private structure
994 * @rx_desc: advanced rx descriptor
995 *
996 * Returns : true if it is FCoE pkt
997 */
998static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
999 union ixgbe_adv_rx_desc *rx_desc)
1000{
1001 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1002
1003 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1004 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1005 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1006 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1007}
1008
9a799d71
AK		 1009/**
1010 * ixgbe_receive_skb - Send a completed packet up the stack
1011 * @adapter: board private structure
1012 * @skb: packet to send up
177db6ff
MC		 1013 * @status: hardware indication of status of receive
1014 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1015 * @rx_desc: rx descriptor
9a799d71 1016 **/
78b6f4ce 1017static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1018 struct sk_buff *skb, u8 status,
1019 struct ixgbe_ring *ring,
1020 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1021{
78b6f4ce
HX		 1022 struct ixgbe_adapter *adapter = q_vector->adapter;
1023 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1024 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1025 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1026
f62bbb5e
JG		 1027 if (is_vlan && (tag & VLAN_VID_MASK))
1028 __vlan_hwaccel_put_tag(skb, tag);
1029
1030 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1031 napi_gro_receive(napi, skb);
1032 else
1033 netif_rx(skb);
9a799d71
AK		 1034}
1035
e59bd25d
AV		 1036/**
1037 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1038 * @adapter: address of board private structure
1039 * @status_err: hardware indication of status of receive
1040 * @skb: skb currently being received and modified
ff886dfc 1041 * @status_err: status error value of last descriptor in packet
e59bd25d 1042 **/
9a799d71 1043static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1044 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1045 struct sk_buff *skb,
1046 u32 status_err)
9a799d71 1047{
ff886dfc 1048 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1049
712744be
JB		 1050 /* Rx csum disabled */
1051 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1052 return;
e59bd25d
AV		 1053
1054 /* if IP and error */
1055 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1056 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1057 adapter->hw_csum_rx_error++;
1058 return;
1059 }
e59bd25d
AV		 1060
1061 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1062 return;
1063
1064 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1065 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1066
1067 /*
1068 * 82599 errata, UDP frames with a 0 checksum can be marked as
1069 * checksum errors.
1070 */
1071 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1072 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1073 return;
1074
e59bd25d
AV		 1075 adapter->hw_csum_rx_error++;
1076 return;
1077 }
1078
9a799d71 1079 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1080 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1081}
1082
84ea2591 1083static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1084{
1085 /*
1086 * Force memory writes to complete before letting h/w
1087 * know there are new descriptors to fetch. (Only
1088 * applicable for weak-ordered memory model archs,
1089 * such as IA-64).
1090 */
1091 wmb();
84ea2591 1092 writel(val, rx_ring->tail);
e8e26350
PW		 1093}
1094
9a799d71
AK		 1095/**
1096 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1097 * @rx_ring: ring to place buffers on
1098 * @cleaned_count: number of buffers to replace
9a799d71 1099 **/
fc77dc3c 1100void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1101{
9a799d71 1102 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1103 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1104 struct sk_buff *skb;
1105 u16 i = rx_ring->next_to_use;
9a799d71 1106
fc77dc3c
AD		 1107 /* do nothing if no valid netdev defined */
1108 if (!rx_ring->netdev)
1109 return;
1110
9a799d71 1111 while (cleaned_count--) {
31f05a2d 1112 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1113 bi = &rx_ring->rx_buffer_info[i];
1114 skb = bi->skb;
9a799d71 1115
d5f398ed 1116 if (!skb) {
fc77dc3c 1117 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1118 rx_ring->rx_buf_len);
9a799d71 1119 if (!skb) {
5b7da515 1120 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1121 goto no_buffers;
1122 }
d716a7d8
AD		 1123 /* initialize queue mapping */
1124 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1125 bi->skb = skb;
d716a7d8 1126 }
9a799d71 1127
d716a7d8 1128 if (!bi->dma) {
b6ec895e 1129 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1130 skb->data,
e8e9f696 1131 rx_ring->rx_buf_len,
1b507730 1132 DMA_FROM_DEVICE);
b6ec895e 1133 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1134 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1135 bi->dma = 0;
1136 goto no_buffers;
1137 }
9a799d71 1138 }
d5f398ed 1139
7d637bcc 1140 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1141 if (!bi->page) {
fc77dc3c 1142 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1143 if (!bi->page) {
5b7da515 1144 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1145 goto no_buffers;
1146 }
1147 }
1148
1149 if (!bi->page_dma) {
1150 /* use a half page if we're re-using */
1151 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1152 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1153 bi->page,
1154 bi->page_offset,
1155 PAGE_SIZE / 2,
1156 DMA_FROM_DEVICE);
b6ec895e 1157 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1158 bi->page_dma)) {
5b7da515 1159 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1160 bi->page_dma = 0;
1161 goto no_buffers;
1162 }
1163 }
1164
1165 /* Refresh the desc even if buffer_addrs didn't change
1166 * because each write-back erases this info. */
3a581073
JB		 1167 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1168 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1169 } else {
3a581073 1170 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1171 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1172 }
1173
1174 i++;
1175 if (i == rx_ring->count)
1176 i = 0;
9a799d71 1177 }
7c6e0a43 1178
9a799d71
AK		 1179no_buffers:
1180 if (rx_ring->next_to_use != i) {
1181 rx_ring->next_to_use = i;
84ea2591 1182 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1183 }
1184}
1185
c267fc16 1186static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1187{
c267fc16
AD		 1188 /* HW will not DMA in data larger than the given buffer, even if it
1189 * parses the (NFS, of course) header to be larger. In that case, it
1190 * fills the header buffer and spills the rest into the page.
1191 */
1192 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1193 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1194 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1195 if (hlen > IXGBE_RX_HDR_SIZE)
1196 hlen = IXGBE_RX_HDR_SIZE;
1197 return hlen;
7c6e0a43
JB		 1198}
1199
f8212f97
AD		 1200/**
1201 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1202 * @skb: pointer to the last skb in the rsc queue
1203 *
1204 * This function changes a queue full of hw rsc buffers into a completed
1205 * packet. It uses the ->prev pointers to find the first packet and then
1206 * turns it into the frag list owner.
1207 **/
aa80175a 1208static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1209{
1210 unsigned int frag_list_size = 0;
aa80175a 1211 unsigned int skb_cnt = 1;
f8212f97
AD		 1212
1213 while (skb->prev) {
1214 struct sk_buff *prev = skb->prev;
1215 frag_list_size += skb->len;
1216 skb->prev = NULL;
1217 skb = prev;
aa80175a 1218 skb_cnt++;
f8212f97
AD		 1219 }
1220
1221 skb_shinfo(skb)->frag_list = skb->next;
1222 skb->next = NULL;
1223 skb->len += frag_list_size;
1224 skb->data_len += frag_list_size;
1225 skb->truesize += frag_list_size;
aa80175a
AD		 1226 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1227
f8212f97
AD		 1228 return skb;
1229}
1230
aa80175a
AD		 1231static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1232{
1233 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1234 IXGBE_RXDADV_RSCCNT_MASK);
1235}
43634e82 1236
4ff7fb12 1237static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1238 struct ixgbe_ring *rx_ring,
4ff7fb12 1239 int budget)
9a799d71 1240{
78b6f4ce 1241 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1242 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1243 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1244 struct sk_buff *skb;
d2f4fbe2 1245 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1246 const int current_node = numa_node_id();
3d8fd385
YZ		 1247#ifdef IXGBE_FCOE
1248 int ddp_bytes = 0;
1249#endif /* IXGBE_FCOE */
c267fc16
AD		 1250 u32 staterr;
1251 u16 i;
1252 u16 cleaned_count = 0;
aa80175a 1253 bool pkt_is_rsc = false;
9a799d71
AK		 1254
1255 i = rx_ring->next_to_clean;
31f05a2d 1256 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1257 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1258
1259 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1260 u32 upper_len = 0;
9a799d71 1261
3c945e5b 1262 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1263
c267fc16
AD		 1264 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1265
9a799d71 1266 skb = rx_buffer_info->skb;
9a799d71 1267 rx_buffer_info->skb = NULL;
c267fc16 1268 prefetch(skb->data);
9a799d71 1269
c267fc16 1270 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1271 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16 1272
b811ce91
JB		 1273 /* linear means we are building an skb from multiple pages */
1274 if (!skb_is_nonlinear(skb)) {
c267fc16 1275 u16 hlen;
aa80175a 1276 if (pkt_is_rsc &&
c267fc16
AD		 1277 !(staterr & IXGBE_RXD_STAT_EOP) &&
1278 !skb->prev) {
43634e82
MC		 1279 /*
1280 * When HWRSC is enabled, delay unmapping
1281 * of the first packet. It carries the
1282 * header information, HW may still
1283 * access the header after the writeback.
1284 * Only unmap it when EOP is reached
1285 */
e8171aaa 1286 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1287 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1288 } else {
b6ec895e 1289 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1290 rx_buffer_info->dma,
1291 rx_ring->rx_buf_len,
1292 DMA_FROM_DEVICE);
e8171aaa 1293 }
4f57ca6e 1294 rx_buffer_info->dma = 0;
c267fc16
AD		 1295
1296 if (ring_is_ps_enabled(rx_ring)) {
1297 hlen = ixgbe_get_hlen(rx_desc);
1298 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1299 } else {
1300 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1301 }
1302
1303 skb_put(skb, hlen);
1304 } else {
1305 /* assume packet split since header is unmapped */
1306 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1307 }
1308
1309 if (upper_len) {
b6ec895e
AD		 1310 dma_unmap_page(rx_ring->dev,
1311 rx_buffer_info->page_dma,
1312 PAGE_SIZE / 2,
1313 DMA_FROM_DEVICE);
9a799d71
AK		 1314 rx_buffer_info->page_dma = 0;
1315 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1316 rx_buffer_info->page,
1317 rx_buffer_info->page_offset,
1318 upper_len);
762f4c57 1319
c267fc16
AD		 1320 if ((page_count(rx_buffer_info->page) == 1) &&
1321 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1322 get_page(rx_buffer_info->page);
c267fc16
AD		 1323 else
1324 rx_buffer_info->page = NULL;
9a799d71
AK		 1325
1326 skb->len += upper_len;
1327 skb->data_len += upper_len;
1328 skb->truesize += upper_len;
1329 }
1330
1331 i++;
1332 if (i == rx_ring->count)
1333 i = 0;
9a799d71 1334
31f05a2d 1335 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1336 prefetch(next_rxd);
9a799d71 1337 cleaned_count++;
f8212f97 1338
aa80175a 1339 if (pkt_is_rsc) {
f8212f97
AD		 1340 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1341 IXGBE_RXDADV_NEXTP_SHIFT;
1342 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1343 } else {
1344 next_buffer = &rx_ring->rx_buffer_info[i];
1345 }
1346
c267fc16 1347 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1348 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1349 rx_buffer_info->skb = next_buffer->skb;
1350 rx_buffer_info->dma = next_buffer->dma;
1351 next_buffer->skb = skb;
1352 next_buffer->dma = 0;
1353 } else {
1354 skb->next = next_buffer->skb;
1355 skb->next->prev = skb;
1356 }
5b7da515 1357 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1358 goto next_desc;
1359 }
1360
aa80175a
AD		 1361 if (skb->prev) {
1362 skb = ixgbe_transform_rsc_queue(skb);
1363 /* if we got here without RSC the packet is invalid */
1364 if (!pkt_is_rsc) {
1365 __pskb_trim(skb, 0);
1366 rx_buffer_info->skb = skb;
1367 goto next_desc;
1368 }
1369 }
c267fc16
AD		 1370
1371 if (ring_is_rsc_enabled(rx_ring)) {
1372 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1373 dma_unmap_single(rx_ring->dev,
1374 IXGBE_RSC_CB(skb)->dma,
1375 rx_ring->rx_buf_len,
1376 DMA_FROM_DEVICE);
1377 IXGBE_RSC_CB(skb)->dma = 0;
1378 IXGBE_RSC_CB(skb)->delay_unmap = false;
1379 }
aa80175a
AD		 1380 }
1381 if (pkt_is_rsc) {
c267fc16
AD		 1382 if (ring_is_ps_enabled(rx_ring))
1383 rx_ring->rx_stats.rsc_count +=
aa80175a 1384 skb_shinfo(skb)->nr_frags;
c267fc16 1385 else
aa80175a
AD		 1386 rx_ring->rx_stats.rsc_count +=
1387 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1388 rx_ring->rx_stats.rsc_flush++;
1389 }
1390
1391 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1392 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1393 dev_kfree_skb_any(skb);
9a799d71
AK		 1394 goto next_desc;
1395 }
1396
ff886dfc 1397 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1398 if (adapter->netdev->features & NETIF_F_RXHASH)
1399 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1400
1401 /* probably a little skewed due to removing CRC */
1402 total_rx_bytes += skb->len;
1403 total_rx_packets++;
1404
fc77dc3c 1405 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1406#ifdef IXGBE_FCOE
1407 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1408 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1409 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1410 staterr);
63d635b2
AD		 1411 if (!ddp_bytes) {
1412 dev_kfree_skb_any(skb);
332d4a7d 1413 goto next_desc;
63d635b2 1414 }
3d8fd385 1415 }
332d4a7d 1416#endif /* IXGBE_FCOE */
fdaff1ce 1417 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1418
4ff7fb12 1419 budget--;
9a799d71
AK		 1420next_desc:
1421 rx_desc->wb.upper.status_error = 0;
1422
4ff7fb12 1423 if (!budget)
c267fc16
AD		 1424 break;
1425
9a799d71
AK		 1426 /* return some buffers to hardware, one at a time is too slow */
1427 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1428 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1429 cleaned_count = 0;
1430 }
1431
1432 /* use prefetched values */
1433 rx_desc = next_rxd;
9a799d71 1434 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1435 }
1436
9a799d71 1437 rx_ring->next_to_clean = i;
7d4987de 1438 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1439
1440 if (cleaned_count)
fc77dc3c 1441 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1442
3d8fd385
YZ		 1443#ifdef IXGBE_FCOE
1444 /* include DDPed FCoE data */
1445 if (ddp_bytes > 0) {
1446 unsigned int mss;
1447
fc77dc3c 1448 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1449 sizeof(struct fc_frame_header) -
1450 sizeof(struct fcoe_crc_eof);
1451 if (mss > 512)
1452 mss &= ~511;
1453 total_rx_bytes += ddp_bytes;
1454 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1455 }
1456#endif /* IXGBE_FCOE */
1457
c267fc16
AD		 1458 u64_stats_update_begin(&rx_ring->syncp);
1459 rx_ring->stats.packets += total_rx_packets;
1460 rx_ring->stats.bytes += total_rx_bytes;
1461 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1462 q_vector->rx.total_packets += total_rx_packets;
1463 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1464
1465 return !!budget;
9a799d71
AK		 1466}
1467
9a799d71
AK		 1468/**
1469 * ixgbe_configure_msix - Configure MSI-X hardware
1470 * @adapter: board private structure
1471 *
1472 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1473 * interrupts.
1474 **/
1475static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1476{
021230d4 1477 struct ixgbe_q_vector *q_vector;
efe3d3c8 1478 int q_vectors, v_idx;
021230d4 1479 u32 mask;
9a799d71 1480
021230d4 1481 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1482
8e34d1aa
AD		 1483 /* Populate MSIX to EITR Select */
1484 if (adapter->num_vfs > 32) {
1485 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1486 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1487 }
1488
4df10466
JB		 1489 /*
1490 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1491 * corresponding register.
1492 */
1493 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1494 struct ixgbe_ring *ring;
7a921c93 1495 q_vector = adapter->q_vector[v_idx];
021230d4 1496
efe3d3c8
AD		 1497 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1498 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1499
1500 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1501 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1502
d5bf4f67
ET		 1503 if (q_vector->tx.ring && !q_vector->rx.ring) {
1504 /* tx only vector */
1505 if (adapter->tx_itr_setting == 1)
1506 q_vector->itr = IXGBE_10K_ITR;
1507 else
1508 q_vector->itr = adapter->tx_itr_setting;
1509 } else {
1510 /* rx or rx/tx vector */
1511 if (adapter->rx_itr_setting == 1)
1512 q_vector->itr = IXGBE_20K_ITR;
1513 else
1514 q_vector->itr = adapter->rx_itr_setting;
1515 }
021230d4 1516
fe49f04a 1517 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1518 }
1519
bd508178
AD		 1520 switch (adapter->hw.mac.type) {
1521 case ixgbe_mac_82598EB:
e8e26350 1522 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1523 v_idx);
bd508178
AD		 1524 break;
1525 case ixgbe_mac_82599EB:
b93a2226 1526 case ixgbe_mac_X540:
e8e26350 1527 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1528 break;
bd508178
AD		 1529 default:
1530 break;
1531 }
021230d4
AV		 1532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1533
41fb9248 1534 /* set up to autoclear timer, and the vectors */
021230d4 1535 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1536 mask &= ~(IXGBE_EIMS_OTHER |
1537 IXGBE_EIMS_MAILBOX |
1538 IXGBE_EIMS_LSC);
1539
021230d4 1540 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1541}
1542
f494e8fa
AV		 1543enum latency_range {
1544 lowest_latency = 0,
1545 low_latency = 1,
1546 bulk_latency = 2,
1547 latency_invalid = 255
1548};
1549
1550/**
1551 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1552 * @q_vector: structure containing interrupt and ring information
1553 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1554 *
1555 * Stores a new ITR value based on packets and byte
1556 * counts during the last interrupt. The advantage of per interrupt
1557 * computation is faster updates and more accurate ITR for the current
1558 * traffic pattern. Constants in this function were computed
1559 * based on theoretical maximum wire speed and thresholds were set based
1560 * on testing data as well as attempting to minimize response time
1561 * while increasing bulk throughput.
1562 * this functionality is controlled by the InterruptThrottleRate module
1563 * parameter (see ixgbe_param.c)
1564 **/
bd198058
AD		 1565static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1566 struct ixgbe_ring_container *ring_container)
f494e8fa 1567{
f494e8fa 1568 u64 bytes_perint;
bd198058
AD		 1569 struct ixgbe_adapter *adapter = q_vector->adapter;
1570 int bytes = ring_container->total_bytes;
1571 int packets = ring_container->total_packets;
1572 u32 timepassed_us;
1573 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1574
1575 if (packets == 0)
bd198058 1576 return;
f494e8fa
AV		 1577
1578 /* simple throttlerate management
1579 * 0-20MB/s lowest (100000 ints/s)
1580 * 20-100MB/s low (20000 ints/s)
1581 * 100-1249MB/s bulk (8000 ints/s)
1582 */
1583 /* what was last interrupt timeslice? */
d5bf4f67 1584 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1585 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1586
1587 switch (itr_setting) {
1588 case lowest_latency:
1589 if (bytes_perint > adapter->eitr_low)
bd198058 1590 itr_setting = low_latency;
f494e8fa
AV		 1591 break;
1592 case low_latency:
1593 if (bytes_perint > adapter->eitr_high)
bd198058 1594 itr_setting = bulk_latency;
f494e8fa 1595 else if (bytes_perint <= adapter->eitr_low)
bd198058 1596 itr_setting = lowest_latency;
f494e8fa
AV		 1597 break;
1598 case bulk_latency:
1599 if (bytes_perint <= adapter->eitr_high)
bd198058 1600 itr_setting = low_latency;
f494e8fa
AV		 1601 break;
1602 }
1603
bd198058
AD		 1604 /* clear work counters since we have the values we need */
1605 ring_container->total_bytes = 0;
1606 ring_container->total_packets = 0;
1607
1608 /* write updated itr to ring container */
1609 ring_container->itr = itr_setting;
f494e8fa
AV		 1610}
1611
509ee935
JB		 1612/**
1613 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1614 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1615 *
1616 * This function is made to be called by ethtool and by the driver
1617 * when it needs to update EITR registers at runtime. Hardware
1618 * specific quirks/differences are taken care of here.
1619 */
fe49f04a 1620void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1621{
fe49f04a 1622 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1623 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1624 int v_idx = q_vector->v_idx;
d5bf4f67 1625 u32 itr_reg = q_vector->itr;
fe49f04a 1626
bd508178
AD		 1627 switch (adapter->hw.mac.type) {
1628 case ixgbe_mac_82598EB:
509ee935
JB		 1629 /* must write high and low 16 bits to reset counter */
1630 itr_reg |= (itr_reg << 16);
bd508178
AD		 1631 break;
1632 case ixgbe_mac_82599EB:
b93a2226 1633 case ixgbe_mac_X540:
509ee935
JB		 1634 /*
1635 * set the WDIS bit to not clear the timer bits and cause an
1636 * immediate assertion of the interrupt
1637 */
1638 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1639 break;
1640 default:
1641 break;
509ee935
JB		 1642 }
1643 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1644}
1645
bd198058 1646static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1647{
d5bf4f67 1648 u32 new_itr = q_vector->itr;
bd198058 1649 u8 current_itr;
f494e8fa 1650
bd198058
AD		 1651 ixgbe_update_itr(q_vector, &q_vector->tx);
1652 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1653
08c8833b 1654 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1655
1656 switch (current_itr) {
1657 /* counts and packets in update_itr are dependent on these numbers */
1658 case lowest_latency:
d5bf4f67 1659 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1660 break;
1661 case low_latency:
d5bf4f67 1662 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1663 break;
1664 case bulk_latency:
d5bf4f67 1665 new_itr = IXGBE_8K_ITR;
f494e8fa 1666 break;
bd198058
AD		 1667 default:
1668 break;
f494e8fa
AV		 1669 }
1670
d5bf4f67 1671 if (new_itr != q_vector->itr) {
fe49f04a 1672 /* do an exponential smoothing */
d5bf4f67
ET		 1673 new_itr = (10 * new_itr * q_vector->itr) /
1674 ((9 * new_itr) + q_vector->itr);
509ee935 1675
bd198058 1676 /* save the algorithm value here */
d5bf4f67 1677 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1678
1679 ixgbe_write_eitr(q_vector);
f494e8fa 1680 }
f494e8fa
AV		 1681}
1682
119fc60a 1683/**
f0f9778d
AD		 1684 * ixgbe_check_overtemp_subtask - check for over tempurature
1685 * @adapter: pointer to adapter
119fc60a 1686 **/
f0f9778d 1687static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1688{
119fc60a
MC		 1689 struct ixgbe_hw *hw = &adapter->hw;
1690 u32 eicr = adapter->interrupt_event;
1691
f0f9778d 1692 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1693 return;
1694
f0f9778d
AD		 1695 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1696 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1697 return;
1698
1699 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1700
7ca647bd 1701 switch (hw->device_id) {
f0f9778d
AD		 1702 case IXGBE_DEV_ID_82599_T3_LOM:
1703 /*
1704 * Since the warning interrupt is for both ports
1705 * we don't have to check if:
1706 * - This interrupt wasn't for our port.
1707 * - We may have missed the interrupt so always have to
1708 * check if we got a LSC
1709 */
1710 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1711 !(eicr & IXGBE_EICR_LSC))
1712 return;
1713
1714 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1715 u32 autoneg;
1716 bool link_up = false;
7ca647bd 1717
7ca647bd
JP		 1718 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1719
f0f9778d
AD		 1720 if (link_up)
1721 return;
1722 }
1723
1724 /* Check if this is not due to overtemp */
1725 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1726 return;
1727
1728 break;
7ca647bd
JP		 1729 default:
1730 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1731 return;
7ca647bd 1732 break;
119fc60a 1733 }
7ca647bd
JP		 1734 e_crit(drv,
1735 "Network adapter has been stopped because it has over heated. "
1736 "Restart the computer. If the problem persists, "
1737 "power off the system and replace the adapter\n");
f0f9778d
AD		 1738
1739 adapter->interrupt_event = 0;
119fc60a
MC		 1740}
1741
0befdb3e
JB		 1742static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1743{
1744 struct ixgbe_hw *hw = &adapter->hw;
1745
1746 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1747 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1748 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1749 /* write to clear the interrupt */
1750 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1751 }
1752}
cf8280ee 1753
4f51bf70
JK		 1754static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1755{
1756 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1757 return;
1758
1759 switch (adapter->hw.mac.type) {
1760 case ixgbe_mac_82599EB:
1761 /*
1762 * Need to check link state so complete overtemp check
1763 * on service task
1764 */
1765 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1766 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1767 adapter->interrupt_event = eicr;
1768 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1769 ixgbe_service_event_schedule(adapter);
1770 return;
1771 }
1772 return;
1773 case ixgbe_mac_X540:
1774 if (!(eicr & IXGBE_EICR_TS))
1775 return;
1776 break;
1777 default:
1778 return;
1779 }
1780
1781 e_crit(drv,
1782 "Network adapter has been stopped because it has over heated. "
1783 "Restart the computer. If the problem persists, "
1784 "power off the system and replace the adapter\n");
1785}
1786
e8e26350
PW		 1787static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1788{
1789 struct ixgbe_hw *hw = &adapter->hw;
1790
73c4b7cd
AD		 1791 if (eicr & IXGBE_EICR_GPI_SDP2) {
1792 /* Clear the interrupt */
1793 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1794 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1795 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1796 ixgbe_service_event_schedule(adapter);
1797 }
73c4b7cd
AD		 1798 }
1799
e8e26350
PW		 1800 if (eicr & IXGBE_EICR_GPI_SDP1) {
1801 /* Clear the interrupt */
1802 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1803 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1804 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1805 ixgbe_service_event_schedule(adapter);
1806 }
e8e26350
PW		 1807 }
1808}
1809
cf8280ee
JB		 1810static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1811{
1812 struct ixgbe_hw *hw = &adapter->hw;
1813
1814 adapter->lsc_int++;
1815 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1816 adapter->link_check_timeout = jiffies;
1817 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1818 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1819 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1820 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1821 }
1822}
1823
fe49f04a
AD		 1824static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1825 u64 qmask)
1826{
1827 u32 mask;
bd508178 1828 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1829
bd508178
AD		 1830 switch (hw->mac.type) {
1831 case ixgbe_mac_82598EB:
fe49f04a 1832 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1833 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1834 break;
1835 case ixgbe_mac_82599EB:
b93a2226 1836 case ixgbe_mac_X540:
fe49f04a 1837 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1838 if (mask)
1839 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1840 mask = (qmask >> 32);
bd508178
AD		 1841 if (mask)
1842 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1843 break;
1844 default:
1845 break;
fe49f04a
AD		 1846 }
1847 /* skip the flush */
1848}
1849
1850static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1851 u64 qmask)
fe49f04a
AD		 1852{
1853 u32 mask;
bd508178 1854 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1855
bd508178
AD		 1856 switch (hw->mac.type) {
1857 case ixgbe_mac_82598EB:
fe49f04a 1858 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1859 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1860 break;
1861 case ixgbe_mac_82599EB:
b93a2226 1862 case ixgbe_mac_X540:
fe49f04a 1863 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1864 if (mask)
1865 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1866 mask = (qmask >> 32);
bd508178
AD		 1867 if (mask)
1868 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1869 break;
1870 default:
1871 break;
fe49f04a
AD		 1872 }
1873 /* skip the flush */
1874}
1875
021230d4 1876/**
2c4af694
AD		 1877 * ixgbe_irq_enable - Enable default interrupt generation settings
1878 * @adapter: board private structure
021230d4 1879 **/
2c4af694
AD		 1880static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1881 bool flush)
9a799d71 1882{
2c4af694 1883 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 1884
2c4af694
AD		 1885 /* don't reenable LSC while waiting for link */
1886 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1887 mask &= ~IXGBE_EIMS_LSC;
9a799d71 1888
2c4af694 1889 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 1890 switch (adapter->hw.mac.type) {
1891 case ixgbe_mac_82599EB:
1892 mask |= IXGBE_EIMS_GPI_SDP0;
1893 break;
1894 case ixgbe_mac_X540:
1895 mask |= IXGBE_EIMS_TS;
1896 break;
1897 default:
1898 break;
1899 }
2c4af694
AD		 1900 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1901 mask |= IXGBE_EIMS_GPI_SDP1;
1902 switch (adapter->hw.mac.type) {
1903 case ixgbe_mac_82599EB:
2c4af694
AD		 1904 mask |= IXGBE_EIMS_GPI_SDP1;
1905 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 1906 case ixgbe_mac_X540:
1907 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 1908 mask |= IXGBE_EIMS_MAILBOX;
1909 break;
1910 default:
1911 break;
9a799d71 1912 }
2c4af694
AD		 1913 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1914 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1915 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 1916
2c4af694
AD		 1917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1918 if (queues)
1919 ixgbe_irq_enable_queues(adapter, ~0);
1920 if (flush)
1921 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1922}
1923
2c4af694 1924static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 1925{
a65151ba 1926 struct ixgbe_adapter *adapter = data;
9a799d71 1927 struct ixgbe_hw *hw = &adapter->hw;
54037505 1928 u32 eicr;
91281fd3 1929
54037505
DS		 1930 /*
1931 * Workaround for Silicon errata. Use clear-by-write instead
1932 * of clear-by-read. Reading with EICS will return the
1933 * interrupt causes without clearing, which later be done
1934 * with the write to EICR.
1935 */
1936 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1937 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 1938
cf8280ee
JB		 1939 if (eicr & IXGBE_EICR_LSC)
1940 ixgbe_check_lsc(adapter);
f0848276 1941
1cdd1ec8
GR		 1942 if (eicr & IXGBE_EICR_MAILBOX)
1943 ixgbe_msg_task(adapter);
efe3d3c8 1944
bd508178
AD		 1945 switch (hw->mac.type) {
1946 case ixgbe_mac_82599EB:
b93a2226 1947 case ixgbe_mac_X540:
2c4af694
AD		 1948 if (eicr & IXGBE_EICR_ECC)
1949 e_info(link, "Received unrecoverable ECC Err, please "
1950 "reboot\n");
c4cf55e5
PWJ		 1951 /* Handle Flow Director Full threshold interrupt */
1952 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1953 int reinit_count = 0;
c4cf55e5 1954 int i;
c4cf55e5 1955 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1956 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1957 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1958 &ring->state))
1959 reinit_count++;
1960 }
1961 if (reinit_count) {
1962 /* no more flow director interrupts until after init */
1963 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 1964 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1965 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1966 }
1967 }
f0f9778d 1968 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 1969 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 1970 break;
1971 default:
1972 break;
c4cf55e5 1973 }
f0848276 1974
bd508178 1975 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 1976
7086400d 1977 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1978 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 1979 ixgbe_irq_enable(adapter, false, false);
f0848276 1980
9a799d71 1981 return IRQ_HANDLED;
f0848276 1982}
91281fd3 1983
4ff7fb12 1984static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 1985{
021230d4 1986 struct ixgbe_q_vector *q_vector = data;
91281fd3 1987
9b471446 1988 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1989
4ff7fb12
AD		 1990 if (q_vector->rx.ring || q_vector->tx.ring)
1991 napi_schedule(&q_vector->napi);
91281fd3 1992
9a799d71 1993 return IRQ_HANDLED;
91281fd3
AD		 1994}
1995
021230d4 1996static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 1997 int r_idx)
021230d4 1998{
7a921c93 1999 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2000 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2001
2274543f 2002 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2003 rx_ring->next = q_vector->rx.ring;
2004 q_vector->rx.ring = rx_ring;
2005 q_vector->rx.count++;
021230d4
AV		 2006}
2007
2008static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2009 int t_idx)
021230d4 2010{
7a921c93 2011 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2012 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2013
2274543f 2014 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2015 tx_ring->next = q_vector->tx.ring;
2016 q_vector->tx.ring = tx_ring;
2017 q_vector->tx.count++;
bd198058 2018 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2019}
2020
9a799d71 2021/**
021230d4
AV		 2022 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2023 * @adapter: board private structure to initialize
9a799d71 2024 *
021230d4
AV		 2025 * This function maps descriptor rings to the queue-specific vectors
2026 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2027 * one vector per ring/queue, but on a constrained vector budget, we
2028 * group the rings as "efficiently" as possible. You would add new
2029 * mapping configurations in here.
9a799d71 2030 **/
4cc6df29 2031static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2032{
4cc6df29
AD		 2033 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2034 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2035 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2036 int v_start = 0;
021230d4 2037
4cc6df29 2038 /* only one q_vector if MSI-X is disabled. */
021230d4 2039 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2040 q_vectors = 1;
d0759ebb 2041
021230d4 2042 /*
4cc6df29
AD		 2043 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2044 * group them so there are multiple queues per vector.
2045 *
2046 * Re-adjusting *qpv takes care of the remainder.
021230d4 2047 */
4cc6df29
AD		 2048 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2049 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2050 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2051 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2052 }
9a799d71 2053
021230d4 2054 /*
4cc6df29
AD		 2055 * If there are not enough q_vectors for each ring to have it's own
2056 * vector then we must pair up Rx/Tx on a each vector
021230d4 2057 */
4cc6df29
AD		 2058 if ((v_start + txr_remaining) > q_vectors)
2059 v_start = 0;
2060
2061 for (; v_start < q_vectors && txr_remaining; v_start++) {
2062 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2063 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2064 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2065 }
021230d4
AV		 2066}
2067
2068/**
2069 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2070 * @adapter: board private structure
2071 *
2072 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2073 * interrupts from the kernel.
2074 **/
2075static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2076{
2077 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2078 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2079 int vector, err;
e8e9f696 2080 int ri = 0, ti = 0;
021230d4 2081
021230d4 2082 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2083 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2084 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2085
4ff7fb12 2086 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2087 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2088 "%s-%s-%d", netdev->name, "TxRx", ri++);
2089 ti++;
2090 } else if (q_vector->rx.ring) {
9fe93afd 2091 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2092 "%s-%s-%d", netdev->name, "rx", ri++);
2093 } else if (q_vector->tx.ring) {
9fe93afd 2094 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2095 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2096 } else {
2097 /* skip this unused q_vector */
2098 continue;
32aa77a4 2099 }
207867f5
AD		 2100 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2101 q_vector->name, q_vector);
9a799d71 2102 if (err) {
396e799c 2103 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2104 "Error: %d\n", err);
021230d4 2105 goto free_queue_irqs;
9a799d71 2106 }
207867f5
AD		 2107 /* If Flow Director is enabled, set interrupt affinity */
2108 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2109 /* assign the mask for this irq */
2110 irq_set_affinity_hint(entry->vector,
2111 q_vector->affinity_mask);
2112 }
9a799d71
AK		 2113 }
2114
021230d4 2115 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2116 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2117 if (err) {
396e799c 2118 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2119 goto free_queue_irqs;
9a799d71
AK		 2120 }
2121
9a799d71
AK		 2122 return 0;
2123
021230d4 2124free_queue_irqs:
207867f5
AD		 2125 while (vector) {
2126 vector--;
2127 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2128 NULL);
2129 free_irq(adapter->msix_entries[vector].vector,
2130 adapter->q_vector[vector]);
2131 }
021230d4
AV		 2132 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2133 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2134 kfree(adapter->msix_entries);
2135 adapter->msix_entries = NULL;
9a799d71
AK		 2136 return err;
2137}
2138
2139/**
021230d4 2140 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2141 * @irq: interrupt number
2142 * @data: pointer to a network interface device structure
9a799d71
AK		 2143 **/
2144static irqreturn_t ixgbe_intr(int irq, void *data)
2145{
a65151ba 2146 struct ixgbe_adapter *adapter = data;
9a799d71 2147 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2148 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2149 u32 eicr;
2150
54037505 2151 /*
6af3b9eb 2152 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2153 * before the read of EICR.
2154 */
2155 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2156
021230d4
AV		 2157 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2158 * therefore no explict interrupt disable is necessary */
2159 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2160 if (!eicr) {
6af3b9eb
ET		 2161 /*
2162 * shared interrupt alert!
f47cf66e 2163 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2164 * have disabled interrupts due to EIAM
2165 * finish the workaround of silicon errata on 82598. Unmask
2166 * the interrupt that we masked before the EICR read.
2167 */
2168 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2169 ixgbe_irq_enable(adapter, true, true);
9a799d71 2170 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2171 }
9a799d71 2172
cf8280ee
JB		 2173 if (eicr & IXGBE_EICR_LSC)
2174 ixgbe_check_lsc(adapter);
021230d4 2175
bd508178
AD		 2176 switch (hw->mac.type) {
2177 case ixgbe_mac_82599EB:
e8e26350 2178 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2179 /* Fall through */
2180 case ixgbe_mac_X540:
2181 if (eicr & IXGBE_EICR_ECC)
2182 e_info(link, "Received unrecoverable ECC err, please "
2183 "reboot\n");
4f51bf70 2184 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2185 break;
2186 default:
2187 break;
2188 }
e8e26350 2189
0befdb3e
JB		 2190 ixgbe_check_fan_failure(adapter, eicr);
2191
7a921c93 2192 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2193 /* would disable interrupts here but EIAM disabled it */
7a921c93 2194 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2195 }
2196
6af3b9eb
ET		 2197 /*
2198 * re-enable link(maybe) and non-queue interrupts, no flush.
2199 * ixgbe_poll will re-enable the queue interrupts
2200 */
2201
2202 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2203 ixgbe_irq_enable(adapter, false, false);
2204
9a799d71
AK		 2205 return IRQ_HANDLED;
2206}
2207
021230d4
AV		 2208static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2209{
efe3d3c8
AD		 2210 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2211 int i;
2212
2213 /* legacy and MSI only use one vector */
2214 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2215 q_vectors = 1;
2216
2217 for (i = 0; i < adapter->num_rx_queues; i++) {
2218 adapter->rx_ring[i]->q_vector = NULL;
2219 adapter->rx_ring[i]->next = NULL;
2220 }
2221 for (i = 0; i < adapter->num_tx_queues; i++) {
2222 adapter->tx_ring[i]->q_vector = NULL;
2223 adapter->tx_ring[i]->next = NULL;
2224 }
021230d4
AV		 2225
2226 for (i = 0; i < q_vectors; i++) {
7a921c93 2227 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2228 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2229 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2230 }
2231}
2232
9a799d71
AK		 2233/**
2234 * ixgbe_request_irq - initialize interrupts
2235 * @adapter: board private structure
2236 *
2237 * Attempts to configure interrupts using the best available
2238 * capabilities of the hardware and kernel.
2239 **/
021230d4 2240static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2241{
2242 struct net_device *netdev = adapter->netdev;
021230d4 2243 int err;
9a799d71 2244
4cc6df29
AD		 2245 /* map all of the rings to the q_vectors */
2246 ixgbe_map_rings_to_vectors(adapter);
2247
2248 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2249 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2250 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2251 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2252 netdev->name, adapter);
4cc6df29 2253 else
a0607fd3 2254 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2255 netdev->name, adapter);
9a799d71 2256
4cc6df29 2257 if (err) {
396e799c 2258 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2259
4cc6df29
AD		 2260 /* place q_vectors and rings back into a known good state */
2261 ixgbe_reset_q_vectors(adapter);
2262 }
2263
9a799d71
AK		 2264 return err;
2265}
2266
2267static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2268{
9a799d71 2269 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2270 int i, q_vectors;
9a799d71 2271
021230d4 2272 q_vectors = adapter->num_msix_vectors;
021230d4 2273 i = q_vectors - 1;
a65151ba 2274 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2275 i--;
4cc6df29 2276
021230d4 2277 for (; i >= 0; i--) {
894ff7cf 2278 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2279 if (!adapter->q_vector[i]->rx.ring &&
2280 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2281 continue;
2282
207867f5
AD		 2283 /* clear the affinity_mask in the IRQ descriptor */
2284 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2285 NULL);
2286
021230d4 2287 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2288 adapter->q_vector[i]);
021230d4 2289 }
021230d4 2290 } else {
a65151ba 2291 free_irq(adapter->pdev->irq, adapter);
9a799d71 2292 }
207867f5
AD		 2293
2294 /* clear q_vector state information */
2295 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2296}
2297
22d5a71b
JB		 2298/**
2299 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2300 * @adapter: board private structure
2301 **/
2302static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2303{
bd508178
AD		 2304 switch (adapter->hw.mac.type) {
2305 case ixgbe_mac_82598EB:
835462fc 2306 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2307 break;
2308 case ixgbe_mac_82599EB:
b93a2226 2309 case ixgbe_mac_X540:
835462fc
NS		 2310 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2311 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2313 break;
2314 default:
2315 break;
22d5a71b
JB		 2316 }
2317 IXGBE_WRITE_FLUSH(&adapter->hw);
2318 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2319 int i;
2320 for (i = 0; i < adapter->num_msix_vectors; i++)
2321 synchronize_irq(adapter->msix_entries[i].vector);
2322 } else {
2323 synchronize_irq(adapter->pdev->irq);
2324 }
2325}
2326
9a799d71
AK		 2327/**
2328 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2329 *
2330 **/
2331static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2332{
d5bf4f67 2333 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2334
d5bf4f67
ET		 2335 /* rx/tx vector */
2336 if (adapter->rx_itr_setting == 1)
2337 q_vector->itr = IXGBE_20K_ITR;
2338 else
2339 q_vector->itr = adapter->rx_itr_setting;
2340
2341 ixgbe_write_eitr(q_vector);
9a799d71 2342
e8e26350
PW		 2343 ixgbe_set_ivar(adapter, 0, 0, 0);
2344 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2345
396e799c 2346 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2347}
2348
43e69bf0
AD		 2349/**
2350 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2351 * @adapter: board private structure
2352 * @ring: structure containing ring specific data
2353 *
2354 * Configure the Tx descriptor ring after a reset.
2355 **/
84418e3b
AD		 2356void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2357 struct ixgbe_ring *ring)
43e69bf0
AD		 2358{
2359 struct ixgbe_hw *hw = &adapter->hw;
2360 u64 tdba = ring->dma;
2f1860b8 2361 int wait_loop = 10;
b88c6de2 2362 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2363 u8 reg_idx = ring->reg_idx;
43e69bf0 2364
2f1860b8 2365 /* disable queue to avoid issues while updating state */
b88c6de2 2366 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2367 IXGBE_WRITE_FLUSH(hw);
2368
43e69bf0 2369 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2370 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2371 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2372 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2373 ring->count * sizeof(union ixgbe_adv_tx_desc));
2374 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2375 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2376 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2377
b88c6de2
AD		 2378 /*
2379 * set WTHRESH to encourage burst writeback, it should not be set
2380 * higher than 1 when ITR is 0 as it could cause false TX hangs
2381 *
2382 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2383 * to or less than the number of on chip descriptors, which is
2384 * currently 40.
2385 */
2386 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2387 txdctl |= (1 << 16); /* WTHRESH = 1 */
2388 else
2389 txdctl |= (8 << 16); /* WTHRESH = 8 */
2390
2391 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2392 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2393 32; /* PTHRESH = 32 */
2f1860b8
AD		 2394
2395 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2396 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2397 adapter->atr_sample_rate) {
2398 ring->atr_sample_rate = adapter->atr_sample_rate;
2399 ring->atr_count = 0;
2400 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2401 } else {
2402 ring->atr_sample_rate = 0;
2403 }
2f1860b8 2404
c84d324c
JF		 2405 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2406
2f1860b8 2407 /* enable queue */
2f1860b8
AD		 2408 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2409
2410 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2411 if (hw->mac.type == ixgbe_mac_82598EB &&
2412 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2413 return;
2414
2415 /* poll to verify queue is enabled */
2416 do {
032b4325 2417 usleep_range(1000, 2000);
2f1860b8
AD		 2418 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2419 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2420 if (!wait_loop)
2421 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2422}
2423
120ff942
AD		 2424static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2425{
2426 struct ixgbe_hw *hw = &adapter->hw;
2427 u32 rttdcs;
72a32f1f 2428 u32 reg;
8b1c0b24 2429 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2430
2431 if (hw->mac.type == ixgbe_mac_82598EB)
2432 return;
2433
2434 /* disable the arbiter while setting MTQC */
2435 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2436 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2437 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2438
2439 /* set transmit pool layout */
8b1c0b24 2440 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2441 case (IXGBE_FLAG_SRIOV_ENABLED):
2442 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2443 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2444 break;
8b1c0b24
JF		 2445 default:
2446 if (!tcs)
2447 reg = IXGBE_MTQC_64Q_1PB;
2448 else if (tcs <= 4)
2449 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2450 else
2451 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2452
8b1c0b24 2453 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2454
8b1c0b24
JF		 2455 /* Enable Security TX Buffer IFG for multiple pb */
2456 if (tcs) {
2457 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2458 reg |= IXGBE_SECTX_DCB;
2459 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2460 }
120ff942
AD		 2461 break;
2462 }
2463
2464 /* re-enable the arbiter */
2465 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2466 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2467}
2468
9a799d71 2469/**
3a581073 2470 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2471 * @adapter: board private structure
2472 *
2473 * Configure the Tx unit of the MAC after a reset.
2474 **/
2475static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2476{
2f1860b8
AD		 2477 struct ixgbe_hw *hw = &adapter->hw;
2478 u32 dmatxctl;
43e69bf0 2479 u32 i;
9a799d71 2480
2f1860b8
AD		 2481 ixgbe_setup_mtqc(adapter);
2482
2483 if (hw->mac.type != ixgbe_mac_82598EB) {
2484 /* DMATXCTL.EN must be before Tx queues are enabled */
2485 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2486 dmatxctl |= IXGBE_DMATXCTL_TE;
2487 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2488 }
2489
9a799d71 2490 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2491 for (i = 0; i < adapter->num_tx_queues; i++)
2492 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2493}
2494
e8e26350 2495#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2496
a6616b42 2497static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2498 struct ixgbe_ring *rx_ring)
cc41ac7c 2499{
cc41ac7c 2500 u32 srrctl;
bf29ee6c 2501 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2502
bd508178
AD		 2503 switch (adapter->hw.mac.type) {
2504 case ixgbe_mac_82598EB: {
2505 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2506 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2507 reg_idx = reg_idx & mask;
cc41ac7c 2508 }
bd508178
AD		 2509 break;
2510 case ixgbe_mac_82599EB:
b93a2226 2511 case ixgbe_mac_X540:
bd508178
AD		 2512 default:
2513 break;
2514 }
2515
bf29ee6c 2516 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2517
2518 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2519 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2520 if (adapter->num_vfs)
2521 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2522
afafd5b0
AD		 2523 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2524 IXGBE_SRRCTL_BSIZEHDR_MASK;
2525
7d637bcc 2526 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2527#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2528 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2529#else
2530 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2531#endif
cc41ac7c 2532 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2533 } else {
afafd5b0
AD		 2534 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2535 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2536 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2537 }
e8e26350 2538
bf29ee6c 2539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2540}
9a799d71 2541
05abb126 2542static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2543{
05abb126
AD		 2544 struct ixgbe_hw *hw = &adapter->hw;
2545 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2546 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2547 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2548 u32 mrqc = 0, reta = 0;
2549 u32 rxcsum;
2550 int i, j;
8b1c0b24 2551 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2552 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2553
2554 if (tcs)
2555 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2556
05abb126
AD		 2557 /* Fill out hash function seeds */
2558 for (i = 0; i < 10; i++)
2559 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2560
2561 /* Fill out redirection table */
2562 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2563 if (j == maxq)
05abb126
AD		 2564 j = 0;
2565 /* reta = 4-byte sliding window of
2566 * 0x00..(indices-1)(indices-1)00..etc. */
2567 reta = (reta << 8) | (j * 0x11);
2568 if ((i & 3) == 3)
2569 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2570 }
0cefafad 2571
05abb126
AD		 2572 /* Disable indicating checksum in descriptor, enables RSS hash */
2573 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2574 rxcsum |= IXGBE_RXCSUM_PCSD;
2575 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2576
8b1c0b24
JF		 2577 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2578 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2579 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2580 } else {
2581 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2582 | IXGBE_FLAG_SRIOV_ENABLED);
2583
2584 switch (mask) {
2585 case (IXGBE_FLAG_RSS_ENABLED):
2586 if (!tcs)
2587 mrqc = IXGBE_MRQC_RSSEN;
2588 else if (tcs <= 4)
2589 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2590 else
2591 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2592 break;
2593 case (IXGBE_FLAG_SRIOV_ENABLED):
2594 mrqc = IXGBE_MRQC_VMDQEN;
2595 break;
2596 default:
2597 break;
2598 }
0cefafad
JB		 2599 }
2600
05abb126
AD		 2601 /* Perform hash on these packet types */
2602 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2603 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2604 | IXGBE_MRQC_RSS_FIELD_IPV6
2605 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2606
2607 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2608}
2609
bb5a9ad2
NS		 2610/**
2611 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2612 * @adapter: address of board private structure
2613 * @index: index of ring to set
bb5a9ad2 2614 **/
082757af 2615static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2616 struct ixgbe_ring *ring)
bb5a9ad2 2617{
bb5a9ad2 2618 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2619 u32 rscctrl;
edd2ea55 2620 int rx_buf_len;
bf29ee6c 2621 u8 reg_idx = ring->reg_idx;
7367096a 2622
7d637bcc 2623 if (!ring_is_rsc_enabled(ring))
7367096a 2624 return;
bb5a9ad2 2625
7367096a
AD		 2626 rx_buf_len = ring->rx_buf_len;
2627 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2628 rscctrl |= IXGBE_RSCCTL_RSCEN;
2629 /*
2630 * we must limit the number of descriptors so that the
2631 * total size of max desc * buf_len is not greater
2632 * than 65535
2633 */
7d637bcc 2634 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2635#if (MAX_SKB_FRAGS > 16)
2636 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2637#elif (MAX_SKB_FRAGS > 8)
2638 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2639#elif (MAX_SKB_FRAGS > 4)
2640 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2641#else
2642 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2643#endif
2644 } else {
919e78a6 2645 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2646 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2647 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2648 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2649 else
2650 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2651 }
7367096a 2652 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2653}
2654
9e10e045
AD		 2655/**
2656 * ixgbe_set_uta - Set unicast filter table address
2657 * @adapter: board private structure
2658 *
2659 * The unicast table address is a register array of 32-bit registers.
2660 * The table is meant to be used in a way similar to how the MTA is used
2661 * however due to certain limitations in the hardware it is necessary to
2662 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2663 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2664 **/
2665static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2666{
2667 struct ixgbe_hw *hw = &adapter->hw;
2668 int i;
2669
2670 /* The UTA table only exists on 82599 hardware and newer */
2671 if (hw->mac.type < ixgbe_mac_82599EB)
2672 return;
2673
2674 /* we only need to do this if VMDq is enabled */
2675 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2676 return;
2677
2678 for (i = 0; i < 128; i++)
2679 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2680}
2681
2682#define IXGBE_MAX_RX_DESC_POLL 10
2683static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2684 struct ixgbe_ring *ring)
2685{
2686 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2687 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2688 u32 rxdctl;
bf29ee6c 2689 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2690
2691 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2692 if (hw->mac.type == ixgbe_mac_82598EB &&
2693 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2694 return;
2695
2696 do {
032b4325 2697 usleep_range(1000, 2000);
9e10e045
AD		 2698 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2699 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2700
2701 if (!wait_loop) {
2702 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2703 "the polling period\n", reg_idx);
2704 }
2705}
2706
2d39d576
YZ		 2707void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2708 struct ixgbe_ring *ring)
2709{
2710 struct ixgbe_hw *hw = &adapter->hw;
2711 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2712 u32 rxdctl;
2713 u8 reg_idx = ring->reg_idx;
2714
2715 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2716 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2717
2718 /* write value back with RXDCTL.ENABLE bit cleared */
2719 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2720
2721 if (hw->mac.type == ixgbe_mac_82598EB &&
2722 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2723 return;
2724
2725 /* the hardware may take up to 100us to really disable the rx queue */
2726 do {
2727 udelay(10);
2728 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2729 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2730
2731 if (!wait_loop) {
2732 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2733 "the polling period\n", reg_idx);
2734 }
2735}
2736
84418e3b
AD		 2737void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2738 struct ixgbe_ring *ring)
acd37177
AD		 2739{
2740 struct ixgbe_hw *hw = &adapter->hw;
2741 u64 rdba = ring->dma;
9e10e045 2742 u32 rxdctl;
bf29ee6c 2743 u8 reg_idx = ring->reg_idx;
acd37177 2744
9e10e045
AD		 2745 /* disable queue to avoid issues while updating state */
2746 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2747 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2748
acd37177
AD		 2749 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2750 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2751 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2752 ring->count * sizeof(union ixgbe_adv_rx_desc));
2753 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2754 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2755 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2756
2757 ixgbe_configure_srrctl(adapter, ring);
2758 ixgbe_configure_rscctl(adapter, ring);
2759
e9f98072
GR		 2760 /* If operating in IOV mode set RLPML for X540 */
2761 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2762 hw->mac.type == ixgbe_mac_X540) {
2763 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2764 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2765 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2766 }
2767
9e10e045
AD		 2768 if (hw->mac.type == ixgbe_mac_82598EB) {
2769 /*
2770 * enable cache line friendly hardware writes:
2771 * PTHRESH=32 descriptors (half the internal cache),
2772 * this also removes ugly rx_no_buffer_count increment
2773 * HTHRESH=4 descriptors (to minimize latency on fetch)
2774 * WTHRESH=8 burst writeback up to two cache lines
2775 */
2776 rxdctl &= ~0x3FFFFF;
2777 rxdctl |= 0x080420;
2778 }
2779
2780 /* enable receive descriptor ring */
2781 rxdctl |= IXGBE_RXDCTL_ENABLE;
2782 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2783
2784 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2785 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2786}
2787
48654521
AD		 2788static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2789{
2790 struct ixgbe_hw *hw = &adapter->hw;
2791 int p;
2792
2793 /* PSRTYPE must be initialized in non 82598 adapters */
2794 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2795 IXGBE_PSRTYPE_UDPHDR |
2796 IXGBE_PSRTYPE_IPV4HDR |
48654521 2797 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2798 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2799
2800 if (hw->mac.type == ixgbe_mac_82598EB)
2801 return;
2802
2803 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2804 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2805
2806 for (p = 0; p < adapter->num_rx_pools; p++)
2807 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2808 psrtype);
2809}
2810
f5b4a52e
AD		 2811static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2812{
2813 struct ixgbe_hw *hw = &adapter->hw;
2814 u32 gcr_ext;
2815 u32 vt_reg_bits;
2816 u32 reg_offset, vf_shift;
2817 u32 vmdctl;
2818
2819 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2820 return;
2821
2822 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2823 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2824 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2825 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2826
2827 vf_shift = adapter->num_vfs % 32;
2828 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2829
2830 /* Enable only the PF's pool for Tx/Rx */
2831 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2832 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2833 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2834 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2835 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2836
2837 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2838 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2839
2840 /*
2841 * Set up VF register offsets for selected VT Mode,
2842 * i.e. 32 or 64 VFs for SR-IOV
2843 */
2844 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2845 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2846 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2847 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2848
2849 /* enable Tx loopback for VF/PF communication */
2850 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2851 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 2852 hw->mac.ops.set_mac_anti_spoofing(hw,
2853 (adapter->antispoofing_enabled =
2854 (adapter->num_vfs != 0)),
a985b6c3 2855 adapter->num_vfs);
f5b4a52e
AD		 2856}
2857
477de6ed 2858static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2859{
9a799d71
AK		 2860 struct ixgbe_hw *hw = &adapter->hw;
2861 struct net_device *netdev = adapter->netdev;
2862 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2863 int rx_buf_len;
477de6ed
AD		 2864 struct ixgbe_ring *rx_ring;
2865 int i;
2866 u32 mhadd, hlreg0;
48654521 2867
9a799d71 2868 /* Decide whether to use packet split mode or not */
a124339a
DS		 2869 /* On by default */
2870 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2871
1cdd1ec8 2872 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2873 if (adapter->num_vfs)
2874 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2875
2876 /* Disable packet split due to 82599 erratum #45 */
2877 if (hw->mac.type == ixgbe_mac_82599EB)
2878 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2879
63f39bd1 2880#ifdef IXGBE_FCOE
477de6ed
AD		 2881 /* adjust max frame to be able to do baby jumbo for FCoE */
2882 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2883 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2884 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2885
477de6ed
AD		 2886#endif /* IXGBE_FCOE */
2887 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2888 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2889 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2890 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2891
2892 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2893 }
2894
919e78a6
AD		 2895 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2896 max_frame += VLAN_HLEN;
2897
2898 /* Set the RX buffer length according to the mode */
2899 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2900 rx_buf_len = IXGBE_RX_HDR_SIZE;
2901 } else {
2902 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2903 (netdev->mtu <= ETH_DATA_LEN))
2904 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2905 /*
2906 * Make best use of allocation by using all but 1K of a
2907 * power of 2 allocation that will be used for skb->head.
2908 */
2909 else if (max_frame <= IXGBE_RXBUFFER_3K)
2910 rx_buf_len = IXGBE_RXBUFFER_3K;
2911 else if (max_frame <= IXGBE_RXBUFFER_7K)
2912 rx_buf_len = IXGBE_RXBUFFER_7K;
2913 else if (max_frame <= IXGBE_RXBUFFER_15K)
2914 rx_buf_len = IXGBE_RXBUFFER_15K;
2915 else
2916 rx_buf_len = IXGBE_MAX_RXBUFFER;
2917 }
2918
477de6ed
AD		 2919 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2920 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2921 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2922 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2923
0cefafad
JB		 2924 /*
2925 * Setup the HW Rx Head and Tail Descriptor Pointers and
2926 * the Base and Length of the Rx Descriptor Ring
2927 */
9a799d71 2928 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2929 rx_ring = adapter->rx_ring[i];
a6616b42 2930 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2931
6e455b89 2932 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2933 set_ring_ps_enabled(rx_ring);
2934 else
2935 clear_ring_ps_enabled(rx_ring);
2936
2937 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2938 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2939 else
7d637bcc 2940 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2941
63f39bd1 2942#ifdef IXGBE_FCOE
e8e9f696 2943 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2944 struct ixgbe_ring_feature *f;
2945 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2946 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2947 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2948 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2949 rx_ring->rx_buf_len =
e8e9f696 2950 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2951 } else if (!ring_is_rsc_enabled(rx_ring) &&
2952 !ring_is_ps_enabled(rx_ring)) {
2953 rx_ring->rx_buf_len =
2954 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2955 }
63f39bd1 2956 }
63f39bd1 2957#endif /* IXGBE_FCOE */
477de6ed 2958 }
477de6ed
AD		 2959}
2960
7367096a
AD		 2961static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2962{
2963 struct ixgbe_hw *hw = &adapter->hw;
2964 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2965
2966 switch (hw->mac.type) {
2967 case ixgbe_mac_82598EB:
2968 /*
2969 * For VMDq support of different descriptor types or
2970 * buffer sizes through the use of multiple SRRCTL
2971 * registers, RDRXCTL.MVMEN must be set to 1
2972 *
2973 * also, the manual doesn't mention it clearly but DCA hints
2974 * will only use queue 0's tags unless this bit is set. Side
2975 * effects of setting this bit are only that SRRCTL must be
2976 * fully programmed [0..15]
2977 */
2978 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2979 break;
2980 case ixgbe_mac_82599EB:
b93a2226 2981 case ixgbe_mac_X540:
7367096a
AD		 2982 /* Disable RSC for ACK packets */
2983 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2984 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2985 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2986 /* hardware requires some bits to be set by default */
2987 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2988 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2989 break;
2990 default:
2991 /* We should do nothing since we don't know this hardware */
2992 return;
2993 }
2994
2995 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2996}
2997
477de6ed
AD		 2998/**
2999 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3000 * @adapter: board private structure
3001 *
3002 * Configure the Rx unit of the MAC after a reset.
3003 **/
3004static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3005{
3006 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3007 int i;
3008 u32 rxctrl;
477de6ed
AD		 3009
3010 /* disable receives while setting up the descriptors */
3011 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3012 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3013
3014 ixgbe_setup_psrtype(adapter);
7367096a 3015 ixgbe_setup_rdrxctl(adapter);
477de6ed 3016
9e10e045 3017 /* Program registers for the distribution of queues */
f5b4a52e 3018 ixgbe_setup_mrqc(adapter);
f5b4a52e 3019
9e10e045
AD		 3020 ixgbe_set_uta(adapter);
3021
477de6ed
AD		 3022 /* set_rx_buffer_len must be called before ring initialization */
3023 ixgbe_set_rx_buffer_len(adapter);
3024
3025 /*
3026 * Setup the HW Rx Head and Tail Descriptor Pointers and
3027 * the Base and Length of the Rx Descriptor Ring
3028 */
9e10e045
AD		 3029 for (i = 0; i < adapter->num_rx_queues; i++)
3030 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3031
9e10e045
AD		 3032 /* disable drop enable for 82598 parts */
3033 if (hw->mac.type == ixgbe_mac_82598EB)
3034 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3035
3036 /* enable all receives */
3037 rxctrl |= IXGBE_RXCTRL_RXEN;
3038 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3039}
3040
068c89b0
DS		 3041static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3042{
3043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3044 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3045 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3046
3047 /* add VID to filter table */
1ada1b1b 3048 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3049 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3050}
3051
3052static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3053{
3054 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3055 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3056 int pool_ndx = adapter->num_vfs;
068c89b0 3057
068c89b0 3058 /* remove VID from filter table */
1ada1b1b 3059 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3060 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3061}
3062
5f6c0181
JB		 3063/**
3064 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3065 * @adapter: driver data
3066 */
3067static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3068{
3069 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3070 u32 vlnctrl;
3071
3072 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3073 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3074 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3075}
3076
3077/**
3078 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3079 * @adapter: driver data
3080 */
3081static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3082{
3083 struct ixgbe_hw *hw = &adapter->hw;
3084 u32 vlnctrl;
3085
3086 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3087 vlnctrl |= IXGBE_VLNCTRL_VFE;
3088 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3089 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3090}
3091
3092/**
3093 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3094 * @adapter: driver data
3095 */
3096static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3097{
3098 struct ixgbe_hw *hw = &adapter->hw;
3099 u32 vlnctrl;
5f6c0181
JB		 3100 int i, j;
3101
3102 switch (hw->mac.type) {
3103 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3104 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3105 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3106 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3107 break;
3108 case ixgbe_mac_82599EB:
b93a2226 3109 case ixgbe_mac_X540:
5f6c0181
JB		 3110 for (i = 0; i < adapter->num_rx_queues; i++) {
3111 j = adapter->rx_ring[i]->reg_idx;
3112 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3113 vlnctrl &= ~IXGBE_RXDCTL_VME;
3114 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3115 }
3116 break;
3117 default:
3118 break;
3119 }
3120}
3121
3122/**
f62bbb5e 3123 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3124 * @adapter: driver data
3125 */
f62bbb5e 3126static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3127{
3128 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3129 u32 vlnctrl;
5f6c0181
JB		 3130 int i, j;
3131
3132 switch (hw->mac.type) {
3133 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3134 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3135 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3136 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3137 break;
3138 case ixgbe_mac_82599EB:
b93a2226 3139 case ixgbe_mac_X540:
5f6c0181
JB		 3140 for (i = 0; i < adapter->num_rx_queues; i++) {
3141 j = adapter->rx_ring[i]->reg_idx;
3142 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3143 vlnctrl |= IXGBE_RXDCTL_VME;
3144 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3145 }
3146 break;
3147 default:
3148 break;
3149 }
3150}
3151
9a799d71
AK		 3152static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3153{
f62bbb5e 3154 u16 vid;
9a799d71 3155
f62bbb5e
JG		 3156 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3157
3158 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3159 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3160}
3161
2850062a
AD		 3162/**
3163 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3164 * @netdev: network interface device structure
3165 *
3166 * Writes unicast address list to the RAR table.
3167 * Returns: -ENOMEM on failure/insufficient address space
3168 * 0 on no addresses written
3169 * X on writing X addresses to the RAR table
3170 **/
3171static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3172{
3173 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3174 struct ixgbe_hw *hw = &adapter->hw;
3175 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3176 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3177 int count = 0;
3178
3179 /* return ENOMEM indicating insufficient memory for addresses */
3180 if (netdev_uc_count(netdev) > rar_entries)
3181 return -ENOMEM;
3182
3183 if (!netdev_uc_empty(netdev) && rar_entries) {
3184 struct netdev_hw_addr *ha;
3185 /* return error if we do not support writing to RAR table */
3186 if (!hw->mac.ops.set_rar)
3187 return -ENOMEM;
3188
3189 netdev_for_each_uc_addr(ha, netdev) {
3190 if (!rar_entries)
3191 break;
3192 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3193 vfn, IXGBE_RAH_AV);
3194 count++;
3195 }
3196 }
3197 /* write the addresses in reverse order to avoid write combining */
3198 for (; rar_entries > 0 ; rar_entries--)
3199 hw->mac.ops.clear_rar(hw, rar_entries);
3200
3201 return count;
3202}
3203
9a799d71 3204/**
2c5645cf 3205 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3206 * @netdev: network interface device structure
3207 *
2c5645cf
CL		 3208 * The set_rx_method entry point is called whenever the unicast/multicast
3209 * address list or the network interface flags are updated. This routine is
3210 * responsible for configuring the hardware for proper unicast, multicast and
3211 * promiscuous mode.
9a799d71 3212 **/
7f870475 3213void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3214{
3215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3216 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3217 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3218 int count;
9a799d71
AK		 3219
3220 /* Check for Promiscuous and All Multicast modes */
3221
3222 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3223
f5dc442b
AD		 3224 /* set all bits that we expect to always be set */
3225 fctrl |= IXGBE_FCTRL_BAM;
3226 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3227 fctrl |= IXGBE_FCTRL_PMCF;
3228
2850062a
AD		 3229 /* clear the bits we are changing the status of */
3230 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3231
9a799d71 3232 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3233 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3234 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3235 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3236 /* don't hardware filter vlans in promisc mode */
3237 ixgbe_vlan_filter_disable(adapter);
9a799d71 3238 } else {
746b9f02
PM		 3239 if (netdev->flags & IFF_ALLMULTI) {
3240 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3241 vmolr |= IXGBE_VMOLR_MPE;
3242 } else {
3243 /*
3244 * Write addresses to the MTA, if the attempt fails
25985edc 3245 * then we should just turn on promiscuous mode so
2850062a
AD		 3246 * that we can at least receive multicast traffic
3247 */
3248 hw->mac.ops.update_mc_addr_list(hw, netdev);
3249 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3250 }
5f6c0181 3251 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3252 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3253 /*
3254 * Write addresses to available RAR registers, if there is not
3255 * sufficient space to store all the addresses then enable
25985edc 3256 * unicast promiscuous mode
2850062a
AD		 3257 */
3258 count = ixgbe_write_uc_addr_list(netdev);
3259 if (count < 0) {
3260 fctrl |= IXGBE_FCTRL_UPE;
3261 vmolr |= IXGBE_VMOLR_ROPE;
3262 }
9a799d71
AK		 3263 }
3264
2850062a 3265 if (adapter->num_vfs) {
1cdd1ec8 3266 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3267 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3268 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3269 IXGBE_VMOLR_ROPE);
3270 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3271 }
3272
3273 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3274
3275 if (netdev->features & NETIF_F_HW_VLAN_RX)
3276 ixgbe_vlan_strip_enable(adapter);
3277 else
3278 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3279}
3280
021230d4
AV		 3281static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3282{
3283 int q_idx;
3284 struct ixgbe_q_vector *q_vector;
3285 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3286
3287 /* legacy and MSI only use one vector */
3288 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3289 q_vectors = 1;
3290
3291 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3292 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3293 napi_enable(&q_vector->napi);
021230d4
AV		 3294 }
3295}
3296
3297static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3298{
3299 int q_idx;
3300 struct ixgbe_q_vector *q_vector;
3301 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3302
3303 /* legacy and MSI only use one vector */
3304 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3305 q_vectors = 1;
3306
3307 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3308 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3309 napi_disable(&q_vector->napi);
3310 }
3311}
3312
7a6b6f51 3313#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3314/*
3315 * ixgbe_configure_dcb - Configure DCB hardware
3316 * @adapter: ixgbe adapter struct
3317 *
3318 * This is called by the driver on open to configure the DCB hardware.
3319 * This is also called by the gennetlink interface when reconfiguring
3320 * the DCB state.
3321 */
3322static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3323{
3324 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3325 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3326
67ebd791
AD		 3327 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3328 if (hw->mac.type == ixgbe_mac_82598EB)
3329 netif_set_gso_max_size(adapter->netdev, 65536);
3330 return;
3331 }
3332
3333 if (hw->mac.type == ixgbe_mac_82598EB)
3334 netif_set_gso_max_size(adapter->netdev, 32768);
3335
2f90b865 3336
2f90b865 3337 /* Enable VLAN tag insert/strip */
f62bbb5e 3338 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3339
2f90b865 3340 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3341
3342 /* reconfigure the hardware */
6f70f6ac 3343 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
971060b1 3344#ifdef IXGBE_FCOE
c27931da
JF		 3345 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3346 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3347#endif
3348 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3349 DCB_TX_CONFIG);
3350 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3351 DCB_RX_CONFIG);
3352 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3353 } else {
3354 struct net_device *dev = adapter->netdev;
3355
4c09f3a0
JF		 3356 if (adapter->ixgbe_ieee_ets) {
3357 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
3358 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3359
3360 ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
3361 }
3362
3363 if (adapter->ixgbe_ieee_pfc) {
3364 struct ieee_pfc *pfc = adapter->ixgbe_ieee_pfc;
3365
3366 ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc->pfc_en);
3367 }
c27931da 3368 }
8187cd48
JF		 3369
3370 /* Enable RSS Hash per TC */
3371 if (hw->mac.type != ixgbe_mac_82598EB) {
3372 int i;
3373 u32 reg = 0;
3374
3375 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3376 u8 msb = 0;
3377 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3378
3379 while (cnt >>= 1)
3380 msb++;
3381
3382 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3383 }
3384 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3385 }
2f90b865 3386}
9da712d2
JF		 3387#endif
3388
3389/* Additional bittime to account for IXGBE framing */
3390#define IXGBE_ETH_FRAMING 20
3391
3392/*
3393 * ixgbe_hpbthresh - calculate high water mark for flow control
3394 *
3395 * @adapter: board private structure to calculate for
3396 * @pb - packet buffer to calculate
3397 */
3398static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3399{
3400 struct ixgbe_hw *hw = &adapter->hw;
3401 struct net_device *dev = adapter->netdev;
3402 int link, tc, kb, marker;
3403 u32 dv_id, rx_pba;
3404
3405 /* Calculate max LAN frame size */
3406 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3407
3408#ifdef IXGBE_FCOE
3409 /* FCoE traffic class uses FCOE jumbo frames */
3410 if (dev->features & NETIF_F_FCOE_MTU) {
3411 int fcoe_pb = 0;
2f90b865 3412
9da712d2
JF		 3413#ifdef CONFIG_IXGBE_DCB
3414 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3415
3416#endif
3417 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3418 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3419 }
2f90b865 3420#endif
80605c65 3421
9da712d2
JF		 3422 /* Calculate delay value for device */
3423 switch (hw->mac.type) {
3424 case ixgbe_mac_X540:
3425 dv_id = IXGBE_DV_X540(link, tc);
3426 break;
3427 default:
3428 dv_id = IXGBE_DV(link, tc);
3429 break;
3430 }
3431
3432 /* Loopback switch introduces additional latency */
3433 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3434 dv_id += IXGBE_B2BT(tc);
3435
3436 /* Delay value is calculated in bit times convert to KB */
3437 kb = IXGBE_BT2KB(dv_id);
3438 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3439
3440 marker = rx_pba - kb;
3441
3442 /* It is possible that the packet buffer is not large enough
3443 * to provide required headroom. In this case throw an error
3444 * to user and a do the best we can.
3445 */
3446 if (marker < 0) {
3447 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3448 "headroom to support flow control."
3449 "Decrease MTU or number of traffic classes\n", pb);
3450 marker = tc + 1;
3451 }
3452
3453 return marker;
3454}
3455
3456/*
3457 * ixgbe_lpbthresh - calculate low water mark for for flow control
3458 *
3459 * @adapter: board private structure to calculate for
3460 * @pb - packet buffer to calculate
3461 */
3462static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3463{
3464 struct ixgbe_hw *hw = &adapter->hw;
3465 struct net_device *dev = adapter->netdev;
3466 int tc;
3467 u32 dv_id;
3468
3469 /* Calculate max LAN frame size */
3470 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3471
3472 /* Calculate delay value for device */
3473 switch (hw->mac.type) {
3474 case ixgbe_mac_X540:
3475 dv_id = IXGBE_LOW_DV_X540(tc);
3476 break;
3477 default:
3478 dv_id = IXGBE_LOW_DV(tc);
3479 break;
3480 }
3481
3482 /* Delay value is calculated in bit times convert to KB */
3483 return IXGBE_BT2KB(dv_id);
3484}
3485
3486/*
3487 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3488 */
3489static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3490{
3491 struct ixgbe_hw *hw = &adapter->hw;
3492 int num_tc = netdev_get_num_tc(adapter->netdev);
3493 int i;
3494
3495 if (!num_tc)
3496 num_tc = 1;
3497
3498 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3499
3500 for (i = 0; i < num_tc; i++) {
3501 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3502
3503 /* Low water marks must not be larger than high water marks */
3504 if (hw->fc.low_water > hw->fc.high_water[i])
3505 hw->fc.low_water = 0;
3506 }
3507}
3508
80605c65
JF		 3509static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3510{
80605c65 3511 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3512 int hdrm;
3513 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3514
3515 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3516 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3517 hdrm = 32 << adapter->fdir_pballoc;
3518 else
3519 hdrm = 0;
80605c65 3520
f7e1027f 3521 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3522 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3523}
3524
e4911d57
AD		 3525static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3526{
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 struct hlist_node *node, *node2;
3529 struct ixgbe_fdir_filter *filter;
3530
3531 spin_lock(&adapter->fdir_perfect_lock);
3532
3533 if (!hlist_empty(&adapter->fdir_filter_list))
3534 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3535
3536 hlist_for_each_entry_safe(filter, node, node2,
3537 &adapter->fdir_filter_list, fdir_node) {
3538 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3539 &filter->filter,
3540 filter->sw_idx,
3541 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3542 IXGBE_FDIR_DROP_QUEUE :
3543 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3544 }
3545
3546 spin_unlock(&adapter->fdir_perfect_lock);
3547}
3548
9a799d71
AK		 3549static void ixgbe_configure(struct ixgbe_adapter *adapter)
3550{
80605c65 3551 ixgbe_configure_pb(adapter);
7a6b6f51 3552#ifdef CONFIG_IXGBE_DCB
67ebd791 3553 ixgbe_configure_dcb(adapter);
2f90b865 3554#endif
9a799d71 3555
4c1d7b4b 3556 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3557 ixgbe_restore_vlan(adapter);
3558
eacd73f7
YZ		 3559#ifdef IXGBE_FCOE
3560 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3561 ixgbe_configure_fcoe(adapter);
3562
3563#endif /* IXGBE_FCOE */
c4cf55e5 3564 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3565 ixgbe_init_fdir_signature_82599(&adapter->hw,
3566 adapter->fdir_pballoc);
e4911d57
AD		 3567 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3568 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3569 adapter->fdir_pballoc);
3570 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3571 }
4c1d7b4b 3572
933d41f1 3573 ixgbe_configure_virtualization(adapter);
c4cf55e5 3574
9a799d71
AK		 3575 ixgbe_configure_tx(adapter);
3576 ixgbe_configure_rx(adapter);
9a799d71
AK		 3577}
3578
e8e26350
PW		 3579static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3580{
3581 switch (hw->phy.type) {
3582 case ixgbe_phy_sfp_avago:
3583 case ixgbe_phy_sfp_ftl:
3584 case ixgbe_phy_sfp_intel:
3585 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3586 case ixgbe_phy_sfp_passive_tyco:
3587 case ixgbe_phy_sfp_passive_unknown:
3588 case ixgbe_phy_sfp_active_unknown:
3589 case ixgbe_phy_sfp_ftl_active:
e8e26350 3590 return true;
8917b447
AD		 3591 case ixgbe_phy_nl:
3592 if (hw->mac.type == ixgbe_mac_82598EB)
3593 return true;
e8e26350
PW		 3594 default:
3595 return false;
3596 }
3597}
3598
0ecc061d 3599/**
e8e26350
PW		 3600 * ixgbe_sfp_link_config - set up SFP+ link
3601 * @adapter: pointer to private adapter struct
3602 **/
3603static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3604{
7086400d
AD		 3605 /*
3606 * We are assuming the worst case scenerio here, and that
3607 * is that an SFP was inserted/removed after the reset
3608 * but before SFP detection was enabled. As such the best
3609 * solution is to just start searching as soon as we start
3610 */
3611 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3612 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3613
7086400d 3614 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3615}
3616
3617/**
3618 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3619 * @hw: pointer to private hardware struct
3620 *
3621 * Returns 0 on success, negative on failure
3622 **/
e8e26350 3623static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3624{
3625 u32 autoneg;
8620a103 3626 bool negotiation, link_up = false;
0ecc061d
PWJ		 3627 u32 ret = IXGBE_ERR_LINK_SETUP;
3628
3629 if (hw->mac.ops.check_link)
3630 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3631
3632 if (ret)
3633 goto link_cfg_out;
3634
0b0c2b31
ET		 3635 autoneg = hw->phy.autoneg_advertised;
3636 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3637 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3638 &negotiation);
0ecc061d
PWJ		 3639 if (ret)
3640 goto link_cfg_out;
3641
8620a103
MC		 3642 if (hw->mac.ops.setup_link)
3643 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3644link_cfg_out:
3645 return ret;
3646}
3647
a34bcfff 3648static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3649{
9a799d71 3650 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3651 u32 gpie = 0;
9a799d71 3652
9b471446 3653 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3654 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3655 IXGBE_GPIE_OCD;
3656 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3657 /*
3658 * use EIAM to auto-mask when MSI-X interrupt is asserted
3659 * this saves a register write for every interrupt
3660 */
3661 switch (hw->mac.type) {
3662 case ixgbe_mac_82598EB:
3663 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3664 break;
9b471446 3665 case ixgbe_mac_82599EB:
b93a2226
DS		 3666 case ixgbe_mac_X540:
3667 default:
9b471446
JB		 3668 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3669 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3670 break;
3671 }
3672 } else {
021230d4
AV		 3673 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3674 * specifically only auto mask tx and rx interrupts */
3675 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3676 }
9a799d71 3677
a34bcfff
AD		 3678 /* XXX: to interrupt immediately for EICS writes, enable this */
3679 /* gpie |= IXGBE_GPIE_EIMEN; */
3680
3681 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3682 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3683 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3684 }
3685
5fdd31f9 3686 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3687 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3688 switch (adapter->hw.mac.type) {
3689 case ixgbe_mac_82599EB:
3690 gpie |= IXGBE_SDP0_GPIEN;
3691 break;
3692 case ixgbe_mac_X540:
3693 gpie |= IXGBE_EIMS_TS;
3694 break;
3695 default:
3696 break;
3697 }
3698 }
5fdd31f9 3699
a34bcfff
AD		 3700 /* Enable fan failure interrupt */
3701 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3702 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3703
2698b208 3704 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3705 gpie |= IXGBE_SDP1_GPIEN;
3706 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3707 }
a34bcfff
AD		 3708
3709 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3710}
3711
c7ccde0f 3712static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3713{
3714 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3715 int err;
a34bcfff
AD		 3716 u32 ctrl_ext;
3717
3718 ixgbe_get_hw_control(adapter);
3719 ixgbe_setup_gpie(adapter);
e8e26350 3720
9a799d71
AK		 3721 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3722 ixgbe_configure_msix(adapter);
3723 else
3724 ixgbe_configure_msi_and_legacy(adapter);
3725
c6ecf39a
DS		 3726 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3727 if (hw->mac.ops.enable_tx_laser &&
3728 ((hw->phy.multispeed_fiber) ||
9f911707 3729 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3730 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3731 hw->mac.ops.enable_tx_laser(hw);
3732
9a799d71 3733 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3734 ixgbe_napi_enable_all(adapter);
3735
73c4b7cd
AD		 3736 if (ixgbe_is_sfp(hw)) {
3737 ixgbe_sfp_link_config(adapter);
3738 } else {
3739 err = ixgbe_non_sfp_link_config(hw);
3740 if (err)
3741 e_err(probe, "link_config FAILED %d\n", err);
3742 }
3743
021230d4
AV		 3744 /* clear any pending interrupts, may auto mask */
3745 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3746 ixgbe_irq_enable(adapter, true, true);
9a799d71 3747
bf069c97
DS		 3748 /*
3749 * If this adapter has a fan, check to see if we had a failure
3750 * before we enabled the interrupt.
3751 */
3752 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3753 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3754 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3755 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3756 }
3757
1da100bb 3758 /* enable transmits */
477de6ed 3759 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3760
9a799d71
AK		 3761 /* bring the link up in the watchdog, this could race with our first
3762 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3763 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3764 adapter->link_check_timeout = jiffies;
7086400d 3765 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3766
3767 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3768 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3769 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3770 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3771}
3772
d4f80882
AV		 3773void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3774{
3775 WARN_ON(in_interrupt());
7086400d
AD		 3776 /* put off any impending NetWatchDogTimeout */
3777 adapter->netdev->trans_start = jiffies;
3778
d4f80882 3779 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3780 usleep_range(1000, 2000);
d4f80882 3781 ixgbe_down(adapter);
5809a1ae
GR		 3782 /*
3783 * If SR-IOV enabled then wait a bit before bringing the adapter
3784 * back up to give the VFs time to respond to the reset. The
3785 * two second wait is based upon the watchdog timer cycle in
3786 * the VF driver.
3787 */
3788 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3789 msleep(2000);
d4f80882
AV		 3790 ixgbe_up(adapter);
3791 clear_bit(__IXGBE_RESETTING, &adapter->state);
3792}
3793
c7ccde0f 3794void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3795{
3796 /* hardware has been reset, we need to reload some things */
3797 ixgbe_configure(adapter);
3798
c7ccde0f 3799 ixgbe_up_complete(adapter);
9a799d71
AK		 3800}
3801
3802void ixgbe_reset(struct ixgbe_adapter *adapter)
3803{
c44ade9e 3804 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3805 int err;
3806
7086400d
AD		 3807 /* lock SFP init bit to prevent race conditions with the watchdog */
3808 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3809 usleep_range(1000, 2000);
3810
3811 /* clear all SFP and link config related flags while holding SFP_INIT */
3812 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3813 IXGBE_FLAG2_SFP_NEEDS_RESET);
3814 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3815
8ca783ab 3816 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3817 switch (err) {
3818 case 0:
3819 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3820 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3821 break;
3822 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3823 e_dev_err("master disable timed out\n");
da4dd0f7 3824 break;
794caeb2
PWJ		 3825 case IXGBE_ERR_EEPROM_VERSION:
3826 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3827 e_dev_warn("This device is a pre-production adapter/LOM. "
3828 "Please be aware there may be issuesassociated with "
3829 "your hardware. If you are experiencing problems "
3830 "please contact your Intel or hardware "
3831 "representative who provided you with this "
3832 "hardware.\n");
794caeb2 3833 break;
da4dd0f7 3834 default:
849c4542 3835 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3836 }
9a799d71 3837
7086400d
AD		 3838 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3839
9a799d71 3840 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3841 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3842 IXGBE_RAH_AV);
9a799d71
AK		 3843}
3844
9a799d71
AK		 3845/**
3846 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3847 * @rx_ring: ring to free buffers from
3848 **/
b6ec895e 3849static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3850{
b6ec895e 3851 struct device *dev = rx_ring->dev;
9a799d71 3852 unsigned long size;
b6ec895e 3853 u16 i;
9a799d71 3854
84418e3b
AD		 3855 /* ring already cleared, nothing to do */
3856 if (!rx_ring->rx_buffer_info)
3857 return;
9a799d71 3858
84418e3b 3859 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3860 for (i = 0; i < rx_ring->count; i++) {
3861 struct ixgbe_rx_buffer *rx_buffer_info;
3862
3863 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3864 if (rx_buffer_info->dma) {
b6ec895e 3865 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3866 rx_ring->rx_buf_len,
1b507730 3867 DMA_FROM_DEVICE);
9a799d71
AK		 3868 rx_buffer_info->dma = 0;
3869 }
3870 if (rx_buffer_info->skb) {
f8212f97 3871 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3872 rx_buffer_info->skb = NULL;
f8212f97
AD		 3873 do {
3874 struct sk_buff *this = skb;
e8171aaa 3875 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3876 dma_unmap_single(dev,
1b507730 3877 IXGBE_RSC_CB(this)->dma,
e8e9f696 3878 rx_ring->rx_buf_len,
1b507730 3879 DMA_FROM_DEVICE);
fd3686a8 3880 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3881 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3882 }
f8212f97
AD		 3883 skb = skb->prev;
3884 dev_kfree_skb(this);
3885 } while (skb);
9a799d71
AK		 3886 }
3887 if (!rx_buffer_info->page)
3888 continue;
4f57ca6e 3889 if (rx_buffer_info->page_dma) {
b6ec895e 3890 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3891 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3892 rx_buffer_info->page_dma = 0;
3893 }
9a799d71
AK		 3894 put_page(rx_buffer_info->page);
3895 rx_buffer_info->page = NULL;
762f4c57 3896 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3897 }
3898
3899 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3900 memset(rx_ring->rx_buffer_info, 0, size);
3901
3902 /* Zero out the descriptor ring */
3903 memset(rx_ring->desc, 0, rx_ring->size);
3904
3905 rx_ring->next_to_clean = 0;
3906 rx_ring->next_to_use = 0;
9a799d71
AK		 3907}
3908
3909/**
3910 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3911 * @tx_ring: ring to be cleaned
3912 **/
b6ec895e 3913static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3914{
3915 struct ixgbe_tx_buffer *tx_buffer_info;
3916 unsigned long size;
b6ec895e 3917 u16 i;
9a799d71 3918
84418e3b
AD		 3919 /* ring already cleared, nothing to do */
3920 if (!tx_ring->tx_buffer_info)
3921 return;
9a799d71 3922
84418e3b 3923 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3924 for (i = 0; i < tx_ring->count; i++) {
3925 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3926 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3927 }
3928
3929 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3930 memset(tx_ring->tx_buffer_info, 0, size);
3931
3932 /* Zero out the descriptor ring */
3933 memset(tx_ring->desc, 0, tx_ring->size);
3934
3935 tx_ring->next_to_use = 0;
3936 tx_ring->next_to_clean = 0;
9a799d71
AK		 3937}
3938
3939/**
021230d4 3940 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3941 * @adapter: board private structure
3942 **/
021230d4 3943static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3944{
3945 int i;
3946
021230d4 3947 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3948 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3949}
3950
3951/**
021230d4 3952 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3953 * @adapter: board private structure
3954 **/
021230d4 3955static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3956{
3957 int i;
3958
021230d4 3959 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3960 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3961}
3962
e4911d57
AD		 3963static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3964{
3965 struct hlist_node *node, *node2;
3966 struct ixgbe_fdir_filter *filter;
3967
3968 spin_lock(&adapter->fdir_perfect_lock);
3969
3970 hlist_for_each_entry_safe(filter, node, node2,
3971 &adapter->fdir_filter_list, fdir_node) {
3972 hlist_del(&filter->fdir_node);
3973 kfree(filter);
3974 }
3975 adapter->fdir_filter_count = 0;
3976
3977 spin_unlock(&adapter->fdir_perfect_lock);
3978}
3979
9a799d71
AK		 3980void ixgbe_down(struct ixgbe_adapter *adapter)
3981{
3982 struct net_device *netdev = adapter->netdev;
7f821875 3983 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3984 u32 rxctrl;
bf29ee6c 3985 int i;
9a799d71
AK		 3986
3987 /* signal that we are down to the interrupt handler */
3988 set_bit(__IXGBE_DOWN, &adapter->state);
3989
3990 /* disable receives */
7f821875
JB		 3991 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3992 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3993
2d39d576
YZ		 3994 /* disable all enabled rx queues */
3995 for (i = 0; i < adapter->num_rx_queues; i++)
3996 /* this call also flushes the previous write */
3997 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3998
032b4325 3999 usleep_range(10000, 20000);
9a799d71 4000
7f821875
JB		 4001 netif_tx_stop_all_queues(netdev);
4002
7086400d 4003 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4004 netif_carrier_off(netdev);
4005 netif_tx_disable(netdev);
4006
4007 ixgbe_irq_disable(adapter);
4008
4009 ixgbe_napi_disable_all(adapter);
4010
d034acf1
AD		 4011 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4012 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4013 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4014
4015 del_timer_sync(&adapter->service_timer);
4016
34cecbbf 4017 if (adapter->num_vfs) {
8e34d1aa
AD		 4018 /* Clear EITR Select mapping */
4019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4020
4021 /* Mark all the VFs as inactive */
4022 for (i = 0 ; i < adapter->num_vfs; i++)
4023 adapter->vfinfo[i].clear_to_send = 0;
34cecbbf 4024
34cecbbf
AD		 4025 /* ping all the active vfs to let them know we are going down */
4026 ixgbe_ping_all_vfs(adapter);
4027
4028 /* Disable all VFTE/VFRE TX/RX */
4029 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4030 }
4031
7f821875
JB		 4032 /* disable transmits in the hardware now that interrupts are off */
4033 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4034 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4035 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4036 }
34cecbbf
AD		 4037
4038 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4039 switch (hw->mac.type) {
4040 case ixgbe_mac_82599EB:
b93a2226 4041 case ixgbe_mac_X540:
88512539 4042 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4043 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4044 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4045 break;
4046 default:
4047 break;
4048 }
7f821875 4049
6f4a0e45
PL		 4050 if (!pci_channel_offline(adapter->pdev))
4051 ixgbe_reset(adapter);
c6ecf39a
DS		 4052
4053 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4054 if (hw->mac.ops.disable_tx_laser &&
4055 ((hw->phy.multispeed_fiber) ||
9f911707 4056 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4057 (hw->mac.type == ixgbe_mac_82599EB))))
4058 hw->mac.ops.disable_tx_laser(hw);
4059
9a799d71
AK		 4060 ixgbe_clean_all_tx_rings(adapter);
4061 ixgbe_clean_all_rx_rings(adapter);
4062
5dd2d332 4063#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4064 /* since we reset the hardware DCA settings were cleared */
e35ec126 4065 ixgbe_setup_dca(adapter);
96b0e0f6 4066#endif
9a799d71
AK		 4067}
4068
9a799d71 4069/**
021230d4
AV		 4070 * ixgbe_poll - NAPI Rx polling callback
4071 * @napi: structure for representing this polling device
4072 * @budget: how many packets driver is allowed to clean
4073 *
4074 * This function is used for legacy and MSI, NAPI mode
9a799d71 4075 **/
021230d4 4076static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4077{
9a1a69ad 4078 struct ixgbe_q_vector *q_vector =
e8e9f696 4079 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4080 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4081 struct ixgbe_ring *ring;
4082 int per_ring_budget;
4083 bool clean_complete = true;
9a799d71 4084
5dd2d332 4085#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4087 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4088#endif
4089
4ff7fb12
AD		 4090 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4091 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4092
4ff7fb12
AD		 4093 /* attempt to distribute budget to each queue fairly, but don't allow
4094 * the budget to go below 1 because we'll exit polling */
4095 if (q_vector->rx.count > 1)
4096 per_ring_budget = max(budget/q_vector->rx.count, 1);
4097 else
4098 per_ring_budget = budget;
d2c7ddd6 4099
4ff7fb12
AD		 4100 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4101 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4102 per_ring_budget);
4103
4104 /* If all work not completed, return budget and keep polling */
4105 if (!clean_complete)
4106 return budget;
4107
4108 /* all work done, exit the polling mode */
4109 napi_complete(napi);
4110 if (adapter->rx_itr_setting & 1)
4111 ixgbe_set_itr(q_vector);
4112 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4113 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4114
4115 return 0;
9a799d71
AK		 4116}
4117
4118/**
4119 * ixgbe_tx_timeout - Respond to a Tx Hang
4120 * @netdev: network interface device structure
4121 **/
4122static void ixgbe_tx_timeout(struct net_device *netdev)
4123{
4124 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4125
4126 /* Do the reset outside of interrupt context */
c83c6cbd 4127 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4128}
4129
4df10466
JB		 4130/**
4131 * ixgbe_set_rss_queues: Allocate queues for RSS
4132 * @adapter: board private structure to initialize
4133 *
4134 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4135 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4136 *
4137 **/
bc97114d
PWJ		 4138static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4139{
4140 bool ret = false;
0cefafad 4141 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4142
4143 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4144 f->mask = 0xF;
4145 adapter->num_rx_queues = f->indices;
4146 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4147 ret = true;
4148 } else {
bc97114d 4149 ret = false;
b9804972
JB		 4150 }
4151
bc97114d
PWJ		 4152 return ret;
4153}
4154
c4cf55e5
PWJ		 4155/**
4156 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4157 * @adapter: board private structure to initialize
4158 *
4159 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4160 * to the original CPU that initiated the Tx session. This runs in addition
4161 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4162 * Rx load across CPUs using RSS.
4163 *
4164 **/
e8e9f696 4165static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4166{
4167 bool ret = false;
4168 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4169
4170 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4171 f_fdir->mask = 0;
4172
4173 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4174 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4175 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4176 adapter->num_tx_queues = f_fdir->indices;
4177 adapter->num_rx_queues = f_fdir->indices;
4178 ret = true;
4179 } else {
4180 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4181 }
4182 return ret;
4183}
4184
0331a832
YZ		 4185#ifdef IXGBE_FCOE
4186/**
4187 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4188 * @adapter: board private structure to initialize
4189 *
4190 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4191 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4192 * rx queues out of the max number of rx queues, instead, it is used as the
4193 * index of the first rx queue used by FCoE.
4194 *
4195 **/
4196static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4197{
0331a832
YZ		 4198 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4199
e5b64635
JF		 4200 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4201 return false;
4202
e901acd6 4203 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4204
e901acd6
JF		 4205 adapter->num_rx_queues = 1;
4206 adapter->num_tx_queues = 1;
e5b64635 4207
e901acd6
JF		 4208 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4209 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4210 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4211 ixgbe_set_fdir_queues(adapter);
4212 else
4213 ixgbe_set_rss_queues(adapter);
e5b64635 4214 }
03ecf91a 4215
e901acd6
JF		 4216 /* adding FCoE rx rings to the end */
4217 f->mask = adapter->num_rx_queues;
4218 adapter->num_rx_queues += f->indices;
4219 adapter->num_tx_queues += f->indices;
0331a832 4220
e5b64635
JF		 4221 return true;
4222}
4223#endif /* IXGBE_FCOE */
4224
e901acd6
JF		 4225/* Artificial max queue cap per traffic class in DCB mode */
4226#define DCB_QUEUE_CAP 8
4227
e5b64635
JF		 4228#ifdef CONFIG_IXGBE_DCB
4229static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4230{
e901acd6
JF		 4231 int per_tc_q, q, i, offset = 0;
4232 struct net_device *dev = adapter->netdev;
4233 int tcs = netdev_get_num_tc(dev);
e5b64635 4234
e901acd6
JF		 4235 if (!tcs)
4236 return false;
e5b64635 4237
e901acd6
JF		 4238 /* Map queue offset and counts onto allocated tx queues */
4239 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4240 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4241
8b1c0b24 4242 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4243 netdev_set_prio_tc_map(dev, i, i);
4244 netdev_set_tc_queue(dev, i, q, offset);
4245 offset += q;
0331a832
YZ		 4246 }
4247
e901acd6
JF		 4248 adapter->num_tx_queues = q * tcs;
4249 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4250
4251#ifdef IXGBE_FCOE
e901acd6
JF		 4252 /* FCoE enabled queues require special configuration indexed
4253 * by feature specific indices and mask. Here we map FCoE
4254 * indices onto the DCB queue pairs allowing FCoE to own
4255 * configuration later.
e5b64635 4256 */
e901acd6
JF		 4257 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4258 int tc;
4259 struct ixgbe_ring_feature *f =
4260 &adapter->ring_feature[RING_F_FCOE];
4261
4262 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4263 f->indices = dev->tc_to_txq[tc].count;
4264 f->mask = dev->tc_to_txq[tc].offset;
4265 }
e5b64635
JF		 4266#endif
4267
e901acd6 4268 return true;
0331a832 4269}
e5b64635 4270#endif
0331a832 4271
1cdd1ec8
GR		 4272/**
4273 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4274 * @adapter: board private structure to initialize
4275 *
4276 * IOV doesn't actually use anything, so just NAK the
4277 * request for now and let the other queue routines
4278 * figure out what to do.
4279 */
4280static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4281{
4282 return false;
4283}
4284
4df10466 4285/*
25985edc 4286 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4287 * @adapter: board private structure to initialize
4288 *
4289 * This is the top level queue allocation routine. The order here is very
4290 * important, starting with the "most" number of features turned on at once,
4291 * and ending with the smallest set of features. This way large combinations
4292 * can be allocated if they're turned on, and smaller combinations are the
4293 * fallthrough conditions.
4294 *
4295 **/
847f53ff 4296static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4297{
1cdd1ec8
GR		 4298 /* Start with base case */
4299 adapter->num_rx_queues = 1;
4300 adapter->num_tx_queues = 1;
4301 adapter->num_rx_pools = adapter->num_rx_queues;
4302 adapter->num_rx_queues_per_pool = 1;
4303
4304 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4305 goto done;
1cdd1ec8 4306
bc97114d
PWJ		 4307#ifdef CONFIG_IXGBE_DCB
4308 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4309 goto done;
bc97114d
PWJ		 4310
4311#endif
e5b64635
JF		 4312#ifdef IXGBE_FCOE
4313 if (ixgbe_set_fcoe_queues(adapter))
4314 goto done;
4315
4316#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4317 if (ixgbe_set_fdir_queues(adapter))
4318 goto done;
4319
bc97114d 4320 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4321 goto done;
4322
4323 /* fallback to base case */
4324 adapter->num_rx_queues = 1;
4325 adapter->num_tx_queues = 1;
4326
4327done:
847f53ff 4328 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4329 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4330 return netif_set_real_num_rx_queues(adapter->netdev,
4331 adapter->num_rx_queues);
b9804972
JB		 4332}
4333
021230d4 4334static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4335 int vectors)
021230d4
AV		 4336{
4337 int err, vector_threshold;
4338
4339 /* We'll want at least 3 (vector_threshold):
4340 * 1) TxQ[0] Cleanup
4341 * 2) RxQ[0] Cleanup
4342 * 3) Other (Link Status Change, etc.)
4343 * 4) TCP Timer (optional)
4344 */
4345 vector_threshold = MIN_MSIX_COUNT;
4346
4347 /* The more we get, the more we will assign to Tx/Rx Cleanup
4348 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4349 * Right now, we simply care about how many we'll get; we'll
4350 * set them up later while requesting irq's.
4351 */
4352 while (vectors >= vector_threshold) {
4353 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4354 vectors);
021230d4
AV		 4355 if (!err) /* Success in acquiring all requested vectors. */
4356 break;
4357 else if (err < 0)
4358 vectors = 0; /* Nasty failure, quit now */
4359 else /* err == number of vectors we should try again with */
4360 vectors = err;
4361 }
4362
4363 if (vectors < vector_threshold) {
4364 /* Can't allocate enough MSI-X interrupts? Oh well.
4365 * This just means we'll go with either a single MSI
4366 * vector or fall back to legacy interrupts.
4367 */
849c4542
ET		 4368 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4369 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4370 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4371 kfree(adapter->msix_entries);
4372 adapter->msix_entries = NULL;
021230d4
AV		 4373 } else {
4374 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4375 /*
4376 * Adjust for only the vectors we'll use, which is minimum
4377 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4378 * vectors we were allocated.
4379 */
4380 adapter->num_msix_vectors = min(vectors,
e8e9f696 4381 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4382 }
4383}
4384
021230d4 4385/**
bc97114d 4386 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4387 * @adapter: board private structure to initialize
4388 *
bc97114d
PWJ		 4389 * Cache the descriptor ring offsets for RSS to the assigned rings.
4390 *
021230d4 4391 **/
bc97114d 4392static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4393{
bc97114d 4394 int i;
bc97114d 4395
9d6b758f
AD		 4396 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4397 return false;
bc97114d 4398
9d6b758f
AD		 4399 for (i = 0; i < adapter->num_rx_queues; i++)
4400 adapter->rx_ring[i]->reg_idx = i;
4401 for (i = 0; i < adapter->num_tx_queues; i++)
4402 adapter->tx_ring[i]->reg_idx = i;
4403
4404 return true;
bc97114d
PWJ		 4405}
4406
4407#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4408
4409/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4410static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4411 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4412{
4413 struct net_device *dev = adapter->netdev;
4414 struct ixgbe_hw *hw = &adapter->hw;
4415 u8 num_tcs = netdev_get_num_tc(dev);
4416
4417 *tx = 0;
4418 *rx = 0;
4419
4420 switch (hw->mac.type) {
4421 case ixgbe_mac_82598EB:
aba70d5e
JF		 4422 *tx = tc << 2;
4423 *rx = tc << 3;
e5b64635
JF		 4424 break;
4425 case ixgbe_mac_82599EB:
4426 case ixgbe_mac_X540:
4fa2e0e1 4427 if (num_tcs > 4) {
e5b64635
JF		 4428 if (tc < 3) {
4429 *tx = tc << 5;
4430 *rx = tc << 4;
4431 } else if (tc < 5) {
4432 *tx = ((tc + 2) << 4);
4433 *rx = tc << 4;
4434 } else if (tc < num_tcs) {
4435 *tx = ((tc + 8) << 3);
4436 *rx = tc << 4;
4437 }
4fa2e0e1 4438 } else {
e5b64635
JF		 4439 *rx = tc << 5;
4440 switch (tc) {
4441 case 0:
4442 *tx = 0;
4443 break;
4444 case 1:
4445 *tx = 64;
4446 break;
4447 case 2:
4448 *tx = 96;
4449 break;
4450 case 3:
4451 *tx = 112;
4452 break;
4453 default:
4454 break;
4455 }
4456 }
4457 break;
4458 default:
4459 break;
4460 }
4461}
4462
bc97114d
PWJ		 4463/**
4464 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4465 * @adapter: board private structure to initialize
4466 *
4467 * Cache the descriptor ring offsets for DCB to the assigned rings.
4468 *
4469 **/
4470static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4471{
e5b64635
JF		 4472 struct net_device *dev = adapter->netdev;
4473 int i, j, k;
4474 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4475
8b1c0b24 4476 if (!num_tcs)
bd508178 4477 return false;
f92ef202 4478
e5b64635
JF		 4479 for (i = 0, k = 0; i < num_tcs; i++) {
4480 unsigned int tx_s, rx_s;
4481 u16 count = dev->tc_to_txq[i].count;
4482
4483 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4484 for (j = 0; j < count; j++, k++) {
4485 adapter->tx_ring[k]->reg_idx = tx_s + j;
4486 adapter->rx_ring[k]->reg_idx = rx_s + j;
4487 adapter->tx_ring[k]->dcb_tc = i;
4488 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4489 }
021230d4 4490 }
e5b64635
JF		 4491
4492 return true;
bc97114d
PWJ		 4493}
4494#endif
4495
c4cf55e5
PWJ		 4496/**
4497 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4498 * @adapter: board private structure to initialize
4499 *
4500 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4501 *
4502 **/
e8e9f696 4503static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4504{
4505 int i;
4506 bool ret = false;
4507
03ecf91a
AD		 4508 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4509 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4510 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4511 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4512 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4513 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4514 ret = true;
4515 }
4516
4517 return ret;
4518}
4519
0331a832
YZ		 4520#ifdef IXGBE_FCOE
4521/**
4522 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4523 * @adapter: board private structure to initialize
4524 *
4525 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4526 *
4527 */
4528static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4529{
0331a832 4530 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4531 int i;
4532 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4533
4534 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4535 return false;
0331a832 4536
bf29ee6c 4537 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4538 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4539 ixgbe_cache_ring_fdir(adapter);
4540 else
4541 ixgbe_cache_ring_rss(adapter);
8faa2a78 4542
bf29ee6c
AD		 4543 fcoe_rx_i = f->mask;
4544 fcoe_tx_i = f->mask;
0331a832 4545 }
bf29ee6c
AD		 4546 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4547 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4548 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4549 }
4550 return true;
0331a832
YZ		 4551}
4552
4553#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4554/**
4555 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4556 * @adapter: board private structure to initialize
4557 *
4558 * SR-IOV doesn't use any descriptor rings but changes the default if
4559 * no other mapping is used.
4560 *
4561 */
4562static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4563{
4a0b9ca0
PW		 4564 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4565 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4566 if (adapter->num_vfs)
4567 return true;
4568 else
4569 return false;
4570}
4571
bc97114d
PWJ		 4572/**
4573 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4574 * @adapter: board private structure to initialize
4575 *
4576 * Once we know the feature-set enabled for the device, we'll cache
4577 * the register offset the descriptor ring is assigned to.
4578 *
4579 * Note, the order the various feature calls is important. It must start with
4580 * the "most" features enabled at the same time, then trickle down to the
4581 * least amount of features turned on at once.
4582 **/
4583static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4584{
4585 /* start with default case */
4a0b9ca0
PW		 4586 adapter->rx_ring[0]->reg_idx = 0;
4587 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4588
1cdd1ec8
GR		 4589 if (ixgbe_cache_ring_sriov(adapter))
4590 return;
4591
e5b64635
JF		 4592#ifdef CONFIG_IXGBE_DCB
4593 if (ixgbe_cache_ring_dcb(adapter))
4594 return;
4595#endif
4596
0331a832
YZ		 4597#ifdef IXGBE_FCOE
4598 if (ixgbe_cache_ring_fcoe(adapter))
4599 return;
0331a832 4600#endif /* IXGBE_FCOE */
bc97114d 4601
c4cf55e5
PWJ		 4602 if (ixgbe_cache_ring_fdir(adapter))
4603 return;
4604
bc97114d
PWJ		 4605 if (ixgbe_cache_ring_rss(adapter))
4606 return;
021230d4
AV		 4607}
4608
9a799d71
AK		 4609/**
4610 * ixgbe_alloc_queues - Allocate memory for all rings
4611 * @adapter: board private structure to initialize
4612 *
4613 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4614 * number of queues at compile-time. The polling_netdev array is
4615 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4616 **/
2f90b865 4617static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4618{
e2ddeba9 4619 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4620
e2ddeba9
ED		 4621 if (nid < 0 || !node_online(nid))
4622 nid = first_online_node;
4623
4624 for (; tx < adapter->num_tx_queues; tx++) {
4625 struct ixgbe_ring *ring;
4626
4627 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4628 if (!ring)
e2ddeba9 4629 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4630 if (!ring)
e2ddeba9 4631 goto err_allocation;
4a0b9ca0 4632 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4633 ring->queue_index = tx;
4634 ring->numa_node = nid;
b6ec895e 4635 ring->dev = &adapter->pdev->dev;
fc77dc3c 4636 ring->netdev = adapter->netdev;
4a0b9ca0 4637
e2ddeba9 4638 adapter->tx_ring[tx] = ring;
021230d4 4639 }
b9804972 4640
e2ddeba9
ED		 4641 for (; rx < adapter->num_rx_queues; rx++) {
4642 struct ixgbe_ring *ring;
4a0b9ca0 4643
e2ddeba9 4644 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4645 if (!ring)
e2ddeba9 4646 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4647 if (!ring)
e2ddeba9
ED		 4648 goto err_allocation;
4649 ring->count = adapter->rx_ring_count;
4650 ring->queue_index = rx;
4651 ring->numa_node = nid;
b6ec895e 4652 ring->dev = &adapter->pdev->dev;
fc77dc3c 4653 ring->netdev = adapter->netdev;
4a0b9ca0 4654
e2ddeba9 4655 adapter->rx_ring[rx] = ring;
021230d4
AV		 4656 }
4657
4658 ixgbe_cache_ring_register(adapter);
4659
4660 return 0;
4661
e2ddeba9
ED		 4662err_allocation:
4663 while (tx)
4664 kfree(adapter->tx_ring[--tx]);
4665
4666 while (rx)
4667 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4668 return -ENOMEM;
4669}
4670
4671/**
4672 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4673 * @adapter: board private structure to initialize
4674 *
4675 * Attempt to configure the interrupts using the best available
4676 * capabilities of the hardware and the kernel.
4677 **/
feea6a57 4678static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4679{
8be0e467 4680 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4681 int err = 0;
4682 int vector, v_budget;
4683
4684 /*
4685 * It's easy to be greedy for MSI-X vectors, but it really
4686 * doesn't do us much good if we have a lot more vectors
4687 * than CPU's. So let's be conservative and only ask for
342bde1b 4688 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4689 */
4690 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4691 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4692
4693 /*
4694 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4695 * hw.mac->max_msix_vectors vectors. With features
4696 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4697 * descriptor queues supported by our device. Thus, we cap it off in
4698 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4699 */
8be0e467 4700 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4701
4702 /* A failure in MSI-X entry allocation isn't fatal, but it does
4703 * mean we disable MSI-X capabilities of the adapter. */
4704 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4705 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4706 if (adapter->msix_entries) {
4707 for (vector = 0; vector < v_budget; vector++)
4708 adapter->msix_entries[vector].entry = vector;
021230d4 4709
7a921c93 4710 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4711
7a921c93
AD		 4712 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4713 goto out;
4714 }
26d27844 4715
7a921c93
AD		 4716 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4717 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4718 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4719 e_err(probe,
03ecf91a 4720 "ATR is not supported while multiple "
45b9f509
AD		 4721 "queues are disabled. Disabling Flow Director\n");
4722 }
c4cf55e5 4723 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4724 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4725 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4726 ixgbe_disable_sriov(adapter);
4727
847f53ff
BH		 4728 err = ixgbe_set_num_queues(adapter);
4729 if (err)
4730 return err;
021230d4 4731
021230d4
AV		 4732 err = pci_enable_msi(adapter->pdev);
4733 if (!err) {
4734 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4735 } else {
849c4542
ET		 4736 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4737 "Unable to allocate MSI interrupt, "
4738 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4739 /* reset err */
4740 err = 0;
4741 }
4742
4743out:
021230d4
AV		 4744 return err;
4745}
4746
7a921c93
AD		 4747/**
4748 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4749 * @adapter: board private structure to initialize
4750 *
4751 * We allocate one q_vector per queue interrupt. If allocation fails we
4752 * return -ENOMEM.
4753 **/
4754static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4755{
4ff7fb12 4756 int v_idx, num_q_vectors;
7a921c93 4757 struct ixgbe_q_vector *q_vector;
7a921c93 4758
4ff7fb12 4759 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4760 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4761 else
7a921c93 4762 num_q_vectors = 1;
7a921c93 4763
4ff7fb12 4764 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4765 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4766 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4767 if (!q_vector)
4768 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4769 GFP_KERNEL);
7a921c93
AD		 4770 if (!q_vector)
4771 goto err_out;
4ff7fb12 4772
7a921c93 4773 q_vector->adapter = adapter;
4ff7fb12
AD		 4774 q_vector->v_idx = v_idx;
4775
207867f5
AD		 4776 /* Allocate the affinity_hint cpumask, configure the mask */
4777 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4778 goto err_out;
4779 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 4780 netif_napi_add(adapter->netdev, &q_vector->napi,
4781 ixgbe_poll, 64);
4782 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4783 }
4784
4785 return 0;
4786
4787err_out:
4ff7fb12
AD		 4788 while (v_idx) {
4789 v_idx--;
4790 q_vector = adapter->q_vector[v_idx];
7a921c93 4791 netif_napi_del(&q_vector->napi);
207867f5 4792 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4793 kfree(q_vector);
4ff7fb12 4794 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4795 }
4796 return -ENOMEM;
4797}
4798
4799/**
4800 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4801 * @adapter: board private structure to initialize
4802 *
4803 * This function frees the memory allocated to the q_vectors. In addition if
4804 * NAPI is enabled it will delete any references to the NAPI struct prior
4805 * to freeing the q_vector.
4806 **/
4807static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4808{
207867f5 4809 int v_idx, num_q_vectors;
7a921c93 4810
91281fd3 4811 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4812 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4813 else
7a921c93 4814 num_q_vectors = 1;
7a921c93 4815
207867f5
AD		 4816 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4817 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4818 adapter->q_vector[v_idx] = NULL;
91281fd3 4819 netif_napi_del(&q_vector->napi);
207867f5 4820 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 4821 kfree(q_vector);
4822 }
4823}
4824
7b25cdba 4825static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4826{
4827 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4828 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4829 pci_disable_msix(adapter->pdev);
4830 kfree(adapter->msix_entries);
4831 adapter->msix_entries = NULL;
4832 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4833 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4834 pci_disable_msi(adapter->pdev);
4835 }
021230d4
AV		 4836}
4837
4838/**
4839 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4840 * @adapter: board private structure to initialize
4841 *
4842 * We determine which interrupt scheme to use based on...
4843 * - Kernel support (MSI, MSI-X)
4844 * - which can be user-defined (via MODULE_PARAM)
4845 * - Hardware queue count (num_*_queues)
4846 * - defined by miscellaneous hardware support/features (RSS, etc.)
4847 **/
2f90b865 4848int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4849{
4850 int err;
4851
4852 /* Number of supported queues */
847f53ff
BH		 4853 err = ixgbe_set_num_queues(adapter);
4854 if (err)
4855 return err;
021230d4 4856
021230d4
AV		 4857 err = ixgbe_set_interrupt_capability(adapter);
4858 if (err) {
849c4542 4859 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4860 goto err_set_interrupt;
9a799d71
AK		 4861 }
4862
7a921c93
AD		 4863 err = ixgbe_alloc_q_vectors(adapter);
4864 if (err) {
849c4542 4865 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4866 goto err_alloc_q_vectors;
4867 }
4868
4869 err = ixgbe_alloc_queues(adapter);
4870 if (err) {
849c4542 4871 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4872 goto err_alloc_queues;
4873 }
4874
849c4542 4875 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4876 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4877 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4878
4879 set_bit(__IXGBE_DOWN, &adapter->state);
4880
9a799d71 4881 return 0;
021230d4 4882
7a921c93
AD		 4883err_alloc_queues:
4884 ixgbe_free_q_vectors(adapter);
4885err_alloc_q_vectors:
4886 ixgbe_reset_interrupt_capability(adapter);
021230d4 4887err_set_interrupt:
7a921c93
AD		 4888 return err;
4889}
4890
4891/**
4892 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4893 * @adapter: board private structure to clear interrupt scheme on
4894 *
4895 * We go through and clear interrupt specific resources and reset the structure
4896 * to pre-load conditions
4897 **/
4898void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4899{
4a0b9ca0
PW		 4900 int i;
4901
4902 for (i = 0; i < adapter->num_tx_queues; i++) {
4903 kfree(adapter->tx_ring[i]);
4904 adapter->tx_ring[i] = NULL;
4905 }
4906 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4907 struct ixgbe_ring *ring = adapter->rx_ring[i];
4908
4909 /* ixgbe_get_stats64() might access this ring, we must wait
4910 * a grace period before freeing it.
4911 */
bcec8b65 4912 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4913 adapter->rx_ring[i] = NULL;
4914 }
7a921c93 4915
b8eb3a10
DS		 4916 adapter->num_tx_queues = 0;
4917 adapter->num_rx_queues = 0;
4918
7a921c93
AD		 4919 ixgbe_free_q_vectors(adapter);
4920 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4921}
4922
4923/**
4924 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4925 * @adapter: board private structure to initialize
4926 *
4927 * ixgbe_sw_init initializes the Adapter private data structure.
4928 * Fields are initialized based on PCI device information and
4929 * OS network device settings (MTU size).
4930 **/
4931static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4932{
4933 struct ixgbe_hw *hw = &adapter->hw;
4934 struct pci_dev *pdev = adapter->pdev;
021230d4 4935 unsigned int rss;
7a6b6f51 4936#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4937 int j;
4938 struct tc_configuration *tc;
4939#endif
021230d4 4940
c44ade9e
JB		 4941 /* PCI config space info */
4942
4943 hw->vendor_id = pdev->vendor;
4944 hw->device_id = pdev->device;
4945 hw->revision_id = pdev->revision;
4946 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4947 hw->subsystem_device_id = pdev->subsystem_device;
4948
021230d4
AV		 4949 /* Set capability flags */
4950 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4951 adapter->ring_feature[RING_F_RSS].indices = rss;
4952 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4953 switch (hw->mac.type) {
4954 case ixgbe_mac_82598EB:
bf069c97
DS		 4955 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4956 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4957 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 4958 break;
b93a2226 4959 case ixgbe_mac_X540:
4f51bf70
JK		 4960 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4961 case ixgbe_mac_82599EB:
e8e26350 4962 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4963 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4964 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4965 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4966 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4967 /* Flow Director hash filters enabled */
4968 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4969 adapter->atr_sample_rate = 20;
c4cf55e5 4970 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4971 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4972 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4973#ifdef IXGBE_FCOE
0d551589
YZ		 4974 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4975 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4976 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4977#ifdef CONFIG_IXGBE_DCB
6ee16520 4978 /* Default traffic class to use for FCoE */
56075a98 4979 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4980#endif
eacd73f7 4981#endif /* IXGBE_FCOE */
bd508178
AD		 4982 break;
4983 default:
4984 break;
f8212f97 4985 }
2f90b865 4986
1fc5f038
AD		 4987 /* n-tuple support exists, always init our spinlock */
4988 spin_lock_init(&adapter->fdir_perfect_lock);
4989
7a6b6f51 4990#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4991 /* Configure DCB traffic classes */
4992 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4993 tc = &adapter->dcb_cfg.tc_config[j];
4994 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4995 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4996 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4997 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4998 tc->dcb_pfc = pfc_disabled;
4999 }
5000 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5001 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5002 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5003 adapter->dcb_set_bitmap = 0x00;
3032309b 5004 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5005 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5006 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5007
5008#endif
9a799d71
AK		 5009
5010 /* default flow control settings */
cd7664f6 5011 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5012 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5013#ifdef CONFIG_DCB
5014 adapter->last_lfc_mode = hw->fc.current_mode;
5015#endif
9da712d2 5016 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5017 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5018 hw->fc.send_xon = true;
71fd570b 5019 hw->fc.disable_fc_autoneg = false;
9a799d71 5020
30efa5a3 5021 /* enable itr by default in dynamic mode */
f7554a2b 5022 adapter->rx_itr_setting = 1;
f7554a2b 5023 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5024
5025 /* set defaults for eitr in MegaBytes */
5026 adapter->eitr_low = 10;
5027 adapter->eitr_high = 20;
5028
5029 /* set default ring sizes */
5030 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5031 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5032
bd198058 5033 /* set default work limits */
59224555 5034 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5035
9a799d71 5036 /* initialize eeprom parameters */
c44ade9e 5037 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5038 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5039 return -EIO;
5040 }
5041
021230d4 5042 /* enable rx csum by default */
9a799d71
AK		 5043 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5044
1a6c14a2
JB		 5045 /* get assigned NUMA node */
5046 adapter->node = dev_to_node(&pdev->dev);
5047
9a799d71
AK		 5048 set_bit(__IXGBE_DOWN, &adapter->state);
5049
5050 return 0;
5051}
5052
5053/**
5054 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5055 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5056 *
5057 * Return 0 on success, negative on failure
5058 **/
b6ec895e 5059int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5060{
b6ec895e 5061 struct device *dev = tx_ring->dev;
9a799d71
AK		 5062 int size;
5063
3a581073 5064 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5065 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5066 if (!tx_ring->tx_buffer_info)
89bf67f1 5067 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5068 if (!tx_ring->tx_buffer_info)
5069 goto err;
9a799d71
AK		 5070
5071 /* round up to nearest 4K */
12207e49 5072 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5073 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5074
b6ec895e 5075 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5076 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5077 if (!tx_ring->desc)
5078 goto err;
9a799d71 5079
3a581073
JB		 5080 tx_ring->next_to_use = 0;
5081 tx_ring->next_to_clean = 0;
9a799d71 5082 return 0;
e01c31a5
JB		 5083
5084err:
5085 vfree(tx_ring->tx_buffer_info);
5086 tx_ring->tx_buffer_info = NULL;
b6ec895e 5087 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5088 return -ENOMEM;
9a799d71
AK		 5089}
5090
69888674
AD		 5091/**
5092 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5093 * @adapter: board private structure
5094 *
5095 * If this function returns with an error, then it's possible one or
5096 * more of the rings is populated (while the rest are not). It is the
5097 * callers duty to clean those orphaned rings.
5098 *
5099 * Return 0 on success, negative on failure
5100 **/
5101static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5102{
5103 int i, err = 0;
5104
5105 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5106 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5107 if (!err)
5108 continue;
396e799c 5109 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5110 break;
5111 }
5112
5113 return err;
5114}
5115
9a799d71
AK		 5116/**
5117 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5118 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5119 *
5120 * Returns 0 on success, negative on failure
5121 **/
b6ec895e 5122int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5123{
b6ec895e 5124 struct device *dev = rx_ring->dev;
021230d4 5125 int size;
9a799d71 5126
3a581073 5127 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5128 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5129 if (!rx_ring->rx_buffer_info)
89bf67f1 5130 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5131 if (!rx_ring->rx_buffer_info)
5132 goto err;
9a799d71 5133
9a799d71 5134 /* Round up to nearest 4K */
3a581073
JB		 5135 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5136 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5137
b6ec895e 5138 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5139 &rx_ring->dma, GFP_KERNEL);
9a799d71 5140
b6ec895e
AD		 5141 if (!rx_ring->desc)
5142 goto err;
9a799d71 5143
3a581073
JB		 5144 rx_ring->next_to_clean = 0;
5145 rx_ring->next_to_use = 0;
9a799d71
AK		 5146
5147 return 0;
b6ec895e
AD		 5148err:
5149 vfree(rx_ring->rx_buffer_info);
5150 rx_ring->rx_buffer_info = NULL;
5151 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5152 return -ENOMEM;
9a799d71
AK		 5153}
5154
69888674
AD		 5155/**
5156 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5157 * @adapter: board private structure
5158 *
5159 * If this function returns with an error, then it's possible one or
5160 * more of the rings is populated (while the rest are not). It is the
5161 * callers duty to clean those orphaned rings.
5162 *
5163 * Return 0 on success, negative on failure
5164 **/
69888674
AD		 5165static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5166{
5167 int i, err = 0;
5168
5169 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5170 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5171 if (!err)
5172 continue;
396e799c 5173 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5174 break;
5175 }
5176
5177 return err;
5178}
5179
9a799d71
AK		 5180/**
5181 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5182 * @tx_ring: Tx descriptor ring for a specific queue
5183 *
5184 * Free all transmit software resources
5185 **/
b6ec895e 5186void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5187{
b6ec895e 5188 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5189
5190 vfree(tx_ring->tx_buffer_info);
5191 tx_ring->tx_buffer_info = NULL;
5192
b6ec895e
AD		 5193 /* if not set, then don't free */
5194 if (!tx_ring->desc)
5195 return;
5196
5197 dma_free_coherent(tx_ring->dev, tx_ring->size,
5198 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5199
5200 tx_ring->desc = NULL;
5201}
5202
5203/**
5204 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5205 * @adapter: board private structure
5206 *
5207 * Free all transmit software resources
5208 **/
5209static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5210{
5211 int i;
5212
5213 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5214 if (adapter->tx_ring[i]->desc)
b6ec895e 5215 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5216}
5217
5218/**
b4617240 5219 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5220 * @rx_ring: ring to clean the resources from
5221 *
5222 * Free all receive software resources
5223 **/
b6ec895e 5224void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5225{
b6ec895e 5226 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5227
5228 vfree(rx_ring->rx_buffer_info);
5229 rx_ring->rx_buffer_info = NULL;
5230
b6ec895e
AD		 5231 /* if not set, then don't free */
5232 if (!rx_ring->desc)
5233 return;
5234
5235 dma_free_coherent(rx_ring->dev, rx_ring->size,
5236 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5237
5238 rx_ring->desc = NULL;
5239}
5240
5241/**
5242 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5243 * @adapter: board private structure
5244 *
5245 * Free all receive software resources
5246 **/
5247static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5248{
5249 int i;
5250
5251 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5252 if (adapter->rx_ring[i]->desc)
b6ec895e 5253 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5254}
5255
9a799d71
AK		 5256/**
5257 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5258 * @netdev: network interface device structure
5259 * @new_mtu: new value for maximum frame size
5260 *
5261 * Returns 0 on success, negative on failure
5262 **/
5263static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5264{
5265 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5266 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5267 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5268
42c783c5 5269 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5270 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5271 hw->mac.type != ixgbe_mac_X540) {
5272 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5273 return -EINVAL;
5274 } else {
5275 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5276 return -EINVAL;
5277 }
9a799d71 5278
396e799c 5279 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5280 /* must set new MTU before calling down or up */
9a799d71
AK		 5281 netdev->mtu = new_mtu;
5282
d4f80882
AV		 5283 if (netif_running(netdev))
5284 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5285
5286 return 0;
5287}
5288
5289/**
5290 * ixgbe_open - Called when a network interface is made active
5291 * @netdev: network interface device structure
5292 *
5293 * Returns 0 on success, negative value on failure
5294 *
5295 * The open entry point is called when a network interface is made
5296 * active by the system (IFF_UP). At this point all resources needed
5297 * for transmit and receive operations are allocated, the interrupt
5298 * handler is registered with the OS, the watchdog timer is started,
5299 * and the stack is notified that the interface is ready.
5300 **/
5301static int ixgbe_open(struct net_device *netdev)
5302{
5303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5304 int err;
4bebfaa5
AK		 5305
5306 /* disallow open during test */
5307 if (test_bit(__IXGBE_TESTING, &adapter->state))
5308 return -EBUSY;
9a799d71 5309
54386467
JB		 5310 netif_carrier_off(netdev);
5311
9a799d71
AK		 5312 /* allocate transmit descriptors */
5313 err = ixgbe_setup_all_tx_resources(adapter);
5314 if (err)
5315 goto err_setup_tx;
5316
9a799d71
AK		 5317 /* allocate receive descriptors */
5318 err = ixgbe_setup_all_rx_resources(adapter);
5319 if (err)
5320 goto err_setup_rx;
5321
5322 ixgbe_configure(adapter);
5323
021230d4 5324 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5325 if (err)
5326 goto err_req_irq;
5327
c7ccde0f 5328 ixgbe_up_complete(adapter);
9a799d71
AK		 5329
5330 return 0;
5331
9a799d71 5332err_req_irq:
9a799d71 5333err_setup_rx:
a20a1199 5334 ixgbe_free_all_rx_resources(adapter);
9a799d71 5335err_setup_tx:
a20a1199 5336 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5337 ixgbe_reset(adapter);
5338
5339 return err;
5340}
5341
5342/**
5343 * ixgbe_close - Disables a network interface
5344 * @netdev: network interface device structure
5345 *
5346 * Returns 0, this is not allowed to fail
5347 *
5348 * The close entry point is called when an interface is de-activated
5349 * by the OS. The hardware is still under the drivers control, but
5350 * needs to be disabled. A global MAC reset is issued to stop the
5351 * hardware, and all transmit and receive resources are freed.
5352 **/
5353static int ixgbe_close(struct net_device *netdev)
5354{
5355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5356
5357 ixgbe_down(adapter);
5358 ixgbe_free_irq(adapter);
5359
e4911d57
AD		 5360 ixgbe_fdir_filter_exit(adapter);
5361
9a799d71
AK		 5362 ixgbe_free_all_tx_resources(adapter);
5363 ixgbe_free_all_rx_resources(adapter);
5364
5eba3699 5365 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5366
5367 return 0;
5368}
5369
b3c8b4ba
AD		 5370#ifdef CONFIG_PM
5371static int ixgbe_resume(struct pci_dev *pdev)
5372{
c60fbb00
AD		 5373 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5374 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5375 u32 err;
5376
5377 pci_set_power_state(pdev, PCI_D0);
5378 pci_restore_state(pdev);
656ab817
DS		 5379 /*
5380 * pci_restore_state clears dev->state_saved so call
5381 * pci_save_state to restore it.
5382 */
5383 pci_save_state(pdev);
9ce77666 5384
5385 err = pci_enable_device_mem(pdev);
b3c8b4ba 5386 if (err) {
849c4542 5387 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5388 return err;
5389 }
5390 pci_set_master(pdev);
5391
dd4d8ca6 5392 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5393
5394 err = ixgbe_init_interrupt_scheme(adapter);
5395 if (err) {
849c4542 5396 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5397 return err;
5398 }
5399
b3c8b4ba
AD		 5400 ixgbe_reset(adapter);
5401
495dce12
WJP		 5402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5403
b3c8b4ba 5404 if (netif_running(netdev)) {
c60fbb00 5405 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5406 if (err)
5407 return err;
5408 }
5409
5410 netif_device_attach(netdev);
5411
5412 return 0;
5413}
b3c8b4ba 5414#endif /* CONFIG_PM */
9d8d05ae
RW		 5415
5416static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5417{
c60fbb00
AD		 5418 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5419 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5420 struct ixgbe_hw *hw = &adapter->hw;
5421 u32 ctrl, fctrl;
5422 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5423#ifdef CONFIG_PM
5424 int retval = 0;
5425#endif
5426
5427 netif_device_detach(netdev);
5428
5429 if (netif_running(netdev)) {
5430 ixgbe_down(adapter);
5431 ixgbe_free_irq(adapter);
5432 ixgbe_free_all_tx_resources(adapter);
5433 ixgbe_free_all_rx_resources(adapter);
5434 }
b3c8b4ba 5435
5f5ae6fc 5436 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5437#ifdef CONFIG_DCB
5438 kfree(adapter->ixgbe_ieee_pfc);
5439 kfree(adapter->ixgbe_ieee_ets);
5440#endif
5f5ae6fc 5441
b3c8b4ba
AD		 5442#ifdef CONFIG_PM
5443 retval = pci_save_state(pdev);
5444 if (retval)
5445 return retval;
4df10466 5446
b3c8b4ba 5447#endif
e8e26350
PW		 5448 if (wufc) {
5449 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5450
e8e26350
PW		 5451 /* turn on all-multi mode if wake on multicast is enabled */
5452 if (wufc & IXGBE_WUFC_MC) {
5453 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5454 fctrl |= IXGBE_FCTRL_MPE;
5455 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5456 }
5457
5458 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5459 ctrl |= IXGBE_CTRL_GIO_DIS;
5460 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5461
5462 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5463 } else {
5464 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5465 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5466 }
5467
bd508178
AD		 5468 switch (hw->mac.type) {
5469 case ixgbe_mac_82598EB:
dd4d8ca6 5470 pci_wake_from_d3(pdev, false);
bd508178
AD		 5471 break;
5472 case ixgbe_mac_82599EB:
b93a2226 5473 case ixgbe_mac_X540:
bd508178
AD		 5474 pci_wake_from_d3(pdev, !!wufc);
5475 break;
5476 default:
5477 break;
5478 }
b3c8b4ba 5479
9d8d05ae
RW		 5480 *enable_wake = !!wufc;
5481
b3c8b4ba
AD		 5482 ixgbe_release_hw_control(adapter);
5483
5484 pci_disable_device(pdev);
5485
9d8d05ae
RW		 5486 return 0;
5487}
5488
5489#ifdef CONFIG_PM
5490static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5491{
5492 int retval;
5493 bool wake;
5494
5495 retval = __ixgbe_shutdown(pdev, &wake);
5496 if (retval)
5497 return retval;
5498
5499 if (wake) {
5500 pci_prepare_to_sleep(pdev);
5501 } else {
5502 pci_wake_from_d3(pdev, false);
5503 pci_set_power_state(pdev, PCI_D3hot);
5504 }
b3c8b4ba
AD		 5505
5506 return 0;
5507}
9d8d05ae 5508#endif /* CONFIG_PM */
b3c8b4ba
AD		 5509
5510static void ixgbe_shutdown(struct pci_dev *pdev)
5511{
9d8d05ae
RW		 5512 bool wake;
5513
5514 __ixgbe_shutdown(pdev, &wake);
5515
5516 if (system_state == SYSTEM_POWER_OFF) {
5517 pci_wake_from_d3(pdev, wake);
5518 pci_set_power_state(pdev, PCI_D3hot);
5519 }
b3c8b4ba
AD		 5520}
5521
9a799d71
AK		 5522/**
5523 * ixgbe_update_stats - Update the board statistics counters.
5524 * @adapter: board private structure
5525 **/
5526void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5527{
2d86f139 5528 struct net_device *netdev = adapter->netdev;
9a799d71 5529 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5530 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5531 u64 total_mpc = 0;
5532 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5533 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5534 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5535 u64 bytes = 0, packets = 0;
9a799d71 5536
d08935c2
DS		 5537 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5538 test_bit(__IXGBE_RESETTING, &adapter->state))
5539 return;
5540
94b982b2 5541 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5542 u64 rsc_count = 0;
94b982b2 5543 u64 rsc_flush = 0;
d51019a4
PW		 5544 for (i = 0; i < 16; i++)
5545 adapter->hw_rx_no_dma_resources +=
7ca647bd 5546 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5547 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5548 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5549 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5550 }
5551 adapter->rsc_total_count = rsc_count;
5552 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5553 }
5554
5b7da515
AD		 5555 for (i = 0; i < adapter->num_rx_queues; i++) {
5556 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5557 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5558 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5559 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5560 bytes += rx_ring->stats.bytes;
5561 packets += rx_ring->stats.packets;
5562 }
5563 adapter->non_eop_descs = non_eop_descs;
5564 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5565 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5566 netdev->stats.rx_bytes = bytes;
5567 netdev->stats.rx_packets = packets;
5568
5569 bytes = 0;
5570 packets = 0;
7ca3bc58 5571 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5572 for (i = 0; i < adapter->num_tx_queues; i++) {
5573 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5574 restart_queue += tx_ring->tx_stats.restart_queue;
5575 tx_busy += tx_ring->tx_stats.tx_busy;
5576 bytes += tx_ring->stats.bytes;
5577 packets += tx_ring->stats.packets;
5578 }
eb985f09 5579 adapter->restart_queue = restart_queue;
5b7da515
AD		 5580 adapter->tx_busy = tx_busy;
5581 netdev->stats.tx_bytes = bytes;
5582 netdev->stats.tx_packets = packets;
7ca3bc58 5583
7ca647bd 5584 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5585
5586 /* 8 register reads */
6f11eef7
AV		 5587 for (i = 0; i < 8; i++) {
5588 /* for packet buffers not used, the register should read 0 */
5589 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5590 missed_rx += mpc;
7ca647bd
JP		 5591 hwstats->mpc[i] += mpc;
5592 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5593 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5594 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5595 switch (hw->mac.type) {
5596 case ixgbe_mac_82598EB:
1a70db4b
ET		 5597 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5598 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5599 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5600 hwstats->pxonrxc[i] +=
5601 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5602 break;
5603 case ixgbe_mac_82599EB:
b93a2226 5604 case ixgbe_mac_X540:
bd508178
AD		 5605 hwstats->pxonrxc[i] +=
5606 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5607 break;
5608 default:
5609 break;
e8e26350 5610 }
6f11eef7 5611 }
1a70db4b
ET		 5612
5613 /*16 register reads */
5614 for (i = 0; i < 16; i++) {
5615 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5616 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5617 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5618 (hw->mac.type == ixgbe_mac_X540)) {
5619 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5620 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5621 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5622 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5623 }
5624 }
5625
7ca647bd 5626 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5627 /* work around hardware counting issue */
7ca647bd 5628 hwstats->gprc -= missed_rx;
6f11eef7 5629
c84d324c
JF		 5630 ixgbe_update_xoff_received(adapter);
5631
6f11eef7 5632 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5633 switch (hw->mac.type) {
5634 case ixgbe_mac_82598EB:
5635 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5636 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5637 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5638 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5639 break;
b93a2226 5640 case ixgbe_mac_X540:
58f6bcf9
ET		 5641 /* OS2BMC stats are X540 only*/
5642 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5643 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5644 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5645 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5646 case ixgbe_mac_82599EB:
7ca647bd 5647 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5648 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5649 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5650 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5651 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5652 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5653 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5654 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5655 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5656#ifdef IXGBE_FCOE
7ca647bd
JP		 5657 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5658 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5659 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5660 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5661 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5662 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5663#endif /* IXGBE_FCOE */
bd508178
AD		 5664 break;
5665 default:
5666 break;
e8e26350 5667 }
9a799d71 5668 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5669 hwstats->bprc += bprc;
5670 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5671 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5672 hwstats->mprc -= bprc;
5673 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5674 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5675 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5676 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5677 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5678 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5679 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5680 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5681 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5682 hwstats->lxontxc += lxon;
6f11eef7 5683 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5684 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5685 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5686 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5687 /*
5688 * 82598 errata - tx of flow control packets is included in tx counters
5689 */
5690 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5691 hwstats->gptc -= xon_off_tot;
5692 hwstats->mptc -= xon_off_tot;
5693 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5694 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5695 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5696 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5697 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5698 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5699 hwstats->ptc64 -= xon_off_tot;
5700 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5701 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5702 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5703 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5704 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5705 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5706
5707 /* Fill out the OS statistics structure */
7ca647bd 5708 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5709
5710 /* Rx Errors */
7ca647bd 5711 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5712 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5713 netdev->stats.rx_length_errors = hwstats->rlec;
5714 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5715 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5716}
5717
5718/**
d034acf1
AD		 5719 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5720 * @adapter - pointer to the device adapter structure
9a799d71 5721 **/
d034acf1 5722static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5723{
cf8280ee 5724 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5725 int i;
cf8280ee 5726
d034acf1
AD		 5727 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5728 return;
5729
5730 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5731
d034acf1 5732 /* if interface is down do nothing */
fe49f04a 5733 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5734 return;
5735
5736 /* do nothing if we are not using signature filters */
5737 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5738 return;
5739
5740 adapter->fdir_overflow++;
5741
93c52dd0
AD		 5742 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5743 for (i = 0; i < adapter->num_tx_queues; i++)
5744 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5745 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5746 /* re-enable flow director interrupts */
5747 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5748 } else {
5749 e_err(probe, "failed to finish FDIR re-initialization, "
5750 "ignored adding FDIR ATR filters\n");
5751 }
93c52dd0
AD		 5752}
5753
5754/**
5755 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5756 * @adapter - pointer to the device adapter structure
5757 *
5758 * This function serves two purposes. First it strobes the interrupt lines
5759 * in order to make certain interrupts are occuring. Secondly it sets the
5760 * bits needed to check for TX hangs. As a result we should immediately
5761 * determine if a hang has occured.
5762 */
5763static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5764{
cf8280ee 5765 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5766 u64 eics = 0;
5767 int i;
cf8280ee 5768
93c52dd0
AD		 5769 /* If we're down or resetting, just bail */
5770 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5771 test_bit(__IXGBE_RESETTING, &adapter->state))
5772 return;
22d5a71b 5773
93c52dd0
AD		 5774 /* Force detection of hung controller */
5775 if (netif_carrier_ok(adapter->netdev)) {
5776 for (i = 0; i < adapter->num_tx_queues; i++)
5777 set_check_for_tx_hang(adapter->tx_ring[i]);
5778 }
22d5a71b 5779
fe49f04a
AD		 5780 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5781 /*
5782 * for legacy and MSI interrupts don't set any bits
5783 * that are enabled for EIAM, because this operation
5784 * would set *both* EIMS and EICS for any bit in EIAM
5785 */
5786 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5787 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5788 } else {
5789 /* get one bit for every active tx/rx interrupt vector */
5790 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5791 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5792 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5793 eics |= ((u64)1 << i);
5794 }
cf8280ee 5795 }
9a799d71 5796
93c52dd0 5797 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5798 ixgbe_irq_rearm_queues(adapter, eics);
5799
cf8280ee
JB		 5800}
5801
e8e26350 5802/**
93c52dd0
AD		 5803 * ixgbe_watchdog_update_link - update the link status
5804 * @adapter - pointer to the device adapter structure
5805 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5806 **/
93c52dd0 5807static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5808{
e8e26350 5809 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5810 u32 link_speed = adapter->link_speed;
5811 bool link_up = adapter->link_up;
c4cf55e5 5812 int i;
e8e26350 5813
93c52dd0
AD		 5814 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5815 return;
5816
5817 if (hw->mac.ops.check_link) {
5818 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5819 } else {
93c52dd0
AD		 5820 /* always assume link is up, if no check link function */
5821 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5822 link_up = true;
c4cf55e5 5823 }
93c52dd0
AD		 5824 if (link_up) {
5825 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5826 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5827 hw->mac.ops.fc_enable(hw, i);
5828 } else {
5829 hw->mac.ops.fc_enable(hw, 0);
5830 }
5831 }
5832
5833 if (link_up ||
5834 time_after(jiffies, (adapter->link_check_timeout +
5835 IXGBE_TRY_LINK_TIMEOUT))) {
5836 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5837 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5838 IXGBE_WRITE_FLUSH(hw);
5839 }
5840
5841 adapter->link_up = link_up;
5842 adapter->link_speed = link_speed;
e8e26350
PW		 5843}
5844
5845/**
93c52dd0
AD		 5846 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5847 * print link up message
5848 * @adapter - pointer to the device adapter structure
e8e26350 5849 **/
93c52dd0 5850static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5851{
93c52dd0 5852 struct net_device *netdev = adapter->netdev;
e8e26350 5853 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5854 u32 link_speed = adapter->link_speed;
5855 bool flow_rx, flow_tx;
e8e26350 5856
93c52dd0
AD		 5857 /* only continue if link was previously down */
5858 if (netif_carrier_ok(netdev))
a985b6c3 5859 return;
63d6e1d8 5860
93c52dd0 5861 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5862
93c52dd0
AD		 5863 switch (hw->mac.type) {
5864 case ixgbe_mac_82598EB: {
5865 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5866 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5867 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5868 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5869 }
5870 break;
5871 case ixgbe_mac_X540:
5872 case ixgbe_mac_82599EB: {
5873 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5874 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5875 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5876 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5877 }
5878 break;
5879 default:
5880 flow_tx = false;
5881 flow_rx = false;
5882 break;
e8e26350 5883 }
93c52dd0
AD		 5884 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5885 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5886 "10 Gbps" :
5887 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5888 "1 Gbps" :
5889 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5890 "100 Mbps" :
5891 "unknown speed"))),
5892 ((flow_rx && flow_tx) ? "RX/TX" :
5893 (flow_rx ? "RX" :
5894 (flow_tx ? "TX" : "None"))));
e8e26350 5895
93c52dd0 5896 netif_carrier_on(netdev);
93c52dd0 5897 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5898}
5899
c4cf55e5 5900/**
93c52dd0
AD		 5901 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5902 * print link down message
5903 * @adapter - pointer to the adapter structure
c4cf55e5 5904 **/
93c52dd0 5905static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5906{
cf8280ee 5907 struct net_device *netdev = adapter->netdev;
c4cf55e5 5908 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5909
93c52dd0
AD		 5910 adapter->link_up = false;
5911 adapter->link_speed = 0;
cf8280ee 5912
93c52dd0
AD		 5913 /* only continue if link was up previously */
5914 if (!netif_carrier_ok(netdev))
5915 return;
264857b8 5916
93c52dd0
AD		 5917 /* poll for SFP+ cable when link is down */
5918 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5919 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5920
93c52dd0
AD		 5921 e_info(drv, "NIC Link is Down\n");
5922 netif_carrier_off(netdev);
5923}
e8e26350 5924
93c52dd0
AD		 5925/**
5926 * ixgbe_watchdog_flush_tx - flush queues on link down
5927 * @adapter - pointer to the device adapter structure
5928 **/
5929static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5930{
c4cf55e5 5931 int i;
93c52dd0 5932 int some_tx_pending = 0;
c4cf55e5 5933
93c52dd0 5934 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5935 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5936 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5937 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5938 some_tx_pending = 1;
5939 break;
5940 }
5941 }
5942
5943 if (some_tx_pending) {
5944 /* We've lost link, so the controller stops DMA,
5945 * but we've got queued Tx work that's never going
5946 * to get done, so reset controller to flush Tx.
5947 * (Do the reset outside of interrupt context).
5948 */
c83c6cbd 5949 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5950 }
c4cf55e5 5951 }
c4cf55e5
PWJ		 5952}
5953
a985b6c3
GR		 5954static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5955{
5956 u32 ssvpc;
5957
5958 /* Do not perform spoof check for 82598 */
5959 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5960 return;
5961
5962 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5963
5964 /*
5965 * ssvpc register is cleared on read, if zero then no
5966 * spoofed packets in the last interval.
5967 */
5968 if (!ssvpc)
5969 return;
5970
5971 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5972}
5973
93c52dd0
AD		 5974/**
5975 * ixgbe_watchdog_subtask - check and bring link up
5976 * @adapter - pointer to the device adapter structure
5977 **/
5978static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5979{
5980 /* if interface is down do nothing */
5981 if (test_bit(__IXGBE_DOWN, &adapter->state))
5982 return;
5983
5984 ixgbe_watchdog_update_link(adapter);
5985
5986 if (adapter->link_up)
5987 ixgbe_watchdog_link_is_up(adapter);
5988 else
5989 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5990
a985b6c3 5991 ixgbe_spoof_check(adapter);
9a799d71 5992 ixgbe_update_stats(adapter);
93c52dd0
AD		 5993
5994 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5995}
10eec955 5996
cf8280ee 5997/**
7086400d
AD		 5998 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5999 * @adapter - the ixgbe adapter structure
cf8280ee 6000 **/
7086400d 6001static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6002{
cf8280ee 6003 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6004 s32 err;
cf8280ee 6005
7086400d
AD		 6006 /* not searching for SFP so there is nothing to do here */
6007 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6008 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6009 return;
10eec955 6010
7086400d
AD		 6011 /* someone else is in init, wait until next service event */
6012 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6013 return;
cf8280ee 6014
7086400d
AD		 6015 err = hw->phy.ops.identify_sfp(hw);
6016 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6017 goto sfp_out;
264857b8 6018
7086400d
AD		 6019 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6020 /* If no cable is present, then we need to reset
6021 * the next time we find a good cable. */
6022 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6023 }
9a799d71 6024
7086400d
AD		 6025 /* exit on error */
6026 if (err)
6027 goto sfp_out;
e8e26350 6028
7086400d
AD		 6029 /* exit if reset not needed */
6030 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6031 goto sfp_out;
9a799d71 6032
7086400d 6033 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6034
7086400d
AD		 6035 /*
6036 * A module may be identified correctly, but the EEPROM may not have
6037 * support for that module. setup_sfp() will fail in that case, so
6038 * we should not allow that module to load.
6039 */
6040 if (hw->mac.type == ixgbe_mac_82598EB)
6041 err = hw->phy.ops.reset(hw);
6042 else
6043 err = hw->mac.ops.setup_sfp(hw);
6044
6045 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6046 goto sfp_out;
6047
6048 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6049 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6050
6051sfp_out:
6052 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6053
6054 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6055 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6056 e_dev_err("failed to initialize because an unsupported "
6057 "SFP+ module type was detected.\n");
6058 e_dev_err("Reload the driver after installing a "
6059 "supported module.\n");
6060 unregister_netdev(adapter->netdev);
bc59fcda 6061 }
7086400d 6062}
bc59fcda 6063
7086400d
AD		 6064/**
6065 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6066 * @adapter - the ixgbe adapter structure
6067 **/
6068static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6069{
6070 struct ixgbe_hw *hw = &adapter->hw;
6071 u32 autoneg;
6072 bool negotiation;
6073
6074 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6075 return;
6076
6077 /* someone else is in init, wait until next service event */
6078 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6079 return;
6080
6081 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6082
6083 autoneg = hw->phy.autoneg_advertised;
6084 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6085 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6086 hw->mac.autotry_restart = false;
6087 if (hw->mac.ops.setup_link)
6088 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6089
6090 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6091 adapter->link_check_timeout = jiffies;
6092 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6093}
6094
6095/**
6096 * ixgbe_service_timer - Timer Call-back
6097 * @data: pointer to adapter cast into an unsigned long
6098 **/
6099static void ixgbe_service_timer(unsigned long data)
6100{
6101 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6102 unsigned long next_event_offset;
6103
6104 /* poll faster when waiting for link */
6105 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6106 next_event_offset = HZ / 10;
6107 else
6108 next_event_offset = HZ * 2;
6109
6110 /* Reset the timer */
6111 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6112
6113 ixgbe_service_event_schedule(adapter);
6114}
6115
c83c6cbd
AD		 6116static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6117{
6118 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6119 return;
6120
6121 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6122
6123 /* If we're already down or resetting, just bail */
6124 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6125 test_bit(__IXGBE_RESETTING, &adapter->state))
6126 return;
6127
6128 ixgbe_dump(adapter);
6129 netdev_err(adapter->netdev, "Reset adapter\n");
6130 adapter->tx_timeout_count++;
6131
6132 ixgbe_reinit_locked(adapter);
6133}
6134
7086400d
AD		 6135/**
6136 * ixgbe_service_task - manages and runs subtasks
6137 * @work: pointer to work_struct containing our data
6138 **/
6139static void ixgbe_service_task(struct work_struct *work)
6140{
6141 struct ixgbe_adapter *adapter = container_of(work,
6142 struct ixgbe_adapter,
6143 service_task);
6144
c83c6cbd 6145 ixgbe_reset_subtask(adapter);
7086400d
AD		 6146 ixgbe_sfp_detection_subtask(adapter);
6147 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6148 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6149 ixgbe_watchdog_subtask(adapter);
d034acf1 6150 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6151 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6152
6153 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6154}
6155
897ab156
AD		 6156void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6157 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6158{
6159 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6160 u16 i = tx_ring->next_to_use;
9a799d71 6161
897ab156 6162 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6163
897ab156
AD		 6164 i++;
6165 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6166
897ab156
AD		 6167 /* set bits to identify this as an advanced context descriptor */
6168 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6169
897ab156
AD		 6170 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6171 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6172 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6173 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6174}
9a799d71 6175
897ab156
AD		 6176static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6177 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6178{
6179 int err;
6180 u32 vlan_macip_lens, type_tucmd;
6181 u32 mss_l4len_idx, l4len;
9a799d71 6182
897ab156
AD		 6183 if (!skb_is_gso(skb))
6184 return 0;
9a799d71 6185
897ab156
AD		 6186 if (skb_header_cloned(skb)) {
6187 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6188 if (err)
6189 return err;
9a799d71 6190 }
9a799d71 6191
897ab156
AD		 6192 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6193 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6194
6195 if (protocol == __constant_htons(ETH_P_IP)) {
6196 struct iphdr *iph = ip_hdr(skb);
6197 iph->tot_len = 0;
6198 iph->check = 0;
6199 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6200 iph->daddr, 0,
6201 IPPROTO_TCP,
6202 0);
6203 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6204 } else if (skb_is_gso_v6(skb)) {
6205 ipv6_hdr(skb)->payload_len = 0;
6206 tcp_hdr(skb)->check =
6207 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6208 &ipv6_hdr(skb)->daddr,
6209 0, IPPROTO_TCP, 0);
6210 }
6211
6212 l4len = tcp_hdrlen(skb);
6213 *hdr_len = skb_transport_offset(skb) + l4len;
6214
6215 /* mss_l4len_id: use 1 as index for TSO */
6216 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6217 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6218 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6219
6220 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6221 vlan_macip_lens = skb_network_header_len(skb);
6222 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6223 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6224
6225 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6226 mss_l4len_idx);
6227
6228 return 1;
6229}
6230
6231static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6232 struct sk_buff *skb, u32 tx_flags,
6233 __be16 protocol)
7ca647bd 6234{
897ab156
AD		 6235 u32 vlan_macip_lens = 0;
6236 u32 mss_l4len_idx = 0;
6237 u32 type_tucmd = 0;
7ca647bd 6238
897ab156 6239 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6240 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6241 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6242 return false;
6243 } else {
6244 u8 l4_hdr = 0;
6245 switch (protocol) {
6246 case __constant_htons(ETH_P_IP):
6247 vlan_macip_lens |= skb_network_header_len(skb);
6248 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6249 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6250 break;
897ab156
AD		 6251 case __constant_htons(ETH_P_IPV6):
6252 vlan_macip_lens |= skb_network_header_len(skb);
6253 l4_hdr = ipv6_hdr(skb)->nexthdr;
6254 break;
6255 default:
6256 if (unlikely(net_ratelimit())) {
6257 dev_warn(tx_ring->dev,
6258 "partial checksum but proto=%x!\n",
6259 skb->protocol);
6260 }
7ca647bd
JP		 6261 break;
6262 }
897ab156
AD		 6263
6264 switch (l4_hdr) {
7ca647bd 6265 case IPPROTO_TCP:
897ab156
AD		 6266 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6267 mss_l4len_idx = tcp_hdrlen(skb) <<
6268 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6269 break;
6270 case IPPROTO_SCTP:
897ab156
AD		 6271 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6272 mss_l4len_idx = sizeof(struct sctphdr) <<
6273 IXGBE_ADVTXD_L4LEN_SHIFT;
6274 break;
6275 case IPPROTO_UDP:
6276 mss_l4len_idx = sizeof(struct udphdr) <<
6277 IXGBE_ADVTXD_L4LEN_SHIFT;
6278 break;
6279 default:
6280 if (unlikely(net_ratelimit())) {
6281 dev_warn(tx_ring->dev,
6282 "partial checksum but l4 proto=%x!\n",
6283 skb->protocol);
6284 }
7ca647bd
JP		 6285 break;
6286 }
7ca647bd
JP		 6287 }
6288
897ab156
AD		 6289 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6290 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6291
897ab156
AD		 6292 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6293 type_tucmd, mss_l4len_idx);
9a799d71 6294
897ab156 6295 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6296}
6297
d3d00239 6298static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6299{
d3d00239
AD		 6300 /* set type for advanced descriptor with frame checksum insertion */
6301 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6302 IXGBE_ADVTXD_DCMD_IFCS |
6303 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6304
d3d00239 6305 /* set HW vlan bit if vlan is present */
66f32a8b 6306 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6307 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6308
d3d00239
AD		 6309 /* set segmentation enable bits for TSO/FSO */
6310#ifdef IXGBE_FCOE
6311 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6312#else
6313 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6314#endif
6315 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6316
d3d00239
AD		 6317 return cmd_type;
6318}
9a799d71 6319
d3d00239
AD		 6320static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6321{
6322 __le32 olinfo_status =
6323 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6324
d3d00239
AD		 6325 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6326 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6327 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6328 /* enble IPv4 checksum for TSO */
6329 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6330 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6331 }
6332
d3d00239
AD		 6333 /* enable L4 checksum for TSO and TX checksum offload */
6334 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6335 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6336
d3d00239
AD		 6337#ifdef IXGBE_FCOE
6338 /* use index 1 context for FCOE/FSO */
6339 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6340 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6341 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6342
d3d00239 6343#endif
7f9643fd
AD		 6344 /*
6345 * Check Context must be set if Tx switch is enabled, which it
6346 * always is for case where virtual functions are running
6347 */
6348 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6349 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6350
d3d00239
AD		 6351 return olinfo_status;
6352}
44df32c5 6353
d3d00239
AD		 6354#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6355 IXGBE_TXD_CMD_RS)
6356
6357static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6358 struct sk_buff *skb,
6359 struct ixgbe_tx_buffer *first,
6360 u32 tx_flags,
6361 const u8 hdr_len)
6362{
6363 struct device *dev = tx_ring->dev;
6364 struct ixgbe_tx_buffer *tx_buffer_info;
6365 union ixgbe_adv_tx_desc *tx_desc;
6366 dma_addr_t dma;
6367 __le32 cmd_type, olinfo_status;
6368 struct skb_frag_struct *frag;
6369 unsigned int f = 0;
6370 unsigned int data_len = skb->data_len;
6371 unsigned int size = skb_headlen(skb);
6372 u32 offset = 0;
6373 u32 paylen = skb->len - hdr_len;
6374 u16 i = tx_ring->next_to_use;
6375 u16 gso_segs;
6376
6377#ifdef IXGBE_FCOE
6378 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6379 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6380 data_len -= sizeof(struct fcoe_crc_eof);
6381 } else {
6382 size -= sizeof(struct fcoe_crc_eof) - data_len;
6383 data_len = 0;
9a799d71
AK		 6384 }
6385 }
44df32c5 6386
d3d00239
AD		 6387#endif
6388 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6389 if (dma_mapping_error(dev, dma))
6390 goto dma_error;
8ad494b0 6391
d3d00239
AD		 6392 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6393 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6394
d3d00239 6395 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6396
d3d00239
AD		 6397 for (;;) {
6398 while (size > IXGBE_MAX_DATA_PER_TXD) {
6399 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6400 tx_desc->read.cmd_type_len =
6401 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6402 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6403
d3d00239
AD		 6404 offset += IXGBE_MAX_DATA_PER_TXD;
6405 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6406
d3d00239
AD		 6407 tx_desc++;
6408 i++;
6409 if (i == tx_ring->count) {
6410 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6411 i = 0;
6412 }
6413 }
e5a43549 6414
e5a43549 6415 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6416 tx_buffer_info->length = offset + size;
6417 tx_buffer_info->tx_flags = tx_flags;
6418 tx_buffer_info->dma = dma;
9a799d71 6419
d3d00239
AD		 6420 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6421 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6422 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6423
d3d00239
AD		 6424 if (!data_len)
6425 break;
9a799d71 6426
d3d00239
AD		 6427 frag = &skb_shinfo(skb)->frags[f];
6428#ifdef IXGBE_FCOE
6429 size = min_t(unsigned int, data_len, frag->size);
6430#else
6431 size = frag->size;
6432#endif
6433 data_len -= size;
6434 f++;
9a799d71 6435
d3d00239
AD		 6436 offset = 0;
6437 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6438
877749bf 6439 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6440 if (dma_mapping_error(dev, dma))
6441 goto dma_error;
9a799d71 6442
d3d00239
AD		 6443 tx_desc++;
6444 i++;
6445 if (i == tx_ring->count) {
6446 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6447 i = 0;
6448 }
6449 }
9a799d71 6450
d3d00239 6451 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6452
d3d00239
AD		 6453 i++;
6454 if (i == tx_ring->count)
6455 i = 0;
9a799d71 6456
d3d00239 6457 tx_ring->next_to_use = i;
eacd73f7 6458
d3d00239
AD		 6459 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6460 gso_segs = skb_shinfo(skb)->gso_segs;
6461#ifdef IXGBE_FCOE
6462 /* adjust for FCoE Sequence Offload */
6463 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6464 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6465 skb_shinfo(skb)->gso_size);
6466#endif /* IXGBE_FCOE */
6467 else
6468 gso_segs = 1;
9a799d71 6469
d3d00239
AD		 6470 /* multiply data chunks by size of headers */
6471 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6472 tx_buffer_info->gso_segs = gso_segs;
6473 tx_buffer_info->skb = skb;
9a799d71 6474
d3d00239
AD		 6475 /* set the timestamp */
6476 first->time_stamp = jiffies;
9a799d71
AK		 6477
6478 /*
6479 * Force memory writes to complete before letting h/w
6480 * know there are new descriptors to fetch. (Only
6481 * applicable for weak-ordered memory model archs,
6482 * such as IA-64).
6483 */
6484 wmb();
6485
d3d00239
AD		 6486 /* set next_to_watch value indicating a packet is present */
6487 first->next_to_watch = tx_desc;
6488
6489 /* notify HW of packet */
84ea2591 6490 writel(i, tx_ring->tail);
d3d00239
AD		 6491
6492 return;
6493dma_error:
6494 dev_err(dev, "TX DMA map failed\n");
6495
6496 /* clear dma mappings for failed tx_buffer_info map */
6497 for (;;) {
6498 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6499 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6500 if (tx_buffer_info == first)
6501 break;
6502 if (i == 0)
6503 i = tx_ring->count;
6504 i--;
6505 }
6506
6507 dev_kfree_skb_any(skb);
6508
6509 tx_ring->next_to_use = i;
9a799d71
AK		 6510}
6511
69830529
AD		 6512static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6513 u32 tx_flags, __be16 protocol)
6514{
6515 struct ixgbe_q_vector *q_vector = ring->q_vector;
6516 union ixgbe_atr_hash_dword input = { .dword = 0 };
6517 union ixgbe_atr_hash_dword common = { .dword = 0 };
6518 union {
6519 unsigned char *network;
6520 struct iphdr *ipv4;
6521 struct ipv6hdr *ipv6;
6522 } hdr;
ee9e0f0b 6523 struct tcphdr *th;
905e4a41 6524 __be16 vlan_id;
c4cf55e5 6525
69830529
AD		 6526 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6527 if (!q_vector)
6528 return;
6529
6530 /* do nothing if sampling is disabled */
6531 if (!ring->atr_sample_rate)
d3ead241 6532 return;
c4cf55e5 6533
69830529 6534 ring->atr_count++;
c4cf55e5 6535
69830529
AD		 6536 /* snag network header to get L4 type and address */
6537 hdr.network = skb_network_header(skb);
6538
6539 /* Currently only IPv4/IPv6 with TCP is supported */
6540 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6541 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6542 (protocol != __constant_htons(ETH_P_IP) ||
6543 hdr.ipv4->protocol != IPPROTO_TCP))
6544 return;
ee9e0f0b
AD		 6545
6546 th = tcp_hdr(skb);
c4cf55e5 6547
66f32a8b
AD		 6548 /* skip this packet since it is invalid or the socket is closing */
6549 if (!th || th->fin)
69830529
AD		 6550 return;
6551
6552 /* sample on all syn packets or once every atr sample count */
6553 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6554 return;
6555
6556 /* reset sample count */
6557 ring->atr_count = 0;
6558
6559 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6560
6561 /*
6562 * src and dst are inverted, think how the receiver sees them
6563 *
6564 * The input is broken into two sections, a non-compressed section
6565 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6566 * is XORed together and stored in the compressed dword.
6567 */
6568 input.formatted.vlan_id = vlan_id;
6569
6570 /*
6571 * since src port and flex bytes occupy the same word XOR them together
6572 * and write the value to source port portion of compressed dword
6573 */
66f32a8b 6574 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6575 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6576 else
6577 common.port.src ^= th->dest ^ protocol;
6578 common.port.dst ^= th->source;
6579
6580 if (protocol == __constant_htons(ETH_P_IP)) {
6581 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6582 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6583 } else {
6584 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6585 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6586 hdr.ipv6->saddr.s6_addr32[1] ^
6587 hdr.ipv6->saddr.s6_addr32[2] ^
6588 hdr.ipv6->saddr.s6_addr32[3] ^
6589 hdr.ipv6->daddr.s6_addr32[0] ^
6590 hdr.ipv6->daddr.s6_addr32[1] ^
6591 hdr.ipv6->daddr.s6_addr32[2] ^
6592 hdr.ipv6->daddr.s6_addr32[3];
6593 }
c4cf55e5
PWJ		 6594
6595 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6596 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6597 input, common, ring->queue_index);
c4cf55e5
PWJ		 6598}
6599
63544e9c 6600static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6601{
fc77dc3c 6602 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6603 /* Herbert's original patch had:
6604 * smp_mb__after_netif_stop_queue();
6605 * but since that doesn't exist yet, just open code it. */
6606 smp_mb();
6607
6608 /* We need to check again in a case another CPU has just
6609 * made room available. */
7d4987de 6610 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6611 return -EBUSY;
6612
6613 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6614 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6615 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6616 return 0;
6617}
6618
82d4e46e 6619static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6620{
7d4987de 6621 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6622 return 0;
fc77dc3c 6623 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6624}
6625
09a3b1f8
SH		 6626static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6627{
6628 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6629 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6630 smp_processor_id();
56075a98 6631#ifdef IXGBE_FCOE
6440752c 6632 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6633
e5b64635
JF		 6634 if (((protocol == htons(ETH_P_FCOE)) ||
6635 (protocol == htons(ETH_P_FIP))) &&
6636 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6637 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6638 txq += adapter->ring_feature[RING_F_FCOE].mask;
6639 return txq;
56075a98
JF		 6640 }
6641#endif
6642
fdd3d631
KK		 6643 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6644 while (unlikely(txq >= dev->real_num_tx_queues))
6645 txq -= dev->real_num_tx_queues;
5f715823 6646 return txq;
fdd3d631 6647 }
c4cf55e5 6648
09a3b1f8
SH		 6649 return skb_tx_hash(dev, skb);
6650}
6651
fc77dc3c 6652netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6653 struct ixgbe_adapter *adapter,
6654 struct ixgbe_ring *tx_ring)
9a799d71 6655{
d3d00239 6656 struct ixgbe_tx_buffer *first;
5f715823 6657 int tso;
d3d00239 6658 u32 tx_flags = 0;
a535c30e
AD		 6659#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6660 unsigned short f;
6661#endif
a535c30e 6662 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6663 __be16 protocol = skb->protocol;
63544e9c 6664 u8 hdr_len = 0;
5e09a105 6665
a535c30e
AD		 6666 /*
6667 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6668 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6669 * + 2 desc gap to keep tail from touching head,
6670 * + 1 desc for context descriptor,
6671 * otherwise try next time
6672 */
6673#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6674 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6675 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6676#else
6677 count += skb_shinfo(skb)->nr_frags;
6678#endif
6679 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6680 tx_ring->tx_stats.tx_busy++;
6681 return NETDEV_TX_BUSY;
6682 }
6683
7f9643fd
AD		 6684#ifdef CONFIG_PCI_IOV
6685 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6686 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6687
6688#endif
66f32a8b 6689 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6690 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6691 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6692 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6693 /* else if it is a SW VLAN check the next protocol and store the tag */
6694 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6695 struct vlan_hdr *vhdr, _vhdr;
6696 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6697 if (!vhdr)
6698 goto out_drop;
6699
6700 protocol = vhdr->h_vlan_encapsulated_proto;
6701 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6702 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6703 }
6704
6705 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6706 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6707 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b
AD		 6708 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6709 tx_flags |= tx_ring->dcb_tc <<
6710 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6711 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6712 struct vlan_ethhdr *vhdr;
6713 if (skb_header_cloned(skb) &&
6714 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6715 goto out_drop;
6716 vhdr = (struct vlan_ethhdr *)skb->data;
6717 vhdr->h_vlan_TCI = htons(tx_flags >>
6718 IXGBE_TX_FLAGS_VLAN_SHIFT);
6719 } else {
6720 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6721 }
9a799d71 6722 }
eacd73f7 6723
a535c30e 6724 /* record the location of the first descriptor for this packet */
d3d00239 6725 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6726
eacd73f7 6727#ifdef IXGBE_FCOE
66f32a8b
AD		 6728 /* setup tx offload for FCoE */
6729 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6730 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6731 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6732 if (tso < 0)
6733 goto out_drop;
6734 else if (tso)
66f32a8b
AD		 6735 tx_flags |= IXGBE_TX_FLAGS_FSO |
6736 IXGBE_TX_FLAGS_FCOE;
6737 else
6738 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6739
66f32a8b 6740 goto xmit_fcoe;
eacd73f7 6741 }
9a799d71 6742
66f32a8b
AD		 6743#endif /* IXGBE_FCOE */
6744 /* setup IPv4/IPv6 offloads */
6745 if (protocol == __constant_htons(ETH_P_IP))
6746 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6747
66f32a8b
AD		 6748 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6749 if (tso < 0)
897ab156 6750 goto out_drop;
66f32a8b
AD		 6751 else if (tso)
6752 tx_flags |= IXGBE_TX_FLAGS_TSO;
6753 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6754 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6755
6756 /* add the ATR filter if ATR is on */
6757 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6758 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6759
6760#ifdef IXGBE_FCOE
6761xmit_fcoe:
6762#endif /* IXGBE_FCOE */
d3d00239
AD		 6763 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6764
6765 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6766
6767 return NETDEV_TX_OK;
897ab156
AD		 6768
6769out_drop:
6770 dev_kfree_skb_any(skb);
6771 return NETDEV_TX_OK;
9a799d71
AK		 6772}
6773
84418e3b
AD		 6774static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6775{
6776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6777 struct ixgbe_ring *tx_ring;
6778
6779 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6780 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6781}
6782
9a799d71
AK		 6783/**
6784 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6785 * @netdev: network interface device structure
6786 * @p: pointer to an address structure
6787 *
6788 * Returns 0 on success, negative on failure
6789 **/
6790static int ixgbe_set_mac(struct net_device *netdev, void *p)
6791{
6792 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6793 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6794 struct sockaddr *addr = p;
6795
6796 if (!is_valid_ether_addr(addr->sa_data))
6797 return -EADDRNOTAVAIL;
6798
6799 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6800 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6801
1cdd1ec8
GR		 6802 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6803 IXGBE_RAH_AV);
9a799d71
AK		 6804
6805 return 0;
6806}
6807
6b73e10d
BH		 6808static int
6809ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6810{
6811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6812 struct ixgbe_hw *hw = &adapter->hw;
6813 u16 value;
6814 int rc;
6815
6816 if (prtad != hw->phy.mdio.prtad)
6817 return -EINVAL;
6818 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6819 if (!rc)
6820 rc = value;
6821 return rc;
6822}
6823
6824static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6825 u16 addr, u16 value)
6826{
6827 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6828 struct ixgbe_hw *hw = &adapter->hw;
6829
6830 if (prtad != hw->phy.mdio.prtad)
6831 return -EINVAL;
6832 return hw->phy.ops.write_reg(hw, addr, devad, value);
6833}
6834
6835static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6836{
6837 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6838
6839 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6840}
6841
0365e6e4
PW		 6842/**
6843 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6844 * netdev->dev_addrs
0365e6e4
PW		 6845 * @netdev: network interface device structure
6846 *
6847 * Returns non-zero on failure
6848 **/
6849static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6850{
6851 int err = 0;
6852 struct ixgbe_adapter *adapter = netdev_priv(dev);
6853 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6854
6855 if (is_valid_ether_addr(mac->san_addr)) {
6856 rtnl_lock();
6857 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6858 rtnl_unlock();
6859 }
6860 return err;
6861}
6862
6863/**
6864 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6865 * netdev->dev_addrs
0365e6e4
PW		 6866 * @netdev: network interface device structure
6867 *
6868 * Returns non-zero on failure
6869 **/
6870static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6871{
6872 int err = 0;
6873 struct ixgbe_adapter *adapter = netdev_priv(dev);
6874 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6875
6876 if (is_valid_ether_addr(mac->san_addr)) {
6877 rtnl_lock();
6878 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6879 rtnl_unlock();
6880 }
6881 return err;
6882}
6883
9a799d71
AK		 6884#ifdef CONFIG_NET_POLL_CONTROLLER
6885/*
6886 * Polling 'interrupt' - used by things like netconsole to send skbs
6887 * without having to re-enable interrupts. It's not called while
6888 * the interrupt routine is executing.
6889 */
6890static void ixgbe_netpoll(struct net_device *netdev)
6891{
6892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6893 int i;
9a799d71 6894
1a647bd2
AD		 6895 /* if interface is down do nothing */
6896 if (test_bit(__IXGBE_DOWN, &adapter->state))
6897 return;
6898
9a799d71 6899 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6900 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6901 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6902 for (i = 0; i < num_q_vectors; i++) {
6903 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 6904 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 6905 }
6906 } else {
6907 ixgbe_intr(adapter->pdev->irq, netdev);
6908 }
9a799d71 6909 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6910}
6911#endif
6912
de1036b1
ED		 6913static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6914 struct rtnl_link_stats64 *stats)
6915{
6916 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6917 int i;
6918
1a51502b 6919 rcu_read_lock();
de1036b1 6920 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6921 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6922 u64 bytes, packets;
6923 unsigned int start;
6924
1a51502b
ED		 6925 if (ring) {
6926 do {
6927 start = u64_stats_fetch_begin_bh(&ring->syncp);
6928 packets = ring->stats.packets;
6929 bytes = ring->stats.bytes;
6930 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6931 stats->rx_packets += packets;
6932 stats->rx_bytes += bytes;
6933 }
de1036b1 6934 }
1ac9ad13
ED		 6935
6936 for (i = 0; i < adapter->num_tx_queues; i++) {
6937 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6938 u64 bytes, packets;
6939 unsigned int start;
6940
6941 if (ring) {
6942 do {
6943 start = u64_stats_fetch_begin_bh(&ring->syncp);
6944 packets = ring->stats.packets;
6945 bytes = ring->stats.bytes;
6946 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6947 stats->tx_packets += packets;
6948 stats->tx_bytes += bytes;
6949 }
6950 }
1a51502b 6951 rcu_read_unlock();
de1036b1
ED		 6952 /* following stats updated by ixgbe_watchdog_task() */
6953 stats->multicast = netdev->stats.multicast;
6954 stats->rx_errors = netdev->stats.rx_errors;
6955 stats->rx_length_errors = netdev->stats.rx_length_errors;
6956 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6957 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6958 return stats;
6959}
6960
8b1c0b24
JF		 6961/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6962 * #adapter: pointer to ixgbe_adapter
6963 * @tc: number of traffic classes currently enabled
6964 *
6965 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6966 * 802.1Q priority maps to a packet buffer that exists.
6967 */
6968static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6969{
6970 struct ixgbe_hw *hw = &adapter->hw;
6971 u32 reg, rsave;
6972 int i;
6973
6974 /* 82598 have a static priority to TC mapping that can not
6975 * be changed so no validation is needed.
6976 */
6977 if (hw->mac.type == ixgbe_mac_82598EB)
6978 return;
6979
6980 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6981 rsave = reg;
6982
6983 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6984 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6985
6986 /* If up2tc is out of bounds default to zero */
6987 if (up2tc > tc)
6988 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6989 }
6990
6991 if (reg != rsave)
6992 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6993
6994 return;
6995}
6996
6997
6998/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6999 * classes.
7000 *
7001 * @netdev: net device to configure
7002 * @tc: number of traffic classes to enable
7003 */
7004int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7005{
8b1c0b24
JF		 7006 struct ixgbe_adapter *adapter = netdev_priv(dev);
7007 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7008
e7589eab
JF		 7009 /* Multiple traffic classes requires multiple queues */
7010 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7011 e_err(drv, "Enable failed, needs MSI-X\n");
7012 return -EINVAL;
7013 }
8b1c0b24
JF		 7014
7015 /* Hardware supports up to 8 traffic classes */
7016 if (tc > MAX_TRAFFIC_CLASS ||
7017 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7018 return -EINVAL;
7019
7020 /* Hardware has to reinitialize queues and interrupts to
7021 * match packet buffer alignment. Unfortunantly, the
7022 * hardware is not flexible enough to do this dynamically.
7023 */
7024 if (netif_running(dev))
7025 ixgbe_close(dev);
7026 ixgbe_clear_interrupt_scheme(adapter);
7027
e7589eab 7028 if (tc) {
8b1c0b24 7029 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7030 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7031
7032 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7033 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7034
7035 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7036 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7037 } else {
8b1c0b24
JF		 7038 netdev_reset_tc(dev);
7039
e7589eab
JF		 7040 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7041
7042 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7043 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7044
7045 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7046 adapter->dcb_cfg.pfc_mode_enable = false;
7047 }
7048
8b1c0b24
JF		 7049 ixgbe_init_interrupt_scheme(adapter);
7050 ixgbe_validate_rtr(adapter, tc);
7051 if (netif_running(dev))
7052 ixgbe_open(dev);
7053
7054 return 0;
7055}
de1036b1 7056
082757af
DS		 7057void ixgbe_do_reset(struct net_device *netdev)
7058{
7059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7060
7061 if (netif_running(netdev))
7062 ixgbe_reinit_locked(adapter);
7063 else
7064 ixgbe_reset(adapter);
7065}
7066
7067static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7068{
7069 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7070
7071#ifdef CONFIG_DCB
7072 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7073 data &= ~NETIF_F_HW_VLAN_RX;
7074#endif
7075
7076 /* return error if RXHASH is being enabled when RSS is not supported */
7077 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7078 data &= ~NETIF_F_RXHASH;
7079
7080 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7081 if (!(data & NETIF_F_RXCSUM))
7082 data &= ~NETIF_F_LRO;
7083
7084 /* Turn off LRO if not RSC capable or invalid ITR settings */
7085 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7086 data &= ~NETIF_F_LRO;
7087 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7088 (adapter->rx_itr_setting != 1 &&
7089 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7090 data &= ~NETIF_F_LRO;
7091 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7092 }
7093
7094 return data;
7095}
7096
7097static int ixgbe_set_features(struct net_device *netdev, u32 data)
7098{
7099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7100 bool need_reset = false;
7101
7102 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7103 if (!(data & NETIF_F_RXCSUM))
7104 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7105 else
7106 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7107
7108 /* Make sure RSC matches LRO, reset if change */
7109 if (!!(data & NETIF_F_LRO) !=
7110 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7111 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7112 switch (adapter->hw.mac.type) {
7113 case ixgbe_mac_X540:
7114 case ixgbe_mac_82599EB:
7115 need_reset = true;
7116 break;
7117 default:
7118 break;
7119 }
7120 }
7121
7122 /*
7123 * Check if Flow Director n-tuple support was enabled or disabled. If
7124 * the state changed, we need to reset.
7125 */
7126 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7127 /* turn off ATR, enable perfect filters and reset */
7128 if (data & NETIF_F_NTUPLE) {
7129 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7130 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7131 need_reset = true;
7132 }
7133 } else if (!(data & NETIF_F_NTUPLE)) {
7134 /* turn off Flow Director, set ATR and reset */
7135 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7136 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7137 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7138 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7139 need_reset = true;
7140 }
7141
7142 if (need_reset)
7143 ixgbe_do_reset(netdev);
7144
7145 return 0;
7146
7147}
7148
0edc3527 7149static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7150 .ndo_open = ixgbe_open,
0edc3527 7151 .ndo_stop = ixgbe_close,
00829823 7152 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7153 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7154 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7155 .ndo_validate_addr = eth_validate_addr,
7156 .ndo_set_mac_address = ixgbe_set_mac,
7157 .ndo_change_mtu = ixgbe_change_mtu,
7158 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7159 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7160 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7161 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7162 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7163 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7164 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7165 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7166 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7167 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7168#ifdef CONFIG_NET_POLL_CONTROLLER
7169 .ndo_poll_controller = ixgbe_netpoll,
7170#endif
332d4a7d
YZ		 7171#ifdef IXGBE_FCOE
7172 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7173 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7174 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7175 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7176 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7177 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7178#endif /* IXGBE_FCOE */
082757af
DS		 7179 .ndo_set_features = ixgbe_set_features,
7180 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7181};
7182
1cdd1ec8
GR		 7183static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7184 const struct ixgbe_info *ii)
7185{
7186#ifdef CONFIG_PCI_IOV
7187 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7188
c6bda30a 7189 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7190 return;
7191
7192 /* The 82599 supports up to 64 VFs per physical function
7193 * but this implementation limits allocation to 63 so that
7194 * basic networking resources are still available to the
7195 * physical function
7196 */
7197 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7198 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7199#endif /* CONFIG_PCI_IOV */
7200}
7201
9a799d71
AK		 7202/**
7203 * ixgbe_probe - Device Initialization Routine
7204 * @pdev: PCI device information struct
7205 * @ent: entry in ixgbe_pci_tbl
7206 *
7207 * Returns 0 on success, negative on failure
7208 *
7209 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7210 * The OS initialization, configuring of the adapter private structure,
7211 * and a hardware reset occur.
7212 **/
7213static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7214 const struct pci_device_id *ent)
9a799d71
AK		 7215{
7216 struct net_device *netdev;
7217 struct ixgbe_adapter *adapter = NULL;
7218 struct ixgbe_hw *hw;
7219 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7220 static int cards_found;
7221 int i, err, pci_using_dac;
289700db 7222 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7223 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7224#ifdef IXGBE_FCOE
7225 u16 device_caps;
7226#endif
289700db 7227 u32 eec;
c23f5b6b 7228 u16 wol_cap;
9a799d71 7229
bded64a7
AG		 7230 /* Catch broken hardware that put the wrong VF device ID in
7231 * the PCIe SR-IOV capability.
7232 */
7233 if (pdev->is_virtfn) {
7234 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7235 pci_name(pdev), pdev->vendor, pdev->device);
7236 return -EINVAL;
7237 }
7238
9ce77666 7239 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7240 if (err)
7241 return err;
7242
1b507730
NN		 7243 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7244 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7245 pci_using_dac = 1;
7246 } else {
1b507730 7247 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7248 if (err) {
1b507730
NN		 7249 err = dma_set_coherent_mask(&pdev->dev,
7250 DMA_BIT_MASK(32));
9a799d71 7251 if (err) {
b8bc0421
DC		 7252 dev_err(&pdev->dev,
7253 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7254 goto err_dma;
7255 }
7256 }
7257 pci_using_dac = 0;
7258 }
7259
9ce77666 7260 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7261 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7262 if (err) {
b8bc0421
DC		 7263 dev_err(&pdev->dev,
7264 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7265 goto err_pci_reg;
7266 }
7267
19d5afd4 7268 pci_enable_pcie_error_reporting(pdev);
6fabd715 7269
9a799d71 7270 pci_set_master(pdev);
fb3b27bc 7271 pci_save_state(pdev);
9a799d71 7272
e901acd6
JF		 7273#ifdef CONFIG_IXGBE_DCB
7274 indices *= MAX_TRAFFIC_CLASS;
7275#endif
7276
c85a2618
JF		 7277 if (ii->mac == ixgbe_mac_82598EB)
7278 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7279 else
7280 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7281
e901acd6 7282#ifdef IXGBE_FCOE
c85a2618
JF		 7283 indices += min_t(unsigned int, num_possible_cpus(),
7284 IXGBE_MAX_FCOE_INDICES);
7285#endif
c85a2618 7286 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7287 if (!netdev) {
7288 err = -ENOMEM;
7289 goto err_alloc_etherdev;
7290 }
7291
9a799d71
AK		 7292 SET_NETDEV_DEV(netdev, &pdev->dev);
7293
9a799d71 7294 adapter = netdev_priv(netdev);
c60fbb00 7295 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7296
7297 adapter->netdev = netdev;
7298 adapter->pdev = pdev;
7299 hw = &adapter->hw;
7300 hw->back = adapter;
7301 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7302
05857980 7303 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7304 pci_resource_len(pdev, 0));
9a799d71
AK		 7305 if (!hw->hw_addr) {
7306 err = -EIO;
7307 goto err_ioremap;
7308 }
7309
7310 for (i = 1; i <= 5; i++) {
7311 if (pci_resource_len(pdev, i) == 0)
7312 continue;
7313 }
7314
0edc3527 7315 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7316 ixgbe_set_ethtool_ops(netdev);
9a799d71 7317 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7318 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7319
9a799d71
AK		 7320 adapter->bd_number = cards_found;
7321
9a799d71
AK		 7322 /* Setup hw api */
7323 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7324 hw->mac.type = ii->mac;
9a799d71 7325
c44ade9e
JB		 7326 /* EEPROM */
7327 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7328 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7329 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7330 if (!(eec & (1 << 8)))
7331 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7332
7333 /* PHY */
7334 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7335 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7336 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7337 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7338 hw->phy.mdio.mmds = 0;
7339 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7340 hw->phy.mdio.dev = netdev;
7341 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7342 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7343
8ca783ab 7344 ii->get_invariants(hw);
9a799d71
AK		 7345
7346 /* setup the private structure */
7347 err = ixgbe_sw_init(adapter);
7348 if (err)
7349 goto err_sw_init;
7350
e86bff0e 7351 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7352 switch (adapter->hw.mac.type) {
7353 case ixgbe_mac_82599EB:
7354 case ixgbe_mac_X540:
e86bff0e 7355 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7356 break;
7357 default:
7358 break;
7359 }
e86bff0e 7360
bf069c97
DS		 7361 /*
7362 * If there is a fan on this device and it has failed log the
7363 * failure.
7364 */
7365 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7366 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7367 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7368 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7369 }
7370
c44ade9e 7371 /* reset_hw fills in the perm_addr as well */
119fc60a 7372 hw->phy.reset_if_overtemp = true;
c44ade9e 7373 err = hw->mac.ops.reset_hw(hw);
119fc60a 7374 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7375 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7376 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7377 err = 0;
7378 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7379 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7380 "module type was detected.\n");
7381 e_dev_err("Reload the driver after installing a supported "
7382 "module.\n");
04f165ef
PW		 7383 goto err_sw_init;
7384 } else if (err) {
849c4542 7385 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7386 goto err_sw_init;
7387 }
7388
1cdd1ec8
GR		 7389 ixgbe_probe_vf(adapter, ii);
7390
396e799c 7391 netdev->features = NETIF_F_SG |
e8e9f696 7392 NETIF_F_IP_CSUM |
082757af 7393 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7394 NETIF_F_HW_VLAN_TX |
7395 NETIF_F_HW_VLAN_RX |
082757af
DS		 7396 NETIF_F_HW_VLAN_FILTER |
7397 NETIF_F_TSO |
7398 NETIF_F_TSO6 |
082757af
DS		 7399 NETIF_F_RXHASH |
7400 NETIF_F_RXCSUM;
9a799d71 7401
082757af 7402 netdev->hw_features = netdev->features;
ad31c402 7403
58be7666
DS		 7404 switch (adapter->hw.mac.type) {
7405 case ixgbe_mac_82599EB:
7406 case ixgbe_mac_X540:
45a5ead0 7407 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7408 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7409 NETIF_F_NTUPLE;
58be7666
DS		 7410 break;
7411 default:
7412 break;
7413 }
45a5ead0 7414
ad31c402
JK		 7415 netdev->vlan_features |= NETIF_F_TSO;
7416 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7417 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7418 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7419 netdev->vlan_features |= NETIF_F_SG;
7420
01789349
JP		 7421 netdev->priv_flags |= IFF_UNICAST_FLT;
7422
1cdd1ec8
GR		 7423 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7424 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7425 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7426
7a6b6f51 7427#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7428 netdev->dcbnl_ops = &dcbnl_ops;
7429#endif
7430
eacd73f7 7431#ifdef IXGBE_FCOE
0d551589 7432 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7433 if (hw->mac.ops.get_device_caps) {
7434 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7435 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7436 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7437 }
7438 }
5e09d7f6
YZ		 7439 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7440 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7441 netdev->vlan_features |= NETIF_F_FSO;
7442 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7443 }
eacd73f7 7444#endif /* IXGBE_FCOE */
7b872a55 7445 if (pci_using_dac) {
9a799d71 7446 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7447 netdev->vlan_features |= NETIF_F_HIGHDMA;
7448 }
9a799d71 7449
082757af
DS		 7450 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7451 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7452 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7453 netdev->features |= NETIF_F_LRO;
7454
9a799d71 7455 /* make sure the EEPROM is good */
c44ade9e 7456 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7457 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7458 err = -EIO;
7459 goto err_eeprom;
7460 }
7461
7462 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7463 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7464
c44ade9e 7465 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7466 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7467 err = -EIO;
7468 goto err_eeprom;
7469 }
7470
c6ecf39a
DS		 7471 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7472 if (hw->mac.ops.disable_tx_laser &&
7473 ((hw->phy.multispeed_fiber) ||
9f911707 7474 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7475 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7476 hw->mac.ops.disable_tx_laser(hw);
7477
7086400d
AD		 7478 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7479 (unsigned long) adapter);
9a799d71 7480
7086400d
AD		 7481 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7482 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7483
021230d4
AV		 7484 err = ixgbe_init_interrupt_scheme(adapter);
7485 if (err)
7486 goto err_sw_init;
9a799d71 7487
082757af
DS		 7488 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7489 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7490 netdev->features &= ~NETIF_F_RXHASH;
082757af 7491 }
67a74ee2 7492
c23f5b6b
ET		 7493 /* WOL not supported for all but the following */
7494 adapter->wol = 0;
e8e26350 7495 switch (pdev->device) {
0b077fea
DS		 7496 case IXGBE_DEV_ID_82599_SFP:
7497 /* Only this subdevice supports WOL */
7498 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7499 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7500 break;
50d6c681
AD		 7501 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7502 /* All except this subdevice support WOL */
0b077fea 7503 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7504 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7505 break;
e8e26350 7506 case IXGBE_DEV_ID_82599_KX4:
9417c464 7507 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7508 break;
c23f5b6b
ET		 7509 case IXGBE_DEV_ID_X540T:
7510 /* Check eeprom to see if it is enabled */
7511 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7512 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7513
7514 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7515 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7516 (hw->bus.func == 0)))
7517 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7518 break;
7519 }
e8e26350
PW		 7520 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7521
04f165ef
PW		 7522 /* pick up the PCI bus settings for reporting later */
7523 hw->mac.ops.get_bus_info(hw);
7524
9a799d71 7525 /* print bus type/speed/width info */
849c4542 7526 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7527 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7528 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7529 "Unknown"),
7530 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7531 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7532 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7533 "Unknown"),
7534 netdev->dev_addr);
289700db
DS		 7535
7536 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7537 if (err)
9fe93afd 7538 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7539 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7540 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7541 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7542 part_str);
e8e26350 7543 else
289700db
DS		 7544 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7545 hw->mac.type, hw->phy.type, part_str);
9a799d71 7546
e8e26350 7547 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7548 e_dev_warn("PCI-Express bandwidth available for this card is "
7549 "not sufficient for optimal performance.\n");
7550 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7551 "is required.\n");
0c254d86
AK		 7552 }
7553
34b0368c
PWJ		 7554 /* save off EEPROM version number */
7555 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7556
9a799d71 7557 /* reset the hardware with the new settings */
794caeb2 7558 err = hw->mac.ops.start_hw(hw);
c44ade9e 7559
794caeb2
PWJ		 7560 if (err == IXGBE_ERR_EEPROM_VERSION) {
7561 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7562 e_dev_warn("This device is a pre-production adapter/LOM. "
7563 "Please be aware there may be issues associated "
7564 "with your hardware. If you are experiencing "
7565 "problems please contact your Intel or hardware "
7566 "representative who provided you with this "
7567 "hardware.\n");
794caeb2 7568 }
9a799d71
AK		 7569 strcpy(netdev->name, "eth%d");
7570 err = register_netdev(netdev);
7571 if (err)
7572 goto err_register;
7573
54386467
JB		 7574 /* carrier off reporting is important to ethtool even BEFORE open */
7575 netif_carrier_off(netdev);
7576
5dd2d332 7577#ifdef CONFIG_IXGBE_DCA
652f093f 7578 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7579 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7580 ixgbe_setup_dca(adapter);
7581 }
7582#endif
1cdd1ec8 7583 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7584 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7585 for (i = 0; i < adapter->num_vfs; i++)
7586 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7587 }
7588
9612de92
ET		 7589 /* Inform firmware of driver version */
7590 if (hw->mac.ops.set_fw_drv_ver)
a38a104d
DS		 7591 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7592 FW_CEM_UNUSED_VER);
9612de92 7593
0365e6e4
PW		 7594 /* add san mac addr to netdev */
7595 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7596
849c4542 7597 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7598 cards_found++;
7599 return 0;
7600
7601err_register:
5eba3699 7602 ixgbe_release_hw_control(adapter);
7a921c93 7603 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7604err_sw_init:
7605err_eeprom:
1cdd1ec8
GR		 7606 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7607 ixgbe_disable_sriov(adapter);
7086400d 7608 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7609 iounmap(hw->hw_addr);
7610err_ioremap:
7611 free_netdev(netdev);
7612err_alloc_etherdev:
e8e9f696
JP		 7613 pci_release_selected_regions(pdev,
7614 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7615err_pci_reg:
7616err_dma:
7617 pci_disable_device(pdev);
7618 return err;
7619}
7620
7621/**
7622 * ixgbe_remove - Device Removal Routine
7623 * @pdev: PCI device information struct
7624 *
7625 * ixgbe_remove is called by the PCI subsystem to alert the driver
7626 * that it should release a PCI device. The could be caused by a
7627 * Hot-Plug event, or because the driver is going to be removed from
7628 * memory.
7629 **/
7630static void __devexit ixgbe_remove(struct pci_dev *pdev)
7631{
c60fbb00
AD		 7632 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7633 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7634
7635 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7636 cancel_work_sync(&adapter->service_task);
9a799d71 7637
5dd2d332 7638#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7639 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7640 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7641 dca_remove_requester(&pdev->dev);
7642 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7643 }
7644
7645#endif
332d4a7d
YZ		 7646#ifdef IXGBE_FCOE
7647 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7648 ixgbe_cleanup_fcoe(adapter);
7649
7650#endif /* IXGBE_FCOE */
0365e6e4
PW		 7651
7652 /* remove the added san mac */
7653 ixgbe_del_sanmac_netdev(netdev);
7654
c4900be0
DS		 7655 if (netdev->reg_state == NETREG_REGISTERED)
7656 unregister_netdev(netdev);
9a799d71 7657
c6bda30a
GR		 7658 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7659 if (!(ixgbe_check_vf_assignment(adapter)))
7660 ixgbe_disable_sriov(adapter);
7661 else
7662 e_dev_warn("Unloading driver while VFs are assigned "
7663 "- VFs will not be deallocated\n");
7664 }
1cdd1ec8 7665
7a921c93 7666 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7667
021230d4 7668 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7669
7670 iounmap(adapter->hw.hw_addr);
9ce77666 7671 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7672 IORESOURCE_MEM));
9a799d71 7673
849c4542 7674 e_dev_info("complete\n");
021230d4 7675
9a799d71
AK		 7676 free_netdev(netdev);
7677
19d5afd4 7678 pci_disable_pcie_error_reporting(pdev);
6fabd715 7679
9a799d71
AK		 7680 pci_disable_device(pdev);
7681}
7682
7683/**
7684 * ixgbe_io_error_detected - called when PCI error is detected
7685 * @pdev: Pointer to PCI device
7686 * @state: The current pci connection state
7687 *
7688 * This function is called after a PCI bus error affecting
7689 * this device has been detected.
7690 */
7691static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7692 pci_channel_state_t state)
9a799d71 7693{
c60fbb00
AD		 7694 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7695 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7696
7697 netif_device_detach(netdev);
7698
3044b8d1
BL		 7699 if (state == pci_channel_io_perm_failure)
7700 return PCI_ERS_RESULT_DISCONNECT;
7701
9a799d71
AK		 7702 if (netif_running(netdev))
7703 ixgbe_down(adapter);
7704 pci_disable_device(pdev);
7705
b4617240 7706 /* Request a slot reset. */
9a799d71
AK		 7707 return PCI_ERS_RESULT_NEED_RESET;
7708}
7709
7710/**
7711 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7712 * @pdev: Pointer to PCI device
7713 *
7714 * Restart the card from scratch, as if from a cold-boot.
7715 */
7716static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7717{
c60fbb00 7718 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7719 pci_ers_result_t result;
7720 int err;
9a799d71 7721
9ce77666 7722 if (pci_enable_device_mem(pdev)) {
396e799c 7723 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7724 result = PCI_ERS_RESULT_DISCONNECT;
7725 } else {
7726 pci_set_master(pdev);
7727 pci_restore_state(pdev);
c0e1f68b 7728 pci_save_state(pdev);
9a799d71 7729
dd4d8ca6 7730 pci_wake_from_d3(pdev, false);
9a799d71 7731
6fabd715 7732 ixgbe_reset(adapter);
88512539 7733 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7734 result = PCI_ERS_RESULT_RECOVERED;
7735 }
7736
7737 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7738 if (err) {
849c4542
ET		 7739 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7740 "failed 0x%0x\n", err);
6fabd715
PWJ		 7741 /* non-fatal, continue */
7742 }
9a799d71 7743
6fabd715 7744 return result;
9a799d71
AK		 7745}
7746
7747/**
7748 * ixgbe_io_resume - called when traffic can start flowing again.
7749 * @pdev: Pointer to PCI device
7750 *
7751 * This callback is called when the error recovery driver tells us that
7752 * its OK to resume normal operation.
7753 */
7754static void ixgbe_io_resume(struct pci_dev *pdev)
7755{
c60fbb00
AD		 7756 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7757 struct net_device *netdev = adapter->netdev;
9a799d71 7758
c7ccde0f
AD		 7759 if (netif_running(netdev))
7760 ixgbe_up(adapter);
9a799d71
AK		 7761
7762 netif_device_attach(netdev);
9a799d71
AK		 7763}
7764
7765static struct pci_error_handlers ixgbe_err_handler = {
7766 .error_detected = ixgbe_io_error_detected,
7767 .slot_reset = ixgbe_io_slot_reset,
7768 .resume = ixgbe_io_resume,
7769};
7770
7771static struct pci_driver ixgbe_driver = {
7772 .name = ixgbe_driver_name,
7773 .id_table = ixgbe_pci_tbl,
7774 .probe = ixgbe_probe,
7775 .remove = __devexit_p(ixgbe_remove),
7776#ifdef CONFIG_PM
7777 .suspend = ixgbe_suspend,
7778 .resume = ixgbe_resume,
7779#endif
7780 .shutdown = ixgbe_shutdown,
7781 .err_handler = &ixgbe_err_handler
7782};
7783
7784/**
7785 * ixgbe_init_module - Driver Registration Routine
7786 *
7787 * ixgbe_init_module is the first routine called when the driver is
7788 * loaded. All it does is register with the PCI subsystem.
7789 **/
7790static int __init ixgbe_init_module(void)
7791{
7792 int ret;
c7689578 7793 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7794 pr_info("%s\n", ixgbe_copyright);
9a799d71 7795
5dd2d332 7796#ifdef CONFIG_IXGBE_DCA
bd0362dd 7797 dca_register_notify(&dca_notifier);
bd0362dd 7798#endif
5dd2d332 7799
9a799d71
AK		 7800 ret = pci_register_driver(&ixgbe_driver);
7801 return ret;
7802}
b4617240 7803
9a799d71
AK		 7804module_init(ixgbe_init_module);
7805
7806/**
7807 * ixgbe_exit_module - Driver Exit Cleanup Routine
7808 *
7809 * ixgbe_exit_module is called just before the driver is removed
7810 * from memory.
7811 **/
7812static void __exit ixgbe_exit_module(void)
7813{
5dd2d332 7814#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7815 dca_unregister_notify(&dca_notifier);
7816#endif
9a799d71 7817 pci_unregister_driver(&ixgbe_driver);
1a51502b 7818 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7819}
bd0362dd 7820
5dd2d332 7821#ifdef CONFIG_IXGBE_DCA
bd0362dd 7822static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7823 void *p)
bd0362dd
JC		 7824{
7825 int ret_val;
7826
7827 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7828 __ixgbe_notify_dca);
bd0362dd
JC		 7829
7830 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7831}
b453368d 7832
5dd2d332 7833#endif /* CONFIG_IXGBE_DCA */
849c4542 7834
9a799d71
AK		 7835module_exit(ixgbe_exit_module);
7836
7837/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)