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ixgbe: update date to 2013
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
815cccbf 47#include <linux/if_bridge.h>
70c71606 48#include <linux/prefetch.h>
eacd73f7 49#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 50
51#include "ixgbe.h"
52#include "ixgbe_common.h"
ee5f784a 53#include "ixgbe_dcb_82599.h"
1cdd1ec8 54#include "ixgbe_sriov.h"
9a799d71
AK		 55
56char ixgbe_driver_name[] = "ixgbe";
9c8eb720 57static const char ixgbe_driver_string[] =
e8e9f696 58 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 59#ifdef IXGBE_FCOE
ea81875a
NP		 60char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 62#else
63static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65#endif
14a8d4bb 66#define DRV_VERSION "3.11.33-k"
9c8eb720 67const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 68static const char ixgbe_copyright[] =
434c5e39 69 "Copyright (c) 1999-2013 Intel Corporation.";
9a799d71
AK		 70
71static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 72 [board_82598] = &ixgbe_82598_info,
e8e26350 73 [board_82599] = &ixgbe_82599_info,
fe15e8e1 74 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 75};
76
77/* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 115 /* required last entry */
116 {0, }
117};
118MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
5dd2d332 120#ifdef CONFIG_IXGBE_DCA
bd0362dd 121static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 122 void *p);
bd0362dd
JC		 123static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127};
128#endif
129
1cdd1ec8
GR		 130#ifdef CONFIG_PCI_IOV
131static unsigned int max_vfs;
132module_param(max_vfs, uint, 0);
e8e9f696 133MODULE_PARM_DESC(max_vfs,
6b42a9c5 134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 135#endif /* CONFIG_PCI_IOV */
136
8ef78adc
PWJ		 137static unsigned int allow_unsupported_sfp;
138module_param(allow_unsupported_sfp, uint, 0);
139MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
b3f4d599 142#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143static int debug = -1;
144module_param(debug, int, 0);
145MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
9a799d71
AK		 147MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149MODULE_LICENSE("GPL");
150MODULE_VERSION(DRV_VERSION);
151
7086400d
AD		 152static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
153{
154 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
155 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
156 schedule_work(&adapter->service_task);
157}
158
159static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
160{
161 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
162
52f33af8 163 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 164 smp_mb__before_clear_bit();
165 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
166}
167
dcd79aeb
TI		 168struct ixgbe_reg_info {
169 u32 ofs;
170 char *name;
171};
172
173static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
174
175 /* General Registers */
176 {IXGBE_CTRL, "CTRL"},
177 {IXGBE_STATUS, "STATUS"},
178 {IXGBE_CTRL_EXT, "CTRL_EXT"},
179
180 /* Interrupt Registers */
181 {IXGBE_EICR, "EICR"},
182
183 /* RX Registers */
184 {IXGBE_SRRCTL(0), "SRRCTL"},
185 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
186 {IXGBE_RDLEN(0), "RDLEN"},
187 {IXGBE_RDH(0), "RDH"},
188 {IXGBE_RDT(0), "RDT"},
189 {IXGBE_RXDCTL(0), "RXDCTL"},
190 {IXGBE_RDBAL(0), "RDBAL"},
191 {IXGBE_RDBAH(0), "RDBAH"},
192
193 /* TX Registers */
194 {IXGBE_TDBAL(0), "TDBAL"},
195 {IXGBE_TDBAH(0), "TDBAH"},
196 {IXGBE_TDLEN(0), "TDLEN"},
197 {IXGBE_TDH(0), "TDH"},
198 {IXGBE_TDT(0), "TDT"},
199 {IXGBE_TXDCTL(0), "TXDCTL"},
200
201 /* List Terminator */
202 {}
203};
204
205
206/*
207 * ixgbe_regdump - register printout routine
208 */
209static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
210{
211 int i = 0, j = 0;
212 char rname[16];
213 u32 regs[64];
214
215 switch (reginfo->ofs) {
216 case IXGBE_SRRCTL(0):
217 for (i = 0; i < 64; i++)
218 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
219 break;
220 case IXGBE_DCA_RXCTRL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
223 break;
224 case IXGBE_RDLEN(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
227 break;
228 case IXGBE_RDH(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
231 break;
232 case IXGBE_RDT(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
235 break;
236 case IXGBE_RXDCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
239 break;
240 case IXGBE_RDBAL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
243 break;
244 case IXGBE_RDBAH(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
247 break;
248 case IXGBE_TDBAL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
251 break;
252 case IXGBE_TDBAH(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
255 break;
256 case IXGBE_TDLEN(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
259 break;
260 case IXGBE_TDH(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
263 break;
264 case IXGBE_TDT(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
267 break;
268 case IXGBE_TXDCTL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
271 break;
272 default:
c7689578 273 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 274 IXGBE_READ_REG(hw, reginfo->ofs));
275 return;
276 }
277
278 for (i = 0; i < 8; i++) {
279 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 280 pr_err("%-15s", rname);
dcd79aeb 281 for (j = 0; j < 8; j++)
c7689578
JP		 282 pr_cont(" %08x", regs[i*8+j]);
283 pr_cont("\n");
dcd79aeb
TI		 284 }
285
286}
287
288/*
289 * ixgbe_dump - Print registers, tx-rings and rx-rings
290 */
291static void ixgbe_dump(struct ixgbe_adapter *adapter)
292{
293 struct net_device *netdev = adapter->netdev;
294 struct ixgbe_hw *hw = &adapter->hw;
295 struct ixgbe_reg_info *reginfo;
296 int n = 0;
297 struct ixgbe_ring *tx_ring;
729739b7 298 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 299 union ixgbe_adv_tx_desc *tx_desc;
300 struct my_u0 { u64 a; u64 b; } *u0;
301 struct ixgbe_ring *rx_ring;
302 union ixgbe_adv_rx_desc *rx_desc;
303 struct ixgbe_rx_buffer *rx_buffer_info;
304 u32 staterr;
305 int i = 0;
306
307 if (!netif_msg_hw(adapter))
308 return;
309
310 /* Print netdevice Info */
311 if (netdev) {
312 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 313 pr_info("Device Name state "
dcd79aeb 314 "trans_start last_rx\n");
c7689578
JP		 315 pr_info("%-15s %016lX %016lX %016lX\n",
316 netdev->name,
317 netdev->state,
318 netdev->trans_start,
319 netdev->last_rx);
dcd79aeb
TI		 320 }
321
322 /* Print Registers */
323 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 324 pr_info(" Register Name Value\n");
dcd79aeb
TI		 325 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
326 reginfo->name; reginfo++) {
327 ixgbe_regdump(hw, reginfo);
328 }
329
330 /* Print TX Ring Summary */
331 if (!netdev || !netif_running(netdev))
332 goto exit;
333
334 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 335 pr_info(" %s %s %s %s\n",
336 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
337 "leng", "ntw", "timestamp");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 341 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
39ac868a 357 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
39ac868a 361 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 364 *
365 * 82598 Advanced Transmit Descriptor (Write-Back Format)
366 * +--------------------------------------------------------------+
367 * 0 | RSV [63:0] |
368 * +--------------------------------------------------------------+
369 * 8 | RSV | STA | NXTSEQ |
370 * +--------------------------------------------------------------+
371 * 63 36 35 32 31 0
372 *
373 * 82599+ Advanced Transmit Descriptor
374 * +--------------------------------------------------------------+
375 * 0 | Buffer Address [63:0] |
376 * +--------------------------------------------------------------+
377 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
378 * +--------------------------------------------------------------+
379 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
380 *
381 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
382 * +--------------------------------------------------------------+
383 * 0 | RSV [63:0] |
384 * +--------------------------------------------------------------+
385 * 8 | RSV | STA | RSV |
386 * +--------------------------------------------------------------+
387 * 63 36 35 32 31 0
dcd79aeb
TI		 388 */
389
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 tx_ring = adapter->tx_ring[n];
c7689578
JP		 392 pr_info("------------------------------------\n");
393 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
394 pr_info("------------------------------------\n");
8ad88e37
JH		 395 pr_info("%s%s %s %s %s %s\n",
396 "T [desc] [address 63:0 ] ",
397 "[PlPOIdStDDt Ln] [bi->dma ] ",
398 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 399
400 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 401 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 402 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 403 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 404 if (dma_unmap_len(tx_buffer, len) > 0) {
405 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
406 i,
407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
409 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 410 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
413 tx_buffer->skb);
414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
416 pr_cont(" NTC/U\n");
417 else if (i == tx_ring->next_to_use)
418 pr_cont(" NTU\n");
419 else if (i == tx_ring->next_to_clean)
420 pr_cont(" NTC\n");
421 else
422 pr_cont("\n");
423
424 if (netif_msg_pktdata(adapter) &&
425 tx_buffer->skb)
426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
428 tx_buffer->skb->data,
429 dma_unmap_len(tx_buffer, len),
430 true);
431 }
dcd79aeb
TI		 432 }
433 }
434
435 /* Print RX Rings Summary */
436rx_ring_summary:
437 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 438 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 439 for (n = 0; n < adapter->num_rx_queues; n++) {
440 rx_ring = adapter->rx_ring[n];
c7689578
JP		 441 pr_info("%5d %5X %5X\n",
442 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 443 }
444
445 /* Print RX Rings */
446 if (!netif_msg_rx_status(adapter))
447 goto exit;
448
449 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
450
39ac868a
JH		 451 /* Receive Descriptor Formats
452 *
453 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 454 * 63 1 0
455 * +-----------------------------------------------------+
456 * 0 | Packet Buffer Address [63:1] |A0/NSE|
457 * +----------------------------------------------+------+
458 * 8 | Header Buffer Address [63:1] | DD |
459 * +-----------------------------------------------------+
460 *
461 *
39ac868a 462 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 463 *
464 * 63 48 47 32 31 30 21 20 16 15 4 3 0
465 * +------------------------------------------------------+
39ac868a
JH		 466 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
467 * | Packet | IP | | | | Type | Type |
468 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 469 * +------------------------------------------------------+
470 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
471 * +------------------------------------------------------+
472 * 63 48 47 32 31 20 19 0
39ac868a
JH		 473 *
474 * 82599+ Advanced Receive Descriptor (Read) Format
475 * 63 1 0
476 * +-----------------------------------------------------+
477 * 0 | Packet Buffer Address [63:1] |A0/NSE|
478 * +----------------------------------------------+------+
479 * 8 | Header Buffer Address [63:1] | DD |
480 * +-----------------------------------------------------+
481 *
482 *
483 * 82599+ Advanced Receive Descriptor (Write-Back) Format
484 *
485 * 63 48 47 32 31 30 21 20 17 16 4 3 0
486 * +------------------------------------------------------+
487 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
488 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
489 * |/ Flow Dir Flt ID | | | | | |
490 * +------------------------------------------------------+
491 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
492 * +------------------------------------------------------+
493 * 63 48 47 32 31 20 19 0
dcd79aeb 494 */
39ac868a 495
dcd79aeb
TI		 496 for (n = 0; n < adapter->num_rx_queues; n++) {
497 rx_ring = adapter->rx_ring[n];
c7689578
JP		 498 pr_info("------------------------------------\n");
499 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
500 pr_info("------------------------------------\n");
8ad88e37
JH		 501 pr_info("%s%s%s",
502 "R [desc] [ PktBuf A0] ",
503 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 504 "<-- Adv Rx Read format\n");
8ad88e37
JH		 505 pr_info("%s%s%s",
506 "RWB[desc] [PcsmIpSHl PtRs] ",
507 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 508 "<-- Adv Rx Write-Back format\n");
509
510 for (i = 0; i < rx_ring->count; i++) {
511 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 512 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 513 u0 = (struct my_u0 *)rx_desc;
514 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
515 if (staterr & IXGBE_RXD_STAT_DD) {
516 /* Descriptor Done */
c7689578 517 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 518 "%016llX ---------------- %p", i,
519 le64_to_cpu(u0->a),
520 le64_to_cpu(u0->b),
521 rx_buffer_info->skb);
522 } else {
c7689578 523 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 524 "%016llX %016llX %p", i,
525 le64_to_cpu(u0->a),
526 le64_to_cpu(u0->b),
527 (u64)rx_buffer_info->dma,
528 rx_buffer_info->skb);
529
9c50c035
ET		 530 if (netif_msg_pktdata(adapter) &&
531 rx_buffer_info->dma) {
dcd79aeb
TI		 532 print_hex_dump(KERN_INFO, "",
533 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 534 page_address(rx_buffer_info->page) +
535 rx_buffer_info->page_offset,
f800326d 536 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 537 }
538 }
539
540 if (i == rx_ring->next_to_use)
c7689578 541 pr_cont(" NTU\n");
dcd79aeb 542 else if (i == rx_ring->next_to_clean)
c7689578 543 pr_cont(" NTC\n");
dcd79aeb 544 else
c7689578 545 pr_cont("\n");
dcd79aeb
TI		 546
547 }
548 }
549
550exit:
551 return;
552}
553
5eba3699
AV		 554static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555{
556 u32 ctrl_ext;
557
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 562}
563
564static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565{
566 u32 ctrl_ext;
567
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 572}
9a799d71 573
49ce9c2c 574/**
e8e26350
PW		 575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
580 *
581 */
582static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 583 u8 queue, u8 msix_vector)
9a799d71
AK		 584{
585 u32 ivar, index;
e8e26350
PW		 586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 if (direction == -1)
591 direction = 0;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
597 break;
598 case ixgbe_mac_82599EB:
b93a2226 599 case ixgbe_mac_X540:
e8e26350
PW		 600 if (direction == -1) {
601 /* other causes */
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
608 break;
609 } else {
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
617 break;
618 }
619 default:
620 break;
621 }
9a799d71
AK		 622}
623
fe49f04a 624static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 625 u64 qmask)
fe49f04a
AD		 626{
627 u32 mask;
628
bd508178
AD		 629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
fe49f04a
AD		 631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 633 break;
634 case ixgbe_mac_82599EB:
b93a2226 635 case ixgbe_mac_X540:
fe49f04a
AD		 636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 640 break;
641 default:
642 break;
fe49f04a
AD		 643 }
644}
645
729739b7
AD		 646void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 648{
729739b7
AD		 649 if (tx_buffer->skb) {
650 dev_kfree_skb_any(tx_buffer->skb);
651 if (dma_unmap_len(tx_buffer, len))
d3d00239 652 dma_unmap_single(ring->dev,
729739b7
AD		 653 dma_unmap_addr(tx_buffer, dma),
654 dma_unmap_len(tx_buffer, len),
655 DMA_TO_DEVICE);
656 } else if (dma_unmap_len(tx_buffer, len)) {
657 dma_unmap_page(ring->dev,
658 dma_unmap_addr(tx_buffer, dma),
659 dma_unmap_len(tx_buffer, len),
660 DMA_TO_DEVICE);
e5a43549 661 }
729739b7
AD		 662 tx_buffer->next_to_watch = NULL;
663 tx_buffer->skb = NULL;
664 dma_unmap_len_set(tx_buffer, len, 0);
665 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 666}
667
943561d3 668static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 669{
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 672 int i;
943561d3 673 u32 data;
c84d324c 674
943561d3
AD		 675 if ((hw->fc.current_mode != ixgbe_fc_full) &&
676 (hw->fc.current_mode != ixgbe_fc_rx_pause))
677 return;
c84d324c 678
943561d3
AD		 679 switch (hw->mac.type) {
680 case ixgbe_mac_82598EB:
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
682 break;
683 default:
684 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
685 }
686 hwstats->lxoffrxc += data;
c84d324c 687
943561d3
AD		 688 /* refill credits (no tx hang) if we received xoff */
689 if (!data)
c84d324c 690 return;
943561d3
AD		 691
692 for (i = 0; i < adapter->num_tx_queues; i++)
693 clear_bit(__IXGBE_HANG_CHECK_ARMED,
694 &adapter->tx_ring[i]->state);
695}
696
697static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698{
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 xoff[8] = {0};
2afaa00d 702 u8 tc;
943561d3
AD		 703 int i;
704 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
705
706 if (adapter->ixgbe_ieee_pfc)
707 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
708
709 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
710 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 711 return;
943561d3 712 }
c84d324c
JF		 713
714 /* update stats for each tc, only valid with PFC enabled */
715 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 716 u32 pxoffrxc;
717
c84d324c
JF		 718 switch (hw->mac.type) {
719 case ixgbe_mac_82598EB:
2afaa00d 720 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 721 break;
c84d324c 722 default:
2afaa00d 723 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 724 }
2afaa00d
PN		 725 hwstats->pxoffrxc[i] += pxoffrxc;
726 /* Get the TC for given UP */
727 tc = netdev_get_prio_tc_map(adapter->netdev, i);
728 xoff[tc] += pxoffrxc;
c84d324c
JF		 729 }
730
731 /* disarm tx queues that have received xoff frames */
732 for (i = 0; i < adapter->num_tx_queues; i++) {
733 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 734
2afaa00d 735 tc = tx_ring->dcb_tc;
c84d324c
JF		 736 if (xoff[tc])
737 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 738 }
26f23d82
YZ		 739}
740
c84d324c 741static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 742{
7d7ce682 743 return ring->stats.packets;
c84d324c
JF		 744}
745
746static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
747{
748 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 749 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 750
c84d324c
JF		 751 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
752 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
753
754 if (head != tail)
755 return (head < tail) ?
756 tail - head : (tail + ring->count - head);
757
758 return 0;
759}
760
761static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
762{
763 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
764 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
765 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
766 bool ret = false;
767
7d637bcc 768 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 769
770 /*
771 * Check for a hung queue, but be thorough. This verifies
772 * that a transmit has been completed since the previous
773 * check AND there is at least one packet pending. The
774 * ARMED bit is set to indicate a potential hang. The
775 * bit is cleared if a pause frame is received to remove
776 * false hang detection due to PFC or 802.3x frames. By
777 * requiring this to fail twice we avoid races with
778 * pfc clearing the ARMED bit and conditions where we
779 * run the check_tx_hang logic with a transmit completion
780 * pending but without time to complete it yet.
781 */
782 if ((tx_done_old == tx_done) && tx_pending) {
783 /* make sure it is true for two checks in a row */
784 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
785 &tx_ring->state);
786 } else {
787 /* update completed stats and continue */
788 tx_ring->tx_stats.tx_done_old = tx_done;
789 /* reset the countdown */
790 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 791 }
792
c84d324c 793 return ret;
9a799d71
AK		 794}
795
c83c6cbd
AD		 796/**
797 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
798 * @adapter: driver private struct
799 **/
800static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
801{
802
803 /* Do the reset outside of interrupt context */
804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
805 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 806 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 807 ixgbe_service_event_schedule(adapter);
808 }
809}
e01c31a5 810
9a799d71
AK		 811/**
812 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 813 * @q_vector: structure containing interrupt and ring information
e01c31a5 814 * @tx_ring: tx ring to clean
9a799d71 815 **/
fe49f04a 816static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 817 struct ixgbe_ring *tx_ring)
9a799d71 818{
fe49f04a 819 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 820 struct ixgbe_tx_buffer *tx_buffer;
821 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 822 unsigned int total_bytes = 0, total_packets = 0;
59224555 823 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 824 unsigned int i = tx_ring->next_to_clean;
825
826 if (test_bit(__IXGBE_DOWN, &adapter->state))
827 return true;
9a799d71 828
d3d00239 829 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 830 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 831 i -= tx_ring->count;
12207e49 832
729739b7 833 do {
d3d00239
AD		 834 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
835
836 /* if next_to_watch is not set then there is no work pending */
837 if (!eop_desc)
838 break;
839
7f83a9e6
AD		 840 /* prevent any other reads prior to eop_desc */
841 rmb();
842
d3d00239
AD		 843 /* if DD is not set pending work has not been completed */
844 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
845 break;
8ad494b0 846
d3d00239
AD		 847 /* clear next_to_watch to prevent false hangs */
848 tx_buffer->next_to_watch = NULL;
8ad494b0 849
091a6246
AD		 850 /* update the statistics for this packet */
851 total_bytes += tx_buffer->bytecount;
852 total_packets += tx_buffer->gso_segs;
853
fd0db0ed
AD		 854 /* free the skb */
855 dev_kfree_skb_any(tx_buffer->skb);
856
729739b7
AD		 857 /* unmap skb header data */
858 dma_unmap_single(tx_ring->dev,
859 dma_unmap_addr(tx_buffer, dma),
860 dma_unmap_len(tx_buffer, len),
861 DMA_TO_DEVICE);
862
fd0db0ed
AD		 863 /* clear tx_buffer data */
864 tx_buffer->skb = NULL;
729739b7 865 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 866
729739b7
AD		 867 /* unmap remaining buffers */
868 while (tx_desc != eop_desc) {
d3d00239
AD		 869 tx_buffer++;
870 tx_desc++;
8ad494b0 871 i++;
729739b7
AD		 872 if (unlikely(!i)) {
873 i -= tx_ring->count;
d3d00239 874 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 875 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 876 }
e01c31a5 877
729739b7
AD		 878 /* unmap any remaining paged data */
879 if (dma_unmap_len(tx_buffer, len)) {
880 dma_unmap_page(tx_ring->dev,
881 dma_unmap_addr(tx_buffer, dma),
882 dma_unmap_len(tx_buffer, len),
883 DMA_TO_DEVICE);
884 dma_unmap_len_set(tx_buffer, len, 0);
885 }
886 }
887
888 /* move us one more past the eop_desc for start of next pkt */
889 tx_buffer++;
890 tx_desc++;
891 i++;
892 if (unlikely(!i)) {
893 i -= tx_ring->count;
894 tx_buffer = tx_ring->tx_buffer_info;
895 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
896 }
897
898 /* issue prefetch for next Tx descriptor */
899 prefetch(tx_desc);
12207e49 900
729739b7
AD		 901 /* update budget accounting */
902 budget--;
903 } while (likely(budget));
904
905 i += tx_ring->count;
9a799d71 906 tx_ring->next_to_clean = i;
d3d00239 907 u64_stats_update_begin(&tx_ring->syncp);
b953799e 908 tx_ring->stats.bytes += total_bytes;
bd198058 909 tx_ring->stats.packets += total_packets;
d3d00239 910 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 911 q_vector->tx.total_bytes += total_bytes;
912 q_vector->tx.total_packets += total_packets;
b953799e 913
c84d324c
JF		 914 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
915 /* schedule immediate reset if we believe we hung */
916 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 917 e_err(drv, "Detected Tx Unit Hang\n"
918 " Tx Queue <%d>\n"
919 " TDH, TDT <%x>, <%x>\n"
920 " next_to_use <%x>\n"
921 " next_to_clean <%x>\n"
922 "tx_buffer_info[next_to_clean]\n"
923 " time_stamp <%lx>\n"
924 " jiffies <%lx>\n",
925 tx_ring->queue_index,
926 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
927 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 928 tx_ring->next_to_use, i,
929 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 930
931 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
932
933 e_info(probe,
934 "tx hang %d detected on queue %d, resetting adapter\n",
935 adapter->tx_timeout_count + 1, tx_ring->queue_index);
936
b953799e 937 /* schedule immediate reset if we believe we hung */
c83c6cbd 938 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 939
940 /* the adapter is about to reset, no point in enabling stuff */
59224555 941 return true;
b953799e 942 }
9a799d71 943
b2d96e0a
AD		 944 netdev_tx_completed_queue(txring_txq(tx_ring),
945 total_packets, total_bytes);
946
e092be60 947#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 948 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 949 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 950 /* Make sure that anybody stopping the queue after this
951 * sees the new next_to_clean.
952 */
953 smp_mb();
729739b7
AD		 954 if (__netif_subqueue_stopped(tx_ring->netdev,
955 tx_ring->queue_index)
956 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
957 netif_wake_subqueue(tx_ring->netdev,
958 tx_ring->queue_index);
5b7da515 959 ++tx_ring->tx_stats.restart_queue;
30eba97a 960 }
e092be60 961 }
9a799d71 962
59224555 963 return !!budget;
9a799d71
AK		 964}
965
5dd2d332 966#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 967static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
968 struct ixgbe_ring *tx_ring,
33cf09c9 969 int cpu)
bd0362dd 970{
33cf09c9 971 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 972 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
973 u16 reg_offset;
33cf09c9 974
33cf09c9
AD		 975 switch (hw->mac.type) {
976 case ixgbe_mac_82598EB:
bdda1a61 977 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 978 break;
979 case ixgbe_mac_82599EB:
b93a2226 980 case ixgbe_mac_X540:
bdda1a61
AD		 981 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
982 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 983 break;
984 default:
bdda1a61
AD		 985 /* for unknown hardware do not write register */
986 return;
bd0362dd 987 }
bdda1a61
AD		 988
989 /*
990 * We can enable relaxed ordering for reads, but not writes when
991 * DCA is enabled. This is due to a known issue in some chipsets
992 * which will cause the DCA tag to be cleared.
993 */
994 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
995 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
996 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
997
998 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 999}
1000
bdda1a61
AD		 1001static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1002 struct ixgbe_ring *rx_ring,
33cf09c9 1003 int cpu)
bd0362dd 1004{
33cf09c9 1005 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1006 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1007 u8 reg_idx = rx_ring->reg_idx;
1008
33cf09c9
AD		 1009
1010 switch (hw->mac.type) {
33cf09c9 1011 case ixgbe_mac_82599EB:
b93a2226 1012 case ixgbe_mac_X540:
bdda1a61 1013 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1014 break;
1015 default:
1016 break;
1017 }
bdda1a61
AD		 1018
1019 /*
1020 * We can enable relaxed ordering for reads, but not writes when
1021 * DCA is enabled. This is due to a known issue in some chipsets
1022 * which will cause the DCA tag to be cleared.
1023 */
1024 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1025 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1026
1027 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1028}
1029
1030static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1031{
1032 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1033 struct ixgbe_ring *ring;
bd0362dd 1034 int cpu = get_cpu();
bd0362dd 1035
33cf09c9
AD		 1036 if (q_vector->cpu == cpu)
1037 goto out_no_update;
1038
a557928e 1039 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1040 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1041
a557928e 1042 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1043 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1044
1045 q_vector->cpu = cpu;
1046out_no_update:
bd0362dd
JC		 1047 put_cpu();
1048}
1049
1050static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1051{
1052 int i;
1053
1054 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1055 return;
1056
e35ec126
AD		 1057 /* always use CB2 mode, difference is masked in the CB driver */
1058 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1059
49c7ffbe 1060 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1061 adapter->q_vector[i]->cpu = -1;
1062 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1063 }
1064}
1065
1066static int __ixgbe_notify_dca(struct device *dev, void *data)
1067{
c60fbb00 1068 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1069 unsigned long event = *(unsigned long *)data;
1070
2a72c31e 1071 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1072 return 0;
1073
bd0362dd
JC		 1074 switch (event) {
1075 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1076 /* if we're already enabled, don't do it again */
1077 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1078 break;
652f093f 1079 if (dca_add_requester(dev) == 0) {
96b0e0f6 1080 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1081 ixgbe_setup_dca(adapter);
1082 break;
1083 }
1084 /* Fall Through since DCA is disabled. */
1085 case DCA_PROVIDER_REMOVE:
1086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1087 dca_remove_requester(dev);
1088 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1090 }
1091 break;
1092 }
1093
652f093f 1094 return 0;
bd0362dd 1095}
67a74ee2 1096
bdda1a61 1097#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1098static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1099 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1100 struct sk_buff *skb)
1101{
8a0da21b
AD		 1102 if (ring->netdev->features & NETIF_F_RXHASH)
1103 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1104}
1105
f800326d 1106#ifdef IXGBE_FCOE
ff886dfc
AD		 1107/**
1108 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1109 * @ring: structure containing ring specific data
ff886dfc
AD		 1110 * @rx_desc: advanced rx descriptor
1111 *
1112 * Returns : true if it is FCoE pkt
1113 */
57efd44c 1114static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1115 union ixgbe_adv_rx_desc *rx_desc)
1116{
1117 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1118
57efd44c 1119 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1120 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1121 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1122 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1123}
1124
f800326d 1125#endif /* IXGBE_FCOE */
e59bd25d
AV		 1126/**
1127 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1128 * @ring: structure containing ring specific data
1129 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1130 * @skb: skb currently being received and modified
1131 **/
8a0da21b 1132static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1133 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1134 struct sk_buff *skb)
9a799d71 1135{
8a0da21b 1136 skb_checksum_none_assert(skb);
9a799d71 1137
712744be 1138 /* Rx csum disabled */
8a0da21b 1139 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1140 return;
e59bd25d
AV		 1141
1142 /* if IP and error */
f56e0cb1
AD		 1143 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1144 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1145 ring->rx_stats.csum_err++;
9a799d71
AK		 1146 return;
1147 }
e59bd25d 1148
f56e0cb1 1149 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1150 return;
1151
f56e0cb1 1152 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1153 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1154
1155 /*
1156 * 82599 errata, UDP frames with a 0 checksum can be marked as
1157 * checksum errors.
1158 */
8a0da21b
AD		 1159 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1160 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1161 return;
1162
8a0da21b 1163 ring->rx_stats.csum_err++;
e59bd25d
AV		 1164 return;
1165 }
1166
9a799d71 1167 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1168 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1169}
1170
84ea2591 1171static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1172{
f56e0cb1 1173 rx_ring->next_to_use = val;
f800326d
AD		 1174
1175 /* update next to alloc since we have filled the ring */
1176 rx_ring->next_to_alloc = val;
e8e26350
PW		 1177 /*
1178 * Force memory writes to complete before letting h/w
1179 * know there are new descriptors to fetch. (Only
1180 * applicable for weak-ordered memory model archs,
1181 * such as IA-64).
1182 */
1183 wmb();
84ea2591 1184 writel(val, rx_ring->tail);
e8e26350
PW		 1185}
1186
f990b79b
AD		 1187static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1188 struct ixgbe_rx_buffer *bi)
1189{
1190 struct page *page = bi->page;
f800326d 1191 dma_addr_t dma = bi->dma;
f990b79b 1192
f800326d
AD		 1193 /* since we are recycling buffers we should seldom need to alloc */
1194 if (likely(dma))
f990b79b
AD		 1195 return true;
1196
f800326d
AD		 1197 /* alloc new page for storage */
1198 if (likely(!page)) {
0614002b
MG		 1199 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1200 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1201 if (unlikely(!page)) {
1202 rx_ring->rx_stats.alloc_rx_page_failed++;
1203 return false;
1204 }
f800326d 1205 bi->page = page;
f990b79b
AD		 1206 }
1207
f800326d
AD		 1208 /* map page for use */
1209 dma = dma_map_page(rx_ring->dev, page, 0,
1210 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1211
1212 /*
1213 * if mapping failed free memory back to system since
1214 * there isn't much point in holding memory we can't use
1215 */
1216 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1217 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1218 bi->page = NULL;
f990b79b 1219
f990b79b
AD		 1220 rx_ring->rx_stats.alloc_rx_page_failed++;
1221 return false;
1222 }
1223
f800326d 1224 bi->dma = dma;
afaa9459 1225 bi->page_offset = 0;
f800326d 1226
f990b79b
AD		 1227 return true;
1228}
1229
9a799d71 1230/**
f990b79b 1231 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1232 * @rx_ring: ring to place buffers on
1233 * @cleaned_count: number of buffers to replace
9a799d71 1234 **/
fc77dc3c 1235void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1236{
9a799d71 1237 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1238 struct ixgbe_rx_buffer *bi;
d5f398ed 1239 u16 i = rx_ring->next_to_use;
9a799d71 1240
f800326d
AD		 1241 /* nothing to do */
1242 if (!cleaned_count)
fc77dc3c
AD		 1243 return;
1244
e4f74028 1245 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1246 bi = &rx_ring->rx_buffer_info[i];
1247 i -= rx_ring->count;
9a799d71 1248
f800326d
AD		 1249 do {
1250 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1251 break;
d5f398ed 1252
f800326d
AD		 1253 /*
1254 * Refresh the desc even if buffer_addrs didn't change
1255 * because each write-back erases this info.
1256 */
1257 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1258
f990b79b
AD		 1259 rx_desc++;
1260 bi++;
9a799d71 1261 i++;
f990b79b 1262 if (unlikely(!i)) {
e4f74028 1263 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1264 bi = rx_ring->rx_buffer_info;
1265 i -= rx_ring->count;
1266 }
1267
1268 /* clear the hdr_addr for the next_to_use descriptor */
1269 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1270
1271 cleaned_count--;
1272 } while (cleaned_count);
7c6e0a43 1273
f990b79b
AD		 1274 i += rx_ring->count;
1275
f56e0cb1 1276 if (rx_ring->next_to_use != i)
84ea2591 1277 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1278}
1279
1d2024f6
AD		 1280/**
1281 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1282 * @data: pointer to the start of the headers
1283 * @max_len: total length of section to find headers in
1284 *
1285 * This function is meant to determine the length of headers that will
1286 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1287 * motivation of doing this is to only perform one pull for IPv4 TCP
1288 * packets so that we can do basic things like calculating the gso_size
1289 * based on the average data per packet.
1290 **/
1291static unsigned int ixgbe_get_headlen(unsigned char *data,
1292 unsigned int max_len)
1293{
1294 union {
1295 unsigned char *network;
1296 /* l2 headers */
1297 struct ethhdr *eth;
1298 struct vlan_hdr *vlan;
1299 /* l3 headers */
1300 struct iphdr *ipv4;
a048b40e 1301 struct ipv6hdr *ipv6;
1d2024f6
AD		 1302 } hdr;
1303 __be16 protocol;
1304 u8 nexthdr = 0; /* default to not TCP */
1305 u8 hlen;
1306
1307 /* this should never happen, but better safe than sorry */
1308 if (max_len < ETH_HLEN)
1309 return max_len;
1310
1311 /* initialize network frame pointer */
1312 hdr.network = data;
1313
1314 /* set first protocol and move network header forward */
1315 protocol = hdr.eth->h_proto;
1316 hdr.network += ETH_HLEN;
1317
1318 /* handle any vlan tag if present */
1319 if (protocol == __constant_htons(ETH_P_8021Q)) {
1320 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1321 return max_len;
1322
1323 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1324 hdr.network += VLAN_HLEN;
1325 }
1326
1327 /* handle L3 protocols */
1328 if (protocol == __constant_htons(ETH_P_IP)) {
1329 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1330 return max_len;
1331
1332 /* access ihl as a u8 to avoid unaligned access on ia64 */
1333 hlen = (hdr.network[0] & 0x0F) << 2;
1334
1335 /* verify hlen meets minimum size requirements */
1336 if (hlen < sizeof(struct iphdr))
1337 return hdr.network - data;
1338
ed83da12
AD		 1339 /* record next protocol if header is present */
1340 if (!hdr.ipv4->frag_off)
1341 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1342 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1343 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1344 return max_len;
1345
1346 /* record next protocol */
1347 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1348 hlen = sizeof(struct ipv6hdr);
f800326d 1349#ifdef IXGBE_FCOE
1d2024f6
AD		 1350 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1351 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1352 return max_len;
ed83da12 1353 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1354#endif
1355 } else {
1356 return hdr.network - data;
1357 }
1358
ed83da12
AD		 1359 /* relocate pointer to start of L4 header */
1360 hdr.network += hlen;
1361
a048b40e 1362 /* finally sort out TCP/UDP */
1d2024f6
AD		 1363 if (nexthdr == IPPROTO_TCP) {
1364 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1365 return max_len;
1366
1367 /* access doff as a u8 to avoid unaligned access on ia64 */
1368 hlen = (hdr.network[12] & 0xF0) >> 2;
1369
1370 /* verify hlen meets minimum size requirements */
1371 if (hlen < sizeof(struct tcphdr))
1372 return hdr.network - data;
1373
1374 hdr.network += hlen;
a048b40e
AD		 1375 } else if (nexthdr == IPPROTO_UDP) {
1376 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1377 return max_len;
1378
1379 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1380 }
1381
1382 /*
1383 * If everything has gone correctly hdr.network should be the
1384 * data section of the packet and will be the end of the header.
1385 * If not then it probably represents the end of the last recognized
1386 * header.
1387 */
1388 if ((hdr.network - data) < max_len)
1389 return hdr.network - data;
1390 else
1391 return max_len;
1392}
1393
1d2024f6
AD		 1394static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1395 struct sk_buff *skb)
1396{
f800326d 1397 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1398
1399 /* set gso_size to avoid messing up TCP MSS */
1400 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1401 IXGBE_CB(skb)->append_cnt);
1402}
1403
1404static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1405 struct sk_buff *skb)
1406{
1407 /* if append_cnt is 0 then frame is not RSC */
1408 if (!IXGBE_CB(skb)->append_cnt)
1409 return;
1410
1411 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1412 rx_ring->rx_stats.rsc_flush++;
1413
1414 ixgbe_set_rsc_gso_size(rx_ring, skb);
1415
1416 /* gso_size is computed using append_cnt so always clear it last */
1417 IXGBE_CB(skb)->append_cnt = 0;
1418}
1419
8a0da21b
AD		 1420/**
1421 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1422 * @rx_ring: rx descriptor ring packet is being transacted on
1423 * @rx_desc: pointer to the EOP Rx descriptor
1424 * @skb: pointer to current skb being populated
f8212f97 1425 *
8a0da21b
AD		 1426 * This function checks the ring, descriptor, and packet information in
1427 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1428 * other fields within the skb.
f8212f97 1429 **/
8a0da21b
AD		 1430static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1431 union ixgbe_adv_rx_desc *rx_desc,
1432 struct sk_buff *skb)
f8212f97 1433{
43e95f11
JF		 1434 struct net_device *dev = rx_ring->netdev;
1435
8a0da21b
AD		 1436 ixgbe_update_rsc_stats(rx_ring, skb);
1437
1438 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1439
8a0da21b
AD		 1440 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1441
6cb562d6 1442 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1443
43e95f11
JF		 1444 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1445 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1446 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1447 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1448 }
1449
8a0da21b 1450 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1451
43e95f11 1452 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1453}
1454
8a0da21b
AD		 1455static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1456 struct sk_buff *skb)
aa80175a 1457{
8a0da21b
AD		 1458 struct ixgbe_adapter *adapter = q_vector->adapter;
1459
1460 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1461 napi_gro_receive(&q_vector->napi, skb);
1462 else
1463 netif_rx(skb);
aa80175a 1464}
43634e82 1465
f800326d
AD		 1466/**
1467 * ixgbe_is_non_eop - process handling of non-EOP buffers
1468 * @rx_ring: Rx ring being processed
1469 * @rx_desc: Rx descriptor for current buffer
1470 * @skb: Current socket buffer containing buffer in progress
1471 *
1472 * This function updates next to clean. If the buffer is an EOP buffer
1473 * this function exits returning false, otherwise it will place the
1474 * sk_buff in the next buffer to be chained and return true indicating
1475 * that this is in fact a non-EOP buffer.
1476 **/
1477static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1480{
1481 u32 ntc = rx_ring->next_to_clean + 1;
1482
1483 /* fetch, update, and store next to clean */
1484 ntc = (ntc < rx_ring->count) ? ntc : 0;
1485 rx_ring->next_to_clean = ntc;
1486
1487 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1488
5a02cbd1
AD		 1489 /* update RSC append count if present */
1490 if (ring_is_rsc_enabled(rx_ring)) {
1491 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1492 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1493
1494 if (unlikely(rsc_enabled)) {
1495 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1496
1497 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1498 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1499
5a02cbd1
AD		 1500 /* update ntc based on RSC value */
1501 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1502 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1503 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1504 }
f800326d
AD		 1505 }
1506
5a02cbd1
AD		 1507 /* if we are the last buffer then there is nothing else to do */
1508 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1509 return false;
1510
f800326d
AD		 1511 /* place skb in next buffer to be received */
1512 rx_ring->rx_buffer_info[ntc].skb = skb;
1513 rx_ring->rx_stats.non_eop_descs++;
1514
1515 return true;
1516}
1517
19861ce2
AD		 1518/**
1519 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1520 * @rx_ring: rx descriptor ring packet is being transacted on
1521 * @skb: pointer to current skb being adjusted
1522 *
1523 * This function is an ixgbe specific version of __pskb_pull_tail. The
1524 * main difference between this version and the original function is that
1525 * this function can make several assumptions about the state of things
1526 * that allow for significant optimizations versus the standard function.
1527 * As a result we can do things like drop a frag and maintain an accurate
1528 * truesize for the skb.
1529 */
1530static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1531 struct sk_buff *skb)
1532{
1533 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1534 unsigned char *va;
1535 unsigned int pull_len;
1536
1537 /*
1538 * it is valid to use page_address instead of kmap since we are
1539 * working with pages allocated out of the lomem pool per
1540 * alloc_page(GFP_ATOMIC)
1541 */
1542 va = skb_frag_address(frag);
1543
1544 /*
1545 * we need the header to contain the greater of either ETH_HLEN or
1546 * 60 bytes if the skb->len is less than 60 for skb_pad.
1547 */
cf3fe7ac 1548 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1549
1550 /* align pull length to size of long to optimize memcpy performance */
1551 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1552
1553 /* update all of the pointers */
1554 skb_frag_size_sub(frag, pull_len);
1555 frag->page_offset += pull_len;
1556 skb->data_len -= pull_len;
1557 skb->tail += pull_len;
19861ce2
AD		 1558}
1559
42073d91
AD		 1560/**
1561 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1562 * @rx_ring: rx descriptor ring packet is being transacted on
1563 * @skb: pointer to current skb being updated
1564 *
1565 * This function provides a basic DMA sync up for the first fragment of an
1566 * skb. The reason for doing this is that the first fragment cannot be
1567 * unmapped until we have reached the end of packet descriptor for a buffer
1568 * chain.
1569 */
1570static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1571 struct sk_buff *skb)
1572{
1573 /* if the page was released unmap it, else just sync our portion */
1574 if (unlikely(IXGBE_CB(skb)->page_released)) {
1575 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1576 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1577 IXGBE_CB(skb)->page_released = false;
1578 } else {
1579 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1580
1581 dma_sync_single_range_for_cpu(rx_ring->dev,
1582 IXGBE_CB(skb)->dma,
1583 frag->page_offset,
1584 ixgbe_rx_bufsz(rx_ring),
1585 DMA_FROM_DEVICE);
1586 }
1587 IXGBE_CB(skb)->dma = 0;
1588}
1589
f800326d
AD		 1590/**
1591 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1592 * @rx_ring: rx descriptor ring packet is being transacted on
1593 * @rx_desc: pointer to the EOP Rx descriptor
1594 * @skb: pointer to current skb being fixed
1595 *
1596 * Check for corrupted packet headers caused by senders on the local L2
1597 * embedded NIC switch not setting up their Tx Descriptors right. These
1598 * should be very rare.
1599 *
1600 * Also address the case where we are pulling data in on pages only
1601 * and as such no data is present in the skb header.
1602 *
1603 * In addition if skb is not at least 60 bytes we need to pad it so that
1604 * it is large enough to qualify as a valid Ethernet frame.
1605 *
1606 * Returns true if an error was encountered and skb was freed.
1607 **/
1608static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1609 union ixgbe_adv_rx_desc *rx_desc,
1610 struct sk_buff *skb)
1611{
f800326d 1612 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1613
1614 /* verify that the packet does not have any known errors */
1615 if (unlikely(ixgbe_test_staterr(rx_desc,
1616 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1617 !(netdev->features & NETIF_F_RXALL))) {
1618 dev_kfree_skb_any(skb);
1619 return true;
1620 }
1621
19861ce2 1622 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1623 if (skb_is_nonlinear(skb))
1624 ixgbe_pull_tail(rx_ring, skb);
f800326d 1625
57efd44c
AD		 1626#ifdef IXGBE_FCOE
1627 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1628 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1629 return false;
1630
1631#endif
f800326d
AD		 1632 /* if skb_pad returns an error the skb was freed */
1633 if (unlikely(skb->len < 60)) {
1634 int pad_len = 60 - skb->len;
1635
1636 if (skb_pad(skb, pad_len))
1637 return true;
1638 __skb_put(skb, pad_len);
1639 }
1640
1641 return false;
1642}
1643
f800326d
AD		 1644/**
1645 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1646 * @rx_ring: rx descriptor ring to store buffers on
1647 * @old_buff: donor buffer to have page reused
1648 *
0549ae20 1649 * Synchronizes page for reuse by the adapter
f800326d
AD		 1650 **/
1651static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1652 struct ixgbe_rx_buffer *old_buff)
1653{
1654 struct ixgbe_rx_buffer *new_buff;
1655 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1656
1657 new_buff = &rx_ring->rx_buffer_info[nta];
1658
1659 /* update, and store next to alloc */
1660 nta++;
1661 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1662
1663 /* transfer page from old buffer to new buffer */
1664 new_buff->page = old_buff->page;
1665 new_buff->dma = old_buff->dma;
0549ae20 1666 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1667
1668 /* sync the buffer for use by the device */
1669 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1670 new_buff->page_offset,
1671 ixgbe_rx_bufsz(rx_ring),
f800326d 1672 DMA_FROM_DEVICE);
f800326d
AD		 1673}
1674
1675/**
1676 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1677 * @rx_ring: rx descriptor ring to transact packets on
1678 * @rx_buffer: buffer containing page to add
1679 * @rx_desc: descriptor containing length of buffer written by hardware
1680 * @skb: sk_buff to place the data into
1681 *
0549ae20
AD		 1682 * This function will add the data contained in rx_buffer->page to the skb.
1683 * This is done either through a direct copy if the data in the buffer is
1684 * less than the skb header size, otherwise it will just attach the page as
1685 * a frag to the skb.
1686 *
1687 * The function will then update the page offset if necessary and return
1688 * true if the buffer can be reused by the adapter.
f800326d 1689 **/
0549ae20 1690static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1691 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1692 union ixgbe_adv_rx_desc *rx_desc,
1693 struct sk_buff *skb)
f800326d 1694{
0549ae20
AD		 1695 struct page *page = rx_buffer->page;
1696 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1697#if (PAGE_SIZE < 8192)
0549ae20 1698 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1699#else
1700 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1701 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1702 ixgbe_rx_bufsz(rx_ring);
1703#endif
0549ae20 1704
cf3fe7ac
AD		 1705 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1706 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1707
1708 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1709
1710 /* we can reuse buffer as-is, just make sure it is local */
1711 if (likely(page_to_nid(page) == numa_node_id()))
1712 return true;
1713
1714 /* this page cannot be reused so discard it */
1715 put_page(page);
1716 return false;
1717 }
1718
0549ae20
AD		 1719 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1720 rx_buffer->page_offset, size, truesize);
1721
09816fbe
AD		 1722 /* avoid re-using remote pages */
1723 if (unlikely(page_to_nid(page) != numa_node_id()))
1724 return false;
1725
1726#if (PAGE_SIZE < 8192)
1727 /* if we are only owner of page we can reuse it */
1728 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1729 return false;
1730
1731 /* flip page offset to other buffer */
1732 rx_buffer->page_offset ^= truesize;
1733
09816fbe
AD		 1734 /*
1735 * since we are the only owner of the page and we need to
1736 * increment it, just set the value to 2 in order to avoid
1737 * an unecessary locked operation
1738 */
1739 atomic_set(&page->_count, 2);
1740#else
1741 /* move offset up to the next cache line */
1742 rx_buffer->page_offset += truesize;
1743
1744 if (rx_buffer->page_offset > last_offset)
1745 return false;
1746
0549ae20
AD		 1747 /* bump ref count on page before it is given to the stack */
1748 get_page(page);
09816fbe 1749#endif
0549ae20
AD		 1750
1751 return true;
f800326d
AD		 1752}
1753
18806c9e
AD		 1754static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1755 union ixgbe_adv_rx_desc *rx_desc)
1756{
1757 struct ixgbe_rx_buffer *rx_buffer;
1758 struct sk_buff *skb;
1759 struct page *page;
1760
1761 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1762 page = rx_buffer->page;
1763 prefetchw(page);
1764
1765 skb = rx_buffer->skb;
1766
1767 if (likely(!skb)) {
1768 void *page_addr = page_address(page) +
1769 rx_buffer->page_offset;
1770
1771 /* prefetch first cache line of first page */
1772 prefetch(page_addr);
1773#if L1_CACHE_BYTES < 128
1774 prefetch(page_addr + L1_CACHE_BYTES);
1775#endif
1776
1777 /* allocate a skb to store the frags */
1778 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1779 IXGBE_RX_HDR_SIZE);
1780 if (unlikely(!skb)) {
1781 rx_ring->rx_stats.alloc_rx_buff_failed++;
1782 return NULL;
1783 }
1784
1785 /*
1786 * we will be copying header into skb->data in
1787 * pskb_may_pull so it is in our interest to prefetch
1788 * it now to avoid a possible cache miss
1789 */
1790 prefetchw(skb->data);
1791
1792 /*
1793 * Delay unmapping of the first packet. It carries the
1794 * header information, HW may still access the header
1795 * after the writeback. Only unmap it when EOP is
1796 * reached
1797 */
1798 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1799 goto dma_sync;
1800
1801 IXGBE_CB(skb)->dma = rx_buffer->dma;
1802 } else {
1803 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1804 ixgbe_dma_sync_frag(rx_ring, skb);
1805
1806dma_sync:
1807 /* we are reusing so sync this buffer for CPU use */
1808 dma_sync_single_range_for_cpu(rx_ring->dev,
1809 rx_buffer->dma,
1810 rx_buffer->page_offset,
1811 ixgbe_rx_bufsz(rx_ring),
1812 DMA_FROM_DEVICE);
1813 }
1814
1815 /* pull page into skb */
1816 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1817 /* hand second half of page back to the ring */
1818 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1819 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1820 /* the page has been released from the ring */
1821 IXGBE_CB(skb)->page_released = true;
1822 } else {
1823 /* we are not reusing the buffer so unmap it */
1824 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1825 ixgbe_rx_pg_size(rx_ring),
1826 DMA_FROM_DEVICE);
1827 }
1828
1829 /* clear contents of buffer_info */
1830 rx_buffer->skb = NULL;
1831 rx_buffer->dma = 0;
1832 rx_buffer->page = NULL;
1833
1834 return skb;
f800326d
AD		 1835}
1836
1837/**
1838 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1839 * @q_vector: structure containing interrupt and ring information
1840 * @rx_ring: rx descriptor ring to transact packets on
1841 * @budget: Total limit on number of packets to process
1842 *
1843 * This function provides a "bounce buffer" approach to Rx interrupt
1844 * processing. The advantage to this is that on systems that have
1845 * expensive overhead for IOMMU access this provides a means of avoiding
1846 * it by maintaining the mapping of the page to the syste.
1847 *
1848 * Returns true if all work is completed without reaching budget
1849 **/
4ff7fb12 1850static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1851 struct ixgbe_ring *rx_ring,
f4de00ed 1852 const int budget)
9a799d71 1853{
d2f4fbe2 1854 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1855#ifdef IXGBE_FCOE
f800326d 1856 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1857 int ddp_bytes;
1858 unsigned int mss = 0;
3d8fd385 1859#endif /* IXGBE_FCOE */
f800326d 1860 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1861
f800326d 1862 do {
f800326d
AD		 1863 union ixgbe_adv_rx_desc *rx_desc;
1864 struct sk_buff *skb;
f800326d
AD		 1865
1866 /* return some buffers to hardware, one at a time is too slow */
1867 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1868 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1869 cleaned_count = 0;
1870 }
1871
18806c9e 1872 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1873
1874 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1875 break;
9a799d71 1876
f800326d
AD		 1877 /*
1878 * This memory barrier is needed to keep us from reading
1879 * any other fields out of the rx_desc until we know the
1880 * RXD_STAT_DD bit is set
1881 */
1882 rmb();
9a799d71 1883
18806c9e
AD		 1884 /* retrieve a buffer from the ring */
1885 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1886
18806c9e
AD		 1887 /* exit if we failed to retrieve a buffer */
1888 if (!skb)
1889 break;
9a799d71 1890
9a799d71 1891 cleaned_count++;
f8212f97 1892
f800326d
AD		 1893 /* place incomplete frames back on ring for completion */
1894 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1895 continue;
c267fc16 1896
f800326d
AD		 1897 /* verify the packet layout is correct */
1898 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1899 continue;
9a799d71 1900
d2f4fbe2
AV		 1901 /* probably a little skewed due to removing CRC */
1902 total_rx_bytes += skb->len;
d2f4fbe2 1903
8a0da21b
AD		 1904 /* populate checksum, timestamp, VLAN, and protocol */
1905 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1906
332d4a7d
YZ		 1907#ifdef IXGBE_FCOE
1908 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1909 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1910 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 1911 /* include DDPed FCoE data */
1912 if (ddp_bytes > 0) {
1913 if (!mss) {
1914 mss = rx_ring->netdev->mtu -
1915 sizeof(struct fcoe_hdr) -
1916 sizeof(struct fc_frame_header) -
1917 sizeof(struct fcoe_crc_eof);
1918 if (mss > 512)
1919 mss &= ~511;
1920 }
1921 total_rx_bytes += ddp_bytes;
1922 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1923 mss);
1924 }
63d635b2
AD		 1925 if (!ddp_bytes) {
1926 dev_kfree_skb_any(skb);
f800326d 1927 continue;
63d635b2 1928 }
3d8fd385 1929 }
f800326d 1930
332d4a7d 1931#endif /* IXGBE_FCOE */
8a0da21b 1932 ixgbe_rx_skb(q_vector, skb);
9a799d71 1933
f800326d 1934 /* update budget accounting */
f4de00ed
AD		 1935 total_rx_packets++;
1936 } while (likely(total_rx_packets < budget));
9a799d71 1937
c267fc16
AD		 1938 u64_stats_update_begin(&rx_ring->syncp);
1939 rx_ring->stats.packets += total_rx_packets;
1940 rx_ring->stats.bytes += total_rx_bytes;
1941 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1942 q_vector->rx.total_packets += total_rx_packets;
1943 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1944
f800326d
AD		 1945 if (cleaned_count)
1946 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1947
f4de00ed 1948 return (total_rx_packets < budget);
9a799d71
AK		 1949}
1950
9a799d71
AK		 1951/**
1952 * ixgbe_configure_msix - Configure MSI-X hardware
1953 * @adapter: board private structure
1954 *
1955 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1956 * interrupts.
1957 **/
1958static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1959{
021230d4 1960 struct ixgbe_q_vector *q_vector;
49c7ffbe 1961 int v_idx;
021230d4 1962 u32 mask;
9a799d71 1963
8e34d1aa
AD		 1964 /* Populate MSIX to EITR Select */
1965 if (adapter->num_vfs > 32) {
1966 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1968 }
1969
4df10466
JB		 1970 /*
1971 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1972 * corresponding register.
1973 */
49c7ffbe 1974 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1975 struct ixgbe_ring *ring;
7a921c93 1976 q_vector = adapter->q_vector[v_idx];
021230d4 1977
a557928e 1978 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1979 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1980
a557928e 1981 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1982 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1983
fe49f04a 1984 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1985 }
1986
bd508178
AD		 1987 switch (adapter->hw.mac.type) {
1988 case ixgbe_mac_82598EB:
e8e26350 1989 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1990 v_idx);
bd508178
AD		 1991 break;
1992 case ixgbe_mac_82599EB:
b93a2226 1993 case ixgbe_mac_X540:
e8e26350 1994 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1995 break;
bd508178
AD		 1996 default:
1997 break;
1998 }
021230d4
AV		 1999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2000
41fb9248 2001 /* set up to autoclear timer, and the vectors */
021230d4 2002 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2003 mask &= ~(IXGBE_EIMS_OTHER |
2004 IXGBE_EIMS_MAILBOX |
2005 IXGBE_EIMS_LSC);
2006
021230d4 2007 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2008}
2009
f494e8fa
AV		 2010enum latency_range {
2011 lowest_latency = 0,
2012 low_latency = 1,
2013 bulk_latency = 2,
2014 latency_invalid = 255
2015};
2016
2017/**
2018 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2019 * @q_vector: structure containing interrupt and ring information
2020 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2021 *
2022 * Stores a new ITR value based on packets and byte
2023 * counts during the last interrupt. The advantage of per interrupt
2024 * computation is faster updates and more accurate ITR for the current
2025 * traffic pattern. Constants in this function were computed
2026 * based on theoretical maximum wire speed and thresholds were set based
2027 * on testing data as well as attempting to minimize response time
2028 * while increasing bulk throughput.
2029 * this functionality is controlled by the InterruptThrottleRate module
2030 * parameter (see ixgbe_param.c)
2031 **/
bd198058
AD		 2032static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2033 struct ixgbe_ring_container *ring_container)
f494e8fa 2034{
bd198058
AD		 2035 int bytes = ring_container->total_bytes;
2036 int packets = ring_container->total_packets;
2037 u32 timepassed_us;
621bd70e 2038 u64 bytes_perint;
bd198058 2039 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2040
2041 if (packets == 0)
bd198058 2042 return;
f494e8fa
AV		 2043
2044 /* simple throttlerate management
621bd70e
AD		 2045 * 0-10MB/s lowest (100000 ints/s)
2046 * 10-20MB/s low (20000 ints/s)
2047 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2048 */
2049 /* what was last interrupt timeslice? */
d5bf4f67 2050 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 2051 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2052
2053 switch (itr_setting) {
2054 case lowest_latency:
621bd70e 2055 if (bytes_perint > 10)
bd198058 2056 itr_setting = low_latency;
f494e8fa
AV		 2057 break;
2058 case low_latency:
621bd70e 2059 if (bytes_perint > 20)
bd198058 2060 itr_setting = bulk_latency;
621bd70e 2061 else if (bytes_perint <= 10)
bd198058 2062 itr_setting = lowest_latency;
f494e8fa
AV		 2063 break;
2064 case bulk_latency:
621bd70e 2065 if (bytes_perint <= 20)
bd198058 2066 itr_setting = low_latency;
f494e8fa
AV		 2067 break;
2068 }
2069
bd198058
AD		 2070 /* clear work counters since we have the values we need */
2071 ring_container->total_bytes = 0;
2072 ring_container->total_packets = 0;
2073
2074 /* write updated itr to ring container */
2075 ring_container->itr = itr_setting;
f494e8fa
AV		 2076}
2077
509ee935
JB		 2078/**
2079 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2080 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2081 *
2082 * This function is made to be called by ethtool and by the driver
2083 * when it needs to update EITR registers at runtime. Hardware
2084 * specific quirks/differences are taken care of here.
2085 */
fe49f04a 2086void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2087{
fe49f04a 2088 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2089 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2090 int v_idx = q_vector->v_idx;
5d967eb7 2091 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2092
bd508178
AD		 2093 switch (adapter->hw.mac.type) {
2094 case ixgbe_mac_82598EB:
509ee935
JB		 2095 /* must write high and low 16 bits to reset counter */
2096 itr_reg |= (itr_reg << 16);
bd508178
AD		 2097 break;
2098 case ixgbe_mac_82599EB:
b93a2226 2099 case ixgbe_mac_X540:
509ee935
JB		 2100 /*
2101 * set the WDIS bit to not clear the timer bits and cause an
2102 * immediate assertion of the interrupt
2103 */
2104 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2105 break;
2106 default:
2107 break;
509ee935
JB		 2108 }
2109 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2110}
2111
bd198058 2112static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2113{
d5bf4f67 2114 u32 new_itr = q_vector->itr;
bd198058 2115 u8 current_itr;
f494e8fa 2116
bd198058
AD		 2117 ixgbe_update_itr(q_vector, &q_vector->tx);
2118 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2119
08c8833b 2120 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2121
2122 switch (current_itr) {
2123 /* counts and packets in update_itr are dependent on these numbers */
2124 case lowest_latency:
d5bf4f67 2125 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2126 break;
2127 case low_latency:
d5bf4f67 2128 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2129 break;
2130 case bulk_latency:
d5bf4f67 2131 new_itr = IXGBE_8K_ITR;
f494e8fa 2132 break;
bd198058
AD		 2133 default:
2134 break;
f494e8fa
AV		 2135 }
2136
d5bf4f67 2137 if (new_itr != q_vector->itr) {
fe49f04a 2138 /* do an exponential smoothing */
d5bf4f67
ET		 2139 new_itr = (10 * new_itr * q_vector->itr) /
2140 ((9 * new_itr) + q_vector->itr);
509ee935 2141
bd198058 2142 /* save the algorithm value here */
5d967eb7 2143 q_vector->itr = new_itr;
fe49f04a
AD		 2144
2145 ixgbe_write_eitr(q_vector);
f494e8fa 2146 }
f494e8fa
AV		 2147}
2148
119fc60a 2149/**
de88eeeb 2150 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2151 * @adapter: pointer to adapter
119fc60a 2152 **/
f0f9778d 2153static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2154{
119fc60a
MC		 2155 struct ixgbe_hw *hw = &adapter->hw;
2156 u32 eicr = adapter->interrupt_event;
2157
f0f9778d 2158 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2159 return;
2160
f0f9778d
AD		 2161 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2162 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2163 return;
2164
2165 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2166
7ca647bd 2167 switch (hw->device_id) {
f0f9778d
AD		 2168 case IXGBE_DEV_ID_82599_T3_LOM:
2169 /*
2170 * Since the warning interrupt is for both ports
2171 * we don't have to check if:
2172 * - This interrupt wasn't for our port.
2173 * - We may have missed the interrupt so always have to
2174 * check if we got a LSC
2175 */
2176 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2177 !(eicr & IXGBE_EICR_LSC))
2178 return;
2179
2180 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2181 u32 speed;
f0f9778d 2182 bool link_up = false;
7ca647bd 2183
3d292265 2184 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2185
f0f9778d
AD		 2186 if (link_up)
2187 return;
2188 }
2189
2190 /* Check if this is not due to overtemp */
2191 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2192 return;
2193
2194 break;
7ca647bd
JP		 2195 default:
2196 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2197 return;
7ca647bd 2198 break;
119fc60a 2199 }
7ca647bd
JP		 2200 e_crit(drv,
2201 "Network adapter has been stopped because it has over heated. "
2202 "Restart the computer. If the problem persists, "
2203 "power off the system and replace the adapter\n");
f0f9778d
AD		 2204
2205 adapter->interrupt_event = 0;
119fc60a
MC		 2206}
2207
0befdb3e
JB		 2208static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2209{
2210 struct ixgbe_hw *hw = &adapter->hw;
2211
2212 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2213 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2214 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2215 /* write to clear the interrupt */
2216 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2217 }
2218}
cf8280ee 2219
4f51bf70
JK		 2220static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2221{
2222 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2223 return;
2224
2225 switch (adapter->hw.mac.type) {
2226 case ixgbe_mac_82599EB:
2227 /*
2228 * Need to check link state so complete overtemp check
2229 * on service task
2230 */
2231 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2232 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2233 adapter->interrupt_event = eicr;
2234 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2235 ixgbe_service_event_schedule(adapter);
2236 return;
2237 }
2238 return;
2239 case ixgbe_mac_X540:
2240 if (!(eicr & IXGBE_EICR_TS))
2241 return;
2242 break;
2243 default:
2244 return;
2245 }
2246
2247 e_crit(drv,
2248 "Network adapter has been stopped because it has over heated. "
2249 "Restart the computer. If the problem persists, "
2250 "power off the system and replace the adapter\n");
2251}
2252
e8e26350
PW		 2253static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2254{
2255 struct ixgbe_hw *hw = &adapter->hw;
2256
73c4b7cd
AD		 2257 if (eicr & IXGBE_EICR_GPI_SDP2) {
2258 /* Clear the interrupt */
2259 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2260 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2261 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2262 ixgbe_service_event_schedule(adapter);
2263 }
73c4b7cd
AD		 2264 }
2265
e8e26350
PW		 2266 if (eicr & IXGBE_EICR_GPI_SDP1) {
2267 /* Clear the interrupt */
2268 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2269 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2270 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2271 ixgbe_service_event_schedule(adapter);
2272 }
e8e26350
PW		 2273 }
2274}
2275
cf8280ee
JB		 2276static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2277{
2278 struct ixgbe_hw *hw = &adapter->hw;
2279
2280 adapter->lsc_int++;
2281 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2282 adapter->link_check_timeout = jiffies;
2283 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2284 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2285 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2286 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2287 }
2288}
2289
fe49f04a
AD		 2290static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2291 u64 qmask)
2292{
2293 u32 mask;
bd508178 2294 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2295
bd508178
AD		 2296 switch (hw->mac.type) {
2297 case ixgbe_mac_82598EB:
fe49f04a 2298 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2299 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2300 break;
2301 case ixgbe_mac_82599EB:
b93a2226 2302 case ixgbe_mac_X540:
fe49f04a 2303 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2304 if (mask)
2305 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2306 mask = (qmask >> 32);
bd508178
AD		 2307 if (mask)
2308 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2309 break;
2310 default:
2311 break;
fe49f04a
AD		 2312 }
2313 /* skip the flush */
2314}
2315
2316static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2317 u64 qmask)
fe49f04a
AD		 2318{
2319 u32 mask;
bd508178 2320 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2321
bd508178
AD		 2322 switch (hw->mac.type) {
2323 case ixgbe_mac_82598EB:
fe49f04a 2324 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2325 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2326 break;
2327 case ixgbe_mac_82599EB:
b93a2226 2328 case ixgbe_mac_X540:
fe49f04a 2329 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2330 if (mask)
2331 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2332 mask = (qmask >> 32);
bd508178
AD		 2333 if (mask)
2334 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2335 break;
2336 default:
2337 break;
fe49f04a
AD		 2338 }
2339 /* skip the flush */
2340}
2341
021230d4 2342/**
2c4af694
AD		 2343 * ixgbe_irq_enable - Enable default interrupt generation settings
2344 * @adapter: board private structure
021230d4 2345 **/
2c4af694
AD		 2346static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2347 bool flush)
9a799d71 2348{
2c4af694 2349 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2350
2c4af694
AD		 2351 /* don't reenable LSC while waiting for link */
2352 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2353 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2354
2c4af694 2355 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2356 switch (adapter->hw.mac.type) {
2357 case ixgbe_mac_82599EB:
2358 mask |= IXGBE_EIMS_GPI_SDP0;
2359 break;
2360 case ixgbe_mac_X540:
2361 mask |= IXGBE_EIMS_TS;
2362 break;
2363 default:
2364 break;
2365 }
2c4af694
AD		 2366 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2367 mask |= IXGBE_EIMS_GPI_SDP1;
2368 switch (adapter->hw.mac.type) {
2369 case ixgbe_mac_82599EB:
2c4af694
AD		 2370 mask |= IXGBE_EIMS_GPI_SDP1;
2371 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2372 case ixgbe_mac_X540:
2373 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2374 mask |= IXGBE_EIMS_MAILBOX;
2375 break;
2376 default:
2377 break;
9a799d71 2378 }
db0677fa 2379
db0677fa
JK		 2380 if (adapter->hw.mac.type == ixgbe_mac_X540)
2381 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2382
2c4af694
AD		 2383 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2384 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2385 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2386
2c4af694
AD		 2387 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2388 if (queues)
2389 ixgbe_irq_enable_queues(adapter, ~0);
2390 if (flush)
2391 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2392}
2393
2c4af694 2394static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2395{
a65151ba 2396 struct ixgbe_adapter *adapter = data;
9a799d71 2397 struct ixgbe_hw *hw = &adapter->hw;
54037505 2398 u32 eicr;
91281fd3 2399
54037505
DS		 2400 /*
2401 * Workaround for Silicon errata. Use clear-by-write instead
2402 * of clear-by-read. Reading with EICS will return the
2403 * interrupt causes without clearing, which later be done
2404 * with the write to EICR.
2405 */
2406 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2407 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2408
cf8280ee
JB		 2409 if (eicr & IXGBE_EICR_LSC)
2410 ixgbe_check_lsc(adapter);
f0848276 2411
1cdd1ec8
GR		 2412 if (eicr & IXGBE_EICR_MAILBOX)
2413 ixgbe_msg_task(adapter);
efe3d3c8 2414
bd508178
AD		 2415 switch (hw->mac.type) {
2416 case ixgbe_mac_82599EB:
b93a2226 2417 case ixgbe_mac_X540:
2c4af694
AD		 2418 if (eicr & IXGBE_EICR_ECC)
2419 e_info(link, "Received unrecoverable ECC Err, please "
2420 "reboot\n");
c4cf55e5
PWJ		 2421 /* Handle Flow Director Full threshold interrupt */
2422 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2423 int reinit_count = 0;
c4cf55e5 2424 int i;
c4cf55e5 2425 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2426 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2427 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2428 &ring->state))
2429 reinit_count++;
2430 }
2431 if (reinit_count) {
2432 /* no more flow director interrupts until after init */
2433 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2434 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2435 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2436 }
2437 }
f0f9778d 2438 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2439 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2440 break;
2441 default:
2442 break;
c4cf55e5 2443 }
f0848276 2444
bd508178 2445 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2446
db0677fa
JK		 2447 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2448 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2449
7086400d 2450 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2451 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2452 ixgbe_irq_enable(adapter, false, false);
f0848276 2453
9a799d71 2454 return IRQ_HANDLED;
f0848276 2455}
91281fd3 2456
4ff7fb12 2457static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2458{
021230d4 2459 struct ixgbe_q_vector *q_vector = data;
91281fd3 2460
9b471446 2461 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2462
4ff7fb12
AD		 2463 if (q_vector->rx.ring || q_vector->tx.ring)
2464 napi_schedule(&q_vector->napi);
91281fd3 2465
9a799d71 2466 return IRQ_HANDLED;
91281fd3
AD		 2467}
2468
eb01b975
AD		 2469/**
2470 * ixgbe_poll - NAPI Rx polling callback
2471 * @napi: structure for representing this polling device
2472 * @budget: how many packets driver is allowed to clean
2473 *
2474 * This function is used for legacy and MSI, NAPI mode
2475 **/
8af3c33f 2476int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2477{
2478 struct ixgbe_q_vector *q_vector =
2479 container_of(napi, struct ixgbe_q_vector, napi);
2480 struct ixgbe_adapter *adapter = q_vector->adapter;
2481 struct ixgbe_ring *ring;
2482 int per_ring_budget;
2483 bool clean_complete = true;
2484
2485#ifdef CONFIG_IXGBE_DCA
2486 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2487 ixgbe_update_dca(q_vector);
2488#endif
2489
2490 ixgbe_for_each_ring(ring, q_vector->tx)
2491 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2492
2493 /* attempt to distribute budget to each queue fairly, but don't allow
2494 * the budget to go below 1 because we'll exit polling */
2495 if (q_vector->rx.count > 1)
2496 per_ring_budget = max(budget/q_vector->rx.count, 1);
2497 else
2498 per_ring_budget = budget;
2499
2500 ixgbe_for_each_ring(ring, q_vector->rx)
2501 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2502 per_ring_budget);
2503
2504 /* If all work not completed, return budget and keep polling */
2505 if (!clean_complete)
2506 return budget;
2507
2508 /* all work done, exit the polling mode */
2509 napi_complete(napi);
2510 if (adapter->rx_itr_setting & 1)
2511 ixgbe_set_itr(q_vector);
2512 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2513 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2514
2515 return 0;
2516}
2517
021230d4
AV		 2518/**
2519 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2520 * @adapter: board private structure
2521 *
2522 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2523 * interrupts from the kernel.
2524 **/
2525static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2526{
2527 struct net_device *netdev = adapter->netdev;
207867f5 2528 int vector, err;
e8e9f696 2529 int ri = 0, ti = 0;
021230d4 2530
49c7ffbe 2531 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2532 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2533 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2534
4ff7fb12 2535 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2536 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2537 "%s-%s-%d", netdev->name, "TxRx", ri++);
2538 ti++;
2539 } else if (q_vector->rx.ring) {
9fe93afd 2540 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2541 "%s-%s-%d", netdev->name, "rx", ri++);
2542 } else if (q_vector->tx.ring) {
9fe93afd 2543 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2544 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2545 } else {
2546 /* skip this unused q_vector */
2547 continue;
32aa77a4 2548 }
207867f5
AD		 2549 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2550 q_vector->name, q_vector);
9a799d71 2551 if (err) {
396e799c 2552 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2553 "Error: %d\n", err);
021230d4 2554 goto free_queue_irqs;
9a799d71 2555 }
207867f5
AD		 2556 /* If Flow Director is enabled, set interrupt affinity */
2557 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2558 /* assign the mask for this irq */
2559 irq_set_affinity_hint(entry->vector,
de88eeeb 2560 &q_vector->affinity_mask);
207867f5 2561 }
9a799d71
AK		 2562 }
2563
021230d4 2564 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2565 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2566 if (err) {
de88eeeb 2567 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2568 goto free_queue_irqs;
9a799d71
AK		 2569 }
2570
9a799d71
AK		 2571 return 0;
2572
021230d4 2573free_queue_irqs:
207867f5
AD		 2574 while (vector) {
2575 vector--;
2576 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2577 NULL);
2578 free_irq(adapter->msix_entries[vector].vector,
2579 adapter->q_vector[vector]);
2580 }
021230d4
AV		 2581 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2582 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2583 kfree(adapter->msix_entries);
2584 adapter->msix_entries = NULL;
9a799d71
AK		 2585 return err;
2586}
2587
2588/**
021230d4 2589 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2590 * @irq: interrupt number
2591 * @data: pointer to a network interface device structure
9a799d71
AK		 2592 **/
2593static irqreturn_t ixgbe_intr(int irq, void *data)
2594{
a65151ba 2595 struct ixgbe_adapter *adapter = data;
9a799d71 2596 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2597 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2598 u32 eicr;
2599
54037505 2600 /*
24ddd967 2601 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2602 * before the read of EICR.
2603 */
2604 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2605
021230d4 2606 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2607 * therefore no explicit interrupt disable is necessary */
021230d4 2608 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2609 if (!eicr) {
6af3b9eb
ET		 2610 /*
2611 * shared interrupt alert!
f47cf66e 2612 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2613 * have disabled interrupts due to EIAM
2614 * finish the workaround of silicon errata on 82598. Unmask
2615 * the interrupt that we masked before the EICR read.
2616 */
2617 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2618 ixgbe_irq_enable(adapter, true, true);
9a799d71 2619 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2620 }
9a799d71 2621
cf8280ee
JB		 2622 if (eicr & IXGBE_EICR_LSC)
2623 ixgbe_check_lsc(adapter);
021230d4 2624
bd508178
AD		 2625 switch (hw->mac.type) {
2626 case ixgbe_mac_82599EB:
e8e26350 2627 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2628 /* Fall through */
2629 case ixgbe_mac_X540:
2630 if (eicr & IXGBE_EICR_ECC)
2631 e_info(link, "Received unrecoverable ECC err, please "
2632 "reboot\n");
4f51bf70 2633 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2634 break;
2635 default:
2636 break;
2637 }
e8e26350 2638
0befdb3e 2639 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2640 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2641 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2642
b9f6ed2b
AD		 2643 /* would disable interrupts here but EIAM disabled it */
2644 napi_schedule(&q_vector->napi);
9a799d71 2645
6af3b9eb
ET		 2646 /*
2647 * re-enable link(maybe) and non-queue interrupts, no flush.
2648 * ixgbe_poll will re-enable the queue interrupts
2649 */
6af3b9eb
ET		 2650 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2651 ixgbe_irq_enable(adapter, false, false);
2652
9a799d71
AK		 2653 return IRQ_HANDLED;
2654}
2655
2656/**
2657 * ixgbe_request_irq - initialize interrupts
2658 * @adapter: board private structure
2659 *
2660 * Attempts to configure interrupts using the best available
2661 * capabilities of the hardware and kernel.
2662 **/
021230d4 2663static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2664{
2665 struct net_device *netdev = adapter->netdev;
021230d4 2666 int err;
9a799d71 2667
4cc6df29 2668 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2669 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2670 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2671 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2672 netdev->name, adapter);
4cc6df29 2673 else
a0607fd3 2674 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2675 netdev->name, adapter);
9a799d71 2676
de88eeeb 2677 if (err)
396e799c 2678 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2679
9a799d71
AK		 2680 return err;
2681}
2682
2683static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2684{
49c7ffbe 2685 int vector;
9a799d71 2686
49c7ffbe
AD		 2687 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2688 free_irq(adapter->pdev->irq, adapter);
2689 return;
2690 }
4cc6df29 2691
49c7ffbe
AD		 2692 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2693 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2694 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2695
49c7ffbe
AD		 2696 /* free only the irqs that were actually requested */
2697 if (!q_vector->rx.ring && !q_vector->tx.ring)
2698 continue;
207867f5 2699
49c7ffbe
AD		 2700 /* clear the affinity_mask in the IRQ descriptor */
2701 irq_set_affinity_hint(entry->vector, NULL);
2702
2703 free_irq(entry->vector, q_vector);
9a799d71 2704 }
49c7ffbe
AD		 2705
2706 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2707}
2708
22d5a71b
JB		 2709/**
2710 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2711 * @adapter: board private structure
2712 **/
2713static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2714{
bd508178
AD		 2715 switch (adapter->hw.mac.type) {
2716 case ixgbe_mac_82598EB:
835462fc 2717 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2718 break;
2719 case ixgbe_mac_82599EB:
b93a2226 2720 case ixgbe_mac_X540:
835462fc
NS		 2721 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2724 break;
2725 default:
2726 break;
22d5a71b
JB		 2727 }
2728 IXGBE_WRITE_FLUSH(&adapter->hw);
2729 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2730 int vector;
2731
2732 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2733 synchronize_irq(adapter->msix_entries[vector].vector);
2734
2735 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2736 } else {
2737 synchronize_irq(adapter->pdev->irq);
2738 }
2739}
2740
9a799d71
AK		 2741/**
2742 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2743 *
2744 **/
2745static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2746{
d5bf4f67 2747 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2748
d5bf4f67 2749 ixgbe_write_eitr(q_vector);
9a799d71 2750
e8e26350
PW		 2751 ixgbe_set_ivar(adapter, 0, 0, 0);
2752 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2753
396e799c 2754 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2755}
2756
43e69bf0
AD		 2757/**
2758 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2759 * @adapter: board private structure
2760 * @ring: structure containing ring specific data
2761 *
2762 * Configure the Tx descriptor ring after a reset.
2763 **/
84418e3b
AD		 2764void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2765 struct ixgbe_ring *ring)
43e69bf0
AD		 2766{
2767 struct ixgbe_hw *hw = &adapter->hw;
2768 u64 tdba = ring->dma;
2f1860b8 2769 int wait_loop = 10;
b88c6de2 2770 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2771 u8 reg_idx = ring->reg_idx;
43e69bf0 2772
2f1860b8 2773 /* disable queue to avoid issues while updating state */
b88c6de2 2774 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2775 IXGBE_WRITE_FLUSH(hw);
2776
43e69bf0 2777 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2778 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2779 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2780 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2781 ring->count * sizeof(union ixgbe_adv_tx_desc));
2782 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2783 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2784 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2785
b88c6de2
AD		 2786 /*
2787 * set WTHRESH to encourage burst writeback, it should not be set
2788 * higher than 1 when ITR is 0 as it could cause false TX hangs
2789 *
2790 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2791 * to or less than the number of on chip descriptors, which is
2792 * currently 40.
2793 */
e954b374 2794 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2795 txdctl |= (1 << 16); /* WTHRESH = 1 */
2796 else
2797 txdctl |= (8 << 16); /* WTHRESH = 8 */
2798
e954b374
AD		 2799 /*
2800 * Setting PTHRESH to 32 both improves performance
2801 * and avoids a TX hang with DFP enabled
2802 */
b88c6de2
AD		 2803 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2804 32; /* PTHRESH = 32 */
2f1860b8
AD		 2805
2806 /* reinitialize flowdirector state */
39cb681b 2807 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2808 ring->atr_sample_rate = adapter->atr_sample_rate;
2809 ring->atr_count = 0;
2810 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2811 } else {
2812 ring->atr_sample_rate = 0;
2813 }
2f1860b8 2814
c84d324c
JF		 2815 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2816
2f1860b8 2817 /* enable queue */
2f1860b8
AD		 2818 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2819
2820 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2821 if (hw->mac.type == ixgbe_mac_82598EB &&
2822 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2823 return;
2824
2825 /* poll to verify queue is enabled */
2826 do {
032b4325 2827 usleep_range(1000, 2000);
2f1860b8
AD		 2828 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2829 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2830 if (!wait_loop)
2831 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2832}
2833
120ff942
AD		 2834static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2835{
2836 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2837 u32 rttdcs, mtqc;
8b1c0b24 2838 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2839
2840 if (hw->mac.type == ixgbe_mac_82598EB)
2841 return;
2842
2843 /* disable the arbiter while setting MTQC */
2844 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2845 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2846 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2847
2848 /* set transmit pool layout */
671c0adb
AD		 2849 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2850 mtqc = IXGBE_MTQC_VT_ENA;
2851 if (tcs > 4)
2852 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2853 else if (tcs > 1)
2854 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2855 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2856 mtqc |= IXGBE_MTQC_32VF;
2857 else
2858 mtqc |= IXGBE_MTQC_64VF;
2859 } else {
2860 if (tcs > 4)
2861 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2862 else if (tcs > 1)
2863 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2864 else
671c0adb
AD		 2865 mtqc = IXGBE_MTQC_64Q_1PB;
2866 }
120ff942 2867
671c0adb 2868 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2869
671c0adb
AD		 2870 /* Enable Security TX Buffer IFG for multiple pb */
2871 if (tcs) {
2872 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2873 sectx |= IXGBE_SECTX_DCB;
2874 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2875 }
2876
2877 /* re-enable the arbiter */
2878 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2879 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2880}
2881
9a799d71 2882/**
3a581073 2883 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2884 * @adapter: board private structure
2885 *
2886 * Configure the Tx unit of the MAC after a reset.
2887 **/
2888static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2889{
2f1860b8
AD		 2890 struct ixgbe_hw *hw = &adapter->hw;
2891 u32 dmatxctl;
43e69bf0 2892 u32 i;
9a799d71 2893
2f1860b8
AD		 2894 ixgbe_setup_mtqc(adapter);
2895
2896 if (hw->mac.type != ixgbe_mac_82598EB) {
2897 /* DMATXCTL.EN must be before Tx queues are enabled */
2898 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2899 dmatxctl |= IXGBE_DMATXCTL_TE;
2900 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2901 }
2902
9a799d71 2903 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2904 for (i = 0; i < adapter->num_tx_queues; i++)
2905 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2906}
2907
3ebe8fde
AD		 2908static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2909 struct ixgbe_ring *ring)
2910{
2911 struct ixgbe_hw *hw = &adapter->hw;
2912 u8 reg_idx = ring->reg_idx;
2913 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2914
2915 srrctl |= IXGBE_SRRCTL_DROP_EN;
2916
2917 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2918}
2919
2920static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2921 struct ixgbe_ring *ring)
2922{
2923 struct ixgbe_hw *hw = &adapter->hw;
2924 u8 reg_idx = ring->reg_idx;
2925 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2926
2927 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2928
2929 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2930}
2931
2932#ifdef CONFIG_IXGBE_DCB
2933void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2934#else
2935static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2936#endif
2937{
2938 int i;
2939 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2940
2941 if (adapter->ixgbe_ieee_pfc)
2942 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2943
2944 /*
2945 * We should set the drop enable bit if:
2946 * SR-IOV is enabled
2947 * or
2948 * Number of Rx queues > 1 and flow control is disabled
2949 *
2950 * This allows us to avoid head of line blocking for security
2951 * and performance reasons.
2952 */
2953 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2954 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2955 for (i = 0; i < adapter->num_rx_queues; i++)
2956 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2957 } else {
2958 for (i = 0; i < adapter->num_rx_queues; i++)
2959 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2960 }
2961}
2962
e8e26350 2963#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2964
a6616b42 2965static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2966 struct ixgbe_ring *rx_ring)
cc41ac7c 2967{
45e9baa5 2968 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2969 u32 srrctl;
bf29ee6c 2970 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2971
45e9baa5
AD		 2972 if (hw->mac.type == ixgbe_mac_82598EB) {
2973 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2974
45e9baa5
AD		 2975 /*
2976 * if VMDq is not active we must program one srrctl register
2977 * per RSS queue since we have enabled RDRXCTL.MVMEN
2978 */
2979 reg_idx &= mask;
2980 }
cc41ac7c 2981
45e9baa5
AD		 2982 /* configure header buffer length, needed for RSC */
2983 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2984
45e9baa5 2985 /* configure the packet buffer length */
f800326d 2986 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2987
2988 /* configure descriptor type */
f800326d 2989 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2990
45e9baa5 2991 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2992}
9a799d71 2993
05abb126 2994static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2995{
05abb126
AD		 2996 struct ixgbe_hw *hw = &adapter->hw;
2997 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2998 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2999 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3000 u32 mrqc = 0, reta = 0;
3001 u32 rxcsum;
3002 int i, j;
671c0adb
AD		 3003 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3004
671c0adb
AD		 3005 /*
3006 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3007 * make full use of any rings they may have. We will use the
3008 * PSRTYPE register to control how many rings we use within the PF.
3009 */
3010 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3011 rss_i = 2;
0cefafad 3012
05abb126
AD		 3013 /* Fill out hash function seeds */
3014 for (i = 0; i < 10; i++)
3015 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3016
3017 /* Fill out redirection table */
3018 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3019 if (j == rss_i)
05abb126
AD		 3020 j = 0;
3021 /* reta = 4-byte sliding window of
3022 * 0x00..(indices-1)(indices-1)00..etc. */
3023 reta = (reta << 8) | (j * 0x11);
3024 if ((i & 3) == 3)
3025 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3026 }
0cefafad 3027
05abb126
AD		 3028 /* Disable indicating checksum in descriptor, enables RSS hash */
3029 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3030 rxcsum |= IXGBE_RXCSUM_PCSD;
3031 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3032
671c0adb 3033 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3034 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3035 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3036 } else {
671c0adb
AD		 3037 u8 tcs = netdev_get_num_tc(adapter->netdev);
3038
3039 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3040 if (tcs > 4)
3041 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3042 else if (tcs > 1)
3043 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3044 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3045 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3046 else
671c0adb
AD		 3047 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3048 } else {
3049 if (tcs > 4)
8b1c0b24 3050 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3051 else if (tcs > 1)
3052 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3053 else
3054 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3055 }
0cefafad
JB		 3056 }
3057
05abb126 3058 /* Perform hash on these packet types */
671c0adb
AD		 3059 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3060 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3061 IXGBE_MRQC_RSS_FIELD_IPV6 |
3062 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3063
ef6afc0c
AD		 3064 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3065 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3066 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3067 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3068
05abb126 3069 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3070}
3071
bb5a9ad2
NS		 3072/**
3073 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3074 * @adapter: address of board private structure
3075 * @index: index of ring to set
bb5a9ad2 3076 **/
082757af 3077static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3078 struct ixgbe_ring *ring)
bb5a9ad2 3079{
bb5a9ad2 3080 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3081 u32 rscctrl;
bf29ee6c 3082 u8 reg_idx = ring->reg_idx;
7367096a 3083
7d637bcc 3084 if (!ring_is_rsc_enabled(ring))
7367096a 3085 return;
bb5a9ad2 3086
7367096a 3087 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3088 rscctrl |= IXGBE_RSCCTL_RSCEN;
3089 /*
3090 * we must limit the number of descriptors so that the
3091 * total size of max desc * buf_len is not greater
642c680e 3092 * than 65536
bb5a9ad2 3093 */
f800326d 3094 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3095 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3096}
3097
9e10e045
AD		 3098#define IXGBE_MAX_RX_DESC_POLL 10
3099static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3100 struct ixgbe_ring *ring)
3101{
3102 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3103 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3104 u32 rxdctl;
bf29ee6c 3105 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3106
3107 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3108 if (hw->mac.type == ixgbe_mac_82598EB &&
3109 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3110 return;
3111
3112 do {
032b4325 3113 usleep_range(1000, 2000);
9e10e045
AD		 3114 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3115 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3116
3117 if (!wait_loop) {
3118 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3119 "the polling period\n", reg_idx);
3120 }
3121}
3122
2d39d576
YZ		 3123void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3124 struct ixgbe_ring *ring)
3125{
3126 struct ixgbe_hw *hw = &adapter->hw;
3127 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3128 u32 rxdctl;
3129 u8 reg_idx = ring->reg_idx;
3130
3131 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3132 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3133
3134 /* write value back with RXDCTL.ENABLE bit cleared */
3135 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3136
3137 if (hw->mac.type == ixgbe_mac_82598EB &&
3138 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3139 return;
3140
3141 /* the hardware may take up to 100us to really disable the rx queue */
3142 do {
3143 udelay(10);
3144 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3145 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3146
3147 if (!wait_loop) {
3148 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3149 "the polling period\n", reg_idx);
3150 }
3151}
3152
84418e3b
AD		 3153void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3154 struct ixgbe_ring *ring)
acd37177
AD		 3155{
3156 struct ixgbe_hw *hw = &adapter->hw;
3157 u64 rdba = ring->dma;
9e10e045 3158 u32 rxdctl;
bf29ee6c 3159 u8 reg_idx = ring->reg_idx;
acd37177 3160
9e10e045
AD		 3161 /* disable queue to avoid issues while updating state */
3162 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3163 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3164
acd37177
AD		 3165 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3166 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3167 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3168 ring->count * sizeof(union ixgbe_adv_rx_desc));
3169 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3170 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3171 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3172
3173 ixgbe_configure_srrctl(adapter, ring);
3174 ixgbe_configure_rscctl(adapter, ring);
3175
3176 if (hw->mac.type == ixgbe_mac_82598EB) {
3177 /*
3178 * enable cache line friendly hardware writes:
3179 * PTHRESH=32 descriptors (half the internal cache),
3180 * this also removes ugly rx_no_buffer_count increment
3181 * HTHRESH=4 descriptors (to minimize latency on fetch)
3182 * WTHRESH=8 burst writeback up to two cache lines
3183 */
3184 rxdctl &= ~0x3FFFFF;
3185 rxdctl |= 0x080420;
3186 }
3187
3188 /* enable receive descriptor ring */
3189 rxdctl |= IXGBE_RXDCTL_ENABLE;
3190 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3191
3192 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3193 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3194}
3195
48654521
AD		 3196static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3197{
3198 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3199 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3200 int p;
3201
3202 /* PSRTYPE must be initialized in non 82598 adapters */
3203 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3204 IXGBE_PSRTYPE_UDPHDR |
3205 IXGBE_PSRTYPE_IPV4HDR |
48654521 3206 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3207 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3208
3209 if (hw->mac.type == ixgbe_mac_82598EB)
3210 return;
3211
fbe7ca7f
AD		 3212 if (rss_i > 3)
3213 psrtype |= 2 << 29;
3214 else if (rss_i > 1)
3215 psrtype |= 1 << 29;
48654521
AD		 3216
3217 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3218 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3219 psrtype);
3220}
3221
f5b4a52e
AD		 3222static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3223{
3224 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3225 u32 reg_offset, vf_shift;
435b19f6 3226 u32 gcr_ext, vmdctl;
de4c7f65 3227 int i;
f5b4a52e
AD		 3228
3229 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3230 return;
3231
3232 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3233 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3234 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3235 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3236 vmdctl |= IXGBE_VT_CTL_REPLEN;
3237 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3238
1d9c0bfd
AD		 3239 vf_shift = VMDQ_P(0) % 32;
3240 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3241
3242 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3243 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3244 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3245 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3246 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3247 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3248 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3249
3250 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3251 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3252
3253 /*
3254 * Set up VF register offsets for selected VT Mode,
3255 * i.e. 32 or 64 VFs for SR-IOV
3256 */
73079ea0
AD		 3257 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3258 case IXGBE_82599_VMDQ_8Q_MASK:
3259 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3260 break;
3261 case IXGBE_82599_VMDQ_4Q_MASK:
3262 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3263 break;
3264 default:
3265 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3266 break;
3267 }
3268
f5b4a52e
AD		 3269 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3270
435b19f6 3271
a985b6c3 3272 /* Enable MAC Anti-Spoofing */
435b19f6 3273 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3274 adapter->num_vfs);
de4c7f65
GR		 3275 /* For VFs that have spoof checking turned off */
3276 for (i = 0; i < adapter->num_vfs; i++) {
3277 if (!adapter->vfinfo[i].spoofchk_enabled)
3278 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3279 }
f5b4a52e
AD		 3280}
3281
477de6ed 3282static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3283{
9a799d71
AK		 3284 struct ixgbe_hw *hw = &adapter->hw;
3285 struct net_device *netdev = adapter->netdev;
3286 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3287 struct ixgbe_ring *rx_ring;
3288 int i;
3289 u32 mhadd, hlreg0;
48654521 3290
63f39bd1 3291#ifdef IXGBE_FCOE
477de6ed
AD		 3292 /* adjust max frame to be able to do baby jumbo for FCoE */
3293 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3294 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3295 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3296
477de6ed 3297#endif /* IXGBE_FCOE */
872844dd
AD		 3298
3299 /* adjust max frame to be at least the size of a standard frame */
3300 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3301 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3302
477de6ed
AD		 3303 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3304 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3305 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3306 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3307
3308 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3309 }
3310
3311 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3312 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3313 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3314 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3315
0cefafad
JB		 3316 /*
3317 * Setup the HW Rx Head and Tail Descriptor Pointers and
3318 * the Base and Length of the Rx Descriptor Ring
3319 */
9a799d71 3320 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3321 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3322 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3323 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3324 else
7d637bcc 3325 clear_ring_rsc_enabled(rx_ring);
477de6ed 3326 }
477de6ed
AD		 3327}
3328
7367096a
AD		 3329static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3330{
3331 struct ixgbe_hw *hw = &adapter->hw;
3332 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3333
3334 switch (hw->mac.type) {
3335 case ixgbe_mac_82598EB:
3336 /*
3337 * For VMDq support of different descriptor types or
3338 * buffer sizes through the use of multiple SRRCTL
3339 * registers, RDRXCTL.MVMEN must be set to 1
3340 *
3341 * also, the manual doesn't mention it clearly but DCA hints
3342 * will only use queue 0's tags unless this bit is set. Side
3343 * effects of setting this bit are only that SRRCTL must be
3344 * fully programmed [0..15]
3345 */
3346 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3347 break;
3348 case ixgbe_mac_82599EB:
b93a2226 3349 case ixgbe_mac_X540:
7367096a
AD		 3350 /* Disable RSC for ACK packets */
3351 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3352 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3353 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3354 /* hardware requires some bits to be set by default */
3355 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3356 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3357 break;
3358 default:
3359 /* We should do nothing since we don't know this hardware */
3360 return;
3361 }
3362
3363 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3364}
3365
477de6ed
AD		 3366/**
3367 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3368 * @adapter: board private structure
3369 *
3370 * Configure the Rx unit of the MAC after a reset.
3371 **/
3372static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3373{
3374 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3375 int i;
3376 u32 rxctrl;
477de6ed
AD		 3377
3378 /* disable receives while setting up the descriptors */
3379 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3380 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3381
3382 ixgbe_setup_psrtype(adapter);
7367096a 3383 ixgbe_setup_rdrxctl(adapter);
477de6ed 3384
9e10e045 3385 /* Program registers for the distribution of queues */
f5b4a52e 3386 ixgbe_setup_mrqc(adapter);
f5b4a52e 3387
477de6ed
AD		 3388 /* set_rx_buffer_len must be called before ring initialization */
3389 ixgbe_set_rx_buffer_len(adapter);
3390
3391 /*
3392 * Setup the HW Rx Head and Tail Descriptor Pointers and
3393 * the Base and Length of the Rx Descriptor Ring
3394 */
9e10e045
AD		 3395 for (i = 0; i < adapter->num_rx_queues; i++)
3396 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3397
9e10e045
AD		 3398 /* disable drop enable for 82598 parts */
3399 if (hw->mac.type == ixgbe_mac_82598EB)
3400 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3401
3402 /* enable all receives */
3403 rxctrl |= IXGBE_RXCTRL_RXEN;
3404 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3405}
3406
8e586137 3407static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3408{
3409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3410 struct ixgbe_hw *hw = &adapter->hw;
3411
3412 /* add VID to filter table */
1d9c0bfd 3413 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3414 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3415
3416 return 0;
068c89b0
DS		 3417}
3418
8e586137 3419static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3420{
3421 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3422 struct ixgbe_hw *hw = &adapter->hw;
3423
068c89b0 3424 /* remove VID from filter table */
1d9c0bfd 3425 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3426 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3427
3428 return 0;
068c89b0
DS		 3429}
3430
5f6c0181
JB		 3431/**
3432 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3433 * @adapter: driver data
3434 */
3435static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3436{
3437 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3438 u32 vlnctrl;
3439
3440 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3441 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3442 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3443}
3444
3445/**
3446 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3447 * @adapter: driver data
3448 */
3449static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3450{
3451 struct ixgbe_hw *hw = &adapter->hw;
3452 u32 vlnctrl;
3453
3454 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3455 vlnctrl |= IXGBE_VLNCTRL_VFE;
3456 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3457 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3458}
3459
3460/**
3461 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3462 * @adapter: driver data
3463 */
3464static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3465{
3466 struct ixgbe_hw *hw = &adapter->hw;
3467 u32 vlnctrl;
5f6c0181
JB		 3468 int i, j;
3469
3470 switch (hw->mac.type) {
3471 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3472 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3473 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3474 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3475 break;
3476 case ixgbe_mac_82599EB:
b93a2226 3477 case ixgbe_mac_X540:
5f6c0181
JB		 3478 for (i = 0; i < adapter->num_rx_queues; i++) {
3479 j = adapter->rx_ring[i]->reg_idx;
3480 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3481 vlnctrl &= ~IXGBE_RXDCTL_VME;
3482 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3483 }
3484 break;
3485 default:
3486 break;
3487 }
3488}
3489
3490/**
f62bbb5e 3491 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3492 * @adapter: driver data
3493 */
f62bbb5e 3494static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3495{
3496 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3497 u32 vlnctrl;
5f6c0181
JB		 3498 int i, j;
3499
3500 switch (hw->mac.type) {
3501 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3502 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3503 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3504 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3505 break;
3506 case ixgbe_mac_82599EB:
b93a2226 3507 case ixgbe_mac_X540:
5f6c0181
JB		 3508 for (i = 0; i < adapter->num_rx_queues; i++) {
3509 j = adapter->rx_ring[i]->reg_idx;
3510 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3511 vlnctrl |= IXGBE_RXDCTL_VME;
3512 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3513 }
3514 break;
3515 default:
3516 break;
3517 }
3518}
3519
9a799d71
AK		 3520static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3521{
f62bbb5e 3522 u16 vid;
9a799d71 3523
f62bbb5e
JG		 3524 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3525
3526 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3527 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3528}
3529
2850062a
AD		 3530/**
3531 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3532 * @netdev: network interface device structure
3533 *
3534 * Writes unicast address list to the RAR table.
3535 * Returns: -ENOMEM on failure/insufficient address space
3536 * 0 on no addresses written
3537 * X on writing X addresses to the RAR table
3538 **/
3539static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3540{
3541 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3542 struct ixgbe_hw *hw = &adapter->hw;
95447461 3543 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3544 int count = 0;
3545
95447461
JF		 3546 /* In SR-IOV mode significantly less RAR entries are available */
3547 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3548 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3549
2850062a
AD		 3550 /* return ENOMEM indicating insufficient memory for addresses */
3551 if (netdev_uc_count(netdev) > rar_entries)
3552 return -ENOMEM;
3553
95447461 3554 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3555 struct netdev_hw_addr *ha;
3556 /* return error if we do not support writing to RAR table */
3557 if (!hw->mac.ops.set_rar)
3558 return -ENOMEM;
3559
3560 netdev_for_each_uc_addr(ha, netdev) {
3561 if (!rar_entries)
3562 break;
3563 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3564 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3565 count++;
3566 }
3567 }
3568 /* write the addresses in reverse order to avoid write combining */
3569 for (; rar_entries > 0 ; rar_entries--)
3570 hw->mac.ops.clear_rar(hw, rar_entries);
3571
3572 return count;
3573}
3574
9a799d71 3575/**
2c5645cf 3576 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3577 * @netdev: network interface device structure
3578 *
2c5645cf
CL		 3579 * The set_rx_method entry point is called whenever the unicast/multicast
3580 * address list or the network interface flags are updated. This routine is
3581 * responsible for configuring the hardware for proper unicast, multicast and
3582 * promiscuous mode.
9a799d71 3583 **/
7f870475 3584void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3585{
3586 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3587 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3588 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3589 int count;
9a799d71
AK		 3590
3591 /* Check for Promiscuous and All Multicast modes */
3592
3593 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3594
f5dc442b 3595 /* set all bits that we expect to always be set */
3f2d1c0f 3596 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3597 fctrl |= IXGBE_FCTRL_BAM;
3598 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3599 fctrl |= IXGBE_FCTRL_PMCF;
3600
2850062a
AD		 3601 /* clear the bits we are changing the status of */
3602 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3603
9a799d71 3604 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3605 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3606 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3607 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3608 /* don't hardware filter vlans in promisc mode */
3609 ixgbe_vlan_filter_disable(adapter);
9a799d71 3610 } else {
746b9f02
PM		 3611 if (netdev->flags & IFF_ALLMULTI) {
3612 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3613 vmolr |= IXGBE_VMOLR_MPE;
3614 } else {
3615 /*
3616 * Write addresses to the MTA, if the attempt fails
25985edc 3617 * then we should just turn on promiscuous mode so
2850062a
AD		 3618 * that we can at least receive multicast traffic
3619 */
3620 hw->mac.ops.update_mc_addr_list(hw, netdev);
3621 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3622 }
5f6c0181 3623 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3624 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3625 }
3626
3627 /*
3628 * Write addresses to available RAR registers, if there is not
3629 * sufficient space to store all the addresses then enable
3630 * unicast promiscuous mode
3631 */
3632 count = ixgbe_write_uc_addr_list(netdev);
3633 if (count < 0) {
3634 fctrl |= IXGBE_FCTRL_UPE;
3635 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3636 }
3637
1d9c0bfd 3638 if (adapter->num_vfs)
1cdd1ec8 3639 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3640
3641 if (hw->mac.type != ixgbe_mac_82598EB) {
3642 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3643 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3644 IXGBE_VMOLR_ROPE);
1d9c0bfd 3645 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3646 }
3647
3f2d1c0f
BG		 3648 /* This is useful for sniffing bad packets. */
3649 if (adapter->netdev->features & NETIF_F_RXALL) {
3650 /* UPE and MPE will be handled by normal PROMISC logic
3651 * in e1000e_set_rx_mode */
3652 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3653 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3654 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3655
3656 fctrl &= ~(IXGBE_FCTRL_DPF);
3657 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3658 }
3659
2850062a 3660 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3661
3662 if (netdev->features & NETIF_F_HW_VLAN_RX)
3663 ixgbe_vlan_strip_enable(adapter);
3664 else
3665 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3666}
3667
021230d4
AV		 3668static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3669{
3670 int q_idx;
021230d4 3671
49c7ffbe
AD		 3672 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3673 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3674}
3675
3676static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3677{
3678 int q_idx;
021230d4 3679
49c7ffbe
AD		 3680 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3681 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3682}
3683
7a6b6f51 3684#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3685/**
2f90b865
AD		 3686 * ixgbe_configure_dcb - Configure DCB hardware
3687 * @adapter: ixgbe adapter struct
3688 *
3689 * This is called by the driver on open to configure the DCB hardware.
3690 * This is also called by the gennetlink interface when reconfiguring
3691 * the DCB state.
3692 */
3693static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3694{
3695 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3696 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3697
67ebd791
AD		 3698 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3699 if (hw->mac.type == ixgbe_mac_82598EB)
3700 netif_set_gso_max_size(adapter->netdev, 65536);
3701 return;
3702 }
3703
3704 if (hw->mac.type == ixgbe_mac_82598EB)
3705 netif_set_gso_max_size(adapter->netdev, 32768);
3706
971060b1 3707#ifdef IXGBE_FCOE
b120818e
JF		 3708 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3709 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3710#endif
b120818e
JF		 3711
3712 /* reconfigure the hardware */
3713 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3714 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3715 DCB_TX_CONFIG);
3716 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3717 DCB_RX_CONFIG);
3718 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3719 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3720 ixgbe_dcb_hw_ets(&adapter->hw,
3721 adapter->ixgbe_ieee_ets,
3722 max_frame);
3723 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3724 adapter->ixgbe_ieee_pfc->pfc_en,
3725 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3726 }
8187cd48
JF		 3727
3728 /* Enable RSS Hash per TC */
3729 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3730 u32 msb = 0;
3731 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3732
d411a936
AD		 3733 while (rss_i) {
3734 msb++;
3735 rss_i >>= 1;
3736 }
8187cd48 3737
4ae63730
AD		 3738 /* write msb to all 8 TCs in one write */
3739 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3740 }
2f90b865 3741}
9da712d2
JF		 3742#endif
3743
3744/* Additional bittime to account for IXGBE framing */
3745#define IXGBE_ETH_FRAMING 20
3746
49ce9c2c 3747/**
9da712d2
JF		 3748 * ixgbe_hpbthresh - calculate high water mark for flow control
3749 *
3750 * @adapter: board private structure to calculate for
49ce9c2c 3751 * @pb: packet buffer to calculate
9da712d2
JF		 3752 */
3753static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3754{
3755 struct ixgbe_hw *hw = &adapter->hw;
3756 struct net_device *dev = adapter->netdev;
3757 int link, tc, kb, marker;
3758 u32 dv_id, rx_pba;
3759
3760 /* Calculate max LAN frame size */
3761 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3762
3763#ifdef IXGBE_FCOE
3764 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3765 if ((dev->features & NETIF_F_FCOE_MTU) &&
3766 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3767 (pb == ixgbe_fcoe_get_tc(adapter)))
3768 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3769
3770#endif
9da712d2
JF		 3771 /* Calculate delay value for device */
3772 switch (hw->mac.type) {
3773 case ixgbe_mac_X540:
3774 dv_id = IXGBE_DV_X540(link, tc);
3775 break;
3776 default:
3777 dv_id = IXGBE_DV(link, tc);
3778 break;
3779 }
3780
3781 /* Loopback switch introduces additional latency */
3782 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3783 dv_id += IXGBE_B2BT(tc);
3784
3785 /* Delay value is calculated in bit times convert to KB */
3786 kb = IXGBE_BT2KB(dv_id);
3787 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3788
3789 marker = rx_pba - kb;
3790
3791 /* It is possible that the packet buffer is not large enough
3792 * to provide required headroom. In this case throw an error
3793 * to user and a do the best we can.
3794 */
3795 if (marker < 0) {
3796 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3797 "headroom to support flow control."
3798 "Decrease MTU or number of traffic classes\n", pb);
3799 marker = tc + 1;
3800 }
3801
3802 return marker;
3803}
3804
49ce9c2c 3805/**
9da712d2
JF		 3806 * ixgbe_lpbthresh - calculate low water mark for for flow control
3807 *
3808 * @adapter: board private structure to calculate for
49ce9c2c 3809 * @pb: packet buffer to calculate
9da712d2
JF		 3810 */
3811static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3812{
3813 struct ixgbe_hw *hw = &adapter->hw;
3814 struct net_device *dev = adapter->netdev;
3815 int tc;
3816 u32 dv_id;
3817
3818 /* Calculate max LAN frame size */
3819 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3820
3821 /* Calculate delay value for device */
3822 switch (hw->mac.type) {
3823 case ixgbe_mac_X540:
3824 dv_id = IXGBE_LOW_DV_X540(tc);
3825 break;
3826 default:
3827 dv_id = IXGBE_LOW_DV(tc);
3828 break;
3829 }
3830
3831 /* Delay value is calculated in bit times convert to KB */
3832 return IXGBE_BT2KB(dv_id);
3833}
3834
3835/*
3836 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3837 */
3838static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3839{
3840 struct ixgbe_hw *hw = &adapter->hw;
3841 int num_tc = netdev_get_num_tc(adapter->netdev);
3842 int i;
3843
3844 if (!num_tc)
3845 num_tc = 1;
3846
3847 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3848
3849 for (i = 0; i < num_tc; i++) {
3850 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3851
3852 /* Low water marks must not be larger than high water marks */
3853 if (hw->fc.low_water > hw->fc.high_water[i])
3854 hw->fc.low_water = 0;
3855 }
3856}
3857
80605c65
JF		 3858static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3859{
80605c65 3860 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3861 int hdrm;
3862 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3863
3864 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3865 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3866 hdrm = 32 << adapter->fdir_pballoc;
3867 else
3868 hdrm = 0;
80605c65 3869
f7e1027f 3870 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3871 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3872}
3873
e4911d57
AD		 3874static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3875{
3876 struct ixgbe_hw *hw = &adapter->hw;
3877 struct hlist_node *node, *node2;
3878 struct ixgbe_fdir_filter *filter;
3879
3880 spin_lock(&adapter->fdir_perfect_lock);
3881
3882 if (!hlist_empty(&adapter->fdir_filter_list))
3883 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3884
3885 hlist_for_each_entry_safe(filter, node, node2,
3886 &adapter->fdir_filter_list, fdir_node) {
3887 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3888 &filter->filter,
3889 filter->sw_idx,
3890 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3891 IXGBE_FDIR_DROP_QUEUE :
3892 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3893 }
3894
3895 spin_unlock(&adapter->fdir_perfect_lock);
3896}
3897
9a799d71
AK		 3898static void ixgbe_configure(struct ixgbe_adapter *adapter)
3899{
d2f5e7f3
AS		 3900 struct ixgbe_hw *hw = &adapter->hw;
3901
80605c65 3902 ixgbe_configure_pb(adapter);
7a6b6f51 3903#ifdef CONFIG_IXGBE_DCB
67ebd791 3904 ixgbe_configure_dcb(adapter);
2f90b865 3905#endif
b35d4d42
AD		 3906 /*
3907 * We must restore virtualization before VLANs or else
3908 * the VLVF registers will not be populated
3909 */
3910 ixgbe_configure_virtualization(adapter);
9a799d71 3911
4c1d7b4b 3912 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3913 ixgbe_restore_vlan(adapter);
3914
d2f5e7f3
AS		 3915 switch (hw->mac.type) {
3916 case ixgbe_mac_82599EB:
3917 case ixgbe_mac_X540:
3918 hw->mac.ops.disable_rx_buff(hw);
3919 break;
3920 default:
3921 break;
3922 }
3923
c4cf55e5 3924 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3925 ixgbe_init_fdir_signature_82599(&adapter->hw,
3926 adapter->fdir_pballoc);
e4911d57
AD		 3927 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3928 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3929 adapter->fdir_pballoc);
3930 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3931 }
4c1d7b4b 3932
d2f5e7f3
AS		 3933 switch (hw->mac.type) {
3934 case ixgbe_mac_82599EB:
3935 case ixgbe_mac_X540:
3936 hw->mac.ops.enable_rx_buff(hw);
3937 break;
3938 default:
3939 break;
3940 }
3941
7c8ae65a
AD		 3942#ifdef IXGBE_FCOE
3943 /* configure FCoE L2 filters, redirection table, and Rx control */
3944 ixgbe_configure_fcoe(adapter);
3945
3946#endif /* IXGBE_FCOE */
9a799d71
AK		 3947 ixgbe_configure_tx(adapter);
3948 ixgbe_configure_rx(adapter);
9a799d71
AK		 3949}
3950
e8e26350
PW		 3951static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3952{
3953 switch (hw->phy.type) {
3954 case ixgbe_phy_sfp_avago:
3955 case ixgbe_phy_sfp_ftl:
3956 case ixgbe_phy_sfp_intel:
3957 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3958 case ixgbe_phy_sfp_passive_tyco:
3959 case ixgbe_phy_sfp_passive_unknown:
3960 case ixgbe_phy_sfp_active_unknown:
3961 case ixgbe_phy_sfp_ftl_active:
e8e26350 3962 return true;
8917b447
AD		 3963 case ixgbe_phy_nl:
3964 if (hw->mac.type == ixgbe_mac_82598EB)
3965 return true;
e8e26350
PW		 3966 default:
3967 return false;
3968 }
3969}
3970
0ecc061d 3971/**
e8e26350
PW		 3972 * ixgbe_sfp_link_config - set up SFP+ link
3973 * @adapter: pointer to private adapter struct
3974 **/
3975static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3976{
7086400d 3977 /*
52f33af8 3978 * We are assuming the worst case scenario here, and that
7086400d
AD		 3979 * is that an SFP was inserted/removed after the reset
3980 * but before SFP detection was enabled. As such the best
3981 * solution is to just start searching as soon as we start
3982 */
3983 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3984 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3985
7086400d 3986 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3987}
3988
3989/**
3990 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3991 * @hw: pointer to private hardware struct
3992 *
3993 * Returns 0 on success, negative on failure
3994 **/
e8e26350 3995static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 3996{
3d292265
JH		 3997 u32 speed;
3998 bool autoneg, link_up = false;
0ecc061d
PWJ		 3999 u32 ret = IXGBE_ERR_LINK_SETUP;
4000
4001 if (hw->mac.ops.check_link)
3d292265 4002 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4003
4004 if (ret)
4005 goto link_cfg_out;
4006
3d292265
JH		 4007 speed = hw->phy.autoneg_advertised;
4008 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4009 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4010 &autoneg);
0ecc061d
PWJ		 4011 if (ret)
4012 goto link_cfg_out;
4013
8620a103 4014 if (hw->mac.ops.setup_link)
fd0326f2 4015 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4016link_cfg_out:
4017 return ret;
4018}
4019
a34bcfff 4020static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4021{
9a799d71 4022 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4023 u32 gpie = 0;
9a799d71 4024
9b471446 4025 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4026 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4027 IXGBE_GPIE_OCD;
4028 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4029 /*
4030 * use EIAM to auto-mask when MSI-X interrupt is asserted
4031 * this saves a register write for every interrupt
4032 */
4033 switch (hw->mac.type) {
4034 case ixgbe_mac_82598EB:
4035 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4036 break;
9b471446 4037 case ixgbe_mac_82599EB:
b93a2226
DS		 4038 case ixgbe_mac_X540:
4039 default:
9b471446
JB		 4040 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4041 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4042 break;
4043 }
4044 } else {
021230d4
AV		 4045 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4046 * specifically only auto mask tx and rx interrupts */
4047 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4048 }
9a799d71 4049
a34bcfff
AD		 4050 /* XXX: to interrupt immediately for EICS writes, enable this */
4051 /* gpie |= IXGBE_GPIE_EIMEN; */
4052
4053 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4054 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4055
4056 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4057 case IXGBE_82599_VMDQ_8Q_MASK:
4058 gpie |= IXGBE_GPIE_VTMODE_16;
4059 break;
4060 case IXGBE_82599_VMDQ_4Q_MASK:
4061 gpie |= IXGBE_GPIE_VTMODE_32;
4062 break;
4063 default:
4064 gpie |= IXGBE_GPIE_VTMODE_64;
4065 break;
4066 }
119fc60a
MC		 4067 }
4068
5fdd31f9 4069 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4070 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4071 switch (adapter->hw.mac.type) {
4072 case ixgbe_mac_82599EB:
4073 gpie |= IXGBE_SDP0_GPIEN;
4074 break;
4075 case ixgbe_mac_X540:
4076 gpie |= IXGBE_EIMS_TS;
4077 break;
4078 default:
4079 break;
4080 }
4081 }
5fdd31f9 4082
a34bcfff
AD		 4083 /* Enable fan failure interrupt */
4084 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4085 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4086
2698b208 4087 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4088 gpie |= IXGBE_SDP1_GPIEN;
4089 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4090 }
a34bcfff
AD		 4091
4092 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4093}
4094
c7ccde0f 4095static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4096{
4097 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4098 int err;
a34bcfff
AD		 4099 u32 ctrl_ext;
4100
4101 ixgbe_get_hw_control(adapter);
4102 ixgbe_setup_gpie(adapter);
e8e26350 4103
9a799d71
AK		 4104 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4105 ixgbe_configure_msix(adapter);
4106 else
4107 ixgbe_configure_msi_and_legacy(adapter);
4108
ec74a471
ET		 4109 /* enable the optics for 82599 SFP+ fiber */
4110 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4111 hw->mac.ops.enable_tx_laser(hw);
4112
9a799d71 4113 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4114 ixgbe_napi_enable_all(adapter);
4115
73c4b7cd
AD		 4116 if (ixgbe_is_sfp(hw)) {
4117 ixgbe_sfp_link_config(adapter);
4118 } else {
4119 err = ixgbe_non_sfp_link_config(hw);
4120 if (err)
4121 e_err(probe, "link_config FAILED %d\n", err);
4122 }
4123
021230d4
AV		 4124 /* clear any pending interrupts, may auto mask */
4125 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4126 ixgbe_irq_enable(adapter, true, true);
9a799d71 4127
bf069c97
DS		 4128 /*
4129 * If this adapter has a fan, check to see if we had a failure
4130 * before we enabled the interrupt.
4131 */
4132 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4133 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4134 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4135 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4136 }
4137
1da100bb 4138 /* enable transmits */
477de6ed 4139 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4140
9a799d71
AK		 4141 /* bring the link up in the watchdog, this could race with our first
4142 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4143 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4144 adapter->link_check_timeout = jiffies;
7086400d 4145 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4146
4147 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4148 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4149 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4150 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4151}
4152
d4f80882
AV		 4153void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4154{
4155 WARN_ON(in_interrupt());
7086400d
AD		 4156 /* put off any impending NetWatchDogTimeout */
4157 adapter->netdev->trans_start = jiffies;
4158
d4f80882 4159 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4160 usleep_range(1000, 2000);
d4f80882 4161 ixgbe_down(adapter);
5809a1ae
GR		 4162 /*
4163 * If SR-IOV enabled then wait a bit before bringing the adapter
4164 * back up to give the VFs time to respond to the reset. The
4165 * two second wait is based upon the watchdog timer cycle in
4166 * the VF driver.
4167 */
4168 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4169 msleep(2000);
d4f80882
AV		 4170 ixgbe_up(adapter);
4171 clear_bit(__IXGBE_RESETTING, &adapter->state);
4172}
4173
c7ccde0f 4174void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4175{
4176 /* hardware has been reset, we need to reload some things */
4177 ixgbe_configure(adapter);
4178
c7ccde0f 4179 ixgbe_up_complete(adapter);
9a799d71
AK		 4180}
4181
4182void ixgbe_reset(struct ixgbe_adapter *adapter)
4183{
c44ade9e 4184 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4185 int err;
4186
7086400d
AD		 4187 /* lock SFP init bit to prevent race conditions with the watchdog */
4188 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4189 usleep_range(1000, 2000);
4190
4191 /* clear all SFP and link config related flags while holding SFP_INIT */
4192 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4193 IXGBE_FLAG2_SFP_NEEDS_RESET);
4194 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4195
8ca783ab 4196 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4197 switch (err) {
4198 case 0:
4199 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4200 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4201 break;
4202 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4203 e_dev_err("master disable timed out\n");
da4dd0f7 4204 break;
794caeb2
PWJ		 4205 case IXGBE_ERR_EEPROM_VERSION:
4206 /* We are running on a pre-production device, log a warning */
849c4542 4207 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4208 "Please be aware there may be issues associated with "
849c4542
ET		 4209 "your hardware. If you are experiencing problems "
4210 "please contact your Intel or hardware "
4211 "representative who provided you with this "
4212 "hardware.\n");
794caeb2 4213 break;
da4dd0f7 4214 default:
849c4542 4215 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4216 }
9a799d71 4217
7086400d
AD		 4218 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4219
9a799d71 4220 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4221 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4222
4223 /* update SAN MAC vmdq pool selection */
4224 if (hw->mac.san_mac_rar_index)
4225 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4226
1a71ab24
JK		 4227 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4228 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4229}
4230
9a799d71
AK		 4231/**
4232 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4233 * @rx_ring: ring to free buffers from
4234 **/
b6ec895e 4235static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4236{
b6ec895e 4237 struct device *dev = rx_ring->dev;
9a799d71 4238 unsigned long size;
b6ec895e 4239 u16 i;
9a799d71 4240
84418e3b
AD		 4241 /* ring already cleared, nothing to do */
4242 if (!rx_ring->rx_buffer_info)
4243 return;
9a799d71 4244
84418e3b 4245 /* Free all the Rx ring sk_buffs */
9a799d71 4246 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4247 struct ixgbe_rx_buffer *rx_buffer;
4248
4249 rx_buffer = &rx_ring->rx_buffer_info[i];
4250 if (rx_buffer->skb) {
4251 struct sk_buff *skb = rx_buffer->skb;
4252 if (IXGBE_CB(skb)->page_released) {
4253 dma_unmap_page(dev,
4254 IXGBE_CB(skb)->dma,
4255 ixgbe_rx_bufsz(rx_ring),
4256 DMA_FROM_DEVICE);
4257 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4258 }
4259 dev_kfree_skb(skb);
9a799d71 4260 }
f800326d
AD		 4261 rx_buffer->skb = NULL;
4262 if (rx_buffer->dma)
4263 dma_unmap_page(dev, rx_buffer->dma,
4264 ixgbe_rx_pg_size(rx_ring),
4265 DMA_FROM_DEVICE);
4266 rx_buffer->dma = 0;
4267 if (rx_buffer->page)
dd411ec4
AD		 4268 __free_pages(rx_buffer->page,
4269 ixgbe_rx_pg_order(rx_ring));
f800326d 4270 rx_buffer->page = NULL;
9a799d71
AK		 4271 }
4272
4273 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4274 memset(rx_ring->rx_buffer_info, 0, size);
4275
4276 /* Zero out the descriptor ring */
4277 memset(rx_ring->desc, 0, rx_ring->size);
4278
f800326d 4279 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4280 rx_ring->next_to_clean = 0;
4281 rx_ring->next_to_use = 0;
9a799d71
AK		 4282}
4283
4284/**
4285 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4286 * @tx_ring: ring to be cleaned
4287 **/
b6ec895e 4288static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4289{
4290 struct ixgbe_tx_buffer *tx_buffer_info;
4291 unsigned long size;
b6ec895e 4292 u16 i;
9a799d71 4293
84418e3b
AD		 4294 /* ring already cleared, nothing to do */
4295 if (!tx_ring->tx_buffer_info)
4296 return;
9a799d71 4297
84418e3b 4298 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4299 for (i = 0; i < tx_ring->count; i++) {
4300 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4301 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4302 }
4303
dad8a3b3
JF		 4304 netdev_tx_reset_queue(txring_txq(tx_ring));
4305
9a799d71
AK		 4306 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4307 memset(tx_ring->tx_buffer_info, 0, size);
4308
4309 /* Zero out the descriptor ring */
4310 memset(tx_ring->desc, 0, tx_ring->size);
4311
4312 tx_ring->next_to_use = 0;
4313 tx_ring->next_to_clean = 0;
9a799d71
AK		 4314}
4315
4316/**
021230d4 4317 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4318 * @adapter: board private structure
4319 **/
021230d4 4320static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4321{
4322 int i;
4323
021230d4 4324 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4325 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4326}
4327
4328/**
021230d4 4329 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4330 * @adapter: board private structure
4331 **/
021230d4 4332static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4333{
4334 int i;
4335
021230d4 4336 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4337 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4338}
4339
e4911d57
AD		 4340static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4341{
4342 struct hlist_node *node, *node2;
4343 struct ixgbe_fdir_filter *filter;
4344
4345 spin_lock(&adapter->fdir_perfect_lock);
4346
4347 hlist_for_each_entry_safe(filter, node, node2,
4348 &adapter->fdir_filter_list, fdir_node) {
4349 hlist_del(&filter->fdir_node);
4350 kfree(filter);
4351 }
4352 adapter->fdir_filter_count = 0;
4353
4354 spin_unlock(&adapter->fdir_perfect_lock);
4355}
4356
9a799d71
AK		 4357void ixgbe_down(struct ixgbe_adapter *adapter)
4358{
4359 struct net_device *netdev = adapter->netdev;
7f821875 4360 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4361 u32 rxctrl;
bf29ee6c 4362 int i;
9a799d71
AK		 4363
4364 /* signal that we are down to the interrupt handler */
4365 set_bit(__IXGBE_DOWN, &adapter->state);
4366
4367 /* disable receives */
7f821875
JB		 4368 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4369 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4370
2d39d576
YZ		 4371 /* disable all enabled rx queues */
4372 for (i = 0; i < adapter->num_rx_queues; i++)
4373 /* this call also flushes the previous write */
4374 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4375
032b4325 4376 usleep_range(10000, 20000);
9a799d71 4377
7f821875
JB		 4378 netif_tx_stop_all_queues(netdev);
4379
7086400d 4380 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4381 netif_carrier_off(netdev);
4382 netif_tx_disable(netdev);
4383
4384 ixgbe_irq_disable(adapter);
4385
4386 ixgbe_napi_disable_all(adapter);
4387
d034acf1
AD		 4388 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4389 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4390 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4391
4392 del_timer_sync(&adapter->service_timer);
4393
34cecbbf 4394 if (adapter->num_vfs) {
8e34d1aa
AD		 4395 /* Clear EITR Select mapping */
4396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4397
4398 /* Mark all the VFs as inactive */
4399 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4400 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4401
34cecbbf
AD		 4402 /* ping all the active vfs to let them know we are going down */
4403 ixgbe_ping_all_vfs(adapter);
4404
4405 /* Disable all VFTE/VFRE TX/RX */
4406 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4407 }
4408
7f821875
JB		 4409 /* disable transmits in the hardware now that interrupts are off */
4410 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4411 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4412 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4413 }
34cecbbf
AD		 4414
4415 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4416 switch (hw->mac.type) {
4417 case ixgbe_mac_82599EB:
b93a2226 4418 case ixgbe_mac_X540:
88512539 4419 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4420 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4421 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4422 break;
4423 default:
4424 break;
4425 }
7f821875 4426
6f4a0e45
PL		 4427 if (!pci_channel_offline(adapter->pdev))
4428 ixgbe_reset(adapter);
c6ecf39a 4429
ec74a471
ET		 4430 /* power down the optics for 82599 SFP+ fiber */
4431 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4432 hw->mac.ops.disable_tx_laser(hw);
4433
9a799d71
AK		 4434 ixgbe_clean_all_tx_rings(adapter);
4435 ixgbe_clean_all_rx_rings(adapter);
4436
5dd2d332 4437#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4438 /* since we reset the hardware DCA settings were cleared */
e35ec126 4439 ixgbe_setup_dca(adapter);
96b0e0f6 4440#endif
9a799d71
AK		 4441}
4442
9a799d71
AK		 4443/**
4444 * ixgbe_tx_timeout - Respond to a Tx Hang
4445 * @netdev: network interface device structure
4446 **/
4447static void ixgbe_tx_timeout(struct net_device *netdev)
4448{
4449 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4450
4451 /* Do the reset outside of interrupt context */
c83c6cbd 4452 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4453}
4454
9a799d71
AK		 4455/**
4456 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4457 * @adapter: board private structure to initialize
4458 *
4459 * ixgbe_sw_init initializes the Adapter private data structure.
4460 * Fields are initialized based on PCI device information and
4461 * OS network device settings (MTU size).
4462 **/
9f9a12f8 4463static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4464{
4465 struct ixgbe_hw *hw = &adapter->hw;
4466 struct pci_dev *pdev = adapter->pdev;
021230d4 4467 unsigned int rss;
cb6d0f5e 4468 u32 fwsm;
7a6b6f51 4469#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4470 int j;
4471 struct tc_configuration *tc;
4472#endif
021230d4 4473
c44ade9e
JB		 4474 /* PCI config space info */
4475
4476 hw->vendor_id = pdev->vendor;
4477 hw->device_id = pdev->device;
4478 hw->revision_id = pdev->revision;
4479 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4480 hw->subsystem_device_id = pdev->subsystem_device;
4481
021230d4 4482 /* Set capability flags */
3ed69d7e 4483 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4484 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4485 switch (hw->mac.type) {
4486 case ixgbe_mac_82598EB:
bf069c97
DS		 4487 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4488 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4489 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4490 break;
b93a2226 4491 case ixgbe_mac_X540:
cb6d0f5e
JK		 4492 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4493 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4494 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4f51bf70 4495 case ixgbe_mac_82599EB:
49c7ffbe 4496 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4497 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4498 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4499 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4500 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4501 /* Flow Director hash filters enabled */
45b9f509 4502 adapter->atr_sample_rate = 20;
c087663e 4503 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4504 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4505 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4506#ifdef IXGBE_FCOE
0d551589
YZ		 4507 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4508 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4509#ifdef CONFIG_IXGBE_DCB
6ee16520 4510 /* Default traffic class to use for FCoE */
56075a98 4511 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4512#endif
eacd73f7 4513#endif /* IXGBE_FCOE */
bd508178
AD		 4514 break;
4515 default:
4516 break;
f8212f97 4517 }
2f90b865 4518
7c8ae65a
AD		 4519#ifdef IXGBE_FCOE
4520 /* FCoE support exists, always init the FCoE lock */
4521 spin_lock_init(&adapter->fcoe.lock);
4522
4523#endif
1fc5f038
AD		 4524 /* n-tuple support exists, always init our spinlock */
4525 spin_lock_init(&adapter->fdir_perfect_lock);
4526
7a6b6f51 4527#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4528 switch (hw->mac.type) {
4529 case ixgbe_mac_X540:
4530 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4531 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4532 break;
4533 default:
4534 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4535 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4536 break;
4537 }
4538
2f90b865
AD		 4539 /* Configure DCB traffic classes */
4540 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4541 tc = &adapter->dcb_cfg.tc_config[j];
4542 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4543 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4544 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4545 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4546 tc->dcb_pfc = pfc_disabled;
4547 }
4de2a022
JF		 4548
4549 /* Initialize default user to priority mapping, UPx->TC0 */
4550 tc = &adapter->dcb_cfg.tc_config[0];
4551 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4552 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4553
2f90b865
AD		 4554 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4555 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4556 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4557 adapter->dcb_set_bitmap = 0x00;
3032309b 4558 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4559 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4560 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4561
4562#endif
9a799d71
AK		 4563
4564 /* default flow control settings */
cd7664f6 4565 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4566 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4567 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4568 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4569 hw->fc.send_xon = true;
db2adc2d
JK		 4570 hw->fc.disable_fc_autoneg =
4571 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
9a799d71 4572
99d74487
AD		 4573#ifdef CONFIG_PCI_IOV
4574 /* assign number of SR-IOV VFs */
4575 if (hw->mac.type != ixgbe_mac_82598EB)
4576 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4577
4578#endif
30efa5a3 4579 /* enable itr by default in dynamic mode */
f7554a2b 4580 adapter->rx_itr_setting = 1;
f7554a2b 4581 adapter->tx_itr_setting = 1;
30efa5a3 4582
30efa5a3
JB		 4583 /* set default ring sizes */
4584 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4585 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4586
bd198058 4587 /* set default work limits */
59224555 4588 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4589
9a799d71 4590 /* initialize eeprom parameters */
c44ade9e 4591 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4592 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4593 return -EIO;
4594 }
4595
9a799d71
AK		 4596 set_bit(__IXGBE_DOWN, &adapter->state);
4597
4598 return 0;
4599}
4600
4601/**
4602 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4603 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4604 *
4605 * Return 0 on success, negative on failure
4606 **/
b6ec895e 4607int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4608{
b6ec895e 4609 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4610 int orig_node = dev_to_node(dev);
4611 int numa_node = -1;
9a799d71
AK		 4612 int size;
4613
3a581073 4614 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4615
4616 if (tx_ring->q_vector)
4617 numa_node = tx_ring->q_vector->numa_node;
4618
4619 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4620 if (!tx_ring->tx_buffer_info)
89bf67f1 4621 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4622 if (!tx_ring->tx_buffer_info)
4623 goto err;
9a799d71
AK		 4624
4625 /* round up to nearest 4K */
12207e49 4626 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4627 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4628
de88eeeb
AD		 4629 set_dev_node(dev, numa_node);
4630 tx_ring->desc = dma_alloc_coherent(dev,
4631 tx_ring->size,
4632 &tx_ring->dma,
4633 GFP_KERNEL);
4634 set_dev_node(dev, orig_node);
4635 if (!tx_ring->desc)
4636 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4637 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4638 if (!tx_ring->desc)
4639 goto err;
9a799d71 4640
3a581073
JB		 4641 tx_ring->next_to_use = 0;
4642 tx_ring->next_to_clean = 0;
9a799d71 4643 return 0;
e01c31a5
JB		 4644
4645err:
4646 vfree(tx_ring->tx_buffer_info);
4647 tx_ring->tx_buffer_info = NULL;
b6ec895e 4648 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4649 return -ENOMEM;
9a799d71
AK		 4650}
4651
69888674
AD		 4652/**
4653 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4654 * @adapter: board private structure
4655 *
4656 * If this function returns with an error, then it's possible one or
4657 * more of the rings is populated (while the rest are not). It is the
4658 * callers duty to clean those orphaned rings.
4659 *
4660 * Return 0 on success, negative on failure
4661 **/
4662static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4663{
4664 int i, err = 0;
4665
4666 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4667 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4668 if (!err)
4669 continue;
de3d5b94 4670
396e799c 4671 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4672 goto err_setup_tx;
69888674
AD		 4673 }
4674
de3d5b94
AD		 4675 return 0;
4676err_setup_tx:
4677 /* rewind the index freeing the rings as we go */
4678 while (i--)
4679 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4680 return err;
4681}
4682
9a799d71
AK		 4683/**
4684 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4685 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4686 *
4687 * Returns 0 on success, negative on failure
4688 **/
b6ec895e 4689int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4690{
b6ec895e 4691 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4692 int orig_node = dev_to_node(dev);
4693 int numa_node = -1;
021230d4 4694 int size;
9a799d71 4695
3a581073 4696 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4697
4698 if (rx_ring->q_vector)
4699 numa_node = rx_ring->q_vector->numa_node;
4700
4701 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4702 if (!rx_ring->rx_buffer_info)
89bf67f1 4703 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4704 if (!rx_ring->rx_buffer_info)
4705 goto err;
9a799d71 4706
9a799d71 4707 /* Round up to nearest 4K */
3a581073
JB		 4708 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4709 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4710
de88eeeb
AD		 4711 set_dev_node(dev, numa_node);
4712 rx_ring->desc = dma_alloc_coherent(dev,
4713 rx_ring->size,
4714 &rx_ring->dma,
4715 GFP_KERNEL);
4716 set_dev_node(dev, orig_node);
4717 if (!rx_ring->desc)
4718 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4719 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4720 if (!rx_ring->desc)
4721 goto err;
9a799d71 4722
3a581073
JB		 4723 rx_ring->next_to_clean = 0;
4724 rx_ring->next_to_use = 0;
9a799d71
AK		 4725
4726 return 0;
b6ec895e
AD		 4727err:
4728 vfree(rx_ring->rx_buffer_info);
4729 rx_ring->rx_buffer_info = NULL;
4730 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4731 return -ENOMEM;
9a799d71
AK		 4732}
4733
69888674
AD		 4734/**
4735 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4736 * @adapter: board private structure
4737 *
4738 * If this function returns with an error, then it's possible one or
4739 * more of the rings is populated (while the rest are not). It is the
4740 * callers duty to clean those orphaned rings.
4741 *
4742 * Return 0 on success, negative on failure
4743 **/
69888674
AD		 4744static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4745{
4746 int i, err = 0;
4747
4748 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4749 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4750 if (!err)
4751 continue;
de3d5b94 4752
396e799c 4753 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4754 goto err_setup_rx;
69888674
AD		 4755 }
4756
7c8ae65a
AD		 4757#ifdef IXGBE_FCOE
4758 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4759 if (!err)
4760#endif
4761 return 0;
de3d5b94
AD		 4762err_setup_rx:
4763 /* rewind the index freeing the rings as we go */
4764 while (i--)
4765 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4766 return err;
4767}
4768
9a799d71
AK		 4769/**
4770 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4771 * @tx_ring: Tx descriptor ring for a specific queue
4772 *
4773 * Free all transmit software resources
4774 **/
b6ec895e 4775void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4776{
b6ec895e 4777 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4778
4779 vfree(tx_ring->tx_buffer_info);
4780 tx_ring->tx_buffer_info = NULL;
4781
b6ec895e
AD		 4782 /* if not set, then don't free */
4783 if (!tx_ring->desc)
4784 return;
4785
4786 dma_free_coherent(tx_ring->dev, tx_ring->size,
4787 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4788
4789 tx_ring->desc = NULL;
4790}
4791
4792/**
4793 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4794 * @adapter: board private structure
4795 *
4796 * Free all transmit software resources
4797 **/
4798static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4799{
4800 int i;
4801
4802 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4803 if (adapter->tx_ring[i]->desc)
b6ec895e 4804 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4805}
4806
4807/**
b4617240 4808 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4809 * @rx_ring: ring to clean the resources from
4810 *
4811 * Free all receive software resources
4812 **/
b6ec895e 4813void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4814{
b6ec895e 4815 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4816
4817 vfree(rx_ring->rx_buffer_info);
4818 rx_ring->rx_buffer_info = NULL;
4819
b6ec895e
AD		 4820 /* if not set, then don't free */
4821 if (!rx_ring->desc)
4822 return;
4823
4824 dma_free_coherent(rx_ring->dev, rx_ring->size,
4825 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4826
4827 rx_ring->desc = NULL;
4828}
4829
4830/**
4831 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4832 * @adapter: board private structure
4833 *
4834 * Free all receive software resources
4835 **/
4836static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4837{
4838 int i;
4839
7c8ae65a
AD		 4840#ifdef IXGBE_FCOE
4841 ixgbe_free_fcoe_ddp_resources(adapter);
4842
4843#endif
9a799d71 4844 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4845 if (adapter->rx_ring[i]->desc)
b6ec895e 4846 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4847}
4848
9a799d71
AK		 4849/**
4850 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4851 * @netdev: network interface device structure
4852 * @new_mtu: new value for maximum frame size
4853 *
4854 * Returns 0 on success, negative on failure
4855 **/
4856static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4857{
4858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4859 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4860
42c783c5 4861 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4862 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4863 return -EINVAL;
4864
4865 /*
872844dd
AD		 4866 * For 82599EB we cannot allow legacy VFs to enable their receive
4867 * paths when MTU greater than 1500 is configured. So display a
4868 * warning that legacy VFs will be disabled.
655309e9
AD		 4869 */
4870 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4871 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4872 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
872844dd 4873 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 4874
396e799c 4875 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4876
021230d4 4877 /* must set new MTU before calling down or up */
9a799d71
AK		 4878 netdev->mtu = new_mtu;
4879
d4f80882
AV		 4880 if (netif_running(netdev))
4881 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4882
4883 return 0;
4884}
4885
4886/**
4887 * ixgbe_open - Called when a network interface is made active
4888 * @netdev: network interface device structure
4889 *
4890 * Returns 0 on success, negative value on failure
4891 *
4892 * The open entry point is called when a network interface is made
4893 * active by the system (IFF_UP). At this point all resources needed
4894 * for transmit and receive operations are allocated, the interrupt
4895 * handler is registered with the OS, the watchdog timer is started,
4896 * and the stack is notified that the interface is ready.
4897 **/
4898static int ixgbe_open(struct net_device *netdev)
4899{
4900 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4901 int err;
4bebfaa5
AK		 4902
4903 /* disallow open during test */
4904 if (test_bit(__IXGBE_TESTING, &adapter->state))
4905 return -EBUSY;
9a799d71 4906
54386467
JB		 4907 netif_carrier_off(netdev);
4908
9a799d71
AK		 4909 /* allocate transmit descriptors */
4910 err = ixgbe_setup_all_tx_resources(adapter);
4911 if (err)
4912 goto err_setup_tx;
4913
9a799d71
AK		 4914 /* allocate receive descriptors */
4915 err = ixgbe_setup_all_rx_resources(adapter);
4916 if (err)
4917 goto err_setup_rx;
4918
4919 ixgbe_configure(adapter);
4920
021230d4 4921 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4922 if (err)
4923 goto err_req_irq;
4924
ac802f5d
AD		 4925 /* Notify the stack of the actual queue counts. */
4926 err = netif_set_real_num_tx_queues(netdev,
4927 adapter->num_rx_pools > 1 ? 1 :
4928 adapter->num_tx_queues);
4929 if (err)
4930 goto err_set_queues;
4931
4932
4933 err = netif_set_real_num_rx_queues(netdev,
4934 adapter->num_rx_pools > 1 ? 1 :
4935 adapter->num_rx_queues);
4936 if (err)
4937 goto err_set_queues;
4938
1a71ab24 4939 ixgbe_ptp_init(adapter);
1a71ab24 4940
c7ccde0f 4941 ixgbe_up_complete(adapter);
9a799d71
AK		 4942
4943 return 0;
4944
ac802f5d
AD		 4945err_set_queues:
4946 ixgbe_free_irq(adapter);
9a799d71 4947err_req_irq:
a20a1199 4948 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4949err_setup_rx:
a20a1199 4950 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4951err_setup_tx:
9a799d71
AK		 4952 ixgbe_reset(adapter);
4953
4954 return err;
4955}
4956
4957/**
4958 * ixgbe_close - Disables a network interface
4959 * @netdev: network interface device structure
4960 *
4961 * Returns 0, this is not allowed to fail
4962 *
4963 * The close entry point is called when an interface is de-activated
4964 * by the OS. The hardware is still under the drivers control, but
4965 * needs to be disabled. A global MAC reset is issued to stop the
4966 * hardware, and all transmit and receive resources are freed.
4967 **/
4968static int ixgbe_close(struct net_device *netdev)
4969{
4970 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 4971
1a71ab24 4972 ixgbe_ptp_stop(adapter);
1a71ab24 4973
9a799d71
AK		 4974 ixgbe_down(adapter);
4975 ixgbe_free_irq(adapter);
4976
e4911d57
AD		 4977 ixgbe_fdir_filter_exit(adapter);
4978
9a799d71
AK		 4979 ixgbe_free_all_tx_resources(adapter);
4980 ixgbe_free_all_rx_resources(adapter);
4981
5eba3699 4982 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4983
4984 return 0;
4985}
4986
b3c8b4ba
AD		 4987#ifdef CONFIG_PM
4988static int ixgbe_resume(struct pci_dev *pdev)
4989{
c60fbb00
AD		 4990 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4991 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4992 u32 err;
4993
4994 pci_set_power_state(pdev, PCI_D0);
4995 pci_restore_state(pdev);
656ab817
DS		 4996 /*
4997 * pci_restore_state clears dev->state_saved so call
4998 * pci_save_state to restore it.
4999 */
5000 pci_save_state(pdev);
9ce77666 5001
5002 err = pci_enable_device_mem(pdev);
b3c8b4ba 5003 if (err) {
849c4542 5004 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5005 return err;
5006 }
5007 pci_set_master(pdev);
5008
dd4d8ca6 5009 pci_wake_from_d3(pdev, false);
b3c8b4ba 5010
b3c8b4ba
AD		 5011 ixgbe_reset(adapter);
5012
495dce12
WJP		 5013 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5014
ac802f5d
AD		 5015 rtnl_lock();
5016 err = ixgbe_init_interrupt_scheme(adapter);
5017 if (!err && netif_running(netdev))
c60fbb00 5018 err = ixgbe_open(netdev);
ac802f5d
AD		 5019
5020 rtnl_unlock();
5021
5022 if (err)
5023 return err;
b3c8b4ba
AD		 5024
5025 netif_device_attach(netdev);
5026
5027 return 0;
5028}
b3c8b4ba 5029#endif /* CONFIG_PM */
9d8d05ae
RW		 5030
5031static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5032{
c60fbb00
AD		 5033 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5034 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5035 struct ixgbe_hw *hw = &adapter->hw;
5036 u32 ctrl, fctrl;
5037 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5038#ifdef CONFIG_PM
5039 int retval = 0;
5040#endif
5041
5042 netif_device_detach(netdev);
5043
5044 if (netif_running(netdev)) {
ab6039a7 5045 rtnl_lock();
b3c8b4ba
AD		 5046 ixgbe_down(adapter);
5047 ixgbe_free_irq(adapter);
5048 ixgbe_free_all_tx_resources(adapter);
5049 ixgbe_free_all_rx_resources(adapter);
ab6039a7 5050 rtnl_unlock();
b3c8b4ba 5051 }
b3c8b4ba 5052
5f5ae6fc
AD		 5053 ixgbe_clear_interrupt_scheme(adapter);
5054
b3c8b4ba
AD		 5055#ifdef CONFIG_PM
5056 retval = pci_save_state(pdev);
5057 if (retval)
5058 return retval;
4df10466 5059
b3c8b4ba 5060#endif
e8e26350
PW		 5061 if (wufc) {
5062 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5063
ec74a471
ET		 5064 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5065 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5066 hw->mac.ops.enable_tx_laser(hw);
5067
e8e26350
PW		 5068 /* turn on all-multi mode if wake on multicast is enabled */
5069 if (wufc & IXGBE_WUFC_MC) {
5070 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5071 fctrl |= IXGBE_FCTRL_MPE;
5072 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5073 }
5074
5075 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5076 ctrl |= IXGBE_CTRL_GIO_DIS;
5077 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5078
5079 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5080 } else {
5081 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5082 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5083 }
5084
bd508178
AD		 5085 switch (hw->mac.type) {
5086 case ixgbe_mac_82598EB:
dd4d8ca6 5087 pci_wake_from_d3(pdev, false);
bd508178
AD		 5088 break;
5089 case ixgbe_mac_82599EB:
b93a2226 5090 case ixgbe_mac_X540:
bd508178
AD		 5091 pci_wake_from_d3(pdev, !!wufc);
5092 break;
5093 default:
5094 break;
5095 }
b3c8b4ba 5096
9d8d05ae
RW		 5097 *enable_wake = !!wufc;
5098
b3c8b4ba
AD		 5099 ixgbe_release_hw_control(adapter);
5100
5101 pci_disable_device(pdev);
5102
9d8d05ae
RW		 5103 return 0;
5104}
5105
5106#ifdef CONFIG_PM
5107static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5108{
5109 int retval;
5110 bool wake;
5111
5112 retval = __ixgbe_shutdown(pdev, &wake);
5113 if (retval)
5114 return retval;
5115
5116 if (wake) {
5117 pci_prepare_to_sleep(pdev);
5118 } else {
5119 pci_wake_from_d3(pdev, false);
5120 pci_set_power_state(pdev, PCI_D3hot);
5121 }
b3c8b4ba
AD		 5122
5123 return 0;
5124}
9d8d05ae 5125#endif /* CONFIG_PM */
b3c8b4ba
AD		 5126
5127static void ixgbe_shutdown(struct pci_dev *pdev)
5128{
9d8d05ae
RW		 5129 bool wake;
5130
5131 __ixgbe_shutdown(pdev, &wake);
5132
5133 if (system_state == SYSTEM_POWER_OFF) {
5134 pci_wake_from_d3(pdev, wake);
5135 pci_set_power_state(pdev, PCI_D3hot);
5136 }
b3c8b4ba
AD		 5137}
5138
9a799d71
AK		 5139/**
5140 * ixgbe_update_stats - Update the board statistics counters.
5141 * @adapter: board private structure
5142 **/
5143void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5144{
2d86f139 5145 struct net_device *netdev = adapter->netdev;
9a799d71 5146 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5147 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5148 u64 total_mpc = 0;
5149 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5150 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5151 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5152 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5153
d08935c2
DS		 5154 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5155 test_bit(__IXGBE_RESETTING, &adapter->state))
5156 return;
5157
94b982b2 5158 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5159 u64 rsc_count = 0;
94b982b2 5160 u64 rsc_flush = 0;
94b982b2 5161 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5162 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5163 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5164 }
5165 adapter->rsc_total_count = rsc_count;
5166 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5167 }
5168
5b7da515
AD		 5169 for (i = 0; i < adapter->num_rx_queues; i++) {
5170 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5171 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5172 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5173 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5174 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5175 bytes += rx_ring->stats.bytes;
5176 packets += rx_ring->stats.packets;
5177 }
5178 adapter->non_eop_descs = non_eop_descs;
5179 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5180 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5181 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5182 netdev->stats.rx_bytes = bytes;
5183 netdev->stats.rx_packets = packets;
5184
5185 bytes = 0;
5186 packets = 0;
7ca3bc58 5187 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5188 for (i = 0; i < adapter->num_tx_queues; i++) {
5189 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5190 restart_queue += tx_ring->tx_stats.restart_queue;
5191 tx_busy += tx_ring->tx_stats.tx_busy;
5192 bytes += tx_ring->stats.bytes;
5193 packets += tx_ring->stats.packets;
5194 }
eb985f09 5195 adapter->restart_queue = restart_queue;
5b7da515
AD		 5196 adapter->tx_busy = tx_busy;
5197 netdev->stats.tx_bytes = bytes;
5198 netdev->stats.tx_packets = packets;
7ca3bc58 5199
7ca647bd 5200 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5201
5202 /* 8 register reads */
6f11eef7
AV		 5203 for (i = 0; i < 8; i++) {
5204 /* for packet buffers not used, the register should read 0 */
5205 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5206 missed_rx += mpc;
7ca647bd
JP		 5207 hwstats->mpc[i] += mpc;
5208 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5209 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5210 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5211 switch (hw->mac.type) {
5212 case ixgbe_mac_82598EB:
1a70db4b
ET		 5213 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5214 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5215 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5216 hwstats->pxonrxc[i] +=
5217 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5218 break;
5219 case ixgbe_mac_82599EB:
b93a2226 5220 case ixgbe_mac_X540:
bd508178
AD		 5221 hwstats->pxonrxc[i] +=
5222 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5223 break;
5224 default:
5225 break;
e8e26350 5226 }
6f11eef7 5227 }
1a70db4b
ET		 5228
5229 /*16 register reads */
5230 for (i = 0; i < 16; i++) {
5231 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5232 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5233 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5234 (hw->mac.type == ixgbe_mac_X540)) {
5235 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5236 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5237 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5238 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5239 }
5240 }
5241
7ca647bd 5242 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5243 /* work around hardware counting issue */
7ca647bd 5244 hwstats->gprc -= missed_rx;
6f11eef7 5245
c84d324c
JF		 5246 ixgbe_update_xoff_received(adapter);
5247
6f11eef7 5248 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5249 switch (hw->mac.type) {
5250 case ixgbe_mac_82598EB:
5251 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5252 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5253 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5254 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5255 break;
b93a2226 5256 case ixgbe_mac_X540:
58f6bcf9
ET		 5257 /* OS2BMC stats are X540 only*/
5258 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5259 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5260 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5261 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5262 case ixgbe_mac_82599EB:
a4d4f629
AD		 5263 for (i = 0; i < 16; i++)
5264 adapter->hw_rx_no_dma_resources +=
5265 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5266 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5267 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5268 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5269 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5270 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5271 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5272 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5273 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5274 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5275#ifdef IXGBE_FCOE
7ca647bd
JP		 5276 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5277 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5278 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5279 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5280 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5281 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5282 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5283 if (adapter->fcoe.ddp_pool) {
5284 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5285 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5286 unsigned int cpu;
5287 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5288 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5289 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5290 noddp += ddp_pool->noddp;
5291 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5292 }
5a1ee270
AD		 5293 hwstats->fcoe_noddp = noddp;
5294 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5295 }
6d45522c 5296#endif /* IXGBE_FCOE */
bd508178
AD		 5297 break;
5298 default:
5299 break;
e8e26350 5300 }
9a799d71 5301 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5302 hwstats->bprc += bprc;
5303 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5304 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5305 hwstats->mprc -= bprc;
5306 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5307 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5308 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5309 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5310 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5311 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5312 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5313 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5314 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5315 hwstats->lxontxc += lxon;
6f11eef7 5316 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5317 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5318 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5319 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5320 /*
5321 * 82598 errata - tx of flow control packets is included in tx counters
5322 */
5323 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5324 hwstats->gptc -= xon_off_tot;
5325 hwstats->mptc -= xon_off_tot;
5326 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5327 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5328 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5329 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5330 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5331 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5332 hwstats->ptc64 -= xon_off_tot;
5333 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5334 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5335 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5336 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5337 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5338 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5339
5340 /* Fill out the OS statistics structure */
7ca647bd 5341 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5342
5343 /* Rx Errors */
7ca647bd 5344 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5345 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5346 netdev->stats.rx_length_errors = hwstats->rlec;
5347 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5348 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5349}
5350
5351/**
d034acf1 5352 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5353 * @adapter: pointer to the device adapter structure
9a799d71 5354 **/
d034acf1 5355static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5356{
cf8280ee 5357 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5358 int i;
cf8280ee 5359
d034acf1
AD		 5360 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5361 return;
5362
5363 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5364
d034acf1 5365 /* if interface is down do nothing */
fe49f04a 5366 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5367 return;
5368
5369 /* do nothing if we are not using signature filters */
5370 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5371 return;
5372
5373 adapter->fdir_overflow++;
5374
93c52dd0
AD		 5375 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5376 for (i = 0; i < adapter->num_tx_queues; i++)
5377 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5378 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5379 /* re-enable flow director interrupts */
5380 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5381 } else {
5382 e_err(probe, "failed to finish FDIR re-initialization, "
5383 "ignored adding FDIR ATR filters\n");
5384 }
93c52dd0
AD		 5385}
5386
5387/**
5388 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5389 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5390 *
5391 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5392 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5393 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5394 * determine if a hang has occurred.
93c52dd0
AD		 5395 */
5396static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5397{
cf8280ee 5398 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5399 u64 eics = 0;
5400 int i;
cf8280ee 5401
93c52dd0
AD		 5402 /* If we're down or resetting, just bail */
5403 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5404 test_bit(__IXGBE_RESETTING, &adapter->state))
5405 return;
22d5a71b 5406
93c52dd0
AD		 5407 /* Force detection of hung controller */
5408 if (netif_carrier_ok(adapter->netdev)) {
5409 for (i = 0; i < adapter->num_tx_queues; i++)
5410 set_check_for_tx_hang(adapter->tx_ring[i]);
5411 }
22d5a71b 5412
fe49f04a
AD		 5413 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5414 /*
5415 * for legacy and MSI interrupts don't set any bits
5416 * that are enabled for EIAM, because this operation
5417 * would set *both* EIMS and EICS for any bit in EIAM
5418 */
5419 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5420 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5421 } else {
5422 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5423 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5424 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5425 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5426 eics |= ((u64)1 << i);
5427 }
cf8280ee 5428 }
9a799d71 5429
93c52dd0 5430 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5431 ixgbe_irq_rearm_queues(adapter, eics);
5432
cf8280ee
JB		 5433}
5434
e8e26350 5435/**
93c52dd0 5436 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5437 * @adapter: pointer to the device adapter structure
5438 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5439 **/
93c52dd0 5440static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5441{
e8e26350 5442 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5443 u32 link_speed = adapter->link_speed;
5444 bool link_up = adapter->link_up;
041441d0 5445 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5446
93c52dd0
AD		 5447 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5448 return;
5449
5450 if (hw->mac.ops.check_link) {
5451 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5452 } else {
93c52dd0
AD		 5453 /* always assume link is up, if no check link function */
5454 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5455 link_up = true;
c4cf55e5 5456 }
041441d0
AD		 5457
5458 if (adapter->ixgbe_ieee_pfc)
5459 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5460
3ebe8fde 5461 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5462 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5463 ixgbe_set_rx_drop_en(adapter);
5464 }
93c52dd0
AD		 5465
5466 if (link_up ||
5467 time_after(jiffies, (adapter->link_check_timeout +
5468 IXGBE_TRY_LINK_TIMEOUT))) {
5469 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5470 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5471 IXGBE_WRITE_FLUSH(hw);
5472 }
5473
5474 adapter->link_up = link_up;
5475 adapter->link_speed = link_speed;
e8e26350
PW		 5476}
5477
107d3018
AD		 5478static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5479{
5480#ifdef CONFIG_IXGBE_DCB
5481 struct net_device *netdev = adapter->netdev;
5482 struct dcb_app app = {
5483 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5484 .protocol = 0,
5485 };
5486 u8 up = 0;
5487
5488 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5489 up = dcb_ieee_getapp_mask(netdev, &app);
5490
5491 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5492#endif
5493}
5494
e8e26350 5495/**
93c52dd0
AD		 5496 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5497 * print link up message
49ce9c2c 5498 * @adapter: pointer to the device adapter structure
e8e26350 5499 **/
93c52dd0 5500static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5501{
93c52dd0 5502 struct net_device *netdev = adapter->netdev;
e8e26350 5503 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5504 u32 link_speed = adapter->link_speed;
5505 bool flow_rx, flow_tx;
e8e26350 5506
93c52dd0
AD		 5507 /* only continue if link was previously down */
5508 if (netif_carrier_ok(netdev))
a985b6c3 5509 return;
63d6e1d8 5510
93c52dd0 5511 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5512
93c52dd0
AD		 5513 switch (hw->mac.type) {
5514 case ixgbe_mac_82598EB: {
5515 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5516 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5517 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5518 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5519 }
5520 break;
5521 case ixgbe_mac_X540:
5522 case ixgbe_mac_82599EB: {
5523 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5524 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5525 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5526 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5527 }
5528 break;
5529 default:
5530 flow_tx = false;
5531 flow_rx = false;
5532 break;
e8e26350 5533 }
3a6a4eda 5534
6cb562d6
JK		 5535 adapter->last_rx_ptp_check = jiffies;
5536
1a71ab24
JK		 5537 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5538 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5539
93c52dd0
AD		 5540 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5541 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5542 "10 Gbps" :
5543 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5544 "1 Gbps" :
5545 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5546 "100 Mbps" :
5547 "unknown speed"))),
5548 ((flow_rx && flow_tx) ? "RX/TX" :
5549 (flow_rx ? "RX" :
5550 (flow_tx ? "TX" : "None"))));
e8e26350 5551
93c52dd0 5552 netif_carrier_on(netdev);
93c52dd0 5553 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5554
107d3018
AD		 5555 /* update the default user priority for VFs */
5556 ixgbe_update_default_up(adapter);
5557
befa2af7
AD		 5558 /* ping all the active vfs to let them know link has changed */
5559 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5560}
5561
c4cf55e5 5562/**
93c52dd0
AD		 5563 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5564 * print link down message
49ce9c2c 5565 * @adapter: pointer to the adapter structure
c4cf55e5 5566 **/
581330ba 5567static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5568{
cf8280ee 5569 struct net_device *netdev = adapter->netdev;
c4cf55e5 5570 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5571
93c52dd0
AD		 5572 adapter->link_up = false;
5573 adapter->link_speed = 0;
cf8280ee 5574
93c52dd0
AD		 5575 /* only continue if link was up previously */
5576 if (!netif_carrier_ok(netdev))
5577 return;
264857b8 5578
93c52dd0
AD		 5579 /* poll for SFP+ cable when link is down */
5580 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5581 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5582
1a71ab24
JK		 5583 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5584 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5585
93c52dd0
AD		 5586 e_info(drv, "NIC Link is Down\n");
5587 netif_carrier_off(netdev);
befa2af7
AD		 5588
5589 /* ping all the active vfs to let them know link has changed */
5590 ixgbe_ping_all_vfs(adapter);
93c52dd0 5591}
e8e26350 5592
93c52dd0
AD		 5593/**
5594 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5595 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5596 **/
5597static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5598{
c4cf55e5 5599 int i;
93c52dd0 5600 int some_tx_pending = 0;
c4cf55e5 5601
93c52dd0 5602 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5603 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5604 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5605 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5606 some_tx_pending = 1;
5607 break;
5608 }
5609 }
5610
5611 if (some_tx_pending) {
5612 /* We've lost link, so the controller stops DMA,
5613 * but we've got queued Tx work that's never going
5614 * to get done, so reset controller to flush Tx.
5615 * (Do the reset outside of interrupt context).
5616 */
12ff3f3b 5617 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 5618 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5619 }
c4cf55e5 5620 }
c4cf55e5
PWJ		 5621}
5622
a985b6c3
GR		 5623static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5624{
5625 u32 ssvpc;
5626
0584d999
GR		 5627 /* Do not perform spoof check for 82598 or if not in IOV mode */
5628 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5629 adapter->num_vfs == 0)
a985b6c3
GR		 5630 return;
5631
5632 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5633
5634 /*
5635 * ssvpc register is cleared on read, if zero then no
5636 * spoofed packets in the last interval.
5637 */
5638 if (!ssvpc)
5639 return;
5640
d6ea0754 5641 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5642}
5643
93c52dd0
AD		 5644/**
5645 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5646 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5647 **/
5648static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5649{
5650 /* if interface is down do nothing */
7edebf9a
ET		 5651 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5652 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5653 return;
5654
5655 ixgbe_watchdog_update_link(adapter);
5656
5657 if (adapter->link_up)
5658 ixgbe_watchdog_link_is_up(adapter);
5659 else
5660 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5661
a985b6c3 5662 ixgbe_spoof_check(adapter);
9a799d71 5663 ixgbe_update_stats(adapter);
93c52dd0
AD		 5664
5665 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5666}
10eec955 5667
cf8280ee 5668/**
7086400d 5669 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5670 * @adapter: the ixgbe adapter structure
cf8280ee 5671 **/
7086400d 5672static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5673{
cf8280ee 5674 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5675 s32 err;
cf8280ee 5676
7086400d
AD		 5677 /* not searching for SFP so there is nothing to do here */
5678 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5679 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5680 return;
10eec955 5681
7086400d
AD		 5682 /* someone else is in init, wait until next service event */
5683 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5684 return;
cf8280ee 5685
7086400d
AD		 5686 err = hw->phy.ops.identify_sfp(hw);
5687 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5688 goto sfp_out;
264857b8 5689
7086400d
AD		 5690 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5691 /* If no cable is present, then we need to reset
5692 * the next time we find a good cable. */
5693 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5694 }
9a799d71 5695
7086400d
AD		 5696 /* exit on error */
5697 if (err)
5698 goto sfp_out;
e8e26350 5699
7086400d
AD		 5700 /* exit if reset not needed */
5701 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5702 goto sfp_out;
9a799d71 5703
7086400d 5704 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5705
7086400d
AD		 5706 /*
5707 * A module may be identified correctly, but the EEPROM may not have
5708 * support for that module. setup_sfp() will fail in that case, so
5709 * we should not allow that module to load.
5710 */
5711 if (hw->mac.type == ixgbe_mac_82598EB)
5712 err = hw->phy.ops.reset(hw);
5713 else
5714 err = hw->mac.ops.setup_sfp(hw);
5715
5716 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5717 goto sfp_out;
5718
5719 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5720 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5721
5722sfp_out:
5723 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5724
5725 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5726 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5727 e_dev_err("failed to initialize because an unsupported "
5728 "SFP+ module type was detected.\n");
5729 e_dev_err("Reload the driver after installing a "
5730 "supported module.\n");
5731 unregister_netdev(adapter->netdev);
bc59fcda 5732 }
7086400d 5733}
bc59fcda 5734
7086400d
AD		 5735/**
5736 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5737 * @adapter: the ixgbe adapter structure
7086400d
AD		 5738 **/
5739static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5740{
5741 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 5742 u32 speed;
5743 bool autoneg = false;
7086400d
AD		 5744
5745 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5746 return;
5747
5748 /* someone else is in init, wait until next service event */
5749 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5750 return;
5751
5752 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5753
3d292265
JH		 5754 speed = hw->phy.autoneg_advertised;
5755 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5756 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
7086400d 5757 if (hw->mac.ops.setup_link)
fd0326f2 5758 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 5759
5760 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5761 adapter->link_check_timeout = jiffies;
5762 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5763}
5764
83c61fa9
GR		 5765#ifdef CONFIG_PCI_IOV
5766static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5767{
5768 int vf;
5769 struct ixgbe_hw *hw = &adapter->hw;
5770 struct net_device *netdev = adapter->netdev;
5771 u32 gpc;
5772 u32 ciaa, ciad;
5773
5774 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5775 if (gpc) /* If incrementing then no need for the check below */
5776 return;
5777 /*
5778 * Check to see if a bad DMA write target from an errant or
5779 * malicious VF has caused a PCIe error. If so then we can
5780 * issue a VFLR to the offending VF(s) and then resume without
5781 * requesting a full slot reset.
5782 */
5783
5784 for (vf = 0; vf < adapter->num_vfs; vf++) {
5785 ciaa = (vf << 16) | 0x80000000;
5786 /* 32 bit read so align, we really want status at offset 6 */
5787 ciaa |= PCI_COMMAND;
5788 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5789 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5790 ciaa &= 0x7FFFFFFF;
5791 /* disable debug mode asap after reading data */
5792 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5793 /* Get the upper 16 bits which will be the PCI status reg */
5794 ciad >>= 16;
5795 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5796 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5797 /* Issue VFLR */
5798 ciaa = (vf << 16) | 0x80000000;
5799 ciaa |= 0xA8;
5800 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5801 ciad = 0x00008000; /* VFLR */
5802 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5803 ciaa &= 0x7FFFFFFF;
5804 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5805 }
5806 }
5807}
5808
5809#endif
7086400d
AD		 5810/**
5811 * ixgbe_service_timer - Timer Call-back
5812 * @data: pointer to adapter cast into an unsigned long
5813 **/
5814static void ixgbe_service_timer(unsigned long data)
5815{
5816 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5817 unsigned long next_event_offset;
83c61fa9 5818 bool ready = true;
7086400d 5819
6bb78cfb
AD		 5820 /* poll faster when waiting for link */
5821 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5822 next_event_offset = HZ / 10;
5823 else
5824 next_event_offset = HZ * 2;
83c61fa9 5825
6bb78cfb 5826#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5827 /*
5828 * don't bother with SR-IOV VF DMA hang check if there are
5829 * no VFs or the link is down
5830 */
5831 if (!adapter->num_vfs ||
6bb78cfb 5832 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5833 goto normal_timer_service;
83c61fa9
GR		 5834
5835 /* If we have VFs allocated then we must check for DMA hangs */
5836 ixgbe_check_for_bad_vf(adapter);
5837 next_event_offset = HZ / 50;
5838 adapter->timer_event_accumulator++;
5839
6bb78cfb 5840 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5841 adapter->timer_event_accumulator = 0;
7086400d 5842 else
6bb78cfb 5843 ready = false;
7086400d 5844
6bb78cfb 5845normal_timer_service:
83c61fa9 5846#endif
7086400d
AD		 5847 /* Reset the timer */
5848 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5849
83c61fa9
GR		 5850 if (ready)
5851 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5852}
5853
c83c6cbd
AD		 5854static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5855{
5856 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5857 return;
5858
5859 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5860
5861 /* If we're already down or resetting, just bail */
5862 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5863 test_bit(__IXGBE_RESETTING, &adapter->state))
5864 return;
5865
5866 ixgbe_dump(adapter);
5867 netdev_err(adapter->netdev, "Reset adapter\n");
5868 adapter->tx_timeout_count++;
5869
5870 ixgbe_reinit_locked(adapter);
5871}
5872
7086400d
AD		 5873/**
5874 * ixgbe_service_task - manages and runs subtasks
5875 * @work: pointer to work_struct containing our data
5876 **/
5877static void ixgbe_service_task(struct work_struct *work)
5878{
5879 struct ixgbe_adapter *adapter = container_of(work,
5880 struct ixgbe_adapter,
5881 service_task);
c83c6cbd 5882 ixgbe_reset_subtask(adapter);
7086400d
AD		 5883 ixgbe_sfp_detection_subtask(adapter);
5884 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5885 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5886 ixgbe_watchdog_subtask(adapter);
d034acf1 5887 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5888 ixgbe_check_hang_subtask(adapter);
891dc082
JK		 5889
5890 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5891 ixgbe_ptp_overflow_check(adapter);
5892 ixgbe_ptp_rx_hang(adapter);
5893 }
7086400d
AD		 5894
5895 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5896}
5897
fd0db0ed
AD		 5898static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5899 struct ixgbe_tx_buffer *first,
244e27ad 5900 u8 *hdr_len)
897ab156 5901{
fd0db0ed 5902 struct sk_buff *skb = first->skb;
897ab156
AD		 5903 u32 vlan_macip_lens, type_tucmd;
5904 u32 mss_l4len_idx, l4len;
9a799d71 5905
8f4fbb9b
AD		 5906 if (skb->ip_summed != CHECKSUM_PARTIAL)
5907 return 0;
5908
897ab156
AD		 5909 if (!skb_is_gso(skb))
5910 return 0;
9a799d71 5911
897ab156 5912 if (skb_header_cloned(skb)) {
244e27ad 5913 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5914 if (err)
5915 return err;
9a799d71 5916 }
9a799d71 5917
897ab156
AD		 5918 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5919 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5920
244e27ad 5921 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5922 struct iphdr *iph = ip_hdr(skb);
5923 iph->tot_len = 0;
5924 iph->check = 0;
5925 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5926 iph->daddr, 0,
5927 IPPROTO_TCP,
5928 0);
5929 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5930 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5931 IXGBE_TX_FLAGS_CSUM |
5932 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5933 } else if (skb_is_gso_v6(skb)) {
5934 ipv6_hdr(skb)->payload_len = 0;
5935 tcp_hdr(skb)->check =
5936 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5937 &ipv6_hdr(skb)->daddr,
5938 0, IPPROTO_TCP, 0);
244e27ad
AD		 5939 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5940 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5941 }
5942
091a6246 5943 /* compute header lengths */
897ab156
AD		 5944 l4len = tcp_hdrlen(skb);
5945 *hdr_len = skb_transport_offset(skb) + l4len;
5946
091a6246
AD		 5947 /* update gso size and bytecount with header size */
5948 first->gso_segs = skb_shinfo(skb)->gso_segs;
5949 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5950
c44f5f51 5951 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 5952 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5953 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 5954
5955 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5956 vlan_macip_lens = skb_network_header_len(skb);
5957 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5958 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5959
5960 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5961 mss_l4len_idx);
897ab156
AD		 5962
5963 return 1;
5964}
5965
244e27ad
AD		 5966static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5967 struct ixgbe_tx_buffer *first)
7ca647bd 5968{
fd0db0ed 5969 struct sk_buff *skb = first->skb;
897ab156
AD		 5970 u32 vlan_macip_lens = 0;
5971 u32 mss_l4len_idx = 0;
5972 u32 type_tucmd = 0;
7ca647bd 5973
897ab156 5974 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 5975 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5976 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
5977 return;
897ab156
AD		 5978 } else {
5979 u8 l4_hdr = 0;
244e27ad 5980 switch (first->protocol) {
897ab156
AD		 5981 case __constant_htons(ETH_P_IP):
5982 vlan_macip_lens |= skb_network_header_len(skb);
5983 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5984 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5985 break;
897ab156
AD		 5986 case __constant_htons(ETH_P_IPV6):
5987 vlan_macip_lens |= skb_network_header_len(skb);
5988 l4_hdr = ipv6_hdr(skb)->nexthdr;
5989 break;
5990 default:
5991 if (unlikely(net_ratelimit())) {
5992 dev_warn(tx_ring->dev,
5993 "partial checksum but proto=%x!\n",
244e27ad 5994 first->protocol);
897ab156 5995 }
7ca647bd
JP		 5996 break;
5997 }
897ab156
AD		 5998
5999 switch (l4_hdr) {
7ca647bd 6000 case IPPROTO_TCP:
897ab156
AD		 6001 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6002 mss_l4len_idx = tcp_hdrlen(skb) <<
6003 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6004 break;
6005 case IPPROTO_SCTP:
897ab156
AD		 6006 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6007 mss_l4len_idx = sizeof(struct sctphdr) <<
6008 IXGBE_ADVTXD_L4LEN_SHIFT;
6009 break;
6010 case IPPROTO_UDP:
6011 mss_l4len_idx = sizeof(struct udphdr) <<
6012 IXGBE_ADVTXD_L4LEN_SHIFT;
6013 break;
6014 default:
6015 if (unlikely(net_ratelimit())) {
6016 dev_warn(tx_ring->dev,
6017 "partial checksum but l4 proto=%x!\n",
244e27ad 6018 l4_hdr);
897ab156 6019 }
7ca647bd
JP		 6020 break;
6021 }
244e27ad
AD		 6022
6023 /* update TX checksum flag */
6024 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6025 }
6026
244e27ad 6027 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6028 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6029 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6030
897ab156
AD		 6031 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6032 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6033}
6034
472148c3
AD		 6035#define IXGBE_SET_FLAG(_input, _flag, _result) \
6036 ((_flag <= _result) ? \
6037 ((u32)(_input & _flag) * (_result / _flag)) : \
6038 ((u32)(_input & _flag) / (_flag / _result)))
6039
6040static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6041{
d3d00239 6042 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6043 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6044 IXGBE_ADVTXD_DCMD_DEXT |
6045 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6046
d3d00239 6047 /* set HW vlan bit if vlan is present */
472148c3
AD		 6048 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6049 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6050
d3d00239 6051 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6052 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6053 IXGBE_ADVTXD_DCMD_TSE);
6054
6055 /* set timestamp bit if present */
6056 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6057 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6058
62748b7b 6059 /* insert frame checksum */
472148c3 6060 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6061
d3d00239
AD		 6062 return cmd_type;
6063}
9a799d71 6064
729739b7
AD		 6065static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6066 u32 tx_flags, unsigned int paylen)
d3d00239 6067{
472148c3 6068 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6069
d3d00239 6070 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6071 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6072 IXGBE_TX_FLAGS_CSUM,
6073 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6074
93f5b3c1 6075 /* enble IPv4 checksum for TSO */
472148c3
AD		 6076 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6077 IXGBE_TX_FLAGS_IPV4,
6078 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6079
7f9643fd
AD		 6080 /*
6081 * Check Context must be set if Tx switch is enabled, which it
6082 * always is for case where virtual functions are running
6083 */
472148c3
AD		 6084 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6085 IXGBE_TX_FLAGS_CC,
6086 IXGBE_ADVTXD_CC);
7f9643fd 6087
472148c3 6088 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6089}
44df32c5 6090
d3d00239
AD		 6091#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6092 IXGBE_TXD_CMD_RS)
6093
6094static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6095 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6096 const u8 hdr_len)
6097{
fd0db0ed 6098 struct sk_buff *skb = first->skb;
729739b7 6099 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6100 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6101 struct skb_frag_struct *frag;
6102 dma_addr_t dma;
6103 unsigned int data_len, size;
244e27ad 6104 u32 tx_flags = first->tx_flags;
472148c3 6105 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6106 u16 i = tx_ring->next_to_use;
d3d00239 6107
729739b7
AD		 6108 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6109
ec718254
AD		 6110 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6111
6112 size = skb_headlen(skb);
6113 data_len = skb->data_len;
729739b7 6114
d3d00239
AD		 6115#ifdef IXGBE_FCOE
6116 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6117 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6118 size -= sizeof(struct fcoe_crc_eof) - data_len;
6119 data_len = 0;
729739b7
AD		 6120 } else {
6121 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6122 }
6123 }
44df32c5 6124
d3d00239 6125#endif
729739b7 6126 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6127
ec718254 6128 tx_buffer = first;
9a799d71 6129
ec718254
AD		 6130 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6131 if (dma_mapping_error(tx_ring->dev, dma))
6132 goto dma_error;
6133
6134 /* record length, and DMA address */
6135 dma_unmap_len_set(tx_buffer, len, size);
6136 dma_unmap_addr_set(tx_buffer, dma, dma);
6137
6138 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6139
729739b7 6140 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6141 tx_desc->read.cmd_type_len =
472148c3 6142 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6143
d3d00239 6144 i++;
729739b7 6145 tx_desc++;
d3d00239 6146 if (i == tx_ring->count) {
e4f74028 6147 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6148 i = 0;
6149 }
ec718254 6150 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6151
6152 dma += IXGBE_MAX_DATA_PER_TXD;
6153 size -= IXGBE_MAX_DATA_PER_TXD;
6154
6155 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6156 }
e5a43549 6157
729739b7
AD		 6158 if (likely(!data_len))
6159 break;
9a799d71 6160
472148c3 6161 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6162
729739b7
AD		 6163 i++;
6164 tx_desc++;
6165 if (i == tx_ring->count) {
6166 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6167 i = 0;
6168 }
ec718254 6169 tx_desc->read.olinfo_status = 0;
9a799d71 6170
d3d00239 6171#ifdef IXGBE_FCOE
9e903e08 6172 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6173#else
9e903e08 6174 size = skb_frag_size(frag);
d3d00239
AD		 6175#endif
6176 data_len -= size;
9a799d71 6177
729739b7
AD		 6178 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6179 DMA_TO_DEVICE);
9a799d71 6180
729739b7 6181 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6182 }
9a799d71 6183
729739b7 6184 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6185 cmd_type |= size | IXGBE_TXD_CMD;
6186 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6187
091a6246 6188 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6189
d3d00239
AD		 6190 /* set the timestamp */
6191 first->time_stamp = jiffies;
9a799d71
AK		 6192
6193 /*
729739b7
AD		 6194 * Force memory writes to complete before letting h/w know there
6195 * are new descriptors to fetch. (Only applicable for weak-ordered
6196 * memory model archs, such as IA-64).
6197 *
6198 * We also need this memory barrier to make certain all of the
6199 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6200 */
6201 wmb();
6202
d3d00239
AD		 6203 /* set next_to_watch value indicating a packet is present */
6204 first->next_to_watch = tx_desc;
6205
729739b7
AD		 6206 i++;
6207 if (i == tx_ring->count)
6208 i = 0;
6209
6210 tx_ring->next_to_use = i;
6211
d3d00239 6212 /* notify HW of packet */
84ea2591 6213 writel(i, tx_ring->tail);
d3d00239
AD		 6214
6215 return;
6216dma_error:
729739b7 6217 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6218
6219 /* clear dma mappings for failed tx_buffer_info map */
6220 for (;;) {
729739b7
AD		 6221 tx_buffer = &tx_ring->tx_buffer_info[i];
6222 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6223 if (tx_buffer == first)
d3d00239
AD		 6224 break;
6225 if (i == 0)
6226 i = tx_ring->count;
6227 i--;
6228 }
6229
d3d00239 6230 tx_ring->next_to_use = i;
9a799d71
AK		 6231}
6232
fd0db0ed 6233static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6234 struct ixgbe_tx_buffer *first)
69830529
AD		 6235{
6236 struct ixgbe_q_vector *q_vector = ring->q_vector;
6237 union ixgbe_atr_hash_dword input = { .dword = 0 };
6238 union ixgbe_atr_hash_dword common = { .dword = 0 };
6239 union {
6240 unsigned char *network;
6241 struct iphdr *ipv4;
6242 struct ipv6hdr *ipv6;
6243 } hdr;
ee9e0f0b 6244 struct tcphdr *th;
905e4a41 6245 __be16 vlan_id;
c4cf55e5 6246
69830529
AD		 6247 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6248 if (!q_vector)
6249 return;
6250
6251 /* do nothing if sampling is disabled */
6252 if (!ring->atr_sample_rate)
d3ead241 6253 return;
c4cf55e5 6254
69830529 6255 ring->atr_count++;
c4cf55e5 6256
69830529 6257 /* snag network header to get L4 type and address */
fd0db0ed 6258 hdr.network = skb_network_header(first->skb);
69830529
AD		 6259
6260 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6261 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6262 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6263 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6264 hdr.ipv4->protocol != IPPROTO_TCP))
6265 return;
ee9e0f0b 6266
fd0db0ed 6267 th = tcp_hdr(first->skb);
c4cf55e5 6268
66f32a8b
AD		 6269 /* skip this packet since it is invalid or the socket is closing */
6270 if (!th || th->fin)
69830529
AD		 6271 return;
6272
6273 /* sample on all syn packets or once every atr sample count */
6274 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6275 return;
6276
6277 /* reset sample count */
6278 ring->atr_count = 0;
6279
244e27ad 6280 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6281
6282 /*
6283 * src and dst are inverted, think how the receiver sees them
6284 *
6285 * The input is broken into two sections, a non-compressed section
6286 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6287 * is XORed together and stored in the compressed dword.
6288 */
6289 input.formatted.vlan_id = vlan_id;
6290
6291 /*
6292 * since src port and flex bytes occupy the same word XOR them together
6293 * and write the value to source port portion of compressed dword
6294 */
244e27ad 6295 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6296 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6297 else
244e27ad 6298 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6299 common.port.dst ^= th->source;
6300
244e27ad 6301 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6302 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6303 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6304 } else {
6305 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6306 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6307 hdr.ipv6->saddr.s6_addr32[1] ^
6308 hdr.ipv6->saddr.s6_addr32[2] ^
6309 hdr.ipv6->saddr.s6_addr32[3] ^
6310 hdr.ipv6->daddr.s6_addr32[0] ^
6311 hdr.ipv6->daddr.s6_addr32[1] ^
6312 hdr.ipv6->daddr.s6_addr32[2] ^
6313 hdr.ipv6->daddr.s6_addr32[3];
6314 }
c4cf55e5
PWJ		 6315
6316 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6317 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6318 input, common, ring->queue_index);
c4cf55e5
PWJ		 6319}
6320
63544e9c 6321static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6322{
fc77dc3c 6323 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6324 /* Herbert's original patch had:
6325 * smp_mb__after_netif_stop_queue();
6326 * but since that doesn't exist yet, just open code it. */
6327 smp_mb();
6328
6329 /* We need to check again in a case another CPU has just
6330 * made room available. */
7d4987de 6331 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6332 return -EBUSY;
6333
6334 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6335 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6336 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6337 return 0;
6338}
6339
82d4e46e 6340static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6341{
7d4987de 6342 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6343 return 0;
fc77dc3c 6344 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6345}
6346
09a3b1f8
SH		 6347static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6348{
6349 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6350 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6351 smp_processor_id();
56075a98 6352#ifdef IXGBE_FCOE
6440752c 6353 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6354
e5b64635
JF		 6355 if (((protocol == htons(ETH_P_FCOE)) ||
6356 (protocol == htons(ETH_P_FIP))) &&
6357 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6358 struct ixgbe_ring_feature *f;
6359
6360 f = &adapter->ring_feature[RING_F_FCOE];
6361
6362 while (txq >= f->indices)
6363 txq -= f->indices;
e4b317e9 6364 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6365
e5b64635 6366 return txq;
56075a98
JF		 6367 }
6368#endif
6369
fdd3d631
KK		 6370 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6371 while (unlikely(txq >= dev->real_num_tx_queues))
6372 txq -= dev->real_num_tx_queues;
5f715823 6373 return txq;
fdd3d631 6374 }
c4cf55e5 6375
09a3b1f8
SH		 6376 return skb_tx_hash(dev, skb);
6377}
6378
fc77dc3c 6379netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6380 struct ixgbe_adapter *adapter,
6381 struct ixgbe_ring *tx_ring)
9a799d71 6382{
d3d00239 6383 struct ixgbe_tx_buffer *first;
5f715823 6384 int tso;
d3d00239 6385 u32 tx_flags = 0;
a535c30e
AD		 6386#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6387 unsigned short f;
6388#endif
a535c30e 6389 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6390 __be16 protocol = skb->protocol;
63544e9c 6391 u8 hdr_len = 0;
5e09a105 6392
a535c30e
AD		 6393 /*
6394 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6395 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6396 * + 2 desc gap to keep tail from touching head,
6397 * + 1 desc for context descriptor,
6398 * otherwise try next time
6399 */
6400#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6401 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6402 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6403#else
6404 count += skb_shinfo(skb)->nr_frags;
6405#endif
6406 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6407 tx_ring->tx_stats.tx_busy++;
6408 return NETDEV_TX_BUSY;
6409 }
6410
fd0db0ed
AD		 6411 /* record the location of the first descriptor for this packet */
6412 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6413 first->skb = skb;
091a6246
AD		 6414 first->bytecount = skb->len;
6415 first->gso_segs = 1;
fd0db0ed 6416
66f32a8b 6417 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6418 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6419 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6420 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6421 /* else if it is a SW VLAN check the next protocol and store the tag */
6422 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6423 struct vlan_hdr *vhdr, _vhdr;
6424 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6425 if (!vhdr)
6426 goto out_drop;
6427
6428 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6429 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6430 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6431 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6432 }
6433
aa7bd467
JK		 6434 skb_tx_timestamp(skb);
6435
3a6a4eda
JK		 6436 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6437 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6438 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 6439
6440 /* schedule check for Tx timestamp */
6441 adapter->ptp_tx_skb = skb_get(skb);
6442 adapter->ptp_tx_start = jiffies;
6443 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 6444 }
3a6a4eda 6445
9e0c5648
AD		 6446#ifdef CONFIG_PCI_IOV
6447 /*
6448 * Use the l2switch_enable flag - would be false if the DMA
6449 * Tx switch had been disabled.
6450 */
6451 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 6452 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 6453
6454#endif
32701dc2 6455 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6456 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6457 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6458 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6459 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6460 tx_flags |= (skb->priority & 0x7) <<
6461 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6462 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6463 struct vlan_ethhdr *vhdr;
6464 if (skb_header_cloned(skb) &&
6465 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6466 goto out_drop;
6467 vhdr = (struct vlan_ethhdr *)skb->data;
6468 vhdr->h_vlan_TCI = htons(tx_flags >>
6469 IXGBE_TX_FLAGS_VLAN_SHIFT);
6470 } else {
6471 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6472 }
9a799d71 6473 }
eacd73f7 6474
244e27ad
AD		 6475 /* record initial flags and protocol */
6476 first->tx_flags = tx_flags;
6477 first->protocol = protocol;
6478
eacd73f7 6479#ifdef IXGBE_FCOE
66f32a8b
AD		 6480 /* setup tx offload for FCoE */
6481 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6482 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6483 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6484 if (tso < 0)
6485 goto out_drop;
9a799d71 6486
66f32a8b 6487 goto xmit_fcoe;
eacd73f7 6488 }
9a799d71 6489
66f32a8b 6490#endif /* IXGBE_FCOE */
244e27ad 6491 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6492 if (tso < 0)
897ab156 6493 goto out_drop;
244e27ad
AD		 6494 else if (!tso)
6495 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6496
6497 /* add the ATR filter if ATR is on */
6498 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6499 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6500
6501#ifdef IXGBE_FCOE
6502xmit_fcoe:
6503#endif /* IXGBE_FCOE */
244e27ad 6504 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6505
6506 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6507
6508 return NETDEV_TX_OK;
897ab156
AD		 6509
6510out_drop:
fd0db0ed
AD		 6511 dev_kfree_skb_any(first->skb);
6512 first->skb = NULL;
6513
897ab156 6514 return NETDEV_TX_OK;
9a799d71
AK		 6515}
6516
a50c29dd
AD		 6517static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6518 struct net_device *netdev)
84418e3b
AD		 6519{
6520 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6521 struct ixgbe_ring *tx_ring;
6522
a50c29dd
AD		 6523 /*
6524 * The minimum packet size for olinfo paylen is 17 so pad the skb
6525 * in order to meet this minimum size requirement.
6526 */
f73332fc
SH		 6527 if (unlikely(skb->len < 17)) {
6528 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6529 return NETDEV_TX_OK;
6530 skb->len = 17;
71a49f77 6531 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6532 }
6533
84418e3b 6534 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6535 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6536}
6537
9a799d71
AK		 6538/**
6539 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6540 * @netdev: network interface device structure
6541 * @p: pointer to an address structure
6542 *
6543 * Returns 0 on success, negative on failure
6544 **/
6545static int ixgbe_set_mac(struct net_device *netdev, void *p)
6546{
6547 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6548 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6549 struct sockaddr *addr = p;
6550
6551 if (!is_valid_ether_addr(addr->sa_data))
6552 return -EADDRNOTAVAIL;
6553
6554 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6555 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6556
1d9c0bfd 6557 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6558
6559 return 0;
6560}
6561
6b73e10d
BH		 6562static int
6563ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6564{
6565 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6566 struct ixgbe_hw *hw = &adapter->hw;
6567 u16 value;
6568 int rc;
6569
6570 if (prtad != hw->phy.mdio.prtad)
6571 return -EINVAL;
6572 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6573 if (!rc)
6574 rc = value;
6575 return rc;
6576}
6577
6578static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6579 u16 addr, u16 value)
6580{
6581 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6582 struct ixgbe_hw *hw = &adapter->hw;
6583
6584 if (prtad != hw->phy.mdio.prtad)
6585 return -EINVAL;
6586 return hw->phy.ops.write_reg(hw, addr, devad, value);
6587}
6588
6589static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6590{
6591 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6592
3a6a4eda 6593 switch (cmd) {
3a6a4eda
JK		 6594 case SIOCSHWTSTAMP:
6595 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 6596 default:
6597 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6598 }
6b73e10d
BH		 6599}
6600
0365e6e4
PW		 6601/**
6602 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6603 * netdev->dev_addrs
0365e6e4
PW		 6604 * @netdev: network interface device structure
6605 *
6606 * Returns non-zero on failure
6607 **/
6608static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6609{
6610 int err = 0;
6611 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6612 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6613
7fa7c9dc 6614 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6615 rtnl_lock();
7fa7c9dc 6616 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6617 rtnl_unlock();
7fa7c9dc
AD		 6618
6619 /* update SAN MAC vmdq pool selection */
6620 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6621 }
6622 return err;
6623}
6624
6625/**
6626 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6627 * netdev->dev_addrs
0365e6e4
PW		 6628 * @netdev: network interface device structure
6629 *
6630 * Returns non-zero on failure
6631 **/
6632static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6633{
6634 int err = 0;
6635 struct ixgbe_adapter *adapter = netdev_priv(dev);
6636 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6637
6638 if (is_valid_ether_addr(mac->san_addr)) {
6639 rtnl_lock();
6640 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6641 rtnl_unlock();
6642 }
6643 return err;
6644}
6645
9a799d71
AK		 6646#ifdef CONFIG_NET_POLL_CONTROLLER
6647/*
6648 * Polling 'interrupt' - used by things like netconsole to send skbs
6649 * without having to re-enable interrupts. It's not called while
6650 * the interrupt routine is executing.
6651 */
6652static void ixgbe_netpoll(struct net_device *netdev)
6653{
6654 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6655 int i;
9a799d71 6656
1a647bd2
AD		 6657 /* if interface is down do nothing */
6658 if (test_bit(__IXGBE_DOWN, &adapter->state))
6659 return;
6660
9a799d71 6661 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6662 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6663 for (i = 0; i < adapter->num_q_vectors; i++)
6664 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6665 } else {
6666 ixgbe_intr(adapter->pdev->irq, netdev);
6667 }
9a799d71 6668 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6669}
9a799d71 6670
581330ba 6671#endif
de1036b1
ED		 6672static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6673 struct rtnl_link_stats64 *stats)
6674{
6675 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6676 int i;
6677
1a51502b 6678 rcu_read_lock();
de1036b1 6679 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6680 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6681 u64 bytes, packets;
6682 unsigned int start;
6683
1a51502b
ED		 6684 if (ring) {
6685 do {
6686 start = u64_stats_fetch_begin_bh(&ring->syncp);
6687 packets = ring->stats.packets;
6688 bytes = ring->stats.bytes;
6689 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6690 stats->rx_packets += packets;
6691 stats->rx_bytes += bytes;
6692 }
de1036b1 6693 }
1ac9ad13
ED		 6694
6695 for (i = 0; i < adapter->num_tx_queues; i++) {
6696 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6697 u64 bytes, packets;
6698 unsigned int start;
6699
6700 if (ring) {
6701 do {
6702 start = u64_stats_fetch_begin_bh(&ring->syncp);
6703 packets = ring->stats.packets;
6704 bytes = ring->stats.bytes;
6705 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6706 stats->tx_packets += packets;
6707 stats->tx_bytes += bytes;
6708 }
6709 }
1a51502b 6710 rcu_read_unlock();
de1036b1
ED		 6711 /* following stats updated by ixgbe_watchdog_task() */
6712 stats->multicast = netdev->stats.multicast;
6713 stats->rx_errors = netdev->stats.rx_errors;
6714 stats->rx_length_errors = netdev->stats.rx_length_errors;
6715 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6716 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6717 return stats;
6718}
6719
8af3c33f 6720#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6721/**
6722 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6723 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6724 * @tc: number of traffic classes currently enabled
6725 *
6726 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6727 * 802.1Q priority maps to a packet buffer that exists.
6728 */
6729static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6730{
6731 struct ixgbe_hw *hw = &adapter->hw;
6732 u32 reg, rsave;
6733 int i;
6734
6735 /* 82598 have a static priority to TC mapping that can not
6736 * be changed so no validation is needed.
6737 */
6738 if (hw->mac.type == ixgbe_mac_82598EB)
6739 return;
6740
6741 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6742 rsave = reg;
6743
6744 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6745 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6746
6747 /* If up2tc is out of bounds default to zero */
6748 if (up2tc > tc)
6749 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6750 }
6751
6752 if (reg != rsave)
6753 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6754
6755 return;
6756}
6757
02debdc9
AD		 6758/**
6759 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6760 * @adapter: Pointer to adapter struct
6761 *
6762 * Populate the netdev user priority to tc map
6763 */
6764static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6765{
6766 struct net_device *dev = adapter->netdev;
6767 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6768 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6769 u8 prio;
6770
6771 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6772 u8 tc = 0;
6773
6774 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6775 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6776 else if (ets)
6777 tc = ets->prio_tc[prio];
6778
6779 netdev_set_prio_tc_map(dev, prio, tc);
6780 }
6781}
6782
49ce9c2c
BH		 6783/**
6784 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6785 *
6786 * @netdev: net device to configure
6787 * @tc: number of traffic classes to enable
6788 */
6789int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6790{
8b1c0b24
JF		 6791 struct ixgbe_adapter *adapter = netdev_priv(dev);
6792 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6793
8b1c0b24 6794 /* Hardware supports up to 8 traffic classes */
4de2a022 6795 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6796 (hw->mac.type == ixgbe_mac_82598EB &&
6797 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6798 return -EINVAL;
6799
6800 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6801 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6802 * hardware is not flexible enough to do this dynamically.
6803 */
6804 if (netif_running(dev))
6805 ixgbe_close(dev);
6806 ixgbe_clear_interrupt_scheme(adapter);
6807
e7589eab 6808 if (tc) {
8b1c0b24 6809 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6810 ixgbe_set_prio_tc_map(adapter);
6811
e7589eab 6812 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6813
943561d3
AD		 6814 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6815 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6816 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6817 }
e7589eab 6818 } else {
8b1c0b24 6819 netdev_reset_tc(dev);
02debdc9 6820
943561d3
AD		 6821 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6822 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6823
6824 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6825
6826 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6827 adapter->dcb_cfg.pfc_mode_enable = false;
6828 }
6829
8b1c0b24
JF		 6830 ixgbe_init_interrupt_scheme(adapter);
6831 ixgbe_validate_rtr(adapter, tc);
6832 if (netif_running(dev))
6833 ixgbe_open(dev);
6834
6835 return 0;
6836}
de1036b1 6837
8af3c33f 6838#endif /* CONFIG_IXGBE_DCB */
da36b647
GR		 6839#ifdef CONFIG_PCI_IOV
6840void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6841{
6842 struct net_device *netdev = adapter->netdev;
6843
6844 rtnl_lock();
6845#ifdef CONFIG_IXGBE_DCB
6846 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
6847#else
6848 if (netif_running(netdev))
6849 ixgbe_close(netdev);
6850 ixgbe_clear_interrupt_scheme(adapter);
6851 ixgbe_init_interrupt_scheme(adapter);
6852 if (netif_running(netdev))
6853 ixgbe_open(netdev);
6854#endif
6855 rtnl_unlock();
6856}
6857
6858#endif
082757af
DS		 6859void ixgbe_do_reset(struct net_device *netdev)
6860{
6861 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6862
6863 if (netif_running(netdev))
6864 ixgbe_reinit_locked(adapter);
6865 else
6866 ixgbe_reset(adapter);
6867}
6868
c8f44aff 6869static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6870 netdev_features_t features)
082757af
DS		 6871{
6872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6873
082757af 6874 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6875 if (!(features & NETIF_F_RXCSUM))
6876 features &= ~NETIF_F_LRO;
082757af 6877
567d2de2
AD		 6878 /* Turn off LRO if not RSC capable */
6879 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6880 features &= ~NETIF_F_LRO;
8e2813f5 6881
567d2de2 6882 return features;
082757af
DS		 6883}
6884
c8f44aff 6885static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6886 netdev_features_t features)
082757af
DS		 6887{
6888 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6889 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6890 bool need_reset = false;
6891
082757af 6892 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6893 if (!(features & NETIF_F_LRO)) {
6894 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6895 need_reset = true;
567d2de2
AD		 6896 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6897 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6898 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6899 if (adapter->rx_itr_setting == 1 ||
6900 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6901 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6902 need_reset = true;
6903 } else if ((changed ^ features) & NETIF_F_LRO) {
6904 e_info(probe, "rx-usecs set too low, "
6905 "disabling RSC\n");
082757af
DS		 6906 }
6907 }
6908
6909 /*
6910 * Check if Flow Director n-tuple support was enabled or disabled. If
6911 * the state changed, we need to reset.
6912 */
39cb681b
AD		 6913 switch (features & NETIF_F_NTUPLE) {
6914 case NETIF_F_NTUPLE:
567d2de2 6915 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6916 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6917 need_reset = true;
6918
567d2de2
AD		 6919 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6920 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6921 break;
6922 default:
6923 /* turn off perfect filters, enable ATR and reset */
6924 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6925 need_reset = true;
6926
6927 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6928
6929 /* We cannot enable ATR if SR-IOV is enabled */
6930 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6931 break;
6932
6933 /* We cannot enable ATR if we have 2 or more traffic classes */
6934 if (netdev_get_num_tc(netdev) > 1)
6935 break;
6936
6937 /* We cannot enable ATR if RSS is disabled */
6938 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6939 break;
6940
6941 /* A sample rate of 0 indicates ATR disabled */
6942 if (!adapter->atr_sample_rate)
6943 break;
6944
6945 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6946 break;
082757af
DS		 6947 }
6948
146d4cc9
JF		 6949 if (features & NETIF_F_HW_VLAN_RX)
6950 ixgbe_vlan_strip_enable(adapter);
6951 else
6952 ixgbe_vlan_strip_disable(adapter);
6953
3f2d1c0f
BG		 6954 if (changed & NETIF_F_RXALL)
6955 need_reset = true;
6956
567d2de2 6957 netdev->features = features;
082757af
DS		 6958 if (need_reset)
6959 ixgbe_do_reset(netdev);
6960
6961 return 0;
082757af
DS		 6962}
6963
edc7d573 6964static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 6965 struct net_device *dev,
6b6e2725 6966 const unsigned char *addr,
0f4b0add
JF		 6967 u16 flags)
6968{
6969 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6970 int err;
6971
6972 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6973 return -EOPNOTSUPP;
0f4b0add 6974
b1ac1ef7
JF		 6975 /* Hardware does not support aging addresses so if a
6976 * ndm_state is given only allow permanent addresses
6977 */
6978 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 6979 pr_info("%s: FDB only supports static addresses\n",
6980 ixgbe_driver_name);
6981 return -EINVAL;
6982 }
6983
46acc460 6984 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 6985 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6986
6987 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6988 err = dev_uc_add_excl(dev, addr);
0f4b0add 6989 else
95447461
JF		 6990 err = -ENOMEM;
6991 } else if (is_multicast_ether_addr(addr)) {
6992 err = dev_mc_add_excl(dev, addr);
6993 } else {
6994 err = -EINVAL;
0f4b0add
JF		 6995 }
6996
6997 /* Only return duplicate errors if NLM_F_EXCL is set */
6998 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6999 err = 0;
7000
7001 return err;
7002}
7003
7004static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
7005 struct net_device *dev,
6b6e2725 7006 const unsigned char *addr)
0f4b0add
JF		 7007{
7008 struct ixgbe_adapter *adapter = netdev_priv(dev);
7009 int err = -EOPNOTSUPP;
7010
7011 if (ndm->ndm_state & NUD_PERMANENT) {
7012 pr_info("%s: FDB only supports static addresses\n",
7013 ixgbe_driver_name);
7014 return -EINVAL;
7015 }
7016
7017 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7018 if (is_unicast_ether_addr(addr))
7019 err = dev_uc_del(dev, addr);
7020 else if (is_multicast_ether_addr(addr))
7021 err = dev_mc_del(dev, addr);
7022 else
7023 err = -EINVAL;
7024 }
7025
7026 return err;
7027}
7028
7029static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7030 struct netlink_callback *cb,
7031 struct net_device *dev,
7032 int idx)
7033{
7034 struct ixgbe_adapter *adapter = netdev_priv(dev);
7035
7036 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7037 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7038
7039 return idx;
7040}
7041
815cccbf
JF		 7042static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7043 struct nlmsghdr *nlh)
7044{
7045 struct ixgbe_adapter *adapter = netdev_priv(dev);
7046 struct nlattr *attr, *br_spec;
7047 int rem;
7048
7049 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7050 return -EOPNOTSUPP;
7051
7052 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7053
7054 nla_for_each_nested(attr, br_spec, rem) {
7055 __u16 mode;
7056 u32 reg = 0;
7057
7058 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7059 continue;
7060
7061 mode = nla_get_u16(attr);
9b735984 7062 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7063 reg = 0;
9b735984
GR		 7064 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7065 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7066 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7067 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7068 } else
815cccbf
JF		 7069 return -EINVAL;
7070
7071 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7072
7073 e_info(drv, "enabling bridge mode: %s\n",
7074 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7075 }
7076
7077 return 0;
7078}
7079
7080static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7081 struct net_device *dev)
7082{
7083 struct ixgbe_adapter *adapter = netdev_priv(dev);
7084 u16 mode;
7085
7086 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7087 return 0;
7088
9b735984 7089 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7090 mode = BRIDGE_MODE_VEB;
7091 else
7092 mode = BRIDGE_MODE_VEPA;
7093
7094 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7095}
7096
0edc3527 7097static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7098 .ndo_open = ixgbe_open,
0edc3527 7099 .ndo_stop = ixgbe_close,
00829823 7100 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7101 .ndo_select_queue = ixgbe_select_queue,
581330ba 7102 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7103 .ndo_validate_addr = eth_validate_addr,
7104 .ndo_set_mac_address = ixgbe_set_mac,
7105 .ndo_change_mtu = ixgbe_change_mtu,
7106 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7107 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7108 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7109 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7110 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7111 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7112 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7113 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7114 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7115 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7116#ifdef CONFIG_IXGBE_DCB
24095aa3 7117 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7118#endif
0edc3527
SH		 7119#ifdef CONFIG_NET_POLL_CONTROLLER
7120 .ndo_poll_controller = ixgbe_netpoll,
7121#endif
332d4a7d
YZ		 7122#ifdef IXGBE_FCOE
7123 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7124 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7125 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7126 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7127 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7128 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7129 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7130#endif /* IXGBE_FCOE */
082757af
DS		 7131 .ndo_set_features = ixgbe_set_features,
7132 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 7133 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7134 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7135 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
815cccbf
JF		 7136 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7137 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
0edc3527
SH		 7138};
7139
8e2813f5
JK		 7140/**
7141 * ixgbe_wol_supported - Check whether device supports WoL
7142 * @hw: hw specific details
7143 * @device_id: the device ID
7144 * @subdev_id: the subsystem device ID
7145 *
7146 * This function is used by probe and ethtool to determine
7147 * which devices have WoL support
7148 *
7149 **/
7150int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7151 u16 subdevice_id)
7152{
7153 struct ixgbe_hw *hw = &adapter->hw;
7154 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7155 int is_wol_supported = 0;
7156
7157 switch (device_id) {
7158 case IXGBE_DEV_ID_82599_SFP:
7159 /* Only these subdevices could supports WOL */
7160 switch (subdevice_id) {
7161 case IXGBE_SUBDEV_ID_82599_560FLR:
7162 /* only support first port */
7163 if (hw->bus.func != 0)
7164 break;
7165 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7166 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7167 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8e2813f5
JK		 7168 is_wol_supported = 1;
7169 break;
7170 }
7171 break;
7172 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7173 /* All except this subdevice support WOL */
7174 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7175 is_wol_supported = 1;
7176 break;
7177 case IXGBE_DEV_ID_82599_KX4:
7178 is_wol_supported = 1;
7179 break;
7180 case IXGBE_DEV_ID_X540T:
df376f0d 7181 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7182 /* check eeprom to see if enabled wol */
7183 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7184 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7185 (hw->bus.func == 0))) {
7186 is_wol_supported = 1;
7187 }
7188 break;
7189 }
7190
7191 return is_wol_supported;
7192}
7193
9a799d71
AK		 7194/**
7195 * ixgbe_probe - Device Initialization Routine
7196 * @pdev: PCI device information struct
7197 * @ent: entry in ixgbe_pci_tbl
7198 *
7199 * Returns 0 on success, negative on failure
7200 *
7201 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7202 * The OS initialization, configuring of the adapter private structure,
7203 * and a hardware reset occur.
7204 **/
1dd06ae8 7205static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7206{
7207 struct net_device *netdev;
7208 struct ixgbe_adapter *adapter = NULL;
7209 struct ixgbe_hw *hw;
7210 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7211 static int cards_found;
7212 int i, err, pci_using_dac;
289700db 7213 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7214 unsigned int indices = num_possible_cpus();
3f4a6f00 7215 unsigned int dcb_max = 0;
eacd73f7
YZ		 7216#ifdef IXGBE_FCOE
7217 u16 device_caps;
7218#endif
289700db 7219 u32 eec;
9a799d71 7220
bded64a7
AG		 7221 /* Catch broken hardware that put the wrong VF device ID in
7222 * the PCIe SR-IOV capability.
7223 */
7224 if (pdev->is_virtfn) {
7225 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7226 pci_name(pdev), pdev->vendor, pdev->device);
7227 return -EINVAL;
7228 }
7229
9ce77666 7230 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7231 if (err)
7232 return err;
7233
1b507730
NN		 7234 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7235 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7236 pci_using_dac = 1;
7237 } else {
1b507730 7238 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7239 if (err) {
1b507730
NN		 7240 err = dma_set_coherent_mask(&pdev->dev,
7241 DMA_BIT_MASK(32));
9a799d71 7242 if (err) {
b8bc0421
DC		 7243 dev_err(&pdev->dev,
7244 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7245 goto err_dma;
7246 }
7247 }
7248 pci_using_dac = 0;
7249 }
7250
9ce77666 7251 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7252 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7253 if (err) {
b8bc0421
DC		 7254 dev_err(&pdev->dev,
7255 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7256 goto err_pci_reg;
7257 }
7258
19d5afd4 7259 pci_enable_pcie_error_reporting(pdev);
6fabd715 7260
9a799d71 7261 pci_set_master(pdev);
fb3b27bc 7262 pci_save_state(pdev);
9a799d71 7263
e901acd6 7264#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7265 if (ii->mac == ixgbe_mac_82598EB)
7266 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7267 IXGBE_MAX_RSS_INDICES);
7268 else
7269 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7270 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7271#endif
7272
c85a2618
JF		 7273 if (ii->mac == ixgbe_mac_82598EB)
7274 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7275 else
7276 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7277
e901acd6 7278#ifdef IXGBE_FCOE
c85a2618
JF		 7279 indices += min_t(unsigned int, num_possible_cpus(),
7280 IXGBE_MAX_FCOE_INDICES);
7281#endif
3f4a6f00 7282 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7283 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7284 if (!netdev) {
7285 err = -ENOMEM;
7286 goto err_alloc_etherdev;
7287 }
7288
9a799d71
AK		 7289 SET_NETDEV_DEV(netdev, &pdev->dev);
7290
9a799d71 7291 adapter = netdev_priv(netdev);
c60fbb00 7292 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7293
7294 adapter->netdev = netdev;
7295 adapter->pdev = pdev;
7296 hw = &adapter->hw;
7297 hw->back = adapter;
b3f4d599 7298 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7299
05857980 7300 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7301 pci_resource_len(pdev, 0));
9a799d71
AK		 7302 if (!hw->hw_addr) {
7303 err = -EIO;
7304 goto err_ioremap;
7305 }
7306
0edc3527 7307 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7308 ixgbe_set_ethtool_ops(netdev);
9a799d71 7309 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7310 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7311
9a799d71
AK		 7312 adapter->bd_number = cards_found;
7313
9a799d71
AK		 7314 /* Setup hw api */
7315 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7316 hw->mac.type = ii->mac;
9a799d71 7317
c44ade9e
JB		 7318 /* EEPROM */
7319 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7320 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7321 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7322 if (!(eec & (1 << 8)))
7323 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7324
7325 /* PHY */
7326 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7327 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7328 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7329 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7330 hw->phy.mdio.mmds = 0;
7331 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7332 hw->phy.mdio.dev = netdev;
7333 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7334 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7335
8ca783ab 7336 ii->get_invariants(hw);
9a799d71
AK		 7337
7338 /* setup the private structure */
7339 err = ixgbe_sw_init(adapter);
7340 if (err)
7341 goto err_sw_init;
7342
e86bff0e 7343 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7344 switch (adapter->hw.mac.type) {
7345 case ixgbe_mac_82599EB:
7346 case ixgbe_mac_X540:
e86bff0e 7347 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7348 break;
7349 default:
7350 break;
7351 }
e86bff0e 7352
bf069c97
DS		 7353 /*
7354 * If there is a fan on this device and it has failed log the
7355 * failure.
7356 */
7357 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7358 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7359 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7360 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7361 }
7362
8ef78adc
PWJ		 7363 if (allow_unsupported_sfp)
7364 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7365
c44ade9e 7366 /* reset_hw fills in the perm_addr as well */
119fc60a 7367 hw->phy.reset_if_overtemp = true;
c44ade9e 7368 err = hw->mac.ops.reset_hw(hw);
119fc60a 7369 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7370 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7371 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7372 err = 0;
7373 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7374 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7375 "module type was detected.\n");
7376 e_dev_err("Reload the driver after installing a supported "
7377 "module.\n");
04f165ef
PW		 7378 goto err_sw_init;
7379 } else if (err) {
849c4542 7380 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7381 goto err_sw_init;
7382 }
7383
99d74487 7384#ifdef CONFIG_PCI_IOV
60a1a680
GR		 7385 /* SR-IOV not supported on the 82598 */
7386 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7387 goto skip_sriov;
7388 /* Mailbox */
7389 ixgbe_init_mbx_params_pf(hw);
7390 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7391 ixgbe_enable_sriov(adapter);
43dc4e01 7392 pci_sriov_set_totalvfs(pdev, 63);
60a1a680 7393skip_sriov:
1cdd1ec8 7394
99d74487 7395#endif
396e799c 7396 netdev->features = NETIF_F_SG |
e8e9f696 7397 NETIF_F_IP_CSUM |
082757af 7398 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7399 NETIF_F_HW_VLAN_TX |
7400 NETIF_F_HW_VLAN_RX |
082757af
DS		 7401 NETIF_F_HW_VLAN_FILTER |
7402 NETIF_F_TSO |
7403 NETIF_F_TSO6 |
082757af
DS		 7404 NETIF_F_RXHASH |
7405 NETIF_F_RXCSUM;
9a799d71 7406
082757af 7407 netdev->hw_features = netdev->features;
ad31c402 7408
58be7666
DS		 7409 switch (adapter->hw.mac.type) {
7410 case ixgbe_mac_82599EB:
7411 case ixgbe_mac_X540:
45a5ead0 7412 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7413 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7414 NETIF_F_NTUPLE;
58be7666
DS		 7415 break;
7416 default:
7417 break;
7418 }
45a5ead0 7419
3f2d1c0f
BG		 7420 netdev->hw_features |= NETIF_F_RXALL;
7421
ad31c402
JK		 7422 netdev->vlan_features |= NETIF_F_TSO;
7423 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7424 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7425 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7426 netdev->vlan_features |= NETIF_F_SG;
7427
01789349 7428 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7429 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7430
7a6b6f51 7431#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7432 netdev->dcbnl_ops = &dcbnl_ops;
7433#endif
7434
eacd73f7 7435#ifdef IXGBE_FCOE
0d551589 7436 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7437 if (hw->mac.ops.get_device_caps) {
7438 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7439 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7440 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7441 }
7c8ae65a
AD		 7442
7443 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7444
a58915c7
AD		 7445 netdev->features |= NETIF_F_FSO |
7446 NETIF_F_FCOE_CRC;
7447
7c8ae65a
AD		 7448 netdev->vlan_features |= NETIF_F_FSO |
7449 NETIF_F_FCOE_CRC |
7450 NETIF_F_FCOE_MTU;
5e09d7f6 7451 }
eacd73f7 7452#endif /* IXGBE_FCOE */
7b872a55 7453 if (pci_using_dac) {
9a799d71 7454 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7455 netdev->vlan_features |= NETIF_F_HIGHDMA;
7456 }
9a799d71 7457
082757af
DS		 7458 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7459 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7460 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7461 netdev->features |= NETIF_F_LRO;
7462
9a799d71 7463 /* make sure the EEPROM is good */
c44ade9e 7464 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7465 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7466 err = -EIO;
35937c05 7467 goto err_sw_init;
9a799d71
AK		 7468 }
7469
7470 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 7471
aaeb6cdf 7472 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 7473 e_dev_err("invalid MAC address\n");
9a799d71 7474 err = -EIO;
35937c05 7475 goto err_sw_init;
9a799d71
AK		 7476 }
7477
7086400d 7478 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7479 (unsigned long) adapter);
9a799d71 7480
7086400d
AD		 7481 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7482 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7483
021230d4
AV		 7484 err = ixgbe_init_interrupt_scheme(adapter);
7485 if (err)
7486 goto err_sw_init;
9a799d71 7487
8e2813f5 7488 /* WOL not supported for all devices */
c23f5b6b 7489 adapter->wol = 0;
8e2813f5
JK		 7490 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7491 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7492 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7493
e8e26350
PW		 7494 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7495
15e5209f
ET		 7496 /* save off EEPROM version number */
7497 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7498 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7499
04f165ef
PW		 7500 /* pick up the PCI bus settings for reporting later */
7501 hw->mac.ops.get_bus_info(hw);
7502
9a799d71 7503 /* print bus type/speed/width info */
849c4542 7504 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7505 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7506 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7507 "Unknown"),
7508 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7509 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7510 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7511 "Unknown"),
7512 netdev->dev_addr);
289700db
DS		 7513
7514 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7515 if (err)
9fe93afd 7516 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7517 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7518 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7519 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7520 part_str);
e8e26350 7521 else
289700db
DS		 7522 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7523 hw->mac.type, hw->phy.type, part_str);
9a799d71 7524
e8e26350 7525 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7526 e_dev_warn("PCI-Express bandwidth available for this card is "
7527 "not sufficient for optimal performance.\n");
7528 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7529 "is required.\n");
0c254d86
AK		 7530 }
7531
9a799d71 7532 /* reset the hardware with the new settings */
794caeb2 7533 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7534 if (err == IXGBE_ERR_EEPROM_VERSION) {
7535 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7536 e_dev_warn("This device is a pre-production adapter/LOM. "
7537 "Please be aware there may be issues associated "
7538 "with your hardware. If you are experiencing "
7539 "problems please contact your Intel or hardware "
7540 "representative who provided you with this "
7541 "hardware.\n");
794caeb2 7542 }
9a799d71
AK		 7543 strcpy(netdev->name, "eth%d");
7544 err = register_netdev(netdev);
7545 if (err)
7546 goto err_register;
7547
ec74a471
ET		 7548 /* power down the optics for 82599 SFP+ fiber */
7549 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 7550 hw->mac.ops.disable_tx_laser(hw);
7551
54386467
JB		 7552 /* carrier off reporting is important to ethtool even BEFORE open */
7553 netif_carrier_off(netdev);
7554
5dd2d332 7555#ifdef CONFIG_IXGBE_DCA
652f093f 7556 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7557 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7558 ixgbe_setup_dca(adapter);
7559 }
7560#endif
1cdd1ec8 7561 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7562 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7563 for (i = 0; i < adapter->num_vfs; i++)
7564 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7565 }
7566
2466dd9c
JK		 7567 /* firmware requires driver version to be 0xFFFFFFFF
7568 * since os does not support feature
7569 */
9612de92 7570 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7571 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7572 0xFF);
9612de92 7573
0365e6e4
PW		 7574 /* add san mac addr to netdev */
7575 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7576
ea81875a 7577 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7578 cards_found++;
3ca8bc6d 7579
1210982b 7580#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7581 if (ixgbe_sysfs_init(adapter))
7582 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7583#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7584
00949167
CS		 7585#ifdef CONFIG_DEBUG_FS
7586 ixgbe_dbg_adapter_init(adapter);
7587#endif /* CONFIG_DEBUG_FS */
7588
9a799d71
AK		 7589 return 0;
7590
7591err_register:
5eba3699 7592 ixgbe_release_hw_control(adapter);
7a921c93 7593 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7594err_sw_init:
99d74487 7595 ixgbe_disable_sriov(adapter);
7086400d 7596 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7597 iounmap(hw->hw_addr);
7598err_ioremap:
7599 free_netdev(netdev);
7600err_alloc_etherdev:
e8e9f696
JP		 7601 pci_release_selected_regions(pdev,
7602 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7603err_pci_reg:
7604err_dma:
7605 pci_disable_device(pdev);
7606 return err;
7607}
7608
7609/**
7610 * ixgbe_remove - Device Removal Routine
7611 * @pdev: PCI device information struct
7612 *
7613 * ixgbe_remove is called by the PCI subsystem to alert the driver
7614 * that it should release a PCI device. The could be caused by a
7615 * Hot-Plug event, or because the driver is going to be removed from
7616 * memory.
7617 **/
9f9a12f8 7618static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 7619{
c60fbb00
AD		 7620 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7621 struct net_device *netdev = adapter->netdev;
9a799d71 7622
00949167
CS		 7623#ifdef CONFIG_DEBUG_FS
7624 ixgbe_dbg_adapter_exit(adapter);
7625#endif /*CONFIG_DEBUG_FS */
7626
9a799d71 7627 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7628 cancel_work_sync(&adapter->service_task);
9a799d71 7629
3a6a4eda 7630
5dd2d332 7631#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7632 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7633 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7634 dca_remove_requester(&pdev->dev);
7635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7636 }
7637
7638#endif
1210982b 7639#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7640 ixgbe_sysfs_exit(adapter);
1210982b 7641#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7642
0365e6e4
PW		 7643 /* remove the added san mac */
7644 ixgbe_del_sanmac_netdev(netdev);
7645
c4900be0
DS		 7646 if (netdev->reg_state == NETREG_REGISTERED)
7647 unregister_netdev(netdev);
9a799d71 7648
da36b647
GR		 7649#ifdef CONFIG_PCI_IOV
7650 /*
7651 * Only disable SR-IOV on unload if the user specified the now
7652 * deprecated max_vfs module parameter.
7653 */
7654 if (max_vfs)
7655 ixgbe_disable_sriov(adapter);
7656#endif
7a921c93 7657 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7658
021230d4 7659 ixgbe_release_hw_control(adapter);
9a799d71 7660
2b1588c3
AD		 7661#ifdef CONFIG_DCB
7662 kfree(adapter->ixgbe_ieee_pfc);
7663 kfree(adapter->ixgbe_ieee_ets);
7664
7665#endif
9a799d71 7666 iounmap(adapter->hw.hw_addr);
9ce77666 7667 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7668 IORESOURCE_MEM));
9a799d71 7669
849c4542 7670 e_dev_info("complete\n");
021230d4 7671
9a799d71
AK		 7672 free_netdev(netdev);
7673
19d5afd4 7674 pci_disable_pcie_error_reporting(pdev);
6fabd715 7675
9a799d71
AK		 7676 pci_disable_device(pdev);
7677}
7678
7679/**
7680 * ixgbe_io_error_detected - called when PCI error is detected
7681 * @pdev: Pointer to PCI device
7682 * @state: The current pci connection state
7683 *
7684 * This function is called after a PCI bus error affecting
7685 * this device has been detected.
7686 */
7687static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7688 pci_channel_state_t state)
9a799d71 7689{
c60fbb00
AD		 7690 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7691 struct net_device *netdev = adapter->netdev;
9a799d71 7692
83c61fa9
GR		 7693#ifdef CONFIG_PCI_IOV
7694 struct pci_dev *bdev, *vfdev;
7695 u32 dw0, dw1, dw2, dw3;
7696 int vf, pos;
7697 u16 req_id, pf_func;
7698
7699 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7700 adapter->num_vfs == 0)
7701 goto skip_bad_vf_detection;
7702
7703 bdev = pdev->bus->self;
62f87c0e 7704 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7705 bdev = bdev->bus->self;
7706
7707 if (!bdev)
7708 goto skip_bad_vf_detection;
7709
7710 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7711 if (!pos)
7712 goto skip_bad_vf_detection;
7713
7714 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7715 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7716 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7717 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7718
7719 req_id = dw1 >> 16;
7720 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7721 if (!(req_id & 0x0080))
7722 goto skip_bad_vf_detection;
7723
7724 pf_func = req_id & 0x01;
7725 if ((pf_func & 1) == (pdev->devfn & 1)) {
7726 unsigned int device_id;
7727
7728 vf = (req_id & 0x7F) >> 1;
7729 e_dev_err("VF %d has caused a PCIe error\n", vf);
7730 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7731 "%8.8x\tdw3: %8.8x\n",
7732 dw0, dw1, dw2, dw3);
7733 switch (adapter->hw.mac.type) {
7734 case ixgbe_mac_82599EB:
7735 device_id = IXGBE_82599_VF_DEVICE_ID;
7736 break;
7737 case ixgbe_mac_X540:
7738 device_id = IXGBE_X540_VF_DEVICE_ID;
7739 break;
7740 default:
7741 device_id = 0;
7742 break;
7743 }
7744
7745 /* Find the pci device of the offending VF */
36e90319 7746 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7747 while (vfdev) {
7748 if (vfdev->devfn == (req_id & 0xFF))
7749 break;
36e90319 7750 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7751 device_id, vfdev);
7752 }
7753 /*
7754 * There's a slim chance the VF could have been hot plugged,
7755 * so if it is no longer present we don't need to issue the
7756 * VFLR. Just clean up the AER in that case.
7757 */
7758 if (vfdev) {
7759 e_dev_err("Issuing VFLR to VF %d\n", vf);
7760 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 7761 /* Free device reference count */
7762 pci_dev_put(vfdev);
83c61fa9
GR		 7763 }
7764
7765 pci_cleanup_aer_uncorrect_error_status(pdev);
7766 }
7767
7768 /*
7769 * Even though the error may have occurred on the other port
7770 * we still need to increment the vf error reference count for
7771 * both ports because the I/O resume function will be called
7772 * for both of them.
7773 */
7774 adapter->vferr_refcount++;
7775
7776 return PCI_ERS_RESULT_RECOVERED;
7777
7778skip_bad_vf_detection:
7779#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7780 netif_device_detach(netdev);
7781
3044b8d1
BL		 7782 if (state == pci_channel_io_perm_failure)
7783 return PCI_ERS_RESULT_DISCONNECT;
7784
9a799d71
AK		 7785 if (netif_running(netdev))
7786 ixgbe_down(adapter);
7787 pci_disable_device(pdev);
7788
b4617240 7789 /* Request a slot reset. */
9a799d71
AK		 7790 return PCI_ERS_RESULT_NEED_RESET;
7791}
7792
7793/**
7794 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7795 * @pdev: Pointer to PCI device
7796 *
7797 * Restart the card from scratch, as if from a cold-boot.
7798 */
7799static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7800{
c60fbb00 7801 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7802 pci_ers_result_t result;
7803 int err;
9a799d71 7804
9ce77666 7805 if (pci_enable_device_mem(pdev)) {
396e799c 7806 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7807 result = PCI_ERS_RESULT_DISCONNECT;
7808 } else {
7809 pci_set_master(pdev);
7810 pci_restore_state(pdev);
c0e1f68b 7811 pci_save_state(pdev);
9a799d71 7812
dd4d8ca6 7813 pci_wake_from_d3(pdev, false);
9a799d71 7814
6fabd715 7815 ixgbe_reset(adapter);
88512539 7816 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7817 result = PCI_ERS_RESULT_RECOVERED;
7818 }
7819
7820 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7821 if (err) {
849c4542
ET		 7822 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7823 "failed 0x%0x\n", err);
6fabd715
PWJ		 7824 /* non-fatal, continue */
7825 }
9a799d71 7826
6fabd715 7827 return result;
9a799d71
AK		 7828}
7829
7830/**
7831 * ixgbe_io_resume - called when traffic can start flowing again.
7832 * @pdev: Pointer to PCI device
7833 *
7834 * This callback is called when the error recovery driver tells us that
7835 * its OK to resume normal operation.
7836 */
7837static void ixgbe_io_resume(struct pci_dev *pdev)
7838{
c60fbb00
AD		 7839 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7840 struct net_device *netdev = adapter->netdev;
9a799d71 7841
83c61fa9
GR		 7842#ifdef CONFIG_PCI_IOV
7843 if (adapter->vferr_refcount) {
7844 e_info(drv, "Resuming after VF err\n");
7845 adapter->vferr_refcount--;
7846 return;
7847 }
7848
7849#endif
c7ccde0f
AD		 7850 if (netif_running(netdev))
7851 ixgbe_up(adapter);
9a799d71
AK		 7852
7853 netif_device_attach(netdev);
9a799d71
AK		 7854}
7855
3646f0e5 7856static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 7857 .error_detected = ixgbe_io_error_detected,
7858 .slot_reset = ixgbe_io_slot_reset,
7859 .resume = ixgbe_io_resume,
7860};
7861
7862static struct pci_driver ixgbe_driver = {
7863 .name = ixgbe_driver_name,
7864 .id_table = ixgbe_pci_tbl,
7865 .probe = ixgbe_probe,
9f9a12f8 7866 .remove = ixgbe_remove,
9a799d71
AK		 7867#ifdef CONFIG_PM
7868 .suspend = ixgbe_suspend,
7869 .resume = ixgbe_resume,
7870#endif
7871 .shutdown = ixgbe_shutdown,
da36b647 7872 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 7873 .err_handler = &ixgbe_err_handler
7874};
7875
7876/**
7877 * ixgbe_init_module - Driver Registration Routine
7878 *
7879 * ixgbe_init_module is the first routine called when the driver is
7880 * loaded. All it does is register with the PCI subsystem.
7881 **/
7882static int __init ixgbe_init_module(void)
7883{
7884 int ret;
c7689578 7885 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7886 pr_info("%s\n", ixgbe_copyright);
9a799d71 7887
00949167
CS		 7888#ifdef CONFIG_DEBUG_FS
7889 ixgbe_dbg_init();
7890#endif /* CONFIG_DEBUG_FS */
7891
5dd2d332 7892#ifdef CONFIG_IXGBE_DCA
bd0362dd 7893 dca_register_notify(&dca_notifier);
bd0362dd 7894#endif
5dd2d332 7895
9a799d71
AK		 7896 ret = pci_register_driver(&ixgbe_driver);
7897 return ret;
7898}
b4617240 7899
9a799d71
AK		 7900module_init(ixgbe_init_module);
7901
7902/**
7903 * ixgbe_exit_module - Driver Exit Cleanup Routine
7904 *
7905 * ixgbe_exit_module is called just before the driver is removed
7906 * from memory.
7907 **/
7908static void __exit ixgbe_exit_module(void)
7909{
5dd2d332 7910#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7911 dca_unregister_notify(&dca_notifier);
7912#endif
9a799d71 7913 pci_unregister_driver(&ixgbe_driver);
00949167
CS		 7914
7915#ifdef CONFIG_DEBUG_FS
7916 ixgbe_dbg_exit();
7917#endif /* CONFIG_DEBUG_FS */
7918
1a51502b 7919 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7920}
bd0362dd 7921
5dd2d332 7922#ifdef CONFIG_IXGBE_DCA
bd0362dd 7923static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7924 void *p)
bd0362dd
JC		 7925{
7926 int ret_val;
7927
7928 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7929 __ixgbe_notify_dca);
bd0362dd
JC		 7930
7931 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7932}
b453368d 7933
5dd2d332 7934#endif /* CONFIG_IXGBE_DCA */
849c4542 7935
9a799d71
AK		 7936module_exit(ixgbe_exit_module);
7937
7938/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)