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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 58 | #ifdef IXGBE_FCOE |
ea81875a NP |
59 | char ixgbe_default_device_descr[] = |
60 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
61 | #else |
62 | static char ixgbe_default_device_descr[] = | |
63 | "Intel(R) 10 Gigabit Network Connection"; | |
64 | #endif | |
75e3d3c6 | 65 | #define MAJ 3 |
eef4560f DS |
66 | #define MIN 9 |
67 | #define BUILD 15 | |
75e3d3c6 | 68 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 69 | __stringify(BUILD) "-k" |
9c8eb720 | 70 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 71 | static const char ixgbe_copyright[] = |
94971820 | 72 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
73 | |
74 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 75 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 76 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 77 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
78 | }; |
79 | ||
80 | /* ixgbe_pci_tbl - PCI Device ID Table | |
81 | * | |
82 | * Wildcard entries (PCI_ANY_ID) should come last | |
83 | * Last entry must be all 0s | |
84 | * | |
85 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
86 | * Class, Class Mask, private data (not used) } | |
87 | */ | |
a3aa1884 | 88 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
9a799d71 AK |
117 | /* required last entry */ |
118 | {0, } | |
119 | }; | |
120 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
121 | ||
5dd2d332 | 122 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 123 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 124 | void *p); |
bd0362dd JC |
125 | static struct notifier_block dca_notifier = { |
126 | .notifier_call = ixgbe_notify_dca, | |
127 | .next = NULL, | |
128 | .priority = 0 | |
129 | }; | |
130 | #endif | |
131 | ||
1cdd1ec8 GR |
132 | #ifdef CONFIG_PCI_IOV |
133 | static unsigned int max_vfs; | |
134 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 135 | MODULE_PARM_DESC(max_vfs, |
6b42a9c5 | 136 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63"); |
1cdd1ec8 GR |
137 | #endif /* CONFIG_PCI_IOV */ |
138 | ||
8ef78adc PWJ |
139 | static unsigned int allow_unsupported_sfp; |
140 | module_param(allow_unsupported_sfp, uint, 0); | |
141 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
142 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
143 | ||
b3f4d599 | 144 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
145 | static int debug = -1; | |
146 | module_param(debug, int, 0); | |
147 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
148 | ||
9a799d71 AK |
149 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
150 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
151 | MODULE_LICENSE("GPL"); | |
152 | MODULE_VERSION(DRV_VERSION); | |
153 | ||
7086400d AD |
154 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
155 | { | |
156 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
157 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
158 | schedule_work(&adapter->service_task); | |
159 | } | |
160 | ||
161 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
162 | { | |
163 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
164 | ||
52f33af8 | 165 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
166 | smp_mb__before_clear_bit(); |
167 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
168 | } | |
169 | ||
dcd79aeb TI |
170 | struct ixgbe_reg_info { |
171 | u32 ofs; | |
172 | char *name; | |
173 | }; | |
174 | ||
175 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
176 | ||
177 | /* General Registers */ | |
178 | {IXGBE_CTRL, "CTRL"}, | |
179 | {IXGBE_STATUS, "STATUS"}, | |
180 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
181 | ||
182 | /* Interrupt Registers */ | |
183 | {IXGBE_EICR, "EICR"}, | |
184 | ||
185 | /* RX Registers */ | |
186 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
187 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
188 | {IXGBE_RDLEN(0), "RDLEN"}, | |
189 | {IXGBE_RDH(0), "RDH"}, | |
190 | {IXGBE_RDT(0), "RDT"}, | |
191 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
192 | {IXGBE_RDBAL(0), "RDBAL"}, | |
193 | {IXGBE_RDBAH(0), "RDBAH"}, | |
194 | ||
195 | /* TX Registers */ | |
196 | {IXGBE_TDBAL(0), "TDBAL"}, | |
197 | {IXGBE_TDBAH(0), "TDBAH"}, | |
198 | {IXGBE_TDLEN(0), "TDLEN"}, | |
199 | {IXGBE_TDH(0), "TDH"}, | |
200 | {IXGBE_TDT(0), "TDT"}, | |
201 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
202 | ||
203 | /* List Terminator */ | |
204 | {} | |
205 | }; | |
206 | ||
207 | ||
208 | /* | |
209 | * ixgbe_regdump - register printout routine | |
210 | */ | |
211 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
212 | { | |
213 | int i = 0, j = 0; | |
214 | char rname[16]; | |
215 | u32 regs[64]; | |
216 | ||
217 | switch (reginfo->ofs) { | |
218 | case IXGBE_SRRCTL(0): | |
219 | for (i = 0; i < 64; i++) | |
220 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
221 | break; | |
222 | case IXGBE_DCA_RXCTRL(0): | |
223 | for (i = 0; i < 64; i++) | |
224 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
225 | break; | |
226 | case IXGBE_RDLEN(0): | |
227 | for (i = 0; i < 64; i++) | |
228 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
229 | break; | |
230 | case IXGBE_RDH(0): | |
231 | for (i = 0; i < 64; i++) | |
232 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
233 | break; | |
234 | case IXGBE_RDT(0): | |
235 | for (i = 0; i < 64; i++) | |
236 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
237 | break; | |
238 | case IXGBE_RXDCTL(0): | |
239 | for (i = 0; i < 64; i++) | |
240 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
241 | break; | |
242 | case IXGBE_RDBAL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
245 | break; | |
246 | case IXGBE_RDBAH(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
249 | break; | |
250 | case IXGBE_TDBAL(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
253 | break; | |
254 | case IXGBE_TDBAH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
257 | break; | |
258 | case IXGBE_TDLEN(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
261 | break; | |
262 | case IXGBE_TDH(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
265 | break; | |
266 | case IXGBE_TDT(0): | |
267 | for (i = 0; i < 64; i++) | |
268 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
269 | break; | |
270 | case IXGBE_TXDCTL(0): | |
271 | for (i = 0; i < 64; i++) | |
272 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
273 | break; | |
274 | default: | |
c7689578 | 275 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
276 | IXGBE_READ_REG(hw, reginfo->ofs)); |
277 | return; | |
278 | } | |
279 | ||
280 | for (i = 0; i < 8; i++) { | |
281 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 282 | pr_err("%-15s", rname); |
dcd79aeb | 283 | for (j = 0; j < 8; j++) |
c7689578 JP |
284 | pr_cont(" %08x", regs[i*8+j]); |
285 | pr_cont("\n"); | |
dcd79aeb TI |
286 | } |
287 | ||
288 | } | |
289 | ||
290 | /* | |
291 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
292 | */ | |
293 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
294 | { | |
295 | struct net_device *netdev = adapter->netdev; | |
296 | struct ixgbe_hw *hw = &adapter->hw; | |
297 | struct ixgbe_reg_info *reginfo; | |
298 | int n = 0; | |
299 | struct ixgbe_ring *tx_ring; | |
729739b7 | 300 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
301 | union ixgbe_adv_tx_desc *tx_desc; |
302 | struct my_u0 { u64 a; u64 b; } *u0; | |
303 | struct ixgbe_ring *rx_ring; | |
304 | union ixgbe_adv_rx_desc *rx_desc; | |
305 | struct ixgbe_rx_buffer *rx_buffer_info; | |
306 | u32 staterr; | |
307 | int i = 0; | |
308 | ||
309 | if (!netif_msg_hw(adapter)) | |
310 | return; | |
311 | ||
312 | /* Print netdevice Info */ | |
313 | if (netdev) { | |
314 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 315 | pr_info("Device Name state " |
dcd79aeb | 316 | "trans_start last_rx\n"); |
c7689578 JP |
317 | pr_info("%-15s %016lX %016lX %016lX\n", |
318 | netdev->name, | |
319 | netdev->state, | |
320 | netdev->trans_start, | |
321 | netdev->last_rx); | |
dcd79aeb TI |
322 | } |
323 | ||
324 | /* Print Registers */ | |
325 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 326 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
327 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
328 | reginfo->name; reginfo++) { | |
329 | ixgbe_regdump(hw, reginfo); | |
330 | } | |
331 | ||
332 | /* Print TX Ring Summary */ | |
333 | if (!netdev || !netif_running(netdev)) | |
334 | goto exit; | |
335 | ||
336 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 337 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
338 | for (n = 0; n < adapter->num_tx_queues; n++) { |
339 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 340 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
d3d00239 | 341 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb | 342 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
343 | (u64)dma_unmap_addr(tx_buffer, dma), |
344 | dma_unmap_len(tx_buffer, len), | |
345 | tx_buffer->next_to_watch, | |
346 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
347 | } |
348 | ||
349 | /* Print TX Rings */ | |
350 | if (!netif_msg_tx_done(adapter)) | |
351 | goto rx_ring_summary; | |
352 | ||
353 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
354 | ||
355 | /* Transmit Descriptor Formats | |
356 | * | |
357 | * Advanced Transmit Descriptor | |
358 | * +--------------------------------------------------------------+ | |
359 | * 0 | Buffer Address [63:0] | | |
360 | * +--------------------------------------------------------------+ | |
361 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
362 | * +--------------------------------------------------------------+ | |
363 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
364 | */ | |
365 | ||
366 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
367 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
368 | pr_info("------------------------------------\n"); |
369 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
370 | pr_info("------------------------------------\n"); | |
371 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
372 | "[PlPOIdStDDt Ln] [bi->dma ] " |
373 | "leng ntw timestamp bi->skb\n"); | |
374 | ||
375 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 376 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 377 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 378 | u0 = (struct my_u0 *)tx_desc; |
c7689578 | 379 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 380 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
381 | le64_to_cpu(u0->a), |
382 | le64_to_cpu(u0->b), | |
729739b7 AD |
383 | (u64)dma_unmap_addr(tx_buffer, dma), |
384 | dma_unmap_len(tx_buffer, len), | |
385 | tx_buffer->next_to_watch, | |
386 | (u64)tx_buffer->time_stamp, | |
387 | tx_buffer->skb); | |
dcd79aeb TI |
388 | if (i == tx_ring->next_to_use && |
389 | i == tx_ring->next_to_clean) | |
c7689578 | 390 | pr_cont(" NTC/U\n"); |
dcd79aeb | 391 | else if (i == tx_ring->next_to_use) |
c7689578 | 392 | pr_cont(" NTU\n"); |
dcd79aeb | 393 | else if (i == tx_ring->next_to_clean) |
c7689578 | 394 | pr_cont(" NTC\n"); |
dcd79aeb | 395 | else |
c7689578 | 396 | pr_cont("\n"); |
dcd79aeb TI |
397 | |
398 | if (netif_msg_pktdata(adapter) && | |
729739b7 | 399 | dma_unmap_len(tx_buffer, len) != 0) |
dcd79aeb TI |
400 | print_hex_dump(KERN_INFO, "", |
401 | DUMP_PREFIX_ADDRESS, 16, 1, | |
729739b7 AD |
402 | phys_to_virt(dma_unmap_addr(tx_buffer, |
403 | dma)), | |
404 | dma_unmap_len(tx_buffer, len), | |
405 | true); | |
dcd79aeb TI |
406 | } |
407 | } | |
408 | ||
409 | /* Print RX Rings Summary */ | |
410 | rx_ring_summary: | |
411 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 412 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
413 | for (n = 0; n < adapter->num_rx_queues; n++) { |
414 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
415 | pr_info("%5d %5X %5X\n", |
416 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
417 | } |
418 | ||
419 | /* Print RX Rings */ | |
420 | if (!netif_msg_rx_status(adapter)) | |
421 | goto exit; | |
422 | ||
423 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
424 | ||
425 | /* Advanced Receive Descriptor (Read) Format | |
426 | * 63 1 0 | |
427 | * +-----------------------------------------------------+ | |
428 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
429 | * +----------------------------------------------+------+ | |
430 | * 8 | Header Buffer Address [63:1] | DD | | |
431 | * +-----------------------------------------------------+ | |
432 | * | |
433 | * | |
434 | * Advanced Receive Descriptor (Write-Back) Format | |
435 | * | |
436 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
437 | * +------------------------------------------------------+ | |
438 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
439 | * | Checksum Ident | | | | Type | Type | | |
440 | * +------------------------------------------------------+ | |
441 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
442 | * +------------------------------------------------------+ | |
443 | * 63 48 47 32 31 20 19 0 | |
444 | */ | |
445 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
446 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
447 | pr_info("------------------------------------\n"); |
448 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
449 | pr_info("------------------------------------\n"); | |
450 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
451 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
452 | "<-- Adv Rx Read format\n"); | |
c7689578 | 453 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
454 | "[vl er S cks ln] ---------------- [bi->skb] " |
455 | "<-- Adv Rx Write-Back format\n"); | |
456 | ||
457 | for (i = 0; i < rx_ring->count; i++) { | |
458 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 459 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
460 | u0 = (struct my_u0 *)rx_desc; |
461 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
462 | if (staterr & IXGBE_RXD_STAT_DD) { | |
463 | /* Descriptor Done */ | |
c7689578 | 464 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
465 | "%016llX ---------------- %p", i, |
466 | le64_to_cpu(u0->a), | |
467 | le64_to_cpu(u0->b), | |
468 | rx_buffer_info->skb); | |
469 | } else { | |
c7689578 | 470 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
471 | "%016llX %016llX %p", i, |
472 | le64_to_cpu(u0->a), | |
473 | le64_to_cpu(u0->b), | |
474 | (u64)rx_buffer_info->dma, | |
475 | rx_buffer_info->skb); | |
476 | ||
477 | if (netif_msg_pktdata(adapter)) { | |
478 | print_hex_dump(KERN_INFO, "", | |
479 | DUMP_PREFIX_ADDRESS, 16, 1, | |
480 | phys_to_virt(rx_buffer_info->dma), | |
f800326d | 481 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
482 | } |
483 | } | |
484 | ||
485 | if (i == rx_ring->next_to_use) | |
c7689578 | 486 | pr_cont(" NTU\n"); |
dcd79aeb | 487 | else if (i == rx_ring->next_to_clean) |
c7689578 | 488 | pr_cont(" NTC\n"); |
dcd79aeb | 489 | else |
c7689578 | 490 | pr_cont("\n"); |
dcd79aeb TI |
491 | |
492 | } | |
493 | } | |
494 | ||
495 | exit: | |
496 | return; | |
497 | } | |
498 | ||
5eba3699 AV |
499 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
500 | { | |
501 | u32 ctrl_ext; | |
502 | ||
503 | /* Let firmware take over control of h/w */ | |
504 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
505 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 506 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
507 | } |
508 | ||
509 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
510 | { | |
511 | u32 ctrl_ext; | |
512 | ||
513 | /* Let firmware know the driver has taken over */ | |
514 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 516 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 517 | } |
9a799d71 | 518 | |
49ce9c2c | 519 | /** |
e8e26350 PW |
520 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors |
521 | * @adapter: pointer to adapter struct | |
522 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
523 | * @queue: queue to map the corresponding interrupt to | |
524 | * @msix_vector: the vector to map to the corresponding queue | |
525 | * | |
526 | */ | |
527 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 528 | u8 queue, u8 msix_vector) |
9a799d71 AK |
529 | { |
530 | u32 ivar, index; | |
e8e26350 PW |
531 | struct ixgbe_hw *hw = &adapter->hw; |
532 | switch (hw->mac.type) { | |
533 | case ixgbe_mac_82598EB: | |
534 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
535 | if (direction == -1) | |
536 | direction = 0; | |
537 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
538 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
539 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
540 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
541 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
542 | break; | |
543 | case ixgbe_mac_82599EB: | |
b93a2226 | 544 | case ixgbe_mac_X540: |
e8e26350 PW |
545 | if (direction == -1) { |
546 | /* other causes */ | |
547 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
548 | index = ((queue & 1) * 8); | |
549 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
550 | ivar &= ~(0xFF << index); | |
551 | ivar |= (msix_vector << index); | |
552 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
553 | break; | |
554 | } else { | |
555 | /* tx or rx causes */ | |
556 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
557 | index = ((16 * (queue & 1)) + (8 * direction)); | |
558 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
559 | ivar &= ~(0xFF << index); | |
560 | ivar |= (msix_vector << index); | |
561 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
562 | break; | |
563 | } | |
564 | default: | |
565 | break; | |
566 | } | |
9a799d71 AK |
567 | } |
568 | ||
fe49f04a | 569 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 570 | u64 qmask) |
fe49f04a AD |
571 | { |
572 | u32 mask; | |
573 | ||
bd508178 AD |
574 | switch (adapter->hw.mac.type) { |
575 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
576 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
577 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
578 | break; |
579 | case ixgbe_mac_82599EB: | |
b93a2226 | 580 | case ixgbe_mac_X540: |
fe49f04a AD |
581 | mask = (qmask & 0xFFFFFFFF); |
582 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
583 | mask = (qmask >> 32); | |
584 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
585 | break; |
586 | default: | |
587 | break; | |
fe49f04a AD |
588 | } |
589 | } | |
590 | ||
729739b7 AD |
591 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
592 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 593 | { |
729739b7 AD |
594 | if (tx_buffer->skb) { |
595 | dev_kfree_skb_any(tx_buffer->skb); | |
596 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 597 | dma_unmap_single(ring->dev, |
729739b7 AD |
598 | dma_unmap_addr(tx_buffer, dma), |
599 | dma_unmap_len(tx_buffer, len), | |
600 | DMA_TO_DEVICE); | |
601 | } else if (dma_unmap_len(tx_buffer, len)) { | |
602 | dma_unmap_page(ring->dev, | |
603 | dma_unmap_addr(tx_buffer, dma), | |
604 | dma_unmap_len(tx_buffer, len), | |
605 | DMA_TO_DEVICE); | |
e5a43549 | 606 | } |
729739b7 AD |
607 | tx_buffer->next_to_watch = NULL; |
608 | tx_buffer->skb = NULL; | |
609 | dma_unmap_len_set(tx_buffer, len, 0); | |
610 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
611 | } |
612 | ||
943561d3 | 613 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
614 | { |
615 | struct ixgbe_hw *hw = &adapter->hw; | |
616 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 617 | int i; |
943561d3 | 618 | u32 data; |
c84d324c | 619 | |
943561d3 AD |
620 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
621 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
622 | return; | |
c84d324c | 623 | |
943561d3 AD |
624 | switch (hw->mac.type) { |
625 | case ixgbe_mac_82598EB: | |
626 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
627 | break; | |
628 | default: | |
629 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
630 | } | |
631 | hwstats->lxoffrxc += data; | |
c84d324c | 632 | |
943561d3 AD |
633 | /* refill credits (no tx hang) if we received xoff */ |
634 | if (!data) | |
c84d324c | 635 | return; |
943561d3 AD |
636 | |
637 | for (i = 0; i < adapter->num_tx_queues; i++) | |
638 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
639 | &adapter->tx_ring[i]->state); | |
640 | } | |
641 | ||
642 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
643 | { | |
644 | struct ixgbe_hw *hw = &adapter->hw; | |
645 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
646 | u32 xoff[8] = {0}; | |
647 | int i; | |
648 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
649 | ||
650 | if (adapter->ixgbe_ieee_pfc) | |
651 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
652 | ||
653 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
654 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 655 | return; |
943561d3 | 656 | } |
c84d324c JF |
657 | |
658 | /* update stats for each tc, only valid with PFC enabled */ | |
659 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
660 | switch (hw->mac.type) { | |
661 | case ixgbe_mac_82598EB: | |
662 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 663 | break; |
c84d324c JF |
664 | default: |
665 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 666 | } |
c84d324c JF |
667 | hwstats->pxoffrxc[i] += xoff[i]; |
668 | } | |
669 | ||
670 | /* disarm tx queues that have received xoff frames */ | |
671 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
672 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 673 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
674 | |
675 | if (xoff[tc]) | |
676 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 677 | } |
26f23d82 YZ |
678 | } |
679 | ||
c84d324c | 680 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 681 | { |
7d7ce682 | 682 | return ring->stats.packets; |
c84d324c JF |
683 | } |
684 | ||
685 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
686 | { | |
687 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 688 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 689 | |
c84d324c JF |
690 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
691 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
692 | ||
693 | if (head != tail) | |
694 | return (head < tail) ? | |
695 | tail - head : (tail + ring->count - head); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
701 | { | |
702 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
703 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
704 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
705 | bool ret = false; | |
706 | ||
7d637bcc | 707 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
708 | |
709 | /* | |
710 | * Check for a hung queue, but be thorough. This verifies | |
711 | * that a transmit has been completed since the previous | |
712 | * check AND there is at least one packet pending. The | |
713 | * ARMED bit is set to indicate a potential hang. The | |
714 | * bit is cleared if a pause frame is received to remove | |
715 | * false hang detection due to PFC or 802.3x frames. By | |
716 | * requiring this to fail twice we avoid races with | |
717 | * pfc clearing the ARMED bit and conditions where we | |
718 | * run the check_tx_hang logic with a transmit completion | |
719 | * pending but without time to complete it yet. | |
720 | */ | |
721 | if ((tx_done_old == tx_done) && tx_pending) { | |
722 | /* make sure it is true for two checks in a row */ | |
723 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
724 | &tx_ring->state); | |
725 | } else { | |
726 | /* update completed stats and continue */ | |
727 | tx_ring->tx_stats.tx_done_old = tx_done; | |
728 | /* reset the countdown */ | |
729 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
730 | } |
731 | ||
c84d324c | 732 | return ret; |
9a799d71 AK |
733 | } |
734 | ||
c83c6cbd AD |
735 | /** |
736 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
737 | * @adapter: driver private struct | |
738 | **/ | |
739 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
740 | { | |
741 | ||
742 | /* Do the reset outside of interrupt context */ | |
743 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
744 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
745 | ixgbe_service_event_schedule(adapter); | |
746 | } | |
747 | } | |
e01c31a5 | 748 | |
9a799d71 AK |
749 | /** |
750 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 751 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 752 | * @tx_ring: tx ring to clean |
9a799d71 | 753 | **/ |
fe49f04a | 754 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 755 | struct ixgbe_ring *tx_ring) |
9a799d71 | 756 | { |
fe49f04a | 757 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
758 | struct ixgbe_tx_buffer *tx_buffer; |
759 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 760 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 761 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
762 | unsigned int i = tx_ring->next_to_clean; |
763 | ||
764 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
765 | return true; | |
9a799d71 | 766 | |
d3d00239 | 767 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 768 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 769 | i -= tx_ring->count; |
12207e49 | 770 | |
729739b7 | 771 | do { |
d3d00239 AD |
772 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
773 | ||
774 | /* if next_to_watch is not set then there is no work pending */ | |
775 | if (!eop_desc) | |
776 | break; | |
777 | ||
7f83a9e6 AD |
778 | /* prevent any other reads prior to eop_desc */ |
779 | rmb(); | |
780 | ||
d3d00239 AD |
781 | /* if DD is not set pending work has not been completed */ |
782 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
783 | break; | |
8ad494b0 | 784 | |
d3d00239 AD |
785 | /* clear next_to_watch to prevent false hangs */ |
786 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 787 | |
091a6246 AD |
788 | /* update the statistics for this packet */ |
789 | total_bytes += tx_buffer->bytecount; | |
790 | total_packets += tx_buffer->gso_segs; | |
791 | ||
3a6a4eda | 792 | #ifdef CONFIG_IXGBE_PTP |
0ede4a60 JK |
793 | if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP)) |
794 | ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb); | |
3a6a4eda | 795 | #endif |
0ede4a60 | 796 | |
fd0db0ed AD |
797 | /* free the skb */ |
798 | dev_kfree_skb_any(tx_buffer->skb); | |
799 | ||
729739b7 AD |
800 | /* unmap skb header data */ |
801 | dma_unmap_single(tx_ring->dev, | |
802 | dma_unmap_addr(tx_buffer, dma), | |
803 | dma_unmap_len(tx_buffer, len), | |
804 | DMA_TO_DEVICE); | |
805 | ||
fd0db0ed AD |
806 | /* clear tx_buffer data */ |
807 | tx_buffer->skb = NULL; | |
729739b7 | 808 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 809 | |
729739b7 AD |
810 | /* unmap remaining buffers */ |
811 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
812 | tx_buffer++; |
813 | tx_desc++; | |
8ad494b0 | 814 | i++; |
729739b7 AD |
815 | if (unlikely(!i)) { |
816 | i -= tx_ring->count; | |
d3d00239 | 817 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 818 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 819 | } |
e01c31a5 | 820 | |
729739b7 AD |
821 | /* unmap any remaining paged data */ |
822 | if (dma_unmap_len(tx_buffer, len)) { | |
823 | dma_unmap_page(tx_ring->dev, | |
824 | dma_unmap_addr(tx_buffer, dma), | |
825 | dma_unmap_len(tx_buffer, len), | |
826 | DMA_TO_DEVICE); | |
827 | dma_unmap_len_set(tx_buffer, len, 0); | |
828 | } | |
829 | } | |
830 | ||
831 | /* move us one more past the eop_desc for start of next pkt */ | |
832 | tx_buffer++; | |
833 | tx_desc++; | |
834 | i++; | |
835 | if (unlikely(!i)) { | |
836 | i -= tx_ring->count; | |
837 | tx_buffer = tx_ring->tx_buffer_info; | |
838 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
839 | } | |
840 | ||
841 | /* issue prefetch for next Tx descriptor */ | |
842 | prefetch(tx_desc); | |
12207e49 | 843 | |
729739b7 AD |
844 | /* update budget accounting */ |
845 | budget--; | |
846 | } while (likely(budget)); | |
847 | ||
848 | i += tx_ring->count; | |
9a799d71 | 849 | tx_ring->next_to_clean = i; |
d3d00239 | 850 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 851 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 852 | tx_ring->stats.packets += total_packets; |
d3d00239 | 853 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
854 | q_vector->tx.total_bytes += total_bytes; |
855 | q_vector->tx.total_packets += total_packets; | |
b953799e | 856 | |
c84d324c JF |
857 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
858 | /* schedule immediate reset if we believe we hung */ | |
859 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
860 | e_err(drv, "Detected Tx Unit Hang\n" |
861 | " Tx Queue <%d>\n" | |
862 | " TDH, TDT <%x>, <%x>\n" | |
863 | " next_to_use <%x>\n" | |
864 | " next_to_clean <%x>\n" | |
865 | "tx_buffer_info[next_to_clean]\n" | |
866 | " time_stamp <%lx>\n" | |
867 | " jiffies <%lx>\n", | |
868 | tx_ring->queue_index, | |
869 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
870 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
871 | tx_ring->next_to_use, i, |
872 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
873 | |
874 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
875 | ||
876 | e_info(probe, | |
877 | "tx hang %d detected on queue %d, resetting adapter\n", | |
878 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
879 | ||
b953799e | 880 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 881 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
882 | |
883 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 884 | return true; |
b953799e | 885 | } |
9a799d71 | 886 | |
b2d96e0a AD |
887 | netdev_tx_completed_queue(txring_txq(tx_ring), |
888 | total_packets, total_bytes); | |
889 | ||
e092be60 | 890 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 891 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 892 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
893 | /* Make sure that anybody stopping the queue after this |
894 | * sees the new next_to_clean. | |
895 | */ | |
896 | smp_mb(); | |
729739b7 AD |
897 | if (__netif_subqueue_stopped(tx_ring->netdev, |
898 | tx_ring->queue_index) | |
899 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
900 | netif_wake_subqueue(tx_ring->netdev, | |
901 | tx_ring->queue_index); | |
5b7da515 | 902 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 903 | } |
e092be60 | 904 | } |
9a799d71 | 905 | |
59224555 | 906 | return !!budget; |
9a799d71 AK |
907 | } |
908 | ||
5dd2d332 | 909 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
910 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
911 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 912 | int cpu) |
bd0362dd | 913 | { |
33cf09c9 | 914 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
915 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
916 | u16 reg_offset; | |
33cf09c9 | 917 | |
33cf09c9 AD |
918 | switch (hw->mac.type) { |
919 | case ixgbe_mac_82598EB: | |
bdda1a61 | 920 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
921 | break; |
922 | case ixgbe_mac_82599EB: | |
b93a2226 | 923 | case ixgbe_mac_X540: |
bdda1a61 AD |
924 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
925 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
926 | break; |
927 | default: | |
bdda1a61 AD |
928 | /* for unknown hardware do not write register */ |
929 | return; | |
bd0362dd | 930 | } |
bdda1a61 AD |
931 | |
932 | /* | |
933 | * We can enable relaxed ordering for reads, but not writes when | |
934 | * DCA is enabled. This is due to a known issue in some chipsets | |
935 | * which will cause the DCA tag to be cleared. | |
936 | */ | |
937 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
938 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
939 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
940 | ||
941 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
942 | } |
943 | ||
bdda1a61 AD |
944 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
945 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 946 | int cpu) |
bd0362dd | 947 | { |
33cf09c9 | 948 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
949 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
950 | u8 reg_idx = rx_ring->reg_idx; | |
951 | ||
33cf09c9 AD |
952 | |
953 | switch (hw->mac.type) { | |
33cf09c9 | 954 | case ixgbe_mac_82599EB: |
b93a2226 | 955 | case ixgbe_mac_X540: |
bdda1a61 | 956 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
957 | break; |
958 | default: | |
959 | break; | |
960 | } | |
bdda1a61 AD |
961 | |
962 | /* | |
963 | * We can enable relaxed ordering for reads, but not writes when | |
964 | * DCA is enabled. This is due to a known issue in some chipsets | |
965 | * which will cause the DCA tag to be cleared. | |
966 | */ | |
967 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
968 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | | |
969 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; | |
970 | ||
971 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
972 | } |
973 | ||
974 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
975 | { | |
976 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 977 | struct ixgbe_ring *ring; |
bd0362dd | 978 | int cpu = get_cpu(); |
bd0362dd | 979 | |
33cf09c9 AD |
980 | if (q_vector->cpu == cpu) |
981 | goto out_no_update; | |
982 | ||
a557928e | 983 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 984 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 985 | |
a557928e | 986 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 987 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
988 | |
989 | q_vector->cpu = cpu; | |
990 | out_no_update: | |
bd0362dd JC |
991 | put_cpu(); |
992 | } | |
993 | ||
994 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
995 | { | |
996 | int i; | |
997 | ||
998 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
999 | return; | |
1000 | ||
e35ec126 AD |
1001 | /* always use CB2 mode, difference is masked in the CB driver */ |
1002 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
1003 | ||
49c7ffbe | 1004 | for (i = 0; i < adapter->num_q_vectors; i++) { |
33cf09c9 AD |
1005 | adapter->q_vector[i]->cpu = -1; |
1006 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1007 | } |
1008 | } | |
1009 | ||
1010 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1011 | { | |
c60fbb00 | 1012 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1013 | unsigned long event = *(unsigned long *)data; |
1014 | ||
2a72c31e | 1015 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1016 | return 0; |
1017 | ||
bd0362dd JC |
1018 | switch (event) { |
1019 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1020 | /* if we're already enabled, don't do it again */ |
1021 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1022 | break; | |
652f093f | 1023 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1024 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1025 | ixgbe_setup_dca(adapter); |
1026 | break; | |
1027 | } | |
1028 | /* Fall Through since DCA is disabled. */ | |
1029 | case DCA_PROVIDER_REMOVE: | |
1030 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1031 | dca_remove_requester(dev); | |
1032 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1033 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1034 | } | |
1035 | break; | |
1036 | } | |
1037 | ||
652f093f | 1038 | return 0; |
bd0362dd | 1039 | } |
67a74ee2 | 1040 | |
bdda1a61 | 1041 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
1042 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1043 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1044 | struct sk_buff *skb) |
1045 | { | |
8a0da21b AD |
1046 | if (ring->netdev->features & NETIF_F_RXHASH) |
1047 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
1048 | } |
1049 | ||
f800326d | 1050 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1051 | /** |
1052 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
57efd44c | 1053 | * @ring: structure containing ring specific data |
ff886dfc AD |
1054 | * @rx_desc: advanced rx descriptor |
1055 | * | |
1056 | * Returns : true if it is FCoE pkt | |
1057 | */ | |
57efd44c | 1058 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, |
ff886dfc AD |
1059 | union ixgbe_adv_rx_desc *rx_desc) |
1060 | { | |
1061 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1062 | ||
57efd44c | 1063 | return test_bit(__IXGBE_RX_FCOE, &ring->state) && |
ff886dfc AD |
1064 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == |
1065 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1066 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1067 | } | |
1068 | ||
f800326d | 1069 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1070 | /** |
1071 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1072 | * @ring: structure containing ring specific data |
1073 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1074 | * @skb: skb currently being received and modified |
1075 | **/ | |
8a0da21b | 1076 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1077 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1078 | struct sk_buff *skb) |
9a799d71 | 1079 | { |
8a0da21b | 1080 | skb_checksum_none_assert(skb); |
9a799d71 | 1081 | |
712744be | 1082 | /* Rx csum disabled */ |
8a0da21b | 1083 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1084 | return; |
e59bd25d AV |
1085 | |
1086 | /* if IP and error */ | |
f56e0cb1 AD |
1087 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1088 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1089 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1090 | return; |
1091 | } | |
e59bd25d | 1092 | |
f56e0cb1 | 1093 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1094 | return; |
1095 | ||
f56e0cb1 | 1096 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1097 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1098 | |
1099 | /* | |
1100 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1101 | * checksum errors. | |
1102 | */ | |
8a0da21b AD |
1103 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1104 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1105 | return; |
1106 | ||
8a0da21b | 1107 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1108 | return; |
1109 | } | |
1110 | ||
9a799d71 | 1111 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1112 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1113 | } |
1114 | ||
84ea2591 | 1115 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1116 | { |
f56e0cb1 | 1117 | rx_ring->next_to_use = val; |
f800326d AD |
1118 | |
1119 | /* update next to alloc since we have filled the ring */ | |
1120 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1121 | /* |
1122 | * Force memory writes to complete before letting h/w | |
1123 | * know there are new descriptors to fetch. (Only | |
1124 | * applicable for weak-ordered memory model archs, | |
1125 | * such as IA-64). | |
1126 | */ | |
1127 | wmb(); | |
84ea2591 | 1128 | writel(val, rx_ring->tail); |
e8e26350 PW |
1129 | } |
1130 | ||
f990b79b AD |
1131 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1132 | struct ixgbe_rx_buffer *bi) | |
1133 | { | |
1134 | struct page *page = bi->page; | |
f800326d | 1135 | dma_addr_t dma = bi->dma; |
f990b79b | 1136 | |
f800326d AD |
1137 | /* since we are recycling buffers we should seldom need to alloc */ |
1138 | if (likely(dma)) | |
f990b79b AD |
1139 | return true; |
1140 | ||
f800326d AD |
1141 | /* alloc new page for storage */ |
1142 | if (likely(!page)) { | |
8633c084 | 1143 | page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP, |
f800326d | 1144 | ixgbe_rx_pg_order(rx_ring)); |
f990b79b AD |
1145 | if (unlikely(!page)) { |
1146 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1147 | return false; | |
1148 | } | |
f800326d | 1149 | bi->page = page; |
f990b79b AD |
1150 | } |
1151 | ||
f800326d AD |
1152 | /* map page for use */ |
1153 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1154 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1155 | ||
1156 | /* | |
1157 | * if mapping failed free memory back to system since | |
1158 | * there isn't much point in holding memory we can't use | |
1159 | */ | |
1160 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1161 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f800326d | 1162 | bi->page = NULL; |
f990b79b | 1163 | |
f990b79b AD |
1164 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1165 | return false; | |
1166 | } | |
1167 | ||
f800326d AD |
1168 | bi->dma = dma; |
1169 | bi->page_offset ^= ixgbe_rx_bufsz(rx_ring); | |
1170 | ||
f990b79b AD |
1171 | return true; |
1172 | } | |
1173 | ||
9a799d71 | 1174 | /** |
f990b79b | 1175 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1176 | * @rx_ring: ring to place buffers on |
1177 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1178 | **/ |
fc77dc3c | 1179 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1180 | { |
9a799d71 | 1181 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1182 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1183 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1184 | |
f800326d AD |
1185 | /* nothing to do */ |
1186 | if (!cleaned_count) | |
fc77dc3c AD |
1187 | return; |
1188 | ||
e4f74028 | 1189 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1190 | bi = &rx_ring->rx_buffer_info[i]; |
1191 | i -= rx_ring->count; | |
9a799d71 | 1192 | |
f800326d AD |
1193 | do { |
1194 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1195 | break; |
d5f398ed | 1196 | |
f800326d AD |
1197 | /* |
1198 | * Refresh the desc even if buffer_addrs didn't change | |
1199 | * because each write-back erases this info. | |
1200 | */ | |
1201 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1202 | |
f990b79b AD |
1203 | rx_desc++; |
1204 | bi++; | |
9a799d71 | 1205 | i++; |
f990b79b | 1206 | if (unlikely(!i)) { |
e4f74028 | 1207 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1208 | bi = rx_ring->rx_buffer_info; |
1209 | i -= rx_ring->count; | |
1210 | } | |
1211 | ||
1212 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1213 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1214 | |
1215 | cleaned_count--; | |
1216 | } while (cleaned_count); | |
7c6e0a43 | 1217 | |
f990b79b AD |
1218 | i += rx_ring->count; |
1219 | ||
f56e0cb1 | 1220 | if (rx_ring->next_to_use != i) |
84ea2591 | 1221 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1222 | } |
1223 | ||
1d2024f6 AD |
1224 | /** |
1225 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1226 | * @data: pointer to the start of the headers | |
1227 | * @max_len: total length of section to find headers in | |
1228 | * | |
1229 | * This function is meant to determine the length of headers that will | |
1230 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1231 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1232 | * packets so that we can do basic things like calculating the gso_size | |
1233 | * based on the average data per packet. | |
1234 | **/ | |
1235 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1236 | unsigned int max_len) | |
1237 | { | |
1238 | union { | |
1239 | unsigned char *network; | |
1240 | /* l2 headers */ | |
1241 | struct ethhdr *eth; | |
1242 | struct vlan_hdr *vlan; | |
1243 | /* l3 headers */ | |
1244 | struct iphdr *ipv4; | |
1245 | } hdr; | |
1246 | __be16 protocol; | |
1247 | u8 nexthdr = 0; /* default to not TCP */ | |
1248 | u8 hlen; | |
1249 | ||
1250 | /* this should never happen, but better safe than sorry */ | |
1251 | if (max_len < ETH_HLEN) | |
1252 | return max_len; | |
1253 | ||
1254 | /* initialize network frame pointer */ | |
1255 | hdr.network = data; | |
1256 | ||
1257 | /* set first protocol and move network header forward */ | |
1258 | protocol = hdr.eth->h_proto; | |
1259 | hdr.network += ETH_HLEN; | |
1260 | ||
1261 | /* handle any vlan tag if present */ | |
1262 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1263 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1264 | return max_len; | |
1265 | ||
1266 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1267 | hdr.network += VLAN_HLEN; | |
1268 | } | |
1269 | ||
1270 | /* handle L3 protocols */ | |
1271 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1272 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1273 | return max_len; | |
1274 | ||
1275 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1276 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1277 | ||
1278 | /* verify hlen meets minimum size requirements */ | |
1279 | if (hlen < sizeof(struct iphdr)) | |
1280 | return hdr.network - data; | |
1281 | ||
1282 | /* record next protocol */ | |
1283 | nexthdr = hdr.ipv4->protocol; | |
1284 | hdr.network += hlen; | |
f800326d | 1285 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1286 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1287 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1288 | return max_len; | |
1289 | hdr.network += FCOE_HEADER_LEN; | |
1290 | #endif | |
1291 | } else { | |
1292 | return hdr.network - data; | |
1293 | } | |
1294 | ||
1295 | /* finally sort out TCP */ | |
1296 | if (nexthdr == IPPROTO_TCP) { | |
1297 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1298 | return max_len; | |
1299 | ||
1300 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1301 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1302 | ||
1303 | /* verify hlen meets minimum size requirements */ | |
1304 | if (hlen < sizeof(struct tcphdr)) | |
1305 | return hdr.network - data; | |
1306 | ||
1307 | hdr.network += hlen; | |
1308 | } | |
1309 | ||
1310 | /* | |
1311 | * If everything has gone correctly hdr.network should be the | |
1312 | * data section of the packet and will be the end of the header. | |
1313 | * If not then it probably represents the end of the last recognized | |
1314 | * header. | |
1315 | */ | |
1316 | if ((hdr.network - data) < max_len) | |
1317 | return hdr.network - data; | |
1318 | else | |
1319 | return max_len; | |
1320 | } | |
1321 | ||
4c1975d7 AD |
1322 | static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring, |
1323 | union ixgbe_adv_rx_desc *rx_desc, | |
1324 | struct sk_buff *skb) | |
aa80175a | 1325 | { |
4c1975d7 AD |
1326 | __le32 rsc_enabled; |
1327 | u32 rsc_cnt; | |
1328 | ||
1329 | if (!ring_is_rsc_enabled(rx_ring)) | |
1330 | return; | |
1331 | ||
1332 | rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1333 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1334 | ||
1335 | /* If this is an RSC frame rsc_cnt should be non-zero */ | |
1336 | if (!rsc_enabled) | |
1337 | return; | |
1338 | ||
1339 | rsc_cnt = le32_to_cpu(rsc_enabled); | |
1340 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1341 | ||
1342 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
aa80175a | 1343 | } |
43634e82 | 1344 | |
1d2024f6 AD |
1345 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1346 | struct sk_buff *skb) | |
1347 | { | |
f800326d | 1348 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1349 | |
1350 | /* set gso_size to avoid messing up TCP MSS */ | |
1351 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1352 | IXGBE_CB(skb)->append_cnt); | |
1353 | } | |
1354 | ||
1355 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1356 | struct sk_buff *skb) | |
1357 | { | |
1358 | /* if append_cnt is 0 then frame is not RSC */ | |
1359 | if (!IXGBE_CB(skb)->append_cnt) | |
1360 | return; | |
1361 | ||
1362 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1363 | rx_ring->rx_stats.rsc_flush++; | |
1364 | ||
1365 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1366 | ||
1367 | /* gso_size is computed using append_cnt so always clear it last */ | |
1368 | IXGBE_CB(skb)->append_cnt = 0; | |
1369 | } | |
1370 | ||
8a0da21b AD |
1371 | /** |
1372 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1373 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1374 | * @rx_desc: pointer to the EOP Rx descriptor | |
1375 | * @skb: pointer to current skb being populated | |
f8212f97 | 1376 | * |
8a0da21b AD |
1377 | * This function checks the ring, descriptor, and packet information in |
1378 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1379 | * other fields within the skb. | |
f8212f97 | 1380 | **/ |
8a0da21b AD |
1381 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1382 | union ixgbe_adv_rx_desc *rx_desc, | |
1383 | struct sk_buff *skb) | |
f8212f97 | 1384 | { |
43e95f11 JF |
1385 | struct net_device *dev = rx_ring->netdev; |
1386 | ||
8a0da21b AD |
1387 | ixgbe_update_rsc_stats(rx_ring, skb); |
1388 | ||
1389 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1390 | |
8a0da21b AD |
1391 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1392 | ||
3a6a4eda | 1393 | #ifdef CONFIG_IXGBE_PTP |
1d1a79b5 | 1394 | ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); |
3a6a4eda JK |
1395 | #endif |
1396 | ||
43e95f11 JF |
1397 | if ((dev->features & NETIF_F_HW_VLAN_RX) && |
1398 | ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
8a0da21b AD |
1399 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
1400 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1401 | } |
1402 | ||
8a0da21b | 1403 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1404 | |
43e95f11 | 1405 | skb->protocol = eth_type_trans(skb, dev); |
f8212f97 AD |
1406 | } |
1407 | ||
8a0da21b AD |
1408 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1409 | struct sk_buff *skb) | |
aa80175a | 1410 | { |
8a0da21b AD |
1411 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1412 | ||
1413 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1414 | napi_gro_receive(&q_vector->napi, skb); | |
1415 | else | |
1416 | netif_rx(skb); | |
aa80175a | 1417 | } |
43634e82 | 1418 | |
f800326d AD |
1419 | /** |
1420 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1421 | * @rx_ring: Rx ring being processed | |
1422 | * @rx_desc: Rx descriptor for current buffer | |
1423 | * @skb: Current socket buffer containing buffer in progress | |
1424 | * | |
1425 | * This function updates next to clean. If the buffer is an EOP buffer | |
1426 | * this function exits returning false, otherwise it will place the | |
1427 | * sk_buff in the next buffer to be chained and return true indicating | |
1428 | * that this is in fact a non-EOP buffer. | |
1429 | **/ | |
1430 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1431 | union ixgbe_adv_rx_desc *rx_desc, | |
1432 | struct sk_buff *skb) | |
1433 | { | |
1434 | u32 ntc = rx_ring->next_to_clean + 1; | |
1435 | ||
1436 | /* fetch, update, and store next to clean */ | |
1437 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1438 | rx_ring->next_to_clean = ntc; | |
1439 | ||
1440 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1441 | ||
1442 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1443 | return false; | |
1444 | ||
1445 | /* append_cnt indicates packet is RSC, if so fetch nextp */ | |
1446 | if (IXGBE_CB(skb)->append_cnt) { | |
1447 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1448 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1449 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1450 | } | |
1451 | ||
1452 | /* place skb in next buffer to be received */ | |
1453 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1454 | rx_ring->rx_stats.non_eop_descs++; | |
1455 | ||
1456 | return true; | |
1457 | } | |
1458 | ||
1459 | /** | |
1460 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1461 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1462 | * @rx_desc: pointer to the EOP Rx descriptor | |
1463 | * @skb: pointer to current skb being fixed | |
1464 | * | |
1465 | * Check for corrupted packet headers caused by senders on the local L2 | |
1466 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1467 | * should be very rare. | |
1468 | * | |
1469 | * Also address the case where we are pulling data in on pages only | |
1470 | * and as such no data is present in the skb header. | |
1471 | * | |
1472 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1473 | * it is large enough to qualify as a valid Ethernet frame. | |
1474 | * | |
1475 | * Returns true if an error was encountered and skb was freed. | |
1476 | **/ | |
1477 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1478 | union ixgbe_adv_rx_desc *rx_desc, | |
1479 | struct sk_buff *skb) | |
1480 | { | |
1481 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1482 | struct net_device *netdev = rx_ring->netdev; | |
1483 | unsigned char *va; | |
1484 | unsigned int pull_len; | |
1485 | ||
1486 | /* if the page was released unmap it, else just sync our portion */ | |
1487 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1488 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1489 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1490 | IXGBE_CB(skb)->page_released = false; | |
1491 | } else { | |
1492 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1493 | IXGBE_CB(skb)->dma, | |
1494 | frag->page_offset, | |
1495 | ixgbe_rx_bufsz(rx_ring), | |
1496 | DMA_FROM_DEVICE); | |
1497 | } | |
1498 | IXGBE_CB(skb)->dma = 0; | |
1499 | ||
1500 | /* verify that the packet does not have any known errors */ | |
1501 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1502 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1503 | !(netdev->features & NETIF_F_RXALL))) { | |
1504 | dev_kfree_skb_any(skb); | |
1505 | return true; | |
1506 | } | |
1507 | ||
1508 | /* | |
1509 | * it is valid to use page_address instead of kmap since we are | |
1510 | * working with pages allocated out of the lomem pool per | |
1511 | * alloc_page(GFP_ATOMIC) | |
1512 | */ | |
1513 | va = skb_frag_address(frag); | |
1514 | ||
1515 | /* | |
1516 | * we need the header to contain the greater of either ETH_HLEN or | |
1517 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1518 | */ | |
1519 | pull_len = skb_frag_size(frag); | |
252562c2 AD |
1520 | if (pull_len > IXGBE_RX_HDR_SIZE) |
1521 | pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE); | |
f800326d AD |
1522 | |
1523 | /* align pull length to size of long to optimize memcpy performance */ | |
1524 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1525 | ||
1526 | /* update all of the pointers */ | |
1527 | skb_frag_size_sub(frag, pull_len); | |
1528 | frag->page_offset += pull_len; | |
1529 | skb->data_len -= pull_len; | |
1530 | skb->tail += pull_len; | |
1531 | ||
1532 | /* | |
1533 | * if we sucked the frag empty then we should free it, | |
1534 | * if there are other frags here something is screwed up in hardware | |
1535 | */ | |
1536 | if (skb_frag_size(frag) == 0) { | |
1537 | BUG_ON(skb_shinfo(skb)->nr_frags != 1); | |
1538 | skb_shinfo(skb)->nr_frags = 0; | |
1539 | __skb_frag_unref(frag); | |
1540 | skb->truesize -= ixgbe_rx_bufsz(rx_ring); | |
1541 | } | |
1542 | ||
57efd44c AD |
1543 | #ifdef IXGBE_FCOE |
1544 | /* do not attempt to pad FCoE Frames as this will disrupt DDP */ | |
1545 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) | |
1546 | return false; | |
1547 | ||
1548 | #endif | |
f800326d AD |
1549 | /* if skb_pad returns an error the skb was freed */ |
1550 | if (unlikely(skb->len < 60)) { | |
1551 | int pad_len = 60 - skb->len; | |
1552 | ||
1553 | if (skb_pad(skb, pad_len)) | |
1554 | return true; | |
1555 | __skb_put(skb, pad_len); | |
1556 | } | |
1557 | ||
1558 | return false; | |
1559 | } | |
1560 | ||
1561 | /** | |
1562 | * ixgbe_can_reuse_page - determine if we can reuse a page | |
1563 | * @rx_buffer: pointer to rx_buffer containing the page we want to reuse | |
1564 | * | |
1565 | * Returns true if page can be reused in another Rx buffer | |
1566 | **/ | |
1567 | static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer) | |
1568 | { | |
1569 | struct page *page = rx_buffer->page; | |
1570 | ||
1571 | /* if we are only owner of page and it is local we can reuse it */ | |
1572 | return likely(page_count(page) == 1) && | |
1573 | likely(page_to_nid(page) == numa_node_id()); | |
1574 | } | |
1575 | ||
1576 | /** | |
1577 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1578 | * @rx_ring: rx descriptor ring to store buffers on | |
1579 | * @old_buff: donor buffer to have page reused | |
1580 | * | |
1581 | * Syncronizes page for reuse by the adapter | |
1582 | **/ | |
1583 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1584 | struct ixgbe_rx_buffer *old_buff) | |
1585 | { | |
1586 | struct ixgbe_rx_buffer *new_buff; | |
1587 | u16 nta = rx_ring->next_to_alloc; | |
1588 | u16 bufsz = ixgbe_rx_bufsz(rx_ring); | |
1589 | ||
1590 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1591 | ||
1592 | /* update, and store next to alloc */ | |
1593 | nta++; | |
1594 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1595 | ||
1596 | /* transfer page from old buffer to new buffer */ | |
1597 | new_buff->page = old_buff->page; | |
1598 | new_buff->dma = old_buff->dma; | |
1599 | ||
1600 | /* flip page offset to other buffer and store to new_buff */ | |
1601 | new_buff->page_offset = old_buff->page_offset ^ bufsz; | |
1602 | ||
1603 | /* sync the buffer for use by the device */ | |
1604 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
1605 | new_buff->page_offset, bufsz, | |
1606 | DMA_FROM_DEVICE); | |
1607 | ||
1608 | /* bump ref count on page before it is given to the stack */ | |
1609 | get_page(new_buff->page); | |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1614 | * @rx_ring: rx descriptor ring to transact packets on | |
1615 | * @rx_buffer: buffer containing page to add | |
1616 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1617 | * @skb: sk_buff to place the data into | |
1618 | * | |
1619 | * This function is based on skb_add_rx_frag. I would have used that | |
1620 | * function however it doesn't handle the truesize case correctly since we | |
1621 | * are allocating more memory than might be used for a single receive. | |
1622 | **/ | |
1623 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, | |
1624 | struct ixgbe_rx_buffer *rx_buffer, | |
1625 | struct sk_buff *skb, int size) | |
1626 | { | |
1627 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1628 | rx_buffer->page, rx_buffer->page_offset, | |
1629 | size); | |
1630 | skb->len += size; | |
1631 | skb->data_len += size; | |
1632 | skb->truesize += ixgbe_rx_bufsz(rx_ring); | |
1633 | } | |
1634 | ||
1635 | /** | |
1636 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1637 | * @q_vector: structure containing interrupt and ring information | |
1638 | * @rx_ring: rx descriptor ring to transact packets on | |
1639 | * @budget: Total limit on number of packets to process | |
1640 | * | |
1641 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1642 | * processing. The advantage to this is that on systems that have | |
1643 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1644 | * it by maintaining the mapping of the page to the syste. | |
1645 | * | |
1646 | * Returns true if all work is completed without reaching budget | |
1647 | **/ | |
4ff7fb12 | 1648 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1649 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1650 | int budget) |
9a799d71 | 1651 | { |
d2f4fbe2 | 1652 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1653 | #ifdef IXGBE_FCOE |
f800326d | 1654 | struct ixgbe_adapter *adapter = q_vector->adapter; |
3d8fd385 YZ |
1655 | int ddp_bytes = 0; |
1656 | #endif /* IXGBE_FCOE */ | |
f800326d | 1657 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1658 | |
f800326d AD |
1659 | do { |
1660 | struct ixgbe_rx_buffer *rx_buffer; | |
1661 | union ixgbe_adv_rx_desc *rx_desc; | |
1662 | struct sk_buff *skb; | |
1663 | struct page *page; | |
1664 | u16 ntc; | |
1665 | ||
1666 | /* return some buffers to hardware, one at a time is too slow */ | |
1667 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1668 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1669 | cleaned_count = 0; | |
1670 | } | |
1671 | ||
1672 | ntc = rx_ring->next_to_clean; | |
1673 | rx_desc = IXGBE_RX_DESC(rx_ring, ntc); | |
1674 | rx_buffer = &rx_ring->rx_buffer_info[ntc]; | |
1675 | ||
1676 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1677 | break; | |
9a799d71 | 1678 | |
f800326d AD |
1679 | /* |
1680 | * This memory barrier is needed to keep us from reading | |
1681 | * any other fields out of the rx_desc until we know the | |
1682 | * RXD_STAT_DD bit is set | |
1683 | */ | |
1684 | rmb(); | |
9a799d71 | 1685 | |
f800326d AD |
1686 | page = rx_buffer->page; |
1687 | prefetchw(page); | |
9a799d71 | 1688 | |
f800326d | 1689 | skb = rx_buffer->skb; |
c267fc16 | 1690 | |
f800326d AD |
1691 | if (likely(!skb)) { |
1692 | void *page_addr = page_address(page) + | |
1693 | rx_buffer->page_offset; | |
9a799d71 | 1694 | |
f800326d AD |
1695 | /* prefetch first cache line of first page */ |
1696 | prefetch(page_addr); | |
1697 | #if L1_CACHE_BYTES < 128 | |
1698 | prefetch(page_addr + L1_CACHE_BYTES); | |
1699 | #endif | |
1700 | ||
1701 | /* allocate a skb to store the frags */ | |
1702 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1703 | IXGBE_RX_HDR_SIZE); | |
1704 | if (unlikely(!skb)) { | |
1705 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1706 | break; | |
c267fc16 AD |
1707 | } |
1708 | ||
f800326d AD |
1709 | /* |
1710 | * we will be copying header into skb->data in | |
1711 | * pskb_may_pull so it is in our interest to prefetch | |
1712 | * it now to avoid a possible cache miss | |
1713 | */ | |
1714 | prefetchw(skb->data); | |
4c1975d7 AD |
1715 | |
1716 | /* | |
1717 | * Delay unmapping of the first packet. It carries the | |
1718 | * header information, HW may still access the header | |
f800326d AD |
1719 | * after the writeback. Only unmap it when EOP is |
1720 | * reached | |
4c1975d7 | 1721 | */ |
f800326d | 1722 | IXGBE_CB(skb)->dma = rx_buffer->dma; |
c267fc16 | 1723 | } else { |
f800326d AD |
1724 | /* we are reusing so sync this buffer for CPU use */ |
1725 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1726 | rx_buffer->dma, | |
1727 | rx_buffer->page_offset, | |
1728 | ixgbe_rx_bufsz(rx_ring), | |
1729 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1730 | } |
1731 | ||
f800326d AD |
1732 | /* pull page into skb */ |
1733 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, | |
1734 | le16_to_cpu(rx_desc->wb.upper.length)); | |
9a799d71 | 1735 | |
f800326d AD |
1736 | if (ixgbe_can_reuse_page(rx_buffer)) { |
1737 | /* hand second half of page back to the ring */ | |
1738 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1739 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1740 | /* the page has been released from the ring */ | |
1741 | IXGBE_CB(skb)->page_released = true; | |
1742 | } else { | |
1743 | /* we are not reusing the buffer so unmap it */ | |
1744 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1745 | ixgbe_rx_pg_size(rx_ring), | |
1746 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1747 | } |
1748 | ||
f800326d AD |
1749 | /* clear contents of buffer_info */ |
1750 | rx_buffer->skb = NULL; | |
1751 | rx_buffer->dma = 0; | |
1752 | rx_buffer->page = NULL; | |
4c1975d7 | 1753 | |
f800326d | 1754 | ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb); |
9a799d71 | 1755 | |
9a799d71 | 1756 | cleaned_count++; |
f8212f97 | 1757 | |
f800326d AD |
1758 | /* place incomplete frames back on ring for completion */ |
1759 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1760 | continue; | |
c267fc16 | 1761 | |
f800326d AD |
1762 | /* verify the packet layout is correct */ |
1763 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1764 | continue; | |
9a799d71 | 1765 | |
d2f4fbe2 AV |
1766 | /* probably a little skewed due to removing CRC */ |
1767 | total_rx_bytes += skb->len; | |
1768 | total_rx_packets++; | |
1769 | ||
8a0da21b AD |
1770 | /* populate checksum, timestamp, VLAN, and protocol */ |
1771 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1772 | ||
332d4a7d YZ |
1773 | #ifdef IXGBE_FCOE |
1774 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
57efd44c | 1775 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { |
f56e0cb1 | 1776 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
63d635b2 AD |
1777 | if (!ddp_bytes) { |
1778 | dev_kfree_skb_any(skb); | |
f800326d | 1779 | continue; |
63d635b2 | 1780 | } |
3d8fd385 | 1781 | } |
f800326d | 1782 | |
332d4a7d | 1783 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1784 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1785 | |
f800326d | 1786 | /* update budget accounting */ |
4ff7fb12 | 1787 | budget--; |
f800326d | 1788 | } while (likely(budget)); |
9a799d71 | 1789 | |
3d8fd385 YZ |
1790 | #ifdef IXGBE_FCOE |
1791 | /* include DDPed FCoE data */ | |
1792 | if (ddp_bytes > 0) { | |
1793 | unsigned int mss; | |
1794 | ||
fc77dc3c | 1795 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1796 | sizeof(struct fc_frame_header) - |
1797 | sizeof(struct fcoe_crc_eof); | |
1798 | if (mss > 512) | |
1799 | mss &= ~511; | |
1800 | total_rx_bytes += ddp_bytes; | |
1801 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1802 | } | |
3d8fd385 | 1803 | |
f800326d | 1804 | #endif /* IXGBE_FCOE */ |
c267fc16 AD |
1805 | u64_stats_update_begin(&rx_ring->syncp); |
1806 | rx_ring->stats.packets += total_rx_packets; | |
1807 | rx_ring->stats.bytes += total_rx_bytes; | |
1808 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1809 | q_vector->rx.total_packets += total_rx_packets; |
1810 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1811 | |
f800326d AD |
1812 | if (cleaned_count) |
1813 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1814 | ||
4ff7fb12 | 1815 | return !!budget; |
9a799d71 AK |
1816 | } |
1817 | ||
9a799d71 AK |
1818 | /** |
1819 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1820 | * @adapter: board private structure | |
1821 | * | |
1822 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1823 | * interrupts. | |
1824 | **/ | |
1825 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1826 | { | |
021230d4 | 1827 | struct ixgbe_q_vector *q_vector; |
49c7ffbe | 1828 | int v_idx; |
021230d4 | 1829 | u32 mask; |
9a799d71 | 1830 | |
8e34d1aa AD |
1831 | /* Populate MSIX to EITR Select */ |
1832 | if (adapter->num_vfs > 32) { | |
1833 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1834 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1835 | } | |
1836 | ||
4df10466 JB |
1837 | /* |
1838 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1839 | * corresponding register. |
1840 | */ | |
49c7ffbe | 1841 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { |
efe3d3c8 | 1842 | struct ixgbe_ring *ring; |
7a921c93 | 1843 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1844 | |
a557928e | 1845 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1846 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1847 | ||
a557928e | 1848 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1849 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1850 | ||
d5bf4f67 ET |
1851 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
1852 | /* tx only vector */ | |
1853 | if (adapter->tx_itr_setting == 1) | |
1854 | q_vector->itr = IXGBE_10K_ITR; | |
1855 | else | |
1856 | q_vector->itr = adapter->tx_itr_setting; | |
1857 | } else { | |
1858 | /* rx or rx/tx vector */ | |
1859 | if (adapter->rx_itr_setting == 1) | |
1860 | q_vector->itr = IXGBE_20K_ITR; | |
1861 | else | |
1862 | q_vector->itr = adapter->rx_itr_setting; | |
1863 | } | |
021230d4 | 1864 | |
fe49f04a | 1865 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1866 | } |
1867 | ||
bd508178 AD |
1868 | switch (adapter->hw.mac.type) { |
1869 | case ixgbe_mac_82598EB: | |
e8e26350 | 1870 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1871 | v_idx); |
bd508178 AD |
1872 | break; |
1873 | case ixgbe_mac_82599EB: | |
b93a2226 | 1874 | case ixgbe_mac_X540: |
e8e26350 | 1875 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1876 | break; |
bd508178 AD |
1877 | default: |
1878 | break; | |
1879 | } | |
021230d4 AV |
1880 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1881 | ||
41fb9248 | 1882 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1883 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
1884 | mask &= ~(IXGBE_EIMS_OTHER | |
1885 | IXGBE_EIMS_MAILBOX | | |
1886 | IXGBE_EIMS_LSC); | |
1887 | ||
021230d4 | 1888 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1889 | } |
1890 | ||
f494e8fa AV |
1891 | enum latency_range { |
1892 | lowest_latency = 0, | |
1893 | low_latency = 1, | |
1894 | bulk_latency = 2, | |
1895 | latency_invalid = 255 | |
1896 | }; | |
1897 | ||
1898 | /** | |
1899 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1900 | * @q_vector: structure containing interrupt and ring information |
1901 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1902 | * |
1903 | * Stores a new ITR value based on packets and byte | |
1904 | * counts during the last interrupt. The advantage of per interrupt | |
1905 | * computation is faster updates and more accurate ITR for the current | |
1906 | * traffic pattern. Constants in this function were computed | |
1907 | * based on theoretical maximum wire speed and thresholds were set based | |
1908 | * on testing data as well as attempting to minimize response time | |
1909 | * while increasing bulk throughput. | |
1910 | * this functionality is controlled by the InterruptThrottleRate module | |
1911 | * parameter (see ixgbe_param.c) | |
1912 | **/ | |
bd198058 AD |
1913 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1914 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1915 | { |
bd198058 AD |
1916 | int bytes = ring_container->total_bytes; |
1917 | int packets = ring_container->total_packets; | |
1918 | u32 timepassed_us; | |
621bd70e | 1919 | u64 bytes_perint; |
bd198058 | 1920 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
1921 | |
1922 | if (packets == 0) | |
bd198058 | 1923 | return; |
f494e8fa AV |
1924 | |
1925 | /* simple throttlerate management | |
621bd70e AD |
1926 | * 0-10MB/s lowest (100000 ints/s) |
1927 | * 10-20MB/s low (20000 ints/s) | |
1928 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
1929 | */ |
1930 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 1931 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
1932 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1933 | ||
1934 | switch (itr_setting) { | |
1935 | case lowest_latency: | |
621bd70e | 1936 | if (bytes_perint > 10) |
bd198058 | 1937 | itr_setting = low_latency; |
f494e8fa AV |
1938 | break; |
1939 | case low_latency: | |
621bd70e | 1940 | if (bytes_perint > 20) |
bd198058 | 1941 | itr_setting = bulk_latency; |
621bd70e | 1942 | else if (bytes_perint <= 10) |
bd198058 | 1943 | itr_setting = lowest_latency; |
f494e8fa AV |
1944 | break; |
1945 | case bulk_latency: | |
621bd70e | 1946 | if (bytes_perint <= 20) |
bd198058 | 1947 | itr_setting = low_latency; |
f494e8fa AV |
1948 | break; |
1949 | } | |
1950 | ||
bd198058 AD |
1951 | /* clear work counters since we have the values we need */ |
1952 | ring_container->total_bytes = 0; | |
1953 | ring_container->total_packets = 0; | |
1954 | ||
1955 | /* write updated itr to ring container */ | |
1956 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1957 | } |
1958 | ||
509ee935 JB |
1959 | /** |
1960 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1961 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1962 | * |
1963 | * This function is made to be called by ethtool and by the driver | |
1964 | * when it needs to update EITR registers at runtime. Hardware | |
1965 | * specific quirks/differences are taken care of here. | |
1966 | */ | |
fe49f04a | 1967 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1968 | { |
fe49f04a | 1969 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1970 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1971 | int v_idx = q_vector->v_idx; |
5d967eb7 | 1972 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 1973 | |
bd508178 AD |
1974 | switch (adapter->hw.mac.type) { |
1975 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1976 | /* must write high and low 16 bits to reset counter */ |
1977 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1978 | break; |
1979 | case ixgbe_mac_82599EB: | |
b93a2226 | 1980 | case ixgbe_mac_X540: |
509ee935 JB |
1981 | /* |
1982 | * set the WDIS bit to not clear the timer bits and cause an | |
1983 | * immediate assertion of the interrupt | |
1984 | */ | |
1985 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1986 | break; |
1987 | default: | |
1988 | break; | |
509ee935 JB |
1989 | } |
1990 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1991 | } | |
1992 | ||
bd198058 | 1993 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1994 | { |
d5bf4f67 | 1995 | u32 new_itr = q_vector->itr; |
bd198058 | 1996 | u8 current_itr; |
f494e8fa | 1997 | |
bd198058 AD |
1998 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1999 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 2000 | |
08c8833b | 2001 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
2002 | |
2003 | switch (current_itr) { | |
2004 | /* counts and packets in update_itr are dependent on these numbers */ | |
2005 | case lowest_latency: | |
d5bf4f67 | 2006 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
2007 | break; |
2008 | case low_latency: | |
d5bf4f67 | 2009 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2010 | break; |
2011 | case bulk_latency: | |
d5bf4f67 | 2012 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 2013 | break; |
bd198058 AD |
2014 | default: |
2015 | break; | |
f494e8fa AV |
2016 | } |
2017 | ||
d5bf4f67 | 2018 | if (new_itr != q_vector->itr) { |
fe49f04a | 2019 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2020 | new_itr = (10 * new_itr * q_vector->itr) / |
2021 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2022 | |
bd198058 | 2023 | /* save the algorithm value here */ |
5d967eb7 | 2024 | q_vector->itr = new_itr; |
fe49f04a AD |
2025 | |
2026 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2027 | } |
f494e8fa AV |
2028 | } |
2029 | ||
119fc60a | 2030 | /** |
de88eeeb | 2031 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2032 | * @adapter: pointer to adapter |
119fc60a | 2033 | **/ |
f0f9778d | 2034 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2035 | { |
119fc60a MC |
2036 | struct ixgbe_hw *hw = &adapter->hw; |
2037 | u32 eicr = adapter->interrupt_event; | |
2038 | ||
f0f9778d | 2039 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2040 | return; |
2041 | ||
f0f9778d AD |
2042 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2043 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2044 | return; | |
2045 | ||
2046 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2047 | ||
7ca647bd | 2048 | switch (hw->device_id) { |
f0f9778d AD |
2049 | case IXGBE_DEV_ID_82599_T3_LOM: |
2050 | /* | |
2051 | * Since the warning interrupt is for both ports | |
2052 | * we don't have to check if: | |
2053 | * - This interrupt wasn't for our port. | |
2054 | * - We may have missed the interrupt so always have to | |
2055 | * check if we got a LSC | |
2056 | */ | |
2057 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
2058 | !(eicr & IXGBE_EICR_LSC)) | |
2059 | return; | |
2060 | ||
2061 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2062 | u32 autoneg; | |
2063 | bool link_up = false; | |
7ca647bd | 2064 | |
7ca647bd JP |
2065 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2066 | ||
f0f9778d AD |
2067 | if (link_up) |
2068 | return; | |
2069 | } | |
2070 | ||
2071 | /* Check if this is not due to overtemp */ | |
2072 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2073 | return; | |
2074 | ||
2075 | break; | |
7ca647bd JP |
2076 | default: |
2077 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2078 | return; |
7ca647bd | 2079 | break; |
119fc60a | 2080 | } |
7ca647bd JP |
2081 | e_crit(drv, |
2082 | "Network adapter has been stopped because it has over heated. " | |
2083 | "Restart the computer. If the problem persists, " | |
2084 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2085 | |
2086 | adapter->interrupt_event = 0; | |
119fc60a MC |
2087 | } |
2088 | ||
0befdb3e JB |
2089 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2090 | { | |
2091 | struct ixgbe_hw *hw = &adapter->hw; | |
2092 | ||
2093 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2094 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2095 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2096 | /* write to clear the interrupt */ |
2097 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2098 | } | |
2099 | } | |
cf8280ee | 2100 | |
4f51bf70 JK |
2101 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2102 | { | |
2103 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2104 | return; | |
2105 | ||
2106 | switch (adapter->hw.mac.type) { | |
2107 | case ixgbe_mac_82599EB: | |
2108 | /* | |
2109 | * Need to check link state so complete overtemp check | |
2110 | * on service task | |
2111 | */ | |
2112 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2113 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2114 | adapter->interrupt_event = eicr; | |
2115 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2116 | ixgbe_service_event_schedule(adapter); | |
2117 | return; | |
2118 | } | |
2119 | return; | |
2120 | case ixgbe_mac_X540: | |
2121 | if (!(eicr & IXGBE_EICR_TS)) | |
2122 | return; | |
2123 | break; | |
2124 | default: | |
2125 | return; | |
2126 | } | |
2127 | ||
2128 | e_crit(drv, | |
2129 | "Network adapter has been stopped because it has over heated. " | |
2130 | "Restart the computer. If the problem persists, " | |
2131 | "power off the system and replace the adapter\n"); | |
2132 | } | |
2133 | ||
e8e26350 PW |
2134 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2135 | { | |
2136 | struct ixgbe_hw *hw = &adapter->hw; | |
2137 | ||
73c4b7cd AD |
2138 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2139 | /* Clear the interrupt */ | |
2140 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2141 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2142 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2143 | ixgbe_service_event_schedule(adapter); | |
2144 | } | |
73c4b7cd AD |
2145 | } |
2146 | ||
e8e26350 PW |
2147 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2148 | /* Clear the interrupt */ | |
2149 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2150 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2151 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2152 | ixgbe_service_event_schedule(adapter); | |
2153 | } | |
e8e26350 PW |
2154 | } |
2155 | } | |
2156 | ||
cf8280ee JB |
2157 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2158 | { | |
2159 | struct ixgbe_hw *hw = &adapter->hw; | |
2160 | ||
2161 | adapter->lsc_int++; | |
2162 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2163 | adapter->link_check_timeout = jiffies; | |
2164 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2165 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2166 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2167 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2168 | } |
2169 | } | |
2170 | ||
fe49f04a AD |
2171 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2172 | u64 qmask) | |
2173 | { | |
2174 | u32 mask; | |
bd508178 | 2175 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2176 | |
bd508178 AD |
2177 | switch (hw->mac.type) { |
2178 | case ixgbe_mac_82598EB: | |
fe49f04a | 2179 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2180 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2181 | break; | |
2182 | case ixgbe_mac_82599EB: | |
b93a2226 | 2183 | case ixgbe_mac_X540: |
fe49f04a | 2184 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2185 | if (mask) |
2186 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2187 | mask = (qmask >> 32); |
bd508178 AD |
2188 | if (mask) |
2189 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2190 | break; | |
2191 | default: | |
2192 | break; | |
fe49f04a AD |
2193 | } |
2194 | /* skip the flush */ | |
2195 | } | |
2196 | ||
2197 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2198 | u64 qmask) |
fe49f04a AD |
2199 | { |
2200 | u32 mask; | |
bd508178 | 2201 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2202 | |
bd508178 AD |
2203 | switch (hw->mac.type) { |
2204 | case ixgbe_mac_82598EB: | |
fe49f04a | 2205 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2206 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2207 | break; | |
2208 | case ixgbe_mac_82599EB: | |
b93a2226 | 2209 | case ixgbe_mac_X540: |
fe49f04a | 2210 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2211 | if (mask) |
2212 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2213 | mask = (qmask >> 32); |
bd508178 AD |
2214 | if (mask) |
2215 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2216 | break; | |
2217 | default: | |
2218 | break; | |
fe49f04a AD |
2219 | } |
2220 | /* skip the flush */ | |
2221 | } | |
2222 | ||
021230d4 | 2223 | /** |
2c4af694 AD |
2224 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2225 | * @adapter: board private structure | |
021230d4 | 2226 | **/ |
2c4af694 AD |
2227 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2228 | bool flush) | |
9a799d71 | 2229 | { |
2c4af694 | 2230 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2231 | |
2c4af694 AD |
2232 | /* don't reenable LSC while waiting for link */ |
2233 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2234 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2235 | |
2c4af694 | 2236 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2237 | switch (adapter->hw.mac.type) { |
2238 | case ixgbe_mac_82599EB: | |
2239 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2240 | break; | |
2241 | case ixgbe_mac_X540: | |
2242 | mask |= IXGBE_EIMS_TS; | |
2243 | break; | |
2244 | default: | |
2245 | break; | |
2246 | } | |
2c4af694 AD |
2247 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2248 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2249 | switch (adapter->hw.mac.type) { | |
2250 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2251 | mask |= IXGBE_EIMS_GPI_SDP1; |
2252 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2253 | case ixgbe_mac_X540: |
2254 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2255 | mask |= IXGBE_EIMS_MAILBOX; |
2256 | break; | |
2257 | default: | |
2258 | break; | |
9a799d71 | 2259 | } |
2c4af694 AD |
2260 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2261 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2262 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2263 | |
2c4af694 AD |
2264 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2265 | if (queues) | |
2266 | ixgbe_irq_enable_queues(adapter, ~0); | |
2267 | if (flush) | |
2268 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2269 | } |
2270 | ||
2c4af694 | 2271 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2272 | { |
a65151ba | 2273 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2274 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2275 | u32 eicr; |
91281fd3 | 2276 | |
54037505 DS |
2277 | /* |
2278 | * Workaround for Silicon errata. Use clear-by-write instead | |
2279 | * of clear-by-read. Reading with EICS will return the | |
2280 | * interrupt causes without clearing, which later be done | |
2281 | * with the write to EICR. | |
2282 | */ | |
2283 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2284 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2285 | |
cf8280ee JB |
2286 | if (eicr & IXGBE_EICR_LSC) |
2287 | ixgbe_check_lsc(adapter); | |
f0848276 | 2288 | |
1cdd1ec8 GR |
2289 | if (eicr & IXGBE_EICR_MAILBOX) |
2290 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2291 | |
bd508178 AD |
2292 | switch (hw->mac.type) { |
2293 | case ixgbe_mac_82599EB: | |
b93a2226 | 2294 | case ixgbe_mac_X540: |
2c4af694 AD |
2295 | if (eicr & IXGBE_EICR_ECC) |
2296 | e_info(link, "Received unrecoverable ECC Err, please " | |
2297 | "reboot\n"); | |
c4cf55e5 PWJ |
2298 | /* Handle Flow Director Full threshold interrupt */ |
2299 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2300 | int reinit_count = 0; |
c4cf55e5 | 2301 | int i; |
c4cf55e5 | 2302 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2303 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2304 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2305 | &ring->state)) |
2306 | reinit_count++; | |
2307 | } | |
2308 | if (reinit_count) { | |
2309 | /* no more flow director interrupts until after init */ | |
2310 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2311 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2312 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2313 | } |
2314 | } | |
f0f9778d | 2315 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2316 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2317 | break; |
2318 | default: | |
2319 | break; | |
c4cf55e5 | 2320 | } |
f0848276 | 2321 | |
bd508178 | 2322 | ixgbe_check_fan_failure(adapter, eicr); |
681ae1ad JK |
2323 | #ifdef CONFIG_IXGBE_PTP |
2324 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
2325 | #endif | |
efe3d3c8 | 2326 | |
7086400d | 2327 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2328 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2329 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2330 | |
9a799d71 | 2331 | return IRQ_HANDLED; |
f0848276 | 2332 | } |
91281fd3 | 2333 | |
4ff7fb12 | 2334 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2335 | { |
021230d4 | 2336 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2337 | |
9b471446 | 2338 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2339 | |
4ff7fb12 AD |
2340 | if (q_vector->rx.ring || q_vector->tx.ring) |
2341 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2342 | |
9a799d71 | 2343 | return IRQ_HANDLED; |
91281fd3 AD |
2344 | } |
2345 | ||
eb01b975 AD |
2346 | /** |
2347 | * ixgbe_poll - NAPI Rx polling callback | |
2348 | * @napi: structure for representing this polling device | |
2349 | * @budget: how many packets driver is allowed to clean | |
2350 | * | |
2351 | * This function is used for legacy and MSI, NAPI mode | |
2352 | **/ | |
8af3c33f | 2353 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2354 | { |
2355 | struct ixgbe_q_vector *q_vector = | |
2356 | container_of(napi, struct ixgbe_q_vector, napi); | |
2357 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2358 | struct ixgbe_ring *ring; | |
2359 | int per_ring_budget; | |
2360 | bool clean_complete = true; | |
2361 | ||
2362 | #ifdef CONFIG_IXGBE_DCA | |
2363 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2364 | ixgbe_update_dca(q_vector); | |
2365 | #endif | |
2366 | ||
2367 | ixgbe_for_each_ring(ring, q_vector->tx) | |
2368 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
2369 | ||
2370 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2371 | * the budget to go below 1 because we'll exit polling */ | |
2372 | if (q_vector->rx.count > 1) | |
2373 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2374 | else | |
2375 | per_ring_budget = budget; | |
2376 | ||
2377 | ixgbe_for_each_ring(ring, q_vector->rx) | |
2378 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
2379 | per_ring_budget); | |
2380 | ||
2381 | /* If all work not completed, return budget and keep polling */ | |
2382 | if (!clean_complete) | |
2383 | return budget; | |
2384 | ||
2385 | /* all work done, exit the polling mode */ | |
2386 | napi_complete(napi); | |
2387 | if (adapter->rx_itr_setting & 1) | |
2388 | ixgbe_set_itr(q_vector); | |
2389 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2390 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2391 | ||
2392 | return 0; | |
2393 | } | |
2394 | ||
021230d4 AV |
2395 | /** |
2396 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2397 | * @adapter: board private structure | |
2398 | * | |
2399 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2400 | * interrupts from the kernel. | |
2401 | **/ | |
2402 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2403 | { | |
2404 | struct net_device *netdev = adapter->netdev; | |
207867f5 | 2405 | int vector, err; |
e8e9f696 | 2406 | int ri = 0, ti = 0; |
021230d4 | 2407 | |
49c7ffbe | 2408 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
d0759ebb | 2409 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2410 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2411 | |
4ff7fb12 | 2412 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2413 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2414 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2415 | ti++; | |
2416 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2417 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2418 | "%s-%s-%d", netdev->name, "rx", ri++); |
2419 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2420 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2421 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2422 | } else { |
2423 | /* skip this unused q_vector */ | |
2424 | continue; | |
32aa77a4 | 2425 | } |
207867f5 AD |
2426 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2427 | q_vector->name, q_vector); | |
9a799d71 | 2428 | if (err) { |
396e799c | 2429 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2430 | "Error: %d\n", err); |
021230d4 | 2431 | goto free_queue_irqs; |
9a799d71 | 2432 | } |
207867f5 AD |
2433 | /* If Flow Director is enabled, set interrupt affinity */ |
2434 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2435 | /* assign the mask for this irq */ | |
2436 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2437 | &q_vector->affinity_mask); |
207867f5 | 2438 | } |
9a799d71 AK |
2439 | } |
2440 | ||
021230d4 | 2441 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2442 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2443 | if (err) { |
de88eeeb | 2444 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2445 | goto free_queue_irqs; |
9a799d71 AK |
2446 | } |
2447 | ||
9a799d71 AK |
2448 | return 0; |
2449 | ||
021230d4 | 2450 | free_queue_irqs: |
207867f5 AD |
2451 | while (vector) { |
2452 | vector--; | |
2453 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2454 | NULL); | |
2455 | free_irq(adapter->msix_entries[vector].vector, | |
2456 | adapter->q_vector[vector]); | |
2457 | } | |
021230d4 AV |
2458 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2459 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2460 | kfree(adapter->msix_entries); |
2461 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2462 | return err; |
2463 | } | |
2464 | ||
2465 | /** | |
021230d4 | 2466 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2467 | * @irq: interrupt number |
2468 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2469 | **/ |
2470 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2471 | { | |
a65151ba | 2472 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2473 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2474 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2475 | u32 eicr; |
2476 | ||
54037505 | 2477 | /* |
24ddd967 | 2478 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2479 | * before the read of EICR. |
2480 | */ | |
2481 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2482 | ||
021230d4 | 2483 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2484 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2485 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2486 | if (!eicr) { |
6af3b9eb ET |
2487 | /* |
2488 | * shared interrupt alert! | |
f47cf66e | 2489 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2490 | * have disabled interrupts due to EIAM |
2491 | * finish the workaround of silicon errata on 82598. Unmask | |
2492 | * the interrupt that we masked before the EICR read. | |
2493 | */ | |
2494 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2495 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2496 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2497 | } |
9a799d71 | 2498 | |
cf8280ee JB |
2499 | if (eicr & IXGBE_EICR_LSC) |
2500 | ixgbe_check_lsc(adapter); | |
021230d4 | 2501 | |
bd508178 AD |
2502 | switch (hw->mac.type) { |
2503 | case ixgbe_mac_82599EB: | |
e8e26350 | 2504 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2505 | /* Fall through */ |
2506 | case ixgbe_mac_X540: | |
2507 | if (eicr & IXGBE_EICR_ECC) | |
2508 | e_info(link, "Received unrecoverable ECC err, please " | |
2509 | "reboot\n"); | |
4f51bf70 | 2510 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2511 | break; |
2512 | default: | |
2513 | break; | |
2514 | } | |
e8e26350 | 2515 | |
0befdb3e | 2516 | ixgbe_check_fan_failure(adapter, eicr); |
681ae1ad JK |
2517 | #ifdef CONFIG_IXGBE_PTP |
2518 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
2519 | #endif | |
0befdb3e | 2520 | |
b9f6ed2b AD |
2521 | /* would disable interrupts here but EIAM disabled it */ |
2522 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2523 | |
6af3b9eb ET |
2524 | /* |
2525 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2526 | * ixgbe_poll will re-enable the queue interrupts | |
2527 | */ | |
6af3b9eb ET |
2528 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2529 | ixgbe_irq_enable(adapter, false, false); | |
2530 | ||
9a799d71 AK |
2531 | return IRQ_HANDLED; |
2532 | } | |
2533 | ||
2534 | /** | |
2535 | * ixgbe_request_irq - initialize interrupts | |
2536 | * @adapter: board private structure | |
2537 | * | |
2538 | * Attempts to configure interrupts using the best available | |
2539 | * capabilities of the hardware and kernel. | |
2540 | **/ | |
021230d4 | 2541 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2542 | { |
2543 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2544 | int err; |
9a799d71 | 2545 | |
4cc6df29 | 2546 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2547 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2548 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2549 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2550 | netdev->name, adapter); |
4cc6df29 | 2551 | else |
a0607fd3 | 2552 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2553 | netdev->name, adapter); |
9a799d71 | 2554 | |
de88eeeb | 2555 | if (err) |
396e799c | 2556 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2557 | |
9a799d71 AK |
2558 | return err; |
2559 | } | |
2560 | ||
2561 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2562 | { | |
49c7ffbe | 2563 | int vector; |
9a799d71 | 2564 | |
49c7ffbe AD |
2565 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2566 | free_irq(adapter->pdev->irq, adapter); | |
2567 | return; | |
2568 | } | |
4cc6df29 | 2569 | |
49c7ffbe AD |
2570 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
2571 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; | |
2572 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
894ff7cf | 2573 | |
49c7ffbe AD |
2574 | /* free only the irqs that were actually requested */ |
2575 | if (!q_vector->rx.ring && !q_vector->tx.ring) | |
2576 | continue; | |
207867f5 | 2577 | |
49c7ffbe AD |
2578 | /* clear the affinity_mask in the IRQ descriptor */ |
2579 | irq_set_affinity_hint(entry->vector, NULL); | |
2580 | ||
2581 | free_irq(entry->vector, q_vector); | |
9a799d71 | 2582 | } |
49c7ffbe AD |
2583 | |
2584 | free_irq(adapter->msix_entries[vector++].vector, adapter); | |
9a799d71 AK |
2585 | } |
2586 | ||
22d5a71b JB |
2587 | /** |
2588 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2589 | * @adapter: board private structure | |
2590 | **/ | |
2591 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2592 | { | |
bd508178 AD |
2593 | switch (adapter->hw.mac.type) { |
2594 | case ixgbe_mac_82598EB: | |
835462fc | 2595 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2596 | break; |
2597 | case ixgbe_mac_82599EB: | |
b93a2226 | 2598 | case ixgbe_mac_X540: |
835462fc NS |
2599 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2600 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2601 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2602 | break; |
2603 | default: | |
2604 | break; | |
22d5a71b JB |
2605 | } |
2606 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2607 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
49c7ffbe AD |
2608 | int vector; |
2609 | ||
2610 | for (vector = 0; vector < adapter->num_q_vectors; vector++) | |
2611 | synchronize_irq(adapter->msix_entries[vector].vector); | |
2612 | ||
2613 | synchronize_irq(adapter->msix_entries[vector++].vector); | |
22d5a71b JB |
2614 | } else { |
2615 | synchronize_irq(adapter->pdev->irq); | |
2616 | } | |
2617 | } | |
2618 | ||
9a799d71 AK |
2619 | /** |
2620 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2621 | * | |
2622 | **/ | |
2623 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2624 | { | |
d5bf4f67 | 2625 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2626 | |
d5bf4f67 ET |
2627 | /* rx/tx vector */ |
2628 | if (adapter->rx_itr_setting == 1) | |
2629 | q_vector->itr = IXGBE_20K_ITR; | |
2630 | else | |
2631 | q_vector->itr = adapter->rx_itr_setting; | |
2632 | ||
2633 | ixgbe_write_eitr(q_vector); | |
9a799d71 | 2634 | |
e8e26350 PW |
2635 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2636 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2637 | |
396e799c | 2638 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2639 | } |
2640 | ||
43e69bf0 AD |
2641 | /** |
2642 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2643 | * @adapter: board private structure | |
2644 | * @ring: structure containing ring specific data | |
2645 | * | |
2646 | * Configure the Tx descriptor ring after a reset. | |
2647 | **/ | |
84418e3b AD |
2648 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2649 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2650 | { |
2651 | struct ixgbe_hw *hw = &adapter->hw; | |
2652 | u64 tdba = ring->dma; | |
2f1860b8 | 2653 | int wait_loop = 10; |
b88c6de2 | 2654 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2655 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2656 | |
2f1860b8 | 2657 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2658 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2659 | IXGBE_WRITE_FLUSH(hw); |
2660 | ||
43e69bf0 | 2661 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2662 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2663 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2664 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2665 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2666 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2667 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2668 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2669 | |
b88c6de2 AD |
2670 | /* |
2671 | * set WTHRESH to encourage burst writeback, it should not be set | |
2672 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2673 | * | |
2674 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2675 | * to or less than the number of on chip descriptors, which is | |
2676 | * currently 40. | |
2677 | */ | |
e954b374 | 2678 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2679 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2680 | else | |
2681 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2682 | ||
e954b374 AD |
2683 | /* |
2684 | * Setting PTHRESH to 32 both improves performance | |
2685 | * and avoids a TX hang with DFP enabled | |
2686 | */ | |
b88c6de2 AD |
2687 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2688 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2689 | |
2690 | /* reinitialize flowdirector state */ | |
39cb681b | 2691 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
ee9e0f0b AD |
2692 | ring->atr_sample_rate = adapter->atr_sample_rate; |
2693 | ring->atr_count = 0; | |
2694 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2695 | } else { | |
2696 | ring->atr_sample_rate = 0; | |
2697 | } | |
2f1860b8 | 2698 | |
c84d324c JF |
2699 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2700 | ||
2f1860b8 | 2701 | /* enable queue */ |
2f1860b8 AD |
2702 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2703 | ||
2704 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2705 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2706 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2707 | return; | |
2708 | ||
2709 | /* poll to verify queue is enabled */ | |
2710 | do { | |
032b4325 | 2711 | usleep_range(1000, 2000); |
2f1860b8 AD |
2712 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2713 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2714 | if (!wait_loop) | |
2715 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2716 | } |
2717 | ||
120ff942 AD |
2718 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2719 | { | |
2720 | struct ixgbe_hw *hw = &adapter->hw; | |
671c0adb | 2721 | u32 rttdcs, mtqc; |
8b1c0b24 | 2722 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2723 | |
2724 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2725 | return; | |
2726 | ||
2727 | /* disable the arbiter while setting MTQC */ | |
2728 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2729 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2730 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2731 | ||
2732 | /* set transmit pool layout */ | |
671c0adb AD |
2733 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2734 | mtqc = IXGBE_MTQC_VT_ENA; | |
2735 | if (tcs > 4) | |
2736 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
2737 | else if (tcs > 1) | |
2738 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2739 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
2740 | mtqc |= IXGBE_MTQC_32VF; | |
2741 | else | |
2742 | mtqc |= IXGBE_MTQC_64VF; | |
2743 | } else { | |
2744 | if (tcs > 4) | |
2745 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
2746 | else if (tcs > 1) | |
2747 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
8b1c0b24 | 2748 | else |
671c0adb AD |
2749 | mtqc = IXGBE_MTQC_64Q_1PB; |
2750 | } | |
120ff942 | 2751 | |
671c0adb | 2752 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
120ff942 | 2753 | |
671c0adb AD |
2754 | /* Enable Security TX Buffer IFG for multiple pb */ |
2755 | if (tcs) { | |
2756 | u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2757 | sectx |= IXGBE_SECTX_DCB; | |
2758 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); | |
120ff942 AD |
2759 | } |
2760 | ||
2761 | /* re-enable the arbiter */ | |
2762 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2763 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2764 | } | |
2765 | ||
9a799d71 | 2766 | /** |
3a581073 | 2767 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2768 | * @adapter: board private structure |
2769 | * | |
2770 | * Configure the Tx unit of the MAC after a reset. | |
2771 | **/ | |
2772 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2773 | { | |
2f1860b8 AD |
2774 | struct ixgbe_hw *hw = &adapter->hw; |
2775 | u32 dmatxctl; | |
43e69bf0 | 2776 | u32 i; |
9a799d71 | 2777 | |
2f1860b8 AD |
2778 | ixgbe_setup_mtqc(adapter); |
2779 | ||
2780 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2781 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2782 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2783 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2784 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2785 | } | |
2786 | ||
9a799d71 | 2787 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2788 | for (i = 0; i < adapter->num_tx_queues; i++) |
2789 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2790 | } |
2791 | ||
3ebe8fde AD |
2792 | static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, |
2793 | struct ixgbe_ring *ring) | |
2794 | { | |
2795 | struct ixgbe_hw *hw = &adapter->hw; | |
2796 | u8 reg_idx = ring->reg_idx; | |
2797 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2798 | ||
2799 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
2800 | ||
2801 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2802 | } | |
2803 | ||
2804 | static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, | |
2805 | struct ixgbe_ring *ring) | |
2806 | { | |
2807 | struct ixgbe_hw *hw = &adapter->hw; | |
2808 | u8 reg_idx = ring->reg_idx; | |
2809 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2810 | ||
2811 | srrctl &= ~IXGBE_SRRCTL_DROP_EN; | |
2812 | ||
2813 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2814 | } | |
2815 | ||
2816 | #ifdef CONFIG_IXGBE_DCB | |
2817 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2818 | #else | |
2819 | static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2820 | #endif | |
2821 | { | |
2822 | int i; | |
2823 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
2824 | ||
2825 | if (adapter->ixgbe_ieee_pfc) | |
2826 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
2827 | ||
2828 | /* | |
2829 | * We should set the drop enable bit if: | |
2830 | * SR-IOV is enabled | |
2831 | * or | |
2832 | * Number of Rx queues > 1 and flow control is disabled | |
2833 | * | |
2834 | * This allows us to avoid head of line blocking for security | |
2835 | * and performance reasons. | |
2836 | */ | |
2837 | if (adapter->num_vfs || (adapter->num_rx_queues > 1 && | |
2838 | !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { | |
2839 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2840 | ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); | |
2841 | } else { | |
2842 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2843 | ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); | |
2844 | } | |
2845 | } | |
2846 | ||
e8e26350 | 2847 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2848 | |
a6616b42 | 2849 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2850 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2851 | { |
45e9baa5 | 2852 | struct ixgbe_hw *hw = &adapter->hw; |
cc41ac7c | 2853 | u32 srrctl; |
bf29ee6c | 2854 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2855 | |
45e9baa5 AD |
2856 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2857 | u16 mask = adapter->ring_feature[RING_F_RSS].mask; | |
cc41ac7c | 2858 | |
45e9baa5 AD |
2859 | /* |
2860 | * if VMDq is not active we must program one srrctl register | |
2861 | * per RSS queue since we have enabled RDRXCTL.MVMEN | |
2862 | */ | |
2863 | reg_idx &= mask; | |
2864 | } | |
cc41ac7c | 2865 | |
45e9baa5 AD |
2866 | /* configure header buffer length, needed for RSC */ |
2867 | srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |
afafd5b0 | 2868 | |
45e9baa5 | 2869 | /* configure the packet buffer length */ |
f800326d AD |
2870 | #if PAGE_SIZE > IXGBE_MAX_RXBUFFER |
2871 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
afafd5b0 | 2872 | #else |
f800326d | 2873 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
afafd5b0 | 2874 | #endif |
45e9baa5 AD |
2875 | |
2876 | /* configure descriptor type */ | |
f800326d | 2877 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2878 | |
45e9baa5 | 2879 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2880 | } |
9a799d71 | 2881 | |
05abb126 | 2882 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2883 | { |
05abb126 AD |
2884 | struct ixgbe_hw *hw = &adapter->hw; |
2885 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2886 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2887 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2888 | u32 mrqc = 0, reta = 0; |
2889 | u32 rxcsum; | |
2890 | int i, j; | |
671c0adb AD |
2891 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; |
2892 | ||
671c0adb AD |
2893 | /* |
2894 | * Program table for at least 2 queues w/ SR-IOV so that VFs can | |
2895 | * make full use of any rings they may have. We will use the | |
2896 | * PSRTYPE register to control how many rings we use within the PF. | |
2897 | */ | |
2898 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) | |
2899 | rss_i = 2; | |
0cefafad | 2900 | |
05abb126 AD |
2901 | /* Fill out hash function seeds */ |
2902 | for (i = 0; i < 10; i++) | |
2903 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2904 | ||
2905 | /* Fill out redirection table */ | |
2906 | for (i = 0, j = 0; i < 128; i++, j++) { | |
671c0adb | 2907 | if (j == rss_i) |
05abb126 AD |
2908 | j = 0; |
2909 | /* reta = 4-byte sliding window of | |
2910 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2911 | reta = (reta << 8) | (j * 0x11); | |
2912 | if ((i & 3) == 3) | |
2913 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2914 | } | |
0cefafad | 2915 | |
05abb126 AD |
2916 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2917 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2918 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2919 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2920 | ||
671c0adb | 2921 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
fbe7ca7f | 2922 | if (adapter->ring_feature[RING_F_RSS].mask) |
671c0adb | 2923 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 | 2924 | } else { |
671c0adb AD |
2925 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
2926 | ||
2927 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
2928 | if (tcs > 4) | |
2929 | mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ | |
2930 | else if (tcs > 1) | |
2931 | mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ | |
2932 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
2933 | mrqc = IXGBE_MRQC_VMDQRSS32EN; | |
8b1c0b24 | 2934 | else |
671c0adb AD |
2935 | mrqc = IXGBE_MRQC_VMDQRSS64EN; |
2936 | } else { | |
2937 | if (tcs > 4) | |
8b1c0b24 | 2938 | mrqc = IXGBE_MRQC_RTRSS8TCEN; |
671c0adb AD |
2939 | else if (tcs > 1) |
2940 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2941 | else | |
2942 | mrqc = IXGBE_MRQC_RSSEN; | |
8b1c0b24 | 2943 | } |
0cefafad JB |
2944 | } |
2945 | ||
05abb126 | 2946 | /* Perform hash on these packet types */ |
671c0adb AD |
2947 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2948 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | | |
2949 | IXGBE_MRQC_RSS_FIELD_IPV6 | | |
2950 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
05abb126 | 2951 | |
ef6afc0c AD |
2952 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
2953 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; | |
2954 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) | |
2955 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
2956 | ||
05abb126 | 2957 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
0cefafad JB |
2958 | } |
2959 | ||
bb5a9ad2 NS |
2960 | /** |
2961 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2962 | * @adapter: address of board private structure | |
2963 | * @index: index of ring to set | |
bb5a9ad2 | 2964 | **/ |
082757af | 2965 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2966 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2967 | { |
bb5a9ad2 | 2968 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2969 | u32 rscctrl; |
bf29ee6c | 2970 | u8 reg_idx = ring->reg_idx; |
7367096a | 2971 | |
7d637bcc | 2972 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2973 | return; |
bb5a9ad2 | 2974 | |
7367096a | 2975 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
2976 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2977 | /* | |
2978 | * we must limit the number of descriptors so that the | |
2979 | * total size of max desc * buf_len is not greater | |
642c680e | 2980 | * than 65536 |
bb5a9ad2 | 2981 | */ |
f800326d AD |
2982 | #if (PAGE_SIZE <= 8192) |
2983 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2984 | #elif (PAGE_SIZE <= 16384) | |
2985 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
bb5a9ad2 | 2986 | #else |
f800326d | 2987 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; |
bb5a9ad2 | 2988 | #endif |
7367096a | 2989 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2990 | } |
2991 | ||
9e10e045 AD |
2992 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2993 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2994 | struct ixgbe_ring *ring) | |
2995 | { | |
2996 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
2997 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
2998 | u32 rxdctl; | |
bf29ee6c | 2999 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
3000 | |
3001 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3002 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3003 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3004 | return; | |
3005 | ||
3006 | do { | |
032b4325 | 3007 | usleep_range(1000, 2000); |
9e10e045 AD |
3008 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3009 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3010 | ||
3011 | if (!wait_loop) { | |
3012 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3013 | "the polling period\n", reg_idx); | |
3014 | } | |
3015 | } | |
3016 | ||
2d39d576 YZ |
3017 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3018 | struct ixgbe_ring *ring) | |
3019 | { | |
3020 | struct ixgbe_hw *hw = &adapter->hw; | |
3021 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3022 | u32 rxdctl; | |
3023 | u8 reg_idx = ring->reg_idx; | |
3024 | ||
3025 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3026 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3027 | ||
3028 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3029 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3030 | ||
3031 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3032 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3033 | return; | |
3034 | ||
3035 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3036 | do { | |
3037 | udelay(10); | |
3038 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3039 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3040 | ||
3041 | if (!wait_loop) { | |
3042 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3043 | "the polling period\n", reg_idx); | |
3044 | } | |
3045 | } | |
3046 | ||
84418e3b AD |
3047 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3048 | struct ixgbe_ring *ring) | |
acd37177 AD |
3049 | { |
3050 | struct ixgbe_hw *hw = &adapter->hw; | |
3051 | u64 rdba = ring->dma; | |
9e10e045 | 3052 | u32 rxdctl; |
bf29ee6c | 3053 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3054 | |
9e10e045 AD |
3055 | /* disable queue to avoid issues while updating state */ |
3056 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3057 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3058 | |
acd37177 AD |
3059 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3060 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3061 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3062 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3063 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3064 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3065 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3066 | |
3067 | ixgbe_configure_srrctl(adapter, ring); | |
3068 | ixgbe_configure_rscctl(adapter, ring); | |
3069 | ||
e9f98072 GR |
3070 | /* If operating in IOV mode set RLPML for X540 */ |
3071 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3072 | hw->mac.type == ixgbe_mac_X540) { | |
3073 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3074 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3075 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3076 | } | |
3077 | ||
9e10e045 AD |
3078 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3079 | /* | |
3080 | * enable cache line friendly hardware writes: | |
3081 | * PTHRESH=32 descriptors (half the internal cache), | |
3082 | * this also removes ugly rx_no_buffer_count increment | |
3083 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3084 | * WTHRESH=8 burst writeback up to two cache lines | |
3085 | */ | |
3086 | rxdctl &= ~0x3FFFFF; | |
3087 | rxdctl |= 0x080420; | |
3088 | } | |
3089 | ||
3090 | /* enable receive descriptor ring */ | |
3091 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3092 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3093 | ||
3094 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3095 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3096 | } |
3097 | ||
48654521 AD |
3098 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3099 | { | |
3100 | struct ixgbe_hw *hw = &adapter->hw; | |
fbe7ca7f | 3101 | int rss_i = adapter->ring_feature[RING_F_RSS].indices; |
48654521 AD |
3102 | int p; |
3103 | ||
3104 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3105 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3106 | IXGBE_PSRTYPE_UDPHDR | |
3107 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3108 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3109 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3110 | |
3111 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3112 | return; | |
3113 | ||
fbe7ca7f AD |
3114 | if (rss_i > 3) |
3115 | psrtype |= 2 << 29; | |
3116 | else if (rss_i > 1) | |
3117 | psrtype |= 1 << 29; | |
48654521 AD |
3118 | |
3119 | for (p = 0; p < adapter->num_rx_pools; p++) | |
1d9c0bfd | 3120 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)), |
48654521 AD |
3121 | psrtype); |
3122 | } | |
3123 | ||
f5b4a52e AD |
3124 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3125 | { | |
3126 | struct ixgbe_hw *hw = &adapter->hw; | |
f5b4a52e | 3127 | u32 reg_offset, vf_shift; |
435b19f6 | 3128 | u32 gcr_ext, vmdctl; |
de4c7f65 | 3129 | int i; |
f5b4a52e AD |
3130 | |
3131 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3132 | return; | |
3133 | ||
3134 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
435b19f6 AD |
3135 | vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; |
3136 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
1d9c0bfd | 3137 | vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; |
435b19f6 AD |
3138 | vmdctl |= IXGBE_VT_CTL_REPLEN; |
3139 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
f5b4a52e | 3140 | |
1d9c0bfd AD |
3141 | vf_shift = VMDQ_P(0) % 32; |
3142 | reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; | |
f5b4a52e AD |
3143 | |
3144 | /* Enable only the PF's pool for Tx/Rx */ | |
435b19f6 AD |
3145 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); |
3146 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); | |
3147 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); | |
3148 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); | |
f5b4a52e AD |
3149 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); |
3150 | ||
3151 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
1d9c0bfd | 3152 | hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); |
f5b4a52e AD |
3153 | |
3154 | /* | |
3155 | * Set up VF register offsets for selected VT Mode, | |
3156 | * i.e. 32 or 64 VFs for SR-IOV | |
3157 | */ | |
73079ea0 AD |
3158 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { |
3159 | case IXGBE_82599_VMDQ_8Q_MASK: | |
3160 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; | |
3161 | break; | |
3162 | case IXGBE_82599_VMDQ_4Q_MASK: | |
3163 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; | |
3164 | break; | |
3165 | default: | |
3166 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; | |
3167 | break; | |
3168 | } | |
3169 | ||
f5b4a52e AD |
3170 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); |
3171 | ||
3172 | /* enable Tx loopback for VF/PF communication */ | |
3173 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
435b19f6 | 3174 | |
a985b6c3 | 3175 | /* Enable MAC Anti-Spoofing */ |
435b19f6 | 3176 | hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), |
a985b6c3 | 3177 | adapter->num_vfs); |
de4c7f65 GR |
3178 | /* For VFs that have spoof checking turned off */ |
3179 | for (i = 0; i < adapter->num_vfs; i++) { | |
3180 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3181 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3182 | } | |
f5b4a52e AD |
3183 | } |
3184 | ||
477de6ed | 3185 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3186 | { |
9a799d71 AK |
3187 | struct ixgbe_hw *hw = &adapter->hw; |
3188 | struct net_device *netdev = adapter->netdev; | |
3189 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3190 | struct ixgbe_ring *rx_ring; |
3191 | int i; | |
3192 | u32 mhadd, hlreg0; | |
48654521 | 3193 | |
63f39bd1 | 3194 | #ifdef IXGBE_FCOE |
477de6ed AD |
3195 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3196 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3197 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3198 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3199 | |
477de6ed AD |
3200 | #endif /* IXGBE_FCOE */ |
3201 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3202 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3203 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3204 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3205 | ||
3206 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3207 | } | |
3208 | ||
919e78a6 AD |
3209 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
3210 | max_frame += VLAN_HLEN; | |
3211 | ||
477de6ed AD |
3212 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
3213 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3214 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3215 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3216 | |
0cefafad JB |
3217 | /* |
3218 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3219 | * the Base and Length of the Rx Descriptor Ring | |
3220 | */ | |
9a799d71 | 3221 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3222 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3223 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3224 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3225 | else |
7d637bcc | 3226 | clear_ring_rsc_enabled(rx_ring); |
477de6ed | 3227 | } |
477de6ed AD |
3228 | } |
3229 | ||
7367096a AD |
3230 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3231 | { | |
3232 | struct ixgbe_hw *hw = &adapter->hw; | |
3233 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3234 | ||
3235 | switch (hw->mac.type) { | |
3236 | case ixgbe_mac_82598EB: | |
3237 | /* | |
3238 | * For VMDq support of different descriptor types or | |
3239 | * buffer sizes through the use of multiple SRRCTL | |
3240 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3241 | * | |
3242 | * also, the manual doesn't mention it clearly but DCA hints | |
3243 | * will only use queue 0's tags unless this bit is set. Side | |
3244 | * effects of setting this bit are only that SRRCTL must be | |
3245 | * fully programmed [0..15] | |
3246 | */ | |
3247 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3248 | break; | |
3249 | case ixgbe_mac_82599EB: | |
b93a2226 | 3250 | case ixgbe_mac_X540: |
7367096a AD |
3251 | /* Disable RSC for ACK packets */ |
3252 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3253 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3254 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3255 | /* hardware requires some bits to be set by default */ | |
3256 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3257 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3258 | break; | |
3259 | default: | |
3260 | /* We should do nothing since we don't know this hardware */ | |
3261 | return; | |
3262 | } | |
3263 | ||
3264 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3265 | } | |
3266 | ||
477de6ed AD |
3267 | /** |
3268 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3269 | * @adapter: board private structure | |
3270 | * | |
3271 | * Configure the Rx unit of the MAC after a reset. | |
3272 | **/ | |
3273 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3274 | { | |
3275 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3276 | int i; |
3277 | u32 rxctrl; | |
477de6ed AD |
3278 | |
3279 | /* disable receives while setting up the descriptors */ | |
3280 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3281 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3282 | ||
3283 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3284 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3285 | |
9e10e045 | 3286 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3287 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3288 | |
477de6ed AD |
3289 | /* set_rx_buffer_len must be called before ring initialization */ |
3290 | ixgbe_set_rx_buffer_len(adapter); | |
3291 | ||
3292 | /* | |
3293 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3294 | * the Base and Length of the Rx Descriptor Ring | |
3295 | */ | |
9e10e045 AD |
3296 | for (i = 0; i < adapter->num_rx_queues; i++) |
3297 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3298 | |
9e10e045 AD |
3299 | /* disable drop enable for 82598 parts */ |
3300 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3301 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3302 | ||
3303 | /* enable all receives */ | |
3304 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3305 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3306 | } |
3307 | ||
8e586137 | 3308 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3309 | { |
3310 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3311 | struct ixgbe_hw *hw = &adapter->hw; | |
3312 | ||
3313 | /* add VID to filter table */ | |
1d9c0bfd | 3314 | hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); |
f62bbb5e | 3315 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3316 | |
3317 | return 0; | |
068c89b0 DS |
3318 | } |
3319 | ||
8e586137 | 3320 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3321 | { |
3322 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3323 | struct ixgbe_hw *hw = &adapter->hw; | |
3324 | ||
068c89b0 | 3325 | /* remove VID from filter table */ |
1d9c0bfd | 3326 | hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); |
f62bbb5e | 3327 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3328 | |
3329 | return 0; | |
068c89b0 DS |
3330 | } |
3331 | ||
5f6c0181 JB |
3332 | /** |
3333 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3334 | * @adapter: driver data | |
3335 | */ | |
3336 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3337 | { | |
3338 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3339 | u32 vlnctrl; |
3340 | ||
3341 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3342 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3343 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3344 | } | |
3345 | ||
3346 | /** | |
3347 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3348 | * @adapter: driver data | |
3349 | */ | |
3350 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3351 | { | |
3352 | struct ixgbe_hw *hw = &adapter->hw; | |
3353 | u32 vlnctrl; | |
3354 | ||
3355 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3356 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3357 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3358 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3359 | } | |
3360 | ||
3361 | /** | |
3362 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3363 | * @adapter: driver data | |
3364 | */ | |
3365 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3366 | { | |
3367 | struct ixgbe_hw *hw = &adapter->hw; | |
3368 | u32 vlnctrl; | |
5f6c0181 JB |
3369 | int i, j; |
3370 | ||
3371 | switch (hw->mac.type) { | |
3372 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3373 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3374 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3375 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3376 | break; | |
3377 | case ixgbe_mac_82599EB: | |
b93a2226 | 3378 | case ixgbe_mac_X540: |
5f6c0181 JB |
3379 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3380 | j = adapter->rx_ring[i]->reg_idx; | |
3381 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3382 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3383 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3384 | } | |
3385 | break; | |
3386 | default: | |
3387 | break; | |
3388 | } | |
3389 | } | |
3390 | ||
3391 | /** | |
f62bbb5e | 3392 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3393 | * @adapter: driver data |
3394 | */ | |
f62bbb5e | 3395 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3396 | { |
3397 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3398 | u32 vlnctrl; |
5f6c0181 JB |
3399 | int i, j; |
3400 | ||
3401 | switch (hw->mac.type) { | |
3402 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3403 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3404 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3405 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3406 | break; | |
3407 | case ixgbe_mac_82599EB: | |
b93a2226 | 3408 | case ixgbe_mac_X540: |
5f6c0181 JB |
3409 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3410 | j = adapter->rx_ring[i]->reg_idx; | |
3411 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3412 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3413 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3414 | } | |
3415 | break; | |
3416 | default: | |
3417 | break; | |
3418 | } | |
3419 | } | |
3420 | ||
9a799d71 AK |
3421 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3422 | { | |
f62bbb5e | 3423 | u16 vid; |
9a799d71 | 3424 | |
f62bbb5e JG |
3425 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3426 | ||
3427 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3428 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3429 | } |
3430 | ||
2850062a AD |
3431 | /** |
3432 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3433 | * @netdev: network interface device structure | |
3434 | * | |
3435 | * Writes unicast address list to the RAR table. | |
3436 | * Returns: -ENOMEM on failure/insufficient address space | |
3437 | * 0 on no addresses written | |
3438 | * X on writing X addresses to the RAR table | |
3439 | **/ | |
3440 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3441 | { | |
3442 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3443 | struct ixgbe_hw *hw = &adapter->hw; | |
95447461 | 3444 | unsigned int rar_entries = hw->mac.num_rar_entries - 1; |
2850062a AD |
3445 | int count = 0; |
3446 | ||
95447461 JF |
3447 | /* In SR-IOV mode significantly less RAR entries are available */ |
3448 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3449 | rar_entries = IXGBE_MAX_PF_MACVLANS - 1; | |
3450 | ||
2850062a AD |
3451 | /* return ENOMEM indicating insufficient memory for addresses */ |
3452 | if (netdev_uc_count(netdev) > rar_entries) | |
3453 | return -ENOMEM; | |
3454 | ||
95447461 | 3455 | if (!netdev_uc_empty(netdev)) { |
2850062a AD |
3456 | struct netdev_hw_addr *ha; |
3457 | /* return error if we do not support writing to RAR table */ | |
3458 | if (!hw->mac.ops.set_rar) | |
3459 | return -ENOMEM; | |
3460 | ||
3461 | netdev_for_each_uc_addr(ha, netdev) { | |
3462 | if (!rar_entries) | |
3463 | break; | |
3464 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
1d9c0bfd | 3465 | VMDQ_P(0), IXGBE_RAH_AV); |
2850062a AD |
3466 | count++; |
3467 | } | |
3468 | } | |
3469 | /* write the addresses in reverse order to avoid write combining */ | |
3470 | for (; rar_entries > 0 ; rar_entries--) | |
3471 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3472 | ||
3473 | return count; | |
3474 | } | |
3475 | ||
9a799d71 | 3476 | /** |
2c5645cf | 3477 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3478 | * @netdev: network interface device structure |
3479 | * | |
2c5645cf CL |
3480 | * The set_rx_method entry point is called whenever the unicast/multicast |
3481 | * address list or the network interface flags are updated. This routine is | |
3482 | * responsible for configuring the hardware for proper unicast, multicast and | |
3483 | * promiscuous mode. | |
9a799d71 | 3484 | **/ |
7f870475 | 3485 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3486 | { |
3487 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3488 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3489 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3490 | int count; | |
9a799d71 AK |
3491 | |
3492 | /* Check for Promiscuous and All Multicast modes */ | |
3493 | ||
3494 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3495 | ||
f5dc442b | 3496 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3497 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3498 | fctrl |= IXGBE_FCTRL_BAM; |
3499 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3500 | fctrl |= IXGBE_FCTRL_PMCF; | |
3501 | ||
2850062a AD |
3502 | /* clear the bits we are changing the status of */ |
3503 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3504 | ||
9a799d71 | 3505 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3506 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3507 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3508 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3509 | /* don't hardware filter vlans in promisc mode */ |
3510 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3511 | } else { |
746b9f02 PM |
3512 | if (netdev->flags & IFF_ALLMULTI) { |
3513 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3514 | vmolr |= IXGBE_VMOLR_MPE; |
3515 | } else { | |
3516 | /* | |
3517 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3518 | * then we should just turn on promiscuous mode so |
2850062a AD |
3519 | * that we can at least receive multicast traffic |
3520 | */ | |
3521 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3522 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3523 | } |
5f6c0181 | 3524 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3525 | hw->addr_ctrl.user_set_promisc = false; |
9dcb373c JF |
3526 | } |
3527 | ||
3528 | /* | |
3529 | * Write addresses to available RAR registers, if there is not | |
3530 | * sufficient space to store all the addresses then enable | |
3531 | * unicast promiscuous mode | |
3532 | */ | |
3533 | count = ixgbe_write_uc_addr_list(netdev); | |
3534 | if (count < 0) { | |
3535 | fctrl |= IXGBE_FCTRL_UPE; | |
3536 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
3537 | } |
3538 | ||
1d9c0bfd | 3539 | if (adapter->num_vfs) |
1cdd1ec8 | 3540 | ixgbe_restore_vf_multicasts(adapter); |
1d9c0bfd AD |
3541 | |
3542 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3543 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & | |
2850062a AD |
3544 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | |
3545 | IXGBE_VMOLR_ROPE); | |
1d9c0bfd | 3546 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); |
2850062a AD |
3547 | } |
3548 | ||
3f2d1c0f BG |
3549 | /* This is useful for sniffing bad packets. */ |
3550 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3551 | /* UPE and MPE will be handled by normal PROMISC logic | |
3552 | * in e1000e_set_rx_mode */ | |
3553 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3554 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3555 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3556 | ||
3557 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3558 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3559 | } | |
3560 | ||
2850062a | 3561 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3562 | |
3563 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3564 | ixgbe_vlan_strip_enable(adapter); | |
3565 | else | |
3566 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3567 | } |
3568 | ||
021230d4 AV |
3569 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3570 | { | |
3571 | int q_idx; | |
021230d4 | 3572 | |
49c7ffbe AD |
3573 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3574 | napi_enable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3575 | } |
3576 | ||
3577 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3578 | { | |
3579 | int q_idx; | |
021230d4 | 3580 | |
49c7ffbe AD |
3581 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3582 | napi_disable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3583 | } |
3584 | ||
7a6b6f51 | 3585 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c | 3586 | /** |
2f90b865 AD |
3587 | * ixgbe_configure_dcb - Configure DCB hardware |
3588 | * @adapter: ixgbe adapter struct | |
3589 | * | |
3590 | * This is called by the driver on open to configure the DCB hardware. | |
3591 | * This is also called by the gennetlink interface when reconfiguring | |
3592 | * the DCB state. | |
3593 | */ | |
3594 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3595 | { | |
3596 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3597 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3598 | |
67ebd791 AD |
3599 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3600 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3601 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3602 | return; | |
3603 | } | |
3604 | ||
3605 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3606 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3607 | ||
2f90b865 | 3608 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 | 3609 | |
971060b1 | 3610 | #ifdef IXGBE_FCOE |
b120818e JF |
3611 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3612 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3613 | #endif |
b120818e JF |
3614 | |
3615 | /* reconfigure the hardware */ | |
3616 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3617 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3618 | DCB_TX_CONFIG); | |
3619 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3620 | DCB_RX_CONFIG); | |
3621 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3622 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3623 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3624 | adapter->ixgbe_ieee_ets, | |
3625 | max_frame); | |
3626 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3627 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3628 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3629 | } |
8187cd48 JF |
3630 | |
3631 | /* Enable RSS Hash per TC */ | |
3632 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4ae63730 AD |
3633 | u32 msb = 0; |
3634 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; | |
8187cd48 | 3635 | |
d411a936 AD |
3636 | while (rss_i) { |
3637 | msb++; | |
3638 | rss_i >>= 1; | |
3639 | } | |
8187cd48 | 3640 | |
4ae63730 AD |
3641 | /* write msb to all 8 TCs in one write */ |
3642 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); | |
8187cd48 | 3643 | } |
2f90b865 | 3644 | } |
9da712d2 JF |
3645 | #endif |
3646 | ||
3647 | /* Additional bittime to account for IXGBE framing */ | |
3648 | #define IXGBE_ETH_FRAMING 20 | |
3649 | ||
49ce9c2c | 3650 | /** |
9da712d2 JF |
3651 | * ixgbe_hpbthresh - calculate high water mark for flow control |
3652 | * | |
3653 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3654 | * @pb: packet buffer to calculate |
9da712d2 JF |
3655 | */ |
3656 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3657 | { | |
3658 | struct ixgbe_hw *hw = &adapter->hw; | |
3659 | struct net_device *dev = adapter->netdev; | |
3660 | int link, tc, kb, marker; | |
3661 | u32 dv_id, rx_pba; | |
3662 | ||
3663 | /* Calculate max LAN frame size */ | |
3664 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3665 | ||
3666 | #ifdef IXGBE_FCOE | |
3667 | /* FCoE traffic class uses FCOE jumbo frames */ | |
800bd607 AD |
3668 | if ((dev->features & NETIF_F_FCOE_MTU) && |
3669 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
3670 | (pb == ixgbe_fcoe_get_tc(adapter))) | |
3671 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9da712d2 JF |
3672 | |
3673 | #endif | |
9da712d2 JF |
3674 | /* Calculate delay value for device */ |
3675 | switch (hw->mac.type) { | |
3676 | case ixgbe_mac_X540: | |
3677 | dv_id = IXGBE_DV_X540(link, tc); | |
3678 | break; | |
3679 | default: | |
3680 | dv_id = IXGBE_DV(link, tc); | |
3681 | break; | |
3682 | } | |
3683 | ||
3684 | /* Loopback switch introduces additional latency */ | |
3685 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3686 | dv_id += IXGBE_B2BT(tc); | |
3687 | ||
3688 | /* Delay value is calculated in bit times convert to KB */ | |
3689 | kb = IXGBE_BT2KB(dv_id); | |
3690 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3691 | ||
3692 | marker = rx_pba - kb; | |
3693 | ||
3694 | /* It is possible that the packet buffer is not large enough | |
3695 | * to provide required headroom. In this case throw an error | |
3696 | * to user and a do the best we can. | |
3697 | */ | |
3698 | if (marker < 0) { | |
3699 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3700 | "headroom to support flow control." | |
3701 | "Decrease MTU or number of traffic classes\n", pb); | |
3702 | marker = tc + 1; | |
3703 | } | |
3704 | ||
3705 | return marker; | |
3706 | } | |
3707 | ||
49ce9c2c | 3708 | /** |
9da712d2 JF |
3709 | * ixgbe_lpbthresh - calculate low water mark for for flow control |
3710 | * | |
3711 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3712 | * @pb: packet buffer to calculate |
9da712d2 JF |
3713 | */ |
3714 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3715 | { | |
3716 | struct ixgbe_hw *hw = &adapter->hw; | |
3717 | struct net_device *dev = adapter->netdev; | |
3718 | int tc; | |
3719 | u32 dv_id; | |
3720 | ||
3721 | /* Calculate max LAN frame size */ | |
3722 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3723 | ||
3724 | /* Calculate delay value for device */ | |
3725 | switch (hw->mac.type) { | |
3726 | case ixgbe_mac_X540: | |
3727 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3728 | break; | |
3729 | default: | |
3730 | dv_id = IXGBE_LOW_DV(tc); | |
3731 | break; | |
3732 | } | |
3733 | ||
3734 | /* Delay value is calculated in bit times convert to KB */ | |
3735 | return IXGBE_BT2KB(dv_id); | |
3736 | } | |
3737 | ||
3738 | /* | |
3739 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3740 | */ | |
3741 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3742 | { | |
3743 | struct ixgbe_hw *hw = &adapter->hw; | |
3744 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3745 | int i; | |
3746 | ||
3747 | if (!num_tc) | |
3748 | num_tc = 1; | |
3749 | ||
3750 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3751 | ||
3752 | for (i = 0; i < num_tc; i++) { | |
3753 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3754 | ||
3755 | /* Low water marks must not be larger than high water marks */ | |
3756 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3757 | hw->fc.low_water = 0; | |
3758 | } | |
3759 | } | |
3760 | ||
80605c65 JF |
3761 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3762 | { | |
80605c65 | 3763 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3764 | int hdrm; |
3765 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3766 | |
3767 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3768 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3769 | hdrm = 32 << adapter->fdir_pballoc; |
3770 | else | |
3771 | hdrm = 0; | |
80605c65 | 3772 | |
f7e1027f | 3773 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3774 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3775 | } |
3776 | ||
e4911d57 AD |
3777 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3778 | { | |
3779 | struct ixgbe_hw *hw = &adapter->hw; | |
3780 | struct hlist_node *node, *node2; | |
3781 | struct ixgbe_fdir_filter *filter; | |
3782 | ||
3783 | spin_lock(&adapter->fdir_perfect_lock); | |
3784 | ||
3785 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3786 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3787 | ||
3788 | hlist_for_each_entry_safe(filter, node, node2, | |
3789 | &adapter->fdir_filter_list, fdir_node) { | |
3790 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3791 | &filter->filter, |
3792 | filter->sw_idx, | |
3793 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3794 | IXGBE_FDIR_DROP_QUEUE : | |
3795 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3796 | } |
3797 | ||
3798 | spin_unlock(&adapter->fdir_perfect_lock); | |
3799 | } | |
3800 | ||
9a799d71 AK |
3801 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3802 | { | |
d2f5e7f3 AS |
3803 | struct ixgbe_hw *hw = &adapter->hw; |
3804 | ||
80605c65 | 3805 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3806 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3807 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3808 | #endif |
9a799d71 | 3809 | |
4c1d7b4b | 3810 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3811 | ixgbe_restore_vlan(adapter); |
3812 | ||
d2f5e7f3 AS |
3813 | switch (hw->mac.type) { |
3814 | case ixgbe_mac_82599EB: | |
3815 | case ixgbe_mac_X540: | |
3816 | hw->mac.ops.disable_rx_buff(hw); | |
3817 | break; | |
3818 | default: | |
3819 | break; | |
3820 | } | |
3821 | ||
c4cf55e5 | 3822 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3823 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3824 | adapter->fdir_pballoc); | |
e4911d57 AD |
3825 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3826 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3827 | adapter->fdir_pballoc); | |
3828 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3829 | } |
4c1d7b4b | 3830 | |
d2f5e7f3 AS |
3831 | switch (hw->mac.type) { |
3832 | case ixgbe_mac_82599EB: | |
3833 | case ixgbe_mac_X540: | |
3834 | hw->mac.ops.enable_rx_buff(hw); | |
3835 | break; | |
3836 | default: | |
3837 | break; | |
3838 | } | |
3839 | ||
933d41f1 | 3840 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3841 | |
7c8ae65a AD |
3842 | #ifdef IXGBE_FCOE |
3843 | /* configure FCoE L2 filters, redirection table, and Rx control */ | |
3844 | ixgbe_configure_fcoe(adapter); | |
3845 | ||
3846 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
3847 | ixgbe_configure_tx(adapter); |
3848 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3849 | } |
3850 | ||
e8e26350 PW |
3851 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3852 | { | |
3853 | switch (hw->phy.type) { | |
3854 | case ixgbe_phy_sfp_avago: | |
3855 | case ixgbe_phy_sfp_ftl: | |
3856 | case ixgbe_phy_sfp_intel: | |
3857 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3858 | case ixgbe_phy_sfp_passive_tyco: |
3859 | case ixgbe_phy_sfp_passive_unknown: | |
3860 | case ixgbe_phy_sfp_active_unknown: | |
3861 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3862 | return true; |
8917b447 AD |
3863 | case ixgbe_phy_nl: |
3864 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3865 | return true; | |
e8e26350 PW |
3866 | default: |
3867 | return false; | |
3868 | } | |
3869 | } | |
3870 | ||
0ecc061d | 3871 | /** |
e8e26350 PW |
3872 | * ixgbe_sfp_link_config - set up SFP+ link |
3873 | * @adapter: pointer to private adapter struct | |
3874 | **/ | |
3875 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3876 | { | |
7086400d | 3877 | /* |
52f33af8 | 3878 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3879 | * is that an SFP was inserted/removed after the reset |
3880 | * but before SFP detection was enabled. As such the best | |
3881 | * solution is to just start searching as soon as we start | |
3882 | */ | |
3883 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3884 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3885 | |
7086400d | 3886 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3887 | } |
3888 | ||
3889 | /** | |
3890 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3891 | * @hw: pointer to private hardware struct |
3892 | * | |
3893 | * Returns 0 on success, negative on failure | |
3894 | **/ | |
e8e26350 | 3895 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3896 | { |
3897 | u32 autoneg; | |
8620a103 | 3898 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3899 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3900 | ||
3901 | if (hw->mac.ops.check_link) | |
3902 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3903 | ||
3904 | if (ret) | |
3905 | goto link_cfg_out; | |
3906 | ||
0b0c2b31 ET |
3907 | autoneg = hw->phy.autoneg_advertised; |
3908 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3909 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3910 | &negotiation); | |
0ecc061d PWJ |
3911 | if (ret) |
3912 | goto link_cfg_out; | |
3913 | ||
8620a103 MC |
3914 | if (hw->mac.ops.setup_link) |
3915 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3916 | link_cfg_out: |
3917 | return ret; | |
3918 | } | |
3919 | ||
a34bcfff | 3920 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3921 | { |
9a799d71 | 3922 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3923 | u32 gpie = 0; |
9a799d71 | 3924 | |
9b471446 | 3925 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3926 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3927 | IXGBE_GPIE_OCD; | |
3928 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3929 | /* |
3930 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3931 | * this saves a register write for every interrupt | |
3932 | */ | |
3933 | switch (hw->mac.type) { | |
3934 | case ixgbe_mac_82598EB: | |
3935 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3936 | break; | |
9b471446 | 3937 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3938 | case ixgbe_mac_X540: |
3939 | default: | |
9b471446 JB |
3940 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3941 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3942 | break; | |
3943 | } | |
3944 | } else { | |
021230d4 AV |
3945 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3946 | * specifically only auto mask tx and rx interrupts */ | |
3947 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3948 | } | |
9a799d71 | 3949 | |
a34bcfff AD |
3950 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3951 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3952 | ||
3953 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3954 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
73079ea0 AD |
3955 | |
3956 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { | |
3957 | case IXGBE_82599_VMDQ_8Q_MASK: | |
3958 | gpie |= IXGBE_GPIE_VTMODE_16; | |
3959 | break; | |
3960 | case IXGBE_82599_VMDQ_4Q_MASK: | |
3961 | gpie |= IXGBE_GPIE_VTMODE_32; | |
3962 | break; | |
3963 | default: | |
3964 | gpie |= IXGBE_GPIE_VTMODE_64; | |
3965 | break; | |
3966 | } | |
119fc60a MC |
3967 | } |
3968 | ||
5fdd31f9 | 3969 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
3970 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
3971 | switch (adapter->hw.mac.type) { | |
3972 | case ixgbe_mac_82599EB: | |
3973 | gpie |= IXGBE_SDP0_GPIEN; | |
3974 | break; | |
3975 | case ixgbe_mac_X540: | |
3976 | gpie |= IXGBE_EIMS_TS; | |
3977 | break; | |
3978 | default: | |
3979 | break; | |
3980 | } | |
3981 | } | |
5fdd31f9 | 3982 | |
a34bcfff AD |
3983 | /* Enable fan failure interrupt */ |
3984 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3985 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3986 | |
2698b208 | 3987 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3988 | gpie |= IXGBE_SDP1_GPIEN; |
3989 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3990 | } |
a34bcfff AD |
3991 | |
3992 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3993 | } | |
3994 | ||
c7ccde0f | 3995 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
3996 | { |
3997 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3998 | int err; |
a34bcfff AD |
3999 | u32 ctrl_ext; |
4000 | ||
4001 | ixgbe_get_hw_control(adapter); | |
4002 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 4003 | |
9a799d71 AK |
4004 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4005 | ixgbe_configure_msix(adapter); | |
4006 | else | |
4007 | ixgbe_configure_msi_and_legacy(adapter); | |
4008 | ||
c6ecf39a DS |
4009 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
4010 | if (hw->mac.ops.enable_tx_laser && | |
4011 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4012 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 4013 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
4014 | hw->mac.ops.enable_tx_laser(hw); |
4015 | ||
9a799d71 | 4016 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
4017 | ixgbe_napi_enable_all(adapter); |
4018 | ||
73c4b7cd AD |
4019 | if (ixgbe_is_sfp(hw)) { |
4020 | ixgbe_sfp_link_config(adapter); | |
4021 | } else { | |
4022 | err = ixgbe_non_sfp_link_config(hw); | |
4023 | if (err) | |
4024 | e_err(probe, "link_config FAILED %d\n", err); | |
4025 | } | |
4026 | ||
021230d4 AV |
4027 | /* clear any pending interrupts, may auto mask */ |
4028 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 4029 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 4030 | |
bf069c97 DS |
4031 | /* |
4032 | * If this adapter has a fan, check to see if we had a failure | |
4033 | * before we enabled the interrupt. | |
4034 | */ | |
4035 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
4036 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
4037 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 4038 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
4039 | } |
4040 | ||
1da100bb | 4041 | /* enable transmits */ |
477de6ed | 4042 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 4043 | |
9a799d71 AK |
4044 | /* bring the link up in the watchdog, this could race with our first |
4045 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
4046 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
4047 | adapter->link_check_timeout = jiffies; | |
7086400d | 4048 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
4049 | |
4050 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
4051 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
4052 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
4053 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
4054 | } |
4055 | ||
d4f80882 AV |
4056 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
4057 | { | |
4058 | WARN_ON(in_interrupt()); | |
7086400d AD |
4059 | /* put off any impending NetWatchDogTimeout */ |
4060 | adapter->netdev->trans_start = jiffies; | |
4061 | ||
d4f80882 | 4062 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 4063 | usleep_range(1000, 2000); |
d4f80882 | 4064 | ixgbe_down(adapter); |
5809a1ae GR |
4065 | /* |
4066 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
4067 | * back up to give the VFs time to respond to the reset. The | |
4068 | * two second wait is based upon the watchdog timer cycle in | |
4069 | * the VF driver. | |
4070 | */ | |
4071 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4072 | msleep(2000); | |
d4f80882 AV |
4073 | ixgbe_up(adapter); |
4074 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4075 | } | |
4076 | ||
c7ccde0f | 4077 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4078 | { |
4079 | /* hardware has been reset, we need to reload some things */ | |
4080 | ixgbe_configure(adapter); | |
4081 | ||
c7ccde0f | 4082 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4083 | } |
4084 | ||
4085 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4086 | { | |
c44ade9e | 4087 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4088 | int err; |
4089 | ||
7086400d AD |
4090 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4091 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4092 | usleep_range(1000, 2000); | |
4093 | ||
4094 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4095 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4096 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4097 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4098 | ||
8ca783ab | 4099 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4100 | switch (err) { |
4101 | case 0: | |
4102 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4103 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4104 | break; |
4105 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4106 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4107 | break; |
794caeb2 PWJ |
4108 | case IXGBE_ERR_EEPROM_VERSION: |
4109 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 4110 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 4111 | "Please be aware there may be issues associated with " |
849c4542 ET |
4112 | "your hardware. If you are experiencing problems " |
4113 | "please contact your Intel or hardware " | |
4114 | "representative who provided you with this " | |
4115 | "hardware.\n"); | |
794caeb2 | 4116 | break; |
da4dd0f7 | 4117 | default: |
849c4542 | 4118 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4119 | } |
9a799d71 | 4120 | |
7086400d AD |
4121 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4122 | ||
9a799d71 | 4123 | /* reprogram the RAR[0] in case user changed it. */ |
1d9c0bfd | 4124 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV); |
7fa7c9dc AD |
4125 | |
4126 | /* update SAN MAC vmdq pool selection */ | |
4127 | if (hw->mac.san_mac_rar_index) | |
4128 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
9a799d71 AK |
4129 | } |
4130 | ||
f800326d AD |
4131 | /** |
4132 | * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers | |
4133 | * @rx_ring: ring to setup | |
4134 | * | |
4135 | * On many IA platforms the L1 cache has a critical stride of 4K, this | |
4136 | * results in each receive buffer starting in the same cache set. To help | |
4137 | * reduce the pressure on this cache set we can interleave the offsets so | |
4138 | * that only every other buffer will be in the same cache set. | |
4139 | **/ | |
4140 | static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring) | |
4141 | { | |
4142 | struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info; | |
4143 | u16 i; | |
4144 | ||
4145 | for (i = 0; i < rx_ring->count; i += 2) { | |
4146 | rx_buffer[0].page_offset = 0; | |
4147 | rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring); | |
4148 | rx_buffer = &rx_buffer[2]; | |
4149 | } | |
4150 | } | |
4151 | ||
9a799d71 AK |
4152 | /** |
4153 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4154 | * @rx_ring: ring to free buffers from |
4155 | **/ | |
b6ec895e | 4156 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4157 | { |
b6ec895e | 4158 | struct device *dev = rx_ring->dev; |
9a799d71 | 4159 | unsigned long size; |
b6ec895e | 4160 | u16 i; |
9a799d71 | 4161 | |
84418e3b AD |
4162 | /* ring already cleared, nothing to do */ |
4163 | if (!rx_ring->rx_buffer_info) | |
4164 | return; | |
9a799d71 | 4165 | |
84418e3b | 4166 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4167 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4168 | struct ixgbe_rx_buffer *rx_buffer; |
4169 | ||
4170 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4171 | if (rx_buffer->skb) { | |
4172 | struct sk_buff *skb = rx_buffer->skb; | |
4173 | if (IXGBE_CB(skb)->page_released) { | |
4174 | dma_unmap_page(dev, | |
4175 | IXGBE_CB(skb)->dma, | |
4176 | ixgbe_rx_bufsz(rx_ring), | |
4177 | DMA_FROM_DEVICE); | |
4178 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4179 | } |
4180 | dev_kfree_skb(skb); | |
9a799d71 | 4181 | } |
f800326d AD |
4182 | rx_buffer->skb = NULL; |
4183 | if (rx_buffer->dma) | |
4184 | dma_unmap_page(dev, rx_buffer->dma, | |
4185 | ixgbe_rx_pg_size(rx_ring), | |
4186 | DMA_FROM_DEVICE); | |
4187 | rx_buffer->dma = 0; | |
4188 | if (rx_buffer->page) | |
dd411ec4 AD |
4189 | __free_pages(rx_buffer->page, |
4190 | ixgbe_rx_pg_order(rx_ring)); | |
f800326d | 4191 | rx_buffer->page = NULL; |
9a799d71 AK |
4192 | } |
4193 | ||
4194 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4195 | memset(rx_ring->rx_buffer_info, 0, size); | |
4196 | ||
f800326d AD |
4197 | ixgbe_init_rx_page_offset(rx_ring); |
4198 | ||
9a799d71 AK |
4199 | /* Zero out the descriptor ring */ |
4200 | memset(rx_ring->desc, 0, rx_ring->size); | |
4201 | ||
f800326d | 4202 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4203 | rx_ring->next_to_clean = 0; |
4204 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4205 | } |
4206 | ||
4207 | /** | |
4208 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4209 | * @tx_ring: ring to be cleaned |
4210 | **/ | |
b6ec895e | 4211 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4212 | { |
4213 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4214 | unsigned long size; | |
b6ec895e | 4215 | u16 i; |
9a799d71 | 4216 | |
84418e3b AD |
4217 | /* ring already cleared, nothing to do */ |
4218 | if (!tx_ring->tx_buffer_info) | |
4219 | return; | |
9a799d71 | 4220 | |
84418e3b | 4221 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4222 | for (i = 0; i < tx_ring->count; i++) { |
4223 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4224 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4225 | } |
4226 | ||
dad8a3b3 JF |
4227 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
4228 | ||
9a799d71 AK |
4229 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4230 | memset(tx_ring->tx_buffer_info, 0, size); | |
4231 | ||
4232 | /* Zero out the descriptor ring */ | |
4233 | memset(tx_ring->desc, 0, tx_ring->size); | |
4234 | ||
4235 | tx_ring->next_to_use = 0; | |
4236 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4237 | } |
4238 | ||
4239 | /** | |
021230d4 | 4240 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4241 | * @adapter: board private structure |
4242 | **/ | |
021230d4 | 4243 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4244 | { |
4245 | int i; | |
4246 | ||
021230d4 | 4247 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4248 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4249 | } |
4250 | ||
4251 | /** | |
021230d4 | 4252 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4253 | * @adapter: board private structure |
4254 | **/ | |
021230d4 | 4255 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4256 | { |
4257 | int i; | |
4258 | ||
021230d4 | 4259 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4260 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4261 | } |
4262 | ||
e4911d57 AD |
4263 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4264 | { | |
4265 | struct hlist_node *node, *node2; | |
4266 | struct ixgbe_fdir_filter *filter; | |
4267 | ||
4268 | spin_lock(&adapter->fdir_perfect_lock); | |
4269 | ||
4270 | hlist_for_each_entry_safe(filter, node, node2, | |
4271 | &adapter->fdir_filter_list, fdir_node) { | |
4272 | hlist_del(&filter->fdir_node); | |
4273 | kfree(filter); | |
4274 | } | |
4275 | adapter->fdir_filter_count = 0; | |
4276 | ||
4277 | spin_unlock(&adapter->fdir_perfect_lock); | |
4278 | } | |
4279 | ||
9a799d71 AK |
4280 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4281 | { | |
4282 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4283 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4284 | u32 rxctrl; |
bf29ee6c | 4285 | int i; |
9a799d71 AK |
4286 | |
4287 | /* signal that we are down to the interrupt handler */ | |
4288 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4289 | ||
4290 | /* disable receives */ | |
7f821875 JB |
4291 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4292 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4293 | |
2d39d576 YZ |
4294 | /* disable all enabled rx queues */ |
4295 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4296 | /* this call also flushes the previous write */ | |
4297 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4298 | ||
032b4325 | 4299 | usleep_range(10000, 20000); |
9a799d71 | 4300 | |
7f821875 JB |
4301 | netif_tx_stop_all_queues(netdev); |
4302 | ||
7086400d | 4303 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4304 | netif_carrier_off(netdev); |
4305 | netif_tx_disable(netdev); | |
4306 | ||
4307 | ixgbe_irq_disable(adapter); | |
4308 | ||
4309 | ixgbe_napi_disable_all(adapter); | |
4310 | ||
d034acf1 AD |
4311 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4312 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4313 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4314 | ||
4315 | del_timer_sync(&adapter->service_timer); | |
4316 | ||
34cecbbf | 4317 | if (adapter->num_vfs) { |
8e34d1aa AD |
4318 | /* Clear EITR Select mapping */ |
4319 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4320 | |
4321 | /* Mark all the VFs as inactive */ | |
4322 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4323 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4324 | |
34cecbbf AD |
4325 | /* ping all the active vfs to let them know we are going down */ |
4326 | ixgbe_ping_all_vfs(adapter); | |
4327 | ||
4328 | /* Disable all VFTE/VFRE TX/RX */ | |
4329 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4330 | } |
4331 | ||
7f821875 JB |
4332 | /* disable transmits in the hardware now that interrupts are off */ |
4333 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4334 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4335 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4336 | } |
34cecbbf AD |
4337 | |
4338 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4339 | switch (hw->mac.type) { |
4340 | case ixgbe_mac_82599EB: | |
b93a2226 | 4341 | case ixgbe_mac_X540: |
88512539 | 4342 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4343 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4344 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4345 | break; |
4346 | default: | |
4347 | break; | |
4348 | } | |
7f821875 | 4349 | |
6f4a0e45 PL |
4350 | if (!pci_channel_offline(adapter->pdev)) |
4351 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4352 | |
4353 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4354 | if (hw->mac.ops.disable_tx_laser && | |
4355 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4356 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4357 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4358 | hw->mac.ops.disable_tx_laser(hw); | |
4359 | ||
9a799d71 AK |
4360 | ixgbe_clean_all_tx_rings(adapter); |
4361 | ixgbe_clean_all_rx_rings(adapter); | |
4362 | ||
5dd2d332 | 4363 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4364 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4365 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4366 | #endif |
9a799d71 AK |
4367 | } |
4368 | ||
9a799d71 AK |
4369 | /** |
4370 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4371 | * @netdev: network interface device structure | |
4372 | **/ | |
4373 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4374 | { | |
4375 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4376 | ||
4377 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4378 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4379 | } |
4380 | ||
9a799d71 AK |
4381 | /** |
4382 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4383 | * @adapter: board private structure to initialize | |
4384 | * | |
4385 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4386 | * Fields are initialized based on PCI device information and | |
4387 | * OS network device settings (MTU size). | |
4388 | **/ | |
4389 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4390 | { | |
4391 | struct ixgbe_hw *hw = &adapter->hw; | |
4392 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4393 | unsigned int rss; |
7a6b6f51 | 4394 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4395 | int j; |
4396 | struct tc_configuration *tc; | |
4397 | #endif | |
021230d4 | 4398 | |
c44ade9e JB |
4399 | /* PCI config space info */ |
4400 | ||
4401 | hw->vendor_id = pdev->vendor; | |
4402 | hw->device_id = pdev->device; | |
4403 | hw->revision_id = pdev->revision; | |
4404 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4405 | hw->subsystem_device_id = pdev->subsystem_device; | |
4406 | ||
021230d4 | 4407 | /* Set capability flags */ |
3ed69d7e | 4408 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
c087663e | 4409 | adapter->ring_feature[RING_F_RSS].limit = rss; |
bd508178 AD |
4410 | switch (hw->mac.type) { |
4411 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
4412 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
4413 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
49c7ffbe | 4414 | adapter->max_q_vectors = MAX_Q_VECTORS_82598; |
bd508178 | 4415 | break; |
b93a2226 | 4416 | case ixgbe_mac_X540: |
4f51bf70 JK |
4417 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
4418 | case ixgbe_mac_82599EB: | |
49c7ffbe | 4419 | adapter->max_q_vectors = MAX_Q_VECTORS_82599; |
0c19d6af PWJ |
4420 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4421 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4422 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4423 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 | 4424 | /* Flow Director hash filters enabled */ |
45b9f509 | 4425 | adapter->atr_sample_rate = 20; |
c087663e | 4426 | adapter->ring_feature[RING_F_FDIR].limit = |
e8e9f696 | 4427 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 4428 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 4429 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4430 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4431 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
61a0f421 | 4432 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 4433 | /* Default traffic class to use for FCoE */ |
56075a98 | 4434 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4435 | #endif |
eacd73f7 | 4436 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
4437 | break; |
4438 | default: | |
4439 | break; | |
f8212f97 | 4440 | } |
2f90b865 | 4441 | |
7c8ae65a AD |
4442 | #ifdef IXGBE_FCOE |
4443 | /* FCoE support exists, always init the FCoE lock */ | |
4444 | spin_lock_init(&adapter->fcoe.lock); | |
4445 | ||
4446 | #endif | |
1fc5f038 AD |
4447 | /* n-tuple support exists, always init our spinlock */ |
4448 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4449 | ||
7a6b6f51 | 4450 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
4451 | switch (hw->mac.type) { |
4452 | case ixgbe_mac_X540: | |
4453 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
4454 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
4455 | break; | |
4456 | default: | |
4457 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
4458 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
4459 | break; | |
4460 | } | |
4461 | ||
2f90b865 AD |
4462 | /* Configure DCB traffic classes */ |
4463 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4464 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4465 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4466 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4467 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4468 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4469 | tc->dcb_pfc = pfc_disabled; | |
4470 | } | |
4de2a022 JF |
4471 | |
4472 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
4473 | tc = &adapter->dcb_cfg.tc_config[0]; | |
4474 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4475 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4476 | ||
2f90b865 AD |
4477 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
4478 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 4479 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 4480 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 4481 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
f525c6d2 JF |
4482 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, |
4483 | sizeof(adapter->temp_dcb_cfg)); | |
2f90b865 AD |
4484 | |
4485 | #endif | |
9a799d71 AK |
4486 | |
4487 | /* default flow control settings */ | |
cd7664f6 | 4488 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4489 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 4490 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
4491 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4492 | hw->fc.send_xon = true; | |
71fd570b | 4493 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4494 | |
99d74487 AD |
4495 | #ifdef CONFIG_PCI_IOV |
4496 | /* assign number of SR-IOV VFs */ | |
4497 | if (hw->mac.type != ixgbe_mac_82598EB) | |
4498 | adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs; | |
4499 | ||
4500 | #endif | |
30efa5a3 | 4501 | /* enable itr by default in dynamic mode */ |
f7554a2b | 4502 | adapter->rx_itr_setting = 1; |
f7554a2b | 4503 | adapter->tx_itr_setting = 1; |
30efa5a3 | 4504 | |
30efa5a3 JB |
4505 | /* set default ring sizes */ |
4506 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4507 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4508 | ||
bd198058 | 4509 | /* set default work limits */ |
59224555 | 4510 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 4511 | |
9a799d71 | 4512 | /* initialize eeprom parameters */ |
c44ade9e | 4513 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4514 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4515 | return -EIO; |
4516 | } | |
4517 | ||
9a799d71 AK |
4518 | set_bit(__IXGBE_DOWN, &adapter->state); |
4519 | ||
4520 | return 0; | |
4521 | } | |
4522 | ||
4523 | /** | |
4524 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 4525 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4526 | * |
4527 | * Return 0 on success, negative on failure | |
4528 | **/ | |
b6ec895e | 4529 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4530 | { |
b6ec895e | 4531 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
4532 | int orig_node = dev_to_node(dev); |
4533 | int numa_node = -1; | |
9a799d71 AK |
4534 | int size; |
4535 | ||
3a581073 | 4536 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
4537 | |
4538 | if (tx_ring->q_vector) | |
4539 | numa_node = tx_ring->q_vector->numa_node; | |
4540 | ||
4541 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4542 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 4543 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
4544 | if (!tx_ring->tx_buffer_info) |
4545 | goto err; | |
9a799d71 AK |
4546 | |
4547 | /* round up to nearest 4K */ | |
12207e49 | 4548 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4549 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4550 | |
de88eeeb AD |
4551 | set_dev_node(dev, numa_node); |
4552 | tx_ring->desc = dma_alloc_coherent(dev, | |
4553 | tx_ring->size, | |
4554 | &tx_ring->dma, | |
4555 | GFP_KERNEL); | |
4556 | set_dev_node(dev, orig_node); | |
4557 | if (!tx_ring->desc) | |
4558 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
4559 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4560 | if (!tx_ring->desc) |
4561 | goto err; | |
9a799d71 | 4562 | |
3a581073 JB |
4563 | tx_ring->next_to_use = 0; |
4564 | tx_ring->next_to_clean = 0; | |
9a799d71 | 4565 | return 0; |
e01c31a5 JB |
4566 | |
4567 | err: | |
4568 | vfree(tx_ring->tx_buffer_info); | |
4569 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 4570 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4571 | return -ENOMEM; |
9a799d71 AK |
4572 | } |
4573 | ||
69888674 AD |
4574 | /** |
4575 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4576 | * @adapter: board private structure | |
4577 | * | |
4578 | * If this function returns with an error, then it's possible one or | |
4579 | * more of the rings is populated (while the rest are not). It is the | |
4580 | * callers duty to clean those orphaned rings. | |
4581 | * | |
4582 | * Return 0 on success, negative on failure | |
4583 | **/ | |
4584 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4585 | { | |
4586 | int i, err = 0; | |
4587 | ||
4588 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 4589 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
4590 | if (!err) |
4591 | continue; | |
de3d5b94 | 4592 | |
396e799c | 4593 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
de3d5b94 | 4594 | goto err_setup_tx; |
69888674 AD |
4595 | } |
4596 | ||
de3d5b94 AD |
4597 | return 0; |
4598 | err_setup_tx: | |
4599 | /* rewind the index freeing the rings as we go */ | |
4600 | while (i--) | |
4601 | ixgbe_free_tx_resources(adapter->tx_ring[i]); | |
69888674 AD |
4602 | return err; |
4603 | } | |
4604 | ||
9a799d71 AK |
4605 | /** |
4606 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 4607 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4608 | * |
4609 | * Returns 0 on success, negative on failure | |
4610 | **/ | |
b6ec895e | 4611 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4612 | { |
b6ec895e | 4613 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
4614 | int orig_node = dev_to_node(dev); |
4615 | int numa_node = -1; | |
021230d4 | 4616 | int size; |
9a799d71 | 4617 | |
3a581073 | 4618 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
4619 | |
4620 | if (rx_ring->q_vector) | |
4621 | numa_node = rx_ring->q_vector->numa_node; | |
4622 | ||
4623 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4624 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 4625 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
4626 | if (!rx_ring->rx_buffer_info) |
4627 | goto err; | |
9a799d71 | 4628 | |
9a799d71 | 4629 | /* Round up to nearest 4K */ |
3a581073 JB |
4630 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4631 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4632 | |
de88eeeb AD |
4633 | set_dev_node(dev, numa_node); |
4634 | rx_ring->desc = dma_alloc_coherent(dev, | |
4635 | rx_ring->size, | |
4636 | &rx_ring->dma, | |
4637 | GFP_KERNEL); | |
4638 | set_dev_node(dev, orig_node); | |
4639 | if (!rx_ring->desc) | |
4640 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
4641 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
4642 | if (!rx_ring->desc) |
4643 | goto err; | |
9a799d71 | 4644 | |
3a581073 JB |
4645 | rx_ring->next_to_clean = 0; |
4646 | rx_ring->next_to_use = 0; | |
9a799d71 | 4647 | |
f800326d AD |
4648 | ixgbe_init_rx_page_offset(rx_ring); |
4649 | ||
9a799d71 | 4650 | return 0; |
b6ec895e AD |
4651 | err: |
4652 | vfree(rx_ring->rx_buffer_info); | |
4653 | rx_ring->rx_buffer_info = NULL; | |
4654 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 4655 | return -ENOMEM; |
9a799d71 AK |
4656 | } |
4657 | ||
69888674 AD |
4658 | /** |
4659 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4660 | * @adapter: board private structure | |
4661 | * | |
4662 | * If this function returns with an error, then it's possible one or | |
4663 | * more of the rings is populated (while the rest are not). It is the | |
4664 | * callers duty to clean those orphaned rings. | |
4665 | * | |
4666 | * Return 0 on success, negative on failure | |
4667 | **/ | |
69888674 AD |
4668 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
4669 | { | |
4670 | int i, err = 0; | |
4671 | ||
4672 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 4673 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
4674 | if (!err) |
4675 | continue; | |
de3d5b94 | 4676 | |
396e799c | 4677 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
de3d5b94 | 4678 | goto err_setup_rx; |
69888674 AD |
4679 | } |
4680 | ||
7c8ae65a AD |
4681 | #ifdef IXGBE_FCOE |
4682 | err = ixgbe_setup_fcoe_ddp_resources(adapter); | |
4683 | if (!err) | |
4684 | #endif | |
4685 | return 0; | |
de3d5b94 AD |
4686 | err_setup_rx: |
4687 | /* rewind the index freeing the rings as we go */ | |
4688 | while (i--) | |
4689 | ixgbe_free_rx_resources(adapter->rx_ring[i]); | |
69888674 AD |
4690 | return err; |
4691 | } | |
4692 | ||
9a799d71 AK |
4693 | /** |
4694 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
4695 | * @tx_ring: Tx descriptor ring for a specific queue |
4696 | * | |
4697 | * Free all transmit software resources | |
4698 | **/ | |
b6ec895e | 4699 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4700 | { |
b6ec895e | 4701 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
4702 | |
4703 | vfree(tx_ring->tx_buffer_info); | |
4704 | tx_ring->tx_buffer_info = NULL; | |
4705 | ||
b6ec895e AD |
4706 | /* if not set, then don't free */ |
4707 | if (!tx_ring->desc) | |
4708 | return; | |
4709 | ||
4710 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
4711 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
4712 | |
4713 | tx_ring->desc = NULL; | |
4714 | } | |
4715 | ||
4716 | /** | |
4717 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4718 | * @adapter: board private structure | |
4719 | * | |
4720 | * Free all transmit software resources | |
4721 | **/ | |
4722 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4723 | { | |
4724 | int i; | |
4725 | ||
4726 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4727 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 4728 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
4729 | } |
4730 | ||
4731 | /** | |
b4617240 | 4732 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4733 | * @rx_ring: ring to clean the resources from |
4734 | * | |
4735 | * Free all receive software resources | |
4736 | **/ | |
b6ec895e | 4737 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4738 | { |
b6ec895e | 4739 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
4740 | |
4741 | vfree(rx_ring->rx_buffer_info); | |
4742 | rx_ring->rx_buffer_info = NULL; | |
4743 | ||
b6ec895e AD |
4744 | /* if not set, then don't free */ |
4745 | if (!rx_ring->desc) | |
4746 | return; | |
4747 | ||
4748 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
4749 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
4750 | |
4751 | rx_ring->desc = NULL; | |
4752 | } | |
4753 | ||
4754 | /** | |
4755 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4756 | * @adapter: board private structure | |
4757 | * | |
4758 | * Free all receive software resources | |
4759 | **/ | |
4760 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4761 | { | |
4762 | int i; | |
4763 | ||
7c8ae65a AD |
4764 | #ifdef IXGBE_FCOE |
4765 | ixgbe_free_fcoe_ddp_resources(adapter); | |
4766 | ||
4767 | #endif | |
9a799d71 | 4768 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 4769 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 4770 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
4771 | } |
4772 | ||
9a799d71 AK |
4773 | /** |
4774 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4775 | * @netdev: network interface device structure | |
4776 | * @new_mtu: new value for maximum frame size | |
4777 | * | |
4778 | * Returns 0 on success, negative on failure | |
4779 | **/ | |
4780 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4781 | { | |
4782 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4783 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4784 | ||
42c783c5 | 4785 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
4786 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
4787 | return -EINVAL; | |
4788 | ||
4789 | /* | |
4790 | * For 82599EB we cannot allow PF to change MTU greater than 1500 | |
4791 | * in SR-IOV mode as it may cause buffer overruns in guest VFs that | |
4792 | * don't allocate and chain buffers correctly. | |
4793 | */ | |
4794 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
4795 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
4796 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
e9f98072 | 4797 | return -EINVAL; |
9a799d71 | 4798 | |
396e799c | 4799 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 4800 | |
021230d4 | 4801 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4802 | netdev->mtu = new_mtu; |
4803 | ||
d4f80882 AV |
4804 | if (netif_running(netdev)) |
4805 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4806 | |
4807 | return 0; | |
4808 | } | |
4809 | ||
4810 | /** | |
4811 | * ixgbe_open - Called when a network interface is made active | |
4812 | * @netdev: network interface device structure | |
4813 | * | |
4814 | * Returns 0 on success, negative value on failure | |
4815 | * | |
4816 | * The open entry point is called when a network interface is made | |
4817 | * active by the system (IFF_UP). At this point all resources needed | |
4818 | * for transmit and receive operations are allocated, the interrupt | |
4819 | * handler is registered with the OS, the watchdog timer is started, | |
4820 | * and the stack is notified that the interface is ready. | |
4821 | **/ | |
4822 | static int ixgbe_open(struct net_device *netdev) | |
4823 | { | |
4824 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4825 | int err; | |
4bebfaa5 AK |
4826 | |
4827 | /* disallow open during test */ | |
4828 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4829 | return -EBUSY; | |
9a799d71 | 4830 | |
54386467 JB |
4831 | netif_carrier_off(netdev); |
4832 | ||
9a799d71 AK |
4833 | /* allocate transmit descriptors */ |
4834 | err = ixgbe_setup_all_tx_resources(adapter); | |
4835 | if (err) | |
4836 | goto err_setup_tx; | |
4837 | ||
9a799d71 AK |
4838 | /* allocate receive descriptors */ |
4839 | err = ixgbe_setup_all_rx_resources(adapter); | |
4840 | if (err) | |
4841 | goto err_setup_rx; | |
4842 | ||
4843 | ixgbe_configure(adapter); | |
4844 | ||
021230d4 | 4845 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4846 | if (err) |
4847 | goto err_req_irq; | |
4848 | ||
ac802f5d AD |
4849 | /* Notify the stack of the actual queue counts. */ |
4850 | err = netif_set_real_num_tx_queues(netdev, | |
4851 | adapter->num_rx_pools > 1 ? 1 : | |
4852 | adapter->num_tx_queues); | |
4853 | if (err) | |
4854 | goto err_set_queues; | |
4855 | ||
4856 | ||
4857 | err = netif_set_real_num_rx_queues(netdev, | |
4858 | adapter->num_rx_pools > 1 ? 1 : | |
4859 | adapter->num_rx_queues); | |
4860 | if (err) | |
4861 | goto err_set_queues; | |
4862 | ||
c7ccde0f | 4863 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4864 | |
4865 | return 0; | |
4866 | ||
ac802f5d AD |
4867 | err_set_queues: |
4868 | ixgbe_free_irq(adapter); | |
9a799d71 | 4869 | err_req_irq: |
a20a1199 | 4870 | ixgbe_free_all_rx_resources(adapter); |
de3d5b94 | 4871 | err_setup_rx: |
a20a1199 | 4872 | ixgbe_free_all_tx_resources(adapter); |
de3d5b94 | 4873 | err_setup_tx: |
9a799d71 AK |
4874 | ixgbe_reset(adapter); |
4875 | ||
4876 | return err; | |
4877 | } | |
4878 | ||
4879 | /** | |
4880 | * ixgbe_close - Disables a network interface | |
4881 | * @netdev: network interface device structure | |
4882 | * | |
4883 | * Returns 0, this is not allowed to fail | |
4884 | * | |
4885 | * The close entry point is called when an interface is de-activated | |
4886 | * by the OS. The hardware is still under the drivers control, but | |
4887 | * needs to be disabled. A global MAC reset is issued to stop the | |
4888 | * hardware, and all transmit and receive resources are freed. | |
4889 | **/ | |
4890 | static int ixgbe_close(struct net_device *netdev) | |
4891 | { | |
4892 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4893 | |
4894 | ixgbe_down(adapter); | |
4895 | ixgbe_free_irq(adapter); | |
4896 | ||
e4911d57 AD |
4897 | ixgbe_fdir_filter_exit(adapter); |
4898 | ||
9a799d71 AK |
4899 | ixgbe_free_all_tx_resources(adapter); |
4900 | ixgbe_free_all_rx_resources(adapter); | |
4901 | ||
5eba3699 | 4902 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4903 | |
4904 | return 0; | |
4905 | } | |
4906 | ||
b3c8b4ba AD |
4907 | #ifdef CONFIG_PM |
4908 | static int ixgbe_resume(struct pci_dev *pdev) | |
4909 | { | |
c60fbb00 AD |
4910 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4911 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
4912 | u32 err; |
4913 | ||
4914 | pci_set_power_state(pdev, PCI_D0); | |
4915 | pci_restore_state(pdev); | |
656ab817 DS |
4916 | /* |
4917 | * pci_restore_state clears dev->state_saved so call | |
4918 | * pci_save_state to restore it. | |
4919 | */ | |
4920 | pci_save_state(pdev); | |
9ce77666 | 4921 | |
4922 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4923 | if (err) { |
849c4542 | 4924 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
4925 | return err; |
4926 | } | |
4927 | pci_set_master(pdev); | |
4928 | ||
dd4d8ca6 | 4929 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 4930 | |
b3c8b4ba AD |
4931 | ixgbe_reset(adapter); |
4932 | ||
495dce12 WJP |
4933 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4934 | ||
ac802f5d AD |
4935 | rtnl_lock(); |
4936 | err = ixgbe_init_interrupt_scheme(adapter); | |
4937 | if (!err && netif_running(netdev)) | |
c60fbb00 | 4938 | err = ixgbe_open(netdev); |
ac802f5d AD |
4939 | |
4940 | rtnl_unlock(); | |
4941 | ||
4942 | if (err) | |
4943 | return err; | |
b3c8b4ba AD |
4944 | |
4945 | netif_device_attach(netdev); | |
4946 | ||
4947 | return 0; | |
4948 | } | |
b3c8b4ba | 4949 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4950 | |
4951 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 4952 | { |
c60fbb00 AD |
4953 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4954 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
4955 | struct ixgbe_hw *hw = &adapter->hw; |
4956 | u32 ctrl, fctrl; | |
4957 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4958 | #ifdef CONFIG_PM |
4959 | int retval = 0; | |
4960 | #endif | |
4961 | ||
4962 | netif_device_detach(netdev); | |
4963 | ||
4964 | if (netif_running(netdev)) { | |
ab6039a7 | 4965 | rtnl_lock(); |
b3c8b4ba AD |
4966 | ixgbe_down(adapter); |
4967 | ixgbe_free_irq(adapter); | |
4968 | ixgbe_free_all_tx_resources(adapter); | |
4969 | ixgbe_free_all_rx_resources(adapter); | |
ab6039a7 | 4970 | rtnl_unlock(); |
b3c8b4ba | 4971 | } |
b3c8b4ba | 4972 | |
5f5ae6fc AD |
4973 | ixgbe_clear_interrupt_scheme(adapter); |
4974 | ||
b3c8b4ba AD |
4975 | #ifdef CONFIG_PM |
4976 | retval = pci_save_state(pdev); | |
4977 | if (retval) | |
4978 | return retval; | |
4df10466 | 4979 | |
b3c8b4ba | 4980 | #endif |
e8e26350 PW |
4981 | if (wufc) { |
4982 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4983 | |
c509e754 DS |
4984 | /* |
4985 | * enable the optics for both mult-speed fiber and | |
4986 | * 82599 SFP+ fiber as we can WoL. | |
4987 | */ | |
4988 | if (hw->mac.ops.enable_tx_laser && | |
4989 | (hw->phy.multispeed_fiber || | |
4990 | (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber && | |
4991 | hw->mac.type == ixgbe_mac_82599EB))) | |
4992 | hw->mac.ops.enable_tx_laser(hw); | |
4993 | ||
e8e26350 PW |
4994 | /* turn on all-multi mode if wake on multicast is enabled */ |
4995 | if (wufc & IXGBE_WUFC_MC) { | |
4996 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4997 | fctrl |= IXGBE_FCTRL_MPE; | |
4998 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4999 | } | |
5000 | ||
5001 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5002 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5003 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5004 | ||
5005 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5006 | } else { | |
5007 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5008 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5009 | } | |
5010 | ||
bd508178 AD |
5011 | switch (hw->mac.type) { |
5012 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5013 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5014 | break; |
5015 | case ixgbe_mac_82599EB: | |
b93a2226 | 5016 | case ixgbe_mac_X540: |
bd508178 AD |
5017 | pci_wake_from_d3(pdev, !!wufc); |
5018 | break; | |
5019 | default: | |
5020 | break; | |
5021 | } | |
b3c8b4ba | 5022 | |
9d8d05ae RW |
5023 | *enable_wake = !!wufc; |
5024 | ||
b3c8b4ba AD |
5025 | ixgbe_release_hw_control(adapter); |
5026 | ||
5027 | pci_disable_device(pdev); | |
5028 | ||
9d8d05ae RW |
5029 | return 0; |
5030 | } | |
5031 | ||
5032 | #ifdef CONFIG_PM | |
5033 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5034 | { | |
5035 | int retval; | |
5036 | bool wake; | |
5037 | ||
5038 | retval = __ixgbe_shutdown(pdev, &wake); | |
5039 | if (retval) | |
5040 | return retval; | |
5041 | ||
5042 | if (wake) { | |
5043 | pci_prepare_to_sleep(pdev); | |
5044 | } else { | |
5045 | pci_wake_from_d3(pdev, false); | |
5046 | pci_set_power_state(pdev, PCI_D3hot); | |
5047 | } | |
b3c8b4ba AD |
5048 | |
5049 | return 0; | |
5050 | } | |
9d8d05ae | 5051 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5052 | |
5053 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5054 | { | |
9d8d05ae RW |
5055 | bool wake; |
5056 | ||
5057 | __ixgbe_shutdown(pdev, &wake); | |
5058 | ||
5059 | if (system_state == SYSTEM_POWER_OFF) { | |
5060 | pci_wake_from_d3(pdev, wake); | |
5061 | pci_set_power_state(pdev, PCI_D3hot); | |
5062 | } | |
b3c8b4ba AD |
5063 | } |
5064 | ||
9a799d71 AK |
5065 | /** |
5066 | * ixgbe_update_stats - Update the board statistics counters. | |
5067 | * @adapter: board private structure | |
5068 | **/ | |
5069 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5070 | { | |
2d86f139 | 5071 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5072 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5073 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5074 | u64 total_mpc = 0; |
5075 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5076 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5077 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 5078 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
9a799d71 | 5079 | |
d08935c2 DS |
5080 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5081 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5082 | return; | |
5083 | ||
94b982b2 | 5084 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5085 | u64 rsc_count = 0; |
94b982b2 | 5086 | u64 rsc_flush = 0; |
94b982b2 | 5087 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5088 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5089 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5090 | } |
5091 | adapter->rsc_total_count = rsc_count; | |
5092 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5093 | } |
5094 | ||
5b7da515 AD |
5095 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5096 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5097 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5098 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5099 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 5100 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
5101 | bytes += rx_ring->stats.bytes; |
5102 | packets += rx_ring->stats.packets; | |
5103 | } | |
5104 | adapter->non_eop_descs = non_eop_descs; | |
5105 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5106 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5107 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5108 | netdev->stats.rx_bytes = bytes; |
5109 | netdev->stats.rx_packets = packets; | |
5110 | ||
5111 | bytes = 0; | |
5112 | packets = 0; | |
7ca3bc58 | 5113 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5114 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5115 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5116 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5117 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5118 | bytes += tx_ring->stats.bytes; | |
5119 | packets += tx_ring->stats.packets; | |
5120 | } | |
eb985f09 | 5121 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5122 | adapter->tx_busy = tx_busy; |
5123 | netdev->stats.tx_bytes = bytes; | |
5124 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5125 | |
7ca647bd | 5126 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5127 | |
5128 | /* 8 register reads */ | |
6f11eef7 AV |
5129 | for (i = 0; i < 8; i++) { |
5130 | /* for packet buffers not used, the register should read 0 */ | |
5131 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5132 | missed_rx += mpc; | |
7ca647bd JP |
5133 | hwstats->mpc[i] += mpc; |
5134 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5135 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5136 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5137 | switch (hw->mac.type) { |
5138 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5139 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5140 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5141 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5142 | hwstats->pxonrxc[i] += |
5143 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5144 | break; |
5145 | case ixgbe_mac_82599EB: | |
b93a2226 | 5146 | case ixgbe_mac_X540: |
bd508178 AD |
5147 | hwstats->pxonrxc[i] += |
5148 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5149 | break; |
5150 | default: | |
5151 | break; | |
e8e26350 | 5152 | } |
6f11eef7 | 5153 | } |
1a70db4b ET |
5154 | |
5155 | /*16 register reads */ | |
5156 | for (i = 0; i < 16; i++) { | |
5157 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5158 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5159 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5160 | (hw->mac.type == ixgbe_mac_X540)) { | |
5161 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5162 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5163 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5164 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5165 | } | |
5166 | } | |
5167 | ||
7ca647bd | 5168 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5169 | /* work around hardware counting issue */ |
7ca647bd | 5170 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5171 | |
c84d324c JF |
5172 | ixgbe_update_xoff_received(adapter); |
5173 | ||
6f11eef7 | 5174 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5175 | switch (hw->mac.type) { |
5176 | case ixgbe_mac_82598EB: | |
5177 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5178 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5179 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5180 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5181 | break; | |
b93a2226 | 5182 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5183 | /* OS2BMC stats are X540 only*/ |
5184 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5185 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5186 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5187 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5188 | case ixgbe_mac_82599EB: | |
a4d4f629 AD |
5189 | for (i = 0; i < 16; i++) |
5190 | adapter->hw_rx_no_dma_resources += | |
5191 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 5192 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5193 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5194 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5195 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5196 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5197 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5198 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5199 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5200 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5201 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5202 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5203 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5204 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5205 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5206 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5207 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc | 5208 | /* Add up per cpu counters for total ddp aloc fail */ |
5a1ee270 AD |
5209 | if (adapter->fcoe.ddp_pool) { |
5210 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
5211 | struct ixgbe_fcoe_ddp_pool *ddp_pool; | |
5212 | unsigned int cpu; | |
5213 | u64 noddp = 0, noddp_ext_buff = 0; | |
7b859ebc | 5214 | for_each_possible_cpu(cpu) { |
5a1ee270 AD |
5215 | ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); |
5216 | noddp += ddp_pool->noddp; | |
5217 | noddp_ext_buff += ddp_pool->noddp_ext_buff; | |
7b859ebc | 5218 | } |
5a1ee270 AD |
5219 | hwstats->fcoe_noddp = noddp; |
5220 | hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; | |
7b859ebc | 5221 | } |
6d45522c | 5222 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5223 | break; |
5224 | default: | |
5225 | break; | |
e8e26350 | 5226 | } |
9a799d71 | 5227 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5228 | hwstats->bprc += bprc; |
5229 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5230 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5231 | hwstats->mprc -= bprc; |
5232 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5233 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5234 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5235 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5236 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5237 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5238 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5239 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5240 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5241 | hwstats->lxontxc += lxon; |
6f11eef7 | 5242 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5243 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5244 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5245 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5246 | /* |
5247 | * 82598 errata - tx of flow control packets is included in tx counters | |
5248 | */ | |
5249 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5250 | hwstats->gptc -= xon_off_tot; |
5251 | hwstats->mptc -= xon_off_tot; | |
5252 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5253 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5254 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5255 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5256 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5257 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5258 | hwstats->ptc64 -= xon_off_tot; | |
5259 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5260 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5261 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5262 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5263 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5264 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5265 | |
5266 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5267 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5268 | |
5269 | /* Rx Errors */ | |
7ca647bd | 5270 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5271 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5272 | netdev->stats.rx_length_errors = hwstats->rlec; |
5273 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5274 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5275 | } |
5276 | ||
5277 | /** | |
d034acf1 | 5278 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
49ce9c2c | 5279 | * @adapter: pointer to the device adapter structure |
9a799d71 | 5280 | **/ |
d034acf1 | 5281 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5282 | { |
cf8280ee | 5283 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5284 | int i; |
cf8280ee | 5285 | |
d034acf1 AD |
5286 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5287 | return; | |
5288 | ||
5289 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 5290 | |
d034acf1 | 5291 | /* if interface is down do nothing */ |
fe49f04a | 5292 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
5293 | return; |
5294 | ||
5295 | /* do nothing if we are not using signature filters */ | |
5296 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
5297 | return; | |
5298 | ||
5299 | adapter->fdir_overflow++; | |
5300 | ||
93c52dd0 AD |
5301 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
5302 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5303 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 5304 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
5305 | /* re-enable flow director interrupts */ |
5306 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
5307 | } else { |
5308 | e_err(probe, "failed to finish FDIR re-initialization, " | |
5309 | "ignored adding FDIR ATR filters\n"); | |
5310 | } | |
93c52dd0 AD |
5311 | } |
5312 | ||
5313 | /** | |
5314 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
49ce9c2c | 5315 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5316 | * |
5317 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 5318 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 5319 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 5320 | * determine if a hang has occurred. |
93c52dd0 AD |
5321 | */ |
5322 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 5323 | { |
cf8280ee | 5324 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5325 | u64 eics = 0; |
5326 | int i; | |
cf8280ee | 5327 | |
93c52dd0 AD |
5328 | /* If we're down or resetting, just bail */ |
5329 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5330 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5331 | return; | |
22d5a71b | 5332 | |
93c52dd0 AD |
5333 | /* Force detection of hung controller */ |
5334 | if (netif_carrier_ok(adapter->netdev)) { | |
5335 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5336 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
5337 | } | |
22d5a71b | 5338 | |
fe49f04a AD |
5339 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5340 | /* | |
5341 | * for legacy and MSI interrupts don't set any bits | |
5342 | * that are enabled for EIAM, because this operation | |
5343 | * would set *both* EIMS and EICS for any bit in EIAM | |
5344 | */ | |
5345 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5346 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
5347 | } else { |
5348 | /* get one bit for every active tx/rx interrupt vector */ | |
49c7ffbe | 5349 | for (i = 0; i < adapter->num_q_vectors; i++) { |
93c52dd0 | 5350 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; |
efe3d3c8 | 5351 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
5352 | eics |= ((u64)1 << i); |
5353 | } | |
cf8280ee | 5354 | } |
9a799d71 | 5355 | |
93c52dd0 | 5356 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
5357 | ixgbe_irq_rearm_queues(adapter, eics); |
5358 | ||
cf8280ee JB |
5359 | } |
5360 | ||
e8e26350 | 5361 | /** |
93c52dd0 | 5362 | * ixgbe_watchdog_update_link - update the link status |
49ce9c2c BH |
5363 | * @adapter: pointer to the device adapter structure |
5364 | * @link_speed: pointer to a u32 to store the link_speed | |
e8e26350 | 5365 | **/ |
93c52dd0 | 5366 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 5367 | { |
e8e26350 | 5368 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5369 | u32 link_speed = adapter->link_speed; |
5370 | bool link_up = adapter->link_up; | |
041441d0 | 5371 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 5372 | |
93c52dd0 AD |
5373 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
5374 | return; | |
5375 | ||
5376 | if (hw->mac.ops.check_link) { | |
5377 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 5378 | } else { |
93c52dd0 AD |
5379 | /* always assume link is up, if no check link function */ |
5380 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
5381 | link_up = true; | |
c4cf55e5 | 5382 | } |
041441d0 AD |
5383 | |
5384 | if (adapter->ixgbe_ieee_pfc) | |
5385 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
5386 | ||
3ebe8fde | 5387 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { |
041441d0 | 5388 | hw->mac.ops.fc_enable(hw); |
3ebe8fde AD |
5389 | ixgbe_set_rx_drop_en(adapter); |
5390 | } | |
93c52dd0 AD |
5391 | |
5392 | if (link_up || | |
5393 | time_after(jiffies, (adapter->link_check_timeout + | |
5394 | IXGBE_TRY_LINK_TIMEOUT))) { | |
5395 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
5396 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
5397 | IXGBE_WRITE_FLUSH(hw); | |
5398 | } | |
5399 | ||
5400 | adapter->link_up = link_up; | |
5401 | adapter->link_speed = link_speed; | |
e8e26350 PW |
5402 | } |
5403 | ||
5404 | /** | |
93c52dd0 AD |
5405 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
5406 | * print link up message | |
49ce9c2c | 5407 | * @adapter: pointer to the device adapter structure |
e8e26350 | 5408 | **/ |
93c52dd0 | 5409 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 5410 | { |
93c52dd0 | 5411 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 5412 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5413 | u32 link_speed = adapter->link_speed; |
5414 | bool flow_rx, flow_tx; | |
e8e26350 | 5415 | |
93c52dd0 AD |
5416 | /* only continue if link was previously down */ |
5417 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 5418 | return; |
63d6e1d8 | 5419 | |
93c52dd0 | 5420 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 5421 | |
93c52dd0 AD |
5422 | switch (hw->mac.type) { |
5423 | case ixgbe_mac_82598EB: { | |
5424 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5425 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
5426 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
5427 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
5428 | } | |
5429 | break; | |
5430 | case ixgbe_mac_X540: | |
5431 | case ixgbe_mac_82599EB: { | |
5432 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5433 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
5434 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
5435 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
5436 | } | |
5437 | break; | |
5438 | default: | |
5439 | flow_tx = false; | |
5440 | flow_rx = false; | |
5441 | break; | |
e8e26350 | 5442 | } |
3a6a4eda JK |
5443 | |
5444 | #ifdef CONFIG_IXGBE_PTP | |
5445 | ixgbe_ptp_start_cyclecounter(adapter); | |
5446 | #endif | |
5447 | ||
93c52dd0 AD |
5448 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
5449 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5450 | "10 Gbps" : | |
5451 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5452 | "1 Gbps" : | |
5453 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
5454 | "100 Mbps" : | |
5455 | "unknown speed"))), | |
5456 | ((flow_rx && flow_tx) ? "RX/TX" : | |
5457 | (flow_rx ? "RX" : | |
5458 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 5459 | |
93c52dd0 | 5460 | netif_carrier_on(netdev); |
93c52dd0 | 5461 | ixgbe_check_vf_rate_limit(adapter); |
befa2af7 AD |
5462 | |
5463 | /* ping all the active vfs to let them know link has changed */ | |
5464 | ixgbe_ping_all_vfs(adapter); | |
e8e26350 PW |
5465 | } |
5466 | ||
c4cf55e5 | 5467 | /** |
93c52dd0 AD |
5468 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
5469 | * print link down message | |
49ce9c2c | 5470 | * @adapter: pointer to the adapter structure |
c4cf55e5 | 5471 | **/ |
581330ba | 5472 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 5473 | { |
cf8280ee | 5474 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 5475 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 5476 | |
93c52dd0 AD |
5477 | adapter->link_up = false; |
5478 | adapter->link_speed = 0; | |
cf8280ee | 5479 | |
93c52dd0 AD |
5480 | /* only continue if link was up previously */ |
5481 | if (!netif_carrier_ok(netdev)) | |
5482 | return; | |
264857b8 | 5483 | |
93c52dd0 AD |
5484 | /* poll for SFP+ cable when link is down */ |
5485 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
5486 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 5487 | |
3a6a4eda JK |
5488 | #ifdef CONFIG_IXGBE_PTP |
5489 | ixgbe_ptp_start_cyclecounter(adapter); | |
5490 | #endif | |
5491 | ||
93c52dd0 AD |
5492 | e_info(drv, "NIC Link is Down\n"); |
5493 | netif_carrier_off(netdev); | |
befa2af7 AD |
5494 | |
5495 | /* ping all the active vfs to let them know link has changed */ | |
5496 | ixgbe_ping_all_vfs(adapter); | |
93c52dd0 | 5497 | } |
e8e26350 | 5498 | |
93c52dd0 AD |
5499 | /** |
5500 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
49ce9c2c | 5501 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5502 | **/ |
5503 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
5504 | { | |
c4cf55e5 | 5505 | int i; |
93c52dd0 | 5506 | int some_tx_pending = 0; |
c4cf55e5 | 5507 | |
93c52dd0 | 5508 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 5509 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 5510 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5511 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5512 | some_tx_pending = 1; | |
5513 | break; | |
5514 | } | |
5515 | } | |
5516 | ||
5517 | if (some_tx_pending) { | |
5518 | /* We've lost link, so the controller stops DMA, | |
5519 | * but we've got queued Tx work that's never going | |
5520 | * to get done, so reset controller to flush Tx. | |
5521 | * (Do the reset outside of interrupt context). | |
5522 | */ | |
c83c6cbd | 5523 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 5524 | } |
c4cf55e5 | 5525 | } |
c4cf55e5 PWJ |
5526 | } |
5527 | ||
a985b6c3 GR |
5528 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
5529 | { | |
5530 | u32 ssvpc; | |
5531 | ||
5532 | /* Do not perform spoof check for 82598 */ | |
5533 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5534 | return; | |
5535 | ||
5536 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
5537 | ||
5538 | /* | |
5539 | * ssvpc register is cleared on read, if zero then no | |
5540 | * spoofed packets in the last interval. | |
5541 | */ | |
5542 | if (!ssvpc) | |
5543 | return; | |
5544 | ||
5545 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
5546 | } | |
5547 | ||
93c52dd0 AD |
5548 | /** |
5549 | * ixgbe_watchdog_subtask - check and bring link up | |
49ce9c2c | 5550 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5551 | **/ |
5552 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
5553 | { | |
5554 | /* if interface is down do nothing */ | |
7edebf9a ET |
5555 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5556 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
5557 | return; |
5558 | ||
5559 | ixgbe_watchdog_update_link(adapter); | |
5560 | ||
5561 | if (adapter->link_up) | |
5562 | ixgbe_watchdog_link_is_up(adapter); | |
5563 | else | |
5564 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 5565 | |
a985b6c3 | 5566 | ixgbe_spoof_check(adapter); |
9a799d71 | 5567 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
5568 | |
5569 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 5570 | } |
10eec955 | 5571 | |
cf8280ee | 5572 | /** |
7086400d | 5573 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
49ce9c2c | 5574 | * @adapter: the ixgbe adapter structure |
cf8280ee | 5575 | **/ |
7086400d | 5576 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 5577 | { |
cf8280ee | 5578 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 5579 | s32 err; |
cf8280ee | 5580 | |
7086400d AD |
5581 | /* not searching for SFP so there is nothing to do here */ |
5582 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
5583 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5584 | return; | |
10eec955 | 5585 | |
7086400d AD |
5586 | /* someone else is in init, wait until next service event */ |
5587 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5588 | return; | |
cf8280ee | 5589 | |
7086400d AD |
5590 | err = hw->phy.ops.identify_sfp(hw); |
5591 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5592 | goto sfp_out; | |
264857b8 | 5593 | |
7086400d AD |
5594 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5595 | /* If no cable is present, then we need to reset | |
5596 | * the next time we find a good cable. */ | |
5597 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 5598 | } |
9a799d71 | 5599 | |
7086400d AD |
5600 | /* exit on error */ |
5601 | if (err) | |
5602 | goto sfp_out; | |
e8e26350 | 5603 | |
7086400d AD |
5604 | /* exit if reset not needed */ |
5605 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5606 | goto sfp_out; | |
9a799d71 | 5607 | |
7086400d | 5608 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 5609 | |
7086400d AD |
5610 | /* |
5611 | * A module may be identified correctly, but the EEPROM may not have | |
5612 | * support for that module. setup_sfp() will fail in that case, so | |
5613 | * we should not allow that module to load. | |
5614 | */ | |
5615 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5616 | err = hw->phy.ops.reset(hw); | |
5617 | else | |
5618 | err = hw->mac.ops.setup_sfp(hw); | |
5619 | ||
5620 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5621 | goto sfp_out; | |
5622 | ||
5623 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
5624 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
5625 | ||
5626 | sfp_out: | |
5627 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5628 | ||
5629 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
5630 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
5631 | e_dev_err("failed to initialize because an unsupported " | |
5632 | "SFP+ module type was detected.\n"); | |
5633 | e_dev_err("Reload the driver after installing a " | |
5634 | "supported module.\n"); | |
5635 | unregister_netdev(adapter->netdev); | |
bc59fcda | 5636 | } |
7086400d | 5637 | } |
bc59fcda | 5638 | |
7086400d AD |
5639 | /** |
5640 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
49ce9c2c | 5641 | * @adapter: the ixgbe adapter structure |
7086400d AD |
5642 | **/ |
5643 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
5644 | { | |
5645 | struct ixgbe_hw *hw = &adapter->hw; | |
5646 | u32 autoneg; | |
5647 | bool negotiation; | |
5648 | ||
5649 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
5650 | return; | |
5651 | ||
5652 | /* someone else is in init, wait until next service event */ | |
5653 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5654 | return; | |
5655 | ||
5656 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5657 | ||
5658 | autoneg = hw->phy.autoneg_advertised; | |
5659 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
5660 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
5661 | if (hw->mac.ops.setup_link) |
5662 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
5663 | ||
5664 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
5665 | adapter->link_check_timeout = jiffies; | |
5666 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5667 | } | |
5668 | ||
83c61fa9 GR |
5669 | #ifdef CONFIG_PCI_IOV |
5670 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
5671 | { | |
5672 | int vf; | |
5673 | struct ixgbe_hw *hw = &adapter->hw; | |
5674 | struct net_device *netdev = adapter->netdev; | |
5675 | u32 gpc; | |
5676 | u32 ciaa, ciad; | |
5677 | ||
5678 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
5679 | if (gpc) /* If incrementing then no need for the check below */ | |
5680 | return; | |
5681 | /* | |
5682 | * Check to see if a bad DMA write target from an errant or | |
5683 | * malicious VF has caused a PCIe error. If so then we can | |
5684 | * issue a VFLR to the offending VF(s) and then resume without | |
5685 | * requesting a full slot reset. | |
5686 | */ | |
5687 | ||
5688 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
5689 | ciaa = (vf << 16) | 0x80000000; | |
5690 | /* 32 bit read so align, we really want status at offset 6 */ | |
5691 | ciaa |= PCI_COMMAND; | |
5692 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5693 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
5694 | ciaa &= 0x7FFFFFFF; | |
5695 | /* disable debug mode asap after reading data */ | |
5696 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5697 | /* Get the upper 16 bits which will be the PCI status reg */ | |
5698 | ciad >>= 16; | |
5699 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
5700 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
5701 | /* Issue VFLR */ | |
5702 | ciaa = (vf << 16) | 0x80000000; | |
5703 | ciaa |= 0xA8; | |
5704 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5705 | ciad = 0x00008000; /* VFLR */ | |
5706 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
5707 | ciaa &= 0x7FFFFFFF; | |
5708 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5709 | } | |
5710 | } | |
5711 | } | |
5712 | ||
5713 | #endif | |
7086400d AD |
5714 | /** |
5715 | * ixgbe_service_timer - Timer Call-back | |
5716 | * @data: pointer to adapter cast into an unsigned long | |
5717 | **/ | |
5718 | static void ixgbe_service_timer(unsigned long data) | |
5719 | { | |
5720 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5721 | unsigned long next_event_offset; | |
83c61fa9 | 5722 | bool ready = true; |
7086400d | 5723 | |
6bb78cfb AD |
5724 | /* poll faster when waiting for link */ |
5725 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
5726 | next_event_offset = HZ / 10; | |
5727 | else | |
5728 | next_event_offset = HZ * 2; | |
83c61fa9 | 5729 | |
6bb78cfb | 5730 | #ifdef CONFIG_PCI_IOV |
83c61fa9 GR |
5731 | /* |
5732 | * don't bother with SR-IOV VF DMA hang check if there are | |
5733 | * no VFs or the link is down | |
5734 | */ | |
5735 | if (!adapter->num_vfs || | |
6bb78cfb | 5736 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
83c61fa9 | 5737 | goto normal_timer_service; |
83c61fa9 GR |
5738 | |
5739 | /* If we have VFs allocated then we must check for DMA hangs */ | |
5740 | ixgbe_check_for_bad_vf(adapter); | |
5741 | next_event_offset = HZ / 50; | |
5742 | adapter->timer_event_accumulator++; | |
5743 | ||
6bb78cfb | 5744 | if (adapter->timer_event_accumulator >= 100) |
83c61fa9 | 5745 | adapter->timer_event_accumulator = 0; |
7086400d | 5746 | else |
6bb78cfb | 5747 | ready = false; |
7086400d | 5748 | |
6bb78cfb | 5749 | normal_timer_service: |
83c61fa9 | 5750 | #endif |
7086400d AD |
5751 | /* Reset the timer */ |
5752 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
5753 | ||
83c61fa9 GR |
5754 | if (ready) |
5755 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
5756 | } |
5757 | ||
c83c6cbd AD |
5758 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
5759 | { | |
5760 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
5761 | return; | |
5762 | ||
5763 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
5764 | ||
5765 | /* If we're already down or resetting, just bail */ | |
5766 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5767 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5768 | return; | |
5769 | ||
5770 | ixgbe_dump(adapter); | |
5771 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
5772 | adapter->tx_timeout_count++; | |
5773 | ||
5774 | ixgbe_reinit_locked(adapter); | |
5775 | } | |
5776 | ||
7086400d AD |
5777 | /** |
5778 | * ixgbe_service_task - manages and runs subtasks | |
5779 | * @work: pointer to work_struct containing our data | |
5780 | **/ | |
5781 | static void ixgbe_service_task(struct work_struct *work) | |
5782 | { | |
5783 | struct ixgbe_adapter *adapter = container_of(work, | |
5784 | struct ixgbe_adapter, | |
5785 | service_task); | |
5786 | ||
c83c6cbd | 5787 | ixgbe_reset_subtask(adapter); |
7086400d AD |
5788 | ixgbe_sfp_detection_subtask(adapter); |
5789 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 5790 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 5791 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 5792 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 5793 | ixgbe_check_hang_subtask(adapter); |
3a6a4eda JK |
5794 | #ifdef CONFIG_IXGBE_PTP |
5795 | ixgbe_ptp_overflow_check(adapter); | |
5796 | #endif | |
7086400d AD |
5797 | |
5798 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
5799 | } |
5800 | ||
fd0db0ed AD |
5801 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
5802 | struct ixgbe_tx_buffer *first, | |
244e27ad | 5803 | u8 *hdr_len) |
897ab156 | 5804 | { |
fd0db0ed | 5805 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5806 | u32 vlan_macip_lens, type_tucmd; |
5807 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 5808 | |
897ab156 AD |
5809 | if (!skb_is_gso(skb)) |
5810 | return 0; | |
9a799d71 | 5811 | |
897ab156 | 5812 | if (skb_header_cloned(skb)) { |
244e27ad | 5813 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
897ab156 AD |
5814 | if (err) |
5815 | return err; | |
9a799d71 | 5816 | } |
9a799d71 | 5817 | |
897ab156 AD |
5818 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
5819 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5820 | ||
244e27ad | 5821 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
897ab156 AD |
5822 | struct iphdr *iph = ip_hdr(skb); |
5823 | iph->tot_len = 0; | |
5824 | iph->check = 0; | |
5825 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5826 | iph->daddr, 0, | |
5827 | IPPROTO_TCP, | |
5828 | 0); | |
5829 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
5830 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5831 | IXGBE_TX_FLAGS_CSUM | | |
5832 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
5833 | } else if (skb_is_gso_v6(skb)) { |
5834 | ipv6_hdr(skb)->payload_len = 0; | |
5835 | tcp_hdr(skb)->check = | |
5836 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
5837 | &ipv6_hdr(skb)->daddr, | |
5838 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
5839 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5840 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
5841 | } |
5842 | ||
091a6246 | 5843 | /* compute header lengths */ |
897ab156 AD |
5844 | l4len = tcp_hdrlen(skb); |
5845 | *hdr_len = skb_transport_offset(skb) + l4len; | |
5846 | ||
091a6246 AD |
5847 | /* update gso size and bytecount with header size */ |
5848 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
5849 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
5850 | ||
897ab156 AD |
5851 | /* mss_l4len_id: use 1 as index for TSO */ |
5852 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
5853 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
5854 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
5855 | ||
5856 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
5857 | vlan_macip_lens = skb_network_header_len(skb); | |
5858 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 5859 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
5860 | |
5861 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 5862 | mss_l4len_idx); |
897ab156 AD |
5863 | |
5864 | return 1; | |
5865 | } | |
5866 | ||
244e27ad AD |
5867 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
5868 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 5869 | { |
fd0db0ed | 5870 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5871 | u32 vlan_macip_lens = 0; |
5872 | u32 mss_l4len_idx = 0; | |
5873 | u32 type_tucmd = 0; | |
7ca647bd | 5874 | |
897ab156 | 5875 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
244e27ad AD |
5876 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
5877 | !(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
5878 | return; | |
897ab156 AD |
5879 | } else { |
5880 | u8 l4_hdr = 0; | |
244e27ad | 5881 | switch (first->protocol) { |
897ab156 AD |
5882 | case __constant_htons(ETH_P_IP): |
5883 | vlan_macip_lens |= skb_network_header_len(skb); | |
5884 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
5885 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 5886 | break; |
897ab156 AD |
5887 | case __constant_htons(ETH_P_IPV6): |
5888 | vlan_macip_lens |= skb_network_header_len(skb); | |
5889 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
5890 | break; | |
5891 | default: | |
5892 | if (unlikely(net_ratelimit())) { | |
5893 | dev_warn(tx_ring->dev, | |
5894 | "partial checksum but proto=%x!\n", | |
244e27ad | 5895 | first->protocol); |
897ab156 | 5896 | } |
7ca647bd JP |
5897 | break; |
5898 | } | |
897ab156 AD |
5899 | |
5900 | switch (l4_hdr) { | |
7ca647bd | 5901 | case IPPROTO_TCP: |
897ab156 AD |
5902 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
5903 | mss_l4len_idx = tcp_hdrlen(skb) << | |
5904 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
5905 | break; |
5906 | case IPPROTO_SCTP: | |
897ab156 AD |
5907 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
5908 | mss_l4len_idx = sizeof(struct sctphdr) << | |
5909 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5910 | break; | |
5911 | case IPPROTO_UDP: | |
5912 | mss_l4len_idx = sizeof(struct udphdr) << | |
5913 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5914 | break; | |
5915 | default: | |
5916 | if (unlikely(net_ratelimit())) { | |
5917 | dev_warn(tx_ring->dev, | |
5918 | "partial checksum but l4 proto=%x!\n", | |
244e27ad | 5919 | l4_hdr); |
897ab156 | 5920 | } |
7ca647bd JP |
5921 | break; |
5922 | } | |
244e27ad AD |
5923 | |
5924 | /* update TX checksum flag */ | |
5925 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
5926 | } |
5927 | ||
244e27ad | 5928 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
897ab156 | 5929 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 5930 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 5931 | |
897ab156 AD |
5932 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
5933 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
5934 | } |
5935 | ||
d3d00239 | 5936 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 5937 | { |
d3d00239 AD |
5938 | /* set type for advanced descriptor with frame checksum insertion */ |
5939 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
5940 | IXGBE_ADVTXD_DCMD_IFCS | | |
5941 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 5942 | |
d3d00239 | 5943 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 5944 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 5945 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 5946 | |
3a6a4eda JK |
5947 | #ifdef CONFIG_IXGBE_PTP |
5948 | if (tx_flags & IXGBE_TX_FLAGS_TSTAMP) | |
5949 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP); | |
5950 | #endif | |
5951 | ||
d3d00239 AD |
5952 | /* set segmentation enable bits for TSO/FSO */ |
5953 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 5954 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
5955 | #else |
5956 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
5957 | #endif | |
5958 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 5959 | |
d3d00239 AD |
5960 | return cmd_type; |
5961 | } | |
9a799d71 | 5962 | |
729739b7 AD |
5963 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
5964 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 5965 | { |
93f5b3c1 | 5966 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 5967 | |
d3d00239 AD |
5968 | /* enable L4 checksum for TSO and TX checksum offload */ |
5969 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5970 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 5971 | |
93f5b3c1 AD |
5972 | /* enble IPv4 checksum for TSO */ |
5973 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
5974 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 5975 | |
93f5b3c1 AD |
5976 | /* use index 1 context for TSO/FSO/FCOE */ |
5977 | #ifdef IXGBE_FCOE | |
5978 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
5979 | #else | |
5980 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 5981 | #endif |
93f5b3c1 AD |
5982 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
5983 | ||
7f9643fd AD |
5984 | /* |
5985 | * Check Context must be set if Tx switch is enabled, which it | |
5986 | * always is for case where virtual functions are running | |
5987 | */ | |
93f5b3c1 AD |
5988 | #ifdef IXGBE_FCOE |
5989 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
5990 | #else | |
7f9643fd | 5991 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 5992 | #endif |
7f9643fd AD |
5993 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
5994 | ||
729739b7 | 5995 | tx_desc->read.olinfo_status = olinfo_status; |
d3d00239 | 5996 | } |
44df32c5 | 5997 | |
d3d00239 AD |
5998 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
5999 | IXGBE_TXD_CMD_RS) | |
6000 | ||
6001 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 6002 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
6003 | const u8 hdr_len) |
6004 | { | |
729739b7 | 6005 | dma_addr_t dma; |
fd0db0ed | 6006 | struct sk_buff *skb = first->skb; |
729739b7 | 6007 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 6008 | union ixgbe_adv_tx_desc *tx_desc; |
729739b7 | 6009 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
d3d00239 AD |
6010 | unsigned int data_len = skb->data_len; |
6011 | unsigned int size = skb_headlen(skb); | |
729739b7 | 6012 | unsigned int paylen = skb->len - hdr_len; |
244e27ad | 6013 | u32 tx_flags = first->tx_flags; |
729739b7 | 6014 | __le32 cmd_type; |
d3d00239 | 6015 | u16 i = tx_ring->next_to_use; |
d3d00239 | 6016 | |
729739b7 AD |
6017 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
6018 | ||
6019 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); | |
6020 | cmd_type = ixgbe_tx_cmd_type(tx_flags); | |
6021 | ||
d3d00239 AD |
6022 | #ifdef IXGBE_FCOE |
6023 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 6024 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
6025 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
6026 | data_len = 0; | |
729739b7 AD |
6027 | } else { |
6028 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
6029 | } |
6030 | } | |
44df32c5 | 6031 | |
d3d00239 | 6032 | #endif |
729739b7 AD |
6033 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
6034 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6035 | goto dma_error; |
8ad494b0 | 6036 | |
729739b7 AD |
6037 | /* record length, and DMA address */ |
6038 | dma_unmap_len_set(first, len, size); | |
6039 | dma_unmap_addr_set(first, dma, dma); | |
9a799d71 | 6040 | |
729739b7 | 6041 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
e5a43549 | 6042 | |
d3d00239 | 6043 | for (;;) { |
729739b7 | 6044 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 AD |
6045 | tx_desc->read.cmd_type_len = |
6046 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
e5a43549 | 6047 | |
d3d00239 | 6048 | i++; |
729739b7 | 6049 | tx_desc++; |
d3d00239 | 6050 | if (i == tx_ring->count) { |
e4f74028 | 6051 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
6052 | i = 0; |
6053 | } | |
729739b7 AD |
6054 | |
6055 | dma += IXGBE_MAX_DATA_PER_TXD; | |
6056 | size -= IXGBE_MAX_DATA_PER_TXD; | |
6057 | ||
6058 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
6059 | tx_desc->read.olinfo_status = 0; | |
d3d00239 | 6060 | } |
e5a43549 | 6061 | |
729739b7 AD |
6062 | if (likely(!data_len)) |
6063 | break; | |
9a799d71 | 6064 | |
f43f313e BG |
6065 | if (unlikely(skb->no_fcs)) |
6066 | cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS)); | |
d3d00239 | 6067 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9a799d71 | 6068 | |
729739b7 AD |
6069 | i++; |
6070 | tx_desc++; | |
6071 | if (i == tx_ring->count) { | |
6072 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
6073 | i = 0; | |
6074 | } | |
9a799d71 | 6075 | |
d3d00239 | 6076 | #ifdef IXGBE_FCOE |
9e903e08 | 6077 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 6078 | #else |
9e903e08 | 6079 | size = skb_frag_size(frag); |
d3d00239 AD |
6080 | #endif |
6081 | data_len -= size; | |
9a799d71 | 6082 | |
729739b7 AD |
6083 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
6084 | DMA_TO_DEVICE); | |
6085 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6086 | goto dma_error; |
9a799d71 | 6087 | |
729739b7 AD |
6088 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6089 | dma_unmap_len_set(tx_buffer, len, size); | |
6090 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
9a799d71 | 6091 | |
729739b7 AD |
6092 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
6093 | tx_desc->read.olinfo_status = 0; | |
9a799d71 | 6094 | |
729739b7 AD |
6095 | frag++; |
6096 | } | |
9a799d71 | 6097 | |
729739b7 AD |
6098 | /* write last descriptor with RS and EOP bits */ |
6099 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
6100 | tx_desc->read.cmd_type_len = cmd_type; | |
eacd73f7 | 6101 | |
091a6246 | 6102 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 6103 | |
d3d00239 AD |
6104 | /* set the timestamp */ |
6105 | first->time_stamp = jiffies; | |
9a799d71 AK |
6106 | |
6107 | /* | |
729739b7 AD |
6108 | * Force memory writes to complete before letting h/w know there |
6109 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
6110 | * memory model archs, such as IA-64). | |
6111 | * | |
6112 | * We also need this memory barrier to make certain all of the | |
6113 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
6114 | */ |
6115 | wmb(); | |
6116 | ||
d3d00239 AD |
6117 | /* set next_to_watch value indicating a packet is present */ |
6118 | first->next_to_watch = tx_desc; | |
6119 | ||
729739b7 AD |
6120 | i++; |
6121 | if (i == tx_ring->count) | |
6122 | i = 0; | |
6123 | ||
6124 | tx_ring->next_to_use = i; | |
6125 | ||
d3d00239 | 6126 | /* notify HW of packet */ |
84ea2591 | 6127 | writel(i, tx_ring->tail); |
d3d00239 AD |
6128 | |
6129 | return; | |
6130 | dma_error: | |
729739b7 | 6131 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
6132 | |
6133 | /* clear dma mappings for failed tx_buffer_info map */ | |
6134 | for (;;) { | |
729739b7 AD |
6135 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6136 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
6137 | if (tx_buffer == first) | |
d3d00239 AD |
6138 | break; |
6139 | if (i == 0) | |
6140 | i = tx_ring->count; | |
6141 | i--; | |
6142 | } | |
6143 | ||
d3d00239 | 6144 | tx_ring->next_to_use = i; |
9a799d71 AK |
6145 | } |
6146 | ||
fd0db0ed | 6147 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 6148 | struct ixgbe_tx_buffer *first) |
69830529 AD |
6149 | { |
6150 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6151 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6152 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6153 | union { | |
6154 | unsigned char *network; | |
6155 | struct iphdr *ipv4; | |
6156 | struct ipv6hdr *ipv6; | |
6157 | } hdr; | |
ee9e0f0b | 6158 | struct tcphdr *th; |
905e4a41 | 6159 | __be16 vlan_id; |
c4cf55e5 | 6160 | |
69830529 AD |
6161 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6162 | if (!q_vector) | |
6163 | return; | |
6164 | ||
6165 | /* do nothing if sampling is disabled */ | |
6166 | if (!ring->atr_sample_rate) | |
d3ead241 | 6167 | return; |
c4cf55e5 | 6168 | |
69830529 | 6169 | ring->atr_count++; |
c4cf55e5 | 6170 | |
69830529 | 6171 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6172 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6173 | |
6174 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
244e27ad | 6175 | if ((first->protocol != __constant_htons(ETH_P_IPV6) || |
69830529 | 6176 | hdr.ipv6->nexthdr != IPPROTO_TCP) && |
244e27ad | 6177 | (first->protocol != __constant_htons(ETH_P_IP) || |
69830529 AD |
6178 | hdr.ipv4->protocol != IPPROTO_TCP)) |
6179 | return; | |
ee9e0f0b | 6180 | |
fd0db0ed | 6181 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6182 | |
66f32a8b AD |
6183 | /* skip this packet since it is invalid or the socket is closing */ |
6184 | if (!th || th->fin) | |
69830529 AD |
6185 | return; |
6186 | ||
6187 | /* sample on all syn packets or once every atr sample count */ | |
6188 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6189 | return; | |
6190 | ||
6191 | /* reset sample count */ | |
6192 | ring->atr_count = 0; | |
6193 | ||
244e27ad | 6194 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
6195 | |
6196 | /* | |
6197 | * src and dst are inverted, think how the receiver sees them | |
6198 | * | |
6199 | * The input is broken into two sections, a non-compressed section | |
6200 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6201 | * is XORed together and stored in the compressed dword. | |
6202 | */ | |
6203 | input.formatted.vlan_id = vlan_id; | |
6204 | ||
6205 | /* | |
6206 | * since src port and flex bytes occupy the same word XOR them together | |
6207 | * and write the value to source port portion of compressed dword | |
6208 | */ | |
244e27ad | 6209 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6210 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6211 | else | |
244e27ad | 6212 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
6213 | common.port.dst ^= th->source; |
6214 | ||
244e27ad | 6215 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
69830529 AD |
6216 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
6217 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6218 | } else { | |
6219 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6220 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6221 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6222 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6223 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6224 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6225 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6226 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6227 | hdr.ipv6->daddr.s6_addr32[3]; | |
6228 | } | |
c4cf55e5 PWJ |
6229 | |
6230 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6231 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6232 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6233 | } |
6234 | ||
63544e9c | 6235 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6236 | { |
fc77dc3c | 6237 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6238 | /* Herbert's original patch had: |
6239 | * smp_mb__after_netif_stop_queue(); | |
6240 | * but since that doesn't exist yet, just open code it. */ | |
6241 | smp_mb(); | |
6242 | ||
6243 | /* We need to check again in a case another CPU has just | |
6244 | * made room available. */ | |
7d4987de | 6245 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6246 | return -EBUSY; |
6247 | ||
6248 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6249 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6250 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6251 | return 0; |
6252 | } | |
6253 | ||
82d4e46e | 6254 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6255 | { |
7d4987de | 6256 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 6257 | return 0; |
fc77dc3c | 6258 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6259 | } |
6260 | ||
09a3b1f8 SH |
6261 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6262 | { | |
6263 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
6264 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
6265 | smp_processor_id(); | |
56075a98 | 6266 | #ifdef IXGBE_FCOE |
6440752c | 6267 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 6268 | |
e5b64635 JF |
6269 | if (((protocol == htons(ETH_P_FCOE)) || |
6270 | (protocol == htons(ETH_P_FIP))) && | |
6271 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
c087663e AD |
6272 | struct ixgbe_ring_feature *f; |
6273 | ||
6274 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6275 | ||
6276 | while (txq >= f->indices) | |
6277 | txq -= f->indices; | |
e4b317e9 | 6278 | txq += adapter->ring_feature[RING_F_FCOE].offset; |
c087663e | 6279 | |
e5b64635 | 6280 | return txq; |
56075a98 JF |
6281 | } |
6282 | #endif | |
6283 | ||
fdd3d631 KK |
6284 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6285 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6286 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6287 | return txq; |
fdd3d631 | 6288 | } |
c4cf55e5 | 6289 | |
09a3b1f8 SH |
6290 | return skb_tx_hash(dev, skb); |
6291 | } | |
6292 | ||
fc77dc3c | 6293 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6294 | struct ixgbe_adapter *adapter, |
6295 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6296 | { |
d3d00239 | 6297 | struct ixgbe_tx_buffer *first; |
5f715823 | 6298 | int tso; |
d3d00239 | 6299 | u32 tx_flags = 0; |
a535c30e AD |
6300 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
6301 | unsigned short f; | |
6302 | #endif | |
a535c30e | 6303 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 6304 | __be16 protocol = skb->protocol; |
63544e9c | 6305 | u8 hdr_len = 0; |
5e09a105 | 6306 | |
a535c30e AD |
6307 | /* |
6308 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 6309 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
6310 | * + 2 desc gap to keep tail from touching head, |
6311 | * + 1 desc for context descriptor, | |
6312 | * otherwise try next time | |
6313 | */ | |
6314 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
6315 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
6316 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
6317 | #else | |
6318 | count += skb_shinfo(skb)->nr_frags; | |
6319 | #endif | |
6320 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
6321 | tx_ring->tx_stats.tx_busy++; | |
6322 | return NETDEV_TX_BUSY; | |
6323 | } | |
6324 | ||
fd0db0ed AD |
6325 | /* record the location of the first descriptor for this packet */ |
6326 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
6327 | first->skb = skb; | |
091a6246 AD |
6328 | first->bytecount = skb->len; |
6329 | first->gso_segs = 1; | |
fd0db0ed | 6330 | |
66f32a8b | 6331 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 6332 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
6333 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
6334 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
6335 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
6336 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6337 | struct vlan_hdr *vhdr, _vhdr; | |
6338 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
6339 | if (!vhdr) | |
6340 | goto out_drop; | |
6341 | ||
6342 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
6343 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
6344 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
6345 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
6346 | } | |
6347 | ||
aa7bd467 JK |
6348 | skb_tx_timestamp(skb); |
6349 | ||
3a6a4eda JK |
6350 | #ifdef CONFIG_IXGBE_PTP |
6351 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { | |
6352 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
6353 | tx_flags |= IXGBE_TX_FLAGS_TSTAMP; | |
6354 | } | |
6355 | #endif | |
6356 | ||
9e0c5648 AD |
6357 | #ifdef CONFIG_PCI_IOV |
6358 | /* | |
6359 | * Use the l2switch_enable flag - would be false if the DMA | |
6360 | * Tx switch had been disabled. | |
6361 | */ | |
6362 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6363 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
6364 | ||
6365 | #endif | |
32701dc2 | 6366 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 6367 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
6368 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
6369 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 6370 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
6371 | tx_flags |= (skb->priority & 0x7) << |
6372 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
6373 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
6374 | struct vlan_ethhdr *vhdr; | |
6375 | if (skb_header_cloned(skb) && | |
6376 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
6377 | goto out_drop; | |
6378 | vhdr = (struct vlan_ethhdr *)skb->data; | |
6379 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
6380 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6381 | } else { | |
6382 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 6383 | } |
9a799d71 | 6384 | } |
eacd73f7 | 6385 | |
244e27ad AD |
6386 | /* record initial flags and protocol */ |
6387 | first->tx_flags = tx_flags; | |
6388 | first->protocol = protocol; | |
6389 | ||
eacd73f7 | 6390 | #ifdef IXGBE_FCOE |
66f32a8b AD |
6391 | /* setup tx offload for FCoE */ |
6392 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
a58915c7 | 6393 | (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { |
244e27ad | 6394 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
6395 | if (tso < 0) |
6396 | goto out_drop; | |
9a799d71 | 6397 | |
66f32a8b | 6398 | goto xmit_fcoe; |
eacd73f7 | 6399 | } |
9a799d71 | 6400 | |
66f32a8b | 6401 | #endif /* IXGBE_FCOE */ |
244e27ad | 6402 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 6403 | if (tso < 0) |
897ab156 | 6404 | goto out_drop; |
244e27ad AD |
6405 | else if (!tso) |
6406 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
6407 | |
6408 | /* add the ATR filter if ATR is on */ | |
6409 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 6410 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
6411 | |
6412 | #ifdef IXGBE_FCOE | |
6413 | xmit_fcoe: | |
6414 | #endif /* IXGBE_FCOE */ | |
244e27ad | 6415 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 AD |
6416 | |
6417 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
6418 | |
6419 | return NETDEV_TX_OK; | |
897ab156 AD |
6420 | |
6421 | out_drop: | |
fd0db0ed AD |
6422 | dev_kfree_skb_any(first->skb); |
6423 | first->skb = NULL; | |
6424 | ||
897ab156 | 6425 | return NETDEV_TX_OK; |
9a799d71 AK |
6426 | } |
6427 | ||
a50c29dd AD |
6428 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
6429 | struct net_device *netdev) | |
84418e3b AD |
6430 | { |
6431 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6432 | struct ixgbe_ring *tx_ring; | |
6433 | ||
a50c29dd AD |
6434 | /* |
6435 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
6436 | * in order to meet this minimum size requirement. | |
6437 | */ | |
f73332fc SH |
6438 | if (unlikely(skb->len < 17)) { |
6439 | if (skb_pad(skb, 17 - skb->len)) | |
a50c29dd AD |
6440 | return NETDEV_TX_OK; |
6441 | skb->len = 17; | |
6442 | } | |
6443 | ||
84418e3b | 6444 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 6445 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6446 | } |
6447 | ||
9a799d71 AK |
6448 | /** |
6449 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6450 | * @netdev: network interface device structure | |
6451 | * @p: pointer to an address structure | |
6452 | * | |
6453 | * Returns 0 on success, negative on failure | |
6454 | **/ | |
6455 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6456 | { | |
6457 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6458 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6459 | struct sockaddr *addr = p; |
6460 | ||
6461 | if (!is_valid_ether_addr(addr->sa_data)) | |
6462 | return -EADDRNOTAVAIL; | |
6463 | ||
6464 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6465 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6466 | |
1d9c0bfd | 6467 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV); |
9a799d71 AK |
6468 | |
6469 | return 0; | |
6470 | } | |
6471 | ||
6b73e10d BH |
6472 | static int |
6473 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6474 | { | |
6475 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6476 | struct ixgbe_hw *hw = &adapter->hw; | |
6477 | u16 value; | |
6478 | int rc; | |
6479 | ||
6480 | if (prtad != hw->phy.mdio.prtad) | |
6481 | return -EINVAL; | |
6482 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6483 | if (!rc) | |
6484 | rc = value; | |
6485 | return rc; | |
6486 | } | |
6487 | ||
6488 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6489 | u16 addr, u16 value) | |
6490 | { | |
6491 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6492 | struct ixgbe_hw *hw = &adapter->hw; | |
6493 | ||
6494 | if (prtad != hw->phy.mdio.prtad) | |
6495 | return -EINVAL; | |
6496 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6497 | } | |
6498 | ||
6499 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6500 | { | |
6501 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6502 | ||
3a6a4eda JK |
6503 | switch (cmd) { |
6504 | #ifdef CONFIG_IXGBE_PTP | |
6505 | case SIOCSHWTSTAMP: | |
6506 | return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd); | |
6507 | #endif | |
6508 | default: | |
6509 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6510 | } | |
6b73e10d BH |
6511 | } |
6512 | ||
0365e6e4 PW |
6513 | /** |
6514 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6515 | * netdev->dev_addrs |
0365e6e4 PW |
6516 | * @netdev: network interface device structure |
6517 | * | |
6518 | * Returns non-zero on failure | |
6519 | **/ | |
6520 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6521 | { | |
6522 | int err = 0; | |
6523 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7fa7c9dc | 6524 | struct ixgbe_hw *hw = &adapter->hw; |
0365e6e4 | 6525 | |
7fa7c9dc | 6526 | if (is_valid_ether_addr(hw->mac.san_addr)) { |
0365e6e4 | 6527 | rtnl_lock(); |
7fa7c9dc | 6528 | err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); |
0365e6e4 | 6529 | rtnl_unlock(); |
7fa7c9dc AD |
6530 | |
6531 | /* update SAN MAC vmdq pool selection */ | |
6532 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
0365e6e4 PW |
6533 | } |
6534 | return err; | |
6535 | } | |
6536 | ||
6537 | /** | |
6538 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6539 | * netdev->dev_addrs |
0365e6e4 PW |
6540 | * @netdev: network interface device structure |
6541 | * | |
6542 | * Returns non-zero on failure | |
6543 | **/ | |
6544 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6545 | { | |
6546 | int err = 0; | |
6547 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6548 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6549 | ||
6550 | if (is_valid_ether_addr(mac->san_addr)) { | |
6551 | rtnl_lock(); | |
6552 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6553 | rtnl_unlock(); | |
6554 | } | |
6555 | return err; | |
6556 | } | |
6557 | ||
9a799d71 AK |
6558 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6559 | /* | |
6560 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6561 | * without having to re-enable interrupts. It's not called while | |
6562 | * the interrupt routine is executing. | |
6563 | */ | |
6564 | static void ixgbe_netpoll(struct net_device *netdev) | |
6565 | { | |
6566 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6567 | int i; |
9a799d71 | 6568 | |
1a647bd2 AD |
6569 | /* if interface is down do nothing */ |
6570 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6571 | return; | |
6572 | ||
9a799d71 | 6573 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 | 6574 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
49c7ffbe AD |
6575 | for (i = 0; i < adapter->num_q_vectors; i++) |
6576 | ixgbe_msix_clean_rings(0, adapter->q_vector[i]); | |
8f9a7167 PWJ |
6577 | } else { |
6578 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6579 | } | |
9a799d71 | 6580 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 | 6581 | } |
9a799d71 | 6582 | |
581330ba | 6583 | #endif |
de1036b1 ED |
6584 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6585 | struct rtnl_link_stats64 *stats) | |
6586 | { | |
6587 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6588 | int i; | |
6589 | ||
1a51502b | 6590 | rcu_read_lock(); |
de1036b1 | 6591 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6592 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6593 | u64 bytes, packets; |
6594 | unsigned int start; | |
6595 | ||
1a51502b ED |
6596 | if (ring) { |
6597 | do { | |
6598 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6599 | packets = ring->stats.packets; | |
6600 | bytes = ring->stats.bytes; | |
6601 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6602 | stats->rx_packets += packets; | |
6603 | stats->rx_bytes += bytes; | |
6604 | } | |
de1036b1 | 6605 | } |
1ac9ad13 ED |
6606 | |
6607 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6608 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6609 | u64 bytes, packets; | |
6610 | unsigned int start; | |
6611 | ||
6612 | if (ring) { | |
6613 | do { | |
6614 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6615 | packets = ring->stats.packets; | |
6616 | bytes = ring->stats.bytes; | |
6617 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6618 | stats->tx_packets += packets; | |
6619 | stats->tx_bytes += bytes; | |
6620 | } | |
6621 | } | |
1a51502b | 6622 | rcu_read_unlock(); |
de1036b1 ED |
6623 | /* following stats updated by ixgbe_watchdog_task() */ |
6624 | stats->multicast = netdev->stats.multicast; | |
6625 | stats->rx_errors = netdev->stats.rx_errors; | |
6626 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6627 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6628 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6629 | return stats; | |
6630 | } | |
6631 | ||
8af3c33f | 6632 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c BH |
6633 | /** |
6634 | * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. | |
6635 | * @adapter: pointer to ixgbe_adapter | |
8b1c0b24 JF |
6636 | * @tc: number of traffic classes currently enabled |
6637 | * | |
6638 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
6639 | * 802.1Q priority maps to a packet buffer that exists. | |
6640 | */ | |
6641 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
6642 | { | |
6643 | struct ixgbe_hw *hw = &adapter->hw; | |
6644 | u32 reg, rsave; | |
6645 | int i; | |
6646 | ||
6647 | /* 82598 have a static priority to TC mapping that can not | |
6648 | * be changed so no validation is needed. | |
6649 | */ | |
6650 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6651 | return; | |
6652 | ||
6653 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
6654 | rsave = reg; | |
6655 | ||
6656 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
6657 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
6658 | ||
6659 | /* If up2tc is out of bounds default to zero */ | |
6660 | if (up2tc > tc) | |
6661 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
6662 | } | |
6663 | ||
6664 | if (reg != rsave) | |
6665 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
6666 | ||
6667 | return; | |
6668 | } | |
6669 | ||
02debdc9 AD |
6670 | /** |
6671 | * ixgbe_set_prio_tc_map - Configure netdev prio tc map | |
6672 | * @adapter: Pointer to adapter struct | |
6673 | * | |
6674 | * Populate the netdev user priority to tc map | |
6675 | */ | |
6676 | static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) | |
6677 | { | |
6678 | struct net_device *dev = adapter->netdev; | |
6679 | struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; | |
6680 | struct ieee_ets *ets = adapter->ixgbe_ieee_ets; | |
6681 | u8 prio; | |
6682 | ||
6683 | for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { | |
6684 | u8 tc = 0; | |
6685 | ||
6686 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) | |
6687 | tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); | |
6688 | else if (ets) | |
6689 | tc = ets->prio_tc[prio]; | |
6690 | ||
6691 | netdev_set_prio_tc_map(dev, prio, tc); | |
6692 | } | |
6693 | } | |
6694 | ||
49ce9c2c BH |
6695 | /** |
6696 | * ixgbe_setup_tc - configure net_device for multiple traffic classes | |
8b1c0b24 JF |
6697 | * |
6698 | * @netdev: net device to configure | |
6699 | * @tc: number of traffic classes to enable | |
6700 | */ | |
6701 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
6702 | { | |
8b1c0b24 JF |
6703 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
6704 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 6705 | |
e7589eab JF |
6706 | /* Multiple traffic classes requires multiple queues */ |
6707 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
6708 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
6709 | return -EINVAL; | |
6710 | } | |
8b1c0b24 JF |
6711 | |
6712 | /* Hardware supports up to 8 traffic classes */ | |
4de2a022 | 6713 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
581330ba AD |
6714 | (hw->mac.type == ixgbe_mac_82598EB && |
6715 | tc < MAX_TRAFFIC_CLASS)) | |
8b1c0b24 JF |
6716 | return -EINVAL; |
6717 | ||
6718 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 6719 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
6720 | * hardware is not flexible enough to do this dynamically. |
6721 | */ | |
6722 | if (netif_running(dev)) | |
6723 | ixgbe_close(dev); | |
6724 | ixgbe_clear_interrupt_scheme(adapter); | |
6725 | ||
e7589eab | 6726 | if (tc) { |
8b1c0b24 | 6727 | netdev_set_num_tc(dev, tc); |
02debdc9 AD |
6728 | ixgbe_set_prio_tc_map(adapter); |
6729 | ||
e7589eab | 6730 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
e7589eab | 6731 | |
943561d3 AD |
6732 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
6733 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 6734 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 6735 | } |
e7589eab | 6736 | } else { |
8b1c0b24 | 6737 | netdev_reset_tc(dev); |
02debdc9 | 6738 | |
943561d3 AD |
6739 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
6740 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
6741 | |
6742 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
e7589eab JF |
6743 | |
6744 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
6745 | adapter->dcb_cfg.pfc_mode_enable = false; | |
6746 | } | |
6747 | ||
8b1c0b24 JF |
6748 | ixgbe_init_interrupt_scheme(adapter); |
6749 | ixgbe_validate_rtr(adapter, tc); | |
6750 | if (netif_running(dev)) | |
6751 | ixgbe_open(dev); | |
6752 | ||
6753 | return 0; | |
6754 | } | |
de1036b1 | 6755 | |
8af3c33f | 6756 | #endif /* CONFIG_IXGBE_DCB */ |
082757af DS |
6757 | void ixgbe_do_reset(struct net_device *netdev) |
6758 | { | |
6759 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6760 | ||
6761 | if (netif_running(netdev)) | |
6762 | ixgbe_reinit_locked(adapter); | |
6763 | else | |
6764 | ixgbe_reset(adapter); | |
6765 | } | |
6766 | ||
c8f44aff | 6767 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 6768 | netdev_features_t features) |
082757af DS |
6769 | { |
6770 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6771 | ||
082757af | 6772 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ |
567d2de2 AD |
6773 | if (!(features & NETIF_F_RXCSUM)) |
6774 | features &= ~NETIF_F_LRO; | |
082757af | 6775 | |
567d2de2 AD |
6776 | /* Turn off LRO if not RSC capable */ |
6777 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
6778 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 6779 | |
567d2de2 | 6780 | return features; |
082757af DS |
6781 | } |
6782 | ||
c8f44aff | 6783 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 6784 | netdev_features_t features) |
082757af DS |
6785 | { |
6786 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 6787 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
6788 | bool need_reset = false; |
6789 | ||
082757af | 6790 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
6791 | if (!(features & NETIF_F_LRO)) { |
6792 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 6793 | need_reset = true; |
567d2de2 AD |
6794 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
6795 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
6796 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
6797 | if (adapter->rx_itr_setting == 1 || | |
6798 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
6799 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
6800 | need_reset = true; | |
6801 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
6802 | e_info(probe, "rx-usecs set too low, " | |
6803 | "disabling RSC\n"); | |
082757af DS |
6804 | } |
6805 | } | |
6806 | ||
6807 | /* | |
6808 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
6809 | * the state changed, we need to reset. | |
6810 | */ | |
39cb681b AD |
6811 | switch (features & NETIF_F_NTUPLE) { |
6812 | case NETIF_F_NTUPLE: | |
567d2de2 | 6813 | /* turn off ATR, enable perfect filters and reset */ |
39cb681b AD |
6814 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) |
6815 | need_reset = true; | |
6816 | ||
567d2de2 AD |
6817 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
6818 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
39cb681b AD |
6819 | break; |
6820 | default: | |
6821 | /* turn off perfect filters, enable ATR and reset */ | |
6822 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6823 | need_reset = true; | |
6824 | ||
6825 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
6826 | ||
6827 | /* We cannot enable ATR if SR-IOV is enabled */ | |
6828 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6829 | break; | |
6830 | ||
6831 | /* We cannot enable ATR if we have 2 or more traffic classes */ | |
6832 | if (netdev_get_num_tc(netdev) > 1) | |
6833 | break; | |
6834 | ||
6835 | /* We cannot enable ATR if RSS is disabled */ | |
6836 | if (adapter->ring_feature[RING_F_RSS].limit <= 1) | |
6837 | break; | |
6838 | ||
6839 | /* A sample rate of 0 indicates ATR disabled */ | |
6840 | if (!adapter->atr_sample_rate) | |
6841 | break; | |
6842 | ||
6843 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6844 | break; | |
082757af DS |
6845 | } |
6846 | ||
146d4cc9 JF |
6847 | if (features & NETIF_F_HW_VLAN_RX) |
6848 | ixgbe_vlan_strip_enable(adapter); | |
6849 | else | |
6850 | ixgbe_vlan_strip_disable(adapter); | |
6851 | ||
3f2d1c0f BG |
6852 | if (changed & NETIF_F_RXALL) |
6853 | need_reset = true; | |
6854 | ||
567d2de2 | 6855 | netdev->features = features; |
082757af DS |
6856 | if (need_reset) |
6857 | ixgbe_do_reset(netdev); | |
6858 | ||
6859 | return 0; | |
082757af DS |
6860 | } |
6861 | ||
0f4b0add JF |
6862 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, |
6863 | struct net_device *dev, | |
6864 | unsigned char *addr, | |
6865 | u16 flags) | |
6866 | { | |
6867 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
95447461 JF |
6868 | int err; |
6869 | ||
6870 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
6871 | return -EOPNOTSUPP; | |
0f4b0add JF |
6872 | |
6873 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6874 | pr_info("%s: FDB only supports static addresses\n", | |
6875 | ixgbe_driver_name); | |
6876 | return -EINVAL; | |
6877 | } | |
6878 | ||
95447461 JF |
6879 | if (is_unicast_ether_addr(addr)) { |
6880 | u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS; | |
6881 | ||
6882 | if (netdev_uc_count(dev) < rar_uc_entries) | |
0f4b0add | 6883 | err = dev_uc_add_excl(dev, addr); |
0f4b0add | 6884 | else |
95447461 JF |
6885 | err = -ENOMEM; |
6886 | } else if (is_multicast_ether_addr(addr)) { | |
6887 | err = dev_mc_add_excl(dev, addr); | |
6888 | } else { | |
6889 | err = -EINVAL; | |
0f4b0add JF |
6890 | } |
6891 | ||
6892 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
6893 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
6894 | err = 0; | |
6895 | ||
6896 | return err; | |
6897 | } | |
6898 | ||
6899 | static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, | |
6900 | struct net_device *dev, | |
6901 | unsigned char *addr) | |
6902 | { | |
6903 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6904 | int err = -EOPNOTSUPP; | |
6905 | ||
6906 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6907 | pr_info("%s: FDB only supports static addresses\n", | |
6908 | ixgbe_driver_name); | |
6909 | return -EINVAL; | |
6910 | } | |
6911 | ||
6912 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6913 | if (is_unicast_ether_addr(addr)) | |
6914 | err = dev_uc_del(dev, addr); | |
6915 | else if (is_multicast_ether_addr(addr)) | |
6916 | err = dev_mc_del(dev, addr); | |
6917 | else | |
6918 | err = -EINVAL; | |
6919 | } | |
6920 | ||
6921 | return err; | |
6922 | } | |
6923 | ||
6924 | static int ixgbe_ndo_fdb_dump(struct sk_buff *skb, | |
6925 | struct netlink_callback *cb, | |
6926 | struct net_device *dev, | |
6927 | int idx) | |
6928 | { | |
6929 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6930 | ||
6931 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6932 | idx = ndo_dflt_fdb_dump(skb, cb, dev, idx); | |
6933 | ||
6934 | return idx; | |
6935 | } | |
6936 | ||
0edc3527 | 6937 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 6938 | .ndo_open = ixgbe_open, |
0edc3527 | 6939 | .ndo_stop = ixgbe_close, |
00829823 | 6940 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6941 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 6942 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6943 | .ndo_validate_addr = eth_validate_addr, |
6944 | .ndo_set_mac_address = ixgbe_set_mac, | |
6945 | .ndo_change_mtu = ixgbe_change_mtu, | |
6946 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
6947 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
6948 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6949 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6950 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6951 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6952 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
581330ba | 6953 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 6954 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 6955 | .ndo_get_stats64 = ixgbe_get_stats64, |
8af3c33f | 6956 | #ifdef CONFIG_IXGBE_DCB |
24095aa3 | 6957 | .ndo_setup_tc = ixgbe_setup_tc, |
8af3c33f | 6958 | #endif |
0edc3527 SH |
6959 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6960 | .ndo_poll_controller = ixgbe_netpoll, | |
6961 | #endif | |
332d4a7d YZ |
6962 | #ifdef IXGBE_FCOE |
6963 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 6964 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 6965 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
6966 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6967 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6968 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 6969 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 6970 | #endif /* IXGBE_FCOE */ |
082757af DS |
6971 | .ndo_set_features = ixgbe_set_features, |
6972 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add JF |
6973 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
6974 | .ndo_fdb_del = ixgbe_ndo_fdb_del, | |
6975 | .ndo_fdb_dump = ixgbe_ndo_fdb_dump, | |
0edc3527 SH |
6976 | }; |
6977 | ||
8e2813f5 JK |
6978 | /** |
6979 | * ixgbe_wol_supported - Check whether device supports WoL | |
6980 | * @hw: hw specific details | |
6981 | * @device_id: the device ID | |
6982 | * @subdev_id: the subsystem device ID | |
6983 | * | |
6984 | * This function is used by probe and ethtool to determine | |
6985 | * which devices have WoL support | |
6986 | * | |
6987 | **/ | |
6988 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
6989 | u16 subdevice_id) | |
6990 | { | |
6991 | struct ixgbe_hw *hw = &adapter->hw; | |
6992 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
6993 | int is_wol_supported = 0; | |
6994 | ||
6995 | switch (device_id) { | |
6996 | case IXGBE_DEV_ID_82599_SFP: | |
6997 | /* Only these subdevices could supports WOL */ | |
6998 | switch (subdevice_id) { | |
6999 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
7000 | /* only support first port */ | |
7001 | if (hw->bus.func != 0) | |
7002 | break; | |
7003 | case IXGBE_SUBDEV_ID_82599_SFP: | |
7004 | is_wol_supported = 1; | |
7005 | break; | |
7006 | } | |
7007 | break; | |
7008 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: | |
7009 | /* All except this subdevice support WOL */ | |
7010 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
7011 | is_wol_supported = 1; | |
7012 | break; | |
7013 | case IXGBE_DEV_ID_82599_KX4: | |
7014 | is_wol_supported = 1; | |
7015 | break; | |
7016 | case IXGBE_DEV_ID_X540T: | |
7017 | /* check eeprom to see if enabled wol */ | |
7018 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
7019 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
7020 | (hw->bus.func == 0))) { | |
7021 | is_wol_supported = 1; | |
7022 | } | |
7023 | break; | |
7024 | } | |
7025 | ||
7026 | return is_wol_supported; | |
7027 | } | |
7028 | ||
9a799d71 AK |
7029 | /** |
7030 | * ixgbe_probe - Device Initialization Routine | |
7031 | * @pdev: PCI device information struct | |
7032 | * @ent: entry in ixgbe_pci_tbl | |
7033 | * | |
7034 | * Returns 0 on success, negative on failure | |
7035 | * | |
7036 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7037 | * The OS initialization, configuring of the adapter private structure, | |
7038 | * and a hardware reset occur. | |
7039 | **/ | |
7040 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7041 | const struct pci_device_id *ent) |
9a799d71 AK |
7042 | { |
7043 | struct net_device *netdev; | |
7044 | struct ixgbe_adapter *adapter = NULL; | |
7045 | struct ixgbe_hw *hw; | |
7046 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7047 | static int cards_found; |
7048 | int i, err, pci_using_dac; | |
289700db | 7049 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7050 | unsigned int indices = num_possible_cpus(); |
3f4a6f00 | 7051 | unsigned int dcb_max = 0; |
eacd73f7 YZ |
7052 | #ifdef IXGBE_FCOE |
7053 | u16 device_caps; | |
7054 | #endif | |
289700db | 7055 | u32 eec; |
9a799d71 | 7056 | |
bded64a7 AG |
7057 | /* Catch broken hardware that put the wrong VF device ID in |
7058 | * the PCIe SR-IOV capability. | |
7059 | */ | |
7060 | if (pdev->is_virtfn) { | |
7061 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7062 | pci_name(pdev), pdev->vendor, pdev->device); | |
7063 | return -EINVAL; | |
7064 | } | |
7065 | ||
9ce77666 | 7066 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7067 | if (err) |
7068 | return err; | |
7069 | ||
1b507730 NN |
7070 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7071 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7072 | pci_using_dac = 1; |
7073 | } else { | |
1b507730 | 7074 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7075 | if (err) { |
1b507730 NN |
7076 | err = dma_set_coherent_mask(&pdev->dev, |
7077 | DMA_BIT_MASK(32)); | |
9a799d71 | 7078 | if (err) { |
b8bc0421 DC |
7079 | dev_err(&pdev->dev, |
7080 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7081 | goto err_dma; |
7082 | } | |
7083 | } | |
7084 | pci_using_dac = 0; | |
7085 | } | |
7086 | ||
9ce77666 | 7087 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7088 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7089 | if (err) { |
b8bc0421 DC |
7090 | dev_err(&pdev->dev, |
7091 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7092 | goto err_pci_reg; |
7093 | } | |
7094 | ||
19d5afd4 | 7095 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7096 | |
9a799d71 | 7097 | pci_set_master(pdev); |
fb3b27bc | 7098 | pci_save_state(pdev); |
9a799d71 | 7099 | |
e901acd6 | 7100 | #ifdef CONFIG_IXGBE_DCB |
3f4a6f00 JF |
7101 | if (ii->mac == ixgbe_mac_82598EB) |
7102 | dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS, | |
7103 | IXGBE_MAX_RSS_INDICES); | |
7104 | else | |
7105 | dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS, | |
7106 | IXGBE_MAX_FDIR_INDICES); | |
e901acd6 JF |
7107 | #endif |
7108 | ||
c85a2618 JF |
7109 | if (ii->mac == ixgbe_mac_82598EB) |
7110 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7111 | else | |
7112 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7113 | ||
e901acd6 | 7114 | #ifdef IXGBE_FCOE |
c85a2618 JF |
7115 | indices += min_t(unsigned int, num_possible_cpus(), |
7116 | IXGBE_MAX_FCOE_INDICES); | |
7117 | #endif | |
3f4a6f00 | 7118 | indices = max_t(unsigned int, dcb_max, indices); |
c85a2618 | 7119 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7120 | if (!netdev) { |
7121 | err = -ENOMEM; | |
7122 | goto err_alloc_etherdev; | |
7123 | } | |
7124 | ||
9a799d71 AK |
7125 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7126 | ||
9a799d71 | 7127 | adapter = netdev_priv(netdev); |
c60fbb00 | 7128 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7129 | |
7130 | adapter->netdev = netdev; | |
7131 | adapter->pdev = pdev; | |
7132 | hw = &adapter->hw; | |
7133 | hw->back = adapter; | |
b3f4d599 | 7134 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 7135 | |
05857980 | 7136 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7137 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7138 | if (!hw->hw_addr) { |
7139 | err = -EIO; | |
7140 | goto err_ioremap; | |
7141 | } | |
7142 | ||
7143 | for (i = 1; i <= 5; i++) { | |
7144 | if (pci_resource_len(pdev, i) == 0) | |
7145 | continue; | |
7146 | } | |
7147 | ||
0edc3527 | 7148 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7149 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7150 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7151 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7152 | |
9a799d71 AK |
7153 | adapter->bd_number = cards_found; |
7154 | ||
9a799d71 AK |
7155 | /* Setup hw api */ |
7156 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7157 | hw->mac.type = ii->mac; |
9a799d71 | 7158 | |
c44ade9e JB |
7159 | /* EEPROM */ |
7160 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7161 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7162 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7163 | if (!(eec & (1 << 8))) | |
7164 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7165 | ||
7166 | /* PHY */ | |
7167 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7168 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7169 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7170 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7171 | hw->phy.mdio.mmds = 0; | |
7172 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7173 | hw->phy.mdio.dev = netdev; | |
7174 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7175 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7176 | |
8ca783ab | 7177 | ii->get_invariants(hw); |
9a799d71 AK |
7178 | |
7179 | /* setup the private structure */ | |
7180 | err = ixgbe_sw_init(adapter); | |
7181 | if (err) | |
7182 | goto err_sw_init; | |
7183 | ||
e86bff0e | 7184 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7185 | switch (adapter->hw.mac.type) { |
7186 | case ixgbe_mac_82599EB: | |
7187 | case ixgbe_mac_X540: | |
e86bff0e | 7188 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7189 | break; |
7190 | default: | |
7191 | break; | |
7192 | } | |
e86bff0e | 7193 | |
bf069c97 DS |
7194 | /* |
7195 | * If there is a fan on this device and it has failed log the | |
7196 | * failure. | |
7197 | */ | |
7198 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7199 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7200 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7201 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7202 | } |
7203 | ||
8ef78adc PWJ |
7204 | if (allow_unsupported_sfp) |
7205 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
7206 | ||
c44ade9e | 7207 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7208 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7209 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7210 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7211 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7212 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7213 | err = 0; |
7214 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7215 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7216 | "module type was detected.\n"); |
7217 | e_dev_err("Reload the driver after installing a supported " | |
7218 | "module.\n"); | |
04f165ef PW |
7219 | goto err_sw_init; |
7220 | } else if (err) { | |
849c4542 | 7221 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7222 | goto err_sw_init; |
7223 | } | |
7224 | ||
99d74487 AD |
7225 | #ifdef CONFIG_PCI_IOV |
7226 | ixgbe_enable_sriov(adapter, ii); | |
1cdd1ec8 | 7227 | |
99d74487 | 7228 | #endif |
396e799c | 7229 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7230 | NETIF_F_IP_CSUM | |
082757af | 7231 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7232 | NETIF_F_HW_VLAN_TX | |
7233 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7234 | NETIF_F_HW_VLAN_FILTER | |
7235 | NETIF_F_TSO | | |
7236 | NETIF_F_TSO6 | | |
082757af DS |
7237 | NETIF_F_RXHASH | |
7238 | NETIF_F_RXCSUM; | |
9a799d71 | 7239 | |
082757af | 7240 | netdev->hw_features = netdev->features; |
ad31c402 | 7241 | |
58be7666 DS |
7242 | switch (adapter->hw.mac.type) { |
7243 | case ixgbe_mac_82599EB: | |
7244 | case ixgbe_mac_X540: | |
45a5ead0 | 7245 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7246 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7247 | NETIF_F_NTUPLE; | |
58be7666 DS |
7248 | break; |
7249 | default: | |
7250 | break; | |
7251 | } | |
45a5ead0 | 7252 | |
3f2d1c0f BG |
7253 | netdev->hw_features |= NETIF_F_RXALL; |
7254 | ||
ad31c402 JK |
7255 | netdev->vlan_features |= NETIF_F_TSO; |
7256 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7257 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7258 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7259 | netdev->vlan_features |= NETIF_F_SG; |
7260 | ||
01789349 | 7261 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7262 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7263 | |
7a6b6f51 | 7264 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7265 | netdev->dcbnl_ops = &dcbnl_ops; |
7266 | #endif | |
7267 | ||
eacd73f7 | 7268 | #ifdef IXGBE_FCOE |
0d551589 | 7269 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7270 | if (hw->mac.ops.get_device_caps) { |
7271 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7272 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7273 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 | 7274 | } |
7c8ae65a AD |
7275 | |
7276 | adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE; | |
7277 | ||
a58915c7 AD |
7278 | netdev->features |= NETIF_F_FSO | |
7279 | NETIF_F_FCOE_CRC; | |
7280 | ||
7c8ae65a AD |
7281 | netdev->vlan_features |= NETIF_F_FSO | |
7282 | NETIF_F_FCOE_CRC | | |
7283 | NETIF_F_FCOE_MTU; | |
5e09d7f6 | 7284 | } |
eacd73f7 | 7285 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7286 | if (pci_using_dac) { |
9a799d71 | 7287 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7288 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7289 | } | |
9a799d71 | 7290 | |
082757af DS |
7291 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7292 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7293 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7294 | netdev->features |= NETIF_F_LRO; |
7295 | ||
9a799d71 | 7296 | /* make sure the EEPROM is good */ |
c44ade9e | 7297 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7298 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 7299 | err = -EIO; |
35937c05 | 7300 | goto err_sw_init; |
9a799d71 AK |
7301 | } |
7302 | ||
7303 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7304 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7305 | ||
c44ade9e | 7306 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7307 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 7308 | err = -EIO; |
35937c05 | 7309 | goto err_sw_init; |
9a799d71 AK |
7310 | } |
7311 | ||
7086400d | 7312 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 7313 | (unsigned long) adapter); |
9a799d71 | 7314 | |
7086400d AD |
7315 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7316 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7317 | |
021230d4 AV |
7318 | err = ixgbe_init_interrupt_scheme(adapter); |
7319 | if (err) | |
7320 | goto err_sw_init; | |
9a799d71 | 7321 | |
8e2813f5 | 7322 | /* WOL not supported for all devices */ |
c23f5b6b | 7323 | adapter->wol = 0; |
8e2813f5 JK |
7324 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
7325 | if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device)) | |
9417c464 | 7326 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 7327 | |
e8e26350 PW |
7328 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7329 | ||
3a6a4eda JK |
7330 | #ifdef CONFIG_IXGBE_PTP |
7331 | ixgbe_ptp_init(adapter); | |
7332 | #endif /* CONFIG_IXGBE_PTP*/ | |
7333 | ||
15e5209f ET |
7334 | /* save off EEPROM version number */ |
7335 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7336 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7337 | ||
04f165ef PW |
7338 | /* pick up the PCI bus settings for reporting later */ |
7339 | hw->mac.ops.get_bus_info(hw); | |
7340 | ||
9a799d71 | 7341 | /* print bus type/speed/width info */ |
849c4542 | 7342 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7343 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7344 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7345 | "Unknown"), |
7346 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7347 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7348 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7349 | "Unknown"), | |
7350 | netdev->dev_addr); | |
289700db DS |
7351 | |
7352 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7353 | if (err) | |
9fe93afd | 7354 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7355 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7356 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7357 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7358 | part_str); |
e8e26350 | 7359 | else |
289700db DS |
7360 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7361 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7362 | |
e8e26350 | 7363 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7364 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7365 | "not sufficient for optimal performance.\n"); | |
7366 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7367 | "is required.\n"); | |
0c254d86 AK |
7368 | } |
7369 | ||
9a799d71 | 7370 | /* reset the hardware with the new settings */ |
794caeb2 | 7371 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
7372 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7373 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7374 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7375 | "Please be aware there may be issues associated " | |
7376 | "with your hardware. If you are experiencing " | |
7377 | "problems please contact your Intel or hardware " | |
7378 | "representative who provided you with this " | |
7379 | "hardware.\n"); | |
794caeb2 | 7380 | } |
9a799d71 AK |
7381 | strcpy(netdev->name, "eth%d"); |
7382 | err = register_netdev(netdev); | |
7383 | if (err) | |
7384 | goto err_register; | |
7385 | ||
93d3ce8f ET |
7386 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7387 | if (hw->mac.ops.disable_tx_laser && | |
7388 | ((hw->phy.multispeed_fiber) || | |
7389 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && | |
7390 | (hw->mac.type == ixgbe_mac_82599EB)))) | |
7391 | hw->mac.ops.disable_tx_laser(hw); | |
7392 | ||
54386467 JB |
7393 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7394 | netif_carrier_off(netdev); | |
7395 | ||
5dd2d332 | 7396 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7397 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7398 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7399 | ixgbe_setup_dca(adapter); |
7400 | } | |
7401 | #endif | |
1cdd1ec8 | 7402 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7403 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7404 | for (i = 0; i < adapter->num_vfs; i++) |
7405 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7406 | } | |
7407 | ||
2466dd9c JK |
7408 | /* firmware requires driver version to be 0xFFFFFFFF |
7409 | * since os does not support feature | |
7410 | */ | |
9612de92 | 7411 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
7412 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
7413 | 0xFF); | |
9612de92 | 7414 | |
0365e6e4 PW |
7415 | /* add san mac addr to netdev */ |
7416 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7417 | |
ea81875a | 7418 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 | 7419 | cards_found++; |
3ca8bc6d | 7420 | |
1210982b | 7421 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
7422 | if (ixgbe_sysfs_init(adapter)) |
7423 | e_err(probe, "failed to allocate sysfs resources\n"); | |
1210982b | 7424 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7425 | |
9a799d71 AK |
7426 | return 0; |
7427 | ||
7428 | err_register: | |
5eba3699 | 7429 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7430 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 7431 | err_sw_init: |
99d74487 | 7432 | ixgbe_disable_sriov(adapter); |
7086400d | 7433 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7434 | iounmap(hw->hw_addr); |
7435 | err_ioremap: | |
7436 | free_netdev(netdev); | |
7437 | err_alloc_etherdev: | |
e8e9f696 JP |
7438 | pci_release_selected_regions(pdev, |
7439 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7440 | err_pci_reg: |
7441 | err_dma: | |
7442 | pci_disable_device(pdev); | |
7443 | return err; | |
7444 | } | |
7445 | ||
7446 | /** | |
7447 | * ixgbe_remove - Device Removal Routine | |
7448 | * @pdev: PCI device information struct | |
7449 | * | |
7450 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7451 | * that it should release a PCI device. The could be caused by a | |
7452 | * Hot-Plug event, or because the driver is going to be removed from | |
7453 | * memory. | |
7454 | **/ | |
7455 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7456 | { | |
c60fbb00 AD |
7457 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7458 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7459 | |
7460 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 7461 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7462 | |
3a6a4eda JK |
7463 | #ifdef CONFIG_IXGBE_PTP |
7464 | ixgbe_ptp_stop(adapter); | |
7465 | #endif | |
7466 | ||
5dd2d332 | 7467 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7468 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7469 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7470 | dca_remove_requester(&pdev->dev); | |
7471 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7472 | } | |
7473 | ||
7474 | #endif | |
1210982b | 7475 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d | 7476 | ixgbe_sysfs_exit(adapter); |
1210982b | 7477 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7478 | |
0365e6e4 PW |
7479 | /* remove the added san mac */ |
7480 | ixgbe_del_sanmac_netdev(netdev); | |
7481 | ||
c4900be0 DS |
7482 | if (netdev->reg_state == NETREG_REGISTERED) |
7483 | unregister_netdev(netdev); | |
9a799d71 | 7484 | |
9297127b | 7485 | ixgbe_disable_sriov(adapter); |
1cdd1ec8 | 7486 | |
7a921c93 | 7487 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7488 | |
021230d4 | 7489 | ixgbe_release_hw_control(adapter); |
9a799d71 | 7490 | |
2b1588c3 AD |
7491 | #ifdef CONFIG_DCB |
7492 | kfree(adapter->ixgbe_ieee_pfc); | |
7493 | kfree(adapter->ixgbe_ieee_ets); | |
7494 | ||
7495 | #endif | |
9a799d71 | 7496 | iounmap(adapter->hw.hw_addr); |
9ce77666 | 7497 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7498 | IORESOURCE_MEM)); |
9a799d71 | 7499 | |
849c4542 | 7500 | e_dev_info("complete\n"); |
021230d4 | 7501 | |
9a799d71 AK |
7502 | free_netdev(netdev); |
7503 | ||
19d5afd4 | 7504 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7505 | |
9a799d71 AK |
7506 | pci_disable_device(pdev); |
7507 | } | |
7508 | ||
7509 | /** | |
7510 | * ixgbe_io_error_detected - called when PCI error is detected | |
7511 | * @pdev: Pointer to PCI device | |
7512 | * @state: The current pci connection state | |
7513 | * | |
7514 | * This function is called after a PCI bus error affecting | |
7515 | * this device has been detected. | |
7516 | */ | |
7517 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7518 | pci_channel_state_t state) |
9a799d71 | 7519 | { |
c60fbb00 AD |
7520 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7521 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7522 | |
83c61fa9 GR |
7523 | #ifdef CONFIG_PCI_IOV |
7524 | struct pci_dev *bdev, *vfdev; | |
7525 | u32 dw0, dw1, dw2, dw3; | |
7526 | int vf, pos; | |
7527 | u16 req_id, pf_func; | |
7528 | ||
7529 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7530 | adapter->num_vfs == 0) | |
7531 | goto skip_bad_vf_detection; | |
7532 | ||
7533 | bdev = pdev->bus->self; | |
7534 | while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) | |
7535 | bdev = bdev->bus->self; | |
7536 | ||
7537 | if (!bdev) | |
7538 | goto skip_bad_vf_detection; | |
7539 | ||
7540 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
7541 | if (!pos) | |
7542 | goto skip_bad_vf_detection; | |
7543 | ||
7544 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
7545 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
7546 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
7547 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
7548 | ||
7549 | req_id = dw1 >> 16; | |
7550 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
7551 | if (!(req_id & 0x0080)) | |
7552 | goto skip_bad_vf_detection; | |
7553 | ||
7554 | pf_func = req_id & 0x01; | |
7555 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
7556 | unsigned int device_id; | |
7557 | ||
7558 | vf = (req_id & 0x7F) >> 1; | |
7559 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
7560 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
7561 | "%8.8x\tdw3: %8.8x\n", | |
7562 | dw0, dw1, dw2, dw3); | |
7563 | switch (adapter->hw.mac.type) { | |
7564 | case ixgbe_mac_82599EB: | |
7565 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
7566 | break; | |
7567 | case ixgbe_mac_X540: | |
7568 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
7569 | break; | |
7570 | default: | |
7571 | device_id = 0; | |
7572 | break; | |
7573 | } | |
7574 | ||
7575 | /* Find the pci device of the offending VF */ | |
36e90319 | 7576 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); |
83c61fa9 GR |
7577 | while (vfdev) { |
7578 | if (vfdev->devfn == (req_id & 0xFF)) | |
7579 | break; | |
36e90319 | 7580 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
83c61fa9 GR |
7581 | device_id, vfdev); |
7582 | } | |
7583 | /* | |
7584 | * There's a slim chance the VF could have been hot plugged, | |
7585 | * so if it is no longer present we don't need to issue the | |
7586 | * VFLR. Just clean up the AER in that case. | |
7587 | */ | |
7588 | if (vfdev) { | |
7589 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
7590 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
7591 | } | |
7592 | ||
7593 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
7594 | } | |
7595 | ||
7596 | /* | |
7597 | * Even though the error may have occurred on the other port | |
7598 | * we still need to increment the vf error reference count for | |
7599 | * both ports because the I/O resume function will be called | |
7600 | * for both of them. | |
7601 | */ | |
7602 | adapter->vferr_refcount++; | |
7603 | ||
7604 | return PCI_ERS_RESULT_RECOVERED; | |
7605 | ||
7606 | skip_bad_vf_detection: | |
7607 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
7608 | netif_device_detach(netdev); |
7609 | ||
3044b8d1 BL |
7610 | if (state == pci_channel_io_perm_failure) |
7611 | return PCI_ERS_RESULT_DISCONNECT; | |
7612 | ||
9a799d71 AK |
7613 | if (netif_running(netdev)) |
7614 | ixgbe_down(adapter); | |
7615 | pci_disable_device(pdev); | |
7616 | ||
b4617240 | 7617 | /* Request a slot reset. */ |
9a799d71 AK |
7618 | return PCI_ERS_RESULT_NEED_RESET; |
7619 | } | |
7620 | ||
7621 | /** | |
7622 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7623 | * @pdev: Pointer to PCI device | |
7624 | * | |
7625 | * Restart the card from scratch, as if from a cold-boot. | |
7626 | */ | |
7627 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7628 | { | |
c60fbb00 | 7629 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7630 | pci_ers_result_t result; |
7631 | int err; | |
9a799d71 | 7632 | |
9ce77666 | 7633 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7634 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7635 | result = PCI_ERS_RESULT_DISCONNECT; |
7636 | } else { | |
7637 | pci_set_master(pdev); | |
7638 | pci_restore_state(pdev); | |
c0e1f68b | 7639 | pci_save_state(pdev); |
9a799d71 | 7640 | |
dd4d8ca6 | 7641 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7642 | |
6fabd715 | 7643 | ixgbe_reset(adapter); |
88512539 | 7644 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7645 | result = PCI_ERS_RESULT_RECOVERED; |
7646 | } | |
7647 | ||
7648 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7649 | if (err) { | |
849c4542 ET |
7650 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7651 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7652 | /* non-fatal, continue */ |
7653 | } | |
9a799d71 | 7654 | |
6fabd715 | 7655 | return result; |
9a799d71 AK |
7656 | } |
7657 | ||
7658 | /** | |
7659 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7660 | * @pdev: Pointer to PCI device | |
7661 | * | |
7662 | * This callback is called when the error recovery driver tells us that | |
7663 | * its OK to resume normal operation. | |
7664 | */ | |
7665 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7666 | { | |
c60fbb00 AD |
7667 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7668 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7669 | |
83c61fa9 GR |
7670 | #ifdef CONFIG_PCI_IOV |
7671 | if (adapter->vferr_refcount) { | |
7672 | e_info(drv, "Resuming after VF err\n"); | |
7673 | adapter->vferr_refcount--; | |
7674 | return; | |
7675 | } | |
7676 | ||
7677 | #endif | |
c7ccde0f AD |
7678 | if (netif_running(netdev)) |
7679 | ixgbe_up(adapter); | |
9a799d71 AK |
7680 | |
7681 | netif_device_attach(netdev); | |
9a799d71 AK |
7682 | } |
7683 | ||
7684 | static struct pci_error_handlers ixgbe_err_handler = { | |
7685 | .error_detected = ixgbe_io_error_detected, | |
7686 | .slot_reset = ixgbe_io_slot_reset, | |
7687 | .resume = ixgbe_io_resume, | |
7688 | }; | |
7689 | ||
7690 | static struct pci_driver ixgbe_driver = { | |
7691 | .name = ixgbe_driver_name, | |
7692 | .id_table = ixgbe_pci_tbl, | |
7693 | .probe = ixgbe_probe, | |
7694 | .remove = __devexit_p(ixgbe_remove), | |
7695 | #ifdef CONFIG_PM | |
7696 | .suspend = ixgbe_suspend, | |
7697 | .resume = ixgbe_resume, | |
7698 | #endif | |
7699 | .shutdown = ixgbe_shutdown, | |
7700 | .err_handler = &ixgbe_err_handler | |
7701 | }; | |
7702 | ||
7703 | /** | |
7704 | * ixgbe_init_module - Driver Registration Routine | |
7705 | * | |
7706 | * ixgbe_init_module is the first routine called when the driver is | |
7707 | * loaded. All it does is register with the PCI subsystem. | |
7708 | **/ | |
7709 | static int __init ixgbe_init_module(void) | |
7710 | { | |
7711 | int ret; | |
c7689578 | 7712 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7713 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7714 | |
5dd2d332 | 7715 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7716 | dca_register_notify(&dca_notifier); |
bd0362dd | 7717 | #endif |
5dd2d332 | 7718 | |
9a799d71 AK |
7719 | ret = pci_register_driver(&ixgbe_driver); |
7720 | return ret; | |
7721 | } | |
b4617240 | 7722 | |
9a799d71 AK |
7723 | module_init(ixgbe_init_module); |
7724 | ||
7725 | /** | |
7726 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7727 | * | |
7728 | * ixgbe_exit_module is called just before the driver is removed | |
7729 | * from memory. | |
7730 | **/ | |
7731 | static void __exit ixgbe_exit_module(void) | |
7732 | { | |
5dd2d332 | 7733 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7734 | dca_unregister_notify(&dca_notifier); |
7735 | #endif | |
9a799d71 | 7736 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7737 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7738 | } |
bd0362dd | 7739 | |
5dd2d332 | 7740 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7741 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7742 | void *p) |
bd0362dd JC |
7743 | { |
7744 | int ret_val; | |
7745 | ||
7746 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7747 | __ixgbe_notify_dca); |
bd0362dd JC |
7748 | |
7749 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7750 | } | |
b453368d | 7751 | |
5dd2d332 | 7752 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7753 | |
9a799d71 AK |
7754 | module_exit(ixgbe_exit_module); |
7755 | ||
7756 | /* ixgbe_main.c */ |