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Merge branch 'bcmgenet_xmit_more'
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
9be4a9bb 79#define DRV_VERSION "4.0.1-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
0391bbe3 82 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 83
84static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 85 [board_82598] = &ixgbe_82598_info,
86 [board_82599] = &ixgbe_82599_info,
87 [board_X540] = &ixgbe_X540_info,
88 [board_X550] = &ixgbe_X550_info,
89 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 90};
91
92/* ixgbe_pci_tbl - PCI Device ID Table
93 *
94 * Wildcard entries (PCI_ANY_ID) should come last
95 * Last entry must be all 0s
96 *
97 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
98 * Class, Class Mask, private data (not used) }
99 */
9baa3c34 100static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
9a799d71
AK		 134 /* required last entry */
135 {0, }
136};
137MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
5dd2d332 139#ifdef CONFIG_IXGBE_DCA
bd0362dd 140static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 141 void *p);
bd0362dd
JC		 142static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146};
147#endif
148
1cdd1ec8
GR		 149#ifdef CONFIG_PCI_IOV
150static unsigned int max_vfs;
151module_param(max_vfs, uint, 0);
e8e9f696 152MODULE_PARM_DESC(max_vfs,
170e8543 153 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 154#endif /* CONFIG_PCI_IOV */
155
8ef78adc
PWJ		 156static unsigned int allow_unsupported_sfp;
157module_param(allow_unsupported_sfp, uint, 0);
158MODULE_PARM_DESC(allow_unsupported_sfp,
159 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
160
b3f4d599 161#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
162static int debug = -1;
163module_param(debug, int, 0);
164MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
165
9a799d71
AK		 166MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
167MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
168MODULE_LICENSE("GPL");
169MODULE_VERSION(DRV_VERSION);
170
14438464
MR		 171static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
172
b8e82001
JK		 173static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
174 u32 reg, u16 *value)
175{
b8e82001
JK		 176 struct pci_dev *parent_dev;
177 struct pci_bus *parent_bus;
178
179 parent_bus = adapter->pdev->bus->parent;
180 if (!parent_bus)
181 return -1;
182
183 parent_dev = parent_bus->self;
184 if (!parent_dev)
185 return -1;
186
c0798edf 187 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 188 return -1;
189
c0798edf 190 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 191 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
192 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
193 return -1;
b8e82001
JK		 194 return 0;
195}
196
197static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
198{
199 struct ixgbe_hw *hw = &adapter->hw;
200 u16 link_status = 0;
201 int err;
202
203 hw->bus.type = ixgbe_bus_type_pci_express;
204
205 /* Get the negotiated link width and speed from PCI config space of the
206 * parent, as this device is behind a switch
207 */
208 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
209
210 /* assume caller will handle error case */
211 if (err)
212 return err;
213
214 hw->bus.width = ixgbe_convert_bus_width(link_status);
215 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
216
217 return 0;
218}
219
e027d1ae
JK		 220/**
221 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
222 * @hw: hw specific details
223 *
224 * This function is used by probe to determine whether a device's PCI-Express
225 * bandwidth details should be gathered from the parent bus instead of from the
226 * device. Used to ensure that various locations all have the correct device ID
227 * checks.
228 */
229static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
230{
231 switch (hw->device_id) {
232 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 233 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 234 return true;
235 default:
236 return false;
237 }
238}
239
240static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
241 int expected_gts)
242{
243 int max_gts = 0;
244 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
245 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
246 struct pci_dev *pdev;
247
248 /* determine whether to use the the parent device
249 */
250 if (ixgbe_pcie_from_parent(&adapter->hw))
251 pdev = adapter->pdev->bus->parent->self;
252 else
253 pdev = adapter->pdev;
254
255 if (pcie_get_minimum_link(pdev, &speed, &width) ||
256 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
257 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
258 return;
259 }
260
261 switch (speed) {
262 case PCIE_SPEED_2_5GT:
263 /* 8b/10b encoding reduces max throughput by 20% */
264 max_gts = 2 * width;
265 break;
266 case PCIE_SPEED_5_0GT:
267 /* 8b/10b encoding reduces max throughput by 20% */
268 max_gts = 4 * width;
269 break;
270 case PCIE_SPEED_8_0GT:
9f0a433c 271 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 272 max_gts = 8 * width;
273 break;
274 default:
275 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
276 return;
277 }
278
279 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
280 max_gts);
281 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
282 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
283 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
284 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
285 "Unknown"),
286 width,
287 (speed == PCIE_SPEED_2_5GT ? "20%" :
288 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 289 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 290 "Unknown"));
291
292 if (max_gts < expected_gts) {
293 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
294 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
295 expected_gts);
296 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
297 }
298}
299
7086400d
AD		 300static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
301{
302 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 303 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 304 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
305 schedule_work(&adapter->service_task);
306}
307
2a1a091c
MR		 308static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
309{
310 struct ixgbe_adapter *adapter = hw->back;
311
312 if (!hw->hw_addr)
313 return;
314 hw->hw_addr = NULL;
315 e_dev_err("Adapter removed\n");
58cf663f
MR		 316 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
317 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 318}
319
f8e2472f 320static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 321{
322 u32 value;
323
324 /* The following check not only optimizes a bit by not
325 * performing a read on the status register when the
326 * register just read was a status register read that
327 * returned IXGBE_FAILED_READ_REG. It also blocks any
328 * potential recursion.
329 */
330 if (reg == IXGBE_STATUS) {
331 ixgbe_remove_adapter(hw);
332 return;
333 }
334 value = ixgbe_read_reg(hw, IXGBE_STATUS);
335 if (value == IXGBE_FAILED_READ_REG)
336 ixgbe_remove_adapter(hw);
337}
338
f8e2472f
MR		 339/**
340 * ixgbe_read_reg - Read from device register
341 * @hw: hw specific details
342 * @reg: offset of register to read
343 *
344 * Returns : value read or IXGBE_FAILED_READ_REG if removed
345 *
346 * This function is used to read device registers. It checks for device
347 * removal by confirming any read that returns all ones by checking the
348 * status register value for all ones. This function avoids reading from
349 * the hardware if a removal was previously detected in which case it
350 * returns IXGBE_FAILED_READ_REG (all ones).
351 */
352u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
353{
354 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
355 u32 value;
356
357 if (ixgbe_removed(reg_addr))
358 return IXGBE_FAILED_READ_REG;
359 value = readl(reg_addr + reg);
360 if (unlikely(value == IXGBE_FAILED_READ_REG))
361 ixgbe_check_remove(hw, reg);
362 return value;
363}
364
14438464
MR		 365static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
366{
367 u16 value;
368
369 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
370 if (value == IXGBE_FAILED_READ_CFG_WORD) {
371 ixgbe_remove_adapter(hw);
372 return true;
373 }
374 return false;
375}
376
377u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
378{
379 struct ixgbe_adapter *adapter = hw->back;
380 u16 value;
381
382 if (ixgbe_removed(hw->hw_addr))
383 return IXGBE_FAILED_READ_CFG_WORD;
384 pci_read_config_word(adapter->pdev, reg, &value);
385 if (value == IXGBE_FAILED_READ_CFG_WORD &&
386 ixgbe_check_cfg_remove(hw, adapter->pdev))
387 return IXGBE_FAILED_READ_CFG_WORD;
388 return value;
389}
390
391#ifdef CONFIG_PCI_IOV
392static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
393{
394 struct ixgbe_adapter *adapter = hw->back;
395 u32 value;
396
397 if (ixgbe_removed(hw->hw_addr))
398 return IXGBE_FAILED_READ_CFG_DWORD;
399 pci_read_config_dword(adapter->pdev, reg, &value);
400 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
401 ixgbe_check_cfg_remove(hw, adapter->pdev))
402 return IXGBE_FAILED_READ_CFG_DWORD;
403 return value;
404}
405#endif /* CONFIG_PCI_IOV */
406
ed19231c
JK		 407void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
408{
409 struct ixgbe_adapter *adapter = hw->back;
410
411 if (ixgbe_removed(hw->hw_addr))
412 return;
413 pci_write_config_word(adapter->pdev, reg, value);
414}
415
7086400d
AD		 416static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
417{
418 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
419
52f33af8 420 /* flush memory to make sure state is correct before next watchdog */
4e857c58 421 smp_mb__before_atomic();
7086400d
AD		 422 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
423}
424
dcd79aeb
TI		 425struct ixgbe_reg_info {
426 u32 ofs;
427 char *name;
428};
429
430static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
431
432 /* General Registers */
433 {IXGBE_CTRL, "CTRL"},
434 {IXGBE_STATUS, "STATUS"},
435 {IXGBE_CTRL_EXT, "CTRL_EXT"},
436
437 /* Interrupt Registers */
438 {IXGBE_EICR, "EICR"},
439
440 /* RX Registers */
441 {IXGBE_SRRCTL(0), "SRRCTL"},
442 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
443 {IXGBE_RDLEN(0), "RDLEN"},
444 {IXGBE_RDH(0), "RDH"},
445 {IXGBE_RDT(0), "RDT"},
446 {IXGBE_RXDCTL(0), "RXDCTL"},
447 {IXGBE_RDBAL(0), "RDBAL"},
448 {IXGBE_RDBAH(0), "RDBAH"},
449
450 /* TX Registers */
451 {IXGBE_TDBAL(0), "TDBAL"},
452 {IXGBE_TDBAH(0), "TDBAH"},
453 {IXGBE_TDLEN(0), "TDLEN"},
454 {IXGBE_TDH(0), "TDH"},
455 {IXGBE_TDT(0), "TDT"},
456 {IXGBE_TXDCTL(0), "TXDCTL"},
457
458 /* List Terminator */
ca8dfe25 459 { .name = NULL }
dcd79aeb
TI		 460};
461
462
463/*
464 * ixgbe_regdump - register printout routine
465 */
466static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
467{
468 int i = 0, j = 0;
469 char rname[16];
470 u32 regs[64];
471
472 switch (reginfo->ofs) {
473 case IXGBE_SRRCTL(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
476 break;
477 case IXGBE_DCA_RXCTRL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
480 break;
481 case IXGBE_RDLEN(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
484 break;
485 case IXGBE_RDH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
488 break;
489 case IXGBE_RDT(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
492 break;
493 case IXGBE_RXDCTL(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
496 break;
497 case IXGBE_RDBAL(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
500 break;
501 case IXGBE_RDBAH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
504 break;
505 case IXGBE_TDBAL(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
508 break;
509 case IXGBE_TDBAH(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
512 break;
513 case IXGBE_TDLEN(0):
514 for (i = 0; i < 64; i++)
515 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
516 break;
517 case IXGBE_TDH(0):
518 for (i = 0; i < 64; i++)
519 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
520 break;
521 case IXGBE_TDT(0):
522 for (i = 0; i < 64; i++)
523 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
524 break;
525 case IXGBE_TXDCTL(0):
526 for (i = 0; i < 64; i++)
527 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
528 break;
529 default:
c7689578 530 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 531 IXGBE_READ_REG(hw, reginfo->ofs));
532 return;
533 }
534
535 for (i = 0; i < 8; i++) {
536 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 537 pr_err("%-15s", rname);
dcd79aeb 538 for (j = 0; j < 8; j++)
c7689578
JP		 539 pr_cont(" %08x", regs[i*8+j]);
540 pr_cont("\n");
dcd79aeb
TI		 541 }
542
543}
544
545/*
546 * ixgbe_dump - Print registers, tx-rings and rx-rings
547 */
548static void ixgbe_dump(struct ixgbe_adapter *adapter)
549{
550 struct net_device *netdev = adapter->netdev;
551 struct ixgbe_hw *hw = &adapter->hw;
552 struct ixgbe_reg_info *reginfo;
553 int n = 0;
554 struct ixgbe_ring *tx_ring;
729739b7 555 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 556 union ixgbe_adv_tx_desc *tx_desc;
557 struct my_u0 { u64 a; u64 b; } *u0;
558 struct ixgbe_ring *rx_ring;
559 union ixgbe_adv_rx_desc *rx_desc;
560 struct ixgbe_rx_buffer *rx_buffer_info;
561 u32 staterr;
562 int i = 0;
563
564 if (!netif_msg_hw(adapter))
565 return;
566
567 /* Print netdevice Info */
568 if (netdev) {
569 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 570 pr_info("Device Name state "
dcd79aeb 571 "trans_start last_rx\n");
c7689578
JP		 572 pr_info("%-15s %016lX %016lX %016lX\n",
573 netdev->name,
574 netdev->state,
575 netdev->trans_start,
576 netdev->last_rx);
dcd79aeb
TI		 577 }
578
579 /* Print Registers */
580 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 581 pr_info(" Register Name Value\n");
dcd79aeb
TI		 582 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
583 reginfo->name; reginfo++) {
584 ixgbe_regdump(hw, reginfo);
585 }
586
587 /* Print TX Ring Summary */
588 if (!netdev || !netif_running(netdev))
e90dd264 589 return;
dcd79aeb
TI		 590
591 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 592 pr_info(" %s %s %s %s\n",
593 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
594 "leng", "ntw", "timestamp");
dcd79aeb
TI		 595 for (n = 0; n < adapter->num_tx_queues; n++) {
596 tx_ring = adapter->tx_ring[n];
729739b7 597 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 598 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 599 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 600 (u64)dma_unmap_addr(tx_buffer, dma),
601 dma_unmap_len(tx_buffer, len),
602 tx_buffer->next_to_watch,
603 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 604 }
605
606 /* Print TX Rings */
607 if (!netif_msg_tx_done(adapter))
608 goto rx_ring_summary;
609
610 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
611
612 /* Transmit Descriptor Formats
613 *
39ac868a 614 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
39ac868a 618 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 621 *
622 * 82598 Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | NXTSEQ |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
629 *
630 * 82599+ Advanced Transmit Descriptor
631 * +--------------------------------------------------------------+
632 * 0 | Buffer Address [63:0] |
633 * +--------------------------------------------------------------+
634 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
635 * +--------------------------------------------------------------+
636 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
637 *
638 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
639 * +--------------------------------------------------------------+
640 * 0 | RSV [63:0] |
641 * +--------------------------------------------------------------+
642 * 8 | RSV | STA | RSV |
643 * +--------------------------------------------------------------+
644 * 63 36 35 32 31 0
dcd79aeb
TI		 645 */
646
647 for (n = 0; n < adapter->num_tx_queues; n++) {
648 tx_ring = adapter->tx_ring[n];
c7689578
JP		 649 pr_info("------------------------------------\n");
650 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
651 pr_info("------------------------------------\n");
8ad88e37
JH		 652 pr_info("%s%s %s %s %s %s\n",
653 "T [desc] [address 63:0 ] ",
654 "[PlPOIdStDDt Ln] [bi->dma ] ",
655 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 656
657 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 658 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 659 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 660 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 661 if (dma_unmap_len(tx_buffer, len) > 0) {
662 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
663 i,
664 le64_to_cpu(u0->a),
665 le64_to_cpu(u0->b),
666 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 667 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 668 tx_buffer->next_to_watch,
669 (u64)tx_buffer->time_stamp,
670 tx_buffer->skb);
671 if (i == tx_ring->next_to_use &&
672 i == tx_ring->next_to_clean)
673 pr_cont(" NTC/U\n");
674 else if (i == tx_ring->next_to_use)
675 pr_cont(" NTU\n");
676 else if (i == tx_ring->next_to_clean)
677 pr_cont(" NTC\n");
678 else
679 pr_cont("\n");
680
681 if (netif_msg_pktdata(adapter) &&
682 tx_buffer->skb)
683 print_hex_dump(KERN_INFO, "",
684 DUMP_PREFIX_ADDRESS, 16, 1,
685 tx_buffer->skb->data,
686 dma_unmap_len(tx_buffer, len),
687 true);
688 }
dcd79aeb
TI		 689 }
690 }
691
692 /* Print RX Rings Summary */
693rx_ring_summary:
694 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 695 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 696 for (n = 0; n < adapter->num_rx_queues; n++) {
697 rx_ring = adapter->rx_ring[n];
c7689578
JP		 698 pr_info("%5d %5X %5X\n",
699 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 700 }
701
702 /* Print RX Rings */
703 if (!netif_msg_rx_status(adapter))
e90dd264 704 return;
dcd79aeb
TI		 705
706 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
707
39ac868a
JH		 708 /* Receive Descriptor Formats
709 *
710 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 711 * 63 1 0
712 * +-----------------------------------------------------+
713 * 0 | Packet Buffer Address [63:1] |A0/NSE|
714 * +----------------------------------------------+------+
715 * 8 | Header Buffer Address [63:1] | DD |
716 * +-----------------------------------------------------+
717 *
718 *
39ac868a 719 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 720 *
721 * 63 48 47 32 31 30 21 20 16 15 4 3 0
722 * +------------------------------------------------------+
39ac868a
JH		 723 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
724 * | Packet | IP | | | | Type | Type |
725 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 726 * +------------------------------------------------------+
727 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
728 * +------------------------------------------------------+
729 * 63 48 47 32 31 20 19 0
39ac868a
JH		 730 *
731 * 82599+ Advanced Receive Descriptor (Read) Format
732 * 63 1 0
733 * +-----------------------------------------------------+
734 * 0 | Packet Buffer Address [63:1] |A0/NSE|
735 * +----------------------------------------------+------+
736 * 8 | Header Buffer Address [63:1] | DD |
737 * +-----------------------------------------------------+
738 *
739 *
740 * 82599+ Advanced Receive Descriptor (Write-Back) Format
741 *
742 * 63 48 47 32 31 30 21 20 17 16 4 3 0
743 * +------------------------------------------------------+
744 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
745 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
746 * |/ Flow Dir Flt ID | | | | | |
747 * +------------------------------------------------------+
748 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
749 * +------------------------------------------------------+
750 * 63 48 47 32 31 20 19 0
dcd79aeb 751 */
39ac868a 752
dcd79aeb
TI		 753 for (n = 0; n < adapter->num_rx_queues; n++) {
754 rx_ring = adapter->rx_ring[n];
c7689578
JP		 755 pr_info("------------------------------------\n");
756 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
757 pr_info("------------------------------------\n");
8ad88e37
JH		 758 pr_info("%s%s%s",
759 "R [desc] [ PktBuf A0] ",
760 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 761 "<-- Adv Rx Read format\n");
8ad88e37
JH		 762 pr_info("%s%s%s",
763 "RWB[desc] [PcsmIpSHl PtRs] ",
764 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 765 "<-- Adv Rx Write-Back format\n");
766
767 for (i = 0; i < rx_ring->count; i++) {
768 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 769 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 770 u0 = (struct my_u0 *)rx_desc;
771 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
772 if (staterr & IXGBE_RXD_STAT_DD) {
773 /* Descriptor Done */
c7689578 774 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 775 "%016llX ---------------- %p", i,
776 le64_to_cpu(u0->a),
777 le64_to_cpu(u0->b),
778 rx_buffer_info->skb);
779 } else {
c7689578 780 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 781 "%016llX %016llX %p", i,
782 le64_to_cpu(u0->a),
783 le64_to_cpu(u0->b),
784 (u64)rx_buffer_info->dma,
785 rx_buffer_info->skb);
786
9c50c035
ET		 787 if (netif_msg_pktdata(adapter) &&
788 rx_buffer_info->dma) {
dcd79aeb
TI		 789 print_hex_dump(KERN_INFO, "",
790 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 791 page_address(rx_buffer_info->page) +
792 rx_buffer_info->page_offset,
f800326d 793 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 794 }
795 }
796
797 if (i == rx_ring->next_to_use)
c7689578 798 pr_cont(" NTU\n");
dcd79aeb 799 else if (i == rx_ring->next_to_clean)
c7689578 800 pr_cont(" NTC\n");
dcd79aeb 801 else
c7689578 802 pr_cont("\n");
dcd79aeb
TI		 803
804 }
805 }
dcd79aeb
TI		 806}
807
5eba3699
AV		 808static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
809{
810 u32 ctrl_ext;
811
812 /* Let firmware take over control of h/w */
813 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
814 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 815 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 816}
817
818static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
819{
820 u32 ctrl_ext;
821
822 /* Let firmware know the driver has taken over */
823 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 825 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 826}
9a799d71 827
49ce9c2c 828/**
e8e26350
PW		 829 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
830 * @adapter: pointer to adapter struct
831 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
832 * @queue: queue to map the corresponding interrupt to
833 * @msix_vector: the vector to map to the corresponding queue
834 *
835 */
836static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 837 u8 queue, u8 msix_vector)
9a799d71
AK		 838{
839 u32 ivar, index;
e8e26350
PW		 840 struct ixgbe_hw *hw = &adapter->hw;
841 switch (hw->mac.type) {
842 case ixgbe_mac_82598EB:
843 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
844 if (direction == -1)
845 direction = 0;
846 index = (((direction * 64) + queue) >> 2) & 0x1F;
847 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
848 ivar &= ~(0xFF << (8 * (queue & 0x3)));
849 ivar |= (msix_vector << (8 * (queue & 0x3)));
850 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
851 break;
852 case ixgbe_mac_82599EB:
b93a2226 853 case ixgbe_mac_X540:
9a75a1ac
DS		 854 case ixgbe_mac_X550:
855 case ixgbe_mac_X550EM_x:
e8e26350
PW		 856 if (direction == -1) {
857 /* other causes */
858 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
859 index = ((queue & 1) * 8);
860 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
861 ivar &= ~(0xFF << index);
862 ivar |= (msix_vector << index);
863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
864 break;
865 } else {
866 /* tx or rx causes */
867 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
868 index = ((16 * (queue & 1)) + (8 * direction));
869 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
870 ivar &= ~(0xFF << index);
871 ivar |= (msix_vector << index);
872 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
873 break;
874 }
875 default:
876 break;
877 }
9a799d71
AK		 878}
879
fe49f04a 880static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 881 u64 qmask)
fe49f04a
AD		 882{
883 u32 mask;
884
bd508178
AD		 885 switch (adapter->hw.mac.type) {
886 case ixgbe_mac_82598EB:
fe49f04a
AD		 887 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 889 break;
890 case ixgbe_mac_82599EB:
b93a2226 891 case ixgbe_mac_X540:
9a75a1ac
DS		 892 case ixgbe_mac_X550:
893 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 894 mask = (qmask & 0xFFFFFFFF);
895 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
896 mask = (qmask >> 32);
897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 898 break;
899 default:
900 break;
fe49f04a
AD		 901 }
902}
903
729739b7
AD		 904void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
905 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 906{
729739b7
AD		 907 if (tx_buffer->skb) {
908 dev_kfree_skb_any(tx_buffer->skb);
909 if (dma_unmap_len(tx_buffer, len))
d3d00239 910 dma_unmap_single(ring->dev,
729739b7
AD		 911 dma_unmap_addr(tx_buffer, dma),
912 dma_unmap_len(tx_buffer, len),
913 DMA_TO_DEVICE);
914 } else if (dma_unmap_len(tx_buffer, len)) {
915 dma_unmap_page(ring->dev,
916 dma_unmap_addr(tx_buffer, dma),
917 dma_unmap_len(tx_buffer, len),
918 DMA_TO_DEVICE);
e5a43549 919 }
729739b7
AD		 920 tx_buffer->next_to_watch = NULL;
921 tx_buffer->skb = NULL;
922 dma_unmap_len_set(tx_buffer, len, 0);
923 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 924}
925
943561d3 926static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 927{
928 struct ixgbe_hw *hw = &adapter->hw;
929 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 930 int i;
943561d3 931 u32 data;
c84d324c 932
943561d3
AD		 933 if ((hw->fc.current_mode != ixgbe_fc_full) &&
934 (hw->fc.current_mode != ixgbe_fc_rx_pause))
935 return;
c84d324c 936
943561d3
AD		 937 switch (hw->mac.type) {
938 case ixgbe_mac_82598EB:
939 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
940 break;
941 default:
942 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
943 }
944 hwstats->lxoffrxc += data;
c84d324c 945
943561d3
AD		 946 /* refill credits (no tx hang) if we received xoff */
947 if (!data)
c84d324c 948 return;
943561d3
AD		 949
950 for (i = 0; i < adapter->num_tx_queues; i++)
951 clear_bit(__IXGBE_HANG_CHECK_ARMED,
952 &adapter->tx_ring[i]->state);
953}
954
955static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
956{
957 struct ixgbe_hw *hw = &adapter->hw;
958 struct ixgbe_hw_stats *hwstats = &adapter->stats;
959 u32 xoff[8] = {0};
2afaa00d 960 u8 tc;
943561d3
AD		 961 int i;
962 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
963
964 if (adapter->ixgbe_ieee_pfc)
965 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
966
967 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
968 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 969 return;
943561d3 970 }
c84d324c
JF		 971
972 /* update stats for each tc, only valid with PFC enabled */
973 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 974 u32 pxoffrxc;
975
c84d324c
JF		 976 switch (hw->mac.type) {
977 case ixgbe_mac_82598EB:
2afaa00d 978 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 979 break;
c84d324c 980 default:
2afaa00d 981 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 982 }
2afaa00d
PN		 983 hwstats->pxoffrxc[i] += pxoffrxc;
984 /* Get the TC for given UP */
985 tc = netdev_get_prio_tc_map(adapter->netdev, i);
986 xoff[tc] += pxoffrxc;
c84d324c
JF		 987 }
988
989 /* disarm tx queues that have received xoff frames */
990 for (i = 0; i < adapter->num_tx_queues; i++) {
991 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 992
2afaa00d 993 tc = tx_ring->dcb_tc;
c84d324c
JF		 994 if (xoff[tc])
995 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 996 }
26f23d82
YZ		 997}
998
c84d324c 999static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1000{
7d7ce682 1001 return ring->stats.packets;
c84d324c
JF		 1002}
1003
1004static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1005{
2a47fa45
JF		 1006 struct ixgbe_adapter *adapter;
1007 struct ixgbe_hw *hw;
1008 u32 head, tail;
1009
1010 if (ring->l2_accel_priv)
1011 adapter = ring->l2_accel_priv->real_adapter;
1012 else
1013 adapter = netdev_priv(ring->netdev);
e01c31a5 1014
2a47fa45
JF		 1015 hw = &adapter->hw;
1016 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1017 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1018
1019 if (head != tail)
1020 return (head < tail) ?
1021 tail - head : (tail + ring->count - head);
1022
1023 return 0;
1024}
1025
1026static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1027{
1028 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1029 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1030 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1031
7d637bcc 1032 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1033
1034 /*
1035 * Check for a hung queue, but be thorough. This verifies
1036 * that a transmit has been completed since the previous
1037 * check AND there is at least one packet pending. The
1038 * ARMED bit is set to indicate a potential hang. The
1039 * bit is cleared if a pause frame is received to remove
1040 * false hang detection due to PFC or 802.3x frames. By
1041 * requiring this to fail twice we avoid races with
1042 * pfc clearing the ARMED bit and conditions where we
1043 * run the check_tx_hang logic with a transmit completion
1044 * pending but without time to complete it yet.
1045 */
e90dd264 1046 if (tx_done_old == tx_done && tx_pending)
c84d324c 1047 /* make sure it is true for two checks in a row */
e90dd264
MR		 1048 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1049 &tx_ring->state);
1050 /* update completed stats and continue */
1051 tx_ring->tx_stats.tx_done_old = tx_done;
1052 /* reset the countdown */
1053 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1054
e90dd264 1055 return false;
9a799d71
AK		 1056}
1057
c83c6cbd
AD		 1058/**
1059 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1060 * @adapter: driver private struct
1061 **/
1062static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1063{
1064
1065 /* Do the reset outside of interrupt context */
1066 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1067 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1068 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1069 ixgbe_service_event_schedule(adapter);
1070 }
1071}
e01c31a5 1072
9a799d71
AK		 1073/**
1074 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1075 * @q_vector: structure containing interrupt and ring information
e01c31a5 1076 * @tx_ring: tx ring to clean
9a799d71 1077 **/
fe49f04a 1078static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1079 struct ixgbe_ring *tx_ring)
9a799d71 1080{
fe49f04a 1081 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1082 struct ixgbe_tx_buffer *tx_buffer;
1083 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1084 unsigned int total_bytes = 0, total_packets = 0;
59224555 1085 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1086 unsigned int i = tx_ring->next_to_clean;
1087
1088 if (test_bit(__IXGBE_DOWN, &adapter->state))
1089 return true;
9a799d71 1090
d3d00239 1091 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1092 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1093 i -= tx_ring->count;
12207e49 1094
729739b7 1095 do {
d3d00239
AD		 1096 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1097
1098 /* if next_to_watch is not set then there is no work pending */
1099 if (!eop_desc)
1100 break;
1101
7f83a9e6 1102 /* prevent any other reads prior to eop_desc */
7e63bf49 1103 read_barrier_depends();
7f83a9e6 1104
d3d00239
AD		 1105 /* if DD is not set pending work has not been completed */
1106 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1107 break;
8ad494b0 1108
d3d00239
AD		 1109 /* clear next_to_watch to prevent false hangs */
1110 tx_buffer->next_to_watch = NULL;
8ad494b0 1111
091a6246
AD		 1112 /* update the statistics for this packet */
1113 total_bytes += tx_buffer->bytecount;
1114 total_packets += tx_buffer->gso_segs;
1115
fd0db0ed 1116 /* free the skb */
fe1f2a97 1117 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1118
729739b7
AD		 1119 /* unmap skb header data */
1120 dma_unmap_single(tx_ring->dev,
1121 dma_unmap_addr(tx_buffer, dma),
1122 dma_unmap_len(tx_buffer, len),
1123 DMA_TO_DEVICE);
1124
fd0db0ed
AD		 1125 /* clear tx_buffer data */
1126 tx_buffer->skb = NULL;
729739b7 1127 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1128
729739b7
AD		 1129 /* unmap remaining buffers */
1130 while (tx_desc != eop_desc) {
d3d00239
AD		 1131 tx_buffer++;
1132 tx_desc++;
8ad494b0 1133 i++;
729739b7
AD		 1134 if (unlikely(!i)) {
1135 i -= tx_ring->count;
d3d00239 1136 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1138 }
e01c31a5 1139
729739b7
AD		 1140 /* unmap any remaining paged data */
1141 if (dma_unmap_len(tx_buffer, len)) {
1142 dma_unmap_page(tx_ring->dev,
1143 dma_unmap_addr(tx_buffer, dma),
1144 dma_unmap_len(tx_buffer, len),
1145 DMA_TO_DEVICE);
1146 dma_unmap_len_set(tx_buffer, len, 0);
1147 }
1148 }
1149
1150 /* move us one more past the eop_desc for start of next pkt */
1151 tx_buffer++;
1152 tx_desc++;
1153 i++;
1154 if (unlikely(!i)) {
1155 i -= tx_ring->count;
1156 tx_buffer = tx_ring->tx_buffer_info;
1157 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1158 }
1159
1160 /* issue prefetch for next Tx descriptor */
1161 prefetch(tx_desc);
12207e49 1162
729739b7
AD		 1163 /* update budget accounting */
1164 budget--;
1165 } while (likely(budget));
1166
1167 i += tx_ring->count;
9a799d71 1168 tx_ring->next_to_clean = i;
d3d00239 1169 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1170 tx_ring->stats.bytes += total_bytes;
bd198058 1171 tx_ring->stats.packets += total_packets;
d3d00239 1172 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1173 q_vector->tx.total_bytes += total_bytes;
1174 q_vector->tx.total_packets += total_packets;
b953799e 1175
c84d324c
JF		 1176 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1177 /* schedule immediate reset if we believe we hung */
1178 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1179 e_err(drv, "Detected Tx Unit Hang\n"
1180 " Tx Queue <%d>\n"
1181 " TDH, TDT <%x>, <%x>\n"
1182 " next_to_use <%x>\n"
1183 " next_to_clean <%x>\n"
1184 "tx_buffer_info[next_to_clean]\n"
1185 " time_stamp <%lx>\n"
1186 " jiffies <%lx>\n",
1187 tx_ring->queue_index,
1188 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1189 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1190 tx_ring->next_to_use, i,
1191 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1192
1193 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1194
1195 e_info(probe,
1196 "tx hang %d detected on queue %d, resetting adapter\n",
1197 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1198
b953799e 1199 /* schedule immediate reset if we believe we hung */
c83c6cbd 1200 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1201
1202 /* the adapter is about to reset, no point in enabling stuff */
59224555 1203 return true;
b953799e 1204 }
9a799d71 1205
b2d96e0a
AD		 1206 netdev_tx_completed_queue(txring_txq(tx_ring),
1207 total_packets, total_bytes);
1208
e092be60 1209#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1210 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1211 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1212 /* Make sure that anybody stopping the queue after this
1213 * sees the new next_to_clean.
1214 */
1215 smp_mb();
729739b7
AD		 1216 if (__netif_subqueue_stopped(tx_ring->netdev,
1217 tx_ring->queue_index)
1218 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1219 netif_wake_subqueue(tx_ring->netdev,
1220 tx_ring->queue_index);
5b7da515 1221 ++tx_ring->tx_stats.restart_queue;
30eba97a 1222 }
e092be60 1223 }
9a799d71 1224
59224555 1225 return !!budget;
9a799d71
AK		 1226}
1227
5dd2d332 1228#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1229static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1230 struct ixgbe_ring *tx_ring,
33cf09c9 1231 int cpu)
bd0362dd 1232{
33cf09c9 1233 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1234 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1235 u16 reg_offset;
33cf09c9 1236
33cf09c9
AD		 1237 switch (hw->mac.type) {
1238 case ixgbe_mac_82598EB:
bdda1a61 1239 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1240 break;
1241 case ixgbe_mac_82599EB:
b93a2226 1242 case ixgbe_mac_X540:
bdda1a61
AD		 1243 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1244 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1245 break;
1246 default:
bdda1a61
AD		 1247 /* for unknown hardware do not write register */
1248 return;
bd0362dd 1249 }
bdda1a61
AD		 1250
1251 /*
1252 * We can enable relaxed ordering for reads, but not writes when
1253 * DCA is enabled. This is due to a known issue in some chipsets
1254 * which will cause the DCA tag to be cleared.
1255 */
1256 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1257 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1258 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1259
1260 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1261}
1262
bdda1a61
AD		 1263static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1264 struct ixgbe_ring *rx_ring,
33cf09c9 1265 int cpu)
bd0362dd 1266{
33cf09c9 1267 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1268 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1269 u8 reg_idx = rx_ring->reg_idx;
1270
33cf09c9
AD		 1271
1272 switch (hw->mac.type) {
33cf09c9 1273 case ixgbe_mac_82599EB:
b93a2226 1274 case ixgbe_mac_X540:
bdda1a61 1275 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1276 break;
1277 default:
1278 break;
1279 }
bdda1a61
AD		 1280
1281 /*
1282 * We can enable relaxed ordering for reads, but not writes when
1283 * DCA is enabled. This is due to a known issue in some chipsets
1284 * which will cause the DCA tag to be cleared.
1285 */
1286 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1287 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1288
1289 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1290}
1291
1292static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1293{
1294 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1295 struct ixgbe_ring *ring;
bd0362dd 1296 int cpu = get_cpu();
bd0362dd 1297
33cf09c9
AD		 1298 if (q_vector->cpu == cpu)
1299 goto out_no_update;
1300
a557928e 1301 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1302 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1303
a557928e 1304 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1305 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1306
1307 q_vector->cpu = cpu;
1308out_no_update:
bd0362dd
JC		 1309 put_cpu();
1310}
1311
1312static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1313{
1314 int i;
1315
1316 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1317 return;
1318
e35ec126
AD		 1319 /* always use CB2 mode, difference is masked in the CB driver */
1320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1321
49c7ffbe 1322 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1323 adapter->q_vector[i]->cpu = -1;
1324 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1325 }
1326}
1327
1328static int __ixgbe_notify_dca(struct device *dev, void *data)
1329{
c60fbb00 1330 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1331 unsigned long event = *(unsigned long *)data;
1332
2a72c31e 1333 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1334 return 0;
1335
bd0362dd
JC		 1336 switch (event) {
1337 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1338 /* if we're already enabled, don't do it again */
1339 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1340 break;
652f093f 1341 if (dca_add_requester(dev) == 0) {
96b0e0f6 1342 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1343 ixgbe_setup_dca(adapter);
1344 break;
1345 }
1346 /* Fall Through since DCA is disabled. */
1347 case DCA_PROVIDER_REMOVE:
1348 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1349 dca_remove_requester(dev);
1350 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1352 }
1353 break;
1354 }
1355
652f093f 1356 return 0;
bd0362dd 1357}
67a74ee2 1358
bdda1a61 1359#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1360static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1361 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1362 struct sk_buff *skb)
1363{
8a0da21b 1364 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1365 skb_set_hash(skb,
1366 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1367 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1368}
1369
f800326d 1370#ifdef IXGBE_FCOE
ff886dfc
AD		 1371/**
1372 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1373 * @ring: structure containing ring specific data
ff886dfc
AD		 1374 * @rx_desc: advanced rx descriptor
1375 *
1376 * Returns : true if it is FCoE pkt
1377 */
57efd44c 1378static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1379 union ixgbe_adv_rx_desc *rx_desc)
1380{
1381 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1382
57efd44c 1383 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1384 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1385 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1386 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1387}
1388
f800326d 1389#endif /* IXGBE_FCOE */
e59bd25d
AV		 1390/**
1391 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1392 * @ring: structure containing ring specific data
1393 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1394 * @skb: skb currently being received and modified
1395 **/
8a0da21b 1396static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1397 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1398 struct sk_buff *skb)
9a799d71 1399{
3f207800
DS		 1400 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1401 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1402 bool encap_pkt = false;
1403
8a0da21b 1404 skb_checksum_none_assert(skb);
9a799d71 1405
712744be 1406 /* Rx csum disabled */
8a0da21b 1407 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1408 return;
e59bd25d 1409
3f207800
DS		 1410 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1411 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1412 encap_pkt = true;
1413 skb->encapsulation = 1;
1414 skb->ip_summed = CHECKSUM_NONE;
1415 }
1416
e59bd25d 1417 /* if IP and error */
f56e0cb1
AD		 1418 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1419 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1420 ring->rx_stats.csum_err++;
9a799d71
AK		 1421 return;
1422 }
e59bd25d 1423
f56e0cb1 1424 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1425 return;
1426
f56e0cb1 1427 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1428 /*
1429 * 82599 errata, UDP frames with a 0 checksum can be marked as
1430 * checksum errors.
1431 */
8a0da21b
AD		 1432 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1433 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1434 return;
1435
8a0da21b 1436 ring->rx_stats.csum_err++;
e59bd25d
AV		 1437 return;
1438 }
1439
9a799d71 1440 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1441 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1442 if (encap_pkt) {
1443 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1444 return;
1445
1446 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1447 ring->rx_stats.csum_err++;
1448 return;
1449 }
1450 /* If we checked the outer header let the stack know */
1451 skb->csum_level = 1;
1452 }
9a799d71
AK		 1453}
1454
f990b79b
AD		 1455static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1456 struct ixgbe_rx_buffer *bi)
1457{
1458 struct page *page = bi->page;
18cb652a 1459 dma_addr_t dma;
f990b79b 1460
f800326d 1461 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1462 if (likely(page))
f990b79b
AD		 1463 return true;
1464
f800326d 1465 /* alloc new page for storage */
18cb652a
AD		 1466 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1467 if (unlikely(!page)) {
1468 rx_ring->rx_stats.alloc_rx_page_failed++;
1469 return false;
f990b79b
AD		 1470 }
1471
f800326d
AD		 1472 /* map page for use */
1473 dma = dma_map_page(rx_ring->dev, page, 0,
1474 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1475
1476 /*
1477 * if mapping failed free memory back to system since
1478 * there isn't much point in holding memory we can't use
1479 */
1480 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1481 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1482
f990b79b
AD		 1483 rx_ring->rx_stats.alloc_rx_page_failed++;
1484 return false;
1485 }
1486
f800326d 1487 bi->dma = dma;
18cb652a 1488 bi->page = page;
afaa9459 1489 bi->page_offset = 0;
f800326d 1490
f990b79b
AD		 1491 return true;
1492}
1493
9a799d71 1494/**
f990b79b 1495 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1496 * @rx_ring: ring to place buffers on
1497 * @cleaned_count: number of buffers to replace
9a799d71 1498 **/
fc77dc3c 1499void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1500{
9a799d71 1501 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1502 struct ixgbe_rx_buffer *bi;
d5f398ed 1503 u16 i = rx_ring->next_to_use;
9a799d71 1504
f800326d
AD		 1505 /* nothing to do */
1506 if (!cleaned_count)
fc77dc3c
AD		 1507 return;
1508
e4f74028 1509 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1510 bi = &rx_ring->rx_buffer_info[i];
1511 i -= rx_ring->count;
9a799d71 1512
f800326d
AD		 1513 do {
1514 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1515 break;
d5f398ed 1516
f800326d
AD		 1517 /*
1518 * Refresh the desc even if buffer_addrs didn't change
1519 * because each write-back erases this info.
1520 */
1521 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1522
f990b79b
AD		 1523 rx_desc++;
1524 bi++;
9a799d71 1525 i++;
f990b79b 1526 if (unlikely(!i)) {
e4f74028 1527 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1528 bi = rx_ring->rx_buffer_info;
1529 i -= rx_ring->count;
1530 }
1531
18cb652a
AD		 1532 /* clear the status bits for the next_to_use descriptor */
1533 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1534
1535 cleaned_count--;
1536 } while (cleaned_count);
7c6e0a43 1537
f990b79b
AD		 1538 i += rx_ring->count;
1539
ad435ec6
AD		 1540 if (rx_ring->next_to_use != i) {
1541 rx_ring->next_to_use = i;
1542
1543 /* update next to alloc since we have filled the ring */
1544 rx_ring->next_to_alloc = i;
1545
1546 /* Force memory writes to complete before letting h/w
1547 * know there are new descriptors to fetch. (Only
1548 * applicable for weak-ordered memory model archs,
1549 * such as IA-64).
1550 */
1551 wmb();
1552 writel(i, rx_ring->tail);
1553 }
9a799d71
AK		 1554}
1555
1d2024f6
AD		 1556static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1557 struct sk_buff *skb)
1558{
f800326d 1559 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1560
1561 /* set gso_size to avoid messing up TCP MSS */
1562 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1563 IXGBE_CB(skb)->append_cnt);
96be80ab 1564 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1565}
1566
1567static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1568 struct sk_buff *skb)
1569{
1570 /* if append_cnt is 0 then frame is not RSC */
1571 if (!IXGBE_CB(skb)->append_cnt)
1572 return;
1573
1574 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1575 rx_ring->rx_stats.rsc_flush++;
1576
1577 ixgbe_set_rsc_gso_size(rx_ring, skb);
1578
1579 /* gso_size is computed using append_cnt so always clear it last */
1580 IXGBE_CB(skb)->append_cnt = 0;
1581}
1582
8a0da21b
AD		 1583/**
1584 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1585 * @rx_ring: rx descriptor ring packet is being transacted on
1586 * @rx_desc: pointer to the EOP Rx descriptor
1587 * @skb: pointer to current skb being populated
f8212f97 1588 *
8a0da21b
AD		 1589 * This function checks the ring, descriptor, and packet information in
1590 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1591 * other fields within the skb.
f8212f97 1592 **/
8a0da21b
AD		 1593static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1594 union ixgbe_adv_rx_desc *rx_desc,
1595 struct sk_buff *skb)
f8212f97 1596{
43e95f11
JF		 1597 struct net_device *dev = rx_ring->netdev;
1598
8a0da21b
AD		 1599 ixgbe_update_rsc_stats(rx_ring, skb);
1600
1601 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1602
8a0da21b
AD		 1603 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1604
eda183c2
JK		 1605 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1606 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1607
f646968f 1608 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1609 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1610 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1611 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1612 }
1613
8a0da21b 1614 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1615
43e95f11 1616 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1617}
1618
8a0da21b
AD		 1619static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1620 struct sk_buff *skb)
aa80175a 1621{
8a0da21b
AD		 1622 struct ixgbe_adapter *adapter = q_vector->adapter;
1623
b4640030 1624 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1625 netif_receive_skb(skb);
1626 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1627 napi_gro_receive(&q_vector->napi, skb);
1628 else
1629 netif_rx(skb);
aa80175a 1630}
43634e82 1631
f800326d
AD		 1632/**
1633 * ixgbe_is_non_eop - process handling of non-EOP buffers
1634 * @rx_ring: Rx ring being processed
1635 * @rx_desc: Rx descriptor for current buffer
1636 * @skb: Current socket buffer containing buffer in progress
1637 *
1638 * This function updates next to clean. If the buffer is an EOP buffer
1639 * this function exits returning false, otherwise it will place the
1640 * sk_buff in the next buffer to be chained and return true indicating
1641 * that this is in fact a non-EOP buffer.
1642 **/
1643static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1644 union ixgbe_adv_rx_desc *rx_desc,
1645 struct sk_buff *skb)
1646{
1647 u32 ntc = rx_ring->next_to_clean + 1;
1648
1649 /* fetch, update, and store next to clean */
1650 ntc = (ntc < rx_ring->count) ? ntc : 0;
1651 rx_ring->next_to_clean = ntc;
1652
1653 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1654
5a02cbd1
AD		 1655 /* update RSC append count if present */
1656 if (ring_is_rsc_enabled(rx_ring)) {
1657 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1658 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1659
1660 if (unlikely(rsc_enabled)) {
1661 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1662
1663 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1664 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1665
5a02cbd1
AD		 1666 /* update ntc based on RSC value */
1667 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1668 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1669 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1670 }
f800326d
AD		 1671 }
1672
5a02cbd1
AD		 1673 /* if we are the last buffer then there is nothing else to do */
1674 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1675 return false;
1676
f800326d
AD		 1677 /* place skb in next buffer to be received */
1678 rx_ring->rx_buffer_info[ntc].skb = skb;
1679 rx_ring->rx_stats.non_eop_descs++;
1680
1681 return true;
1682}
1683
19861ce2
AD		 1684/**
1685 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1686 * @rx_ring: rx descriptor ring packet is being transacted on
1687 * @skb: pointer to current skb being adjusted
1688 *
1689 * This function is an ixgbe specific version of __pskb_pull_tail. The
1690 * main difference between this version and the original function is that
1691 * this function can make several assumptions about the state of things
1692 * that allow for significant optimizations versus the standard function.
1693 * As a result we can do things like drop a frag and maintain an accurate
1694 * truesize for the skb.
1695 */
1696static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1697 struct sk_buff *skb)
1698{
1699 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1700 unsigned char *va;
1701 unsigned int pull_len;
1702
1703 /*
1704 * it is valid to use page_address instead of kmap since we are
1705 * working with pages allocated out of the lomem pool per
1706 * alloc_page(GFP_ATOMIC)
1707 */
1708 va = skb_frag_address(frag);
1709
1710 /*
1711 * we need the header to contain the greater of either ETH_HLEN or
1712 * 60 bytes if the skb->len is less than 60 for skb_pad.
1713 */
8496e338 1714 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1715
1716 /* align pull length to size of long to optimize memcpy performance */
1717 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1718
1719 /* update all of the pointers */
1720 skb_frag_size_sub(frag, pull_len);
1721 frag->page_offset += pull_len;
1722 skb->data_len -= pull_len;
1723 skb->tail += pull_len;
19861ce2
AD		 1724}
1725
42073d91
AD		 1726/**
1727 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1728 * @rx_ring: rx descriptor ring packet is being transacted on
1729 * @skb: pointer to current skb being updated
1730 *
1731 * This function provides a basic DMA sync up for the first fragment of an
1732 * skb. The reason for doing this is that the first fragment cannot be
1733 * unmapped until we have reached the end of packet descriptor for a buffer
1734 * chain.
1735 */
1736static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1737 struct sk_buff *skb)
1738{
1739 /* if the page was released unmap it, else just sync our portion */
1740 if (unlikely(IXGBE_CB(skb)->page_released)) {
1741 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1742 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1743 IXGBE_CB(skb)->page_released = false;
1744 } else {
1745 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1746
1747 dma_sync_single_range_for_cpu(rx_ring->dev,
1748 IXGBE_CB(skb)->dma,
1749 frag->page_offset,
1750 ixgbe_rx_bufsz(rx_ring),
1751 DMA_FROM_DEVICE);
1752 }
1753 IXGBE_CB(skb)->dma = 0;
1754}
1755
f800326d
AD		 1756/**
1757 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1758 * @rx_ring: rx descriptor ring packet is being transacted on
1759 * @rx_desc: pointer to the EOP Rx descriptor
1760 * @skb: pointer to current skb being fixed
1761 *
1762 * Check for corrupted packet headers caused by senders on the local L2
1763 * embedded NIC switch not setting up their Tx Descriptors right. These
1764 * should be very rare.
1765 *
1766 * Also address the case where we are pulling data in on pages only
1767 * and as such no data is present in the skb header.
1768 *
1769 * In addition if skb is not at least 60 bytes we need to pad it so that
1770 * it is large enough to qualify as a valid Ethernet frame.
1771 *
1772 * Returns true if an error was encountered and skb was freed.
1773 **/
1774static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1775 union ixgbe_adv_rx_desc *rx_desc,
1776 struct sk_buff *skb)
1777{
f800326d 1778 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1779
1780 /* verify that the packet does not have any known errors */
1781 if (unlikely(ixgbe_test_staterr(rx_desc,
1782 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1783 !(netdev->features & NETIF_F_RXALL))) {
1784 dev_kfree_skb_any(skb);
1785 return true;
1786 }
1787
19861ce2 1788 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1789 if (skb_is_nonlinear(skb))
1790 ixgbe_pull_tail(rx_ring, skb);
f800326d 1791
57efd44c
AD		 1792#ifdef IXGBE_FCOE
1793 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1794 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1795 return false;
1796
1797#endif
a94d9e22
AD		 1798 /* if eth_skb_pad returns an error the skb was freed */
1799 if (eth_skb_pad(skb))
1800 return true;
f800326d
AD		 1801
1802 return false;
1803}
1804
f800326d
AD		 1805/**
1806 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1807 * @rx_ring: rx descriptor ring to store buffers on
1808 * @old_buff: donor buffer to have page reused
1809 *
0549ae20 1810 * Synchronizes page for reuse by the adapter
f800326d
AD		 1811 **/
1812static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1813 struct ixgbe_rx_buffer *old_buff)
1814{
1815 struct ixgbe_rx_buffer *new_buff;
1816 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1817
1818 new_buff = &rx_ring->rx_buffer_info[nta];
1819
1820 /* update, and store next to alloc */
1821 nta++;
1822 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1823
1824 /* transfer page from old buffer to new buffer */
18cb652a 1825 *new_buff = *old_buff;
f800326d
AD		 1826
1827 /* sync the buffer for use by the device */
1828 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1829 new_buff->page_offset,
1830 ixgbe_rx_bufsz(rx_ring),
f800326d 1831 DMA_FROM_DEVICE);
f800326d
AD		 1832}
1833
18cb652a
AD		 1834static inline bool ixgbe_page_is_reserved(struct page *page)
1835{
1836 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
1837}
1838
f800326d
AD		 1839/**
1840 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1841 * @rx_ring: rx descriptor ring to transact packets on
1842 * @rx_buffer: buffer containing page to add
1843 * @rx_desc: descriptor containing length of buffer written by hardware
1844 * @skb: sk_buff to place the data into
1845 *
0549ae20
AD		 1846 * This function will add the data contained in rx_buffer->page to the skb.
1847 * This is done either through a direct copy if the data in the buffer is
1848 * less than the skb header size, otherwise it will just attach the page as
1849 * a frag to the skb.
1850 *
1851 * The function will then update the page offset if necessary and return
1852 * true if the buffer can be reused by the adapter.
f800326d 1853 **/
0549ae20 1854static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1855 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1856 union ixgbe_adv_rx_desc *rx_desc,
1857 struct sk_buff *skb)
f800326d 1858{
0549ae20
AD		 1859 struct page *page = rx_buffer->page;
1860 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1861#if (PAGE_SIZE < 8192)
0549ae20 1862 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1863#else
1864 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1865 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1866 ixgbe_rx_bufsz(rx_ring);
1867#endif
0549ae20 1868
cf3fe7ac
AD		 1869 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1870 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1871
1872 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1873
18cb652a
AD		 1874 /* page is not reserved, we can reuse buffer as-is */
1875 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1876 return true;
1877
1878 /* this page cannot be reused so discard it */
18cb652a 1879 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1880 return false;
1881 }
1882
0549ae20
AD		 1883 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1884 rx_buffer->page_offset, size, truesize);
1885
09816fbe 1886 /* avoid re-using remote pages */
18cb652a 1887 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1888 return false;
1889
1890#if (PAGE_SIZE < 8192)
1891 /* if we are only owner of page we can reuse it */
1892 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1893 return false;
1894
1895 /* flip page offset to other buffer */
1896 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1897#else
1898 /* move offset up to the next cache line */
1899 rx_buffer->page_offset += truesize;
1900
1901 if (rx_buffer->page_offset > last_offset)
1902 return false;
09816fbe 1903#endif
0549ae20 1904
18cb652a
AD		 1905 /* Even if we own the page, we are not allowed to use atomic_set()
1906 * This would break get_page_unless_zero() users.
1907 */
1908 atomic_inc(&page->_count);
1909
0549ae20 1910 return true;
f800326d
AD		 1911}
1912
18806c9e
AD		 1913static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1914 union ixgbe_adv_rx_desc *rx_desc)
1915{
1916 struct ixgbe_rx_buffer *rx_buffer;
1917 struct sk_buff *skb;
1918 struct page *page;
1919
1920 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1921 page = rx_buffer->page;
1922 prefetchw(page);
1923
1924 skb = rx_buffer->skb;
1925
1926 if (likely(!skb)) {
1927 void *page_addr = page_address(page) +
1928 rx_buffer->page_offset;
1929
1930 /* prefetch first cache line of first page */
1931 prefetch(page_addr);
1932#if L1_CACHE_BYTES < 128
1933 prefetch(page_addr + L1_CACHE_BYTES);
1934#endif
1935
1936 /* allocate a skb to store the frags */
67fd893e
AD		 1937 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1938 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1939 if (unlikely(!skb)) {
1940 rx_ring->rx_stats.alloc_rx_buff_failed++;
1941 return NULL;
1942 }
1943
1944 /*
1945 * we will be copying header into skb->data in
1946 * pskb_may_pull so it is in our interest to prefetch
1947 * it now to avoid a possible cache miss
1948 */
1949 prefetchw(skb->data);
1950
1951 /*
1952 * Delay unmapping of the first packet. It carries the
1953 * header information, HW may still access the header
1954 * after the writeback. Only unmap it when EOP is
1955 * reached
1956 */
1957 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1958 goto dma_sync;
1959
1960 IXGBE_CB(skb)->dma = rx_buffer->dma;
1961 } else {
1962 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1963 ixgbe_dma_sync_frag(rx_ring, skb);
1964
1965dma_sync:
1966 /* we are reusing so sync this buffer for CPU use */
1967 dma_sync_single_range_for_cpu(rx_ring->dev,
1968 rx_buffer->dma,
1969 rx_buffer->page_offset,
1970 ixgbe_rx_bufsz(rx_ring),
1971 DMA_FROM_DEVICE);
18cb652a
AD		 1972
1973 rx_buffer->skb = NULL;
18806c9e
AD		 1974 }
1975
1976 /* pull page into skb */
1977 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1978 /* hand second half of page back to the ring */
1979 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1980 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1981 /* the page has been released from the ring */
1982 IXGBE_CB(skb)->page_released = true;
1983 } else {
1984 /* we are not reusing the buffer so unmap it */
1985 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1986 ixgbe_rx_pg_size(rx_ring),
1987 DMA_FROM_DEVICE);
1988 }
1989
1990 /* clear contents of buffer_info */
18806c9e
AD		 1991 rx_buffer->page = NULL;
1992
1993 return skb;
f800326d
AD		 1994}
1995
1996/**
1997 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1998 * @q_vector: structure containing interrupt and ring information
1999 * @rx_ring: rx descriptor ring to transact packets on
2000 * @budget: Total limit on number of packets to process
2001 *
2002 * This function provides a "bounce buffer" approach to Rx interrupt
2003 * processing. The advantage to this is that on systems that have
2004 * expensive overhead for IOMMU access this provides a means of avoiding
2005 * it by maintaining the mapping of the page to the syste.
2006 *
5a85e737 2007 * Returns amount of work completed
f800326d 2008 **/
5a85e737 2009static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2010 struct ixgbe_ring *rx_ring,
f4de00ed 2011 const int budget)
9a799d71 2012{
d2f4fbe2 2013 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2014#ifdef IXGBE_FCOE
f800326d 2015 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2016 int ddp_bytes;
2017 unsigned int mss = 0;
3d8fd385 2018#endif /* IXGBE_FCOE */
f800326d 2019 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2020
fdabfc8a 2021 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2022 union ixgbe_adv_rx_desc *rx_desc;
2023 struct sk_buff *skb;
f800326d
AD		 2024
2025 /* return some buffers to hardware, one at a time is too slow */
2026 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2027 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2028 cleaned_count = 0;
2029 }
2030
18806c9e 2031 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2032
124b74c1 2033 if (!rx_desc->wb.upper.status_error)
f800326d 2034 break;
9a799d71 2035
124b74c1 2036 /* This memory barrier is needed to keep us from reading
f800326d 2037 * any other fields out of the rx_desc until we know the
124b74c1 2038 * descriptor has been written back
f800326d 2039 */
124b74c1 2040 dma_rmb();
9a799d71 2041
18806c9e
AD		 2042 /* retrieve a buffer from the ring */
2043 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2044
18806c9e
AD		 2045 /* exit if we failed to retrieve a buffer */
2046 if (!skb)
2047 break;
9a799d71 2048
9a799d71 2049 cleaned_count++;
f8212f97 2050
f800326d
AD		 2051 /* place incomplete frames back on ring for completion */
2052 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2053 continue;
c267fc16 2054
f800326d
AD		 2055 /* verify the packet layout is correct */
2056 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2057 continue;
9a799d71 2058
d2f4fbe2
AV		 2059 /* probably a little skewed due to removing CRC */
2060 total_rx_bytes += skb->len;
d2f4fbe2 2061
8a0da21b
AD		 2062 /* populate checksum, timestamp, VLAN, and protocol */
2063 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2064
332d4a7d
YZ		 2065#ifdef IXGBE_FCOE
2066 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2067 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2068 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2069 /* include DDPed FCoE data */
2070 if (ddp_bytes > 0) {
2071 if (!mss) {
2072 mss = rx_ring->netdev->mtu -
2073 sizeof(struct fcoe_hdr) -
2074 sizeof(struct fc_frame_header) -
2075 sizeof(struct fcoe_crc_eof);
2076 if (mss > 512)
2077 mss &= ~511;
2078 }
2079 total_rx_bytes += ddp_bytes;
2080 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2081 mss);
2082 }
63d635b2
AD		 2083 if (!ddp_bytes) {
2084 dev_kfree_skb_any(skb);
f800326d 2085 continue;
63d635b2 2086 }
3d8fd385 2087 }
f800326d 2088
332d4a7d 2089#endif /* IXGBE_FCOE */
8b80cda5 2090 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2091 ixgbe_rx_skb(q_vector, skb);
9a799d71 2092
f800326d 2093 /* update budget accounting */
f4de00ed 2094 total_rx_packets++;
fdabfc8a 2095 }
9a799d71 2096
c267fc16
AD		 2097 u64_stats_update_begin(&rx_ring->syncp);
2098 rx_ring->stats.packets += total_rx_packets;
2099 rx_ring->stats.bytes += total_rx_bytes;
2100 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2101 q_vector->rx.total_packets += total_rx_packets;
2102 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2103
5a85e737 2104 return total_rx_packets;
9a799d71
AK		 2105}
2106
e0d1095a 2107#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2108/* must be called with local_bh_disable()d */
2109static int ixgbe_low_latency_recv(struct napi_struct *napi)
2110{
2111 struct ixgbe_q_vector *q_vector =
2112 container_of(napi, struct ixgbe_q_vector, napi);
2113 struct ixgbe_adapter *adapter = q_vector->adapter;
2114 struct ixgbe_ring *ring;
2115 int found = 0;
2116
2117 if (test_bit(__IXGBE_DOWN, &adapter->state))
2118 return LL_FLUSH_FAILED;
2119
2120 if (!ixgbe_qv_lock_poll(q_vector))
2121 return LL_FLUSH_BUSY;
2122
2123 ixgbe_for_each_ring(ring, q_vector->rx) {
2124 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2125#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2126 if (found)
2127 ring->stats.cleaned += found;
2128 else
2129 ring->stats.misses++;
2130#endif
5a85e737
ET		 2131 if (found)
2132 break;
2133 }
2134
2135 ixgbe_qv_unlock_poll(q_vector);
2136
2137 return found;
2138}
e0d1095a 2139#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2140
9a799d71
AK		 2141/**
2142 * ixgbe_configure_msix - Configure MSI-X hardware
2143 * @adapter: board private structure
2144 *
2145 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2146 * interrupts.
2147 **/
2148static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2149{
021230d4 2150 struct ixgbe_q_vector *q_vector;
49c7ffbe 2151 int v_idx;
021230d4 2152 u32 mask;
9a799d71 2153
8e34d1aa
AD		 2154 /* Populate MSIX to EITR Select */
2155 if (adapter->num_vfs > 32) {
2156 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2157 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2158 }
2159
4df10466
JB		 2160 /*
2161 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2162 * corresponding register.
2163 */
49c7ffbe 2164 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2165 struct ixgbe_ring *ring;
7a921c93 2166 q_vector = adapter->q_vector[v_idx];
021230d4 2167
a557928e 2168 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2169 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2170
a557928e 2171 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2172 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2173
fe49f04a 2174 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2175 }
2176
bd508178
AD		 2177 switch (adapter->hw.mac.type) {
2178 case ixgbe_mac_82598EB:
e8e26350 2179 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2180 v_idx);
bd508178
AD		 2181 break;
2182 case ixgbe_mac_82599EB:
b93a2226 2183 case ixgbe_mac_X540:
9a75a1ac
DS		 2184 case ixgbe_mac_X550:
2185 case ixgbe_mac_X550EM_x:
e8e26350 2186 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2187 break;
bd508178
AD		 2188 default:
2189 break;
2190 }
021230d4
AV		 2191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2192
41fb9248 2193 /* set up to autoclear timer, and the vectors */
021230d4 2194 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2195 mask &= ~(IXGBE_EIMS_OTHER |
2196 IXGBE_EIMS_MAILBOX |
2197 IXGBE_EIMS_LSC);
2198
021230d4 2199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2200}
2201
f494e8fa
AV		 2202enum latency_range {
2203 lowest_latency = 0,
2204 low_latency = 1,
2205 bulk_latency = 2,
2206 latency_invalid = 255
2207};
2208
2209/**
2210 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2211 * @q_vector: structure containing interrupt and ring information
2212 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2213 *
2214 * Stores a new ITR value based on packets and byte
2215 * counts during the last interrupt. The advantage of per interrupt
2216 * computation is faster updates and more accurate ITR for the current
2217 * traffic pattern. Constants in this function were computed
2218 * based on theoretical maximum wire speed and thresholds were set based
2219 * on testing data as well as attempting to minimize response time
2220 * while increasing bulk throughput.
2221 * this functionality is controlled by the InterruptThrottleRate module
2222 * parameter (see ixgbe_param.c)
2223 **/
bd198058
AD		 2224static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2225 struct ixgbe_ring_container *ring_container)
f494e8fa 2226{
bd198058
AD		 2227 int bytes = ring_container->total_bytes;
2228 int packets = ring_container->total_packets;
2229 u32 timepassed_us;
621bd70e 2230 u64 bytes_perint;
bd198058 2231 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2232
2233 if (packets == 0)
bd198058 2234 return;
f494e8fa
AV		 2235
2236 /* simple throttlerate management
621bd70e
AD		 2237 * 0-10MB/s lowest (100000 ints/s)
2238 * 10-20MB/s low (20000 ints/s)
2239 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2240 */
2241 /* what was last interrupt timeslice? */
d5bf4f67 2242 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2243 if (timepassed_us == 0)
2244 return;
2245
f494e8fa
AV		 2246 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2247
2248 switch (itr_setting) {
2249 case lowest_latency:
621bd70e 2250 if (bytes_perint > 10)
bd198058 2251 itr_setting = low_latency;
f494e8fa
AV		 2252 break;
2253 case low_latency:
621bd70e 2254 if (bytes_perint > 20)
bd198058 2255 itr_setting = bulk_latency;
621bd70e 2256 else if (bytes_perint <= 10)
bd198058 2257 itr_setting = lowest_latency;
f494e8fa
AV		 2258 break;
2259 case bulk_latency:
621bd70e 2260 if (bytes_perint <= 20)
bd198058 2261 itr_setting = low_latency;
f494e8fa
AV		 2262 break;
2263 }
2264
bd198058
AD		 2265 /* clear work counters since we have the values we need */
2266 ring_container->total_bytes = 0;
2267 ring_container->total_packets = 0;
2268
2269 /* write updated itr to ring container */
2270 ring_container->itr = itr_setting;
f494e8fa
AV		 2271}
2272
509ee935
JB		 2273/**
2274 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2275 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2276 *
2277 * This function is made to be called by ethtool and by the driver
2278 * when it needs to update EITR registers at runtime. Hardware
2279 * specific quirks/differences are taken care of here.
2280 */
fe49f04a 2281void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2282{
fe49f04a 2283 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2284 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2285 int v_idx = q_vector->v_idx;
5d967eb7 2286 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2287
bd508178
AD		 2288 switch (adapter->hw.mac.type) {
2289 case ixgbe_mac_82598EB:
509ee935
JB		 2290 /* must write high and low 16 bits to reset counter */
2291 itr_reg |= (itr_reg << 16);
bd508178
AD		 2292 break;
2293 case ixgbe_mac_82599EB:
b93a2226 2294 case ixgbe_mac_X540:
9a75a1ac
DS		 2295 case ixgbe_mac_X550:
2296 case ixgbe_mac_X550EM_x:
509ee935
JB		 2297 /*
2298 * set the WDIS bit to not clear the timer bits and cause an
2299 * immediate assertion of the interrupt
2300 */
2301 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2302 break;
2303 default:
2304 break;
509ee935
JB		 2305 }
2306 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2307}
2308
bd198058 2309static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2310{
d5bf4f67 2311 u32 new_itr = q_vector->itr;
bd198058 2312 u8 current_itr;
f494e8fa 2313
bd198058
AD		 2314 ixgbe_update_itr(q_vector, &q_vector->tx);
2315 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2316
08c8833b 2317 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2318
2319 switch (current_itr) {
2320 /* counts and packets in update_itr are dependent on these numbers */
2321 case lowest_latency:
d5bf4f67 2322 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2323 break;
2324 case low_latency:
d5bf4f67 2325 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2326 break;
2327 case bulk_latency:
d5bf4f67 2328 new_itr = IXGBE_8K_ITR;
f494e8fa 2329 break;
bd198058
AD		 2330 default:
2331 break;
f494e8fa
AV		 2332 }
2333
d5bf4f67 2334 if (new_itr != q_vector->itr) {
fe49f04a 2335 /* do an exponential smoothing */
d5bf4f67
ET		 2336 new_itr = (10 * new_itr * q_vector->itr) /
2337 ((9 * new_itr) + q_vector->itr);
509ee935 2338
bd198058 2339 /* save the algorithm value here */
5d967eb7 2340 q_vector->itr = new_itr;
fe49f04a
AD		 2341
2342 ixgbe_write_eitr(q_vector);
f494e8fa 2343 }
f494e8fa
AV		 2344}
2345
119fc60a 2346/**
de88eeeb 2347 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2348 * @adapter: pointer to adapter
119fc60a 2349 **/
f0f9778d 2350static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2351{
119fc60a
MC		 2352 struct ixgbe_hw *hw = &adapter->hw;
2353 u32 eicr = adapter->interrupt_event;
2354
f0f9778d 2355 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2356 return;
2357
f0f9778d
AD		 2358 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2359 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2360 return;
2361
2362 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2363
7ca647bd 2364 switch (hw->device_id) {
f0f9778d
AD		 2365 case IXGBE_DEV_ID_82599_T3_LOM:
2366 /*
2367 * Since the warning interrupt is for both ports
2368 * we don't have to check if:
2369 * - This interrupt wasn't for our port.
2370 * - We may have missed the interrupt so always have to
2371 * check if we got a LSC
2372 */
2373 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2374 !(eicr & IXGBE_EICR_LSC))
2375 return;
2376
2377 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2378 u32 speed;
f0f9778d 2379 bool link_up = false;
7ca647bd 2380
3d292265 2381 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2382
f0f9778d
AD		 2383 if (link_up)
2384 return;
2385 }
2386
2387 /* Check if this is not due to overtemp */
2388 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2389 return;
2390
2391 break;
7ca647bd
JP		 2392 default:
2393 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2394 return;
7ca647bd 2395 break;
119fc60a 2396 }
7ca647bd
JP		 2397 e_crit(drv,
2398 "Network adapter has been stopped because it has over heated. "
2399 "Restart the computer. If the problem persists, "
2400 "power off the system and replace the adapter\n");
f0f9778d
AD		 2401
2402 adapter->interrupt_event = 0;
119fc60a
MC		 2403}
2404
0befdb3e
JB		 2405static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2406{
2407 struct ixgbe_hw *hw = &adapter->hw;
2408
2409 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2410 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2411 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2412 /* write to clear the interrupt */
2413 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2414 }
2415}
cf8280ee 2416
4f51bf70
JK		 2417static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2418{
2419 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2420 return;
2421
2422 switch (adapter->hw.mac.type) {
2423 case ixgbe_mac_82599EB:
2424 /*
2425 * Need to check link state so complete overtemp check
2426 * on service task
2427 */
2428 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2429 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2430 adapter->interrupt_event = eicr;
2431 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2432 ixgbe_service_event_schedule(adapter);
2433 return;
2434 }
2435 return;
2436 case ixgbe_mac_X540:
2437 if (!(eicr & IXGBE_EICR_TS))
2438 return;
2439 break;
2440 default:
2441 return;
2442 }
2443
2444 e_crit(drv,
2445 "Network adapter has been stopped because it has over heated. "
2446 "Restart the computer. If the problem persists, "
2447 "power off the system and replace the adapter\n");
2448}
2449
e8e26350
PW		 2450static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2451{
2452 struct ixgbe_hw *hw = &adapter->hw;
2453
73c4b7cd
AD		 2454 if (eicr & IXGBE_EICR_GPI_SDP2) {
2455 /* Clear the interrupt */
2456 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2457 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2458 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2459 ixgbe_service_event_schedule(adapter);
2460 }
73c4b7cd
AD		 2461 }
2462
e8e26350
PW		 2463 if (eicr & IXGBE_EICR_GPI_SDP1) {
2464 /* Clear the interrupt */
2465 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2466 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2467 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2468 ixgbe_service_event_schedule(adapter);
2469 }
e8e26350
PW		 2470 }
2471}
2472
cf8280ee
JB		 2473static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2474{
2475 struct ixgbe_hw *hw = &adapter->hw;
2476
2477 adapter->lsc_int++;
2478 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2479 adapter->link_check_timeout = jiffies;
2480 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2481 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2482 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2483 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2484 }
2485}
2486
fe49f04a
AD		 2487static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2488 u64 qmask)
2489{
2490 u32 mask;
bd508178 2491 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2492
bd508178
AD		 2493 switch (hw->mac.type) {
2494 case ixgbe_mac_82598EB:
fe49f04a 2495 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2496 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2497 break;
2498 case ixgbe_mac_82599EB:
b93a2226 2499 case ixgbe_mac_X540:
9a75a1ac
DS		 2500 case ixgbe_mac_X550:
2501 case ixgbe_mac_X550EM_x:
fe49f04a 2502 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2503 if (mask)
2504 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2505 mask = (qmask >> 32);
bd508178
AD		 2506 if (mask)
2507 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2508 break;
2509 default:
2510 break;
fe49f04a
AD		 2511 }
2512 /* skip the flush */
2513}
2514
2515static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2516 u64 qmask)
fe49f04a
AD		 2517{
2518 u32 mask;
bd508178 2519 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2520
bd508178
AD		 2521 switch (hw->mac.type) {
2522 case ixgbe_mac_82598EB:
fe49f04a 2523 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2524 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2525 break;
2526 case ixgbe_mac_82599EB:
b93a2226 2527 case ixgbe_mac_X540:
9a75a1ac
DS		 2528 case ixgbe_mac_X550:
2529 case ixgbe_mac_X550EM_x:
fe49f04a 2530 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2531 if (mask)
2532 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2533 mask = (qmask >> 32);
bd508178
AD		 2534 if (mask)
2535 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2536 break;
2537 default:
2538 break;
fe49f04a
AD		 2539 }
2540 /* skip the flush */
2541}
2542
021230d4 2543/**
2c4af694
AD		 2544 * ixgbe_irq_enable - Enable default interrupt generation settings
2545 * @adapter: board private structure
021230d4 2546 **/
2c4af694
AD		 2547static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2548 bool flush)
9a799d71 2549{
2c4af694 2550 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2551
2c4af694
AD		 2552 /* don't reenable LSC while waiting for link */
2553 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2554 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2555
2c4af694 2556 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2557 switch (adapter->hw.mac.type) {
2558 case ixgbe_mac_82599EB:
2559 mask |= IXGBE_EIMS_GPI_SDP0;
2560 break;
2561 case ixgbe_mac_X540:
9a75a1ac
DS		 2562 case ixgbe_mac_X550:
2563 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2564 mask |= IXGBE_EIMS_TS;
2565 break;
2566 default:
2567 break;
2568 }
2c4af694
AD		 2569 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2570 mask |= IXGBE_EIMS_GPI_SDP1;
2571 switch (adapter->hw.mac.type) {
2572 case ixgbe_mac_82599EB:
2c4af694
AD		 2573 mask |= IXGBE_EIMS_GPI_SDP1;
2574 mask |= IXGBE_EIMS_GPI_SDP2;
9a75a1ac 2575 /* fall through */
858bc081 2576 case ixgbe_mac_X540:
9a75a1ac
DS		 2577 case ixgbe_mac_X550:
2578 case ixgbe_mac_X550EM_x:
858bc081 2579 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2580 mask |= IXGBE_EIMS_MAILBOX;
2581 break;
2582 default:
2583 break;
9a799d71 2584 }
db0677fa 2585
2c4af694
AD		 2586 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2587 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2588 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2589
2c4af694
AD		 2590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2591 if (queues)
2592 ixgbe_irq_enable_queues(adapter, ~0);
2593 if (flush)
2594 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2595}
2596
2c4af694 2597static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2598{
a65151ba 2599 struct ixgbe_adapter *adapter = data;
9a799d71 2600 struct ixgbe_hw *hw = &adapter->hw;
54037505 2601 u32 eicr;
91281fd3 2602
54037505
DS		 2603 /*
2604 * Workaround for Silicon errata. Use clear-by-write instead
2605 * of clear-by-read. Reading with EICS will return the
2606 * interrupt causes without clearing, which later be done
2607 * with the write to EICR.
2608 */
2609 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2610
2611 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2612 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2613 * the bits are high when ixgbe_msix_other is called. There is a race
2614 * condition otherwise which results in possible performance loss
2615 * especially if the ixgbe_msix_other interrupt is triggering
2616 * consistently (as it would when PPS is turned on for the X540 device)
2617 */
2618 eicr &= 0xFFFF0000;
2619
54037505 2620 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2621
cf8280ee
JB		 2622 if (eicr & IXGBE_EICR_LSC)
2623 ixgbe_check_lsc(adapter);
f0848276 2624
1cdd1ec8
GR		 2625 if (eicr & IXGBE_EICR_MAILBOX)
2626 ixgbe_msg_task(adapter);
efe3d3c8 2627
bd508178
AD		 2628 switch (hw->mac.type) {
2629 case ixgbe_mac_82599EB:
b93a2226 2630 case ixgbe_mac_X540:
9a75a1ac
DS		 2631 case ixgbe_mac_X550:
2632 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2633 if (eicr & IXGBE_EICR_ECC) {
2634 e_info(link, "Received ECC Err, initiating reset\n");
2635 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2636 ixgbe_service_event_schedule(adapter);
2637 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2638 }
c4cf55e5
PWJ		 2639 /* Handle Flow Director Full threshold interrupt */
2640 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2641 int reinit_count = 0;
c4cf55e5 2642 int i;
c4cf55e5 2643 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2644 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2645 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2646 &ring->state))
2647 reinit_count++;
2648 }
2649 if (reinit_count) {
2650 /* no more flow director interrupts until after init */
2651 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2652 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2653 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2654 }
2655 }
f0f9778d 2656 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2657 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2658 break;
2659 default:
2660 break;
c4cf55e5 2661 }
f0848276 2662
bd508178 2663 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2664
db0677fa
JK		 2665 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2666 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2667
7086400d 2668 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2669 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2670 ixgbe_irq_enable(adapter, false, false);
f0848276 2671
9a799d71 2672 return IRQ_HANDLED;
f0848276 2673}
91281fd3 2674
4ff7fb12 2675static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2676{
021230d4 2677 struct ixgbe_q_vector *q_vector = data;
91281fd3 2678
9b471446 2679 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2680
4ff7fb12
AD		 2681 if (q_vector->rx.ring || q_vector->tx.ring)
2682 napi_schedule(&q_vector->napi);
91281fd3 2683
9a799d71 2684 return IRQ_HANDLED;
91281fd3
AD		 2685}
2686
eb01b975
AD		 2687/**
2688 * ixgbe_poll - NAPI Rx polling callback
2689 * @napi: structure for representing this polling device
2690 * @budget: how many packets driver is allowed to clean
2691 *
2692 * This function is used for legacy and MSI, NAPI mode
2693 **/
8af3c33f 2694int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2695{
2696 struct ixgbe_q_vector *q_vector =
2697 container_of(napi, struct ixgbe_q_vector, napi);
2698 struct ixgbe_adapter *adapter = q_vector->adapter;
2699 struct ixgbe_ring *ring;
2700 int per_ring_budget;
2701 bool clean_complete = true;
2702
2703#ifdef CONFIG_IXGBE_DCA
2704 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2705 ixgbe_update_dca(q_vector);
2706#endif
2707
2708 ixgbe_for_each_ring(ring, q_vector->tx)
2709 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2710
5a85e737
ET		 2711 if (!ixgbe_qv_lock_napi(q_vector))
2712 return budget;
2713
eb01b975
AD		 2714 /* attempt to distribute budget to each queue fairly, but don't allow
2715 * the budget to go below 1 because we'll exit polling */
2716 if (q_vector->rx.count > 1)
2717 per_ring_budget = max(budget/q_vector->rx.count, 1);
2718 else
2719 per_ring_budget = budget;
2720
2721 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2722 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2723 per_ring_budget) < per_ring_budget);
eb01b975 2724
5a85e737 2725 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2726 /* If all work not completed, return budget and keep polling */
2727 if (!clean_complete)
2728 return budget;
2729
2730 /* all work done, exit the polling mode */
2731 napi_complete(napi);
2732 if (adapter->rx_itr_setting & 1)
2733 ixgbe_set_itr(q_vector);
2734 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2735 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2736
2737 return 0;
2738}
2739
021230d4
AV		 2740/**
2741 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2742 * @adapter: board private structure
2743 *
2744 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2745 * interrupts from the kernel.
2746 **/
2747static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2748{
2749 struct net_device *netdev = adapter->netdev;
207867f5 2750 int vector, err;
e8e9f696 2751 int ri = 0, ti = 0;
021230d4 2752
49c7ffbe 2753 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2754 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2755 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2756
4ff7fb12 2757 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2758 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2759 "%s-%s-%d", netdev->name, "TxRx", ri++);
2760 ti++;
2761 } else if (q_vector->rx.ring) {
9fe93afd 2762 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2763 "%s-%s-%d", netdev->name, "rx", ri++);
2764 } else if (q_vector->tx.ring) {
9fe93afd 2765 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2766 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2767 } else {
2768 /* skip this unused q_vector */
2769 continue;
32aa77a4 2770 }
207867f5
AD		 2771 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2772 q_vector->name, q_vector);
9a799d71 2773 if (err) {
396e799c 2774 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2775 "Error: %d\n", err);
021230d4 2776 goto free_queue_irqs;
9a799d71 2777 }
207867f5
AD		 2778 /* If Flow Director is enabled, set interrupt affinity */
2779 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2780 /* assign the mask for this irq */
2781 irq_set_affinity_hint(entry->vector,
de88eeeb 2782 &q_vector->affinity_mask);
207867f5 2783 }
9a799d71
AK		 2784 }
2785
021230d4 2786 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2787 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2788 if (err) {
de88eeeb 2789 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2790 goto free_queue_irqs;
9a799d71
AK		 2791 }
2792
9a799d71
AK		 2793 return 0;
2794
021230d4 2795free_queue_irqs:
207867f5
AD		 2796 while (vector) {
2797 vector--;
2798 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2799 NULL);
2800 free_irq(adapter->msix_entries[vector].vector,
2801 adapter->q_vector[vector]);
2802 }
021230d4
AV		 2803 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2804 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2805 kfree(adapter->msix_entries);
2806 adapter->msix_entries = NULL;
9a799d71
AK		 2807 return err;
2808}
2809
2810/**
021230d4 2811 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2812 * @irq: interrupt number
2813 * @data: pointer to a network interface device structure
9a799d71
AK		 2814 **/
2815static irqreturn_t ixgbe_intr(int irq, void *data)
2816{
a65151ba 2817 struct ixgbe_adapter *adapter = data;
9a799d71 2818 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2819 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2820 u32 eicr;
2821
54037505 2822 /*
24ddd967 2823 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2824 * before the read of EICR.
2825 */
2826 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2827
021230d4 2828 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2829 * therefore no explicit interrupt disable is necessary */
021230d4 2830 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2831 if (!eicr) {
6af3b9eb
ET		 2832 /*
2833 * shared interrupt alert!
f47cf66e 2834 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2835 * have disabled interrupts due to EIAM
2836 * finish the workaround of silicon errata on 82598. Unmask
2837 * the interrupt that we masked before the EICR read.
2838 */
2839 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2840 ixgbe_irq_enable(adapter, true, true);
9a799d71 2841 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2842 }
9a799d71 2843
cf8280ee
JB		 2844 if (eicr & IXGBE_EICR_LSC)
2845 ixgbe_check_lsc(adapter);
021230d4 2846
bd508178
AD		 2847 switch (hw->mac.type) {
2848 case ixgbe_mac_82599EB:
e8e26350 2849 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2850 /* Fall through */
2851 case ixgbe_mac_X540:
9a75a1ac
DS		 2852 case ixgbe_mac_X550:
2853 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2854 if (eicr & IXGBE_EICR_ECC) {
2855 e_info(link, "Received ECC Err, initiating reset\n");
2856 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2857 ixgbe_service_event_schedule(adapter);
2858 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2859 }
4f51bf70 2860 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2861 break;
2862 default:
2863 break;
2864 }
e8e26350 2865
0befdb3e 2866 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2867 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2868 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2869
b9f6ed2b
AD		 2870 /* would disable interrupts here but EIAM disabled it */
2871 napi_schedule(&q_vector->napi);
9a799d71 2872
6af3b9eb
ET		 2873 /*
2874 * re-enable link(maybe) and non-queue interrupts, no flush.
2875 * ixgbe_poll will re-enable the queue interrupts
2876 */
6af3b9eb
ET		 2877 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2878 ixgbe_irq_enable(adapter, false, false);
2879
9a799d71
AK		 2880 return IRQ_HANDLED;
2881}
2882
2883/**
2884 * ixgbe_request_irq - initialize interrupts
2885 * @adapter: board private structure
2886 *
2887 * Attempts to configure interrupts using the best available
2888 * capabilities of the hardware and kernel.
2889 **/
021230d4 2890static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2891{
2892 struct net_device *netdev = adapter->netdev;
021230d4 2893 int err;
9a799d71 2894
4cc6df29 2895 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2896 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2897 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2898 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2899 netdev->name, adapter);
4cc6df29 2900 else
a0607fd3 2901 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2902 netdev->name, adapter);
9a799d71 2903
de88eeeb 2904 if (err)
396e799c 2905 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2906
9a799d71
AK		 2907 return err;
2908}
2909
2910static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2911{
49c7ffbe 2912 int vector;
9a799d71 2913
49c7ffbe
AD		 2914 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2915 free_irq(adapter->pdev->irq, adapter);
2916 return;
2917 }
4cc6df29 2918
49c7ffbe
AD		 2919 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2920 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2921 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2922
49c7ffbe
AD		 2923 /* free only the irqs that were actually requested */
2924 if (!q_vector->rx.ring && !q_vector->tx.ring)
2925 continue;
207867f5 2926
49c7ffbe
AD		 2927 /* clear the affinity_mask in the IRQ descriptor */
2928 irq_set_affinity_hint(entry->vector, NULL);
2929
2930 free_irq(entry->vector, q_vector);
9a799d71 2931 }
49c7ffbe
AD		 2932
2933 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2934}
2935
22d5a71b
JB		 2936/**
2937 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2938 * @adapter: board private structure
2939 **/
2940static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2941{
bd508178
AD		 2942 switch (adapter->hw.mac.type) {
2943 case ixgbe_mac_82598EB:
835462fc 2944 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2945 break;
2946 case ixgbe_mac_82599EB:
b93a2226 2947 case ixgbe_mac_X540:
9a75a1ac
DS		 2948 case ixgbe_mac_X550:
2949 case ixgbe_mac_X550EM_x:
835462fc
NS		 2950 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2952 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2953 break;
2954 default:
2955 break;
22d5a71b
JB		 2956 }
2957 IXGBE_WRITE_FLUSH(&adapter->hw);
2958 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2959 int vector;
2960
2961 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2962 synchronize_irq(adapter->msix_entries[vector].vector);
2963
2964 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2965 } else {
2966 synchronize_irq(adapter->pdev->irq);
2967 }
2968}
2969
9a799d71
AK		 2970/**
2971 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2972 *
2973 **/
2974static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2975{
d5bf4f67 2976 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2977
d5bf4f67 2978 ixgbe_write_eitr(q_vector);
9a799d71 2979
e8e26350
PW		 2980 ixgbe_set_ivar(adapter, 0, 0, 0);
2981 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2982
396e799c 2983 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2984}
2985
43e69bf0
AD		 2986/**
2987 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2988 * @adapter: board private structure
2989 * @ring: structure containing ring specific data
2990 *
2991 * Configure the Tx descriptor ring after a reset.
2992 **/
84418e3b
AD		 2993void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2994 struct ixgbe_ring *ring)
43e69bf0
AD		 2995{
2996 struct ixgbe_hw *hw = &adapter->hw;
2997 u64 tdba = ring->dma;
2f1860b8 2998 int wait_loop = 10;
b88c6de2 2999 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3000 u8 reg_idx = ring->reg_idx;
43e69bf0 3001
2f1860b8 3002 /* disable queue to avoid issues while updating state */
b88c6de2 3003 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3004 IXGBE_WRITE_FLUSH(hw);
3005
43e69bf0 3006 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3007 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3008 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3009 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3010 ring->count * sizeof(union ixgbe_adv_tx_desc));
3011 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3012 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3013 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3014
b88c6de2
AD		 3015 /*
3016 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3017 * higher than 1 when:
3018 * - ITR is 0 as it could cause false TX hangs
3019 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3020 *
3021 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3022 * to or less than the number of on chip descriptors, which is
3023 * currently 40.
3024 */
67da097e 3025 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3026 txdctl |= (1 << 16); /* WTHRESH = 1 */
3027 else
3028 txdctl |= (8 << 16); /* WTHRESH = 8 */
3029
e954b374
AD		 3030 /*
3031 * Setting PTHRESH to 32 both improves performance
3032 * and avoids a TX hang with DFP enabled
3033 */
b88c6de2
AD		 3034 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3035 32; /* PTHRESH = 32 */
2f1860b8
AD		 3036
3037 /* reinitialize flowdirector state */
39cb681b 3038 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3039 ring->atr_sample_rate = adapter->atr_sample_rate;
3040 ring->atr_count = 0;
3041 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3042 } else {
3043 ring->atr_sample_rate = 0;
3044 }
2f1860b8 3045
fd786b7b
AD		 3046 /* initialize XPS */
3047 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3048 struct ixgbe_q_vector *q_vector = ring->q_vector;
3049
3050 if (q_vector)
2a47fa45 3051 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3052 &q_vector->affinity_mask,
3053 ring->queue_index);
3054 }
3055
c84d324c
JF		 3056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3057
2f1860b8 3058 /* enable queue */
2f1860b8
AD		 3059 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3060
3061 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3062 if (hw->mac.type == ixgbe_mac_82598EB &&
3063 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3064 return;
3065
3066 /* poll to verify queue is enabled */
3067 do {
032b4325 3068 usleep_range(1000, 2000);
2f1860b8
AD		 3069 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3070 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3071 if (!wait_loop)
3072 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3073}
3074
120ff942
AD		 3075static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3076{
3077 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3078 u32 rttdcs, mtqc;
8b1c0b24 3079 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3080
3081 if (hw->mac.type == ixgbe_mac_82598EB)
3082 return;
3083
3084 /* disable the arbiter while setting MTQC */
3085 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3086 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3087 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3088
3089 /* set transmit pool layout */
671c0adb
AD		 3090 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3091 mtqc = IXGBE_MTQC_VT_ENA;
3092 if (tcs > 4)
3093 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3094 else if (tcs > 1)
3095 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3096 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3097 mtqc |= IXGBE_MTQC_32VF;
3098 else
3099 mtqc |= IXGBE_MTQC_64VF;
3100 } else {
3101 if (tcs > 4)
3102 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3103 else if (tcs > 1)
3104 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3105 else
671c0adb
AD		 3106 mtqc = IXGBE_MTQC_64Q_1PB;
3107 }
120ff942 3108
671c0adb 3109 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3110
671c0adb
AD		 3111 /* Enable Security TX Buffer IFG for multiple pb */
3112 if (tcs) {
3113 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3114 sectx |= IXGBE_SECTX_DCB;
3115 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3116 }
3117
3118 /* re-enable the arbiter */
3119 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3120 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3121}
3122
9a799d71 3123/**
3a581073 3124 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3125 * @adapter: board private structure
3126 *
3127 * Configure the Tx unit of the MAC after a reset.
3128 **/
3129static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3130{
2f1860b8
AD		 3131 struct ixgbe_hw *hw = &adapter->hw;
3132 u32 dmatxctl;
43e69bf0 3133 u32 i;
9a799d71 3134
2f1860b8
AD		 3135 ixgbe_setup_mtqc(adapter);
3136
3137 if (hw->mac.type != ixgbe_mac_82598EB) {
3138 /* DMATXCTL.EN must be before Tx queues are enabled */
3139 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3140 dmatxctl |= IXGBE_DMATXCTL_TE;
3141 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3142 }
3143
9a799d71 3144 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3145 for (i = 0; i < adapter->num_tx_queues; i++)
3146 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3147}
3148
3ebe8fde
AD		 3149static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3150 struct ixgbe_ring *ring)
3151{
3152 struct ixgbe_hw *hw = &adapter->hw;
3153 u8 reg_idx = ring->reg_idx;
3154 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3155
3156 srrctl |= IXGBE_SRRCTL_DROP_EN;
3157
3158 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3159}
3160
3161static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3162 struct ixgbe_ring *ring)
3163{
3164 struct ixgbe_hw *hw = &adapter->hw;
3165 u8 reg_idx = ring->reg_idx;
3166 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3167
3168 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3169
3170 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3171}
3172
3173#ifdef CONFIG_IXGBE_DCB
3174void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3175#else
3176static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3177#endif
3178{
3179 int i;
3180 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3181
3182 if (adapter->ixgbe_ieee_pfc)
3183 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3184
3185 /*
3186 * We should set the drop enable bit if:
3187 * SR-IOV is enabled
3188 * or
3189 * Number of Rx queues > 1 and flow control is disabled
3190 *
3191 * This allows us to avoid head of line blocking for security
3192 * and performance reasons.
3193 */
3194 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3195 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3196 for (i = 0; i < adapter->num_rx_queues; i++)
3197 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3198 } else {
3199 for (i = 0; i < adapter->num_rx_queues; i++)
3200 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3201 }
3202}
3203
e8e26350 3204#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3205
a6616b42 3206static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3207 struct ixgbe_ring *rx_ring)
cc41ac7c 3208{
45e9baa5 3209 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3210 u32 srrctl;
bf29ee6c 3211 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3212
45e9baa5
AD		 3213 if (hw->mac.type == ixgbe_mac_82598EB) {
3214 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3215
45e9baa5
AD		 3216 /*
3217 * if VMDq is not active we must program one srrctl register
3218 * per RSS queue since we have enabled RDRXCTL.MVMEN
3219 */
3220 reg_idx &= mask;
3221 }
cc41ac7c 3222
45e9baa5
AD		 3223 /* configure header buffer length, needed for RSC */
3224 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3225
45e9baa5 3226 /* configure the packet buffer length */
f800326d 3227 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3228
3229 /* configure descriptor type */
f800326d 3230 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3231
45e9baa5 3232 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3233}
9a799d71 3234
d1b849b9 3235static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed)
0cefafad 3236{
05abb126 3237 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3238 u32 reta = 0;
05abb126 3239 int i, j;
0f9b232b 3240 int reta_entries = 128;
671c0adb 3241 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
0f9b232b 3242 int indices_multi;
671c0adb 3243
671c0adb
AD		 3244 /*
3245 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3246 * make full use of any rings they may have. We will use the
3247 * PSRTYPE register to control how many rings we use within the PF.
3248 */
3249 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3250 rss_i = 2;
0cefafad 3251
05abb126
AD		 3252 /* Fill out hash function seeds */
3253 for (i = 0; i < 10; i++)
3254 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3255
0f9b232b
DS		 3256 /* Fill out the redirection table as follows:
3257 * 82598: 128 (8 bit wide) entries containing pair of 4 bit RSS indices
3258 * 82599/X540: 128 (8 bit wide) entries containing 4 bit RSS index
3259 * X550: 512 (8 bit wide) entries containing 6 bit RSS index
3260 */
3261 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3262 indices_multi = 0x11;
3263 else
3264 indices_multi = 0x1;
3265
3266 switch (adapter->hw.mac.type) {
3267 case ixgbe_mac_X550:
3268 case ixgbe_mac_X550EM_x:
3269 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3270 reta_entries = 512;
3271 default:
3272 break;
3273 }
3274
05abb126 3275 /* Fill out redirection table */
0f9b232b
DS		 3276 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3277 if (j == rss_i)
3278 j = 0;
3279 reta = (reta << 8) | (j * indices_multi);
3280 if ((i & 3) == 3) {
3281 if (i < 128)
3282 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3283 else
3284 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3285 reta);
3286 }
3287 }
3288}
3289
3290static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter, const u32 *seed)
3291{
3292 struct ixgbe_hw *hw = &adapter->hw;
3293 u32 vfreta = 0;
3294 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3295 unsigned int pf_pool = adapter->num_vfs;
3296 int i, j;
3297
3298 /* Fill out hash function seeds */
3299 for (i = 0; i < 10; i++)
3300 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), seed[i]);
3301
3302 /* Fill out the redirection table */
3303 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3304 if (j == rss_i)
05abb126 3305 j = 0;
0f9b232b 3306 vfreta = (vfreta << 8) | j;
05abb126 3307 if ((i & 3) == 3)
0f9b232b
DS		 3308 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3309 vfreta);
05abb126 3310 }
d1b849b9
DS		 3311}
3312
3313static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3314{
3315 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3316 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
9913c61c 3317 u32 rss_key[10];
d1b849b9 3318 u32 rxcsum;
0cefafad 3319
05abb126
AD		 3320 /* Disable indicating checksum in descriptor, enables RSS hash */
3321 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3322 rxcsum |= IXGBE_RXCSUM_PCSD;
3323 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3324
671c0adb 3325 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3326 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3327 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3328 } else {
671c0adb
AD		 3329 u8 tcs = netdev_get_num_tc(adapter->netdev);
3330
3331 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3332 if (tcs > 4)
3333 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3334 else if (tcs > 1)
3335 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3336 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3337 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3338 else
671c0adb
AD		 3339 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3340 } else {
3341 if (tcs > 4)
8b1c0b24 3342 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3343 else if (tcs > 1)
3344 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3345 else
3346 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3347 }
0cefafad
JB		 3348 }
3349
05abb126 3350 /* Perform hash on these packet types */
d1b849b9
DS		 3351 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3352 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3353 IXGBE_MRQC_RSS_FIELD_IPV6 |
3354 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3355
ef6afc0c 3356 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3357 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3358 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3359 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3360
9913c61c 3361 netdev_rss_key_fill(rss_key, sizeof(rss_key));
0f9b232b
DS		 3362 if ((hw->mac.type >= ixgbe_mac_X550) &&
3363 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3364 unsigned int pf_pool = adapter->num_vfs;
3365
3366 /* Enable VF RSS mode */
3367 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3368 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3369
3370 /* Setup RSS through the VF registers */
3371 ixgbe_setup_vfreta(adapter, rss_key);
3372 vfmrqc = IXGBE_MRQC_RSSEN;
3373 vfmrqc |= rss_field;
3374 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3375 } else {
3376 ixgbe_setup_reta(adapter, rss_key);
3377 mrqc |= rss_field;
3378 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3379 }
0cefafad
JB		 3380}
3381
bb5a9ad2
NS		 3382/**
3383 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3384 * @adapter: address of board private structure
3385 * @index: index of ring to set
bb5a9ad2 3386 **/
082757af 3387static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3388 struct ixgbe_ring *ring)
bb5a9ad2 3389{
bb5a9ad2 3390 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3391 u32 rscctrl;
bf29ee6c 3392 u8 reg_idx = ring->reg_idx;
7367096a 3393
7d637bcc 3394 if (!ring_is_rsc_enabled(ring))
7367096a 3395 return;
bb5a9ad2 3396
7367096a 3397 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3398 rscctrl |= IXGBE_RSCCTL_RSCEN;
3399 /*
3400 * we must limit the number of descriptors so that the
3401 * total size of max desc * buf_len is not greater
642c680e 3402 * than 65536
bb5a9ad2 3403 */
f800326d 3404 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3405 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3406}
3407
9e10e045
AD		 3408#define IXGBE_MAX_RX_DESC_POLL 10
3409static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3410 struct ixgbe_ring *ring)
3411{
3412 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3413 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3414 u32 rxdctl;
bf29ee6c 3415 u8 reg_idx = ring->reg_idx;
9e10e045 3416
b0483c8f
MR		 3417 if (ixgbe_removed(hw->hw_addr))
3418 return;
9e10e045
AD		 3419 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3420 if (hw->mac.type == ixgbe_mac_82598EB &&
3421 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3422 return;
3423
3424 do {
032b4325 3425 usleep_range(1000, 2000);
9e10e045
AD		 3426 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3427 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3428
3429 if (!wait_loop) {
3430 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3431 "the polling period\n", reg_idx);
3432 }
3433}
3434
2d39d576
YZ		 3435void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3436 struct ixgbe_ring *ring)
3437{
3438 struct ixgbe_hw *hw = &adapter->hw;
3439 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3440 u32 rxdctl;
3441 u8 reg_idx = ring->reg_idx;
3442
b0483c8f
MR		 3443 if (ixgbe_removed(hw->hw_addr))
3444 return;
2d39d576
YZ		 3445 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3446 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3447
3448 /* write value back with RXDCTL.ENABLE bit cleared */
3449 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3450
3451 if (hw->mac.type == ixgbe_mac_82598EB &&
3452 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3453 return;
3454
3455 /* the hardware may take up to 100us to really disable the rx queue */
3456 do {
3457 udelay(10);
3458 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3459 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3460
3461 if (!wait_loop) {
3462 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3463 "the polling period\n", reg_idx);
3464 }
3465}
3466
84418e3b
AD		 3467void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3468 struct ixgbe_ring *ring)
acd37177
AD		 3469{
3470 struct ixgbe_hw *hw = &adapter->hw;
3471 u64 rdba = ring->dma;
9e10e045 3472 u32 rxdctl;
bf29ee6c 3473 u8 reg_idx = ring->reg_idx;
acd37177 3474
9e10e045
AD		 3475 /* disable queue to avoid issues while updating state */
3476 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3477 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3478
acd37177
AD		 3479 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3480 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3481 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3482 ring->count * sizeof(union ixgbe_adv_rx_desc));
3483 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3484 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3485 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3486
3487 ixgbe_configure_srrctl(adapter, ring);
3488 ixgbe_configure_rscctl(adapter, ring);
3489
3490 if (hw->mac.type == ixgbe_mac_82598EB) {
3491 /*
3492 * enable cache line friendly hardware writes:
3493 * PTHRESH=32 descriptors (half the internal cache),
3494 * this also removes ugly rx_no_buffer_count increment
3495 * HTHRESH=4 descriptors (to minimize latency on fetch)
3496 * WTHRESH=8 burst writeback up to two cache lines
3497 */
3498 rxdctl &= ~0x3FFFFF;
3499 rxdctl |= 0x080420;
3500 }
3501
3502 /* enable receive descriptor ring */
3503 rxdctl |= IXGBE_RXDCTL_ENABLE;
3504 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3505
3506 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3507 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3508}
3509
48654521
AD		 3510static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3511{
3512 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3513 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3514 u16 pool;
48654521
AD		 3515
3516 /* PSRTYPE must be initialized in non 82598 adapters */
3517 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3518 IXGBE_PSRTYPE_UDPHDR |
3519 IXGBE_PSRTYPE_IPV4HDR |
48654521 3520 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3521 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3522
3523 if (hw->mac.type == ixgbe_mac_82598EB)
3524 return;
3525
fbe7ca7f
AD		 3526 if (rss_i > 3)
3527 psrtype |= 2 << 29;
3528 else if (rss_i > 1)
3529 psrtype |= 1 << 29;
48654521 3530
2a47fa45
JF		 3531 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3532 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3533}
3534
f5b4a52e
AD		 3535static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3536{
3537 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3538 u32 reg_offset, vf_shift;
435b19f6 3539 u32 gcr_ext, vmdctl;
de4c7f65 3540 int i;
f5b4a52e
AD		 3541
3542 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3543 return;
3544
3545 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3546 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3547 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3548 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3549 vmdctl |= IXGBE_VT_CTL_REPLEN;
3550 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3551
1d9c0bfd
AD		 3552 vf_shift = VMDQ_P(0) % 32;
3553 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3554
3555 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3556 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3557 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3558 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3559 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3560 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3561 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3562
3563 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3564 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3565
3566 /*
3567 * Set up VF register offsets for selected VT Mode,
3568 * i.e. 32 or 64 VFs for SR-IOV
3569 */
73079ea0
AD		 3570 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3571 case IXGBE_82599_VMDQ_8Q_MASK:
3572 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3573 break;
3574 case IXGBE_82599_VMDQ_4Q_MASK:
3575 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3576 break;
3577 default:
3578 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3579 break;
3580 }
3581
f5b4a52e
AD		 3582 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3583
435b19f6 3584
a985b6c3 3585 /* Enable MAC Anti-Spoofing */
435b19f6 3586 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3587 adapter->num_vfs);
5b7f000f
DS		 3588
3589 /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3590 * calling set_ethertype_anti_spoofing for each VF in loop below
3591 */
3592 if (hw->mac.ops.set_ethertype_anti_spoofing)
3593 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3594 (IXGBE_ETQF_FILTER_EN | /* enable filter */
3595 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3596 IXGBE_ETH_P_LLDP)); /* LLDP eth type */
3597
de4c7f65
GR		 3598 /* For VFs that have spoof checking turned off */
3599 for (i = 0; i < adapter->num_vfs; i++) {
3600 if (!adapter->vfinfo[i].spoofchk_enabled)
3601 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3602
3603 /* enable ethertype anti spoofing if hw supports it */
3604 if (hw->mac.ops.set_ethertype_anti_spoofing)
3605 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
de4c7f65 3606 }
f5b4a52e
AD		 3607}
3608
477de6ed 3609static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3610{
9a799d71
AK		 3611 struct ixgbe_hw *hw = &adapter->hw;
3612 struct net_device *netdev = adapter->netdev;
3613 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3614 struct ixgbe_ring *rx_ring;
3615 int i;
3616 u32 mhadd, hlreg0;
48654521 3617
63f39bd1 3618#ifdef IXGBE_FCOE
477de6ed
AD		 3619 /* adjust max frame to be able to do baby jumbo for FCoE */
3620 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3621 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3622 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3623
477de6ed 3624#endif /* IXGBE_FCOE */
872844dd
AD		 3625
3626 /* adjust max frame to be at least the size of a standard frame */
3627 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3628 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3629
477de6ed
AD		 3630 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3631 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3632 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3633 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3634
3635 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3636 }
3637
3638 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3639 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3640 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3641 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3642
0cefafad
JB		 3643 /*
3644 * Setup the HW Rx Head and Tail Descriptor Pointers and
3645 * the Base and Length of the Rx Descriptor Ring
3646 */
9a799d71 3647 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3648 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3649 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3650 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3651 else
7d637bcc 3652 clear_ring_rsc_enabled(rx_ring);
477de6ed 3653 }
477de6ed
AD		 3654}
3655
7367096a
AD		 3656static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3657{
3658 struct ixgbe_hw *hw = &adapter->hw;
3659 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3660
3661 switch (hw->mac.type) {
9a75a1ac
DS		 3662 case ixgbe_mac_X550:
3663 case ixgbe_mac_X550EM_x:
7367096a
AD		 3664 case ixgbe_mac_82598EB:
3665 /*
3666 * For VMDq support of different descriptor types or
3667 * buffer sizes through the use of multiple SRRCTL
3668 * registers, RDRXCTL.MVMEN must be set to 1
3669 *
3670 * also, the manual doesn't mention it clearly but DCA hints
3671 * will only use queue 0's tags unless this bit is set. Side
3672 * effects of setting this bit are only that SRRCTL must be
3673 * fully programmed [0..15]
3674 */
3675 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3676 break;
3677 case ixgbe_mac_82599EB:
b93a2226 3678 case ixgbe_mac_X540:
7367096a
AD		 3679 /* Disable RSC for ACK packets */
3680 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3681 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3682 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3683 /* hardware requires some bits to be set by default */
3684 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3685 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3686 break;
3687 default:
3688 /* We should do nothing since we don't know this hardware */
3689 return;
3690 }
3691
3692 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3693}
3694
477de6ed
AD		 3695/**
3696 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3697 * @adapter: board private structure
3698 *
3699 * Configure the Rx unit of the MAC after a reset.
3700 **/
3701static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3702{
3703 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3704 int i;
6dcc28b9 3705 u32 rxctrl, rfctl;
477de6ed
AD		 3706
3707 /* disable receives while setting up the descriptors */
3708 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3709 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3710
3711 ixgbe_setup_psrtype(adapter);
7367096a 3712 ixgbe_setup_rdrxctl(adapter);
477de6ed 3713
6dcc28b9
JK		 3714 /* RSC Setup */
3715 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3716 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3717 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3718 rfctl |= IXGBE_RFCTL_RSC_DIS;
3719 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3720
9e10e045 3721 /* Program registers for the distribution of queues */
f5b4a52e 3722 ixgbe_setup_mrqc(adapter);
f5b4a52e 3723
477de6ed
AD		 3724 /* set_rx_buffer_len must be called before ring initialization */
3725 ixgbe_set_rx_buffer_len(adapter);
3726
3727 /*
3728 * Setup the HW Rx Head and Tail Descriptor Pointers and
3729 * the Base and Length of the Rx Descriptor Ring
3730 */
9e10e045
AD		 3731 for (i = 0; i < adapter->num_rx_queues; i++)
3732 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3733
9e10e045
AD		 3734 /* disable drop enable for 82598 parts */
3735 if (hw->mac.type == ixgbe_mac_82598EB)
3736 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3737
3738 /* enable all receives */
3739 rxctrl |= IXGBE_RXCTRL_RXEN;
3740 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3741}
3742
80d5c368
PM		 3743static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3744 __be16 proto, u16 vid)
068c89b0
DS		 3745{
3746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3747 struct ixgbe_hw *hw = &adapter->hw;
3748
3749 /* add VID to filter table */
1d9c0bfd 3750 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3751 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3752
3753 return 0;
068c89b0
DS		 3754}
3755
80d5c368
PM		 3756static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3757 __be16 proto, u16 vid)
068c89b0
DS		 3758{
3759 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3760 struct ixgbe_hw *hw = &adapter->hw;
3761
068c89b0 3762 /* remove VID from filter table */
1d9c0bfd 3763 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3764 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3765
3766 return 0;
068c89b0
DS		 3767}
3768
f62bbb5e
JG		 3769/**
3770 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3771 * @adapter: driver data
3772 */
3773static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3774{
3775 struct ixgbe_hw *hw = &adapter->hw;
3776 u32 vlnctrl;
5f6c0181
JB		 3777 int i, j;
3778
3779 switch (hw->mac.type) {
3780 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3781 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3782 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3783 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3784 break;
3785 case ixgbe_mac_82599EB:
b93a2226 3786 case ixgbe_mac_X540:
9a75a1ac
DS		 3787 case ixgbe_mac_X550:
3788 case ixgbe_mac_X550EM_x:
5f6c0181 3789 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3790 struct ixgbe_ring *ring = adapter->rx_ring[i];
3791
3792 if (ring->l2_accel_priv)
3793 continue;
3794 j = ring->reg_idx;
5f6c0181
JB		 3795 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3796 vlnctrl &= ~IXGBE_RXDCTL_VME;
3797 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3798 }
3799 break;
3800 default:
3801 break;
3802 }
3803}
3804
3805/**
f62bbb5e 3806 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3807 * @adapter: driver data
3808 */
f62bbb5e 3809static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3810{
3811 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3812 u32 vlnctrl;
5f6c0181
JB		 3813 int i, j;
3814
3815 switch (hw->mac.type) {
3816 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3817 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3818 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3819 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3820 break;
3821 case ixgbe_mac_82599EB:
b93a2226 3822 case ixgbe_mac_X540:
9a75a1ac
DS		 3823 case ixgbe_mac_X550:
3824 case ixgbe_mac_X550EM_x:
5f6c0181 3825 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3826 struct ixgbe_ring *ring = adapter->rx_ring[i];
3827
3828 if (ring->l2_accel_priv)
3829 continue;
3830 j = ring->reg_idx;
5f6c0181
JB		 3831 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3832 vlnctrl |= IXGBE_RXDCTL_VME;
3833 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3834 }
3835 break;
3836 default:
3837 break;
3838 }
3839}
3840
9a799d71
AK		 3841static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3842{
f62bbb5e 3843 u16 vid;
9a799d71 3844
80d5c368 3845 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3846
3847 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3848 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3849}
3850
b335e75b
JK		 3851/**
3852 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3853 * @netdev: network interface device structure
3854 *
3855 * Writes multicast address list to the MTA hash table.
3856 * Returns: -ENOMEM on failure
3857 * 0 on no addresses written
3858 * X on writing X addresses to MTA
3859 **/
3860static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3861{
3862 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3863 struct ixgbe_hw *hw = &adapter->hw;
3864
3865 if (!netif_running(netdev))
3866 return 0;
3867
3868 if (hw->mac.ops.update_mc_addr_list)
3869 hw->mac.ops.update_mc_addr_list(hw, netdev);
3870 else
3871 return -ENOMEM;
3872
3873#ifdef CONFIG_PCI_IOV
5d7daa35 3874 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3875#endif
3876
3877 return netdev_mc_count(netdev);
3878}
3879
5d7daa35
JK		 3880#ifdef CONFIG_PCI_IOV
3881void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3882{
3883 struct ixgbe_hw *hw = &adapter->hw;
3884 int i;
3885 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3886 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3887 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3888 adapter->mac_table[i].queue,
3889 IXGBE_RAH_AV);
3890 else
3891 hw->mac.ops.clear_rar(hw, i);
3892
3893 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3894 }
3895}
3896#endif
3897
3898static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3899{
3900 struct ixgbe_hw *hw = &adapter->hw;
3901 int i;
3902 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3903 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3904 if (adapter->mac_table[i].state &
3905 IXGBE_MAC_STATE_IN_USE)
3906 hw->mac.ops.set_rar(hw, i,
3907 adapter->mac_table[i].addr,
3908 adapter->mac_table[i].queue,
3909 IXGBE_RAH_AV);
3910 else
3911 hw->mac.ops.clear_rar(hw, i);
3912
3913 adapter->mac_table[i].state &=
3914 ~(IXGBE_MAC_STATE_MODIFIED);
3915 }
3916 }
3917}
3918
3919static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3920{
3921 int i;
3922 struct ixgbe_hw *hw = &adapter->hw;
3923
3924 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3925 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3926 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 3927 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 3928 adapter->mac_table[i].queue = 0;
3929 }
3930 ixgbe_sync_mac_table(adapter);
3931}
3932
3933static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3934{
3935 struct ixgbe_hw *hw = &adapter->hw;
3936 int i, count = 0;
3937
3938 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3939 if (adapter->mac_table[i].state == 0)
3940 count++;
3941 }
3942 return count;
3943}
3944
3945/* this function destroys the first RAR entry */
3946static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3947 u8 *addr)
3948{
3949 struct ixgbe_hw *hw = &adapter->hw;
3950
3951 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3952 adapter->mac_table[0].queue = VMDQ_P(0);
3953 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3954 IXGBE_MAC_STATE_IN_USE);
3955 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3956 adapter->mac_table[0].queue,
3957 IXGBE_RAH_AV);
3958}
3959
3960int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3961{
3962 struct ixgbe_hw *hw = &adapter->hw;
3963 int i;
3964
3965 if (is_zero_ether_addr(addr))
3966 return -EINVAL;
3967
3968 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3969 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3970 continue;
3971 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3972 IXGBE_MAC_STATE_IN_USE);
3973 ether_addr_copy(adapter->mac_table[i].addr, addr);
3974 adapter->mac_table[i].queue = queue;
3975 ixgbe_sync_mac_table(adapter);
3976 return i;
3977 }
3978 return -ENOMEM;
3979}
3980
3981int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3982{
3983 /* search table for addr, if found, set to 0 and sync */
3984 int i;
3985 struct ixgbe_hw *hw = &adapter->hw;
3986
3987 if (is_zero_ether_addr(addr))
3988 return -EINVAL;
3989
3990 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3991 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3992 adapter->mac_table[i].queue == queue) {
3993 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3994 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 3995 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 3996 adapter->mac_table[i].queue = 0;
3997 ixgbe_sync_mac_table(adapter);
3998 return 0;
3999 }
4000 }
4001 return -ENOMEM;
4002}
2850062a
AD		 4003/**
4004 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4005 * @netdev: network interface device structure
4006 *
4007 * Writes unicast address list to the RAR table.
4008 * Returns: -ENOMEM on failure/insufficient address space
4009 * 0 on no addresses written
4010 * X on writing X addresses to the RAR table
4011 **/
5d7daa35 4012static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4013{
4014 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4015 int count = 0;
4016
4017 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4018 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4019 return -ENOMEM;
4020
95447461 4021 if (!netdev_uc_empty(netdev)) {
2850062a 4022 struct netdev_hw_addr *ha;
2850062a 4023 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4024 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4025 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4026 count++;
4027 }
4028 }
2850062a
AD		 4029 return count;
4030}
4031
9a799d71 4032/**
2c5645cf 4033 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4034 * @netdev: network interface device structure
4035 *
2c5645cf
CL		 4036 * The set_rx_method entry point is called whenever the unicast/multicast
4037 * address list or the network interface flags are updated. This routine is
4038 * responsible for configuring the hardware for proper unicast, multicast and
4039 * promiscuous mode.
9a799d71 4040 **/
7f870475 4041void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4042{
4043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4044 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4045 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4046 u32 vlnctrl;
2850062a 4047 int count;
9a799d71
AK		 4048
4049 /* Check for Promiscuous and All Multicast modes */
9a799d71 4050 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4051 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4052
f5dc442b 4053 /* set all bits that we expect to always be set */
3f2d1c0f 4054 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4055 fctrl |= IXGBE_FCTRL_BAM;
4056 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4057 fctrl |= IXGBE_FCTRL_PMCF;
4058
2850062a
AD		 4059 /* clear the bits we are changing the status of */
4060 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4061 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4062 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4063 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4064 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4065 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4066 /* Only disable hardware filter vlans in promiscuous mode
4067 * if SR-IOV and VMDQ are disabled - otherwise ensure
4068 * that hardware VLAN filters remain enabled.
4069 */
4556dc59
VY		 4070 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4071 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4072 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4073 } else {
746b9f02
PM		 4074 if (netdev->flags & IFF_ALLMULTI) {
4075 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4076 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4077 }
a9b8943e 4078 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4079 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4080 }
4081
4082 /*
4083 * Write addresses to available RAR registers, if there is not
4084 * sufficient space to store all the addresses then enable
4085 * unicast promiscuous mode
4086 */
5d7daa35 4087 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4088 if (count < 0) {
4089 fctrl |= IXGBE_FCTRL_UPE;
4090 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4091 }
4092
cf78959c
ET		 4093 /* Write addresses to the MTA, if the attempt fails
4094 * then we should just turn on promiscuous mode so
4095 * that we can at least receive multicast traffic
4096 */
b335e75b
JK		 4097 count = ixgbe_write_mc_addr_list(netdev);
4098 if (count < 0) {
4099 fctrl |= IXGBE_FCTRL_MPE;
4100 vmolr |= IXGBE_VMOLR_MPE;
4101 } else if (count) {
4102 vmolr |= IXGBE_VMOLR_ROMPE;
4103 }
1d9c0bfd
AD		 4104
4105 if (hw->mac.type != ixgbe_mac_82598EB) {
4106 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4107 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4108 IXGBE_VMOLR_ROPE);
1d9c0bfd 4109 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4110 }
4111
3f2d1c0f
BG		 4112 /* This is useful for sniffing bad packets. */
4113 if (adapter->netdev->features & NETIF_F_RXALL) {
4114 /* UPE and MPE will be handled by normal PROMISC logic
4115 * in e1000e_set_rx_mode */
4116 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4117 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4118 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4119
4120 fctrl &= ~(IXGBE_FCTRL_DPF);
4121 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4122 }
4123
a9b8943e 4124 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4125 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4126
f646968f 4127 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4128 ixgbe_vlan_strip_enable(adapter);
4129 else
4130 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4131}
4132
021230d4
AV		 4133static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4134{
4135 int q_idx;
021230d4 4136
5a85e737
ET		 4137 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4138 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4139 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4140 }
021230d4
AV		 4141}
4142
4143static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4144{
4145 int q_idx;
021230d4 4146
5a85e737 4147 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4148 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4149 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4150 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4151 usleep_range(1000, 20000);
5a85e737
ET		 4152 }
4153 }
021230d4
AV		 4154}
4155
7a6b6f51 4156#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4157/**
2f90b865
AD		 4158 * ixgbe_configure_dcb - Configure DCB hardware
4159 * @adapter: ixgbe adapter struct
4160 *
4161 * This is called by the driver on open to configure the DCB hardware.
4162 * This is also called by the gennetlink interface when reconfiguring
4163 * the DCB state.
4164 */
4165static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4166{
4167 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4168 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4169
67ebd791
AD		 4170 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4171 if (hw->mac.type == ixgbe_mac_82598EB)
4172 netif_set_gso_max_size(adapter->netdev, 65536);
4173 return;
4174 }
4175
4176 if (hw->mac.type == ixgbe_mac_82598EB)
4177 netif_set_gso_max_size(adapter->netdev, 32768);
4178
971060b1 4179#ifdef IXGBE_FCOE
b120818e
JF		 4180 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4181 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4182#endif
b120818e
JF		 4183
4184 /* reconfigure the hardware */
4185 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4186 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4187 DCB_TX_CONFIG);
4188 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4189 DCB_RX_CONFIG);
4190 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4191 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4192 ixgbe_dcb_hw_ets(&adapter->hw,
4193 adapter->ixgbe_ieee_ets,
4194 max_frame);
4195 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4196 adapter->ixgbe_ieee_pfc->pfc_en,
4197 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4198 }
8187cd48
JF		 4199
4200 /* Enable RSS Hash per TC */
4201 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4202 u32 msb = 0;
4203 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4204
d411a936
AD		 4205 while (rss_i) {
4206 msb++;
4207 rss_i >>= 1;
4208 }
8187cd48 4209
4ae63730
AD		 4210 /* write msb to all 8 TCs in one write */
4211 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4212 }
2f90b865 4213}
9da712d2
JF		 4214#endif
4215
4216/* Additional bittime to account for IXGBE framing */
4217#define IXGBE_ETH_FRAMING 20
4218
49ce9c2c 4219/**
9da712d2
JF		 4220 * ixgbe_hpbthresh - calculate high water mark for flow control
4221 *
4222 * @adapter: board private structure to calculate for
49ce9c2c 4223 * @pb: packet buffer to calculate
9da712d2
JF		 4224 */
4225static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4226{
4227 struct ixgbe_hw *hw = &adapter->hw;
4228 struct net_device *dev = adapter->netdev;
4229 int link, tc, kb, marker;
4230 u32 dv_id, rx_pba;
4231
4232 /* Calculate max LAN frame size */
4233 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4234
4235#ifdef IXGBE_FCOE
4236 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4237 if ((dev->features & NETIF_F_FCOE_MTU) &&
4238 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4239 (pb == ixgbe_fcoe_get_tc(adapter)))
4240 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4241#endif
e5776620 4242
9da712d2
JF		 4243 /* Calculate delay value for device */
4244 switch (hw->mac.type) {
4245 case ixgbe_mac_X540:
9a75a1ac
DS		 4246 case ixgbe_mac_X550:
4247 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4248 dv_id = IXGBE_DV_X540(link, tc);
4249 break;
4250 default:
4251 dv_id = IXGBE_DV(link, tc);
4252 break;
4253 }
4254
4255 /* Loopback switch introduces additional latency */
4256 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4257 dv_id += IXGBE_B2BT(tc);
4258
4259 /* Delay value is calculated in bit times convert to KB */
4260 kb = IXGBE_BT2KB(dv_id);
4261 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4262
4263 marker = rx_pba - kb;
4264
4265 /* It is possible that the packet buffer is not large enough
4266 * to provide required headroom. In this case throw an error
4267 * to user and a do the best we can.
4268 */
4269 if (marker < 0) {
4270 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4271 "headroom to support flow control."
4272 "Decrease MTU or number of traffic classes\n", pb);
4273 marker = tc + 1;
4274 }
4275
4276 return marker;
4277}
4278
49ce9c2c 4279/**
9da712d2
JF		 4280 * ixgbe_lpbthresh - calculate low water mark for for flow control
4281 *
4282 * @adapter: board private structure to calculate for
49ce9c2c 4283 * @pb: packet buffer to calculate
9da712d2 4284 */
e5776620 4285static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4286{
4287 struct ixgbe_hw *hw = &adapter->hw;
4288 struct net_device *dev = adapter->netdev;
4289 int tc;
4290 u32 dv_id;
4291
4292 /* Calculate max LAN frame size */
4293 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4294
e5776620
JK		 4295#ifdef IXGBE_FCOE
4296 /* FCoE traffic class uses FCOE jumbo frames */
4297 if ((dev->features & NETIF_F_FCOE_MTU) &&
4298 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4299 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4300 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4301#endif
4302
9da712d2
JF		 4303 /* Calculate delay value for device */
4304 switch (hw->mac.type) {
4305 case ixgbe_mac_X540:
9a75a1ac
DS		 4306 case ixgbe_mac_X550:
4307 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4308 dv_id = IXGBE_LOW_DV_X540(tc);
4309 break;
4310 default:
4311 dv_id = IXGBE_LOW_DV(tc);
4312 break;
4313 }
4314
4315 /* Delay value is calculated in bit times convert to KB */
4316 return IXGBE_BT2KB(dv_id);
4317}
4318
4319/*
4320 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4321 */
4322static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4323{
4324 struct ixgbe_hw *hw = &adapter->hw;
4325 int num_tc = netdev_get_num_tc(adapter->netdev);
4326 int i;
4327
4328 if (!num_tc)
4329 num_tc = 1;
4330
9da712d2
JF		 4331 for (i = 0; i < num_tc; i++) {
4332 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4333 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4334
4335 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4336 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4337 hw->fc.low_water[i] = 0;
9da712d2 4338 }
e5776620
JK		 4339
4340 for (; i < MAX_TRAFFIC_CLASS; i++)
4341 hw->fc.high_water[i] = 0;
9da712d2
JF		 4342}
4343
80605c65
JF		 4344static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4345{
80605c65 4346 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4347 int hdrm;
4348 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4349
4350 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4351 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4352 hdrm = 32 << adapter->fdir_pballoc;
4353 else
4354 hdrm = 0;
80605c65 4355
f7e1027f 4356 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4357 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4358}
4359
e4911d57
AD		 4360static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4361{
4362 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4363 struct hlist_node *node2;
e4911d57
AD		 4364 struct ixgbe_fdir_filter *filter;
4365
4366 spin_lock(&adapter->fdir_perfect_lock);
4367
4368 if (!hlist_empty(&adapter->fdir_filter_list))
4369 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4370
b67bfe0d 4371 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4372 &adapter->fdir_filter_list, fdir_node) {
4373 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4374 &filter->filter,
4375 filter->sw_idx,
4376 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4377 IXGBE_FDIR_DROP_QUEUE :
4378 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4379 }
4380
4381 spin_unlock(&adapter->fdir_perfect_lock);
4382}
4383
2a47fa45
JF		 4384static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4385 struct ixgbe_adapter *adapter)
4386{
4387 struct ixgbe_hw *hw = &adapter->hw;
4388 u32 vmolr;
4389
4390 /* No unicast promiscuous support for VMDQ devices. */
4391 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4392 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4393
4394 /* clear the affected bit */
4395 vmolr &= ~IXGBE_VMOLR_MPE;
4396
4397 if (dev->flags & IFF_ALLMULTI) {
4398 vmolr |= IXGBE_VMOLR_MPE;
4399 } else {
4400 vmolr |= IXGBE_VMOLR_ROMPE;
4401 hw->mac.ops.update_mc_addr_list(hw, dev);
4402 }
5d7daa35 4403 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4404 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4405}
4406
2a47fa45
JF		 4407static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4408{
4409 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4410 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4411 struct ixgbe_hw *hw = &adapter->hw;
4412 u16 pool = vadapter->pool;
4413 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4414 IXGBE_PSRTYPE_UDPHDR |
4415 IXGBE_PSRTYPE_IPV4HDR |
4416 IXGBE_PSRTYPE_L2HDR |
4417 IXGBE_PSRTYPE_IPV6HDR;
4418
4419 if (hw->mac.type == ixgbe_mac_82598EB)
4420 return;
4421
4422 if (rss_i > 3)
4423 psrtype |= 2 << 29;
4424 else if (rss_i > 1)
4425 psrtype |= 1 << 29;
4426
4427 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4428}
4429
4430/**
4431 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4432 * @rx_ring: ring to free buffers from
4433 **/
4434static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4435{
4436 struct device *dev = rx_ring->dev;
4437 unsigned long size;
4438 u16 i;
4439
4440 /* ring already cleared, nothing to do */
4441 if (!rx_ring->rx_buffer_info)
4442 return;
4443
4444 /* Free all the Rx ring sk_buffs */
4445 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4446 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4447
2a47fa45
JF		 4448 if (rx_buffer->skb) {
4449 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4450 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4451 dma_unmap_page(dev,
4452 IXGBE_CB(skb)->dma,
4453 ixgbe_rx_bufsz(rx_ring),
4454 DMA_FROM_DEVICE);
2a47fa45 4455 dev_kfree_skb(skb);
4d2fcfbc 4456 rx_buffer->skb = NULL;
2a47fa45 4457 }
18cb652a
AD		 4458
4459 if (!rx_buffer->page)
4460 continue;
4461
4462 dma_unmap_page(dev, rx_buffer->dma,
4463 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4464 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4465
2a47fa45
JF		 4466 rx_buffer->page = NULL;
4467 }
4468
4469 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4470 memset(rx_ring->rx_buffer_info, 0, size);
4471
4472 /* Zero out the descriptor ring */
4473 memset(rx_ring->desc, 0, rx_ring->size);
4474
4475 rx_ring->next_to_alloc = 0;
4476 rx_ring->next_to_clean = 0;
4477 rx_ring->next_to_use = 0;
4478}
4479
4480static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4481 struct ixgbe_ring *rx_ring)
4482{
4483 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4484 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4485
4486 /* shutdown specific queue receive and wait for dma to settle */
4487 ixgbe_disable_rx_queue(adapter, rx_ring);
4488 usleep_range(10000, 20000);
4489 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4490 ixgbe_clean_rx_ring(rx_ring);
4491 rx_ring->l2_accel_priv = NULL;
4492}
4493
ae72c8d0
JF		 4494static int ixgbe_fwd_ring_down(struct net_device *vdev,
4495 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4496{
4497 struct ixgbe_adapter *adapter = accel->real_adapter;
4498 unsigned int rxbase = accel->rx_base_queue;
4499 unsigned int txbase = accel->tx_base_queue;
4500 int i;
4501
4502 netif_tx_stop_all_queues(vdev);
4503
4504 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4505 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4506 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4507 }
4508
4509 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4510 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4511 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4512 }
4513
4514
4515 return 0;
4516}
4517
4518static int ixgbe_fwd_ring_up(struct net_device *vdev,
4519 struct ixgbe_fwd_adapter *accel)
4520{
4521 struct ixgbe_adapter *adapter = accel->real_adapter;
4522 unsigned int rxbase, txbase, queues;
4523 int i, baseq, err = 0;
4524
4525 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4526 return 0;
4527
4528 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4529 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4530 accel->pool, adapter->num_rx_pools,
4531 baseq, baseq + adapter->num_rx_queues_per_pool,
4532 adapter->fwd_bitmask);
4533
4534 accel->netdev = vdev;
4535 accel->rx_base_queue = rxbase = baseq;
4536 accel->tx_base_queue = txbase = baseq;
4537
4538 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4539 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4540
4541 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4542 adapter->rx_ring[rxbase + i]->netdev = vdev;
4543 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4544 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4545 }
4546
4547 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4548 adapter->tx_ring[txbase + i]->netdev = vdev;
4549 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4550 }
4551
4552 queues = min_t(unsigned int,
4553 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4554 err = netif_set_real_num_tx_queues(vdev, queues);
4555 if (err)
4556 goto fwd_queue_err;
4557
2a47fa45
JF		 4558 err = netif_set_real_num_rx_queues(vdev, queues);
4559 if (err)
4560 goto fwd_queue_err;
4561
4562 if (is_valid_ether_addr(vdev->dev_addr))
4563 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4564
4565 ixgbe_fwd_psrtype(accel);
4566 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4567 return err;
4568fwd_queue_err:
4569 ixgbe_fwd_ring_down(vdev, accel);
4570 return err;
4571}
4572
4573static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4574{
4575 struct net_device *upper;
4576 struct list_head *iter;
4577 int err;
4578
4579 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4580 if (netif_is_macvlan(upper)) {
4581 struct macvlan_dev *dfwd = netdev_priv(upper);
4582 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4583
4584 if (dfwd->fwd_priv) {
4585 err = ixgbe_fwd_ring_up(upper, vadapter);
4586 if (err)
4587 continue;
4588 }
4589 }
4590 }
4591}
4592
9a799d71
AK		 4593static void ixgbe_configure(struct ixgbe_adapter *adapter)
4594{
d2f5e7f3
AS		 4595 struct ixgbe_hw *hw = &adapter->hw;
4596
80605c65 4597 ixgbe_configure_pb(adapter);
7a6b6f51 4598#ifdef CONFIG_IXGBE_DCB
67ebd791 4599 ixgbe_configure_dcb(adapter);
2f90b865 4600#endif
b35d4d42
AD		 4601 /*
4602 * We must restore virtualization before VLANs or else
4603 * the VLVF registers will not be populated
4604 */
4605 ixgbe_configure_virtualization(adapter);
9a799d71 4606
4c1d7b4b 4607 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4608 ixgbe_restore_vlan(adapter);
4609
d2f5e7f3
AS		 4610 switch (hw->mac.type) {
4611 case ixgbe_mac_82599EB:
4612 case ixgbe_mac_X540:
4613 hw->mac.ops.disable_rx_buff(hw);
4614 break;
4615 default:
4616 break;
4617 }
4618
c4cf55e5 4619 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4620 ixgbe_init_fdir_signature_82599(&adapter->hw,
4621 adapter->fdir_pballoc);
e4911d57
AD		 4622 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4623 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4624 adapter->fdir_pballoc);
4625 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4626 }
4c1d7b4b 4627
d2f5e7f3
AS		 4628 switch (hw->mac.type) {
4629 case ixgbe_mac_82599EB:
4630 case ixgbe_mac_X540:
4631 hw->mac.ops.enable_rx_buff(hw);
4632 break;
4633 default:
4634 break;
4635 }
4636
7c8ae65a
AD		 4637#ifdef IXGBE_FCOE
4638 /* configure FCoE L2 filters, redirection table, and Rx control */
4639 ixgbe_configure_fcoe(adapter);
4640
4641#endif /* IXGBE_FCOE */
9a799d71
AK		 4642 ixgbe_configure_tx(adapter);
4643 ixgbe_configure_rx(adapter);
2a47fa45 4644 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4645}
4646
e8e26350
PW		 4647static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4648{
4649 switch (hw->phy.type) {
4650 case ixgbe_phy_sfp_avago:
4651 case ixgbe_phy_sfp_ftl:
4652 case ixgbe_phy_sfp_intel:
4653 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4654 case ixgbe_phy_sfp_passive_tyco:
4655 case ixgbe_phy_sfp_passive_unknown:
4656 case ixgbe_phy_sfp_active_unknown:
4657 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4658 case ixgbe_phy_qsfp_passive_unknown:
4659 case ixgbe_phy_qsfp_active_unknown:
4660 case ixgbe_phy_qsfp_intel:
4661 case ixgbe_phy_qsfp_unknown:
d9cd46cd
ET		 4662 /* ixgbe_phy_none is set when no SFP module is present */
4663 case ixgbe_phy_none:
e8e26350 4664 return true;
8917b447
AD		 4665 case ixgbe_phy_nl:
4666 if (hw->mac.type == ixgbe_mac_82598EB)
4667 return true;
e8e26350
PW		 4668 default:
4669 return false;
4670 }
4671}
4672
0ecc061d 4673/**
e8e26350
PW		 4674 * ixgbe_sfp_link_config - set up SFP+ link
4675 * @adapter: pointer to private adapter struct
4676 **/
4677static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4678{
7086400d 4679 /*
52f33af8 4680 * We are assuming the worst case scenario here, and that
7086400d
AD		 4681 * is that an SFP was inserted/removed after the reset
4682 * but before SFP detection was enabled. As such the best
4683 * solution is to just start searching as soon as we start
4684 */
4685 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4686 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4687
7086400d 4688 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4689}
4690
4691/**
4692 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4693 * @hw: pointer to private hardware struct
4694 *
4695 * Returns 0 on success, negative on failure
4696 **/
e8e26350 4697static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4698{
3d292265
JH		 4699 u32 speed;
4700 bool autoneg, link_up = false;
0ecc061d
PWJ		 4701 u32 ret = IXGBE_ERR_LINK_SETUP;
4702
4703 if (hw->mac.ops.check_link)
3d292265 4704 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4705
4706 if (ret)
e90dd264 4707 return ret;
0ecc061d 4708
3d292265
JH		 4709 speed = hw->phy.autoneg_advertised;
4710 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4711 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4712 &autoneg);
0ecc061d 4713 if (ret)
e90dd264 4714 return ret;
0ecc061d 4715
8620a103 4716 if (hw->mac.ops.setup_link)
fd0326f2 4717 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4718
0ecc061d
PWJ		 4719 return ret;
4720}
4721
a34bcfff 4722static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4723{
9a799d71 4724 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4725 u32 gpie = 0;
9a799d71 4726
9b471446 4727 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4728 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4729 IXGBE_GPIE_OCD;
4730 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4731 /*
4732 * use EIAM to auto-mask when MSI-X interrupt is asserted
4733 * this saves a register write for every interrupt
4734 */
4735 switch (hw->mac.type) {
4736 case ixgbe_mac_82598EB:
4737 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4738 break;
9b471446 4739 case ixgbe_mac_82599EB:
b93a2226 4740 case ixgbe_mac_X540:
9a75a1ac
DS		 4741 case ixgbe_mac_X550:
4742 case ixgbe_mac_X550EM_x:
b93a2226 4743 default:
9b471446
JB		 4744 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4745 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4746 break;
4747 }
4748 } else {
021230d4
AV		 4749 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4750 * specifically only auto mask tx and rx interrupts */
4751 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4752 }
9a799d71 4753
a34bcfff
AD		 4754 /* XXX: to interrupt immediately for EICS writes, enable this */
4755 /* gpie |= IXGBE_GPIE_EIMEN; */
4756
4757 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4758 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4759
4760 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4761 case IXGBE_82599_VMDQ_8Q_MASK:
4762 gpie |= IXGBE_GPIE_VTMODE_16;
4763 break;
4764 case IXGBE_82599_VMDQ_4Q_MASK:
4765 gpie |= IXGBE_GPIE_VTMODE_32;
4766 break;
4767 default:
4768 gpie |= IXGBE_GPIE_VTMODE_64;
4769 break;
4770 }
119fc60a
MC		 4771 }
4772
5fdd31f9 4773 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4774 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4775 switch (adapter->hw.mac.type) {
4776 case ixgbe_mac_82599EB:
4777 gpie |= IXGBE_SDP0_GPIEN;
4778 break;
4779 case ixgbe_mac_X540:
4780 gpie |= IXGBE_EIMS_TS;
4781 break;
4782 default:
4783 break;
4784 }
4785 }
5fdd31f9 4786
a34bcfff
AD		 4787 /* Enable fan failure interrupt */
4788 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4789 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4790
2698b208 4791 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4792 gpie |= IXGBE_SDP1_GPIEN;
4793 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4794 }
a34bcfff
AD		 4795
4796 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4797}
4798
c7ccde0f 4799static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4800{
4801 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4802 int err;
a34bcfff
AD		 4803 u32 ctrl_ext;
4804
4805 ixgbe_get_hw_control(adapter);
4806 ixgbe_setup_gpie(adapter);
e8e26350 4807
9a799d71
AK		 4808 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4809 ixgbe_configure_msix(adapter);
4810 else
4811 ixgbe_configure_msi_and_legacy(adapter);
4812
ec74a471
ET		 4813 /* enable the optics for 82599 SFP+ fiber */
4814 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4815 hw->mac.ops.enable_tx_laser(hw);
4816
4e857c58 4817 smp_mb__before_atomic();
9a799d71 4818 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4819 ixgbe_napi_enable_all(adapter);
4820
73c4b7cd
AD		 4821 if (ixgbe_is_sfp(hw)) {
4822 ixgbe_sfp_link_config(adapter);
4823 } else {
4824 err = ixgbe_non_sfp_link_config(hw);
4825 if (err)
4826 e_err(probe, "link_config FAILED %d\n", err);
4827 }
4828
021230d4
AV		 4829 /* clear any pending interrupts, may auto mask */
4830 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4831 ixgbe_irq_enable(adapter, true, true);
9a799d71 4832
bf069c97
DS		 4833 /*
4834 * If this adapter has a fan, check to see if we had a failure
4835 * before we enabled the interrupt.
4836 */
4837 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4838 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4839 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4840 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4841 }
4842
9a799d71
AK		 4843 /* bring the link up in the watchdog, this could race with our first
4844 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4845 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4846 adapter->link_check_timeout = jiffies;
7086400d 4847 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4848
4849 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4850 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4851 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4852 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4853}
4854
d4f80882
AV		 4855void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4856{
4857 WARN_ON(in_interrupt());
7086400d
AD		 4858 /* put off any impending NetWatchDogTimeout */
4859 adapter->netdev->trans_start = jiffies;
4860
d4f80882 4861 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4862 usleep_range(1000, 2000);
d4f80882 4863 ixgbe_down(adapter);
5809a1ae
GR		 4864 /*
4865 * If SR-IOV enabled then wait a bit before bringing the adapter
4866 * back up to give the VFs time to respond to the reset. The
4867 * two second wait is based upon the watchdog timer cycle in
4868 * the VF driver.
4869 */
4870 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4871 msleep(2000);
d4f80882
AV		 4872 ixgbe_up(adapter);
4873 clear_bit(__IXGBE_RESETTING, &adapter->state);
4874}
4875
c7ccde0f 4876void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4877{
4878 /* hardware has been reset, we need to reload some things */
4879 ixgbe_configure(adapter);
4880
c7ccde0f 4881 ixgbe_up_complete(adapter);
9a799d71
AK		 4882}
4883
4884void ixgbe_reset(struct ixgbe_adapter *adapter)
4885{
c44ade9e 4886 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4887 struct net_device *netdev = adapter->netdev;
8ca783ab 4888 int err;
5d7daa35 4889 u8 old_addr[ETH_ALEN];
8ca783ab 4890
b0483c8f
MR		 4891 if (ixgbe_removed(hw->hw_addr))
4892 return;
7086400d
AD		 4893 /* lock SFP init bit to prevent race conditions with the watchdog */
4894 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4895 usleep_range(1000, 2000);
4896
4897 /* clear all SFP and link config related flags while holding SFP_INIT */
4898 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4899 IXGBE_FLAG2_SFP_NEEDS_RESET);
4900 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4901
8ca783ab 4902 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4903 switch (err) {
4904 case 0:
4905 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4906 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4907 break;
4908 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4909 e_dev_err("master disable timed out\n");
da4dd0f7 4910 break;
794caeb2
PWJ		 4911 case IXGBE_ERR_EEPROM_VERSION:
4912 /* We are running on a pre-production device, log a warning */
849c4542 4913 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4914 "Please be aware there may be issues associated with "
849c4542
ET		 4915 "your hardware. If you are experiencing problems "
4916 "please contact your Intel or hardware "
4917 "representative who provided you with this "
4918 "hardware.\n");
794caeb2 4919 break;
da4dd0f7 4920 default:
849c4542 4921 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4922 }
9a799d71 4923
7086400d 4924 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 4925 /* do not flush user set addresses */
4926 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4927 ixgbe_flush_sw_mac_table(adapter);
4928 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 4929
4930 /* update SAN MAC vmdq pool selection */
4931 if (hw->mac.san_mac_rar_index)
4932 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4933
8fecf67c 4934 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4935 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4936}
4937
9a799d71
AK		 4938/**
4939 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4940 * @tx_ring: ring to be cleaned
4941 **/
b6ec895e 4942static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4943{
4944 struct ixgbe_tx_buffer *tx_buffer_info;
4945 unsigned long size;
b6ec895e 4946 u16 i;
9a799d71 4947
84418e3b
AD		 4948 /* ring already cleared, nothing to do */
4949 if (!tx_ring->tx_buffer_info)
4950 return;
9a799d71 4951
84418e3b 4952 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4953 for (i = 0; i < tx_ring->count; i++) {
4954 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4955 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4956 }
4957
dad8a3b3
JF		 4958 netdev_tx_reset_queue(txring_txq(tx_ring));
4959
9a799d71
AK		 4960 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4961 memset(tx_ring->tx_buffer_info, 0, size);
4962
4963 /* Zero out the descriptor ring */
4964 memset(tx_ring->desc, 0, tx_ring->size);
4965
4966 tx_ring->next_to_use = 0;
4967 tx_ring->next_to_clean = 0;
9a799d71
AK		 4968}
4969
4970/**
021230d4 4971 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4972 * @adapter: board private structure
4973 **/
021230d4 4974static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4975{
4976 int i;
4977
021230d4 4978 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4979 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4980}
4981
4982/**
021230d4 4983 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4984 * @adapter: board private structure
4985 **/
021230d4 4986static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4987{
4988 int i;
4989
021230d4 4990 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4991 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4992}
4993
e4911d57
AD		 4994static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4995{
b67bfe0d 4996 struct hlist_node *node2;
e4911d57
AD		 4997 struct ixgbe_fdir_filter *filter;
4998
4999 spin_lock(&adapter->fdir_perfect_lock);
5000
b67bfe0d 5001 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5002 &adapter->fdir_filter_list, fdir_node) {
5003 hlist_del(&filter->fdir_node);
5004 kfree(filter);
5005 }
5006 adapter->fdir_filter_count = 0;
5007
5008 spin_unlock(&adapter->fdir_perfect_lock);
5009}
5010
9a799d71
AK		 5011void ixgbe_down(struct ixgbe_adapter *adapter)
5012{
5013 struct net_device *netdev = adapter->netdev;
7f821875 5014 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5015 struct net_device *upper;
5016 struct list_head *iter;
9a799d71 5017 u32 rxctrl;
bf29ee6c 5018 int i;
9a799d71
AK		 5019
5020 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5021 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5022 return; /* do nothing if already down */
9a799d71
AK		 5023
5024 /* disable receives */
7f821875
JB		 5025 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5026 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 5027
2d39d576
YZ		 5028 /* disable all enabled rx queues */
5029 for (i = 0; i < adapter->num_rx_queues; i++)
5030 /* this call also flushes the previous write */
5031 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5032
032b4325 5033 usleep_range(10000, 20000);
9a799d71 5034
7f821875
JB		 5035 netif_tx_stop_all_queues(netdev);
5036
7086400d 5037 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5038 netif_carrier_off(netdev);
5039 netif_tx_disable(netdev);
5040
2a47fa45
JF		 5041 /* disable any upper devices */
5042 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5043 if (netif_is_macvlan(upper)) {
5044 struct macvlan_dev *vlan = netdev_priv(upper);
5045
5046 if (vlan->fwd_priv) {
5047 netif_tx_stop_all_queues(upper);
5048 netif_carrier_off(upper);
5049 netif_tx_disable(upper);
5050 }
5051 }
5052 }
5053
c0dfb90e
JF		 5054 ixgbe_irq_disable(adapter);
5055
5056 ixgbe_napi_disable_all(adapter);
5057
d034acf1
AD		 5058 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5059 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5060 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5061
5062 del_timer_sync(&adapter->service_timer);
5063
34cecbbf 5064 if (adapter->num_vfs) {
8e34d1aa
AD		 5065 /* Clear EITR Select mapping */
5066 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5067
5068 /* Mark all the VFs as inactive */
5069 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5070 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5071
34cecbbf
AD		 5072 /* ping all the active vfs to let them know we are going down */
5073 ixgbe_ping_all_vfs(adapter);
5074
5075 /* Disable all VFTE/VFRE TX/RX */
5076 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5077 }
5078
7f821875
JB		 5079 /* disable transmits in the hardware now that interrupts are off */
5080 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5081 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5082 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5083 }
34cecbbf 5084
9a75a1ac 5085 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5086 switch (hw->mac.type) {
5087 case ixgbe_mac_82599EB:
b93a2226 5088 case ixgbe_mac_X540:
9a75a1ac
DS		 5089 case ixgbe_mac_X550:
5090 case ixgbe_mac_X550EM_x:
88512539 5091 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5092 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5093 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5094 break;
5095 default:
5096 break;
5097 }
7f821875 5098
6f4a0e45
PL		 5099 if (!pci_channel_offline(adapter->pdev))
5100 ixgbe_reset(adapter);
c6ecf39a 5101
ec74a471
ET		 5102 /* power down the optics for 82599 SFP+ fiber */
5103 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5104 hw->mac.ops.disable_tx_laser(hw);
5105
9a799d71
AK		 5106 ixgbe_clean_all_tx_rings(adapter);
5107 ixgbe_clean_all_rx_rings(adapter);
5108
5dd2d332 5109#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5110 /* since we reset the hardware DCA settings were cleared */
e35ec126 5111 ixgbe_setup_dca(adapter);
96b0e0f6 5112#endif
9a799d71
AK		 5113}
5114
9a799d71
AK		 5115/**
5116 * ixgbe_tx_timeout - Respond to a Tx Hang
5117 * @netdev: network interface device structure
5118 **/
5119static void ixgbe_tx_timeout(struct net_device *netdev)
5120{
5121 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5122
5123 /* Do the reset outside of interrupt context */
c83c6cbd 5124 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5125}
5126
9a799d71
AK		 5127/**
5128 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5129 * @adapter: board private structure to initialize
5130 *
5131 * ixgbe_sw_init initializes the Adapter private data structure.
5132 * Fields are initialized based on PCI device information and
5133 * OS network device settings (MTU size).
5134 **/
9f9a12f8 5135static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5136{
5137 struct ixgbe_hw *hw = &adapter->hw;
5138 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5139 unsigned int rss, fdir;
cb6d0f5e 5140 u32 fwsm;
7a6b6f51 5141#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5142 int j;
5143 struct tc_configuration *tc;
5144#endif
021230d4 5145
c44ade9e
JB		 5146 /* PCI config space info */
5147
5148 hw->vendor_id = pdev->vendor;
5149 hw->device_id = pdev->device;
5150 hw->revision_id = pdev->revision;
5151 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5152 hw->subsystem_device_id = pdev->subsystem_device;
5153
8fc3bb6d 5154 /* Set common capability flags and settings */
0f9b232b 5155 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5156 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5157 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5158 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5159 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5160 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5161 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5162 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5163 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5164#ifdef CONFIG_IXGBE_DCA
5165 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5166#endif
5167#ifdef IXGBE_FCOE
5168 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5169 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5170#ifdef CONFIG_IXGBE_DCB
5171 /* Default traffic class to use for FCoE */
5172 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5173#endif /* CONFIG_IXGBE_DCB */
5174#endif /* IXGBE_FCOE */
5175
5d7daa35
JK		 5176 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5177 hw->mac.num_rar_entries,
5178 GFP_ATOMIC);
5179
8fc3bb6d 5180 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5181 switch (hw->mac.type) {
5182 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5183 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5184 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5185
bf069c97
DS		 5186 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5187 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5188
49c7ffbe 5189 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5190 adapter->ring_feature[RING_F_FDIR].limit = 0;
5191 adapter->atr_sample_rate = 0;
5192 adapter->fdir_pballoc = 0;
5193#ifdef IXGBE_FCOE
5194 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5195 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5196#ifdef CONFIG_IXGBE_DCB
5197 adapter->fcoe.up = 0;
5198#endif /* IXGBE_DCB */
5199#endif /* IXGBE_FCOE */
5200 break;
5201 case ixgbe_mac_82599EB:
5202 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5203 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5204 break;
b93a2226 5205 case ixgbe_mac_X540:
cb6d0f5e
JK		 5206 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5207 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5208 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5209 break;
9a75a1ac
DS		 5210 case ixgbe_mac_X550EM_x:
5211 case ixgbe_mac_X550:
5212#ifdef CONFIG_IXGBE_DCA
5213 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5214#endif
5215 break;
bd508178
AD		 5216 default:
5217 break;
f8212f97 5218 }
2f90b865 5219
7c8ae65a
AD		 5220#ifdef IXGBE_FCOE
5221 /* FCoE support exists, always init the FCoE lock */
5222 spin_lock_init(&adapter->fcoe.lock);
5223
5224#endif
1fc5f038
AD		 5225 /* n-tuple support exists, always init our spinlock */
5226 spin_lock_init(&adapter->fdir_perfect_lock);
5227
7a6b6f51 5228#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5229 switch (hw->mac.type) {
5230 case ixgbe_mac_X540:
9a75a1ac
DS		 5231 case ixgbe_mac_X550:
5232 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5233 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5234 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5235 break;
5236 default:
5237 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5238 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5239 break;
5240 }
5241
2f90b865
AD		 5242 /* Configure DCB traffic classes */
5243 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5244 tc = &adapter->dcb_cfg.tc_config[j];
5245 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5246 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5247 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5248 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5249 tc->dcb_pfc = pfc_disabled;
5250 }
4de2a022
JF		 5251
5252 /* Initialize default user to priority mapping, UPx->TC0 */
5253 tc = &adapter->dcb_cfg.tc_config[0];
5254 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5255 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5256
2f90b865
AD		 5257 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5258 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5259 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5260 adapter->dcb_set_bitmap = 0x00;
3032309b 5261 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5262 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5263 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5264
5265#endif
9a799d71
AK		 5266
5267 /* default flow control settings */
cd7664f6 5268 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5269 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5270 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5271 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5272 hw->fc.send_xon = true;
73d80953 5273 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5274
99d74487 5275#ifdef CONFIG_PCI_IOV
170e8543
JK		 5276 if (max_vfs > 0)
5277 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5278
99d74487 5279 /* assign number of SR-IOV VFs */
170e8543 5280 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5281 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5282 adapter->num_vfs = 0;
5283 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5284 } else {
5285 adapter->num_vfs = max_vfs;
5286 }
5287 }
5288#endif /* CONFIG_PCI_IOV */
99d74487 5289
30efa5a3 5290 /* enable itr by default in dynamic mode */
f7554a2b 5291 adapter->rx_itr_setting = 1;
f7554a2b 5292 adapter->tx_itr_setting = 1;
30efa5a3 5293
30efa5a3
JB		 5294 /* set default ring sizes */
5295 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5296 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5297
bd198058 5298 /* set default work limits */
59224555 5299 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5300
9a799d71 5301 /* initialize eeprom parameters */
c44ade9e 5302 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5303 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5304 return -EIO;
5305 }
5306
2a47fa45
JF		 5307 /* PF holds first pool slot */
5308 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5309 set_bit(__IXGBE_DOWN, &adapter->state);
5310
5311 return 0;
5312}
5313
5314/**
5315 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5316 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5317 *
5318 * Return 0 on success, negative on failure
5319 **/
b6ec895e 5320int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5321{
b6ec895e 5322 struct device *dev = tx_ring->dev;
de88eeeb 5323 int orig_node = dev_to_node(dev);
ca8dfe25 5324 int ring_node = -1;
9a799d71
AK		 5325 int size;
5326
3a581073 5327 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5328
5329 if (tx_ring->q_vector)
ca8dfe25 5330 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5331
ca8dfe25 5332 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5333 if (!tx_ring->tx_buffer_info)
89bf67f1 5334 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5335 if (!tx_ring->tx_buffer_info)
5336 goto err;
9a799d71 5337
827da44c
JS		 5338 u64_stats_init(&tx_ring->syncp);
5339
9a799d71 5340 /* round up to nearest 4K */
12207e49 5341 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5342 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5343
ca8dfe25 5344 set_dev_node(dev, ring_node);
de88eeeb
AD		 5345 tx_ring->desc = dma_alloc_coherent(dev,
5346 tx_ring->size,
5347 &tx_ring->dma,
5348 GFP_KERNEL);
5349 set_dev_node(dev, orig_node);
5350 if (!tx_ring->desc)
5351 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5352 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5353 if (!tx_ring->desc)
5354 goto err;
9a799d71 5355
3a581073
JB		 5356 tx_ring->next_to_use = 0;
5357 tx_ring->next_to_clean = 0;
9a799d71 5358 return 0;
e01c31a5
JB		 5359
5360err:
5361 vfree(tx_ring->tx_buffer_info);
5362 tx_ring->tx_buffer_info = NULL;
b6ec895e 5363 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5364 return -ENOMEM;
9a799d71
AK		 5365}
5366
69888674
AD		 5367/**
5368 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5369 * @adapter: board private structure
5370 *
5371 * If this function returns with an error, then it's possible one or
5372 * more of the rings is populated (while the rest are not). It is the
5373 * callers duty to clean those orphaned rings.
5374 *
5375 * Return 0 on success, negative on failure
5376 **/
5377static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5378{
5379 int i, err = 0;
5380
5381 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5382 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5383 if (!err)
5384 continue;
de3d5b94 5385
396e799c 5386 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5387 goto err_setup_tx;
69888674
AD		 5388 }
5389
de3d5b94
AD		 5390 return 0;
5391err_setup_tx:
5392 /* rewind the index freeing the rings as we go */
5393 while (i--)
5394 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5395 return err;
5396}
5397
9a799d71
AK		 5398/**
5399 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5400 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5401 *
5402 * Returns 0 on success, negative on failure
5403 **/
b6ec895e 5404int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5405{
b6ec895e 5406 struct device *dev = rx_ring->dev;
de88eeeb 5407 int orig_node = dev_to_node(dev);
ca8dfe25 5408 int ring_node = -1;
021230d4 5409 int size;
9a799d71 5410
3a581073 5411 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5412
5413 if (rx_ring->q_vector)
ca8dfe25 5414 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5415
ca8dfe25 5416 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5417 if (!rx_ring->rx_buffer_info)
89bf67f1 5418 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5419 if (!rx_ring->rx_buffer_info)
5420 goto err;
9a799d71 5421
827da44c
JS		 5422 u64_stats_init(&rx_ring->syncp);
5423
9a799d71 5424 /* Round up to nearest 4K */
3a581073
JB		 5425 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5426 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5427
ca8dfe25 5428 set_dev_node(dev, ring_node);
de88eeeb
AD		 5429 rx_ring->desc = dma_alloc_coherent(dev,
5430 rx_ring->size,
5431 &rx_ring->dma,
5432 GFP_KERNEL);
5433 set_dev_node(dev, orig_node);
5434 if (!rx_ring->desc)
5435 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5436 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5437 if (!rx_ring->desc)
5438 goto err;
9a799d71 5439
3a581073
JB		 5440 rx_ring->next_to_clean = 0;
5441 rx_ring->next_to_use = 0;
9a799d71
AK		 5442
5443 return 0;
b6ec895e
AD		 5444err:
5445 vfree(rx_ring->rx_buffer_info);
5446 rx_ring->rx_buffer_info = NULL;
5447 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5448 return -ENOMEM;
9a799d71
AK		 5449}
5450
69888674
AD		 5451/**
5452 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5453 * @adapter: board private structure
5454 *
5455 * If this function returns with an error, then it's possible one or
5456 * more of the rings is populated (while the rest are not). It is the
5457 * callers duty to clean those orphaned rings.
5458 *
5459 * Return 0 on success, negative on failure
5460 **/
69888674
AD		 5461static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5462{
5463 int i, err = 0;
5464
5465 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5466 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5467 if (!err)
5468 continue;
de3d5b94 5469
396e799c 5470 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5471 goto err_setup_rx;
69888674
AD		 5472 }
5473
7c8ae65a
AD		 5474#ifdef IXGBE_FCOE
5475 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5476 if (!err)
5477#endif
5478 return 0;
de3d5b94
AD		 5479err_setup_rx:
5480 /* rewind the index freeing the rings as we go */
5481 while (i--)
5482 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5483 return err;
5484}
5485
9a799d71
AK		 5486/**
5487 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5488 * @tx_ring: Tx descriptor ring for a specific queue
5489 *
5490 * Free all transmit software resources
5491 **/
b6ec895e 5492void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5493{
b6ec895e 5494 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5495
5496 vfree(tx_ring->tx_buffer_info);
5497 tx_ring->tx_buffer_info = NULL;
5498
b6ec895e
AD		 5499 /* if not set, then don't free */
5500 if (!tx_ring->desc)
5501 return;
5502
5503 dma_free_coherent(tx_ring->dev, tx_ring->size,
5504 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5505
5506 tx_ring->desc = NULL;
5507}
5508
5509/**
5510 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5511 * @adapter: board private structure
5512 *
5513 * Free all transmit software resources
5514 **/
5515static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5516{
5517 int i;
5518
5519 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5520 if (adapter->tx_ring[i]->desc)
b6ec895e 5521 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5522}
5523
5524/**
b4617240 5525 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5526 * @rx_ring: ring to clean the resources from
5527 *
5528 * Free all receive software resources
5529 **/
b6ec895e 5530void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5531{
b6ec895e 5532 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5533
5534 vfree(rx_ring->rx_buffer_info);
5535 rx_ring->rx_buffer_info = NULL;
5536
b6ec895e
AD		 5537 /* if not set, then don't free */
5538 if (!rx_ring->desc)
5539 return;
5540
5541 dma_free_coherent(rx_ring->dev, rx_ring->size,
5542 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5543
5544 rx_ring->desc = NULL;
5545}
5546
5547/**
5548 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5549 * @adapter: board private structure
5550 *
5551 * Free all receive software resources
5552 **/
5553static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5554{
5555 int i;
5556
7c8ae65a
AD		 5557#ifdef IXGBE_FCOE
5558 ixgbe_free_fcoe_ddp_resources(adapter);
5559
5560#endif
9a799d71 5561 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5562 if (adapter->rx_ring[i]->desc)
b6ec895e 5563 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5564}
5565
9a799d71
AK		 5566/**
5567 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5568 * @netdev: network interface device structure
5569 * @new_mtu: new value for maximum frame size
5570 *
5571 * Returns 0 on success, negative on failure
5572 **/
5573static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5574{
5575 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5576 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5577
42c783c5 5578 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5579 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5580 return -EINVAL;
5581
5582 /*
872844dd
AD		 5583 * For 82599EB we cannot allow legacy VFs to enable their receive
5584 * paths when MTU greater than 1500 is configured. So display a
5585 * warning that legacy VFs will be disabled.
655309e9
AD		 5586 */
5587 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5588 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5589 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5590 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5591
396e799c 5592 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5593
021230d4 5594 /* must set new MTU before calling down or up */
9a799d71
AK		 5595 netdev->mtu = new_mtu;
5596
d4f80882
AV		 5597 if (netif_running(netdev))
5598 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5599
5600 return 0;
5601}
5602
5603/**
5604 * ixgbe_open - Called when a network interface is made active
5605 * @netdev: network interface device structure
5606 *
5607 * Returns 0 on success, negative value on failure
5608 *
5609 * The open entry point is called when a network interface is made
5610 * active by the system (IFF_UP). At this point all resources needed
5611 * for transmit and receive operations are allocated, the interrupt
5612 * handler is registered with the OS, the watchdog timer is started,
5613 * and the stack is notified that the interface is ready.
5614 **/
5615static int ixgbe_open(struct net_device *netdev)
5616{
5617 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5618 int err, queues;
4bebfaa5
AK		 5619
5620 /* disallow open during test */
5621 if (test_bit(__IXGBE_TESTING, &adapter->state))
5622 return -EBUSY;
9a799d71 5623
54386467
JB		 5624 netif_carrier_off(netdev);
5625
9a799d71
AK		 5626 /* allocate transmit descriptors */
5627 err = ixgbe_setup_all_tx_resources(adapter);
5628 if (err)
5629 goto err_setup_tx;
5630
9a799d71
AK		 5631 /* allocate receive descriptors */
5632 err = ixgbe_setup_all_rx_resources(adapter);
5633 if (err)
5634 goto err_setup_rx;
5635
5636 ixgbe_configure(adapter);
5637
021230d4 5638 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5639 if (err)
5640 goto err_req_irq;
5641
ac802f5d 5642 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5643 if (adapter->num_rx_pools > 1)
5644 queues = adapter->num_rx_queues_per_pool;
5645 else
5646 queues = adapter->num_tx_queues;
5647
5648 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5649 if (err)
5650 goto err_set_queues;
5651
2a47fa45
JF		 5652 if (adapter->num_rx_pools > 1 &&
5653 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5654 queues = IXGBE_MAX_L2A_QUEUES;
5655 else
5656 queues = adapter->num_rx_queues;
5657 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5658 if (err)
5659 goto err_set_queues;
5660
1a71ab24 5661 ixgbe_ptp_init(adapter);
1a71ab24 5662
c7ccde0f 5663 ixgbe_up_complete(adapter);
9a799d71 5664
3f207800
DS		 5665#if IS_ENABLED(CONFIG_IXGBE_VXLAN)
5666 vxlan_get_rx_port(netdev);
5667
5668#endif
9a799d71
AK		 5669 return 0;
5670
ac802f5d
AD		 5671err_set_queues:
5672 ixgbe_free_irq(adapter);
9a799d71 5673err_req_irq:
a20a1199 5674 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5675err_setup_rx:
a20a1199 5676 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5677err_setup_tx:
9a799d71
AK		 5678 ixgbe_reset(adapter);
5679
5680 return err;
5681}
5682
a0cccce2
JK		 5683static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5684{
5685 ixgbe_ptp_suspend(adapter);
5686
5687 ixgbe_down(adapter);
5688 ixgbe_free_irq(adapter);
5689
5690 ixgbe_free_all_tx_resources(adapter);
5691 ixgbe_free_all_rx_resources(adapter);
5692}
5693
9a799d71
AK		 5694/**
5695 * ixgbe_close - Disables a network interface
5696 * @netdev: network interface device structure
5697 *
5698 * Returns 0, this is not allowed to fail
5699 *
5700 * The close entry point is called when an interface is de-activated
5701 * by the OS. The hardware is still under the drivers control, but
5702 * needs to be disabled. A global MAC reset is issued to stop the
5703 * hardware, and all transmit and receive resources are freed.
5704 **/
5705static int ixgbe_close(struct net_device *netdev)
5706{
5707 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5708
1a71ab24 5709 ixgbe_ptp_stop(adapter);
1a71ab24 5710
a0cccce2 5711 ixgbe_close_suspend(adapter);
9a799d71 5712
e4911d57
AD		 5713 ixgbe_fdir_filter_exit(adapter);
5714
5eba3699 5715 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5716
5717 return 0;
5718}
5719
b3c8b4ba
AD		 5720#ifdef CONFIG_PM
5721static int ixgbe_resume(struct pci_dev *pdev)
5722{
c60fbb00
AD		 5723 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5724 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5725 u32 err;
5726
0391bbe3 5727 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5728 pci_set_power_state(pdev, PCI_D0);
5729 pci_restore_state(pdev);
656ab817
DS		 5730 /*
5731 * pci_restore_state clears dev->state_saved so call
5732 * pci_save_state to restore it.
5733 */
5734 pci_save_state(pdev);
9ce77666 5735
5736 err = pci_enable_device_mem(pdev);
b3c8b4ba 5737 if (err) {
849c4542 5738 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5739 return err;
5740 }
4e857c58 5741 smp_mb__before_atomic();
41c62843 5742 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5743 pci_set_master(pdev);
5744
dd4d8ca6 5745 pci_wake_from_d3(pdev, false);
b3c8b4ba 5746
b3c8b4ba
AD		 5747 ixgbe_reset(adapter);
5748
495dce12
WJP		 5749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5750
ac802f5d
AD		 5751 rtnl_lock();
5752 err = ixgbe_init_interrupt_scheme(adapter);
5753 if (!err && netif_running(netdev))
c60fbb00 5754 err = ixgbe_open(netdev);
ac802f5d
AD		 5755
5756 rtnl_unlock();
5757
5758 if (err)
5759 return err;
b3c8b4ba
AD		 5760
5761 netif_device_attach(netdev);
5762
5763 return 0;
5764}
b3c8b4ba 5765#endif /* CONFIG_PM */
9d8d05ae
RW		 5766
5767static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5768{
c60fbb00
AD		 5769 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5770 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5771 struct ixgbe_hw *hw = &adapter->hw;
5772 u32 ctrl, fctrl;
5773 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5774#ifdef CONFIG_PM
5775 int retval = 0;
5776#endif
5777
5778 netif_device_detach(netdev);
5779
499ab5cc 5780 rtnl_lock();
a0cccce2
JK		 5781 if (netif_running(netdev))
5782 ixgbe_close_suspend(adapter);
499ab5cc 5783 rtnl_unlock();
b3c8b4ba 5784
5f5ae6fc
AD		 5785 ixgbe_clear_interrupt_scheme(adapter);
5786
b3c8b4ba
AD		 5787#ifdef CONFIG_PM
5788 retval = pci_save_state(pdev);
5789 if (retval)
5790 return retval;
4df10466 5791
b3c8b4ba 5792#endif
f4f1040a
JK		 5793 if (hw->mac.ops.stop_link_on_d3)
5794 hw->mac.ops.stop_link_on_d3(hw);
5795
e8e26350
PW		 5796 if (wufc) {
5797 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5798
ec74a471
ET		 5799 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5800 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5801 hw->mac.ops.enable_tx_laser(hw);
5802
e8e26350
PW		 5803 /* turn on all-multi mode if wake on multicast is enabled */
5804 if (wufc & IXGBE_WUFC_MC) {
5805 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5806 fctrl |= IXGBE_FCTRL_MPE;
5807 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5808 }
5809
5810 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5811 ctrl |= IXGBE_CTRL_GIO_DIS;
5812 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5813
5814 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5815 } else {
5816 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5817 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5818 }
5819
bd508178
AD		 5820 switch (hw->mac.type) {
5821 case ixgbe_mac_82598EB:
dd4d8ca6 5822 pci_wake_from_d3(pdev, false);
bd508178
AD		 5823 break;
5824 case ixgbe_mac_82599EB:
b93a2226 5825 case ixgbe_mac_X540:
9a75a1ac
DS		 5826 case ixgbe_mac_X550:
5827 case ixgbe_mac_X550EM_x:
bd508178
AD		 5828 pci_wake_from_d3(pdev, !!wufc);
5829 break;
5830 default:
5831 break;
5832 }
b3c8b4ba 5833
9d8d05ae
RW		 5834 *enable_wake = !!wufc;
5835
b3c8b4ba
AD		 5836 ixgbe_release_hw_control(adapter);
5837
41c62843
MR		 5838 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5839 pci_disable_device(pdev);
b3c8b4ba 5840
9d8d05ae
RW		 5841 return 0;
5842}
5843
5844#ifdef CONFIG_PM
5845static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5846{
5847 int retval;
5848 bool wake;
5849
5850 retval = __ixgbe_shutdown(pdev, &wake);
5851 if (retval)
5852 return retval;
5853
5854 if (wake) {
5855 pci_prepare_to_sleep(pdev);
5856 } else {
5857 pci_wake_from_d3(pdev, false);
5858 pci_set_power_state(pdev, PCI_D3hot);
5859 }
b3c8b4ba
AD		 5860
5861 return 0;
5862}
9d8d05ae 5863#endif /* CONFIG_PM */
b3c8b4ba
AD		 5864
5865static void ixgbe_shutdown(struct pci_dev *pdev)
5866{
9d8d05ae
RW		 5867 bool wake;
5868
5869 __ixgbe_shutdown(pdev, &wake);
5870
5871 if (system_state == SYSTEM_POWER_OFF) {
5872 pci_wake_from_d3(pdev, wake);
5873 pci_set_power_state(pdev, PCI_D3hot);
5874 }
b3c8b4ba
AD		 5875}
5876
9a799d71
AK		 5877/**
5878 * ixgbe_update_stats - Update the board statistics counters.
5879 * @adapter: board private structure
5880 **/
5881void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5882{
2d86f139 5883 struct net_device *netdev = adapter->netdev;
9a799d71 5884 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5885 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5886 u64 total_mpc = 0;
5887 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5888 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5889 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5890 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5891
d08935c2
DS		 5892 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5893 test_bit(__IXGBE_RESETTING, &adapter->state))
5894 return;
5895
94b982b2 5896 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5897 u64 rsc_count = 0;
94b982b2 5898 u64 rsc_flush = 0;
94b982b2 5899 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5900 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5901 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5902 }
5903 adapter->rsc_total_count = rsc_count;
5904 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5905 }
5906
5b7da515
AD		 5907 for (i = 0; i < adapter->num_rx_queues; i++) {
5908 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5909 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5910 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5911 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5912 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5913 bytes += rx_ring->stats.bytes;
5914 packets += rx_ring->stats.packets;
5915 }
5916 adapter->non_eop_descs = non_eop_descs;
5917 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5918 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5919 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5920 netdev->stats.rx_bytes = bytes;
5921 netdev->stats.rx_packets = packets;
5922
5923 bytes = 0;
5924 packets = 0;
7ca3bc58 5925 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5926 for (i = 0; i < adapter->num_tx_queues; i++) {
5927 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5928 restart_queue += tx_ring->tx_stats.restart_queue;
5929 tx_busy += tx_ring->tx_stats.tx_busy;
5930 bytes += tx_ring->stats.bytes;
5931 packets += tx_ring->stats.packets;
5932 }
eb985f09 5933 adapter->restart_queue = restart_queue;
5b7da515
AD		 5934 adapter->tx_busy = tx_busy;
5935 netdev->stats.tx_bytes = bytes;
5936 netdev->stats.tx_packets = packets;
7ca3bc58 5937
7ca647bd 5938 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5939
5940 /* 8 register reads */
6f11eef7
AV		 5941 for (i = 0; i < 8; i++) {
5942 /* for packet buffers not used, the register should read 0 */
5943 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5944 missed_rx += mpc;
7ca647bd
JP		 5945 hwstats->mpc[i] += mpc;
5946 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5947 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5948 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5949 switch (hw->mac.type) {
5950 case ixgbe_mac_82598EB:
1a70db4b
ET		 5951 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5952 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5953 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5954 hwstats->pxonrxc[i] +=
5955 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5956 break;
5957 case ixgbe_mac_82599EB:
b93a2226 5958 case ixgbe_mac_X540:
9a75a1ac
DS		 5959 case ixgbe_mac_X550:
5960 case ixgbe_mac_X550EM_x:
bd508178
AD		 5961 hwstats->pxonrxc[i] +=
5962 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5963 break;
5964 default:
5965 break;
e8e26350 5966 }
6f11eef7 5967 }
1a70db4b
ET		 5968
5969 /*16 register reads */
5970 for (i = 0; i < 16; i++) {
5971 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5972 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5973 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 5974 (hw->mac.type == ixgbe_mac_X540) ||
5975 (hw->mac.type == ixgbe_mac_X550) ||
5976 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 5977 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5978 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5979 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5980 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5981 }
5982 }
5983
7ca647bd 5984 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5985 /* work around hardware counting issue */
7ca647bd 5986 hwstats->gprc -= missed_rx;
6f11eef7 5987
c84d324c
JF		 5988 ixgbe_update_xoff_received(adapter);
5989
6f11eef7 5990 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5991 switch (hw->mac.type) {
5992 case ixgbe_mac_82598EB:
5993 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5994 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5995 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5996 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5997 break;
b93a2226 5998 case ixgbe_mac_X540:
9a75a1ac
DS		 5999 case ixgbe_mac_X550:
6000 case ixgbe_mac_X550EM_x:
6001 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6002 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6003 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6004 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6005 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6006 case ixgbe_mac_82599EB:
a4d4f629
AD		 6007 for (i = 0; i < 16; i++)
6008 adapter->hw_rx_no_dma_resources +=
6009 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6010 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6011 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6012 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6013 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6014 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6015 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6016 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6017 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6018 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6019#ifdef IXGBE_FCOE
7ca647bd
JP		 6020 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6021 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6022 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6023 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6024 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6025 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6026 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6027 if (adapter->fcoe.ddp_pool) {
6028 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6029 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6030 unsigned int cpu;
6031 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6032 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6033 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6034 noddp += ddp_pool->noddp;
6035 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6036 }
5a1ee270
AD		 6037 hwstats->fcoe_noddp = noddp;
6038 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6039 }
6d45522c 6040#endif /* IXGBE_FCOE */
bd508178
AD		 6041 break;
6042 default:
6043 break;
e8e26350 6044 }
9a799d71 6045 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6046 hwstats->bprc += bprc;
6047 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6048 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6049 hwstats->mprc -= bprc;
6050 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6051 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6052 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6053 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6054 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6055 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6056 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6057 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6058 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6059 hwstats->lxontxc += lxon;
6f11eef7 6060 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6061 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6062 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6063 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6064 /*
6065 * 82598 errata - tx of flow control packets is included in tx counters
6066 */
6067 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6068 hwstats->gptc -= xon_off_tot;
6069 hwstats->mptc -= xon_off_tot;
6070 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6071 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6072 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6073 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6074 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6075 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6076 hwstats->ptc64 -= xon_off_tot;
6077 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6078 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6079 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6080 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6081 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6082 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6083
6084 /* Fill out the OS statistics structure */
7ca647bd 6085 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6086
6087 /* Rx Errors */
7ca647bd 6088 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6089 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6090 netdev->stats.rx_length_errors = hwstats->rlec;
6091 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6092 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6093}
6094
6095/**
d034acf1 6096 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6097 * @adapter: pointer to the device adapter structure
9a799d71 6098 **/
d034acf1 6099static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6100{
cf8280ee 6101 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6102 int i;
cf8280ee 6103
d034acf1
AD		 6104 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6105 return;
6106
6107 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6108
d034acf1 6109 /* if interface is down do nothing */
fe49f04a 6110 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6111 return;
6112
6113 /* do nothing if we are not using signature filters */
6114 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6115 return;
6116
6117 adapter->fdir_overflow++;
6118
93c52dd0
AD		 6119 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6120 for (i = 0; i < adapter->num_tx_queues; i++)
6121 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6122 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6123 /* re-enable flow director interrupts */
6124 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6125 } else {
6126 e_err(probe, "failed to finish FDIR re-initialization, "
6127 "ignored adding FDIR ATR filters\n");
6128 }
93c52dd0
AD		 6129}
6130
6131/**
6132 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6133 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6134 *
6135 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6136 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6137 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6138 * determine if a hang has occurred.
93c52dd0
AD		 6139 */
6140static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6141{
cf8280ee 6142 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6143 u64 eics = 0;
6144 int i;
cf8280ee 6145
09f40aed 6146 /* If we're down, removing or resetting, just bail */
93c52dd0 6147 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6148 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6149 test_bit(__IXGBE_RESETTING, &adapter->state))
6150 return;
22d5a71b 6151
93c52dd0
AD		 6152 /* Force detection of hung controller */
6153 if (netif_carrier_ok(adapter->netdev)) {
6154 for (i = 0; i < adapter->num_tx_queues; i++)
6155 set_check_for_tx_hang(adapter->tx_ring[i]);
6156 }
22d5a71b 6157
fe49f04a
AD		 6158 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6159 /*
6160 * for legacy and MSI interrupts don't set any bits
6161 * that are enabled for EIAM, because this operation
6162 * would set *both* EIMS and EICS for any bit in EIAM
6163 */
6164 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6165 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6166 } else {
6167 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6168 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6169 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6170 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6171 eics |= ((u64)1 << i);
6172 }
cf8280ee 6173 }
9a799d71 6174
93c52dd0 6175 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6176 ixgbe_irq_rearm_queues(adapter, eics);
6177
cf8280ee
JB		 6178}
6179
e8e26350 6180/**
93c52dd0 6181 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6182 * @adapter: pointer to the device adapter structure
6183 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6184 **/
93c52dd0 6185static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6186{
e8e26350 6187 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6188 u32 link_speed = adapter->link_speed;
6189 bool link_up = adapter->link_up;
041441d0 6190 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6191
93c52dd0
AD		 6192 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6193 return;
6194
6195 if (hw->mac.ops.check_link) {
6196 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6197 } else {
93c52dd0
AD		 6198 /* always assume link is up, if no check link function */
6199 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6200 link_up = true;
c4cf55e5 6201 }
041441d0
AD		 6202
6203 if (adapter->ixgbe_ieee_pfc)
6204 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6205
3ebe8fde 6206 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6207 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6208 ixgbe_set_rx_drop_en(adapter);
6209 }
93c52dd0
AD		 6210
6211 if (link_up ||
6212 time_after(jiffies, (adapter->link_check_timeout +
6213 IXGBE_TRY_LINK_TIMEOUT))) {
6214 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6215 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6216 IXGBE_WRITE_FLUSH(hw);
6217 }
6218
6219 adapter->link_up = link_up;
6220 adapter->link_speed = link_speed;
e8e26350
PW		 6221}
6222
107d3018
AD		 6223static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6224{
6225#ifdef CONFIG_IXGBE_DCB
6226 struct net_device *netdev = adapter->netdev;
6227 struct dcb_app app = {
6228 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6229 .protocol = 0,
6230 };
6231 u8 up = 0;
6232
6233 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6234 up = dcb_ieee_getapp_mask(netdev, &app);
6235
6236 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6237#endif
6238}
6239
e8e26350 6240/**
93c52dd0
AD		 6241 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6242 * print link up message
49ce9c2c 6243 * @adapter: pointer to the device adapter structure
e8e26350 6244 **/
93c52dd0 6245static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6246{
93c52dd0 6247 struct net_device *netdev = adapter->netdev;
e8e26350 6248 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6249 struct net_device *upper;
6250 struct list_head *iter;
93c52dd0
AD		 6251 u32 link_speed = adapter->link_speed;
6252 bool flow_rx, flow_tx;
e8e26350 6253
93c52dd0
AD		 6254 /* only continue if link was previously down */
6255 if (netif_carrier_ok(netdev))
a985b6c3 6256 return;
63d6e1d8 6257
93c52dd0 6258 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6259
93c52dd0
AD		 6260 switch (hw->mac.type) {
6261 case ixgbe_mac_82598EB: {
6262 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6263 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6264 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6265 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6266 }
6267 break;
6268 case ixgbe_mac_X540:
9a75a1ac
DS		 6269 case ixgbe_mac_X550:
6270 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6271 case ixgbe_mac_82599EB: {
6272 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6273 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6274 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6275 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6276 }
6277 break;
6278 default:
6279 flow_tx = false;
6280 flow_rx = false;
6281 break;
e8e26350 6282 }
3a6a4eda 6283
6cb562d6
JK		 6284 adapter->last_rx_ptp_check = jiffies;
6285
8fecf67c 6286 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6287 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6288
93c52dd0
AD		 6289 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6290 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6291 "10 Gbps" :
6292 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6293 "1 Gbps" :
6294 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6295 "100 Mbps" :
6296 "unknown speed"))),
6297 ((flow_rx && flow_tx) ? "RX/TX" :
6298 (flow_rx ? "RX" :
6299 (flow_tx ? "TX" : "None"))));
e8e26350 6300
93c52dd0 6301 netif_carrier_on(netdev);
93c52dd0 6302 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6303
cdc04dcc
ET		 6304 /* enable transmits */
6305 netif_tx_wake_all_queues(adapter->netdev);
6306
6307 /* enable any upper devices */
6308 rtnl_lock();
6309 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6310 if (netif_is_macvlan(upper)) {
6311 struct macvlan_dev *vlan = netdev_priv(upper);
6312
6313 if (vlan->fwd_priv)
6314 netif_tx_wake_all_queues(upper);
6315 }
6316 }
6317 rtnl_unlock();
6318
107d3018
AD		 6319 /* update the default user priority for VFs */
6320 ixgbe_update_default_up(adapter);
6321
befa2af7
AD		 6322 /* ping all the active vfs to let them know link has changed */
6323 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6324}
6325
c4cf55e5 6326/**
93c52dd0
AD		 6327 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6328 * print link down message
49ce9c2c 6329 * @adapter: pointer to the adapter structure
c4cf55e5 6330 **/
581330ba 6331static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6332{
cf8280ee 6333 struct net_device *netdev = adapter->netdev;
c4cf55e5 6334 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6335
93c52dd0
AD		 6336 adapter->link_up = false;
6337 adapter->link_speed = 0;
cf8280ee 6338
93c52dd0
AD		 6339 /* only continue if link was up previously */
6340 if (!netif_carrier_ok(netdev))
6341 return;
264857b8 6342
93c52dd0
AD		 6343 /* poll for SFP+ cable when link is down */
6344 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6345 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6346
8fecf67c 6347 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6348 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6349
93c52dd0
AD		 6350 e_info(drv, "NIC Link is Down\n");
6351 netif_carrier_off(netdev);
befa2af7
AD		 6352
6353 /* ping all the active vfs to let them know link has changed */
6354 ixgbe_ping_all_vfs(adapter);
93c52dd0 6355}
e8e26350 6356
07923c17
ET		 6357static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6358{
6359 int i;
6360
6361 for (i = 0; i < adapter->num_tx_queues; i++) {
6362 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6363
6364 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6365 return true;
6366 }
6367
6368 return false;
6369}
6370
6371static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6372{
6373 struct ixgbe_hw *hw = &adapter->hw;
6374 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6375 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6376
6377 int i, j;
6378
6379 if (!adapter->num_vfs)
6380 return false;
6381
9a75a1ac
DS		 6382 /* resetting the PF is only needed for MAC before X550 */
6383 if (hw->mac.type >= ixgbe_mac_X550)
6384 return false;
6385
07923c17
ET		 6386 for (i = 0; i < adapter->num_vfs; i++) {
6387 for (j = 0; j < q_per_pool; j++) {
6388 u32 h, t;
6389
6390 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6391 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6392
6393 if (h != t)
6394 return true;
6395 }
6396 }
6397
6398 return false;
6399}
6400
93c52dd0
AD		 6401/**
6402 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6403 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6404 **/
6405static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6406{
93c52dd0 6407 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6408 if (ixgbe_ring_tx_pending(adapter) ||
6409 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6410 /* We've lost link, so the controller stops DMA,
6411 * but we've got queued Tx work that's never going
6412 * to get done, so reset controller to flush Tx.
6413 * (Do the reset outside of interrupt context).
6414 */
12ff3f3b 6415 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6416 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6417 }
c4cf55e5 6418 }
c4cf55e5
PWJ		 6419}
6420
9079e416
ET		 6421#ifdef CONFIG_PCI_IOV
6422static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6423 struct pci_dev *vfdev)
6424{
6425 if (!pci_wait_for_pending_transaction(vfdev))
6426 e_dev_warn("Issuing VFLR with pending transactions\n");
6427
6428 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6429 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6430
6431 msleep(100);
6432}
6433
6434static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6435{
6436 struct ixgbe_hw *hw = &adapter->hw;
6437 struct pci_dev *pdev = adapter->pdev;
6438 struct pci_dev *vfdev;
6439 u32 gpc;
6440 int pos;
6441 unsigned short vf_id;
6442
6443 if (!(netif_carrier_ok(adapter->netdev)))
6444 return;
6445
6446 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6447 if (gpc) /* If incrementing then no need for the check below */
6448 return;
6449 /* Check to see if a bad DMA write target from an errant or
6450 * malicious VF has caused a PCIe error. If so then we can
6451 * issue a VFLR to the offending VF(s) and then resume without
6452 * requesting a full slot reset.
6453 */
6454
6455 if (!pdev)
6456 return;
6457
6458 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6459 if (!pos)
6460 return;
6461
6462 /* get the device ID for the VF */
6463 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6464
6465 /* check status reg for all VFs owned by this PF */
6466 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6467 while (vfdev) {
6468 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6469 u16 status_reg;
6470
6471 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6472 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6473 /* issue VFLR */
6474 ixgbe_issue_vf_flr(adapter, vfdev);
6475 }
6476
6477 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6478 }
6479}
6480
a985b6c3
GR		 6481static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6482{
6483 u32 ssvpc;
6484
0584d999
GR		 6485 /* Do not perform spoof check for 82598 or if not in IOV mode */
6486 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6487 adapter->num_vfs == 0)
a985b6c3
GR		 6488 return;
6489
6490 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6491
6492 /*
6493 * ssvpc register is cleared on read, if zero then no
6494 * spoofed packets in the last interval.
6495 */
6496 if (!ssvpc)
6497 return;
6498
d6ea0754 6499 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6500}
9079e416
ET		 6501#else
6502static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6503{
6504}
6505
6506static void
6507ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6508{
6509}
6510#endif /* CONFIG_PCI_IOV */
6511
a985b6c3 6512
93c52dd0
AD		 6513/**
6514 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6515 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6516 **/
6517static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6518{
09f40aed 6519 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6520 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6521 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6522 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6523 return;
6524
6525 ixgbe_watchdog_update_link(adapter);
6526
6527 if (adapter->link_up)
6528 ixgbe_watchdog_link_is_up(adapter);
6529 else
6530 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6531
9079e416 6532 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6533 ixgbe_spoof_check(adapter);
9a799d71 6534 ixgbe_update_stats(adapter);
93c52dd0
AD		 6535
6536 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6537}
10eec955 6538
cf8280ee 6539/**
7086400d 6540 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6541 * @adapter: the ixgbe adapter structure
cf8280ee 6542 **/
7086400d 6543static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6544{
cf8280ee 6545 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6546 s32 err;
cf8280ee 6547
7086400d
AD		 6548 /* not searching for SFP so there is nothing to do here */
6549 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6550 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6551 return;
10eec955 6552
7086400d
AD		 6553 /* someone else is in init, wait until next service event */
6554 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6555 return;
cf8280ee 6556
7086400d
AD		 6557 err = hw->phy.ops.identify_sfp(hw);
6558 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6559 goto sfp_out;
264857b8 6560
7086400d
AD		 6561 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6562 /* If no cable is present, then we need to reset
6563 * the next time we find a good cable. */
6564 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6565 }
9a799d71 6566
7086400d
AD		 6567 /* exit on error */
6568 if (err)
6569 goto sfp_out;
e8e26350 6570
7086400d
AD		 6571 /* exit if reset not needed */
6572 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6573 goto sfp_out;
9a799d71 6574
7086400d 6575 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6576
7086400d
AD		 6577 /*
6578 * A module may be identified correctly, but the EEPROM may not have
6579 * support for that module. setup_sfp() will fail in that case, so
6580 * we should not allow that module to load.
6581 */
6582 if (hw->mac.type == ixgbe_mac_82598EB)
6583 err = hw->phy.ops.reset(hw);
6584 else
6585 err = hw->mac.ops.setup_sfp(hw);
6586
6587 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6588 goto sfp_out;
6589
6590 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6591 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6592
6593sfp_out:
6594 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6595
6596 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6597 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6598 e_dev_err("failed to initialize because an unsupported "
6599 "SFP+ module type was detected.\n");
6600 e_dev_err("Reload the driver after installing a "
6601 "supported module.\n");
6602 unregister_netdev(adapter->netdev);
bc59fcda 6603 }
7086400d 6604}
bc59fcda 6605
7086400d
AD		 6606/**
6607 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6608 * @adapter: the ixgbe adapter structure
7086400d
AD		 6609 **/
6610static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6611{
6612 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6613 u32 speed;
6614 bool autoneg = false;
7086400d
AD		 6615
6616 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6617 return;
6618
6619 /* someone else is in init, wait until next service event */
6620 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6621 return;
6622
6623 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6624
3d292265 6625 speed = hw->phy.autoneg_advertised;
ed33ff66 6626 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6627 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6628
6629 /* setup the highest link when no autoneg */
6630 if (!autoneg) {
6631 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6632 speed = IXGBE_LINK_SPEED_10GB_FULL;
6633 }
6634 }
6635
7086400d 6636 if (hw->mac.ops.setup_link)
fd0326f2 6637 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6638
6639 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6640 adapter->link_check_timeout = jiffies;
6641 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6642}
6643
6644/**
6645 * ixgbe_service_timer - Timer Call-back
6646 * @data: pointer to adapter cast into an unsigned long
6647 **/
6648static void ixgbe_service_timer(unsigned long data)
6649{
6650 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6651 unsigned long next_event_offset;
6652
6bb78cfb
AD		 6653 /* poll faster when waiting for link */
6654 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6655 next_event_offset = HZ / 10;
6656 else
6657 next_event_offset = HZ * 2;
83c61fa9 6658
7086400d
AD		 6659 /* Reset the timer */
6660 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6661
9079e416 6662 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6663}
6664
c83c6cbd
AD		 6665static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6666{
6667 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6668 return;
6669
6670 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6671
09f40aed 6672 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6673 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6674 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6675 test_bit(__IXGBE_RESETTING, &adapter->state))
6676 return;
6677
6678 ixgbe_dump(adapter);
6679 netdev_err(adapter->netdev, "Reset adapter\n");
6680 adapter->tx_timeout_count++;
6681
8f4c5c9f 6682 rtnl_lock();
c83c6cbd 6683 ixgbe_reinit_locked(adapter);
8f4c5c9f 6684 rtnl_unlock();
c83c6cbd
AD		 6685}
6686
7086400d
AD		 6687/**
6688 * ixgbe_service_task - manages and runs subtasks
6689 * @work: pointer to work_struct containing our data
6690 **/
6691static void ixgbe_service_task(struct work_struct *work)
6692{
6693 struct ixgbe_adapter *adapter = container_of(work,
6694 struct ixgbe_adapter,
6695 service_task);
b0483c8f
MR		 6696 if (ixgbe_removed(adapter->hw.hw_addr)) {
6697 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6698 rtnl_lock();
6699 ixgbe_down(adapter);
6700 rtnl_unlock();
6701 }
6702 ixgbe_service_event_complete(adapter);
6703 return;
6704 }
c83c6cbd 6705 ixgbe_reset_subtask(adapter);
7086400d
AD		 6706 ixgbe_sfp_detection_subtask(adapter);
6707 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6708 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6709 ixgbe_watchdog_subtask(adapter);
d034acf1 6710 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6711 ixgbe_check_hang_subtask(adapter);
891dc082 6712
8fecf67c 6713 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6714 ixgbe_ptp_overflow_check(adapter);
6715 ixgbe_ptp_rx_hang(adapter);
6716 }
7086400d
AD		 6717
6718 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6719}
6720
fd0db0ed
AD		 6721static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6722 struct ixgbe_tx_buffer *first,
244e27ad 6723 u8 *hdr_len)
897ab156 6724{
fd0db0ed 6725 struct sk_buff *skb = first->skb;
897ab156
AD		 6726 u32 vlan_macip_lens, type_tucmd;
6727 u32 mss_l4len_idx, l4len;
2049e1f6 6728 int err;
9a799d71 6729
8f4fbb9b
AD		 6730 if (skb->ip_summed != CHECKSUM_PARTIAL)
6731 return 0;
6732
897ab156
AD		 6733 if (!skb_is_gso(skb))
6734 return 0;
9a799d71 6735
2049e1f6
FR		 6736 err = skb_cow_head(skb, 0);
6737 if (err < 0)
6738 return err;
9a799d71 6739
897ab156
AD		 6740 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6741 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6742
a1108ffd 6743 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6744 struct iphdr *iph = ip_hdr(skb);
6745 iph->tot_len = 0;
6746 iph->check = 0;
6747 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6748 iph->daddr, 0,
6749 IPPROTO_TCP,
6750 0);
6751 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6752 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6753 IXGBE_TX_FLAGS_CSUM |
6754 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6755 } else if (skb_is_gso_v6(skb)) {
6756 ipv6_hdr(skb)->payload_len = 0;
6757 tcp_hdr(skb)->check =
6758 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6759 &ipv6_hdr(skb)->daddr,
6760 0, IPPROTO_TCP, 0);
244e27ad
AD		 6761 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6762 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6763 }
6764
091a6246 6765 /* compute header lengths */
897ab156
AD		 6766 l4len = tcp_hdrlen(skb);
6767 *hdr_len = skb_transport_offset(skb) + l4len;
6768
091a6246
AD		 6769 /* update gso size and bytecount with header size */
6770 first->gso_segs = skb_shinfo(skb)->gso_segs;
6771 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6772
c44f5f51 6773 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6774 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6775 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6776
6777 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6778 vlan_macip_lens = skb_network_header_len(skb);
6779 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6780 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6781
6782 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6783 mss_l4len_idx);
897ab156
AD		 6784
6785 return 1;
6786}
6787
244e27ad
AD		 6788static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6789 struct ixgbe_tx_buffer *first)
7ca647bd 6790{
fd0db0ed 6791 struct sk_buff *skb = first->skb;
897ab156
AD		 6792 u32 vlan_macip_lens = 0;
6793 u32 mss_l4len_idx = 0;
6794 u32 type_tucmd = 0;
7ca647bd 6795
897ab156 6796 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6797 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6798 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6799 return;
897ab156
AD		 6800 } else {
6801 u8 l4_hdr = 0;
244e27ad 6802 switch (first->protocol) {
a1108ffd 6803 case htons(ETH_P_IP):
897ab156
AD		 6804 vlan_macip_lens |= skb_network_header_len(skb);
6805 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6806 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6807 break;
a1108ffd 6808 case htons(ETH_P_IPV6):
897ab156
AD		 6809 vlan_macip_lens |= skb_network_header_len(skb);
6810 l4_hdr = ipv6_hdr(skb)->nexthdr;
6811 break;
6812 default:
6813 if (unlikely(net_ratelimit())) {
6814 dev_warn(tx_ring->dev,
6815 "partial checksum but proto=%x!\n",
244e27ad 6816 first->protocol);
897ab156 6817 }
7ca647bd
JP		 6818 break;
6819 }
897ab156
AD		 6820
6821 switch (l4_hdr) {
7ca647bd 6822 case IPPROTO_TCP:
897ab156
AD		 6823 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6824 mss_l4len_idx = tcp_hdrlen(skb) <<
6825 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6826 break;
6827 case IPPROTO_SCTP:
897ab156
AD		 6828 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6829 mss_l4len_idx = sizeof(struct sctphdr) <<
6830 IXGBE_ADVTXD_L4LEN_SHIFT;
6831 break;
6832 case IPPROTO_UDP:
6833 mss_l4len_idx = sizeof(struct udphdr) <<
6834 IXGBE_ADVTXD_L4LEN_SHIFT;
6835 break;
6836 default:
6837 if (unlikely(net_ratelimit())) {
6838 dev_warn(tx_ring->dev,
6839 "partial checksum but l4 proto=%x!\n",
244e27ad 6840 l4_hdr);
897ab156 6841 }
7ca647bd
JP		 6842 break;
6843 }
244e27ad
AD		 6844
6845 /* update TX checksum flag */
6846 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6847 }
6848
244e27ad 6849 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6850 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6851 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6852
897ab156
AD		 6853 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6854 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6855}
6856
472148c3
AD		 6857#define IXGBE_SET_FLAG(_input, _flag, _result) \
6858 ((_flag <= _result) ? \
6859 ((u32)(_input & _flag) * (_result / _flag)) : \
6860 ((u32)(_input & _flag) / (_flag / _result)))
6861
6862static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6863{
d3d00239 6864 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6865 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6866 IXGBE_ADVTXD_DCMD_DEXT |
6867 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6868
d3d00239 6869 /* set HW vlan bit if vlan is present */
472148c3
AD		 6870 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6871 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6872
d3d00239 6873 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6874 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6875 IXGBE_ADVTXD_DCMD_TSE);
6876
6877 /* set timestamp bit if present */
6878 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6879 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6880
62748b7b 6881 /* insert frame checksum */
472148c3 6882 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6883
d3d00239
AD		 6884 return cmd_type;
6885}
9a799d71 6886
729739b7
AD		 6887static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6888 u32 tx_flags, unsigned int paylen)
d3d00239 6889{
472148c3 6890 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6891
d3d00239 6892 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6893 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6894 IXGBE_TX_FLAGS_CSUM,
6895 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6896
93f5b3c1 6897 /* enble IPv4 checksum for TSO */
472148c3
AD		 6898 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6899 IXGBE_TX_FLAGS_IPV4,
6900 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6901
7f9643fd
AD		 6902 /*
6903 * Check Context must be set if Tx switch is enabled, which it
6904 * always is for case where virtual functions are running
6905 */
472148c3
AD		 6906 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6907 IXGBE_TX_FLAGS_CC,
6908 IXGBE_ADVTXD_CC);
7f9643fd 6909
472148c3 6910 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6911}
44df32c5 6912
2367a173
DB		 6913static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6914{
6915 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6916
6917 /* Herbert's original patch had:
6918 * smp_mb__after_netif_stop_queue();
6919 * but since that doesn't exist yet, just open code it.
6920 */
6921 smp_mb();
6922
6923 /* We need to check again in a case another CPU has just
6924 * made room available.
6925 */
6926 if (likely(ixgbe_desc_unused(tx_ring) < size))
6927 return -EBUSY;
6928
6929 /* A reprieve! - use start_queue because it doesn't call schedule */
6930 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6931 ++tx_ring->tx_stats.restart_queue;
6932 return 0;
6933}
6934
6935static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6936{
6937 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6938 return 0;
6939
6940 return __ixgbe_maybe_stop_tx(tx_ring, size);
6941}
6942
d3d00239
AD		 6943#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6944 IXGBE_TXD_CMD_RS)
6945
6946static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6947 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6948 const u8 hdr_len)
6949{
fd0db0ed 6950 struct sk_buff *skb = first->skb;
729739b7 6951 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6952 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6953 struct skb_frag_struct *frag;
6954 dma_addr_t dma;
6955 unsigned int data_len, size;
244e27ad 6956 u32 tx_flags = first->tx_flags;
472148c3 6957 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6958 u16 i = tx_ring->next_to_use;
d3d00239 6959
729739b7
AD		 6960 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6961
ec718254
AD		 6962 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6963
6964 size = skb_headlen(skb);
6965 data_len = skb->data_len;
729739b7 6966
d3d00239
AD		 6967#ifdef IXGBE_FCOE
6968 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6969 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6970 size -= sizeof(struct fcoe_crc_eof) - data_len;
6971 data_len = 0;
729739b7
AD		 6972 } else {
6973 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6974 }
6975 }
44df32c5 6976
d3d00239 6977#endif
729739b7 6978 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6979
ec718254 6980 tx_buffer = first;
9a799d71 6981
ec718254
AD		 6982 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6983 if (dma_mapping_error(tx_ring->dev, dma))
6984 goto dma_error;
6985
6986 /* record length, and DMA address */
6987 dma_unmap_len_set(tx_buffer, len, size);
6988 dma_unmap_addr_set(tx_buffer, dma, dma);
6989
6990 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6991
729739b7 6992 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6993 tx_desc->read.cmd_type_len =
472148c3 6994 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6995
d3d00239 6996 i++;
729739b7 6997 tx_desc++;
d3d00239 6998 if (i == tx_ring->count) {
e4f74028 6999 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7000 i = 0;
7001 }
ec718254 7002 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7003
7004 dma += IXGBE_MAX_DATA_PER_TXD;
7005 size -= IXGBE_MAX_DATA_PER_TXD;
7006
7007 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7008 }
e5a43549 7009
729739b7
AD		 7010 if (likely(!data_len))
7011 break;
9a799d71 7012
472148c3 7013 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7014
729739b7
AD		 7015 i++;
7016 tx_desc++;
7017 if (i == tx_ring->count) {
7018 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7019 i = 0;
7020 }
ec718254 7021 tx_desc->read.olinfo_status = 0;
9a799d71 7022
d3d00239 7023#ifdef IXGBE_FCOE
9e903e08 7024 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7025#else
9e903e08 7026 size = skb_frag_size(frag);
d3d00239
AD		 7027#endif
7028 data_len -= size;
9a799d71 7029
729739b7
AD		 7030 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7031 DMA_TO_DEVICE);
9a799d71 7032
729739b7 7033 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7034 }
9a799d71 7035
729739b7 7036 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7037 cmd_type |= size | IXGBE_TXD_CMD;
7038 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7039
091a6246 7040 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7041
d3d00239
AD		 7042 /* set the timestamp */
7043 first->time_stamp = jiffies;
9a799d71
AK		 7044
7045 /*
729739b7
AD		 7046 * Force memory writes to complete before letting h/w know there
7047 * are new descriptors to fetch. (Only applicable for weak-ordered
7048 * memory model archs, such as IA-64).
7049 *
7050 * We also need this memory barrier to make certain all of the
7051 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7052 */
7053 wmb();
7054
d3d00239
AD		 7055 /* set next_to_watch value indicating a packet is present */
7056 first->next_to_watch = tx_desc;
7057
729739b7
AD		 7058 i++;
7059 if (i == tx_ring->count)
7060 i = 0;
7061
7062 tx_ring->next_to_use = i;
7063
2367a173
DB		 7064 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7065
7066 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7067 writel(i, tx_ring->tail);
7068
7069 /* we need this if more than one processor can write to our tail
7070 * at a time, it synchronizes IO on IA64/Altix systems
7071 */
7072 mmiowb();
9c938cdd 7073 }
2367a173 7074
d3d00239
AD		 7075 return;
7076dma_error:
729739b7 7077 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7078
7079 /* clear dma mappings for failed tx_buffer_info map */
7080 for (;;) {
729739b7
AD		 7081 tx_buffer = &tx_ring->tx_buffer_info[i];
7082 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7083 if (tx_buffer == first)
d3d00239
AD		 7084 break;
7085 if (i == 0)
7086 i = tx_ring->count;
7087 i--;
7088 }
7089
d3d00239 7090 tx_ring->next_to_use = i;
9a799d71
AK		 7091}
7092
fd0db0ed 7093static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7094 struct ixgbe_tx_buffer *first)
69830529
AD		 7095{
7096 struct ixgbe_q_vector *q_vector = ring->q_vector;
7097 union ixgbe_atr_hash_dword input = { .dword = 0 };
7098 union ixgbe_atr_hash_dword common = { .dword = 0 };
7099 union {
7100 unsigned char *network;
7101 struct iphdr *ipv4;
7102 struct ipv6hdr *ipv6;
7103 } hdr;
ee9e0f0b 7104 struct tcphdr *th;
905e4a41 7105 __be16 vlan_id;
c4cf55e5 7106
69830529
AD		 7107 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7108 if (!q_vector)
7109 return;
7110
7111 /* do nothing if sampling is disabled */
7112 if (!ring->atr_sample_rate)
d3ead241 7113 return;
c4cf55e5 7114
69830529 7115 ring->atr_count++;
c4cf55e5 7116
69830529 7117 /* snag network header to get L4 type and address */
fd0db0ed 7118 hdr.network = skb_network_header(first->skb);
69830529
AD		 7119
7120 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 7121 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 7122 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 7123 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 7124 hdr.ipv4->protocol != IPPROTO_TCP))
7125 return;
ee9e0f0b 7126
fd0db0ed 7127 th = tcp_hdr(first->skb);
c4cf55e5 7128
66f32a8b
AD		 7129 /* skip this packet since it is invalid or the socket is closing */
7130 if (!th || th->fin)
69830529
AD		 7131 return;
7132
7133 /* sample on all syn packets or once every atr sample count */
7134 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7135 return;
7136
7137 /* reset sample count */
7138 ring->atr_count = 0;
7139
244e27ad 7140 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7141
7142 /*
7143 * src and dst are inverted, think how the receiver sees them
7144 *
7145 * The input is broken into two sections, a non-compressed section
7146 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7147 * is XORed together and stored in the compressed dword.
7148 */
7149 input.formatted.vlan_id = vlan_id;
7150
7151 /*
7152 * since src port and flex bytes occupy the same word XOR them together
7153 * and write the value to source port portion of compressed dword
7154 */
244e27ad 7155 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7156 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7157 else
244e27ad 7158 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7159 common.port.dst ^= th->source;
7160
a1108ffd 7161 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7162 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7163 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7164 } else {
7165 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7166 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7167 hdr.ipv6->saddr.s6_addr32[1] ^
7168 hdr.ipv6->saddr.s6_addr32[2] ^
7169 hdr.ipv6->saddr.s6_addr32[3] ^
7170 hdr.ipv6->daddr.s6_addr32[0] ^
7171 hdr.ipv6->daddr.s6_addr32[1] ^
7172 hdr.ipv6->daddr.s6_addr32[2] ^
7173 hdr.ipv6->daddr.s6_addr32[3];
7174 }
c4cf55e5
PWJ		 7175
7176 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7177 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7178 input, common, ring->queue_index);
c4cf55e5
PWJ		 7179}
7180
f663dd9a 7181static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7182 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7183{
f663dd9a
JW		 7184 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7185#ifdef IXGBE_FCOE
97488bd1
AD		 7186 struct ixgbe_adapter *adapter;
7187 struct ixgbe_ring_feature *f;
7188 int txq;
f663dd9a
JW		 7189#endif
7190
7191 if (fwd_adapter)
7192 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7193
7194#ifdef IXGBE_FCOE
5e09a105 7195
97488bd1
AD		 7196 /*
7197 * only execute the code below if protocol is FCoE
7198 * or FIP and we have FCoE enabled on the adapter
7199 */
7200 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7201 case htons(ETH_P_FCOE):
7202 case htons(ETH_P_FIP):
97488bd1 7203 adapter = netdev_priv(dev);
c087663e 7204
97488bd1
AD		 7205 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7206 break;
7207 default:
99932d4f 7208 return fallback(dev, skb);
97488bd1 7209 }
c087663e 7210
97488bd1 7211 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7212
97488bd1
AD		 7213 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7214 smp_processor_id();
56075a98 7215
97488bd1
AD		 7216 while (txq >= f->indices)
7217 txq -= f->indices;
c4cf55e5 7218
97488bd1 7219 return txq + f->offset;
f663dd9a 7220#else
99932d4f 7221 return fallback(dev, skb);
f663dd9a 7222#endif
09a3b1f8
SH		 7223}
7224
fc77dc3c 7225netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7226 struct ixgbe_adapter *adapter,
7227 struct ixgbe_ring *tx_ring)
9a799d71 7228{
d3d00239 7229 struct ixgbe_tx_buffer *first;
5f715823 7230 int tso;
d3d00239 7231 u32 tx_flags = 0;
a535c30e 7232 unsigned short f;
a535c30e 7233 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7234 __be16 protocol = skb->protocol;
63544e9c 7235 u8 hdr_len = 0;
5e09a105 7236
a535c30e
AD		 7237 /*
7238 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7239 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7240 * + 2 desc gap to keep tail from touching head,
7241 * + 1 desc for context descriptor,
7242 * otherwise try next time
7243 */
a535c30e
AD		 7244 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7245 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7246
a535c30e
AD		 7247 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7248 tx_ring->tx_stats.tx_busy++;
7249 return NETDEV_TX_BUSY;
7250 }
7251
fd0db0ed
AD		 7252 /* record the location of the first descriptor for this packet */
7253 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7254 first->skb = skb;
091a6246
AD		 7255 first->bytecount = skb->len;
7256 first->gso_segs = 1;
fd0db0ed 7257
66f32a8b 7258 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7259 if (skb_vlan_tag_present(skb)) {
7260 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7261 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7262 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7263 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7264 struct vlan_hdr *vhdr, _vhdr;
7265 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7266 if (!vhdr)
7267 goto out_drop;
7268
9e0c5648
AD		 7269 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7270 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7271 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7272 }
0213668f 7273 protocol = vlan_get_protocol(skb);
66f32a8b 7274
d5234933
MR		 7275 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7276 adapter->ptp_clock &&
7277 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7278 &adapter->state)) {
3a6a4eda
JK		 7279 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7280 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7281
7282 /* schedule check for Tx timestamp */
7283 adapter->ptp_tx_skb = skb_get(skb);
7284 adapter->ptp_tx_start = jiffies;
7285 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7286 }
3a6a4eda 7287
ff29a86e
JK		 7288 skb_tx_timestamp(skb);
7289
9e0c5648
AD		 7290#ifdef CONFIG_PCI_IOV
7291 /*
7292 * Use the l2switch_enable flag - would be false if the DMA
7293 * Tx switch had been disabled.
7294 */
7295 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7296 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7297
7298#endif
32701dc2 7299 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7300 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7301 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7302 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7303 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7304 tx_flags |= (skb->priority & 0x7) <<
7305 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7306 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7307 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7308
7309 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7310 goto out_drop;
7311 vhdr = (struct vlan_ethhdr *)skb->data;
7312 vhdr->h_vlan_TCI = htons(tx_flags >>
7313 IXGBE_TX_FLAGS_VLAN_SHIFT);
7314 } else {
7315 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7316 }
9a799d71 7317 }
eacd73f7 7318
244e27ad
AD		 7319 /* record initial flags and protocol */
7320 first->tx_flags = tx_flags;
7321 first->protocol = protocol;
7322
eacd73f7 7323#ifdef IXGBE_FCOE
66f32a8b 7324 /* setup tx offload for FCoE */
a1108ffd 7325 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7326 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7327 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7328 if (tso < 0)
7329 goto out_drop;
9a799d71 7330
66f32a8b 7331 goto xmit_fcoe;
eacd73f7 7332 }
9a799d71 7333
66f32a8b 7334#endif /* IXGBE_FCOE */
244e27ad 7335 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7336 if (tso < 0)
897ab156 7337 goto out_drop;
244e27ad
AD		 7338 else if (!tso)
7339 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7340
7341 /* add the ATR filter if ATR is on */
7342 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7343 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7344
7345#ifdef IXGBE_FCOE
7346xmit_fcoe:
7347#endif /* IXGBE_FCOE */
244e27ad 7348 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7349
9a799d71 7350 return NETDEV_TX_OK;
897ab156
AD		 7351
7352out_drop:
fd0db0ed
AD		 7353 dev_kfree_skb_any(first->skb);
7354 first->skb = NULL;
7355
897ab156 7356 return NETDEV_TX_OK;
9a799d71
AK		 7357}
7358
2a47fa45
JF		 7359static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7360 struct net_device *netdev,
7361 struct ixgbe_ring *ring)
84418e3b
AD		 7362{
7363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7364 struct ixgbe_ring *tx_ring;
7365
a50c29dd
AD		 7366 /*
7367 * The minimum packet size for olinfo paylen is 17 so pad the skb
7368 * in order to meet this minimum size requirement.
7369 */
a94d9e22
AD		 7370 if (skb_put_padto(skb, 17))
7371 return NETDEV_TX_OK;
a50c29dd 7372
2a47fa45
JF		 7373 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7374
fc77dc3c 7375 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7376}
7377
2a47fa45
JF		 7378static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7379 struct net_device *netdev)
7380{
7381 return __ixgbe_xmit_frame(skb, netdev, NULL);
7382}
7383
9a799d71
AK		 7384/**
7385 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7386 * @netdev: network interface device structure
7387 * @p: pointer to an address structure
7388 *
7389 * Returns 0 on success, negative on failure
7390 **/
7391static int ixgbe_set_mac(struct net_device *netdev, void *p)
7392{
7393 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7394 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7395 struct sockaddr *addr = p;
5d7daa35 7396 int ret;
9a799d71
AK		 7397
7398 if (!is_valid_ether_addr(addr->sa_data))
7399 return -EADDRNOTAVAIL;
7400
5d7daa35 7401 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7402 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7403 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7404
5d7daa35
JK		 7405 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7406 return ret > 0 ? 0 : ret;
9a799d71
AK		 7407}
7408
6b73e10d
BH		 7409static int
7410ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7411{
7412 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7413 struct ixgbe_hw *hw = &adapter->hw;
7414 u16 value;
7415 int rc;
7416
7417 if (prtad != hw->phy.mdio.prtad)
7418 return -EINVAL;
7419 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7420 if (!rc)
7421 rc = value;
7422 return rc;
7423}
7424
7425static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7426 u16 addr, u16 value)
7427{
7428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7429 struct ixgbe_hw *hw = &adapter->hw;
7430
7431 if (prtad != hw->phy.mdio.prtad)
7432 return -EINVAL;
7433 return hw->phy.ops.write_reg(hw, addr, devad, value);
7434}
7435
7436static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7437{
7438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7439
3a6a4eda 7440 switch (cmd) {
3a6a4eda 7441 case SIOCSHWTSTAMP:
93501d48
JK		 7442 return ixgbe_ptp_set_ts_config(adapter, req);
7443 case SIOCGHWTSTAMP:
7444 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7445 default:
7446 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7447 }
6b73e10d
BH		 7448}
7449
0365e6e4
PW		 7450/**
7451 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7452 * netdev->dev_addrs
0365e6e4
PW		 7453 * @netdev: network interface device structure
7454 *
7455 * Returns non-zero on failure
7456 **/
7457static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7458{
7459 int err = 0;
7460 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7461 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7462
7fa7c9dc 7463 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7464 rtnl_lock();
7fa7c9dc 7465 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7466 rtnl_unlock();
7fa7c9dc
AD		 7467
7468 /* update SAN MAC vmdq pool selection */
7469 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7470 }
7471 return err;
7472}
7473
7474/**
7475 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7476 * netdev->dev_addrs
0365e6e4
PW		 7477 * @netdev: network interface device structure
7478 *
7479 * Returns non-zero on failure
7480 **/
7481static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7482{
7483 int err = 0;
7484 struct ixgbe_adapter *adapter = netdev_priv(dev);
7485 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7486
7487 if (is_valid_ether_addr(mac->san_addr)) {
7488 rtnl_lock();
7489 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7490 rtnl_unlock();
7491 }
7492 return err;
7493}
7494
9a799d71
AK		 7495#ifdef CONFIG_NET_POLL_CONTROLLER
7496/*
7497 * Polling 'interrupt' - used by things like netconsole to send skbs
7498 * without having to re-enable interrupts. It's not called while
7499 * the interrupt routine is executing.
7500 */
7501static void ixgbe_netpoll(struct net_device *netdev)
7502{
7503 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7504 int i;
9a799d71 7505
1a647bd2
AD		 7506 /* if interface is down do nothing */
7507 if (test_bit(__IXGBE_DOWN, &adapter->state))
7508 return;
7509
9a799d71 7510 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7511 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7512 for (i = 0; i < adapter->num_q_vectors; i++)
7513 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7514 } else {
7515 ixgbe_intr(adapter->pdev->irq, netdev);
7516 }
9a799d71 7517 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7518}
9a799d71 7519
581330ba 7520#endif
de1036b1
ED		 7521static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7522 struct rtnl_link_stats64 *stats)
7523{
7524 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7525 int i;
7526
1a51502b 7527 rcu_read_lock();
de1036b1 7528 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7529 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7530 u64 bytes, packets;
7531 unsigned int start;
7532
1a51502b
ED		 7533 if (ring) {
7534 do {
57a7744e 7535 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7536 packets = ring->stats.packets;
7537 bytes = ring->stats.bytes;
57a7744e 7538 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7539 stats->rx_packets += packets;
7540 stats->rx_bytes += bytes;
7541 }
de1036b1 7542 }
1ac9ad13
ED		 7543
7544 for (i = 0; i < adapter->num_tx_queues; i++) {
7545 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7546 u64 bytes, packets;
7547 unsigned int start;
7548
7549 if (ring) {
7550 do {
57a7744e 7551 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7552 packets = ring->stats.packets;
7553 bytes = ring->stats.bytes;
57a7744e 7554 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7555 stats->tx_packets += packets;
7556 stats->tx_bytes += bytes;
7557 }
7558 }
1a51502b 7559 rcu_read_unlock();
de1036b1
ED		 7560 /* following stats updated by ixgbe_watchdog_task() */
7561 stats->multicast = netdev->stats.multicast;
7562 stats->rx_errors = netdev->stats.rx_errors;
7563 stats->rx_length_errors = netdev->stats.rx_length_errors;
7564 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7565 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7566 return stats;
7567}
7568
8af3c33f 7569#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7570/**
7571 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7572 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7573 * @tc: number of traffic classes currently enabled
7574 *
7575 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7576 * 802.1Q priority maps to a packet buffer that exists.
7577 */
7578static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7579{
7580 struct ixgbe_hw *hw = &adapter->hw;
7581 u32 reg, rsave;
7582 int i;
7583
7584 /* 82598 have a static priority to TC mapping that can not
7585 * be changed so no validation is needed.
7586 */
7587 if (hw->mac.type == ixgbe_mac_82598EB)
7588 return;
7589
7590 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7591 rsave = reg;
7592
7593 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7594 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7595
7596 /* If up2tc is out of bounds default to zero */
7597 if (up2tc > tc)
7598 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7599 }
7600
7601 if (reg != rsave)
7602 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7603
7604 return;
7605}
7606
02debdc9
AD		 7607/**
7608 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7609 * @adapter: Pointer to adapter struct
7610 *
7611 * Populate the netdev user priority to tc map
7612 */
7613static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7614{
7615 struct net_device *dev = adapter->netdev;
7616 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7617 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7618 u8 prio;
7619
7620 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7621 u8 tc = 0;
7622
7623 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7624 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7625 else if (ets)
7626 tc = ets->prio_tc[prio];
7627
7628 netdev_set_prio_tc_map(dev, prio, tc);
7629 }
7630}
7631
cca73c59 7632#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7633/**
7634 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7635 *
7636 * @netdev: net device to configure
7637 * @tc: number of traffic classes to enable
7638 */
7639int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7640{
8b1c0b24
JF		 7641 struct ixgbe_adapter *adapter = netdev_priv(dev);
7642 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7643 bool pools;
8b1c0b24 7644
8b1c0b24 7645 /* Hardware supports up to 8 traffic classes */
4de2a022 7646 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7647 (hw->mac.type == ixgbe_mac_82598EB &&
7648 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7649 return -EINVAL;
7650
2a47fa45
JF		 7651 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7652 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7653 return -EBUSY;
7654
8b1c0b24 7655 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7656 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7657 * hardware is not flexible enough to do this dynamically.
7658 */
7659 if (netif_running(dev))
7660 ixgbe_close(dev);
7661 ixgbe_clear_interrupt_scheme(adapter);
7662
cca73c59 7663#ifdef CONFIG_IXGBE_DCB
e7589eab 7664 if (tc) {
8b1c0b24 7665 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7666 ixgbe_set_prio_tc_map(adapter);
7667
e7589eab 7668 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7669
943561d3
AD		 7670 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7671 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7672 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7673 }
e7589eab 7674 } else {
8b1c0b24 7675 netdev_reset_tc(dev);
02debdc9 7676
943561d3
AD		 7677 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7678 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7679
7680 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7681
7682 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7683 adapter->dcb_cfg.pfc_mode_enable = false;
7684 }
7685
8b1c0b24 7686 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7687
7688#endif /* CONFIG_IXGBE_DCB */
7689 ixgbe_init_interrupt_scheme(adapter);
7690
8b1c0b24 7691 if (netif_running(dev))
cca73c59 7692 return ixgbe_open(dev);
8b1c0b24
JF		 7693
7694 return 0;
7695}
de1036b1 7696
da36b647
GR		 7697#ifdef CONFIG_PCI_IOV
7698void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7699{
7700 struct net_device *netdev = adapter->netdev;
7701
7702 rtnl_lock();
da36b647 7703 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7704 rtnl_unlock();
7705}
7706
7707#endif
082757af
DS		 7708void ixgbe_do_reset(struct net_device *netdev)
7709{
7710 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7711
7712 if (netif_running(netdev))
7713 ixgbe_reinit_locked(adapter);
7714 else
7715 ixgbe_reset(adapter);
7716}
7717
c8f44aff 7718static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7719 netdev_features_t features)
082757af
DS		 7720{
7721 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7722
082757af 7723 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7724 if (!(features & NETIF_F_RXCSUM))
7725 features &= ~NETIF_F_LRO;
082757af 7726
567d2de2
AD		 7727 /* Turn off LRO if not RSC capable */
7728 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7729 features &= ~NETIF_F_LRO;
8e2813f5 7730
567d2de2 7731 return features;
082757af
DS		 7732}
7733
c8f44aff 7734static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7735 netdev_features_t features)
082757af
DS		 7736{
7737 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7738 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7739 bool need_reset = false;
7740
082757af 7741 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7742 if (!(features & NETIF_F_LRO)) {
7743 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7744 need_reset = true;
567d2de2
AD		 7745 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7746 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7747 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7748 if (adapter->rx_itr_setting == 1 ||
7749 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7750 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7751 need_reset = true;
7752 } else if ((changed ^ features) & NETIF_F_LRO) {
7753 e_info(probe, "rx-usecs set too low, "
7754 "disabling RSC\n");
082757af
DS		 7755 }
7756 }
7757
7758 /*
7759 * Check if Flow Director n-tuple support was enabled or disabled. If
7760 * the state changed, we need to reset.
7761 */
39cb681b
AD		 7762 switch (features & NETIF_F_NTUPLE) {
7763 case NETIF_F_NTUPLE:
567d2de2 7764 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7765 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7766 need_reset = true;
7767
567d2de2
AD		 7768 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7769 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7770 break;
7771 default:
7772 /* turn off perfect filters, enable ATR and reset */
7773 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7774 need_reset = true;
7775
7776 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7777
7778 /* We cannot enable ATR if SR-IOV is enabled */
7779 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7780 break;
7781
7782 /* We cannot enable ATR if we have 2 or more traffic classes */
7783 if (netdev_get_num_tc(netdev) > 1)
7784 break;
7785
7786 /* We cannot enable ATR if RSS is disabled */
7787 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7788 break;
7789
7790 /* A sample rate of 0 indicates ATR disabled */
7791 if (!adapter->atr_sample_rate)
7792 break;
7793
7794 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7795 break;
082757af
DS		 7796 }
7797
f646968f 7798 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7799 ixgbe_vlan_strip_enable(adapter);
7800 else
7801 ixgbe_vlan_strip_disable(adapter);
7802
3f2d1c0f
BG		 7803 if (changed & NETIF_F_RXALL)
7804 need_reset = true;
7805
567d2de2 7806 netdev->features = features;
082757af
DS		 7807 if (need_reset)
7808 ixgbe_do_reset(netdev);
7809
7810 return 0;
082757af
DS		 7811}
7812
3f207800
DS		 7813/**
7814 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
7815 * @dev: The port's netdev
7816 * @sa_family: Socket Family that VXLAN is notifiying us about
7817 * @port: New UDP port number that VXLAN started listening to
7818 **/
7819static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
7820 __be16 port)
7821{
7822 struct ixgbe_adapter *adapter = netdev_priv(dev);
7823 struct ixgbe_hw *hw = &adapter->hw;
7824 u16 new_port = ntohs(port);
7825
7826 if (sa_family == AF_INET6)
7827 return;
7828
7829 if (adapter->vxlan_port == new_port) {
7830 netdev_info(dev, "Port %d already offloaded\n", new_port);
7831 return;
7832 }
7833
7834 if (adapter->vxlan_port) {
7835 netdev_info(dev,
7836 "Hit Max num of UDP ports, not adding port %d\n",
7837 new_port);
7838 return;
7839 }
7840
7841 adapter->vxlan_port = new_port;
7842 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
7843}
7844
7845/**
7846 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
7847 * @dev: The port's netdev
7848 * @sa_family: Socket Family that VXLAN is notifying us about
7849 * @port: UDP port number that VXLAN stopped listening to
7850 **/
7851static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
7852 __be16 port)
7853{
7854 struct ixgbe_adapter *adapter = netdev_priv(dev);
7855 struct ixgbe_hw *hw = &adapter->hw;
7856 u16 new_port = ntohs(port);
7857
7858 if (sa_family == AF_INET6)
7859 return;
7860
7861 if (adapter->vxlan_port != new_port) {
7862 netdev_info(dev, "Port %d was not found, not deleting\n",
7863 new_port);
7864 return;
7865 }
7866
7867 adapter->vxlan_port = 0;
7868 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 0);
7869}
7870
edc7d573 7871static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7872 struct net_device *dev,
f6f6424b 7873 const unsigned char *addr, u16 vid,
0f4b0add
JF		 7874 u16 flags)
7875{
bcfd3432 7876 /* guarantee we can provide a unique filter for the unicast address */
46acc460 7877 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 7878 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7879 return -ENOMEM;
0f4b0add
JF		 7880 }
7881
f6f6424b 7882 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 7883}
7884
815cccbf 7885static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 7886 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 7887{
7888 struct ixgbe_adapter *adapter = netdev_priv(dev);
7889 struct nlattr *attr, *br_spec;
7890 int rem;
7891
7892 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7893 return -EOPNOTSUPP;
7894
7895 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 7896 if (!br_spec)
7897 return -EINVAL;
815cccbf
JF		 7898
7899 nla_for_each_nested(attr, br_spec, rem) {
7900 __u16 mode;
7901 u32 reg = 0;
7902
7903 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7904 continue;
7905
b7c1a314
TG		 7906 if (nla_len(attr) < sizeof(mode))
7907 return -EINVAL;
7908
815cccbf 7909 mode = nla_get_u16(attr);
9b735984 7910 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7911 reg = 0;
9b735984
GR		 7912 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7913 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7914 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7915 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7916 } else
815cccbf
JF		 7917 return -EINVAL;
7918
7919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7920
7921 e_info(drv, "enabling bridge mode: %s\n",
7922 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7923 }
7924
7925 return 0;
7926}
7927
7928static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7929 struct net_device *dev,
7930 u32 filter_mask)
815cccbf
JF		 7931{
7932 struct ixgbe_adapter *adapter = netdev_priv(dev);
7933 u16 mode;
7934
7935 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7936 return 0;
7937
9b735984 7938 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7939 mode = BRIDGE_MODE_VEB;
7940 else
7941 mode = BRIDGE_MODE_VEPA;
7942
2c3c031c 7943 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0);
815cccbf
JF		 7944}
7945
2a47fa45
JF		 7946static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7947{
7948 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7949 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 7950 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 7951 unsigned int limit;
2a47fa45
JF		 7952 int pool, err;
7953
aac2f1bf
JK		 7954 /* Hardware has a limited number of available pools. Each VF, and the
7955 * PF require a pool. Check to ensure we don't attempt to use more
7956 * then the available number of pools.
7957 */
7958 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
7959 return ERR_PTR(-EINVAL);
7960
219354d4
JF		 7961#ifdef CONFIG_RPS
7962 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7963 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7964 vdev->name);
7965 return ERR_PTR(-EINVAL);
7966 }
7967#endif
2a47fa45 7968 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7969 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7970 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7971 netdev_info(pdev,
7972 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7973 pdev->name);
7974 return ERR_PTR(-EINVAL);
7975 }
7976
7977 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7978 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7979 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7980 return ERR_PTR(-EBUSY);
7981
7982 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7983 if (!fwd_adapter)
7984 return ERR_PTR(-ENOMEM);
7985
7986 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7987 adapter->num_rx_pools++;
7988 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7989 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7990
7991 /* Enable VMDq flag so device will be set in VM mode */
7992 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7993 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7994 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7995
7996 /* Force reinit of ring allocation with VMDQ enabled */
7997 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7998 if (err)
7999 goto fwd_add_err;
8000 fwd_adapter->pool = pool;
8001 fwd_adapter->real_adapter = adapter;
8002 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8003 if (err)
8004 goto fwd_add_err;
8005 netif_tx_start_all_queues(vdev);
8006 return fwd_adapter;
8007fwd_add_err:
8008 /* unwind counter and free adapter struct */
8009 netdev_info(pdev,
8010 "%s: dfwd hardware acceleration failed\n", vdev->name);
8011 clear_bit(pool, &adapter->fwd_bitmask);
8012 adapter->num_rx_pools--;
8013 kfree(fwd_adapter);
8014 return ERR_PTR(err);
8015}
8016
8017static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8018{
8019 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8020 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8021 unsigned int limit;
2a47fa45
JF		 8022
8023 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8024 adapter->num_rx_pools--;
8025
51f3773b
JF		 8026 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8027 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8028 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8029 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8030 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8031 fwd_adapter->pool, adapter->num_rx_pools,
8032 fwd_adapter->rx_base_queue,
8033 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8034 adapter->fwd_bitmask);
8035 kfree(fwd_adapter);
8036}
8037
0edc3527 8038static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8039 .ndo_open = ixgbe_open,
0edc3527 8040 .ndo_stop = ixgbe_close,
00829823 8041 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8042 .ndo_select_queue = ixgbe_select_queue,
581330ba 8043 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8044 .ndo_validate_addr = eth_validate_addr,
8045 .ndo_set_mac_address = ixgbe_set_mac,
8046 .ndo_change_mtu = ixgbe_change_mtu,
8047 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8048 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8049 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8050 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8051 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8052 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8053 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8054 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 8055 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8056 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8057#ifdef CONFIG_IXGBE_DCB
24095aa3 8058 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8059#endif
0edc3527
SH		 8060#ifdef CONFIG_NET_POLL_CONTROLLER
8061 .ndo_poll_controller = ixgbe_netpoll,
8062#endif
e0d1095a 8063#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8064 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8065#endif
332d4a7d
YZ		 8066#ifdef IXGBE_FCOE
8067 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8068 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8069 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8070 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8071 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8072 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8073 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8074#endif /* IXGBE_FCOE */
082757af
DS		 8075 .ndo_set_features = ixgbe_set_features,
8076 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8077 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8078 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8079 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8080 .ndo_dfwd_add_station = ixgbe_fwd_add,
8081 .ndo_dfwd_del_station = ixgbe_fwd_del,
3f207800
DS		 8082 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8083 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
0edc3527
SH		 8084};
8085
e027d1ae
JK		 8086/**
8087 * ixgbe_enumerate_functions - Get the number of ports this device has
8088 * @adapter: adapter structure
8089 *
8090 * This function enumerates the phsyical functions co-located on a single slot,
8091 * in order to determine how many ports a device has. This is most useful in
8092 * determining the required GT/s of PCIe bandwidth necessary for optimal
8093 * performance.
8094 **/
8095static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8096{
caafb95d 8097 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8098 int physfns = 0;
8099
f1f96579
JK		 8100 /* Some cards can not use the generic count PCIe functions method,
8101 * because they are behind a parent switch, so we hardcode these with
8102 * the correct number of functions.
e027d1ae 8103 */
8818970d 8104 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8105 physfns = 4;
8818970d
JK		 8106
8107 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8108 /* don't count virtual functions */
caafb95d
JK		 8109 if (entry->is_virtfn)
8110 continue;
8111
8112 /* When the devices on the bus don't all match our device ID,
8113 * we can't reliably determine the correct number of
8114 * functions. This can occur if a function has been direct
8115 * attached to a virtual machine using VT-d, for example. In
8116 * this case, simply return -1 to indicate this.
8117 */
8118 if ((entry->vendor != pdev->vendor) ||
8119 (entry->device != pdev->device))
8120 return -1;
8121
8122 physfns++;
e027d1ae
JK		 8123 }
8124
8125 return physfns;
8126}
8127
8e2813f5
JK		 8128/**
8129 * ixgbe_wol_supported - Check whether device supports WoL
8130 * @hw: hw specific details
8131 * @device_id: the device ID
8132 * @subdev_id: the subsystem device ID
8133 *
8134 * This function is used by probe and ethtool to determine
8135 * which devices have WoL support
8136 *
8137 **/
8138int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8139 u16 subdevice_id)
8140{
8141 struct ixgbe_hw *hw = &adapter->hw;
8142 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8143 int is_wol_supported = 0;
8144
8145 switch (device_id) {
8146 case IXGBE_DEV_ID_82599_SFP:
8147 /* Only these subdevices could supports WOL */
8148 switch (subdevice_id) {
87557440 8149 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8150 case IXGBE_SUBDEV_ID_82599_560FLR:
8151 /* only support first port */
8152 if (hw->bus.func != 0)
8153 break;
5700ff26 8154 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8155 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8156 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8157 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8158 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8159 is_wol_supported = 1;
8160 break;
8161 }
8162 break;
5daebbb0
DS		 8163 case IXGBE_DEV_ID_82599EN_SFP:
8164 /* Only this subdevice supports WOL */
8165 switch (subdevice_id) {
8166 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8167 is_wol_supported = 1;
8168 break;
8169 }
8170 break;
8e2813f5
JK		 8171 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8172 /* All except this subdevice support WOL */
8173 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8174 is_wol_supported = 1;
8175 break;
8176 case IXGBE_DEV_ID_82599_KX4:
8177 is_wol_supported = 1;
8178 break;
8179 case IXGBE_DEV_ID_X540T:
df376f0d 8180 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 8181 /* check eeprom to see if enabled wol */
8182 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8183 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8184 (hw->bus.func == 0))) {
8185 is_wol_supported = 1;
8186 }
8187 break;
8188 }
8189
8190 return is_wol_supported;
8191}
8192
c762dff2
MP		 8193/**
8194 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8195 * @adapter: Pointer to adapter struct
8196 */
8197static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8198{
8199#ifdef CONFIG_OF
8200 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8201 struct ixgbe_hw *hw = &adapter->hw;
8202 const unsigned char *addr;
8203
8204 addr = of_get_mac_address(dp);
8205 if (addr) {
8206 ether_addr_copy(hw->mac.perm_addr, addr);
8207 return;
8208 }
8209#endif /* CONFIG_OF */
8210
8211#ifdef CONFIG_SPARC
8212 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8213#endif /* CONFIG_SPARC */
8214}
8215
9a799d71
AK		 8216/**
8217 * ixgbe_probe - Device Initialization Routine
8218 * @pdev: PCI device information struct
8219 * @ent: entry in ixgbe_pci_tbl
8220 *
8221 * Returns 0 on success, negative on failure
8222 *
8223 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8224 * The OS initialization, configuring of the adapter private structure,
8225 * and a hardware reset occur.
8226 **/
1dd06ae8 8227static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8228{
8229 struct net_device *netdev;
8230 struct ixgbe_adapter *adapter = NULL;
8231 struct ixgbe_hw *hw;
8232 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8233 int i, err, pci_using_dac, expected_gts;
d3cb9869 8234 unsigned int indices = MAX_TX_QUEUES;
289700db 8235 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8236 bool disable_dev = false;
eacd73f7
YZ		 8237#ifdef IXGBE_FCOE
8238 u16 device_caps;
8239#endif
289700db 8240 u32 eec;
9a799d71 8241
bded64a7
AG		 8242 /* Catch broken hardware that put the wrong VF device ID in
8243 * the PCIe SR-IOV capability.
8244 */
8245 if (pdev->is_virtfn) {
8246 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8247 pci_name(pdev), pdev->vendor, pdev->device);
8248 return -EINVAL;
8249 }
8250
9ce77666 8251 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8252 if (err)
8253 return err;
8254
f5f2eda8 8255 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8256 pci_using_dac = 1;
8257 } else {
f5f2eda8 8258 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8259 if (err) {
f5f2eda8
RK		 8260 dev_err(&pdev->dev,
8261 "No usable DMA configuration, aborting\n");
8262 goto err_dma;
9a799d71
AK		 8263 }
8264 pci_using_dac = 0;
8265 }
8266
9ce77666 8267 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8268 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8269 if (err) {
b8bc0421
DC		 8270 dev_err(&pdev->dev,
8271 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8272 goto err_pci_reg;
8273 }
8274
19d5afd4 8275 pci_enable_pcie_error_reporting(pdev);
6fabd715 8276
9a799d71 8277 pci_set_master(pdev);
fb3b27bc 8278 pci_save_state(pdev);
9a799d71 8279
d3cb9869 8280 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8281#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8282 /* 8 TC w/ 4 queues per TC */
8283 indices = 4 * MAX_TRAFFIC_CLASS;
8284#else
8285 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8286#endif
d3cb9869 8287 }
e901acd6 8288
c85a2618 8289 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8290 if (!netdev) {
8291 err = -ENOMEM;
8292 goto err_alloc_etherdev;
8293 }
8294
9a799d71
AK		 8295 SET_NETDEV_DEV(netdev, &pdev->dev);
8296
9a799d71
AK		 8297 adapter = netdev_priv(netdev);
8298
8299 adapter->netdev = netdev;
8300 adapter->pdev = pdev;
8301 hw = &adapter->hw;
8302 hw->back = adapter;
b3f4d599 8303 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8304
05857980 8305 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8306 pci_resource_len(pdev, 0));
2a1a091c 8307 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8308 if (!hw->hw_addr) {
8309 err = -EIO;
8310 goto err_ioremap;
8311 }
8312
0edc3527 8313 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8314 ixgbe_set_ethtool_ops(netdev);
9a799d71 8315 netdev->watchdog_timeo = 5 * HZ;
339de30f 8316 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8317
9a799d71
AK		 8318 /* Setup hw api */
8319 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8320 hw->mac.type = ii->mac;
9a799d71 8321
c44ade9e
JB		 8322 /* EEPROM */
8323 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8324 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8325 if (ixgbe_removed(hw->hw_addr)) {
8326 err = -EIO;
8327 goto err_ioremap;
8328 }
c44ade9e
JB		 8329 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8330 if (!(eec & (1 << 8)))
8331 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8332
8333 /* PHY */
8334 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8335 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8336 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8337 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8338 hw->phy.mdio.mmds = 0;
8339 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8340 hw->phy.mdio.dev = netdev;
8341 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8342 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8343
8ca783ab 8344 ii->get_invariants(hw);
9a799d71
AK		 8345
8346 /* setup the private structure */
8347 err = ixgbe_sw_init(adapter);
8348 if (err)
8349 goto err_sw_init;
8350
e86bff0e 8351 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8352 switch (adapter->hw.mac.type) {
8353 case ixgbe_mac_82599EB:
8354 case ixgbe_mac_X540:
9a75a1ac
DS		 8355 case ixgbe_mac_X550:
8356 case ixgbe_mac_X550EM_x:
e86bff0e 8357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8358 break;
8359 default:
8360 break;
8361 }
e86bff0e 8362
bf069c97
DS		 8363 /*
8364 * If there is a fan on this device and it has failed log the
8365 * failure.
8366 */
8367 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8368 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8369 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8370 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8371 }
8372
8ef78adc
PWJ		 8373 if (allow_unsupported_sfp)
8374 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8375
c44ade9e 8376 /* reset_hw fills in the perm_addr as well */
119fc60a 8377 hw->phy.reset_if_overtemp = true;
c44ade9e 8378 err = hw->mac.ops.reset_hw(hw);
119fc60a 8379 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8380 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8381 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8382 err = 0;
8383 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8384 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8385 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8386 goto err_sw_init;
8387 } else if (err) {
849c4542 8388 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8389 goto err_sw_init;
8390 }
8391
99d74487 8392#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8393 /* SR-IOV not supported on the 82598 */
8394 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8395 goto skip_sriov;
8396 /* Mailbox */
8397 ixgbe_init_mbx_params_pf(hw);
8398 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8399 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8400 ixgbe_enable_sriov(adapter);
60a1a680 8401skip_sriov:
1cdd1ec8 8402
99d74487 8403#endif
396e799c 8404 netdev->features = NETIF_F_SG |
e8e9f696 8405 NETIF_F_IP_CSUM |
082757af 8406 NETIF_F_IPV6_CSUM |
f646968f
PM		 8407 NETIF_F_HW_VLAN_CTAG_TX |
8408 NETIF_F_HW_VLAN_CTAG_RX |
8409 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8410 NETIF_F_TSO |
8411 NETIF_F_TSO6 |
082757af 8412 NETIF_F_RXHASH |
8bf1264d 8413 NETIF_F_RXCSUM;
9a799d71 8414
8bf1264d 8415 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8416
58be7666
DS		 8417 switch (adapter->hw.mac.type) {
8418 case ixgbe_mac_82599EB:
8419 case ixgbe_mac_X540:
9a75a1ac
DS		 8420 case ixgbe_mac_X550:
8421 case ixgbe_mac_X550EM_x:
45a5ead0 8422 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8423 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8424 NETIF_F_NTUPLE;
58be7666
DS		 8425 break;
8426 default:
8427 break;
8428 }
45a5ead0 8429
3f2d1c0f
BG		 8430 netdev->hw_features |= NETIF_F_RXALL;
8431
ad31c402
JK		 8432 netdev->vlan_features |= NETIF_F_TSO;
8433 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8434 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8435 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8436 netdev->vlan_features |= NETIF_F_SG;
8437
01789349 8438 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8439 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8440
3f207800
DS		 8441 switch (adapter->hw.mac.type) {
8442 case ixgbe_mac_X550:
8443 case ixgbe_mac_X550EM_x:
8444 netdev->hw_enc_features |= NETIF_F_RXCSUM;
8445 break;
8446 default:
8447 break;
8448 }
8449
7a6b6f51 8450#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8451 netdev->dcbnl_ops = &dcbnl_ops;
8452#endif
8453
eacd73f7 8454#ifdef IXGBE_FCOE
0d551589 8455 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8456 unsigned int fcoe_l;
8457
eacd73f7
YZ		 8458 if (hw->mac.ops.get_device_caps) {
8459 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8460 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8461 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8462 }
7c8ae65a 8463
d3cb9869
AD		 8464
8465 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8466 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8467
a58915c7
AD		 8468 netdev->features |= NETIF_F_FSO |
8469 NETIF_F_FCOE_CRC;
8470
7c8ae65a
AD		 8471 netdev->vlan_features |= NETIF_F_FSO |
8472 NETIF_F_FCOE_CRC |
8473 NETIF_F_FCOE_MTU;
5e09d7f6 8474 }
eacd73f7 8475#endif /* IXGBE_FCOE */
7b872a55 8476 if (pci_using_dac) {
9a799d71 8477 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8478 netdev->vlan_features |= NETIF_F_HIGHDMA;
8479 }
9a799d71 8480
082757af
DS		 8481 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8482 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8483 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8484 netdev->features |= NETIF_F_LRO;
8485
9a799d71 8486 /* make sure the EEPROM is good */
c44ade9e 8487 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8488 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8489 err = -EIO;
35937c05 8490 goto err_sw_init;
9a799d71
AK		 8491 }
8492
c762dff2
MP		 8493 ixgbe_get_platform_mac_addr(adapter);
8494
9a799d71 8495 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8496
aaeb6cdf 8497 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8498 e_dev_err("invalid MAC address\n");
9a799d71 8499 err = -EIO;
35937c05 8500 goto err_sw_init;
9a799d71
AK		 8501 }
8502
5d7daa35
JK		 8503 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8504
7086400d 8505 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8506 (unsigned long) adapter);
9a799d71 8507
58cf663f
MR		 8508 if (ixgbe_removed(hw->hw_addr)) {
8509 err = -EIO;
8510 goto err_sw_init;
8511 }
7086400d 8512 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8513 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8514 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8515
021230d4
AV		 8516 err = ixgbe_init_interrupt_scheme(adapter);
8517 if (err)
8518 goto err_sw_init;
9a799d71 8519
8e2813f5 8520 /* WOL not supported for all devices */
c23f5b6b 8521 adapter->wol = 0;
8e2813f5 8522 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8523 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8524 pdev->subsystem_device);
6b92b0ba 8525 if (hw->wol_enabled)
9417c464 8526 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8527
e8e26350
PW		 8528 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8529
15e5209f
ET		 8530 /* save off EEPROM version number */
8531 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8532 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8533
04f165ef
PW		 8534 /* pick up the PCI bus settings for reporting later */
8535 hw->mac.ops.get_bus_info(hw);
e027d1ae 8536 if (ixgbe_pcie_from_parent(hw))
b8e82001 8537 ixgbe_get_parent_bus_info(adapter);
04f165ef 8538
e027d1ae
JK		 8539 /* calculate the expected PCIe bandwidth required for optimal
8540 * performance. Note that some older parts will never have enough
8541 * bandwidth due to being older generation PCIe parts. We clamp these
8542 * parts to ensure no warning is displayed if it can't be fixed.
8543 */
8544 switch (hw->mac.type) {
8545 case ixgbe_mac_82598EB:
8546 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8547 break;
8548 default:
8549 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8550 break;
0c254d86 8551 }
caafb95d
JK		 8552
8553 /* don't check link if we failed to enumerate functions */
8554 if (expected_gts > 0)
8555 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8556
339de30f 8557 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8558 if (err)
339de30f 8559 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8560 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8561 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8562 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8563 part_str);
6a2aae5a
JK		 8564 else
8565 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8566 hw->mac.type, hw->phy.type, part_str);
8567
8568 e_dev_info("%pM\n", netdev->dev_addr);
8569
9a799d71 8570 /* reset the hardware with the new settings */
794caeb2 8571 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8572 if (err == IXGBE_ERR_EEPROM_VERSION) {
8573 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8574 e_dev_warn("This device is a pre-production adapter/LOM. "
8575 "Please be aware there may be issues associated "
8576 "with your hardware. If you are experiencing "
8577 "problems please contact your Intel or hardware "
8578 "representative who provided you with this "
8579 "hardware.\n");
794caeb2 8580 }
9a799d71
AK		 8581 strcpy(netdev->name, "eth%d");
8582 err = register_netdev(netdev);
8583 if (err)
8584 goto err_register;
8585
0fb6a55c
ET		 8586 pci_set_drvdata(pdev, adapter);
8587
ec74a471
ET		 8588 /* power down the optics for 82599 SFP+ fiber */
8589 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8590 hw->mac.ops.disable_tx_laser(hw);
8591
54386467
JB		 8592 /* carrier off reporting is important to ethtool even BEFORE open */
8593 netif_carrier_off(netdev);
8594
5dd2d332 8595#ifdef CONFIG_IXGBE_DCA
652f093f 8596 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8597 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8598 ixgbe_setup_dca(adapter);
8599 }
8600#endif
1cdd1ec8 8601 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8602 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8603 for (i = 0; i < adapter->num_vfs; i++)
8604 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8605 }
8606
2466dd9c
JK		 8607 /* firmware requires driver version to be 0xFFFFFFFF
8608 * since os does not support feature
8609 */
9612de92 8610 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8611 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8612 0xFF);
9612de92 8613
0365e6e4
PW		 8614 /* add san mac addr to netdev */
8615 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8616
ea81875a 8617 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8618
1210982b 8619#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8620 if (ixgbe_sysfs_init(adapter))
8621 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8622#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8623
00949167 8624 ixgbe_dbg_adapter_init(adapter);
00949167 8625
d1a35ee2
ET		 8626 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8627 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8628 hw->mac.ops.setup_link(hw,
8629 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8630 true);
8631
9a799d71
AK		 8632 return 0;
8633
8634err_register:
5eba3699 8635 ixgbe_release_hw_control(adapter);
7a921c93 8636 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8637err_sw_init:
99d74487 8638 ixgbe_disable_sriov(adapter);
7086400d 8639 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8640 iounmap(adapter->io_addr);
5d7daa35 8641 kfree(adapter->mac_table);
9a799d71 8642err_ioremap:
b5b2ffc0 8643 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8644 free_netdev(netdev);
8645err_alloc_etherdev:
e8e9f696
JP		 8646 pci_release_selected_regions(pdev,
8647 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8648err_pci_reg:
8649err_dma:
b5b2ffc0 8650 if (!adapter || disable_dev)
41c62843 8651 pci_disable_device(pdev);
9a799d71
AK		 8652 return err;
8653}
8654
8655/**
8656 * ixgbe_remove - Device Removal Routine
8657 * @pdev: PCI device information struct
8658 *
8659 * ixgbe_remove is called by the PCI subsystem to alert the driver
8660 * that it should release a PCI device. The could be caused by a
8661 * Hot-Plug event, or because the driver is going to be removed from
8662 * memory.
8663 **/
9f9a12f8 8664static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8665{
c60fbb00 8666 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 8667 struct net_device *netdev;
b5b2ffc0 8668 bool disable_dev;
9a799d71 8669
0fb6a55c
ET		 8670 /* if !adapter then we already cleaned up in probe */
8671 if (!adapter)
8672 return;
8673
8674 netdev = adapter->netdev;
00949167 8675 ixgbe_dbg_adapter_exit(adapter);
00949167 8676
09f40aed 8677 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8678 cancel_work_sync(&adapter->service_task);
9a799d71 8679
3a6a4eda 8680
5dd2d332 8681#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8682 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8683 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8684 dca_remove_requester(&pdev->dev);
8685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8686 }
8687
8688#endif
1210982b 8689#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8690 ixgbe_sysfs_exit(adapter);
1210982b 8691#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8692
0365e6e4
PW		 8693 /* remove the added san mac */
8694 ixgbe_del_sanmac_netdev(netdev);
8695
c4900be0
DS		 8696 if (netdev->reg_state == NETREG_REGISTERED)
8697 unregister_netdev(netdev);
9a799d71 8698
da36b647
GR		 8699#ifdef CONFIG_PCI_IOV
8700 /*
8701 * Only disable SR-IOV on unload if the user specified the now
8702 * deprecated max_vfs module parameter.
8703 */
8704 if (max_vfs)
8705 ixgbe_disable_sriov(adapter);
8706#endif
7a921c93 8707 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8708
021230d4 8709 ixgbe_release_hw_control(adapter);
9a799d71 8710
2b1588c3
AD		 8711#ifdef CONFIG_DCB
8712 kfree(adapter->ixgbe_ieee_pfc);
8713 kfree(adapter->ixgbe_ieee_ets);
8714
8715#endif
2a1a091c 8716 iounmap(adapter->io_addr);
9ce77666 8717 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8718 IORESOURCE_MEM));
9a799d71 8719
849c4542 8720 e_dev_info("complete\n");
021230d4 8721
5d7daa35 8722 kfree(adapter->mac_table);
b5b2ffc0 8723 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8724 free_netdev(netdev);
8725
19d5afd4 8726 pci_disable_pcie_error_reporting(pdev);
6fabd715 8727
b5b2ffc0 8728 if (disable_dev)
41c62843 8729 pci_disable_device(pdev);
9a799d71
AK		 8730}
8731
8732/**
8733 * ixgbe_io_error_detected - called when PCI error is detected
8734 * @pdev: Pointer to PCI device
8735 * @state: The current pci connection state
8736 *
8737 * This function is called after a PCI bus error affecting
8738 * this device has been detected.
8739 */
8740static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8741 pci_channel_state_t state)
9a799d71 8742{
c60fbb00
AD		 8743 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8744 struct net_device *netdev = adapter->netdev;
9a799d71 8745
83c61fa9 8746#ifdef CONFIG_PCI_IOV
14438464 8747 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8748 struct pci_dev *bdev, *vfdev;
8749 u32 dw0, dw1, dw2, dw3;
8750 int vf, pos;
8751 u16 req_id, pf_func;
8752
8753 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8754 adapter->num_vfs == 0)
8755 goto skip_bad_vf_detection;
8756
8757 bdev = pdev->bus->self;
62f87c0e 8758 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8759 bdev = bdev->bus->self;
8760
8761 if (!bdev)
8762 goto skip_bad_vf_detection;
8763
8764 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8765 if (!pos)
8766 goto skip_bad_vf_detection;
8767
14438464
MR		 8768 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8769 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8770 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8771 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8772 if (ixgbe_removed(hw->hw_addr))
8773 goto skip_bad_vf_detection;
83c61fa9
GR		 8774
8775 req_id = dw1 >> 16;
8776 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8777 if (!(req_id & 0x0080))
8778 goto skip_bad_vf_detection;
8779
8780 pf_func = req_id & 0x01;
8781 if ((pf_func & 1) == (pdev->devfn & 1)) {
8782 unsigned int device_id;
8783
8784 vf = (req_id & 0x7F) >> 1;
8785 e_dev_err("VF %d has caused a PCIe error\n", vf);
8786 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8787 "%8.8x\tdw3: %8.8x\n",
8788 dw0, dw1, dw2, dw3);
8789 switch (adapter->hw.mac.type) {
8790 case ixgbe_mac_82599EB:
8791 device_id = IXGBE_82599_VF_DEVICE_ID;
8792 break;
8793 case ixgbe_mac_X540:
8794 device_id = IXGBE_X540_VF_DEVICE_ID;
8795 break;
9a75a1ac
DS		 8796 case ixgbe_mac_X550:
8797 device_id = IXGBE_DEV_ID_X550_VF;
8798 break;
8799 case ixgbe_mac_X550EM_x:
8800 device_id = IXGBE_DEV_ID_X550EM_X_VF;
8801 break;
83c61fa9
GR		 8802 default:
8803 device_id = 0;
8804 break;
8805 }
8806
8807 /* Find the pci device of the offending VF */
36e90319 8808 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8809 while (vfdev) {
8810 if (vfdev->devfn == (req_id & 0xFF))
8811 break;
36e90319 8812 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8813 device_id, vfdev);
8814 }
8815 /*
8816 * There's a slim chance the VF could have been hot plugged,
8817 * so if it is no longer present we don't need to issue the
8818 * VFLR. Just clean up the AER in that case.
8819 */
8820 if (vfdev) {
9079e416 8821 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 8822 /* Free device reference count */
8823 pci_dev_put(vfdev);
83c61fa9
GR		 8824 }
8825
8826 pci_cleanup_aer_uncorrect_error_status(pdev);
8827 }
8828
8829 /*
8830 * Even though the error may have occurred on the other port
8831 * we still need to increment the vf error reference count for
8832 * both ports because the I/O resume function will be called
8833 * for both of them.
8834 */
8835 adapter->vferr_refcount++;
8836
8837 return PCI_ERS_RESULT_RECOVERED;
8838
8839skip_bad_vf_detection:
8840#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8841 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8842 return PCI_ERS_RESULT_DISCONNECT;
8843
41c62843 8844 rtnl_lock();
9a799d71
AK		 8845 netif_device_detach(netdev);
8846
41c62843
MR		 8847 if (state == pci_channel_io_perm_failure) {
8848 rtnl_unlock();
3044b8d1 8849 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8850 }
3044b8d1 8851
9a799d71
AK		 8852 if (netif_running(netdev))
8853 ixgbe_down(adapter);
41c62843
MR		 8854
8855 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8856 pci_disable_device(pdev);
8857 rtnl_unlock();
9a799d71 8858
b4617240 8859 /* Request a slot reset. */
9a799d71
AK		 8860 return PCI_ERS_RESULT_NEED_RESET;
8861}
8862
8863/**
8864 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8865 * @pdev: Pointer to PCI device
8866 *
8867 * Restart the card from scratch, as if from a cold-boot.
8868 */
8869static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8870{
c60fbb00 8871 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8872 pci_ers_result_t result;
8873 int err;
9a799d71 8874
9ce77666 8875 if (pci_enable_device_mem(pdev)) {
396e799c 8876 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8877 result = PCI_ERS_RESULT_DISCONNECT;
8878 } else {
4e857c58 8879 smp_mb__before_atomic();
41c62843 8880 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8881 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8882 pci_set_master(pdev);
8883 pci_restore_state(pdev);
c0e1f68b 8884 pci_save_state(pdev);
9a799d71 8885
dd4d8ca6 8886 pci_wake_from_d3(pdev, false);
9a799d71 8887
6fabd715 8888 ixgbe_reset(adapter);
88512539 8889 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8890 result = PCI_ERS_RESULT_RECOVERED;
8891 }
8892
8893 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8894 if (err) {
849c4542
ET		 8895 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8896 "failed 0x%0x\n", err);
6fabd715
PWJ		 8897 /* non-fatal, continue */
8898 }
9a799d71 8899
6fabd715 8900 return result;
9a799d71
AK		 8901}
8902
8903/**
8904 * ixgbe_io_resume - called when traffic can start flowing again.
8905 * @pdev: Pointer to PCI device
8906 *
8907 * This callback is called when the error recovery driver tells us that
8908 * its OK to resume normal operation.
8909 */
8910static void ixgbe_io_resume(struct pci_dev *pdev)
8911{
c60fbb00
AD		 8912 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8913 struct net_device *netdev = adapter->netdev;
9a799d71 8914
83c61fa9
GR		 8915#ifdef CONFIG_PCI_IOV
8916 if (adapter->vferr_refcount) {
8917 e_info(drv, "Resuming after VF err\n");
8918 adapter->vferr_refcount--;
8919 return;
8920 }
8921
8922#endif
c7ccde0f
AD		 8923 if (netif_running(netdev))
8924 ixgbe_up(adapter);
9a799d71
AK		 8925
8926 netif_device_attach(netdev);
9a799d71
AK		 8927}
8928
3646f0e5 8929static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8930 .error_detected = ixgbe_io_error_detected,
8931 .slot_reset = ixgbe_io_slot_reset,
8932 .resume = ixgbe_io_resume,
8933};
8934
8935static struct pci_driver ixgbe_driver = {
8936 .name = ixgbe_driver_name,
8937 .id_table = ixgbe_pci_tbl,
8938 .probe = ixgbe_probe,
9f9a12f8 8939 .remove = ixgbe_remove,
9a799d71
AK		 8940#ifdef CONFIG_PM
8941 .suspend = ixgbe_suspend,
8942 .resume = ixgbe_resume,
8943#endif
8944 .shutdown = ixgbe_shutdown,
da36b647 8945 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8946 .err_handler = &ixgbe_err_handler
8947};
8948
8949/**
8950 * ixgbe_init_module - Driver Registration Routine
8951 *
8952 * ixgbe_init_module is the first routine called when the driver is
8953 * loaded. All it does is register with the PCI subsystem.
8954 **/
8955static int __init ixgbe_init_module(void)
8956{
8957 int ret;
c7689578 8958 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8959 pr_info("%s\n", ixgbe_copyright);
9a799d71 8960
00949167 8961 ixgbe_dbg_init();
00949167 8962
f01fc1a8
JK		 8963 ret = pci_register_driver(&ixgbe_driver);
8964 if (ret) {
f01fc1a8 8965 ixgbe_dbg_exit();
f01fc1a8
JK		 8966 return ret;
8967 }
8968
5dd2d332 8969#ifdef CONFIG_IXGBE_DCA
bd0362dd 8970 dca_register_notify(&dca_notifier);
bd0362dd 8971#endif
5dd2d332 8972
f01fc1a8 8973 return 0;
9a799d71 8974}
b4617240 8975
9a799d71
AK		 8976module_init(ixgbe_init_module);
8977
8978/**
8979 * ixgbe_exit_module - Driver Exit Cleanup Routine
8980 *
8981 * ixgbe_exit_module is called just before the driver is removed
8982 * from memory.
8983 **/
8984static void __exit ixgbe_exit_module(void)
8985{
5dd2d332 8986#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8987 dca_unregister_notify(&dca_notifier);
8988#endif
9a799d71 8989 pci_unregister_driver(&ixgbe_driver);
00949167 8990
00949167 8991 ixgbe_dbg_exit();
00949167 8992
1a51502b 8993 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8994}
bd0362dd 8995
5dd2d332 8996#ifdef CONFIG_IXGBE_DCA
bd0362dd 8997static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8998 void *p)
bd0362dd
JC		 8999{
9000 int ret_val;
9001
9002 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9003 __ixgbe_notify_dca);
bd0362dd
JC		 9004
9005 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9006}
b453368d 9007
5dd2d332 9008#endif /* CONFIG_IXGBE_DCA */
849c4542 9009
9a799d71
AK		 9010module_exit(ixgbe_exit_module);
9011
9012/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)