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net: set and query VEB/VEPA bridge mode via PF_BRIDGE
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
6b42a9c5 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
7086400d
AD		 155static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
156{
157 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
158 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
159 schedule_work(&adapter->service_task);
160}
161
162static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
163{
164 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
165
52f33af8 166 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 167 smp_mb__before_clear_bit();
168 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
169}
170
dcd79aeb
TI		 171struct ixgbe_reg_info {
172 u32 ofs;
173 char *name;
174};
175
176static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
177
178 /* General Registers */
179 {IXGBE_CTRL, "CTRL"},
180 {IXGBE_STATUS, "STATUS"},
181 {IXGBE_CTRL_EXT, "CTRL_EXT"},
182
183 /* Interrupt Registers */
184 {IXGBE_EICR, "EICR"},
185
186 /* RX Registers */
187 {IXGBE_SRRCTL(0), "SRRCTL"},
188 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
189 {IXGBE_RDLEN(0), "RDLEN"},
190 {IXGBE_RDH(0), "RDH"},
191 {IXGBE_RDT(0), "RDT"},
192 {IXGBE_RXDCTL(0), "RXDCTL"},
193 {IXGBE_RDBAL(0), "RDBAL"},
194 {IXGBE_RDBAH(0), "RDBAH"},
195
196 /* TX Registers */
197 {IXGBE_TDBAL(0), "TDBAL"},
198 {IXGBE_TDBAH(0), "TDBAH"},
199 {IXGBE_TDLEN(0), "TDLEN"},
200 {IXGBE_TDH(0), "TDH"},
201 {IXGBE_TDT(0), "TDT"},
202 {IXGBE_TXDCTL(0), "TXDCTL"},
203
204 /* List Terminator */
205 {}
206};
207
208
209/*
210 * ixgbe_regdump - register printout routine
211 */
212static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
213{
214 int i = 0, j = 0;
215 char rname[16];
216 u32 regs[64];
217
218 switch (reginfo->ofs) {
219 case IXGBE_SRRCTL(0):
220 for (i = 0; i < 64; i++)
221 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
222 break;
223 case IXGBE_DCA_RXCTRL(0):
224 for (i = 0; i < 64; i++)
225 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
226 break;
227 case IXGBE_RDLEN(0):
228 for (i = 0; i < 64; i++)
229 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
230 break;
231 case IXGBE_RDH(0):
232 for (i = 0; i < 64; i++)
233 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
234 break;
235 case IXGBE_RDT(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
238 break;
239 case IXGBE_RXDCTL(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
242 break;
243 case IXGBE_RDBAL(0):
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
246 break;
247 case IXGBE_RDBAH(0):
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
250 break;
251 case IXGBE_TDBAL(0):
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
254 break;
255 case IXGBE_TDBAH(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
258 break;
259 case IXGBE_TDLEN(0):
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
262 break;
263 case IXGBE_TDH(0):
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
266 break;
267 case IXGBE_TDT(0):
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
270 break;
271 case IXGBE_TXDCTL(0):
272 for (i = 0; i < 64; i++)
273 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
274 break;
275 default:
c7689578 276 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 277 IXGBE_READ_REG(hw, reginfo->ofs));
278 return;
279 }
280
281 for (i = 0; i < 8; i++) {
282 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 283 pr_err("%-15s", rname);
dcd79aeb 284 for (j = 0; j < 8; j++)
c7689578
JP		 285 pr_cont(" %08x", regs[i*8+j]);
286 pr_cont("\n");
dcd79aeb
TI		 287 }
288
289}
290
291/*
292 * ixgbe_dump - Print registers, tx-rings and rx-rings
293 */
294static void ixgbe_dump(struct ixgbe_adapter *adapter)
295{
296 struct net_device *netdev = adapter->netdev;
297 struct ixgbe_hw *hw = &adapter->hw;
298 struct ixgbe_reg_info *reginfo;
299 int n = 0;
300 struct ixgbe_ring *tx_ring;
729739b7 301 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 302 union ixgbe_adv_tx_desc *tx_desc;
303 struct my_u0 { u64 a; u64 b; } *u0;
304 struct ixgbe_ring *rx_ring;
305 union ixgbe_adv_rx_desc *rx_desc;
306 struct ixgbe_rx_buffer *rx_buffer_info;
307 u32 staterr;
308 int i = 0;
309
310 if (!netif_msg_hw(adapter))
311 return;
312
313 /* Print netdevice Info */
314 if (netdev) {
315 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 316 pr_info("Device Name state "
dcd79aeb 317 "trans_start last_rx\n");
c7689578
JP		 318 pr_info("%-15s %016lX %016lX %016lX\n",
319 netdev->name,
320 netdev->state,
321 netdev->trans_start,
322 netdev->last_rx);
dcd79aeb
TI		 323 }
324
325 /* Print Registers */
326 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 327 pr_info(" Register Name Value\n");
dcd79aeb
TI		 328 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
329 reginfo->name; reginfo++) {
330 ixgbe_regdump(hw, reginfo);
331 }
332
333 /* Print TX Ring Summary */
334 if (!netdev || !netif_running(netdev))
335 goto exit;
336
337 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 338 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 339 for (n = 0; n < adapter->num_tx_queues; n++) {
340 tx_ring = adapter->tx_ring[n];
729739b7 341 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 342 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 343 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 344 (u64)dma_unmap_addr(tx_buffer, dma),
345 dma_unmap_len(tx_buffer, len),
346 tx_buffer->next_to_watch,
347 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 348 }
349
350 /* Print TX Rings */
351 if (!netif_msg_tx_done(adapter))
352 goto rx_ring_summary;
353
354 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
355
356 /* Transmit Descriptor Formats
357 *
358 * Advanced Transmit Descriptor
359 * +--------------------------------------------------------------+
360 * 0 | Buffer Address [63:0] |
361 * +--------------------------------------------------------------+
362 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
363 * +--------------------------------------------------------------+
364 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
365 */
366
367 for (n = 0; n < adapter->num_tx_queues; n++) {
368 tx_ring = adapter->tx_ring[n];
c7689578
JP		 369 pr_info("------------------------------------\n");
370 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
371 pr_info("------------------------------------\n");
372 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 373 "[PlPOIdStDDt Ln] [bi->dma ] "
374 "leng ntw timestamp bi->skb\n");
375
376 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 377 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 378 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 379 u0 = (struct my_u0 *)tx_desc;
c7689578 380 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 381 " %04X %p %016llX %p", i,
dcd79aeb
TI		 382 le64_to_cpu(u0->a),
383 le64_to_cpu(u0->b),
729739b7
AD		 384 (u64)dma_unmap_addr(tx_buffer, dma),
385 dma_unmap_len(tx_buffer, len),
386 tx_buffer->next_to_watch,
387 (u64)tx_buffer->time_stamp,
388 tx_buffer->skb);
dcd79aeb
TI		 389 if (i == tx_ring->next_to_use &&
390 i == tx_ring->next_to_clean)
c7689578 391 pr_cont(" NTC/U\n");
dcd79aeb 392 else if (i == tx_ring->next_to_use)
c7689578 393 pr_cont(" NTU\n");
dcd79aeb 394 else if (i == tx_ring->next_to_clean)
c7689578 395 pr_cont(" NTC\n");
dcd79aeb 396 else
c7689578 397 pr_cont("\n");
dcd79aeb
TI		 398
399 if (netif_msg_pktdata(adapter) &&
9c50c035 400 tx_buffer->skb)
dcd79aeb
TI		 401 print_hex_dump(KERN_INFO, "",
402 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035 403 tx_buffer->skb->data,
729739b7
AD		 404 dma_unmap_len(tx_buffer, len),
405 true);
dcd79aeb
TI		 406 }
407 }
408
409 /* Print RX Rings Summary */
410rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 412 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
c7689578
JP		 415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
c7689578
JP		 447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
c7689578 453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
c7689578 464 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
c7689578 470 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
9c50c035
ET		 477 if (netif_msg_pktdata(adapter) &&
478 rx_buffer_info->dma) {
dcd79aeb
TI		 479 print_hex_dump(KERN_INFO, "",
480 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 481 page_address(rx_buffer_info->page) +
482 rx_buffer_info->page_offset,
f800326d 483 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 484 }
485 }
486
487 if (i == rx_ring->next_to_use)
c7689578 488 pr_cont(" NTU\n");
dcd79aeb 489 else if (i == rx_ring->next_to_clean)
c7689578 490 pr_cont(" NTC\n");
dcd79aeb 491 else
c7689578 492 pr_cont("\n");
dcd79aeb
TI		 493
494 }
495 }
496
497exit:
498 return;
499}
500
5eba3699
AV		 501static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
502{
503 u32 ctrl_ext;
504
505 /* Let firmware take over control of h/w */
506 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
507 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 508 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 509}
510
511static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
512{
513 u32 ctrl_ext;
514
515 /* Let firmware know the driver has taken over */
516 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
517 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 518 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 519}
9a799d71 520
49ce9c2c 521/**
e8e26350
PW		 522 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
523 * @adapter: pointer to adapter struct
524 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
525 * @queue: queue to map the corresponding interrupt to
526 * @msix_vector: the vector to map to the corresponding queue
527 *
528 */
529static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 530 u8 queue, u8 msix_vector)
9a799d71
AK		 531{
532 u32 ivar, index;
e8e26350
PW		 533 struct ixgbe_hw *hw = &adapter->hw;
534 switch (hw->mac.type) {
535 case ixgbe_mac_82598EB:
536 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
537 if (direction == -1)
538 direction = 0;
539 index = (((direction * 64) + queue) >> 2) & 0x1F;
540 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
541 ivar &= ~(0xFF << (8 * (queue & 0x3)));
542 ivar |= (msix_vector << (8 * (queue & 0x3)));
543 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
544 break;
545 case ixgbe_mac_82599EB:
b93a2226 546 case ixgbe_mac_X540:
e8e26350
PW		 547 if (direction == -1) {
548 /* other causes */
549 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
550 index = ((queue & 1) * 8);
551 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
552 ivar &= ~(0xFF << index);
553 ivar |= (msix_vector << index);
554 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
555 break;
556 } else {
557 /* tx or rx causes */
558 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
559 index = ((16 * (queue & 1)) + (8 * direction));
560 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
561 ivar &= ~(0xFF << index);
562 ivar |= (msix_vector << index);
563 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
564 break;
565 }
566 default:
567 break;
568 }
9a799d71
AK		 569}
570
fe49f04a 571static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 572 u64 qmask)
fe49f04a
AD		 573{
574 u32 mask;
575
bd508178
AD		 576 switch (adapter->hw.mac.type) {
577 case ixgbe_mac_82598EB:
fe49f04a
AD		 578 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 580 break;
581 case ixgbe_mac_82599EB:
b93a2226 582 case ixgbe_mac_X540:
fe49f04a
AD		 583 mask = (qmask & 0xFFFFFFFF);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
585 mask = (qmask >> 32);
586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 587 break;
588 default:
589 break;
fe49f04a
AD		 590 }
591}
592
729739b7
AD		 593void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
594 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 595{
729739b7
AD		 596 if (tx_buffer->skb) {
597 dev_kfree_skb_any(tx_buffer->skb);
598 if (dma_unmap_len(tx_buffer, len))
d3d00239 599 dma_unmap_single(ring->dev,
729739b7
AD		 600 dma_unmap_addr(tx_buffer, dma),
601 dma_unmap_len(tx_buffer, len),
602 DMA_TO_DEVICE);
603 } else if (dma_unmap_len(tx_buffer, len)) {
604 dma_unmap_page(ring->dev,
605 dma_unmap_addr(tx_buffer, dma),
606 dma_unmap_len(tx_buffer, len),
607 DMA_TO_DEVICE);
e5a43549 608 }
729739b7
AD		 609 tx_buffer->next_to_watch = NULL;
610 tx_buffer->skb = NULL;
611 dma_unmap_len_set(tx_buffer, len, 0);
612 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 613}
614
943561d3 615static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 616{
617 struct ixgbe_hw *hw = &adapter->hw;
618 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 619 int i;
943561d3 620 u32 data;
c84d324c 621
943561d3
AD		 622 if ((hw->fc.current_mode != ixgbe_fc_full) &&
623 (hw->fc.current_mode != ixgbe_fc_rx_pause))
624 return;
c84d324c 625
943561d3
AD		 626 switch (hw->mac.type) {
627 case ixgbe_mac_82598EB:
628 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
629 break;
630 default:
631 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
632 }
633 hwstats->lxoffrxc += data;
c84d324c 634
943561d3
AD		 635 /* refill credits (no tx hang) if we received xoff */
636 if (!data)
c84d324c 637 return;
943561d3
AD		 638
639 for (i = 0; i < adapter->num_tx_queues; i++)
640 clear_bit(__IXGBE_HANG_CHECK_ARMED,
641 &adapter->tx_ring[i]->state);
642}
643
644static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
645{
646 struct ixgbe_hw *hw = &adapter->hw;
647 struct ixgbe_hw_stats *hwstats = &adapter->stats;
648 u32 xoff[8] = {0};
649 int i;
650 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
651
652 if (adapter->ixgbe_ieee_pfc)
653 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
654
655 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
656 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 657 return;
943561d3 658 }
c84d324c
JF		 659
660 /* update stats for each tc, only valid with PFC enabled */
661 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
662 switch (hw->mac.type) {
663 case ixgbe_mac_82598EB:
664 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 665 break;
c84d324c
JF		 666 default:
667 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 668 }
c84d324c
JF		 669 hwstats->pxoffrxc[i] += xoff[i];
670 }
671
672 /* disarm tx queues that have received xoff frames */
673 for (i = 0; i < adapter->num_tx_queues; i++) {
674 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 675 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 676
677 if (xoff[tc])
678 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 679 }
26f23d82
YZ		 680}
681
c84d324c 682static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 683{
7d7ce682 684 return ring->stats.packets;
c84d324c
JF		 685}
686
687static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
688{
689 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 690 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 691
c84d324c
JF		 692 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
693 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
694
695 if (head != tail)
696 return (head < tail) ?
697 tail - head : (tail + ring->count - head);
698
699 return 0;
700}
701
702static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
703{
704 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
705 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
706 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
707 bool ret = false;
708
7d637bcc 709 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 710
711 /*
712 * Check for a hung queue, but be thorough. This verifies
713 * that a transmit has been completed since the previous
714 * check AND there is at least one packet pending. The
715 * ARMED bit is set to indicate a potential hang. The
716 * bit is cleared if a pause frame is received to remove
717 * false hang detection due to PFC or 802.3x frames. By
718 * requiring this to fail twice we avoid races with
719 * pfc clearing the ARMED bit and conditions where we
720 * run the check_tx_hang logic with a transmit completion
721 * pending but without time to complete it yet.
722 */
723 if ((tx_done_old == tx_done) && tx_pending) {
724 /* make sure it is true for two checks in a row */
725 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
726 &tx_ring->state);
727 } else {
728 /* update completed stats and continue */
729 tx_ring->tx_stats.tx_done_old = tx_done;
730 /* reset the countdown */
731 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 732 }
733
c84d324c 734 return ret;
9a799d71
AK		 735}
736
c83c6cbd
AD		 737/**
738 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
739 * @adapter: driver private struct
740 **/
741static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
742{
743
744 /* Do the reset outside of interrupt context */
745 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
746 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
747 ixgbe_service_event_schedule(adapter);
748 }
749}
e01c31a5 750
9a799d71
AK		 751/**
752 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 753 * @q_vector: structure containing interrupt and ring information
e01c31a5 754 * @tx_ring: tx ring to clean
9a799d71 755 **/
fe49f04a 756static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 757 struct ixgbe_ring *tx_ring)
9a799d71 758{
fe49f04a 759 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 760 struct ixgbe_tx_buffer *tx_buffer;
761 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 762 unsigned int total_bytes = 0, total_packets = 0;
59224555 763 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 764 unsigned int i = tx_ring->next_to_clean;
765
766 if (test_bit(__IXGBE_DOWN, &adapter->state))
767 return true;
9a799d71 768
d3d00239 769 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 770 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 771 i -= tx_ring->count;
12207e49 772
729739b7 773 do {
d3d00239
AD		 774 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
775
776 /* if next_to_watch is not set then there is no work pending */
777 if (!eop_desc)
778 break;
779
7f83a9e6
AD		 780 /* prevent any other reads prior to eop_desc */
781 rmb();
782
d3d00239
AD		 783 /* if DD is not set pending work has not been completed */
784 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
785 break;
8ad494b0 786
d3d00239
AD		 787 /* clear next_to_watch to prevent false hangs */
788 tx_buffer->next_to_watch = NULL;
8ad494b0 789
091a6246
AD		 790 /* update the statistics for this packet */
791 total_bytes += tx_buffer->bytecount;
792 total_packets += tx_buffer->gso_segs;
793
3a6a4eda 794#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 795 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
796 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 797#endif
0ede4a60 798
fd0db0ed
AD		 799 /* free the skb */
800 dev_kfree_skb_any(tx_buffer->skb);
801
729739b7
AD		 802 /* unmap skb header data */
803 dma_unmap_single(tx_ring->dev,
804 dma_unmap_addr(tx_buffer, dma),
805 dma_unmap_len(tx_buffer, len),
806 DMA_TO_DEVICE);
807
fd0db0ed
AD		 808 /* clear tx_buffer data */
809 tx_buffer->skb = NULL;
729739b7 810 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 811
729739b7
AD		 812 /* unmap remaining buffers */
813 while (tx_desc != eop_desc) {
d3d00239
AD		 814 tx_buffer++;
815 tx_desc++;
8ad494b0 816 i++;
729739b7
AD		 817 if (unlikely(!i)) {
818 i -= tx_ring->count;
d3d00239 819 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 820 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 821 }
e01c31a5 822
729739b7
AD		 823 /* unmap any remaining paged data */
824 if (dma_unmap_len(tx_buffer, len)) {
825 dma_unmap_page(tx_ring->dev,
826 dma_unmap_addr(tx_buffer, dma),
827 dma_unmap_len(tx_buffer, len),
828 DMA_TO_DEVICE);
829 dma_unmap_len_set(tx_buffer, len, 0);
830 }
831 }
832
833 /* move us one more past the eop_desc for start of next pkt */
834 tx_buffer++;
835 tx_desc++;
836 i++;
837 if (unlikely(!i)) {
838 i -= tx_ring->count;
839 tx_buffer = tx_ring->tx_buffer_info;
840 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
841 }
842
843 /* issue prefetch for next Tx descriptor */
844 prefetch(tx_desc);
12207e49 845
729739b7
AD		 846 /* update budget accounting */
847 budget--;
848 } while (likely(budget));
849
850 i += tx_ring->count;
9a799d71 851 tx_ring->next_to_clean = i;
d3d00239 852 u64_stats_update_begin(&tx_ring->syncp);
b953799e 853 tx_ring->stats.bytes += total_bytes;
bd198058 854 tx_ring->stats.packets += total_packets;
d3d00239 855 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 856 q_vector->tx.total_bytes += total_bytes;
857 q_vector->tx.total_packets += total_packets;
b953799e 858
c84d324c
JF		 859 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
860 /* schedule immediate reset if we believe we hung */
861 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 862 e_err(drv, "Detected Tx Unit Hang\n"
863 " Tx Queue <%d>\n"
864 " TDH, TDT <%x>, <%x>\n"
865 " next_to_use <%x>\n"
866 " next_to_clean <%x>\n"
867 "tx_buffer_info[next_to_clean]\n"
868 " time_stamp <%lx>\n"
869 " jiffies <%lx>\n",
870 tx_ring->queue_index,
871 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
872 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 873 tx_ring->next_to_use, i,
874 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 875
876 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
877
878 e_info(probe,
879 "tx hang %d detected on queue %d, resetting adapter\n",
880 adapter->tx_timeout_count + 1, tx_ring->queue_index);
881
b953799e 882 /* schedule immediate reset if we believe we hung */
c83c6cbd 883 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 884
885 /* the adapter is about to reset, no point in enabling stuff */
59224555 886 return true;
b953799e 887 }
9a799d71 888
b2d96e0a
AD		 889 netdev_tx_completed_queue(txring_txq(tx_ring),
890 total_packets, total_bytes);
891
e092be60 892#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 893 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 894 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 895 /* Make sure that anybody stopping the queue after this
896 * sees the new next_to_clean.
897 */
898 smp_mb();
729739b7
AD		 899 if (__netif_subqueue_stopped(tx_ring->netdev,
900 tx_ring->queue_index)
901 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
902 netif_wake_subqueue(tx_ring->netdev,
903 tx_ring->queue_index);
5b7da515 904 ++tx_ring->tx_stats.restart_queue;
30eba97a 905 }
e092be60 906 }
9a799d71 907
59224555 908 return !!budget;
9a799d71
AK		 909}
910
5dd2d332 911#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 912static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
913 struct ixgbe_ring *tx_ring,
33cf09c9 914 int cpu)
bd0362dd 915{
33cf09c9 916 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 917 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
918 u16 reg_offset;
33cf09c9 919
33cf09c9
AD		 920 switch (hw->mac.type) {
921 case ixgbe_mac_82598EB:
bdda1a61 922 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 923 break;
924 case ixgbe_mac_82599EB:
b93a2226 925 case ixgbe_mac_X540:
bdda1a61
AD		 926 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
927 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 928 break;
929 default:
bdda1a61
AD		 930 /* for unknown hardware do not write register */
931 return;
bd0362dd 932 }
bdda1a61
AD		 933
934 /*
935 * We can enable relaxed ordering for reads, but not writes when
936 * DCA is enabled. This is due to a known issue in some chipsets
937 * which will cause the DCA tag to be cleared.
938 */
939 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
940 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
941 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
942
943 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 944}
945
bdda1a61
AD		 946static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
947 struct ixgbe_ring *rx_ring,
33cf09c9 948 int cpu)
bd0362dd 949{
33cf09c9 950 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 951 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
952 u8 reg_idx = rx_ring->reg_idx;
953
33cf09c9
AD		 954
955 switch (hw->mac.type) {
33cf09c9 956 case ixgbe_mac_82599EB:
b93a2226 957 case ixgbe_mac_X540:
bdda1a61 958 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 959 break;
960 default:
961 break;
962 }
bdda1a61
AD		 963
964 /*
965 * We can enable relaxed ordering for reads, but not writes when
966 * DCA is enabled. This is due to a known issue in some chipsets
967 * which will cause the DCA tag to be cleared.
968 */
969 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
970 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
971 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
972
973 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 974}
975
976static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
977{
978 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 979 struct ixgbe_ring *ring;
bd0362dd 980 int cpu = get_cpu();
bd0362dd 981
33cf09c9
AD		 982 if (q_vector->cpu == cpu)
983 goto out_no_update;
984
a557928e 985 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 986 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 987
a557928e 988 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 989 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 990
991 q_vector->cpu = cpu;
992out_no_update:
bd0362dd
JC		 993 put_cpu();
994}
995
996static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
997{
998 int i;
999
1000 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1001 return;
1002
e35ec126
AD		 1003 /* always use CB2 mode, difference is masked in the CB driver */
1004 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1005
49c7ffbe 1006 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1007 adapter->q_vector[i]->cpu = -1;
1008 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1009 }
1010}
1011
1012static int __ixgbe_notify_dca(struct device *dev, void *data)
1013{
c60fbb00 1014 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1015 unsigned long event = *(unsigned long *)data;
1016
2a72c31e 1017 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1018 return 0;
1019
bd0362dd
JC		 1020 switch (event) {
1021 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1022 /* if we're already enabled, don't do it again */
1023 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1024 break;
652f093f 1025 if (dca_add_requester(dev) == 0) {
96b0e0f6 1026 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1027 ixgbe_setup_dca(adapter);
1028 break;
1029 }
1030 /* Fall Through since DCA is disabled. */
1031 case DCA_PROVIDER_REMOVE:
1032 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1033 dca_remove_requester(dev);
1034 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1036 }
1037 break;
1038 }
1039
652f093f 1040 return 0;
bd0362dd 1041}
67a74ee2 1042
bdda1a61 1043#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1044static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1045 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1046 struct sk_buff *skb)
1047{
8a0da21b
AD		 1048 if (ring->netdev->features & NETIF_F_RXHASH)
1049 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1050}
1051
f800326d 1052#ifdef IXGBE_FCOE
ff886dfc
AD		 1053/**
1054 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1055 * @ring: structure containing ring specific data
ff886dfc
AD		 1056 * @rx_desc: advanced rx descriptor
1057 *
1058 * Returns : true if it is FCoE pkt
1059 */
57efd44c 1060static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1061 union ixgbe_adv_rx_desc *rx_desc)
1062{
1063 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1064
57efd44c 1065 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1066 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1067 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1068 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1069}
1070
f800326d 1071#endif /* IXGBE_FCOE */
e59bd25d
AV		 1072/**
1073 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1074 * @ring: structure containing ring specific data
1075 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1076 * @skb: skb currently being received and modified
1077 **/
8a0da21b 1078static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1079 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1080 struct sk_buff *skb)
9a799d71 1081{
8a0da21b 1082 skb_checksum_none_assert(skb);
9a799d71 1083
712744be 1084 /* Rx csum disabled */
8a0da21b 1085 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1086 return;
e59bd25d
AV		 1087
1088 /* if IP and error */
f56e0cb1
AD		 1089 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1090 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1091 ring->rx_stats.csum_err++;
9a799d71
AK		 1092 return;
1093 }
e59bd25d 1094
f56e0cb1 1095 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1096 return;
1097
f56e0cb1 1098 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1099 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1100
1101 /*
1102 * 82599 errata, UDP frames with a 0 checksum can be marked as
1103 * checksum errors.
1104 */
8a0da21b
AD		 1105 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1106 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1107 return;
1108
8a0da21b 1109 ring->rx_stats.csum_err++;
e59bd25d
AV		 1110 return;
1111 }
1112
9a799d71 1113 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1114 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1115}
1116
84ea2591 1117static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1118{
f56e0cb1 1119 rx_ring->next_to_use = val;
f800326d
AD		 1120
1121 /* update next to alloc since we have filled the ring */
1122 rx_ring->next_to_alloc = val;
e8e26350
PW		 1123 /*
1124 * Force memory writes to complete before letting h/w
1125 * know there are new descriptors to fetch. (Only
1126 * applicable for weak-ordered memory model archs,
1127 * such as IA-64).
1128 */
1129 wmb();
84ea2591 1130 writel(val, rx_ring->tail);
e8e26350
PW		 1131}
1132
f990b79b
AD		 1133static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1134 struct ixgbe_rx_buffer *bi)
1135{
1136 struct page *page = bi->page;
f800326d 1137 dma_addr_t dma = bi->dma;
f990b79b 1138
f800326d
AD		 1139 /* since we are recycling buffers we should seldom need to alloc */
1140 if (likely(dma))
f990b79b
AD		 1141 return true;
1142
f800326d
AD		 1143 /* alloc new page for storage */
1144 if (likely(!page)) {
0614002b
MG		 1145 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1146 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1147 if (unlikely(!page)) {
1148 rx_ring->rx_stats.alloc_rx_page_failed++;
1149 return false;
1150 }
f800326d 1151 bi->page = page;
f990b79b
AD		 1152 }
1153
f800326d
AD		 1154 /* map page for use */
1155 dma = dma_map_page(rx_ring->dev, page, 0,
1156 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1157
1158 /*
1159 * if mapping failed free memory back to system since
1160 * there isn't much point in holding memory we can't use
1161 */
1162 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1163 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1164 bi->page = NULL;
f990b79b 1165
f990b79b
AD		 1166 rx_ring->rx_stats.alloc_rx_page_failed++;
1167 return false;
1168 }
1169
f800326d 1170 bi->dma = dma;
afaa9459 1171 bi->page_offset = 0;
f800326d 1172
f990b79b
AD		 1173 return true;
1174}
1175
9a799d71 1176/**
f990b79b 1177 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1178 * @rx_ring: ring to place buffers on
1179 * @cleaned_count: number of buffers to replace
9a799d71 1180 **/
fc77dc3c 1181void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1182{
9a799d71 1183 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1184 struct ixgbe_rx_buffer *bi;
d5f398ed 1185 u16 i = rx_ring->next_to_use;
9a799d71 1186
f800326d
AD		 1187 /* nothing to do */
1188 if (!cleaned_count)
fc77dc3c
AD		 1189 return;
1190
e4f74028 1191 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1192 bi = &rx_ring->rx_buffer_info[i];
1193 i -= rx_ring->count;
9a799d71 1194
f800326d
AD		 1195 do {
1196 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1197 break;
d5f398ed 1198
f800326d
AD		 1199 /*
1200 * Refresh the desc even if buffer_addrs didn't change
1201 * because each write-back erases this info.
1202 */
1203 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1204
f990b79b
AD		 1205 rx_desc++;
1206 bi++;
9a799d71 1207 i++;
f990b79b 1208 if (unlikely(!i)) {
e4f74028 1209 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1210 bi = rx_ring->rx_buffer_info;
1211 i -= rx_ring->count;
1212 }
1213
1214 /* clear the hdr_addr for the next_to_use descriptor */
1215 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1216
1217 cleaned_count--;
1218 } while (cleaned_count);
7c6e0a43 1219
f990b79b
AD		 1220 i += rx_ring->count;
1221
f56e0cb1 1222 if (rx_ring->next_to_use != i)
84ea2591 1223 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1224}
1225
1d2024f6
AD		 1226/**
1227 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1228 * @data: pointer to the start of the headers
1229 * @max_len: total length of section to find headers in
1230 *
1231 * This function is meant to determine the length of headers that will
1232 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1233 * motivation of doing this is to only perform one pull for IPv4 TCP
1234 * packets so that we can do basic things like calculating the gso_size
1235 * based on the average data per packet.
1236 **/
1237static unsigned int ixgbe_get_headlen(unsigned char *data,
1238 unsigned int max_len)
1239{
1240 union {
1241 unsigned char *network;
1242 /* l2 headers */
1243 struct ethhdr *eth;
1244 struct vlan_hdr *vlan;
1245 /* l3 headers */
1246 struct iphdr *ipv4;
a048b40e 1247 struct ipv6hdr *ipv6;
1d2024f6
AD		 1248 } hdr;
1249 __be16 protocol;
1250 u8 nexthdr = 0; /* default to not TCP */
1251 u8 hlen;
1252
1253 /* this should never happen, but better safe than sorry */
1254 if (max_len < ETH_HLEN)
1255 return max_len;
1256
1257 /* initialize network frame pointer */
1258 hdr.network = data;
1259
1260 /* set first protocol and move network header forward */
1261 protocol = hdr.eth->h_proto;
1262 hdr.network += ETH_HLEN;
1263
1264 /* handle any vlan tag if present */
1265 if (protocol == __constant_htons(ETH_P_8021Q)) {
1266 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1267 return max_len;
1268
1269 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1270 hdr.network += VLAN_HLEN;
1271 }
1272
1273 /* handle L3 protocols */
1274 if (protocol == __constant_htons(ETH_P_IP)) {
1275 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1276 return max_len;
1277
1278 /* access ihl as a u8 to avoid unaligned access on ia64 */
1279 hlen = (hdr.network[0] & 0x0F) << 2;
1280
1281 /* verify hlen meets minimum size requirements */
1282 if (hlen < sizeof(struct iphdr))
1283 return hdr.network - data;
1284
1285 /* record next protocol */
1286 nexthdr = hdr.ipv4->protocol;
1287 hdr.network += hlen;
a048b40e
AD		 1288 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1289 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1290 return max_len;
1291
1292 /* record next protocol */
1293 nexthdr = hdr.ipv6->nexthdr;
1294 hdr.network += sizeof(struct ipv6hdr);
f800326d 1295#ifdef IXGBE_FCOE
1d2024f6
AD		 1296 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1297 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1298 return max_len;
1299 hdr.network += FCOE_HEADER_LEN;
1300#endif
1301 } else {
1302 return hdr.network - data;
1303 }
1304
a048b40e 1305 /* finally sort out TCP/UDP */
1d2024f6
AD		 1306 if (nexthdr == IPPROTO_TCP) {
1307 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1308 return max_len;
1309
1310 /* access doff as a u8 to avoid unaligned access on ia64 */
1311 hlen = (hdr.network[12] & 0xF0) >> 2;
1312
1313 /* verify hlen meets minimum size requirements */
1314 if (hlen < sizeof(struct tcphdr))
1315 return hdr.network - data;
1316
1317 hdr.network += hlen;
a048b40e
AD		 1318 } else if (nexthdr == IPPROTO_UDP) {
1319 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1320 return max_len;
1321
1322 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1323 }
1324
1325 /*
1326 * If everything has gone correctly hdr.network should be the
1327 * data section of the packet and will be the end of the header.
1328 * If not then it probably represents the end of the last recognized
1329 * header.
1330 */
1331 if ((hdr.network - data) < max_len)
1332 return hdr.network - data;
1333 else
1334 return max_len;
1335}
1336
1d2024f6
AD		 1337static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1338 struct sk_buff *skb)
1339{
f800326d 1340 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1341
1342 /* set gso_size to avoid messing up TCP MSS */
1343 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1344 IXGBE_CB(skb)->append_cnt);
1345}
1346
1347static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1348 struct sk_buff *skb)
1349{
1350 /* if append_cnt is 0 then frame is not RSC */
1351 if (!IXGBE_CB(skb)->append_cnt)
1352 return;
1353
1354 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1355 rx_ring->rx_stats.rsc_flush++;
1356
1357 ixgbe_set_rsc_gso_size(rx_ring, skb);
1358
1359 /* gso_size is computed using append_cnt so always clear it last */
1360 IXGBE_CB(skb)->append_cnt = 0;
1361}
1362
8a0da21b
AD		 1363/**
1364 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1365 * @rx_ring: rx descriptor ring packet is being transacted on
1366 * @rx_desc: pointer to the EOP Rx descriptor
1367 * @skb: pointer to current skb being populated
f8212f97 1368 *
8a0da21b
AD		 1369 * This function checks the ring, descriptor, and packet information in
1370 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1371 * other fields within the skb.
f8212f97 1372 **/
8a0da21b
AD		 1373static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1374 union ixgbe_adv_rx_desc *rx_desc,
1375 struct sk_buff *skb)
f8212f97 1376{
43e95f11
JF		 1377 struct net_device *dev = rx_ring->netdev;
1378
8a0da21b
AD		 1379 ixgbe_update_rsc_stats(rx_ring, skb);
1380
1381 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1382
8a0da21b
AD		 1383 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1384
3a6a4eda 1385#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1386 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1387#endif
1388
43e95f11
JF		 1389 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1390 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1391 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1392 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1393 }
1394
8a0da21b 1395 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1396
43e95f11 1397 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1398}
1399
8a0da21b
AD		 1400static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1401 struct sk_buff *skb)
aa80175a 1402{
8a0da21b
AD		 1403 struct ixgbe_adapter *adapter = q_vector->adapter;
1404
1405 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1406 napi_gro_receive(&q_vector->napi, skb);
1407 else
1408 netif_rx(skb);
aa80175a 1409}
43634e82 1410
f800326d
AD		 1411/**
1412 * ixgbe_is_non_eop - process handling of non-EOP buffers
1413 * @rx_ring: Rx ring being processed
1414 * @rx_desc: Rx descriptor for current buffer
1415 * @skb: Current socket buffer containing buffer in progress
1416 *
1417 * This function updates next to clean. If the buffer is an EOP buffer
1418 * this function exits returning false, otherwise it will place the
1419 * sk_buff in the next buffer to be chained and return true indicating
1420 * that this is in fact a non-EOP buffer.
1421 **/
1422static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1423 union ixgbe_adv_rx_desc *rx_desc,
1424 struct sk_buff *skb)
1425{
1426 u32 ntc = rx_ring->next_to_clean + 1;
1427
1428 /* fetch, update, and store next to clean */
1429 ntc = (ntc < rx_ring->count) ? ntc : 0;
1430 rx_ring->next_to_clean = ntc;
1431
1432 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1433
5a02cbd1
AD		 1434 /* update RSC append count if present */
1435 if (ring_is_rsc_enabled(rx_ring)) {
1436 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1437 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1438
1439 if (unlikely(rsc_enabled)) {
1440 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1441
1442 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1443 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1444
5a02cbd1
AD		 1445 /* update ntc based on RSC value */
1446 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1447 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1448 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1449 }
f800326d
AD		 1450 }
1451
5a02cbd1
AD		 1452 /* if we are the last buffer then there is nothing else to do */
1453 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1454 return false;
1455
f800326d
AD		 1456 /* place skb in next buffer to be received */
1457 rx_ring->rx_buffer_info[ntc].skb = skb;
1458 rx_ring->rx_stats.non_eop_descs++;
1459
1460 return true;
1461}
1462
19861ce2
AD		 1463/**
1464 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1465 * @rx_ring: rx descriptor ring packet is being transacted on
1466 * @skb: pointer to current skb being adjusted
1467 *
1468 * This function is an ixgbe specific version of __pskb_pull_tail. The
1469 * main difference between this version and the original function is that
1470 * this function can make several assumptions about the state of things
1471 * that allow for significant optimizations versus the standard function.
1472 * As a result we can do things like drop a frag and maintain an accurate
1473 * truesize for the skb.
1474 */
1475static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1476 struct sk_buff *skb)
1477{
1478 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1479 unsigned char *va;
1480 unsigned int pull_len;
1481
1482 /*
1483 * it is valid to use page_address instead of kmap since we are
1484 * working with pages allocated out of the lomem pool per
1485 * alloc_page(GFP_ATOMIC)
1486 */
1487 va = skb_frag_address(frag);
1488
1489 /*
1490 * we need the header to contain the greater of either ETH_HLEN or
1491 * 60 bytes if the skb->len is less than 60 for skb_pad.
1492 */
cf3fe7ac 1493 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1494
1495 /* align pull length to size of long to optimize memcpy performance */
1496 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1497
1498 /* update all of the pointers */
1499 skb_frag_size_sub(frag, pull_len);
1500 frag->page_offset += pull_len;
1501 skb->data_len -= pull_len;
1502 skb->tail += pull_len;
19861ce2
AD		 1503}
1504
42073d91
AD		 1505/**
1506 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1507 * @rx_ring: rx descriptor ring packet is being transacted on
1508 * @skb: pointer to current skb being updated
1509 *
1510 * This function provides a basic DMA sync up for the first fragment of an
1511 * skb. The reason for doing this is that the first fragment cannot be
1512 * unmapped until we have reached the end of packet descriptor for a buffer
1513 * chain.
1514 */
1515static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1516 struct sk_buff *skb)
1517{
1518 /* if the page was released unmap it, else just sync our portion */
1519 if (unlikely(IXGBE_CB(skb)->page_released)) {
1520 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1521 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1522 IXGBE_CB(skb)->page_released = false;
1523 } else {
1524 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1525
1526 dma_sync_single_range_for_cpu(rx_ring->dev,
1527 IXGBE_CB(skb)->dma,
1528 frag->page_offset,
1529 ixgbe_rx_bufsz(rx_ring),
1530 DMA_FROM_DEVICE);
1531 }
1532 IXGBE_CB(skb)->dma = 0;
1533}
1534
f800326d
AD		 1535/**
1536 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1537 * @rx_ring: rx descriptor ring packet is being transacted on
1538 * @rx_desc: pointer to the EOP Rx descriptor
1539 * @skb: pointer to current skb being fixed
1540 *
1541 * Check for corrupted packet headers caused by senders on the local L2
1542 * embedded NIC switch not setting up their Tx Descriptors right. These
1543 * should be very rare.
1544 *
1545 * Also address the case where we are pulling data in on pages only
1546 * and as such no data is present in the skb header.
1547 *
1548 * In addition if skb is not at least 60 bytes we need to pad it so that
1549 * it is large enough to qualify as a valid Ethernet frame.
1550 *
1551 * Returns true if an error was encountered and skb was freed.
1552 **/
1553static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1554 union ixgbe_adv_rx_desc *rx_desc,
1555 struct sk_buff *skb)
1556{
f800326d 1557 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1558
1559 /* verify that the packet does not have any known errors */
1560 if (unlikely(ixgbe_test_staterr(rx_desc,
1561 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1562 !(netdev->features & NETIF_F_RXALL))) {
1563 dev_kfree_skb_any(skb);
1564 return true;
1565 }
1566
19861ce2 1567 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1568 if (skb_is_nonlinear(skb))
1569 ixgbe_pull_tail(rx_ring, skb);
f800326d 1570
57efd44c
AD		 1571#ifdef IXGBE_FCOE
1572 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1573 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1574 return false;
1575
1576#endif
f800326d
AD		 1577 /* if skb_pad returns an error the skb was freed */
1578 if (unlikely(skb->len < 60)) {
1579 int pad_len = 60 - skb->len;
1580
1581 if (skb_pad(skb, pad_len))
1582 return true;
1583 __skb_put(skb, pad_len);
1584 }
1585
1586 return false;
1587}
1588
f800326d
AD		 1589/**
1590 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1591 * @rx_ring: rx descriptor ring to store buffers on
1592 * @old_buff: donor buffer to have page reused
1593 *
0549ae20 1594 * Synchronizes page for reuse by the adapter
f800326d
AD		 1595 **/
1596static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1597 struct ixgbe_rx_buffer *old_buff)
1598{
1599 struct ixgbe_rx_buffer *new_buff;
1600 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1601
1602 new_buff = &rx_ring->rx_buffer_info[nta];
1603
1604 /* update, and store next to alloc */
1605 nta++;
1606 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1607
1608 /* transfer page from old buffer to new buffer */
1609 new_buff->page = old_buff->page;
1610 new_buff->dma = old_buff->dma;
0549ae20 1611 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1612
1613 /* sync the buffer for use by the device */
1614 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1615 new_buff->page_offset,
1616 ixgbe_rx_bufsz(rx_ring),
f800326d 1617 DMA_FROM_DEVICE);
f800326d
AD		 1618}
1619
1620/**
1621 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1622 * @rx_ring: rx descriptor ring to transact packets on
1623 * @rx_buffer: buffer containing page to add
1624 * @rx_desc: descriptor containing length of buffer written by hardware
1625 * @skb: sk_buff to place the data into
1626 *
0549ae20
AD		 1627 * This function will add the data contained in rx_buffer->page to the skb.
1628 * This is done either through a direct copy if the data in the buffer is
1629 * less than the skb header size, otherwise it will just attach the page as
1630 * a frag to the skb.
1631 *
1632 * The function will then update the page offset if necessary and return
1633 * true if the buffer can be reused by the adapter.
f800326d 1634 **/
0549ae20 1635static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1636 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1637 union ixgbe_adv_rx_desc *rx_desc,
1638 struct sk_buff *skb)
f800326d 1639{
0549ae20
AD		 1640 struct page *page = rx_buffer->page;
1641 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1642#if (PAGE_SIZE < 8192)
0549ae20 1643 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1644#else
1645 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1646 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1647 ixgbe_rx_bufsz(rx_ring);
1648#endif
0549ae20 1649
cf3fe7ac
AD		 1650 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1651 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1652
1653 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1654
1655 /* we can reuse buffer as-is, just make sure it is local */
1656 if (likely(page_to_nid(page) == numa_node_id()))
1657 return true;
1658
1659 /* this page cannot be reused so discard it */
1660 put_page(page);
1661 return false;
1662 }
1663
0549ae20
AD		 1664 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1665 rx_buffer->page_offset, size, truesize);
1666
09816fbe
AD		 1667 /* avoid re-using remote pages */
1668 if (unlikely(page_to_nid(page) != numa_node_id()))
1669 return false;
1670
1671#if (PAGE_SIZE < 8192)
1672 /* if we are only owner of page we can reuse it */
1673 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1674 return false;
1675
1676 /* flip page offset to other buffer */
1677 rx_buffer->page_offset ^= truesize;
1678
09816fbe
AD		 1679 /*
1680 * since we are the only owner of the page and we need to
1681 * increment it, just set the value to 2 in order to avoid
1682 * an unecessary locked operation
1683 */
1684 atomic_set(&page->_count, 2);
1685#else
1686 /* move offset up to the next cache line */
1687 rx_buffer->page_offset += truesize;
1688
1689 if (rx_buffer->page_offset > last_offset)
1690 return false;
1691
0549ae20
AD		 1692 /* bump ref count on page before it is given to the stack */
1693 get_page(page);
09816fbe 1694#endif
0549ae20
AD		 1695
1696 return true;
f800326d
AD		 1697}
1698
18806c9e
AD		 1699static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1700 union ixgbe_adv_rx_desc *rx_desc)
1701{
1702 struct ixgbe_rx_buffer *rx_buffer;
1703 struct sk_buff *skb;
1704 struct page *page;
1705
1706 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1707 page = rx_buffer->page;
1708 prefetchw(page);
1709
1710 skb = rx_buffer->skb;
1711
1712 if (likely(!skb)) {
1713 void *page_addr = page_address(page) +
1714 rx_buffer->page_offset;
1715
1716 /* prefetch first cache line of first page */
1717 prefetch(page_addr);
1718#if L1_CACHE_BYTES < 128
1719 prefetch(page_addr + L1_CACHE_BYTES);
1720#endif
1721
1722 /* allocate a skb to store the frags */
1723 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1724 IXGBE_RX_HDR_SIZE);
1725 if (unlikely(!skb)) {
1726 rx_ring->rx_stats.alloc_rx_buff_failed++;
1727 return NULL;
1728 }
1729
1730 /*
1731 * we will be copying header into skb->data in
1732 * pskb_may_pull so it is in our interest to prefetch
1733 * it now to avoid a possible cache miss
1734 */
1735 prefetchw(skb->data);
1736
1737 /*
1738 * Delay unmapping of the first packet. It carries the
1739 * header information, HW may still access the header
1740 * after the writeback. Only unmap it when EOP is
1741 * reached
1742 */
1743 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1744 goto dma_sync;
1745
1746 IXGBE_CB(skb)->dma = rx_buffer->dma;
1747 } else {
1748 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1749 ixgbe_dma_sync_frag(rx_ring, skb);
1750
1751dma_sync:
1752 /* we are reusing so sync this buffer for CPU use */
1753 dma_sync_single_range_for_cpu(rx_ring->dev,
1754 rx_buffer->dma,
1755 rx_buffer->page_offset,
1756 ixgbe_rx_bufsz(rx_ring),
1757 DMA_FROM_DEVICE);
1758 }
1759
1760 /* pull page into skb */
1761 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1762 /* hand second half of page back to the ring */
1763 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1764 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1765 /* the page has been released from the ring */
1766 IXGBE_CB(skb)->page_released = true;
1767 } else {
1768 /* we are not reusing the buffer so unmap it */
1769 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1770 ixgbe_rx_pg_size(rx_ring),
1771 DMA_FROM_DEVICE);
1772 }
1773
1774 /* clear contents of buffer_info */
1775 rx_buffer->skb = NULL;
1776 rx_buffer->dma = 0;
1777 rx_buffer->page = NULL;
1778
1779 return skb;
f800326d
AD		 1780}
1781
1782/**
1783 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1784 * @q_vector: structure containing interrupt and ring information
1785 * @rx_ring: rx descriptor ring to transact packets on
1786 * @budget: Total limit on number of packets to process
1787 *
1788 * This function provides a "bounce buffer" approach to Rx interrupt
1789 * processing. The advantage to this is that on systems that have
1790 * expensive overhead for IOMMU access this provides a means of avoiding
1791 * it by maintaining the mapping of the page to the syste.
1792 *
1793 * Returns true if all work is completed without reaching budget
1794 **/
4ff7fb12 1795static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1796 struct ixgbe_ring *rx_ring,
4ff7fb12 1797 int budget)
9a799d71 1798{
d2f4fbe2 1799 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1800#ifdef IXGBE_FCOE
f800326d 1801 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1802 int ddp_bytes;
1803 unsigned int mss = 0;
3d8fd385 1804#endif /* IXGBE_FCOE */
f800326d 1805 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1806
f800326d 1807 do {
f800326d
AD		 1808 union ixgbe_adv_rx_desc *rx_desc;
1809 struct sk_buff *skb;
f800326d
AD		 1810
1811 /* return some buffers to hardware, one at a time is too slow */
1812 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1813 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1814 cleaned_count = 0;
1815 }
1816
18806c9e 1817 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1818
1819 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1820 break;
9a799d71 1821
f800326d
AD		 1822 /*
1823 * This memory barrier is needed to keep us from reading
1824 * any other fields out of the rx_desc until we know the
1825 * RXD_STAT_DD bit is set
1826 */
1827 rmb();
9a799d71 1828
18806c9e
AD		 1829 /* retrieve a buffer from the ring */
1830 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1831
18806c9e
AD		 1832 /* exit if we failed to retrieve a buffer */
1833 if (!skb)
1834 break;
9a799d71 1835
9a799d71 1836 cleaned_count++;
f8212f97 1837
f800326d
AD		 1838 /* place incomplete frames back on ring for completion */
1839 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1840 continue;
c267fc16 1841
f800326d
AD		 1842 /* verify the packet layout is correct */
1843 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1844 continue;
9a799d71 1845
d2f4fbe2
AV		 1846 /* probably a little skewed due to removing CRC */
1847 total_rx_bytes += skb->len;
1848 total_rx_packets++;
1849
8a0da21b
AD		 1850 /* populate checksum, timestamp, VLAN, and protocol */
1851 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1852
332d4a7d
YZ		 1853#ifdef IXGBE_FCOE
1854 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1855 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1856 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 1857 /* include DDPed FCoE data */
1858 if (ddp_bytes > 0) {
1859 if (!mss) {
1860 mss = rx_ring->netdev->mtu -
1861 sizeof(struct fcoe_hdr) -
1862 sizeof(struct fc_frame_header) -
1863 sizeof(struct fcoe_crc_eof);
1864 if (mss > 512)
1865 mss &= ~511;
1866 }
1867 total_rx_bytes += ddp_bytes;
1868 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1869 mss);
1870 }
63d635b2
AD		 1871 if (!ddp_bytes) {
1872 dev_kfree_skb_any(skb);
f800326d 1873 continue;
63d635b2 1874 }
3d8fd385 1875 }
f800326d 1876
332d4a7d 1877#endif /* IXGBE_FCOE */
8a0da21b 1878 ixgbe_rx_skb(q_vector, skb);
9a799d71 1879
f800326d 1880 /* update budget accounting */
4ff7fb12 1881 budget--;
f800326d 1882 } while (likely(budget));
9a799d71 1883
c267fc16
AD		 1884 u64_stats_update_begin(&rx_ring->syncp);
1885 rx_ring->stats.packets += total_rx_packets;
1886 rx_ring->stats.bytes += total_rx_bytes;
1887 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1888 q_vector->rx.total_packets += total_rx_packets;
1889 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1890
f800326d
AD		 1891 if (cleaned_count)
1892 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1893
4ff7fb12 1894 return !!budget;
9a799d71
AK		 1895}
1896
9a799d71
AK		 1897/**
1898 * ixgbe_configure_msix - Configure MSI-X hardware
1899 * @adapter: board private structure
1900 *
1901 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1902 * interrupts.
1903 **/
1904static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1905{
021230d4 1906 struct ixgbe_q_vector *q_vector;
49c7ffbe 1907 int v_idx;
021230d4 1908 u32 mask;
9a799d71 1909
8e34d1aa
AD		 1910 /* Populate MSIX to EITR Select */
1911 if (adapter->num_vfs > 32) {
1912 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1913 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1914 }
1915
4df10466
JB		 1916 /*
1917 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1918 * corresponding register.
1919 */
49c7ffbe 1920 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1921 struct ixgbe_ring *ring;
7a921c93 1922 q_vector = adapter->q_vector[v_idx];
021230d4 1923
a557928e 1924 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1925 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1926
a557928e 1927 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1928 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1929
d5bf4f67
ET		 1930 if (q_vector->tx.ring && !q_vector->rx.ring) {
1931 /* tx only vector */
1932 if (adapter->tx_itr_setting == 1)
1933 q_vector->itr = IXGBE_10K_ITR;
1934 else
1935 q_vector->itr = adapter->tx_itr_setting;
1936 } else {
1937 /* rx or rx/tx vector */
1938 if (adapter->rx_itr_setting == 1)
1939 q_vector->itr = IXGBE_20K_ITR;
1940 else
1941 q_vector->itr = adapter->rx_itr_setting;
1942 }
021230d4 1943
fe49f04a 1944 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1945 }
1946
bd508178
AD		 1947 switch (adapter->hw.mac.type) {
1948 case ixgbe_mac_82598EB:
e8e26350 1949 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1950 v_idx);
bd508178
AD		 1951 break;
1952 case ixgbe_mac_82599EB:
b93a2226 1953 case ixgbe_mac_X540:
e8e26350 1954 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1955 break;
bd508178
AD		 1956 default:
1957 break;
1958 }
021230d4
AV		 1959 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1960
41fb9248 1961 /* set up to autoclear timer, and the vectors */
021230d4 1962 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1963 mask &= ~(IXGBE_EIMS_OTHER |
1964 IXGBE_EIMS_MAILBOX |
1965 IXGBE_EIMS_LSC);
1966
021230d4 1967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1968}
1969
f494e8fa
AV		 1970enum latency_range {
1971 lowest_latency = 0,
1972 low_latency = 1,
1973 bulk_latency = 2,
1974 latency_invalid = 255
1975};
1976
1977/**
1978 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1979 * @q_vector: structure containing interrupt and ring information
1980 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1981 *
1982 * Stores a new ITR value based on packets and byte
1983 * counts during the last interrupt. The advantage of per interrupt
1984 * computation is faster updates and more accurate ITR for the current
1985 * traffic pattern. Constants in this function were computed
1986 * based on theoretical maximum wire speed and thresholds were set based
1987 * on testing data as well as attempting to minimize response time
1988 * while increasing bulk throughput.
1989 * this functionality is controlled by the InterruptThrottleRate module
1990 * parameter (see ixgbe_param.c)
1991 **/
bd198058
AD		 1992static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1993 struct ixgbe_ring_container *ring_container)
f494e8fa 1994{
bd198058
AD		 1995 int bytes = ring_container->total_bytes;
1996 int packets = ring_container->total_packets;
1997 u32 timepassed_us;
621bd70e 1998 u64 bytes_perint;
bd198058 1999 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2000
2001 if (packets == 0)
bd198058 2002 return;
f494e8fa
AV		 2003
2004 /* simple throttlerate management
621bd70e
AD		 2005 * 0-10MB/s lowest (100000 ints/s)
2006 * 10-20MB/s low (20000 ints/s)
2007 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2008 */
2009 /* what was last interrupt timeslice? */
d5bf4f67 2010 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 2011 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2012
2013 switch (itr_setting) {
2014 case lowest_latency:
621bd70e 2015 if (bytes_perint > 10)
bd198058 2016 itr_setting = low_latency;
f494e8fa
AV		 2017 break;
2018 case low_latency:
621bd70e 2019 if (bytes_perint > 20)
bd198058 2020 itr_setting = bulk_latency;
621bd70e 2021 else if (bytes_perint <= 10)
bd198058 2022 itr_setting = lowest_latency;
f494e8fa
AV		 2023 break;
2024 case bulk_latency:
621bd70e 2025 if (bytes_perint <= 20)
bd198058 2026 itr_setting = low_latency;
f494e8fa
AV		 2027 break;
2028 }
2029
bd198058
AD		 2030 /* clear work counters since we have the values we need */
2031 ring_container->total_bytes = 0;
2032 ring_container->total_packets = 0;
2033
2034 /* write updated itr to ring container */
2035 ring_container->itr = itr_setting;
f494e8fa
AV		 2036}
2037
509ee935
JB		 2038/**
2039 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2040 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2041 *
2042 * This function is made to be called by ethtool and by the driver
2043 * when it needs to update EITR registers at runtime. Hardware
2044 * specific quirks/differences are taken care of here.
2045 */
fe49f04a 2046void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2047{
fe49f04a 2048 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2049 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2050 int v_idx = q_vector->v_idx;
5d967eb7 2051 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2052
bd508178
AD		 2053 switch (adapter->hw.mac.type) {
2054 case ixgbe_mac_82598EB:
509ee935
JB		 2055 /* must write high and low 16 bits to reset counter */
2056 itr_reg |= (itr_reg << 16);
bd508178
AD		 2057 break;
2058 case ixgbe_mac_82599EB:
b93a2226 2059 case ixgbe_mac_X540:
509ee935
JB		 2060 /*
2061 * set the WDIS bit to not clear the timer bits and cause an
2062 * immediate assertion of the interrupt
2063 */
2064 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2065 break;
2066 default:
2067 break;
509ee935
JB		 2068 }
2069 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2070}
2071
bd198058 2072static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2073{
d5bf4f67 2074 u32 new_itr = q_vector->itr;
bd198058 2075 u8 current_itr;
f494e8fa 2076
bd198058
AD		 2077 ixgbe_update_itr(q_vector, &q_vector->tx);
2078 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2079
08c8833b 2080 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2081
2082 switch (current_itr) {
2083 /* counts and packets in update_itr are dependent on these numbers */
2084 case lowest_latency:
d5bf4f67 2085 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2086 break;
2087 case low_latency:
d5bf4f67 2088 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2089 break;
2090 case bulk_latency:
d5bf4f67 2091 new_itr = IXGBE_8K_ITR;
f494e8fa 2092 break;
bd198058
AD		 2093 default:
2094 break;
f494e8fa
AV		 2095 }
2096
d5bf4f67 2097 if (new_itr != q_vector->itr) {
fe49f04a 2098 /* do an exponential smoothing */
d5bf4f67
ET		 2099 new_itr = (10 * new_itr * q_vector->itr) /
2100 ((9 * new_itr) + q_vector->itr);
509ee935 2101
bd198058 2102 /* save the algorithm value here */
5d967eb7 2103 q_vector->itr = new_itr;
fe49f04a
AD		 2104
2105 ixgbe_write_eitr(q_vector);
f494e8fa 2106 }
f494e8fa
AV		 2107}
2108
119fc60a 2109/**
de88eeeb 2110 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2111 * @adapter: pointer to adapter
119fc60a 2112 **/
f0f9778d 2113static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2114{
119fc60a
MC		 2115 struct ixgbe_hw *hw = &adapter->hw;
2116 u32 eicr = adapter->interrupt_event;
2117
f0f9778d 2118 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2119 return;
2120
f0f9778d
AD		 2121 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2122 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2123 return;
2124
2125 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2126
7ca647bd 2127 switch (hw->device_id) {
f0f9778d
AD		 2128 case IXGBE_DEV_ID_82599_T3_LOM:
2129 /*
2130 * Since the warning interrupt is for both ports
2131 * we don't have to check if:
2132 * - This interrupt wasn't for our port.
2133 * - We may have missed the interrupt so always have to
2134 * check if we got a LSC
2135 */
2136 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2137 !(eicr & IXGBE_EICR_LSC))
2138 return;
2139
2140 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2141 u32 autoneg;
2142 bool link_up = false;
7ca647bd 2143
7ca647bd
JP		 2144 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2145
f0f9778d
AD		 2146 if (link_up)
2147 return;
2148 }
2149
2150 /* Check if this is not due to overtemp */
2151 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2152 return;
2153
2154 break;
7ca647bd
JP		 2155 default:
2156 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2157 return;
7ca647bd 2158 break;
119fc60a 2159 }
7ca647bd
JP		 2160 e_crit(drv,
2161 "Network adapter has been stopped because it has over heated. "
2162 "Restart the computer. If the problem persists, "
2163 "power off the system and replace the adapter\n");
f0f9778d
AD		 2164
2165 adapter->interrupt_event = 0;
119fc60a
MC		 2166}
2167
0befdb3e
JB		 2168static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2169{
2170 struct ixgbe_hw *hw = &adapter->hw;
2171
2172 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2173 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2174 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2175 /* write to clear the interrupt */
2176 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2177 }
2178}
cf8280ee 2179
4f51bf70
JK		 2180static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2181{
2182 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2183 return;
2184
2185 switch (adapter->hw.mac.type) {
2186 case ixgbe_mac_82599EB:
2187 /*
2188 * Need to check link state so complete overtemp check
2189 * on service task
2190 */
2191 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2192 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2193 adapter->interrupt_event = eicr;
2194 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2195 ixgbe_service_event_schedule(adapter);
2196 return;
2197 }
2198 return;
2199 case ixgbe_mac_X540:
2200 if (!(eicr & IXGBE_EICR_TS))
2201 return;
2202 break;
2203 default:
2204 return;
2205 }
2206
2207 e_crit(drv,
2208 "Network adapter has been stopped because it has over heated. "
2209 "Restart the computer. If the problem persists, "
2210 "power off the system and replace the adapter\n");
2211}
2212
e8e26350
PW		 2213static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2214{
2215 struct ixgbe_hw *hw = &adapter->hw;
2216
73c4b7cd
AD		 2217 if (eicr & IXGBE_EICR_GPI_SDP2) {
2218 /* Clear the interrupt */
2219 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2220 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2221 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2222 ixgbe_service_event_schedule(adapter);
2223 }
73c4b7cd
AD		 2224 }
2225
e8e26350
PW		 2226 if (eicr & IXGBE_EICR_GPI_SDP1) {
2227 /* Clear the interrupt */
2228 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2229 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2230 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2231 ixgbe_service_event_schedule(adapter);
2232 }
e8e26350
PW		 2233 }
2234}
2235
cf8280ee
JB		 2236static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2237{
2238 struct ixgbe_hw *hw = &adapter->hw;
2239
2240 adapter->lsc_int++;
2241 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2242 adapter->link_check_timeout = jiffies;
2243 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2244 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2245 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2246 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2247 }
2248}
2249
fe49f04a
AD		 2250static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2251 u64 qmask)
2252{
2253 u32 mask;
bd508178 2254 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2255
bd508178
AD		 2256 switch (hw->mac.type) {
2257 case ixgbe_mac_82598EB:
fe49f04a 2258 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2259 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2260 break;
2261 case ixgbe_mac_82599EB:
b93a2226 2262 case ixgbe_mac_X540:
fe49f04a 2263 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2264 if (mask)
2265 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2266 mask = (qmask >> 32);
bd508178
AD		 2267 if (mask)
2268 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2269 break;
2270 default:
2271 break;
fe49f04a
AD		 2272 }
2273 /* skip the flush */
2274}
2275
2276static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2277 u64 qmask)
fe49f04a
AD		 2278{
2279 u32 mask;
bd508178 2280 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2281
bd508178
AD		 2282 switch (hw->mac.type) {
2283 case ixgbe_mac_82598EB:
fe49f04a 2284 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2285 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2286 break;
2287 case ixgbe_mac_82599EB:
b93a2226 2288 case ixgbe_mac_X540:
fe49f04a 2289 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2290 if (mask)
2291 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2292 mask = (qmask >> 32);
bd508178
AD		 2293 if (mask)
2294 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2295 break;
2296 default:
2297 break;
fe49f04a
AD		 2298 }
2299 /* skip the flush */
2300}
2301
021230d4 2302/**
2c4af694
AD		 2303 * ixgbe_irq_enable - Enable default interrupt generation settings
2304 * @adapter: board private structure
021230d4 2305 **/
2c4af694
AD		 2306static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2307 bool flush)
9a799d71 2308{
2c4af694 2309 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2310
2c4af694
AD		 2311 /* don't reenable LSC while waiting for link */
2312 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2313 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2314
2c4af694 2315 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2316 switch (adapter->hw.mac.type) {
2317 case ixgbe_mac_82599EB:
2318 mask |= IXGBE_EIMS_GPI_SDP0;
2319 break;
2320 case ixgbe_mac_X540:
2321 mask |= IXGBE_EIMS_TS;
2322 break;
2323 default:
2324 break;
2325 }
2c4af694
AD		 2326 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2327 mask |= IXGBE_EIMS_GPI_SDP1;
2328 switch (adapter->hw.mac.type) {
2329 case ixgbe_mac_82599EB:
2c4af694
AD		 2330 mask |= IXGBE_EIMS_GPI_SDP1;
2331 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2332 case ixgbe_mac_X540:
2333 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2334 mask |= IXGBE_EIMS_MAILBOX;
2335 break;
2336 default:
2337 break;
9a799d71 2338 }
db0677fa
JK		 2339
2340#ifdef CONFIG_IXGBE_PTP
2341 if (adapter->hw.mac.type == ixgbe_mac_X540)
2342 mask |= IXGBE_EIMS_TIMESYNC;
2343#endif
2344
2c4af694
AD		 2345 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2346 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2347 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2348
2c4af694
AD		 2349 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2350 if (queues)
2351 ixgbe_irq_enable_queues(adapter, ~0);
2352 if (flush)
2353 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2354}
2355
2c4af694 2356static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2357{
a65151ba 2358 struct ixgbe_adapter *adapter = data;
9a799d71 2359 struct ixgbe_hw *hw = &adapter->hw;
54037505 2360 u32 eicr;
91281fd3 2361
54037505
DS		 2362 /*
2363 * Workaround for Silicon errata. Use clear-by-write instead
2364 * of clear-by-read. Reading with EICS will return the
2365 * interrupt causes without clearing, which later be done
2366 * with the write to EICR.
2367 */
2368 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2369 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2370
cf8280ee
JB		 2371 if (eicr & IXGBE_EICR_LSC)
2372 ixgbe_check_lsc(adapter);
f0848276 2373
1cdd1ec8
GR		 2374 if (eicr & IXGBE_EICR_MAILBOX)
2375 ixgbe_msg_task(adapter);
efe3d3c8 2376
bd508178
AD		 2377 switch (hw->mac.type) {
2378 case ixgbe_mac_82599EB:
b93a2226 2379 case ixgbe_mac_X540:
2c4af694
AD		 2380 if (eicr & IXGBE_EICR_ECC)
2381 e_info(link, "Received unrecoverable ECC Err, please "
2382 "reboot\n");
c4cf55e5
PWJ		 2383 /* Handle Flow Director Full threshold interrupt */
2384 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2385 int reinit_count = 0;
c4cf55e5 2386 int i;
c4cf55e5 2387 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2388 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2389 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2390 &ring->state))
2391 reinit_count++;
2392 }
2393 if (reinit_count) {
2394 /* no more flow director interrupts until after init */
2395 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2396 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2397 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2398 }
2399 }
f0f9778d 2400 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2401 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2402 break;
2403 default:
2404 break;
c4cf55e5 2405 }
f0848276 2406
bd508178 2407 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2408
681ae1ad 2409#ifdef CONFIG_IXGBE_PTP
db0677fa
JK		 2410 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2411 ixgbe_ptp_check_pps_event(adapter, eicr);
681ae1ad 2412#endif
efe3d3c8 2413
7086400d 2414 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2415 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2416 ixgbe_irq_enable(adapter, false, false);
f0848276 2417
9a799d71 2418 return IRQ_HANDLED;
f0848276 2419}
91281fd3 2420
4ff7fb12 2421static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2422{
021230d4 2423 struct ixgbe_q_vector *q_vector = data;
91281fd3 2424
9b471446 2425 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2426
4ff7fb12
AD		 2427 if (q_vector->rx.ring || q_vector->tx.ring)
2428 napi_schedule(&q_vector->napi);
91281fd3 2429
9a799d71 2430 return IRQ_HANDLED;
91281fd3
AD		 2431}
2432
eb01b975
AD		 2433/**
2434 * ixgbe_poll - NAPI Rx polling callback
2435 * @napi: structure for representing this polling device
2436 * @budget: how many packets driver is allowed to clean
2437 *
2438 * This function is used for legacy and MSI, NAPI mode
2439 **/
8af3c33f 2440int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2441{
2442 struct ixgbe_q_vector *q_vector =
2443 container_of(napi, struct ixgbe_q_vector, napi);
2444 struct ixgbe_adapter *adapter = q_vector->adapter;
2445 struct ixgbe_ring *ring;
2446 int per_ring_budget;
2447 bool clean_complete = true;
2448
2449#ifdef CONFIG_IXGBE_DCA
2450 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2451 ixgbe_update_dca(q_vector);
2452#endif
2453
2454 ixgbe_for_each_ring(ring, q_vector->tx)
2455 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2456
2457 /* attempt to distribute budget to each queue fairly, but don't allow
2458 * the budget to go below 1 because we'll exit polling */
2459 if (q_vector->rx.count > 1)
2460 per_ring_budget = max(budget/q_vector->rx.count, 1);
2461 else
2462 per_ring_budget = budget;
2463
2464 ixgbe_for_each_ring(ring, q_vector->rx)
2465 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2466 per_ring_budget);
2467
2468 /* If all work not completed, return budget and keep polling */
2469 if (!clean_complete)
2470 return budget;
2471
2472 /* all work done, exit the polling mode */
2473 napi_complete(napi);
2474 if (adapter->rx_itr_setting & 1)
2475 ixgbe_set_itr(q_vector);
2476 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2477 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2478
2479 return 0;
2480}
2481
021230d4
AV		 2482/**
2483 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2484 * @adapter: board private structure
2485 *
2486 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2487 * interrupts from the kernel.
2488 **/
2489static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2490{
2491 struct net_device *netdev = adapter->netdev;
207867f5 2492 int vector, err;
e8e9f696 2493 int ri = 0, ti = 0;
021230d4 2494
49c7ffbe 2495 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2496 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2497 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2498
4ff7fb12 2499 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2500 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2501 "%s-%s-%d", netdev->name, "TxRx", ri++);
2502 ti++;
2503 } else if (q_vector->rx.ring) {
9fe93afd 2504 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2505 "%s-%s-%d", netdev->name, "rx", ri++);
2506 } else if (q_vector->tx.ring) {
9fe93afd 2507 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2508 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2509 } else {
2510 /* skip this unused q_vector */
2511 continue;
32aa77a4 2512 }
207867f5
AD		 2513 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2514 q_vector->name, q_vector);
9a799d71 2515 if (err) {
396e799c 2516 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2517 "Error: %d\n", err);
021230d4 2518 goto free_queue_irqs;
9a799d71 2519 }
207867f5
AD		 2520 /* If Flow Director is enabled, set interrupt affinity */
2521 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2522 /* assign the mask for this irq */
2523 irq_set_affinity_hint(entry->vector,
de88eeeb 2524 &q_vector->affinity_mask);
207867f5 2525 }
9a799d71
AK		 2526 }
2527
021230d4 2528 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2529 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2530 if (err) {
de88eeeb 2531 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2532 goto free_queue_irqs;
9a799d71
AK		 2533 }
2534
9a799d71
AK		 2535 return 0;
2536
021230d4 2537free_queue_irqs:
207867f5
AD		 2538 while (vector) {
2539 vector--;
2540 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2541 NULL);
2542 free_irq(adapter->msix_entries[vector].vector,
2543 adapter->q_vector[vector]);
2544 }
021230d4
AV		 2545 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2546 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2547 kfree(adapter->msix_entries);
2548 adapter->msix_entries = NULL;
9a799d71
AK		 2549 return err;
2550}
2551
2552/**
021230d4 2553 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2554 * @irq: interrupt number
2555 * @data: pointer to a network interface device structure
9a799d71
AK		 2556 **/
2557static irqreturn_t ixgbe_intr(int irq, void *data)
2558{
a65151ba 2559 struct ixgbe_adapter *adapter = data;
9a799d71 2560 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2561 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2562 u32 eicr;
2563
54037505 2564 /*
24ddd967 2565 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2566 * before the read of EICR.
2567 */
2568 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2569
021230d4 2570 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2571 * therefore no explicit interrupt disable is necessary */
021230d4 2572 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2573 if (!eicr) {
6af3b9eb
ET		 2574 /*
2575 * shared interrupt alert!
f47cf66e 2576 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2577 * have disabled interrupts due to EIAM
2578 * finish the workaround of silicon errata on 82598. Unmask
2579 * the interrupt that we masked before the EICR read.
2580 */
2581 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2582 ixgbe_irq_enable(adapter, true, true);
9a799d71 2583 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2584 }
9a799d71 2585
cf8280ee
JB		 2586 if (eicr & IXGBE_EICR_LSC)
2587 ixgbe_check_lsc(adapter);
021230d4 2588
bd508178
AD		 2589 switch (hw->mac.type) {
2590 case ixgbe_mac_82599EB:
e8e26350 2591 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2592 /* Fall through */
2593 case ixgbe_mac_X540:
2594 if (eicr & IXGBE_EICR_ECC)
2595 e_info(link, "Received unrecoverable ECC err, please "
2596 "reboot\n");
4f51bf70 2597 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2598 break;
2599 default:
2600 break;
2601 }
e8e26350 2602
0befdb3e 2603 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad 2604#ifdef CONFIG_IXGBE_PTP
db0677fa
JK		 2605 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2606 ixgbe_ptp_check_pps_event(adapter, eicr);
681ae1ad 2607#endif
0befdb3e 2608
b9f6ed2b
AD		 2609 /* would disable interrupts here but EIAM disabled it */
2610 napi_schedule(&q_vector->napi);
9a799d71 2611
6af3b9eb
ET		 2612 /*
2613 * re-enable link(maybe) and non-queue interrupts, no flush.
2614 * ixgbe_poll will re-enable the queue interrupts
2615 */
6af3b9eb
ET		 2616 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2617 ixgbe_irq_enable(adapter, false, false);
2618
9a799d71
AK		 2619 return IRQ_HANDLED;
2620}
2621
2622/**
2623 * ixgbe_request_irq - initialize interrupts
2624 * @adapter: board private structure
2625 *
2626 * Attempts to configure interrupts using the best available
2627 * capabilities of the hardware and kernel.
2628 **/
021230d4 2629static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2630{
2631 struct net_device *netdev = adapter->netdev;
021230d4 2632 int err;
9a799d71 2633
4cc6df29 2634 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2635 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2636 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2637 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2638 netdev->name, adapter);
4cc6df29 2639 else
a0607fd3 2640 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2641 netdev->name, adapter);
9a799d71 2642
de88eeeb 2643 if (err)
396e799c 2644 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2645
9a799d71
AK		 2646 return err;
2647}
2648
2649static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2650{
49c7ffbe 2651 int vector;
9a799d71 2652
49c7ffbe
AD		 2653 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2654 free_irq(adapter->pdev->irq, adapter);
2655 return;
2656 }
4cc6df29 2657
49c7ffbe
AD		 2658 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2659 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2660 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2661
49c7ffbe
AD		 2662 /* free only the irqs that were actually requested */
2663 if (!q_vector->rx.ring && !q_vector->tx.ring)
2664 continue;
207867f5 2665
49c7ffbe
AD		 2666 /* clear the affinity_mask in the IRQ descriptor */
2667 irq_set_affinity_hint(entry->vector, NULL);
2668
2669 free_irq(entry->vector, q_vector);
9a799d71 2670 }
49c7ffbe
AD		 2671
2672 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2673}
2674
22d5a71b
JB		 2675/**
2676 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2677 * @adapter: board private structure
2678 **/
2679static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2680{
bd508178
AD		 2681 switch (adapter->hw.mac.type) {
2682 case ixgbe_mac_82598EB:
835462fc 2683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2684 break;
2685 case ixgbe_mac_82599EB:
b93a2226 2686 case ixgbe_mac_X540:
835462fc
NS		 2687 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2688 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2689 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2690 break;
2691 default:
2692 break;
22d5a71b
JB		 2693 }
2694 IXGBE_WRITE_FLUSH(&adapter->hw);
2695 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2696 int vector;
2697
2698 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2699 synchronize_irq(adapter->msix_entries[vector].vector);
2700
2701 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2702 } else {
2703 synchronize_irq(adapter->pdev->irq);
2704 }
2705}
2706
9a799d71
AK		 2707/**
2708 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2709 *
2710 **/
2711static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2712{
d5bf4f67 2713 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2714
d5bf4f67
ET		 2715 /* rx/tx vector */
2716 if (adapter->rx_itr_setting == 1)
2717 q_vector->itr = IXGBE_20K_ITR;
2718 else
2719 q_vector->itr = adapter->rx_itr_setting;
2720
2721 ixgbe_write_eitr(q_vector);
9a799d71 2722
e8e26350
PW		 2723 ixgbe_set_ivar(adapter, 0, 0, 0);
2724 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2725
396e799c 2726 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2727}
2728
43e69bf0
AD		 2729/**
2730 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2731 * @adapter: board private structure
2732 * @ring: structure containing ring specific data
2733 *
2734 * Configure the Tx descriptor ring after a reset.
2735 **/
84418e3b
AD		 2736void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2737 struct ixgbe_ring *ring)
43e69bf0
AD		 2738{
2739 struct ixgbe_hw *hw = &adapter->hw;
2740 u64 tdba = ring->dma;
2f1860b8 2741 int wait_loop = 10;
b88c6de2 2742 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2743 u8 reg_idx = ring->reg_idx;
43e69bf0 2744
2f1860b8 2745 /* disable queue to avoid issues while updating state */
b88c6de2 2746 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2747 IXGBE_WRITE_FLUSH(hw);
2748
43e69bf0 2749 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2750 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2751 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2752 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2753 ring->count * sizeof(union ixgbe_adv_tx_desc));
2754 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2755 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2756 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2757
b88c6de2
AD		 2758 /*
2759 * set WTHRESH to encourage burst writeback, it should not be set
2760 * higher than 1 when ITR is 0 as it could cause false TX hangs
2761 *
2762 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2763 * to or less than the number of on chip descriptors, which is
2764 * currently 40.
2765 */
e954b374 2766 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2767 txdctl |= (1 << 16); /* WTHRESH = 1 */
2768 else
2769 txdctl |= (8 << 16); /* WTHRESH = 8 */
2770
e954b374
AD		 2771 /*
2772 * Setting PTHRESH to 32 both improves performance
2773 * and avoids a TX hang with DFP enabled
2774 */
b88c6de2
AD		 2775 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2776 32; /* PTHRESH = 32 */
2f1860b8
AD		 2777
2778 /* reinitialize flowdirector state */
39cb681b 2779 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2780 ring->atr_sample_rate = adapter->atr_sample_rate;
2781 ring->atr_count = 0;
2782 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2783 } else {
2784 ring->atr_sample_rate = 0;
2785 }
2f1860b8 2786
c84d324c
JF		 2787 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2788
2f1860b8 2789 /* enable queue */
2f1860b8
AD		 2790 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2791
2792 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2793 if (hw->mac.type == ixgbe_mac_82598EB &&
2794 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2795 return;
2796
2797 /* poll to verify queue is enabled */
2798 do {
032b4325 2799 usleep_range(1000, 2000);
2f1860b8
AD		 2800 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2801 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2802 if (!wait_loop)
2803 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2804}
2805
120ff942
AD		 2806static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2807{
2808 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2809 u32 rttdcs, mtqc;
8b1c0b24 2810 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2811
2812 if (hw->mac.type == ixgbe_mac_82598EB)
2813 return;
2814
2815 /* disable the arbiter while setting MTQC */
2816 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2817 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2818 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2819
2820 /* set transmit pool layout */
671c0adb
AD		 2821 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2822 mtqc = IXGBE_MTQC_VT_ENA;
2823 if (tcs > 4)
2824 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2825 else if (tcs > 1)
2826 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2827 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2828 mtqc |= IXGBE_MTQC_32VF;
2829 else
2830 mtqc |= IXGBE_MTQC_64VF;
2831 } else {
2832 if (tcs > 4)
2833 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2834 else if (tcs > 1)
2835 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2836 else
671c0adb
AD		 2837 mtqc = IXGBE_MTQC_64Q_1PB;
2838 }
120ff942 2839
671c0adb 2840 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2841
671c0adb
AD		 2842 /* Enable Security TX Buffer IFG for multiple pb */
2843 if (tcs) {
2844 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2845 sectx |= IXGBE_SECTX_DCB;
2846 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2847 }
2848
2849 /* re-enable the arbiter */
2850 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2851 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2852}
2853
9a799d71 2854/**
3a581073 2855 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2856 * @adapter: board private structure
2857 *
2858 * Configure the Tx unit of the MAC after a reset.
2859 **/
2860static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2861{
2f1860b8
AD		 2862 struct ixgbe_hw *hw = &adapter->hw;
2863 u32 dmatxctl;
43e69bf0 2864 u32 i;
9a799d71 2865
2f1860b8
AD		 2866 ixgbe_setup_mtqc(adapter);
2867
2868 if (hw->mac.type != ixgbe_mac_82598EB) {
2869 /* DMATXCTL.EN must be before Tx queues are enabled */
2870 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2871 dmatxctl |= IXGBE_DMATXCTL_TE;
2872 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2873 }
2874
9a799d71 2875 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2876 for (i = 0; i < adapter->num_tx_queues; i++)
2877 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2878}
2879
3ebe8fde
AD		 2880static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2881 struct ixgbe_ring *ring)
2882{
2883 struct ixgbe_hw *hw = &adapter->hw;
2884 u8 reg_idx = ring->reg_idx;
2885 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2886
2887 srrctl |= IXGBE_SRRCTL_DROP_EN;
2888
2889 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2890}
2891
2892static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2893 struct ixgbe_ring *ring)
2894{
2895 struct ixgbe_hw *hw = &adapter->hw;
2896 u8 reg_idx = ring->reg_idx;
2897 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2898
2899 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2900
2901 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2902}
2903
2904#ifdef CONFIG_IXGBE_DCB
2905void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2906#else
2907static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2908#endif
2909{
2910 int i;
2911 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2912
2913 if (adapter->ixgbe_ieee_pfc)
2914 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2915
2916 /*
2917 * We should set the drop enable bit if:
2918 * SR-IOV is enabled
2919 * or
2920 * Number of Rx queues > 1 and flow control is disabled
2921 *
2922 * This allows us to avoid head of line blocking for security
2923 * and performance reasons.
2924 */
2925 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2926 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2927 for (i = 0; i < adapter->num_rx_queues; i++)
2928 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2929 } else {
2930 for (i = 0; i < adapter->num_rx_queues; i++)
2931 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2932 }
2933}
2934
e8e26350 2935#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2936
a6616b42 2937static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2938 struct ixgbe_ring *rx_ring)
cc41ac7c 2939{
45e9baa5 2940 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2941 u32 srrctl;
bf29ee6c 2942 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2943
45e9baa5
AD		 2944 if (hw->mac.type == ixgbe_mac_82598EB) {
2945 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2946
45e9baa5
AD		 2947 /*
2948 * if VMDq is not active we must program one srrctl register
2949 * per RSS queue since we have enabled RDRXCTL.MVMEN
2950 */
2951 reg_idx &= mask;
2952 }
cc41ac7c 2953
45e9baa5
AD		 2954 /* configure header buffer length, needed for RSC */
2955 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2956
45e9baa5 2957 /* configure the packet buffer length */
f800326d 2958 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2959
2960 /* configure descriptor type */
f800326d 2961 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2962
45e9baa5 2963 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2964}
9a799d71 2965
05abb126 2966static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2967{
05abb126
AD		 2968 struct ixgbe_hw *hw = &adapter->hw;
2969 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2970 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2971 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2972 u32 mrqc = 0, reta = 0;
2973 u32 rxcsum;
2974 int i, j;
671c0adb
AD		 2975 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2976
671c0adb
AD		 2977 /*
2978 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2979 * make full use of any rings they may have. We will use the
2980 * PSRTYPE register to control how many rings we use within the PF.
2981 */
2982 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2983 rss_i = 2;
0cefafad 2984
05abb126
AD		 2985 /* Fill out hash function seeds */
2986 for (i = 0; i < 10; i++)
2987 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2988
2989 /* Fill out redirection table */
2990 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 2991 if (j == rss_i)
05abb126
AD		 2992 j = 0;
2993 /* reta = 4-byte sliding window of
2994 * 0x00..(indices-1)(indices-1)00..etc. */
2995 reta = (reta << 8) | (j * 0x11);
2996 if ((i & 3) == 3)
2997 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2998 }
0cefafad 2999
05abb126
AD		 3000 /* Disable indicating checksum in descriptor, enables RSS hash */
3001 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3002 rxcsum |= IXGBE_RXCSUM_PCSD;
3003 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3004
671c0adb 3005 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3006 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3007 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3008 } else {
671c0adb
AD		 3009 u8 tcs = netdev_get_num_tc(adapter->netdev);
3010
3011 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3012 if (tcs > 4)
3013 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3014 else if (tcs > 1)
3015 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3016 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3017 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3018 else
671c0adb
AD		 3019 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3020 } else {
3021 if (tcs > 4)
8b1c0b24 3022 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3023 else if (tcs > 1)
3024 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3025 else
3026 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3027 }
0cefafad
JB		 3028 }
3029
05abb126 3030 /* Perform hash on these packet types */
671c0adb
AD		 3031 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3032 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3033 IXGBE_MRQC_RSS_FIELD_IPV6 |
3034 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3035
ef6afc0c
AD		 3036 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3037 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3038 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3039 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3040
05abb126 3041 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3042}
3043
bb5a9ad2
NS		 3044/**
3045 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3046 * @adapter: address of board private structure
3047 * @index: index of ring to set
bb5a9ad2 3048 **/
082757af 3049static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3050 struct ixgbe_ring *ring)
bb5a9ad2 3051{
bb5a9ad2 3052 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3053 u32 rscctrl;
bf29ee6c 3054 u8 reg_idx = ring->reg_idx;
7367096a 3055
7d637bcc 3056 if (!ring_is_rsc_enabled(ring))
7367096a 3057 return;
bb5a9ad2 3058
7367096a 3059 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3060 rscctrl |= IXGBE_RSCCTL_RSCEN;
3061 /*
3062 * we must limit the number of descriptors so that the
3063 * total size of max desc * buf_len is not greater
642c680e 3064 * than 65536
bb5a9ad2 3065 */
f800326d 3066 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3067 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3068}
3069
9e10e045
AD		 3070#define IXGBE_MAX_RX_DESC_POLL 10
3071static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3072 struct ixgbe_ring *ring)
3073{
3074 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3075 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3076 u32 rxdctl;
bf29ee6c 3077 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3078
3079 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3080 if (hw->mac.type == ixgbe_mac_82598EB &&
3081 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3082 return;
3083
3084 do {
032b4325 3085 usleep_range(1000, 2000);
9e10e045
AD		 3086 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3087 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3088
3089 if (!wait_loop) {
3090 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3091 "the polling period\n", reg_idx);
3092 }
3093}
3094
2d39d576
YZ		 3095void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3096 struct ixgbe_ring *ring)
3097{
3098 struct ixgbe_hw *hw = &adapter->hw;
3099 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3100 u32 rxdctl;
3101 u8 reg_idx = ring->reg_idx;
3102
3103 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3104 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3105
3106 /* write value back with RXDCTL.ENABLE bit cleared */
3107 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3108
3109 if (hw->mac.type == ixgbe_mac_82598EB &&
3110 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3111 return;
3112
3113 /* the hardware may take up to 100us to really disable the rx queue */
3114 do {
3115 udelay(10);
3116 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3117 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3118
3119 if (!wait_loop) {
3120 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3121 "the polling period\n", reg_idx);
3122 }
3123}
3124
84418e3b
AD		 3125void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3126 struct ixgbe_ring *ring)
acd37177
AD		 3127{
3128 struct ixgbe_hw *hw = &adapter->hw;
3129 u64 rdba = ring->dma;
9e10e045 3130 u32 rxdctl;
bf29ee6c 3131 u8 reg_idx = ring->reg_idx;
acd37177 3132
9e10e045
AD		 3133 /* disable queue to avoid issues while updating state */
3134 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3135 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3136
acd37177
AD		 3137 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3138 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3139 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3140 ring->count * sizeof(union ixgbe_adv_rx_desc));
3141 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3142 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3143 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3144
3145 ixgbe_configure_srrctl(adapter, ring);
3146 ixgbe_configure_rscctl(adapter, ring);
3147
e9f98072
GR		 3148 /* If operating in IOV mode set RLPML for X540 */
3149 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3150 hw->mac.type == ixgbe_mac_X540) {
3151 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3152 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3153 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3154 }
3155
9e10e045
AD		 3156 if (hw->mac.type == ixgbe_mac_82598EB) {
3157 /*
3158 * enable cache line friendly hardware writes:
3159 * PTHRESH=32 descriptors (half the internal cache),
3160 * this also removes ugly rx_no_buffer_count increment
3161 * HTHRESH=4 descriptors (to minimize latency on fetch)
3162 * WTHRESH=8 burst writeback up to two cache lines
3163 */
3164 rxdctl &= ~0x3FFFFF;
3165 rxdctl |= 0x080420;
3166 }
3167
3168 /* enable receive descriptor ring */
3169 rxdctl |= IXGBE_RXDCTL_ENABLE;
3170 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3171
3172 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3173 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3174}
3175
48654521
AD		 3176static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3177{
3178 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3179 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3180 int p;
3181
3182 /* PSRTYPE must be initialized in non 82598 adapters */
3183 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3184 IXGBE_PSRTYPE_UDPHDR |
3185 IXGBE_PSRTYPE_IPV4HDR |
48654521 3186 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3187 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3188
3189 if (hw->mac.type == ixgbe_mac_82598EB)
3190 return;
3191
fbe7ca7f
AD		 3192 if (rss_i > 3)
3193 psrtype |= 2 << 29;
3194 else if (rss_i > 1)
3195 psrtype |= 1 << 29;
48654521
AD		 3196
3197 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3198 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3199 psrtype);
3200}
3201
f5b4a52e
AD		 3202static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3203{
3204 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3205 u32 reg_offset, vf_shift;
435b19f6 3206 u32 gcr_ext, vmdctl;
de4c7f65 3207 int i;
f5b4a52e
AD		 3208
3209 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3210 return;
3211
3212 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3213 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3214 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3215 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3216 vmdctl |= IXGBE_VT_CTL_REPLEN;
3217 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3218
1d9c0bfd
AD		 3219 vf_shift = VMDQ_P(0) % 32;
3220 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3221
3222 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3223 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3224 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3225 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3226 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3227 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3228
3229 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3230 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3231
3232 /*
3233 * Set up VF register offsets for selected VT Mode,
3234 * i.e. 32 or 64 VFs for SR-IOV
3235 */
73079ea0
AD		 3236 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3237 case IXGBE_82599_VMDQ_8Q_MASK:
3238 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3239 break;
3240 case IXGBE_82599_VMDQ_4Q_MASK:
3241 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3242 break;
3243 default:
3244 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3245 break;
3246 }
3247
f5b4a52e
AD		 3248 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3249
3250 /* enable Tx loopback for VF/PF communication */
3251 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
435b19f6 3252
a985b6c3 3253 /* Enable MAC Anti-Spoofing */
435b19f6 3254 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3255 adapter->num_vfs);
de4c7f65
GR		 3256 /* For VFs that have spoof checking turned off */
3257 for (i = 0; i < adapter->num_vfs; i++) {
3258 if (!adapter->vfinfo[i].spoofchk_enabled)
3259 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3260 }
f5b4a52e
AD		 3261}
3262
477de6ed 3263static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3264{
9a799d71
AK		 3265 struct ixgbe_hw *hw = &adapter->hw;
3266 struct net_device *netdev = adapter->netdev;
3267 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3268 struct ixgbe_ring *rx_ring;
3269 int i;
3270 u32 mhadd, hlreg0;
48654521 3271
63f39bd1 3272#ifdef IXGBE_FCOE
477de6ed
AD		 3273 /* adjust max frame to be able to do baby jumbo for FCoE */
3274 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3275 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3276 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3277
477de6ed 3278#endif /* IXGBE_FCOE */
872844dd
AD		 3279
3280 /* adjust max frame to be at least the size of a standard frame */
3281 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3282 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3283
477de6ed
AD		 3284 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3285 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3286 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3287 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3288
3289 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3290 }
3291
3292 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3293 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3294 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3295 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3296
0cefafad
JB		 3297 /*
3298 * Setup the HW Rx Head and Tail Descriptor Pointers and
3299 * the Base and Length of the Rx Descriptor Ring
3300 */
9a799d71 3301 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3302 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3303 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3304 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3305 else
7d637bcc 3306 clear_ring_rsc_enabled(rx_ring);
477de6ed 3307 }
477de6ed
AD		 3308}
3309
7367096a
AD		 3310static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3311{
3312 struct ixgbe_hw *hw = &adapter->hw;
3313 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3314
3315 switch (hw->mac.type) {
3316 case ixgbe_mac_82598EB:
3317 /*
3318 * For VMDq support of different descriptor types or
3319 * buffer sizes through the use of multiple SRRCTL
3320 * registers, RDRXCTL.MVMEN must be set to 1
3321 *
3322 * also, the manual doesn't mention it clearly but DCA hints
3323 * will only use queue 0's tags unless this bit is set. Side
3324 * effects of setting this bit are only that SRRCTL must be
3325 * fully programmed [0..15]
3326 */
3327 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3328 break;
3329 case ixgbe_mac_82599EB:
b93a2226 3330 case ixgbe_mac_X540:
7367096a
AD		 3331 /* Disable RSC for ACK packets */
3332 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3333 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3334 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3335 /* hardware requires some bits to be set by default */
3336 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3337 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3338 break;
3339 default:
3340 /* We should do nothing since we don't know this hardware */
3341 return;
3342 }
3343
3344 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3345}
3346
477de6ed
AD		 3347/**
3348 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3349 * @adapter: board private structure
3350 *
3351 * Configure the Rx unit of the MAC after a reset.
3352 **/
3353static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3354{
3355 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3356 int i;
3357 u32 rxctrl;
477de6ed
AD		 3358
3359 /* disable receives while setting up the descriptors */
3360 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3361 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3362
3363 ixgbe_setup_psrtype(adapter);
7367096a 3364 ixgbe_setup_rdrxctl(adapter);
477de6ed 3365
9e10e045 3366 /* Program registers for the distribution of queues */
f5b4a52e 3367 ixgbe_setup_mrqc(adapter);
f5b4a52e 3368
477de6ed
AD		 3369 /* set_rx_buffer_len must be called before ring initialization */
3370 ixgbe_set_rx_buffer_len(adapter);
3371
3372 /*
3373 * Setup the HW Rx Head and Tail Descriptor Pointers and
3374 * the Base and Length of the Rx Descriptor Ring
3375 */
9e10e045
AD		 3376 for (i = 0; i < adapter->num_rx_queues; i++)
3377 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3378
9e10e045
AD		 3379 /* disable drop enable for 82598 parts */
3380 if (hw->mac.type == ixgbe_mac_82598EB)
3381 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3382
3383 /* enable all receives */
3384 rxctrl |= IXGBE_RXCTRL_RXEN;
3385 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3386}
3387
8e586137 3388static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3389{
3390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3391 struct ixgbe_hw *hw = &adapter->hw;
3392
3393 /* add VID to filter table */
1d9c0bfd 3394 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3395 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3396
3397 return 0;
068c89b0
DS		 3398}
3399
8e586137 3400static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3401{
3402 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3403 struct ixgbe_hw *hw = &adapter->hw;
3404
068c89b0 3405 /* remove VID from filter table */
1d9c0bfd 3406 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3407 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3408
3409 return 0;
068c89b0
DS		 3410}
3411
5f6c0181
JB		 3412/**
3413 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3414 * @adapter: driver data
3415 */
3416static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3417{
3418 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3419 u32 vlnctrl;
3420
3421 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3422 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3423 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3424}
3425
3426/**
3427 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3428 * @adapter: driver data
3429 */
3430static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3431{
3432 struct ixgbe_hw *hw = &adapter->hw;
3433 u32 vlnctrl;
3434
3435 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3436 vlnctrl |= IXGBE_VLNCTRL_VFE;
3437 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3438 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3439}
3440
3441/**
3442 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3443 * @adapter: driver data
3444 */
3445static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3446{
3447 struct ixgbe_hw *hw = &adapter->hw;
3448 u32 vlnctrl;
5f6c0181
JB		 3449 int i, j;
3450
3451 switch (hw->mac.type) {
3452 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3453 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3454 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3455 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3456 break;
3457 case ixgbe_mac_82599EB:
b93a2226 3458 case ixgbe_mac_X540:
5f6c0181
JB		 3459 for (i = 0; i < adapter->num_rx_queues; i++) {
3460 j = adapter->rx_ring[i]->reg_idx;
3461 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3462 vlnctrl &= ~IXGBE_RXDCTL_VME;
3463 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3464 }
3465 break;
3466 default:
3467 break;
3468 }
3469}
3470
3471/**
f62bbb5e 3472 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3473 * @adapter: driver data
3474 */
f62bbb5e 3475static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3476{
3477 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3478 u32 vlnctrl;
5f6c0181
JB		 3479 int i, j;
3480
3481 switch (hw->mac.type) {
3482 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3483 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3484 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3485 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3486 break;
3487 case ixgbe_mac_82599EB:
b93a2226 3488 case ixgbe_mac_X540:
5f6c0181
JB		 3489 for (i = 0; i < adapter->num_rx_queues; i++) {
3490 j = adapter->rx_ring[i]->reg_idx;
3491 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3492 vlnctrl |= IXGBE_RXDCTL_VME;
3493 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3494 }
3495 break;
3496 default:
3497 break;
3498 }
3499}
3500
9a799d71
AK		 3501static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3502{
f62bbb5e 3503 u16 vid;
9a799d71 3504
f62bbb5e
JG		 3505 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3506
3507 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3508 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3509}
3510
2850062a
AD		 3511/**
3512 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3513 * @netdev: network interface device structure
3514 *
3515 * Writes unicast address list to the RAR table.
3516 * Returns: -ENOMEM on failure/insufficient address space
3517 * 0 on no addresses written
3518 * X on writing X addresses to the RAR table
3519 **/
3520static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3521{
3522 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3523 struct ixgbe_hw *hw = &adapter->hw;
95447461 3524 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3525 int count = 0;
3526
95447461
JF		 3527 /* In SR-IOV mode significantly less RAR entries are available */
3528 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3529 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3530
2850062a
AD		 3531 /* return ENOMEM indicating insufficient memory for addresses */
3532 if (netdev_uc_count(netdev) > rar_entries)
3533 return -ENOMEM;
3534
95447461 3535 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3536 struct netdev_hw_addr *ha;
3537 /* return error if we do not support writing to RAR table */
3538 if (!hw->mac.ops.set_rar)
3539 return -ENOMEM;
3540
3541 netdev_for_each_uc_addr(ha, netdev) {
3542 if (!rar_entries)
3543 break;
3544 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3545 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3546 count++;
3547 }
3548 }
3549 /* write the addresses in reverse order to avoid write combining */
3550 for (; rar_entries > 0 ; rar_entries--)
3551 hw->mac.ops.clear_rar(hw, rar_entries);
3552
3553 return count;
3554}
3555
9a799d71 3556/**
2c5645cf 3557 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3558 * @netdev: network interface device structure
3559 *
2c5645cf
CL		 3560 * The set_rx_method entry point is called whenever the unicast/multicast
3561 * address list or the network interface flags are updated. This routine is
3562 * responsible for configuring the hardware for proper unicast, multicast and
3563 * promiscuous mode.
9a799d71 3564 **/
7f870475 3565void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3566{
3567 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3568 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3569 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3570 int count;
9a799d71
AK		 3571
3572 /* Check for Promiscuous and All Multicast modes */
3573
3574 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3575
f5dc442b 3576 /* set all bits that we expect to always be set */
3f2d1c0f 3577 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3578 fctrl |= IXGBE_FCTRL_BAM;
3579 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3580 fctrl |= IXGBE_FCTRL_PMCF;
3581
2850062a
AD		 3582 /* clear the bits we are changing the status of */
3583 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3584
9a799d71 3585 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3586 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3587 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3588 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3589 /* don't hardware filter vlans in promisc mode */
3590 ixgbe_vlan_filter_disable(adapter);
9a799d71 3591 } else {
746b9f02
PM		 3592 if (netdev->flags & IFF_ALLMULTI) {
3593 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3594 vmolr |= IXGBE_VMOLR_MPE;
3595 } else {
3596 /*
3597 * Write addresses to the MTA, if the attempt fails
25985edc 3598 * then we should just turn on promiscuous mode so
2850062a
AD		 3599 * that we can at least receive multicast traffic
3600 */
3601 hw->mac.ops.update_mc_addr_list(hw, netdev);
3602 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3603 }
5f6c0181 3604 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3605 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3606 }
3607
3608 /*
3609 * Write addresses to available RAR registers, if there is not
3610 * sufficient space to store all the addresses then enable
3611 * unicast promiscuous mode
3612 */
3613 count = ixgbe_write_uc_addr_list(netdev);
3614 if (count < 0) {
3615 fctrl |= IXGBE_FCTRL_UPE;
3616 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3617 }
3618
1d9c0bfd 3619 if (adapter->num_vfs)
1cdd1ec8 3620 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3621
3622 if (hw->mac.type != ixgbe_mac_82598EB) {
3623 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3624 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3625 IXGBE_VMOLR_ROPE);
1d9c0bfd 3626 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3627 }
3628
3f2d1c0f
BG		 3629 /* This is useful for sniffing bad packets. */
3630 if (adapter->netdev->features & NETIF_F_RXALL) {
3631 /* UPE and MPE will be handled by normal PROMISC logic
3632 * in e1000e_set_rx_mode */
3633 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3634 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3635 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3636
3637 fctrl &= ~(IXGBE_FCTRL_DPF);
3638 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3639 }
3640
2850062a 3641 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3642
3643 if (netdev->features & NETIF_F_HW_VLAN_RX)
3644 ixgbe_vlan_strip_enable(adapter);
3645 else
3646 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3647}
3648
021230d4
AV		 3649static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3650{
3651 int q_idx;
021230d4 3652
49c7ffbe
AD		 3653 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3654 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3655}
3656
3657static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3658{
3659 int q_idx;
021230d4 3660
49c7ffbe
AD		 3661 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3662 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3663}
3664
7a6b6f51 3665#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3666/**
2f90b865
AD		 3667 * ixgbe_configure_dcb - Configure DCB hardware
3668 * @adapter: ixgbe adapter struct
3669 *
3670 * This is called by the driver on open to configure the DCB hardware.
3671 * This is also called by the gennetlink interface when reconfiguring
3672 * the DCB state.
3673 */
3674static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3675{
3676 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3677 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3678
67ebd791
AD		 3679 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3680 if (hw->mac.type == ixgbe_mac_82598EB)
3681 netif_set_gso_max_size(adapter->netdev, 65536);
3682 return;
3683 }
3684
3685 if (hw->mac.type == ixgbe_mac_82598EB)
3686 netif_set_gso_max_size(adapter->netdev, 32768);
3687
971060b1 3688#ifdef IXGBE_FCOE
b120818e
JF		 3689 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3690 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3691#endif
b120818e
JF		 3692
3693 /* reconfigure the hardware */
3694 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3695 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3696 DCB_TX_CONFIG);
3697 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3698 DCB_RX_CONFIG);
3699 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3700 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3701 ixgbe_dcb_hw_ets(&adapter->hw,
3702 adapter->ixgbe_ieee_ets,
3703 max_frame);
3704 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3705 adapter->ixgbe_ieee_pfc->pfc_en,
3706 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3707 }
8187cd48
JF		 3708
3709 /* Enable RSS Hash per TC */
3710 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3711 u32 msb = 0;
3712 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3713
d411a936
AD		 3714 while (rss_i) {
3715 msb++;
3716 rss_i >>= 1;
3717 }
8187cd48 3718
4ae63730
AD		 3719 /* write msb to all 8 TCs in one write */
3720 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3721 }
2f90b865 3722}
9da712d2
JF		 3723#endif
3724
3725/* Additional bittime to account for IXGBE framing */
3726#define IXGBE_ETH_FRAMING 20
3727
49ce9c2c 3728/**
9da712d2
JF		 3729 * ixgbe_hpbthresh - calculate high water mark for flow control
3730 *
3731 * @adapter: board private structure to calculate for
49ce9c2c 3732 * @pb: packet buffer to calculate
9da712d2
JF		 3733 */
3734static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3735{
3736 struct ixgbe_hw *hw = &adapter->hw;
3737 struct net_device *dev = adapter->netdev;
3738 int link, tc, kb, marker;
3739 u32 dv_id, rx_pba;
3740
3741 /* Calculate max LAN frame size */
3742 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3743
3744#ifdef IXGBE_FCOE
3745 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3746 if ((dev->features & NETIF_F_FCOE_MTU) &&
3747 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3748 (pb == ixgbe_fcoe_get_tc(adapter)))
3749 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3750
3751#endif
9da712d2
JF		 3752 /* Calculate delay value for device */
3753 switch (hw->mac.type) {
3754 case ixgbe_mac_X540:
3755 dv_id = IXGBE_DV_X540(link, tc);
3756 break;
3757 default:
3758 dv_id = IXGBE_DV(link, tc);
3759 break;
3760 }
3761
3762 /* Loopback switch introduces additional latency */
3763 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3764 dv_id += IXGBE_B2BT(tc);
3765
3766 /* Delay value is calculated in bit times convert to KB */
3767 kb = IXGBE_BT2KB(dv_id);
3768 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3769
3770 marker = rx_pba - kb;
3771
3772 /* It is possible that the packet buffer is not large enough
3773 * to provide required headroom. In this case throw an error
3774 * to user and a do the best we can.
3775 */
3776 if (marker < 0) {
3777 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3778 "headroom to support flow control."
3779 "Decrease MTU or number of traffic classes\n", pb);
3780 marker = tc + 1;
3781 }
3782
3783 return marker;
3784}
3785
49ce9c2c 3786/**
9da712d2
JF		 3787 * ixgbe_lpbthresh - calculate low water mark for for flow control
3788 *
3789 * @adapter: board private structure to calculate for
49ce9c2c 3790 * @pb: packet buffer to calculate
9da712d2
JF		 3791 */
3792static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3793{
3794 struct ixgbe_hw *hw = &adapter->hw;
3795 struct net_device *dev = adapter->netdev;
3796 int tc;
3797 u32 dv_id;
3798
3799 /* Calculate max LAN frame size */
3800 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3801
3802 /* Calculate delay value for device */
3803 switch (hw->mac.type) {
3804 case ixgbe_mac_X540:
3805 dv_id = IXGBE_LOW_DV_X540(tc);
3806 break;
3807 default:
3808 dv_id = IXGBE_LOW_DV(tc);
3809 break;
3810 }
3811
3812 /* Delay value is calculated in bit times convert to KB */
3813 return IXGBE_BT2KB(dv_id);
3814}
3815
3816/*
3817 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3818 */
3819static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3820{
3821 struct ixgbe_hw *hw = &adapter->hw;
3822 int num_tc = netdev_get_num_tc(adapter->netdev);
3823 int i;
3824
3825 if (!num_tc)
3826 num_tc = 1;
3827
3828 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3829
3830 for (i = 0; i < num_tc; i++) {
3831 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3832
3833 /* Low water marks must not be larger than high water marks */
3834 if (hw->fc.low_water > hw->fc.high_water[i])
3835 hw->fc.low_water = 0;
3836 }
3837}
3838
80605c65
JF		 3839static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3840{
80605c65 3841 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3842 int hdrm;
3843 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3844
3845 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3846 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3847 hdrm = 32 << adapter->fdir_pballoc;
3848 else
3849 hdrm = 0;
80605c65 3850
f7e1027f 3851 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3852 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3853}
3854
e4911d57
AD		 3855static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3856{
3857 struct ixgbe_hw *hw = &adapter->hw;
3858 struct hlist_node *node, *node2;
3859 struct ixgbe_fdir_filter *filter;
3860
3861 spin_lock(&adapter->fdir_perfect_lock);
3862
3863 if (!hlist_empty(&adapter->fdir_filter_list))
3864 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3865
3866 hlist_for_each_entry_safe(filter, node, node2,
3867 &adapter->fdir_filter_list, fdir_node) {
3868 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3869 &filter->filter,
3870 filter->sw_idx,
3871 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3872 IXGBE_FDIR_DROP_QUEUE :
3873 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3874 }
3875
3876 spin_unlock(&adapter->fdir_perfect_lock);
3877}
3878
9a799d71
AK		 3879static void ixgbe_configure(struct ixgbe_adapter *adapter)
3880{
d2f5e7f3
AS		 3881 struct ixgbe_hw *hw = &adapter->hw;
3882
80605c65 3883 ixgbe_configure_pb(adapter);
7a6b6f51 3884#ifdef CONFIG_IXGBE_DCB
67ebd791 3885 ixgbe_configure_dcb(adapter);
2f90b865 3886#endif
b35d4d42
AD		 3887 /*
3888 * We must restore virtualization before VLANs or else
3889 * the VLVF registers will not be populated
3890 */
3891 ixgbe_configure_virtualization(adapter);
9a799d71 3892
4c1d7b4b 3893 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3894 ixgbe_restore_vlan(adapter);
3895
d2f5e7f3
AS		 3896 switch (hw->mac.type) {
3897 case ixgbe_mac_82599EB:
3898 case ixgbe_mac_X540:
3899 hw->mac.ops.disable_rx_buff(hw);
3900 break;
3901 default:
3902 break;
3903 }
3904
c4cf55e5 3905 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3906 ixgbe_init_fdir_signature_82599(&adapter->hw,
3907 adapter->fdir_pballoc);
e4911d57
AD		 3908 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3909 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3910 adapter->fdir_pballoc);
3911 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3912 }
4c1d7b4b 3913
d2f5e7f3
AS		 3914 switch (hw->mac.type) {
3915 case ixgbe_mac_82599EB:
3916 case ixgbe_mac_X540:
3917 hw->mac.ops.enable_rx_buff(hw);
3918 break;
3919 default:
3920 break;
3921 }
3922
7c8ae65a
AD		 3923#ifdef IXGBE_FCOE
3924 /* configure FCoE L2 filters, redirection table, and Rx control */
3925 ixgbe_configure_fcoe(adapter);
3926
3927#endif /* IXGBE_FCOE */
9a799d71
AK		 3928 ixgbe_configure_tx(adapter);
3929 ixgbe_configure_rx(adapter);
9a799d71
AK		 3930}
3931
e8e26350
PW		 3932static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3933{
3934 switch (hw->phy.type) {
3935 case ixgbe_phy_sfp_avago:
3936 case ixgbe_phy_sfp_ftl:
3937 case ixgbe_phy_sfp_intel:
3938 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3939 case ixgbe_phy_sfp_passive_tyco:
3940 case ixgbe_phy_sfp_passive_unknown:
3941 case ixgbe_phy_sfp_active_unknown:
3942 case ixgbe_phy_sfp_ftl_active:
e8e26350 3943 return true;
8917b447
AD		 3944 case ixgbe_phy_nl:
3945 if (hw->mac.type == ixgbe_mac_82598EB)
3946 return true;
e8e26350
PW		 3947 default:
3948 return false;
3949 }
3950}
3951
0ecc061d 3952/**
e8e26350
PW		 3953 * ixgbe_sfp_link_config - set up SFP+ link
3954 * @adapter: pointer to private adapter struct
3955 **/
3956static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3957{
7086400d 3958 /*
52f33af8 3959 * We are assuming the worst case scenario here, and that
7086400d
AD		 3960 * is that an SFP was inserted/removed after the reset
3961 * but before SFP detection was enabled. As such the best
3962 * solution is to just start searching as soon as we start
3963 */
3964 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3965 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3966
7086400d 3967 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3968}
3969
3970/**
3971 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3972 * @hw: pointer to private hardware struct
3973 *
3974 * Returns 0 on success, negative on failure
3975 **/
e8e26350 3976static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3977{
3978 u32 autoneg;
8620a103 3979 bool negotiation, link_up = false;
0ecc061d
PWJ		 3980 u32 ret = IXGBE_ERR_LINK_SETUP;
3981
3982 if (hw->mac.ops.check_link)
3983 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3984
3985 if (ret)
3986 goto link_cfg_out;
3987
0b0c2b31
ET		 3988 autoneg = hw->phy.autoneg_advertised;
3989 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3990 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3991 &negotiation);
0ecc061d
PWJ		 3992 if (ret)
3993 goto link_cfg_out;
3994
8620a103
MC		 3995 if (hw->mac.ops.setup_link)
3996 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3997link_cfg_out:
3998 return ret;
3999}
4000
a34bcfff 4001static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4002{
9a799d71 4003 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4004 u32 gpie = 0;
9a799d71 4005
9b471446 4006 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4007 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4008 IXGBE_GPIE_OCD;
4009 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4010 /*
4011 * use EIAM to auto-mask when MSI-X interrupt is asserted
4012 * this saves a register write for every interrupt
4013 */
4014 switch (hw->mac.type) {
4015 case ixgbe_mac_82598EB:
4016 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4017 break;
9b471446 4018 case ixgbe_mac_82599EB:
b93a2226
DS		 4019 case ixgbe_mac_X540:
4020 default:
9b471446
JB		 4021 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4022 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4023 break;
4024 }
4025 } else {
021230d4
AV		 4026 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4027 * specifically only auto mask tx and rx interrupts */
4028 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4029 }
9a799d71 4030
a34bcfff
AD		 4031 /* XXX: to interrupt immediately for EICS writes, enable this */
4032 /* gpie |= IXGBE_GPIE_EIMEN; */
4033
4034 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4035 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4036
4037 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4038 case IXGBE_82599_VMDQ_8Q_MASK:
4039 gpie |= IXGBE_GPIE_VTMODE_16;
4040 break;
4041 case IXGBE_82599_VMDQ_4Q_MASK:
4042 gpie |= IXGBE_GPIE_VTMODE_32;
4043 break;
4044 default:
4045 gpie |= IXGBE_GPIE_VTMODE_64;
4046 break;
4047 }
119fc60a
MC		 4048 }
4049
5fdd31f9 4050 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4051 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4052 switch (adapter->hw.mac.type) {
4053 case ixgbe_mac_82599EB:
4054 gpie |= IXGBE_SDP0_GPIEN;
4055 break;
4056 case ixgbe_mac_X540:
4057 gpie |= IXGBE_EIMS_TS;
4058 break;
4059 default:
4060 break;
4061 }
4062 }
5fdd31f9 4063
a34bcfff
AD		 4064 /* Enable fan failure interrupt */
4065 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4066 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4067
2698b208 4068 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4069 gpie |= IXGBE_SDP1_GPIEN;
4070 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4071 }
a34bcfff
AD		 4072
4073 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4074}
4075
c7ccde0f 4076static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4077{
4078 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4079 int err;
a34bcfff
AD		 4080 u32 ctrl_ext;
4081
4082 ixgbe_get_hw_control(adapter);
4083 ixgbe_setup_gpie(adapter);
e8e26350 4084
9a799d71
AK		 4085 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4086 ixgbe_configure_msix(adapter);
4087 else
4088 ixgbe_configure_msi_and_legacy(adapter);
4089
c6ecf39a
DS		 4090 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4091 if (hw->mac.ops.enable_tx_laser &&
4092 ((hw->phy.multispeed_fiber) ||
9f911707 4093 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4094 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4095 hw->mac.ops.enable_tx_laser(hw);
4096
9a799d71 4097 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4098 ixgbe_napi_enable_all(adapter);
4099
73c4b7cd
AD		 4100 if (ixgbe_is_sfp(hw)) {
4101 ixgbe_sfp_link_config(adapter);
4102 } else {
4103 err = ixgbe_non_sfp_link_config(hw);
4104 if (err)
4105 e_err(probe, "link_config FAILED %d\n", err);
4106 }
4107
021230d4
AV		 4108 /* clear any pending interrupts, may auto mask */
4109 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4110 ixgbe_irq_enable(adapter, true, true);
9a799d71 4111
bf069c97
DS		 4112 /*
4113 * If this adapter has a fan, check to see if we had a failure
4114 * before we enabled the interrupt.
4115 */
4116 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4117 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4118 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4119 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4120 }
4121
1da100bb 4122 /* enable transmits */
477de6ed 4123 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4124
9a799d71
AK		 4125 /* bring the link up in the watchdog, this could race with our first
4126 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4127 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4128 adapter->link_check_timeout = jiffies;
7086400d 4129 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4130
4131 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4132 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4133 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4134 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4135}
4136
d4f80882
AV		 4137void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4138{
4139 WARN_ON(in_interrupt());
7086400d
AD		 4140 /* put off any impending NetWatchDogTimeout */
4141 adapter->netdev->trans_start = jiffies;
4142
d4f80882 4143 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4144 usleep_range(1000, 2000);
d4f80882 4145 ixgbe_down(adapter);
5809a1ae
GR		 4146 /*
4147 * If SR-IOV enabled then wait a bit before bringing the adapter
4148 * back up to give the VFs time to respond to the reset. The
4149 * two second wait is based upon the watchdog timer cycle in
4150 * the VF driver.
4151 */
4152 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4153 msleep(2000);
d4f80882
AV		 4154 ixgbe_up(adapter);
4155 clear_bit(__IXGBE_RESETTING, &adapter->state);
4156}
4157
c7ccde0f 4158void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4159{
4160 /* hardware has been reset, we need to reload some things */
4161 ixgbe_configure(adapter);
4162
c7ccde0f 4163 ixgbe_up_complete(adapter);
9a799d71
AK		 4164}
4165
4166void ixgbe_reset(struct ixgbe_adapter *adapter)
4167{
c44ade9e 4168 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4169 int err;
4170
7086400d
AD		 4171 /* lock SFP init bit to prevent race conditions with the watchdog */
4172 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4173 usleep_range(1000, 2000);
4174
4175 /* clear all SFP and link config related flags while holding SFP_INIT */
4176 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4177 IXGBE_FLAG2_SFP_NEEDS_RESET);
4178 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4179
8ca783ab 4180 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4181 switch (err) {
4182 case 0:
4183 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4184 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4185 break;
4186 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4187 e_dev_err("master disable timed out\n");
da4dd0f7 4188 break;
794caeb2
PWJ		 4189 case IXGBE_ERR_EEPROM_VERSION:
4190 /* We are running on a pre-production device, log a warning */
849c4542 4191 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4192 "Please be aware there may be issues associated with "
849c4542
ET		 4193 "your hardware. If you are experiencing problems "
4194 "please contact your Intel or hardware "
4195 "representative who provided you with this "
4196 "hardware.\n");
794caeb2 4197 break;
da4dd0f7 4198 default:
849c4542 4199 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4200 }
9a799d71 4201
7086400d
AD		 4202 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4203
9a799d71 4204 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4205 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4206
4207 /* update SAN MAC vmdq pool selection */
4208 if (hw->mac.san_mac_rar_index)
4209 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24
JK		 4210
4211#ifdef CONFIG_IXGBE_PTP
4212 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4213 ixgbe_ptp_reset(adapter);
4214#endif
9a799d71
AK		 4215}
4216
9a799d71
AK		 4217/**
4218 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4219 * @rx_ring: ring to free buffers from
4220 **/
b6ec895e 4221static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4222{
b6ec895e 4223 struct device *dev = rx_ring->dev;
9a799d71 4224 unsigned long size;
b6ec895e 4225 u16 i;
9a799d71 4226
84418e3b
AD		 4227 /* ring already cleared, nothing to do */
4228 if (!rx_ring->rx_buffer_info)
4229 return;
9a799d71 4230
84418e3b 4231 /* Free all the Rx ring sk_buffs */
9a799d71 4232 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4233 struct ixgbe_rx_buffer *rx_buffer;
4234
4235 rx_buffer = &rx_ring->rx_buffer_info[i];
4236 if (rx_buffer->skb) {
4237 struct sk_buff *skb = rx_buffer->skb;
4238 if (IXGBE_CB(skb)->page_released) {
4239 dma_unmap_page(dev,
4240 IXGBE_CB(skb)->dma,
4241 ixgbe_rx_bufsz(rx_ring),
4242 DMA_FROM_DEVICE);
4243 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4244 }
4245 dev_kfree_skb(skb);
9a799d71 4246 }
f800326d
AD		 4247 rx_buffer->skb = NULL;
4248 if (rx_buffer->dma)
4249 dma_unmap_page(dev, rx_buffer->dma,
4250 ixgbe_rx_pg_size(rx_ring),
4251 DMA_FROM_DEVICE);
4252 rx_buffer->dma = 0;
4253 if (rx_buffer->page)
dd411ec4
AD		 4254 __free_pages(rx_buffer->page,
4255 ixgbe_rx_pg_order(rx_ring));
f800326d 4256 rx_buffer->page = NULL;
9a799d71
AK		 4257 }
4258
4259 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4260 memset(rx_ring->rx_buffer_info, 0, size);
4261
4262 /* Zero out the descriptor ring */
4263 memset(rx_ring->desc, 0, rx_ring->size);
4264
f800326d 4265 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4266 rx_ring->next_to_clean = 0;
4267 rx_ring->next_to_use = 0;
9a799d71
AK		 4268}
4269
4270/**
4271 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4272 * @tx_ring: ring to be cleaned
4273 **/
b6ec895e 4274static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4275{
4276 struct ixgbe_tx_buffer *tx_buffer_info;
4277 unsigned long size;
b6ec895e 4278 u16 i;
9a799d71 4279
84418e3b
AD		 4280 /* ring already cleared, nothing to do */
4281 if (!tx_ring->tx_buffer_info)
4282 return;
9a799d71 4283
84418e3b 4284 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4285 for (i = 0; i < tx_ring->count; i++) {
4286 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4287 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4288 }
4289
dad8a3b3
JF		 4290 netdev_tx_reset_queue(txring_txq(tx_ring));
4291
9a799d71
AK		 4292 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4293 memset(tx_ring->tx_buffer_info, 0, size);
4294
4295 /* Zero out the descriptor ring */
4296 memset(tx_ring->desc, 0, tx_ring->size);
4297
4298 tx_ring->next_to_use = 0;
4299 tx_ring->next_to_clean = 0;
9a799d71
AK		 4300}
4301
4302/**
021230d4 4303 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4304 * @adapter: board private structure
4305 **/
021230d4 4306static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4307{
4308 int i;
4309
021230d4 4310 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4311 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4312}
4313
4314/**
021230d4 4315 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4316 * @adapter: board private structure
4317 **/
021230d4 4318static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4319{
4320 int i;
4321
021230d4 4322 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4323 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4324}
4325
e4911d57
AD		 4326static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4327{
4328 struct hlist_node *node, *node2;
4329 struct ixgbe_fdir_filter *filter;
4330
4331 spin_lock(&adapter->fdir_perfect_lock);
4332
4333 hlist_for_each_entry_safe(filter, node, node2,
4334 &adapter->fdir_filter_list, fdir_node) {
4335 hlist_del(&filter->fdir_node);
4336 kfree(filter);
4337 }
4338 adapter->fdir_filter_count = 0;
4339
4340 spin_unlock(&adapter->fdir_perfect_lock);
4341}
4342
9a799d71
AK		 4343void ixgbe_down(struct ixgbe_adapter *adapter)
4344{
4345 struct net_device *netdev = adapter->netdev;
7f821875 4346 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4347 u32 rxctrl;
bf29ee6c 4348 int i;
9a799d71
AK		 4349
4350 /* signal that we are down to the interrupt handler */
4351 set_bit(__IXGBE_DOWN, &adapter->state);
4352
4353 /* disable receives */
7f821875
JB		 4354 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4355 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4356
2d39d576
YZ		 4357 /* disable all enabled rx queues */
4358 for (i = 0; i < adapter->num_rx_queues; i++)
4359 /* this call also flushes the previous write */
4360 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4361
032b4325 4362 usleep_range(10000, 20000);
9a799d71 4363
7f821875
JB		 4364 netif_tx_stop_all_queues(netdev);
4365
7086400d 4366 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4367 netif_carrier_off(netdev);
4368 netif_tx_disable(netdev);
4369
4370 ixgbe_irq_disable(adapter);
4371
4372 ixgbe_napi_disable_all(adapter);
4373
d034acf1
AD		 4374 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4375 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4376 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4377
4378 del_timer_sync(&adapter->service_timer);
4379
34cecbbf 4380 if (adapter->num_vfs) {
8e34d1aa
AD		 4381 /* Clear EITR Select mapping */
4382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4383
4384 /* Mark all the VFs as inactive */
4385 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4386 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4387
34cecbbf
AD		 4388 /* ping all the active vfs to let them know we are going down */
4389 ixgbe_ping_all_vfs(adapter);
4390
4391 /* Disable all VFTE/VFRE TX/RX */
4392 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4393 }
4394
7f821875
JB		 4395 /* disable transmits in the hardware now that interrupts are off */
4396 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4397 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4398 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4399 }
34cecbbf
AD		 4400
4401 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4402 switch (hw->mac.type) {
4403 case ixgbe_mac_82599EB:
b93a2226 4404 case ixgbe_mac_X540:
88512539 4405 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4406 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4407 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4408 break;
4409 default:
4410 break;
4411 }
7f821875 4412
6f4a0e45
PL		 4413 if (!pci_channel_offline(adapter->pdev))
4414 ixgbe_reset(adapter);
c6ecf39a
DS		 4415
4416 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4417 if (hw->mac.ops.disable_tx_laser &&
4418 ((hw->phy.multispeed_fiber) ||
9f911707 4419 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4420 (hw->mac.type == ixgbe_mac_82599EB))))
4421 hw->mac.ops.disable_tx_laser(hw);
4422
9a799d71
AK		 4423 ixgbe_clean_all_tx_rings(adapter);
4424 ixgbe_clean_all_rx_rings(adapter);
4425
5dd2d332 4426#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4427 /* since we reset the hardware DCA settings were cleared */
e35ec126 4428 ixgbe_setup_dca(adapter);
96b0e0f6 4429#endif
9a799d71
AK		 4430}
4431
9a799d71
AK		 4432/**
4433 * ixgbe_tx_timeout - Respond to a Tx Hang
4434 * @netdev: network interface device structure
4435 **/
4436static void ixgbe_tx_timeout(struct net_device *netdev)
4437{
4438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4439
4440 /* Do the reset outside of interrupt context */
c83c6cbd 4441 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4442}
4443
9a799d71
AK		 4444/**
4445 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4446 * @adapter: board private structure to initialize
4447 *
4448 * ixgbe_sw_init initializes the Adapter private data structure.
4449 * Fields are initialized based on PCI device information and
4450 * OS network device settings (MTU size).
4451 **/
4452static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4453{
4454 struct ixgbe_hw *hw = &adapter->hw;
4455 struct pci_dev *pdev = adapter->pdev;
021230d4 4456 unsigned int rss;
7a6b6f51 4457#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4458 int j;
4459 struct tc_configuration *tc;
4460#endif
021230d4 4461
c44ade9e
JB		 4462 /* PCI config space info */
4463
4464 hw->vendor_id = pdev->vendor;
4465 hw->device_id = pdev->device;
4466 hw->revision_id = pdev->revision;
4467 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4468 hw->subsystem_device_id = pdev->subsystem_device;
4469
021230d4 4470 /* Set capability flags */
3ed69d7e 4471 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4472 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4473 switch (hw->mac.type) {
4474 case ixgbe_mac_82598EB:
bf069c97
DS		 4475 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4476 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4477 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4478 break;
b93a2226 4479 case ixgbe_mac_X540:
4f51bf70
JK		 4480 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4481 case ixgbe_mac_82599EB:
49c7ffbe 4482 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4483 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4484 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4485 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4486 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4487 /* Flow Director hash filters enabled */
45b9f509 4488 adapter->atr_sample_rate = 20;
c087663e 4489 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4490 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4491 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4492#ifdef IXGBE_FCOE
0d551589
YZ		 4493 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4494 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4495#ifdef CONFIG_IXGBE_DCB
6ee16520 4496 /* Default traffic class to use for FCoE */
56075a98 4497 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4498#endif
eacd73f7 4499#endif /* IXGBE_FCOE */
bd508178
AD		 4500 break;
4501 default:
4502 break;
f8212f97 4503 }
2f90b865 4504
7c8ae65a
AD		 4505#ifdef IXGBE_FCOE
4506 /* FCoE support exists, always init the FCoE lock */
4507 spin_lock_init(&adapter->fcoe.lock);
4508
4509#endif
1fc5f038
AD		 4510 /* n-tuple support exists, always init our spinlock */
4511 spin_lock_init(&adapter->fdir_perfect_lock);
4512
7a6b6f51 4513#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4514 switch (hw->mac.type) {
4515 case ixgbe_mac_X540:
4516 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4517 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4518 break;
4519 default:
4520 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4521 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4522 break;
4523 }
4524
2f90b865
AD		 4525 /* Configure DCB traffic classes */
4526 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4527 tc = &adapter->dcb_cfg.tc_config[j];
4528 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4529 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4530 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4531 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4532 tc->dcb_pfc = pfc_disabled;
4533 }
4de2a022
JF		 4534
4535 /* Initialize default user to priority mapping, UPx->TC0 */
4536 tc = &adapter->dcb_cfg.tc_config[0];
4537 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4538 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4539
2f90b865
AD		 4540 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4541 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4542 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4543 adapter->dcb_set_bitmap = 0x00;
3032309b 4544 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4545 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4546 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4547
4548#endif
9a799d71
AK		 4549
4550 /* default flow control settings */
cd7664f6 4551 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4552 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4553 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4554 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4555 hw->fc.send_xon = true;
71fd570b 4556 hw->fc.disable_fc_autoneg = false;
9a799d71 4557
99d74487
AD		 4558#ifdef CONFIG_PCI_IOV
4559 /* assign number of SR-IOV VFs */
4560 if (hw->mac.type != ixgbe_mac_82598EB)
4561 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4562
4563#endif
30efa5a3 4564 /* enable itr by default in dynamic mode */
f7554a2b 4565 adapter->rx_itr_setting = 1;
f7554a2b 4566 adapter->tx_itr_setting = 1;
30efa5a3 4567
30efa5a3
JB		 4568 /* set default ring sizes */
4569 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4570 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4571
bd198058 4572 /* set default work limits */
59224555 4573 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4574
9a799d71 4575 /* initialize eeprom parameters */
c44ade9e 4576 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4577 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4578 return -EIO;
4579 }
4580
9a799d71
AK		 4581 set_bit(__IXGBE_DOWN, &adapter->state);
4582
4583 return 0;
4584}
4585
4586/**
4587 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4588 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4589 *
4590 * Return 0 on success, negative on failure
4591 **/
b6ec895e 4592int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4593{
b6ec895e 4594 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4595 int orig_node = dev_to_node(dev);
4596 int numa_node = -1;
9a799d71
AK		 4597 int size;
4598
3a581073 4599 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4600
4601 if (tx_ring->q_vector)
4602 numa_node = tx_ring->q_vector->numa_node;
4603
4604 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4605 if (!tx_ring->tx_buffer_info)
89bf67f1 4606 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4607 if (!tx_ring->tx_buffer_info)
4608 goto err;
9a799d71
AK		 4609
4610 /* round up to nearest 4K */
12207e49 4611 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4612 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4613
de88eeeb
AD		 4614 set_dev_node(dev, numa_node);
4615 tx_ring->desc = dma_alloc_coherent(dev,
4616 tx_ring->size,
4617 &tx_ring->dma,
4618 GFP_KERNEL);
4619 set_dev_node(dev, orig_node);
4620 if (!tx_ring->desc)
4621 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4622 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4623 if (!tx_ring->desc)
4624 goto err;
9a799d71 4625
3a581073
JB		 4626 tx_ring->next_to_use = 0;
4627 tx_ring->next_to_clean = 0;
9a799d71 4628 return 0;
e01c31a5
JB		 4629
4630err:
4631 vfree(tx_ring->tx_buffer_info);
4632 tx_ring->tx_buffer_info = NULL;
b6ec895e 4633 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4634 return -ENOMEM;
9a799d71
AK		 4635}
4636
69888674
AD		 4637/**
4638 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4639 * @adapter: board private structure
4640 *
4641 * If this function returns with an error, then it's possible one or
4642 * more of the rings is populated (while the rest are not). It is the
4643 * callers duty to clean those orphaned rings.
4644 *
4645 * Return 0 on success, negative on failure
4646 **/
4647static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4648{
4649 int i, err = 0;
4650
4651 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4652 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4653 if (!err)
4654 continue;
de3d5b94 4655
396e799c 4656 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4657 goto err_setup_tx;
69888674
AD		 4658 }
4659
de3d5b94
AD		 4660 return 0;
4661err_setup_tx:
4662 /* rewind the index freeing the rings as we go */
4663 while (i--)
4664 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4665 return err;
4666}
4667
9a799d71
AK		 4668/**
4669 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4670 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4671 *
4672 * Returns 0 on success, negative on failure
4673 **/
b6ec895e 4674int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4675{
b6ec895e 4676 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4677 int orig_node = dev_to_node(dev);
4678 int numa_node = -1;
021230d4 4679 int size;
9a799d71 4680
3a581073 4681 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4682
4683 if (rx_ring->q_vector)
4684 numa_node = rx_ring->q_vector->numa_node;
4685
4686 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4687 if (!rx_ring->rx_buffer_info)
89bf67f1 4688 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4689 if (!rx_ring->rx_buffer_info)
4690 goto err;
9a799d71 4691
9a799d71 4692 /* Round up to nearest 4K */
3a581073
JB		 4693 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4694 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4695
de88eeeb
AD		 4696 set_dev_node(dev, numa_node);
4697 rx_ring->desc = dma_alloc_coherent(dev,
4698 rx_ring->size,
4699 &rx_ring->dma,
4700 GFP_KERNEL);
4701 set_dev_node(dev, orig_node);
4702 if (!rx_ring->desc)
4703 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4704 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4705 if (!rx_ring->desc)
4706 goto err;
9a799d71 4707
3a581073
JB		 4708 rx_ring->next_to_clean = 0;
4709 rx_ring->next_to_use = 0;
9a799d71
AK		 4710
4711 return 0;
b6ec895e
AD		 4712err:
4713 vfree(rx_ring->rx_buffer_info);
4714 rx_ring->rx_buffer_info = NULL;
4715 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4716 return -ENOMEM;
9a799d71
AK		 4717}
4718
69888674
AD		 4719/**
4720 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4721 * @adapter: board private structure
4722 *
4723 * If this function returns with an error, then it's possible one or
4724 * more of the rings is populated (while the rest are not). It is the
4725 * callers duty to clean those orphaned rings.
4726 *
4727 * Return 0 on success, negative on failure
4728 **/
69888674
AD		 4729static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4730{
4731 int i, err = 0;
4732
4733 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4734 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4735 if (!err)
4736 continue;
de3d5b94 4737
396e799c 4738 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4739 goto err_setup_rx;
69888674
AD		 4740 }
4741
7c8ae65a
AD		 4742#ifdef IXGBE_FCOE
4743 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4744 if (!err)
4745#endif
4746 return 0;
de3d5b94
AD		 4747err_setup_rx:
4748 /* rewind the index freeing the rings as we go */
4749 while (i--)
4750 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4751 return err;
4752}
4753
9a799d71
AK		 4754/**
4755 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4756 * @tx_ring: Tx descriptor ring for a specific queue
4757 *
4758 * Free all transmit software resources
4759 **/
b6ec895e 4760void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4761{
b6ec895e 4762 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4763
4764 vfree(tx_ring->tx_buffer_info);
4765 tx_ring->tx_buffer_info = NULL;
4766
b6ec895e
AD		 4767 /* if not set, then don't free */
4768 if (!tx_ring->desc)
4769 return;
4770
4771 dma_free_coherent(tx_ring->dev, tx_ring->size,
4772 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4773
4774 tx_ring->desc = NULL;
4775}
4776
4777/**
4778 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4779 * @adapter: board private structure
4780 *
4781 * Free all transmit software resources
4782 **/
4783static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4784{
4785 int i;
4786
4787 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4788 if (adapter->tx_ring[i]->desc)
b6ec895e 4789 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4790}
4791
4792/**
b4617240 4793 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4794 * @rx_ring: ring to clean the resources from
4795 *
4796 * Free all receive software resources
4797 **/
b6ec895e 4798void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4799{
b6ec895e 4800 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4801
4802 vfree(rx_ring->rx_buffer_info);
4803 rx_ring->rx_buffer_info = NULL;
4804
b6ec895e
AD		 4805 /* if not set, then don't free */
4806 if (!rx_ring->desc)
4807 return;
4808
4809 dma_free_coherent(rx_ring->dev, rx_ring->size,
4810 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4811
4812 rx_ring->desc = NULL;
4813}
4814
4815/**
4816 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4817 * @adapter: board private structure
4818 *
4819 * Free all receive software resources
4820 **/
4821static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4822{
4823 int i;
4824
7c8ae65a
AD		 4825#ifdef IXGBE_FCOE
4826 ixgbe_free_fcoe_ddp_resources(adapter);
4827
4828#endif
9a799d71 4829 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4830 if (adapter->rx_ring[i]->desc)
b6ec895e 4831 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4832}
4833
9a799d71
AK		 4834/**
4835 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4836 * @netdev: network interface device structure
4837 * @new_mtu: new value for maximum frame size
4838 *
4839 * Returns 0 on success, negative on failure
4840 **/
4841static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4842{
4843 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4844 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4845
42c783c5 4846 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4847 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4848 return -EINVAL;
4849
4850 /*
872844dd
AD		 4851 * For 82599EB we cannot allow legacy VFs to enable their receive
4852 * paths when MTU greater than 1500 is configured. So display a
4853 * warning that legacy VFs will be disabled.
655309e9
AD		 4854 */
4855 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4856 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4857 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
872844dd 4858 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 4859
396e799c 4860 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4861
021230d4 4862 /* must set new MTU before calling down or up */
9a799d71
AK		 4863 netdev->mtu = new_mtu;
4864
d4f80882
AV		 4865 if (netif_running(netdev))
4866 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4867
4868 return 0;
4869}
4870
4871/**
4872 * ixgbe_open - Called when a network interface is made active
4873 * @netdev: network interface device structure
4874 *
4875 * Returns 0 on success, negative value on failure
4876 *
4877 * The open entry point is called when a network interface is made
4878 * active by the system (IFF_UP). At this point all resources needed
4879 * for transmit and receive operations are allocated, the interrupt
4880 * handler is registered with the OS, the watchdog timer is started,
4881 * and the stack is notified that the interface is ready.
4882 **/
4883static int ixgbe_open(struct net_device *netdev)
4884{
4885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4886 int err;
4bebfaa5
AK		 4887
4888 /* disallow open during test */
4889 if (test_bit(__IXGBE_TESTING, &adapter->state))
4890 return -EBUSY;
9a799d71 4891
54386467
JB		 4892 netif_carrier_off(netdev);
4893
9a799d71
AK		 4894 /* allocate transmit descriptors */
4895 err = ixgbe_setup_all_tx_resources(adapter);
4896 if (err)
4897 goto err_setup_tx;
4898
9a799d71
AK		 4899 /* allocate receive descriptors */
4900 err = ixgbe_setup_all_rx_resources(adapter);
4901 if (err)
4902 goto err_setup_rx;
4903
4904 ixgbe_configure(adapter);
4905
021230d4 4906 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4907 if (err)
4908 goto err_req_irq;
4909
ac802f5d
AD		 4910 /* Notify the stack of the actual queue counts. */
4911 err = netif_set_real_num_tx_queues(netdev,
4912 adapter->num_rx_pools > 1 ? 1 :
4913 adapter->num_tx_queues);
4914 if (err)
4915 goto err_set_queues;
4916
4917
4918 err = netif_set_real_num_rx_queues(netdev,
4919 adapter->num_rx_pools > 1 ? 1 :
4920 adapter->num_rx_queues);
4921 if (err)
4922 goto err_set_queues;
4923
1a71ab24
JK		 4924#ifdef CONFIG_IXGBE_PTP
4925 ixgbe_ptp_init(adapter);
4926#endif /* CONFIG_IXGBE_PTP*/
4927
c7ccde0f 4928 ixgbe_up_complete(adapter);
9a799d71
AK		 4929
4930 return 0;
4931
ac802f5d
AD		 4932err_set_queues:
4933 ixgbe_free_irq(adapter);
9a799d71 4934err_req_irq:
a20a1199 4935 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4936err_setup_rx:
a20a1199 4937 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4938err_setup_tx:
9a799d71
AK		 4939 ixgbe_reset(adapter);
4940
4941 return err;
4942}
4943
4944/**
4945 * ixgbe_close - Disables a network interface
4946 * @netdev: network interface device structure
4947 *
4948 * Returns 0, this is not allowed to fail
4949 *
4950 * The close entry point is called when an interface is de-activated
4951 * by the OS. The hardware is still under the drivers control, but
4952 * needs to be disabled. A global MAC reset is issued to stop the
4953 * hardware, and all transmit and receive resources are freed.
4954 **/
4955static int ixgbe_close(struct net_device *netdev)
4956{
4957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 4958
1a71ab24
JK		 4959#ifdef CONFIG_IXGBE_PTP
4960 ixgbe_ptp_stop(adapter);
4961#endif
4962
9a799d71
AK		 4963 ixgbe_down(adapter);
4964 ixgbe_free_irq(adapter);
4965
e4911d57
AD		 4966 ixgbe_fdir_filter_exit(adapter);
4967
9a799d71
AK		 4968 ixgbe_free_all_tx_resources(adapter);
4969 ixgbe_free_all_rx_resources(adapter);
4970
5eba3699 4971 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4972
4973 return 0;
4974}
4975
b3c8b4ba
AD		 4976#ifdef CONFIG_PM
4977static int ixgbe_resume(struct pci_dev *pdev)
4978{
c60fbb00
AD		 4979 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4980 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4981 u32 err;
4982
4983 pci_set_power_state(pdev, PCI_D0);
4984 pci_restore_state(pdev);
656ab817
DS		 4985 /*
4986 * pci_restore_state clears dev->state_saved so call
4987 * pci_save_state to restore it.
4988 */
4989 pci_save_state(pdev);
9ce77666 4990
4991 err = pci_enable_device_mem(pdev);
b3c8b4ba 4992 if (err) {
849c4542 4993 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4994 return err;
4995 }
4996 pci_set_master(pdev);
4997
dd4d8ca6 4998 pci_wake_from_d3(pdev, false);
b3c8b4ba 4999
b3c8b4ba
AD		 5000 ixgbe_reset(adapter);
5001
495dce12
WJP		 5002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5003
ac802f5d
AD		 5004 rtnl_lock();
5005 err = ixgbe_init_interrupt_scheme(adapter);
5006 if (!err && netif_running(netdev))
c60fbb00 5007 err = ixgbe_open(netdev);
ac802f5d
AD		 5008
5009 rtnl_unlock();
5010
5011 if (err)
5012 return err;
b3c8b4ba
AD		 5013
5014 netif_device_attach(netdev);
5015
5016 return 0;
5017}
b3c8b4ba 5018#endif /* CONFIG_PM */
9d8d05ae
RW		 5019
5020static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5021{
c60fbb00
AD		 5022 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5023 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5024 struct ixgbe_hw *hw = &adapter->hw;
5025 u32 ctrl, fctrl;
5026 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5027#ifdef CONFIG_PM
5028 int retval = 0;
5029#endif
5030
5031 netif_device_detach(netdev);
5032
5033 if (netif_running(netdev)) {
ab6039a7 5034 rtnl_lock();
b3c8b4ba
AD		 5035 ixgbe_down(adapter);
5036 ixgbe_free_irq(adapter);
5037 ixgbe_free_all_tx_resources(adapter);
5038 ixgbe_free_all_rx_resources(adapter);
ab6039a7 5039 rtnl_unlock();
b3c8b4ba 5040 }
b3c8b4ba 5041
5f5ae6fc
AD		 5042 ixgbe_clear_interrupt_scheme(adapter);
5043
b3c8b4ba
AD		 5044#ifdef CONFIG_PM
5045 retval = pci_save_state(pdev);
5046 if (retval)
5047 return retval;
4df10466 5048
b3c8b4ba 5049#endif
e8e26350
PW		 5050 if (wufc) {
5051 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5052
c509e754
DS		 5053 /*
5054 * enable the optics for both mult-speed fiber and
5055 * 82599 SFP+ fiber as we can WoL.
5056 */
5057 if (hw->mac.ops.enable_tx_laser &&
5058 (hw->phy.multispeed_fiber ||
5059 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
5060 hw->mac.type == ixgbe_mac_82599EB)))
5061 hw->mac.ops.enable_tx_laser(hw);
5062
e8e26350
PW		 5063 /* turn on all-multi mode if wake on multicast is enabled */
5064 if (wufc & IXGBE_WUFC_MC) {
5065 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5066 fctrl |= IXGBE_FCTRL_MPE;
5067 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5068 }
5069
5070 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5071 ctrl |= IXGBE_CTRL_GIO_DIS;
5072 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5073
5074 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5075 } else {
5076 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5077 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5078 }
5079
bd508178
AD		 5080 switch (hw->mac.type) {
5081 case ixgbe_mac_82598EB:
dd4d8ca6 5082 pci_wake_from_d3(pdev, false);
bd508178
AD		 5083 break;
5084 case ixgbe_mac_82599EB:
b93a2226 5085 case ixgbe_mac_X540:
bd508178
AD		 5086 pci_wake_from_d3(pdev, !!wufc);
5087 break;
5088 default:
5089 break;
5090 }
b3c8b4ba 5091
9d8d05ae
RW		 5092 *enable_wake = !!wufc;
5093
b3c8b4ba
AD		 5094 ixgbe_release_hw_control(adapter);
5095
5096 pci_disable_device(pdev);
5097
9d8d05ae
RW		 5098 return 0;
5099}
5100
5101#ifdef CONFIG_PM
5102static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5103{
5104 int retval;
5105 bool wake;
5106
5107 retval = __ixgbe_shutdown(pdev, &wake);
5108 if (retval)
5109 return retval;
5110
5111 if (wake) {
5112 pci_prepare_to_sleep(pdev);
5113 } else {
5114 pci_wake_from_d3(pdev, false);
5115 pci_set_power_state(pdev, PCI_D3hot);
5116 }
b3c8b4ba
AD		 5117
5118 return 0;
5119}
9d8d05ae 5120#endif /* CONFIG_PM */
b3c8b4ba
AD		 5121
5122static void ixgbe_shutdown(struct pci_dev *pdev)
5123{
9d8d05ae
RW		 5124 bool wake;
5125
5126 __ixgbe_shutdown(pdev, &wake);
5127
5128 if (system_state == SYSTEM_POWER_OFF) {
5129 pci_wake_from_d3(pdev, wake);
5130 pci_set_power_state(pdev, PCI_D3hot);
5131 }
b3c8b4ba
AD		 5132}
5133
9a799d71
AK		 5134/**
5135 * ixgbe_update_stats - Update the board statistics counters.
5136 * @adapter: board private structure
5137 **/
5138void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5139{
2d86f139 5140 struct net_device *netdev = adapter->netdev;
9a799d71 5141 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5142 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5143 u64 total_mpc = 0;
5144 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5145 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5146 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5147 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5148
d08935c2
DS		 5149 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5150 test_bit(__IXGBE_RESETTING, &adapter->state))
5151 return;
5152
94b982b2 5153 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5154 u64 rsc_count = 0;
94b982b2 5155 u64 rsc_flush = 0;
94b982b2 5156 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5157 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5158 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5159 }
5160 adapter->rsc_total_count = rsc_count;
5161 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5162 }
5163
5b7da515
AD		 5164 for (i = 0; i < adapter->num_rx_queues; i++) {
5165 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5166 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5167 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5168 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5169 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5170 bytes += rx_ring->stats.bytes;
5171 packets += rx_ring->stats.packets;
5172 }
5173 adapter->non_eop_descs = non_eop_descs;
5174 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5175 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5176 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5177 netdev->stats.rx_bytes = bytes;
5178 netdev->stats.rx_packets = packets;
5179
5180 bytes = 0;
5181 packets = 0;
7ca3bc58 5182 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5183 for (i = 0; i < adapter->num_tx_queues; i++) {
5184 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5185 restart_queue += tx_ring->tx_stats.restart_queue;
5186 tx_busy += tx_ring->tx_stats.tx_busy;
5187 bytes += tx_ring->stats.bytes;
5188 packets += tx_ring->stats.packets;
5189 }
eb985f09 5190 adapter->restart_queue = restart_queue;
5b7da515
AD		 5191 adapter->tx_busy = tx_busy;
5192 netdev->stats.tx_bytes = bytes;
5193 netdev->stats.tx_packets = packets;
7ca3bc58 5194
7ca647bd 5195 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5196
5197 /* 8 register reads */
6f11eef7
AV		 5198 for (i = 0; i < 8; i++) {
5199 /* for packet buffers not used, the register should read 0 */
5200 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5201 missed_rx += mpc;
7ca647bd
JP		 5202 hwstats->mpc[i] += mpc;
5203 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5204 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5205 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5206 switch (hw->mac.type) {
5207 case ixgbe_mac_82598EB:
1a70db4b
ET		 5208 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5209 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5210 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5211 hwstats->pxonrxc[i] +=
5212 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5213 break;
5214 case ixgbe_mac_82599EB:
b93a2226 5215 case ixgbe_mac_X540:
bd508178
AD		 5216 hwstats->pxonrxc[i] +=
5217 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5218 break;
5219 default:
5220 break;
e8e26350 5221 }
6f11eef7 5222 }
1a70db4b
ET		 5223
5224 /*16 register reads */
5225 for (i = 0; i < 16; i++) {
5226 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5227 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5228 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5229 (hw->mac.type == ixgbe_mac_X540)) {
5230 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5231 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5232 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5233 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5234 }
5235 }
5236
7ca647bd 5237 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5238 /* work around hardware counting issue */
7ca647bd 5239 hwstats->gprc -= missed_rx;
6f11eef7 5240
c84d324c
JF		 5241 ixgbe_update_xoff_received(adapter);
5242
6f11eef7 5243 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5244 switch (hw->mac.type) {
5245 case ixgbe_mac_82598EB:
5246 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5247 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5248 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5249 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5250 break;
b93a2226 5251 case ixgbe_mac_X540:
58f6bcf9
ET		 5252 /* OS2BMC stats are X540 only*/
5253 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5254 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5255 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5256 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5257 case ixgbe_mac_82599EB:
a4d4f629
AD		 5258 for (i = 0; i < 16; i++)
5259 adapter->hw_rx_no_dma_resources +=
5260 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5261 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5262 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5263 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5264 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5265 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5266 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5267 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5268 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5269 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5270#ifdef IXGBE_FCOE
7ca647bd
JP		 5271 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5272 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5273 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5274 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5275 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5276 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5277 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5278 if (adapter->fcoe.ddp_pool) {
5279 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5280 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5281 unsigned int cpu;
5282 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5283 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5284 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5285 noddp += ddp_pool->noddp;
5286 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5287 }
5a1ee270
AD		 5288 hwstats->fcoe_noddp = noddp;
5289 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5290 }
6d45522c 5291#endif /* IXGBE_FCOE */
bd508178
AD		 5292 break;
5293 default:
5294 break;
e8e26350 5295 }
9a799d71 5296 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5297 hwstats->bprc += bprc;
5298 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5299 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5300 hwstats->mprc -= bprc;
5301 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5302 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5303 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5304 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5305 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5306 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5307 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5308 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5309 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5310 hwstats->lxontxc += lxon;
6f11eef7 5311 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5312 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5313 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5314 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5315 /*
5316 * 82598 errata - tx of flow control packets is included in tx counters
5317 */
5318 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5319 hwstats->gptc -= xon_off_tot;
5320 hwstats->mptc -= xon_off_tot;
5321 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5322 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5323 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5324 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5325 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5326 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5327 hwstats->ptc64 -= xon_off_tot;
5328 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5329 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5330 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5331 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5332 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5333 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5334
5335 /* Fill out the OS statistics structure */
7ca647bd 5336 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5337
5338 /* Rx Errors */
7ca647bd 5339 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5340 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5341 netdev->stats.rx_length_errors = hwstats->rlec;
5342 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5343 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5344}
5345
5346/**
d034acf1 5347 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5348 * @adapter: pointer to the device adapter structure
9a799d71 5349 **/
d034acf1 5350static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5351{
cf8280ee 5352 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5353 int i;
cf8280ee 5354
d034acf1
AD		 5355 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5356 return;
5357
5358 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5359
d034acf1 5360 /* if interface is down do nothing */
fe49f04a 5361 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5362 return;
5363
5364 /* do nothing if we are not using signature filters */
5365 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5366 return;
5367
5368 adapter->fdir_overflow++;
5369
93c52dd0
AD		 5370 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5371 for (i = 0; i < adapter->num_tx_queues; i++)
5372 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5373 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5374 /* re-enable flow director interrupts */
5375 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5376 } else {
5377 e_err(probe, "failed to finish FDIR re-initialization, "
5378 "ignored adding FDIR ATR filters\n");
5379 }
93c52dd0
AD		 5380}
5381
5382/**
5383 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5384 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5385 *
5386 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5387 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5388 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5389 * determine if a hang has occurred.
93c52dd0
AD		 5390 */
5391static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5392{
cf8280ee 5393 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5394 u64 eics = 0;
5395 int i;
cf8280ee 5396
93c52dd0
AD		 5397 /* If we're down or resetting, just bail */
5398 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5399 test_bit(__IXGBE_RESETTING, &adapter->state))
5400 return;
22d5a71b 5401
93c52dd0
AD		 5402 /* Force detection of hung controller */
5403 if (netif_carrier_ok(adapter->netdev)) {
5404 for (i = 0; i < adapter->num_tx_queues; i++)
5405 set_check_for_tx_hang(adapter->tx_ring[i]);
5406 }
22d5a71b 5407
fe49f04a
AD		 5408 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5409 /*
5410 * for legacy and MSI interrupts don't set any bits
5411 * that are enabled for EIAM, because this operation
5412 * would set *both* EIMS and EICS for any bit in EIAM
5413 */
5414 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5415 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5416 } else {
5417 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5418 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5419 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5420 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5421 eics |= ((u64)1 << i);
5422 }
cf8280ee 5423 }
9a799d71 5424
93c52dd0 5425 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5426 ixgbe_irq_rearm_queues(adapter, eics);
5427
cf8280ee
JB		 5428}
5429
e8e26350 5430/**
93c52dd0 5431 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5432 * @adapter: pointer to the device adapter structure
5433 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5434 **/
93c52dd0 5435static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5436{
e8e26350 5437 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5438 u32 link_speed = adapter->link_speed;
5439 bool link_up = adapter->link_up;
041441d0 5440 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5441
93c52dd0
AD		 5442 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5443 return;
5444
5445 if (hw->mac.ops.check_link) {
5446 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5447 } else {
93c52dd0
AD		 5448 /* always assume link is up, if no check link function */
5449 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5450 link_up = true;
c4cf55e5 5451 }
041441d0
AD		 5452
5453 if (adapter->ixgbe_ieee_pfc)
5454 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5455
3ebe8fde 5456 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5457 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5458 ixgbe_set_rx_drop_en(adapter);
5459 }
93c52dd0
AD		 5460
5461 if (link_up ||
5462 time_after(jiffies, (adapter->link_check_timeout +
5463 IXGBE_TRY_LINK_TIMEOUT))) {
5464 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5465 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5466 IXGBE_WRITE_FLUSH(hw);
5467 }
5468
5469 adapter->link_up = link_up;
5470 adapter->link_speed = link_speed;
e8e26350
PW		 5471}
5472
107d3018
AD		 5473static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5474{
5475#ifdef CONFIG_IXGBE_DCB
5476 struct net_device *netdev = adapter->netdev;
5477 struct dcb_app app = {
5478 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5479 .protocol = 0,
5480 };
5481 u8 up = 0;
5482
5483 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5484 up = dcb_ieee_getapp_mask(netdev, &app);
5485
5486 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5487#endif
5488}
5489
e8e26350 5490/**
93c52dd0
AD		 5491 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5492 * print link up message
49ce9c2c 5493 * @adapter: pointer to the device adapter structure
e8e26350 5494 **/
93c52dd0 5495static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5496{
93c52dd0 5497 struct net_device *netdev = adapter->netdev;
e8e26350 5498 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5499 u32 link_speed = adapter->link_speed;
5500 bool flow_rx, flow_tx;
e8e26350 5501
93c52dd0
AD		 5502 /* only continue if link was previously down */
5503 if (netif_carrier_ok(netdev))
a985b6c3 5504 return;
63d6e1d8 5505
93c52dd0 5506 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5507
93c52dd0
AD		 5508 switch (hw->mac.type) {
5509 case ixgbe_mac_82598EB: {
5510 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5511 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5512 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5513 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5514 }
5515 break;
5516 case ixgbe_mac_X540:
5517 case ixgbe_mac_82599EB: {
5518 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5519 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5520 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5521 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5522 }
5523 break;
5524 default:
5525 flow_tx = false;
5526 flow_rx = false;
5527 break;
e8e26350 5528 }
3a6a4eda
JK		 5529
5530#ifdef CONFIG_IXGBE_PTP
1a71ab24
JK		 5531 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5532 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda
JK		 5533#endif
5534
93c52dd0
AD		 5535 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5536 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5537 "10 Gbps" :
5538 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5539 "1 Gbps" :
5540 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5541 "100 Mbps" :
5542 "unknown speed"))),
5543 ((flow_rx && flow_tx) ? "RX/TX" :
5544 (flow_rx ? "RX" :
5545 (flow_tx ? "TX" : "None"))));
e8e26350 5546
93c52dd0 5547 netif_carrier_on(netdev);
93c52dd0 5548 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5549
107d3018
AD		 5550 /* update the default user priority for VFs */
5551 ixgbe_update_default_up(adapter);
5552
befa2af7
AD		 5553 /* ping all the active vfs to let them know link has changed */
5554 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5555}
5556
c4cf55e5 5557/**
93c52dd0
AD		 5558 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5559 * print link down message
49ce9c2c 5560 * @adapter: pointer to the adapter structure
c4cf55e5 5561 **/
581330ba 5562static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5563{
cf8280ee 5564 struct net_device *netdev = adapter->netdev;
c4cf55e5 5565 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5566
93c52dd0
AD		 5567 adapter->link_up = false;
5568 adapter->link_speed = 0;
cf8280ee 5569
93c52dd0
AD		 5570 /* only continue if link was up previously */
5571 if (!netif_carrier_ok(netdev))
5572 return;
264857b8 5573
93c52dd0
AD		 5574 /* poll for SFP+ cable when link is down */
5575 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5576 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5577
3a6a4eda 5578#ifdef CONFIG_IXGBE_PTP
1a71ab24
JK		 5579 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5580 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda
JK		 5581#endif
5582
93c52dd0
AD		 5583 e_info(drv, "NIC Link is Down\n");
5584 netif_carrier_off(netdev);
befa2af7
AD		 5585
5586 /* ping all the active vfs to let them know link has changed */
5587 ixgbe_ping_all_vfs(adapter);
93c52dd0 5588}
e8e26350 5589
93c52dd0
AD		 5590/**
5591 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5592 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5593 **/
5594static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5595{
c4cf55e5 5596 int i;
93c52dd0 5597 int some_tx_pending = 0;
c4cf55e5 5598
93c52dd0 5599 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5600 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5601 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5602 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5603 some_tx_pending = 1;
5604 break;
5605 }
5606 }
5607
5608 if (some_tx_pending) {
5609 /* We've lost link, so the controller stops DMA,
5610 * but we've got queued Tx work that's never going
5611 * to get done, so reset controller to flush Tx.
5612 * (Do the reset outside of interrupt context).
5613 */
c83c6cbd 5614 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5615 }
c4cf55e5 5616 }
c4cf55e5
PWJ		 5617}
5618
a985b6c3
GR		 5619static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5620{
5621 u32 ssvpc;
5622
0584d999
GR		 5623 /* Do not perform spoof check for 82598 or if not in IOV mode */
5624 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5625 adapter->num_vfs == 0)
a985b6c3
GR		 5626 return;
5627
5628 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5629
5630 /*
5631 * ssvpc register is cleared on read, if zero then no
5632 * spoofed packets in the last interval.
5633 */
5634 if (!ssvpc)
5635 return;
5636
d6ea0754 5637 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5638}
5639
93c52dd0
AD		 5640/**
5641 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5642 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5643 **/
5644static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5645{
5646 /* if interface is down do nothing */
7edebf9a
ET		 5647 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5648 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5649 return;
5650
5651 ixgbe_watchdog_update_link(adapter);
5652
5653 if (adapter->link_up)
5654 ixgbe_watchdog_link_is_up(adapter);
5655 else
5656 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5657
a985b6c3 5658 ixgbe_spoof_check(adapter);
9a799d71 5659 ixgbe_update_stats(adapter);
93c52dd0
AD		 5660
5661 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5662}
10eec955 5663
cf8280ee 5664/**
7086400d 5665 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5666 * @adapter: the ixgbe adapter structure
cf8280ee 5667 **/
7086400d 5668static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5669{
cf8280ee 5670 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5671 s32 err;
cf8280ee 5672
7086400d
AD		 5673 /* not searching for SFP so there is nothing to do here */
5674 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5675 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5676 return;
10eec955 5677
7086400d
AD		 5678 /* someone else is in init, wait until next service event */
5679 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5680 return;
cf8280ee 5681
7086400d
AD		 5682 err = hw->phy.ops.identify_sfp(hw);
5683 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5684 goto sfp_out;
264857b8 5685
7086400d
AD		 5686 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5687 /* If no cable is present, then we need to reset
5688 * the next time we find a good cable. */
5689 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5690 }
9a799d71 5691
7086400d
AD		 5692 /* exit on error */
5693 if (err)
5694 goto sfp_out;
e8e26350 5695
7086400d
AD		 5696 /* exit if reset not needed */
5697 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5698 goto sfp_out;
9a799d71 5699
7086400d 5700 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5701
7086400d
AD		 5702 /*
5703 * A module may be identified correctly, but the EEPROM may not have
5704 * support for that module. setup_sfp() will fail in that case, so
5705 * we should not allow that module to load.
5706 */
5707 if (hw->mac.type == ixgbe_mac_82598EB)
5708 err = hw->phy.ops.reset(hw);
5709 else
5710 err = hw->mac.ops.setup_sfp(hw);
5711
5712 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5713 goto sfp_out;
5714
5715 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5716 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5717
5718sfp_out:
5719 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5720
5721 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5722 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5723 e_dev_err("failed to initialize because an unsupported "
5724 "SFP+ module type was detected.\n");
5725 e_dev_err("Reload the driver after installing a "
5726 "supported module.\n");
5727 unregister_netdev(adapter->netdev);
bc59fcda 5728 }
7086400d 5729}
bc59fcda 5730
7086400d
AD		 5731/**
5732 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5733 * @adapter: the ixgbe adapter structure
7086400d
AD		 5734 **/
5735static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5736{
5737 struct ixgbe_hw *hw = &adapter->hw;
5738 u32 autoneg;
5739 bool negotiation;
5740
5741 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5742 return;
5743
5744 /* someone else is in init, wait until next service event */
5745 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5746 return;
5747
5748 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5749
5750 autoneg = hw->phy.autoneg_advertised;
5751 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5752 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5753 if (hw->mac.ops.setup_link)
5754 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5755
5756 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5757 adapter->link_check_timeout = jiffies;
5758 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5759}
5760
83c61fa9
GR		 5761#ifdef CONFIG_PCI_IOV
5762static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5763{
5764 int vf;
5765 struct ixgbe_hw *hw = &adapter->hw;
5766 struct net_device *netdev = adapter->netdev;
5767 u32 gpc;
5768 u32 ciaa, ciad;
5769
5770 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5771 if (gpc) /* If incrementing then no need for the check below */
5772 return;
5773 /*
5774 * Check to see if a bad DMA write target from an errant or
5775 * malicious VF has caused a PCIe error. If so then we can
5776 * issue a VFLR to the offending VF(s) and then resume without
5777 * requesting a full slot reset.
5778 */
5779
5780 for (vf = 0; vf < adapter->num_vfs; vf++) {
5781 ciaa = (vf << 16) | 0x80000000;
5782 /* 32 bit read so align, we really want status at offset 6 */
5783 ciaa |= PCI_COMMAND;
5784 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5785 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5786 ciaa &= 0x7FFFFFFF;
5787 /* disable debug mode asap after reading data */
5788 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5789 /* Get the upper 16 bits which will be the PCI status reg */
5790 ciad >>= 16;
5791 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5792 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5793 /* Issue VFLR */
5794 ciaa = (vf << 16) | 0x80000000;
5795 ciaa |= 0xA8;
5796 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5797 ciad = 0x00008000; /* VFLR */
5798 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5799 ciaa &= 0x7FFFFFFF;
5800 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5801 }
5802 }
5803}
5804
5805#endif
7086400d
AD		 5806/**
5807 * ixgbe_service_timer - Timer Call-back
5808 * @data: pointer to adapter cast into an unsigned long
5809 **/
5810static void ixgbe_service_timer(unsigned long data)
5811{
5812 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5813 unsigned long next_event_offset;
83c61fa9 5814 bool ready = true;
7086400d 5815
6bb78cfb
AD		 5816 /* poll faster when waiting for link */
5817 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5818 next_event_offset = HZ / 10;
5819 else
5820 next_event_offset = HZ * 2;
83c61fa9 5821
6bb78cfb 5822#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5823 /*
5824 * don't bother with SR-IOV VF DMA hang check if there are
5825 * no VFs or the link is down
5826 */
5827 if (!adapter->num_vfs ||
6bb78cfb 5828 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5829 goto normal_timer_service;
83c61fa9
GR		 5830
5831 /* If we have VFs allocated then we must check for DMA hangs */
5832 ixgbe_check_for_bad_vf(adapter);
5833 next_event_offset = HZ / 50;
5834 adapter->timer_event_accumulator++;
5835
6bb78cfb 5836 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5837 adapter->timer_event_accumulator = 0;
7086400d 5838 else
6bb78cfb 5839 ready = false;
7086400d 5840
6bb78cfb 5841normal_timer_service:
83c61fa9 5842#endif
7086400d
AD		 5843 /* Reset the timer */
5844 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5845
83c61fa9
GR		 5846 if (ready)
5847 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5848}
5849
c83c6cbd
AD		 5850static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5851{
5852 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5853 return;
5854
5855 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5856
5857 /* If we're already down or resetting, just bail */
5858 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5859 test_bit(__IXGBE_RESETTING, &adapter->state))
5860 return;
5861
5862 ixgbe_dump(adapter);
5863 netdev_err(adapter->netdev, "Reset adapter\n");
5864 adapter->tx_timeout_count++;
5865
5866 ixgbe_reinit_locked(adapter);
5867}
5868
7086400d
AD		 5869/**
5870 * ixgbe_service_task - manages and runs subtasks
5871 * @work: pointer to work_struct containing our data
5872 **/
5873static void ixgbe_service_task(struct work_struct *work)
5874{
5875 struct ixgbe_adapter *adapter = container_of(work,
5876 struct ixgbe_adapter,
5877 service_task);
5878
c83c6cbd 5879 ixgbe_reset_subtask(adapter);
7086400d
AD		 5880 ixgbe_sfp_detection_subtask(adapter);
5881 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5882 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5883 ixgbe_watchdog_subtask(adapter);
d034acf1 5884 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5885 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5886#ifdef CONFIG_IXGBE_PTP
5887 ixgbe_ptp_overflow_check(adapter);
5888#endif
7086400d
AD		 5889
5890 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5891}
5892
fd0db0ed
AD		 5893static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5894 struct ixgbe_tx_buffer *first,
244e27ad 5895 u8 *hdr_len)
897ab156 5896{
fd0db0ed 5897 struct sk_buff *skb = first->skb;
897ab156
AD		 5898 u32 vlan_macip_lens, type_tucmd;
5899 u32 mss_l4len_idx, l4len;
9a799d71 5900
897ab156
AD		 5901 if (!skb_is_gso(skb))
5902 return 0;
9a799d71 5903
897ab156 5904 if (skb_header_cloned(skb)) {
244e27ad 5905 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5906 if (err)
5907 return err;
9a799d71 5908 }
9a799d71 5909
897ab156
AD		 5910 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5911 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5912
244e27ad 5913 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5914 struct iphdr *iph = ip_hdr(skb);
5915 iph->tot_len = 0;
5916 iph->check = 0;
5917 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5918 iph->daddr, 0,
5919 IPPROTO_TCP,
5920 0);
5921 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5922 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5923 IXGBE_TX_FLAGS_CSUM |
5924 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5925 } else if (skb_is_gso_v6(skb)) {
5926 ipv6_hdr(skb)->payload_len = 0;
5927 tcp_hdr(skb)->check =
5928 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5929 &ipv6_hdr(skb)->daddr,
5930 0, IPPROTO_TCP, 0);
244e27ad
AD		 5931 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5932 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5933 }
5934
091a6246 5935 /* compute header lengths */
897ab156
AD		 5936 l4len = tcp_hdrlen(skb);
5937 *hdr_len = skb_transport_offset(skb) + l4len;
5938
091a6246
AD		 5939 /* update gso size and bytecount with header size */
5940 first->gso_segs = skb_shinfo(skb)->gso_segs;
5941 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5942
897ab156
AD		 5943 /* mss_l4len_id: use 1 as index for TSO */
5944 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5945 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5946 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5947
5948 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5949 vlan_macip_lens = skb_network_header_len(skb);
5950 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5951 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5952
5953 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5954 mss_l4len_idx);
897ab156
AD		 5955
5956 return 1;
5957}
5958
244e27ad
AD		 5959static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5960 struct ixgbe_tx_buffer *first)
7ca647bd 5961{
fd0db0ed 5962 struct sk_buff *skb = first->skb;
897ab156
AD		 5963 u32 vlan_macip_lens = 0;
5964 u32 mss_l4len_idx = 0;
5965 u32 type_tucmd = 0;
7ca647bd 5966
897ab156 5967 if (skb->ip_summed != CHECKSUM_PARTIAL) {
62748b7b
AD		 5968 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5969 if (unlikely(skb->no_fcs))
5970 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5971 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5972 return;
5973 }
897ab156
AD		 5974 } else {
5975 u8 l4_hdr = 0;
244e27ad 5976 switch (first->protocol) {
897ab156
AD		 5977 case __constant_htons(ETH_P_IP):
5978 vlan_macip_lens |= skb_network_header_len(skb);
5979 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5980 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5981 break;
897ab156
AD		 5982 case __constant_htons(ETH_P_IPV6):
5983 vlan_macip_lens |= skb_network_header_len(skb);
5984 l4_hdr = ipv6_hdr(skb)->nexthdr;
5985 break;
5986 default:
5987 if (unlikely(net_ratelimit())) {
5988 dev_warn(tx_ring->dev,
5989 "partial checksum but proto=%x!\n",
244e27ad 5990 first->protocol);
897ab156 5991 }
7ca647bd
JP		 5992 break;
5993 }
897ab156
AD		 5994
5995 switch (l4_hdr) {
7ca647bd 5996 case IPPROTO_TCP:
897ab156
AD		 5997 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5998 mss_l4len_idx = tcp_hdrlen(skb) <<
5999 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6000 break;
6001 case IPPROTO_SCTP:
897ab156
AD		 6002 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6003 mss_l4len_idx = sizeof(struct sctphdr) <<
6004 IXGBE_ADVTXD_L4LEN_SHIFT;
6005 break;
6006 case IPPROTO_UDP:
6007 mss_l4len_idx = sizeof(struct udphdr) <<
6008 IXGBE_ADVTXD_L4LEN_SHIFT;
6009 break;
6010 default:
6011 if (unlikely(net_ratelimit())) {
6012 dev_warn(tx_ring->dev,
6013 "partial checksum but l4 proto=%x!\n",
244e27ad 6014 l4_hdr);
897ab156 6015 }
7ca647bd
JP		 6016 break;
6017 }
244e27ad
AD		 6018
6019 /* update TX checksum flag */
6020 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6021 }
6022
244e27ad 6023 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6024 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6025 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6026
897ab156
AD		 6027 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6028 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6029}
6030
d3d00239 6031static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6032{
d3d00239
AD		 6033 /* set type for advanced descriptor with frame checksum insertion */
6034 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
d3d00239 6035 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6036
d3d00239 6037 /* set HW vlan bit if vlan is present */
66f32a8b 6038 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6039 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6040
3a6a4eda
JK		 6041#ifdef CONFIG_IXGBE_PTP
6042 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6043 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
6044#endif
6045
d3d00239
AD		 6046 /* set segmentation enable bits for TSO/FSO */
6047#ifdef IXGBE_FCOE
93f5b3c1 6048 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 6049#else
6050 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6051#endif
6052 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6053
62748b7b
AD		 6054 /* insert frame checksum */
6055 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6056 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6057
d3d00239
AD		 6058 return cmd_type;
6059}
9a799d71 6060
729739b7
AD		 6061static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6062 u32 tx_flags, unsigned int paylen)
d3d00239 6063{
93f5b3c1 6064 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 6065
d3d00239
AD		 6066 /* enable L4 checksum for TSO and TX checksum offload */
6067 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6068 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6069
93f5b3c1
AD		 6070 /* enble IPv4 checksum for TSO */
6071 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6072 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6073
93f5b3c1
AD		 6074 /* use index 1 context for TSO/FSO/FCOE */
6075#ifdef IXGBE_FCOE
6076 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6077#else
6078 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 6079#endif
93f5b3c1
AD		 6080 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6081
7f9643fd
AD		 6082 /*
6083 * Check Context must be set if Tx switch is enabled, which it
6084 * always is for case where virtual functions are running
6085 */
93f5b3c1
AD		 6086#ifdef IXGBE_FCOE
6087 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6088#else
7f9643fd 6089 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 6090#endif
7f9643fd
AD		 6091 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6092
729739b7 6093 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 6094}
44df32c5 6095
d3d00239
AD		 6096#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6097 IXGBE_TXD_CMD_RS)
6098
6099static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6100 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6101 const u8 hdr_len)
6102{
729739b7 6103 dma_addr_t dma;
fd0db0ed 6104 struct sk_buff *skb = first->skb;
729739b7 6105 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6106 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6107 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6108 unsigned int data_len = skb->data_len;
6109 unsigned int size = skb_headlen(skb);
729739b7 6110 unsigned int paylen = skb->len - hdr_len;
244e27ad 6111 u32 tx_flags = first->tx_flags;
729739b7 6112 __le32 cmd_type;
d3d00239 6113 u16 i = tx_ring->next_to_use;
d3d00239 6114
729739b7
AD		 6115 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6116
6117 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6118 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6119
d3d00239
AD		 6120#ifdef IXGBE_FCOE
6121 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6122 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6123 size -= sizeof(struct fcoe_crc_eof) - data_len;
6124 data_len = 0;
729739b7
AD		 6125 } else {
6126 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6127 }
6128 }
44df32c5 6129
d3d00239 6130#endif
729739b7
AD		 6131 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6132 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6133 goto dma_error;
8ad494b0 6134
729739b7
AD		 6135 /* record length, and DMA address */
6136 dma_unmap_len_set(first, len, size);
6137 dma_unmap_addr_set(first, dma, dma);
9a799d71 6138
729739b7 6139 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6140
d3d00239 6141 for (;;) {
729739b7 6142 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6143 tx_desc->read.cmd_type_len =
6144 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6145
d3d00239 6146 i++;
729739b7 6147 tx_desc++;
d3d00239 6148 if (i == tx_ring->count) {
e4f74028 6149 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6150 i = 0;
6151 }
729739b7
AD		 6152
6153 dma += IXGBE_MAX_DATA_PER_TXD;
6154 size -= IXGBE_MAX_DATA_PER_TXD;
6155
6156 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6157 tx_desc->read.olinfo_status = 0;
d3d00239 6158 }
e5a43549 6159
729739b7
AD		 6160 if (likely(!data_len))
6161 break;
9a799d71 6162
d3d00239 6163 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6164
729739b7
AD		 6165 i++;
6166 tx_desc++;
6167 if (i == tx_ring->count) {
6168 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6169 i = 0;
6170 }
9a799d71 6171
d3d00239 6172#ifdef IXGBE_FCOE
9e903e08 6173 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6174#else
9e903e08 6175 size = skb_frag_size(frag);
d3d00239
AD		 6176#endif
6177 data_len -= size;
9a799d71 6178
729739b7
AD		 6179 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6180 DMA_TO_DEVICE);
6181 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6182 goto dma_error;
9a799d71 6183
729739b7
AD		 6184 tx_buffer = &tx_ring->tx_buffer_info[i];
6185 dma_unmap_len_set(tx_buffer, len, size);
6186 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6187
729739b7
AD		 6188 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6189 tx_desc->read.olinfo_status = 0;
9a799d71 6190
729739b7
AD		 6191 frag++;
6192 }
9a799d71 6193
729739b7
AD		 6194 /* write last descriptor with RS and EOP bits */
6195 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6196 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6197
091a6246 6198 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6199
d3d00239
AD		 6200 /* set the timestamp */
6201 first->time_stamp = jiffies;
9a799d71
AK		 6202
6203 /*
729739b7
AD		 6204 * Force memory writes to complete before letting h/w know there
6205 * are new descriptors to fetch. (Only applicable for weak-ordered
6206 * memory model archs, such as IA-64).
6207 *
6208 * We also need this memory barrier to make certain all of the
6209 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6210 */
6211 wmb();
6212
d3d00239
AD		 6213 /* set next_to_watch value indicating a packet is present */
6214 first->next_to_watch = tx_desc;
6215
729739b7
AD		 6216 i++;
6217 if (i == tx_ring->count)
6218 i = 0;
6219
6220 tx_ring->next_to_use = i;
6221
d3d00239 6222 /* notify HW of packet */
84ea2591 6223 writel(i, tx_ring->tail);
d3d00239
AD		 6224
6225 return;
6226dma_error:
729739b7 6227 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6228
6229 /* clear dma mappings for failed tx_buffer_info map */
6230 for (;;) {
729739b7
AD		 6231 tx_buffer = &tx_ring->tx_buffer_info[i];
6232 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6233 if (tx_buffer == first)
d3d00239
AD		 6234 break;
6235 if (i == 0)
6236 i = tx_ring->count;
6237 i--;
6238 }
6239
d3d00239 6240 tx_ring->next_to_use = i;
9a799d71
AK		 6241}
6242
fd0db0ed 6243static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6244 struct ixgbe_tx_buffer *first)
69830529
AD		 6245{
6246 struct ixgbe_q_vector *q_vector = ring->q_vector;
6247 union ixgbe_atr_hash_dword input = { .dword = 0 };
6248 union ixgbe_atr_hash_dword common = { .dword = 0 };
6249 union {
6250 unsigned char *network;
6251 struct iphdr *ipv4;
6252 struct ipv6hdr *ipv6;
6253 } hdr;
ee9e0f0b 6254 struct tcphdr *th;
905e4a41 6255 __be16 vlan_id;
c4cf55e5 6256
69830529
AD		 6257 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6258 if (!q_vector)
6259 return;
6260
6261 /* do nothing if sampling is disabled */
6262 if (!ring->atr_sample_rate)
d3ead241 6263 return;
c4cf55e5 6264
69830529 6265 ring->atr_count++;
c4cf55e5 6266
69830529 6267 /* snag network header to get L4 type and address */
fd0db0ed 6268 hdr.network = skb_network_header(first->skb);
69830529
AD		 6269
6270 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6271 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6272 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6273 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6274 hdr.ipv4->protocol != IPPROTO_TCP))
6275 return;
ee9e0f0b 6276
fd0db0ed 6277 th = tcp_hdr(first->skb);
c4cf55e5 6278
66f32a8b
AD		 6279 /* skip this packet since it is invalid or the socket is closing */
6280 if (!th || th->fin)
69830529
AD		 6281 return;
6282
6283 /* sample on all syn packets or once every atr sample count */
6284 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6285 return;
6286
6287 /* reset sample count */
6288 ring->atr_count = 0;
6289
244e27ad 6290 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6291
6292 /*
6293 * src and dst are inverted, think how the receiver sees them
6294 *
6295 * The input is broken into two sections, a non-compressed section
6296 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6297 * is XORed together and stored in the compressed dword.
6298 */
6299 input.formatted.vlan_id = vlan_id;
6300
6301 /*
6302 * since src port and flex bytes occupy the same word XOR them together
6303 * and write the value to source port portion of compressed dword
6304 */
244e27ad 6305 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6306 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6307 else
244e27ad 6308 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6309 common.port.dst ^= th->source;
6310
244e27ad 6311 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6312 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6313 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6314 } else {
6315 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6316 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6317 hdr.ipv6->saddr.s6_addr32[1] ^
6318 hdr.ipv6->saddr.s6_addr32[2] ^
6319 hdr.ipv6->saddr.s6_addr32[3] ^
6320 hdr.ipv6->daddr.s6_addr32[0] ^
6321 hdr.ipv6->daddr.s6_addr32[1] ^
6322 hdr.ipv6->daddr.s6_addr32[2] ^
6323 hdr.ipv6->daddr.s6_addr32[3];
6324 }
c4cf55e5
PWJ		 6325
6326 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6327 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6328 input, common, ring->queue_index);
c4cf55e5
PWJ		 6329}
6330
63544e9c 6331static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6332{
fc77dc3c 6333 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6334 /* Herbert's original patch had:
6335 * smp_mb__after_netif_stop_queue();
6336 * but since that doesn't exist yet, just open code it. */
6337 smp_mb();
6338
6339 /* We need to check again in a case another CPU has just
6340 * made room available. */
7d4987de 6341 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6342 return -EBUSY;
6343
6344 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6345 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6346 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6347 return 0;
6348}
6349
82d4e46e 6350static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6351{
7d4987de 6352 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6353 return 0;
fc77dc3c 6354 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6355}
6356
09a3b1f8
SH		 6357static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6358{
6359 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6360 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6361 smp_processor_id();
56075a98 6362#ifdef IXGBE_FCOE
6440752c 6363 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6364
e5b64635
JF		 6365 if (((protocol == htons(ETH_P_FCOE)) ||
6366 (protocol == htons(ETH_P_FIP))) &&
6367 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6368 struct ixgbe_ring_feature *f;
6369
6370 f = &adapter->ring_feature[RING_F_FCOE];
6371
6372 while (txq >= f->indices)
6373 txq -= f->indices;
e4b317e9 6374 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6375
e5b64635 6376 return txq;
56075a98
JF		 6377 }
6378#endif
6379
fdd3d631
KK		 6380 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6381 while (unlikely(txq >= dev->real_num_tx_queues))
6382 txq -= dev->real_num_tx_queues;
5f715823 6383 return txq;
fdd3d631 6384 }
c4cf55e5 6385
09a3b1f8
SH		 6386 return skb_tx_hash(dev, skb);
6387}
6388
fc77dc3c 6389netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6390 struct ixgbe_adapter *adapter,
6391 struct ixgbe_ring *tx_ring)
9a799d71 6392{
d3d00239 6393 struct ixgbe_tx_buffer *first;
5f715823 6394 int tso;
d3d00239 6395 u32 tx_flags = 0;
a535c30e
AD		 6396#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6397 unsigned short f;
6398#endif
a535c30e 6399 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6400 __be16 protocol = skb->protocol;
63544e9c 6401 u8 hdr_len = 0;
5e09a105 6402
a535c30e
AD		 6403 /*
6404 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6405 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6406 * + 2 desc gap to keep tail from touching head,
6407 * + 1 desc for context descriptor,
6408 * otherwise try next time
6409 */
6410#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6411 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6412 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6413#else
6414 count += skb_shinfo(skb)->nr_frags;
6415#endif
6416 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6417 tx_ring->tx_stats.tx_busy++;
6418 return NETDEV_TX_BUSY;
6419 }
6420
fd0db0ed
AD		 6421 /* record the location of the first descriptor for this packet */
6422 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6423 first->skb = skb;
091a6246
AD		 6424 first->bytecount = skb->len;
6425 first->gso_segs = 1;
fd0db0ed 6426
66f32a8b 6427 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6428 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6429 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6430 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6431 /* else if it is a SW VLAN check the next protocol and store the tag */
6432 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6433 struct vlan_hdr *vhdr, _vhdr;
6434 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6435 if (!vhdr)
6436 goto out_drop;
6437
6438 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6439 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6440 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6441 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6442 }
6443
aa7bd467
JK		 6444 skb_tx_timestamp(skb);
6445
3a6a4eda
JK		 6446#ifdef CONFIG_IXGBE_PTP
6447 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6448 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6449 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6450 }
6451#endif
6452
9e0c5648
AD		 6453#ifdef CONFIG_PCI_IOV
6454 /*
6455 * Use the l2switch_enable flag - would be false if the DMA
6456 * Tx switch had been disabled.
6457 */
6458 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6459 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6460
6461#endif
32701dc2 6462 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6463 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6464 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6465 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6466 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6467 tx_flags |= (skb->priority & 0x7) <<
6468 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6469 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6470 struct vlan_ethhdr *vhdr;
6471 if (skb_header_cloned(skb) &&
6472 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6473 goto out_drop;
6474 vhdr = (struct vlan_ethhdr *)skb->data;
6475 vhdr->h_vlan_TCI = htons(tx_flags >>
6476 IXGBE_TX_FLAGS_VLAN_SHIFT);
6477 } else {
6478 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6479 }
9a799d71 6480 }
eacd73f7 6481
244e27ad
AD		 6482 /* record initial flags and protocol */
6483 first->tx_flags = tx_flags;
6484 first->protocol = protocol;
6485
eacd73f7 6486#ifdef IXGBE_FCOE
66f32a8b
AD		 6487 /* setup tx offload for FCoE */
6488 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6489 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6490 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6491 if (tso < 0)
6492 goto out_drop;
9a799d71 6493
66f32a8b 6494 goto xmit_fcoe;
eacd73f7 6495 }
9a799d71 6496
66f32a8b 6497#endif /* IXGBE_FCOE */
244e27ad 6498 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6499 if (tso < 0)
897ab156 6500 goto out_drop;
244e27ad
AD		 6501 else if (!tso)
6502 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6503
6504 /* add the ATR filter if ATR is on */
6505 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6506 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6507
6508#ifdef IXGBE_FCOE
6509xmit_fcoe:
6510#endif /* IXGBE_FCOE */
244e27ad 6511 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6512
6513 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6514
6515 return NETDEV_TX_OK;
897ab156
AD		 6516
6517out_drop:
fd0db0ed
AD		 6518 dev_kfree_skb_any(first->skb);
6519 first->skb = NULL;
6520
897ab156 6521 return NETDEV_TX_OK;
9a799d71
AK		 6522}
6523
a50c29dd
AD		 6524static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6525 struct net_device *netdev)
84418e3b
AD		 6526{
6527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6528 struct ixgbe_ring *tx_ring;
6529
a50c29dd
AD		 6530 /*
6531 * The minimum packet size for olinfo paylen is 17 so pad the skb
6532 * in order to meet this minimum size requirement.
6533 */
f73332fc
SH		 6534 if (unlikely(skb->len < 17)) {
6535 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6536 return NETDEV_TX_OK;
6537 skb->len = 17;
71a49f77 6538 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6539 }
6540
84418e3b 6541 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6542 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6543}
6544
9a799d71
AK		 6545/**
6546 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6547 * @netdev: network interface device structure
6548 * @p: pointer to an address structure
6549 *
6550 * Returns 0 on success, negative on failure
6551 **/
6552static int ixgbe_set_mac(struct net_device *netdev, void *p)
6553{
6554 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6555 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6556 struct sockaddr *addr = p;
6557
6558 if (!is_valid_ether_addr(addr->sa_data))
6559 return -EADDRNOTAVAIL;
6560
6561 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6562 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6563
1d9c0bfd 6564 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6565
6566 return 0;
6567}
6568
6b73e10d
BH		 6569static int
6570ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6571{
6572 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6573 struct ixgbe_hw *hw = &adapter->hw;
6574 u16 value;
6575 int rc;
6576
6577 if (prtad != hw->phy.mdio.prtad)
6578 return -EINVAL;
6579 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6580 if (!rc)
6581 rc = value;
6582 return rc;
6583}
6584
6585static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6586 u16 addr, u16 value)
6587{
6588 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6589 struct ixgbe_hw *hw = &adapter->hw;
6590
6591 if (prtad != hw->phy.mdio.prtad)
6592 return -EINVAL;
6593 return hw->phy.ops.write_reg(hw, addr, devad, value);
6594}
6595
6596static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6597{
6598 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6599
3a6a4eda
JK		 6600 switch (cmd) {
6601#ifdef CONFIG_IXGBE_PTP
6602 case SIOCSHWTSTAMP:
6603 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6604#endif
6605 default:
6606 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6607 }
6b73e10d
BH		 6608}
6609
0365e6e4
PW		 6610/**
6611 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6612 * netdev->dev_addrs
0365e6e4
PW		 6613 * @netdev: network interface device structure
6614 *
6615 * Returns non-zero on failure
6616 **/
6617static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6618{
6619 int err = 0;
6620 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6621 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6622
7fa7c9dc 6623 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6624 rtnl_lock();
7fa7c9dc 6625 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6626 rtnl_unlock();
7fa7c9dc
AD		 6627
6628 /* update SAN MAC vmdq pool selection */
6629 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6630 }
6631 return err;
6632}
6633
6634/**
6635 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6636 * netdev->dev_addrs
0365e6e4
PW		 6637 * @netdev: network interface device structure
6638 *
6639 * Returns non-zero on failure
6640 **/
6641static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6642{
6643 int err = 0;
6644 struct ixgbe_adapter *adapter = netdev_priv(dev);
6645 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6646
6647 if (is_valid_ether_addr(mac->san_addr)) {
6648 rtnl_lock();
6649 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6650 rtnl_unlock();
6651 }
6652 return err;
6653}
6654
9a799d71
AK		 6655#ifdef CONFIG_NET_POLL_CONTROLLER
6656/*
6657 * Polling 'interrupt' - used by things like netconsole to send skbs
6658 * without having to re-enable interrupts. It's not called while
6659 * the interrupt routine is executing.
6660 */
6661static void ixgbe_netpoll(struct net_device *netdev)
6662{
6663 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6664 int i;
9a799d71 6665
1a647bd2
AD		 6666 /* if interface is down do nothing */
6667 if (test_bit(__IXGBE_DOWN, &adapter->state))
6668 return;
6669
9a799d71 6670 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6671 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6672 for (i = 0; i < adapter->num_q_vectors; i++)
6673 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6674 } else {
6675 ixgbe_intr(adapter->pdev->irq, netdev);
6676 }
9a799d71 6677 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6678}
9a799d71 6679
581330ba 6680#endif
de1036b1
ED		 6681static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6682 struct rtnl_link_stats64 *stats)
6683{
6684 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6685 int i;
6686
1a51502b 6687 rcu_read_lock();
de1036b1 6688 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6689 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6690 u64 bytes, packets;
6691 unsigned int start;
6692
1a51502b
ED		 6693 if (ring) {
6694 do {
6695 start = u64_stats_fetch_begin_bh(&ring->syncp);
6696 packets = ring->stats.packets;
6697 bytes = ring->stats.bytes;
6698 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6699 stats->rx_packets += packets;
6700 stats->rx_bytes += bytes;
6701 }
de1036b1 6702 }
1ac9ad13
ED		 6703
6704 for (i = 0; i < adapter->num_tx_queues; i++) {
6705 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6706 u64 bytes, packets;
6707 unsigned int start;
6708
6709 if (ring) {
6710 do {
6711 start = u64_stats_fetch_begin_bh(&ring->syncp);
6712 packets = ring->stats.packets;
6713 bytes = ring->stats.bytes;
6714 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6715 stats->tx_packets += packets;
6716 stats->tx_bytes += bytes;
6717 }
6718 }
1a51502b 6719 rcu_read_unlock();
de1036b1
ED		 6720 /* following stats updated by ixgbe_watchdog_task() */
6721 stats->multicast = netdev->stats.multicast;
6722 stats->rx_errors = netdev->stats.rx_errors;
6723 stats->rx_length_errors = netdev->stats.rx_length_errors;
6724 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6725 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6726 return stats;
6727}
6728
8af3c33f 6729#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6730/**
6731 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6732 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6733 * @tc: number of traffic classes currently enabled
6734 *
6735 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6736 * 802.1Q priority maps to a packet buffer that exists.
6737 */
6738static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6739{
6740 struct ixgbe_hw *hw = &adapter->hw;
6741 u32 reg, rsave;
6742 int i;
6743
6744 /* 82598 have a static priority to TC mapping that can not
6745 * be changed so no validation is needed.
6746 */
6747 if (hw->mac.type == ixgbe_mac_82598EB)
6748 return;
6749
6750 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6751 rsave = reg;
6752
6753 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6754 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6755
6756 /* If up2tc is out of bounds default to zero */
6757 if (up2tc > tc)
6758 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6759 }
6760
6761 if (reg != rsave)
6762 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6763
6764 return;
6765}
6766
02debdc9
AD		 6767/**
6768 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6769 * @adapter: Pointer to adapter struct
6770 *
6771 * Populate the netdev user priority to tc map
6772 */
6773static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6774{
6775 struct net_device *dev = adapter->netdev;
6776 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6777 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6778 u8 prio;
6779
6780 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6781 u8 tc = 0;
6782
6783 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6784 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6785 else if (ets)
6786 tc = ets->prio_tc[prio];
6787
6788 netdev_set_prio_tc_map(dev, prio, tc);
6789 }
6790}
6791
49ce9c2c
BH		 6792/**
6793 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6794 *
6795 * @netdev: net device to configure
6796 * @tc: number of traffic classes to enable
6797 */
6798int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6799{
8b1c0b24
JF		 6800 struct ixgbe_adapter *adapter = netdev_priv(dev);
6801 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6802
8b1c0b24 6803 /* Hardware supports up to 8 traffic classes */
4de2a022 6804 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6805 (hw->mac.type == ixgbe_mac_82598EB &&
6806 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6807 return -EINVAL;
6808
6809 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6810 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6811 * hardware is not flexible enough to do this dynamically.
6812 */
6813 if (netif_running(dev))
6814 ixgbe_close(dev);
6815 ixgbe_clear_interrupt_scheme(adapter);
6816
e7589eab 6817 if (tc) {
8b1c0b24 6818 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6819 ixgbe_set_prio_tc_map(adapter);
6820
e7589eab 6821 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6822
943561d3
AD		 6823 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6824 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6825 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6826 }
e7589eab 6827 } else {
8b1c0b24 6828 netdev_reset_tc(dev);
02debdc9 6829
943561d3
AD		 6830 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6831 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6832
6833 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6834
6835 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6836 adapter->dcb_cfg.pfc_mode_enable = false;
6837 }
6838
8b1c0b24
JF		 6839 ixgbe_init_interrupt_scheme(adapter);
6840 ixgbe_validate_rtr(adapter, tc);
6841 if (netif_running(dev))
6842 ixgbe_open(dev);
6843
6844 return 0;
6845}
de1036b1 6846
8af3c33f 6847#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6848void ixgbe_do_reset(struct net_device *netdev)
6849{
6850 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6851
6852 if (netif_running(netdev))
6853 ixgbe_reinit_locked(adapter);
6854 else
6855 ixgbe_reset(adapter);
6856}
6857
c8f44aff 6858static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6859 netdev_features_t features)
082757af
DS		 6860{
6861 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6862
082757af 6863 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6864 if (!(features & NETIF_F_RXCSUM))
6865 features &= ~NETIF_F_LRO;
082757af 6866
567d2de2
AD		 6867 /* Turn off LRO if not RSC capable */
6868 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6869 features &= ~NETIF_F_LRO;
8e2813f5 6870
567d2de2 6871 return features;
082757af
DS		 6872}
6873
c8f44aff 6874static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6875 netdev_features_t features)
082757af
DS		 6876{
6877 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6878 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6879 bool need_reset = false;
6880
082757af 6881 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6882 if (!(features & NETIF_F_LRO)) {
6883 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6884 need_reset = true;
567d2de2
AD		 6885 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6886 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6887 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6888 if (adapter->rx_itr_setting == 1 ||
6889 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6890 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6891 need_reset = true;
6892 } else if ((changed ^ features) & NETIF_F_LRO) {
6893 e_info(probe, "rx-usecs set too low, "
6894 "disabling RSC\n");
082757af
DS		 6895 }
6896 }
6897
6898 /*
6899 * Check if Flow Director n-tuple support was enabled or disabled. If
6900 * the state changed, we need to reset.
6901 */
39cb681b
AD		 6902 switch (features & NETIF_F_NTUPLE) {
6903 case NETIF_F_NTUPLE:
567d2de2 6904 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6905 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6906 need_reset = true;
6907
567d2de2
AD		 6908 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6909 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6910 break;
6911 default:
6912 /* turn off perfect filters, enable ATR and reset */
6913 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6914 need_reset = true;
6915
6916 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6917
6918 /* We cannot enable ATR if SR-IOV is enabled */
6919 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6920 break;
6921
6922 /* We cannot enable ATR if we have 2 or more traffic classes */
6923 if (netdev_get_num_tc(netdev) > 1)
6924 break;
6925
6926 /* We cannot enable ATR if RSS is disabled */
6927 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6928 break;
6929
6930 /* A sample rate of 0 indicates ATR disabled */
6931 if (!adapter->atr_sample_rate)
6932 break;
6933
6934 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6935 break;
082757af
DS		 6936 }
6937
146d4cc9
JF		 6938 if (features & NETIF_F_HW_VLAN_RX)
6939 ixgbe_vlan_strip_enable(adapter);
6940 else
6941 ixgbe_vlan_strip_disable(adapter);
6942
3f2d1c0f
BG		 6943 if (changed & NETIF_F_RXALL)
6944 need_reset = true;
6945
567d2de2 6946 netdev->features = features;
082757af
DS		 6947 if (need_reset)
6948 ixgbe_do_reset(netdev);
6949
6950 return 0;
082757af
DS		 6951}
6952
edc7d573 6953static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 6954 struct net_device *dev,
6b6e2725 6955 const unsigned char *addr,
0f4b0add
JF		 6956 u16 flags)
6957{
6958 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6959 int err;
6960
6961 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6962 return -EOPNOTSUPP;
0f4b0add
JF		 6963
6964 if (ndm->ndm_state & NUD_PERMANENT) {
6965 pr_info("%s: FDB only supports static addresses\n",
6966 ixgbe_driver_name);
6967 return -EINVAL;
6968 }
6969
95447461
JF		 6970 if (is_unicast_ether_addr(addr)) {
6971 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6972
6973 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6974 err = dev_uc_add_excl(dev, addr);
0f4b0add 6975 else
95447461
JF		 6976 err = -ENOMEM;
6977 } else if (is_multicast_ether_addr(addr)) {
6978 err = dev_mc_add_excl(dev, addr);
6979 } else {
6980 err = -EINVAL;
0f4b0add
JF		 6981 }
6982
6983 /* Only return duplicate errors if NLM_F_EXCL is set */
6984 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6985 err = 0;
6986
6987 return err;
6988}
6989
6990static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6991 struct net_device *dev,
6b6e2725 6992 const unsigned char *addr)
0f4b0add
JF		 6993{
6994 struct ixgbe_adapter *adapter = netdev_priv(dev);
6995 int err = -EOPNOTSUPP;
6996
6997 if (ndm->ndm_state & NUD_PERMANENT) {
6998 pr_info("%s: FDB only supports static addresses\n",
6999 ixgbe_driver_name);
7000 return -EINVAL;
7001 }
7002
7003 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7004 if (is_unicast_ether_addr(addr))
7005 err = dev_uc_del(dev, addr);
7006 else if (is_multicast_ether_addr(addr))
7007 err = dev_mc_del(dev, addr);
7008 else
7009 err = -EINVAL;
7010 }
7011
7012 return err;
7013}
7014
7015static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7016 struct netlink_callback *cb,
7017 struct net_device *dev,
7018 int idx)
7019{
7020 struct ixgbe_adapter *adapter = netdev_priv(dev);
7021
7022 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7023 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7024
7025 return idx;
7026}
7027
0edc3527 7028static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7029 .ndo_open = ixgbe_open,
0edc3527 7030 .ndo_stop = ixgbe_close,
00829823 7031 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7032 .ndo_select_queue = ixgbe_select_queue,
581330ba 7033 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7034 .ndo_validate_addr = eth_validate_addr,
7035 .ndo_set_mac_address = ixgbe_set_mac,
7036 .ndo_change_mtu = ixgbe_change_mtu,
7037 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7038 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7039 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7040 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7041 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7042 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7043 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7044 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7045 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7046 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7047#ifdef CONFIG_IXGBE_DCB
24095aa3 7048 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7049#endif
0edc3527
SH		 7050#ifdef CONFIG_NET_POLL_CONTROLLER
7051 .ndo_poll_controller = ixgbe_netpoll,
7052#endif
332d4a7d
YZ		 7053#ifdef IXGBE_FCOE
7054 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7055 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7056 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7057 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7058 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7059 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7060 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7061#endif /* IXGBE_FCOE */
082757af
DS		 7062 .ndo_set_features = ixgbe_set_features,
7063 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 7064 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7065 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7066 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 7067};
7068
8e2813f5
JK		 7069/**
7070 * ixgbe_wol_supported - Check whether device supports WoL
7071 * @hw: hw specific details
7072 * @device_id: the device ID
7073 * @subdev_id: the subsystem device ID
7074 *
7075 * This function is used by probe and ethtool to determine
7076 * which devices have WoL support
7077 *
7078 **/
7079int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7080 u16 subdevice_id)
7081{
7082 struct ixgbe_hw *hw = &adapter->hw;
7083 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7084 int is_wol_supported = 0;
7085
7086 switch (device_id) {
7087 case IXGBE_DEV_ID_82599_SFP:
7088 /* Only these subdevices could supports WOL */
7089 switch (subdevice_id) {
7090 case IXGBE_SUBDEV_ID_82599_560FLR:
7091 /* only support first port */
7092 if (hw->bus.func != 0)
7093 break;
7094 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7095 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7096 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8e2813f5
JK		 7097 is_wol_supported = 1;
7098 break;
7099 }
7100 break;
7101 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7102 /* All except this subdevice support WOL */
7103 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7104 is_wol_supported = 1;
7105 break;
7106 case IXGBE_DEV_ID_82599_KX4:
7107 is_wol_supported = 1;
7108 break;
7109 case IXGBE_DEV_ID_X540T:
df376f0d 7110 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7111 /* check eeprom to see if enabled wol */
7112 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7113 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7114 (hw->bus.func == 0))) {
7115 is_wol_supported = 1;
7116 }
7117 break;
7118 }
7119
7120 return is_wol_supported;
7121}
7122
9a799d71
AK		 7123/**
7124 * ixgbe_probe - Device Initialization Routine
7125 * @pdev: PCI device information struct
7126 * @ent: entry in ixgbe_pci_tbl
7127 *
7128 * Returns 0 on success, negative on failure
7129 *
7130 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7131 * The OS initialization, configuring of the adapter private structure,
7132 * and a hardware reset occur.
7133 **/
7134static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7135 const struct pci_device_id *ent)
9a799d71
AK		 7136{
7137 struct net_device *netdev;
7138 struct ixgbe_adapter *adapter = NULL;
7139 struct ixgbe_hw *hw;
7140 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7141 static int cards_found;
7142 int i, err, pci_using_dac;
289700db 7143 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7144 unsigned int indices = num_possible_cpus();
3f4a6f00 7145 unsigned int dcb_max = 0;
eacd73f7
YZ		 7146#ifdef IXGBE_FCOE
7147 u16 device_caps;
7148#endif
289700db 7149 u32 eec;
9a799d71 7150
bded64a7
AG		 7151 /* Catch broken hardware that put the wrong VF device ID in
7152 * the PCIe SR-IOV capability.
7153 */
7154 if (pdev->is_virtfn) {
7155 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7156 pci_name(pdev), pdev->vendor, pdev->device);
7157 return -EINVAL;
7158 }
7159
9ce77666 7160 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7161 if (err)
7162 return err;
7163
1b507730
NN		 7164 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7165 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7166 pci_using_dac = 1;
7167 } else {
1b507730 7168 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7169 if (err) {
1b507730
NN		 7170 err = dma_set_coherent_mask(&pdev->dev,
7171 DMA_BIT_MASK(32));
9a799d71 7172 if (err) {
b8bc0421
DC		 7173 dev_err(&pdev->dev,
7174 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7175 goto err_dma;
7176 }
7177 }
7178 pci_using_dac = 0;
7179 }
7180
9ce77666 7181 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7182 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7183 if (err) {
b8bc0421
DC		 7184 dev_err(&pdev->dev,
7185 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7186 goto err_pci_reg;
7187 }
7188
19d5afd4 7189 pci_enable_pcie_error_reporting(pdev);
6fabd715 7190
9a799d71 7191 pci_set_master(pdev);
fb3b27bc 7192 pci_save_state(pdev);
9a799d71 7193
e901acd6 7194#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7195 if (ii->mac == ixgbe_mac_82598EB)
7196 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7197 IXGBE_MAX_RSS_INDICES);
7198 else
7199 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7200 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7201#endif
7202
c85a2618
JF		 7203 if (ii->mac == ixgbe_mac_82598EB)
7204 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7205 else
7206 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7207
e901acd6 7208#ifdef IXGBE_FCOE
c85a2618
JF		 7209 indices += min_t(unsigned int, num_possible_cpus(),
7210 IXGBE_MAX_FCOE_INDICES);
7211#endif
3f4a6f00 7212 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7213 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7214 if (!netdev) {
7215 err = -ENOMEM;
7216 goto err_alloc_etherdev;
7217 }
7218
9a799d71
AK		 7219 SET_NETDEV_DEV(netdev, &pdev->dev);
7220
9a799d71 7221 adapter = netdev_priv(netdev);
c60fbb00 7222 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7223
7224 adapter->netdev = netdev;
7225 adapter->pdev = pdev;
7226 hw = &adapter->hw;
7227 hw->back = adapter;
b3f4d599 7228 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7229
05857980 7230 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7231 pci_resource_len(pdev, 0));
9a799d71
AK		 7232 if (!hw->hw_addr) {
7233 err = -EIO;
7234 goto err_ioremap;
7235 }
7236
0edc3527 7237 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7238 ixgbe_set_ethtool_ops(netdev);
9a799d71 7239 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7240 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7241
9a799d71
AK		 7242 adapter->bd_number = cards_found;
7243
9a799d71
AK		 7244 /* Setup hw api */
7245 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7246 hw->mac.type = ii->mac;
9a799d71 7247
c44ade9e
JB		 7248 /* EEPROM */
7249 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7250 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7251 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7252 if (!(eec & (1 << 8)))
7253 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7254
7255 /* PHY */
7256 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7257 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7258 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7259 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7260 hw->phy.mdio.mmds = 0;
7261 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7262 hw->phy.mdio.dev = netdev;
7263 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7264 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7265
8ca783ab 7266 ii->get_invariants(hw);
9a799d71
AK		 7267
7268 /* setup the private structure */
7269 err = ixgbe_sw_init(adapter);
7270 if (err)
7271 goto err_sw_init;
7272
e86bff0e 7273 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7274 switch (adapter->hw.mac.type) {
7275 case ixgbe_mac_82599EB:
7276 case ixgbe_mac_X540:
e86bff0e 7277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7278 break;
7279 default:
7280 break;
7281 }
e86bff0e 7282
bf069c97
DS		 7283 /*
7284 * If there is a fan on this device and it has failed log the
7285 * failure.
7286 */
7287 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7288 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7289 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7290 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7291 }
7292
8ef78adc
PWJ		 7293 if (allow_unsupported_sfp)
7294 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7295
c44ade9e 7296 /* reset_hw fills in the perm_addr as well */
119fc60a 7297 hw->phy.reset_if_overtemp = true;
c44ade9e 7298 err = hw->mac.ops.reset_hw(hw);
119fc60a 7299 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7300 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7301 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7302 err = 0;
7303 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7304 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7305 "module type was detected.\n");
7306 e_dev_err("Reload the driver after installing a supported "
7307 "module.\n");
04f165ef
PW		 7308 goto err_sw_init;
7309 } else if (err) {
849c4542 7310 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7311 goto err_sw_init;
7312 }
7313
99d74487
AD		 7314#ifdef CONFIG_PCI_IOV
7315 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7316
99d74487 7317#endif
396e799c 7318 netdev->features = NETIF_F_SG |
e8e9f696 7319 NETIF_F_IP_CSUM |
082757af 7320 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7321 NETIF_F_HW_VLAN_TX |
7322 NETIF_F_HW_VLAN_RX |
082757af
DS		 7323 NETIF_F_HW_VLAN_FILTER |
7324 NETIF_F_TSO |
7325 NETIF_F_TSO6 |
082757af
DS		 7326 NETIF_F_RXHASH |
7327 NETIF_F_RXCSUM;
9a799d71 7328
082757af 7329 netdev->hw_features = netdev->features;
ad31c402 7330
58be7666
DS		 7331 switch (adapter->hw.mac.type) {
7332 case ixgbe_mac_82599EB:
7333 case ixgbe_mac_X540:
45a5ead0 7334 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7335 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7336 NETIF_F_NTUPLE;
58be7666
DS		 7337 break;
7338 default:
7339 break;
7340 }
45a5ead0 7341
3f2d1c0f
BG		 7342 netdev->hw_features |= NETIF_F_RXALL;
7343
ad31c402
JK		 7344 netdev->vlan_features |= NETIF_F_TSO;
7345 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7346 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7347 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7348 netdev->vlan_features |= NETIF_F_SG;
7349
01789349 7350 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7351 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7352
7a6b6f51 7353#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7354 netdev->dcbnl_ops = &dcbnl_ops;
7355#endif
7356
eacd73f7 7357#ifdef IXGBE_FCOE
0d551589 7358 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7359 if (hw->mac.ops.get_device_caps) {
7360 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7361 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7362 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7363 }
7c8ae65a
AD		 7364
7365 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7366
a58915c7
AD		 7367 netdev->features |= NETIF_F_FSO |
7368 NETIF_F_FCOE_CRC;
7369
7c8ae65a
AD		 7370 netdev->vlan_features |= NETIF_F_FSO |
7371 NETIF_F_FCOE_CRC |
7372 NETIF_F_FCOE_MTU;
5e09d7f6 7373 }
eacd73f7 7374#endif /* IXGBE_FCOE */
7b872a55 7375 if (pci_using_dac) {
9a799d71 7376 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7377 netdev->vlan_features |= NETIF_F_HIGHDMA;
7378 }
9a799d71 7379
082757af
DS		 7380 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7381 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7382 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7383 netdev->features |= NETIF_F_LRO;
7384
9a799d71 7385 /* make sure the EEPROM is good */
c44ade9e 7386 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7387 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7388 err = -EIO;
35937c05 7389 goto err_sw_init;
9a799d71
AK		 7390 }
7391
7392 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7393 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7394
c44ade9e 7395 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7396 e_dev_err("invalid MAC address\n");
9a799d71 7397 err = -EIO;
35937c05 7398 goto err_sw_init;
9a799d71
AK		 7399 }
7400
7086400d 7401 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7402 (unsigned long) adapter);
9a799d71 7403
7086400d
AD		 7404 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7405 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7406
021230d4
AV		 7407 err = ixgbe_init_interrupt_scheme(adapter);
7408 if (err)
7409 goto err_sw_init;
9a799d71 7410
8e2813f5 7411 /* WOL not supported for all devices */
c23f5b6b 7412 adapter->wol = 0;
8e2813f5
JK		 7413 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7414 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7415 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7416
e8e26350
PW		 7417 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7418
15e5209f
ET		 7419 /* save off EEPROM version number */
7420 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7421 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7422
04f165ef
PW		 7423 /* pick up the PCI bus settings for reporting later */
7424 hw->mac.ops.get_bus_info(hw);
7425
9a799d71 7426 /* print bus type/speed/width info */
849c4542 7427 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7428 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7429 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7430 "Unknown"),
7431 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7432 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7433 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7434 "Unknown"),
7435 netdev->dev_addr);
289700db
DS		 7436
7437 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7438 if (err)
9fe93afd 7439 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7440 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7441 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7442 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7443 part_str);
e8e26350 7444 else
289700db
DS		 7445 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7446 hw->mac.type, hw->phy.type, part_str);
9a799d71 7447
e8e26350 7448 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7449 e_dev_warn("PCI-Express bandwidth available for this card is "
7450 "not sufficient for optimal performance.\n");
7451 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7452 "is required.\n");
0c254d86
AK		 7453 }
7454
9a799d71 7455 /* reset the hardware with the new settings */
794caeb2 7456 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7457 if (err == IXGBE_ERR_EEPROM_VERSION) {
7458 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7459 e_dev_warn("This device is a pre-production adapter/LOM. "
7460 "Please be aware there may be issues associated "
7461 "with your hardware. If you are experiencing "
7462 "problems please contact your Intel or hardware "
7463 "representative who provided you with this "
7464 "hardware.\n");
794caeb2 7465 }
9a799d71
AK		 7466 strcpy(netdev->name, "eth%d");
7467 err = register_netdev(netdev);
7468 if (err)
7469 goto err_register;
7470
93d3ce8f
ET		 7471 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7472 if (hw->mac.ops.disable_tx_laser &&
7473 ((hw->phy.multispeed_fiber) ||
7474 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7475 (hw->mac.type == ixgbe_mac_82599EB))))
7476 hw->mac.ops.disable_tx_laser(hw);
7477
54386467
JB		 7478 /* carrier off reporting is important to ethtool even BEFORE open */
7479 netif_carrier_off(netdev);
7480
5dd2d332 7481#ifdef CONFIG_IXGBE_DCA
652f093f 7482 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7483 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7484 ixgbe_setup_dca(adapter);
7485 }
7486#endif
1cdd1ec8 7487 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7488 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7489 for (i = 0; i < adapter->num_vfs; i++)
7490 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7491 }
7492
2466dd9c
JK		 7493 /* firmware requires driver version to be 0xFFFFFFFF
7494 * since os does not support feature
7495 */
9612de92 7496 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7497 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7498 0xFF);
9612de92 7499
0365e6e4
PW		 7500 /* add san mac addr to netdev */
7501 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7502
ea81875a 7503 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7504 cards_found++;
3ca8bc6d 7505
1210982b 7506#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7507 if (ixgbe_sysfs_init(adapter))
7508 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7509#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7510
00949167
CS		 7511#ifdef CONFIG_DEBUG_FS
7512 ixgbe_dbg_adapter_init(adapter);
7513#endif /* CONFIG_DEBUG_FS */
7514
9a799d71
AK		 7515 return 0;
7516
7517err_register:
5eba3699 7518 ixgbe_release_hw_control(adapter);
7a921c93 7519 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7520err_sw_init:
99d74487 7521 ixgbe_disable_sriov(adapter);
7086400d 7522 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7523 iounmap(hw->hw_addr);
7524err_ioremap:
7525 free_netdev(netdev);
7526err_alloc_etherdev:
e8e9f696
JP		 7527 pci_release_selected_regions(pdev,
7528 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7529err_pci_reg:
7530err_dma:
7531 pci_disable_device(pdev);
7532 return err;
7533}
7534
7535/**
7536 * ixgbe_remove - Device Removal Routine
7537 * @pdev: PCI device information struct
7538 *
7539 * ixgbe_remove is called by the PCI subsystem to alert the driver
7540 * that it should release a PCI device. The could be caused by a
7541 * Hot-Plug event, or because the driver is going to be removed from
7542 * memory.
7543 **/
7544static void __devexit ixgbe_remove(struct pci_dev *pdev)
7545{
c60fbb00
AD		 7546 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7547 struct net_device *netdev = adapter->netdev;
9a799d71 7548
00949167
CS		 7549#ifdef CONFIG_DEBUG_FS
7550 ixgbe_dbg_adapter_exit(adapter);
7551#endif /*CONFIG_DEBUG_FS */
7552
9a799d71 7553 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7554 cancel_work_sync(&adapter->service_task);
9a799d71 7555
3a6a4eda 7556
5dd2d332 7557#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7558 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7559 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7560 dca_remove_requester(&pdev->dev);
7561 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7562 }
7563
7564#endif
1210982b 7565#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7566 ixgbe_sysfs_exit(adapter);
1210982b 7567#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7568
0365e6e4
PW		 7569 /* remove the added san mac */
7570 ixgbe_del_sanmac_netdev(netdev);
7571
c4900be0
DS		 7572 if (netdev->reg_state == NETREG_REGISTERED)
7573 unregister_netdev(netdev);
9a799d71 7574
9297127b 7575 ixgbe_disable_sriov(adapter);
1cdd1ec8 7576
7a921c93 7577 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7578
021230d4 7579 ixgbe_release_hw_control(adapter);
9a799d71 7580
2b1588c3
AD		 7581#ifdef CONFIG_DCB
7582 kfree(adapter->ixgbe_ieee_pfc);
7583 kfree(adapter->ixgbe_ieee_ets);
7584
7585#endif
9a799d71 7586 iounmap(adapter->hw.hw_addr);
9ce77666 7587 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7588 IORESOURCE_MEM));
9a799d71 7589
849c4542 7590 e_dev_info("complete\n");
021230d4 7591
9a799d71
AK		 7592 free_netdev(netdev);
7593
19d5afd4 7594 pci_disable_pcie_error_reporting(pdev);
6fabd715 7595
9a799d71
AK		 7596 pci_disable_device(pdev);
7597}
7598
7599/**
7600 * ixgbe_io_error_detected - called when PCI error is detected
7601 * @pdev: Pointer to PCI device
7602 * @state: The current pci connection state
7603 *
7604 * This function is called after a PCI bus error affecting
7605 * this device has been detected.
7606 */
7607static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7608 pci_channel_state_t state)
9a799d71 7609{
c60fbb00
AD		 7610 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7611 struct net_device *netdev = adapter->netdev;
9a799d71 7612
83c61fa9
GR		 7613#ifdef CONFIG_PCI_IOV
7614 struct pci_dev *bdev, *vfdev;
7615 u32 dw0, dw1, dw2, dw3;
7616 int vf, pos;
7617 u16 req_id, pf_func;
7618
7619 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7620 adapter->num_vfs == 0)
7621 goto skip_bad_vf_detection;
7622
7623 bdev = pdev->bus->self;
62f87c0e 7624 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7625 bdev = bdev->bus->self;
7626
7627 if (!bdev)
7628 goto skip_bad_vf_detection;
7629
7630 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7631 if (!pos)
7632 goto skip_bad_vf_detection;
7633
7634 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7635 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7636 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7637 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7638
7639 req_id = dw1 >> 16;
7640 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7641 if (!(req_id & 0x0080))
7642 goto skip_bad_vf_detection;
7643
7644 pf_func = req_id & 0x01;
7645 if ((pf_func & 1) == (pdev->devfn & 1)) {
7646 unsigned int device_id;
7647
7648 vf = (req_id & 0x7F) >> 1;
7649 e_dev_err("VF %d has caused a PCIe error\n", vf);
7650 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7651 "%8.8x\tdw3: %8.8x\n",
7652 dw0, dw1, dw2, dw3);
7653 switch (adapter->hw.mac.type) {
7654 case ixgbe_mac_82599EB:
7655 device_id = IXGBE_82599_VF_DEVICE_ID;
7656 break;
7657 case ixgbe_mac_X540:
7658 device_id = IXGBE_X540_VF_DEVICE_ID;
7659 break;
7660 default:
7661 device_id = 0;
7662 break;
7663 }
7664
7665 /* Find the pci device of the offending VF */
36e90319 7666 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7667 while (vfdev) {
7668 if (vfdev->devfn == (req_id & 0xFF))
7669 break;
36e90319 7670 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7671 device_id, vfdev);
7672 }
7673 /*
7674 * There's a slim chance the VF could have been hot plugged,
7675 * so if it is no longer present we don't need to issue the
7676 * VFLR. Just clean up the AER in that case.
7677 */
7678 if (vfdev) {
7679 e_dev_err("Issuing VFLR to VF %d\n", vf);
7680 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7681 }
7682
7683 pci_cleanup_aer_uncorrect_error_status(pdev);
7684 }
7685
7686 /*
7687 * Even though the error may have occurred on the other port
7688 * we still need to increment the vf error reference count for
7689 * both ports because the I/O resume function will be called
7690 * for both of them.
7691 */
7692 adapter->vferr_refcount++;
7693
7694 return PCI_ERS_RESULT_RECOVERED;
7695
7696skip_bad_vf_detection:
7697#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7698 netif_device_detach(netdev);
7699
3044b8d1
BL		 7700 if (state == pci_channel_io_perm_failure)
7701 return PCI_ERS_RESULT_DISCONNECT;
7702
9a799d71
AK		 7703 if (netif_running(netdev))
7704 ixgbe_down(adapter);
7705 pci_disable_device(pdev);
7706
b4617240 7707 /* Request a slot reset. */
9a799d71
AK		 7708 return PCI_ERS_RESULT_NEED_RESET;
7709}
7710
7711/**
7712 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7713 * @pdev: Pointer to PCI device
7714 *
7715 * Restart the card from scratch, as if from a cold-boot.
7716 */
7717static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7718{
c60fbb00 7719 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7720 pci_ers_result_t result;
7721 int err;
9a799d71 7722
9ce77666 7723 if (pci_enable_device_mem(pdev)) {
396e799c 7724 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7725 result = PCI_ERS_RESULT_DISCONNECT;
7726 } else {
7727 pci_set_master(pdev);
7728 pci_restore_state(pdev);
c0e1f68b 7729 pci_save_state(pdev);
9a799d71 7730
dd4d8ca6 7731 pci_wake_from_d3(pdev, false);
9a799d71 7732
6fabd715 7733 ixgbe_reset(adapter);
88512539 7734 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7735 result = PCI_ERS_RESULT_RECOVERED;
7736 }
7737
7738 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7739 if (err) {
849c4542
ET		 7740 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7741 "failed 0x%0x\n", err);
6fabd715
PWJ		 7742 /* non-fatal, continue */
7743 }
9a799d71 7744
6fabd715 7745 return result;
9a799d71
AK		 7746}
7747
7748/**
7749 * ixgbe_io_resume - called when traffic can start flowing again.
7750 * @pdev: Pointer to PCI device
7751 *
7752 * This callback is called when the error recovery driver tells us that
7753 * its OK to resume normal operation.
7754 */
7755static void ixgbe_io_resume(struct pci_dev *pdev)
7756{
c60fbb00
AD		 7757 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7758 struct net_device *netdev = adapter->netdev;
9a799d71 7759
83c61fa9
GR		 7760#ifdef CONFIG_PCI_IOV
7761 if (adapter->vferr_refcount) {
7762 e_info(drv, "Resuming after VF err\n");
7763 adapter->vferr_refcount--;
7764 return;
7765 }
7766
7767#endif
c7ccde0f
AD		 7768 if (netif_running(netdev))
7769 ixgbe_up(adapter);
9a799d71
AK		 7770
7771 netif_device_attach(netdev);
9a799d71
AK		 7772}
7773
3646f0e5 7774static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 7775 .error_detected = ixgbe_io_error_detected,
7776 .slot_reset = ixgbe_io_slot_reset,
7777 .resume = ixgbe_io_resume,
7778};
7779
7780static struct pci_driver ixgbe_driver = {
7781 .name = ixgbe_driver_name,
7782 .id_table = ixgbe_pci_tbl,
7783 .probe = ixgbe_probe,
7784 .remove = __devexit_p(ixgbe_remove),
7785#ifdef CONFIG_PM
7786 .suspend = ixgbe_suspend,
7787 .resume = ixgbe_resume,
7788#endif
7789 .shutdown = ixgbe_shutdown,
7790 .err_handler = &ixgbe_err_handler
7791};
7792
7793/**
7794 * ixgbe_init_module - Driver Registration Routine
7795 *
7796 * ixgbe_init_module is the first routine called when the driver is
7797 * loaded. All it does is register with the PCI subsystem.
7798 **/
7799static int __init ixgbe_init_module(void)
7800{
7801 int ret;
c7689578 7802 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7803 pr_info("%s\n", ixgbe_copyright);
9a799d71 7804
00949167
CS		 7805#ifdef CONFIG_DEBUG_FS
7806 ixgbe_dbg_init();
7807#endif /* CONFIG_DEBUG_FS */
7808
5dd2d332 7809#ifdef CONFIG_IXGBE_DCA
bd0362dd 7810 dca_register_notify(&dca_notifier);
bd0362dd 7811#endif
5dd2d332 7812
9a799d71
AK		 7813 ret = pci_register_driver(&ixgbe_driver);
7814 return ret;
7815}
b4617240 7816
9a799d71
AK		 7817module_init(ixgbe_init_module);
7818
7819/**
7820 * ixgbe_exit_module - Driver Exit Cleanup Routine
7821 *
7822 * ixgbe_exit_module is called just before the driver is removed
7823 * from memory.
7824 **/
7825static void __exit ixgbe_exit_module(void)
7826{
5dd2d332 7827#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7828 dca_unregister_notify(&dca_notifier);
7829#endif
9a799d71 7830 pci_unregister_driver(&ixgbe_driver);
00949167
CS		 7831
7832#ifdef CONFIG_DEBUG_FS
7833 ixgbe_dbg_exit();
7834#endif /* CONFIG_DEBUG_FS */
7835
1a51502b 7836 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7837}
bd0362dd 7838
5dd2d332 7839#ifdef CONFIG_IXGBE_DCA
bd0362dd 7840static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7841 void *p)
bd0362dd
JC		 7842{
7843 int ret_val;
7844
7845 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7846 __ixgbe_notify_dca);
bd0362dd
JC		 7847
7848 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7849}
b453368d 7850
5dd2d332 7851#endif /* CONFIG_IXGBE_DCA */
849c4542 7852
9a799d71
AK		 7853module_exit(ixgbe_exit_module);
7854
7855/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)