projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
arch,doc: Convert smp_mb__*()
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/ethtool.h>
01789349 46#include <linux/if.h>
9a799d71 47#include <linux/if_vlan.h>
2a47fa45 48#include <linux/if_macvlan.h>
815cccbf 49#include <linux/if_bridge.h>
70c71606 50#include <linux/prefetch.h>
eacd73f7 51#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 52
53#include "ixgbe.h"
54#include "ixgbe_common.h"
ee5f784a 55#include "ixgbe_dcb_82599.h"
1cdd1ec8 56#include "ixgbe_sriov.h"
9a799d71
AK		 57
58char ixgbe_driver_name[] = "ixgbe";
9c8eb720 59static const char ixgbe_driver_string[] =
e8e9f696 60 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 61#ifdef IXGBE_FCOE
ea81875a
NP		 62char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 64#else
65static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67#endif
f341c4e0 68#define DRV_VERSION "3.19.1-k"
9c8eb720 69const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 70static const char ixgbe_copyright[] =
0391bbe3 71 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 72
73static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 74 [board_82598] = &ixgbe_82598_info,
e8e26350 75 [board_82599] = &ixgbe_82599_info,
fe15e8e1 76 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 77};
78
79/* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
170e8543 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
14438464
MR		 155static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
b8e82001
JK		 157static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159{
b8e82001
JK		 160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
c0798edf 171 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 172 return -1;
173
c0798edf 174 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
b8e82001
JK		 178 return 0;
179}
180
181static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182{
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202}
203
e027d1ae
JK		 204/**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214{
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 218 return true;
219 default:
220 return false;
221 }
222}
223
224static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226{
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
9f0a433c 255 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 273 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282}
283
7086400d
AD		 284static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285{
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290}
291
2a1a091c
MR		 292static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293{
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
58cf663f
MR		 300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 302}
303
304void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
305{
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321}
322
14438464
MR		 323static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
324{
325 u16 value;
326
327 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
328 if (value == IXGBE_FAILED_READ_CFG_WORD) {
329 ixgbe_remove_adapter(hw);
330 return true;
331 }
332 return false;
333}
334
335u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
336{
337 struct ixgbe_adapter *adapter = hw->back;
338 u16 value;
339
340 if (ixgbe_removed(hw->hw_addr))
341 return IXGBE_FAILED_READ_CFG_WORD;
342 pci_read_config_word(adapter->pdev, reg, &value);
343 if (value == IXGBE_FAILED_READ_CFG_WORD &&
344 ixgbe_check_cfg_remove(hw, adapter->pdev))
345 return IXGBE_FAILED_READ_CFG_WORD;
346 return value;
347}
348
349#ifdef CONFIG_PCI_IOV
350static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
351{
352 struct ixgbe_adapter *adapter = hw->back;
353 u32 value;
354
355 if (ixgbe_removed(hw->hw_addr))
356 return IXGBE_FAILED_READ_CFG_DWORD;
357 pci_read_config_dword(adapter->pdev, reg, &value);
358 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
359 ixgbe_check_cfg_remove(hw, adapter->pdev))
360 return IXGBE_FAILED_READ_CFG_DWORD;
361 return value;
362}
363#endif /* CONFIG_PCI_IOV */
364
ed19231c
JK		 365void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
366{
367 struct ixgbe_adapter *adapter = hw->back;
368
369 if (ixgbe_removed(hw->hw_addr))
370 return;
371 pci_write_config_word(adapter->pdev, reg, value);
372}
373
7086400d
AD		 374static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
375{
376 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
377
52f33af8 378 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 379 smp_mb__before_clear_bit();
380 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
381}
382
dcd79aeb
TI		 383struct ixgbe_reg_info {
384 u32 ofs;
385 char *name;
386};
387
388static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
389
390 /* General Registers */
391 {IXGBE_CTRL, "CTRL"},
392 {IXGBE_STATUS, "STATUS"},
393 {IXGBE_CTRL_EXT, "CTRL_EXT"},
394
395 /* Interrupt Registers */
396 {IXGBE_EICR, "EICR"},
397
398 /* RX Registers */
399 {IXGBE_SRRCTL(0), "SRRCTL"},
400 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
401 {IXGBE_RDLEN(0), "RDLEN"},
402 {IXGBE_RDH(0), "RDH"},
403 {IXGBE_RDT(0), "RDT"},
404 {IXGBE_RXDCTL(0), "RXDCTL"},
405 {IXGBE_RDBAL(0), "RDBAL"},
406 {IXGBE_RDBAH(0), "RDBAH"},
407
408 /* TX Registers */
409 {IXGBE_TDBAL(0), "TDBAL"},
410 {IXGBE_TDBAH(0), "TDBAH"},
411 {IXGBE_TDLEN(0), "TDLEN"},
412 {IXGBE_TDH(0), "TDH"},
413 {IXGBE_TDT(0), "TDT"},
414 {IXGBE_TXDCTL(0), "TXDCTL"},
415
416 /* List Terminator */
417 {}
418};
419
420
421/*
422 * ixgbe_regdump - register printout routine
423 */
424static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
425{
426 int i = 0, j = 0;
427 char rname[16];
428 u32 regs[64];
429
430 switch (reginfo->ofs) {
431 case IXGBE_SRRCTL(0):
432 for (i = 0; i < 64; i++)
433 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
434 break;
435 case IXGBE_DCA_RXCTRL(0):
436 for (i = 0; i < 64; i++)
437 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
438 break;
439 case IXGBE_RDLEN(0):
440 for (i = 0; i < 64; i++)
441 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
442 break;
443 case IXGBE_RDH(0):
444 for (i = 0; i < 64; i++)
445 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
446 break;
447 case IXGBE_RDT(0):
448 for (i = 0; i < 64; i++)
449 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
450 break;
451 case IXGBE_RXDCTL(0):
452 for (i = 0; i < 64; i++)
453 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
454 break;
455 case IXGBE_RDBAL(0):
456 for (i = 0; i < 64; i++)
457 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
458 break;
459 case IXGBE_RDBAH(0):
460 for (i = 0; i < 64; i++)
461 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
462 break;
463 case IXGBE_TDBAL(0):
464 for (i = 0; i < 64; i++)
465 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
466 break;
467 case IXGBE_TDBAH(0):
468 for (i = 0; i < 64; i++)
469 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
470 break;
471 case IXGBE_TDLEN(0):
472 for (i = 0; i < 64; i++)
473 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
474 break;
475 case IXGBE_TDH(0):
476 for (i = 0; i < 64; i++)
477 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
478 break;
479 case IXGBE_TDT(0):
480 for (i = 0; i < 64; i++)
481 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
482 break;
483 case IXGBE_TXDCTL(0):
484 for (i = 0; i < 64; i++)
485 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
486 break;
487 default:
c7689578 488 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 489 IXGBE_READ_REG(hw, reginfo->ofs));
490 return;
491 }
492
493 for (i = 0; i < 8; i++) {
494 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 495 pr_err("%-15s", rname);
dcd79aeb 496 for (j = 0; j < 8; j++)
c7689578
JP		 497 pr_cont(" %08x", regs[i*8+j]);
498 pr_cont("\n");
dcd79aeb
TI		 499 }
500
501}
502
503/*
504 * ixgbe_dump - Print registers, tx-rings and rx-rings
505 */
506static void ixgbe_dump(struct ixgbe_adapter *adapter)
507{
508 struct net_device *netdev = adapter->netdev;
509 struct ixgbe_hw *hw = &adapter->hw;
510 struct ixgbe_reg_info *reginfo;
511 int n = 0;
512 struct ixgbe_ring *tx_ring;
729739b7 513 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 514 union ixgbe_adv_tx_desc *tx_desc;
515 struct my_u0 { u64 a; u64 b; } *u0;
516 struct ixgbe_ring *rx_ring;
517 union ixgbe_adv_rx_desc *rx_desc;
518 struct ixgbe_rx_buffer *rx_buffer_info;
519 u32 staterr;
520 int i = 0;
521
522 if (!netif_msg_hw(adapter))
523 return;
524
525 /* Print netdevice Info */
526 if (netdev) {
527 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 528 pr_info("Device Name state "
dcd79aeb 529 "trans_start last_rx\n");
c7689578
JP		 530 pr_info("%-15s %016lX %016lX %016lX\n",
531 netdev->name,
532 netdev->state,
533 netdev->trans_start,
534 netdev->last_rx);
dcd79aeb
TI		 535 }
536
537 /* Print Registers */
538 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 539 pr_info(" Register Name Value\n");
dcd79aeb
TI		 540 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
541 reginfo->name; reginfo++) {
542 ixgbe_regdump(hw, reginfo);
543 }
544
545 /* Print TX Ring Summary */
546 if (!netdev || !netif_running(netdev))
547 goto exit;
548
549 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 550 pr_info(" %s %s %s %s\n",
551 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
552 "leng", "ntw", "timestamp");
dcd79aeb
TI		 553 for (n = 0; n < adapter->num_tx_queues; n++) {
554 tx_ring = adapter->tx_ring[n];
729739b7 555 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 556 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 557 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 558 (u64)dma_unmap_addr(tx_buffer, dma),
559 dma_unmap_len(tx_buffer, len),
560 tx_buffer->next_to_watch,
561 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 562 }
563
564 /* Print TX Rings */
565 if (!netif_msg_tx_done(adapter))
566 goto rx_ring_summary;
567
568 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
569
570 /* Transmit Descriptor Formats
571 *
39ac868a 572 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 573 * +--------------------------------------------------------------+
574 * 0 | Buffer Address [63:0] |
575 * +--------------------------------------------------------------+
39ac868a 576 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 577 * +--------------------------------------------------------------+
578 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 579 *
580 * 82598 Advanced Transmit Descriptor (Write-Back Format)
581 * +--------------------------------------------------------------+
582 * 0 | RSV [63:0] |
583 * +--------------------------------------------------------------+
584 * 8 | RSV | STA | NXTSEQ |
585 * +--------------------------------------------------------------+
586 * 63 36 35 32 31 0
587 *
588 * 82599+ Advanced Transmit Descriptor
589 * +--------------------------------------------------------------+
590 * 0 | Buffer Address [63:0] |
591 * +--------------------------------------------------------------+
592 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
593 * +--------------------------------------------------------------+
594 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
595 *
596 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
597 * +--------------------------------------------------------------+
598 * 0 | RSV [63:0] |
599 * +--------------------------------------------------------------+
600 * 8 | RSV | STA | RSV |
601 * +--------------------------------------------------------------+
602 * 63 36 35 32 31 0
dcd79aeb
TI		 603 */
604
605 for (n = 0; n < adapter->num_tx_queues; n++) {
606 tx_ring = adapter->tx_ring[n];
c7689578
JP		 607 pr_info("------------------------------------\n");
608 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
609 pr_info("------------------------------------\n");
8ad88e37
JH		 610 pr_info("%s%s %s %s %s %s\n",
611 "T [desc] [address 63:0 ] ",
612 "[PlPOIdStDDt Ln] [bi->dma ] ",
613 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 614
615 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 616 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 617 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 618 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 619 if (dma_unmap_len(tx_buffer, len) > 0) {
620 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
621 i,
622 le64_to_cpu(u0->a),
623 le64_to_cpu(u0->b),
624 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 625 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 626 tx_buffer->next_to_watch,
627 (u64)tx_buffer->time_stamp,
628 tx_buffer->skb);
629 if (i == tx_ring->next_to_use &&
630 i == tx_ring->next_to_clean)
631 pr_cont(" NTC/U\n");
632 else if (i == tx_ring->next_to_use)
633 pr_cont(" NTU\n");
634 else if (i == tx_ring->next_to_clean)
635 pr_cont(" NTC\n");
636 else
637 pr_cont("\n");
638
639 if (netif_msg_pktdata(adapter) &&
640 tx_buffer->skb)
641 print_hex_dump(KERN_INFO, "",
642 DUMP_PREFIX_ADDRESS, 16, 1,
643 tx_buffer->skb->data,
644 dma_unmap_len(tx_buffer, len),
645 true);
646 }
dcd79aeb
TI		 647 }
648 }
649
650 /* Print RX Rings Summary */
651rx_ring_summary:
652 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 653 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 654 for (n = 0; n < adapter->num_rx_queues; n++) {
655 rx_ring = adapter->rx_ring[n];
c7689578
JP		 656 pr_info("%5d %5X %5X\n",
657 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 658 }
659
660 /* Print RX Rings */
661 if (!netif_msg_rx_status(adapter))
662 goto exit;
663
664 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
665
39ac868a
JH		 666 /* Receive Descriptor Formats
667 *
668 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 669 * 63 1 0
670 * +-----------------------------------------------------+
671 * 0 | Packet Buffer Address [63:1] |A0/NSE|
672 * +----------------------------------------------+------+
673 * 8 | Header Buffer Address [63:1] | DD |
674 * +-----------------------------------------------------+
675 *
676 *
39ac868a 677 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 678 *
679 * 63 48 47 32 31 30 21 20 16 15 4 3 0
680 * +------------------------------------------------------+
39ac868a
JH		 681 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
682 * | Packet | IP | | | | Type | Type |
683 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 684 * +------------------------------------------------------+
685 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
686 * +------------------------------------------------------+
687 * 63 48 47 32 31 20 19 0
39ac868a
JH		 688 *
689 * 82599+ Advanced Receive Descriptor (Read) Format
690 * 63 1 0
691 * +-----------------------------------------------------+
692 * 0 | Packet Buffer Address [63:1] |A0/NSE|
693 * +----------------------------------------------+------+
694 * 8 | Header Buffer Address [63:1] | DD |
695 * +-----------------------------------------------------+
696 *
697 *
698 * 82599+ Advanced Receive Descriptor (Write-Back) Format
699 *
700 * 63 48 47 32 31 30 21 20 17 16 4 3 0
701 * +------------------------------------------------------+
702 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
703 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
704 * |/ Flow Dir Flt ID | | | | | |
705 * +------------------------------------------------------+
706 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
707 * +------------------------------------------------------+
708 * 63 48 47 32 31 20 19 0
dcd79aeb 709 */
39ac868a 710
dcd79aeb
TI		 711 for (n = 0; n < adapter->num_rx_queues; n++) {
712 rx_ring = adapter->rx_ring[n];
c7689578
JP		 713 pr_info("------------------------------------\n");
714 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
715 pr_info("------------------------------------\n");
8ad88e37
JH		 716 pr_info("%s%s%s",
717 "R [desc] [ PktBuf A0] ",
718 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 719 "<-- Adv Rx Read format\n");
8ad88e37
JH		 720 pr_info("%s%s%s",
721 "RWB[desc] [PcsmIpSHl PtRs] ",
722 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 723 "<-- Adv Rx Write-Back format\n");
724
725 for (i = 0; i < rx_ring->count; i++) {
726 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 727 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 728 u0 = (struct my_u0 *)rx_desc;
729 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
730 if (staterr & IXGBE_RXD_STAT_DD) {
731 /* Descriptor Done */
c7689578 732 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 733 "%016llX ---------------- %p", i,
734 le64_to_cpu(u0->a),
735 le64_to_cpu(u0->b),
736 rx_buffer_info->skb);
737 } else {
c7689578 738 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 739 "%016llX %016llX %p", i,
740 le64_to_cpu(u0->a),
741 le64_to_cpu(u0->b),
742 (u64)rx_buffer_info->dma,
743 rx_buffer_info->skb);
744
9c50c035
ET		 745 if (netif_msg_pktdata(adapter) &&
746 rx_buffer_info->dma) {
dcd79aeb
TI		 747 print_hex_dump(KERN_INFO, "",
748 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 749 page_address(rx_buffer_info->page) +
750 rx_buffer_info->page_offset,
f800326d 751 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 752 }
753 }
754
755 if (i == rx_ring->next_to_use)
c7689578 756 pr_cont(" NTU\n");
dcd79aeb 757 else if (i == rx_ring->next_to_clean)
c7689578 758 pr_cont(" NTC\n");
dcd79aeb 759 else
c7689578 760 pr_cont("\n");
dcd79aeb
TI		 761
762 }
763 }
764
765exit:
766 return;
767}
768
5eba3699
AV		 769static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
770{
771 u32 ctrl_ext;
772
773 /* Let firmware take over control of h/w */
774 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
775 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 776 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 777}
778
779static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
780{
781 u32 ctrl_ext;
782
783 /* Let firmware know the driver has taken over */
784 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 786 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 787}
9a799d71 788
49ce9c2c 789/**
e8e26350
PW		 790 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
791 * @adapter: pointer to adapter struct
792 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
793 * @queue: queue to map the corresponding interrupt to
794 * @msix_vector: the vector to map to the corresponding queue
795 *
796 */
797static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 798 u8 queue, u8 msix_vector)
9a799d71
AK		 799{
800 u32 ivar, index;
e8e26350
PW		 801 struct ixgbe_hw *hw = &adapter->hw;
802 switch (hw->mac.type) {
803 case ixgbe_mac_82598EB:
804 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
805 if (direction == -1)
806 direction = 0;
807 index = (((direction * 64) + queue) >> 2) & 0x1F;
808 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
809 ivar &= ~(0xFF << (8 * (queue & 0x3)));
810 ivar |= (msix_vector << (8 * (queue & 0x3)));
811 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
812 break;
813 case ixgbe_mac_82599EB:
b93a2226 814 case ixgbe_mac_X540:
e8e26350
PW		 815 if (direction == -1) {
816 /* other causes */
817 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
818 index = ((queue & 1) * 8);
819 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
820 ivar &= ~(0xFF << index);
821 ivar |= (msix_vector << index);
822 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
823 break;
824 } else {
825 /* tx or rx causes */
826 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
827 index = ((16 * (queue & 1)) + (8 * direction));
828 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
829 ivar &= ~(0xFF << index);
830 ivar |= (msix_vector << index);
831 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
832 break;
833 }
834 default:
835 break;
836 }
9a799d71
AK		 837}
838
fe49f04a 839static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 840 u64 qmask)
fe49f04a
AD		 841{
842 u32 mask;
843
bd508178
AD		 844 switch (adapter->hw.mac.type) {
845 case ixgbe_mac_82598EB:
fe49f04a
AD		 846 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
847 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 848 break;
849 case ixgbe_mac_82599EB:
b93a2226 850 case ixgbe_mac_X540:
fe49f04a
AD		 851 mask = (qmask & 0xFFFFFFFF);
852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
853 mask = (qmask >> 32);
854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 855 break;
856 default:
857 break;
fe49f04a
AD		 858 }
859}
860
729739b7
AD		 861void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
862 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 863{
729739b7
AD		 864 if (tx_buffer->skb) {
865 dev_kfree_skb_any(tx_buffer->skb);
866 if (dma_unmap_len(tx_buffer, len))
d3d00239 867 dma_unmap_single(ring->dev,
729739b7
AD		 868 dma_unmap_addr(tx_buffer, dma),
869 dma_unmap_len(tx_buffer, len),
870 DMA_TO_DEVICE);
871 } else if (dma_unmap_len(tx_buffer, len)) {
872 dma_unmap_page(ring->dev,
873 dma_unmap_addr(tx_buffer, dma),
874 dma_unmap_len(tx_buffer, len),
875 DMA_TO_DEVICE);
e5a43549 876 }
729739b7
AD		 877 tx_buffer->next_to_watch = NULL;
878 tx_buffer->skb = NULL;
879 dma_unmap_len_set(tx_buffer, len, 0);
880 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 881}
882
943561d3 883static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 884{
885 struct ixgbe_hw *hw = &adapter->hw;
886 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 887 int i;
943561d3 888 u32 data;
c84d324c 889
943561d3
AD		 890 if ((hw->fc.current_mode != ixgbe_fc_full) &&
891 (hw->fc.current_mode != ixgbe_fc_rx_pause))
892 return;
c84d324c 893
943561d3
AD		 894 switch (hw->mac.type) {
895 case ixgbe_mac_82598EB:
896 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
897 break;
898 default:
899 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
900 }
901 hwstats->lxoffrxc += data;
c84d324c 902
943561d3
AD		 903 /* refill credits (no tx hang) if we received xoff */
904 if (!data)
c84d324c 905 return;
943561d3
AD		 906
907 for (i = 0; i < adapter->num_tx_queues; i++)
908 clear_bit(__IXGBE_HANG_CHECK_ARMED,
909 &adapter->tx_ring[i]->state);
910}
911
912static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
913{
914 struct ixgbe_hw *hw = &adapter->hw;
915 struct ixgbe_hw_stats *hwstats = &adapter->stats;
916 u32 xoff[8] = {0};
2afaa00d 917 u8 tc;
943561d3
AD		 918 int i;
919 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
920
921 if (adapter->ixgbe_ieee_pfc)
922 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
923
924 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
925 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 926 return;
943561d3 927 }
c84d324c
JF		 928
929 /* update stats for each tc, only valid with PFC enabled */
930 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 931 u32 pxoffrxc;
932
c84d324c
JF		 933 switch (hw->mac.type) {
934 case ixgbe_mac_82598EB:
2afaa00d 935 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 936 break;
c84d324c 937 default:
2afaa00d 938 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 939 }
2afaa00d
PN		 940 hwstats->pxoffrxc[i] += pxoffrxc;
941 /* Get the TC for given UP */
942 tc = netdev_get_prio_tc_map(adapter->netdev, i);
943 xoff[tc] += pxoffrxc;
c84d324c
JF		 944 }
945
946 /* disarm tx queues that have received xoff frames */
947 for (i = 0; i < adapter->num_tx_queues; i++) {
948 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 949
2afaa00d 950 tc = tx_ring->dcb_tc;
c84d324c
JF		 951 if (xoff[tc])
952 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 953 }
26f23d82
YZ		 954}
955
c84d324c 956static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 957{
7d7ce682 958 return ring->stats.packets;
c84d324c
JF		 959}
960
961static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
962{
2a47fa45
JF		 963 struct ixgbe_adapter *adapter;
964 struct ixgbe_hw *hw;
965 u32 head, tail;
966
967 if (ring->l2_accel_priv)
968 adapter = ring->l2_accel_priv->real_adapter;
969 else
970 adapter = netdev_priv(ring->netdev);
e01c31a5 971
2a47fa45
JF		 972 hw = &adapter->hw;
973 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
974 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 975
976 if (head != tail)
977 return (head < tail) ?
978 tail - head : (tail + ring->count - head);
979
980 return 0;
981}
982
983static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
984{
985 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
986 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
987 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
988 bool ret = false;
989
7d637bcc 990 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 991
992 /*
993 * Check for a hung queue, but be thorough. This verifies
994 * that a transmit has been completed since the previous
995 * check AND there is at least one packet pending. The
996 * ARMED bit is set to indicate a potential hang. The
997 * bit is cleared if a pause frame is received to remove
998 * false hang detection due to PFC or 802.3x frames. By
999 * requiring this to fail twice we avoid races with
1000 * pfc clearing the ARMED bit and conditions where we
1001 * run the check_tx_hang logic with a transmit completion
1002 * pending but without time to complete it yet.
1003 */
1004 if ((tx_done_old == tx_done) && tx_pending) {
1005 /* make sure it is true for two checks in a row */
1006 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1007 &tx_ring->state);
1008 } else {
1009 /* update completed stats and continue */
1010 tx_ring->tx_stats.tx_done_old = tx_done;
1011 /* reset the countdown */
1012 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 1013 }
1014
c84d324c 1015 return ret;
9a799d71
AK		 1016}
1017
c83c6cbd
AD		 1018/**
1019 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1020 * @adapter: driver private struct
1021 **/
1022static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1023{
1024
1025 /* Do the reset outside of interrupt context */
1026 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1027 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1028 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1029 ixgbe_service_event_schedule(adapter);
1030 }
1031}
e01c31a5 1032
9a799d71
AK		 1033/**
1034 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1035 * @q_vector: structure containing interrupt and ring information
e01c31a5 1036 * @tx_ring: tx ring to clean
9a799d71 1037 **/
fe49f04a 1038static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1039 struct ixgbe_ring *tx_ring)
9a799d71 1040{
fe49f04a 1041 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1042 struct ixgbe_tx_buffer *tx_buffer;
1043 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1044 unsigned int total_bytes = 0, total_packets = 0;
59224555 1045 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1046 unsigned int i = tx_ring->next_to_clean;
1047
1048 if (test_bit(__IXGBE_DOWN, &adapter->state))
1049 return true;
9a799d71 1050
d3d00239 1051 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1052 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1053 i -= tx_ring->count;
12207e49 1054
729739b7 1055 do {
d3d00239
AD		 1056 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1057
1058 /* if next_to_watch is not set then there is no work pending */
1059 if (!eop_desc)
1060 break;
1061
7f83a9e6 1062 /* prevent any other reads prior to eop_desc */
7e63bf49 1063 read_barrier_depends();
7f83a9e6 1064
d3d00239
AD		 1065 /* if DD is not set pending work has not been completed */
1066 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1067 break;
8ad494b0 1068
d3d00239
AD		 1069 /* clear next_to_watch to prevent false hangs */
1070 tx_buffer->next_to_watch = NULL;
8ad494b0 1071
091a6246
AD		 1072 /* update the statistics for this packet */
1073 total_bytes += tx_buffer->bytecount;
1074 total_packets += tx_buffer->gso_segs;
1075
fd0db0ed
AD		 1076 /* free the skb */
1077 dev_kfree_skb_any(tx_buffer->skb);
1078
729739b7
AD		 1079 /* unmap skb header data */
1080 dma_unmap_single(tx_ring->dev,
1081 dma_unmap_addr(tx_buffer, dma),
1082 dma_unmap_len(tx_buffer, len),
1083 DMA_TO_DEVICE);
1084
fd0db0ed
AD		 1085 /* clear tx_buffer data */
1086 tx_buffer->skb = NULL;
729739b7 1087 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1088
729739b7
AD		 1089 /* unmap remaining buffers */
1090 while (tx_desc != eop_desc) {
d3d00239
AD		 1091 tx_buffer++;
1092 tx_desc++;
8ad494b0 1093 i++;
729739b7
AD		 1094 if (unlikely(!i)) {
1095 i -= tx_ring->count;
d3d00239 1096 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1097 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1098 }
e01c31a5 1099
729739b7
AD		 1100 /* unmap any remaining paged data */
1101 if (dma_unmap_len(tx_buffer, len)) {
1102 dma_unmap_page(tx_ring->dev,
1103 dma_unmap_addr(tx_buffer, dma),
1104 dma_unmap_len(tx_buffer, len),
1105 DMA_TO_DEVICE);
1106 dma_unmap_len_set(tx_buffer, len, 0);
1107 }
1108 }
1109
1110 /* move us one more past the eop_desc for start of next pkt */
1111 tx_buffer++;
1112 tx_desc++;
1113 i++;
1114 if (unlikely(!i)) {
1115 i -= tx_ring->count;
1116 tx_buffer = tx_ring->tx_buffer_info;
1117 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1118 }
1119
1120 /* issue prefetch for next Tx descriptor */
1121 prefetch(tx_desc);
12207e49 1122
729739b7
AD		 1123 /* update budget accounting */
1124 budget--;
1125 } while (likely(budget));
1126
1127 i += tx_ring->count;
9a799d71 1128 tx_ring->next_to_clean = i;
d3d00239 1129 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1130 tx_ring->stats.bytes += total_bytes;
bd198058 1131 tx_ring->stats.packets += total_packets;
d3d00239 1132 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1133 q_vector->tx.total_bytes += total_bytes;
1134 q_vector->tx.total_packets += total_packets;
b953799e 1135
c84d324c
JF		 1136 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1137 /* schedule immediate reset if we believe we hung */
1138 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1139 e_err(drv, "Detected Tx Unit Hang\n"
1140 " Tx Queue <%d>\n"
1141 " TDH, TDT <%x>, <%x>\n"
1142 " next_to_use <%x>\n"
1143 " next_to_clean <%x>\n"
1144 "tx_buffer_info[next_to_clean]\n"
1145 " time_stamp <%lx>\n"
1146 " jiffies <%lx>\n",
1147 tx_ring->queue_index,
1148 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1149 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1150 tx_ring->next_to_use, i,
1151 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1152
1153 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1154
1155 e_info(probe,
1156 "tx hang %d detected on queue %d, resetting adapter\n",
1157 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1158
b953799e 1159 /* schedule immediate reset if we believe we hung */
c83c6cbd 1160 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1161
1162 /* the adapter is about to reset, no point in enabling stuff */
59224555 1163 return true;
b953799e 1164 }
9a799d71 1165
b2d96e0a
AD		 1166 netdev_tx_completed_queue(txring_txq(tx_ring),
1167 total_packets, total_bytes);
1168
e092be60 1169#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1170 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1171 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1172 /* Make sure that anybody stopping the queue after this
1173 * sees the new next_to_clean.
1174 */
1175 smp_mb();
729739b7
AD		 1176 if (__netif_subqueue_stopped(tx_ring->netdev,
1177 tx_ring->queue_index)
1178 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1179 netif_wake_subqueue(tx_ring->netdev,
1180 tx_ring->queue_index);
5b7da515 1181 ++tx_ring->tx_stats.restart_queue;
30eba97a 1182 }
e092be60 1183 }
9a799d71 1184
59224555 1185 return !!budget;
9a799d71
AK		 1186}
1187
5dd2d332 1188#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1189static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1190 struct ixgbe_ring *tx_ring,
33cf09c9 1191 int cpu)
bd0362dd 1192{
33cf09c9 1193 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1194 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1195 u16 reg_offset;
33cf09c9 1196
33cf09c9
AD		 1197 switch (hw->mac.type) {
1198 case ixgbe_mac_82598EB:
bdda1a61 1199 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1200 break;
1201 case ixgbe_mac_82599EB:
b93a2226 1202 case ixgbe_mac_X540:
bdda1a61
AD		 1203 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1204 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1205 break;
1206 default:
bdda1a61
AD		 1207 /* for unknown hardware do not write register */
1208 return;
bd0362dd 1209 }
bdda1a61
AD		 1210
1211 /*
1212 * We can enable relaxed ordering for reads, but not writes when
1213 * DCA is enabled. This is due to a known issue in some chipsets
1214 * which will cause the DCA tag to be cleared.
1215 */
1216 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1217 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1218 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1219
1220 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1221}
1222
bdda1a61
AD		 1223static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1224 struct ixgbe_ring *rx_ring,
33cf09c9 1225 int cpu)
bd0362dd 1226{
33cf09c9 1227 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1228 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1229 u8 reg_idx = rx_ring->reg_idx;
1230
33cf09c9
AD		 1231
1232 switch (hw->mac.type) {
33cf09c9 1233 case ixgbe_mac_82599EB:
b93a2226 1234 case ixgbe_mac_X540:
bdda1a61 1235 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1236 break;
1237 default:
1238 break;
1239 }
bdda1a61
AD		 1240
1241 /*
1242 * We can enable relaxed ordering for reads, but not writes when
1243 * DCA is enabled. This is due to a known issue in some chipsets
1244 * which will cause the DCA tag to be cleared.
1245 */
1246 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1247 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1248
1249 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1250}
1251
1252static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1253{
1254 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1255 struct ixgbe_ring *ring;
bd0362dd 1256 int cpu = get_cpu();
bd0362dd 1257
33cf09c9
AD		 1258 if (q_vector->cpu == cpu)
1259 goto out_no_update;
1260
a557928e 1261 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1262 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1263
a557928e 1264 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1265 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1266
1267 q_vector->cpu = cpu;
1268out_no_update:
bd0362dd
JC		 1269 put_cpu();
1270}
1271
1272static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1273{
1274 int i;
1275
1276 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1277 return;
1278
e35ec126
AD		 1279 /* always use CB2 mode, difference is masked in the CB driver */
1280 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1281
49c7ffbe 1282 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1283 adapter->q_vector[i]->cpu = -1;
1284 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1285 }
1286}
1287
1288static int __ixgbe_notify_dca(struct device *dev, void *data)
1289{
c60fbb00 1290 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1291 unsigned long event = *(unsigned long *)data;
1292
2a72c31e 1293 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1294 return 0;
1295
bd0362dd
JC		 1296 switch (event) {
1297 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1298 /* if we're already enabled, don't do it again */
1299 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1300 break;
652f093f 1301 if (dca_add_requester(dev) == 0) {
96b0e0f6 1302 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1303 ixgbe_setup_dca(adapter);
1304 break;
1305 }
1306 /* Fall Through since DCA is disabled. */
1307 case DCA_PROVIDER_REMOVE:
1308 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1309 dca_remove_requester(dev);
1310 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1311 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1312 }
1313 break;
1314 }
1315
652f093f 1316 return 0;
bd0362dd 1317}
67a74ee2 1318
bdda1a61 1319#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1320static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1321 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1322 struct sk_buff *skb)
1323{
8a0da21b 1324 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1325 skb_set_hash(skb,
1326 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1327 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1328}
1329
f800326d 1330#ifdef IXGBE_FCOE
ff886dfc
AD		 1331/**
1332 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1333 * @ring: structure containing ring specific data
ff886dfc
AD		 1334 * @rx_desc: advanced rx descriptor
1335 *
1336 * Returns : true if it is FCoE pkt
1337 */
57efd44c 1338static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1339 union ixgbe_adv_rx_desc *rx_desc)
1340{
1341 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1342
57efd44c 1343 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1344 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1345 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1346 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1347}
1348
f800326d 1349#endif /* IXGBE_FCOE */
e59bd25d
AV		 1350/**
1351 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1352 * @ring: structure containing ring specific data
1353 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1354 * @skb: skb currently being received and modified
1355 **/
8a0da21b 1356static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1357 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1358 struct sk_buff *skb)
9a799d71 1359{
8a0da21b 1360 skb_checksum_none_assert(skb);
9a799d71 1361
712744be 1362 /* Rx csum disabled */
8a0da21b 1363 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1364 return;
e59bd25d
AV		 1365
1366 /* if IP and error */
f56e0cb1
AD		 1367 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1368 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1369 ring->rx_stats.csum_err++;
9a799d71
AK		 1370 return;
1371 }
e59bd25d 1372
f56e0cb1 1373 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1374 return;
1375
f56e0cb1 1376 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1377 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1378
1379 /*
1380 * 82599 errata, UDP frames with a 0 checksum can be marked as
1381 * checksum errors.
1382 */
8a0da21b
AD		 1383 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1384 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1385 return;
1386
8a0da21b 1387 ring->rx_stats.csum_err++;
e59bd25d
AV		 1388 return;
1389 }
1390
9a799d71 1391 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1392 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1393}
1394
84ea2591 1395static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1396{
f56e0cb1 1397 rx_ring->next_to_use = val;
f800326d
AD		 1398
1399 /* update next to alloc since we have filled the ring */
1400 rx_ring->next_to_alloc = val;
e8e26350
PW		 1401 /*
1402 * Force memory writes to complete before letting h/w
1403 * know there are new descriptors to fetch. (Only
1404 * applicable for weak-ordered memory model archs,
1405 * such as IA-64).
1406 */
1407 wmb();
84227bcd 1408 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1409}
1410
f990b79b
AD		 1411static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1412 struct ixgbe_rx_buffer *bi)
1413{
1414 struct page *page = bi->page;
f800326d 1415 dma_addr_t dma = bi->dma;
f990b79b 1416
f800326d
AD		 1417 /* since we are recycling buffers we should seldom need to alloc */
1418 if (likely(dma))
f990b79b
AD		 1419 return true;
1420
f800326d
AD		 1421 /* alloc new page for storage */
1422 if (likely(!page)) {
0614002b
MG		 1423 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1424 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1425 if (unlikely(!page)) {
1426 rx_ring->rx_stats.alloc_rx_page_failed++;
1427 return false;
1428 }
f800326d 1429 bi->page = page;
f990b79b
AD		 1430 }
1431
f800326d
AD		 1432 /* map page for use */
1433 dma = dma_map_page(rx_ring->dev, page, 0,
1434 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1435
1436 /*
1437 * if mapping failed free memory back to system since
1438 * there isn't much point in holding memory we can't use
1439 */
1440 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1441 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1442 bi->page = NULL;
f990b79b 1443
f990b79b
AD		 1444 rx_ring->rx_stats.alloc_rx_page_failed++;
1445 return false;
1446 }
1447
f800326d 1448 bi->dma = dma;
afaa9459 1449 bi->page_offset = 0;
f800326d 1450
f990b79b
AD		 1451 return true;
1452}
1453
9a799d71 1454/**
f990b79b 1455 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1456 * @rx_ring: ring to place buffers on
1457 * @cleaned_count: number of buffers to replace
9a799d71 1458 **/
fc77dc3c 1459void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1460{
9a799d71 1461 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1462 struct ixgbe_rx_buffer *bi;
d5f398ed 1463 u16 i = rx_ring->next_to_use;
9a799d71 1464
f800326d
AD		 1465 /* nothing to do */
1466 if (!cleaned_count)
fc77dc3c
AD		 1467 return;
1468
e4f74028 1469 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1470 bi = &rx_ring->rx_buffer_info[i];
1471 i -= rx_ring->count;
9a799d71 1472
f800326d
AD		 1473 do {
1474 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1475 break;
d5f398ed 1476
f800326d
AD		 1477 /*
1478 * Refresh the desc even if buffer_addrs didn't change
1479 * because each write-back erases this info.
1480 */
1481 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1482
f990b79b
AD		 1483 rx_desc++;
1484 bi++;
9a799d71 1485 i++;
f990b79b 1486 if (unlikely(!i)) {
e4f74028 1487 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1488 bi = rx_ring->rx_buffer_info;
1489 i -= rx_ring->count;
1490 }
1491
1492 /* clear the hdr_addr for the next_to_use descriptor */
1493 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1494
1495 cleaned_count--;
1496 } while (cleaned_count);
7c6e0a43 1497
f990b79b
AD		 1498 i += rx_ring->count;
1499
f56e0cb1 1500 if (rx_ring->next_to_use != i)
84ea2591 1501 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1502}
1503
1d2024f6
AD		 1504/**
1505 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1506 * @data: pointer to the start of the headers
1507 * @max_len: total length of section to find headers in
1508 *
1509 * This function is meant to determine the length of headers that will
1510 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1511 * motivation of doing this is to only perform one pull for IPv4 TCP
1512 * packets so that we can do basic things like calculating the gso_size
1513 * based on the average data per packet.
1514 **/
1515static unsigned int ixgbe_get_headlen(unsigned char *data,
1516 unsigned int max_len)
1517{
1518 union {
1519 unsigned char *network;
1520 /* l2 headers */
1521 struct ethhdr *eth;
1522 struct vlan_hdr *vlan;
1523 /* l3 headers */
1524 struct iphdr *ipv4;
a048b40e 1525 struct ipv6hdr *ipv6;
1d2024f6
AD		 1526 } hdr;
1527 __be16 protocol;
1528 u8 nexthdr = 0; /* default to not TCP */
1529 u8 hlen;
1530
1531 /* this should never happen, but better safe than sorry */
1532 if (max_len < ETH_HLEN)
1533 return max_len;
1534
1535 /* initialize network frame pointer */
1536 hdr.network = data;
1537
1538 /* set first protocol and move network header forward */
1539 protocol = hdr.eth->h_proto;
1540 hdr.network += ETH_HLEN;
1541
1542 /* handle any vlan tag if present */
a1108ffd 1543 if (protocol == htons(ETH_P_8021Q)) {
1d2024f6
AD		 1544 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1545 return max_len;
1546
1547 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1548 hdr.network += VLAN_HLEN;
1549 }
1550
1551 /* handle L3 protocols */
a1108ffd 1552 if (protocol == htons(ETH_P_IP)) {
1d2024f6
AD		 1553 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1554 return max_len;
1555
1556 /* access ihl as a u8 to avoid unaligned access on ia64 */
1557 hlen = (hdr.network[0] & 0x0F) << 2;
1558
1559 /* verify hlen meets minimum size requirements */
1560 if (hlen < sizeof(struct iphdr))
1561 return hdr.network - data;
1562
ed83da12 1563 /* record next protocol if header is present */
20967f42 1564 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1565 nexthdr = hdr.ipv4->protocol;
a1108ffd 1566 } else if (protocol == htons(ETH_P_IPV6)) {
a048b40e
AD		 1567 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1568 return max_len;
1569
1570 /* record next protocol */
1571 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1572 hlen = sizeof(struct ipv6hdr);
f800326d 1573#ifdef IXGBE_FCOE
a1108ffd 1574 } else if (protocol == htons(ETH_P_FCOE)) {
1d2024f6
AD		 1575 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1576 return max_len;
ed83da12 1577 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1578#endif
1579 } else {
1580 return hdr.network - data;
1581 }
1582
ed83da12
AD		 1583 /* relocate pointer to start of L4 header */
1584 hdr.network += hlen;
1585
a048b40e 1586 /* finally sort out TCP/UDP */
1d2024f6
AD		 1587 if (nexthdr == IPPROTO_TCP) {
1588 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1589 return max_len;
1590
1591 /* access doff as a u8 to avoid unaligned access on ia64 */
1592 hlen = (hdr.network[12] & 0xF0) >> 2;
1593
1594 /* verify hlen meets minimum size requirements */
1595 if (hlen < sizeof(struct tcphdr))
1596 return hdr.network - data;
1597
1598 hdr.network += hlen;
a048b40e
AD		 1599 } else if (nexthdr == IPPROTO_UDP) {
1600 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1601 return max_len;
1602
1603 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1604 }
1605
1606 /*
1607 * If everything has gone correctly hdr.network should be the
1608 * data section of the packet and will be the end of the header.
1609 * If not then it probably represents the end of the last recognized
1610 * header.
1611 */
1612 if ((hdr.network - data) < max_len)
1613 return hdr.network - data;
1614 else
1615 return max_len;
1616}
1617
1d2024f6
AD		 1618static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1619 struct sk_buff *skb)
1620{
f800326d 1621 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1622
1623 /* set gso_size to avoid messing up TCP MSS */
1624 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1625 IXGBE_CB(skb)->append_cnt);
96be80ab 1626 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1627}
1628
1629static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1630 struct sk_buff *skb)
1631{
1632 /* if append_cnt is 0 then frame is not RSC */
1633 if (!IXGBE_CB(skb)->append_cnt)
1634 return;
1635
1636 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1637 rx_ring->rx_stats.rsc_flush++;
1638
1639 ixgbe_set_rsc_gso_size(rx_ring, skb);
1640
1641 /* gso_size is computed using append_cnt so always clear it last */
1642 IXGBE_CB(skb)->append_cnt = 0;
1643}
1644
8a0da21b
AD		 1645/**
1646 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1647 * @rx_ring: rx descriptor ring packet is being transacted on
1648 * @rx_desc: pointer to the EOP Rx descriptor
1649 * @skb: pointer to current skb being populated
f8212f97 1650 *
8a0da21b
AD		 1651 * This function checks the ring, descriptor, and packet information in
1652 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1653 * other fields within the skb.
f8212f97 1654 **/
8a0da21b
AD		 1655static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1656 union ixgbe_adv_rx_desc *rx_desc,
1657 struct sk_buff *skb)
f8212f97 1658{
43e95f11
JF		 1659 struct net_device *dev = rx_ring->netdev;
1660
8a0da21b
AD		 1661 ixgbe_update_rsc_stats(rx_ring, skb);
1662
1663 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1664
8a0da21b
AD		 1665 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1666
6cb562d6 1667 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1668
f646968f 1669 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1670 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1671 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1672 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1673 }
1674
8a0da21b 1675 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1676
43e95f11 1677 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1678}
1679
8a0da21b
AD		 1680static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1681 struct sk_buff *skb)
aa80175a 1682{
8a0da21b
AD		 1683 struct ixgbe_adapter *adapter = q_vector->adapter;
1684
b4640030 1685 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1686 netif_receive_skb(skb);
1687 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1688 napi_gro_receive(&q_vector->napi, skb);
1689 else
1690 netif_rx(skb);
aa80175a 1691}
43634e82 1692
f800326d
AD		 1693/**
1694 * ixgbe_is_non_eop - process handling of non-EOP buffers
1695 * @rx_ring: Rx ring being processed
1696 * @rx_desc: Rx descriptor for current buffer
1697 * @skb: Current socket buffer containing buffer in progress
1698 *
1699 * This function updates next to clean. If the buffer is an EOP buffer
1700 * this function exits returning false, otherwise it will place the
1701 * sk_buff in the next buffer to be chained and return true indicating
1702 * that this is in fact a non-EOP buffer.
1703 **/
1704static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1705 union ixgbe_adv_rx_desc *rx_desc,
1706 struct sk_buff *skb)
1707{
1708 u32 ntc = rx_ring->next_to_clean + 1;
1709
1710 /* fetch, update, and store next to clean */
1711 ntc = (ntc < rx_ring->count) ? ntc : 0;
1712 rx_ring->next_to_clean = ntc;
1713
1714 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1715
5a02cbd1
AD		 1716 /* update RSC append count if present */
1717 if (ring_is_rsc_enabled(rx_ring)) {
1718 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1719 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1720
1721 if (unlikely(rsc_enabled)) {
1722 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1723
1724 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1725 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1726
5a02cbd1
AD		 1727 /* update ntc based on RSC value */
1728 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1729 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1730 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1731 }
f800326d
AD		 1732 }
1733
5a02cbd1
AD		 1734 /* if we are the last buffer then there is nothing else to do */
1735 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1736 return false;
1737
f800326d
AD		 1738 /* place skb in next buffer to be received */
1739 rx_ring->rx_buffer_info[ntc].skb = skb;
1740 rx_ring->rx_stats.non_eop_descs++;
1741
1742 return true;
1743}
1744
19861ce2
AD		 1745/**
1746 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1747 * @rx_ring: rx descriptor ring packet is being transacted on
1748 * @skb: pointer to current skb being adjusted
1749 *
1750 * This function is an ixgbe specific version of __pskb_pull_tail. The
1751 * main difference between this version and the original function is that
1752 * this function can make several assumptions about the state of things
1753 * that allow for significant optimizations versus the standard function.
1754 * As a result we can do things like drop a frag and maintain an accurate
1755 * truesize for the skb.
1756 */
1757static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1758 struct sk_buff *skb)
1759{
1760 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1761 unsigned char *va;
1762 unsigned int pull_len;
1763
1764 /*
1765 * it is valid to use page_address instead of kmap since we are
1766 * working with pages allocated out of the lomem pool per
1767 * alloc_page(GFP_ATOMIC)
1768 */
1769 va = skb_frag_address(frag);
1770
1771 /*
1772 * we need the header to contain the greater of either ETH_HLEN or
1773 * 60 bytes if the skb->len is less than 60 for skb_pad.
1774 */
cf3fe7ac 1775 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1776
1777 /* align pull length to size of long to optimize memcpy performance */
1778 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1779
1780 /* update all of the pointers */
1781 skb_frag_size_sub(frag, pull_len);
1782 frag->page_offset += pull_len;
1783 skb->data_len -= pull_len;
1784 skb->tail += pull_len;
19861ce2
AD		 1785}
1786
42073d91
AD		 1787/**
1788 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1789 * @rx_ring: rx descriptor ring packet is being transacted on
1790 * @skb: pointer to current skb being updated
1791 *
1792 * This function provides a basic DMA sync up for the first fragment of an
1793 * skb. The reason for doing this is that the first fragment cannot be
1794 * unmapped until we have reached the end of packet descriptor for a buffer
1795 * chain.
1796 */
1797static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1798 struct sk_buff *skb)
1799{
1800 /* if the page was released unmap it, else just sync our portion */
1801 if (unlikely(IXGBE_CB(skb)->page_released)) {
1802 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1803 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1804 IXGBE_CB(skb)->page_released = false;
1805 } else {
1806 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1807
1808 dma_sync_single_range_for_cpu(rx_ring->dev,
1809 IXGBE_CB(skb)->dma,
1810 frag->page_offset,
1811 ixgbe_rx_bufsz(rx_ring),
1812 DMA_FROM_DEVICE);
1813 }
1814 IXGBE_CB(skb)->dma = 0;
1815}
1816
f800326d
AD		 1817/**
1818 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1819 * @rx_ring: rx descriptor ring packet is being transacted on
1820 * @rx_desc: pointer to the EOP Rx descriptor
1821 * @skb: pointer to current skb being fixed
1822 *
1823 * Check for corrupted packet headers caused by senders on the local L2
1824 * embedded NIC switch not setting up their Tx Descriptors right. These
1825 * should be very rare.
1826 *
1827 * Also address the case where we are pulling data in on pages only
1828 * and as such no data is present in the skb header.
1829 *
1830 * In addition if skb is not at least 60 bytes we need to pad it so that
1831 * it is large enough to qualify as a valid Ethernet frame.
1832 *
1833 * Returns true if an error was encountered and skb was freed.
1834 **/
1835static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1836 union ixgbe_adv_rx_desc *rx_desc,
1837 struct sk_buff *skb)
1838{
f800326d 1839 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1840
1841 /* verify that the packet does not have any known errors */
1842 if (unlikely(ixgbe_test_staterr(rx_desc,
1843 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1844 !(netdev->features & NETIF_F_RXALL))) {
1845 dev_kfree_skb_any(skb);
1846 return true;
1847 }
1848
19861ce2 1849 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1850 if (skb_is_nonlinear(skb))
1851 ixgbe_pull_tail(rx_ring, skb);
f800326d 1852
57efd44c
AD		 1853#ifdef IXGBE_FCOE
1854 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1855 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1856 return false;
1857
1858#endif
f800326d
AD		 1859 /* if skb_pad returns an error the skb was freed */
1860 if (unlikely(skb->len < 60)) {
1861 int pad_len = 60 - skb->len;
1862
1863 if (skb_pad(skb, pad_len))
1864 return true;
1865 __skb_put(skb, pad_len);
1866 }
1867
1868 return false;
1869}
1870
f800326d
AD		 1871/**
1872 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1873 * @rx_ring: rx descriptor ring to store buffers on
1874 * @old_buff: donor buffer to have page reused
1875 *
0549ae20 1876 * Synchronizes page for reuse by the adapter
f800326d
AD		 1877 **/
1878static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1879 struct ixgbe_rx_buffer *old_buff)
1880{
1881 struct ixgbe_rx_buffer *new_buff;
1882 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1883
1884 new_buff = &rx_ring->rx_buffer_info[nta];
1885
1886 /* update, and store next to alloc */
1887 nta++;
1888 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1889
1890 /* transfer page from old buffer to new buffer */
1891 new_buff->page = old_buff->page;
1892 new_buff->dma = old_buff->dma;
0549ae20 1893 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1894
1895 /* sync the buffer for use by the device */
1896 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1897 new_buff->page_offset,
1898 ixgbe_rx_bufsz(rx_ring),
f800326d 1899 DMA_FROM_DEVICE);
f800326d
AD		 1900}
1901
1902/**
1903 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1904 * @rx_ring: rx descriptor ring to transact packets on
1905 * @rx_buffer: buffer containing page to add
1906 * @rx_desc: descriptor containing length of buffer written by hardware
1907 * @skb: sk_buff to place the data into
1908 *
0549ae20
AD		 1909 * This function will add the data contained in rx_buffer->page to the skb.
1910 * This is done either through a direct copy if the data in the buffer is
1911 * less than the skb header size, otherwise it will just attach the page as
1912 * a frag to the skb.
1913 *
1914 * The function will then update the page offset if necessary and return
1915 * true if the buffer can be reused by the adapter.
f800326d 1916 **/
0549ae20 1917static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1918 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1919 union ixgbe_adv_rx_desc *rx_desc,
1920 struct sk_buff *skb)
f800326d 1921{
0549ae20
AD		 1922 struct page *page = rx_buffer->page;
1923 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1924#if (PAGE_SIZE < 8192)
0549ae20 1925 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1926#else
1927 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1928 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1929 ixgbe_rx_bufsz(rx_ring);
1930#endif
0549ae20 1931
cf3fe7ac
AD		 1932 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1933 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1934
1935 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1936
1937 /* we can reuse buffer as-is, just make sure it is local */
1938 if (likely(page_to_nid(page) == numa_node_id()))
1939 return true;
1940
1941 /* this page cannot be reused so discard it */
1942 put_page(page);
1943 return false;
1944 }
1945
0549ae20
AD		 1946 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1947 rx_buffer->page_offset, size, truesize);
1948
09816fbe
AD		 1949 /* avoid re-using remote pages */
1950 if (unlikely(page_to_nid(page) != numa_node_id()))
1951 return false;
1952
1953#if (PAGE_SIZE < 8192)
1954 /* if we are only owner of page we can reuse it */
1955 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1956 return false;
1957
1958 /* flip page offset to other buffer */
1959 rx_buffer->page_offset ^= truesize;
1960
09816fbe
AD		 1961 /*
1962 * since we are the only owner of the page and we need to
1963 * increment it, just set the value to 2 in order to avoid
1964 * an unecessary locked operation
1965 */
1966 atomic_set(&page->_count, 2);
1967#else
1968 /* move offset up to the next cache line */
1969 rx_buffer->page_offset += truesize;
1970
1971 if (rx_buffer->page_offset > last_offset)
1972 return false;
1973
0549ae20
AD		 1974 /* bump ref count on page before it is given to the stack */
1975 get_page(page);
09816fbe 1976#endif
0549ae20
AD		 1977
1978 return true;
f800326d
AD		 1979}
1980
18806c9e
AD		 1981static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1982 union ixgbe_adv_rx_desc *rx_desc)
1983{
1984 struct ixgbe_rx_buffer *rx_buffer;
1985 struct sk_buff *skb;
1986 struct page *page;
1987
1988 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1989 page = rx_buffer->page;
1990 prefetchw(page);
1991
1992 skb = rx_buffer->skb;
1993
1994 if (likely(!skb)) {
1995 void *page_addr = page_address(page) +
1996 rx_buffer->page_offset;
1997
1998 /* prefetch first cache line of first page */
1999 prefetch(page_addr);
2000#if L1_CACHE_BYTES < 128
2001 prefetch(page_addr + L1_CACHE_BYTES);
2002#endif
2003
2004 /* allocate a skb to store the frags */
2005 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
2006 IXGBE_RX_HDR_SIZE);
2007 if (unlikely(!skb)) {
2008 rx_ring->rx_stats.alloc_rx_buff_failed++;
2009 return NULL;
2010 }
2011
2012 /*
2013 * we will be copying header into skb->data in
2014 * pskb_may_pull so it is in our interest to prefetch
2015 * it now to avoid a possible cache miss
2016 */
2017 prefetchw(skb->data);
2018
2019 /*
2020 * Delay unmapping of the first packet. It carries the
2021 * header information, HW may still access the header
2022 * after the writeback. Only unmap it when EOP is
2023 * reached
2024 */
2025 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2026 goto dma_sync;
2027
2028 IXGBE_CB(skb)->dma = rx_buffer->dma;
2029 } else {
2030 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2031 ixgbe_dma_sync_frag(rx_ring, skb);
2032
2033dma_sync:
2034 /* we are reusing so sync this buffer for CPU use */
2035 dma_sync_single_range_for_cpu(rx_ring->dev,
2036 rx_buffer->dma,
2037 rx_buffer->page_offset,
2038 ixgbe_rx_bufsz(rx_ring),
2039 DMA_FROM_DEVICE);
2040 }
2041
2042 /* pull page into skb */
2043 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2044 /* hand second half of page back to the ring */
2045 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2046 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2047 /* the page has been released from the ring */
2048 IXGBE_CB(skb)->page_released = true;
2049 } else {
2050 /* we are not reusing the buffer so unmap it */
2051 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2052 ixgbe_rx_pg_size(rx_ring),
2053 DMA_FROM_DEVICE);
2054 }
2055
2056 /* clear contents of buffer_info */
2057 rx_buffer->skb = NULL;
2058 rx_buffer->dma = 0;
2059 rx_buffer->page = NULL;
2060
2061 return skb;
f800326d
AD		 2062}
2063
2064/**
2065 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2066 * @q_vector: structure containing interrupt and ring information
2067 * @rx_ring: rx descriptor ring to transact packets on
2068 * @budget: Total limit on number of packets to process
2069 *
2070 * This function provides a "bounce buffer" approach to Rx interrupt
2071 * processing. The advantage to this is that on systems that have
2072 * expensive overhead for IOMMU access this provides a means of avoiding
2073 * it by maintaining the mapping of the page to the syste.
2074 *
5a85e737 2075 * Returns amount of work completed
f800326d 2076 **/
5a85e737 2077static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2078 struct ixgbe_ring *rx_ring,
f4de00ed 2079 const int budget)
9a799d71 2080{
d2f4fbe2 2081 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2082#ifdef IXGBE_FCOE
f800326d 2083 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2084 int ddp_bytes;
2085 unsigned int mss = 0;
3d8fd385 2086#endif /* IXGBE_FCOE */
f800326d 2087 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2088
fdabfc8a 2089 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2090 union ixgbe_adv_rx_desc *rx_desc;
2091 struct sk_buff *skb;
f800326d
AD		 2092
2093 /* return some buffers to hardware, one at a time is too slow */
2094 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2095 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2096 cleaned_count = 0;
2097 }
2098
18806c9e 2099 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2100
2101 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2102 break;
9a799d71 2103
f800326d
AD		 2104 /*
2105 * This memory barrier is needed to keep us from reading
2106 * any other fields out of the rx_desc until we know the
2107 * RXD_STAT_DD bit is set
2108 */
2109 rmb();
9a799d71 2110
18806c9e
AD		 2111 /* retrieve a buffer from the ring */
2112 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2113
18806c9e
AD		 2114 /* exit if we failed to retrieve a buffer */
2115 if (!skb)
2116 break;
9a799d71 2117
9a799d71 2118 cleaned_count++;
f8212f97 2119
f800326d
AD		 2120 /* place incomplete frames back on ring for completion */
2121 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2122 continue;
c267fc16 2123
f800326d
AD		 2124 /* verify the packet layout is correct */
2125 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2126 continue;
9a799d71 2127
d2f4fbe2
AV		 2128 /* probably a little skewed due to removing CRC */
2129 total_rx_bytes += skb->len;
d2f4fbe2 2130
8a0da21b
AD		 2131 /* populate checksum, timestamp, VLAN, and protocol */
2132 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2133
332d4a7d
YZ		 2134#ifdef IXGBE_FCOE
2135 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2136 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2137 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2138 /* include DDPed FCoE data */
2139 if (ddp_bytes > 0) {
2140 if (!mss) {
2141 mss = rx_ring->netdev->mtu -
2142 sizeof(struct fcoe_hdr) -
2143 sizeof(struct fc_frame_header) -
2144 sizeof(struct fcoe_crc_eof);
2145 if (mss > 512)
2146 mss &= ~511;
2147 }
2148 total_rx_bytes += ddp_bytes;
2149 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2150 mss);
2151 }
63d635b2
AD		 2152 if (!ddp_bytes) {
2153 dev_kfree_skb_any(skb);
f800326d 2154 continue;
63d635b2 2155 }
3d8fd385 2156 }
f800326d 2157
332d4a7d 2158#endif /* IXGBE_FCOE */
8b80cda5 2159 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2160 ixgbe_rx_skb(q_vector, skb);
9a799d71 2161
f800326d 2162 /* update budget accounting */
f4de00ed 2163 total_rx_packets++;
fdabfc8a 2164 }
9a799d71 2165
c267fc16
AD		 2166 u64_stats_update_begin(&rx_ring->syncp);
2167 rx_ring->stats.packets += total_rx_packets;
2168 rx_ring->stats.bytes += total_rx_bytes;
2169 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2170 q_vector->rx.total_packets += total_rx_packets;
2171 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2172
f800326d
AD		 2173 if (cleaned_count)
2174 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2175
5a85e737 2176 return total_rx_packets;
9a799d71
AK		 2177}
2178
e0d1095a 2179#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2180/* must be called with local_bh_disable()d */
2181static int ixgbe_low_latency_recv(struct napi_struct *napi)
2182{
2183 struct ixgbe_q_vector *q_vector =
2184 container_of(napi, struct ixgbe_q_vector, napi);
2185 struct ixgbe_adapter *adapter = q_vector->adapter;
2186 struct ixgbe_ring *ring;
2187 int found = 0;
2188
2189 if (test_bit(__IXGBE_DOWN, &adapter->state))
2190 return LL_FLUSH_FAILED;
2191
2192 if (!ixgbe_qv_lock_poll(q_vector))
2193 return LL_FLUSH_BUSY;
2194
2195 ixgbe_for_each_ring(ring, q_vector->rx) {
2196 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2197#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2198 if (found)
2199 ring->stats.cleaned += found;
2200 else
2201 ring->stats.misses++;
2202#endif
5a85e737
ET		 2203 if (found)
2204 break;
2205 }
2206
2207 ixgbe_qv_unlock_poll(q_vector);
2208
2209 return found;
2210}
e0d1095a 2211#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2212
9a799d71
AK		 2213/**
2214 * ixgbe_configure_msix - Configure MSI-X hardware
2215 * @adapter: board private structure
2216 *
2217 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2218 * interrupts.
2219 **/
2220static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2221{
021230d4 2222 struct ixgbe_q_vector *q_vector;
49c7ffbe 2223 int v_idx;
021230d4 2224 u32 mask;
9a799d71 2225
8e34d1aa
AD		 2226 /* Populate MSIX to EITR Select */
2227 if (adapter->num_vfs > 32) {
2228 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2230 }
2231
4df10466
JB		 2232 /*
2233 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2234 * corresponding register.
2235 */
49c7ffbe 2236 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2237 struct ixgbe_ring *ring;
7a921c93 2238 q_vector = adapter->q_vector[v_idx];
021230d4 2239
a557928e 2240 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2241 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2242
a557928e 2243 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2244 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2245
fe49f04a 2246 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2247 }
2248
bd508178
AD		 2249 switch (adapter->hw.mac.type) {
2250 case ixgbe_mac_82598EB:
e8e26350 2251 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2252 v_idx);
bd508178
AD		 2253 break;
2254 case ixgbe_mac_82599EB:
b93a2226 2255 case ixgbe_mac_X540:
e8e26350 2256 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2257 break;
bd508178
AD		 2258 default:
2259 break;
2260 }
021230d4
AV		 2261 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2262
41fb9248 2263 /* set up to autoclear timer, and the vectors */
021230d4 2264 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2265 mask &= ~(IXGBE_EIMS_OTHER |
2266 IXGBE_EIMS_MAILBOX |
2267 IXGBE_EIMS_LSC);
2268
021230d4 2269 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2270}
2271
f494e8fa
AV		 2272enum latency_range {
2273 lowest_latency = 0,
2274 low_latency = 1,
2275 bulk_latency = 2,
2276 latency_invalid = 255
2277};
2278
2279/**
2280 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2281 * @q_vector: structure containing interrupt and ring information
2282 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2283 *
2284 * Stores a new ITR value based on packets and byte
2285 * counts during the last interrupt. The advantage of per interrupt
2286 * computation is faster updates and more accurate ITR for the current
2287 * traffic pattern. Constants in this function were computed
2288 * based on theoretical maximum wire speed and thresholds were set based
2289 * on testing data as well as attempting to minimize response time
2290 * while increasing bulk throughput.
2291 * this functionality is controlled by the InterruptThrottleRate module
2292 * parameter (see ixgbe_param.c)
2293 **/
bd198058
AD		 2294static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2295 struct ixgbe_ring_container *ring_container)
f494e8fa 2296{
bd198058
AD		 2297 int bytes = ring_container->total_bytes;
2298 int packets = ring_container->total_packets;
2299 u32 timepassed_us;
621bd70e 2300 u64 bytes_perint;
bd198058 2301 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2302
2303 if (packets == 0)
bd198058 2304 return;
f494e8fa
AV		 2305
2306 /* simple throttlerate management
621bd70e
AD		 2307 * 0-10MB/s lowest (100000 ints/s)
2308 * 10-20MB/s low (20000 ints/s)
2309 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2310 */
2311 /* what was last interrupt timeslice? */
d5bf4f67 2312 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2313 if (timepassed_us == 0)
2314 return;
2315
f494e8fa
AV		 2316 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2317
2318 switch (itr_setting) {
2319 case lowest_latency:
621bd70e 2320 if (bytes_perint > 10)
bd198058 2321 itr_setting = low_latency;
f494e8fa
AV		 2322 break;
2323 case low_latency:
621bd70e 2324 if (bytes_perint > 20)
bd198058 2325 itr_setting = bulk_latency;
621bd70e 2326 else if (bytes_perint <= 10)
bd198058 2327 itr_setting = lowest_latency;
f494e8fa
AV		 2328 break;
2329 case bulk_latency:
621bd70e 2330 if (bytes_perint <= 20)
bd198058 2331 itr_setting = low_latency;
f494e8fa
AV		 2332 break;
2333 }
2334
bd198058
AD		 2335 /* clear work counters since we have the values we need */
2336 ring_container->total_bytes = 0;
2337 ring_container->total_packets = 0;
2338
2339 /* write updated itr to ring container */
2340 ring_container->itr = itr_setting;
f494e8fa
AV		 2341}
2342
509ee935
JB		 2343/**
2344 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2345 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2346 *
2347 * This function is made to be called by ethtool and by the driver
2348 * when it needs to update EITR registers at runtime. Hardware
2349 * specific quirks/differences are taken care of here.
2350 */
fe49f04a 2351void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2352{
fe49f04a 2353 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2354 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2355 int v_idx = q_vector->v_idx;
5d967eb7 2356 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2357
bd508178
AD		 2358 switch (adapter->hw.mac.type) {
2359 case ixgbe_mac_82598EB:
509ee935
JB		 2360 /* must write high and low 16 bits to reset counter */
2361 itr_reg |= (itr_reg << 16);
bd508178
AD		 2362 break;
2363 case ixgbe_mac_82599EB:
b93a2226 2364 case ixgbe_mac_X540:
509ee935
JB		 2365 /*
2366 * set the WDIS bit to not clear the timer bits and cause an
2367 * immediate assertion of the interrupt
2368 */
2369 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2370 break;
2371 default:
2372 break;
509ee935
JB		 2373 }
2374 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2375}
2376
bd198058 2377static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2378{
d5bf4f67 2379 u32 new_itr = q_vector->itr;
bd198058 2380 u8 current_itr;
f494e8fa 2381
bd198058
AD		 2382 ixgbe_update_itr(q_vector, &q_vector->tx);
2383 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2384
08c8833b 2385 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2386
2387 switch (current_itr) {
2388 /* counts and packets in update_itr are dependent on these numbers */
2389 case lowest_latency:
d5bf4f67 2390 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2391 break;
2392 case low_latency:
d5bf4f67 2393 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2394 break;
2395 case bulk_latency:
d5bf4f67 2396 new_itr = IXGBE_8K_ITR;
f494e8fa 2397 break;
bd198058
AD		 2398 default:
2399 break;
f494e8fa
AV		 2400 }
2401
d5bf4f67 2402 if (new_itr != q_vector->itr) {
fe49f04a 2403 /* do an exponential smoothing */
d5bf4f67
ET		 2404 new_itr = (10 * new_itr * q_vector->itr) /
2405 ((9 * new_itr) + q_vector->itr);
509ee935 2406
bd198058 2407 /* save the algorithm value here */
5d967eb7 2408 q_vector->itr = new_itr;
fe49f04a
AD		 2409
2410 ixgbe_write_eitr(q_vector);
f494e8fa 2411 }
f494e8fa
AV		 2412}
2413
119fc60a 2414/**
de88eeeb 2415 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2416 * @adapter: pointer to adapter
119fc60a 2417 **/
f0f9778d 2418static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2419{
119fc60a
MC		 2420 struct ixgbe_hw *hw = &adapter->hw;
2421 u32 eicr = adapter->interrupt_event;
2422
f0f9778d 2423 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2424 return;
2425
f0f9778d
AD		 2426 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2427 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2428 return;
2429
2430 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2431
7ca647bd 2432 switch (hw->device_id) {
f0f9778d
AD		 2433 case IXGBE_DEV_ID_82599_T3_LOM:
2434 /*
2435 * Since the warning interrupt is for both ports
2436 * we don't have to check if:
2437 * - This interrupt wasn't for our port.
2438 * - We may have missed the interrupt so always have to
2439 * check if we got a LSC
2440 */
2441 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2442 !(eicr & IXGBE_EICR_LSC))
2443 return;
2444
2445 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2446 u32 speed;
f0f9778d 2447 bool link_up = false;
7ca647bd 2448
3d292265 2449 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2450
f0f9778d
AD		 2451 if (link_up)
2452 return;
2453 }
2454
2455 /* Check if this is not due to overtemp */
2456 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2457 return;
2458
2459 break;
7ca647bd
JP		 2460 default:
2461 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2462 return;
7ca647bd 2463 break;
119fc60a 2464 }
7ca647bd
JP		 2465 e_crit(drv,
2466 "Network adapter has been stopped because it has over heated. "
2467 "Restart the computer. If the problem persists, "
2468 "power off the system and replace the adapter\n");
f0f9778d
AD		 2469
2470 adapter->interrupt_event = 0;
119fc60a
MC		 2471}
2472
0befdb3e
JB		 2473static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2474{
2475 struct ixgbe_hw *hw = &adapter->hw;
2476
2477 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2478 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2479 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2480 /* write to clear the interrupt */
2481 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2482 }
2483}
cf8280ee 2484
4f51bf70
JK		 2485static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2486{
2487 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2488 return;
2489
2490 switch (adapter->hw.mac.type) {
2491 case ixgbe_mac_82599EB:
2492 /*
2493 * Need to check link state so complete overtemp check
2494 * on service task
2495 */
2496 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2497 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2498 adapter->interrupt_event = eicr;
2499 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2500 ixgbe_service_event_schedule(adapter);
2501 return;
2502 }
2503 return;
2504 case ixgbe_mac_X540:
2505 if (!(eicr & IXGBE_EICR_TS))
2506 return;
2507 break;
2508 default:
2509 return;
2510 }
2511
2512 e_crit(drv,
2513 "Network adapter has been stopped because it has over heated. "
2514 "Restart the computer. If the problem persists, "
2515 "power off the system and replace the adapter\n");
2516}
2517
e8e26350
PW		 2518static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2519{
2520 struct ixgbe_hw *hw = &adapter->hw;
2521
73c4b7cd
AD		 2522 if (eicr & IXGBE_EICR_GPI_SDP2) {
2523 /* Clear the interrupt */
2524 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2525 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2526 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2527 ixgbe_service_event_schedule(adapter);
2528 }
73c4b7cd
AD		 2529 }
2530
e8e26350
PW		 2531 if (eicr & IXGBE_EICR_GPI_SDP1) {
2532 /* Clear the interrupt */
2533 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2534 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2535 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2536 ixgbe_service_event_schedule(adapter);
2537 }
e8e26350
PW		 2538 }
2539}
2540
cf8280ee
JB		 2541static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2542{
2543 struct ixgbe_hw *hw = &adapter->hw;
2544
2545 adapter->lsc_int++;
2546 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2547 adapter->link_check_timeout = jiffies;
2548 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2549 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2550 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2551 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2552 }
2553}
2554
fe49f04a
AD		 2555static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2556 u64 qmask)
2557{
2558 u32 mask;
bd508178 2559 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2560
bd508178
AD		 2561 switch (hw->mac.type) {
2562 case ixgbe_mac_82598EB:
fe49f04a 2563 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2564 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2565 break;
2566 case ixgbe_mac_82599EB:
b93a2226 2567 case ixgbe_mac_X540:
fe49f04a 2568 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2571 mask = (qmask >> 32);
bd508178
AD		 2572 if (mask)
2573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2574 break;
2575 default:
2576 break;
fe49f04a
AD		 2577 }
2578 /* skip the flush */
2579}
2580
2581static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2582 u64 qmask)
fe49f04a
AD		 2583{
2584 u32 mask;
bd508178 2585 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2586
bd508178
AD		 2587 switch (hw->mac.type) {
2588 case ixgbe_mac_82598EB:
fe49f04a 2589 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2591 break;
2592 case ixgbe_mac_82599EB:
b93a2226 2593 case ixgbe_mac_X540:
fe49f04a 2594 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2595 if (mask)
2596 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2597 mask = (qmask >> 32);
bd508178
AD		 2598 if (mask)
2599 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2600 break;
2601 default:
2602 break;
fe49f04a
AD		 2603 }
2604 /* skip the flush */
2605}
2606
021230d4 2607/**
2c4af694
AD		 2608 * ixgbe_irq_enable - Enable default interrupt generation settings
2609 * @adapter: board private structure
021230d4 2610 **/
2c4af694
AD		 2611static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2612 bool flush)
9a799d71 2613{
2c4af694 2614 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2615
2c4af694
AD		 2616 /* don't reenable LSC while waiting for link */
2617 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2618 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2619
2c4af694 2620 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2621 switch (adapter->hw.mac.type) {
2622 case ixgbe_mac_82599EB:
2623 mask |= IXGBE_EIMS_GPI_SDP0;
2624 break;
2625 case ixgbe_mac_X540:
2626 mask |= IXGBE_EIMS_TS;
2627 break;
2628 default:
2629 break;
2630 }
2c4af694
AD		 2631 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2632 mask |= IXGBE_EIMS_GPI_SDP1;
2633 switch (adapter->hw.mac.type) {
2634 case ixgbe_mac_82599EB:
2c4af694
AD		 2635 mask |= IXGBE_EIMS_GPI_SDP1;
2636 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2637 case ixgbe_mac_X540:
2638 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2639 mask |= IXGBE_EIMS_MAILBOX;
2640 break;
2641 default:
2642 break;
9a799d71 2643 }
db0677fa 2644
db0677fa
JK		 2645 if (adapter->hw.mac.type == ixgbe_mac_X540)
2646 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2647
2c4af694
AD		 2648 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2649 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2650 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2651
2c4af694
AD		 2652 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2653 if (queues)
2654 ixgbe_irq_enable_queues(adapter, ~0);
2655 if (flush)
2656 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2657}
2658
2c4af694 2659static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2660{
a65151ba 2661 struct ixgbe_adapter *adapter = data;
9a799d71 2662 struct ixgbe_hw *hw = &adapter->hw;
54037505 2663 u32 eicr;
91281fd3 2664
54037505
DS		 2665 /*
2666 * Workaround for Silicon errata. Use clear-by-write instead
2667 * of clear-by-read. Reading with EICS will return the
2668 * interrupt causes without clearing, which later be done
2669 * with the write to EICR.
2670 */
2671 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2672
2673 /* The lower 16bits of the EICR register are for the queue interrupts
2674 * which should be masked here in order to not accidently clear them if
2675 * the bits are high when ixgbe_msix_other is called. There is a race
2676 * condition otherwise which results in possible performance loss
2677 * especially if the ixgbe_msix_other interrupt is triggering
2678 * consistently (as it would when PPS is turned on for the X540 device)
2679 */
2680 eicr &= 0xFFFF0000;
2681
54037505 2682 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2683
cf8280ee
JB		 2684 if (eicr & IXGBE_EICR_LSC)
2685 ixgbe_check_lsc(adapter);
f0848276 2686
1cdd1ec8
GR		 2687 if (eicr & IXGBE_EICR_MAILBOX)
2688 ixgbe_msg_task(adapter);
efe3d3c8 2689
bd508178
AD		 2690 switch (hw->mac.type) {
2691 case ixgbe_mac_82599EB:
b93a2226 2692 case ixgbe_mac_X540:
d773ce2d
DS		 2693 if (eicr & IXGBE_EICR_ECC) {
2694 e_info(link, "Received ECC Err, initiating reset\n");
2695 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2696 ixgbe_service_event_schedule(adapter);
2697 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2698 }
c4cf55e5
PWJ		 2699 /* Handle Flow Director Full threshold interrupt */
2700 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2701 int reinit_count = 0;
c4cf55e5 2702 int i;
c4cf55e5 2703 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2704 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2705 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2706 &ring->state))
2707 reinit_count++;
2708 }
2709 if (reinit_count) {
2710 /* no more flow director interrupts until after init */
2711 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2712 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2713 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2714 }
2715 }
f0f9778d 2716 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2717 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2718 break;
2719 default:
2720 break;
c4cf55e5 2721 }
f0848276 2722
bd508178 2723 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2724
db0677fa
JK		 2725 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2726 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2727
7086400d 2728 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2729 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2730 ixgbe_irq_enable(adapter, false, false);
f0848276 2731
9a799d71 2732 return IRQ_HANDLED;
f0848276 2733}
91281fd3 2734
4ff7fb12 2735static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2736{
021230d4 2737 struct ixgbe_q_vector *q_vector = data;
91281fd3 2738
9b471446 2739 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2740
4ff7fb12
AD		 2741 if (q_vector->rx.ring || q_vector->tx.ring)
2742 napi_schedule(&q_vector->napi);
91281fd3 2743
9a799d71 2744 return IRQ_HANDLED;
91281fd3
AD		 2745}
2746
eb01b975
AD		 2747/**
2748 * ixgbe_poll - NAPI Rx polling callback
2749 * @napi: structure for representing this polling device
2750 * @budget: how many packets driver is allowed to clean
2751 *
2752 * This function is used for legacy and MSI, NAPI mode
2753 **/
8af3c33f 2754int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2755{
2756 struct ixgbe_q_vector *q_vector =
2757 container_of(napi, struct ixgbe_q_vector, napi);
2758 struct ixgbe_adapter *adapter = q_vector->adapter;
2759 struct ixgbe_ring *ring;
2760 int per_ring_budget;
2761 bool clean_complete = true;
2762
2763#ifdef CONFIG_IXGBE_DCA
2764 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2765 ixgbe_update_dca(q_vector);
2766#endif
2767
2768 ixgbe_for_each_ring(ring, q_vector->tx)
2769 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2770
5a85e737
ET		 2771 if (!ixgbe_qv_lock_napi(q_vector))
2772 return budget;
2773
eb01b975
AD		 2774 /* attempt to distribute budget to each queue fairly, but don't allow
2775 * the budget to go below 1 because we'll exit polling */
2776 if (q_vector->rx.count > 1)
2777 per_ring_budget = max(budget/q_vector->rx.count, 1);
2778 else
2779 per_ring_budget = budget;
2780
2781 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2782 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2783 per_ring_budget) < per_ring_budget);
eb01b975 2784
5a85e737 2785 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2786 /* If all work not completed, return budget and keep polling */
2787 if (!clean_complete)
2788 return budget;
2789
2790 /* all work done, exit the polling mode */
2791 napi_complete(napi);
2792 if (adapter->rx_itr_setting & 1)
2793 ixgbe_set_itr(q_vector);
2794 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2795 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2796
2797 return 0;
2798}
2799
021230d4
AV		 2800/**
2801 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2802 * @adapter: board private structure
2803 *
2804 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2805 * interrupts from the kernel.
2806 **/
2807static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2808{
2809 struct net_device *netdev = adapter->netdev;
207867f5 2810 int vector, err;
e8e9f696 2811 int ri = 0, ti = 0;
021230d4 2812
49c7ffbe 2813 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2814 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2815 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2816
4ff7fb12 2817 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2818 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2819 "%s-%s-%d", netdev->name, "TxRx", ri++);
2820 ti++;
2821 } else if (q_vector->rx.ring) {
9fe93afd 2822 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2823 "%s-%s-%d", netdev->name, "rx", ri++);
2824 } else if (q_vector->tx.ring) {
9fe93afd 2825 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2826 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2827 } else {
2828 /* skip this unused q_vector */
2829 continue;
32aa77a4 2830 }
207867f5
AD		 2831 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2832 q_vector->name, q_vector);
9a799d71 2833 if (err) {
396e799c 2834 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2835 "Error: %d\n", err);
021230d4 2836 goto free_queue_irqs;
9a799d71 2837 }
207867f5
AD		 2838 /* If Flow Director is enabled, set interrupt affinity */
2839 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2840 /* assign the mask for this irq */
2841 irq_set_affinity_hint(entry->vector,
de88eeeb 2842 &q_vector->affinity_mask);
207867f5 2843 }
9a799d71
AK		 2844 }
2845
021230d4 2846 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2847 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2848 if (err) {
de88eeeb 2849 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2850 goto free_queue_irqs;
9a799d71
AK		 2851 }
2852
9a799d71
AK		 2853 return 0;
2854
021230d4 2855free_queue_irqs:
207867f5
AD		 2856 while (vector) {
2857 vector--;
2858 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2859 NULL);
2860 free_irq(adapter->msix_entries[vector].vector,
2861 adapter->q_vector[vector]);
2862 }
021230d4
AV		 2863 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2864 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2865 kfree(adapter->msix_entries);
2866 adapter->msix_entries = NULL;
9a799d71
AK		 2867 return err;
2868}
2869
2870/**
021230d4 2871 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2872 * @irq: interrupt number
2873 * @data: pointer to a network interface device structure
9a799d71
AK		 2874 **/
2875static irqreturn_t ixgbe_intr(int irq, void *data)
2876{
a65151ba 2877 struct ixgbe_adapter *adapter = data;
9a799d71 2878 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2879 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2880 u32 eicr;
2881
54037505 2882 /*
24ddd967 2883 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2884 * before the read of EICR.
2885 */
2886 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2887
021230d4 2888 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2889 * therefore no explicit interrupt disable is necessary */
021230d4 2890 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2891 if (!eicr) {
6af3b9eb
ET		 2892 /*
2893 * shared interrupt alert!
f47cf66e 2894 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2895 * have disabled interrupts due to EIAM
2896 * finish the workaround of silicon errata on 82598. Unmask
2897 * the interrupt that we masked before the EICR read.
2898 */
2899 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2900 ixgbe_irq_enable(adapter, true, true);
9a799d71 2901 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2902 }
9a799d71 2903
cf8280ee
JB		 2904 if (eicr & IXGBE_EICR_LSC)
2905 ixgbe_check_lsc(adapter);
021230d4 2906
bd508178
AD		 2907 switch (hw->mac.type) {
2908 case ixgbe_mac_82599EB:
e8e26350 2909 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2910 /* Fall through */
2911 case ixgbe_mac_X540:
d773ce2d
DS		 2912 if (eicr & IXGBE_EICR_ECC) {
2913 e_info(link, "Received ECC Err, initiating reset\n");
2914 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2915 ixgbe_service_event_schedule(adapter);
2916 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2917 }
4f51bf70 2918 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2919 break;
2920 default:
2921 break;
2922 }
e8e26350 2923
0befdb3e 2924 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2925 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2926 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2927
b9f6ed2b
AD		 2928 /* would disable interrupts here but EIAM disabled it */
2929 napi_schedule(&q_vector->napi);
9a799d71 2930
6af3b9eb
ET		 2931 /*
2932 * re-enable link(maybe) and non-queue interrupts, no flush.
2933 * ixgbe_poll will re-enable the queue interrupts
2934 */
6af3b9eb
ET		 2935 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2936 ixgbe_irq_enable(adapter, false, false);
2937
9a799d71
AK		 2938 return IRQ_HANDLED;
2939}
2940
2941/**
2942 * ixgbe_request_irq - initialize interrupts
2943 * @adapter: board private structure
2944 *
2945 * Attempts to configure interrupts using the best available
2946 * capabilities of the hardware and kernel.
2947 **/
021230d4 2948static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2949{
2950 struct net_device *netdev = adapter->netdev;
021230d4 2951 int err;
9a799d71 2952
4cc6df29 2953 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2954 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2955 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2956 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2957 netdev->name, adapter);
4cc6df29 2958 else
a0607fd3 2959 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2960 netdev->name, adapter);
9a799d71 2961
de88eeeb 2962 if (err)
396e799c 2963 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2964
9a799d71
AK		 2965 return err;
2966}
2967
2968static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2969{
49c7ffbe 2970 int vector;
9a799d71 2971
49c7ffbe
AD		 2972 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2973 free_irq(adapter->pdev->irq, adapter);
2974 return;
2975 }
4cc6df29 2976
49c7ffbe
AD		 2977 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2978 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2979 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2980
49c7ffbe
AD		 2981 /* free only the irqs that were actually requested */
2982 if (!q_vector->rx.ring && !q_vector->tx.ring)
2983 continue;
207867f5 2984
49c7ffbe
AD		 2985 /* clear the affinity_mask in the IRQ descriptor */
2986 irq_set_affinity_hint(entry->vector, NULL);
2987
2988 free_irq(entry->vector, q_vector);
9a799d71 2989 }
49c7ffbe
AD		 2990
2991 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2992}
2993
22d5a71b
JB		 2994/**
2995 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2996 * @adapter: board private structure
2997 **/
2998static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2999{
bd508178
AD		 3000 switch (adapter->hw.mac.type) {
3001 case ixgbe_mac_82598EB:
835462fc 3002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3003 break;
3004 case ixgbe_mac_82599EB:
b93a2226 3005 case ixgbe_mac_X540:
835462fc
NS		 3006 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3007 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3008 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3009 break;
3010 default:
3011 break;
22d5a71b
JB		 3012 }
3013 IXGBE_WRITE_FLUSH(&adapter->hw);
3014 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3015 int vector;
3016
3017 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3018 synchronize_irq(adapter->msix_entries[vector].vector);
3019
3020 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3021 } else {
3022 synchronize_irq(adapter->pdev->irq);
3023 }
3024}
3025
9a799d71
AK		 3026/**
3027 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3028 *
3029 **/
3030static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3031{
d5bf4f67 3032 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3033
d5bf4f67 3034 ixgbe_write_eitr(q_vector);
9a799d71 3035
e8e26350
PW		 3036 ixgbe_set_ivar(adapter, 0, 0, 0);
3037 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3038
396e799c 3039 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3040}
3041
43e69bf0
AD		 3042/**
3043 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3044 * @adapter: board private structure
3045 * @ring: structure containing ring specific data
3046 *
3047 * Configure the Tx descriptor ring after a reset.
3048 **/
84418e3b
AD		 3049void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3050 struct ixgbe_ring *ring)
43e69bf0
AD		 3051{
3052 struct ixgbe_hw *hw = &adapter->hw;
3053 u64 tdba = ring->dma;
2f1860b8 3054 int wait_loop = 10;
b88c6de2 3055 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3056 u8 reg_idx = ring->reg_idx;
43e69bf0 3057
2f1860b8 3058 /* disable queue to avoid issues while updating state */
b88c6de2 3059 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3060 IXGBE_WRITE_FLUSH(hw);
3061
43e69bf0 3062 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3063 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3064 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3065 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3066 ring->count * sizeof(union ixgbe_adv_tx_desc));
3067 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3068 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3069 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3070
b88c6de2
AD		 3071 /*
3072 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3073 * higher than 1 when:
3074 * - ITR is 0 as it could cause false TX hangs
3075 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3076 *
3077 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3078 * to or less than the number of on chip descriptors, which is
3079 * currently 40.
3080 */
67da097e
ET		 3081#if IS_ENABLED(CONFIG_BQL)
3082 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3083#else
e954b374 3084 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3085#endif
b88c6de2
AD		 3086 txdctl |= (1 << 16); /* WTHRESH = 1 */
3087 else
3088 txdctl |= (8 << 16); /* WTHRESH = 8 */
3089
e954b374
AD		 3090 /*
3091 * Setting PTHRESH to 32 both improves performance
3092 * and avoids a TX hang with DFP enabled
3093 */
b88c6de2
AD		 3094 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3095 32; /* PTHRESH = 32 */
2f1860b8
AD		 3096
3097 /* reinitialize flowdirector state */
39cb681b 3098 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3099 ring->atr_sample_rate = adapter->atr_sample_rate;
3100 ring->atr_count = 0;
3101 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3102 } else {
3103 ring->atr_sample_rate = 0;
3104 }
2f1860b8 3105
fd786b7b
AD		 3106 /* initialize XPS */
3107 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3108 struct ixgbe_q_vector *q_vector = ring->q_vector;
3109
3110 if (q_vector)
2a47fa45 3111 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3112 &q_vector->affinity_mask,
3113 ring->queue_index);
3114 }
3115
c84d324c
JF		 3116 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3117
2f1860b8 3118 /* enable queue */
2f1860b8
AD		 3119 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3120
3121 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3122 if (hw->mac.type == ixgbe_mac_82598EB &&
3123 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3124 return;
3125
3126 /* poll to verify queue is enabled */
3127 do {
032b4325 3128 usleep_range(1000, 2000);
2f1860b8
AD		 3129 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3130 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3131 if (!wait_loop)
3132 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3133}
3134
120ff942
AD		 3135static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3136{
3137 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3138 u32 rttdcs, mtqc;
8b1c0b24 3139 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3140
3141 if (hw->mac.type == ixgbe_mac_82598EB)
3142 return;
3143
3144 /* disable the arbiter while setting MTQC */
3145 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3146 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3147 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3148
3149 /* set transmit pool layout */
671c0adb
AD		 3150 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3151 mtqc = IXGBE_MTQC_VT_ENA;
3152 if (tcs > 4)
3153 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3154 else if (tcs > 1)
3155 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3156 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3157 mtqc |= IXGBE_MTQC_32VF;
3158 else
3159 mtqc |= IXGBE_MTQC_64VF;
3160 } else {
3161 if (tcs > 4)
3162 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3163 else if (tcs > 1)
3164 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3165 else
671c0adb
AD		 3166 mtqc = IXGBE_MTQC_64Q_1PB;
3167 }
120ff942 3168
671c0adb 3169 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3170
671c0adb
AD		 3171 /* Enable Security TX Buffer IFG for multiple pb */
3172 if (tcs) {
3173 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3174 sectx |= IXGBE_SECTX_DCB;
3175 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3176 }
3177
3178 /* re-enable the arbiter */
3179 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3180 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3181}
3182
9a799d71 3183/**
3a581073 3184 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3185 * @adapter: board private structure
3186 *
3187 * Configure the Tx unit of the MAC after a reset.
3188 **/
3189static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3190{
2f1860b8
AD		 3191 struct ixgbe_hw *hw = &adapter->hw;
3192 u32 dmatxctl;
43e69bf0 3193 u32 i;
9a799d71 3194
2f1860b8
AD		 3195 ixgbe_setup_mtqc(adapter);
3196
3197 if (hw->mac.type != ixgbe_mac_82598EB) {
3198 /* DMATXCTL.EN must be before Tx queues are enabled */
3199 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3200 dmatxctl |= IXGBE_DMATXCTL_TE;
3201 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3202 }
3203
9a799d71 3204 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3205 for (i = 0; i < adapter->num_tx_queues; i++)
3206 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3207}
3208
3ebe8fde
AD		 3209static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3210 struct ixgbe_ring *ring)
3211{
3212 struct ixgbe_hw *hw = &adapter->hw;
3213 u8 reg_idx = ring->reg_idx;
3214 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3215
3216 srrctl |= IXGBE_SRRCTL_DROP_EN;
3217
3218 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3219}
3220
3221static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3222 struct ixgbe_ring *ring)
3223{
3224 struct ixgbe_hw *hw = &adapter->hw;
3225 u8 reg_idx = ring->reg_idx;
3226 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3227
3228 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3229
3230 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3231}
3232
3233#ifdef CONFIG_IXGBE_DCB
3234void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3235#else
3236static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3237#endif
3238{
3239 int i;
3240 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3241
3242 if (adapter->ixgbe_ieee_pfc)
3243 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3244
3245 /*
3246 * We should set the drop enable bit if:
3247 * SR-IOV is enabled
3248 * or
3249 * Number of Rx queues > 1 and flow control is disabled
3250 *
3251 * This allows us to avoid head of line blocking for security
3252 * and performance reasons.
3253 */
3254 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3255 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3256 for (i = 0; i < adapter->num_rx_queues; i++)
3257 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3258 } else {
3259 for (i = 0; i < adapter->num_rx_queues; i++)
3260 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3261 }
3262}
3263
e8e26350 3264#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3265
a6616b42 3266static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3267 struct ixgbe_ring *rx_ring)
cc41ac7c 3268{
45e9baa5 3269 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3270 u32 srrctl;
bf29ee6c 3271 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3272
45e9baa5
AD		 3273 if (hw->mac.type == ixgbe_mac_82598EB) {
3274 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3275
45e9baa5
AD		 3276 /*
3277 * if VMDq is not active we must program one srrctl register
3278 * per RSS queue since we have enabled RDRXCTL.MVMEN
3279 */
3280 reg_idx &= mask;
3281 }
cc41ac7c 3282
45e9baa5
AD		 3283 /* configure header buffer length, needed for RSC */
3284 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3285
45e9baa5 3286 /* configure the packet buffer length */
f800326d 3287 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3288
3289 /* configure descriptor type */
f800326d 3290 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3291
45e9baa5 3292 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3293}
9a799d71 3294
05abb126 3295static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3296{
05abb126
AD		 3297 struct ixgbe_hw *hw = &adapter->hw;
3298 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3299 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3300 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3301 u32 mrqc = 0, reta = 0;
3302 u32 rxcsum;
3303 int i, j;
671c0adb
AD		 3304 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3305
671c0adb
AD		 3306 /*
3307 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3308 * make full use of any rings they may have. We will use the
3309 * PSRTYPE register to control how many rings we use within the PF.
3310 */
3311 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3312 rss_i = 2;
0cefafad 3313
05abb126
AD		 3314 /* Fill out hash function seeds */
3315 for (i = 0; i < 10; i++)
3316 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3317
3318 /* Fill out redirection table */
3319 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3320 if (j == rss_i)
05abb126
AD		 3321 j = 0;
3322 /* reta = 4-byte sliding window of
3323 * 0x00..(indices-1)(indices-1)00..etc. */
3324 reta = (reta << 8) | (j * 0x11);
3325 if ((i & 3) == 3)
3326 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3327 }
0cefafad 3328
05abb126
AD		 3329 /* Disable indicating checksum in descriptor, enables RSS hash */
3330 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3331 rxcsum |= IXGBE_RXCSUM_PCSD;
3332 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3333
671c0adb 3334 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3335 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3336 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3337 } else {
671c0adb
AD		 3338 u8 tcs = netdev_get_num_tc(adapter->netdev);
3339
3340 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3341 if (tcs > 4)
3342 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3343 else if (tcs > 1)
3344 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3345 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3346 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3347 else
671c0adb
AD		 3348 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3349 } else {
3350 if (tcs > 4)
8b1c0b24 3351 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3352 else if (tcs > 1)
3353 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3354 else
3355 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3356 }
0cefafad
JB		 3357 }
3358
05abb126 3359 /* Perform hash on these packet types */
671c0adb
AD		 3360 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3361 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3362 IXGBE_MRQC_RSS_FIELD_IPV6 |
3363 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3364
ef6afc0c
AD		 3365 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3366 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3367 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3368 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3369
05abb126 3370 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3371}
3372
bb5a9ad2
NS		 3373/**
3374 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3375 * @adapter: address of board private structure
3376 * @index: index of ring to set
bb5a9ad2 3377 **/
082757af 3378static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3379 struct ixgbe_ring *ring)
bb5a9ad2 3380{
bb5a9ad2 3381 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3382 u32 rscctrl;
bf29ee6c 3383 u8 reg_idx = ring->reg_idx;
7367096a 3384
7d637bcc 3385 if (!ring_is_rsc_enabled(ring))
7367096a 3386 return;
bb5a9ad2 3387
7367096a 3388 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3389 rscctrl |= IXGBE_RSCCTL_RSCEN;
3390 /*
3391 * we must limit the number of descriptors so that the
3392 * total size of max desc * buf_len is not greater
642c680e 3393 * than 65536
bb5a9ad2 3394 */
f800326d 3395 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3396 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3397}
3398
9e10e045
AD		 3399#define IXGBE_MAX_RX_DESC_POLL 10
3400static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3401 struct ixgbe_ring *ring)
3402{
3403 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3404 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3405 u32 rxdctl;
bf29ee6c 3406 u8 reg_idx = ring->reg_idx;
9e10e045 3407
b0483c8f
MR		 3408 if (ixgbe_removed(hw->hw_addr))
3409 return;
9e10e045
AD		 3410 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3411 if (hw->mac.type == ixgbe_mac_82598EB &&
3412 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3413 return;
3414
3415 do {
032b4325 3416 usleep_range(1000, 2000);
9e10e045
AD		 3417 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3418 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3419
3420 if (!wait_loop) {
3421 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3422 "the polling period\n", reg_idx);
3423 }
3424}
3425
2d39d576
YZ		 3426void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3427 struct ixgbe_ring *ring)
3428{
3429 struct ixgbe_hw *hw = &adapter->hw;
3430 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3431 u32 rxdctl;
3432 u8 reg_idx = ring->reg_idx;
3433
b0483c8f
MR		 3434 if (ixgbe_removed(hw->hw_addr))
3435 return;
2d39d576
YZ		 3436 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3437 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3438
3439 /* write value back with RXDCTL.ENABLE bit cleared */
3440 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3441
3442 if (hw->mac.type == ixgbe_mac_82598EB &&
3443 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3444 return;
3445
3446 /* the hardware may take up to 100us to really disable the rx queue */
3447 do {
3448 udelay(10);
3449 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3450 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3451
3452 if (!wait_loop) {
3453 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3454 "the polling period\n", reg_idx);
3455 }
3456}
3457
84418e3b
AD		 3458void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3459 struct ixgbe_ring *ring)
acd37177
AD		 3460{
3461 struct ixgbe_hw *hw = &adapter->hw;
3462 u64 rdba = ring->dma;
9e10e045 3463 u32 rxdctl;
bf29ee6c 3464 u8 reg_idx = ring->reg_idx;
acd37177 3465
9e10e045
AD		 3466 /* disable queue to avoid issues while updating state */
3467 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3468 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3469
acd37177
AD		 3470 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3471 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3472 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3473 ring->count * sizeof(union ixgbe_adv_rx_desc));
3474 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3475 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3476 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3477
3478 ixgbe_configure_srrctl(adapter, ring);
3479 ixgbe_configure_rscctl(adapter, ring);
3480
3481 if (hw->mac.type == ixgbe_mac_82598EB) {
3482 /*
3483 * enable cache line friendly hardware writes:
3484 * PTHRESH=32 descriptors (half the internal cache),
3485 * this also removes ugly rx_no_buffer_count increment
3486 * HTHRESH=4 descriptors (to minimize latency on fetch)
3487 * WTHRESH=8 burst writeback up to two cache lines
3488 */
3489 rxdctl &= ~0x3FFFFF;
3490 rxdctl |= 0x080420;
3491 }
3492
3493 /* enable receive descriptor ring */
3494 rxdctl |= IXGBE_RXDCTL_ENABLE;
3495 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3496
3497 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3498 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3499}
3500
48654521
AD		 3501static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3502{
3503 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3504 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3505 u16 pool;
48654521
AD		 3506
3507 /* PSRTYPE must be initialized in non 82598 adapters */
3508 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3509 IXGBE_PSRTYPE_UDPHDR |
3510 IXGBE_PSRTYPE_IPV4HDR |
48654521 3511 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3512 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3513
3514 if (hw->mac.type == ixgbe_mac_82598EB)
3515 return;
3516
fbe7ca7f
AD		 3517 if (rss_i > 3)
3518 psrtype |= 2 << 29;
3519 else if (rss_i > 1)
3520 psrtype |= 1 << 29;
48654521 3521
2a47fa45
JF		 3522 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3523 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3524}
3525
f5b4a52e
AD		 3526static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3527{
3528 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3529 u32 reg_offset, vf_shift;
435b19f6 3530 u32 gcr_ext, vmdctl;
de4c7f65 3531 int i;
f5b4a52e
AD		 3532
3533 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3534 return;
3535
3536 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3537 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3538 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3539 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3540 vmdctl |= IXGBE_VT_CTL_REPLEN;
3541 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3542
1d9c0bfd
AD		 3543 vf_shift = VMDQ_P(0) % 32;
3544 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3545
3546 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3547 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3548 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3549 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3550 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3551 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3552 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3553
3554 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3555 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3556
3557 /*
3558 * Set up VF register offsets for selected VT Mode,
3559 * i.e. 32 or 64 VFs for SR-IOV
3560 */
73079ea0
AD		 3561 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3562 case IXGBE_82599_VMDQ_8Q_MASK:
3563 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3564 break;
3565 case IXGBE_82599_VMDQ_4Q_MASK:
3566 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3567 break;
3568 default:
3569 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3570 break;
3571 }
3572
f5b4a52e
AD		 3573 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3574
435b19f6 3575
a985b6c3 3576 /* Enable MAC Anti-Spoofing */
435b19f6 3577 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3578 adapter->num_vfs);
de4c7f65
GR		 3579 /* For VFs that have spoof checking turned off */
3580 for (i = 0; i < adapter->num_vfs; i++) {
3581 if (!adapter->vfinfo[i].spoofchk_enabled)
3582 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3583 }
f5b4a52e
AD		 3584}
3585
477de6ed 3586static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3587{
9a799d71
AK		 3588 struct ixgbe_hw *hw = &adapter->hw;
3589 struct net_device *netdev = adapter->netdev;
3590 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3591 struct ixgbe_ring *rx_ring;
3592 int i;
3593 u32 mhadd, hlreg0;
48654521 3594
63f39bd1 3595#ifdef IXGBE_FCOE
477de6ed
AD		 3596 /* adjust max frame to be able to do baby jumbo for FCoE */
3597 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3598 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3599 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3600
477de6ed 3601#endif /* IXGBE_FCOE */
872844dd
AD		 3602
3603 /* adjust max frame to be at least the size of a standard frame */
3604 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3605 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3606
477de6ed
AD		 3607 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3608 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3609 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3610 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3611
3612 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3613 }
3614
3615 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3616 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3617 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3618 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3619
0cefafad
JB		 3620 /*
3621 * Setup the HW Rx Head and Tail Descriptor Pointers and
3622 * the Base and Length of the Rx Descriptor Ring
3623 */
9a799d71 3624 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3625 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3626 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3627 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3628 else
7d637bcc 3629 clear_ring_rsc_enabled(rx_ring);
477de6ed 3630 }
477de6ed
AD		 3631}
3632
7367096a
AD		 3633static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3634{
3635 struct ixgbe_hw *hw = &adapter->hw;
3636 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3637
3638 switch (hw->mac.type) {
3639 case ixgbe_mac_82598EB:
3640 /*
3641 * For VMDq support of different descriptor types or
3642 * buffer sizes through the use of multiple SRRCTL
3643 * registers, RDRXCTL.MVMEN must be set to 1
3644 *
3645 * also, the manual doesn't mention it clearly but DCA hints
3646 * will only use queue 0's tags unless this bit is set. Side
3647 * effects of setting this bit are only that SRRCTL must be
3648 * fully programmed [0..15]
3649 */
3650 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3651 break;
3652 case ixgbe_mac_82599EB:
b93a2226 3653 case ixgbe_mac_X540:
7367096a
AD		 3654 /* Disable RSC for ACK packets */
3655 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3656 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3657 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3658 /* hardware requires some bits to be set by default */
3659 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3660 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3661 break;
3662 default:
3663 /* We should do nothing since we don't know this hardware */
3664 return;
3665 }
3666
3667 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3668}
3669
477de6ed
AD		 3670/**
3671 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3672 * @adapter: board private structure
3673 *
3674 * Configure the Rx unit of the MAC after a reset.
3675 **/
3676static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3677{
3678 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3679 int i;
6dcc28b9 3680 u32 rxctrl, rfctl;
477de6ed
AD		 3681
3682 /* disable receives while setting up the descriptors */
3683 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3684 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3685
3686 ixgbe_setup_psrtype(adapter);
7367096a 3687 ixgbe_setup_rdrxctl(adapter);
477de6ed 3688
6dcc28b9
JK		 3689 /* RSC Setup */
3690 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3691 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3692 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3693 rfctl |= IXGBE_RFCTL_RSC_DIS;
3694 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3695
9e10e045 3696 /* Program registers for the distribution of queues */
f5b4a52e 3697 ixgbe_setup_mrqc(adapter);
f5b4a52e 3698
477de6ed
AD		 3699 /* set_rx_buffer_len must be called before ring initialization */
3700 ixgbe_set_rx_buffer_len(adapter);
3701
3702 /*
3703 * Setup the HW Rx Head and Tail Descriptor Pointers and
3704 * the Base and Length of the Rx Descriptor Ring
3705 */
9e10e045
AD		 3706 for (i = 0; i < adapter->num_rx_queues; i++)
3707 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3708
9e10e045
AD		 3709 /* disable drop enable for 82598 parts */
3710 if (hw->mac.type == ixgbe_mac_82598EB)
3711 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3712
3713 /* enable all receives */
3714 rxctrl |= IXGBE_RXCTRL_RXEN;
3715 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3716}
3717
80d5c368
PM		 3718static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3719 __be16 proto, u16 vid)
068c89b0
DS		 3720{
3721 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3722 struct ixgbe_hw *hw = &adapter->hw;
3723
3724 /* add VID to filter table */
1d9c0bfd 3725 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3726 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3727
3728 return 0;
068c89b0
DS		 3729}
3730
80d5c368
PM		 3731static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3732 __be16 proto, u16 vid)
068c89b0
DS		 3733{
3734 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3735 struct ixgbe_hw *hw = &adapter->hw;
3736
068c89b0 3737 /* remove VID from filter table */
1d9c0bfd 3738 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3739 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3740
3741 return 0;
068c89b0
DS		 3742}
3743
5f6c0181
JB		 3744/**
3745 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3746 * @adapter: driver data
3747 */
3748static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3749{
3750 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3751 u32 vlnctrl;
3752
3753 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3754 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3755 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3756}
3757
3758/**
3759 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3760 * @adapter: driver data
3761 */
3762static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3763{
3764 struct ixgbe_hw *hw = &adapter->hw;
3765 u32 vlnctrl;
3766
3767 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3768 vlnctrl |= IXGBE_VLNCTRL_VFE;
3769 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3770 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3771}
3772
3773/**
3774 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3775 * @adapter: driver data
3776 */
3777static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3778{
3779 struct ixgbe_hw *hw = &adapter->hw;
3780 u32 vlnctrl;
5f6c0181
JB		 3781 int i, j;
3782
3783 switch (hw->mac.type) {
3784 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3785 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3786 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3787 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3788 break;
3789 case ixgbe_mac_82599EB:
b93a2226 3790 case ixgbe_mac_X540:
5f6c0181 3791 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3792 struct ixgbe_ring *ring = adapter->rx_ring[i];
3793
3794 if (ring->l2_accel_priv)
3795 continue;
3796 j = ring->reg_idx;
5f6c0181
JB		 3797 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3798 vlnctrl &= ~IXGBE_RXDCTL_VME;
3799 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3800 }
3801 break;
3802 default:
3803 break;
3804 }
3805}
3806
3807/**
f62bbb5e 3808 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3809 * @adapter: driver data
3810 */
f62bbb5e 3811static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3812{
3813 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3814 u32 vlnctrl;
5f6c0181
JB		 3815 int i, j;
3816
3817 switch (hw->mac.type) {
3818 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3819 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3820 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3821 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3822 break;
3823 case ixgbe_mac_82599EB:
b93a2226 3824 case ixgbe_mac_X540:
5f6c0181 3825 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3826 struct ixgbe_ring *ring = adapter->rx_ring[i];
3827
3828 if (ring->l2_accel_priv)
3829 continue;
3830 j = ring->reg_idx;
5f6c0181
JB		 3831 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3832 vlnctrl |= IXGBE_RXDCTL_VME;
3833 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3834 }
3835 break;
3836 default:
3837 break;
3838 }
3839}
3840
9a799d71
AK		 3841static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3842{
f62bbb5e 3843 u16 vid;
9a799d71 3844
80d5c368 3845 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3846
3847 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3848 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3849}
3850
2850062a
AD		 3851/**
3852 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3853 * @netdev: network interface device structure
3854 *
3855 * Writes unicast address list to the RAR table.
3856 * Returns: -ENOMEM on failure/insufficient address space
3857 * 0 on no addresses written
3858 * X on writing X addresses to the RAR table
3859 **/
3860static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3861{
3862 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3863 struct ixgbe_hw *hw = &adapter->hw;
95447461 3864 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3865 int count = 0;
3866
2a47fa45 3867 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
95447461
JF		 3868 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3869 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3870
2850062a
AD		 3871 /* return ENOMEM indicating insufficient memory for addresses */
3872 if (netdev_uc_count(netdev) > rar_entries)
3873 return -ENOMEM;
3874
95447461 3875 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3876 struct netdev_hw_addr *ha;
3877 /* return error if we do not support writing to RAR table */
3878 if (!hw->mac.ops.set_rar)
3879 return -ENOMEM;
3880
3881 netdev_for_each_uc_addr(ha, netdev) {
3882 if (!rar_entries)
3883 break;
3884 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3885 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3886 count++;
3887 }
3888 }
3889 /* write the addresses in reverse order to avoid write combining */
3890 for (; rar_entries > 0 ; rar_entries--)
3891 hw->mac.ops.clear_rar(hw, rar_entries);
3892
3893 return count;
3894}
3895
9a799d71 3896/**
2c5645cf 3897 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3898 * @netdev: network interface device structure
3899 *
2c5645cf
CL		 3900 * The set_rx_method entry point is called whenever the unicast/multicast
3901 * address list or the network interface flags are updated. This routine is
3902 * responsible for configuring the hardware for proper unicast, multicast and
3903 * promiscuous mode.
9a799d71 3904 **/
7f870475 3905void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3906{
3907 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3908 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3909 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3910 int count;
9a799d71
AK		 3911
3912 /* Check for Promiscuous and All Multicast modes */
3913
3914 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3915
f5dc442b 3916 /* set all bits that we expect to always be set */
3f2d1c0f 3917 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3918 fctrl |= IXGBE_FCTRL_BAM;
3919 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3920 fctrl |= IXGBE_FCTRL_PMCF;
3921
2850062a
AD		 3922 /* clear the bits we are changing the status of */
3923 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3924
9a799d71 3925 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3926 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3927 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3928 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3929 /* Only disable hardware filter vlans in promiscuous mode
3930 * if SR-IOV and VMDQ are disabled - otherwise ensure
3931 * that hardware VLAN filters remain enabled.
3932 */
3933 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3934 IXGBE_FLAG_SRIOV_ENABLED)))
3935 ixgbe_vlan_filter_disable(adapter);
3936 else
3937 ixgbe_vlan_filter_enable(adapter);
9a799d71 3938 } else {
746b9f02
PM		 3939 if (netdev->flags & IFF_ALLMULTI) {
3940 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3941 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3942 }
5f6c0181 3943 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3944 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3945 }
3946
3947 /*
3948 * Write addresses to available RAR registers, if there is not
3949 * sufficient space to store all the addresses then enable
3950 * unicast promiscuous mode
3951 */
3952 count = ixgbe_write_uc_addr_list(netdev);
3953 if (count < 0) {
3954 fctrl |= IXGBE_FCTRL_UPE;
3955 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3956 }
3957
cf78959c
ET		 3958 /* Write addresses to the MTA, if the attempt fails
3959 * then we should just turn on promiscuous mode so
3960 * that we can at least receive multicast traffic
3961 */
3962 hw->mac.ops.update_mc_addr_list(hw, netdev);
3963 vmolr |= IXGBE_VMOLR_ROMPE;
3964
1d9c0bfd 3965 if (adapter->num_vfs)
1cdd1ec8 3966 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3967
3968 if (hw->mac.type != ixgbe_mac_82598EB) {
3969 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3970 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3971 IXGBE_VMOLR_ROPE);
1d9c0bfd 3972 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3973 }
3974
3f2d1c0f
BG		 3975 /* This is useful for sniffing bad packets. */
3976 if (adapter->netdev->features & NETIF_F_RXALL) {
3977 /* UPE and MPE will be handled by normal PROMISC logic
3978 * in e1000e_set_rx_mode */
3979 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3980 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3981 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3982
3983 fctrl &= ~(IXGBE_FCTRL_DPF);
3984 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3985 }
3986
2850062a 3987 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3988
f646968f 3989 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3990 ixgbe_vlan_strip_enable(adapter);
3991 else
3992 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3993}
3994
021230d4
AV		 3995static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3996{
3997 int q_idx;
021230d4 3998
5a85e737
ET		 3999 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4000 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4001 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4002 }
021230d4
AV		 4003}
4004
4005static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4006{
4007 int q_idx;
021230d4 4008
5a85e737 4009 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4010 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4011 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4012 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4013 usleep_range(1000, 20000);
5a85e737
ET		 4014 }
4015 }
021230d4
AV		 4016}
4017
7a6b6f51 4018#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4019/**
2f90b865
AD		 4020 * ixgbe_configure_dcb - Configure DCB hardware
4021 * @adapter: ixgbe adapter struct
4022 *
4023 * This is called by the driver on open to configure the DCB hardware.
4024 * This is also called by the gennetlink interface when reconfiguring
4025 * the DCB state.
4026 */
4027static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4028{
4029 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4030 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4031
67ebd791
AD		 4032 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4033 if (hw->mac.type == ixgbe_mac_82598EB)
4034 netif_set_gso_max_size(adapter->netdev, 65536);
4035 return;
4036 }
4037
4038 if (hw->mac.type == ixgbe_mac_82598EB)
4039 netif_set_gso_max_size(adapter->netdev, 32768);
4040
971060b1 4041#ifdef IXGBE_FCOE
b120818e
JF		 4042 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4043 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4044#endif
b120818e
JF		 4045
4046 /* reconfigure the hardware */
4047 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4048 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4049 DCB_TX_CONFIG);
4050 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4051 DCB_RX_CONFIG);
4052 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4053 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4054 ixgbe_dcb_hw_ets(&adapter->hw,
4055 adapter->ixgbe_ieee_ets,
4056 max_frame);
4057 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4058 adapter->ixgbe_ieee_pfc->pfc_en,
4059 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4060 }
8187cd48
JF		 4061
4062 /* Enable RSS Hash per TC */
4063 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4064 u32 msb = 0;
4065 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4066
d411a936
AD		 4067 while (rss_i) {
4068 msb++;
4069 rss_i >>= 1;
4070 }
8187cd48 4071
4ae63730
AD		 4072 /* write msb to all 8 TCs in one write */
4073 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4074 }
2f90b865 4075}
9da712d2
JF		 4076#endif
4077
4078/* Additional bittime to account for IXGBE framing */
4079#define IXGBE_ETH_FRAMING 20
4080
49ce9c2c 4081/**
9da712d2
JF		 4082 * ixgbe_hpbthresh - calculate high water mark for flow control
4083 *
4084 * @adapter: board private structure to calculate for
49ce9c2c 4085 * @pb: packet buffer to calculate
9da712d2
JF		 4086 */
4087static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4088{
4089 struct ixgbe_hw *hw = &adapter->hw;
4090 struct net_device *dev = adapter->netdev;
4091 int link, tc, kb, marker;
4092 u32 dv_id, rx_pba;
4093
4094 /* Calculate max LAN frame size */
4095 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4096
4097#ifdef IXGBE_FCOE
4098 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4099 if ((dev->features & NETIF_F_FCOE_MTU) &&
4100 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4101 (pb == ixgbe_fcoe_get_tc(adapter)))
4102 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 4103
4104#endif
9da712d2
JF		 4105 /* Calculate delay value for device */
4106 switch (hw->mac.type) {
4107 case ixgbe_mac_X540:
4108 dv_id = IXGBE_DV_X540(link, tc);
4109 break;
4110 default:
4111 dv_id = IXGBE_DV(link, tc);
4112 break;
4113 }
4114
4115 /* Loopback switch introduces additional latency */
4116 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4117 dv_id += IXGBE_B2BT(tc);
4118
4119 /* Delay value is calculated in bit times convert to KB */
4120 kb = IXGBE_BT2KB(dv_id);
4121 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4122
4123 marker = rx_pba - kb;
4124
4125 /* It is possible that the packet buffer is not large enough
4126 * to provide required headroom. In this case throw an error
4127 * to user and a do the best we can.
4128 */
4129 if (marker < 0) {
4130 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4131 "headroom to support flow control."
4132 "Decrease MTU or number of traffic classes\n", pb);
4133 marker = tc + 1;
4134 }
4135
4136 return marker;
4137}
4138
49ce9c2c 4139/**
9da712d2
JF		 4140 * ixgbe_lpbthresh - calculate low water mark for for flow control
4141 *
4142 * @adapter: board private structure to calculate for
49ce9c2c 4143 * @pb: packet buffer to calculate
9da712d2
JF		 4144 */
4145static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4146{
4147 struct ixgbe_hw *hw = &adapter->hw;
4148 struct net_device *dev = adapter->netdev;
4149 int tc;
4150 u32 dv_id;
4151
4152 /* Calculate max LAN frame size */
4153 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4154
4155 /* Calculate delay value for device */
4156 switch (hw->mac.type) {
4157 case ixgbe_mac_X540:
4158 dv_id = IXGBE_LOW_DV_X540(tc);
4159 break;
4160 default:
4161 dv_id = IXGBE_LOW_DV(tc);
4162 break;
4163 }
4164
4165 /* Delay value is calculated in bit times convert to KB */
4166 return IXGBE_BT2KB(dv_id);
4167}
4168
4169/*
4170 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4171 */
4172static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4173{
4174 struct ixgbe_hw *hw = &adapter->hw;
4175 int num_tc = netdev_get_num_tc(adapter->netdev);
4176 int i;
4177
4178 if (!num_tc)
4179 num_tc = 1;
4180
4181 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4182
4183 for (i = 0; i < num_tc; i++) {
4184 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4185
4186 /* Low water marks must not be larger than high water marks */
4187 if (hw->fc.low_water > hw->fc.high_water[i])
4188 hw->fc.low_water = 0;
4189 }
4190}
4191
80605c65
JF		 4192static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4193{
80605c65 4194 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4195 int hdrm;
4196 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4197
4198 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4199 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4200 hdrm = 32 << adapter->fdir_pballoc;
4201 else
4202 hdrm = 0;
80605c65 4203
f7e1027f 4204 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4205 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4206}
4207
e4911d57
AD		 4208static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4209{
4210 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4211 struct hlist_node *node2;
e4911d57
AD		 4212 struct ixgbe_fdir_filter *filter;
4213
4214 spin_lock(&adapter->fdir_perfect_lock);
4215
4216 if (!hlist_empty(&adapter->fdir_filter_list))
4217 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4218
b67bfe0d 4219 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4220 &adapter->fdir_filter_list, fdir_node) {
4221 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4222 &filter->filter,
4223 filter->sw_idx,
4224 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4225 IXGBE_FDIR_DROP_QUEUE :
4226 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4227 }
4228
4229 spin_unlock(&adapter->fdir_perfect_lock);
4230}
4231
2a47fa45
JF		 4232static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4233 struct ixgbe_adapter *adapter)
4234{
4235 struct ixgbe_hw *hw = &adapter->hw;
4236 u32 vmolr;
4237
4238 /* No unicast promiscuous support for VMDQ devices. */
4239 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4240 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4241
4242 /* clear the affected bit */
4243 vmolr &= ~IXGBE_VMOLR_MPE;
4244
4245 if (dev->flags & IFF_ALLMULTI) {
4246 vmolr |= IXGBE_VMOLR_MPE;
4247 } else {
4248 vmolr |= IXGBE_VMOLR_ROMPE;
4249 hw->mac.ops.update_mc_addr_list(hw, dev);
4250 }
4251 ixgbe_write_uc_addr_list(adapter->netdev);
4252 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4253}
4254
4255static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4256 u8 *addr, u16 pool)
4257{
4258 struct ixgbe_hw *hw = &adapter->hw;
4259 unsigned int entry;
4260
4261 entry = hw->mac.num_rar_entries - pool;
4262 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4263}
4264
4265static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4266{
4267 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4268 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4269 struct ixgbe_hw *hw = &adapter->hw;
4270 u16 pool = vadapter->pool;
4271 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4272 IXGBE_PSRTYPE_UDPHDR |
4273 IXGBE_PSRTYPE_IPV4HDR |
4274 IXGBE_PSRTYPE_L2HDR |
4275 IXGBE_PSRTYPE_IPV6HDR;
4276
4277 if (hw->mac.type == ixgbe_mac_82598EB)
4278 return;
4279
4280 if (rss_i > 3)
4281 psrtype |= 2 << 29;
4282 else if (rss_i > 1)
4283 psrtype |= 1 << 29;
4284
4285 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4286}
4287
4288/**
4289 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4290 * @rx_ring: ring to free buffers from
4291 **/
4292static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4293{
4294 struct device *dev = rx_ring->dev;
4295 unsigned long size;
4296 u16 i;
4297
4298 /* ring already cleared, nothing to do */
4299 if (!rx_ring->rx_buffer_info)
4300 return;
4301
4302 /* Free all the Rx ring sk_buffs */
4303 for (i = 0; i < rx_ring->count; i++) {
4304 struct ixgbe_rx_buffer *rx_buffer;
4305
4306 rx_buffer = &rx_ring->rx_buffer_info[i];
4307 if (rx_buffer->skb) {
4308 struct sk_buff *skb = rx_buffer->skb;
4309 if (IXGBE_CB(skb)->page_released) {
4310 dma_unmap_page(dev,
4311 IXGBE_CB(skb)->dma,
4312 ixgbe_rx_bufsz(rx_ring),
4313 DMA_FROM_DEVICE);
4314 IXGBE_CB(skb)->page_released = false;
4315 }
4316 dev_kfree_skb(skb);
4317 }
4318 rx_buffer->skb = NULL;
4319 if (rx_buffer->dma)
4320 dma_unmap_page(dev, rx_buffer->dma,
4321 ixgbe_rx_pg_size(rx_ring),
4322 DMA_FROM_DEVICE);
4323 rx_buffer->dma = 0;
4324 if (rx_buffer->page)
4325 __free_pages(rx_buffer->page,
4326 ixgbe_rx_pg_order(rx_ring));
4327 rx_buffer->page = NULL;
4328 }
4329
4330 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4331 memset(rx_ring->rx_buffer_info, 0, size);
4332
4333 /* Zero out the descriptor ring */
4334 memset(rx_ring->desc, 0, rx_ring->size);
4335
4336 rx_ring->next_to_alloc = 0;
4337 rx_ring->next_to_clean = 0;
4338 rx_ring->next_to_use = 0;
4339}
4340
4341static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4342 struct ixgbe_ring *rx_ring)
4343{
4344 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4345 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4346
4347 /* shutdown specific queue receive and wait for dma to settle */
4348 ixgbe_disable_rx_queue(adapter, rx_ring);
4349 usleep_range(10000, 20000);
4350 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4351 ixgbe_clean_rx_ring(rx_ring);
4352 rx_ring->l2_accel_priv = NULL;
4353}
4354
ae72c8d0
JF		 4355static int ixgbe_fwd_ring_down(struct net_device *vdev,
4356 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4357{
4358 struct ixgbe_adapter *adapter = accel->real_adapter;
4359 unsigned int rxbase = accel->rx_base_queue;
4360 unsigned int txbase = accel->tx_base_queue;
4361 int i;
4362
4363 netif_tx_stop_all_queues(vdev);
4364
4365 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4366 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4367 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4368 }
4369
4370 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4371 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4372 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4373 }
4374
4375
4376 return 0;
4377}
4378
4379static int ixgbe_fwd_ring_up(struct net_device *vdev,
4380 struct ixgbe_fwd_adapter *accel)
4381{
4382 struct ixgbe_adapter *adapter = accel->real_adapter;
4383 unsigned int rxbase, txbase, queues;
4384 int i, baseq, err = 0;
4385
4386 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4387 return 0;
4388
4389 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4390 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4391 accel->pool, adapter->num_rx_pools,
4392 baseq, baseq + adapter->num_rx_queues_per_pool,
4393 adapter->fwd_bitmask);
4394
4395 accel->netdev = vdev;
4396 accel->rx_base_queue = rxbase = baseq;
4397 accel->tx_base_queue = txbase = baseq;
4398
4399 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4400 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4401
4402 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4403 adapter->rx_ring[rxbase + i]->netdev = vdev;
4404 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4405 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4406 }
4407
4408 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4409 adapter->tx_ring[txbase + i]->netdev = vdev;
4410 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4411 }
4412
4413 queues = min_t(unsigned int,
4414 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4415 err = netif_set_real_num_tx_queues(vdev, queues);
4416 if (err)
4417 goto fwd_queue_err;
4418
2a47fa45
JF		 4419 err = netif_set_real_num_rx_queues(vdev, queues);
4420 if (err)
4421 goto fwd_queue_err;
4422
4423 if (is_valid_ether_addr(vdev->dev_addr))
4424 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4425
4426 ixgbe_fwd_psrtype(accel);
4427 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4428 return err;
4429fwd_queue_err:
4430 ixgbe_fwd_ring_down(vdev, accel);
4431 return err;
4432}
4433
4434static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4435{
4436 struct net_device *upper;
4437 struct list_head *iter;
4438 int err;
4439
4440 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4441 if (netif_is_macvlan(upper)) {
4442 struct macvlan_dev *dfwd = netdev_priv(upper);
4443 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4444
4445 if (dfwd->fwd_priv) {
4446 err = ixgbe_fwd_ring_up(upper, vadapter);
4447 if (err)
4448 continue;
4449 }
4450 }
4451 }
4452}
4453
9a799d71
AK		 4454static void ixgbe_configure(struct ixgbe_adapter *adapter)
4455{
d2f5e7f3
AS		 4456 struct ixgbe_hw *hw = &adapter->hw;
4457
80605c65 4458 ixgbe_configure_pb(adapter);
7a6b6f51 4459#ifdef CONFIG_IXGBE_DCB
67ebd791 4460 ixgbe_configure_dcb(adapter);
2f90b865 4461#endif
b35d4d42
AD		 4462 /*
4463 * We must restore virtualization before VLANs or else
4464 * the VLVF registers will not be populated
4465 */
4466 ixgbe_configure_virtualization(adapter);
9a799d71 4467
4c1d7b4b 4468 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4469 ixgbe_restore_vlan(adapter);
4470
d2f5e7f3
AS		 4471 switch (hw->mac.type) {
4472 case ixgbe_mac_82599EB:
4473 case ixgbe_mac_X540:
4474 hw->mac.ops.disable_rx_buff(hw);
4475 break;
4476 default:
4477 break;
4478 }
4479
c4cf55e5 4480 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4481 ixgbe_init_fdir_signature_82599(&adapter->hw,
4482 adapter->fdir_pballoc);
e4911d57
AD		 4483 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4484 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4485 adapter->fdir_pballoc);
4486 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4487 }
4c1d7b4b 4488
d2f5e7f3
AS		 4489 switch (hw->mac.type) {
4490 case ixgbe_mac_82599EB:
4491 case ixgbe_mac_X540:
4492 hw->mac.ops.enable_rx_buff(hw);
4493 break;
4494 default:
4495 break;
4496 }
4497
7c8ae65a
AD		 4498#ifdef IXGBE_FCOE
4499 /* configure FCoE L2 filters, redirection table, and Rx control */
4500 ixgbe_configure_fcoe(adapter);
4501
4502#endif /* IXGBE_FCOE */
9a799d71
AK		 4503 ixgbe_configure_tx(adapter);
4504 ixgbe_configure_rx(adapter);
2a47fa45 4505 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4506}
4507
e8e26350
PW		 4508static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4509{
4510 switch (hw->phy.type) {
4511 case ixgbe_phy_sfp_avago:
4512 case ixgbe_phy_sfp_ftl:
4513 case ixgbe_phy_sfp_intel:
4514 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4515 case ixgbe_phy_sfp_passive_tyco:
4516 case ixgbe_phy_sfp_passive_unknown:
4517 case ixgbe_phy_sfp_active_unknown:
4518 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4519 case ixgbe_phy_qsfp_passive_unknown:
4520 case ixgbe_phy_qsfp_active_unknown:
4521 case ixgbe_phy_qsfp_intel:
4522 case ixgbe_phy_qsfp_unknown:
e8e26350 4523 return true;
8917b447
AD		 4524 case ixgbe_phy_nl:
4525 if (hw->mac.type == ixgbe_mac_82598EB)
4526 return true;
e8e26350
PW		 4527 default:
4528 return false;
4529 }
4530}
4531
0ecc061d 4532/**
e8e26350
PW		 4533 * ixgbe_sfp_link_config - set up SFP+ link
4534 * @adapter: pointer to private adapter struct
4535 **/
4536static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4537{
7086400d 4538 /*
52f33af8 4539 * We are assuming the worst case scenario here, and that
7086400d
AD		 4540 * is that an SFP was inserted/removed after the reset
4541 * but before SFP detection was enabled. As such the best
4542 * solution is to just start searching as soon as we start
4543 */
4544 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4545 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4546
7086400d 4547 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4548}
4549
4550/**
4551 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4552 * @hw: pointer to private hardware struct
4553 *
4554 * Returns 0 on success, negative on failure
4555 **/
e8e26350 4556static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4557{
3d292265
JH		 4558 u32 speed;
4559 bool autoneg, link_up = false;
0ecc061d
PWJ		 4560 u32 ret = IXGBE_ERR_LINK_SETUP;
4561
4562 if (hw->mac.ops.check_link)
3d292265 4563 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4564
4565 if (ret)
4566 goto link_cfg_out;
4567
3d292265
JH		 4568 speed = hw->phy.autoneg_advertised;
4569 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4570 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4571 &autoneg);
0ecc061d
PWJ		 4572 if (ret)
4573 goto link_cfg_out;
4574
8620a103 4575 if (hw->mac.ops.setup_link)
fd0326f2 4576 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4577link_cfg_out:
4578 return ret;
4579}
4580
a34bcfff 4581static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4582{
9a799d71 4583 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4584 u32 gpie = 0;
9a799d71 4585
9b471446 4586 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4587 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4588 IXGBE_GPIE_OCD;
4589 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4590 /*
4591 * use EIAM to auto-mask when MSI-X interrupt is asserted
4592 * this saves a register write for every interrupt
4593 */
4594 switch (hw->mac.type) {
4595 case ixgbe_mac_82598EB:
4596 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4597 break;
9b471446 4598 case ixgbe_mac_82599EB:
b93a2226
DS		 4599 case ixgbe_mac_X540:
4600 default:
9b471446
JB		 4601 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4602 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4603 break;
4604 }
4605 } else {
021230d4
AV		 4606 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4607 * specifically only auto mask tx and rx interrupts */
4608 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4609 }
9a799d71 4610
a34bcfff
AD		 4611 /* XXX: to interrupt immediately for EICS writes, enable this */
4612 /* gpie |= IXGBE_GPIE_EIMEN; */
4613
4614 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4615 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4616
4617 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4618 case IXGBE_82599_VMDQ_8Q_MASK:
4619 gpie |= IXGBE_GPIE_VTMODE_16;
4620 break;
4621 case IXGBE_82599_VMDQ_4Q_MASK:
4622 gpie |= IXGBE_GPIE_VTMODE_32;
4623 break;
4624 default:
4625 gpie |= IXGBE_GPIE_VTMODE_64;
4626 break;
4627 }
119fc60a
MC		 4628 }
4629
5fdd31f9 4630 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4631 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4632 switch (adapter->hw.mac.type) {
4633 case ixgbe_mac_82599EB:
4634 gpie |= IXGBE_SDP0_GPIEN;
4635 break;
4636 case ixgbe_mac_X540:
4637 gpie |= IXGBE_EIMS_TS;
4638 break;
4639 default:
4640 break;
4641 }
4642 }
5fdd31f9 4643
a34bcfff
AD		 4644 /* Enable fan failure interrupt */
4645 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4646 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4647
2698b208 4648 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4649 gpie |= IXGBE_SDP1_GPIEN;
4650 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4651 }
a34bcfff
AD		 4652
4653 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4654}
4655
c7ccde0f 4656static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4657{
4658 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4659 int err;
a34bcfff
AD		 4660 u32 ctrl_ext;
4661
4662 ixgbe_get_hw_control(adapter);
4663 ixgbe_setup_gpie(adapter);
e8e26350 4664
9a799d71
AK		 4665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4666 ixgbe_configure_msix(adapter);
4667 else
4668 ixgbe_configure_msi_and_legacy(adapter);
4669
ec74a471
ET		 4670 /* enable the optics for 82599 SFP+ fiber */
4671 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4672 hw->mac.ops.enable_tx_laser(hw);
4673
c3049c8f 4674 smp_mb__before_clear_bit();
9a799d71 4675 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4676 ixgbe_napi_enable_all(adapter);
4677
73c4b7cd
AD		 4678 if (ixgbe_is_sfp(hw)) {
4679 ixgbe_sfp_link_config(adapter);
4680 } else {
4681 err = ixgbe_non_sfp_link_config(hw);
4682 if (err)
4683 e_err(probe, "link_config FAILED %d\n", err);
4684 }
4685
021230d4
AV		 4686 /* clear any pending interrupts, may auto mask */
4687 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4688 ixgbe_irq_enable(adapter, true, true);
9a799d71 4689
bf069c97
DS		 4690 /*
4691 * If this adapter has a fan, check to see if we had a failure
4692 * before we enabled the interrupt.
4693 */
4694 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4695 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4696 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4697 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4698 }
4699
9a799d71
AK		 4700 /* bring the link up in the watchdog, this could race with our first
4701 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4702 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4703 adapter->link_check_timeout = jiffies;
7086400d 4704 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4705
4706 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4707 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4708 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4709 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4710}
4711
d4f80882
AV		 4712void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4713{
4714 WARN_ON(in_interrupt());
7086400d
AD		 4715 /* put off any impending NetWatchDogTimeout */
4716 adapter->netdev->trans_start = jiffies;
4717
d4f80882 4718 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4719 usleep_range(1000, 2000);
d4f80882 4720 ixgbe_down(adapter);
5809a1ae
GR		 4721 /*
4722 * If SR-IOV enabled then wait a bit before bringing the adapter
4723 * back up to give the VFs time to respond to the reset. The
4724 * two second wait is based upon the watchdog timer cycle in
4725 * the VF driver.
4726 */
4727 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4728 msleep(2000);
d4f80882
AV		 4729 ixgbe_up(adapter);
4730 clear_bit(__IXGBE_RESETTING, &adapter->state);
4731}
4732
c7ccde0f 4733void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4734{
4735 /* hardware has been reset, we need to reload some things */
4736 ixgbe_configure(adapter);
4737
c7ccde0f 4738 ixgbe_up_complete(adapter);
9a799d71
AK		 4739}
4740
4741void ixgbe_reset(struct ixgbe_adapter *adapter)
4742{
c44ade9e 4743 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4744 int err;
4745
b0483c8f
MR		 4746 if (ixgbe_removed(hw->hw_addr))
4747 return;
7086400d
AD		 4748 /* lock SFP init bit to prevent race conditions with the watchdog */
4749 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4750 usleep_range(1000, 2000);
4751
4752 /* clear all SFP and link config related flags while holding SFP_INIT */
4753 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4754 IXGBE_FLAG2_SFP_NEEDS_RESET);
4755 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4756
8ca783ab 4757 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4758 switch (err) {
4759 case 0:
4760 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4761 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4762 break;
4763 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4764 e_dev_err("master disable timed out\n");
da4dd0f7 4765 break;
794caeb2
PWJ		 4766 case IXGBE_ERR_EEPROM_VERSION:
4767 /* We are running on a pre-production device, log a warning */
849c4542 4768 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4769 "Please be aware there may be issues associated with "
849c4542
ET		 4770 "your hardware. If you are experiencing problems "
4771 "please contact your Intel or hardware "
4772 "representative who provided you with this "
4773 "hardware.\n");
794caeb2 4774 break;
da4dd0f7 4775 default:
849c4542 4776 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4777 }
9a799d71 4778
7086400d
AD		 4779 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4780
9a799d71 4781 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4782 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4783
4784 /* update SAN MAC vmdq pool selection */
4785 if (hw->mac.san_mac_rar_index)
4786 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4787
8fecf67c 4788 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4789 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4790}
4791
9a799d71
AK		 4792/**
4793 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4794 * @tx_ring: ring to be cleaned
4795 **/
b6ec895e 4796static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4797{
4798 struct ixgbe_tx_buffer *tx_buffer_info;
4799 unsigned long size;
b6ec895e 4800 u16 i;
9a799d71 4801
84418e3b
AD		 4802 /* ring already cleared, nothing to do */
4803 if (!tx_ring->tx_buffer_info)
4804 return;
9a799d71 4805
84418e3b 4806 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4807 for (i = 0; i < tx_ring->count; i++) {
4808 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4809 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4810 }
4811
dad8a3b3
JF		 4812 netdev_tx_reset_queue(txring_txq(tx_ring));
4813
9a799d71
AK		 4814 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4815 memset(tx_ring->tx_buffer_info, 0, size);
4816
4817 /* Zero out the descriptor ring */
4818 memset(tx_ring->desc, 0, tx_ring->size);
4819
4820 tx_ring->next_to_use = 0;
4821 tx_ring->next_to_clean = 0;
9a799d71
AK		 4822}
4823
4824/**
021230d4 4825 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4826 * @adapter: board private structure
4827 **/
021230d4 4828static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4829{
4830 int i;
4831
021230d4 4832 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4833 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4834}
4835
4836/**
021230d4 4837 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4838 * @adapter: board private structure
4839 **/
021230d4 4840static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4841{
4842 int i;
4843
021230d4 4844 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4845 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4846}
4847
e4911d57
AD		 4848static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4849{
b67bfe0d 4850 struct hlist_node *node2;
e4911d57
AD		 4851 struct ixgbe_fdir_filter *filter;
4852
4853 spin_lock(&adapter->fdir_perfect_lock);
4854
b67bfe0d 4855 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4856 &adapter->fdir_filter_list, fdir_node) {
4857 hlist_del(&filter->fdir_node);
4858 kfree(filter);
4859 }
4860 adapter->fdir_filter_count = 0;
4861
4862 spin_unlock(&adapter->fdir_perfect_lock);
4863}
4864
9a799d71
AK		 4865void ixgbe_down(struct ixgbe_adapter *adapter)
4866{
4867 struct net_device *netdev = adapter->netdev;
7f821875 4868 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4869 struct net_device *upper;
4870 struct list_head *iter;
9a799d71 4871 u32 rxctrl;
bf29ee6c 4872 int i;
9a799d71
AK		 4873
4874 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4875 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4876 return; /* do nothing if already down */
9a799d71
AK		 4877
4878 /* disable receives */
7f821875
JB		 4879 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4880 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4881
2d39d576
YZ		 4882 /* disable all enabled rx queues */
4883 for (i = 0; i < adapter->num_rx_queues; i++)
4884 /* this call also flushes the previous write */
4885 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4886
032b4325 4887 usleep_range(10000, 20000);
9a799d71 4888
7f821875
JB		 4889 netif_tx_stop_all_queues(netdev);
4890
7086400d 4891 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4892 netif_carrier_off(netdev);
4893 netif_tx_disable(netdev);
4894
2a47fa45
JF		 4895 /* disable any upper devices */
4896 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4897 if (netif_is_macvlan(upper)) {
4898 struct macvlan_dev *vlan = netdev_priv(upper);
4899
4900 if (vlan->fwd_priv) {
4901 netif_tx_stop_all_queues(upper);
4902 netif_carrier_off(upper);
4903 netif_tx_disable(upper);
4904 }
4905 }
4906 }
4907
c0dfb90e
JF		 4908 ixgbe_irq_disable(adapter);
4909
4910 ixgbe_napi_disable_all(adapter);
4911
d034acf1
AD		 4912 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4913 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4914 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4915
4916 del_timer_sync(&adapter->service_timer);
4917
34cecbbf 4918 if (adapter->num_vfs) {
8e34d1aa
AD		 4919 /* Clear EITR Select mapping */
4920 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4921
4922 /* Mark all the VFs as inactive */
4923 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4924 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4925
34cecbbf
AD		 4926 /* ping all the active vfs to let them know we are going down */
4927 ixgbe_ping_all_vfs(adapter);
4928
4929 /* Disable all VFTE/VFRE TX/RX */
4930 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4931 }
4932
7f821875
JB		 4933 /* disable transmits in the hardware now that interrupts are off */
4934 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4935 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4936 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4937 }
34cecbbf
AD		 4938
4939 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4940 switch (hw->mac.type) {
4941 case ixgbe_mac_82599EB:
b93a2226 4942 case ixgbe_mac_X540:
88512539 4943 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4944 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4945 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4946 break;
4947 default:
4948 break;
4949 }
7f821875 4950
6f4a0e45
PL		 4951 if (!pci_channel_offline(adapter->pdev))
4952 ixgbe_reset(adapter);
c6ecf39a 4953
ec74a471
ET		 4954 /* power down the optics for 82599 SFP+ fiber */
4955 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4956 hw->mac.ops.disable_tx_laser(hw);
4957
9a799d71
AK		 4958 ixgbe_clean_all_tx_rings(adapter);
4959 ixgbe_clean_all_rx_rings(adapter);
4960
5dd2d332 4961#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4962 /* since we reset the hardware DCA settings were cleared */
e35ec126 4963 ixgbe_setup_dca(adapter);
96b0e0f6 4964#endif
9a799d71
AK		 4965}
4966
9a799d71
AK		 4967/**
4968 * ixgbe_tx_timeout - Respond to a Tx Hang
4969 * @netdev: network interface device structure
4970 **/
4971static void ixgbe_tx_timeout(struct net_device *netdev)
4972{
4973 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4974
4975 /* Do the reset outside of interrupt context */
c83c6cbd 4976 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4977}
4978
9a799d71
AK		 4979/**
4980 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4981 * @adapter: board private structure to initialize
4982 *
4983 * ixgbe_sw_init initializes the Adapter private data structure.
4984 * Fields are initialized based on PCI device information and
4985 * OS network device settings (MTU size).
4986 **/
9f9a12f8 4987static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4988{
4989 struct ixgbe_hw *hw = &adapter->hw;
4990 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4991 unsigned int rss, fdir;
cb6d0f5e 4992 u32 fwsm;
7a6b6f51 4993#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4994 int j;
4995 struct tc_configuration *tc;
4996#endif
021230d4 4997
c44ade9e
JB		 4998 /* PCI config space info */
4999
5000 hw->vendor_id = pdev->vendor;
5001 hw->device_id = pdev->device;
5002 hw->revision_id = pdev->revision;
5003 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5004 hw->subsystem_device_id = pdev->subsystem_device;
5005
8fc3bb6d 5006 /* Set common capability flags and settings */
3ed69d7e 5007 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5008 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5009 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5010 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5011 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5012 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5013 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5014 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5015 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5016#ifdef CONFIG_IXGBE_DCA
5017 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5018#endif
5019#ifdef IXGBE_FCOE
5020 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5021 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5022#ifdef CONFIG_IXGBE_DCB
5023 /* Default traffic class to use for FCoE */
5024 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5025#endif /* CONFIG_IXGBE_DCB */
5026#endif /* IXGBE_FCOE */
5027
5028 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5029 switch (hw->mac.type) {
5030 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5031 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5032 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5033
bf069c97
DS		 5034 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5035 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5036
49c7ffbe 5037 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5038 adapter->ring_feature[RING_F_FDIR].limit = 0;
5039 adapter->atr_sample_rate = 0;
5040 adapter->fdir_pballoc = 0;
5041#ifdef IXGBE_FCOE
5042 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5043 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5044#ifdef CONFIG_IXGBE_DCB
5045 adapter->fcoe.up = 0;
5046#endif /* IXGBE_DCB */
5047#endif /* IXGBE_FCOE */
5048 break;
5049 case ixgbe_mac_82599EB:
5050 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5051 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5052 break;
b93a2226 5053 case ixgbe_mac_X540:
cb6d0f5e
JK		 5054 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5055 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5056 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5057 break;
5058 default:
5059 break;
f8212f97 5060 }
2f90b865 5061
7c8ae65a
AD		 5062#ifdef IXGBE_FCOE
5063 /* FCoE support exists, always init the FCoE lock */
5064 spin_lock_init(&adapter->fcoe.lock);
5065
5066#endif
1fc5f038
AD		 5067 /* n-tuple support exists, always init our spinlock */
5068 spin_lock_init(&adapter->fdir_perfect_lock);
5069
7a6b6f51 5070#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5071 switch (hw->mac.type) {
5072 case ixgbe_mac_X540:
5073 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5074 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5075 break;
5076 default:
5077 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5078 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5079 break;
5080 }
5081
2f90b865
AD		 5082 /* Configure DCB traffic classes */
5083 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5084 tc = &adapter->dcb_cfg.tc_config[j];
5085 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5086 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5087 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5088 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5089 tc->dcb_pfc = pfc_disabled;
5090 }
4de2a022
JF		 5091
5092 /* Initialize default user to priority mapping, UPx->TC0 */
5093 tc = &adapter->dcb_cfg.tc_config[0];
5094 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5095 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5096
2f90b865
AD		 5097 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5098 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5099 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5100 adapter->dcb_set_bitmap = 0x00;
3032309b 5101 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5102 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5103 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5104
5105#endif
9a799d71
AK		 5106
5107 /* default flow control settings */
cd7664f6 5108 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5109 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5110 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5111 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5112 hw->fc.send_xon = true;
73d80953 5113 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5114
99d74487 5115#ifdef CONFIG_PCI_IOV
170e8543
JK		 5116 if (max_vfs > 0)
5117 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5118
99d74487 5119 /* assign number of SR-IOV VFs */
170e8543 5120 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5121 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5122 adapter->num_vfs = 0;
5123 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5124 } else {
5125 adapter->num_vfs = max_vfs;
5126 }
5127 }
5128#endif /* CONFIG_PCI_IOV */
99d74487 5129
30efa5a3 5130 /* enable itr by default in dynamic mode */
f7554a2b 5131 adapter->rx_itr_setting = 1;
f7554a2b 5132 adapter->tx_itr_setting = 1;
30efa5a3 5133
30efa5a3
JB		 5134 /* set default ring sizes */
5135 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5136 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5137
bd198058 5138 /* set default work limits */
59224555 5139 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5140
9a799d71 5141 /* initialize eeprom parameters */
c44ade9e 5142 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5143 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5144 return -EIO;
5145 }
5146
2a47fa45
JF		 5147 /* PF holds first pool slot */
5148 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5149 set_bit(__IXGBE_DOWN, &adapter->state);
5150
5151 return 0;
5152}
5153
5154/**
5155 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5156 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5157 *
5158 * Return 0 on success, negative on failure
5159 **/
b6ec895e 5160int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5161{
b6ec895e 5162 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5163 int orig_node = dev_to_node(dev);
5164 int numa_node = -1;
9a799d71
AK		 5165 int size;
5166
3a581073 5167 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5168
5169 if (tx_ring->q_vector)
5170 numa_node = tx_ring->q_vector->numa_node;
5171
5172 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5173 if (!tx_ring->tx_buffer_info)
89bf67f1 5174 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5175 if (!tx_ring->tx_buffer_info)
5176 goto err;
9a799d71 5177
827da44c
JS		 5178 u64_stats_init(&tx_ring->syncp);
5179
9a799d71 5180 /* round up to nearest 4K */
12207e49 5181 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5182 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5183
de88eeeb
AD		 5184 set_dev_node(dev, numa_node);
5185 tx_ring->desc = dma_alloc_coherent(dev,
5186 tx_ring->size,
5187 &tx_ring->dma,
5188 GFP_KERNEL);
5189 set_dev_node(dev, orig_node);
5190 if (!tx_ring->desc)
5191 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5192 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5193 if (!tx_ring->desc)
5194 goto err;
9a799d71 5195
3a581073
JB		 5196 tx_ring->next_to_use = 0;
5197 tx_ring->next_to_clean = 0;
9a799d71 5198 return 0;
e01c31a5
JB		 5199
5200err:
5201 vfree(tx_ring->tx_buffer_info);
5202 tx_ring->tx_buffer_info = NULL;
b6ec895e 5203 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5204 return -ENOMEM;
9a799d71
AK		 5205}
5206
69888674
AD		 5207/**
5208 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5209 * @adapter: board private structure
5210 *
5211 * If this function returns with an error, then it's possible one or
5212 * more of the rings is populated (while the rest are not). It is the
5213 * callers duty to clean those orphaned rings.
5214 *
5215 * Return 0 on success, negative on failure
5216 **/
5217static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5218{
5219 int i, err = 0;
5220
5221 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5222 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5223 if (!err)
5224 continue;
de3d5b94 5225
396e799c 5226 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5227 goto err_setup_tx;
69888674
AD		 5228 }
5229
de3d5b94
AD		 5230 return 0;
5231err_setup_tx:
5232 /* rewind the index freeing the rings as we go */
5233 while (i--)
5234 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5235 return err;
5236}
5237
9a799d71
AK		 5238/**
5239 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5240 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5241 *
5242 * Returns 0 on success, negative on failure
5243 **/
b6ec895e 5244int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5245{
b6ec895e 5246 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5247 int orig_node = dev_to_node(dev);
5248 int numa_node = -1;
021230d4 5249 int size;
9a799d71 5250
3a581073 5251 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5252
5253 if (rx_ring->q_vector)
5254 numa_node = rx_ring->q_vector->numa_node;
5255
5256 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5257 if (!rx_ring->rx_buffer_info)
89bf67f1 5258 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5259 if (!rx_ring->rx_buffer_info)
5260 goto err;
9a799d71 5261
827da44c
JS		 5262 u64_stats_init(&rx_ring->syncp);
5263
9a799d71 5264 /* Round up to nearest 4K */
3a581073
JB		 5265 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5266 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5267
de88eeeb
AD		 5268 set_dev_node(dev, numa_node);
5269 rx_ring->desc = dma_alloc_coherent(dev,
5270 rx_ring->size,
5271 &rx_ring->dma,
5272 GFP_KERNEL);
5273 set_dev_node(dev, orig_node);
5274 if (!rx_ring->desc)
5275 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5276 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5277 if (!rx_ring->desc)
5278 goto err;
9a799d71 5279
3a581073
JB		 5280 rx_ring->next_to_clean = 0;
5281 rx_ring->next_to_use = 0;
9a799d71
AK		 5282
5283 return 0;
b6ec895e
AD		 5284err:
5285 vfree(rx_ring->rx_buffer_info);
5286 rx_ring->rx_buffer_info = NULL;
5287 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5288 return -ENOMEM;
9a799d71
AK		 5289}
5290
69888674
AD		 5291/**
5292 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5293 * @adapter: board private structure
5294 *
5295 * If this function returns with an error, then it's possible one or
5296 * more of the rings is populated (while the rest are not). It is the
5297 * callers duty to clean those orphaned rings.
5298 *
5299 * Return 0 on success, negative on failure
5300 **/
69888674
AD		 5301static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5302{
5303 int i, err = 0;
5304
5305 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5306 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5307 if (!err)
5308 continue;
de3d5b94 5309
396e799c 5310 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5311 goto err_setup_rx;
69888674
AD		 5312 }
5313
7c8ae65a
AD		 5314#ifdef IXGBE_FCOE
5315 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5316 if (!err)
5317#endif
5318 return 0;
de3d5b94
AD		 5319err_setup_rx:
5320 /* rewind the index freeing the rings as we go */
5321 while (i--)
5322 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5323 return err;
5324}
5325
9a799d71
AK		 5326/**
5327 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5328 * @tx_ring: Tx descriptor ring for a specific queue
5329 *
5330 * Free all transmit software resources
5331 **/
b6ec895e 5332void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5333{
b6ec895e 5334 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5335
5336 vfree(tx_ring->tx_buffer_info);
5337 tx_ring->tx_buffer_info = NULL;
5338
b6ec895e
AD		 5339 /* if not set, then don't free */
5340 if (!tx_ring->desc)
5341 return;
5342
5343 dma_free_coherent(tx_ring->dev, tx_ring->size,
5344 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5345
5346 tx_ring->desc = NULL;
5347}
5348
5349/**
5350 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5351 * @adapter: board private structure
5352 *
5353 * Free all transmit software resources
5354 **/
5355static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5356{
5357 int i;
5358
5359 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5360 if (adapter->tx_ring[i]->desc)
b6ec895e 5361 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5362}
5363
5364/**
b4617240 5365 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5366 * @rx_ring: ring to clean the resources from
5367 *
5368 * Free all receive software resources
5369 **/
b6ec895e 5370void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5371{
b6ec895e 5372 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5373
5374 vfree(rx_ring->rx_buffer_info);
5375 rx_ring->rx_buffer_info = NULL;
5376
b6ec895e
AD		 5377 /* if not set, then don't free */
5378 if (!rx_ring->desc)
5379 return;
5380
5381 dma_free_coherent(rx_ring->dev, rx_ring->size,
5382 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5383
5384 rx_ring->desc = NULL;
5385}
5386
5387/**
5388 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5389 * @adapter: board private structure
5390 *
5391 * Free all receive software resources
5392 **/
5393static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5394{
5395 int i;
5396
7c8ae65a
AD		 5397#ifdef IXGBE_FCOE
5398 ixgbe_free_fcoe_ddp_resources(adapter);
5399
5400#endif
9a799d71 5401 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5402 if (adapter->rx_ring[i]->desc)
b6ec895e 5403 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5404}
5405
9a799d71
AK		 5406/**
5407 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5408 * @netdev: network interface device structure
5409 * @new_mtu: new value for maximum frame size
5410 *
5411 * Returns 0 on success, negative on failure
5412 **/
5413static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5414{
5415 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5416 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5417
42c783c5 5418 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5419 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5420 return -EINVAL;
5421
5422 /*
872844dd
AD		 5423 * For 82599EB we cannot allow legacy VFs to enable their receive
5424 * paths when MTU greater than 1500 is configured. So display a
5425 * warning that legacy VFs will be disabled.
655309e9
AD		 5426 */
5427 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5428 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5429 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5430 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5431
396e799c 5432 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5433
021230d4 5434 /* must set new MTU before calling down or up */
9a799d71
AK		 5435 netdev->mtu = new_mtu;
5436
d4f80882
AV		 5437 if (netif_running(netdev))
5438 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5439
5440 return 0;
5441}
5442
5443/**
5444 * ixgbe_open - Called when a network interface is made active
5445 * @netdev: network interface device structure
5446 *
5447 * Returns 0 on success, negative value on failure
5448 *
5449 * The open entry point is called when a network interface is made
5450 * active by the system (IFF_UP). At this point all resources needed
5451 * for transmit and receive operations are allocated, the interrupt
5452 * handler is registered with the OS, the watchdog timer is started,
5453 * and the stack is notified that the interface is ready.
5454 **/
5455static int ixgbe_open(struct net_device *netdev)
5456{
5457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5458 int err, queues;
4bebfaa5
AK		 5459
5460 /* disallow open during test */
5461 if (test_bit(__IXGBE_TESTING, &adapter->state))
5462 return -EBUSY;
9a799d71 5463
54386467
JB		 5464 netif_carrier_off(netdev);
5465
9a799d71
AK		 5466 /* allocate transmit descriptors */
5467 err = ixgbe_setup_all_tx_resources(adapter);
5468 if (err)
5469 goto err_setup_tx;
5470
9a799d71
AK		 5471 /* allocate receive descriptors */
5472 err = ixgbe_setup_all_rx_resources(adapter);
5473 if (err)
5474 goto err_setup_rx;
5475
5476 ixgbe_configure(adapter);
5477
021230d4 5478 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5479 if (err)
5480 goto err_req_irq;
5481
ac802f5d 5482 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5483 if (adapter->num_rx_pools > 1)
5484 queues = adapter->num_rx_queues_per_pool;
5485 else
5486 queues = adapter->num_tx_queues;
5487
5488 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5489 if (err)
5490 goto err_set_queues;
5491
2a47fa45
JF		 5492 if (adapter->num_rx_pools > 1 &&
5493 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5494 queues = IXGBE_MAX_L2A_QUEUES;
5495 else
5496 queues = adapter->num_rx_queues;
5497 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5498 if (err)
5499 goto err_set_queues;
5500
1a71ab24 5501 ixgbe_ptp_init(adapter);
1a71ab24 5502
c7ccde0f 5503 ixgbe_up_complete(adapter);
9a799d71
AK		 5504
5505 return 0;
5506
ac802f5d
AD		 5507err_set_queues:
5508 ixgbe_free_irq(adapter);
9a799d71 5509err_req_irq:
a20a1199 5510 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5511err_setup_rx:
a20a1199 5512 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5513err_setup_tx:
9a799d71
AK		 5514 ixgbe_reset(adapter);
5515
5516 return err;
5517}
5518
5519/**
5520 * ixgbe_close - Disables a network interface
5521 * @netdev: network interface device structure
5522 *
5523 * Returns 0, this is not allowed to fail
5524 *
5525 * The close entry point is called when an interface is de-activated
5526 * by the OS. The hardware is still under the drivers control, but
5527 * needs to be disabled. A global MAC reset is issued to stop the
5528 * hardware, and all transmit and receive resources are freed.
5529 **/
5530static int ixgbe_close(struct net_device *netdev)
5531{
5532 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5533
1a71ab24 5534 ixgbe_ptp_stop(adapter);
1a71ab24 5535
9a799d71
AK		 5536 ixgbe_down(adapter);
5537 ixgbe_free_irq(adapter);
5538
e4911d57
AD		 5539 ixgbe_fdir_filter_exit(adapter);
5540
9a799d71
AK		 5541 ixgbe_free_all_tx_resources(adapter);
5542 ixgbe_free_all_rx_resources(adapter);
5543
5eba3699 5544 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5545
5546 return 0;
5547}
5548
b3c8b4ba
AD		 5549#ifdef CONFIG_PM
5550static int ixgbe_resume(struct pci_dev *pdev)
5551{
c60fbb00
AD		 5552 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5553 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5554 u32 err;
5555
0391bbe3 5556 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5557 pci_set_power_state(pdev, PCI_D0);
5558 pci_restore_state(pdev);
656ab817
DS		 5559 /*
5560 * pci_restore_state clears dev->state_saved so call
5561 * pci_save_state to restore it.
5562 */
5563 pci_save_state(pdev);
9ce77666 5564
5565 err = pci_enable_device_mem(pdev);
b3c8b4ba 5566 if (err) {
849c4542 5567 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5568 return err;
5569 }
41c62843
MR		 5570 smp_mb__before_clear_bit();
5571 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5572 pci_set_master(pdev);
5573
dd4d8ca6 5574 pci_wake_from_d3(pdev, false);
b3c8b4ba 5575
b3c8b4ba
AD		 5576 ixgbe_reset(adapter);
5577
495dce12
WJP		 5578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5579
ac802f5d
AD		 5580 rtnl_lock();
5581 err = ixgbe_init_interrupt_scheme(adapter);
5582 if (!err && netif_running(netdev))
c60fbb00 5583 err = ixgbe_open(netdev);
ac802f5d
AD		 5584
5585 rtnl_unlock();
5586
5587 if (err)
5588 return err;
b3c8b4ba
AD		 5589
5590 netif_device_attach(netdev);
5591
5592 return 0;
5593}
b3c8b4ba 5594#endif /* CONFIG_PM */
9d8d05ae
RW		 5595
5596static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5597{
c60fbb00
AD		 5598 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5599 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5600 struct ixgbe_hw *hw = &adapter->hw;
5601 u32 ctrl, fctrl;
5602 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5603#ifdef CONFIG_PM
5604 int retval = 0;
5605#endif
5606
5607 netif_device_detach(netdev);
5608
499ab5cc 5609 rtnl_lock();
b3c8b4ba
AD		 5610 if (netif_running(netdev)) {
5611 ixgbe_down(adapter);
5612 ixgbe_free_irq(adapter);
5613 ixgbe_free_all_tx_resources(adapter);
5614 ixgbe_free_all_rx_resources(adapter);
5615 }
499ab5cc 5616 rtnl_unlock();
b3c8b4ba 5617
5f5ae6fc
AD		 5618 ixgbe_clear_interrupt_scheme(adapter);
5619
b3c8b4ba
AD		 5620#ifdef CONFIG_PM
5621 retval = pci_save_state(pdev);
5622 if (retval)
5623 return retval;
4df10466 5624
b3c8b4ba 5625#endif
f4f1040a
JK		 5626 if (hw->mac.ops.stop_link_on_d3)
5627 hw->mac.ops.stop_link_on_d3(hw);
5628
e8e26350
PW		 5629 if (wufc) {
5630 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5631
ec74a471
ET		 5632 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5633 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5634 hw->mac.ops.enable_tx_laser(hw);
5635
e8e26350
PW		 5636 /* turn on all-multi mode if wake on multicast is enabled */
5637 if (wufc & IXGBE_WUFC_MC) {
5638 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5639 fctrl |= IXGBE_FCTRL_MPE;
5640 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5641 }
5642
5643 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5644 ctrl |= IXGBE_CTRL_GIO_DIS;
5645 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5646
5647 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5648 } else {
5649 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5650 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5651 }
5652
bd508178
AD		 5653 switch (hw->mac.type) {
5654 case ixgbe_mac_82598EB:
dd4d8ca6 5655 pci_wake_from_d3(pdev, false);
bd508178
AD		 5656 break;
5657 case ixgbe_mac_82599EB:
b93a2226 5658 case ixgbe_mac_X540:
bd508178
AD		 5659 pci_wake_from_d3(pdev, !!wufc);
5660 break;
5661 default:
5662 break;
5663 }
b3c8b4ba 5664
9d8d05ae
RW		 5665 *enable_wake = !!wufc;
5666
b3c8b4ba
AD		 5667 ixgbe_release_hw_control(adapter);
5668
41c62843
MR		 5669 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5670 pci_disable_device(pdev);
b3c8b4ba 5671
9d8d05ae
RW		 5672 return 0;
5673}
5674
5675#ifdef CONFIG_PM
5676static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5677{
5678 int retval;
5679 bool wake;
5680
5681 retval = __ixgbe_shutdown(pdev, &wake);
5682 if (retval)
5683 return retval;
5684
5685 if (wake) {
5686 pci_prepare_to_sleep(pdev);
5687 } else {
5688 pci_wake_from_d3(pdev, false);
5689 pci_set_power_state(pdev, PCI_D3hot);
5690 }
b3c8b4ba
AD		 5691
5692 return 0;
5693}
9d8d05ae 5694#endif /* CONFIG_PM */
b3c8b4ba
AD		 5695
5696static void ixgbe_shutdown(struct pci_dev *pdev)
5697{
9d8d05ae
RW		 5698 bool wake;
5699
5700 __ixgbe_shutdown(pdev, &wake);
5701
5702 if (system_state == SYSTEM_POWER_OFF) {
5703 pci_wake_from_d3(pdev, wake);
5704 pci_set_power_state(pdev, PCI_D3hot);
5705 }
b3c8b4ba
AD		 5706}
5707
9a799d71
AK		 5708/**
5709 * ixgbe_update_stats - Update the board statistics counters.
5710 * @adapter: board private structure
5711 **/
5712void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5713{
2d86f139 5714 struct net_device *netdev = adapter->netdev;
9a799d71 5715 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5716 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5717 u64 total_mpc = 0;
5718 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5719 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5720 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5721 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5722
d08935c2
DS		 5723 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5724 test_bit(__IXGBE_RESETTING, &adapter->state))
5725 return;
5726
94b982b2 5727 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5728 u64 rsc_count = 0;
94b982b2 5729 u64 rsc_flush = 0;
94b982b2 5730 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5731 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5732 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5733 }
5734 adapter->rsc_total_count = rsc_count;
5735 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5736 }
5737
5b7da515
AD		 5738 for (i = 0; i < adapter->num_rx_queues; i++) {
5739 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5740 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5741 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5742 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5743 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5744 bytes += rx_ring->stats.bytes;
5745 packets += rx_ring->stats.packets;
5746 }
5747 adapter->non_eop_descs = non_eop_descs;
5748 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5749 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5750 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5751 netdev->stats.rx_bytes = bytes;
5752 netdev->stats.rx_packets = packets;
5753
5754 bytes = 0;
5755 packets = 0;
7ca3bc58 5756 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5757 for (i = 0; i < adapter->num_tx_queues; i++) {
5758 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5759 restart_queue += tx_ring->tx_stats.restart_queue;
5760 tx_busy += tx_ring->tx_stats.tx_busy;
5761 bytes += tx_ring->stats.bytes;
5762 packets += tx_ring->stats.packets;
5763 }
eb985f09 5764 adapter->restart_queue = restart_queue;
5b7da515
AD		 5765 adapter->tx_busy = tx_busy;
5766 netdev->stats.tx_bytes = bytes;
5767 netdev->stats.tx_packets = packets;
7ca3bc58 5768
7ca647bd 5769 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5770
5771 /* 8 register reads */
6f11eef7
AV		 5772 for (i = 0; i < 8; i++) {
5773 /* for packet buffers not used, the register should read 0 */
5774 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5775 missed_rx += mpc;
7ca647bd
JP		 5776 hwstats->mpc[i] += mpc;
5777 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5778 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5779 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5780 switch (hw->mac.type) {
5781 case ixgbe_mac_82598EB:
1a70db4b
ET		 5782 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5783 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5784 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5785 hwstats->pxonrxc[i] +=
5786 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5787 break;
5788 case ixgbe_mac_82599EB:
b93a2226 5789 case ixgbe_mac_X540:
bd508178
AD		 5790 hwstats->pxonrxc[i] +=
5791 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5792 break;
5793 default:
5794 break;
e8e26350 5795 }
6f11eef7 5796 }
1a70db4b
ET		 5797
5798 /*16 register reads */
5799 for (i = 0; i < 16; i++) {
5800 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5801 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5802 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5803 (hw->mac.type == ixgbe_mac_X540)) {
5804 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5805 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5806 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5807 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5808 }
5809 }
5810
7ca647bd 5811 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5812 /* work around hardware counting issue */
7ca647bd 5813 hwstats->gprc -= missed_rx;
6f11eef7 5814
c84d324c
JF		 5815 ixgbe_update_xoff_received(adapter);
5816
6f11eef7 5817 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5818 switch (hw->mac.type) {
5819 case ixgbe_mac_82598EB:
5820 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5821 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5822 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5823 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5824 break;
b93a2226 5825 case ixgbe_mac_X540:
58f6bcf9
ET		 5826 /* OS2BMC stats are X540 only*/
5827 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5828 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5829 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5830 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5831 case ixgbe_mac_82599EB:
a4d4f629
AD		 5832 for (i = 0; i < 16; i++)
5833 adapter->hw_rx_no_dma_resources +=
5834 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5835 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5836 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5837 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5838 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5839 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5840 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5841 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5842 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5843 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5844#ifdef IXGBE_FCOE
7ca647bd
JP		 5845 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5846 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5847 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5848 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5849 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5850 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5851 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5852 if (adapter->fcoe.ddp_pool) {
5853 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5854 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5855 unsigned int cpu;
5856 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5857 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5858 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5859 noddp += ddp_pool->noddp;
5860 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5861 }
5a1ee270
AD		 5862 hwstats->fcoe_noddp = noddp;
5863 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5864 }
6d45522c 5865#endif /* IXGBE_FCOE */
bd508178
AD		 5866 break;
5867 default:
5868 break;
e8e26350 5869 }
9a799d71 5870 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5871 hwstats->bprc += bprc;
5872 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5873 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5874 hwstats->mprc -= bprc;
5875 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5876 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5877 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5878 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5879 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5880 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5881 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5882 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5883 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5884 hwstats->lxontxc += lxon;
6f11eef7 5885 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5886 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5887 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5888 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5889 /*
5890 * 82598 errata - tx of flow control packets is included in tx counters
5891 */
5892 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5893 hwstats->gptc -= xon_off_tot;
5894 hwstats->mptc -= xon_off_tot;
5895 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5896 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5897 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5898 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5899 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5900 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5901 hwstats->ptc64 -= xon_off_tot;
5902 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5903 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5904 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5905 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5906 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5907 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5908
5909 /* Fill out the OS statistics structure */
7ca647bd 5910 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5911
5912 /* Rx Errors */
7ca647bd 5913 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5914 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5915 netdev->stats.rx_length_errors = hwstats->rlec;
5916 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5917 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5918}
5919
5920/**
d034acf1 5921 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5922 * @adapter: pointer to the device adapter structure
9a799d71 5923 **/
d034acf1 5924static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5925{
cf8280ee 5926 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5927 int i;
cf8280ee 5928
d034acf1
AD		 5929 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5930 return;
5931
5932 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5933
d034acf1 5934 /* if interface is down do nothing */
fe49f04a 5935 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5936 return;
5937
5938 /* do nothing if we are not using signature filters */
5939 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5940 return;
5941
5942 adapter->fdir_overflow++;
5943
93c52dd0
AD		 5944 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5945 for (i = 0; i < adapter->num_tx_queues; i++)
5946 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5947 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5948 /* re-enable flow director interrupts */
5949 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5950 } else {
5951 e_err(probe, "failed to finish FDIR re-initialization, "
5952 "ignored adding FDIR ATR filters\n");
5953 }
93c52dd0
AD		 5954}
5955
5956/**
5957 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5958 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5959 *
5960 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5961 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5962 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5963 * determine if a hang has occurred.
93c52dd0
AD		 5964 */
5965static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5966{
cf8280ee 5967 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5968 u64 eics = 0;
5969 int i;
cf8280ee 5970
09f40aed 5971 /* If we're down, removing or resetting, just bail */
93c52dd0 5972 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 5973 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 5974 test_bit(__IXGBE_RESETTING, &adapter->state))
5975 return;
22d5a71b 5976
93c52dd0
AD		 5977 /* Force detection of hung controller */
5978 if (netif_carrier_ok(adapter->netdev)) {
5979 for (i = 0; i < adapter->num_tx_queues; i++)
5980 set_check_for_tx_hang(adapter->tx_ring[i]);
5981 }
22d5a71b 5982
fe49f04a
AD		 5983 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5984 /*
5985 * for legacy and MSI interrupts don't set any bits
5986 * that are enabled for EIAM, because this operation
5987 * would set *both* EIMS and EICS for any bit in EIAM
5988 */
5989 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5990 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5991 } else {
5992 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5993 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5994 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5995 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5996 eics |= ((u64)1 << i);
5997 }
cf8280ee 5998 }
9a799d71 5999
93c52dd0 6000 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6001 ixgbe_irq_rearm_queues(adapter, eics);
6002
cf8280ee
JB		 6003}
6004
e8e26350 6005/**
93c52dd0 6006 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6007 * @adapter: pointer to the device adapter structure
6008 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6009 **/
93c52dd0 6010static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6011{
e8e26350 6012 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6013 u32 link_speed = adapter->link_speed;
6014 bool link_up = adapter->link_up;
041441d0 6015 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6016
93c52dd0
AD		 6017 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6018 return;
6019
6020 if (hw->mac.ops.check_link) {
6021 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6022 } else {
93c52dd0
AD		 6023 /* always assume link is up, if no check link function */
6024 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6025 link_up = true;
c4cf55e5 6026 }
041441d0
AD		 6027
6028 if (adapter->ixgbe_ieee_pfc)
6029 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6030
3ebe8fde 6031 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6032 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6033 ixgbe_set_rx_drop_en(adapter);
6034 }
93c52dd0
AD		 6035
6036 if (link_up ||
6037 time_after(jiffies, (adapter->link_check_timeout +
6038 IXGBE_TRY_LINK_TIMEOUT))) {
6039 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6040 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6041 IXGBE_WRITE_FLUSH(hw);
6042 }
6043
6044 adapter->link_up = link_up;
6045 adapter->link_speed = link_speed;
e8e26350
PW		 6046}
6047
107d3018
AD		 6048static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6049{
6050#ifdef CONFIG_IXGBE_DCB
6051 struct net_device *netdev = adapter->netdev;
6052 struct dcb_app app = {
6053 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6054 .protocol = 0,
6055 };
6056 u8 up = 0;
6057
6058 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6059 up = dcb_ieee_getapp_mask(netdev, &app);
6060
6061 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6062#endif
6063}
6064
e8e26350 6065/**
93c52dd0
AD		 6066 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6067 * print link up message
49ce9c2c 6068 * @adapter: pointer to the device adapter structure
e8e26350 6069 **/
93c52dd0 6070static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6071{
93c52dd0 6072 struct net_device *netdev = adapter->netdev;
e8e26350 6073 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6074 struct net_device *upper;
6075 struct list_head *iter;
93c52dd0
AD		 6076 u32 link_speed = adapter->link_speed;
6077 bool flow_rx, flow_tx;
e8e26350 6078
93c52dd0
AD		 6079 /* only continue if link was previously down */
6080 if (netif_carrier_ok(netdev))
a985b6c3 6081 return;
63d6e1d8 6082
93c52dd0 6083 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6084
93c52dd0
AD		 6085 switch (hw->mac.type) {
6086 case ixgbe_mac_82598EB: {
6087 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6088 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6089 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6090 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6091 }
6092 break;
6093 case ixgbe_mac_X540:
6094 case ixgbe_mac_82599EB: {
6095 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6096 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6097 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6098 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6099 }
6100 break;
6101 default:
6102 flow_tx = false;
6103 flow_rx = false;
6104 break;
e8e26350 6105 }
3a6a4eda 6106
6cb562d6
JK		 6107 adapter->last_rx_ptp_check = jiffies;
6108
8fecf67c 6109 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6110 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6111
93c52dd0
AD		 6112 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6113 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6114 "10 Gbps" :
6115 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6116 "1 Gbps" :
6117 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6118 "100 Mbps" :
6119 "unknown speed"))),
6120 ((flow_rx && flow_tx) ? "RX/TX" :
6121 (flow_rx ? "RX" :
6122 (flow_tx ? "TX" : "None"))));
e8e26350 6123
93c52dd0 6124 netif_carrier_on(netdev);
93c52dd0 6125 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6126
cdc04dcc
ET		 6127 /* enable transmits */
6128 netif_tx_wake_all_queues(adapter->netdev);
6129
6130 /* enable any upper devices */
6131 rtnl_lock();
6132 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6133 if (netif_is_macvlan(upper)) {
6134 struct macvlan_dev *vlan = netdev_priv(upper);
6135
6136 if (vlan->fwd_priv)
6137 netif_tx_wake_all_queues(upper);
6138 }
6139 }
6140 rtnl_unlock();
6141
107d3018
AD		 6142 /* update the default user priority for VFs */
6143 ixgbe_update_default_up(adapter);
6144
befa2af7
AD		 6145 /* ping all the active vfs to let them know link has changed */
6146 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6147}
6148
c4cf55e5 6149/**
93c52dd0
AD		 6150 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6151 * print link down message
49ce9c2c 6152 * @adapter: pointer to the adapter structure
c4cf55e5 6153 **/
581330ba 6154static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6155{
cf8280ee 6156 struct net_device *netdev = adapter->netdev;
c4cf55e5 6157 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6158
93c52dd0
AD		 6159 adapter->link_up = false;
6160 adapter->link_speed = 0;
cf8280ee 6161
93c52dd0
AD		 6162 /* only continue if link was up previously */
6163 if (!netif_carrier_ok(netdev))
6164 return;
264857b8 6165
93c52dd0
AD		 6166 /* poll for SFP+ cable when link is down */
6167 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6168 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6169
8fecf67c 6170 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6171 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6172
93c52dd0
AD		 6173 e_info(drv, "NIC Link is Down\n");
6174 netif_carrier_off(netdev);
befa2af7
AD		 6175
6176 /* ping all the active vfs to let them know link has changed */
6177 ixgbe_ping_all_vfs(adapter);
93c52dd0 6178}
e8e26350 6179
93c52dd0
AD		 6180/**
6181 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6182 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6183 **/
6184static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6185{
c4cf55e5 6186 int i;
93c52dd0 6187 int some_tx_pending = 0;
c4cf55e5 6188
93c52dd0 6189 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6190 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6191 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6192 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6193 some_tx_pending = 1;
6194 break;
6195 }
6196 }
6197
6198 if (some_tx_pending) {
6199 /* We've lost link, so the controller stops DMA,
6200 * but we've got queued Tx work that's never going
6201 * to get done, so reset controller to flush Tx.
6202 * (Do the reset outside of interrupt context).
6203 */
12ff3f3b 6204 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6205 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6206 }
c4cf55e5 6207 }
c4cf55e5
PWJ		 6208}
6209
a985b6c3
GR		 6210static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6211{
6212 u32 ssvpc;
6213
0584d999
GR		 6214 /* Do not perform spoof check for 82598 or if not in IOV mode */
6215 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6216 adapter->num_vfs == 0)
a985b6c3
GR		 6217 return;
6218
6219 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6220
6221 /*
6222 * ssvpc register is cleared on read, if zero then no
6223 * spoofed packets in the last interval.
6224 */
6225 if (!ssvpc)
6226 return;
6227
d6ea0754 6228 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6229}
6230
93c52dd0
AD		 6231/**
6232 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6233 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6234 **/
6235static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6236{
09f40aed 6237 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6238 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6239 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6240 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6241 return;
6242
6243 ixgbe_watchdog_update_link(adapter);
6244
6245 if (adapter->link_up)
6246 ixgbe_watchdog_link_is_up(adapter);
6247 else
6248 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6249
a985b6c3 6250 ixgbe_spoof_check(adapter);
9a799d71 6251 ixgbe_update_stats(adapter);
93c52dd0
AD		 6252
6253 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6254}
10eec955 6255
cf8280ee 6256/**
7086400d 6257 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6258 * @adapter: the ixgbe adapter structure
cf8280ee 6259 **/
7086400d 6260static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6261{
cf8280ee 6262 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6263 s32 err;
cf8280ee 6264
7086400d
AD		 6265 /* not searching for SFP so there is nothing to do here */
6266 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6267 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6268 return;
10eec955 6269
7086400d
AD		 6270 /* someone else is in init, wait until next service event */
6271 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6272 return;
cf8280ee 6273
7086400d
AD		 6274 err = hw->phy.ops.identify_sfp(hw);
6275 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6276 goto sfp_out;
264857b8 6277
7086400d
AD		 6278 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6279 /* If no cable is present, then we need to reset
6280 * the next time we find a good cable. */
6281 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6282 }
9a799d71 6283
7086400d
AD		 6284 /* exit on error */
6285 if (err)
6286 goto sfp_out;
e8e26350 6287
7086400d
AD		 6288 /* exit if reset not needed */
6289 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6290 goto sfp_out;
9a799d71 6291
7086400d 6292 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6293
7086400d
AD		 6294 /*
6295 * A module may be identified correctly, but the EEPROM may not have
6296 * support for that module. setup_sfp() will fail in that case, so
6297 * we should not allow that module to load.
6298 */
6299 if (hw->mac.type == ixgbe_mac_82598EB)
6300 err = hw->phy.ops.reset(hw);
6301 else
6302 err = hw->mac.ops.setup_sfp(hw);
6303
6304 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6305 goto sfp_out;
6306
6307 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6308 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6309
6310sfp_out:
6311 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6312
6313 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6314 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6315 e_dev_err("failed to initialize because an unsupported "
6316 "SFP+ module type was detected.\n");
6317 e_dev_err("Reload the driver after installing a "
6318 "supported module.\n");
6319 unregister_netdev(adapter->netdev);
bc59fcda 6320 }
7086400d 6321}
bc59fcda 6322
7086400d
AD		 6323/**
6324 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6325 * @adapter: the ixgbe adapter structure
7086400d
AD		 6326 **/
6327static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6328{
6329 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6330 u32 speed;
6331 bool autoneg = false;
7086400d
AD		 6332
6333 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6334 return;
6335
6336 /* someone else is in init, wait until next service event */
6337 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6338 return;
6339
6340 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6341
3d292265 6342 speed = hw->phy.autoneg_advertised;
ed33ff66 6343 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6344 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6345
6346 /* setup the highest link when no autoneg */
6347 if (!autoneg) {
6348 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6349 speed = IXGBE_LINK_SPEED_10GB_FULL;
6350 }
6351 }
6352
7086400d 6353 if (hw->mac.ops.setup_link)
fd0326f2 6354 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6355
6356 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6357 adapter->link_check_timeout = jiffies;
6358 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6359}
6360
83c61fa9
GR		 6361#ifdef CONFIG_PCI_IOV
6362static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6363{
6364 int vf;
6365 struct ixgbe_hw *hw = &adapter->hw;
6366 struct net_device *netdev = adapter->netdev;
6367 u32 gpc;
6368 u32 ciaa, ciad;
6369
6370 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6371 if (gpc) /* If incrementing then no need for the check below */
6372 return;
6373 /*
6374 * Check to see if a bad DMA write target from an errant or
6375 * malicious VF has caused a PCIe error. If so then we can
6376 * issue a VFLR to the offending VF(s) and then resume without
6377 * requesting a full slot reset.
6378 */
6379
6380 for (vf = 0; vf < adapter->num_vfs; vf++) {
6381 ciaa = (vf << 16) | 0x80000000;
6382 /* 32 bit read so align, we really want status at offset 6 */
6383 ciaa |= PCI_COMMAND;
6384 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6385 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6386 ciaa &= 0x7FFFFFFF;
6387 /* disable debug mode asap after reading data */
6388 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6389 /* Get the upper 16 bits which will be the PCI status reg */
6390 ciad >>= 16;
6391 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6392 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6393 /* Issue VFLR */
6394 ciaa = (vf << 16) | 0x80000000;
6395 ciaa |= 0xA8;
6396 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6397 ciad = 0x00008000; /* VFLR */
6398 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6399 ciaa &= 0x7FFFFFFF;
6400 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6401 }
6402 }
6403}
6404
6405#endif
7086400d
AD		 6406/**
6407 * ixgbe_service_timer - Timer Call-back
6408 * @data: pointer to adapter cast into an unsigned long
6409 **/
6410static void ixgbe_service_timer(unsigned long data)
6411{
6412 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6413 unsigned long next_event_offset;
83c61fa9 6414 bool ready = true;
7086400d 6415
6bb78cfb
AD		 6416 /* poll faster when waiting for link */
6417 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6418 next_event_offset = HZ / 10;
6419 else
6420 next_event_offset = HZ * 2;
83c61fa9 6421
6bb78cfb 6422#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6423 /*
6424 * don't bother with SR-IOV VF DMA hang check if there are
6425 * no VFs or the link is down
6426 */
6427 if (!adapter->num_vfs ||
6bb78cfb 6428 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6429 goto normal_timer_service;
83c61fa9
GR		 6430
6431 /* If we have VFs allocated then we must check for DMA hangs */
6432 ixgbe_check_for_bad_vf(adapter);
6433 next_event_offset = HZ / 50;
6434 adapter->timer_event_accumulator++;
6435
6bb78cfb 6436 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6437 adapter->timer_event_accumulator = 0;
7086400d 6438 else
6bb78cfb 6439 ready = false;
7086400d 6440
6bb78cfb 6441normal_timer_service:
83c61fa9 6442#endif
7086400d
AD		 6443 /* Reset the timer */
6444 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6445
83c61fa9
GR		 6446 if (ready)
6447 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6448}
6449
c83c6cbd
AD		 6450static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6451{
6452 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6453 return;
6454
6455 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6456
09f40aed 6457 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6458 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6459 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6460 test_bit(__IXGBE_RESETTING, &adapter->state))
6461 return;
6462
6463 ixgbe_dump(adapter);
6464 netdev_err(adapter->netdev, "Reset adapter\n");
6465 adapter->tx_timeout_count++;
6466
8f4c5c9f 6467 rtnl_lock();
c83c6cbd 6468 ixgbe_reinit_locked(adapter);
8f4c5c9f 6469 rtnl_unlock();
c83c6cbd
AD		 6470}
6471
7086400d
AD		 6472/**
6473 * ixgbe_service_task - manages and runs subtasks
6474 * @work: pointer to work_struct containing our data
6475 **/
6476static void ixgbe_service_task(struct work_struct *work)
6477{
6478 struct ixgbe_adapter *adapter = container_of(work,
6479 struct ixgbe_adapter,
6480 service_task);
b0483c8f
MR		 6481 if (ixgbe_removed(adapter->hw.hw_addr)) {
6482 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6483 rtnl_lock();
6484 ixgbe_down(adapter);
6485 rtnl_unlock();
6486 }
6487 ixgbe_service_event_complete(adapter);
6488 return;
6489 }
c83c6cbd 6490 ixgbe_reset_subtask(adapter);
7086400d
AD		 6491 ixgbe_sfp_detection_subtask(adapter);
6492 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6493 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6494 ixgbe_watchdog_subtask(adapter);
d034acf1 6495 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6496 ixgbe_check_hang_subtask(adapter);
891dc082 6497
8fecf67c 6498 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6499 ixgbe_ptp_overflow_check(adapter);
6500 ixgbe_ptp_rx_hang(adapter);
6501 }
7086400d
AD		 6502
6503 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6504}
6505
fd0db0ed
AD		 6506static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6507 struct ixgbe_tx_buffer *first,
244e27ad 6508 u8 *hdr_len)
897ab156 6509{
fd0db0ed 6510 struct sk_buff *skb = first->skb;
897ab156
AD		 6511 u32 vlan_macip_lens, type_tucmd;
6512 u32 mss_l4len_idx, l4len;
2049e1f6 6513 int err;
9a799d71 6514
8f4fbb9b
AD		 6515 if (skb->ip_summed != CHECKSUM_PARTIAL)
6516 return 0;
6517
897ab156
AD		 6518 if (!skb_is_gso(skb))
6519 return 0;
9a799d71 6520
2049e1f6
FR		 6521 err = skb_cow_head(skb, 0);
6522 if (err < 0)
6523 return err;
9a799d71 6524
897ab156
AD		 6525 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6526 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6527
a1108ffd 6528 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6529 struct iphdr *iph = ip_hdr(skb);
6530 iph->tot_len = 0;
6531 iph->check = 0;
6532 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6533 iph->daddr, 0,
6534 IPPROTO_TCP,
6535 0);
6536 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6537 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6538 IXGBE_TX_FLAGS_CSUM |
6539 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6540 } else if (skb_is_gso_v6(skb)) {
6541 ipv6_hdr(skb)->payload_len = 0;
6542 tcp_hdr(skb)->check =
6543 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6544 &ipv6_hdr(skb)->daddr,
6545 0, IPPROTO_TCP, 0);
244e27ad
AD		 6546 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6547 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6548 }
6549
091a6246 6550 /* compute header lengths */
897ab156
AD		 6551 l4len = tcp_hdrlen(skb);
6552 *hdr_len = skb_transport_offset(skb) + l4len;
6553
091a6246
AD		 6554 /* update gso size and bytecount with header size */
6555 first->gso_segs = skb_shinfo(skb)->gso_segs;
6556 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6557
c44f5f51 6558 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6559 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6560 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6561
6562 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6563 vlan_macip_lens = skb_network_header_len(skb);
6564 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6565 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6566
6567 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6568 mss_l4len_idx);
897ab156
AD		 6569
6570 return 1;
6571}
6572
244e27ad
AD		 6573static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6574 struct ixgbe_tx_buffer *first)
7ca647bd 6575{
fd0db0ed 6576 struct sk_buff *skb = first->skb;
897ab156
AD		 6577 u32 vlan_macip_lens = 0;
6578 u32 mss_l4len_idx = 0;
6579 u32 type_tucmd = 0;
7ca647bd 6580
897ab156 6581 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6582 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6583 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6584 return;
897ab156
AD		 6585 } else {
6586 u8 l4_hdr = 0;
244e27ad 6587 switch (first->protocol) {
a1108ffd 6588 case htons(ETH_P_IP):
897ab156
AD		 6589 vlan_macip_lens |= skb_network_header_len(skb);
6590 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6591 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6592 break;
a1108ffd 6593 case htons(ETH_P_IPV6):
897ab156
AD		 6594 vlan_macip_lens |= skb_network_header_len(skb);
6595 l4_hdr = ipv6_hdr(skb)->nexthdr;
6596 break;
6597 default:
6598 if (unlikely(net_ratelimit())) {
6599 dev_warn(tx_ring->dev,
6600 "partial checksum but proto=%x!\n",
244e27ad 6601 first->protocol);
897ab156 6602 }
7ca647bd
JP		 6603 break;
6604 }
897ab156
AD		 6605
6606 switch (l4_hdr) {
7ca647bd 6607 case IPPROTO_TCP:
897ab156
AD		 6608 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6609 mss_l4len_idx = tcp_hdrlen(skb) <<
6610 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6611 break;
6612 case IPPROTO_SCTP:
897ab156
AD		 6613 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6614 mss_l4len_idx = sizeof(struct sctphdr) <<
6615 IXGBE_ADVTXD_L4LEN_SHIFT;
6616 break;
6617 case IPPROTO_UDP:
6618 mss_l4len_idx = sizeof(struct udphdr) <<
6619 IXGBE_ADVTXD_L4LEN_SHIFT;
6620 break;
6621 default:
6622 if (unlikely(net_ratelimit())) {
6623 dev_warn(tx_ring->dev,
6624 "partial checksum but l4 proto=%x!\n",
244e27ad 6625 l4_hdr);
897ab156 6626 }
7ca647bd
JP		 6627 break;
6628 }
244e27ad
AD		 6629
6630 /* update TX checksum flag */
6631 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6632 }
6633
244e27ad 6634 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6635 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6636 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6637
897ab156
AD		 6638 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6639 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6640}
6641
472148c3
AD		 6642#define IXGBE_SET_FLAG(_input, _flag, _result) \
6643 ((_flag <= _result) ? \
6644 ((u32)(_input & _flag) * (_result / _flag)) : \
6645 ((u32)(_input & _flag) / (_flag / _result)))
6646
6647static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6648{
d3d00239 6649 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6650 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6651 IXGBE_ADVTXD_DCMD_DEXT |
6652 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6653
d3d00239 6654 /* set HW vlan bit if vlan is present */
472148c3
AD		 6655 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6656 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6657
d3d00239 6658 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6659 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6660 IXGBE_ADVTXD_DCMD_TSE);
6661
6662 /* set timestamp bit if present */
6663 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6664 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6665
62748b7b 6666 /* insert frame checksum */
472148c3 6667 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6668
d3d00239
AD		 6669 return cmd_type;
6670}
9a799d71 6671
729739b7
AD		 6672static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6673 u32 tx_flags, unsigned int paylen)
d3d00239 6674{
472148c3 6675 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6676
d3d00239 6677 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6678 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6679 IXGBE_TX_FLAGS_CSUM,
6680 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6681
93f5b3c1 6682 /* enble IPv4 checksum for TSO */
472148c3
AD		 6683 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6684 IXGBE_TX_FLAGS_IPV4,
6685 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6686
7f9643fd
AD		 6687 /*
6688 * Check Context must be set if Tx switch is enabled, which it
6689 * always is for case where virtual functions are running
6690 */
472148c3
AD		 6691 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6692 IXGBE_TX_FLAGS_CC,
6693 IXGBE_ADVTXD_CC);
7f9643fd 6694
472148c3 6695 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6696}
44df32c5 6697
d3d00239
AD		 6698#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6699 IXGBE_TXD_CMD_RS)
6700
6701static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6702 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6703 const u8 hdr_len)
6704{
fd0db0ed 6705 struct sk_buff *skb = first->skb;
729739b7 6706 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6707 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6708 struct skb_frag_struct *frag;
6709 dma_addr_t dma;
6710 unsigned int data_len, size;
244e27ad 6711 u32 tx_flags = first->tx_flags;
472148c3 6712 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6713 u16 i = tx_ring->next_to_use;
d3d00239 6714
729739b7
AD		 6715 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6716
ec718254
AD		 6717 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6718
6719 size = skb_headlen(skb);
6720 data_len = skb->data_len;
729739b7 6721
d3d00239
AD		 6722#ifdef IXGBE_FCOE
6723 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6724 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6725 size -= sizeof(struct fcoe_crc_eof) - data_len;
6726 data_len = 0;
729739b7
AD		 6727 } else {
6728 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6729 }
6730 }
44df32c5 6731
d3d00239 6732#endif
729739b7 6733 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6734
ec718254 6735 tx_buffer = first;
9a799d71 6736
ec718254
AD		 6737 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6738 if (dma_mapping_error(tx_ring->dev, dma))
6739 goto dma_error;
6740
6741 /* record length, and DMA address */
6742 dma_unmap_len_set(tx_buffer, len, size);
6743 dma_unmap_addr_set(tx_buffer, dma, dma);
6744
6745 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6746
729739b7 6747 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6748 tx_desc->read.cmd_type_len =
472148c3 6749 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6750
d3d00239 6751 i++;
729739b7 6752 tx_desc++;
d3d00239 6753 if (i == tx_ring->count) {
e4f74028 6754 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6755 i = 0;
6756 }
ec718254 6757 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6758
6759 dma += IXGBE_MAX_DATA_PER_TXD;
6760 size -= IXGBE_MAX_DATA_PER_TXD;
6761
6762 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6763 }
e5a43549 6764
729739b7
AD		 6765 if (likely(!data_len))
6766 break;
9a799d71 6767
472148c3 6768 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6769
729739b7
AD		 6770 i++;
6771 tx_desc++;
6772 if (i == tx_ring->count) {
6773 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6774 i = 0;
6775 }
ec718254 6776 tx_desc->read.olinfo_status = 0;
9a799d71 6777
d3d00239 6778#ifdef IXGBE_FCOE
9e903e08 6779 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6780#else
9e903e08 6781 size = skb_frag_size(frag);
d3d00239
AD		 6782#endif
6783 data_len -= size;
9a799d71 6784
729739b7
AD		 6785 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6786 DMA_TO_DEVICE);
9a799d71 6787
729739b7 6788 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6789 }
9a799d71 6790
729739b7 6791 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6792 cmd_type |= size | IXGBE_TXD_CMD;
6793 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6794
091a6246 6795 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6796
d3d00239
AD		 6797 /* set the timestamp */
6798 first->time_stamp = jiffies;
9a799d71
AK		 6799
6800 /*
729739b7
AD		 6801 * Force memory writes to complete before letting h/w know there
6802 * are new descriptors to fetch. (Only applicable for weak-ordered
6803 * memory model archs, such as IA-64).
6804 *
6805 * We also need this memory barrier to make certain all of the
6806 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6807 */
6808 wmb();
6809
d3d00239
AD		 6810 /* set next_to_watch value indicating a packet is present */
6811 first->next_to_watch = tx_desc;
6812
729739b7
AD		 6813 i++;
6814 if (i == tx_ring->count)
6815 i = 0;
6816
6817 tx_ring->next_to_use = i;
6818
d3d00239 6819 /* notify HW of packet */
84227bcd 6820 ixgbe_write_tail(tx_ring, i);
d3d00239
AD		 6821
6822 return;
6823dma_error:
729739b7 6824 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6825
6826 /* clear dma mappings for failed tx_buffer_info map */
6827 for (;;) {
729739b7
AD		 6828 tx_buffer = &tx_ring->tx_buffer_info[i];
6829 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6830 if (tx_buffer == first)
d3d00239
AD		 6831 break;
6832 if (i == 0)
6833 i = tx_ring->count;
6834 i--;
6835 }
6836
d3d00239 6837 tx_ring->next_to_use = i;
9a799d71
AK		 6838}
6839
fd0db0ed 6840static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6841 struct ixgbe_tx_buffer *first)
69830529
AD		 6842{
6843 struct ixgbe_q_vector *q_vector = ring->q_vector;
6844 union ixgbe_atr_hash_dword input = { .dword = 0 };
6845 union ixgbe_atr_hash_dword common = { .dword = 0 };
6846 union {
6847 unsigned char *network;
6848 struct iphdr *ipv4;
6849 struct ipv6hdr *ipv6;
6850 } hdr;
ee9e0f0b 6851 struct tcphdr *th;
905e4a41 6852 __be16 vlan_id;
c4cf55e5 6853
69830529
AD		 6854 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6855 if (!q_vector)
6856 return;
6857
6858 /* do nothing if sampling is disabled */
6859 if (!ring->atr_sample_rate)
d3ead241 6860 return;
c4cf55e5 6861
69830529 6862 ring->atr_count++;
c4cf55e5 6863
69830529 6864 /* snag network header to get L4 type and address */
fd0db0ed 6865 hdr.network = skb_network_header(first->skb);
69830529
AD		 6866
6867 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 6868 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 6869 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 6870 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 6871 hdr.ipv4->protocol != IPPROTO_TCP))
6872 return;
ee9e0f0b 6873
fd0db0ed 6874 th = tcp_hdr(first->skb);
c4cf55e5 6875
66f32a8b
AD		 6876 /* skip this packet since it is invalid or the socket is closing */
6877 if (!th || th->fin)
69830529
AD		 6878 return;
6879
6880 /* sample on all syn packets or once every atr sample count */
6881 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6882 return;
6883
6884 /* reset sample count */
6885 ring->atr_count = 0;
6886
244e27ad 6887 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6888
6889 /*
6890 * src and dst are inverted, think how the receiver sees them
6891 *
6892 * The input is broken into two sections, a non-compressed section
6893 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6894 * is XORed together and stored in the compressed dword.
6895 */
6896 input.formatted.vlan_id = vlan_id;
6897
6898 /*
6899 * since src port and flex bytes occupy the same word XOR them together
6900 * and write the value to source port portion of compressed dword
6901 */
244e27ad 6902 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 6903 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 6904 else
244e27ad 6905 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6906 common.port.dst ^= th->source;
6907
a1108ffd 6908 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 6909 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6910 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6911 } else {
6912 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6913 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6914 hdr.ipv6->saddr.s6_addr32[1] ^
6915 hdr.ipv6->saddr.s6_addr32[2] ^
6916 hdr.ipv6->saddr.s6_addr32[3] ^
6917 hdr.ipv6->daddr.s6_addr32[0] ^
6918 hdr.ipv6->daddr.s6_addr32[1] ^
6919 hdr.ipv6->daddr.s6_addr32[2] ^
6920 hdr.ipv6->daddr.s6_addr32[3];
6921 }
c4cf55e5
PWJ		 6922
6923 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6924 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6925 input, common, ring->queue_index);
c4cf55e5
PWJ		 6926}
6927
63544e9c 6928static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6929{
fc77dc3c 6930 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6931 /* Herbert's original patch had:
6932 * smp_mb__after_netif_stop_queue();
6933 * but since that doesn't exist yet, just open code it. */
6934 smp_mb();
6935
6936 /* We need to check again in a case another CPU has just
6937 * made room available. */
7d4987de 6938 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6939 return -EBUSY;
6940
6941 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6942 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6943 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6944 return 0;
6945}
6946
82d4e46e 6947static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6948{
7d4987de 6949 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6950 return 0;
fc77dc3c 6951 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6952}
6953
f663dd9a 6954static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 6955 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 6956{
f663dd9a
JW		 6957 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
6958#ifdef IXGBE_FCOE
97488bd1
AD		 6959 struct ixgbe_adapter *adapter;
6960 struct ixgbe_ring_feature *f;
6961 int txq;
f663dd9a
JW		 6962#endif
6963
6964 if (fwd_adapter)
6965 return skb->queue_mapping + fwd_adapter->tx_base_queue;
6966
6967#ifdef IXGBE_FCOE
5e09a105 6968
97488bd1
AD		 6969 /*
6970 * only execute the code below if protocol is FCoE
6971 * or FIP and we have FCoE enabled on the adapter
6972 */
6973 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 6974 case htons(ETH_P_FCOE):
6975 case htons(ETH_P_FIP):
97488bd1 6976 adapter = netdev_priv(dev);
c087663e 6977
97488bd1
AD		 6978 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6979 break;
6980 default:
99932d4f 6981 return fallback(dev, skb);
97488bd1 6982 }
c087663e 6983
97488bd1 6984 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6985
97488bd1
AD		 6986 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6987 smp_processor_id();
56075a98 6988
97488bd1
AD		 6989 while (txq >= f->indices)
6990 txq -= f->indices;
c4cf55e5 6991
97488bd1 6992 return txq + f->offset;
f663dd9a 6993#else
99932d4f 6994 return fallback(dev, skb);
f663dd9a 6995#endif
09a3b1f8
SH		 6996}
6997
fc77dc3c 6998netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6999 struct ixgbe_adapter *adapter,
7000 struct ixgbe_ring *tx_ring)
9a799d71 7001{
d3d00239 7002 struct ixgbe_tx_buffer *first;
5f715823 7003 int tso;
d3d00239 7004 u32 tx_flags = 0;
a535c30e 7005 unsigned short f;
a535c30e 7006 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7007 __be16 protocol = skb->protocol;
63544e9c 7008 u8 hdr_len = 0;
5e09a105 7009
a535c30e
AD		 7010 /*
7011 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7012 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7013 * + 2 desc gap to keep tail from touching head,
7014 * + 1 desc for context descriptor,
7015 * otherwise try next time
7016 */
a535c30e
AD		 7017 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7018 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7019
a535c30e
AD		 7020 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7021 tx_ring->tx_stats.tx_busy++;
7022 return NETDEV_TX_BUSY;
7023 }
7024
fd0db0ed
AD		 7025 /* record the location of the first descriptor for this packet */
7026 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7027 first->skb = skb;
091a6246
AD		 7028 first->bytecount = skb->len;
7029 first->gso_segs = 1;
fd0db0ed 7030
66f32a8b 7031 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7032 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7033 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7034 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7035 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7036 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7037 struct vlan_hdr *vhdr, _vhdr;
7038 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7039 if (!vhdr)
7040 goto out_drop;
7041
7042 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7043 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7044 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7045 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7046 }
7047
151b260c
JK		 7048 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
7049 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7050 &adapter->state))) {
3a6a4eda
JK		 7051 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7052 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7053
7054 /* schedule check for Tx timestamp */
7055 adapter->ptp_tx_skb = skb_get(skb);
7056 adapter->ptp_tx_start = jiffies;
7057 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7058 }
3a6a4eda 7059
ff29a86e
JK		 7060 skb_tx_timestamp(skb);
7061
9e0c5648
AD		 7062#ifdef CONFIG_PCI_IOV
7063 /*
7064 * Use the l2switch_enable flag - would be false if the DMA
7065 * Tx switch had been disabled.
7066 */
7067 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7068 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7069
7070#endif
32701dc2 7071 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7072 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7073 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7074 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7075 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7076 tx_flags |= (skb->priority & 0x7) <<
7077 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7078 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7079 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7080
7081 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7082 goto out_drop;
7083 vhdr = (struct vlan_ethhdr *)skb->data;
7084 vhdr->h_vlan_TCI = htons(tx_flags >>
7085 IXGBE_TX_FLAGS_VLAN_SHIFT);
7086 } else {
7087 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7088 }
9a799d71 7089 }
eacd73f7 7090
244e27ad
AD		 7091 /* record initial flags and protocol */
7092 first->tx_flags = tx_flags;
7093 first->protocol = protocol;
7094
eacd73f7 7095#ifdef IXGBE_FCOE
66f32a8b 7096 /* setup tx offload for FCoE */
a1108ffd 7097 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7098 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7099 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7100 if (tso < 0)
7101 goto out_drop;
9a799d71 7102
66f32a8b 7103 goto xmit_fcoe;
eacd73f7 7104 }
9a799d71 7105
66f32a8b 7106#endif /* IXGBE_FCOE */
244e27ad 7107 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7108 if (tso < 0)
897ab156 7109 goto out_drop;
244e27ad
AD		 7110 else if (!tso)
7111 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7112
7113 /* add the ATR filter if ATR is on */
7114 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7115 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7116
7117#ifdef IXGBE_FCOE
7118xmit_fcoe:
7119#endif /* IXGBE_FCOE */
244e27ad 7120 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 7121
7122 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7123
7124 return NETDEV_TX_OK;
897ab156
AD		 7125
7126out_drop:
fd0db0ed
AD		 7127 dev_kfree_skb_any(first->skb);
7128 first->skb = NULL;
7129
897ab156 7130 return NETDEV_TX_OK;
9a799d71
AK		 7131}
7132
2a47fa45
JF		 7133static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7134 struct net_device *netdev,
7135 struct ixgbe_ring *ring)
84418e3b
AD		 7136{
7137 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7138 struct ixgbe_ring *tx_ring;
7139
a50c29dd
AD		 7140 /*
7141 * The minimum packet size for olinfo paylen is 17 so pad the skb
7142 * in order to meet this minimum size requirement.
7143 */
f73332fc
SH		 7144 if (unlikely(skb->len < 17)) {
7145 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7146 return NETDEV_TX_OK;
7147 skb->len = 17;
71a49f77 7148 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7149 }
7150
2a47fa45
JF		 7151 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7152
fc77dc3c 7153 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7154}
7155
2a47fa45
JF		 7156static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7157 struct net_device *netdev)
7158{
7159 return __ixgbe_xmit_frame(skb, netdev, NULL);
7160}
7161
9a799d71
AK		 7162/**
7163 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7164 * @netdev: network interface device structure
7165 * @p: pointer to an address structure
7166 *
7167 * Returns 0 on success, negative on failure
7168 **/
7169static int ixgbe_set_mac(struct net_device *netdev, void *p)
7170{
7171 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7172 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7173 struct sockaddr *addr = p;
7174
7175 if (!is_valid_ether_addr(addr->sa_data))
7176 return -EADDRNOTAVAIL;
7177
7178 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7179 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7180
1d9c0bfd 7181 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 7182
7183 return 0;
7184}
7185
6b73e10d
BH		 7186static int
7187ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7188{
7189 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7190 struct ixgbe_hw *hw = &adapter->hw;
7191 u16 value;
7192 int rc;
7193
7194 if (prtad != hw->phy.mdio.prtad)
7195 return -EINVAL;
7196 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7197 if (!rc)
7198 rc = value;
7199 return rc;
7200}
7201
7202static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7203 u16 addr, u16 value)
7204{
7205 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7206 struct ixgbe_hw *hw = &adapter->hw;
7207
7208 if (prtad != hw->phy.mdio.prtad)
7209 return -EINVAL;
7210 return hw->phy.ops.write_reg(hw, addr, devad, value);
7211}
7212
7213static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7214{
7215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7216
3a6a4eda 7217 switch (cmd) {
3a6a4eda 7218 case SIOCSHWTSTAMP:
93501d48
JK		 7219 return ixgbe_ptp_set_ts_config(adapter, req);
7220 case SIOCGHWTSTAMP:
7221 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7222 default:
7223 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7224 }
6b73e10d
BH		 7225}
7226
0365e6e4
PW		 7227/**
7228 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7229 * netdev->dev_addrs
0365e6e4
PW		 7230 * @netdev: network interface device structure
7231 *
7232 * Returns non-zero on failure
7233 **/
7234static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7235{
7236 int err = 0;
7237 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7238 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7239
7fa7c9dc 7240 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7241 rtnl_lock();
7fa7c9dc 7242 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7243 rtnl_unlock();
7fa7c9dc
AD		 7244
7245 /* update SAN MAC vmdq pool selection */
7246 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7247 }
7248 return err;
7249}
7250
7251/**
7252 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7253 * netdev->dev_addrs
0365e6e4
PW		 7254 * @netdev: network interface device structure
7255 *
7256 * Returns non-zero on failure
7257 **/
7258static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7259{
7260 int err = 0;
7261 struct ixgbe_adapter *adapter = netdev_priv(dev);
7262 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7263
7264 if (is_valid_ether_addr(mac->san_addr)) {
7265 rtnl_lock();
7266 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7267 rtnl_unlock();
7268 }
7269 return err;
7270}
7271
9a799d71
AK		 7272#ifdef CONFIG_NET_POLL_CONTROLLER
7273/*
7274 * Polling 'interrupt' - used by things like netconsole to send skbs
7275 * without having to re-enable interrupts. It's not called while
7276 * the interrupt routine is executing.
7277 */
7278static void ixgbe_netpoll(struct net_device *netdev)
7279{
7280 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7281 int i;
9a799d71 7282
1a647bd2
AD		 7283 /* if interface is down do nothing */
7284 if (test_bit(__IXGBE_DOWN, &adapter->state))
7285 return;
7286
9a799d71 7287 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7288 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7289 for (i = 0; i < adapter->num_q_vectors; i++)
7290 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7291 } else {
7292 ixgbe_intr(adapter->pdev->irq, netdev);
7293 }
9a799d71 7294 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7295}
9a799d71 7296
581330ba 7297#endif
de1036b1
ED		 7298static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7299 struct rtnl_link_stats64 *stats)
7300{
7301 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7302 int i;
7303
1a51502b 7304 rcu_read_lock();
de1036b1 7305 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7306 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7307 u64 bytes, packets;
7308 unsigned int start;
7309
1a51502b
ED		 7310 if (ring) {
7311 do {
57a7744e 7312 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7313 packets = ring->stats.packets;
7314 bytes = ring->stats.bytes;
57a7744e 7315 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7316 stats->rx_packets += packets;
7317 stats->rx_bytes += bytes;
7318 }
de1036b1 7319 }
1ac9ad13
ED		 7320
7321 for (i = 0; i < adapter->num_tx_queues; i++) {
7322 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7323 u64 bytes, packets;
7324 unsigned int start;
7325
7326 if (ring) {
7327 do {
57a7744e 7328 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7329 packets = ring->stats.packets;
7330 bytes = ring->stats.bytes;
57a7744e 7331 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7332 stats->tx_packets += packets;
7333 stats->tx_bytes += bytes;
7334 }
7335 }
1a51502b 7336 rcu_read_unlock();
de1036b1
ED		 7337 /* following stats updated by ixgbe_watchdog_task() */
7338 stats->multicast = netdev->stats.multicast;
7339 stats->rx_errors = netdev->stats.rx_errors;
7340 stats->rx_length_errors = netdev->stats.rx_length_errors;
7341 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7342 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7343 return stats;
7344}
7345
8af3c33f 7346#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7347/**
7348 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7349 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7350 * @tc: number of traffic classes currently enabled
7351 *
7352 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7353 * 802.1Q priority maps to a packet buffer that exists.
7354 */
7355static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7356{
7357 struct ixgbe_hw *hw = &adapter->hw;
7358 u32 reg, rsave;
7359 int i;
7360
7361 /* 82598 have a static priority to TC mapping that can not
7362 * be changed so no validation is needed.
7363 */
7364 if (hw->mac.type == ixgbe_mac_82598EB)
7365 return;
7366
7367 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7368 rsave = reg;
7369
7370 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7371 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7372
7373 /* If up2tc is out of bounds default to zero */
7374 if (up2tc > tc)
7375 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7376 }
7377
7378 if (reg != rsave)
7379 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7380
7381 return;
7382}
7383
02debdc9
AD		 7384/**
7385 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7386 * @adapter: Pointer to adapter struct
7387 *
7388 * Populate the netdev user priority to tc map
7389 */
7390static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7391{
7392 struct net_device *dev = adapter->netdev;
7393 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7394 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7395 u8 prio;
7396
7397 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7398 u8 tc = 0;
7399
7400 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7401 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7402 else if (ets)
7403 tc = ets->prio_tc[prio];
7404
7405 netdev_set_prio_tc_map(dev, prio, tc);
7406 }
7407}
7408
cca73c59 7409#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7410/**
7411 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7412 *
7413 * @netdev: net device to configure
7414 * @tc: number of traffic classes to enable
7415 */
7416int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7417{
8b1c0b24
JF		 7418 struct ixgbe_adapter *adapter = netdev_priv(dev);
7419 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7420 bool pools;
8b1c0b24 7421
8b1c0b24 7422 /* Hardware supports up to 8 traffic classes */
4de2a022 7423 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7424 (hw->mac.type == ixgbe_mac_82598EB &&
7425 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7426 return -EINVAL;
7427
2a47fa45
JF		 7428 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7429 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7430 return -EBUSY;
7431
8b1c0b24 7432 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7433 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7434 * hardware is not flexible enough to do this dynamically.
7435 */
7436 if (netif_running(dev))
7437 ixgbe_close(dev);
7438 ixgbe_clear_interrupt_scheme(adapter);
7439
cca73c59 7440#ifdef CONFIG_IXGBE_DCB
e7589eab 7441 if (tc) {
8b1c0b24 7442 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7443 ixgbe_set_prio_tc_map(adapter);
7444
e7589eab 7445 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7446
943561d3
AD		 7447 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7448 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7449 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7450 }
e7589eab 7451 } else {
8b1c0b24 7452 netdev_reset_tc(dev);
02debdc9 7453
943561d3
AD		 7454 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7455 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7456
7457 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7458
7459 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7460 adapter->dcb_cfg.pfc_mode_enable = false;
7461 }
7462
8b1c0b24 7463 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7464
7465#endif /* CONFIG_IXGBE_DCB */
7466 ixgbe_init_interrupt_scheme(adapter);
7467
8b1c0b24 7468 if (netif_running(dev))
cca73c59 7469 return ixgbe_open(dev);
8b1c0b24
JF		 7470
7471 return 0;
7472}
de1036b1 7473
da36b647
GR		 7474#ifdef CONFIG_PCI_IOV
7475void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7476{
7477 struct net_device *netdev = adapter->netdev;
7478
7479 rtnl_lock();
da36b647 7480 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7481 rtnl_unlock();
7482}
7483
7484#endif
082757af
DS		 7485void ixgbe_do_reset(struct net_device *netdev)
7486{
7487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7488
7489 if (netif_running(netdev))
7490 ixgbe_reinit_locked(adapter);
7491 else
7492 ixgbe_reset(adapter);
7493}
7494
c8f44aff 7495static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7496 netdev_features_t features)
082757af
DS		 7497{
7498 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7499
082757af 7500 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7501 if (!(features & NETIF_F_RXCSUM))
7502 features &= ~NETIF_F_LRO;
082757af 7503
567d2de2
AD		 7504 /* Turn off LRO if not RSC capable */
7505 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7506 features &= ~NETIF_F_LRO;
8e2813f5 7507
567d2de2 7508 return features;
082757af
DS		 7509}
7510
c8f44aff 7511static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7512 netdev_features_t features)
082757af
DS		 7513{
7514 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7515 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7516 bool need_reset = false;
7517
082757af 7518 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7519 if (!(features & NETIF_F_LRO)) {
7520 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7521 need_reset = true;
567d2de2
AD		 7522 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7523 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7524 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7525 if (adapter->rx_itr_setting == 1 ||
7526 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7527 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7528 need_reset = true;
7529 } else if ((changed ^ features) & NETIF_F_LRO) {
7530 e_info(probe, "rx-usecs set too low, "
7531 "disabling RSC\n");
082757af
DS		 7532 }
7533 }
7534
7535 /*
7536 * Check if Flow Director n-tuple support was enabled or disabled. If
7537 * the state changed, we need to reset.
7538 */
39cb681b
AD		 7539 switch (features & NETIF_F_NTUPLE) {
7540 case NETIF_F_NTUPLE:
567d2de2 7541 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7542 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7543 need_reset = true;
7544
567d2de2
AD		 7545 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7546 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7547 break;
7548 default:
7549 /* turn off perfect filters, enable ATR and reset */
7550 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7551 need_reset = true;
7552
7553 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7554
7555 /* We cannot enable ATR if SR-IOV is enabled */
7556 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7557 break;
7558
7559 /* We cannot enable ATR if we have 2 or more traffic classes */
7560 if (netdev_get_num_tc(netdev) > 1)
7561 break;
7562
7563 /* We cannot enable ATR if RSS is disabled */
7564 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7565 break;
7566
7567 /* A sample rate of 0 indicates ATR disabled */
7568 if (!adapter->atr_sample_rate)
7569 break;
7570
7571 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7572 break;
082757af
DS		 7573 }
7574
f646968f 7575 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7576 ixgbe_vlan_strip_enable(adapter);
7577 else
7578 ixgbe_vlan_strip_disable(adapter);
7579
3f2d1c0f
BG		 7580 if (changed & NETIF_F_RXALL)
7581 need_reset = true;
7582
567d2de2 7583 netdev->features = features;
082757af
DS		 7584 if (need_reset)
7585 ixgbe_do_reset(netdev);
7586
7587 return 0;
082757af
DS		 7588}
7589
edc7d573 7590static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7591 struct net_device *dev,
6b6e2725 7592 const unsigned char *addr,
0f4b0add
JF		 7593 u16 flags)
7594{
7595 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7596 int err;
7597
7598 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7599 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7600
b1ac1ef7
JF		 7601 /* Hardware does not support aging addresses so if a
7602 * ndm_state is given only allow permanent addresses
7603 */
7604 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7605 pr_info("%s: FDB only supports static addresses\n",
7606 ixgbe_driver_name);
7607 return -EINVAL;
7608 }
7609
46acc460 7610 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7611 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7612
7613 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7614 err = dev_uc_add_excl(dev, addr);
0f4b0add 7615 else
95447461
JF		 7616 err = -ENOMEM;
7617 } else if (is_multicast_ether_addr(addr)) {
7618 err = dev_mc_add_excl(dev, addr);
7619 } else {
7620 err = -EINVAL;
0f4b0add
JF		 7621 }
7622
7623 /* Only return duplicate errors if NLM_F_EXCL is set */
7624 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7625 err = 0;
7626
7627 return err;
7628}
7629
815cccbf
JF		 7630static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7631 struct nlmsghdr *nlh)
7632{
7633 struct ixgbe_adapter *adapter = netdev_priv(dev);
7634 struct nlattr *attr, *br_spec;
7635 int rem;
7636
7637 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7638 return -EOPNOTSUPP;
7639
7640 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7641
7642 nla_for_each_nested(attr, br_spec, rem) {
7643 __u16 mode;
7644 u32 reg = 0;
7645
7646 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7647 continue;
7648
7649 mode = nla_get_u16(attr);
9b735984 7650 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7651 reg = 0;
9b735984
GR		 7652 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7653 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7654 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7655 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7656 } else
815cccbf
JF		 7657 return -EINVAL;
7658
7659 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7660
7661 e_info(drv, "enabling bridge mode: %s\n",
7662 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7663 }
7664
7665 return 0;
7666}
7667
7668static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7669 struct net_device *dev,
7670 u32 filter_mask)
815cccbf
JF		 7671{
7672 struct ixgbe_adapter *adapter = netdev_priv(dev);
7673 u16 mode;
7674
7675 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7676 return 0;
7677
9b735984 7678 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7679 mode = BRIDGE_MODE_VEB;
7680 else
7681 mode = BRIDGE_MODE_VEPA;
7682
7683 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7684}
7685
2a47fa45
JF		 7686static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7687{
7688 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7689 struct ixgbe_adapter *adapter = netdev_priv(pdev);
51f3773b 7690 unsigned int limit;
2a47fa45
JF		 7691 int pool, err;
7692
219354d4
JF		 7693#ifdef CONFIG_RPS
7694 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7695 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7696 vdev->name);
7697 return ERR_PTR(-EINVAL);
7698 }
7699#endif
2a47fa45 7700 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7701 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7702 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7703 netdev_info(pdev,
7704 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7705 pdev->name);
7706 return ERR_PTR(-EINVAL);
7707 }
7708
7709 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7710 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7711 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7712 return ERR_PTR(-EBUSY);
7713
7714 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7715 if (!fwd_adapter)
7716 return ERR_PTR(-ENOMEM);
7717
7718 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7719 adapter->num_rx_pools++;
7720 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7721 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7722
7723 /* Enable VMDq flag so device will be set in VM mode */
7724 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7725 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7726 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7727
7728 /* Force reinit of ring allocation with VMDQ enabled */
7729 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7730 if (err)
7731 goto fwd_add_err;
7732 fwd_adapter->pool = pool;
7733 fwd_adapter->real_adapter = adapter;
7734 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7735 if (err)
7736 goto fwd_add_err;
7737 netif_tx_start_all_queues(vdev);
7738 return fwd_adapter;
7739fwd_add_err:
7740 /* unwind counter and free adapter struct */
7741 netdev_info(pdev,
7742 "%s: dfwd hardware acceleration failed\n", vdev->name);
7743 clear_bit(pool, &adapter->fwd_bitmask);
7744 adapter->num_rx_pools--;
7745 kfree(fwd_adapter);
7746 return ERR_PTR(err);
7747}
7748
7749static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7750{
7751 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7752 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7753 unsigned int limit;
2a47fa45
JF		 7754
7755 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7756 adapter->num_rx_pools--;
7757
51f3773b
JF		 7758 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7759 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7760 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7761 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7762 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7763 fwd_adapter->pool, adapter->num_rx_pools,
7764 fwd_adapter->rx_base_queue,
7765 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7766 adapter->fwd_bitmask);
7767 kfree(fwd_adapter);
7768}
7769
0edc3527 7770static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7771 .ndo_open = ixgbe_open,
0edc3527 7772 .ndo_stop = ixgbe_close,
00829823 7773 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7774 .ndo_select_queue = ixgbe_select_queue,
581330ba 7775 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7776 .ndo_validate_addr = eth_validate_addr,
7777 .ndo_set_mac_address = ixgbe_set_mac,
7778 .ndo_change_mtu = ixgbe_change_mtu,
7779 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7780 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7781 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7782 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7783 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7784 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7785 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7786 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7787 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7788 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7789#ifdef CONFIG_IXGBE_DCB
24095aa3 7790 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7791#endif
0edc3527
SH		 7792#ifdef CONFIG_NET_POLL_CONTROLLER
7793 .ndo_poll_controller = ixgbe_netpoll,
7794#endif
e0d1095a 7795#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7796 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7797#endif
332d4a7d
YZ		 7798#ifdef IXGBE_FCOE
7799 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7800 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7801 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7802 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7803 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7804 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7805 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7806#endif /* IXGBE_FCOE */
082757af
DS		 7807 .ndo_set_features = ixgbe_set_features,
7808 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7809 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7810 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7811 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7812 .ndo_dfwd_add_station = ixgbe_fwd_add,
7813 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7814};
7815
e027d1ae
JK		 7816/**
7817 * ixgbe_enumerate_functions - Get the number of ports this device has
7818 * @adapter: adapter structure
7819 *
7820 * This function enumerates the phsyical functions co-located on a single slot,
7821 * in order to determine how many ports a device has. This is most useful in
7822 * determining the required GT/s of PCIe bandwidth necessary for optimal
7823 * performance.
7824 **/
7825static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7826{
e027d1ae
JK		 7827 struct list_head *entry;
7828 int physfns = 0;
7829
f1f96579
JK		 7830 /* Some cards can not use the generic count PCIe functions method,
7831 * because they are behind a parent switch, so we hardcode these with
7832 * the correct number of functions.
e027d1ae 7833 */
f1f96579 7834 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7835 physfns = 4;
f1f96579 7836 } else {
e027d1ae
JK		 7837 list_for_each(entry, &adapter->pdev->bus_list) {
7838 struct pci_dev *pdev =
7839 list_entry(entry, struct pci_dev, bus_list);
7840 /* don't count virtual functions */
7841 if (!pdev->is_virtfn)
7842 physfns++;
7843 }
7844 }
7845
7846 return physfns;
7847}
7848
8e2813f5
JK		 7849/**
7850 * ixgbe_wol_supported - Check whether device supports WoL
7851 * @hw: hw specific details
7852 * @device_id: the device ID
7853 * @subdev_id: the subsystem device ID
7854 *
7855 * This function is used by probe and ethtool to determine
7856 * which devices have WoL support
7857 *
7858 **/
7859int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7860 u16 subdevice_id)
7861{
7862 struct ixgbe_hw *hw = &adapter->hw;
7863 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7864 int is_wol_supported = 0;
7865
7866 switch (device_id) {
7867 case IXGBE_DEV_ID_82599_SFP:
7868 /* Only these subdevices could supports WOL */
7869 switch (subdevice_id) {
87557440 7870 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7871 case IXGBE_SUBDEV_ID_82599_560FLR:
7872 /* only support first port */
7873 if (hw->bus.func != 0)
7874 break;
5700ff26 7875 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7876 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7877 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7878 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7879 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7880 is_wol_supported = 1;
7881 break;
7882 }
7883 break;
5daebbb0
DS		 7884 case IXGBE_DEV_ID_82599EN_SFP:
7885 /* Only this subdevice supports WOL */
7886 switch (subdevice_id) {
7887 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7888 is_wol_supported = 1;
7889 break;
7890 }
7891 break;
8e2813f5
JK		 7892 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7893 /* All except this subdevice support WOL */
7894 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7895 is_wol_supported = 1;
7896 break;
7897 case IXGBE_DEV_ID_82599_KX4:
7898 is_wol_supported = 1;
7899 break;
7900 case IXGBE_DEV_ID_X540T:
df376f0d 7901 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7902 /* check eeprom to see if enabled wol */
7903 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7904 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7905 (hw->bus.func == 0))) {
7906 is_wol_supported = 1;
7907 }
7908 break;
7909 }
7910
7911 return is_wol_supported;
7912}
7913
9a799d71
AK		 7914/**
7915 * ixgbe_probe - Device Initialization Routine
7916 * @pdev: PCI device information struct
7917 * @ent: entry in ixgbe_pci_tbl
7918 *
7919 * Returns 0 on success, negative on failure
7920 *
7921 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7922 * The OS initialization, configuring of the adapter private structure,
7923 * and a hardware reset occur.
7924 **/
1dd06ae8 7925static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7926{
7927 struct net_device *netdev;
7928 struct ixgbe_adapter *adapter = NULL;
7929 struct ixgbe_hw *hw;
7930 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7931 static int cards_found;
e027d1ae 7932 int i, err, pci_using_dac, expected_gts;
d3cb9869 7933 unsigned int indices = MAX_TX_QUEUES;
289700db 7934 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7935#ifdef IXGBE_FCOE
7936 u16 device_caps;
7937#endif
289700db 7938 u32 eec;
9a799d71 7939
bded64a7
AG		 7940 /* Catch broken hardware that put the wrong VF device ID in
7941 * the PCIe SR-IOV capability.
7942 */
7943 if (pdev->is_virtfn) {
7944 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7945 pci_name(pdev), pdev->vendor, pdev->device);
7946 return -EINVAL;
7947 }
7948
9ce77666 7949 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7950 if (err)
7951 return err;
7952
f5f2eda8 7953 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7954 pci_using_dac = 1;
7955 } else {
f5f2eda8 7956 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7957 if (err) {
f5f2eda8
RK		 7958 dev_err(&pdev->dev,
7959 "No usable DMA configuration, aborting\n");
7960 goto err_dma;
9a799d71
AK		 7961 }
7962 pci_using_dac = 0;
7963 }
7964
9ce77666 7965 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7966 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7967 if (err) {
b8bc0421
DC		 7968 dev_err(&pdev->dev,
7969 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7970 goto err_pci_reg;
7971 }
7972
19d5afd4 7973 pci_enable_pcie_error_reporting(pdev);
6fabd715 7974
9a799d71 7975 pci_set_master(pdev);
fb3b27bc 7976 pci_save_state(pdev);
9a799d71 7977
d3cb9869 7978 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7979#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7980 /* 8 TC w/ 4 queues per TC */
7981 indices = 4 * MAX_TRAFFIC_CLASS;
7982#else
7983 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7984#endif
d3cb9869 7985 }
e901acd6 7986
c85a2618 7987 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7988 if (!netdev) {
7989 err = -ENOMEM;
7990 goto err_alloc_etherdev;
7991 }
7992
9a799d71
AK		 7993 SET_NETDEV_DEV(netdev, &pdev->dev);
7994
9a799d71 7995 adapter = netdev_priv(netdev);
c60fbb00 7996 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7997
7998 adapter->netdev = netdev;
7999 adapter->pdev = pdev;
8000 hw = &adapter->hw;
8001 hw->back = adapter;
b3f4d599 8002 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8003
05857980 8004 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8005 pci_resource_len(pdev, 0));
2a1a091c 8006 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8007 if (!hw->hw_addr) {
8008 err = -EIO;
8009 goto err_ioremap;
8010 }
8011
0edc3527 8012 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8013 ixgbe_set_ethtool_ops(netdev);
9a799d71 8014 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 8015 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 8016
9a799d71
AK		 8017 adapter->bd_number = cards_found;
8018
9a799d71
AK		 8019 /* Setup hw api */
8020 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8021 hw->mac.type = ii->mac;
9a799d71 8022
c44ade9e
JB		 8023 /* EEPROM */
8024 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8025 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8026 if (ixgbe_removed(hw->hw_addr)) {
8027 err = -EIO;
8028 goto err_ioremap;
8029 }
c44ade9e
JB		 8030 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8031 if (!(eec & (1 << 8)))
8032 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8033
8034 /* PHY */
8035 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8036 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8037 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8038 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8039 hw->phy.mdio.mmds = 0;
8040 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8041 hw->phy.mdio.dev = netdev;
8042 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8043 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8044
8ca783ab 8045 ii->get_invariants(hw);
9a799d71
AK		 8046
8047 /* setup the private structure */
8048 err = ixgbe_sw_init(adapter);
8049 if (err)
8050 goto err_sw_init;
8051
e86bff0e 8052 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8053 switch (adapter->hw.mac.type) {
8054 case ixgbe_mac_82599EB:
8055 case ixgbe_mac_X540:
e86bff0e 8056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8057 break;
8058 default:
8059 break;
8060 }
e86bff0e 8061
bf069c97
DS		 8062 /*
8063 * If there is a fan on this device and it has failed log the
8064 * failure.
8065 */
8066 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8067 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8068 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8069 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8070 }
8071
8ef78adc
PWJ		 8072 if (allow_unsupported_sfp)
8073 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8074
c44ade9e 8075 /* reset_hw fills in the perm_addr as well */
119fc60a 8076 hw->phy.reset_if_overtemp = true;
c44ade9e 8077 err = hw->mac.ops.reset_hw(hw);
119fc60a 8078 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8079 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8080 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8081 err = 0;
8082 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8083 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8084 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8085 goto err_sw_init;
8086 } else if (err) {
849c4542 8087 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8088 goto err_sw_init;
8089 }
8090
99d74487 8091#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8092 /* SR-IOV not supported on the 82598 */
8093 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8094 goto skip_sriov;
8095 /* Mailbox */
8096 ixgbe_init_mbx_params_pf(hw);
8097 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8098 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8099 ixgbe_enable_sriov(adapter);
60a1a680 8100skip_sriov:
1cdd1ec8 8101
99d74487 8102#endif
396e799c 8103 netdev->features = NETIF_F_SG |
e8e9f696 8104 NETIF_F_IP_CSUM |
082757af 8105 NETIF_F_IPV6_CSUM |
f646968f
PM		 8106 NETIF_F_HW_VLAN_CTAG_TX |
8107 NETIF_F_HW_VLAN_CTAG_RX |
8108 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8109 NETIF_F_TSO |
8110 NETIF_F_TSO6 |
082757af 8111 NETIF_F_RXHASH |
8bf1264d 8112 NETIF_F_RXCSUM;
9a799d71 8113
8bf1264d 8114 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8115
58be7666
DS		 8116 switch (adapter->hw.mac.type) {
8117 case ixgbe_mac_82599EB:
8118 case ixgbe_mac_X540:
45a5ead0 8119 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8120 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8121 NETIF_F_NTUPLE;
58be7666
DS		 8122 break;
8123 default:
8124 break;
8125 }
45a5ead0 8126
3f2d1c0f
BG		 8127 netdev->hw_features |= NETIF_F_RXALL;
8128
ad31c402
JK		 8129 netdev->vlan_features |= NETIF_F_TSO;
8130 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8131 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8132 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8133 netdev->vlan_features |= NETIF_F_SG;
8134
01789349 8135 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8136 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8137
7a6b6f51 8138#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8139 netdev->dcbnl_ops = &dcbnl_ops;
8140#endif
8141
eacd73f7 8142#ifdef IXGBE_FCOE
0d551589 8143 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8144 unsigned int fcoe_l;
8145
eacd73f7
YZ		 8146 if (hw->mac.ops.get_device_caps) {
8147 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8148 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8149 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8150 }
7c8ae65a 8151
d3cb9869
AD		 8152
8153 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8154 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8155
a58915c7
AD		 8156 netdev->features |= NETIF_F_FSO |
8157 NETIF_F_FCOE_CRC;
8158
7c8ae65a
AD		 8159 netdev->vlan_features |= NETIF_F_FSO |
8160 NETIF_F_FCOE_CRC |
8161 NETIF_F_FCOE_MTU;
5e09d7f6 8162 }
eacd73f7 8163#endif /* IXGBE_FCOE */
7b872a55 8164 if (pci_using_dac) {
9a799d71 8165 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8166 netdev->vlan_features |= NETIF_F_HIGHDMA;
8167 }
9a799d71 8168
082757af
DS		 8169 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8170 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8171 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8172 netdev->features |= NETIF_F_LRO;
8173
9a799d71 8174 /* make sure the EEPROM is good */
c44ade9e 8175 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8176 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8177 err = -EIO;
35937c05 8178 goto err_sw_init;
9a799d71
AK		 8179 }
8180
8181 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8182
aaeb6cdf 8183 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8184 e_dev_err("invalid MAC address\n");
9a799d71 8185 err = -EIO;
35937c05 8186 goto err_sw_init;
9a799d71
AK		 8187 }
8188
7086400d 8189 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8190 (unsigned long) adapter);
9a799d71 8191
58cf663f
MR		 8192 if (ixgbe_removed(hw->hw_addr)) {
8193 err = -EIO;
8194 goto err_sw_init;
8195 }
7086400d 8196 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8197 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8198 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8199
021230d4
AV		 8200 err = ixgbe_init_interrupt_scheme(adapter);
8201 if (err)
8202 goto err_sw_init;
9a799d71 8203
8e2813f5 8204 /* WOL not supported for all devices */
c23f5b6b 8205 adapter->wol = 0;
8e2813f5 8206 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8207 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8208 pdev->subsystem_device);
6b92b0ba 8209 if (hw->wol_enabled)
9417c464 8210 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8211
e8e26350
PW		 8212 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8213
15e5209f
ET		 8214 /* save off EEPROM version number */
8215 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8216 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8217
04f165ef
PW		 8218 /* pick up the PCI bus settings for reporting later */
8219 hw->mac.ops.get_bus_info(hw);
e027d1ae 8220 if (ixgbe_pcie_from_parent(hw))
b8e82001 8221 ixgbe_get_parent_bus_info(adapter);
04f165ef 8222
e027d1ae
JK		 8223 /* calculate the expected PCIe bandwidth required for optimal
8224 * performance. Note that some older parts will never have enough
8225 * bandwidth due to being older generation PCIe parts. We clamp these
8226 * parts to ensure no warning is displayed if it can't be fixed.
8227 */
8228 switch (hw->mac.type) {
8229 case ixgbe_mac_82598EB:
8230 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8231 break;
8232 default:
8233 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8234 break;
0c254d86 8235 }
e027d1ae 8236 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8237
6a2aae5a
JK		 8238 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8239 if (err)
8240 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8241 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8242 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8243 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8244 part_str);
8245 else
8246 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8247 hw->mac.type, hw->phy.type, part_str);
8248
8249 e_dev_info("%pM\n", netdev->dev_addr);
8250
9a799d71 8251 /* reset the hardware with the new settings */
794caeb2 8252 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8253 if (err == IXGBE_ERR_EEPROM_VERSION) {
8254 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8255 e_dev_warn("This device is a pre-production adapter/LOM. "
8256 "Please be aware there may be issues associated "
8257 "with your hardware. If you are experiencing "
8258 "problems please contact your Intel or hardware "
8259 "representative who provided you with this "
8260 "hardware.\n");
794caeb2 8261 }
9a799d71
AK		 8262 strcpy(netdev->name, "eth%d");
8263 err = register_netdev(netdev);
8264 if (err)
8265 goto err_register;
8266
ec74a471
ET		 8267 /* power down the optics for 82599 SFP+ fiber */
8268 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8269 hw->mac.ops.disable_tx_laser(hw);
8270
54386467
JB		 8271 /* carrier off reporting is important to ethtool even BEFORE open */
8272 netif_carrier_off(netdev);
8273
5dd2d332 8274#ifdef CONFIG_IXGBE_DCA
652f093f 8275 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8276 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8277 ixgbe_setup_dca(adapter);
8278 }
8279#endif
1cdd1ec8 8280 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8281 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8282 for (i = 0; i < adapter->num_vfs; i++)
8283 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8284 }
8285
2466dd9c
JK		 8286 /* firmware requires driver version to be 0xFFFFFFFF
8287 * since os does not support feature
8288 */
9612de92 8289 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8290 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8291 0xFF);
9612de92 8292
0365e6e4
PW		 8293 /* add san mac addr to netdev */
8294 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8295
ea81875a 8296 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8297 cards_found++;
3ca8bc6d 8298
1210982b 8299#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8300 if (ixgbe_sysfs_init(adapter))
8301 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8302#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8303
00949167 8304 ixgbe_dbg_adapter_init(adapter);
00949167 8305
0b2679d6 8306 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7155d051 8307 if (ixgbe_mng_enabled(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8308 hw->mac.ops.setup_link(hw,
8309 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8310 true);
8311
9a799d71
AK		 8312 return 0;
8313
8314err_register:
5eba3699 8315 ixgbe_release_hw_control(adapter);
7a921c93 8316 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8317err_sw_init:
99d74487 8318 ixgbe_disable_sriov(adapter);
7086400d 8319 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8320 iounmap(adapter->io_addr);
9a799d71
AK		 8321err_ioremap:
8322 free_netdev(netdev);
8323err_alloc_etherdev:
e8e9f696
JP		 8324 pci_release_selected_regions(pdev,
8325 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8326err_pci_reg:
8327err_dma:
41c62843
MR		 8328 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8329 pci_disable_device(pdev);
9a799d71
AK		 8330 return err;
8331}
8332
8333/**
8334 * ixgbe_remove - Device Removal Routine
8335 * @pdev: PCI device information struct
8336 *
8337 * ixgbe_remove is called by the PCI subsystem to alert the driver
8338 * that it should release a PCI device. The could be caused by a
8339 * Hot-Plug event, or because the driver is going to be removed from
8340 * memory.
8341 **/
9f9a12f8 8342static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8343{
c60fbb00
AD		 8344 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8345 struct net_device *netdev = adapter->netdev;
9a799d71 8346
00949167 8347 ixgbe_dbg_adapter_exit(adapter);
00949167 8348
09f40aed 8349 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8350 cancel_work_sync(&adapter->service_task);
9a799d71 8351
3a6a4eda 8352
5dd2d332 8353#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8354 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8355 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8356 dca_remove_requester(&pdev->dev);
8357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8358 }
8359
8360#endif
1210982b 8361#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8362 ixgbe_sysfs_exit(adapter);
1210982b 8363#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8364
0365e6e4
PW		 8365 /* remove the added san mac */
8366 ixgbe_del_sanmac_netdev(netdev);
8367
c4900be0
DS		 8368 if (netdev->reg_state == NETREG_REGISTERED)
8369 unregister_netdev(netdev);
9a799d71 8370
da36b647
GR		 8371#ifdef CONFIG_PCI_IOV
8372 /*
8373 * Only disable SR-IOV on unload if the user specified the now
8374 * deprecated max_vfs module parameter.
8375 */
8376 if (max_vfs)
8377 ixgbe_disable_sriov(adapter);
8378#endif
7a921c93 8379 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8380
021230d4 8381 ixgbe_release_hw_control(adapter);
9a799d71 8382
2b1588c3
AD		 8383#ifdef CONFIG_DCB
8384 kfree(adapter->ixgbe_ieee_pfc);
8385 kfree(adapter->ixgbe_ieee_ets);
8386
8387#endif
2a1a091c 8388 iounmap(adapter->io_addr);
9ce77666 8389 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8390 IORESOURCE_MEM));
9a799d71 8391
849c4542 8392 e_dev_info("complete\n");
021230d4 8393
9a799d71
AK		 8394 free_netdev(netdev);
8395
19d5afd4 8396 pci_disable_pcie_error_reporting(pdev);
6fabd715 8397
41c62843
MR		 8398 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8399 pci_disable_device(pdev);
9a799d71
AK		 8400}
8401
8402/**
8403 * ixgbe_io_error_detected - called when PCI error is detected
8404 * @pdev: Pointer to PCI device
8405 * @state: The current pci connection state
8406 *
8407 * This function is called after a PCI bus error affecting
8408 * this device has been detected.
8409 */
8410static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8411 pci_channel_state_t state)
9a799d71 8412{
c60fbb00
AD		 8413 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8414 struct net_device *netdev = adapter->netdev;
9a799d71 8415
83c61fa9 8416#ifdef CONFIG_PCI_IOV
14438464 8417 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8418 struct pci_dev *bdev, *vfdev;
8419 u32 dw0, dw1, dw2, dw3;
8420 int vf, pos;
8421 u16 req_id, pf_func;
8422
8423 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8424 adapter->num_vfs == 0)
8425 goto skip_bad_vf_detection;
8426
8427 bdev = pdev->bus->self;
62f87c0e 8428 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8429 bdev = bdev->bus->self;
8430
8431 if (!bdev)
8432 goto skip_bad_vf_detection;
8433
8434 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8435 if (!pos)
8436 goto skip_bad_vf_detection;
8437
14438464
MR		 8438 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8439 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8440 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8441 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8442 if (ixgbe_removed(hw->hw_addr))
8443 goto skip_bad_vf_detection;
83c61fa9
GR		 8444
8445 req_id = dw1 >> 16;
8446 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8447 if (!(req_id & 0x0080))
8448 goto skip_bad_vf_detection;
8449
8450 pf_func = req_id & 0x01;
8451 if ((pf_func & 1) == (pdev->devfn & 1)) {
8452 unsigned int device_id;
8453
8454 vf = (req_id & 0x7F) >> 1;
8455 e_dev_err("VF %d has caused a PCIe error\n", vf);
8456 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8457 "%8.8x\tdw3: %8.8x\n",
8458 dw0, dw1, dw2, dw3);
8459 switch (adapter->hw.mac.type) {
8460 case ixgbe_mac_82599EB:
8461 device_id = IXGBE_82599_VF_DEVICE_ID;
8462 break;
8463 case ixgbe_mac_X540:
8464 device_id = IXGBE_X540_VF_DEVICE_ID;
8465 break;
8466 default:
8467 device_id = 0;
8468 break;
8469 }
8470
8471 /* Find the pci device of the offending VF */
36e90319 8472 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8473 while (vfdev) {
8474 if (vfdev->devfn == (req_id & 0xFF))
8475 break;
36e90319 8476 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8477 device_id, vfdev);
8478 }
8479 /*
8480 * There's a slim chance the VF could have been hot plugged,
8481 * so if it is no longer present we don't need to issue the
8482 * VFLR. Just clean up the AER in that case.
8483 */
8484 if (vfdev) {
8485 e_dev_err("Issuing VFLR to VF %d\n", vf);
8486 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8487 /* Free device reference count */
8488 pci_dev_put(vfdev);
83c61fa9
GR		 8489 }
8490
8491 pci_cleanup_aer_uncorrect_error_status(pdev);
8492 }
8493
8494 /*
8495 * Even though the error may have occurred on the other port
8496 * we still need to increment the vf error reference count for
8497 * both ports because the I/O resume function will be called
8498 * for both of them.
8499 */
8500 adapter->vferr_refcount++;
8501
8502 return PCI_ERS_RESULT_RECOVERED;
8503
8504skip_bad_vf_detection:
8505#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8506 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8507 return PCI_ERS_RESULT_DISCONNECT;
8508
41c62843 8509 rtnl_lock();
9a799d71
AK		 8510 netif_device_detach(netdev);
8511
41c62843
MR		 8512 if (state == pci_channel_io_perm_failure) {
8513 rtnl_unlock();
3044b8d1 8514 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8515 }
3044b8d1 8516
9a799d71
AK		 8517 if (netif_running(netdev))
8518 ixgbe_down(adapter);
41c62843
MR		 8519
8520 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8521 pci_disable_device(pdev);
8522 rtnl_unlock();
9a799d71 8523
b4617240 8524 /* Request a slot reset. */
9a799d71
AK		 8525 return PCI_ERS_RESULT_NEED_RESET;
8526}
8527
8528/**
8529 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8530 * @pdev: Pointer to PCI device
8531 *
8532 * Restart the card from scratch, as if from a cold-boot.
8533 */
8534static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8535{
c60fbb00 8536 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8537 pci_ers_result_t result;
8538 int err;
9a799d71 8539
9ce77666 8540 if (pci_enable_device_mem(pdev)) {
396e799c 8541 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8542 result = PCI_ERS_RESULT_DISCONNECT;
8543 } else {
41c62843
MR		 8544 smp_mb__before_clear_bit();
8545 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8546 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8547 pci_set_master(pdev);
8548 pci_restore_state(pdev);
c0e1f68b 8549 pci_save_state(pdev);
9a799d71 8550
dd4d8ca6 8551 pci_wake_from_d3(pdev, false);
9a799d71 8552
6fabd715 8553 ixgbe_reset(adapter);
88512539 8554 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8555 result = PCI_ERS_RESULT_RECOVERED;
8556 }
8557
8558 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8559 if (err) {
849c4542
ET		 8560 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8561 "failed 0x%0x\n", err);
6fabd715
PWJ		 8562 /* non-fatal, continue */
8563 }
9a799d71 8564
6fabd715 8565 return result;
9a799d71
AK		 8566}
8567
8568/**
8569 * ixgbe_io_resume - called when traffic can start flowing again.
8570 * @pdev: Pointer to PCI device
8571 *
8572 * This callback is called when the error recovery driver tells us that
8573 * its OK to resume normal operation.
8574 */
8575static void ixgbe_io_resume(struct pci_dev *pdev)
8576{
c60fbb00
AD		 8577 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8578 struct net_device *netdev = adapter->netdev;
9a799d71 8579
83c61fa9
GR		 8580#ifdef CONFIG_PCI_IOV
8581 if (adapter->vferr_refcount) {
8582 e_info(drv, "Resuming after VF err\n");
8583 adapter->vferr_refcount--;
8584 return;
8585 }
8586
8587#endif
c7ccde0f
AD		 8588 if (netif_running(netdev))
8589 ixgbe_up(adapter);
9a799d71
AK		 8590
8591 netif_device_attach(netdev);
9a799d71
AK		 8592}
8593
3646f0e5 8594static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8595 .error_detected = ixgbe_io_error_detected,
8596 .slot_reset = ixgbe_io_slot_reset,
8597 .resume = ixgbe_io_resume,
8598};
8599
8600static struct pci_driver ixgbe_driver = {
8601 .name = ixgbe_driver_name,
8602 .id_table = ixgbe_pci_tbl,
8603 .probe = ixgbe_probe,
9f9a12f8 8604 .remove = ixgbe_remove,
9a799d71
AK		 8605#ifdef CONFIG_PM
8606 .suspend = ixgbe_suspend,
8607 .resume = ixgbe_resume,
8608#endif
8609 .shutdown = ixgbe_shutdown,
da36b647 8610 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8611 .err_handler = &ixgbe_err_handler
8612};
8613
8614/**
8615 * ixgbe_init_module - Driver Registration Routine
8616 *
8617 * ixgbe_init_module is the first routine called when the driver is
8618 * loaded. All it does is register with the PCI subsystem.
8619 **/
8620static int __init ixgbe_init_module(void)
8621{
8622 int ret;
c7689578 8623 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8624 pr_info("%s\n", ixgbe_copyright);
9a799d71 8625
00949167 8626 ixgbe_dbg_init();
00949167 8627
f01fc1a8
JK		 8628 ret = pci_register_driver(&ixgbe_driver);
8629 if (ret) {
f01fc1a8 8630 ixgbe_dbg_exit();
f01fc1a8
JK		 8631 return ret;
8632 }
8633
5dd2d332 8634#ifdef CONFIG_IXGBE_DCA
bd0362dd 8635 dca_register_notify(&dca_notifier);
bd0362dd 8636#endif
5dd2d332 8637
f01fc1a8 8638 return 0;
9a799d71 8639}
b4617240 8640
9a799d71
AK		 8641module_init(ixgbe_init_module);
8642
8643/**
8644 * ixgbe_exit_module - Driver Exit Cleanup Routine
8645 *
8646 * ixgbe_exit_module is called just before the driver is removed
8647 * from memory.
8648 **/
8649static void __exit ixgbe_exit_module(void)
8650{
5dd2d332 8651#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8652 dca_unregister_notify(&dca_notifier);
8653#endif
9a799d71 8654 pci_unregister_driver(&ixgbe_driver);
00949167 8655
00949167 8656 ixgbe_dbg_exit();
00949167 8657
1a51502b 8658 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8659}
bd0362dd 8660
5dd2d332 8661#ifdef CONFIG_IXGBE_DCA
bd0362dd 8662static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8663 void *p)
bd0362dd
JC		 8664{
8665 int ret_val;
8666
8667 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8668 __ixgbe_notify_dca);
bd0362dd
JC		 8669
8670 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8671}
b453368d 8672
5dd2d332 8673#endif /* CONFIG_IXGBE_DCA */
849c4542 8674
9a799d71
AK		 8675module_exit(ixgbe_exit_module);
8676
8677/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)