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ixgbe: Fix up some ethtool results when adapter is removed
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
2a47fa45 47#include <linux/if_macvlan.h>
815cccbf 48#include <linux/if_bridge.h>
70c71606 49#include <linux/prefetch.h>
eacd73f7 50#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 51
52#include "ixgbe.h"
53#include "ixgbe_common.h"
ee5f784a 54#include "ixgbe_dcb_82599.h"
1cdd1ec8 55#include "ixgbe_sriov.h"
9a799d71
AK		 56
57char ixgbe_driver_name[] = "ixgbe";
9c8eb720 58static const char ixgbe_driver_string[] =
e8e9f696 59 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 60#ifdef IXGBE_FCOE
ea81875a
NP		 61char ixgbe_default_device_descr[] =
62 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 63#else
64static char ixgbe_default_device_descr[] =
65 "Intel(R) 10 Gigabit Network Connection";
66#endif
f341c4e0 67#define DRV_VERSION "3.19.1-k"
9c8eb720 68const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 69static const char ixgbe_copyright[] =
0391bbe3 70 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 71
72static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 73 [board_82598] = &ixgbe_82598_info,
e8e26350 74 [board_82599] = &ixgbe_82599_info,
fe15e8e1 75 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 76};
77
78/* ixgbe_pci_tbl - PCI Device ID Table
79 *
80 * Wildcard entries (PCI_ANY_ID) should come last
81 * Last entry must be all 0s
82 *
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
85 */
a3aa1884 86static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
170e8543 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
b8e82001
JK		 154static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
155 u32 reg, u16 *value)
156{
b8e82001
JK		 157 struct pci_dev *parent_dev;
158 struct pci_bus *parent_bus;
159
160 parent_bus = adapter->pdev->bus->parent;
161 if (!parent_bus)
162 return -1;
163
164 parent_dev = parent_bus->self;
165 if (!parent_dev)
166 return -1;
167
c0798edf 168 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 169 return -1;
170
c0798edf 171 pcie_capability_read_word(parent_dev, reg, value);
b8e82001
JK		 172 return 0;
173}
174
175static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176{
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196}
197
e027d1ae
JK		 198/**
199 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
200 * @hw: hw specific details
201 *
202 * This function is used by probe to determine whether a device's PCI-Express
203 * bandwidth details should be gathered from the parent bus instead of from the
204 * device. Used to ensure that various locations all have the correct device ID
205 * checks.
206 */
207static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
208{
209 switch (hw->device_id) {
210 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 211 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 212 return true;
213 default:
214 return false;
215 }
216}
217
218static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
219 int expected_gts)
220{
221 int max_gts = 0;
222 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
223 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
224 struct pci_dev *pdev;
225
226 /* determine whether to use the the parent device
227 */
228 if (ixgbe_pcie_from_parent(&adapter->hw))
229 pdev = adapter->pdev->bus->parent->self;
230 else
231 pdev = adapter->pdev;
232
233 if (pcie_get_minimum_link(pdev, &speed, &width) ||
234 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
235 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
236 return;
237 }
238
239 switch (speed) {
240 case PCIE_SPEED_2_5GT:
241 /* 8b/10b encoding reduces max throughput by 20% */
242 max_gts = 2 * width;
243 break;
244 case PCIE_SPEED_5_0GT:
245 /* 8b/10b encoding reduces max throughput by 20% */
246 max_gts = 4 * width;
247 break;
248 case PCIE_SPEED_8_0GT:
9f0a433c 249 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 250 max_gts = 8 * width;
251 break;
252 default:
253 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
254 return;
255 }
256
257 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
258 max_gts);
259 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
260 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
261 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
262 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
263 "Unknown"),
264 width,
265 (speed == PCIE_SPEED_2_5GT ? "20%" :
266 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 267 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 268 "Unknown"));
269
270 if (max_gts < expected_gts) {
271 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
272 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
273 expected_gts);
274 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
275 }
276}
277
7086400d
AD		 278static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
279{
280 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 281 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 282 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
283 schedule_work(&adapter->service_task);
284}
285
2a1a091c
MR		 286static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
287{
288 struct ixgbe_adapter *adapter = hw->back;
289
290 if (!hw->hw_addr)
291 return;
292 hw->hw_addr = NULL;
293 e_dev_err("Adapter removed\n");
b0483c8f 294 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 295}
296
297void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
298{
299 u32 value;
300
301 /* The following check not only optimizes a bit by not
302 * performing a read on the status register when the
303 * register just read was a status register read that
304 * returned IXGBE_FAILED_READ_REG. It also blocks any
305 * potential recursion.
306 */
307 if (reg == IXGBE_STATUS) {
308 ixgbe_remove_adapter(hw);
309 return;
310 }
311 value = ixgbe_read_reg(hw, IXGBE_STATUS);
312 if (value == IXGBE_FAILED_READ_REG)
313 ixgbe_remove_adapter(hw);
314}
315
7086400d
AD		 316static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
317{
318 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
319
52f33af8 320 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 321 smp_mb__before_clear_bit();
322 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
323}
324
dcd79aeb
TI		 325struct ixgbe_reg_info {
326 u32 ofs;
327 char *name;
328};
329
330static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
331
332 /* General Registers */
333 {IXGBE_CTRL, "CTRL"},
334 {IXGBE_STATUS, "STATUS"},
335 {IXGBE_CTRL_EXT, "CTRL_EXT"},
336
337 /* Interrupt Registers */
338 {IXGBE_EICR, "EICR"},
339
340 /* RX Registers */
341 {IXGBE_SRRCTL(0), "SRRCTL"},
342 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
343 {IXGBE_RDLEN(0), "RDLEN"},
344 {IXGBE_RDH(0), "RDH"},
345 {IXGBE_RDT(0), "RDT"},
346 {IXGBE_RXDCTL(0), "RXDCTL"},
347 {IXGBE_RDBAL(0), "RDBAL"},
348 {IXGBE_RDBAH(0), "RDBAH"},
349
350 /* TX Registers */
351 {IXGBE_TDBAL(0), "TDBAL"},
352 {IXGBE_TDBAH(0), "TDBAH"},
353 {IXGBE_TDLEN(0), "TDLEN"},
354 {IXGBE_TDH(0), "TDH"},
355 {IXGBE_TDT(0), "TDT"},
356 {IXGBE_TXDCTL(0), "TXDCTL"},
357
358 /* List Terminator */
359 {}
360};
361
362
363/*
364 * ixgbe_regdump - register printout routine
365 */
366static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
367{
368 int i = 0, j = 0;
369 char rname[16];
370 u32 regs[64];
371
372 switch (reginfo->ofs) {
373 case IXGBE_SRRCTL(0):
374 for (i = 0; i < 64; i++)
375 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
376 break;
377 case IXGBE_DCA_RXCTRL(0):
378 for (i = 0; i < 64; i++)
379 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
380 break;
381 case IXGBE_RDLEN(0):
382 for (i = 0; i < 64; i++)
383 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
384 break;
385 case IXGBE_RDH(0):
386 for (i = 0; i < 64; i++)
387 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
388 break;
389 case IXGBE_RDT(0):
390 for (i = 0; i < 64; i++)
391 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
392 break;
393 case IXGBE_RXDCTL(0):
394 for (i = 0; i < 64; i++)
395 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
396 break;
397 case IXGBE_RDBAL(0):
398 for (i = 0; i < 64; i++)
399 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
400 break;
401 case IXGBE_RDBAH(0):
402 for (i = 0; i < 64; i++)
403 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
404 break;
405 case IXGBE_TDBAL(0):
406 for (i = 0; i < 64; i++)
407 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
408 break;
409 case IXGBE_TDBAH(0):
410 for (i = 0; i < 64; i++)
411 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
412 break;
413 case IXGBE_TDLEN(0):
414 for (i = 0; i < 64; i++)
415 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
416 break;
417 case IXGBE_TDH(0):
418 for (i = 0; i < 64; i++)
419 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
420 break;
421 case IXGBE_TDT(0):
422 for (i = 0; i < 64; i++)
423 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
424 break;
425 case IXGBE_TXDCTL(0):
426 for (i = 0; i < 64; i++)
427 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
428 break;
429 default:
c7689578 430 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 431 IXGBE_READ_REG(hw, reginfo->ofs));
432 return;
433 }
434
435 for (i = 0; i < 8; i++) {
436 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 437 pr_err("%-15s", rname);
dcd79aeb 438 for (j = 0; j < 8; j++)
c7689578
JP		 439 pr_cont(" %08x", regs[i*8+j]);
440 pr_cont("\n");
dcd79aeb
TI		 441 }
442
443}
444
445/*
446 * ixgbe_dump - Print registers, tx-rings and rx-rings
447 */
448static void ixgbe_dump(struct ixgbe_adapter *adapter)
449{
450 struct net_device *netdev = adapter->netdev;
451 struct ixgbe_hw *hw = &adapter->hw;
452 struct ixgbe_reg_info *reginfo;
453 int n = 0;
454 struct ixgbe_ring *tx_ring;
729739b7 455 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 456 union ixgbe_adv_tx_desc *tx_desc;
457 struct my_u0 { u64 a; u64 b; } *u0;
458 struct ixgbe_ring *rx_ring;
459 union ixgbe_adv_rx_desc *rx_desc;
460 struct ixgbe_rx_buffer *rx_buffer_info;
461 u32 staterr;
462 int i = 0;
463
464 if (!netif_msg_hw(adapter))
465 return;
466
467 /* Print netdevice Info */
468 if (netdev) {
469 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 470 pr_info("Device Name state "
dcd79aeb 471 "trans_start last_rx\n");
c7689578
JP		 472 pr_info("%-15s %016lX %016lX %016lX\n",
473 netdev->name,
474 netdev->state,
475 netdev->trans_start,
476 netdev->last_rx);
dcd79aeb
TI		 477 }
478
479 /* Print Registers */
480 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 481 pr_info(" Register Name Value\n");
dcd79aeb
TI		 482 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
483 reginfo->name; reginfo++) {
484 ixgbe_regdump(hw, reginfo);
485 }
486
487 /* Print TX Ring Summary */
488 if (!netdev || !netif_running(netdev))
489 goto exit;
490
491 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 492 pr_info(" %s %s %s %s\n",
493 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
494 "leng", "ntw", "timestamp");
dcd79aeb
TI		 495 for (n = 0; n < adapter->num_tx_queues; n++) {
496 tx_ring = adapter->tx_ring[n];
729739b7 497 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 498 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 499 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 500 (u64)dma_unmap_addr(tx_buffer, dma),
501 dma_unmap_len(tx_buffer, len),
502 tx_buffer->next_to_watch,
503 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 504 }
505
506 /* Print TX Rings */
507 if (!netif_msg_tx_done(adapter))
508 goto rx_ring_summary;
509
510 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
511
512 /* Transmit Descriptor Formats
513 *
39ac868a 514 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 515 * +--------------------------------------------------------------+
516 * 0 | Buffer Address [63:0] |
517 * +--------------------------------------------------------------+
39ac868a 518 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 519 * +--------------------------------------------------------------+
520 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 521 *
522 * 82598 Advanced Transmit Descriptor (Write-Back Format)
523 * +--------------------------------------------------------------+
524 * 0 | RSV [63:0] |
525 * +--------------------------------------------------------------+
526 * 8 | RSV | STA | NXTSEQ |
527 * +--------------------------------------------------------------+
528 * 63 36 35 32 31 0
529 *
530 * 82599+ Advanced Transmit Descriptor
531 * +--------------------------------------------------------------+
532 * 0 | Buffer Address [63:0] |
533 * +--------------------------------------------------------------+
534 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
535 * +--------------------------------------------------------------+
536 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
537 *
538 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
539 * +--------------------------------------------------------------+
540 * 0 | RSV [63:0] |
541 * +--------------------------------------------------------------+
542 * 8 | RSV | STA | RSV |
543 * +--------------------------------------------------------------+
544 * 63 36 35 32 31 0
dcd79aeb
TI		 545 */
546
547 for (n = 0; n < adapter->num_tx_queues; n++) {
548 tx_ring = adapter->tx_ring[n];
c7689578
JP		 549 pr_info("------------------------------------\n");
550 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
551 pr_info("------------------------------------\n");
8ad88e37
JH		 552 pr_info("%s%s %s %s %s %s\n",
553 "T [desc] [address 63:0 ] ",
554 "[PlPOIdStDDt Ln] [bi->dma ] ",
555 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 556
557 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 558 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 559 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 560 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 561 if (dma_unmap_len(tx_buffer, len) > 0) {
562 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
563 i,
564 le64_to_cpu(u0->a),
565 le64_to_cpu(u0->b),
566 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 567 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 568 tx_buffer->next_to_watch,
569 (u64)tx_buffer->time_stamp,
570 tx_buffer->skb);
571 if (i == tx_ring->next_to_use &&
572 i == tx_ring->next_to_clean)
573 pr_cont(" NTC/U\n");
574 else if (i == tx_ring->next_to_use)
575 pr_cont(" NTU\n");
576 else if (i == tx_ring->next_to_clean)
577 pr_cont(" NTC\n");
578 else
579 pr_cont("\n");
580
581 if (netif_msg_pktdata(adapter) &&
582 tx_buffer->skb)
583 print_hex_dump(KERN_INFO, "",
584 DUMP_PREFIX_ADDRESS, 16, 1,
585 tx_buffer->skb->data,
586 dma_unmap_len(tx_buffer, len),
587 true);
588 }
dcd79aeb
TI		 589 }
590 }
591
592 /* Print RX Rings Summary */
593rx_ring_summary:
594 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 595 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 596 for (n = 0; n < adapter->num_rx_queues; n++) {
597 rx_ring = adapter->rx_ring[n];
c7689578
JP		 598 pr_info("%5d %5X %5X\n",
599 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 600 }
601
602 /* Print RX Rings */
603 if (!netif_msg_rx_status(adapter))
604 goto exit;
605
606 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
607
39ac868a
JH		 608 /* Receive Descriptor Formats
609 *
610 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 611 * 63 1 0
612 * +-----------------------------------------------------+
613 * 0 | Packet Buffer Address [63:1] |A0/NSE|
614 * +----------------------------------------------+------+
615 * 8 | Header Buffer Address [63:1] | DD |
616 * +-----------------------------------------------------+
617 *
618 *
39ac868a 619 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 620 *
621 * 63 48 47 32 31 30 21 20 16 15 4 3 0
622 * +------------------------------------------------------+
39ac868a
JH		 623 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
624 * | Packet | IP | | | | Type | Type |
625 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 626 * +------------------------------------------------------+
627 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
628 * +------------------------------------------------------+
629 * 63 48 47 32 31 20 19 0
39ac868a
JH		 630 *
631 * 82599+ Advanced Receive Descriptor (Read) Format
632 * 63 1 0
633 * +-----------------------------------------------------+
634 * 0 | Packet Buffer Address [63:1] |A0/NSE|
635 * +----------------------------------------------+------+
636 * 8 | Header Buffer Address [63:1] | DD |
637 * +-----------------------------------------------------+
638 *
639 *
640 * 82599+ Advanced Receive Descriptor (Write-Back) Format
641 *
642 * 63 48 47 32 31 30 21 20 17 16 4 3 0
643 * +------------------------------------------------------+
644 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
645 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
646 * |/ Flow Dir Flt ID | | | | | |
647 * +------------------------------------------------------+
648 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
649 * +------------------------------------------------------+
650 * 63 48 47 32 31 20 19 0
dcd79aeb 651 */
39ac868a 652
dcd79aeb
TI		 653 for (n = 0; n < adapter->num_rx_queues; n++) {
654 rx_ring = adapter->rx_ring[n];
c7689578
JP		 655 pr_info("------------------------------------\n");
656 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
657 pr_info("------------------------------------\n");
8ad88e37
JH		 658 pr_info("%s%s%s",
659 "R [desc] [ PktBuf A0] ",
660 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 661 "<-- Adv Rx Read format\n");
8ad88e37
JH		 662 pr_info("%s%s%s",
663 "RWB[desc] [PcsmIpSHl PtRs] ",
664 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 665 "<-- Adv Rx Write-Back format\n");
666
667 for (i = 0; i < rx_ring->count; i++) {
668 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 669 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 670 u0 = (struct my_u0 *)rx_desc;
671 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
672 if (staterr & IXGBE_RXD_STAT_DD) {
673 /* Descriptor Done */
c7689578 674 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 675 "%016llX ---------------- %p", i,
676 le64_to_cpu(u0->a),
677 le64_to_cpu(u0->b),
678 rx_buffer_info->skb);
679 } else {
c7689578 680 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 681 "%016llX %016llX %p", i,
682 le64_to_cpu(u0->a),
683 le64_to_cpu(u0->b),
684 (u64)rx_buffer_info->dma,
685 rx_buffer_info->skb);
686
9c50c035
ET		 687 if (netif_msg_pktdata(adapter) &&
688 rx_buffer_info->dma) {
dcd79aeb
TI		 689 print_hex_dump(KERN_INFO, "",
690 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 691 page_address(rx_buffer_info->page) +
692 rx_buffer_info->page_offset,
f800326d 693 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 694 }
695 }
696
697 if (i == rx_ring->next_to_use)
c7689578 698 pr_cont(" NTU\n");
dcd79aeb 699 else if (i == rx_ring->next_to_clean)
c7689578 700 pr_cont(" NTC\n");
dcd79aeb 701 else
c7689578 702 pr_cont("\n");
dcd79aeb
TI		 703
704 }
705 }
706
707exit:
708 return;
709}
710
5eba3699
AV		 711static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
712{
713 u32 ctrl_ext;
714
715 /* Let firmware take over control of h/w */
716 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
717 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 718 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 719}
720
721static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
722{
723 u32 ctrl_ext;
724
725 /* Let firmware know the driver has taken over */
726 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
727 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 728 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 729}
9a799d71 730
49ce9c2c 731/**
e8e26350
PW		 732 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
733 * @adapter: pointer to adapter struct
734 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
735 * @queue: queue to map the corresponding interrupt to
736 * @msix_vector: the vector to map to the corresponding queue
737 *
738 */
739static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 740 u8 queue, u8 msix_vector)
9a799d71
AK		 741{
742 u32 ivar, index;
e8e26350
PW		 743 struct ixgbe_hw *hw = &adapter->hw;
744 switch (hw->mac.type) {
745 case ixgbe_mac_82598EB:
746 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
747 if (direction == -1)
748 direction = 0;
749 index = (((direction * 64) + queue) >> 2) & 0x1F;
750 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
751 ivar &= ~(0xFF << (8 * (queue & 0x3)));
752 ivar |= (msix_vector << (8 * (queue & 0x3)));
753 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
754 break;
755 case ixgbe_mac_82599EB:
b93a2226 756 case ixgbe_mac_X540:
e8e26350
PW		 757 if (direction == -1) {
758 /* other causes */
759 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
760 index = ((queue & 1) * 8);
761 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
762 ivar &= ~(0xFF << index);
763 ivar |= (msix_vector << index);
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
765 break;
766 } else {
767 /* tx or rx causes */
768 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
769 index = ((16 * (queue & 1)) + (8 * direction));
770 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
771 ivar &= ~(0xFF << index);
772 ivar |= (msix_vector << index);
773 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
774 break;
775 }
776 default:
777 break;
778 }
9a799d71
AK		 779}
780
fe49f04a 781static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 782 u64 qmask)
fe49f04a
AD		 783{
784 u32 mask;
785
bd508178
AD		 786 switch (adapter->hw.mac.type) {
787 case ixgbe_mac_82598EB:
fe49f04a
AD		 788 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 790 break;
791 case ixgbe_mac_82599EB:
b93a2226 792 case ixgbe_mac_X540:
fe49f04a
AD		 793 mask = (qmask & 0xFFFFFFFF);
794 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
795 mask = (qmask >> 32);
796 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 797 break;
798 default:
799 break;
fe49f04a
AD		 800 }
801}
802
729739b7
AD		 803void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
804 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 805{
729739b7
AD		 806 if (tx_buffer->skb) {
807 dev_kfree_skb_any(tx_buffer->skb);
808 if (dma_unmap_len(tx_buffer, len))
d3d00239 809 dma_unmap_single(ring->dev,
729739b7
AD		 810 dma_unmap_addr(tx_buffer, dma),
811 dma_unmap_len(tx_buffer, len),
812 DMA_TO_DEVICE);
813 } else if (dma_unmap_len(tx_buffer, len)) {
814 dma_unmap_page(ring->dev,
815 dma_unmap_addr(tx_buffer, dma),
816 dma_unmap_len(tx_buffer, len),
817 DMA_TO_DEVICE);
e5a43549 818 }
729739b7
AD		 819 tx_buffer->next_to_watch = NULL;
820 tx_buffer->skb = NULL;
821 dma_unmap_len_set(tx_buffer, len, 0);
822 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 823}
824
943561d3 825static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 826{
827 struct ixgbe_hw *hw = &adapter->hw;
828 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 829 int i;
943561d3 830 u32 data;
c84d324c 831
943561d3
AD		 832 if ((hw->fc.current_mode != ixgbe_fc_full) &&
833 (hw->fc.current_mode != ixgbe_fc_rx_pause))
834 return;
c84d324c 835
943561d3
AD		 836 switch (hw->mac.type) {
837 case ixgbe_mac_82598EB:
838 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
839 break;
840 default:
841 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
842 }
843 hwstats->lxoffrxc += data;
c84d324c 844
943561d3
AD		 845 /* refill credits (no tx hang) if we received xoff */
846 if (!data)
c84d324c 847 return;
943561d3
AD		 848
849 for (i = 0; i < adapter->num_tx_queues; i++)
850 clear_bit(__IXGBE_HANG_CHECK_ARMED,
851 &adapter->tx_ring[i]->state);
852}
853
854static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
855{
856 struct ixgbe_hw *hw = &adapter->hw;
857 struct ixgbe_hw_stats *hwstats = &adapter->stats;
858 u32 xoff[8] = {0};
2afaa00d 859 u8 tc;
943561d3
AD		 860 int i;
861 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
862
863 if (adapter->ixgbe_ieee_pfc)
864 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
865
866 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
867 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 868 return;
943561d3 869 }
c84d324c
JF		 870
871 /* update stats for each tc, only valid with PFC enabled */
872 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 873 u32 pxoffrxc;
874
c84d324c
JF		 875 switch (hw->mac.type) {
876 case ixgbe_mac_82598EB:
2afaa00d 877 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 878 break;
c84d324c 879 default:
2afaa00d 880 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 881 }
2afaa00d
PN		 882 hwstats->pxoffrxc[i] += pxoffrxc;
883 /* Get the TC for given UP */
884 tc = netdev_get_prio_tc_map(adapter->netdev, i);
885 xoff[tc] += pxoffrxc;
c84d324c
JF		 886 }
887
888 /* disarm tx queues that have received xoff frames */
889 for (i = 0; i < adapter->num_tx_queues; i++) {
890 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 891
2afaa00d 892 tc = tx_ring->dcb_tc;
c84d324c
JF		 893 if (xoff[tc])
894 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 895 }
26f23d82
YZ		 896}
897
c84d324c 898static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 899{
7d7ce682 900 return ring->stats.packets;
c84d324c
JF		 901}
902
903static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
904{
2a47fa45
JF		 905 struct ixgbe_adapter *adapter;
906 struct ixgbe_hw *hw;
907 u32 head, tail;
908
909 if (ring->l2_accel_priv)
910 adapter = ring->l2_accel_priv->real_adapter;
911 else
912 adapter = netdev_priv(ring->netdev);
e01c31a5 913
2a47fa45
JF		 914 hw = &adapter->hw;
915 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
916 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 917
918 if (head != tail)
919 return (head < tail) ?
920 tail - head : (tail + ring->count - head);
921
922 return 0;
923}
924
925static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
926{
927 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
928 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
929 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
930 bool ret = false;
931
7d637bcc 932 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 933
934 /*
935 * Check for a hung queue, but be thorough. This verifies
936 * that a transmit has been completed since the previous
937 * check AND there is at least one packet pending. The
938 * ARMED bit is set to indicate a potential hang. The
939 * bit is cleared if a pause frame is received to remove
940 * false hang detection due to PFC or 802.3x frames. By
941 * requiring this to fail twice we avoid races with
942 * pfc clearing the ARMED bit and conditions where we
943 * run the check_tx_hang logic with a transmit completion
944 * pending but without time to complete it yet.
945 */
946 if ((tx_done_old == tx_done) && tx_pending) {
947 /* make sure it is true for two checks in a row */
948 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
949 &tx_ring->state);
950 } else {
951 /* update completed stats and continue */
952 tx_ring->tx_stats.tx_done_old = tx_done;
953 /* reset the countdown */
954 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 955 }
956
c84d324c 957 return ret;
9a799d71
AK		 958}
959
c83c6cbd
AD		 960/**
961 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
962 * @adapter: driver private struct
963 **/
964static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
965{
966
967 /* Do the reset outside of interrupt context */
968 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
969 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 970 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 971 ixgbe_service_event_schedule(adapter);
972 }
973}
e01c31a5 974
9a799d71
AK		 975/**
976 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 977 * @q_vector: structure containing interrupt and ring information
e01c31a5 978 * @tx_ring: tx ring to clean
9a799d71 979 **/
fe49f04a 980static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 981 struct ixgbe_ring *tx_ring)
9a799d71 982{
fe49f04a 983 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 984 struct ixgbe_tx_buffer *tx_buffer;
985 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 986 unsigned int total_bytes = 0, total_packets = 0;
59224555 987 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 988 unsigned int i = tx_ring->next_to_clean;
989
990 if (test_bit(__IXGBE_DOWN, &adapter->state))
991 return true;
9a799d71 992
d3d00239 993 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 994 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 995 i -= tx_ring->count;
12207e49 996
729739b7 997 do {
d3d00239
AD		 998 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
999
1000 /* if next_to_watch is not set then there is no work pending */
1001 if (!eop_desc)
1002 break;
1003
7f83a9e6 1004 /* prevent any other reads prior to eop_desc */
7e63bf49 1005 read_barrier_depends();
7f83a9e6 1006
d3d00239
AD		 1007 /* if DD is not set pending work has not been completed */
1008 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1009 break;
8ad494b0 1010
d3d00239
AD		 1011 /* clear next_to_watch to prevent false hangs */
1012 tx_buffer->next_to_watch = NULL;
8ad494b0 1013
091a6246
AD		 1014 /* update the statistics for this packet */
1015 total_bytes += tx_buffer->bytecount;
1016 total_packets += tx_buffer->gso_segs;
1017
fd0db0ed
AD		 1018 /* free the skb */
1019 dev_kfree_skb_any(tx_buffer->skb);
1020
729739b7
AD		 1021 /* unmap skb header data */
1022 dma_unmap_single(tx_ring->dev,
1023 dma_unmap_addr(tx_buffer, dma),
1024 dma_unmap_len(tx_buffer, len),
1025 DMA_TO_DEVICE);
1026
fd0db0ed
AD		 1027 /* clear tx_buffer data */
1028 tx_buffer->skb = NULL;
729739b7 1029 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1030
729739b7
AD		 1031 /* unmap remaining buffers */
1032 while (tx_desc != eop_desc) {
d3d00239
AD		 1033 tx_buffer++;
1034 tx_desc++;
8ad494b0 1035 i++;
729739b7
AD		 1036 if (unlikely(!i)) {
1037 i -= tx_ring->count;
d3d00239 1038 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1039 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1040 }
e01c31a5 1041
729739b7
AD		 1042 /* unmap any remaining paged data */
1043 if (dma_unmap_len(tx_buffer, len)) {
1044 dma_unmap_page(tx_ring->dev,
1045 dma_unmap_addr(tx_buffer, dma),
1046 dma_unmap_len(tx_buffer, len),
1047 DMA_TO_DEVICE);
1048 dma_unmap_len_set(tx_buffer, len, 0);
1049 }
1050 }
1051
1052 /* move us one more past the eop_desc for start of next pkt */
1053 tx_buffer++;
1054 tx_desc++;
1055 i++;
1056 if (unlikely(!i)) {
1057 i -= tx_ring->count;
1058 tx_buffer = tx_ring->tx_buffer_info;
1059 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1060 }
1061
1062 /* issue prefetch for next Tx descriptor */
1063 prefetch(tx_desc);
12207e49 1064
729739b7
AD		 1065 /* update budget accounting */
1066 budget--;
1067 } while (likely(budget));
1068
1069 i += tx_ring->count;
9a799d71 1070 tx_ring->next_to_clean = i;
d3d00239 1071 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1072 tx_ring->stats.bytes += total_bytes;
bd198058 1073 tx_ring->stats.packets += total_packets;
d3d00239 1074 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1075 q_vector->tx.total_bytes += total_bytes;
1076 q_vector->tx.total_packets += total_packets;
b953799e 1077
c84d324c
JF		 1078 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1079 /* schedule immediate reset if we believe we hung */
1080 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1081 e_err(drv, "Detected Tx Unit Hang\n"
1082 " Tx Queue <%d>\n"
1083 " TDH, TDT <%x>, <%x>\n"
1084 " next_to_use <%x>\n"
1085 " next_to_clean <%x>\n"
1086 "tx_buffer_info[next_to_clean]\n"
1087 " time_stamp <%lx>\n"
1088 " jiffies <%lx>\n",
1089 tx_ring->queue_index,
1090 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1091 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1092 tx_ring->next_to_use, i,
1093 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1094
1095 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1096
1097 e_info(probe,
1098 "tx hang %d detected on queue %d, resetting adapter\n",
1099 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1100
b953799e 1101 /* schedule immediate reset if we believe we hung */
c83c6cbd 1102 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1103
1104 /* the adapter is about to reset, no point in enabling stuff */
59224555 1105 return true;
b953799e 1106 }
9a799d71 1107
b2d96e0a
AD		 1108 netdev_tx_completed_queue(txring_txq(tx_ring),
1109 total_packets, total_bytes);
1110
e092be60 1111#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1112 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1113 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1114 /* Make sure that anybody stopping the queue after this
1115 * sees the new next_to_clean.
1116 */
1117 smp_mb();
729739b7
AD		 1118 if (__netif_subqueue_stopped(tx_ring->netdev,
1119 tx_ring->queue_index)
1120 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1121 netif_wake_subqueue(tx_ring->netdev,
1122 tx_ring->queue_index);
5b7da515 1123 ++tx_ring->tx_stats.restart_queue;
30eba97a 1124 }
e092be60 1125 }
9a799d71 1126
59224555 1127 return !!budget;
9a799d71
AK		 1128}
1129
5dd2d332 1130#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1131static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1132 struct ixgbe_ring *tx_ring,
33cf09c9 1133 int cpu)
bd0362dd 1134{
33cf09c9 1135 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1136 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1137 u16 reg_offset;
33cf09c9 1138
33cf09c9
AD		 1139 switch (hw->mac.type) {
1140 case ixgbe_mac_82598EB:
bdda1a61 1141 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1142 break;
1143 case ixgbe_mac_82599EB:
b93a2226 1144 case ixgbe_mac_X540:
bdda1a61
AD		 1145 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1146 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1147 break;
1148 default:
bdda1a61
AD		 1149 /* for unknown hardware do not write register */
1150 return;
bd0362dd 1151 }
bdda1a61
AD		 1152
1153 /*
1154 * We can enable relaxed ordering for reads, but not writes when
1155 * DCA is enabled. This is due to a known issue in some chipsets
1156 * which will cause the DCA tag to be cleared.
1157 */
1158 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1159 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1160 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1161
1162 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1163}
1164
bdda1a61
AD		 1165static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1166 struct ixgbe_ring *rx_ring,
33cf09c9 1167 int cpu)
bd0362dd 1168{
33cf09c9 1169 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1170 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1171 u8 reg_idx = rx_ring->reg_idx;
1172
33cf09c9
AD		 1173
1174 switch (hw->mac.type) {
33cf09c9 1175 case ixgbe_mac_82599EB:
b93a2226 1176 case ixgbe_mac_X540:
bdda1a61 1177 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1178 break;
1179 default:
1180 break;
1181 }
bdda1a61
AD		 1182
1183 /*
1184 * We can enable relaxed ordering for reads, but not writes when
1185 * DCA is enabled. This is due to a known issue in some chipsets
1186 * which will cause the DCA tag to be cleared.
1187 */
1188 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1189 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1190
1191 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1192}
1193
1194static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1195{
1196 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1197 struct ixgbe_ring *ring;
bd0362dd 1198 int cpu = get_cpu();
bd0362dd 1199
33cf09c9
AD		 1200 if (q_vector->cpu == cpu)
1201 goto out_no_update;
1202
a557928e 1203 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1204 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1205
a557928e 1206 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1207 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1208
1209 q_vector->cpu = cpu;
1210out_no_update:
bd0362dd
JC		 1211 put_cpu();
1212}
1213
1214static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1215{
1216 int i;
1217
1218 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1219 return;
1220
e35ec126
AD		 1221 /* always use CB2 mode, difference is masked in the CB driver */
1222 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1223
49c7ffbe 1224 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1225 adapter->q_vector[i]->cpu = -1;
1226 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1227 }
1228}
1229
1230static int __ixgbe_notify_dca(struct device *dev, void *data)
1231{
c60fbb00 1232 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1233 unsigned long event = *(unsigned long *)data;
1234
2a72c31e 1235 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1236 return 0;
1237
bd0362dd
JC		 1238 switch (event) {
1239 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1240 /* if we're already enabled, don't do it again */
1241 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1242 break;
652f093f 1243 if (dca_add_requester(dev) == 0) {
96b0e0f6 1244 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1245 ixgbe_setup_dca(adapter);
1246 break;
1247 }
1248 /* Fall Through since DCA is disabled. */
1249 case DCA_PROVIDER_REMOVE:
1250 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1251 dca_remove_requester(dev);
1252 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1254 }
1255 break;
1256 }
1257
652f093f 1258 return 0;
bd0362dd 1259}
67a74ee2 1260
bdda1a61 1261#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1262static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1263 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1264 struct sk_buff *skb)
1265{
8a0da21b
AD		 1266 if (ring->netdev->features & NETIF_F_RXHASH)
1267 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1268}
1269
f800326d 1270#ifdef IXGBE_FCOE
ff886dfc
AD		 1271/**
1272 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1273 * @ring: structure containing ring specific data
ff886dfc
AD		 1274 * @rx_desc: advanced rx descriptor
1275 *
1276 * Returns : true if it is FCoE pkt
1277 */
57efd44c 1278static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1279 union ixgbe_adv_rx_desc *rx_desc)
1280{
1281 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1282
57efd44c 1283 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1284 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1285 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1286 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1287}
1288
f800326d 1289#endif /* IXGBE_FCOE */
e59bd25d
AV		 1290/**
1291 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1292 * @ring: structure containing ring specific data
1293 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1294 * @skb: skb currently being received and modified
1295 **/
8a0da21b 1296static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1297 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1298 struct sk_buff *skb)
9a799d71 1299{
8a0da21b 1300 skb_checksum_none_assert(skb);
9a799d71 1301
712744be 1302 /* Rx csum disabled */
8a0da21b 1303 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1304 return;
e59bd25d
AV		 1305
1306 /* if IP and error */
f56e0cb1
AD		 1307 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1308 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1309 ring->rx_stats.csum_err++;
9a799d71
AK		 1310 return;
1311 }
e59bd25d 1312
f56e0cb1 1313 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1314 return;
1315
f56e0cb1 1316 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1317 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1318
1319 /*
1320 * 82599 errata, UDP frames with a 0 checksum can be marked as
1321 * checksum errors.
1322 */
8a0da21b
AD		 1323 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1324 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1325 return;
1326
8a0da21b 1327 ring->rx_stats.csum_err++;
e59bd25d
AV		 1328 return;
1329 }
1330
9a799d71 1331 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1332 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1333}
1334
84ea2591 1335static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1336{
f56e0cb1 1337 rx_ring->next_to_use = val;
f800326d
AD		 1338
1339 /* update next to alloc since we have filled the ring */
1340 rx_ring->next_to_alloc = val;
e8e26350
PW		 1341 /*
1342 * Force memory writes to complete before letting h/w
1343 * know there are new descriptors to fetch. (Only
1344 * applicable for weak-ordered memory model archs,
1345 * such as IA-64).
1346 */
1347 wmb();
84227bcd 1348 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1349}
1350
f990b79b
AD		 1351static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1352 struct ixgbe_rx_buffer *bi)
1353{
1354 struct page *page = bi->page;
f800326d 1355 dma_addr_t dma = bi->dma;
f990b79b 1356
f800326d
AD		 1357 /* since we are recycling buffers we should seldom need to alloc */
1358 if (likely(dma))
f990b79b
AD		 1359 return true;
1360
f800326d
AD		 1361 /* alloc new page for storage */
1362 if (likely(!page)) {
0614002b
MG		 1363 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1364 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1365 if (unlikely(!page)) {
1366 rx_ring->rx_stats.alloc_rx_page_failed++;
1367 return false;
1368 }
f800326d 1369 bi->page = page;
f990b79b
AD		 1370 }
1371
f800326d
AD		 1372 /* map page for use */
1373 dma = dma_map_page(rx_ring->dev, page, 0,
1374 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1375
1376 /*
1377 * if mapping failed free memory back to system since
1378 * there isn't much point in holding memory we can't use
1379 */
1380 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1381 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1382 bi->page = NULL;
f990b79b 1383
f990b79b
AD		 1384 rx_ring->rx_stats.alloc_rx_page_failed++;
1385 return false;
1386 }
1387
f800326d 1388 bi->dma = dma;
afaa9459 1389 bi->page_offset = 0;
f800326d 1390
f990b79b
AD		 1391 return true;
1392}
1393
9a799d71 1394/**
f990b79b 1395 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1396 * @rx_ring: ring to place buffers on
1397 * @cleaned_count: number of buffers to replace
9a799d71 1398 **/
fc77dc3c 1399void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1400{
9a799d71 1401 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1402 struct ixgbe_rx_buffer *bi;
d5f398ed 1403 u16 i = rx_ring->next_to_use;
9a799d71 1404
f800326d
AD		 1405 /* nothing to do */
1406 if (!cleaned_count)
fc77dc3c
AD		 1407 return;
1408
e4f74028 1409 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1410 bi = &rx_ring->rx_buffer_info[i];
1411 i -= rx_ring->count;
9a799d71 1412
f800326d
AD		 1413 do {
1414 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1415 break;
d5f398ed 1416
f800326d
AD		 1417 /*
1418 * Refresh the desc even if buffer_addrs didn't change
1419 * because each write-back erases this info.
1420 */
1421 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1422
f990b79b
AD		 1423 rx_desc++;
1424 bi++;
9a799d71 1425 i++;
f990b79b 1426 if (unlikely(!i)) {
e4f74028 1427 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1428 bi = rx_ring->rx_buffer_info;
1429 i -= rx_ring->count;
1430 }
1431
1432 /* clear the hdr_addr for the next_to_use descriptor */
1433 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1434
1435 cleaned_count--;
1436 } while (cleaned_count);
7c6e0a43 1437
f990b79b
AD		 1438 i += rx_ring->count;
1439
f56e0cb1 1440 if (rx_ring->next_to_use != i)
84ea2591 1441 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1442}
1443
1d2024f6
AD		 1444/**
1445 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1446 * @data: pointer to the start of the headers
1447 * @max_len: total length of section to find headers in
1448 *
1449 * This function is meant to determine the length of headers that will
1450 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1451 * motivation of doing this is to only perform one pull for IPv4 TCP
1452 * packets so that we can do basic things like calculating the gso_size
1453 * based on the average data per packet.
1454 **/
1455static unsigned int ixgbe_get_headlen(unsigned char *data,
1456 unsigned int max_len)
1457{
1458 union {
1459 unsigned char *network;
1460 /* l2 headers */
1461 struct ethhdr *eth;
1462 struct vlan_hdr *vlan;
1463 /* l3 headers */
1464 struct iphdr *ipv4;
a048b40e 1465 struct ipv6hdr *ipv6;
1d2024f6
AD		 1466 } hdr;
1467 __be16 protocol;
1468 u8 nexthdr = 0; /* default to not TCP */
1469 u8 hlen;
1470
1471 /* this should never happen, but better safe than sorry */
1472 if (max_len < ETH_HLEN)
1473 return max_len;
1474
1475 /* initialize network frame pointer */
1476 hdr.network = data;
1477
1478 /* set first protocol and move network header forward */
1479 protocol = hdr.eth->h_proto;
1480 hdr.network += ETH_HLEN;
1481
1482 /* handle any vlan tag if present */
1483 if (protocol == __constant_htons(ETH_P_8021Q)) {
1484 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1485 return max_len;
1486
1487 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1488 hdr.network += VLAN_HLEN;
1489 }
1490
1491 /* handle L3 protocols */
1492 if (protocol == __constant_htons(ETH_P_IP)) {
1493 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1494 return max_len;
1495
1496 /* access ihl as a u8 to avoid unaligned access on ia64 */
1497 hlen = (hdr.network[0] & 0x0F) << 2;
1498
1499 /* verify hlen meets minimum size requirements */
1500 if (hlen < sizeof(struct iphdr))
1501 return hdr.network - data;
1502
ed83da12 1503 /* record next protocol if header is present */
20967f42 1504 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1505 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1506 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1507 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1508 return max_len;
1509
1510 /* record next protocol */
1511 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1512 hlen = sizeof(struct ipv6hdr);
f800326d 1513#ifdef IXGBE_FCOE
1d2024f6
AD		 1514 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1515 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1516 return max_len;
ed83da12 1517 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1518#endif
1519 } else {
1520 return hdr.network - data;
1521 }
1522
ed83da12
AD		 1523 /* relocate pointer to start of L4 header */
1524 hdr.network += hlen;
1525
a048b40e 1526 /* finally sort out TCP/UDP */
1d2024f6
AD		 1527 if (nexthdr == IPPROTO_TCP) {
1528 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1529 return max_len;
1530
1531 /* access doff as a u8 to avoid unaligned access on ia64 */
1532 hlen = (hdr.network[12] & 0xF0) >> 2;
1533
1534 /* verify hlen meets minimum size requirements */
1535 if (hlen < sizeof(struct tcphdr))
1536 return hdr.network - data;
1537
1538 hdr.network += hlen;
a048b40e
AD		 1539 } else if (nexthdr == IPPROTO_UDP) {
1540 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1541 return max_len;
1542
1543 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1544 }
1545
1546 /*
1547 * If everything has gone correctly hdr.network should be the
1548 * data section of the packet and will be the end of the header.
1549 * If not then it probably represents the end of the last recognized
1550 * header.
1551 */
1552 if ((hdr.network - data) < max_len)
1553 return hdr.network - data;
1554 else
1555 return max_len;
1556}
1557
1d2024f6
AD		 1558static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1559 struct sk_buff *skb)
1560{
f800326d 1561 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1562
1563 /* set gso_size to avoid messing up TCP MSS */
1564 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1565 IXGBE_CB(skb)->append_cnt);
96be80ab 1566 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1567}
1568
1569static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1570 struct sk_buff *skb)
1571{
1572 /* if append_cnt is 0 then frame is not RSC */
1573 if (!IXGBE_CB(skb)->append_cnt)
1574 return;
1575
1576 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1577 rx_ring->rx_stats.rsc_flush++;
1578
1579 ixgbe_set_rsc_gso_size(rx_ring, skb);
1580
1581 /* gso_size is computed using append_cnt so always clear it last */
1582 IXGBE_CB(skb)->append_cnt = 0;
1583}
1584
8a0da21b
AD		 1585/**
1586 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1587 * @rx_ring: rx descriptor ring packet is being transacted on
1588 * @rx_desc: pointer to the EOP Rx descriptor
1589 * @skb: pointer to current skb being populated
f8212f97 1590 *
8a0da21b
AD		 1591 * This function checks the ring, descriptor, and packet information in
1592 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1593 * other fields within the skb.
f8212f97 1594 **/
8a0da21b
AD		 1595static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1596 union ixgbe_adv_rx_desc *rx_desc,
1597 struct sk_buff *skb)
f8212f97 1598{
43e95f11
JF		 1599 struct net_device *dev = rx_ring->netdev;
1600
8a0da21b
AD		 1601 ixgbe_update_rsc_stats(rx_ring, skb);
1602
1603 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1604
8a0da21b
AD		 1605 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1606
6cb562d6 1607 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1608
f646968f 1609 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1610 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1611 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1612 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1613 }
1614
8a0da21b 1615 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1616
43e95f11 1617 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1618}
1619
8a0da21b
AD		 1620static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1621 struct sk_buff *skb)
aa80175a 1622{
8a0da21b
AD		 1623 struct ixgbe_adapter *adapter = q_vector->adapter;
1624
b4640030 1625 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1626 netif_receive_skb(skb);
1627 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1628 napi_gro_receive(&q_vector->napi, skb);
1629 else
1630 netif_rx(skb);
aa80175a 1631}
43634e82 1632
f800326d
AD		 1633/**
1634 * ixgbe_is_non_eop - process handling of non-EOP buffers
1635 * @rx_ring: Rx ring being processed
1636 * @rx_desc: Rx descriptor for current buffer
1637 * @skb: Current socket buffer containing buffer in progress
1638 *
1639 * This function updates next to clean. If the buffer is an EOP buffer
1640 * this function exits returning false, otherwise it will place the
1641 * sk_buff in the next buffer to be chained and return true indicating
1642 * that this is in fact a non-EOP buffer.
1643 **/
1644static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1645 union ixgbe_adv_rx_desc *rx_desc,
1646 struct sk_buff *skb)
1647{
1648 u32 ntc = rx_ring->next_to_clean + 1;
1649
1650 /* fetch, update, and store next to clean */
1651 ntc = (ntc < rx_ring->count) ? ntc : 0;
1652 rx_ring->next_to_clean = ntc;
1653
1654 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1655
5a02cbd1
AD		 1656 /* update RSC append count if present */
1657 if (ring_is_rsc_enabled(rx_ring)) {
1658 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1659 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1660
1661 if (unlikely(rsc_enabled)) {
1662 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1663
1664 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1665 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1666
5a02cbd1
AD		 1667 /* update ntc based on RSC value */
1668 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1669 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1670 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1671 }
f800326d
AD		 1672 }
1673
5a02cbd1
AD		 1674 /* if we are the last buffer then there is nothing else to do */
1675 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1676 return false;
1677
f800326d
AD		 1678 /* place skb in next buffer to be received */
1679 rx_ring->rx_buffer_info[ntc].skb = skb;
1680 rx_ring->rx_stats.non_eop_descs++;
1681
1682 return true;
1683}
1684
19861ce2
AD		 1685/**
1686 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1687 * @rx_ring: rx descriptor ring packet is being transacted on
1688 * @skb: pointer to current skb being adjusted
1689 *
1690 * This function is an ixgbe specific version of __pskb_pull_tail. The
1691 * main difference between this version and the original function is that
1692 * this function can make several assumptions about the state of things
1693 * that allow for significant optimizations versus the standard function.
1694 * As a result we can do things like drop a frag and maintain an accurate
1695 * truesize for the skb.
1696 */
1697static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1698 struct sk_buff *skb)
1699{
1700 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1701 unsigned char *va;
1702 unsigned int pull_len;
1703
1704 /*
1705 * it is valid to use page_address instead of kmap since we are
1706 * working with pages allocated out of the lomem pool per
1707 * alloc_page(GFP_ATOMIC)
1708 */
1709 va = skb_frag_address(frag);
1710
1711 /*
1712 * we need the header to contain the greater of either ETH_HLEN or
1713 * 60 bytes if the skb->len is less than 60 for skb_pad.
1714 */
cf3fe7ac 1715 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1716
1717 /* align pull length to size of long to optimize memcpy performance */
1718 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1719
1720 /* update all of the pointers */
1721 skb_frag_size_sub(frag, pull_len);
1722 frag->page_offset += pull_len;
1723 skb->data_len -= pull_len;
1724 skb->tail += pull_len;
19861ce2
AD		 1725}
1726
42073d91
AD		 1727/**
1728 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1729 * @rx_ring: rx descriptor ring packet is being transacted on
1730 * @skb: pointer to current skb being updated
1731 *
1732 * This function provides a basic DMA sync up for the first fragment of an
1733 * skb. The reason for doing this is that the first fragment cannot be
1734 * unmapped until we have reached the end of packet descriptor for a buffer
1735 * chain.
1736 */
1737static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1738 struct sk_buff *skb)
1739{
1740 /* if the page was released unmap it, else just sync our portion */
1741 if (unlikely(IXGBE_CB(skb)->page_released)) {
1742 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1743 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1744 IXGBE_CB(skb)->page_released = false;
1745 } else {
1746 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1747
1748 dma_sync_single_range_for_cpu(rx_ring->dev,
1749 IXGBE_CB(skb)->dma,
1750 frag->page_offset,
1751 ixgbe_rx_bufsz(rx_ring),
1752 DMA_FROM_DEVICE);
1753 }
1754 IXGBE_CB(skb)->dma = 0;
1755}
1756
f800326d
AD		 1757/**
1758 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1759 * @rx_ring: rx descriptor ring packet is being transacted on
1760 * @rx_desc: pointer to the EOP Rx descriptor
1761 * @skb: pointer to current skb being fixed
1762 *
1763 * Check for corrupted packet headers caused by senders on the local L2
1764 * embedded NIC switch not setting up their Tx Descriptors right. These
1765 * should be very rare.
1766 *
1767 * Also address the case where we are pulling data in on pages only
1768 * and as such no data is present in the skb header.
1769 *
1770 * In addition if skb is not at least 60 bytes we need to pad it so that
1771 * it is large enough to qualify as a valid Ethernet frame.
1772 *
1773 * Returns true if an error was encountered and skb was freed.
1774 **/
1775static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1776 union ixgbe_adv_rx_desc *rx_desc,
1777 struct sk_buff *skb)
1778{
f800326d 1779 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1780
1781 /* verify that the packet does not have any known errors */
1782 if (unlikely(ixgbe_test_staterr(rx_desc,
1783 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1784 !(netdev->features & NETIF_F_RXALL))) {
1785 dev_kfree_skb_any(skb);
1786 return true;
1787 }
1788
19861ce2 1789 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1790 if (skb_is_nonlinear(skb))
1791 ixgbe_pull_tail(rx_ring, skb);
f800326d 1792
57efd44c
AD		 1793#ifdef IXGBE_FCOE
1794 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1795 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1796 return false;
1797
1798#endif
f800326d
AD		 1799 /* if skb_pad returns an error the skb was freed */
1800 if (unlikely(skb->len < 60)) {
1801 int pad_len = 60 - skb->len;
1802
1803 if (skb_pad(skb, pad_len))
1804 return true;
1805 __skb_put(skb, pad_len);
1806 }
1807
1808 return false;
1809}
1810
f800326d
AD		 1811/**
1812 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1813 * @rx_ring: rx descriptor ring to store buffers on
1814 * @old_buff: donor buffer to have page reused
1815 *
0549ae20 1816 * Synchronizes page for reuse by the adapter
f800326d
AD		 1817 **/
1818static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1819 struct ixgbe_rx_buffer *old_buff)
1820{
1821 struct ixgbe_rx_buffer *new_buff;
1822 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1823
1824 new_buff = &rx_ring->rx_buffer_info[nta];
1825
1826 /* update, and store next to alloc */
1827 nta++;
1828 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1829
1830 /* transfer page from old buffer to new buffer */
1831 new_buff->page = old_buff->page;
1832 new_buff->dma = old_buff->dma;
0549ae20 1833 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1834
1835 /* sync the buffer for use by the device */
1836 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1837 new_buff->page_offset,
1838 ixgbe_rx_bufsz(rx_ring),
f800326d 1839 DMA_FROM_DEVICE);
f800326d
AD		 1840}
1841
1842/**
1843 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1844 * @rx_ring: rx descriptor ring to transact packets on
1845 * @rx_buffer: buffer containing page to add
1846 * @rx_desc: descriptor containing length of buffer written by hardware
1847 * @skb: sk_buff to place the data into
1848 *
0549ae20
AD		 1849 * This function will add the data contained in rx_buffer->page to the skb.
1850 * This is done either through a direct copy if the data in the buffer is
1851 * less than the skb header size, otherwise it will just attach the page as
1852 * a frag to the skb.
1853 *
1854 * The function will then update the page offset if necessary and return
1855 * true if the buffer can be reused by the adapter.
f800326d 1856 **/
0549ae20 1857static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1858 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1859 union ixgbe_adv_rx_desc *rx_desc,
1860 struct sk_buff *skb)
f800326d 1861{
0549ae20
AD		 1862 struct page *page = rx_buffer->page;
1863 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1864#if (PAGE_SIZE < 8192)
0549ae20 1865 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1866#else
1867 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1868 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1869 ixgbe_rx_bufsz(rx_ring);
1870#endif
0549ae20 1871
cf3fe7ac
AD		 1872 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1873 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1874
1875 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1876
1877 /* we can reuse buffer as-is, just make sure it is local */
1878 if (likely(page_to_nid(page) == numa_node_id()))
1879 return true;
1880
1881 /* this page cannot be reused so discard it */
1882 put_page(page);
1883 return false;
1884 }
1885
0549ae20
AD		 1886 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1887 rx_buffer->page_offset, size, truesize);
1888
09816fbe
AD		 1889 /* avoid re-using remote pages */
1890 if (unlikely(page_to_nid(page) != numa_node_id()))
1891 return false;
1892
1893#if (PAGE_SIZE < 8192)
1894 /* if we are only owner of page we can reuse it */
1895 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1896 return false;
1897
1898 /* flip page offset to other buffer */
1899 rx_buffer->page_offset ^= truesize;
1900
09816fbe
AD		 1901 /*
1902 * since we are the only owner of the page and we need to
1903 * increment it, just set the value to 2 in order to avoid
1904 * an unecessary locked operation
1905 */
1906 atomic_set(&page->_count, 2);
1907#else
1908 /* move offset up to the next cache line */
1909 rx_buffer->page_offset += truesize;
1910
1911 if (rx_buffer->page_offset > last_offset)
1912 return false;
1913
0549ae20
AD		 1914 /* bump ref count on page before it is given to the stack */
1915 get_page(page);
09816fbe 1916#endif
0549ae20
AD		 1917
1918 return true;
f800326d
AD		 1919}
1920
18806c9e
AD		 1921static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1922 union ixgbe_adv_rx_desc *rx_desc)
1923{
1924 struct ixgbe_rx_buffer *rx_buffer;
1925 struct sk_buff *skb;
1926 struct page *page;
1927
1928 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1929 page = rx_buffer->page;
1930 prefetchw(page);
1931
1932 skb = rx_buffer->skb;
1933
1934 if (likely(!skb)) {
1935 void *page_addr = page_address(page) +
1936 rx_buffer->page_offset;
1937
1938 /* prefetch first cache line of first page */
1939 prefetch(page_addr);
1940#if L1_CACHE_BYTES < 128
1941 prefetch(page_addr + L1_CACHE_BYTES);
1942#endif
1943
1944 /* allocate a skb to store the frags */
1945 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1946 IXGBE_RX_HDR_SIZE);
1947 if (unlikely(!skb)) {
1948 rx_ring->rx_stats.alloc_rx_buff_failed++;
1949 return NULL;
1950 }
1951
1952 /*
1953 * we will be copying header into skb->data in
1954 * pskb_may_pull so it is in our interest to prefetch
1955 * it now to avoid a possible cache miss
1956 */
1957 prefetchw(skb->data);
1958
1959 /*
1960 * Delay unmapping of the first packet. It carries the
1961 * header information, HW may still access the header
1962 * after the writeback. Only unmap it when EOP is
1963 * reached
1964 */
1965 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1966 goto dma_sync;
1967
1968 IXGBE_CB(skb)->dma = rx_buffer->dma;
1969 } else {
1970 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1971 ixgbe_dma_sync_frag(rx_ring, skb);
1972
1973dma_sync:
1974 /* we are reusing so sync this buffer for CPU use */
1975 dma_sync_single_range_for_cpu(rx_ring->dev,
1976 rx_buffer->dma,
1977 rx_buffer->page_offset,
1978 ixgbe_rx_bufsz(rx_ring),
1979 DMA_FROM_DEVICE);
1980 }
1981
1982 /* pull page into skb */
1983 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1984 /* hand second half of page back to the ring */
1985 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1986 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1987 /* the page has been released from the ring */
1988 IXGBE_CB(skb)->page_released = true;
1989 } else {
1990 /* we are not reusing the buffer so unmap it */
1991 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1992 ixgbe_rx_pg_size(rx_ring),
1993 DMA_FROM_DEVICE);
1994 }
1995
1996 /* clear contents of buffer_info */
1997 rx_buffer->skb = NULL;
1998 rx_buffer->dma = 0;
1999 rx_buffer->page = NULL;
2000
2001 return skb;
f800326d
AD		 2002}
2003
2004/**
2005 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2006 * @q_vector: structure containing interrupt and ring information
2007 * @rx_ring: rx descriptor ring to transact packets on
2008 * @budget: Total limit on number of packets to process
2009 *
2010 * This function provides a "bounce buffer" approach to Rx interrupt
2011 * processing. The advantage to this is that on systems that have
2012 * expensive overhead for IOMMU access this provides a means of avoiding
2013 * it by maintaining the mapping of the page to the syste.
2014 *
5a85e737 2015 * Returns amount of work completed
f800326d 2016 **/
5a85e737 2017static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2018 struct ixgbe_ring *rx_ring,
f4de00ed 2019 const int budget)
9a799d71 2020{
d2f4fbe2 2021 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2022#ifdef IXGBE_FCOE
f800326d 2023 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2024 int ddp_bytes;
2025 unsigned int mss = 0;
3d8fd385 2026#endif /* IXGBE_FCOE */
f800326d 2027 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2028
f800326d 2029 do {
f800326d
AD		 2030 union ixgbe_adv_rx_desc *rx_desc;
2031 struct sk_buff *skb;
f800326d
AD		 2032
2033 /* return some buffers to hardware, one at a time is too slow */
2034 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2035 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2036 cleaned_count = 0;
2037 }
2038
18806c9e 2039 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2040
2041 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2042 break;
9a799d71 2043
f800326d
AD		 2044 /*
2045 * This memory barrier is needed to keep us from reading
2046 * any other fields out of the rx_desc until we know the
2047 * RXD_STAT_DD bit is set
2048 */
2049 rmb();
9a799d71 2050
18806c9e
AD		 2051 /* retrieve a buffer from the ring */
2052 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2053
18806c9e
AD		 2054 /* exit if we failed to retrieve a buffer */
2055 if (!skb)
2056 break;
9a799d71 2057
9a799d71 2058 cleaned_count++;
f8212f97 2059
f800326d
AD		 2060 /* place incomplete frames back on ring for completion */
2061 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2062 continue;
c267fc16 2063
f800326d
AD		 2064 /* verify the packet layout is correct */
2065 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2066 continue;
9a799d71 2067
d2f4fbe2
AV		 2068 /* probably a little skewed due to removing CRC */
2069 total_rx_bytes += skb->len;
d2f4fbe2 2070
8a0da21b
AD		 2071 /* populate checksum, timestamp, VLAN, and protocol */
2072 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2073
332d4a7d
YZ		 2074#ifdef IXGBE_FCOE
2075 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2076 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2077 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2078 /* include DDPed FCoE data */
2079 if (ddp_bytes > 0) {
2080 if (!mss) {
2081 mss = rx_ring->netdev->mtu -
2082 sizeof(struct fcoe_hdr) -
2083 sizeof(struct fc_frame_header) -
2084 sizeof(struct fcoe_crc_eof);
2085 if (mss > 512)
2086 mss &= ~511;
2087 }
2088 total_rx_bytes += ddp_bytes;
2089 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2090 mss);
2091 }
63d635b2
AD		 2092 if (!ddp_bytes) {
2093 dev_kfree_skb_any(skb);
f800326d 2094 continue;
63d635b2 2095 }
3d8fd385 2096 }
f800326d 2097
332d4a7d 2098#endif /* IXGBE_FCOE */
8b80cda5 2099 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2100 ixgbe_rx_skb(q_vector, skb);
9a799d71 2101
f800326d 2102 /* update budget accounting */
f4de00ed
AD		 2103 total_rx_packets++;
2104 } while (likely(total_rx_packets < budget));
9a799d71 2105
c267fc16
AD		 2106 u64_stats_update_begin(&rx_ring->syncp);
2107 rx_ring->stats.packets += total_rx_packets;
2108 rx_ring->stats.bytes += total_rx_bytes;
2109 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2110 q_vector->rx.total_packets += total_rx_packets;
2111 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2112
f800326d
AD		 2113 if (cleaned_count)
2114 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2115
5a85e737 2116 return total_rx_packets;
9a799d71
AK		 2117}
2118
e0d1095a 2119#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2120/* must be called with local_bh_disable()d */
2121static int ixgbe_low_latency_recv(struct napi_struct *napi)
2122{
2123 struct ixgbe_q_vector *q_vector =
2124 container_of(napi, struct ixgbe_q_vector, napi);
2125 struct ixgbe_adapter *adapter = q_vector->adapter;
2126 struct ixgbe_ring *ring;
2127 int found = 0;
2128
2129 if (test_bit(__IXGBE_DOWN, &adapter->state))
2130 return LL_FLUSH_FAILED;
2131
2132 if (!ixgbe_qv_lock_poll(q_vector))
2133 return LL_FLUSH_BUSY;
2134
2135 ixgbe_for_each_ring(ring, q_vector->rx) {
2136 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2137#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2138 if (found)
2139 ring->stats.cleaned += found;
2140 else
2141 ring->stats.misses++;
2142#endif
5a85e737
ET		 2143 if (found)
2144 break;
2145 }
2146
2147 ixgbe_qv_unlock_poll(q_vector);
2148
2149 return found;
2150}
e0d1095a 2151#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2152
9a799d71
AK		 2153/**
2154 * ixgbe_configure_msix - Configure MSI-X hardware
2155 * @adapter: board private structure
2156 *
2157 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2158 * interrupts.
2159 **/
2160static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2161{
021230d4 2162 struct ixgbe_q_vector *q_vector;
49c7ffbe 2163 int v_idx;
021230d4 2164 u32 mask;
9a799d71 2165
8e34d1aa
AD		 2166 /* Populate MSIX to EITR Select */
2167 if (adapter->num_vfs > 32) {
2168 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2170 }
2171
4df10466
JB		 2172 /*
2173 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2174 * corresponding register.
2175 */
49c7ffbe 2176 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2177 struct ixgbe_ring *ring;
7a921c93 2178 q_vector = adapter->q_vector[v_idx];
021230d4 2179
a557928e 2180 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2181 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2182
a557928e 2183 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2184 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2185
fe49f04a 2186 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2187 }
2188
bd508178
AD		 2189 switch (adapter->hw.mac.type) {
2190 case ixgbe_mac_82598EB:
e8e26350 2191 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2192 v_idx);
bd508178
AD		 2193 break;
2194 case ixgbe_mac_82599EB:
b93a2226 2195 case ixgbe_mac_X540:
e8e26350 2196 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2197 break;
bd508178
AD		 2198 default:
2199 break;
2200 }
021230d4
AV		 2201 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2202
41fb9248 2203 /* set up to autoclear timer, and the vectors */
021230d4 2204 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2205 mask &= ~(IXGBE_EIMS_OTHER |
2206 IXGBE_EIMS_MAILBOX |
2207 IXGBE_EIMS_LSC);
2208
021230d4 2209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2210}
2211
f494e8fa
AV		 2212enum latency_range {
2213 lowest_latency = 0,
2214 low_latency = 1,
2215 bulk_latency = 2,
2216 latency_invalid = 255
2217};
2218
2219/**
2220 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2221 * @q_vector: structure containing interrupt and ring information
2222 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2223 *
2224 * Stores a new ITR value based on packets and byte
2225 * counts during the last interrupt. The advantage of per interrupt
2226 * computation is faster updates and more accurate ITR for the current
2227 * traffic pattern. Constants in this function were computed
2228 * based on theoretical maximum wire speed and thresholds were set based
2229 * on testing data as well as attempting to minimize response time
2230 * while increasing bulk throughput.
2231 * this functionality is controlled by the InterruptThrottleRate module
2232 * parameter (see ixgbe_param.c)
2233 **/
bd198058
AD		 2234static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2235 struct ixgbe_ring_container *ring_container)
f494e8fa 2236{
bd198058
AD		 2237 int bytes = ring_container->total_bytes;
2238 int packets = ring_container->total_packets;
2239 u32 timepassed_us;
621bd70e 2240 u64 bytes_perint;
bd198058 2241 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2242
2243 if (packets == 0)
bd198058 2244 return;
f494e8fa
AV		 2245
2246 /* simple throttlerate management
621bd70e
AD		 2247 * 0-10MB/s lowest (100000 ints/s)
2248 * 10-20MB/s low (20000 ints/s)
2249 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2250 */
2251 /* what was last interrupt timeslice? */
d5bf4f67 2252 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2253 if (timepassed_us == 0)
2254 return;
2255
f494e8fa
AV		 2256 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2257
2258 switch (itr_setting) {
2259 case lowest_latency:
621bd70e 2260 if (bytes_perint > 10)
bd198058 2261 itr_setting = low_latency;
f494e8fa
AV		 2262 break;
2263 case low_latency:
621bd70e 2264 if (bytes_perint > 20)
bd198058 2265 itr_setting = bulk_latency;
621bd70e 2266 else if (bytes_perint <= 10)
bd198058 2267 itr_setting = lowest_latency;
f494e8fa
AV		 2268 break;
2269 case bulk_latency:
621bd70e 2270 if (bytes_perint <= 20)
bd198058 2271 itr_setting = low_latency;
f494e8fa
AV		 2272 break;
2273 }
2274
bd198058
AD		 2275 /* clear work counters since we have the values we need */
2276 ring_container->total_bytes = 0;
2277 ring_container->total_packets = 0;
2278
2279 /* write updated itr to ring container */
2280 ring_container->itr = itr_setting;
f494e8fa
AV		 2281}
2282
509ee935
JB		 2283/**
2284 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2285 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2286 *
2287 * This function is made to be called by ethtool and by the driver
2288 * when it needs to update EITR registers at runtime. Hardware
2289 * specific quirks/differences are taken care of here.
2290 */
fe49f04a 2291void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2292{
fe49f04a 2293 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2294 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2295 int v_idx = q_vector->v_idx;
5d967eb7 2296 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2297
bd508178
AD		 2298 switch (adapter->hw.mac.type) {
2299 case ixgbe_mac_82598EB:
509ee935
JB		 2300 /* must write high and low 16 bits to reset counter */
2301 itr_reg |= (itr_reg << 16);
bd508178
AD		 2302 break;
2303 case ixgbe_mac_82599EB:
b93a2226 2304 case ixgbe_mac_X540:
509ee935
JB		 2305 /*
2306 * set the WDIS bit to not clear the timer bits and cause an
2307 * immediate assertion of the interrupt
2308 */
2309 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2310 break;
2311 default:
2312 break;
509ee935
JB		 2313 }
2314 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2315}
2316
bd198058 2317static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2318{
d5bf4f67 2319 u32 new_itr = q_vector->itr;
bd198058 2320 u8 current_itr;
f494e8fa 2321
bd198058
AD		 2322 ixgbe_update_itr(q_vector, &q_vector->tx);
2323 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2324
08c8833b 2325 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2326
2327 switch (current_itr) {
2328 /* counts and packets in update_itr are dependent on these numbers */
2329 case lowest_latency:
d5bf4f67 2330 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2331 break;
2332 case low_latency:
d5bf4f67 2333 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2334 break;
2335 case bulk_latency:
d5bf4f67 2336 new_itr = IXGBE_8K_ITR;
f494e8fa 2337 break;
bd198058
AD		 2338 default:
2339 break;
f494e8fa
AV		 2340 }
2341
d5bf4f67 2342 if (new_itr != q_vector->itr) {
fe49f04a 2343 /* do an exponential smoothing */
d5bf4f67
ET		 2344 new_itr = (10 * new_itr * q_vector->itr) /
2345 ((9 * new_itr) + q_vector->itr);
509ee935 2346
bd198058 2347 /* save the algorithm value here */
5d967eb7 2348 q_vector->itr = new_itr;
fe49f04a
AD		 2349
2350 ixgbe_write_eitr(q_vector);
f494e8fa 2351 }
f494e8fa
AV		 2352}
2353
119fc60a 2354/**
de88eeeb 2355 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2356 * @adapter: pointer to adapter
119fc60a 2357 **/
f0f9778d 2358static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2359{
119fc60a
MC		 2360 struct ixgbe_hw *hw = &adapter->hw;
2361 u32 eicr = adapter->interrupt_event;
2362
f0f9778d 2363 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2364 return;
2365
f0f9778d
AD		 2366 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2367 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2368 return;
2369
2370 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2371
7ca647bd 2372 switch (hw->device_id) {
f0f9778d
AD		 2373 case IXGBE_DEV_ID_82599_T3_LOM:
2374 /*
2375 * Since the warning interrupt is for both ports
2376 * we don't have to check if:
2377 * - This interrupt wasn't for our port.
2378 * - We may have missed the interrupt so always have to
2379 * check if we got a LSC
2380 */
2381 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2382 !(eicr & IXGBE_EICR_LSC))
2383 return;
2384
2385 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2386 u32 speed;
f0f9778d 2387 bool link_up = false;
7ca647bd 2388
3d292265 2389 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2390
f0f9778d
AD		 2391 if (link_up)
2392 return;
2393 }
2394
2395 /* Check if this is not due to overtemp */
2396 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2397 return;
2398
2399 break;
7ca647bd
JP		 2400 default:
2401 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2402 return;
7ca647bd 2403 break;
119fc60a 2404 }
7ca647bd
JP		 2405 e_crit(drv,
2406 "Network adapter has been stopped because it has over heated. "
2407 "Restart the computer. If the problem persists, "
2408 "power off the system and replace the adapter\n");
f0f9778d
AD		 2409
2410 adapter->interrupt_event = 0;
119fc60a
MC		 2411}
2412
0befdb3e
JB		 2413static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2414{
2415 struct ixgbe_hw *hw = &adapter->hw;
2416
2417 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2418 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2419 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2420 /* write to clear the interrupt */
2421 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2422 }
2423}
cf8280ee 2424
4f51bf70
JK		 2425static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2426{
2427 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2428 return;
2429
2430 switch (adapter->hw.mac.type) {
2431 case ixgbe_mac_82599EB:
2432 /*
2433 * Need to check link state so complete overtemp check
2434 * on service task
2435 */
2436 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2437 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2438 adapter->interrupt_event = eicr;
2439 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2440 ixgbe_service_event_schedule(adapter);
2441 return;
2442 }
2443 return;
2444 case ixgbe_mac_X540:
2445 if (!(eicr & IXGBE_EICR_TS))
2446 return;
2447 break;
2448 default:
2449 return;
2450 }
2451
2452 e_crit(drv,
2453 "Network adapter has been stopped because it has over heated. "
2454 "Restart the computer. If the problem persists, "
2455 "power off the system and replace the adapter\n");
2456}
2457
e8e26350
PW		 2458static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2459{
2460 struct ixgbe_hw *hw = &adapter->hw;
2461
73c4b7cd
AD		 2462 if (eicr & IXGBE_EICR_GPI_SDP2) {
2463 /* Clear the interrupt */
2464 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2465 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2466 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2467 ixgbe_service_event_schedule(adapter);
2468 }
73c4b7cd
AD		 2469 }
2470
e8e26350
PW		 2471 if (eicr & IXGBE_EICR_GPI_SDP1) {
2472 /* Clear the interrupt */
2473 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2474 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2475 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2476 ixgbe_service_event_schedule(adapter);
2477 }
e8e26350
PW		 2478 }
2479}
2480
cf8280ee
JB		 2481static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2482{
2483 struct ixgbe_hw *hw = &adapter->hw;
2484
2485 adapter->lsc_int++;
2486 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2487 adapter->link_check_timeout = jiffies;
2488 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2489 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2490 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2491 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2492 }
2493}
2494
fe49f04a
AD		 2495static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2496 u64 qmask)
2497{
2498 u32 mask;
bd508178 2499 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2500
bd508178
AD		 2501 switch (hw->mac.type) {
2502 case ixgbe_mac_82598EB:
fe49f04a 2503 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2504 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2505 break;
2506 case ixgbe_mac_82599EB:
b93a2226 2507 case ixgbe_mac_X540:
fe49f04a 2508 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2509 if (mask)
2510 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2511 mask = (qmask >> 32);
bd508178
AD		 2512 if (mask)
2513 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2514 break;
2515 default:
2516 break;
fe49f04a
AD		 2517 }
2518 /* skip the flush */
2519}
2520
2521static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2522 u64 qmask)
fe49f04a
AD		 2523{
2524 u32 mask;
bd508178 2525 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2526
bd508178
AD		 2527 switch (hw->mac.type) {
2528 case ixgbe_mac_82598EB:
fe49f04a 2529 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2530 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2531 break;
2532 case ixgbe_mac_82599EB:
b93a2226 2533 case ixgbe_mac_X540:
fe49f04a 2534 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2535 if (mask)
2536 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2537 mask = (qmask >> 32);
bd508178
AD		 2538 if (mask)
2539 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2540 break;
2541 default:
2542 break;
fe49f04a
AD		 2543 }
2544 /* skip the flush */
2545}
2546
021230d4 2547/**
2c4af694
AD		 2548 * ixgbe_irq_enable - Enable default interrupt generation settings
2549 * @adapter: board private structure
021230d4 2550 **/
2c4af694
AD		 2551static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2552 bool flush)
9a799d71 2553{
2c4af694 2554 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2555
2c4af694
AD		 2556 /* don't reenable LSC while waiting for link */
2557 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2558 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2559
2c4af694 2560 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2561 switch (adapter->hw.mac.type) {
2562 case ixgbe_mac_82599EB:
2563 mask |= IXGBE_EIMS_GPI_SDP0;
2564 break;
2565 case ixgbe_mac_X540:
2566 mask |= IXGBE_EIMS_TS;
2567 break;
2568 default:
2569 break;
2570 }
2c4af694
AD		 2571 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2572 mask |= IXGBE_EIMS_GPI_SDP1;
2573 switch (adapter->hw.mac.type) {
2574 case ixgbe_mac_82599EB:
2c4af694
AD		 2575 mask |= IXGBE_EIMS_GPI_SDP1;
2576 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2577 case ixgbe_mac_X540:
2578 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2579 mask |= IXGBE_EIMS_MAILBOX;
2580 break;
2581 default:
2582 break;
9a799d71 2583 }
db0677fa 2584
db0677fa
JK		 2585 if (adapter->hw.mac.type == ixgbe_mac_X540)
2586 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2587
2c4af694
AD		 2588 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2589 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2590 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2591
2c4af694
AD		 2592 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2593 if (queues)
2594 ixgbe_irq_enable_queues(adapter, ~0);
2595 if (flush)
2596 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2597}
2598
2c4af694 2599static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2600{
a65151ba 2601 struct ixgbe_adapter *adapter = data;
9a799d71 2602 struct ixgbe_hw *hw = &adapter->hw;
54037505 2603 u32 eicr;
91281fd3 2604
54037505
DS		 2605 /*
2606 * Workaround for Silicon errata. Use clear-by-write instead
2607 * of clear-by-read. Reading with EICS will return the
2608 * interrupt causes without clearing, which later be done
2609 * with the write to EICR.
2610 */
2611 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2612
2613 /* The lower 16bits of the EICR register are for the queue interrupts
2614 * which should be masked here in order to not accidently clear them if
2615 * the bits are high when ixgbe_msix_other is called. There is a race
2616 * condition otherwise which results in possible performance loss
2617 * especially if the ixgbe_msix_other interrupt is triggering
2618 * consistently (as it would when PPS is turned on for the X540 device)
2619 */
2620 eicr &= 0xFFFF0000;
2621
54037505 2622 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2623
cf8280ee
JB		 2624 if (eicr & IXGBE_EICR_LSC)
2625 ixgbe_check_lsc(adapter);
f0848276 2626
1cdd1ec8
GR		 2627 if (eicr & IXGBE_EICR_MAILBOX)
2628 ixgbe_msg_task(adapter);
efe3d3c8 2629
bd508178
AD		 2630 switch (hw->mac.type) {
2631 case ixgbe_mac_82599EB:
b93a2226 2632 case ixgbe_mac_X540:
d773ce2d
DS		 2633 if (eicr & IXGBE_EICR_ECC) {
2634 e_info(link, "Received ECC Err, initiating reset\n");
2635 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2636 ixgbe_service_event_schedule(adapter);
2637 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2638 }
c4cf55e5
PWJ		 2639 /* Handle Flow Director Full threshold interrupt */
2640 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2641 int reinit_count = 0;
c4cf55e5 2642 int i;
c4cf55e5 2643 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2644 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2645 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2646 &ring->state))
2647 reinit_count++;
2648 }
2649 if (reinit_count) {
2650 /* no more flow director interrupts until after init */
2651 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2652 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2653 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2654 }
2655 }
f0f9778d 2656 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2657 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2658 break;
2659 default:
2660 break;
c4cf55e5 2661 }
f0848276 2662
bd508178 2663 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2664
db0677fa
JK		 2665 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2666 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2667
7086400d 2668 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2669 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2670 ixgbe_irq_enable(adapter, false, false);
f0848276 2671
9a799d71 2672 return IRQ_HANDLED;
f0848276 2673}
91281fd3 2674
4ff7fb12 2675static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2676{
021230d4 2677 struct ixgbe_q_vector *q_vector = data;
91281fd3 2678
9b471446 2679 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2680
4ff7fb12
AD		 2681 if (q_vector->rx.ring || q_vector->tx.ring)
2682 napi_schedule(&q_vector->napi);
91281fd3 2683
9a799d71 2684 return IRQ_HANDLED;
91281fd3
AD		 2685}
2686
eb01b975
AD		 2687/**
2688 * ixgbe_poll - NAPI Rx polling callback
2689 * @napi: structure for representing this polling device
2690 * @budget: how many packets driver is allowed to clean
2691 *
2692 * This function is used for legacy and MSI, NAPI mode
2693 **/
8af3c33f 2694int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2695{
2696 struct ixgbe_q_vector *q_vector =
2697 container_of(napi, struct ixgbe_q_vector, napi);
2698 struct ixgbe_adapter *adapter = q_vector->adapter;
2699 struct ixgbe_ring *ring;
2700 int per_ring_budget;
2701 bool clean_complete = true;
2702
2703#ifdef CONFIG_IXGBE_DCA
2704 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2705 ixgbe_update_dca(q_vector);
2706#endif
2707
2708 ixgbe_for_each_ring(ring, q_vector->tx)
2709 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2710
5a85e737
ET		 2711 if (!ixgbe_qv_lock_napi(q_vector))
2712 return budget;
2713
eb01b975
AD		 2714 /* attempt to distribute budget to each queue fairly, but don't allow
2715 * the budget to go below 1 because we'll exit polling */
2716 if (q_vector->rx.count > 1)
2717 per_ring_budget = max(budget/q_vector->rx.count, 1);
2718 else
2719 per_ring_budget = budget;
2720
2721 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2722 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2723 per_ring_budget) < per_ring_budget);
eb01b975 2724
5a85e737 2725 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2726 /* If all work not completed, return budget and keep polling */
2727 if (!clean_complete)
2728 return budget;
2729
2730 /* all work done, exit the polling mode */
2731 napi_complete(napi);
2732 if (adapter->rx_itr_setting & 1)
2733 ixgbe_set_itr(q_vector);
2734 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2735 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2736
2737 return 0;
2738}
2739
021230d4
AV		 2740/**
2741 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2742 * @adapter: board private structure
2743 *
2744 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2745 * interrupts from the kernel.
2746 **/
2747static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2748{
2749 struct net_device *netdev = adapter->netdev;
207867f5 2750 int vector, err;
e8e9f696 2751 int ri = 0, ti = 0;
021230d4 2752
49c7ffbe 2753 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2754 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2755 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2756
4ff7fb12 2757 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2758 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2759 "%s-%s-%d", netdev->name, "TxRx", ri++);
2760 ti++;
2761 } else if (q_vector->rx.ring) {
9fe93afd 2762 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2763 "%s-%s-%d", netdev->name, "rx", ri++);
2764 } else if (q_vector->tx.ring) {
9fe93afd 2765 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2766 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2767 } else {
2768 /* skip this unused q_vector */
2769 continue;
32aa77a4 2770 }
207867f5
AD		 2771 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2772 q_vector->name, q_vector);
9a799d71 2773 if (err) {
396e799c 2774 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2775 "Error: %d\n", err);
021230d4 2776 goto free_queue_irqs;
9a799d71 2777 }
207867f5
AD		 2778 /* If Flow Director is enabled, set interrupt affinity */
2779 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2780 /* assign the mask for this irq */
2781 irq_set_affinity_hint(entry->vector,
de88eeeb 2782 &q_vector->affinity_mask);
207867f5 2783 }
9a799d71
AK		 2784 }
2785
021230d4 2786 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2787 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2788 if (err) {
de88eeeb 2789 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2790 goto free_queue_irqs;
9a799d71
AK		 2791 }
2792
9a799d71
AK		 2793 return 0;
2794
021230d4 2795free_queue_irqs:
207867f5
AD		 2796 while (vector) {
2797 vector--;
2798 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2799 NULL);
2800 free_irq(adapter->msix_entries[vector].vector,
2801 adapter->q_vector[vector]);
2802 }
021230d4
AV		 2803 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2804 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2805 kfree(adapter->msix_entries);
2806 adapter->msix_entries = NULL;
9a799d71
AK		 2807 return err;
2808}
2809
2810/**
021230d4 2811 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2812 * @irq: interrupt number
2813 * @data: pointer to a network interface device structure
9a799d71
AK		 2814 **/
2815static irqreturn_t ixgbe_intr(int irq, void *data)
2816{
a65151ba 2817 struct ixgbe_adapter *adapter = data;
9a799d71 2818 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2819 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2820 u32 eicr;
2821
54037505 2822 /*
24ddd967 2823 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2824 * before the read of EICR.
2825 */
2826 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2827
021230d4 2828 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2829 * therefore no explicit interrupt disable is necessary */
021230d4 2830 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2831 if (!eicr) {
6af3b9eb
ET		 2832 /*
2833 * shared interrupt alert!
f47cf66e 2834 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2835 * have disabled interrupts due to EIAM
2836 * finish the workaround of silicon errata on 82598. Unmask
2837 * the interrupt that we masked before the EICR read.
2838 */
2839 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2840 ixgbe_irq_enable(adapter, true, true);
9a799d71 2841 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2842 }
9a799d71 2843
cf8280ee
JB		 2844 if (eicr & IXGBE_EICR_LSC)
2845 ixgbe_check_lsc(adapter);
021230d4 2846
bd508178
AD		 2847 switch (hw->mac.type) {
2848 case ixgbe_mac_82599EB:
e8e26350 2849 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2850 /* Fall through */
2851 case ixgbe_mac_X540:
d773ce2d
DS		 2852 if (eicr & IXGBE_EICR_ECC) {
2853 e_info(link, "Received ECC Err, initiating reset\n");
2854 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2855 ixgbe_service_event_schedule(adapter);
2856 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2857 }
4f51bf70 2858 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2859 break;
2860 default:
2861 break;
2862 }
e8e26350 2863
0befdb3e 2864 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2865 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2866 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2867
b9f6ed2b
AD		 2868 /* would disable interrupts here but EIAM disabled it */
2869 napi_schedule(&q_vector->napi);
9a799d71 2870
6af3b9eb
ET		 2871 /*
2872 * re-enable link(maybe) and non-queue interrupts, no flush.
2873 * ixgbe_poll will re-enable the queue interrupts
2874 */
6af3b9eb
ET		 2875 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2876 ixgbe_irq_enable(adapter, false, false);
2877
9a799d71
AK		 2878 return IRQ_HANDLED;
2879}
2880
2881/**
2882 * ixgbe_request_irq - initialize interrupts
2883 * @adapter: board private structure
2884 *
2885 * Attempts to configure interrupts using the best available
2886 * capabilities of the hardware and kernel.
2887 **/
021230d4 2888static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2889{
2890 struct net_device *netdev = adapter->netdev;
021230d4 2891 int err;
9a799d71 2892
4cc6df29 2893 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2894 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2895 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2896 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2897 netdev->name, adapter);
4cc6df29 2898 else
a0607fd3 2899 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2900 netdev->name, adapter);
9a799d71 2901
de88eeeb 2902 if (err)
396e799c 2903 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2904
9a799d71
AK		 2905 return err;
2906}
2907
2908static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2909{
49c7ffbe 2910 int vector;
9a799d71 2911
49c7ffbe
AD		 2912 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2913 free_irq(adapter->pdev->irq, adapter);
2914 return;
2915 }
4cc6df29 2916
49c7ffbe
AD		 2917 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2918 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2919 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2920
49c7ffbe
AD		 2921 /* free only the irqs that were actually requested */
2922 if (!q_vector->rx.ring && !q_vector->tx.ring)
2923 continue;
207867f5 2924
49c7ffbe
AD		 2925 /* clear the affinity_mask in the IRQ descriptor */
2926 irq_set_affinity_hint(entry->vector, NULL);
2927
2928 free_irq(entry->vector, q_vector);
9a799d71 2929 }
49c7ffbe
AD		 2930
2931 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2932}
2933
22d5a71b
JB		 2934/**
2935 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2936 * @adapter: board private structure
2937 **/
2938static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2939{
bd508178
AD		 2940 switch (adapter->hw.mac.type) {
2941 case ixgbe_mac_82598EB:
835462fc 2942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2943 break;
2944 case ixgbe_mac_82599EB:
b93a2226 2945 case ixgbe_mac_X540:
835462fc
NS		 2946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2948 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2949 break;
2950 default:
2951 break;
22d5a71b
JB		 2952 }
2953 IXGBE_WRITE_FLUSH(&adapter->hw);
2954 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2955 int vector;
2956
2957 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2958 synchronize_irq(adapter->msix_entries[vector].vector);
2959
2960 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2961 } else {
2962 synchronize_irq(adapter->pdev->irq);
2963 }
2964}
2965
9a799d71
AK		 2966/**
2967 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2968 *
2969 **/
2970static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2971{
d5bf4f67 2972 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2973
d5bf4f67 2974 ixgbe_write_eitr(q_vector);
9a799d71 2975
e8e26350
PW		 2976 ixgbe_set_ivar(adapter, 0, 0, 0);
2977 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2978
396e799c 2979 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2980}
2981
43e69bf0
AD		 2982/**
2983 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2984 * @adapter: board private structure
2985 * @ring: structure containing ring specific data
2986 *
2987 * Configure the Tx descriptor ring after a reset.
2988 **/
84418e3b
AD		 2989void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2990 struct ixgbe_ring *ring)
43e69bf0
AD		 2991{
2992 struct ixgbe_hw *hw = &adapter->hw;
2993 u64 tdba = ring->dma;
2f1860b8 2994 int wait_loop = 10;
b88c6de2 2995 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2996 u8 reg_idx = ring->reg_idx;
43e69bf0 2997
2f1860b8 2998 /* disable queue to avoid issues while updating state */
b88c6de2 2999 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3000 IXGBE_WRITE_FLUSH(hw);
3001
43e69bf0 3002 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3003 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3004 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3005 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3006 ring->count * sizeof(union ixgbe_adv_tx_desc));
3007 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3008 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3009 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3010
b88c6de2
AD		 3011 /*
3012 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3013 * higher than 1 when:
3014 * - ITR is 0 as it could cause false TX hangs
3015 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3016 *
3017 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3018 * to or less than the number of on chip descriptors, which is
3019 * currently 40.
3020 */
67da097e
ET		 3021#if IS_ENABLED(CONFIG_BQL)
3022 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3023#else
e954b374 3024 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3025#endif
b88c6de2
AD		 3026 txdctl |= (1 << 16); /* WTHRESH = 1 */
3027 else
3028 txdctl |= (8 << 16); /* WTHRESH = 8 */
3029
e954b374
AD		 3030 /*
3031 * Setting PTHRESH to 32 both improves performance
3032 * and avoids a TX hang with DFP enabled
3033 */
b88c6de2
AD		 3034 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3035 32; /* PTHRESH = 32 */
2f1860b8
AD		 3036
3037 /* reinitialize flowdirector state */
39cb681b 3038 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3039 ring->atr_sample_rate = adapter->atr_sample_rate;
3040 ring->atr_count = 0;
3041 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3042 } else {
3043 ring->atr_sample_rate = 0;
3044 }
2f1860b8 3045
fd786b7b
AD		 3046 /* initialize XPS */
3047 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3048 struct ixgbe_q_vector *q_vector = ring->q_vector;
3049
3050 if (q_vector)
2a47fa45 3051 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3052 &q_vector->affinity_mask,
3053 ring->queue_index);
3054 }
3055
c84d324c
JF		 3056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3057
2f1860b8 3058 /* enable queue */
2f1860b8
AD		 3059 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3060
3061 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3062 if (hw->mac.type == ixgbe_mac_82598EB &&
3063 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3064 return;
3065
3066 /* poll to verify queue is enabled */
3067 do {
032b4325 3068 usleep_range(1000, 2000);
2f1860b8
AD		 3069 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3070 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3071 if (!wait_loop)
3072 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3073}
3074
120ff942
AD		 3075static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3076{
3077 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3078 u32 rttdcs, mtqc;
8b1c0b24 3079 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3080
3081 if (hw->mac.type == ixgbe_mac_82598EB)
3082 return;
3083
3084 /* disable the arbiter while setting MTQC */
3085 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3086 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3087 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3088
3089 /* set transmit pool layout */
671c0adb
AD		 3090 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3091 mtqc = IXGBE_MTQC_VT_ENA;
3092 if (tcs > 4)
3093 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3094 else if (tcs > 1)
3095 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3096 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3097 mtqc |= IXGBE_MTQC_32VF;
3098 else
3099 mtqc |= IXGBE_MTQC_64VF;
3100 } else {
3101 if (tcs > 4)
3102 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3103 else if (tcs > 1)
3104 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3105 else
671c0adb
AD		 3106 mtqc = IXGBE_MTQC_64Q_1PB;
3107 }
120ff942 3108
671c0adb 3109 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3110
671c0adb
AD		 3111 /* Enable Security TX Buffer IFG for multiple pb */
3112 if (tcs) {
3113 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3114 sectx |= IXGBE_SECTX_DCB;
3115 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3116 }
3117
3118 /* re-enable the arbiter */
3119 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3120 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3121}
3122
9a799d71 3123/**
3a581073 3124 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3125 * @adapter: board private structure
3126 *
3127 * Configure the Tx unit of the MAC after a reset.
3128 **/
3129static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3130{
2f1860b8
AD		 3131 struct ixgbe_hw *hw = &adapter->hw;
3132 u32 dmatxctl;
43e69bf0 3133 u32 i;
9a799d71 3134
2f1860b8
AD		 3135 ixgbe_setup_mtqc(adapter);
3136
3137 if (hw->mac.type != ixgbe_mac_82598EB) {
3138 /* DMATXCTL.EN must be before Tx queues are enabled */
3139 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3140 dmatxctl |= IXGBE_DMATXCTL_TE;
3141 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3142 }
3143
9a799d71 3144 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3145 for (i = 0; i < adapter->num_tx_queues; i++)
3146 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3147}
3148
3ebe8fde
AD		 3149static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3150 struct ixgbe_ring *ring)
3151{
3152 struct ixgbe_hw *hw = &adapter->hw;
3153 u8 reg_idx = ring->reg_idx;
3154 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3155
3156 srrctl |= IXGBE_SRRCTL_DROP_EN;
3157
3158 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3159}
3160
3161static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3162 struct ixgbe_ring *ring)
3163{
3164 struct ixgbe_hw *hw = &adapter->hw;
3165 u8 reg_idx = ring->reg_idx;
3166 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3167
3168 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3169
3170 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3171}
3172
3173#ifdef CONFIG_IXGBE_DCB
3174void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3175#else
3176static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3177#endif
3178{
3179 int i;
3180 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3181
3182 if (adapter->ixgbe_ieee_pfc)
3183 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3184
3185 /*
3186 * We should set the drop enable bit if:
3187 * SR-IOV is enabled
3188 * or
3189 * Number of Rx queues > 1 and flow control is disabled
3190 *
3191 * This allows us to avoid head of line blocking for security
3192 * and performance reasons.
3193 */
3194 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3195 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3196 for (i = 0; i < adapter->num_rx_queues; i++)
3197 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3198 } else {
3199 for (i = 0; i < adapter->num_rx_queues; i++)
3200 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3201 }
3202}
3203
e8e26350 3204#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3205
a6616b42 3206static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3207 struct ixgbe_ring *rx_ring)
cc41ac7c 3208{
45e9baa5 3209 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3210 u32 srrctl;
bf29ee6c 3211 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3212
45e9baa5
AD		 3213 if (hw->mac.type == ixgbe_mac_82598EB) {
3214 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3215
45e9baa5
AD		 3216 /*
3217 * if VMDq is not active we must program one srrctl register
3218 * per RSS queue since we have enabled RDRXCTL.MVMEN
3219 */
3220 reg_idx &= mask;
3221 }
cc41ac7c 3222
45e9baa5
AD		 3223 /* configure header buffer length, needed for RSC */
3224 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3225
45e9baa5 3226 /* configure the packet buffer length */
f800326d 3227 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3228
3229 /* configure descriptor type */
f800326d 3230 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3231
45e9baa5 3232 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3233}
9a799d71 3234
05abb126 3235static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3236{
05abb126
AD		 3237 struct ixgbe_hw *hw = &adapter->hw;
3238 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3239 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3240 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3241 u32 mrqc = 0, reta = 0;
3242 u32 rxcsum;
3243 int i, j;
671c0adb
AD		 3244 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3245
671c0adb
AD		 3246 /*
3247 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3248 * make full use of any rings they may have. We will use the
3249 * PSRTYPE register to control how many rings we use within the PF.
3250 */
3251 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3252 rss_i = 2;
0cefafad 3253
05abb126
AD		 3254 /* Fill out hash function seeds */
3255 for (i = 0; i < 10; i++)
3256 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3257
3258 /* Fill out redirection table */
3259 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3260 if (j == rss_i)
05abb126
AD		 3261 j = 0;
3262 /* reta = 4-byte sliding window of
3263 * 0x00..(indices-1)(indices-1)00..etc. */
3264 reta = (reta << 8) | (j * 0x11);
3265 if ((i & 3) == 3)
3266 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3267 }
0cefafad 3268
05abb126
AD		 3269 /* Disable indicating checksum in descriptor, enables RSS hash */
3270 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3271 rxcsum |= IXGBE_RXCSUM_PCSD;
3272 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3273
671c0adb 3274 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3275 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3276 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3277 } else {
671c0adb
AD		 3278 u8 tcs = netdev_get_num_tc(adapter->netdev);
3279
3280 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3281 if (tcs > 4)
3282 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3283 else if (tcs > 1)
3284 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3285 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3286 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3287 else
671c0adb
AD		 3288 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3289 } else {
3290 if (tcs > 4)
8b1c0b24 3291 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3292 else if (tcs > 1)
3293 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3294 else
3295 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3296 }
0cefafad
JB		 3297 }
3298
05abb126 3299 /* Perform hash on these packet types */
671c0adb
AD		 3300 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3301 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3302 IXGBE_MRQC_RSS_FIELD_IPV6 |
3303 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3304
ef6afc0c
AD		 3305 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3306 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3307 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3308 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3309
05abb126 3310 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3311}
3312
bb5a9ad2
NS		 3313/**
3314 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3315 * @adapter: address of board private structure
3316 * @index: index of ring to set
bb5a9ad2 3317 **/
082757af 3318static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3319 struct ixgbe_ring *ring)
bb5a9ad2 3320{
bb5a9ad2 3321 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3322 u32 rscctrl;
bf29ee6c 3323 u8 reg_idx = ring->reg_idx;
7367096a 3324
7d637bcc 3325 if (!ring_is_rsc_enabled(ring))
7367096a 3326 return;
bb5a9ad2 3327
7367096a 3328 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3329 rscctrl |= IXGBE_RSCCTL_RSCEN;
3330 /*
3331 * we must limit the number of descriptors so that the
3332 * total size of max desc * buf_len is not greater
642c680e 3333 * than 65536
bb5a9ad2 3334 */
f800326d 3335 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3336 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3337}
3338
9e10e045
AD		 3339#define IXGBE_MAX_RX_DESC_POLL 10
3340static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3341 struct ixgbe_ring *ring)
3342{
3343 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3344 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3345 u32 rxdctl;
bf29ee6c 3346 u8 reg_idx = ring->reg_idx;
9e10e045 3347
b0483c8f
MR		 3348 if (ixgbe_removed(hw->hw_addr))
3349 return;
9e10e045
AD		 3350 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3351 if (hw->mac.type == ixgbe_mac_82598EB &&
3352 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3353 return;
3354
3355 do {
032b4325 3356 usleep_range(1000, 2000);
9e10e045
AD		 3357 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3358 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3359
3360 if (!wait_loop) {
3361 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3362 "the polling period\n", reg_idx);
3363 }
3364}
3365
2d39d576
YZ		 3366void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3367 struct ixgbe_ring *ring)
3368{
3369 struct ixgbe_hw *hw = &adapter->hw;
3370 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3371 u32 rxdctl;
3372 u8 reg_idx = ring->reg_idx;
3373
b0483c8f
MR		 3374 if (ixgbe_removed(hw->hw_addr))
3375 return;
2d39d576
YZ		 3376 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3377 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3378
3379 /* write value back with RXDCTL.ENABLE bit cleared */
3380 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3381
3382 if (hw->mac.type == ixgbe_mac_82598EB &&
3383 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3384 return;
3385
3386 /* the hardware may take up to 100us to really disable the rx queue */
3387 do {
3388 udelay(10);
3389 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3390 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3391
3392 if (!wait_loop) {
3393 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3394 "the polling period\n", reg_idx);
3395 }
3396}
3397
84418e3b
AD		 3398void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3399 struct ixgbe_ring *ring)
acd37177
AD		 3400{
3401 struct ixgbe_hw *hw = &adapter->hw;
3402 u64 rdba = ring->dma;
9e10e045 3403 u32 rxdctl;
bf29ee6c 3404 u8 reg_idx = ring->reg_idx;
acd37177 3405
9e10e045
AD		 3406 /* disable queue to avoid issues while updating state */
3407 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3408 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3409
acd37177
AD		 3410 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3411 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3412 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3413 ring->count * sizeof(union ixgbe_adv_rx_desc));
3414 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3415 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3416 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3417
3418 ixgbe_configure_srrctl(adapter, ring);
3419 ixgbe_configure_rscctl(adapter, ring);
3420
3421 if (hw->mac.type == ixgbe_mac_82598EB) {
3422 /*
3423 * enable cache line friendly hardware writes:
3424 * PTHRESH=32 descriptors (half the internal cache),
3425 * this also removes ugly rx_no_buffer_count increment
3426 * HTHRESH=4 descriptors (to minimize latency on fetch)
3427 * WTHRESH=8 burst writeback up to two cache lines
3428 */
3429 rxdctl &= ~0x3FFFFF;
3430 rxdctl |= 0x080420;
3431 }
3432
3433 /* enable receive descriptor ring */
3434 rxdctl |= IXGBE_RXDCTL_ENABLE;
3435 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3436
3437 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3438 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3439}
3440
48654521
AD		 3441static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3442{
3443 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3444 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3445 u16 pool;
48654521
AD		 3446
3447 /* PSRTYPE must be initialized in non 82598 adapters */
3448 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3449 IXGBE_PSRTYPE_UDPHDR |
3450 IXGBE_PSRTYPE_IPV4HDR |
48654521 3451 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3452 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3453
3454 if (hw->mac.type == ixgbe_mac_82598EB)
3455 return;
3456
fbe7ca7f
AD		 3457 if (rss_i > 3)
3458 psrtype |= 2 << 29;
3459 else if (rss_i > 1)
3460 psrtype |= 1 << 29;
48654521 3461
2a47fa45
JF		 3462 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3463 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3464}
3465
f5b4a52e
AD		 3466static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3467{
3468 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3469 u32 reg_offset, vf_shift;
435b19f6 3470 u32 gcr_ext, vmdctl;
de4c7f65 3471 int i;
f5b4a52e
AD		 3472
3473 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3474 return;
3475
3476 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3477 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3478 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3479 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3480 vmdctl |= IXGBE_VT_CTL_REPLEN;
3481 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3482
1d9c0bfd
AD		 3483 vf_shift = VMDQ_P(0) % 32;
3484 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3485
3486 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3487 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3488 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3489 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3490 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3491 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3492 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3493
3494 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3495 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3496
3497 /*
3498 * Set up VF register offsets for selected VT Mode,
3499 * i.e. 32 or 64 VFs for SR-IOV
3500 */
73079ea0
AD		 3501 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3502 case IXGBE_82599_VMDQ_8Q_MASK:
3503 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3504 break;
3505 case IXGBE_82599_VMDQ_4Q_MASK:
3506 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3507 break;
3508 default:
3509 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3510 break;
3511 }
3512
f5b4a52e
AD		 3513 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3514
435b19f6 3515
a985b6c3 3516 /* Enable MAC Anti-Spoofing */
435b19f6 3517 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3518 adapter->num_vfs);
de4c7f65
GR		 3519 /* For VFs that have spoof checking turned off */
3520 for (i = 0; i < adapter->num_vfs; i++) {
3521 if (!adapter->vfinfo[i].spoofchk_enabled)
3522 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3523 }
f5b4a52e
AD		 3524}
3525
477de6ed 3526static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3527{
9a799d71
AK		 3528 struct ixgbe_hw *hw = &adapter->hw;
3529 struct net_device *netdev = adapter->netdev;
3530 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3531 struct ixgbe_ring *rx_ring;
3532 int i;
3533 u32 mhadd, hlreg0;
48654521 3534
63f39bd1 3535#ifdef IXGBE_FCOE
477de6ed
AD		 3536 /* adjust max frame to be able to do baby jumbo for FCoE */
3537 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3538 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3539 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3540
477de6ed 3541#endif /* IXGBE_FCOE */
872844dd
AD		 3542
3543 /* adjust max frame to be at least the size of a standard frame */
3544 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3545 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3546
477de6ed
AD		 3547 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3548 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3549 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3550 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3551
3552 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3553 }
3554
3555 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3556 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3557 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3558 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3559
0cefafad
JB		 3560 /*
3561 * Setup the HW Rx Head and Tail Descriptor Pointers and
3562 * the Base and Length of the Rx Descriptor Ring
3563 */
9a799d71 3564 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3565 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3566 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3567 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3568 else
7d637bcc 3569 clear_ring_rsc_enabled(rx_ring);
477de6ed 3570 }
477de6ed
AD		 3571}
3572
7367096a
AD		 3573static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3574{
3575 struct ixgbe_hw *hw = &adapter->hw;
3576 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3577
3578 switch (hw->mac.type) {
3579 case ixgbe_mac_82598EB:
3580 /*
3581 * For VMDq support of different descriptor types or
3582 * buffer sizes through the use of multiple SRRCTL
3583 * registers, RDRXCTL.MVMEN must be set to 1
3584 *
3585 * also, the manual doesn't mention it clearly but DCA hints
3586 * will only use queue 0's tags unless this bit is set. Side
3587 * effects of setting this bit are only that SRRCTL must be
3588 * fully programmed [0..15]
3589 */
3590 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3591 break;
3592 case ixgbe_mac_82599EB:
b93a2226 3593 case ixgbe_mac_X540:
7367096a
AD		 3594 /* Disable RSC for ACK packets */
3595 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3596 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3597 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3598 /* hardware requires some bits to be set by default */
3599 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3600 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3601 break;
3602 default:
3603 /* We should do nothing since we don't know this hardware */
3604 return;
3605 }
3606
3607 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3608}
3609
477de6ed
AD		 3610/**
3611 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3612 * @adapter: board private structure
3613 *
3614 * Configure the Rx unit of the MAC after a reset.
3615 **/
3616static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3617{
3618 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3619 int i;
6dcc28b9 3620 u32 rxctrl, rfctl;
477de6ed
AD		 3621
3622 /* disable receives while setting up the descriptors */
3623 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3624 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3625
3626 ixgbe_setup_psrtype(adapter);
7367096a 3627 ixgbe_setup_rdrxctl(adapter);
477de6ed 3628
6dcc28b9
JK		 3629 /* RSC Setup */
3630 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3631 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3632 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3633 rfctl |= IXGBE_RFCTL_RSC_DIS;
3634 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3635
9e10e045 3636 /* Program registers for the distribution of queues */
f5b4a52e 3637 ixgbe_setup_mrqc(adapter);
f5b4a52e 3638
477de6ed
AD		 3639 /* set_rx_buffer_len must be called before ring initialization */
3640 ixgbe_set_rx_buffer_len(adapter);
3641
3642 /*
3643 * Setup the HW Rx Head and Tail Descriptor Pointers and
3644 * the Base and Length of the Rx Descriptor Ring
3645 */
9e10e045
AD		 3646 for (i = 0; i < adapter->num_rx_queues; i++)
3647 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3648
9e10e045
AD		 3649 /* disable drop enable for 82598 parts */
3650 if (hw->mac.type == ixgbe_mac_82598EB)
3651 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3652
3653 /* enable all receives */
3654 rxctrl |= IXGBE_RXCTRL_RXEN;
3655 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3656}
3657
80d5c368
PM		 3658static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3659 __be16 proto, u16 vid)
068c89b0
DS		 3660{
3661 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3662 struct ixgbe_hw *hw = &adapter->hw;
3663
3664 /* add VID to filter table */
1d9c0bfd 3665 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3666 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3667
3668 return 0;
068c89b0
DS		 3669}
3670
80d5c368
PM		 3671static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3672 __be16 proto, u16 vid)
068c89b0
DS		 3673{
3674 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3675 struct ixgbe_hw *hw = &adapter->hw;
3676
068c89b0 3677 /* remove VID from filter table */
1d9c0bfd 3678 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3679 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3680
3681 return 0;
068c89b0
DS		 3682}
3683
5f6c0181
JB		 3684/**
3685 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3686 * @adapter: driver data
3687 */
3688static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3689{
3690 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3691 u32 vlnctrl;
3692
3693 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3694 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3695 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3696}
3697
3698/**
3699 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3700 * @adapter: driver data
3701 */
3702static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3703{
3704 struct ixgbe_hw *hw = &adapter->hw;
3705 u32 vlnctrl;
3706
3707 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3708 vlnctrl |= IXGBE_VLNCTRL_VFE;
3709 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3710 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3711}
3712
3713/**
3714 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3715 * @adapter: driver data
3716 */
3717static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3718{
3719 struct ixgbe_hw *hw = &adapter->hw;
3720 u32 vlnctrl;
5f6c0181
JB		 3721 int i, j;
3722
3723 switch (hw->mac.type) {
3724 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3725 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3726 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3727 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3728 break;
3729 case ixgbe_mac_82599EB:
b93a2226 3730 case ixgbe_mac_X540:
5f6c0181 3731 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3732 struct ixgbe_ring *ring = adapter->rx_ring[i];
3733
3734 if (ring->l2_accel_priv)
3735 continue;
3736 j = ring->reg_idx;
5f6c0181
JB		 3737 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3738 vlnctrl &= ~IXGBE_RXDCTL_VME;
3739 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3740 }
3741 break;
3742 default:
3743 break;
3744 }
3745}
3746
3747/**
f62bbb5e 3748 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3749 * @adapter: driver data
3750 */
f62bbb5e 3751static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3752{
3753 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3754 u32 vlnctrl;
5f6c0181
JB		 3755 int i, j;
3756
3757 switch (hw->mac.type) {
3758 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3759 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3760 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3761 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3762 break;
3763 case ixgbe_mac_82599EB:
b93a2226 3764 case ixgbe_mac_X540:
5f6c0181 3765 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3766 struct ixgbe_ring *ring = adapter->rx_ring[i];
3767
3768 if (ring->l2_accel_priv)
3769 continue;
3770 j = ring->reg_idx;
5f6c0181
JB		 3771 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3772 vlnctrl |= IXGBE_RXDCTL_VME;
3773 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3774 }
3775 break;
3776 default:
3777 break;
3778 }
3779}
3780
9a799d71
AK		 3781static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3782{
f62bbb5e 3783 u16 vid;
9a799d71 3784
80d5c368 3785 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3786
3787 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3788 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3789}
3790
2850062a
AD		 3791/**
3792 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3793 * @netdev: network interface device structure
3794 *
3795 * Writes unicast address list to the RAR table.
3796 * Returns: -ENOMEM on failure/insufficient address space
3797 * 0 on no addresses written
3798 * X on writing X addresses to the RAR table
3799 **/
3800static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3801{
3802 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3803 struct ixgbe_hw *hw = &adapter->hw;
95447461 3804 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3805 int count = 0;
3806
2a47fa45 3807 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
95447461
JF		 3808 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3809 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3810
2850062a
AD		 3811 /* return ENOMEM indicating insufficient memory for addresses */
3812 if (netdev_uc_count(netdev) > rar_entries)
3813 return -ENOMEM;
3814
95447461 3815 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3816 struct netdev_hw_addr *ha;
3817 /* return error if we do not support writing to RAR table */
3818 if (!hw->mac.ops.set_rar)
3819 return -ENOMEM;
3820
3821 netdev_for_each_uc_addr(ha, netdev) {
3822 if (!rar_entries)
3823 break;
3824 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3825 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3826 count++;
3827 }
3828 }
3829 /* write the addresses in reverse order to avoid write combining */
3830 for (; rar_entries > 0 ; rar_entries--)
3831 hw->mac.ops.clear_rar(hw, rar_entries);
3832
3833 return count;
3834}
3835
9a799d71 3836/**
2c5645cf 3837 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3838 * @netdev: network interface device structure
3839 *
2c5645cf
CL		 3840 * The set_rx_method entry point is called whenever the unicast/multicast
3841 * address list or the network interface flags are updated. This routine is
3842 * responsible for configuring the hardware for proper unicast, multicast and
3843 * promiscuous mode.
9a799d71 3844 **/
7f870475 3845void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3846{
3847 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3848 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3849 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3850 int count;
9a799d71
AK		 3851
3852 /* Check for Promiscuous and All Multicast modes */
3853
3854 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3855
f5dc442b 3856 /* set all bits that we expect to always be set */
3f2d1c0f 3857 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3858 fctrl |= IXGBE_FCTRL_BAM;
3859 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3860 fctrl |= IXGBE_FCTRL_PMCF;
3861
2850062a
AD		 3862 /* clear the bits we are changing the status of */
3863 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3864
9a799d71 3865 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3866 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3867 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3868 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3869 /* Only disable hardware filter vlans in promiscuous mode
3870 * if SR-IOV and VMDQ are disabled - otherwise ensure
3871 * that hardware VLAN filters remain enabled.
3872 */
3873 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3874 IXGBE_FLAG_SRIOV_ENABLED)))
3875 ixgbe_vlan_filter_disable(adapter);
3876 else
3877 ixgbe_vlan_filter_enable(adapter);
9a799d71 3878 } else {
746b9f02
PM		 3879 if (netdev->flags & IFF_ALLMULTI) {
3880 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3881 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3882 }
5f6c0181 3883 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3884 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3885 }
3886
3887 /*
3888 * Write addresses to available RAR registers, if there is not
3889 * sufficient space to store all the addresses then enable
3890 * unicast promiscuous mode
3891 */
3892 count = ixgbe_write_uc_addr_list(netdev);
3893 if (count < 0) {
3894 fctrl |= IXGBE_FCTRL_UPE;
3895 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3896 }
3897
cf78959c
ET		 3898 /* Write addresses to the MTA, if the attempt fails
3899 * then we should just turn on promiscuous mode so
3900 * that we can at least receive multicast traffic
3901 */
3902 hw->mac.ops.update_mc_addr_list(hw, netdev);
3903 vmolr |= IXGBE_VMOLR_ROMPE;
3904
1d9c0bfd 3905 if (adapter->num_vfs)
1cdd1ec8 3906 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3907
3908 if (hw->mac.type != ixgbe_mac_82598EB) {
3909 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3910 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3911 IXGBE_VMOLR_ROPE);
1d9c0bfd 3912 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3913 }
3914
3f2d1c0f
BG		 3915 /* This is useful for sniffing bad packets. */
3916 if (adapter->netdev->features & NETIF_F_RXALL) {
3917 /* UPE and MPE will be handled by normal PROMISC logic
3918 * in e1000e_set_rx_mode */
3919 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3920 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3921 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3922
3923 fctrl &= ~(IXGBE_FCTRL_DPF);
3924 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3925 }
3926
2850062a 3927 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3928
f646968f 3929 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3930 ixgbe_vlan_strip_enable(adapter);
3931 else
3932 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3933}
3934
021230d4
AV		 3935static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3936{
3937 int q_idx;
021230d4 3938
5a85e737
ET		 3939 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3940 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 3941 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 3942 }
021230d4
AV		 3943}
3944
3945static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3946{
3947 int q_idx;
021230d4 3948
5a85e737 3949 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 3950 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 3951 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 3952 pr_info("QV %d locked\n", q_idx);
27d9ce4f 3953 usleep_range(1000, 20000);
5a85e737
ET		 3954 }
3955 }
021230d4
AV		 3956}
3957
7a6b6f51 3958#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3959/**
2f90b865
AD		 3960 * ixgbe_configure_dcb - Configure DCB hardware
3961 * @adapter: ixgbe adapter struct
3962 *
3963 * This is called by the driver on open to configure the DCB hardware.
3964 * This is also called by the gennetlink interface when reconfiguring
3965 * the DCB state.
3966 */
3967static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3968{
3969 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3970 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3971
67ebd791
AD		 3972 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3973 if (hw->mac.type == ixgbe_mac_82598EB)
3974 netif_set_gso_max_size(adapter->netdev, 65536);
3975 return;
3976 }
3977
3978 if (hw->mac.type == ixgbe_mac_82598EB)
3979 netif_set_gso_max_size(adapter->netdev, 32768);
3980
971060b1 3981#ifdef IXGBE_FCOE
b120818e
JF		 3982 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3983 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3984#endif
b120818e
JF		 3985
3986 /* reconfigure the hardware */
3987 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3988 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3989 DCB_TX_CONFIG);
3990 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3991 DCB_RX_CONFIG);
3992 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3993 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3994 ixgbe_dcb_hw_ets(&adapter->hw,
3995 adapter->ixgbe_ieee_ets,
3996 max_frame);
3997 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3998 adapter->ixgbe_ieee_pfc->pfc_en,
3999 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4000 }
8187cd48
JF		 4001
4002 /* Enable RSS Hash per TC */
4003 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4004 u32 msb = 0;
4005 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4006
d411a936
AD		 4007 while (rss_i) {
4008 msb++;
4009 rss_i >>= 1;
4010 }
8187cd48 4011
4ae63730
AD		 4012 /* write msb to all 8 TCs in one write */
4013 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4014 }
2f90b865 4015}
9da712d2
JF		 4016#endif
4017
4018/* Additional bittime to account for IXGBE framing */
4019#define IXGBE_ETH_FRAMING 20
4020
49ce9c2c 4021/**
9da712d2
JF		 4022 * ixgbe_hpbthresh - calculate high water mark for flow control
4023 *
4024 * @adapter: board private structure to calculate for
49ce9c2c 4025 * @pb: packet buffer to calculate
9da712d2
JF		 4026 */
4027static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4028{
4029 struct ixgbe_hw *hw = &adapter->hw;
4030 struct net_device *dev = adapter->netdev;
4031 int link, tc, kb, marker;
4032 u32 dv_id, rx_pba;
4033
4034 /* Calculate max LAN frame size */
4035 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4036
4037#ifdef IXGBE_FCOE
4038 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4039 if ((dev->features & NETIF_F_FCOE_MTU) &&
4040 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4041 (pb == ixgbe_fcoe_get_tc(adapter)))
4042 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 4043
4044#endif
9da712d2
JF		 4045 /* Calculate delay value for device */
4046 switch (hw->mac.type) {
4047 case ixgbe_mac_X540:
4048 dv_id = IXGBE_DV_X540(link, tc);
4049 break;
4050 default:
4051 dv_id = IXGBE_DV(link, tc);
4052 break;
4053 }
4054
4055 /* Loopback switch introduces additional latency */
4056 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4057 dv_id += IXGBE_B2BT(tc);
4058
4059 /* Delay value is calculated in bit times convert to KB */
4060 kb = IXGBE_BT2KB(dv_id);
4061 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4062
4063 marker = rx_pba - kb;
4064
4065 /* It is possible that the packet buffer is not large enough
4066 * to provide required headroom. In this case throw an error
4067 * to user and a do the best we can.
4068 */
4069 if (marker < 0) {
4070 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4071 "headroom to support flow control."
4072 "Decrease MTU or number of traffic classes\n", pb);
4073 marker = tc + 1;
4074 }
4075
4076 return marker;
4077}
4078
49ce9c2c 4079/**
9da712d2
JF		 4080 * ixgbe_lpbthresh - calculate low water mark for for flow control
4081 *
4082 * @adapter: board private structure to calculate for
49ce9c2c 4083 * @pb: packet buffer to calculate
9da712d2
JF		 4084 */
4085static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4086{
4087 struct ixgbe_hw *hw = &adapter->hw;
4088 struct net_device *dev = adapter->netdev;
4089 int tc;
4090 u32 dv_id;
4091
4092 /* Calculate max LAN frame size */
4093 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4094
4095 /* Calculate delay value for device */
4096 switch (hw->mac.type) {
4097 case ixgbe_mac_X540:
4098 dv_id = IXGBE_LOW_DV_X540(tc);
4099 break;
4100 default:
4101 dv_id = IXGBE_LOW_DV(tc);
4102 break;
4103 }
4104
4105 /* Delay value is calculated in bit times convert to KB */
4106 return IXGBE_BT2KB(dv_id);
4107}
4108
4109/*
4110 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4111 */
4112static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4113{
4114 struct ixgbe_hw *hw = &adapter->hw;
4115 int num_tc = netdev_get_num_tc(adapter->netdev);
4116 int i;
4117
4118 if (!num_tc)
4119 num_tc = 1;
4120
4121 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4122
4123 for (i = 0; i < num_tc; i++) {
4124 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4125
4126 /* Low water marks must not be larger than high water marks */
4127 if (hw->fc.low_water > hw->fc.high_water[i])
4128 hw->fc.low_water = 0;
4129 }
4130}
4131
80605c65
JF		 4132static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4133{
80605c65 4134 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4135 int hdrm;
4136 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4137
4138 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4139 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4140 hdrm = 32 << adapter->fdir_pballoc;
4141 else
4142 hdrm = 0;
80605c65 4143
f7e1027f 4144 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4145 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4146}
4147
e4911d57
AD		 4148static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4149{
4150 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4151 struct hlist_node *node2;
e4911d57
AD		 4152 struct ixgbe_fdir_filter *filter;
4153
4154 spin_lock(&adapter->fdir_perfect_lock);
4155
4156 if (!hlist_empty(&adapter->fdir_filter_list))
4157 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4158
b67bfe0d 4159 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4160 &adapter->fdir_filter_list, fdir_node) {
4161 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4162 &filter->filter,
4163 filter->sw_idx,
4164 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4165 IXGBE_FDIR_DROP_QUEUE :
4166 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4167 }
4168
4169 spin_unlock(&adapter->fdir_perfect_lock);
4170}
4171
2a47fa45
JF		 4172static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4173 struct ixgbe_adapter *adapter)
4174{
4175 struct ixgbe_hw *hw = &adapter->hw;
4176 u32 vmolr;
4177
4178 /* No unicast promiscuous support for VMDQ devices. */
4179 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4180 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4181
4182 /* clear the affected bit */
4183 vmolr &= ~IXGBE_VMOLR_MPE;
4184
4185 if (dev->flags & IFF_ALLMULTI) {
4186 vmolr |= IXGBE_VMOLR_MPE;
4187 } else {
4188 vmolr |= IXGBE_VMOLR_ROMPE;
4189 hw->mac.ops.update_mc_addr_list(hw, dev);
4190 }
4191 ixgbe_write_uc_addr_list(adapter->netdev);
4192 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4193}
4194
4195static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4196 u8 *addr, u16 pool)
4197{
4198 struct ixgbe_hw *hw = &adapter->hw;
4199 unsigned int entry;
4200
4201 entry = hw->mac.num_rar_entries - pool;
4202 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4203}
4204
4205static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4206{
4207 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4208 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4209 struct ixgbe_hw *hw = &adapter->hw;
4210 u16 pool = vadapter->pool;
4211 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4212 IXGBE_PSRTYPE_UDPHDR |
4213 IXGBE_PSRTYPE_IPV4HDR |
4214 IXGBE_PSRTYPE_L2HDR |
4215 IXGBE_PSRTYPE_IPV6HDR;
4216
4217 if (hw->mac.type == ixgbe_mac_82598EB)
4218 return;
4219
4220 if (rss_i > 3)
4221 psrtype |= 2 << 29;
4222 else if (rss_i > 1)
4223 psrtype |= 1 << 29;
4224
4225 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4226}
4227
4228/**
4229 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4230 * @rx_ring: ring to free buffers from
4231 **/
4232static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4233{
4234 struct device *dev = rx_ring->dev;
4235 unsigned long size;
4236 u16 i;
4237
4238 /* ring already cleared, nothing to do */
4239 if (!rx_ring->rx_buffer_info)
4240 return;
4241
4242 /* Free all the Rx ring sk_buffs */
4243 for (i = 0; i < rx_ring->count; i++) {
4244 struct ixgbe_rx_buffer *rx_buffer;
4245
4246 rx_buffer = &rx_ring->rx_buffer_info[i];
4247 if (rx_buffer->skb) {
4248 struct sk_buff *skb = rx_buffer->skb;
4249 if (IXGBE_CB(skb)->page_released) {
4250 dma_unmap_page(dev,
4251 IXGBE_CB(skb)->dma,
4252 ixgbe_rx_bufsz(rx_ring),
4253 DMA_FROM_DEVICE);
4254 IXGBE_CB(skb)->page_released = false;
4255 }
4256 dev_kfree_skb(skb);
4257 }
4258 rx_buffer->skb = NULL;
4259 if (rx_buffer->dma)
4260 dma_unmap_page(dev, rx_buffer->dma,
4261 ixgbe_rx_pg_size(rx_ring),
4262 DMA_FROM_DEVICE);
4263 rx_buffer->dma = 0;
4264 if (rx_buffer->page)
4265 __free_pages(rx_buffer->page,
4266 ixgbe_rx_pg_order(rx_ring));
4267 rx_buffer->page = NULL;
4268 }
4269
4270 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4271 memset(rx_ring->rx_buffer_info, 0, size);
4272
4273 /* Zero out the descriptor ring */
4274 memset(rx_ring->desc, 0, rx_ring->size);
4275
4276 rx_ring->next_to_alloc = 0;
4277 rx_ring->next_to_clean = 0;
4278 rx_ring->next_to_use = 0;
4279}
4280
4281static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4282 struct ixgbe_ring *rx_ring)
4283{
4284 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4285 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4286
4287 /* shutdown specific queue receive and wait for dma to settle */
4288 ixgbe_disable_rx_queue(adapter, rx_ring);
4289 usleep_range(10000, 20000);
4290 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4291 ixgbe_clean_rx_ring(rx_ring);
4292 rx_ring->l2_accel_priv = NULL;
4293}
4294
ae72c8d0
JF		 4295static int ixgbe_fwd_ring_down(struct net_device *vdev,
4296 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4297{
4298 struct ixgbe_adapter *adapter = accel->real_adapter;
4299 unsigned int rxbase = accel->rx_base_queue;
4300 unsigned int txbase = accel->tx_base_queue;
4301 int i;
4302
4303 netif_tx_stop_all_queues(vdev);
4304
4305 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4306 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4307 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4308 }
4309
4310 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4311 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4312 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4313 }
4314
4315
4316 return 0;
4317}
4318
4319static int ixgbe_fwd_ring_up(struct net_device *vdev,
4320 struct ixgbe_fwd_adapter *accel)
4321{
4322 struct ixgbe_adapter *adapter = accel->real_adapter;
4323 unsigned int rxbase, txbase, queues;
4324 int i, baseq, err = 0;
4325
4326 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4327 return 0;
4328
4329 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4330 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4331 accel->pool, adapter->num_rx_pools,
4332 baseq, baseq + adapter->num_rx_queues_per_pool,
4333 adapter->fwd_bitmask);
4334
4335 accel->netdev = vdev;
4336 accel->rx_base_queue = rxbase = baseq;
4337 accel->tx_base_queue = txbase = baseq;
4338
4339 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4340 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4341
4342 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4343 adapter->rx_ring[rxbase + i]->netdev = vdev;
4344 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4345 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4346 }
4347
4348 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4349 adapter->tx_ring[txbase + i]->netdev = vdev;
4350 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4351 }
4352
4353 queues = min_t(unsigned int,
4354 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4355 err = netif_set_real_num_tx_queues(vdev, queues);
4356 if (err)
4357 goto fwd_queue_err;
4358
2a47fa45
JF		 4359 err = netif_set_real_num_rx_queues(vdev, queues);
4360 if (err)
4361 goto fwd_queue_err;
4362
4363 if (is_valid_ether_addr(vdev->dev_addr))
4364 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4365
4366 ixgbe_fwd_psrtype(accel);
4367 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4368 return err;
4369fwd_queue_err:
4370 ixgbe_fwd_ring_down(vdev, accel);
4371 return err;
4372}
4373
4374static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4375{
4376 struct net_device *upper;
4377 struct list_head *iter;
4378 int err;
4379
4380 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4381 if (netif_is_macvlan(upper)) {
4382 struct macvlan_dev *dfwd = netdev_priv(upper);
4383 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4384
4385 if (dfwd->fwd_priv) {
4386 err = ixgbe_fwd_ring_up(upper, vadapter);
4387 if (err)
4388 continue;
4389 }
4390 }
4391 }
4392}
4393
9a799d71
AK		 4394static void ixgbe_configure(struct ixgbe_adapter *adapter)
4395{
d2f5e7f3
AS		 4396 struct ixgbe_hw *hw = &adapter->hw;
4397
80605c65 4398 ixgbe_configure_pb(adapter);
7a6b6f51 4399#ifdef CONFIG_IXGBE_DCB
67ebd791 4400 ixgbe_configure_dcb(adapter);
2f90b865 4401#endif
b35d4d42
AD		 4402 /*
4403 * We must restore virtualization before VLANs or else
4404 * the VLVF registers will not be populated
4405 */
4406 ixgbe_configure_virtualization(adapter);
9a799d71 4407
4c1d7b4b 4408 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4409 ixgbe_restore_vlan(adapter);
4410
d2f5e7f3
AS		 4411 switch (hw->mac.type) {
4412 case ixgbe_mac_82599EB:
4413 case ixgbe_mac_X540:
4414 hw->mac.ops.disable_rx_buff(hw);
4415 break;
4416 default:
4417 break;
4418 }
4419
c4cf55e5 4420 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4421 ixgbe_init_fdir_signature_82599(&adapter->hw,
4422 adapter->fdir_pballoc);
e4911d57
AD		 4423 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4424 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4425 adapter->fdir_pballoc);
4426 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4427 }
4c1d7b4b 4428
d2f5e7f3
AS		 4429 switch (hw->mac.type) {
4430 case ixgbe_mac_82599EB:
4431 case ixgbe_mac_X540:
4432 hw->mac.ops.enable_rx_buff(hw);
4433 break;
4434 default:
4435 break;
4436 }
4437
7c8ae65a
AD		 4438#ifdef IXGBE_FCOE
4439 /* configure FCoE L2 filters, redirection table, and Rx control */
4440 ixgbe_configure_fcoe(adapter);
4441
4442#endif /* IXGBE_FCOE */
9a799d71
AK		 4443 ixgbe_configure_tx(adapter);
4444 ixgbe_configure_rx(adapter);
2a47fa45 4445 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4446}
4447
e8e26350
PW		 4448static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4449{
4450 switch (hw->phy.type) {
4451 case ixgbe_phy_sfp_avago:
4452 case ixgbe_phy_sfp_ftl:
4453 case ixgbe_phy_sfp_intel:
4454 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4455 case ixgbe_phy_sfp_passive_tyco:
4456 case ixgbe_phy_sfp_passive_unknown:
4457 case ixgbe_phy_sfp_active_unknown:
4458 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4459 case ixgbe_phy_qsfp_passive_unknown:
4460 case ixgbe_phy_qsfp_active_unknown:
4461 case ixgbe_phy_qsfp_intel:
4462 case ixgbe_phy_qsfp_unknown:
e8e26350 4463 return true;
8917b447
AD		 4464 case ixgbe_phy_nl:
4465 if (hw->mac.type == ixgbe_mac_82598EB)
4466 return true;
e8e26350
PW		 4467 default:
4468 return false;
4469 }
4470}
4471
0ecc061d 4472/**
e8e26350
PW		 4473 * ixgbe_sfp_link_config - set up SFP+ link
4474 * @adapter: pointer to private adapter struct
4475 **/
4476static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4477{
7086400d 4478 /*
52f33af8 4479 * We are assuming the worst case scenario here, and that
7086400d
AD		 4480 * is that an SFP was inserted/removed after the reset
4481 * but before SFP detection was enabled. As such the best
4482 * solution is to just start searching as soon as we start
4483 */
4484 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4485 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4486
7086400d 4487 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4488}
4489
4490/**
4491 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4492 * @hw: pointer to private hardware struct
4493 *
4494 * Returns 0 on success, negative on failure
4495 **/
e8e26350 4496static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4497{
3d292265
JH		 4498 u32 speed;
4499 bool autoneg, link_up = false;
0ecc061d
PWJ		 4500 u32 ret = IXGBE_ERR_LINK_SETUP;
4501
4502 if (hw->mac.ops.check_link)
3d292265 4503 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4504
4505 if (ret)
4506 goto link_cfg_out;
4507
3d292265
JH		 4508 speed = hw->phy.autoneg_advertised;
4509 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4510 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4511 &autoneg);
0ecc061d
PWJ		 4512 if (ret)
4513 goto link_cfg_out;
4514
8620a103 4515 if (hw->mac.ops.setup_link)
fd0326f2 4516 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4517link_cfg_out:
4518 return ret;
4519}
4520
a34bcfff 4521static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4522{
9a799d71 4523 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4524 u32 gpie = 0;
9a799d71 4525
9b471446 4526 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4527 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4528 IXGBE_GPIE_OCD;
4529 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4530 /*
4531 * use EIAM to auto-mask when MSI-X interrupt is asserted
4532 * this saves a register write for every interrupt
4533 */
4534 switch (hw->mac.type) {
4535 case ixgbe_mac_82598EB:
4536 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4537 break;
9b471446 4538 case ixgbe_mac_82599EB:
b93a2226
DS		 4539 case ixgbe_mac_X540:
4540 default:
9b471446
JB		 4541 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4542 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4543 break;
4544 }
4545 } else {
021230d4
AV		 4546 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4547 * specifically only auto mask tx and rx interrupts */
4548 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4549 }
9a799d71 4550
a34bcfff
AD		 4551 /* XXX: to interrupt immediately for EICS writes, enable this */
4552 /* gpie |= IXGBE_GPIE_EIMEN; */
4553
4554 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4555 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4556
4557 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4558 case IXGBE_82599_VMDQ_8Q_MASK:
4559 gpie |= IXGBE_GPIE_VTMODE_16;
4560 break;
4561 case IXGBE_82599_VMDQ_4Q_MASK:
4562 gpie |= IXGBE_GPIE_VTMODE_32;
4563 break;
4564 default:
4565 gpie |= IXGBE_GPIE_VTMODE_64;
4566 break;
4567 }
119fc60a
MC		 4568 }
4569
5fdd31f9 4570 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4571 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4572 switch (adapter->hw.mac.type) {
4573 case ixgbe_mac_82599EB:
4574 gpie |= IXGBE_SDP0_GPIEN;
4575 break;
4576 case ixgbe_mac_X540:
4577 gpie |= IXGBE_EIMS_TS;
4578 break;
4579 default:
4580 break;
4581 }
4582 }
5fdd31f9 4583
a34bcfff
AD		 4584 /* Enable fan failure interrupt */
4585 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4586 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4587
2698b208 4588 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4589 gpie |= IXGBE_SDP1_GPIEN;
4590 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4591 }
a34bcfff
AD		 4592
4593 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4594}
4595
c7ccde0f 4596static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4597{
4598 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4599 struct net_device *upper;
4600 struct list_head *iter;
a34bcfff 4601 int err;
a34bcfff
AD		 4602 u32 ctrl_ext;
4603
4604 ixgbe_get_hw_control(adapter);
4605 ixgbe_setup_gpie(adapter);
e8e26350 4606
9a799d71
AK		 4607 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4608 ixgbe_configure_msix(adapter);
4609 else
4610 ixgbe_configure_msi_and_legacy(adapter);
4611
ec74a471
ET		 4612 /* enable the optics for 82599 SFP+ fiber */
4613 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4614 hw->mac.ops.enable_tx_laser(hw);
4615
c3049c8f 4616 smp_mb__before_clear_bit();
9a799d71 4617 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4618 ixgbe_napi_enable_all(adapter);
4619
73c4b7cd
AD		 4620 if (ixgbe_is_sfp(hw)) {
4621 ixgbe_sfp_link_config(adapter);
4622 } else {
4623 err = ixgbe_non_sfp_link_config(hw);
4624 if (err)
4625 e_err(probe, "link_config FAILED %d\n", err);
4626 }
4627
021230d4
AV		 4628 /* clear any pending interrupts, may auto mask */
4629 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4630 ixgbe_irq_enable(adapter, true, true);
9a799d71 4631
bf069c97
DS		 4632 /*
4633 * If this adapter has a fan, check to see if we had a failure
4634 * before we enabled the interrupt.
4635 */
4636 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4637 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4638 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4639 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4640 }
4641
1da100bb 4642 /* enable transmits */
477de6ed 4643 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4644
2a47fa45
JF		 4645 /* enable any upper devices */
4646 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4647 if (netif_is_macvlan(upper)) {
4648 struct macvlan_dev *vlan = netdev_priv(upper);
4649
4650 if (vlan->fwd_priv)
4651 netif_tx_start_all_queues(upper);
4652 }
4653 }
4654
9a799d71
AK		 4655 /* bring the link up in the watchdog, this could race with our first
4656 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4657 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4658 adapter->link_check_timeout = jiffies;
7086400d 4659 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4660
4661 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4662 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4663 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4664 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4665}
4666
d4f80882
AV		 4667void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4668{
4669 WARN_ON(in_interrupt());
7086400d
AD		 4670 /* put off any impending NetWatchDogTimeout */
4671 adapter->netdev->trans_start = jiffies;
4672
d4f80882 4673 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4674 usleep_range(1000, 2000);
d4f80882 4675 ixgbe_down(adapter);
5809a1ae
GR		 4676 /*
4677 * If SR-IOV enabled then wait a bit before bringing the adapter
4678 * back up to give the VFs time to respond to the reset. The
4679 * two second wait is based upon the watchdog timer cycle in
4680 * the VF driver.
4681 */
4682 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4683 msleep(2000);
d4f80882
AV		 4684 ixgbe_up(adapter);
4685 clear_bit(__IXGBE_RESETTING, &adapter->state);
4686}
4687
c7ccde0f 4688void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4689{
4690 /* hardware has been reset, we need to reload some things */
4691 ixgbe_configure(adapter);
4692
c7ccde0f 4693 ixgbe_up_complete(adapter);
9a799d71
AK		 4694}
4695
4696void ixgbe_reset(struct ixgbe_adapter *adapter)
4697{
c44ade9e 4698 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4699 int err;
4700
b0483c8f
MR		 4701 if (ixgbe_removed(hw->hw_addr))
4702 return;
7086400d
AD		 4703 /* lock SFP init bit to prevent race conditions with the watchdog */
4704 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4705 usleep_range(1000, 2000);
4706
4707 /* clear all SFP and link config related flags while holding SFP_INIT */
4708 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4709 IXGBE_FLAG2_SFP_NEEDS_RESET);
4710 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4711
8ca783ab 4712 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4713 switch (err) {
4714 case 0:
4715 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4716 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4717 break;
4718 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4719 e_dev_err("master disable timed out\n");
da4dd0f7 4720 break;
794caeb2
PWJ		 4721 case IXGBE_ERR_EEPROM_VERSION:
4722 /* We are running on a pre-production device, log a warning */
849c4542 4723 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4724 "Please be aware there may be issues associated with "
849c4542
ET		 4725 "your hardware. If you are experiencing problems "
4726 "please contact your Intel or hardware "
4727 "representative who provided you with this "
4728 "hardware.\n");
794caeb2 4729 break;
da4dd0f7 4730 default:
849c4542 4731 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4732 }
9a799d71 4733
7086400d
AD		 4734 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4735
9a799d71 4736 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4737 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4738
4739 /* update SAN MAC vmdq pool selection */
4740 if (hw->mac.san_mac_rar_index)
4741 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4742
8fecf67c 4743 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4744 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4745}
4746
9a799d71
AK		 4747/**
4748 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4749 * @tx_ring: ring to be cleaned
4750 **/
b6ec895e 4751static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4752{
4753 struct ixgbe_tx_buffer *tx_buffer_info;
4754 unsigned long size;
b6ec895e 4755 u16 i;
9a799d71 4756
84418e3b
AD		 4757 /* ring already cleared, nothing to do */
4758 if (!tx_ring->tx_buffer_info)
4759 return;
9a799d71 4760
84418e3b 4761 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4762 for (i = 0; i < tx_ring->count; i++) {
4763 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4764 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4765 }
4766
dad8a3b3
JF		 4767 netdev_tx_reset_queue(txring_txq(tx_ring));
4768
9a799d71
AK		 4769 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4770 memset(tx_ring->tx_buffer_info, 0, size);
4771
4772 /* Zero out the descriptor ring */
4773 memset(tx_ring->desc, 0, tx_ring->size);
4774
4775 tx_ring->next_to_use = 0;
4776 tx_ring->next_to_clean = 0;
9a799d71
AK		 4777}
4778
4779/**
021230d4 4780 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4781 * @adapter: board private structure
4782 **/
021230d4 4783static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4784{
4785 int i;
4786
021230d4 4787 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4788 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4789}
4790
4791/**
021230d4 4792 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4793 * @adapter: board private structure
4794 **/
021230d4 4795static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4796{
4797 int i;
4798
021230d4 4799 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4800 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4801}
4802
e4911d57
AD		 4803static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4804{
b67bfe0d 4805 struct hlist_node *node2;
e4911d57
AD		 4806 struct ixgbe_fdir_filter *filter;
4807
4808 spin_lock(&adapter->fdir_perfect_lock);
4809
b67bfe0d 4810 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4811 &adapter->fdir_filter_list, fdir_node) {
4812 hlist_del(&filter->fdir_node);
4813 kfree(filter);
4814 }
4815 adapter->fdir_filter_count = 0;
4816
4817 spin_unlock(&adapter->fdir_perfect_lock);
4818}
4819
9a799d71
AK		 4820void ixgbe_down(struct ixgbe_adapter *adapter)
4821{
4822 struct net_device *netdev = adapter->netdev;
7f821875 4823 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4824 struct net_device *upper;
4825 struct list_head *iter;
9a799d71 4826 u32 rxctrl;
bf29ee6c 4827 int i;
9a799d71
AK		 4828
4829 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4830 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4831 return; /* do nothing if already down */
9a799d71
AK		 4832
4833 /* disable receives */
7f821875
JB		 4834 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4835 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4836
2d39d576
YZ		 4837 /* disable all enabled rx queues */
4838 for (i = 0; i < adapter->num_rx_queues; i++)
4839 /* this call also flushes the previous write */
4840 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4841
032b4325 4842 usleep_range(10000, 20000);
9a799d71 4843
7f821875
JB		 4844 netif_tx_stop_all_queues(netdev);
4845
7086400d 4846 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4847 netif_carrier_off(netdev);
4848 netif_tx_disable(netdev);
4849
2a47fa45
JF		 4850 /* disable any upper devices */
4851 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4852 if (netif_is_macvlan(upper)) {
4853 struct macvlan_dev *vlan = netdev_priv(upper);
4854
4855 if (vlan->fwd_priv) {
4856 netif_tx_stop_all_queues(upper);
4857 netif_carrier_off(upper);
4858 netif_tx_disable(upper);
4859 }
4860 }
4861 }
4862
c0dfb90e
JF		 4863 ixgbe_irq_disable(adapter);
4864
4865 ixgbe_napi_disable_all(adapter);
4866
d034acf1
AD		 4867 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4868 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4869 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4870
4871 del_timer_sync(&adapter->service_timer);
4872
34cecbbf 4873 if (adapter->num_vfs) {
8e34d1aa
AD		 4874 /* Clear EITR Select mapping */
4875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4876
4877 /* Mark all the VFs as inactive */
4878 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4879 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4880
34cecbbf
AD		 4881 /* ping all the active vfs to let them know we are going down */
4882 ixgbe_ping_all_vfs(adapter);
4883
4884 /* Disable all VFTE/VFRE TX/RX */
4885 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4886 }
4887
7f821875
JB		 4888 /* disable transmits in the hardware now that interrupts are off */
4889 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4890 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4891 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4892 }
34cecbbf
AD		 4893
4894 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4895 switch (hw->mac.type) {
4896 case ixgbe_mac_82599EB:
b93a2226 4897 case ixgbe_mac_X540:
88512539 4898 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4899 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4900 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4901 break;
4902 default:
4903 break;
4904 }
7f821875 4905
6f4a0e45
PL		 4906 if (!pci_channel_offline(adapter->pdev))
4907 ixgbe_reset(adapter);
c6ecf39a 4908
ec74a471
ET		 4909 /* power down the optics for 82599 SFP+ fiber */
4910 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4911 hw->mac.ops.disable_tx_laser(hw);
4912
9a799d71
AK		 4913 ixgbe_clean_all_tx_rings(adapter);
4914 ixgbe_clean_all_rx_rings(adapter);
4915
5dd2d332 4916#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4917 /* since we reset the hardware DCA settings were cleared */
e35ec126 4918 ixgbe_setup_dca(adapter);
96b0e0f6 4919#endif
9a799d71
AK		 4920}
4921
9a799d71
AK		 4922/**
4923 * ixgbe_tx_timeout - Respond to a Tx Hang
4924 * @netdev: network interface device structure
4925 **/
4926static void ixgbe_tx_timeout(struct net_device *netdev)
4927{
4928 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4929
4930 /* Do the reset outside of interrupt context */
c83c6cbd 4931 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4932}
4933
9a799d71
AK		 4934/**
4935 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4936 * @adapter: board private structure to initialize
4937 *
4938 * ixgbe_sw_init initializes the Adapter private data structure.
4939 * Fields are initialized based on PCI device information and
4940 * OS network device settings (MTU size).
4941 **/
9f9a12f8 4942static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4943{
4944 struct ixgbe_hw *hw = &adapter->hw;
4945 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4946 unsigned int rss, fdir;
cb6d0f5e 4947 u32 fwsm;
7a6b6f51 4948#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4949 int j;
4950 struct tc_configuration *tc;
4951#endif
021230d4 4952
c44ade9e
JB		 4953 /* PCI config space info */
4954
4955 hw->vendor_id = pdev->vendor;
4956 hw->device_id = pdev->device;
4957 hw->revision_id = pdev->revision;
4958 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4959 hw->subsystem_device_id = pdev->subsystem_device;
4960
8fc3bb6d 4961 /* Set common capability flags and settings */
3ed69d7e 4962 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4963 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 4964 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4965 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 4966 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4967 adapter->atr_sample_rate = 20;
d3cb9869
AD		 4968 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4969 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 4970 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4971#ifdef CONFIG_IXGBE_DCA
4972 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4973#endif
4974#ifdef IXGBE_FCOE
4975 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4976 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4977#ifdef CONFIG_IXGBE_DCB
4978 /* Default traffic class to use for FCoE */
4979 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4980#endif /* CONFIG_IXGBE_DCB */
4981#endif /* IXGBE_FCOE */
4982
4983 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 4984 switch (hw->mac.type) {
4985 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 4986 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4987 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4988
bf069c97
DS		 4989 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4990 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 4991
49c7ffbe 4992 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 4993 adapter->ring_feature[RING_F_FDIR].limit = 0;
4994 adapter->atr_sample_rate = 0;
4995 adapter->fdir_pballoc = 0;
4996#ifdef IXGBE_FCOE
4997 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4998 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4999#ifdef CONFIG_IXGBE_DCB
5000 adapter->fcoe.up = 0;
5001#endif /* IXGBE_DCB */
5002#endif /* IXGBE_FCOE */
5003 break;
5004 case ixgbe_mac_82599EB:
5005 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5006 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5007 break;
b93a2226 5008 case ixgbe_mac_X540:
cb6d0f5e
JK		 5009 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5010 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5011 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5012 break;
5013 default:
5014 break;
f8212f97 5015 }
2f90b865 5016
7c8ae65a
AD		 5017#ifdef IXGBE_FCOE
5018 /* FCoE support exists, always init the FCoE lock */
5019 spin_lock_init(&adapter->fcoe.lock);
5020
5021#endif
1fc5f038
AD		 5022 /* n-tuple support exists, always init our spinlock */
5023 spin_lock_init(&adapter->fdir_perfect_lock);
5024
7a6b6f51 5025#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5026 switch (hw->mac.type) {
5027 case ixgbe_mac_X540:
5028 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5029 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5030 break;
5031 default:
5032 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5033 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5034 break;
5035 }
5036
2f90b865
AD		 5037 /* Configure DCB traffic classes */
5038 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5039 tc = &adapter->dcb_cfg.tc_config[j];
5040 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5041 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5042 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5043 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5044 tc->dcb_pfc = pfc_disabled;
5045 }
4de2a022
JF		 5046
5047 /* Initialize default user to priority mapping, UPx->TC0 */
5048 tc = &adapter->dcb_cfg.tc_config[0];
5049 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5050 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5051
2f90b865
AD		 5052 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5053 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5054 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5055 adapter->dcb_set_bitmap = 0x00;
3032309b 5056 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5057 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5058 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5059
5060#endif
9a799d71
AK		 5061
5062 /* default flow control settings */
cd7664f6 5063 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5064 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5065 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5066 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5067 hw->fc.send_xon = true;
73d80953 5068 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5069
99d74487 5070#ifdef CONFIG_PCI_IOV
170e8543
JK		 5071 if (max_vfs > 0)
5072 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5073
99d74487 5074 /* assign number of SR-IOV VFs */
170e8543 5075 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5076 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5077 adapter->num_vfs = 0;
5078 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5079 } else {
5080 adapter->num_vfs = max_vfs;
5081 }
5082 }
5083#endif /* CONFIG_PCI_IOV */
99d74487 5084
30efa5a3 5085 /* enable itr by default in dynamic mode */
f7554a2b 5086 adapter->rx_itr_setting = 1;
f7554a2b 5087 adapter->tx_itr_setting = 1;
30efa5a3 5088
30efa5a3
JB		 5089 /* set default ring sizes */
5090 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5091 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5092
bd198058 5093 /* set default work limits */
59224555 5094 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5095
9a799d71 5096 /* initialize eeprom parameters */
c44ade9e 5097 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5098 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5099 return -EIO;
5100 }
5101
2a47fa45
JF		 5102 /* PF holds first pool slot */
5103 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5104 set_bit(__IXGBE_DOWN, &adapter->state);
5105
5106 return 0;
5107}
5108
5109/**
5110 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5111 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5112 *
5113 * Return 0 on success, negative on failure
5114 **/
b6ec895e 5115int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5116{
b6ec895e 5117 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5118 int orig_node = dev_to_node(dev);
5119 int numa_node = -1;
9a799d71
AK		 5120 int size;
5121
3a581073 5122 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5123
5124 if (tx_ring->q_vector)
5125 numa_node = tx_ring->q_vector->numa_node;
5126
5127 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5128 if (!tx_ring->tx_buffer_info)
89bf67f1 5129 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5130 if (!tx_ring->tx_buffer_info)
5131 goto err;
9a799d71 5132
827da44c
JS		 5133 u64_stats_init(&tx_ring->syncp);
5134
9a799d71 5135 /* round up to nearest 4K */
12207e49 5136 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5137 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5138
de88eeeb
AD		 5139 set_dev_node(dev, numa_node);
5140 tx_ring->desc = dma_alloc_coherent(dev,
5141 tx_ring->size,
5142 &tx_ring->dma,
5143 GFP_KERNEL);
5144 set_dev_node(dev, orig_node);
5145 if (!tx_ring->desc)
5146 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5147 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5148 if (!tx_ring->desc)
5149 goto err;
9a799d71 5150
3a581073
JB		 5151 tx_ring->next_to_use = 0;
5152 tx_ring->next_to_clean = 0;
9a799d71 5153 return 0;
e01c31a5
JB		 5154
5155err:
5156 vfree(tx_ring->tx_buffer_info);
5157 tx_ring->tx_buffer_info = NULL;
b6ec895e 5158 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5159 return -ENOMEM;
9a799d71
AK		 5160}
5161
69888674
AD		 5162/**
5163 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5164 * @adapter: board private structure
5165 *
5166 * If this function returns with an error, then it's possible one or
5167 * more of the rings is populated (while the rest are not). It is the
5168 * callers duty to clean those orphaned rings.
5169 *
5170 * Return 0 on success, negative on failure
5171 **/
5172static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5173{
5174 int i, err = 0;
5175
5176 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5177 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5178 if (!err)
5179 continue;
de3d5b94 5180
396e799c 5181 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5182 goto err_setup_tx;
69888674
AD		 5183 }
5184
de3d5b94
AD		 5185 return 0;
5186err_setup_tx:
5187 /* rewind the index freeing the rings as we go */
5188 while (i--)
5189 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5190 return err;
5191}
5192
9a799d71
AK		 5193/**
5194 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5195 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5196 *
5197 * Returns 0 on success, negative on failure
5198 **/
b6ec895e 5199int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5200{
b6ec895e 5201 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5202 int orig_node = dev_to_node(dev);
5203 int numa_node = -1;
021230d4 5204 int size;
9a799d71 5205
3a581073 5206 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5207
5208 if (rx_ring->q_vector)
5209 numa_node = rx_ring->q_vector->numa_node;
5210
5211 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5212 if (!rx_ring->rx_buffer_info)
89bf67f1 5213 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5214 if (!rx_ring->rx_buffer_info)
5215 goto err;
9a799d71 5216
827da44c
JS		 5217 u64_stats_init(&rx_ring->syncp);
5218
9a799d71 5219 /* Round up to nearest 4K */
3a581073
JB		 5220 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5221 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5222
de88eeeb
AD		 5223 set_dev_node(dev, numa_node);
5224 rx_ring->desc = dma_alloc_coherent(dev,
5225 rx_ring->size,
5226 &rx_ring->dma,
5227 GFP_KERNEL);
5228 set_dev_node(dev, orig_node);
5229 if (!rx_ring->desc)
5230 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5231 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5232 if (!rx_ring->desc)
5233 goto err;
9a799d71 5234
3a581073
JB		 5235 rx_ring->next_to_clean = 0;
5236 rx_ring->next_to_use = 0;
9a799d71
AK		 5237
5238 return 0;
b6ec895e
AD		 5239err:
5240 vfree(rx_ring->rx_buffer_info);
5241 rx_ring->rx_buffer_info = NULL;
5242 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5243 return -ENOMEM;
9a799d71
AK		 5244}
5245
69888674
AD		 5246/**
5247 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5248 * @adapter: board private structure
5249 *
5250 * If this function returns with an error, then it's possible one or
5251 * more of the rings is populated (while the rest are not). It is the
5252 * callers duty to clean those orphaned rings.
5253 *
5254 * Return 0 on success, negative on failure
5255 **/
69888674
AD		 5256static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5257{
5258 int i, err = 0;
5259
5260 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5261 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5262 if (!err)
5263 continue;
de3d5b94 5264
396e799c 5265 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5266 goto err_setup_rx;
69888674
AD		 5267 }
5268
7c8ae65a
AD		 5269#ifdef IXGBE_FCOE
5270 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5271 if (!err)
5272#endif
5273 return 0;
de3d5b94
AD		 5274err_setup_rx:
5275 /* rewind the index freeing the rings as we go */
5276 while (i--)
5277 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5278 return err;
5279}
5280
9a799d71
AK		 5281/**
5282 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5283 * @tx_ring: Tx descriptor ring for a specific queue
5284 *
5285 * Free all transmit software resources
5286 **/
b6ec895e 5287void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5288{
b6ec895e 5289 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5290
5291 vfree(tx_ring->tx_buffer_info);
5292 tx_ring->tx_buffer_info = NULL;
5293
b6ec895e
AD		 5294 /* if not set, then don't free */
5295 if (!tx_ring->desc)
5296 return;
5297
5298 dma_free_coherent(tx_ring->dev, tx_ring->size,
5299 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5300
5301 tx_ring->desc = NULL;
5302}
5303
5304/**
5305 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5306 * @adapter: board private structure
5307 *
5308 * Free all transmit software resources
5309 **/
5310static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5311{
5312 int i;
5313
5314 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5315 if (adapter->tx_ring[i]->desc)
b6ec895e 5316 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5317}
5318
5319/**
b4617240 5320 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5321 * @rx_ring: ring to clean the resources from
5322 *
5323 * Free all receive software resources
5324 **/
b6ec895e 5325void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5326{
b6ec895e 5327 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5328
5329 vfree(rx_ring->rx_buffer_info);
5330 rx_ring->rx_buffer_info = NULL;
5331
b6ec895e
AD		 5332 /* if not set, then don't free */
5333 if (!rx_ring->desc)
5334 return;
5335
5336 dma_free_coherent(rx_ring->dev, rx_ring->size,
5337 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5338
5339 rx_ring->desc = NULL;
5340}
5341
5342/**
5343 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5344 * @adapter: board private structure
5345 *
5346 * Free all receive software resources
5347 **/
5348static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5349{
5350 int i;
5351
7c8ae65a
AD		 5352#ifdef IXGBE_FCOE
5353 ixgbe_free_fcoe_ddp_resources(adapter);
5354
5355#endif
9a799d71 5356 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5357 if (adapter->rx_ring[i]->desc)
b6ec895e 5358 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5359}
5360
9a799d71
AK		 5361/**
5362 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5363 * @netdev: network interface device structure
5364 * @new_mtu: new value for maximum frame size
5365 *
5366 * Returns 0 on success, negative on failure
5367 **/
5368static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5369{
5370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5371 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5372
42c783c5 5373 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5374 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5375 return -EINVAL;
5376
5377 /*
872844dd
AD		 5378 * For 82599EB we cannot allow legacy VFs to enable their receive
5379 * paths when MTU greater than 1500 is configured. So display a
5380 * warning that legacy VFs will be disabled.
655309e9
AD		 5381 */
5382 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5383 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5384 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5385 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5386
396e799c 5387 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5388
021230d4 5389 /* must set new MTU before calling down or up */
9a799d71
AK		 5390 netdev->mtu = new_mtu;
5391
d4f80882
AV		 5392 if (netif_running(netdev))
5393 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5394
5395 return 0;
5396}
5397
5398/**
5399 * ixgbe_open - Called when a network interface is made active
5400 * @netdev: network interface device structure
5401 *
5402 * Returns 0 on success, negative value on failure
5403 *
5404 * The open entry point is called when a network interface is made
5405 * active by the system (IFF_UP). At this point all resources needed
5406 * for transmit and receive operations are allocated, the interrupt
5407 * handler is registered with the OS, the watchdog timer is started,
5408 * and the stack is notified that the interface is ready.
5409 **/
5410static int ixgbe_open(struct net_device *netdev)
5411{
5412 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5413 int err, queues;
4bebfaa5
AK		 5414
5415 /* disallow open during test */
5416 if (test_bit(__IXGBE_TESTING, &adapter->state))
5417 return -EBUSY;
9a799d71 5418
54386467
JB		 5419 netif_carrier_off(netdev);
5420
9a799d71
AK		 5421 /* allocate transmit descriptors */
5422 err = ixgbe_setup_all_tx_resources(adapter);
5423 if (err)
5424 goto err_setup_tx;
5425
9a799d71
AK		 5426 /* allocate receive descriptors */
5427 err = ixgbe_setup_all_rx_resources(adapter);
5428 if (err)
5429 goto err_setup_rx;
5430
5431 ixgbe_configure(adapter);
5432
021230d4 5433 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5434 if (err)
5435 goto err_req_irq;
5436
ac802f5d 5437 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5438 if (adapter->num_rx_pools > 1)
5439 queues = adapter->num_rx_queues_per_pool;
5440 else
5441 queues = adapter->num_tx_queues;
5442
5443 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5444 if (err)
5445 goto err_set_queues;
5446
2a47fa45
JF		 5447 if (adapter->num_rx_pools > 1 &&
5448 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5449 queues = IXGBE_MAX_L2A_QUEUES;
5450 else
5451 queues = adapter->num_rx_queues;
5452 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5453 if (err)
5454 goto err_set_queues;
5455
1a71ab24 5456 ixgbe_ptp_init(adapter);
1a71ab24 5457
c7ccde0f 5458 ixgbe_up_complete(adapter);
9a799d71
AK		 5459
5460 return 0;
5461
ac802f5d
AD		 5462err_set_queues:
5463 ixgbe_free_irq(adapter);
9a799d71 5464err_req_irq:
a20a1199 5465 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5466err_setup_rx:
a20a1199 5467 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5468err_setup_tx:
9a799d71
AK		 5469 ixgbe_reset(adapter);
5470
5471 return err;
5472}
5473
5474/**
5475 * ixgbe_close - Disables a network interface
5476 * @netdev: network interface device structure
5477 *
5478 * Returns 0, this is not allowed to fail
5479 *
5480 * The close entry point is called when an interface is de-activated
5481 * by the OS. The hardware is still under the drivers control, but
5482 * needs to be disabled. A global MAC reset is issued to stop the
5483 * hardware, and all transmit and receive resources are freed.
5484 **/
5485static int ixgbe_close(struct net_device *netdev)
5486{
5487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5488
1a71ab24 5489 ixgbe_ptp_stop(adapter);
1a71ab24 5490
9a799d71
AK		 5491 ixgbe_down(adapter);
5492 ixgbe_free_irq(adapter);
5493
e4911d57
AD		 5494 ixgbe_fdir_filter_exit(adapter);
5495
9a799d71
AK		 5496 ixgbe_free_all_tx_resources(adapter);
5497 ixgbe_free_all_rx_resources(adapter);
5498
5eba3699 5499 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5500
5501 return 0;
5502}
5503
b3c8b4ba
AD		 5504#ifdef CONFIG_PM
5505static int ixgbe_resume(struct pci_dev *pdev)
5506{
c60fbb00
AD		 5507 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5508 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5509 u32 err;
5510
0391bbe3 5511 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5512 pci_set_power_state(pdev, PCI_D0);
5513 pci_restore_state(pdev);
656ab817
DS		 5514 /*
5515 * pci_restore_state clears dev->state_saved so call
5516 * pci_save_state to restore it.
5517 */
5518 pci_save_state(pdev);
9ce77666 5519
5520 err = pci_enable_device_mem(pdev);
b3c8b4ba 5521 if (err) {
849c4542 5522 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5523 return err;
5524 }
5525 pci_set_master(pdev);
5526
dd4d8ca6 5527 pci_wake_from_d3(pdev, false);
b3c8b4ba 5528
b3c8b4ba
AD		 5529 ixgbe_reset(adapter);
5530
495dce12
WJP		 5531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5532
ac802f5d
AD		 5533 rtnl_lock();
5534 err = ixgbe_init_interrupt_scheme(adapter);
5535 if (!err && netif_running(netdev))
c60fbb00 5536 err = ixgbe_open(netdev);
ac802f5d
AD		 5537
5538 rtnl_unlock();
5539
5540 if (err)
5541 return err;
b3c8b4ba
AD		 5542
5543 netif_device_attach(netdev);
5544
5545 return 0;
5546}
b3c8b4ba 5547#endif /* CONFIG_PM */
9d8d05ae
RW		 5548
5549static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5550{
c60fbb00
AD		 5551 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5552 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5553 struct ixgbe_hw *hw = &adapter->hw;
5554 u32 ctrl, fctrl;
5555 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5556#ifdef CONFIG_PM
5557 int retval = 0;
5558#endif
5559
5560 netif_device_detach(netdev);
5561
499ab5cc 5562 rtnl_lock();
b3c8b4ba
AD		 5563 if (netif_running(netdev)) {
5564 ixgbe_down(adapter);
5565 ixgbe_free_irq(adapter);
5566 ixgbe_free_all_tx_resources(adapter);
5567 ixgbe_free_all_rx_resources(adapter);
5568 }
499ab5cc 5569 rtnl_unlock();
b3c8b4ba 5570
5f5ae6fc
AD		 5571 ixgbe_clear_interrupt_scheme(adapter);
5572
b3c8b4ba
AD		 5573#ifdef CONFIG_PM
5574 retval = pci_save_state(pdev);
5575 if (retval)
5576 return retval;
4df10466 5577
b3c8b4ba 5578#endif
f4f1040a
JK		 5579 if (hw->mac.ops.stop_link_on_d3)
5580 hw->mac.ops.stop_link_on_d3(hw);
5581
e8e26350
PW		 5582 if (wufc) {
5583 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5584
ec74a471
ET		 5585 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5586 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5587 hw->mac.ops.enable_tx_laser(hw);
5588
e8e26350
PW		 5589 /* turn on all-multi mode if wake on multicast is enabled */
5590 if (wufc & IXGBE_WUFC_MC) {
5591 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5592 fctrl |= IXGBE_FCTRL_MPE;
5593 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5594 }
5595
5596 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5597 ctrl |= IXGBE_CTRL_GIO_DIS;
5598 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5599
5600 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5601 } else {
5602 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5603 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5604 }
5605
bd508178
AD		 5606 switch (hw->mac.type) {
5607 case ixgbe_mac_82598EB:
dd4d8ca6 5608 pci_wake_from_d3(pdev, false);
bd508178
AD		 5609 break;
5610 case ixgbe_mac_82599EB:
b93a2226 5611 case ixgbe_mac_X540:
bd508178
AD		 5612 pci_wake_from_d3(pdev, !!wufc);
5613 break;
5614 default:
5615 break;
5616 }
b3c8b4ba 5617
9d8d05ae
RW		 5618 *enable_wake = !!wufc;
5619
b3c8b4ba
AD		 5620 ixgbe_release_hw_control(adapter);
5621
5622 pci_disable_device(pdev);
5623
9d8d05ae
RW		 5624 return 0;
5625}
5626
5627#ifdef CONFIG_PM
5628static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5629{
5630 int retval;
5631 bool wake;
5632
5633 retval = __ixgbe_shutdown(pdev, &wake);
5634 if (retval)
5635 return retval;
5636
5637 if (wake) {
5638 pci_prepare_to_sleep(pdev);
5639 } else {
5640 pci_wake_from_d3(pdev, false);
5641 pci_set_power_state(pdev, PCI_D3hot);
5642 }
b3c8b4ba
AD		 5643
5644 return 0;
5645}
9d8d05ae 5646#endif /* CONFIG_PM */
b3c8b4ba
AD		 5647
5648static void ixgbe_shutdown(struct pci_dev *pdev)
5649{
9d8d05ae
RW		 5650 bool wake;
5651
5652 __ixgbe_shutdown(pdev, &wake);
5653
5654 if (system_state == SYSTEM_POWER_OFF) {
5655 pci_wake_from_d3(pdev, wake);
5656 pci_set_power_state(pdev, PCI_D3hot);
5657 }
b3c8b4ba
AD		 5658}
5659
9a799d71
AK		 5660/**
5661 * ixgbe_update_stats - Update the board statistics counters.
5662 * @adapter: board private structure
5663 **/
5664void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5665{
2d86f139 5666 struct net_device *netdev = adapter->netdev;
9a799d71 5667 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5668 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5669 u64 total_mpc = 0;
5670 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5671 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5672 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5673 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5674
d08935c2
DS		 5675 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5676 test_bit(__IXGBE_RESETTING, &adapter->state))
5677 return;
5678
94b982b2 5679 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5680 u64 rsc_count = 0;
94b982b2 5681 u64 rsc_flush = 0;
94b982b2 5682 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5683 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5684 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5685 }
5686 adapter->rsc_total_count = rsc_count;
5687 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5688 }
5689
5b7da515
AD		 5690 for (i = 0; i < adapter->num_rx_queues; i++) {
5691 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5692 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5693 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5694 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5695 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5696 bytes += rx_ring->stats.bytes;
5697 packets += rx_ring->stats.packets;
5698 }
5699 adapter->non_eop_descs = non_eop_descs;
5700 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5701 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5702 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5703 netdev->stats.rx_bytes = bytes;
5704 netdev->stats.rx_packets = packets;
5705
5706 bytes = 0;
5707 packets = 0;
7ca3bc58 5708 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5709 for (i = 0; i < adapter->num_tx_queues; i++) {
5710 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5711 restart_queue += tx_ring->tx_stats.restart_queue;
5712 tx_busy += tx_ring->tx_stats.tx_busy;
5713 bytes += tx_ring->stats.bytes;
5714 packets += tx_ring->stats.packets;
5715 }
eb985f09 5716 adapter->restart_queue = restart_queue;
5b7da515
AD		 5717 adapter->tx_busy = tx_busy;
5718 netdev->stats.tx_bytes = bytes;
5719 netdev->stats.tx_packets = packets;
7ca3bc58 5720
7ca647bd 5721 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5722
5723 /* 8 register reads */
6f11eef7
AV		 5724 for (i = 0; i < 8; i++) {
5725 /* for packet buffers not used, the register should read 0 */
5726 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5727 missed_rx += mpc;
7ca647bd
JP		 5728 hwstats->mpc[i] += mpc;
5729 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5730 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5731 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5732 switch (hw->mac.type) {
5733 case ixgbe_mac_82598EB:
1a70db4b
ET		 5734 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5735 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5736 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5737 hwstats->pxonrxc[i] +=
5738 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5739 break;
5740 case ixgbe_mac_82599EB:
b93a2226 5741 case ixgbe_mac_X540:
bd508178
AD		 5742 hwstats->pxonrxc[i] +=
5743 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5744 break;
5745 default:
5746 break;
e8e26350 5747 }
6f11eef7 5748 }
1a70db4b
ET		 5749
5750 /*16 register reads */
5751 for (i = 0; i < 16; i++) {
5752 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5753 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5754 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5755 (hw->mac.type == ixgbe_mac_X540)) {
5756 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5757 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5758 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5759 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5760 }
5761 }
5762
7ca647bd 5763 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5764 /* work around hardware counting issue */
7ca647bd 5765 hwstats->gprc -= missed_rx;
6f11eef7 5766
c84d324c
JF		 5767 ixgbe_update_xoff_received(adapter);
5768
6f11eef7 5769 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5770 switch (hw->mac.type) {
5771 case ixgbe_mac_82598EB:
5772 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5773 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5774 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5775 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5776 break;
b93a2226 5777 case ixgbe_mac_X540:
58f6bcf9
ET		 5778 /* OS2BMC stats are X540 only*/
5779 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5780 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5781 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5782 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5783 case ixgbe_mac_82599EB:
a4d4f629
AD		 5784 for (i = 0; i < 16; i++)
5785 adapter->hw_rx_no_dma_resources +=
5786 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5787 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5788 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5789 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5790 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5791 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5792 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5793 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5794 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5795 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5796#ifdef IXGBE_FCOE
7ca647bd
JP		 5797 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5798 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5799 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5800 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5801 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5802 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5803 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5804 if (adapter->fcoe.ddp_pool) {
5805 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5806 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5807 unsigned int cpu;
5808 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5809 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5810 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5811 noddp += ddp_pool->noddp;
5812 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5813 }
5a1ee270
AD		 5814 hwstats->fcoe_noddp = noddp;
5815 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5816 }
6d45522c 5817#endif /* IXGBE_FCOE */
bd508178
AD		 5818 break;
5819 default:
5820 break;
e8e26350 5821 }
9a799d71 5822 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5823 hwstats->bprc += bprc;
5824 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5825 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5826 hwstats->mprc -= bprc;
5827 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5828 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5829 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5830 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5831 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5832 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5833 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5834 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5835 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5836 hwstats->lxontxc += lxon;
6f11eef7 5837 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5838 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5839 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5840 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5841 /*
5842 * 82598 errata - tx of flow control packets is included in tx counters
5843 */
5844 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5845 hwstats->gptc -= xon_off_tot;
5846 hwstats->mptc -= xon_off_tot;
5847 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5848 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5849 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5850 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5851 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5852 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5853 hwstats->ptc64 -= xon_off_tot;
5854 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5855 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5856 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5857 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5858 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5859 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5860
5861 /* Fill out the OS statistics structure */
7ca647bd 5862 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5863
5864 /* Rx Errors */
7ca647bd 5865 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5866 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5867 netdev->stats.rx_length_errors = hwstats->rlec;
5868 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5869 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5870}
5871
5872/**
d034acf1 5873 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5874 * @adapter: pointer to the device adapter structure
9a799d71 5875 **/
d034acf1 5876static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5877{
cf8280ee 5878 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5879 int i;
cf8280ee 5880
d034acf1
AD		 5881 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5882 return;
5883
5884 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5885
d034acf1 5886 /* if interface is down do nothing */
fe49f04a 5887 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5888 return;
5889
5890 /* do nothing if we are not using signature filters */
5891 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5892 return;
5893
5894 adapter->fdir_overflow++;
5895
93c52dd0
AD		 5896 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5897 for (i = 0; i < adapter->num_tx_queues; i++)
5898 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5899 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5900 /* re-enable flow director interrupts */
5901 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5902 } else {
5903 e_err(probe, "failed to finish FDIR re-initialization, "
5904 "ignored adding FDIR ATR filters\n");
5905 }
93c52dd0
AD		 5906}
5907
5908/**
5909 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5910 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5911 *
5912 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5913 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5914 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5915 * determine if a hang has occurred.
93c52dd0
AD		 5916 */
5917static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5918{
cf8280ee 5919 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5920 u64 eics = 0;
5921 int i;
cf8280ee 5922
09f40aed 5923 /* If we're down, removing or resetting, just bail */
93c52dd0 5924 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 5925 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 5926 test_bit(__IXGBE_RESETTING, &adapter->state))
5927 return;
22d5a71b 5928
93c52dd0
AD		 5929 /* Force detection of hung controller */
5930 if (netif_carrier_ok(adapter->netdev)) {
5931 for (i = 0; i < adapter->num_tx_queues; i++)
5932 set_check_for_tx_hang(adapter->tx_ring[i]);
5933 }
22d5a71b 5934
fe49f04a
AD		 5935 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5936 /*
5937 * for legacy and MSI interrupts don't set any bits
5938 * that are enabled for EIAM, because this operation
5939 * would set *both* EIMS and EICS for any bit in EIAM
5940 */
5941 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5942 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5943 } else {
5944 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5945 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5946 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5947 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5948 eics |= ((u64)1 << i);
5949 }
cf8280ee 5950 }
9a799d71 5951
93c52dd0 5952 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5953 ixgbe_irq_rearm_queues(adapter, eics);
5954
cf8280ee
JB		 5955}
5956
e8e26350 5957/**
93c52dd0 5958 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5959 * @adapter: pointer to the device adapter structure
5960 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5961 **/
93c52dd0 5962static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5963{
e8e26350 5964 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5965 u32 link_speed = adapter->link_speed;
5966 bool link_up = adapter->link_up;
041441d0 5967 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5968
93c52dd0
AD		 5969 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5970 return;
5971
5972 if (hw->mac.ops.check_link) {
5973 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5974 } else {
93c52dd0
AD		 5975 /* always assume link is up, if no check link function */
5976 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5977 link_up = true;
c4cf55e5 5978 }
041441d0
AD		 5979
5980 if (adapter->ixgbe_ieee_pfc)
5981 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5982
3ebe8fde 5983 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5984 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5985 ixgbe_set_rx_drop_en(adapter);
5986 }
93c52dd0
AD		 5987
5988 if (link_up ||
5989 time_after(jiffies, (adapter->link_check_timeout +
5990 IXGBE_TRY_LINK_TIMEOUT))) {
5991 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5992 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5993 IXGBE_WRITE_FLUSH(hw);
5994 }
5995
5996 adapter->link_up = link_up;
5997 adapter->link_speed = link_speed;
e8e26350
PW		 5998}
5999
107d3018
AD		 6000static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6001{
6002#ifdef CONFIG_IXGBE_DCB
6003 struct net_device *netdev = adapter->netdev;
6004 struct dcb_app app = {
6005 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6006 .protocol = 0,
6007 };
6008 u8 up = 0;
6009
6010 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6011 up = dcb_ieee_getapp_mask(netdev, &app);
6012
6013 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6014#endif
6015}
6016
e8e26350 6017/**
93c52dd0
AD		 6018 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6019 * print link up message
49ce9c2c 6020 * @adapter: pointer to the device adapter structure
e8e26350 6021 **/
93c52dd0 6022static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6023{
93c52dd0 6024 struct net_device *netdev = adapter->netdev;
e8e26350 6025 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6026 u32 link_speed = adapter->link_speed;
6027 bool flow_rx, flow_tx;
e8e26350 6028
93c52dd0
AD		 6029 /* only continue if link was previously down */
6030 if (netif_carrier_ok(netdev))
a985b6c3 6031 return;
63d6e1d8 6032
93c52dd0 6033 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6034
93c52dd0
AD		 6035 switch (hw->mac.type) {
6036 case ixgbe_mac_82598EB: {
6037 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6038 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6039 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6040 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6041 }
6042 break;
6043 case ixgbe_mac_X540:
6044 case ixgbe_mac_82599EB: {
6045 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6046 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6047 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6048 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6049 }
6050 break;
6051 default:
6052 flow_tx = false;
6053 flow_rx = false;
6054 break;
e8e26350 6055 }
3a6a4eda 6056
6cb562d6
JK		 6057 adapter->last_rx_ptp_check = jiffies;
6058
8fecf67c 6059 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6060 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6061
93c52dd0
AD		 6062 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6063 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6064 "10 Gbps" :
6065 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6066 "1 Gbps" :
6067 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6068 "100 Mbps" :
6069 "unknown speed"))),
6070 ((flow_rx && flow_tx) ? "RX/TX" :
6071 (flow_rx ? "RX" :
6072 (flow_tx ? "TX" : "None"))));
e8e26350 6073
93c52dd0 6074 netif_carrier_on(netdev);
93c52dd0 6075 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6076
107d3018
AD		 6077 /* update the default user priority for VFs */
6078 ixgbe_update_default_up(adapter);
6079
befa2af7
AD		 6080 /* ping all the active vfs to let them know link has changed */
6081 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6082}
6083
c4cf55e5 6084/**
93c52dd0
AD		 6085 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6086 * print link down message
49ce9c2c 6087 * @adapter: pointer to the adapter structure
c4cf55e5 6088 **/
581330ba 6089static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6090{
cf8280ee 6091 struct net_device *netdev = adapter->netdev;
c4cf55e5 6092 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6093
93c52dd0
AD		 6094 adapter->link_up = false;
6095 adapter->link_speed = 0;
cf8280ee 6096
93c52dd0
AD		 6097 /* only continue if link was up previously */
6098 if (!netif_carrier_ok(netdev))
6099 return;
264857b8 6100
93c52dd0
AD		 6101 /* poll for SFP+ cable when link is down */
6102 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6103 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6104
8fecf67c 6105 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6106 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6107
93c52dd0
AD		 6108 e_info(drv, "NIC Link is Down\n");
6109 netif_carrier_off(netdev);
befa2af7
AD		 6110
6111 /* ping all the active vfs to let them know link has changed */
6112 ixgbe_ping_all_vfs(adapter);
93c52dd0 6113}
e8e26350 6114
93c52dd0
AD		 6115/**
6116 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6117 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6118 **/
6119static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6120{
c4cf55e5 6121 int i;
93c52dd0 6122 int some_tx_pending = 0;
c4cf55e5 6123
93c52dd0 6124 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6125 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6126 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6127 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6128 some_tx_pending = 1;
6129 break;
6130 }
6131 }
6132
6133 if (some_tx_pending) {
6134 /* We've lost link, so the controller stops DMA,
6135 * but we've got queued Tx work that's never going
6136 * to get done, so reset controller to flush Tx.
6137 * (Do the reset outside of interrupt context).
6138 */
12ff3f3b 6139 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6140 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6141 }
c4cf55e5 6142 }
c4cf55e5
PWJ		 6143}
6144
a985b6c3
GR		 6145static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6146{
6147 u32 ssvpc;
6148
0584d999
GR		 6149 /* Do not perform spoof check for 82598 or if not in IOV mode */
6150 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6151 adapter->num_vfs == 0)
a985b6c3
GR		 6152 return;
6153
6154 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6155
6156 /*
6157 * ssvpc register is cleared on read, if zero then no
6158 * spoofed packets in the last interval.
6159 */
6160 if (!ssvpc)
6161 return;
6162
d6ea0754 6163 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6164}
6165
93c52dd0
AD		 6166/**
6167 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6168 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6169 **/
6170static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6171{
09f40aed 6172 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6173 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6174 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6175 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6176 return;
6177
6178 ixgbe_watchdog_update_link(adapter);
6179
6180 if (adapter->link_up)
6181 ixgbe_watchdog_link_is_up(adapter);
6182 else
6183 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6184
a985b6c3 6185 ixgbe_spoof_check(adapter);
9a799d71 6186 ixgbe_update_stats(adapter);
93c52dd0
AD		 6187
6188 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6189}
10eec955 6190
cf8280ee 6191/**
7086400d 6192 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6193 * @adapter: the ixgbe adapter structure
cf8280ee 6194 **/
7086400d 6195static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6196{
cf8280ee 6197 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6198 s32 err;
cf8280ee 6199
7086400d
AD		 6200 /* not searching for SFP so there is nothing to do here */
6201 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6202 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6203 return;
10eec955 6204
7086400d
AD		 6205 /* someone else is in init, wait until next service event */
6206 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6207 return;
cf8280ee 6208
7086400d
AD		 6209 err = hw->phy.ops.identify_sfp(hw);
6210 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6211 goto sfp_out;
264857b8 6212
7086400d
AD		 6213 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6214 /* If no cable is present, then we need to reset
6215 * the next time we find a good cable. */
6216 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6217 }
9a799d71 6218
7086400d
AD		 6219 /* exit on error */
6220 if (err)
6221 goto sfp_out;
e8e26350 6222
7086400d
AD		 6223 /* exit if reset not needed */
6224 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6225 goto sfp_out;
9a799d71 6226
7086400d 6227 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6228
7086400d
AD		 6229 /*
6230 * A module may be identified correctly, but the EEPROM may not have
6231 * support for that module. setup_sfp() will fail in that case, so
6232 * we should not allow that module to load.
6233 */
6234 if (hw->mac.type == ixgbe_mac_82598EB)
6235 err = hw->phy.ops.reset(hw);
6236 else
6237 err = hw->mac.ops.setup_sfp(hw);
6238
6239 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6240 goto sfp_out;
6241
6242 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6243 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6244
6245sfp_out:
6246 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6247
6248 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6249 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6250 e_dev_err("failed to initialize because an unsupported "
6251 "SFP+ module type was detected.\n");
6252 e_dev_err("Reload the driver after installing a "
6253 "supported module.\n");
6254 unregister_netdev(adapter->netdev);
bc59fcda 6255 }
7086400d 6256}
bc59fcda 6257
7086400d
AD		 6258/**
6259 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6260 * @adapter: the ixgbe adapter structure
7086400d
AD		 6261 **/
6262static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6263{
6264 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6265 u32 speed;
6266 bool autoneg = false;
7086400d
AD		 6267
6268 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6269 return;
6270
6271 /* someone else is in init, wait until next service event */
6272 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6273 return;
6274
6275 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6276
3d292265 6277 speed = hw->phy.autoneg_advertised;
ed33ff66 6278 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6279 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6280
6281 /* setup the highest link when no autoneg */
6282 if (!autoneg) {
6283 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6284 speed = IXGBE_LINK_SPEED_10GB_FULL;
6285 }
6286 }
6287
7086400d 6288 if (hw->mac.ops.setup_link)
fd0326f2 6289 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6290
6291 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6292 adapter->link_check_timeout = jiffies;
6293 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6294}
6295
83c61fa9
GR		 6296#ifdef CONFIG_PCI_IOV
6297static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6298{
6299 int vf;
6300 struct ixgbe_hw *hw = &adapter->hw;
6301 struct net_device *netdev = adapter->netdev;
6302 u32 gpc;
6303 u32 ciaa, ciad;
6304
6305 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6306 if (gpc) /* If incrementing then no need for the check below */
6307 return;
6308 /*
6309 * Check to see if a bad DMA write target from an errant or
6310 * malicious VF has caused a PCIe error. If so then we can
6311 * issue a VFLR to the offending VF(s) and then resume without
6312 * requesting a full slot reset.
6313 */
6314
6315 for (vf = 0; vf < adapter->num_vfs; vf++) {
6316 ciaa = (vf << 16) | 0x80000000;
6317 /* 32 bit read so align, we really want status at offset 6 */
6318 ciaa |= PCI_COMMAND;
6319 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6320 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6321 ciaa &= 0x7FFFFFFF;
6322 /* disable debug mode asap after reading data */
6323 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6324 /* Get the upper 16 bits which will be the PCI status reg */
6325 ciad >>= 16;
6326 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6327 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6328 /* Issue VFLR */
6329 ciaa = (vf << 16) | 0x80000000;
6330 ciaa |= 0xA8;
6331 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6332 ciad = 0x00008000; /* VFLR */
6333 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6334 ciaa &= 0x7FFFFFFF;
6335 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6336 }
6337 }
6338}
6339
6340#endif
7086400d
AD		 6341/**
6342 * ixgbe_service_timer - Timer Call-back
6343 * @data: pointer to adapter cast into an unsigned long
6344 **/
6345static void ixgbe_service_timer(unsigned long data)
6346{
6347 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6348 unsigned long next_event_offset;
83c61fa9 6349 bool ready = true;
7086400d 6350
6bb78cfb
AD		 6351 /* poll faster when waiting for link */
6352 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6353 next_event_offset = HZ / 10;
6354 else
6355 next_event_offset = HZ * 2;
83c61fa9 6356
6bb78cfb 6357#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6358 /*
6359 * don't bother with SR-IOV VF DMA hang check if there are
6360 * no VFs or the link is down
6361 */
6362 if (!adapter->num_vfs ||
6bb78cfb 6363 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6364 goto normal_timer_service;
83c61fa9
GR		 6365
6366 /* If we have VFs allocated then we must check for DMA hangs */
6367 ixgbe_check_for_bad_vf(adapter);
6368 next_event_offset = HZ / 50;
6369 adapter->timer_event_accumulator++;
6370
6bb78cfb 6371 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6372 adapter->timer_event_accumulator = 0;
7086400d 6373 else
6bb78cfb 6374 ready = false;
7086400d 6375
6bb78cfb 6376normal_timer_service:
83c61fa9 6377#endif
7086400d
AD		 6378 /* Reset the timer */
6379 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6380
83c61fa9
GR		 6381 if (ready)
6382 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6383}
6384
c83c6cbd
AD		 6385static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6386{
6387 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6388 return;
6389
6390 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6391
09f40aed 6392 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6393 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6394 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6395 test_bit(__IXGBE_RESETTING, &adapter->state))
6396 return;
6397
6398 ixgbe_dump(adapter);
6399 netdev_err(adapter->netdev, "Reset adapter\n");
6400 adapter->tx_timeout_count++;
6401
8f4c5c9f 6402 rtnl_lock();
c83c6cbd 6403 ixgbe_reinit_locked(adapter);
8f4c5c9f 6404 rtnl_unlock();
c83c6cbd
AD		 6405}
6406
7086400d
AD		 6407/**
6408 * ixgbe_service_task - manages and runs subtasks
6409 * @work: pointer to work_struct containing our data
6410 **/
6411static void ixgbe_service_task(struct work_struct *work)
6412{
6413 struct ixgbe_adapter *adapter = container_of(work,
6414 struct ixgbe_adapter,
6415 service_task);
b0483c8f
MR		 6416 if (ixgbe_removed(adapter->hw.hw_addr)) {
6417 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6418 rtnl_lock();
6419 ixgbe_down(adapter);
6420 rtnl_unlock();
6421 }
6422 ixgbe_service_event_complete(adapter);
6423 return;
6424 }
c83c6cbd 6425 ixgbe_reset_subtask(adapter);
7086400d
AD		 6426 ixgbe_sfp_detection_subtask(adapter);
6427 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6428 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6429 ixgbe_watchdog_subtask(adapter);
d034acf1 6430 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6431 ixgbe_check_hang_subtask(adapter);
891dc082 6432
8fecf67c 6433 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6434 ixgbe_ptp_overflow_check(adapter);
6435 ixgbe_ptp_rx_hang(adapter);
6436 }
7086400d
AD		 6437
6438 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6439}
6440
fd0db0ed
AD		 6441static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6442 struct ixgbe_tx_buffer *first,
244e27ad 6443 u8 *hdr_len)
897ab156 6444{
fd0db0ed 6445 struct sk_buff *skb = first->skb;
897ab156
AD		 6446 u32 vlan_macip_lens, type_tucmd;
6447 u32 mss_l4len_idx, l4len;
9a799d71 6448
8f4fbb9b
AD		 6449 if (skb->ip_summed != CHECKSUM_PARTIAL)
6450 return 0;
6451
897ab156
AD		 6452 if (!skb_is_gso(skb))
6453 return 0;
9a799d71 6454
897ab156 6455 if (skb_header_cloned(skb)) {
244e27ad 6456 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6457 if (err)
6458 return err;
9a799d71 6459 }
9a799d71 6460
897ab156
AD		 6461 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6462 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6463
244e27ad 6464 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 6465 struct iphdr *iph = ip_hdr(skb);
6466 iph->tot_len = 0;
6467 iph->check = 0;
6468 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6469 iph->daddr, 0,
6470 IPPROTO_TCP,
6471 0);
6472 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6473 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6474 IXGBE_TX_FLAGS_CSUM |
6475 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6476 } else if (skb_is_gso_v6(skb)) {
6477 ipv6_hdr(skb)->payload_len = 0;
6478 tcp_hdr(skb)->check =
6479 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6480 &ipv6_hdr(skb)->daddr,
6481 0, IPPROTO_TCP, 0);
244e27ad
AD		 6482 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6483 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6484 }
6485
091a6246 6486 /* compute header lengths */
897ab156
AD		 6487 l4len = tcp_hdrlen(skb);
6488 *hdr_len = skb_transport_offset(skb) + l4len;
6489
091a6246
AD		 6490 /* update gso size and bytecount with header size */
6491 first->gso_segs = skb_shinfo(skb)->gso_segs;
6492 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6493
c44f5f51 6494 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6495 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6496 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6497
6498 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6499 vlan_macip_lens = skb_network_header_len(skb);
6500 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6501 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6502
6503 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6504 mss_l4len_idx);
897ab156
AD		 6505
6506 return 1;
6507}
6508
244e27ad
AD		 6509static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6510 struct ixgbe_tx_buffer *first)
7ca647bd 6511{
fd0db0ed 6512 struct sk_buff *skb = first->skb;
897ab156
AD		 6513 u32 vlan_macip_lens = 0;
6514 u32 mss_l4len_idx = 0;
6515 u32 type_tucmd = 0;
7ca647bd 6516
897ab156 6517 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6518 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6519 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6520 return;
897ab156
AD		 6521 } else {
6522 u8 l4_hdr = 0;
244e27ad 6523 switch (first->protocol) {
897ab156
AD		 6524 case __constant_htons(ETH_P_IP):
6525 vlan_macip_lens |= skb_network_header_len(skb);
6526 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6527 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6528 break;
897ab156
AD		 6529 case __constant_htons(ETH_P_IPV6):
6530 vlan_macip_lens |= skb_network_header_len(skb);
6531 l4_hdr = ipv6_hdr(skb)->nexthdr;
6532 break;
6533 default:
6534 if (unlikely(net_ratelimit())) {
6535 dev_warn(tx_ring->dev,
6536 "partial checksum but proto=%x!\n",
244e27ad 6537 first->protocol);
897ab156 6538 }
7ca647bd
JP		 6539 break;
6540 }
897ab156
AD		 6541
6542 switch (l4_hdr) {
7ca647bd 6543 case IPPROTO_TCP:
897ab156
AD		 6544 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6545 mss_l4len_idx = tcp_hdrlen(skb) <<
6546 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6547 break;
6548 case IPPROTO_SCTP:
897ab156
AD		 6549 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6550 mss_l4len_idx = sizeof(struct sctphdr) <<
6551 IXGBE_ADVTXD_L4LEN_SHIFT;
6552 break;
6553 case IPPROTO_UDP:
6554 mss_l4len_idx = sizeof(struct udphdr) <<
6555 IXGBE_ADVTXD_L4LEN_SHIFT;
6556 break;
6557 default:
6558 if (unlikely(net_ratelimit())) {
6559 dev_warn(tx_ring->dev,
6560 "partial checksum but l4 proto=%x!\n",
244e27ad 6561 l4_hdr);
897ab156 6562 }
7ca647bd
JP		 6563 break;
6564 }
244e27ad
AD		 6565
6566 /* update TX checksum flag */
6567 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6568 }
6569
244e27ad 6570 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6571 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6572 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6573
897ab156
AD		 6574 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6575 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6576}
6577
472148c3
AD		 6578#define IXGBE_SET_FLAG(_input, _flag, _result) \
6579 ((_flag <= _result) ? \
6580 ((u32)(_input & _flag) * (_result / _flag)) : \
6581 ((u32)(_input & _flag) / (_flag / _result)))
6582
6583static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6584{
d3d00239 6585 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6586 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6587 IXGBE_ADVTXD_DCMD_DEXT |
6588 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6589
d3d00239 6590 /* set HW vlan bit if vlan is present */
472148c3
AD		 6591 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6592 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6593
d3d00239 6594 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6595 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6596 IXGBE_ADVTXD_DCMD_TSE);
6597
6598 /* set timestamp bit if present */
6599 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6600 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6601
62748b7b 6602 /* insert frame checksum */
472148c3 6603 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6604
d3d00239
AD		 6605 return cmd_type;
6606}
9a799d71 6607
729739b7
AD		 6608static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6609 u32 tx_flags, unsigned int paylen)
d3d00239 6610{
472148c3 6611 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6612
d3d00239 6613 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6614 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6615 IXGBE_TX_FLAGS_CSUM,
6616 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6617
93f5b3c1 6618 /* enble IPv4 checksum for TSO */
472148c3
AD		 6619 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6620 IXGBE_TX_FLAGS_IPV4,
6621 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6622
7f9643fd
AD		 6623 /*
6624 * Check Context must be set if Tx switch is enabled, which it
6625 * always is for case where virtual functions are running
6626 */
472148c3
AD		 6627 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6628 IXGBE_TX_FLAGS_CC,
6629 IXGBE_ADVTXD_CC);
7f9643fd 6630
472148c3 6631 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6632}
44df32c5 6633
d3d00239
AD		 6634#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6635 IXGBE_TXD_CMD_RS)
6636
6637static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6638 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6639 const u8 hdr_len)
6640{
fd0db0ed 6641 struct sk_buff *skb = first->skb;
729739b7 6642 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6643 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6644 struct skb_frag_struct *frag;
6645 dma_addr_t dma;
6646 unsigned int data_len, size;
244e27ad 6647 u32 tx_flags = first->tx_flags;
472148c3 6648 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6649 u16 i = tx_ring->next_to_use;
d3d00239 6650
729739b7
AD		 6651 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6652
ec718254
AD		 6653 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6654
6655 size = skb_headlen(skb);
6656 data_len = skb->data_len;
729739b7 6657
d3d00239
AD		 6658#ifdef IXGBE_FCOE
6659 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6660 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6661 size -= sizeof(struct fcoe_crc_eof) - data_len;
6662 data_len = 0;
729739b7
AD		 6663 } else {
6664 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6665 }
6666 }
44df32c5 6667
d3d00239 6668#endif
729739b7 6669 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6670
ec718254 6671 tx_buffer = first;
9a799d71 6672
ec718254
AD		 6673 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6674 if (dma_mapping_error(tx_ring->dev, dma))
6675 goto dma_error;
6676
6677 /* record length, and DMA address */
6678 dma_unmap_len_set(tx_buffer, len, size);
6679 dma_unmap_addr_set(tx_buffer, dma, dma);
6680
6681 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6682
729739b7 6683 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6684 tx_desc->read.cmd_type_len =
472148c3 6685 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6686
d3d00239 6687 i++;
729739b7 6688 tx_desc++;
d3d00239 6689 if (i == tx_ring->count) {
e4f74028 6690 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6691 i = 0;
6692 }
ec718254 6693 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6694
6695 dma += IXGBE_MAX_DATA_PER_TXD;
6696 size -= IXGBE_MAX_DATA_PER_TXD;
6697
6698 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6699 }
e5a43549 6700
729739b7
AD		 6701 if (likely(!data_len))
6702 break;
9a799d71 6703
472148c3 6704 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6705
729739b7
AD		 6706 i++;
6707 tx_desc++;
6708 if (i == tx_ring->count) {
6709 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6710 i = 0;
6711 }
ec718254 6712 tx_desc->read.olinfo_status = 0;
9a799d71 6713
d3d00239 6714#ifdef IXGBE_FCOE
9e903e08 6715 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6716#else
9e903e08 6717 size = skb_frag_size(frag);
d3d00239
AD		 6718#endif
6719 data_len -= size;
9a799d71 6720
729739b7
AD		 6721 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6722 DMA_TO_DEVICE);
9a799d71 6723
729739b7 6724 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6725 }
9a799d71 6726
729739b7 6727 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6728 cmd_type |= size | IXGBE_TXD_CMD;
6729 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6730
091a6246 6731 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6732
d3d00239
AD		 6733 /* set the timestamp */
6734 first->time_stamp = jiffies;
9a799d71
AK		 6735
6736 /*
729739b7
AD		 6737 * Force memory writes to complete before letting h/w know there
6738 * are new descriptors to fetch. (Only applicable for weak-ordered
6739 * memory model archs, such as IA-64).
6740 *
6741 * We also need this memory barrier to make certain all of the
6742 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6743 */
6744 wmb();
6745
d3d00239
AD		 6746 /* set next_to_watch value indicating a packet is present */
6747 first->next_to_watch = tx_desc;
6748
729739b7
AD		 6749 i++;
6750 if (i == tx_ring->count)
6751 i = 0;
6752
6753 tx_ring->next_to_use = i;
6754
d3d00239 6755 /* notify HW of packet */
84227bcd 6756 ixgbe_write_tail(tx_ring, i);
d3d00239
AD		 6757
6758 return;
6759dma_error:
729739b7 6760 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6761
6762 /* clear dma mappings for failed tx_buffer_info map */
6763 for (;;) {
729739b7
AD		 6764 tx_buffer = &tx_ring->tx_buffer_info[i];
6765 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6766 if (tx_buffer == first)
d3d00239
AD		 6767 break;
6768 if (i == 0)
6769 i = tx_ring->count;
6770 i--;
6771 }
6772
d3d00239 6773 tx_ring->next_to_use = i;
9a799d71
AK		 6774}
6775
fd0db0ed 6776static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6777 struct ixgbe_tx_buffer *first)
69830529
AD		 6778{
6779 struct ixgbe_q_vector *q_vector = ring->q_vector;
6780 union ixgbe_atr_hash_dword input = { .dword = 0 };
6781 union ixgbe_atr_hash_dword common = { .dword = 0 };
6782 union {
6783 unsigned char *network;
6784 struct iphdr *ipv4;
6785 struct ipv6hdr *ipv6;
6786 } hdr;
ee9e0f0b 6787 struct tcphdr *th;
905e4a41 6788 __be16 vlan_id;
c4cf55e5 6789
69830529
AD		 6790 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6791 if (!q_vector)
6792 return;
6793
6794 /* do nothing if sampling is disabled */
6795 if (!ring->atr_sample_rate)
d3ead241 6796 return;
c4cf55e5 6797
69830529 6798 ring->atr_count++;
c4cf55e5 6799
69830529 6800 /* snag network header to get L4 type and address */
fd0db0ed 6801 hdr.network = skb_network_header(first->skb);
69830529
AD		 6802
6803 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6804 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6805 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6806 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6807 hdr.ipv4->protocol != IPPROTO_TCP))
6808 return;
ee9e0f0b 6809
fd0db0ed 6810 th = tcp_hdr(first->skb);
c4cf55e5 6811
66f32a8b
AD		 6812 /* skip this packet since it is invalid or the socket is closing */
6813 if (!th || th->fin)
69830529
AD		 6814 return;
6815
6816 /* sample on all syn packets or once every atr sample count */
6817 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6818 return;
6819
6820 /* reset sample count */
6821 ring->atr_count = 0;
6822
244e27ad 6823 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6824
6825 /*
6826 * src and dst are inverted, think how the receiver sees them
6827 *
6828 * The input is broken into two sections, a non-compressed section
6829 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6830 * is XORed together and stored in the compressed dword.
6831 */
6832 input.formatted.vlan_id = vlan_id;
6833
6834 /*
6835 * since src port and flex bytes occupy the same word XOR them together
6836 * and write the value to source port portion of compressed dword
6837 */
244e27ad 6838 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6839 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6840 else
244e27ad 6841 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6842 common.port.dst ^= th->source;
6843
244e27ad 6844 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6845 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6846 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6847 } else {
6848 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6849 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6850 hdr.ipv6->saddr.s6_addr32[1] ^
6851 hdr.ipv6->saddr.s6_addr32[2] ^
6852 hdr.ipv6->saddr.s6_addr32[3] ^
6853 hdr.ipv6->daddr.s6_addr32[0] ^
6854 hdr.ipv6->daddr.s6_addr32[1] ^
6855 hdr.ipv6->daddr.s6_addr32[2] ^
6856 hdr.ipv6->daddr.s6_addr32[3];
6857 }
c4cf55e5
PWJ		 6858
6859 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6860 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6861 input, common, ring->queue_index);
c4cf55e5
PWJ		 6862}
6863
63544e9c 6864static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6865{
fc77dc3c 6866 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6867 /* Herbert's original patch had:
6868 * smp_mb__after_netif_stop_queue();
6869 * but since that doesn't exist yet, just open code it. */
6870 smp_mb();
6871
6872 /* We need to check again in a case another CPU has just
6873 * made room available. */
7d4987de 6874 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6875 return -EBUSY;
6876
6877 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6878 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6879 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6880 return 0;
6881}
6882
82d4e46e 6883static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6884{
7d4987de 6885 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6886 return 0;
fc77dc3c 6887 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6888}
6889
f663dd9a 6890static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 6891 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 6892{
f663dd9a
JW		 6893 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
6894#ifdef IXGBE_FCOE
97488bd1
AD		 6895 struct ixgbe_adapter *adapter;
6896 struct ixgbe_ring_feature *f;
6897 int txq;
f663dd9a
JW		 6898#endif
6899
6900 if (fwd_adapter)
6901 return skb->queue_mapping + fwd_adapter->tx_base_queue;
6902
6903#ifdef IXGBE_FCOE
5e09a105 6904
97488bd1
AD		 6905 /*
6906 * only execute the code below if protocol is FCoE
6907 * or FIP and we have FCoE enabled on the adapter
6908 */
6909 switch (vlan_get_protocol(skb)) {
6910 case __constant_htons(ETH_P_FCOE):
6911 case __constant_htons(ETH_P_FIP):
6912 adapter = netdev_priv(dev);
c087663e 6913
97488bd1
AD		 6914 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6915 break;
6916 default:
99932d4f 6917 return fallback(dev, skb);
97488bd1 6918 }
c087663e 6919
97488bd1 6920 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6921
97488bd1
AD		 6922 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6923 smp_processor_id();
56075a98 6924
97488bd1
AD		 6925 while (txq >= f->indices)
6926 txq -= f->indices;
c4cf55e5 6927
97488bd1 6928 return txq + f->offset;
f663dd9a 6929#else
99932d4f 6930 return fallback(dev, skb);
f663dd9a 6931#endif
09a3b1f8
SH		 6932}
6933
fc77dc3c 6934netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6935 struct ixgbe_adapter *adapter,
6936 struct ixgbe_ring *tx_ring)
9a799d71 6937{
d3d00239 6938 struct ixgbe_tx_buffer *first;
5f715823 6939 int tso;
d3d00239 6940 u32 tx_flags = 0;
a535c30e 6941 unsigned short f;
a535c30e 6942 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6943 __be16 protocol = skb->protocol;
63544e9c 6944 u8 hdr_len = 0;
5e09a105 6945
a535c30e
AD		 6946 /*
6947 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6948 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6949 * + 2 desc gap to keep tail from touching head,
6950 * + 1 desc for context descriptor,
6951 * otherwise try next time
6952 */
a535c30e
AD		 6953 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6954 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 6955
a535c30e
AD		 6956 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6957 tx_ring->tx_stats.tx_busy++;
6958 return NETDEV_TX_BUSY;
6959 }
6960
fd0db0ed
AD		 6961 /* record the location of the first descriptor for this packet */
6962 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6963 first->skb = skb;
091a6246
AD		 6964 first->bytecount = skb->len;
6965 first->gso_segs = 1;
fd0db0ed 6966
66f32a8b 6967 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6968 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6969 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6970 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6971 /* else if it is a SW VLAN check the next protocol and store the tag */
6972 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6973 struct vlan_hdr *vhdr, _vhdr;
6974 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6975 if (!vhdr)
6976 goto out_drop;
6977
6978 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6979 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6980 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6981 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6982 }
6983
aa7bd467
JK		 6984 skb_tx_timestamp(skb);
6985
3a6a4eda
JK		 6986 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6987 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6988 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 6989
6990 /* schedule check for Tx timestamp */
6991 adapter->ptp_tx_skb = skb_get(skb);
6992 adapter->ptp_tx_start = jiffies;
6993 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 6994 }
3a6a4eda 6995
9e0c5648
AD		 6996#ifdef CONFIG_PCI_IOV
6997 /*
6998 * Use the l2switch_enable flag - would be false if the DMA
6999 * Tx switch had been disabled.
7000 */
7001 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7002 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7003
7004#endif
32701dc2 7005 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7006 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7007 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7008 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7009 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7010 tx_flags |= (skb->priority & 0x7) <<
7011 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7012 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7013 struct vlan_ethhdr *vhdr;
7014 if (skb_header_cloned(skb) &&
7015 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7016 goto out_drop;
7017 vhdr = (struct vlan_ethhdr *)skb->data;
7018 vhdr->h_vlan_TCI = htons(tx_flags >>
7019 IXGBE_TX_FLAGS_VLAN_SHIFT);
7020 } else {
7021 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7022 }
9a799d71 7023 }
eacd73f7 7024
244e27ad
AD		 7025 /* record initial flags and protocol */
7026 first->tx_flags = tx_flags;
7027 first->protocol = protocol;
7028
eacd73f7 7029#ifdef IXGBE_FCOE
66f32a8b
AD		 7030 /* setup tx offload for FCoE */
7031 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 7032 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7033 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7034 if (tso < 0)
7035 goto out_drop;
9a799d71 7036
66f32a8b 7037 goto xmit_fcoe;
eacd73f7 7038 }
9a799d71 7039
66f32a8b 7040#endif /* IXGBE_FCOE */
244e27ad 7041 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7042 if (tso < 0)
897ab156 7043 goto out_drop;
244e27ad
AD		 7044 else if (!tso)
7045 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7046
7047 /* add the ATR filter if ATR is on */
7048 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7049 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7050
7051#ifdef IXGBE_FCOE
7052xmit_fcoe:
7053#endif /* IXGBE_FCOE */
244e27ad 7054 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 7055
7056 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7057
7058 return NETDEV_TX_OK;
897ab156
AD		 7059
7060out_drop:
fd0db0ed
AD		 7061 dev_kfree_skb_any(first->skb);
7062 first->skb = NULL;
7063
897ab156 7064 return NETDEV_TX_OK;
9a799d71
AK		 7065}
7066
2a47fa45
JF		 7067static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7068 struct net_device *netdev,
7069 struct ixgbe_ring *ring)
84418e3b
AD		 7070{
7071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7072 struct ixgbe_ring *tx_ring;
7073
a50c29dd
AD		 7074 /*
7075 * The minimum packet size for olinfo paylen is 17 so pad the skb
7076 * in order to meet this minimum size requirement.
7077 */
f73332fc
SH		 7078 if (unlikely(skb->len < 17)) {
7079 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7080 return NETDEV_TX_OK;
7081 skb->len = 17;
71a49f77 7082 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7083 }
7084
2a47fa45
JF		 7085 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7086
fc77dc3c 7087 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7088}
7089
2a47fa45
JF		 7090static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7091 struct net_device *netdev)
7092{
7093 return __ixgbe_xmit_frame(skb, netdev, NULL);
7094}
7095
9a799d71
AK		 7096/**
7097 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7098 * @netdev: network interface device structure
7099 * @p: pointer to an address structure
7100 *
7101 * Returns 0 on success, negative on failure
7102 **/
7103static int ixgbe_set_mac(struct net_device *netdev, void *p)
7104{
7105 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7106 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7107 struct sockaddr *addr = p;
7108
7109 if (!is_valid_ether_addr(addr->sa_data))
7110 return -EADDRNOTAVAIL;
7111
7112 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7113 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7114
1d9c0bfd 7115 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 7116
7117 return 0;
7118}
7119
6b73e10d
BH		 7120static int
7121ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7122{
7123 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7124 struct ixgbe_hw *hw = &adapter->hw;
7125 u16 value;
7126 int rc;
7127
7128 if (prtad != hw->phy.mdio.prtad)
7129 return -EINVAL;
7130 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7131 if (!rc)
7132 rc = value;
7133 return rc;
7134}
7135
7136static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7137 u16 addr, u16 value)
7138{
7139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7140 struct ixgbe_hw *hw = &adapter->hw;
7141
7142 if (prtad != hw->phy.mdio.prtad)
7143 return -EINVAL;
7144 return hw->phy.ops.write_reg(hw, addr, devad, value);
7145}
7146
7147static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7148{
7149 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7150
3a6a4eda 7151 switch (cmd) {
3a6a4eda
JK		 7152 case SIOCSHWTSTAMP:
7153 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 7154 default:
7155 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7156 }
6b73e10d
BH		 7157}
7158
0365e6e4
PW		 7159/**
7160 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7161 * netdev->dev_addrs
0365e6e4
PW		 7162 * @netdev: network interface device structure
7163 *
7164 * Returns non-zero on failure
7165 **/
7166static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7167{
7168 int err = 0;
7169 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7170 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7171
7fa7c9dc 7172 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7173 rtnl_lock();
7fa7c9dc 7174 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7175 rtnl_unlock();
7fa7c9dc
AD		 7176
7177 /* update SAN MAC vmdq pool selection */
7178 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7179 }
7180 return err;
7181}
7182
7183/**
7184 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7185 * netdev->dev_addrs
0365e6e4
PW		 7186 * @netdev: network interface device structure
7187 *
7188 * Returns non-zero on failure
7189 **/
7190static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7191{
7192 int err = 0;
7193 struct ixgbe_adapter *adapter = netdev_priv(dev);
7194 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7195
7196 if (is_valid_ether_addr(mac->san_addr)) {
7197 rtnl_lock();
7198 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7199 rtnl_unlock();
7200 }
7201 return err;
7202}
7203
9a799d71
AK		 7204#ifdef CONFIG_NET_POLL_CONTROLLER
7205/*
7206 * Polling 'interrupt' - used by things like netconsole to send skbs
7207 * without having to re-enable interrupts. It's not called while
7208 * the interrupt routine is executing.
7209 */
7210static void ixgbe_netpoll(struct net_device *netdev)
7211{
7212 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7213 int i;
9a799d71 7214
1a647bd2
AD		 7215 /* if interface is down do nothing */
7216 if (test_bit(__IXGBE_DOWN, &adapter->state))
7217 return;
7218
9a799d71 7219 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7220 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7221 for (i = 0; i < adapter->num_q_vectors; i++)
7222 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7223 } else {
7224 ixgbe_intr(adapter->pdev->irq, netdev);
7225 }
9a799d71 7226 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7227}
9a799d71 7228
581330ba 7229#endif
de1036b1
ED		 7230static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7231 struct rtnl_link_stats64 *stats)
7232{
7233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7234 int i;
7235
1a51502b 7236 rcu_read_lock();
de1036b1 7237 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7238 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7239 u64 bytes, packets;
7240 unsigned int start;
7241
1a51502b
ED		 7242 if (ring) {
7243 do {
7244 start = u64_stats_fetch_begin_bh(&ring->syncp);
7245 packets = ring->stats.packets;
7246 bytes = ring->stats.bytes;
7247 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7248 stats->rx_packets += packets;
7249 stats->rx_bytes += bytes;
7250 }
de1036b1 7251 }
1ac9ad13
ED		 7252
7253 for (i = 0; i < adapter->num_tx_queues; i++) {
7254 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7255 u64 bytes, packets;
7256 unsigned int start;
7257
7258 if (ring) {
7259 do {
7260 start = u64_stats_fetch_begin_bh(&ring->syncp);
7261 packets = ring->stats.packets;
7262 bytes = ring->stats.bytes;
7263 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7264 stats->tx_packets += packets;
7265 stats->tx_bytes += bytes;
7266 }
7267 }
1a51502b 7268 rcu_read_unlock();
de1036b1
ED		 7269 /* following stats updated by ixgbe_watchdog_task() */
7270 stats->multicast = netdev->stats.multicast;
7271 stats->rx_errors = netdev->stats.rx_errors;
7272 stats->rx_length_errors = netdev->stats.rx_length_errors;
7273 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7274 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7275 return stats;
7276}
7277
8af3c33f 7278#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7279/**
7280 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7281 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7282 * @tc: number of traffic classes currently enabled
7283 *
7284 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7285 * 802.1Q priority maps to a packet buffer that exists.
7286 */
7287static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7288{
7289 struct ixgbe_hw *hw = &adapter->hw;
7290 u32 reg, rsave;
7291 int i;
7292
7293 /* 82598 have a static priority to TC mapping that can not
7294 * be changed so no validation is needed.
7295 */
7296 if (hw->mac.type == ixgbe_mac_82598EB)
7297 return;
7298
7299 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7300 rsave = reg;
7301
7302 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7303 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7304
7305 /* If up2tc is out of bounds default to zero */
7306 if (up2tc > tc)
7307 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7308 }
7309
7310 if (reg != rsave)
7311 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7312
7313 return;
7314}
7315
02debdc9
AD		 7316/**
7317 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7318 * @adapter: Pointer to adapter struct
7319 *
7320 * Populate the netdev user priority to tc map
7321 */
7322static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7323{
7324 struct net_device *dev = adapter->netdev;
7325 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7326 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7327 u8 prio;
7328
7329 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7330 u8 tc = 0;
7331
7332 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7333 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7334 else if (ets)
7335 tc = ets->prio_tc[prio];
7336
7337 netdev_set_prio_tc_map(dev, prio, tc);
7338 }
7339}
7340
cca73c59 7341#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7342/**
7343 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7344 *
7345 * @netdev: net device to configure
7346 * @tc: number of traffic classes to enable
7347 */
7348int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7349{
8b1c0b24
JF		 7350 struct ixgbe_adapter *adapter = netdev_priv(dev);
7351 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7352 bool pools;
8b1c0b24 7353
8b1c0b24 7354 /* Hardware supports up to 8 traffic classes */
4de2a022 7355 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7356 (hw->mac.type == ixgbe_mac_82598EB &&
7357 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7358 return -EINVAL;
7359
2a47fa45
JF		 7360 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7361 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7362 return -EBUSY;
7363
8b1c0b24 7364 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7365 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7366 * hardware is not flexible enough to do this dynamically.
7367 */
7368 if (netif_running(dev))
7369 ixgbe_close(dev);
7370 ixgbe_clear_interrupt_scheme(adapter);
7371
cca73c59 7372#ifdef CONFIG_IXGBE_DCB
e7589eab 7373 if (tc) {
8b1c0b24 7374 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7375 ixgbe_set_prio_tc_map(adapter);
7376
e7589eab 7377 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7378
943561d3
AD		 7379 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7380 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7381 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7382 }
e7589eab 7383 } else {
8b1c0b24 7384 netdev_reset_tc(dev);
02debdc9 7385
943561d3
AD		 7386 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7387 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7388
7389 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7390
7391 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7392 adapter->dcb_cfg.pfc_mode_enable = false;
7393 }
7394
8b1c0b24 7395 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7396
7397#endif /* CONFIG_IXGBE_DCB */
7398 ixgbe_init_interrupt_scheme(adapter);
7399
8b1c0b24 7400 if (netif_running(dev))
cca73c59 7401 return ixgbe_open(dev);
8b1c0b24
JF		 7402
7403 return 0;
7404}
de1036b1 7405
da36b647
GR		 7406#ifdef CONFIG_PCI_IOV
7407void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7408{
7409 struct net_device *netdev = adapter->netdev;
7410
7411 rtnl_lock();
da36b647 7412 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7413 rtnl_unlock();
7414}
7415
7416#endif
082757af
DS		 7417void ixgbe_do_reset(struct net_device *netdev)
7418{
7419 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7420
7421 if (netif_running(netdev))
7422 ixgbe_reinit_locked(adapter);
7423 else
7424 ixgbe_reset(adapter);
7425}
7426
c8f44aff 7427static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7428 netdev_features_t features)
082757af
DS		 7429{
7430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7431
082757af 7432 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7433 if (!(features & NETIF_F_RXCSUM))
7434 features &= ~NETIF_F_LRO;
082757af 7435
567d2de2
AD		 7436 /* Turn off LRO if not RSC capable */
7437 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7438 features &= ~NETIF_F_LRO;
8e2813f5 7439
567d2de2 7440 return features;
082757af
DS		 7441}
7442
c8f44aff 7443static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7444 netdev_features_t features)
082757af
DS		 7445{
7446 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7447 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7448 bool need_reset = false;
7449
082757af 7450 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7451 if (!(features & NETIF_F_LRO)) {
7452 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7453 need_reset = true;
567d2de2
AD		 7454 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7455 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7456 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7457 if (adapter->rx_itr_setting == 1 ||
7458 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7459 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7460 need_reset = true;
7461 } else if ((changed ^ features) & NETIF_F_LRO) {
7462 e_info(probe, "rx-usecs set too low, "
7463 "disabling RSC\n");
082757af
DS		 7464 }
7465 }
7466
7467 /*
7468 * Check if Flow Director n-tuple support was enabled or disabled. If
7469 * the state changed, we need to reset.
7470 */
39cb681b
AD		 7471 switch (features & NETIF_F_NTUPLE) {
7472 case NETIF_F_NTUPLE:
567d2de2 7473 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7474 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7475 need_reset = true;
7476
567d2de2
AD		 7477 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7478 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7479 break;
7480 default:
7481 /* turn off perfect filters, enable ATR and reset */
7482 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7483 need_reset = true;
7484
7485 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7486
7487 /* We cannot enable ATR if SR-IOV is enabled */
7488 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7489 break;
7490
7491 /* We cannot enable ATR if we have 2 or more traffic classes */
7492 if (netdev_get_num_tc(netdev) > 1)
7493 break;
7494
7495 /* We cannot enable ATR if RSS is disabled */
7496 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7497 break;
7498
7499 /* A sample rate of 0 indicates ATR disabled */
7500 if (!adapter->atr_sample_rate)
7501 break;
7502
7503 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7504 break;
082757af
DS		 7505 }
7506
f646968f 7507 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7508 ixgbe_vlan_strip_enable(adapter);
7509 else
7510 ixgbe_vlan_strip_disable(adapter);
7511
3f2d1c0f
BG		 7512 if (changed & NETIF_F_RXALL)
7513 need_reset = true;
7514
567d2de2 7515 netdev->features = features;
082757af
DS		 7516 if (need_reset)
7517 ixgbe_do_reset(netdev);
7518
7519 return 0;
082757af
DS		 7520}
7521
edc7d573 7522static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7523 struct net_device *dev,
6b6e2725 7524 const unsigned char *addr,
0f4b0add
JF		 7525 u16 flags)
7526{
7527 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7528 int err;
7529
7530 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7531 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7532
b1ac1ef7
JF		 7533 /* Hardware does not support aging addresses so if a
7534 * ndm_state is given only allow permanent addresses
7535 */
7536 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7537 pr_info("%s: FDB only supports static addresses\n",
7538 ixgbe_driver_name);
7539 return -EINVAL;
7540 }
7541
46acc460 7542 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7543 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7544
7545 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7546 err = dev_uc_add_excl(dev, addr);
0f4b0add 7547 else
95447461
JF		 7548 err = -ENOMEM;
7549 } else if (is_multicast_ether_addr(addr)) {
7550 err = dev_mc_add_excl(dev, addr);
7551 } else {
7552 err = -EINVAL;
0f4b0add
JF		 7553 }
7554
7555 /* Only return duplicate errors if NLM_F_EXCL is set */
7556 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7557 err = 0;
7558
7559 return err;
7560}
7561
815cccbf
JF		 7562static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7563 struct nlmsghdr *nlh)
7564{
7565 struct ixgbe_adapter *adapter = netdev_priv(dev);
7566 struct nlattr *attr, *br_spec;
7567 int rem;
7568
7569 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7570 return -EOPNOTSUPP;
7571
7572 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7573
7574 nla_for_each_nested(attr, br_spec, rem) {
7575 __u16 mode;
7576 u32 reg = 0;
7577
7578 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7579 continue;
7580
7581 mode = nla_get_u16(attr);
9b735984 7582 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7583 reg = 0;
9b735984
GR		 7584 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7585 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7586 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7587 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7588 } else
815cccbf
JF		 7589 return -EINVAL;
7590
7591 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7592
7593 e_info(drv, "enabling bridge mode: %s\n",
7594 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7595 }
7596
7597 return 0;
7598}
7599
7600static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7601 struct net_device *dev,
7602 u32 filter_mask)
815cccbf
JF		 7603{
7604 struct ixgbe_adapter *adapter = netdev_priv(dev);
7605 u16 mode;
7606
7607 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7608 return 0;
7609
9b735984 7610 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7611 mode = BRIDGE_MODE_VEB;
7612 else
7613 mode = BRIDGE_MODE_VEPA;
7614
7615 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7616}
7617
2a47fa45
JF		 7618static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7619{
7620 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7621 struct ixgbe_adapter *adapter = netdev_priv(pdev);
51f3773b 7622 unsigned int limit;
2a47fa45
JF		 7623 int pool, err;
7624
219354d4
JF		 7625#ifdef CONFIG_RPS
7626 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7627 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7628 vdev->name);
7629 return ERR_PTR(-EINVAL);
7630 }
7631#endif
2a47fa45 7632 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7633 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7634 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7635 netdev_info(pdev,
7636 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7637 pdev->name);
7638 return ERR_PTR(-EINVAL);
7639 }
7640
7641 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7642 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7643 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7644 return ERR_PTR(-EBUSY);
7645
7646 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7647 if (!fwd_adapter)
7648 return ERR_PTR(-ENOMEM);
7649
7650 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7651 adapter->num_rx_pools++;
7652 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7653 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7654
7655 /* Enable VMDq flag so device will be set in VM mode */
7656 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7657 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7658 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7659
7660 /* Force reinit of ring allocation with VMDQ enabled */
7661 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7662 if (err)
7663 goto fwd_add_err;
7664 fwd_adapter->pool = pool;
7665 fwd_adapter->real_adapter = adapter;
7666 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7667 if (err)
7668 goto fwd_add_err;
7669 netif_tx_start_all_queues(vdev);
7670 return fwd_adapter;
7671fwd_add_err:
7672 /* unwind counter and free adapter struct */
7673 netdev_info(pdev,
7674 "%s: dfwd hardware acceleration failed\n", vdev->name);
7675 clear_bit(pool, &adapter->fwd_bitmask);
7676 adapter->num_rx_pools--;
7677 kfree(fwd_adapter);
7678 return ERR_PTR(err);
7679}
7680
7681static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7682{
7683 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7684 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7685 unsigned int limit;
2a47fa45
JF		 7686
7687 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7688 adapter->num_rx_pools--;
7689
51f3773b
JF		 7690 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7691 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7692 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7693 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7694 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7695 fwd_adapter->pool, adapter->num_rx_pools,
7696 fwd_adapter->rx_base_queue,
7697 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7698 adapter->fwd_bitmask);
7699 kfree(fwd_adapter);
7700}
7701
0edc3527 7702static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7703 .ndo_open = ixgbe_open,
0edc3527 7704 .ndo_stop = ixgbe_close,
00829823 7705 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7706 .ndo_select_queue = ixgbe_select_queue,
581330ba 7707 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7708 .ndo_validate_addr = eth_validate_addr,
7709 .ndo_set_mac_address = ixgbe_set_mac,
7710 .ndo_change_mtu = ixgbe_change_mtu,
7711 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7712 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7713 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7714 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7715 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7716 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7717 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7718 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7719 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7720 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7721#ifdef CONFIG_IXGBE_DCB
24095aa3 7722 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7723#endif
0edc3527
SH		 7724#ifdef CONFIG_NET_POLL_CONTROLLER
7725 .ndo_poll_controller = ixgbe_netpoll,
7726#endif
e0d1095a 7727#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7728 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7729#endif
332d4a7d
YZ		 7730#ifdef IXGBE_FCOE
7731 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7732 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7733 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7734 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7735 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7736 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7737 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7738#endif /* IXGBE_FCOE */
082757af
DS		 7739 .ndo_set_features = ixgbe_set_features,
7740 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7741 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7742 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7743 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7744 .ndo_dfwd_add_station = ixgbe_fwd_add,
7745 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7746};
7747
e027d1ae
JK		 7748/**
7749 * ixgbe_enumerate_functions - Get the number of ports this device has
7750 * @adapter: adapter structure
7751 *
7752 * This function enumerates the phsyical functions co-located on a single slot,
7753 * in order to determine how many ports a device has. This is most useful in
7754 * determining the required GT/s of PCIe bandwidth necessary for optimal
7755 * performance.
7756 **/
7757static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7758{
e027d1ae
JK		 7759 struct list_head *entry;
7760 int physfns = 0;
7761
f1f96579
JK		 7762 /* Some cards can not use the generic count PCIe functions method,
7763 * because they are behind a parent switch, so we hardcode these with
7764 * the correct number of functions.
e027d1ae 7765 */
f1f96579 7766 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7767 physfns = 4;
f1f96579 7768 } else {
e027d1ae
JK		 7769 list_for_each(entry, &adapter->pdev->bus_list) {
7770 struct pci_dev *pdev =
7771 list_entry(entry, struct pci_dev, bus_list);
7772 /* don't count virtual functions */
7773 if (!pdev->is_virtfn)
7774 physfns++;
7775 }
7776 }
7777
7778 return physfns;
7779}
7780
8e2813f5
JK		 7781/**
7782 * ixgbe_wol_supported - Check whether device supports WoL
7783 * @hw: hw specific details
7784 * @device_id: the device ID
7785 * @subdev_id: the subsystem device ID
7786 *
7787 * This function is used by probe and ethtool to determine
7788 * which devices have WoL support
7789 *
7790 **/
7791int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7792 u16 subdevice_id)
7793{
7794 struct ixgbe_hw *hw = &adapter->hw;
7795 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7796 int is_wol_supported = 0;
7797
7798 switch (device_id) {
7799 case IXGBE_DEV_ID_82599_SFP:
7800 /* Only these subdevices could supports WOL */
7801 switch (subdevice_id) {
87557440 7802 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7803 case IXGBE_SUBDEV_ID_82599_560FLR:
7804 /* only support first port */
7805 if (hw->bus.func != 0)
7806 break;
5700ff26 7807 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7808 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7809 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7810 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7811 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7812 is_wol_supported = 1;
7813 break;
7814 }
7815 break;
5daebbb0
DS		 7816 case IXGBE_DEV_ID_82599EN_SFP:
7817 /* Only this subdevice supports WOL */
7818 switch (subdevice_id) {
7819 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7820 is_wol_supported = 1;
7821 break;
7822 }
7823 break;
8e2813f5
JK		 7824 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7825 /* All except this subdevice support WOL */
7826 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7827 is_wol_supported = 1;
7828 break;
7829 case IXGBE_DEV_ID_82599_KX4:
7830 is_wol_supported = 1;
7831 break;
7832 case IXGBE_DEV_ID_X540T:
df376f0d 7833 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7834 /* check eeprom to see if enabled wol */
7835 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7836 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7837 (hw->bus.func == 0))) {
7838 is_wol_supported = 1;
7839 }
7840 break;
7841 }
7842
7843 return is_wol_supported;
7844}
7845
9a799d71
AK		 7846/**
7847 * ixgbe_probe - Device Initialization Routine
7848 * @pdev: PCI device information struct
7849 * @ent: entry in ixgbe_pci_tbl
7850 *
7851 * Returns 0 on success, negative on failure
7852 *
7853 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7854 * The OS initialization, configuring of the adapter private structure,
7855 * and a hardware reset occur.
7856 **/
1dd06ae8 7857static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7858{
7859 struct net_device *netdev;
7860 struct ixgbe_adapter *adapter = NULL;
7861 struct ixgbe_hw *hw;
7862 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7863 static int cards_found;
e027d1ae 7864 int i, err, pci_using_dac, expected_gts;
d3cb9869 7865 unsigned int indices = MAX_TX_QUEUES;
289700db 7866 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7867#ifdef IXGBE_FCOE
7868 u16 device_caps;
7869#endif
289700db 7870 u32 eec;
9a799d71 7871
bded64a7
AG		 7872 /* Catch broken hardware that put the wrong VF device ID in
7873 * the PCIe SR-IOV capability.
7874 */
7875 if (pdev->is_virtfn) {
7876 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7877 pci_name(pdev), pdev->vendor, pdev->device);
7878 return -EINVAL;
7879 }
7880
9ce77666 7881 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7882 if (err)
7883 return err;
7884
f5f2eda8 7885 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7886 pci_using_dac = 1;
7887 } else {
f5f2eda8 7888 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7889 if (err) {
f5f2eda8
RK		 7890 dev_err(&pdev->dev,
7891 "No usable DMA configuration, aborting\n");
7892 goto err_dma;
9a799d71
AK		 7893 }
7894 pci_using_dac = 0;
7895 }
7896
9ce77666 7897 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7898 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7899 if (err) {
b8bc0421
DC		 7900 dev_err(&pdev->dev,
7901 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7902 goto err_pci_reg;
7903 }
7904
19d5afd4 7905 pci_enable_pcie_error_reporting(pdev);
6fabd715 7906
9a799d71 7907 pci_set_master(pdev);
fb3b27bc 7908 pci_save_state(pdev);
9a799d71 7909
d3cb9869 7910 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7911#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7912 /* 8 TC w/ 4 queues per TC */
7913 indices = 4 * MAX_TRAFFIC_CLASS;
7914#else
7915 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7916#endif
d3cb9869 7917 }
e901acd6 7918
c85a2618 7919 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7920 if (!netdev) {
7921 err = -ENOMEM;
7922 goto err_alloc_etherdev;
7923 }
7924
9a799d71
AK		 7925 SET_NETDEV_DEV(netdev, &pdev->dev);
7926
9a799d71 7927 adapter = netdev_priv(netdev);
c60fbb00 7928 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7929
7930 adapter->netdev = netdev;
7931 adapter->pdev = pdev;
7932 hw = &adapter->hw;
7933 hw->back = adapter;
b3f4d599 7934 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7935
05857980 7936 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7937 pci_resource_len(pdev, 0));
2a1a091c 7938 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 7939 if (!hw->hw_addr) {
7940 err = -EIO;
7941 goto err_ioremap;
7942 }
7943
0edc3527 7944 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7945 ixgbe_set_ethtool_ops(netdev);
9a799d71 7946 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7947 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7948
9a799d71
AK		 7949 adapter->bd_number = cards_found;
7950
9a799d71
AK		 7951 /* Setup hw api */
7952 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7953 hw->mac.type = ii->mac;
9a799d71 7954
c44ade9e
JB		 7955 /* EEPROM */
7956 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7957 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7958 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7959 if (!(eec & (1 << 8)))
7960 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7961
7962 /* PHY */
7963 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7964 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7965 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7966 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7967 hw->phy.mdio.mmds = 0;
7968 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7969 hw->phy.mdio.dev = netdev;
7970 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7971 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7972
8ca783ab 7973 ii->get_invariants(hw);
9a799d71
AK		 7974
7975 /* setup the private structure */
7976 err = ixgbe_sw_init(adapter);
7977 if (err)
7978 goto err_sw_init;
7979
0b2679d6
DS		 7980 /* Cache if MNG FW is up so we don't have to read the REG later */
7981 if (hw->mac.ops.mng_fw_enabled)
7982 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7983
e86bff0e 7984 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7985 switch (adapter->hw.mac.type) {
7986 case ixgbe_mac_82599EB:
7987 case ixgbe_mac_X540:
e86bff0e 7988 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7989 break;
7990 default:
7991 break;
7992 }
e86bff0e 7993
bf069c97
DS		 7994 /*
7995 * If there is a fan on this device and it has failed log the
7996 * failure.
7997 */
7998 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7999 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8000 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8001 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8002 }
8003
8ef78adc
PWJ		 8004 if (allow_unsupported_sfp)
8005 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8006
c44ade9e 8007 /* reset_hw fills in the perm_addr as well */
119fc60a 8008 hw->phy.reset_if_overtemp = true;
c44ade9e 8009 err = hw->mac.ops.reset_hw(hw);
119fc60a 8010 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8011 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8012 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8013 err = 0;
8014 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8015 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8016 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8017 goto err_sw_init;
8018 } else if (err) {
849c4542 8019 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8020 goto err_sw_init;
8021 }
8022
99d74487 8023#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8024 /* SR-IOV not supported on the 82598 */
8025 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8026 goto skip_sriov;
8027 /* Mailbox */
8028 ixgbe_init_mbx_params_pf(hw);
8029 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8030 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8031 ixgbe_enable_sriov(adapter);
60a1a680 8032skip_sriov:
1cdd1ec8 8033
99d74487 8034#endif
396e799c 8035 netdev->features = NETIF_F_SG |
e8e9f696 8036 NETIF_F_IP_CSUM |
082757af 8037 NETIF_F_IPV6_CSUM |
f646968f
PM		 8038 NETIF_F_HW_VLAN_CTAG_TX |
8039 NETIF_F_HW_VLAN_CTAG_RX |
8040 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8041 NETIF_F_TSO |
8042 NETIF_F_TSO6 |
082757af 8043 NETIF_F_RXHASH |
8bf1264d 8044 NETIF_F_RXCSUM;
9a799d71 8045
8bf1264d 8046 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8047
58be7666
DS		 8048 switch (adapter->hw.mac.type) {
8049 case ixgbe_mac_82599EB:
8050 case ixgbe_mac_X540:
45a5ead0 8051 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8052 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8053 NETIF_F_NTUPLE;
58be7666
DS		 8054 break;
8055 default:
8056 break;
8057 }
45a5ead0 8058
3f2d1c0f
BG		 8059 netdev->hw_features |= NETIF_F_RXALL;
8060
ad31c402
JK		 8061 netdev->vlan_features |= NETIF_F_TSO;
8062 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8063 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8064 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8065 netdev->vlan_features |= NETIF_F_SG;
8066
01789349 8067 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8068 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8069
7a6b6f51 8070#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8071 netdev->dcbnl_ops = &dcbnl_ops;
8072#endif
8073
eacd73f7 8074#ifdef IXGBE_FCOE
0d551589 8075 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8076 unsigned int fcoe_l;
8077
eacd73f7
YZ		 8078 if (hw->mac.ops.get_device_caps) {
8079 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8080 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8081 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8082 }
7c8ae65a 8083
d3cb9869
AD		 8084
8085 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8086 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8087
a58915c7
AD		 8088 netdev->features |= NETIF_F_FSO |
8089 NETIF_F_FCOE_CRC;
8090
7c8ae65a
AD		 8091 netdev->vlan_features |= NETIF_F_FSO |
8092 NETIF_F_FCOE_CRC |
8093 NETIF_F_FCOE_MTU;
5e09d7f6 8094 }
eacd73f7 8095#endif /* IXGBE_FCOE */
7b872a55 8096 if (pci_using_dac) {
9a799d71 8097 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8098 netdev->vlan_features |= NETIF_F_HIGHDMA;
8099 }
9a799d71 8100
082757af
DS		 8101 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8102 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8103 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8104 netdev->features |= NETIF_F_LRO;
8105
9a799d71 8106 /* make sure the EEPROM is good */
c44ade9e 8107 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8108 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8109 err = -EIO;
35937c05 8110 goto err_sw_init;
9a799d71
AK		 8111 }
8112
8113 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8114
aaeb6cdf 8115 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8116 e_dev_err("invalid MAC address\n");
9a799d71 8117 err = -EIO;
35937c05 8118 goto err_sw_init;
9a799d71
AK		 8119 }
8120
7086400d 8121 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8122 (unsigned long) adapter);
9a799d71 8123
7086400d
AD		 8124 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8125 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8126
021230d4
AV		 8127 err = ixgbe_init_interrupt_scheme(adapter);
8128 if (err)
8129 goto err_sw_init;
9a799d71 8130
8e2813f5 8131 /* WOL not supported for all devices */
c23f5b6b 8132 adapter->wol = 0;
8e2813f5 8133 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8134 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8135 pdev->subsystem_device);
6b92b0ba 8136 if (hw->wol_enabled)
9417c464 8137 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8138
e8e26350
PW		 8139 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8140
15e5209f
ET		 8141 /* save off EEPROM version number */
8142 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8143 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8144
04f165ef
PW		 8145 /* pick up the PCI bus settings for reporting later */
8146 hw->mac.ops.get_bus_info(hw);
e027d1ae 8147 if (ixgbe_pcie_from_parent(hw))
b8e82001 8148 ixgbe_get_parent_bus_info(adapter);
04f165ef 8149
e027d1ae
JK		 8150 /* calculate the expected PCIe bandwidth required for optimal
8151 * performance. Note that some older parts will never have enough
8152 * bandwidth due to being older generation PCIe parts. We clamp these
8153 * parts to ensure no warning is displayed if it can't be fixed.
8154 */
8155 switch (hw->mac.type) {
8156 case ixgbe_mac_82598EB:
8157 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8158 break;
8159 default:
8160 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8161 break;
0c254d86 8162 }
e027d1ae 8163 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8164
6a2aae5a
JK		 8165 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8166 if (err)
8167 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8168 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8169 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8170 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8171 part_str);
8172 else
8173 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8174 hw->mac.type, hw->phy.type, part_str);
8175
8176 e_dev_info("%pM\n", netdev->dev_addr);
8177
9a799d71 8178 /* reset the hardware with the new settings */
794caeb2 8179 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8180 if (err == IXGBE_ERR_EEPROM_VERSION) {
8181 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8182 e_dev_warn("This device is a pre-production adapter/LOM. "
8183 "Please be aware there may be issues associated "
8184 "with your hardware. If you are experiencing "
8185 "problems please contact your Intel or hardware "
8186 "representative who provided you with this "
8187 "hardware.\n");
794caeb2 8188 }
9a799d71
AK		 8189 strcpy(netdev->name, "eth%d");
8190 err = register_netdev(netdev);
8191 if (err)
8192 goto err_register;
8193
ec74a471
ET		 8194 /* power down the optics for 82599 SFP+ fiber */
8195 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8196 hw->mac.ops.disable_tx_laser(hw);
8197
54386467
JB		 8198 /* carrier off reporting is important to ethtool even BEFORE open */
8199 netif_carrier_off(netdev);
8200
5dd2d332 8201#ifdef CONFIG_IXGBE_DCA
652f093f 8202 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8203 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8204 ixgbe_setup_dca(adapter);
8205 }
8206#endif
1cdd1ec8 8207 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8208 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8209 for (i = 0; i < adapter->num_vfs; i++)
8210 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8211 }
8212
2466dd9c
JK		 8213 /* firmware requires driver version to be 0xFFFFFFFF
8214 * since os does not support feature
8215 */
9612de92 8216 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8217 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8218 0xFF);
9612de92 8219
0365e6e4
PW		 8220 /* add san mac addr to netdev */
8221 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8222
ea81875a 8223 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8224 cards_found++;
3ca8bc6d 8225
1210982b 8226#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8227 if (ixgbe_sysfs_init(adapter))
8228 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8229#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8230
00949167 8231 ixgbe_dbg_adapter_init(adapter);
00949167 8232
0b2679d6
DS		 8233 /* Need link setup for MNG FW, else wait for IXGBE_UP */
8234 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
8235 hw->mac.ops.setup_link(hw,
8236 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8237 true);
8238
9a799d71
AK		 8239 return 0;
8240
8241err_register:
5eba3699 8242 ixgbe_release_hw_control(adapter);
7a921c93 8243 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8244err_sw_init:
99d74487 8245 ixgbe_disable_sriov(adapter);
7086400d 8246 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8247 iounmap(adapter->io_addr);
9a799d71
AK		 8248err_ioremap:
8249 free_netdev(netdev);
8250err_alloc_etherdev:
e8e9f696
JP		 8251 pci_release_selected_regions(pdev,
8252 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8253err_pci_reg:
8254err_dma:
8255 pci_disable_device(pdev);
8256 return err;
8257}
8258
8259/**
8260 * ixgbe_remove - Device Removal Routine
8261 * @pdev: PCI device information struct
8262 *
8263 * ixgbe_remove is called by the PCI subsystem to alert the driver
8264 * that it should release a PCI device. The could be caused by a
8265 * Hot-Plug event, or because the driver is going to be removed from
8266 * memory.
8267 **/
9f9a12f8 8268static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8269{
c60fbb00
AD		 8270 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8271 struct net_device *netdev = adapter->netdev;
9a799d71 8272
00949167 8273 ixgbe_dbg_adapter_exit(adapter);
00949167 8274
09f40aed 8275 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8276 cancel_work_sync(&adapter->service_task);
9a799d71 8277
3a6a4eda 8278
5dd2d332 8279#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8281 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8282 dca_remove_requester(&pdev->dev);
8283 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8284 }
8285
8286#endif
1210982b 8287#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8288 ixgbe_sysfs_exit(adapter);
1210982b 8289#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8290
0365e6e4
PW		 8291 /* remove the added san mac */
8292 ixgbe_del_sanmac_netdev(netdev);
8293
c4900be0
DS		 8294 if (netdev->reg_state == NETREG_REGISTERED)
8295 unregister_netdev(netdev);
9a799d71 8296
da36b647
GR		 8297#ifdef CONFIG_PCI_IOV
8298 /*
8299 * Only disable SR-IOV on unload if the user specified the now
8300 * deprecated max_vfs module parameter.
8301 */
8302 if (max_vfs)
8303 ixgbe_disable_sriov(adapter);
8304#endif
7a921c93 8305 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8306
021230d4 8307 ixgbe_release_hw_control(adapter);
9a799d71 8308
2b1588c3
AD		 8309#ifdef CONFIG_DCB
8310 kfree(adapter->ixgbe_ieee_pfc);
8311 kfree(adapter->ixgbe_ieee_ets);
8312
8313#endif
2a1a091c 8314 iounmap(adapter->io_addr);
9ce77666 8315 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8316 IORESOURCE_MEM));
9a799d71 8317
849c4542 8318 e_dev_info("complete\n");
021230d4 8319
9a799d71
AK		 8320 free_netdev(netdev);
8321
19d5afd4 8322 pci_disable_pcie_error_reporting(pdev);
6fabd715 8323
9a799d71
AK		 8324 pci_disable_device(pdev);
8325}
8326
8327/**
8328 * ixgbe_io_error_detected - called when PCI error is detected
8329 * @pdev: Pointer to PCI device
8330 * @state: The current pci connection state
8331 *
8332 * This function is called after a PCI bus error affecting
8333 * this device has been detected.
8334 */
8335static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8336 pci_channel_state_t state)
9a799d71 8337{
c60fbb00
AD		 8338 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8339 struct net_device *netdev = adapter->netdev;
9a799d71 8340
83c61fa9
GR		 8341#ifdef CONFIG_PCI_IOV
8342 struct pci_dev *bdev, *vfdev;
8343 u32 dw0, dw1, dw2, dw3;
8344 int vf, pos;
8345 u16 req_id, pf_func;
8346
8347 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8348 adapter->num_vfs == 0)
8349 goto skip_bad_vf_detection;
8350
8351 bdev = pdev->bus->self;
62f87c0e 8352 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8353 bdev = bdev->bus->self;
8354
8355 if (!bdev)
8356 goto skip_bad_vf_detection;
8357
8358 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8359 if (!pos)
8360 goto skip_bad_vf_detection;
8361
8362 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8363 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8364 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8365 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8366
8367 req_id = dw1 >> 16;
8368 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8369 if (!(req_id & 0x0080))
8370 goto skip_bad_vf_detection;
8371
8372 pf_func = req_id & 0x01;
8373 if ((pf_func & 1) == (pdev->devfn & 1)) {
8374 unsigned int device_id;
8375
8376 vf = (req_id & 0x7F) >> 1;
8377 e_dev_err("VF %d has caused a PCIe error\n", vf);
8378 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8379 "%8.8x\tdw3: %8.8x\n",
8380 dw0, dw1, dw2, dw3);
8381 switch (adapter->hw.mac.type) {
8382 case ixgbe_mac_82599EB:
8383 device_id = IXGBE_82599_VF_DEVICE_ID;
8384 break;
8385 case ixgbe_mac_X540:
8386 device_id = IXGBE_X540_VF_DEVICE_ID;
8387 break;
8388 default:
8389 device_id = 0;
8390 break;
8391 }
8392
8393 /* Find the pci device of the offending VF */
36e90319 8394 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8395 while (vfdev) {
8396 if (vfdev->devfn == (req_id & 0xFF))
8397 break;
36e90319 8398 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8399 device_id, vfdev);
8400 }
8401 /*
8402 * There's a slim chance the VF could have been hot plugged,
8403 * so if it is no longer present we don't need to issue the
8404 * VFLR. Just clean up the AER in that case.
8405 */
8406 if (vfdev) {
8407 e_dev_err("Issuing VFLR to VF %d\n", vf);
8408 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8409 /* Free device reference count */
8410 pci_dev_put(vfdev);
83c61fa9
GR		 8411 }
8412
8413 pci_cleanup_aer_uncorrect_error_status(pdev);
8414 }
8415
8416 /*
8417 * Even though the error may have occurred on the other port
8418 * we still need to increment the vf error reference count for
8419 * both ports because the I/O resume function will be called
8420 * for both of them.
8421 */
8422 adapter->vferr_refcount++;
8423
8424 return PCI_ERS_RESULT_RECOVERED;
8425
8426skip_bad_vf_detection:
8427#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8428 netif_device_detach(netdev);
8429
3044b8d1
BL		 8430 if (state == pci_channel_io_perm_failure)
8431 return PCI_ERS_RESULT_DISCONNECT;
8432
9a799d71
AK		 8433 if (netif_running(netdev))
8434 ixgbe_down(adapter);
8435 pci_disable_device(pdev);
8436
b4617240 8437 /* Request a slot reset. */
9a799d71
AK		 8438 return PCI_ERS_RESULT_NEED_RESET;
8439}
8440
8441/**
8442 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8443 * @pdev: Pointer to PCI device
8444 *
8445 * Restart the card from scratch, as if from a cold-boot.
8446 */
8447static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8448{
c60fbb00 8449 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8450 pci_ers_result_t result;
8451 int err;
9a799d71 8452
9ce77666 8453 if (pci_enable_device_mem(pdev)) {
396e799c 8454 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8455 result = PCI_ERS_RESULT_DISCONNECT;
8456 } else {
0391bbe3 8457 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8458 pci_set_master(pdev);
8459 pci_restore_state(pdev);
c0e1f68b 8460 pci_save_state(pdev);
9a799d71 8461
dd4d8ca6 8462 pci_wake_from_d3(pdev, false);
9a799d71 8463
6fabd715 8464 ixgbe_reset(adapter);
88512539 8465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8466 result = PCI_ERS_RESULT_RECOVERED;
8467 }
8468
8469 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8470 if (err) {
849c4542
ET		 8471 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8472 "failed 0x%0x\n", err);
6fabd715
PWJ		 8473 /* non-fatal, continue */
8474 }
9a799d71 8475
6fabd715 8476 return result;
9a799d71
AK		 8477}
8478
8479/**
8480 * ixgbe_io_resume - called when traffic can start flowing again.
8481 * @pdev: Pointer to PCI device
8482 *
8483 * This callback is called when the error recovery driver tells us that
8484 * its OK to resume normal operation.
8485 */
8486static void ixgbe_io_resume(struct pci_dev *pdev)
8487{
c60fbb00
AD		 8488 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8489 struct net_device *netdev = adapter->netdev;
9a799d71 8490
83c61fa9
GR		 8491#ifdef CONFIG_PCI_IOV
8492 if (adapter->vferr_refcount) {
8493 e_info(drv, "Resuming after VF err\n");
8494 adapter->vferr_refcount--;
8495 return;
8496 }
8497
8498#endif
c7ccde0f
AD		 8499 if (netif_running(netdev))
8500 ixgbe_up(adapter);
9a799d71
AK		 8501
8502 netif_device_attach(netdev);
9a799d71
AK		 8503}
8504
3646f0e5 8505static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8506 .error_detected = ixgbe_io_error_detected,
8507 .slot_reset = ixgbe_io_slot_reset,
8508 .resume = ixgbe_io_resume,
8509};
8510
8511static struct pci_driver ixgbe_driver = {
8512 .name = ixgbe_driver_name,
8513 .id_table = ixgbe_pci_tbl,
8514 .probe = ixgbe_probe,
9f9a12f8 8515 .remove = ixgbe_remove,
9a799d71
AK		 8516#ifdef CONFIG_PM
8517 .suspend = ixgbe_suspend,
8518 .resume = ixgbe_resume,
8519#endif
8520 .shutdown = ixgbe_shutdown,
da36b647 8521 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8522 .err_handler = &ixgbe_err_handler
8523};
8524
8525/**
8526 * ixgbe_init_module - Driver Registration Routine
8527 *
8528 * ixgbe_init_module is the first routine called when the driver is
8529 * loaded. All it does is register with the PCI subsystem.
8530 **/
8531static int __init ixgbe_init_module(void)
8532{
8533 int ret;
c7689578 8534 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8535 pr_info("%s\n", ixgbe_copyright);
9a799d71 8536
00949167 8537 ixgbe_dbg_init();
00949167 8538
f01fc1a8
JK		 8539 ret = pci_register_driver(&ixgbe_driver);
8540 if (ret) {
f01fc1a8 8541 ixgbe_dbg_exit();
f01fc1a8
JK		 8542 return ret;
8543 }
8544
5dd2d332 8545#ifdef CONFIG_IXGBE_DCA
bd0362dd 8546 dca_register_notify(&dca_notifier);
bd0362dd 8547#endif
5dd2d332 8548
f01fc1a8 8549 return 0;
9a799d71 8550}
b4617240 8551
9a799d71
AK		 8552module_init(ixgbe_init_module);
8553
8554/**
8555 * ixgbe_exit_module - Driver Exit Cleanup Routine
8556 *
8557 * ixgbe_exit_module is called just before the driver is removed
8558 * from memory.
8559 **/
8560static void __exit ixgbe_exit_module(void)
8561{
5dd2d332 8562#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8563 dca_unregister_notify(&dca_notifier);
8564#endif
9a799d71 8565 pci_unregister_driver(&ixgbe_driver);
00949167 8566
00949167 8567 ixgbe_dbg_exit();
00949167 8568
1a51502b 8569 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8570}
bd0362dd 8571
5dd2d332 8572#ifdef CONFIG_IXGBE_DCA
bd0362dd 8573static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8574 void *p)
bd0362dd
JC		 8575{
8576 int ret_val;
8577
8578 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8579 __ixgbe_notify_dca);
bd0362dd
JC		 8580
8581 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8582}
b453368d 8583
5dd2d332 8584#endif /* CONFIG_IXGBE_DCA */
849c4542 8585
9a799d71
AK		 8586module_exit(ixgbe_exit_module);
8587
8588/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)