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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
434c5e39 | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGBE_H_ | |
30 | #define _IXGBE_H_ | |
31 | ||
f62bbb5e | 32 | #include <linux/bitops.h> |
9a799d71 AK |
33 | #include <linux/types.h> |
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
b25ebfd2 | 36 | #include <linux/cpumask.h> |
6fabd715 | 37 | #include <linux/aer.h> |
f62bbb5e | 38 | #include <linux/if_vlan.h> |
6cb562d6 | 39 | #include <linux/jiffies.h> |
9a799d71 | 40 | |
3a6a4eda JK |
41 | #include <linux/clocksource.h> |
42 | #include <linux/net_tstamp.h> | |
43 | #include <linux/ptp_clock_kernel.h> | |
3a6a4eda | 44 | |
9a799d71 AK |
45 | #include "ixgbe_type.h" |
46 | #include "ixgbe_common.h" | |
2f90b865 | 47 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
48 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
49 | #define IXGBE_FCOE | |
50 | #include "ixgbe_fcoe.h" | |
51 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 52 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
53 | #include <linux/dca.h> |
54 | #endif | |
9a799d71 | 55 | |
076bb0c8 | 56 | #include <net/busy_poll.h> |
5a85e737 | 57 | |
e0d1095a | 58 | #ifdef CONFIG_NET_RX_BUSY_POLL |
b4640030 | 59 | #define BP_EXTENDED_STATS |
7e15b90f | 60 | #endif |
849c4542 ET |
61 | /* common prefix used by pr_<> macros */ |
62 | #undef pr_fmt | |
63 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
64 | |
65 | /* TX/RX descriptor defines */ | |
6bacb300 | 66 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 67 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
68 | #define IXGBE_MAX_TXD 4096 |
69 | #define IXGBE_MIN_TXD 64 | |
70 | ||
fb44519d | 71 | #if (PAGE_SIZE < 8192) |
6bacb300 | 72 | #define IXGBE_DEFAULT_RXD 512 |
fb44519d AB |
73 | #else |
74 | #define IXGBE_DEFAULT_RXD 128 | |
75 | #endif | |
9a799d71 AK |
76 | #define IXGBE_MAX_RXD 4096 |
77 | #define IXGBE_MIN_RXD 64 | |
78 | ||
9a799d71 | 79 | /* flow control */ |
2b9ade93 | 80 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 81 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 82 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 83 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 84 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
85 | #define IXGBE_MIN_FCPAUSE 0 |
86 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
87 | ||
88 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 89 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
90 | #define IXGBE_RXBUFFER_2K 2048 |
91 | #define IXGBE_RXBUFFER_3K 3072 | |
92 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 93 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 94 | |
13958070 | 95 | /* |
252562c2 AD |
96 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
97 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
98 | * this adds up to 448 bytes of extra data. | |
99 | * | |
100 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
101 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 102 | */ |
252562c2 | 103 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 | 104 | |
9a799d71 AK |
105 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
106 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
107 | ||
472148c3 AD |
108 | enum ixgbe_tx_flags { |
109 | /* cmd_type flags */ | |
110 | IXGBE_TX_FLAGS_HW_VLAN = 0x01, | |
111 | IXGBE_TX_FLAGS_TSO = 0x02, | |
112 | IXGBE_TX_FLAGS_TSTAMP = 0x04, | |
113 | ||
114 | /* olinfo flags */ | |
115 | IXGBE_TX_FLAGS_CC = 0x08, | |
116 | IXGBE_TX_FLAGS_IPV4 = 0x10, | |
117 | IXGBE_TX_FLAGS_CSUM = 0x20, | |
118 | ||
119 | /* software defined flags */ | |
120 | IXGBE_TX_FLAGS_SW_VLAN = 0x40, | |
121 | IXGBE_TX_FLAGS_FCOE = 0x80, | |
122 | }; | |
123 | ||
124 | /* VLAN info */ | |
9a799d71 | 125 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
126 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
127 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
128 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
129 | ||
7f870475 GR |
130 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
131 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
132 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
133 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 134 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 135 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
136 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
137 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
138 | |
139 | struct vf_data_storage { | |
140 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
141 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
142 | u16 num_vf_mc_hashes; | |
143 | u16 default_vf_vlan_id; | |
144 | u16 vlans_enabled; | |
7f870475 | 145 | bool clear_to_send; |
7f01648a | 146 | bool pf_set_mac; |
7f01648a GR |
147 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
148 | u16 pf_qos; | |
ff4ab206 | 149 | u16 tx_rate; |
de4c7f65 GR |
150 | u16 vlan_count; |
151 | u8 spoofchk_enabled; | |
374c65d6 | 152 | unsigned int vf_api; |
7f870475 GR |
153 | }; |
154 | ||
a1cbb15c GR |
155 | struct vf_macvlans { |
156 | struct list_head l; | |
157 | int vf; | |
158 | int rar_entry; | |
159 | bool free; | |
160 | bool is_macvlan; | |
161 | u8 vf_macvlan[ETH_ALEN]; | |
162 | }; | |
163 | ||
a535c30e AD |
164 | #define IXGBE_MAX_TXD_PWR 14 |
165 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
166 | ||
167 | /* Tx Descriptors needed, worst case */ | |
168 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
990a3158 | 169 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
a535c30e | 170 | |
9a799d71 AK |
171 | /* wrapper around a pointer to a socket buffer, |
172 | * so a DMA handle can be stored along with the buffer */ | |
173 | struct ixgbe_tx_buffer { | |
d3d00239 | 174 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 175 | unsigned long time_stamp; |
fd0db0ed AD |
176 | struct sk_buff *skb; |
177 | unsigned int bytecount; | |
178 | unsigned short gso_segs; | |
244e27ad | 179 | __be16 protocol; |
729739b7 AD |
180 | DEFINE_DMA_UNMAP_ADDR(dma); |
181 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 182 | u32 tx_flags; |
9a799d71 AK |
183 | }; |
184 | ||
185 | struct ixgbe_rx_buffer { | |
186 | struct sk_buff *skb; | |
187 | dma_addr_t dma; | |
188 | struct page *page; | |
762f4c57 | 189 | unsigned int page_offset; |
9a799d71 AK |
190 | }; |
191 | ||
192 | struct ixgbe_queue_stats { | |
193 | u64 packets; | |
194 | u64 bytes; | |
b4640030 | 195 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
196 | u64 yields; |
197 | u64 misses; | |
198 | u64 cleaned; | |
b4640030 | 199 | #endif /* BP_EXTENDED_STATS */ |
9a799d71 AK |
200 | }; |
201 | ||
5b7da515 AD |
202 | struct ixgbe_tx_queue_stats { |
203 | u64 restart_queue; | |
204 | u64 tx_busy; | |
c84d324c | 205 | u64 tx_done_old; |
5b7da515 AD |
206 | }; |
207 | ||
208 | struct ixgbe_rx_queue_stats { | |
209 | u64 rsc_count; | |
210 | u64 rsc_flush; | |
211 | u64 non_eop_descs; | |
212 | u64 alloc_rx_page_failed; | |
213 | u64 alloc_rx_buff_failed; | |
8a0da21b | 214 | u64 csum_err; |
5b7da515 AD |
215 | }; |
216 | ||
f800326d | 217 | enum ixgbe_ring_state_t { |
7d637bcc | 218 | __IXGBE_TX_FDIR_INIT_DONE, |
fd786b7b | 219 | __IXGBE_TX_XPS_INIT_DONE, |
7d637bcc | 220 | __IXGBE_TX_DETECT_HANG, |
c84d324c | 221 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 222 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 223 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
57efd44c | 224 | __IXGBE_RX_FCOE, |
7d637bcc AD |
225 | }; |
226 | ||
2a47fa45 JF |
227 | struct ixgbe_fwd_adapter { |
228 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
229 | struct net_device *netdev; | |
230 | struct ixgbe_adapter *real_adapter; | |
231 | unsigned int tx_base_queue; | |
232 | unsigned int rx_base_queue; | |
233 | int pool; | |
234 | }; | |
235 | ||
7d637bcc AD |
236 | #define check_for_tx_hang(ring) \ |
237 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
238 | #define set_check_for_tx_hang(ring) \ | |
239 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
240 | #define clear_check_for_tx_hang(ring) \ | |
241 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
242 | #define ring_is_rsc_enabled(ring) \ | |
243 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
244 | #define set_ring_rsc_enabled(ring) \ | |
245 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
246 | #define clear_ring_rsc_enabled(ring) \ | |
247 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 248 | struct ixgbe_ring { |
efe3d3c8 | 249 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
250 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
251 | struct net_device *netdev; /* netdev ring belongs to */ | |
252 | struct device *dev; /* device for DMA mapping */ | |
2a47fa45 | 253 | struct ixgbe_fwd_adapter *l2_accel_priv; |
9a799d71 | 254 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
255 | union { |
256 | struct ixgbe_tx_buffer *tx_buffer_info; | |
257 | struct ixgbe_rx_buffer *rx_buffer_info; | |
258 | }; | |
6cb562d6 | 259 | unsigned long last_rx_timestamp; |
7d637bcc | 260 | unsigned long state; |
bd198058 | 261 | u8 __iomem *tail; |
d3ee4294 AD |
262 | dma_addr_t dma; /* phys. address of descriptor ring */ |
263 | unsigned int size; /* length in bytes */ | |
bd198058 | 264 | |
ae540af1 | 265 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
266 | |
267 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
268 | u8 reg_idx; /* holds the special value that gets |
269 | * the hardware register offset | |
270 | * associated with this ring, which is | |
271 | * different for DCB and RSS modes | |
272 | */ | |
d3ee4294 AD |
273 | u16 next_to_use; |
274 | u16 next_to_clean; | |
275 | ||
f800326d | 276 | union { |
d3ee4294 | 277 | u16 next_to_alloc; |
f800326d AD |
278 | struct { |
279 | u8 atr_sample_rate; | |
280 | u8 atr_count; | |
281 | }; | |
f800326d | 282 | }; |
9a799d71 | 283 | |
bd198058 | 284 | u8 dcb_tc; |
9a799d71 | 285 | struct ixgbe_queue_stats stats; |
de1036b1 | 286 | struct u64_stats_sync syncp; |
5b7da515 AD |
287 | union { |
288 | struct ixgbe_tx_queue_stats tx_stats; | |
289 | struct ixgbe_rx_queue_stats rx_stats; | |
290 | }; | |
7ca3bc58 | 291 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 292 | |
c7e4358a SN |
293 | enum ixgbe_ring_f_enum { |
294 | RING_F_NONE = 0, | |
7f870475 | 295 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 296 | RING_F_RSS, |
c4cf55e5 | 297 | RING_F_FDIR, |
0331a832 YZ |
298 | #ifdef IXGBE_FCOE |
299 | RING_F_FCOE, | |
300 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
301 | |
302 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
303 | }; | |
304 | ||
021230d4 | 305 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 306 | #define IXGBE_MAX_VMDQ_INDICES 64 |
d3cb9869 | 307 | #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ |
0331a832 | 308 | #define IXGBE_MAX_FCOE_INDICES 8 |
d3cb9869 AD |
309 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) |
310 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
2a47fa45 JF |
311 | #define IXGBE_MAX_L2A_QUEUES 4 |
312 | #define IXGBE_MAX_L2A_QUEUES 4 | |
313 | #define IXGBE_BAD_L2A_QUEUE 3 | |
314 | #define IXGBE_MAX_MACVLANS 31 | |
315 | #define IXGBE_MAX_DCBMACVLANS 8 | |
316 | ||
021230d4 | 317 | struct ixgbe_ring_feature { |
c087663e AD |
318 | u16 limit; /* upper limit on feature indices */ |
319 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
320 | u16 mask; /* Mask used for feature to ring mapping */ |
321 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 322 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 323 | |
73079ea0 AD |
324 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
325 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
326 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
327 | ||
f800326d AD |
328 | /* |
329 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
330 | * this is twice the size of a half page we need to double the page order | |
331 | * for FCoE enabled Rx queues. | |
332 | */ | |
09816fbe | 333 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 334 | { |
09816fbe AD |
335 | #ifdef IXGBE_FCOE |
336 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
337 | return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : | |
338 | IXGBE_RXBUFFER_3K; | |
339 | #endif | |
340 | return IXGBE_RXBUFFER_2K; | |
f800326d | 341 | } |
09816fbe AD |
342 | |
343 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
344 | { | |
345 | #ifdef IXGBE_FCOE | |
346 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
347 | return (PAGE_SIZE < 8192) ? 1 : 0; | |
f800326d | 348 | #endif |
09816fbe AD |
349 | return 0; |
350 | } | |
f800326d | 351 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 352 | |
08c8833b | 353 | struct ixgbe_ring_container { |
efe3d3c8 | 354 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
355 | unsigned int total_bytes; /* total bytes processed this int */ |
356 | unsigned int total_packets; /* total packets processed this int */ | |
357 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
358 | u8 count; /* total number of rings in vector */ |
359 | u8 itr; /* current ITR setting for ring */ | |
360 | }; | |
021230d4 | 361 | |
a557928e AD |
362 | /* iterator for handling rings in ring container */ |
363 | #define ixgbe_for_each_ring(pos, head) \ | |
364 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
365 | ||
2f90b865 AD |
366 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
367 | ? 8 : 1) | |
368 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS | |
369 | ||
49c7ffbe | 370 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
371 | * but we only use one per queue-specific vector. |
372 | */ | |
373 | struct ixgbe_q_vector { | |
374 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
375 | #ifdef CONFIG_IXGBE_DCA |
376 | int cpu; /* CPU for DCA */ | |
377 | #endif | |
d5bf4f67 ET |
378 | u16 v_idx; /* index of q_vector within array, also used for |
379 | * finding the bit in EICR and friends that | |
380 | * represents the vector for this ring */ | |
381 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 382 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
383 | |
384 | struct napi_struct napi; | |
de88eeeb AD |
385 | cpumask_t affinity_mask; |
386 | int numa_node; | |
387 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 388 | char name[IFNAMSIZ + 9]; |
de88eeeb | 389 | |
e0d1095a | 390 | #ifdef CONFIG_NET_RX_BUSY_POLL |
5a85e737 ET |
391 | unsigned int state; |
392 | #define IXGBE_QV_STATE_IDLE 0 | |
27d9ce4f JK |
393 | #define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */ |
394 | #define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */ | |
395 | #define IXGBE_QV_STATE_DISABLED 4 /* QV is disabled */ | |
396 | #define IXGBE_QV_OWNED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL) | |
397 | #define IXGBE_QV_LOCKED (IXGBE_QV_OWNED | IXGBE_QV_STATE_DISABLED) | |
398 | #define IXGBE_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ | |
399 | #define IXGBE_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ | |
5a85e737 ET |
400 | #define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD) |
401 | #define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD) | |
402 | spinlock_t lock; | |
e0d1095a | 403 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 404 | |
de88eeeb AD |
405 | /* for dynamic allocation of rings associated with this q_vector */ |
406 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 407 | }; |
e0d1095a | 408 | #ifdef CONFIG_NET_RX_BUSY_POLL |
5a85e737 ET |
409 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
410 | { | |
411 | ||
412 | spin_lock_init(&q_vector->lock); | |
413 | q_vector->state = IXGBE_QV_STATE_IDLE; | |
414 | } | |
415 | ||
416 | /* called from the device poll routine to get ownership of a q_vector */ | |
417 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
418 | { | |
419 | int rc = true; | |
27d9ce4f | 420 | spin_lock_bh(&q_vector->lock); |
5a85e737 ET |
421 | if (q_vector->state & IXGBE_QV_LOCKED) { |
422 | WARN_ON(q_vector->state & IXGBE_QV_STATE_NAPI); | |
423 | q_vector->state |= IXGBE_QV_STATE_NAPI_YIELD; | |
424 | rc = false; | |
b4640030 | 425 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
426 | q_vector->tx.ring->stats.yields++; |
427 | #endif | |
78d820e8 | 428 | } else { |
5a85e737 ET |
429 | /* we don't care if someone yielded */ |
430 | q_vector->state = IXGBE_QV_STATE_NAPI; | |
78d820e8 | 431 | } |
27d9ce4f | 432 | spin_unlock_bh(&q_vector->lock); |
5a85e737 ET |
433 | return rc; |
434 | } | |
435 | ||
436 | /* returns true is someone tried to get the qv while napi had it */ | |
437 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
438 | { | |
439 | int rc = false; | |
27d9ce4f | 440 | spin_lock_bh(&q_vector->lock); |
5a85e737 ET |
441 | WARN_ON(q_vector->state & (IXGBE_QV_STATE_POLL | |
442 | IXGBE_QV_STATE_NAPI_YIELD)); | |
443 | ||
444 | if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) | |
445 | rc = true; | |
27d9ce4f JK |
446 | /* will reset state to idle, unless QV is disabled */ |
447 | q_vector->state &= IXGBE_QV_STATE_DISABLED; | |
448 | spin_unlock_bh(&q_vector->lock); | |
5a85e737 ET |
449 | return rc; |
450 | } | |
451 | ||
452 | /* called from ixgbe_low_latency_poll() */ | |
453 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
454 | { | |
455 | int rc = true; | |
456 | spin_lock_bh(&q_vector->lock); | |
457 | if ((q_vector->state & IXGBE_QV_LOCKED)) { | |
458 | q_vector->state |= IXGBE_QV_STATE_POLL_YIELD; | |
459 | rc = false; | |
b4640030 | 460 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
461 | q_vector->rx.ring->stats.yields++; |
462 | #endif | |
78d820e8 | 463 | } else { |
5a85e737 ET |
464 | /* preserve yield marks */ |
465 | q_vector->state |= IXGBE_QV_STATE_POLL; | |
78d820e8 | 466 | } |
5a85e737 ET |
467 | spin_unlock_bh(&q_vector->lock); |
468 | return rc; | |
469 | } | |
470 | ||
471 | /* returns true if someone tried to get the qv while it was locked */ | |
472 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
473 | { | |
474 | int rc = false; | |
475 | spin_lock_bh(&q_vector->lock); | |
476 | WARN_ON(q_vector->state & (IXGBE_QV_STATE_NAPI)); | |
477 | ||
478 | if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) | |
479 | rc = true; | |
27d9ce4f JK |
480 | /* will reset state to idle, unless QV is disabled */ |
481 | q_vector->state &= IXGBE_QV_STATE_DISABLED; | |
5a85e737 ET |
482 | spin_unlock_bh(&q_vector->lock); |
483 | return rc; | |
484 | } | |
485 | ||
486 | /* true if a socket is polling, even if it did not get the lock */ | |
b4640030 | 487 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 | 488 | { |
27d9ce4f | 489 | WARN_ON(!(q_vector->state & IXGBE_QV_OWNED)); |
5a85e737 ET |
490 | return q_vector->state & IXGBE_QV_USER_PEND; |
491 | } | |
27d9ce4f JK |
492 | |
493 | /* false if QV is currently owned */ | |
494 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
495 | { | |
496 | int rc = true; | |
497 | spin_lock_bh(&q_vector->lock); | |
498 | if (q_vector->state & IXGBE_QV_OWNED) | |
499 | rc = false; | |
500 | q_vector->state |= IXGBE_QV_STATE_DISABLED; | |
501 | spin_unlock_bh(&q_vector->lock); | |
502 | ||
503 | return rc; | |
504 | } | |
505 | ||
e0d1095a | 506 | #else /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 ET |
507 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
508 | { | |
509 | } | |
510 | ||
511 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
512 | { | |
513 | return true; | |
514 | } | |
515 | ||
516 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
517 | { | |
518 | return false; | |
519 | } | |
520 | ||
521 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
522 | { | |
523 | return false; | |
524 | } | |
525 | ||
526 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
527 | { | |
528 | return false; | |
529 | } | |
530 | ||
b4640030 | 531 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 ET |
532 | { |
533 | return false; | |
534 | } | |
27d9ce4f JK |
535 | |
536 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
537 | { | |
538 | return true; | |
539 | } | |
540 | ||
e0d1095a | 541 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 542 | |
3ca8bc6d DS |
543 | #ifdef CONFIG_IXGBE_HWMON |
544 | ||
545 | #define IXGBE_HWMON_TYPE_LOC 0 | |
546 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
547 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
548 | #define IXGBE_HWMON_TYPE_MAX 3 | |
549 | ||
550 | struct hwmon_attr { | |
551 | struct device_attribute dev_attr; | |
552 | struct ixgbe_hw *hw; | |
553 | struct ixgbe_thermal_diode_data *sensor; | |
554 | char name[12]; | |
555 | }; | |
556 | ||
557 | struct hwmon_buff { | |
03b77d81 GR |
558 | struct attribute_group group; |
559 | const struct attribute_group *groups[2]; | |
560 | struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; | |
561 | struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; | |
3ca8bc6d DS |
562 | unsigned int n_hwmon; |
563 | }; | |
564 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 565 | |
d5bf4f67 ET |
566 | /* |
567 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
568 | * with the first 3 bits reserved 0 | |
9a799d71 | 569 | */ |
d5bf4f67 ET |
570 | #define IXGBE_MIN_RSC_ITR 24 |
571 | #define IXGBE_100K_ITR 40 | |
572 | #define IXGBE_20K_ITR 200 | |
573 | #define IXGBE_10K_ITR 400 | |
574 | #define IXGBE_8K_ITR 500 | |
9a799d71 | 575 | |
f56e0cb1 AD |
576 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
577 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
578 | const u32 stat_err_bits) | |
579 | { | |
580 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
581 | } | |
582 | ||
7d4987de AD |
583 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
584 | { | |
585 | u16 ntc = ring->next_to_clean; | |
586 | u16 ntu = ring->next_to_use; | |
587 | ||
588 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
589 | } | |
9a799d71 | 590 | |
84227bcd MR |
591 | static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value) |
592 | { | |
593 | writel(value, ring->tail); | |
594 | } | |
595 | ||
e4f74028 | 596 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 597 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 598 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 599 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 600 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 601 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 602 | |
c88887e0 | 603 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
604 | #ifdef IXGBE_FCOE |
605 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
606 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
607 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 608 | |
021230d4 AV |
609 | #define OTHER_VECTOR 1 |
610 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
611 | ||
e8e26350 | 612 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 613 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 614 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 615 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 616 | |
49c7ffbe | 617 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 618 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 619 | |
8f15486d | 620 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
621 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
622 | ||
46646e61 AD |
623 | /* default to trying for four seconds */ |
624 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
625 | ||
9a799d71 AK |
626 | /* board specific private data structure */ |
627 | struct ixgbe_adapter { | |
46646e61 AD |
628 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
629 | /* OS defined structs */ | |
630 | struct net_device *netdev; | |
631 | struct pci_dev *pdev; | |
632 | ||
e606bfe7 AD |
633 | unsigned long state; |
634 | ||
635 | /* Some features need tri-state capability, | |
636 | * thus the additional *_CAPABLE flags. | |
637 | */ | |
638 | u32 flags; | |
a16a0d2f AD |
639 | #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0) |
640 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) | |
641 | #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2) | |
642 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) | |
643 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) | |
644 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) | |
645 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) | |
646 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) | |
647 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) | |
648 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) | |
649 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) | |
650 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) | |
651 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) | |
652 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) | |
653 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) | |
654 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) | |
655 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) | |
656 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) | |
657 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) | |
658 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) | |
659 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) | |
660 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) | |
661 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) | |
662 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) | |
e606bfe7 AD |
663 | |
664 | u32 flags2; | |
a16a0d2f | 665 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) |
e606bfe7 AD |
666 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) |
667 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 668 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
669 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
670 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 671 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 672 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
ef6afc0c AD |
673 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) |
674 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) | |
8fecf67c JK |
675 | #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) |
676 | #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11) | |
d033d526 | 677 | |
46646e61 AD |
678 | /* Tx fast path data */ |
679 | int num_tx_queues; | |
680 | u16 tx_itr_setting; | |
bd198058 AD |
681 | u16 tx_work_limit; |
682 | ||
46646e61 AD |
683 | /* Rx fast path data */ |
684 | int num_rx_queues; | |
685 | u16 rx_itr_setting; | |
686 | ||
9a799d71 | 687 | /* TX */ |
4a0b9ca0 | 688 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 689 | |
7ca3bc58 JB |
690 | u64 restart_queue; |
691 | u64 lsc_int; | |
46646e61 | 692 | u32 tx_timeout_count; |
7ca3bc58 | 693 | |
9a799d71 | 694 | /* RX */ |
46646e61 | 695 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
696 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
697 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 698 | u64 hw_csum_rx_error; |
e8e26350 | 699 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
700 | u64 rsc_total_count; |
701 | u64 rsc_total_flush; | |
9a799d71 | 702 | u64 non_eop_descs; |
9a799d71 AK |
703 | u32 alloc_rx_page_failed; |
704 | u32 alloc_rx_buff_failed; | |
705 | ||
49c7ffbe | 706 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 707 | |
46646e61 AD |
708 | /* DCB parameters */ |
709 | struct ieee_pfc *ixgbe_ieee_pfc; | |
710 | struct ieee_ets *ixgbe_ieee_ets; | |
711 | struct ixgbe_dcb_config dcb_cfg; | |
712 | struct ixgbe_dcb_config temp_dcb_cfg; | |
713 | u8 dcb_set_bitmap; | |
714 | u8 dcbx_cap; | |
715 | enum ixgbe_fc_mode last_lfc_mode; | |
716 | ||
49c7ffbe AD |
717 | int num_q_vectors; /* current number of q_vectors for device */ |
718 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
719 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
720 | struct msix_entry *msix_entries; | |
9a799d71 | 721 | |
da4dd0f7 PWJ |
722 | u32 test_icr; |
723 | struct ixgbe_ring test_tx_ring; | |
724 | struct ixgbe_ring test_rx_ring; | |
725 | ||
9a799d71 AK |
726 | /* structs defined in ixgbe_hw.h */ |
727 | struct ixgbe_hw hw; | |
728 | u16 msg_enable; | |
729 | struct ixgbe_hw_stats stats; | |
021230d4 | 730 | |
9a799d71 | 731 | u64 tx_busy; |
30efa5a3 JB |
732 | unsigned int tx_ring_count; |
733 | unsigned int rx_ring_count; | |
cf8280ee JB |
734 | |
735 | u32 link_speed; | |
736 | bool link_up; | |
737 | unsigned long link_check_timeout; | |
738 | ||
7086400d | 739 | struct timer_list service_timer; |
46646e61 AD |
740 | struct work_struct service_task; |
741 | ||
742 | struct hlist_head fdir_filter_list; | |
743 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
744 | union ixgbe_atr_input fdir_mask; | |
745 | int fdir_filter_count; | |
c4cf55e5 PWJ |
746 | u32 fdir_pballoc; |
747 | u32 atr_sample_rate; | |
748 | spinlock_t fdir_perfect_lock; | |
46646e61 | 749 | |
d0ed8937 YZ |
750 | #ifdef IXGBE_FCOE |
751 | struct ixgbe_fcoe fcoe; | |
752 | #endif /* IXGBE_FCOE */ | |
2a1a091c | 753 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
e8e26350 | 754 | u32 wol; |
46646e61 | 755 | |
46646e61 AD |
756 | u16 bd_number; |
757 | ||
15e5209f ET |
758 | u16 eeprom_verh; |
759 | u16 eeprom_verl; | |
c23f5b6b | 760 | u16 eeprom_cap; |
7f870475 | 761 | |
119fc60a | 762 | u32 interrupt_event; |
46646e61 | 763 | u32 led_reg; |
1a6c14a2 | 764 | |
3a6a4eda JK |
765 | struct ptp_clock *ptp_clock; |
766 | struct ptp_clock_info ptp_caps; | |
891dc082 JK |
767 | struct work_struct ptp_tx_work; |
768 | struct sk_buff *ptp_tx_skb; | |
93501d48 | 769 | struct hwtstamp_config tstamp_config; |
891dc082 | 770 | unsigned long ptp_tx_start; |
3a6a4eda | 771 | unsigned long last_overflow_check; |
6cb562d6 | 772 | unsigned long last_rx_ptp_check; |
3a6a4eda JK |
773 | spinlock_t tmreg_lock; |
774 | struct cyclecounter cc; | |
775 | struct timecounter tc; | |
776 | u32 base_incval; | |
3a6a4eda | 777 | |
7f870475 GR |
778 | /* SR-IOV */ |
779 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
780 | unsigned int num_vfs; | |
781 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 782 | int vf_rate_link_speed; |
a1cbb15c GR |
783 | struct vf_macvlans vf_mvs; |
784 | struct vf_macvlans *mv_list; | |
3e05334f | 785 | |
83c61fa9 GR |
786 | u32 timer_event_accumulator; |
787 | u32 vferr_refcount; | |
3ca8bc6d DS |
788 | struct kobject *info_kobj; |
789 | #ifdef CONFIG_IXGBE_HWMON | |
03b77d81 | 790 | struct hwmon_buff *ixgbe_hwmon_buff; |
3ca8bc6d | 791 | #endif /* CONFIG_IXGBE_HWMON */ |
00949167 CS |
792 | #ifdef CONFIG_DEBUG_FS |
793 | struct dentry *ixgbe_dbg_adapter; | |
794 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
795 | |
796 | u8 default_up; | |
2a47fa45 | 797 | unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ |
3e05334f AD |
798 | }; |
799 | ||
800 | struct ixgbe_fdir_filter { | |
801 | struct hlist_node fdir_node; | |
802 | union ixgbe_atr_input filter; | |
803 | u16 sw_idx; | |
804 | u16 action; | |
9a799d71 AK |
805 | }; |
806 | ||
70e5576c | 807 | enum ixgbe_state_t { |
9a799d71 AK |
808 | __IXGBE_TESTING, |
809 | __IXGBE_RESETTING, | |
c4900be0 | 810 | __IXGBE_DOWN, |
41c62843 | 811 | __IXGBE_DISABLED, |
09f40aed | 812 | __IXGBE_REMOVING, |
7086400d | 813 | __IXGBE_SERVICE_SCHED, |
58cf663f | 814 | __IXGBE_SERVICE_INITED, |
7086400d | 815 | __IXGBE_IN_SFP_INIT, |
8fecf67c | 816 | __IXGBE_PTP_RUNNING, |
151b260c | 817 | __IXGBE_PTP_TX_IN_PROGRESS, |
9a799d71 AK |
818 | }; |
819 | ||
4c1975d7 AD |
820 | struct ixgbe_cb { |
821 | union { /* Union defining head/tail partner */ | |
822 | struct sk_buff *head; | |
823 | struct sk_buff *tail; | |
824 | }; | |
aa80175a | 825 | dma_addr_t dma; |
4c1975d7 | 826 | u16 append_cnt; |
f800326d | 827 | bool page_released; |
aa80175a | 828 | }; |
4c1975d7 | 829 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 830 | |
9a799d71 | 831 | enum ixgbe_boards { |
3957d63d | 832 | board_82598, |
e8e26350 | 833 | board_82599, |
fe15e8e1 | 834 | board_X540, |
9a799d71 AK |
835 | }; |
836 | ||
3957d63d | 837 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 838 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 839 | extern struct ixgbe_info ixgbe_X540_info; |
7a6b6f51 | 840 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 841 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 | 842 | #endif |
9a799d71 AK |
843 | |
844 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 845 | extern const char ixgbe_driver_version[]; |
8af3c33f | 846 | #ifdef IXGBE_FCOE |
ea81875a | 847 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 848 | #endif /* IXGBE_FCOE */ |
9a799d71 | 849 | |
5ccc921a JP |
850 | void ixgbe_up(struct ixgbe_adapter *adapter); |
851 | void ixgbe_down(struct ixgbe_adapter *adapter); | |
852 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); | |
853 | void ixgbe_reset(struct ixgbe_adapter *adapter); | |
854 | void ixgbe_set_ethtool_ops(struct net_device *netdev); | |
855 | int ixgbe_setup_rx_resources(struct ixgbe_ring *); | |
856 | int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
857 | void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
858 | void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
859 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
860 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
861 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); | |
862 | void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
863 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); | |
864 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
8e2813f5 | 865 | u16 subdevice_id); |
5ccc921a JP |
866 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
867 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, | |
868 | struct ixgbe_ring *); | |
869 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, | |
870 | struct ixgbe_tx_buffer *); | |
871 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); | |
872 | void ixgbe_write_eitr(struct ixgbe_q_vector *); | |
873 | int ixgbe_poll(struct napi_struct *napi, int budget); | |
874 | int ethtool_ioctl(struct ifreq *ifr); | |
875 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
876 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
877 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
878 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
879 | union ixgbe_atr_hash_dword input, | |
880 | union ixgbe_atr_hash_dword common, | |
881 | u8 queue); | |
882 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
883 | union ixgbe_atr_input *input_mask); | |
884 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
885 | union ixgbe_atr_input *input, | |
886 | u16 soft_id, u8 queue); | |
887 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
888 | union ixgbe_atr_input *input, | |
889 | u16 soft_id); | |
890 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
891 | union ixgbe_atr_input *mask); | |
5ccc921a | 892 | void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 893 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a | 894 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
8af3c33f | 895 | #endif |
5ccc921a JP |
896 | int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
897 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); | |
898 | void ixgbe_do_reset(struct net_device *netdev); | |
1210982b | 899 | #ifdef CONFIG_IXGBE_HWMON |
5ccc921a JP |
900 | void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
901 | int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 902 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 | 903 | #ifdef IXGBE_FCOE |
5ccc921a JP |
904 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); |
905 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, | |
906 | u8 *hdr_len); | |
907 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
908 | union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); | |
909 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
910 | struct scatterlist *sgl, unsigned int sgc); | |
911 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
912 | struct scatterlist *sgl, unsigned int sgc); | |
913 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
914 | int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
915 | void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
916 | int ixgbe_fcoe_enable(struct net_device *netdev); | |
917 | int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 | 918 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a JP |
919 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); |
920 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
6ee16520 | 921 | #endif /* CONFIG_IXGBE_DCB */ |
5ccc921a JP |
922 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
923 | int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, | |
924 | struct netdev_fcoe_hbainfo *info); | |
925 | u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); | |
eacd73f7 | 926 | #endif /* IXGBE_FCOE */ |
00949167 | 927 | #ifdef CONFIG_DEBUG_FS |
5ccc921a JP |
928 | void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); |
929 | void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
930 | void ixgbe_dbg_init(void); | |
931 | void ixgbe_dbg_exit(void); | |
33243fb0 JP |
932 | #else |
933 | static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} | |
934 | static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} | |
935 | static inline void ixgbe_dbg_init(void) {} | |
936 | static inline void ixgbe_dbg_exit(void) {} | |
00949167 | 937 | #endif /* CONFIG_DEBUG_FS */ |
b2d96e0a AD |
938 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
939 | { | |
940 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
941 | } | |
942 | ||
5ccc921a JP |
943 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter); |
944 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); | |
945 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
946 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); | |
947 | void __ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector, | |
948 | struct sk_buff *skb); | |
39dfb71b AD |
949 | static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, |
950 | union ixgbe_adv_rx_desc *rx_desc, | |
951 | struct sk_buff *skb) | |
952 | { | |
953 | if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) | |
954 | return; | |
955 | ||
956 | __ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, skb); | |
957 | ||
958 | /* | |
959 | * Update the last_rx_timestamp timer in order to enable watchdog check | |
960 | * for error case of latched timestamp on a dropped packet. | |
961 | */ | |
962 | rx_ring->last_rx_timestamp = jiffies; | |
963 | } | |
964 | ||
93501d48 JK |
965 | int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); |
966 | int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); | |
5ccc921a JP |
967 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); |
968 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); | |
969 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); | |
da36b647 GR |
970 | #ifdef CONFIG_PCI_IOV |
971 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); | |
972 | #endif | |
3a6a4eda | 973 | |
2a47fa45 JF |
974 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
975 | struct ixgbe_adapter *adapter, | |
976 | struct ixgbe_ring *tx_ring); | |
9a799d71 | 977 | #endif /* _IXGBE_H_ */ |