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Merge branch 'for-davem' of git://git.infradead.org/users/linville/wireless-next
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
59224555 56#define IXGBE_DEFAULT_TX_WORK 256
9a799d71
AK		 57#define IXGBE_MAX_TXD 4096
58#define IXGBE_MIN_TXD 64
59
6bacb300 60#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 61#define IXGBE_MAX_RXD 4096
62#define IXGBE_MIN_RXD 64
63
9a799d71 64/* flow control */
2b9ade93 65#define IXGBE_MIN_FCRTL 0x40
9a799d71 66#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 67#define IXGBE_MIN_FCRTH 0x600
9a799d71 68#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
13958070 74#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
919e78a6
AD		 75#define IXGBE_RXBUFFER_2K 2048
76#define IXGBE_RXBUFFER_3K 3072
77#define IXGBE_RXBUFFER_4K 4096
78#define IXGBE_RXBUFFER_7K 7168
79#define IXGBE_RXBUFFER_8K 8192
80#define IXGBE_RXBUFFER_15K 15360
81#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 82
13958070
AD		 83/*
84 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
85 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
86 * this adds up to 512 bytes of extra data meaning the smallest allocation
87 * we could have is 1K.
88 * i.e. RXBUFFER_512 --> size-1024 slab
89 */
90#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 91
92#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
93
9a799d71
AK		 94/* How many Rx Buffers do we bundle into one write to the hardware ? */
95#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
96
97#define IXGBE_TX_FLAGS_CSUM (u32)(1)
66f32a8b
AD		 98#define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
99#define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
100#define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
101#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
102#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
103#define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
7f9643fd
AD		 104#define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
105#define IXGBE_TX_FLAGS_MAPPED_AS_PAGE (u32)(1 << 8)
9a799d71 106#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
66f32a8b
AD		 107#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
108#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
9a799d71
AK		 109#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
110
0a924578
PWJ		 111#define IXGBE_MAX_RSC_INT_RATE 162760
112
7f870475
GR		 113#define IXGBE_MAX_VF_MC_ENTRIES 30
114#define IXGBE_MAX_VF_FUNCTIONS 64
115#define IXGBE_MAX_VFTA_ENTRIES 128
116#define MAX_EMULATION_MAC_ADDRS 16
a1cbb15c 117#define IXGBE_MAX_PF_MACVLANS 15
7f870475
GR		 118#define VMDQ_P(p) ((p) + adapter->num_vfs)
119
120struct vf_data_storage {
121 unsigned char vf_mac_addresses[ETH_ALEN];
122 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
123 u16 num_vf_mc_hashes;
124 u16 default_vf_vlan_id;
125 u16 vlans_enabled;
7f870475 126 bool clear_to_send;
7f01648a 127 bool pf_set_mac;
7f01648a
GR		 128 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
129 u16 pf_qos;
ff4ab206 130 u16 tx_rate;
c6bda30a 131 struct pci_dev *vfdev;
7f870475
GR		 132};
133
a1cbb15c
GR		 134struct vf_macvlans {
135 struct list_head l;
136 int vf;
137 int rar_entry;
138 bool free;
139 bool is_macvlan;
140 u8 vf_macvlan[ETH_ALEN];
141};
142
a535c30e
AD		 143#define IXGBE_MAX_TXD_PWR 14
144#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
145
146/* Tx Descriptors needed, worst case */
147#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
148#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
149
9a799d71
AK		 150/* wrapper around a pointer to a socket buffer,
151 * so a DMA handle can be stored along with the buffer */
152struct ixgbe_tx_buffer {
d3d00239 153 union ixgbe_adv_tx_desc *next_to_watch;
9a799d71 154 unsigned long time_stamp;
d3d00239
AD		 155 dma_addr_t dma;
156 u32 length;
157 u32 tx_flags;
158 struct sk_buff *skb;
159 u32 bytecount;
8ad494b0 160 u16 gso_segs;
9a799d71
AK		 161};
162
163struct ixgbe_rx_buffer {
164 struct sk_buff *skb;
165 dma_addr_t dma;
166 struct page *page;
167 dma_addr_t page_dma;
762f4c57 168 unsigned int page_offset;
9a799d71
AK		 169};
170
171struct ixgbe_queue_stats {
172 u64 packets;
173 u64 bytes;
174};
175
5b7da515
AD		 176struct ixgbe_tx_queue_stats {
177 u64 restart_queue;
178 u64 tx_busy;
c84d324c
JF		 179 u64 completed;
180 u64 tx_done_old;
5b7da515
AD		 181};
182
183struct ixgbe_rx_queue_stats {
184 u64 rsc_count;
185 u64 rsc_flush;
186 u64 non_eop_descs;
187 u64 alloc_rx_page_failed;
188 u64 alloc_rx_buff_failed;
189};
190
7d637bcc
AD		 191enum ixbge_ring_state_t {
192 __IXGBE_TX_FDIR_INIT_DONE,
193 __IXGBE_TX_DETECT_HANG,
c84d324c 194 __IXGBE_HANG_CHECK_ARMED,
7d637bcc
AD		 195 __IXGBE_RX_PS_ENABLED,
196 __IXGBE_RX_RSC_ENABLED,
197};
198
199#define ring_is_ps_enabled(ring) \
200 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
201#define set_ring_ps_enabled(ring) \
202 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
203#define clear_ring_ps_enabled(ring) \
204 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
205#define check_for_tx_hang(ring) \
206 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
207#define set_check_for_tx_hang(ring) \
208 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
209#define clear_check_for_tx_hang(ring) \
210 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
211#define ring_is_rsc_enabled(ring) \
212 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
213#define set_ring_rsc_enabled(ring) \
214 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
215#define clear_ring_rsc_enabled(ring) \
216 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 217struct ixgbe_ring {
efe3d3c8 218 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
9a799d71 219 void *desc; /* descriptor ring memory */
b6ec895e 220 struct device *dev; /* device for DMA mapping */
fc77dc3c 221 struct net_device *netdev; /* netdev ring belongs to */
9a799d71
AK		 222 union {
223 struct ixgbe_tx_buffer *tx_buffer_info;
224 struct ixgbe_rx_buffer *rx_buffer_info;
225 };
7d637bcc 226 unsigned long state;
bd198058
AD		 227 u8 __iomem *tail;
228
ae540af1
JB		 229 u16 count; /* amount of descriptors */
230 u16 rx_buf_len;
ae540af1
JB		 231
232 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 233 u8 reg_idx; /* holds the special value that gets
234 * the hardware register offset
235 * associated with this ring, which is
236 * different for DCB and RSS modes
237 */
bd198058
AD		 238 u8 atr_sample_rate;
239 u8 atr_count;
9a799d71 240
bd198058
AD		 241 u16 next_to_use;
242 u16 next_to_clean;
9a799d71 243
bd198058 244 u8 dcb_tc;
9a799d71 245 struct ixgbe_queue_stats stats;
de1036b1 246 struct u64_stats_sync syncp;
5b7da515
AD		 247 union {
248 struct ixgbe_tx_queue_stats tx_stats;
249 struct ixgbe_rx_queue_stats rx_stats;
250 };
5b7da515 251 int numa_node;
ae540af1
JB		 252 unsigned int size; /* length in bytes */
253 dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b 254 struct rcu_head rcu;
33cf09c9 255 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
7ca3bc58 256} ____cacheline_internodealigned_in_smp;
9a799d71 257
c7e4358a
SN		 258enum ixgbe_ring_f_enum {
259 RING_F_NONE = 0,
7f870475 260 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 261 RING_F_RSS,
c4cf55e5 262 RING_F_FDIR,
0331a832
YZ		 263#ifdef IXGBE_FCOE
264 RING_F_FCOE,
265#endif /* IXGBE_FCOE */
c7e4358a
SN		 266
267 RING_F_ARRAY_SIZE /* must be last in enum set */
268};
269
021230d4 270#define IXGBE_MAX_RSS_INDICES 16
7f870475 271#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 272#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 273#ifdef IXGBE_FCOE
274#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 275#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
276#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
277#else
278#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
279#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 280#endif /* IXGBE_FCOE */
021230d4
AV		 281struct ixgbe_ring_feature {
282 int indices;
283 int mask;
7ca3bc58 284} ____cacheline_internodealigned_in_smp;
021230d4 285
08c8833b 286struct ixgbe_ring_container {
efe3d3c8 287 struct ixgbe_ring *ring; /* pointer to linked list of rings */
bd198058
AD		 288 unsigned int total_bytes; /* total bytes processed this int */
289 unsigned int total_packets; /* total packets processed this int */
290 u16 work_limit; /* total work allowed per interrupt */
08c8833b
AD		 291 u8 count; /* total number of rings in vector */
292 u8 itr; /* current ITR setting for ring */
293};
021230d4 294
2f90b865
AD		 295#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
296 ? 8 : 1)
297#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
298
021230d4
AV		 299/* MAX_MSIX_Q_VECTORS of these are allocated,
300 * but we only use one per queue-specific vector.
301 */
302struct ixgbe_q_vector {
303 struct ixgbe_adapter *adapter;
33cf09c9
AD		 304#ifdef CONFIG_IXGBE_DCA
305 int cpu; /* CPU for DCA */
306#endif
d5bf4f67
ET		 307 u16 v_idx; /* index of q_vector within array, also used for
308 * finding the bit in EICR and friends that
309 * represents the vector for this ring */
310 u16 itr; /* Interrupt throttle rate written to EITR */
08c8833b 311 struct ixgbe_ring_container rx, tx;
d5bf4f67
ET		 312
313 struct napi_struct napi;
b25ebfd2 314 cpumask_var_t affinity_mask;
d0759ebb 315 char name[IFNAMSIZ + 9];
021230d4
AV		 316};
317
d5bf4f67
ET		 318/*
319 * microsecond values for various ITR rates shifted by 2 to fit itr register
320 * with the first 3 bits reserved 0
9a799d71 321 */
d5bf4f67
ET		 322#define IXGBE_MIN_RSC_ITR 24
323#define IXGBE_100K_ITR 40
324#define IXGBE_20K_ITR 200
325#define IXGBE_10K_ITR 400
326#define IXGBE_8K_ITR 500
9a799d71 327
7d4987de
AD		 328static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
329{
330 u16 ntc = ring->next_to_clean;
331 u16 ntu = ring->next_to_use;
332
333 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
334}
9a799d71
AK		 335
336#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 337 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 338#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 339 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 340#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 341 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 342
343#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 344#ifdef IXGBE_FCOE
345/* Use 3K as the baby jumbo frame size for FCoE */
346#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
347#endif /* IXGBE_FCOE */
9a799d71 348
021230d4
AV		 349#define OTHER_VECTOR 1
350#define NON_Q_VECTORS (OTHER_VECTOR)
351
e8e26350
PW		 352#define MAX_MSIX_VECTORS_82599 64
353#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 354#define MAX_MSIX_VECTORS_82598 18
355#define MAX_MSIX_Q_VECTORS_82598 16
356
e8e26350
PW		 357#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
358#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 359
021230d4 360#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 361#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
362
9a799d71
AK		 363/* board specific private data structure */
364struct ixgbe_adapter {
e606bfe7
AD		 365 unsigned long state;
366
367 /* Some features need tri-state capability,
368 * thus the additional *_CAPABLE flags.
369 */
370 u32 flags;
371#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
372#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
373#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
374#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
375#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
376#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
377#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
378#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
379#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
380#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
381#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
382#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
383#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
384#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
385#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
386#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
387#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
388#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
389#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
390#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
7086400d
AD		 391#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
392#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
393#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
394#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
395#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
396#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
397#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
e606bfe7
AD		 398
399 u32 flags2;
400#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
401#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
402#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
f0f9778d 403#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
7086400d
AD		 404#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
405#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
c83c6cbd 406#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
d034acf1 407#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
e606bfe7 408
f62bbb5e 409 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71 410 u16 bd_number;
7a921c93 411 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
d033d526
JF		 412
413 /* DCB parameters */
414 struct ieee_pfc *ixgbe_ieee_pfc;
415 struct ieee_ets *ixgbe_ieee_ets;
2f90b865
AD		 416 struct ixgbe_dcb_config dcb_cfg;
417 struct ixgbe_dcb_config temp_dcb_cfg;
418 u8 dcb_set_bitmap;
3032309b 419 u8 dcbx_cap;
264857b8 420 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 421
f494e8fa 422 /* Interrupt Throttle Rate */
f7554a2b
NS		 423 u32 rx_itr_setting;
424 u32 tx_itr_setting;
f494e8fa
AV		 425 u16 eitr_low;
426 u16 eitr_high;
427
bd198058
AD		 428 /* Work limits */
429 u16 tx_work_limit;
430
9a799d71 431 /* TX */
4a0b9ca0 432 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 433 int num_tx_queues;
9a799d71
AK		 434 u32 tx_timeout_count;
435 bool detect_tx_hung;
436
7ca3bc58
JB		 437 u64 restart_queue;
438 u64 lsc_int;
439
9a799d71 440 /* RX */
4a0b9ca0 441 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 442 int num_rx_queues;
7f870475
GR		 443 int num_rx_pools; /* == num_rx_queues in 82598 */
444 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 445 u64 hw_csum_rx_error;
e8e26350 446 u64 hw_rx_no_dma_resources;
9a799d71 447 u64 non_eop_descs;
021230d4 448 int num_msix_vectors;
eb7f139c 449 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 450 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 451 struct msix_entry *msix_entries;
452
9a799d71
AK		 453 u32 alloc_rx_page_failed;
454 u32 alloc_rx_buff_failed;
455
96b0e0f6
JB		 456/* default to trying for four seconds */
457#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 458
459 /* OS defined structs */
460 struct net_device *netdev;
461 struct pci_dev *pdev;
9a799d71 462
da4dd0f7
PWJ		 463 u32 test_icr;
464 struct ixgbe_ring test_tx_ring;
465 struct ixgbe_ring test_rx_ring;
466
9a799d71
AK		 467 /* structs defined in ixgbe_hw.h */
468 struct ixgbe_hw hw;
469 u16 msg_enable;
470 struct ixgbe_hw_stats stats;
021230d4
AV		 471
472 /* Interrupt Throttle Rate */
f7554a2b
NS		 473 u32 rx_eitr_param;
474 u32 tx_eitr_param;
9a799d71 475
9a799d71 476 u64 tx_busy;
30efa5a3
JB		 477 unsigned int tx_ring_count;
478 unsigned int rx_ring_count;
cf8280ee
JB		 479
480 u32 link_speed;
481 bool link_up;
482 unsigned long link_check_timeout;
483
7086400d 484 struct work_struct service_task;
7086400d 485 struct timer_list service_timer;
c4cf55e5
PWJ		 486 u32 fdir_pballoc;
487 u32 atr_sample_rate;
d034acf1 488 unsigned long fdir_overflow; /* number of times ATR was backed off */
c4cf55e5 489 spinlock_t fdir_perfect_lock;
d0ed8937
YZ		 490#ifdef IXGBE_FCOE
491 struct ixgbe_fcoe fcoe;
492#endif /* IXGBE_FCOE */
94b982b2
MC		 493 u64 rsc_total_count;
494 u64 rsc_total_flush;
e8e26350 495 u32 wol;
34b0368c 496 u16 eeprom_version;
c23f5b6b 497 u16 eeprom_cap;
7f870475 498
1a6c14a2 499 int node;
66e6961c 500 u32 led_reg;
119fc60a 501 u32 interrupt_event;
1a6c14a2 502
7f870475
GR		 503 /* SR-IOV */
504 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
505 unsigned int num_vfs;
506 struct vf_data_storage *vfinfo;
ff4ab206 507 int vf_rate_link_speed;
a1cbb15c
GR		 508 struct vf_macvlans vf_mvs;
509 struct vf_macvlans *mv_list;
510 bool antispoofing_enabled;
3e05334f
AD		 511
512 struct hlist_head fdir_filter_list;
513 union ixgbe_atr_input fdir_mask;
514 int fdir_filter_count;
515};
516
517struct ixgbe_fdir_filter {
518 struct hlist_node fdir_node;
519 union ixgbe_atr_input filter;
520 u16 sw_idx;
521 u16 action;
9a799d71
AK		 522};
523
524enum ixbge_state_t {
525 __IXGBE_TESTING,
526 __IXGBE_RESETTING,
c4900be0 527 __IXGBE_DOWN,
7086400d
AD		 528 __IXGBE_SERVICE_SCHED,
529 __IXGBE_IN_SFP_INIT,
9a799d71
AK		 530};
531
aa80175a
AD		 532struct ixgbe_rsc_cb {
533 dma_addr_t dma;
534 u16 skb_cnt;
535 bool delay_unmap;
536};
537#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
538
9a799d71 539enum ixgbe_boards {
3957d63d 540 board_82598,
e8e26350 541 board_82599,
fe15e8e1 542 board_X540,
9a799d71
AK		 543};
544
3957d63d 545extern struct ixgbe_info ixgbe_82598_info;
e8e26350 546extern struct ixgbe_info ixgbe_82599_info;
fe15e8e1 547extern struct ixgbe_info ixgbe_X540_info;
7a6b6f51 548#ifdef CONFIG_IXGBE_DCB
32953543 549extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 550extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
551 struct ixgbe_dcb_config *dst_dcb_cfg,
552 int tc_max);
553#endif
9a799d71
AK		 554
555extern char ixgbe_driver_name[];
9c8eb720 556extern const char ixgbe_driver_version[];
9a799d71 557
c7ccde0f 558extern void ixgbe_up(struct ixgbe_adapter *adapter);
9a799d71 559extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 560extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 561extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 562extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 563extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
564extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
565extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
566extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 567extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
568extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
2d39d576
YZ		 569extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
570 struct ixgbe_ring *);
b4617240 571extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 572extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 573extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 574extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 575 struct ixgbe_adapter *,
576 struct ixgbe_ring *);
b6ec895e 577extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 578 struct ixgbe_tx_buffer *);
fc77dc3c 579extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a
AD		 580extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
581extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772 582extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
c04f6ca8
AD		 583extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
584extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
ffff4772 585extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 586 union ixgbe_atr_hash_dword input,
587 union ixgbe_atr_hash_dword common,
ffff4772 588 u8 queue);
c04f6ca8
AD		 589extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
590 union ixgbe_atr_input *input_mask);
591extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
592 union ixgbe_atr_input *input,
593 u16 soft_id, u8 queue);
594extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
595 union ixgbe_atr_input *input,
596 u16 soft_id);
597extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
598 union ixgbe_atr_input *mask);
7f870475 599extern void ixgbe_set_rx_mode(struct net_device *netdev);
e5b64635 600extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
897ab156 601extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
082757af 602extern void ixgbe_do_reset(struct net_device *netdev);
eacd73f7
YZ		 603#ifdef IXGBE_FCOE
604extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
897ab156 605extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
eacd73f7 606 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 607extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
608extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
ff886dfc
AD		 609 union ixgbe_adv_rx_desc *rx_desc,
610 struct sk_buff *skb,
611 u32 staterr);
332d4a7d
YZ		 612extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
613 struct scatterlist *sgl, unsigned int sgc);
68a683cf
YZ		 614extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
615 struct scatterlist *sgl, unsigned int sgc);
332d4a7d 616extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 617extern int ixgbe_fcoe_enable(struct net_device *netdev);
618extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 619#ifdef CONFIG_IXGBE_DCB
620extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
621extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
622#endif /* CONFIG_IXGBE_DCB */
61a1fa10 623extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 624#endif /* IXGBE_FCOE */
9a799d71
AK		 625
626#endif /* _IXGBE_H_ */
Linux 6.x block layer and io_uring tree(s)