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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
434c5e39 | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGBE_H_ | |
30 | #define _IXGBE_H_ | |
31 | ||
f62bbb5e | 32 | #include <linux/bitops.h> |
9a799d71 AK |
33 | #include <linux/types.h> |
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
b25ebfd2 | 36 | #include <linux/cpumask.h> |
6fabd715 | 37 | #include <linux/aer.h> |
f62bbb5e | 38 | #include <linux/if_vlan.h> |
6cb562d6 | 39 | #include <linux/jiffies.h> |
9a799d71 | 40 | |
3a6a4eda JK |
41 | #include <linux/clocksource.h> |
42 | #include <linux/net_tstamp.h> | |
43 | #include <linux/ptp_clock_kernel.h> | |
3a6a4eda | 44 | |
9a799d71 AK |
45 | #include "ixgbe_type.h" |
46 | #include "ixgbe_common.h" | |
2f90b865 | 47 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
48 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
49 | #define IXGBE_FCOE | |
50 | #include "ixgbe_fcoe.h" | |
51 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 52 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
53 | #include <linux/dca.h> |
54 | #endif | |
9a799d71 | 55 | |
076bb0c8 | 56 | #include <net/busy_poll.h> |
5a85e737 | 57 | |
e0d1095a | 58 | #ifdef CONFIG_NET_RX_BUSY_POLL |
b4640030 | 59 | #define BP_EXTENDED_STATS |
7e15b90f | 60 | #endif |
849c4542 ET |
61 | /* common prefix used by pr_<> macros */ |
62 | #undef pr_fmt | |
63 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
64 | |
65 | /* TX/RX descriptor defines */ | |
6bacb300 | 66 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 67 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
68 | #define IXGBE_MAX_TXD 4096 |
69 | #define IXGBE_MIN_TXD 64 | |
70 | ||
fb44519d | 71 | #if (PAGE_SIZE < 8192) |
6bacb300 | 72 | #define IXGBE_DEFAULT_RXD 512 |
fb44519d AB |
73 | #else |
74 | #define IXGBE_DEFAULT_RXD 128 | |
75 | #endif | |
9a799d71 AK |
76 | #define IXGBE_MAX_RXD 4096 |
77 | #define IXGBE_MIN_RXD 64 | |
78 | ||
9a799d71 | 79 | /* flow control */ |
2b9ade93 | 80 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 81 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 82 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 83 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 84 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
85 | #define IXGBE_MIN_FCPAUSE 0 |
86 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
87 | ||
88 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 89 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
90 | #define IXGBE_RXBUFFER_2K 2048 |
91 | #define IXGBE_RXBUFFER_3K 3072 | |
92 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 93 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 94 | |
13958070 | 95 | /* |
252562c2 AD |
96 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
97 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
98 | * this adds up to 448 bytes of extra data. | |
99 | * | |
100 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
101 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 102 | */ |
252562c2 | 103 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 | 104 | |
9a799d71 AK |
105 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
106 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
107 | ||
472148c3 AD |
108 | enum ixgbe_tx_flags { |
109 | /* cmd_type flags */ | |
110 | IXGBE_TX_FLAGS_HW_VLAN = 0x01, | |
111 | IXGBE_TX_FLAGS_TSO = 0x02, | |
112 | IXGBE_TX_FLAGS_TSTAMP = 0x04, | |
113 | ||
114 | /* olinfo flags */ | |
115 | IXGBE_TX_FLAGS_CC = 0x08, | |
116 | IXGBE_TX_FLAGS_IPV4 = 0x10, | |
117 | IXGBE_TX_FLAGS_CSUM = 0x20, | |
118 | ||
119 | /* software defined flags */ | |
120 | IXGBE_TX_FLAGS_SW_VLAN = 0x40, | |
121 | IXGBE_TX_FLAGS_FCOE = 0x80, | |
122 | }; | |
123 | ||
124 | /* VLAN info */ | |
9a799d71 | 125 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
126 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
127 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
128 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
129 | ||
7f870475 GR |
130 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
131 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
132 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
133 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 134 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 135 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
136 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
137 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
138 | |
139 | struct vf_data_storage { | |
140 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
141 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
142 | u16 num_vf_mc_hashes; | |
143 | u16 default_vf_vlan_id; | |
144 | u16 vlans_enabled; | |
7f870475 | 145 | bool clear_to_send; |
7f01648a | 146 | bool pf_set_mac; |
7f01648a GR |
147 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
148 | u16 pf_qos; | |
ff4ab206 | 149 | u16 tx_rate; |
de4c7f65 GR |
150 | u16 vlan_count; |
151 | u8 spoofchk_enabled; | |
374c65d6 | 152 | unsigned int vf_api; |
7f870475 GR |
153 | }; |
154 | ||
a1cbb15c GR |
155 | struct vf_macvlans { |
156 | struct list_head l; | |
157 | int vf; | |
a1cbb15c GR |
158 | bool free; |
159 | bool is_macvlan; | |
160 | u8 vf_macvlan[ETH_ALEN]; | |
161 | }; | |
162 | ||
a535c30e AD |
163 | #define IXGBE_MAX_TXD_PWR 14 |
164 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
165 | ||
166 | /* Tx Descriptors needed, worst case */ | |
167 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
990a3158 | 168 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
a535c30e | 169 | |
9a799d71 AK |
170 | /* wrapper around a pointer to a socket buffer, |
171 | * so a DMA handle can be stored along with the buffer */ | |
172 | struct ixgbe_tx_buffer { | |
d3d00239 | 173 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 174 | unsigned long time_stamp; |
fd0db0ed AD |
175 | struct sk_buff *skb; |
176 | unsigned int bytecount; | |
177 | unsigned short gso_segs; | |
244e27ad | 178 | __be16 protocol; |
729739b7 AD |
179 | DEFINE_DMA_UNMAP_ADDR(dma); |
180 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 181 | u32 tx_flags; |
9a799d71 AK |
182 | }; |
183 | ||
184 | struct ixgbe_rx_buffer { | |
185 | struct sk_buff *skb; | |
186 | dma_addr_t dma; | |
187 | struct page *page; | |
762f4c57 | 188 | unsigned int page_offset; |
9a799d71 AK |
189 | }; |
190 | ||
191 | struct ixgbe_queue_stats { | |
192 | u64 packets; | |
193 | u64 bytes; | |
b4640030 | 194 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
195 | u64 yields; |
196 | u64 misses; | |
197 | u64 cleaned; | |
b4640030 | 198 | #endif /* BP_EXTENDED_STATS */ |
9a799d71 AK |
199 | }; |
200 | ||
5b7da515 AD |
201 | struct ixgbe_tx_queue_stats { |
202 | u64 restart_queue; | |
203 | u64 tx_busy; | |
c84d324c | 204 | u64 tx_done_old; |
5b7da515 AD |
205 | }; |
206 | ||
207 | struct ixgbe_rx_queue_stats { | |
208 | u64 rsc_count; | |
209 | u64 rsc_flush; | |
210 | u64 non_eop_descs; | |
211 | u64 alloc_rx_page_failed; | |
212 | u64 alloc_rx_buff_failed; | |
8a0da21b | 213 | u64 csum_err; |
5b7da515 AD |
214 | }; |
215 | ||
f800326d | 216 | enum ixgbe_ring_state_t { |
7d637bcc | 217 | __IXGBE_TX_FDIR_INIT_DONE, |
fd786b7b | 218 | __IXGBE_TX_XPS_INIT_DONE, |
7d637bcc | 219 | __IXGBE_TX_DETECT_HANG, |
c84d324c | 220 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 221 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 222 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
57efd44c | 223 | __IXGBE_RX_FCOE, |
7d637bcc AD |
224 | }; |
225 | ||
2a47fa45 JF |
226 | struct ixgbe_fwd_adapter { |
227 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
228 | struct net_device *netdev; | |
229 | struct ixgbe_adapter *real_adapter; | |
230 | unsigned int tx_base_queue; | |
231 | unsigned int rx_base_queue; | |
232 | int pool; | |
233 | }; | |
234 | ||
7d637bcc AD |
235 | #define check_for_tx_hang(ring) \ |
236 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
237 | #define set_check_for_tx_hang(ring) \ | |
238 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
239 | #define clear_check_for_tx_hang(ring) \ | |
240 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
241 | #define ring_is_rsc_enabled(ring) \ | |
242 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
243 | #define set_ring_rsc_enabled(ring) \ | |
244 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
245 | #define clear_ring_rsc_enabled(ring) \ | |
246 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 247 | struct ixgbe_ring { |
efe3d3c8 | 248 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
249 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
250 | struct net_device *netdev; /* netdev ring belongs to */ | |
251 | struct device *dev; /* device for DMA mapping */ | |
2a47fa45 | 252 | struct ixgbe_fwd_adapter *l2_accel_priv; |
9a799d71 | 253 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
254 | union { |
255 | struct ixgbe_tx_buffer *tx_buffer_info; | |
256 | struct ixgbe_rx_buffer *rx_buffer_info; | |
257 | }; | |
7d637bcc | 258 | unsigned long state; |
bd198058 | 259 | u8 __iomem *tail; |
d3ee4294 AD |
260 | dma_addr_t dma; /* phys. address of descriptor ring */ |
261 | unsigned int size; /* length in bytes */ | |
bd198058 | 262 | |
ae540af1 | 263 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
264 | |
265 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
266 | u8 reg_idx; /* holds the special value that gets |
267 | * the hardware register offset | |
268 | * associated with this ring, which is | |
269 | * different for DCB and RSS modes | |
270 | */ | |
d3ee4294 AD |
271 | u16 next_to_use; |
272 | u16 next_to_clean; | |
273 | ||
f800326d | 274 | union { |
d3ee4294 | 275 | u16 next_to_alloc; |
f800326d AD |
276 | struct { |
277 | u8 atr_sample_rate; | |
278 | u8 atr_count; | |
279 | }; | |
f800326d | 280 | }; |
9a799d71 | 281 | |
bd198058 | 282 | u8 dcb_tc; |
9a799d71 | 283 | struct ixgbe_queue_stats stats; |
de1036b1 | 284 | struct u64_stats_sync syncp; |
5b7da515 AD |
285 | union { |
286 | struct ixgbe_tx_queue_stats tx_stats; | |
287 | struct ixgbe_rx_queue_stats rx_stats; | |
288 | }; | |
7ca3bc58 | 289 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 290 | |
c7e4358a SN |
291 | enum ixgbe_ring_f_enum { |
292 | RING_F_NONE = 0, | |
7f870475 | 293 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 294 | RING_F_RSS, |
c4cf55e5 | 295 | RING_F_FDIR, |
0331a832 YZ |
296 | #ifdef IXGBE_FCOE |
297 | RING_F_FCOE, | |
298 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
299 | |
300 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
301 | }; | |
302 | ||
021230d4 | 303 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 304 | #define IXGBE_MAX_VMDQ_INDICES 64 |
d3cb9869 | 305 | #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ |
0331a832 | 306 | #define IXGBE_MAX_FCOE_INDICES 8 |
d3cb9869 AD |
307 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) |
308 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
2a47fa45 | 309 | #define IXGBE_MAX_L2A_QUEUES 4 |
2a47fa45 JF |
310 | #define IXGBE_BAD_L2A_QUEUE 3 |
311 | #define IXGBE_MAX_MACVLANS 31 | |
312 | #define IXGBE_MAX_DCBMACVLANS 8 | |
313 | ||
021230d4 | 314 | struct ixgbe_ring_feature { |
c087663e AD |
315 | u16 limit; /* upper limit on feature indices */ |
316 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
317 | u16 mask; /* Mask used for feature to ring mapping */ |
318 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 319 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 320 | |
73079ea0 AD |
321 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
322 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
323 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
324 | ||
f800326d AD |
325 | /* |
326 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
327 | * this is twice the size of a half page we need to double the page order | |
328 | * for FCoE enabled Rx queues. | |
329 | */ | |
09816fbe | 330 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 331 | { |
09816fbe AD |
332 | #ifdef IXGBE_FCOE |
333 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
334 | return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : | |
335 | IXGBE_RXBUFFER_3K; | |
336 | #endif | |
337 | return IXGBE_RXBUFFER_2K; | |
f800326d | 338 | } |
09816fbe AD |
339 | |
340 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
341 | { | |
342 | #ifdef IXGBE_FCOE | |
343 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
344 | return (PAGE_SIZE < 8192) ? 1 : 0; | |
f800326d | 345 | #endif |
09816fbe AD |
346 | return 0; |
347 | } | |
f800326d | 348 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 349 | |
08c8833b | 350 | struct ixgbe_ring_container { |
efe3d3c8 | 351 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
352 | unsigned int total_bytes; /* total bytes processed this int */ |
353 | unsigned int total_packets; /* total packets processed this int */ | |
354 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
355 | u8 count; /* total number of rings in vector */ |
356 | u8 itr; /* current ITR setting for ring */ | |
357 | }; | |
021230d4 | 358 | |
a557928e AD |
359 | /* iterator for handling rings in ring container */ |
360 | #define ixgbe_for_each_ring(pos, head) \ | |
361 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
362 | ||
2f90b865 | 363 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
e7cf745b | 364 | ? 8 : 1) |
2f90b865 AD |
365 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS |
366 | ||
49c7ffbe | 367 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
368 | * but we only use one per queue-specific vector. |
369 | */ | |
370 | struct ixgbe_q_vector { | |
371 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
372 | #ifdef CONFIG_IXGBE_DCA |
373 | int cpu; /* CPU for DCA */ | |
374 | #endif | |
d5bf4f67 ET |
375 | u16 v_idx; /* index of q_vector within array, also used for |
376 | * finding the bit in EICR and friends that | |
377 | * represents the vector for this ring */ | |
378 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 379 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
380 | |
381 | struct napi_struct napi; | |
de88eeeb AD |
382 | cpumask_t affinity_mask; |
383 | int numa_node; | |
384 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 385 | char name[IFNAMSIZ + 9]; |
de88eeeb | 386 | |
e0d1095a | 387 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 | 388 | atomic_t state; |
e0d1095a | 389 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 390 | |
de88eeeb AD |
391 | /* for dynamic allocation of rings associated with this q_vector */ |
392 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 393 | }; |
adc81090 | 394 | |
e0d1095a | 395 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 AD |
396 | enum ixgbe_qv_state_t { |
397 | IXGBE_QV_STATE_IDLE = 0, | |
398 | IXGBE_QV_STATE_NAPI, | |
399 | IXGBE_QV_STATE_POLL, | |
400 | IXGBE_QV_STATE_DISABLE | |
401 | }; | |
402 | ||
5a85e737 ET |
403 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
404 | { | |
adc81090 AD |
405 | /* reset state to idle */ |
406 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
407 | } |
408 | ||
409 | /* called from the device poll routine to get ownership of a q_vector */ | |
410 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
411 | { | |
adc81090 AD |
412 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
413 | IXGBE_QV_STATE_NAPI); | |
b4640030 | 414 | #ifdef BP_EXTENDED_STATS |
adc81090 | 415 | if (rc != IXGBE_QV_STATE_IDLE) |
7e15b90f ET |
416 | q_vector->tx.ring->stats.yields++; |
417 | #endif | |
adc81090 AD |
418 | |
419 | return rc == IXGBE_QV_STATE_IDLE; | |
5a85e737 ET |
420 | } |
421 | ||
422 | /* returns true is someone tried to get the qv while napi had it */ | |
adc81090 | 423 | static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) |
5a85e737 | 424 | { |
adc81090 AD |
425 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); |
426 | ||
427 | /* flush any outstanding Rx frames */ | |
428 | if (q_vector->napi.gro_list) | |
429 | napi_gro_flush(&q_vector->napi, false); | |
430 | ||
431 | /* reset state to idle */ | |
432 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
433 | } |
434 | ||
435 | /* called from ixgbe_low_latency_poll() */ | |
436 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
437 | { | |
adc81090 AD |
438 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
439 | IXGBE_QV_STATE_POLL); | |
b4640030 | 440 | #ifdef BP_EXTENDED_STATS |
adc81090 AD |
441 | if (rc != IXGBE_QV_STATE_IDLE) |
442 | q_vector->tx.ring->stats.yields++; | |
7e15b90f | 443 | #endif |
adc81090 | 444 | return rc == IXGBE_QV_STATE_IDLE; |
5a85e737 ET |
445 | } |
446 | ||
447 | /* returns true if someone tried to get the qv while it was locked */ | |
adc81090 | 448 | static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) |
5a85e737 | 449 | { |
adc81090 AD |
450 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); |
451 | ||
452 | /* reset state to idle */ | |
453 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
454 | } |
455 | ||
456 | /* true if a socket is polling, even if it did not get the lock */ | |
b4640030 | 457 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 | 458 | { |
adc81090 | 459 | return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; |
5a85e737 | 460 | } |
27d9ce4f JK |
461 | |
462 | /* false if QV is currently owned */ | |
463 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
464 | { | |
adc81090 AD |
465 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
466 | IXGBE_QV_STATE_DISABLE); | |
467 | ||
468 | return rc == IXGBE_QV_STATE_IDLE; | |
27d9ce4f JK |
469 | } |
470 | ||
e0d1095a | 471 | #else /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 ET |
472 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
473 | { | |
474 | } | |
475 | ||
476 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
477 | { | |
478 | return true; | |
479 | } | |
480 | ||
481 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
482 | { | |
483 | return false; | |
484 | } | |
485 | ||
486 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
487 | { | |
488 | return false; | |
489 | } | |
490 | ||
491 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
492 | { | |
493 | return false; | |
494 | } | |
495 | ||
b4640030 | 496 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 ET |
497 | { |
498 | return false; | |
499 | } | |
27d9ce4f JK |
500 | |
501 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
502 | { | |
503 | return true; | |
504 | } | |
505 | ||
e0d1095a | 506 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 507 | |
3ca8bc6d DS |
508 | #ifdef CONFIG_IXGBE_HWMON |
509 | ||
510 | #define IXGBE_HWMON_TYPE_LOC 0 | |
511 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
512 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
513 | #define IXGBE_HWMON_TYPE_MAX 3 | |
514 | ||
515 | struct hwmon_attr { | |
516 | struct device_attribute dev_attr; | |
517 | struct ixgbe_hw *hw; | |
518 | struct ixgbe_thermal_diode_data *sensor; | |
519 | char name[12]; | |
520 | }; | |
521 | ||
522 | struct hwmon_buff { | |
03b77d81 GR |
523 | struct attribute_group group; |
524 | const struct attribute_group *groups[2]; | |
525 | struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; | |
526 | struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; | |
3ca8bc6d DS |
527 | unsigned int n_hwmon; |
528 | }; | |
529 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 530 | |
d5bf4f67 ET |
531 | /* |
532 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
533 | * with the first 3 bits reserved 0 | |
9a799d71 | 534 | */ |
d5bf4f67 ET |
535 | #define IXGBE_MIN_RSC_ITR 24 |
536 | #define IXGBE_100K_ITR 40 | |
537 | #define IXGBE_20K_ITR 200 | |
538 | #define IXGBE_10K_ITR 400 | |
539 | #define IXGBE_8K_ITR 500 | |
9a799d71 | 540 | |
f56e0cb1 AD |
541 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
542 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
543 | const u32 stat_err_bits) | |
544 | { | |
545 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
546 | } | |
547 | ||
7d4987de AD |
548 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
549 | { | |
550 | u16 ntc = ring->next_to_clean; | |
551 | u16 ntu = ring->next_to_use; | |
552 | ||
553 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
554 | } | |
9a799d71 | 555 | |
e4f74028 | 556 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 557 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 558 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 559 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 560 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 561 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 562 | |
c88887e0 | 563 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
564 | #ifdef IXGBE_FCOE |
565 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
566 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
567 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 568 | |
021230d4 AV |
569 | #define OTHER_VECTOR 1 |
570 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
571 | ||
e8e26350 | 572 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 573 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 574 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 575 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 576 | |
5d7daa35 JK |
577 | struct ixgbe_mac_addr { |
578 | u8 addr[ETH_ALEN]; | |
579 | u16 queue; | |
580 | u16 state; /* bitmask */ | |
581 | }; | |
582 | #define IXGBE_MAC_STATE_DEFAULT 0x1 | |
583 | #define IXGBE_MAC_STATE_MODIFIED 0x2 | |
584 | #define IXGBE_MAC_STATE_IN_USE 0x4 | |
585 | ||
49c7ffbe | 586 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 587 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 588 | |
8f15486d | 589 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
590 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
591 | ||
46646e61 AD |
592 | /* default to trying for four seconds */ |
593 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
594 | ||
9a799d71 AK |
595 | /* board specific private data structure */ |
596 | struct ixgbe_adapter { | |
46646e61 AD |
597 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
598 | /* OS defined structs */ | |
599 | struct net_device *netdev; | |
600 | struct pci_dev *pdev; | |
601 | ||
e606bfe7 AD |
602 | unsigned long state; |
603 | ||
604 | /* Some features need tri-state capability, | |
605 | * thus the additional *_CAPABLE flags. | |
606 | */ | |
607 | u32 flags; | |
a16a0d2f | 608 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) |
a16a0d2f AD |
609 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) |
610 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) | |
611 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) | |
612 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) | |
613 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) | |
614 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) | |
615 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) | |
616 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) | |
617 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) | |
618 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) | |
619 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) | |
620 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) | |
621 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) | |
622 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) | |
623 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) | |
624 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) | |
625 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) | |
626 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) | |
627 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) | |
628 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) | |
629 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) | |
e606bfe7 AD |
630 | |
631 | u32 flags2; | |
a16a0d2f | 632 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) |
e606bfe7 AD |
633 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) |
634 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 635 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
636 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
637 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 638 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 639 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
ef6afc0c AD |
640 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) |
641 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) | |
8fecf67c JK |
642 | #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) |
643 | #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11) | |
d033d526 | 644 | |
46646e61 AD |
645 | /* Tx fast path data */ |
646 | int num_tx_queues; | |
647 | u16 tx_itr_setting; | |
bd198058 AD |
648 | u16 tx_work_limit; |
649 | ||
46646e61 AD |
650 | /* Rx fast path data */ |
651 | int num_rx_queues; | |
652 | u16 rx_itr_setting; | |
653 | ||
9a799d71 | 654 | /* TX */ |
4a0b9ca0 | 655 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 656 | |
7ca3bc58 JB |
657 | u64 restart_queue; |
658 | u64 lsc_int; | |
46646e61 | 659 | u32 tx_timeout_count; |
7ca3bc58 | 660 | |
9a799d71 | 661 | /* RX */ |
46646e61 | 662 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
663 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
664 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 665 | u64 hw_csum_rx_error; |
e8e26350 | 666 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
667 | u64 rsc_total_count; |
668 | u64 rsc_total_flush; | |
9a799d71 | 669 | u64 non_eop_descs; |
9a799d71 AK |
670 | u32 alloc_rx_page_failed; |
671 | u32 alloc_rx_buff_failed; | |
672 | ||
49c7ffbe | 673 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 674 | |
46646e61 AD |
675 | /* DCB parameters */ |
676 | struct ieee_pfc *ixgbe_ieee_pfc; | |
677 | struct ieee_ets *ixgbe_ieee_ets; | |
678 | struct ixgbe_dcb_config dcb_cfg; | |
679 | struct ixgbe_dcb_config temp_dcb_cfg; | |
680 | u8 dcb_set_bitmap; | |
681 | u8 dcbx_cap; | |
682 | enum ixgbe_fc_mode last_lfc_mode; | |
683 | ||
49c7ffbe AD |
684 | int num_q_vectors; /* current number of q_vectors for device */ |
685 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
686 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
687 | struct msix_entry *msix_entries; | |
9a799d71 | 688 | |
da4dd0f7 PWJ |
689 | u32 test_icr; |
690 | struct ixgbe_ring test_tx_ring; | |
691 | struct ixgbe_ring test_rx_ring; | |
692 | ||
9a799d71 AK |
693 | /* structs defined in ixgbe_hw.h */ |
694 | struct ixgbe_hw hw; | |
695 | u16 msg_enable; | |
696 | struct ixgbe_hw_stats stats; | |
021230d4 | 697 | |
9a799d71 | 698 | u64 tx_busy; |
30efa5a3 JB |
699 | unsigned int tx_ring_count; |
700 | unsigned int rx_ring_count; | |
cf8280ee JB |
701 | |
702 | u32 link_speed; | |
703 | bool link_up; | |
704 | unsigned long link_check_timeout; | |
705 | ||
7086400d | 706 | struct timer_list service_timer; |
46646e61 AD |
707 | struct work_struct service_task; |
708 | ||
709 | struct hlist_head fdir_filter_list; | |
710 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
711 | union ixgbe_atr_input fdir_mask; | |
712 | int fdir_filter_count; | |
c4cf55e5 PWJ |
713 | u32 fdir_pballoc; |
714 | u32 atr_sample_rate; | |
715 | spinlock_t fdir_perfect_lock; | |
46646e61 | 716 | |
d0ed8937 YZ |
717 | #ifdef IXGBE_FCOE |
718 | struct ixgbe_fcoe fcoe; | |
719 | #endif /* IXGBE_FCOE */ | |
2a1a091c | 720 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
e8e26350 | 721 | u32 wol; |
46646e61 | 722 | |
15e5209f ET |
723 | u16 eeprom_verh; |
724 | u16 eeprom_verl; | |
c23f5b6b | 725 | u16 eeprom_cap; |
7f870475 | 726 | |
119fc60a | 727 | u32 interrupt_event; |
46646e61 | 728 | u32 led_reg; |
1a6c14a2 | 729 | |
3a6a4eda JK |
730 | struct ptp_clock *ptp_clock; |
731 | struct ptp_clock_info ptp_caps; | |
891dc082 JK |
732 | struct work_struct ptp_tx_work; |
733 | struct sk_buff *ptp_tx_skb; | |
93501d48 | 734 | struct hwtstamp_config tstamp_config; |
891dc082 | 735 | unsigned long ptp_tx_start; |
3a6a4eda | 736 | unsigned long last_overflow_check; |
6cb562d6 | 737 | unsigned long last_rx_ptp_check; |
eda183c2 | 738 | unsigned long last_rx_timestamp; |
3a6a4eda JK |
739 | spinlock_t tmreg_lock; |
740 | struct cyclecounter cc; | |
741 | struct timecounter tc; | |
742 | u32 base_incval; | |
3a6a4eda | 743 | |
7f870475 GR |
744 | /* SR-IOV */ |
745 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
746 | unsigned int num_vfs; | |
747 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 748 | int vf_rate_link_speed; |
a1cbb15c GR |
749 | struct vf_macvlans vf_mvs; |
750 | struct vf_macvlans *mv_list; | |
3e05334f | 751 | |
83c61fa9 GR |
752 | u32 timer_event_accumulator; |
753 | u32 vferr_refcount; | |
5d7daa35 | 754 | struct ixgbe_mac_addr *mac_table; |
3ca8bc6d DS |
755 | struct kobject *info_kobj; |
756 | #ifdef CONFIG_IXGBE_HWMON | |
03b77d81 | 757 | struct hwmon_buff *ixgbe_hwmon_buff; |
3ca8bc6d | 758 | #endif /* CONFIG_IXGBE_HWMON */ |
00949167 CS |
759 | #ifdef CONFIG_DEBUG_FS |
760 | struct dentry *ixgbe_dbg_adapter; | |
761 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
762 | |
763 | u8 default_up; | |
2a47fa45 | 764 | unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ |
3e05334f AD |
765 | }; |
766 | ||
767 | struct ixgbe_fdir_filter { | |
768 | struct hlist_node fdir_node; | |
769 | union ixgbe_atr_input filter; | |
770 | u16 sw_idx; | |
771 | u16 action; | |
9a799d71 AK |
772 | }; |
773 | ||
70e5576c | 774 | enum ixgbe_state_t { |
9a799d71 AK |
775 | __IXGBE_TESTING, |
776 | __IXGBE_RESETTING, | |
c4900be0 | 777 | __IXGBE_DOWN, |
41c62843 | 778 | __IXGBE_DISABLED, |
09f40aed | 779 | __IXGBE_REMOVING, |
7086400d | 780 | __IXGBE_SERVICE_SCHED, |
58cf663f | 781 | __IXGBE_SERVICE_INITED, |
7086400d | 782 | __IXGBE_IN_SFP_INIT, |
8fecf67c | 783 | __IXGBE_PTP_RUNNING, |
151b260c | 784 | __IXGBE_PTP_TX_IN_PROGRESS, |
9a799d71 AK |
785 | }; |
786 | ||
4c1975d7 AD |
787 | struct ixgbe_cb { |
788 | union { /* Union defining head/tail partner */ | |
789 | struct sk_buff *head; | |
790 | struct sk_buff *tail; | |
791 | }; | |
aa80175a | 792 | dma_addr_t dma; |
4c1975d7 | 793 | u16 append_cnt; |
f800326d | 794 | bool page_released; |
aa80175a | 795 | }; |
4c1975d7 | 796 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 797 | |
9a799d71 | 798 | enum ixgbe_boards { |
3957d63d | 799 | board_82598, |
e8e26350 | 800 | board_82599, |
fe15e8e1 | 801 | board_X540, |
9a799d71 AK |
802 | }; |
803 | ||
3957d63d | 804 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 805 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 806 | extern struct ixgbe_info ixgbe_X540_info; |
7a6b6f51 | 807 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 808 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 | 809 | #endif |
9a799d71 AK |
810 | |
811 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 812 | extern const char ixgbe_driver_version[]; |
8af3c33f | 813 | #ifdef IXGBE_FCOE |
ea81875a | 814 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 815 | #endif /* IXGBE_FCOE */ |
9a799d71 | 816 | |
5ccc921a JP |
817 | void ixgbe_up(struct ixgbe_adapter *adapter); |
818 | void ixgbe_down(struct ixgbe_adapter *adapter); | |
819 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); | |
820 | void ixgbe_reset(struct ixgbe_adapter *adapter); | |
821 | void ixgbe_set_ethtool_ops(struct net_device *netdev); | |
822 | int ixgbe_setup_rx_resources(struct ixgbe_ring *); | |
823 | int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
824 | void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
825 | void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
826 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
827 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
828 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); | |
829 | void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
830 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); | |
831 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
8e2813f5 | 832 | u16 subdevice_id); |
5d7daa35 JK |
833 | #ifdef CONFIG_PCI_IOV |
834 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); | |
835 | #endif | |
836 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, | |
837 | u8 *addr, u16 queue); | |
838 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, | |
839 | u8 *addr, u16 queue); | |
5ccc921a JP |
840 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
841 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, | |
842 | struct ixgbe_ring *); | |
843 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, | |
844 | struct ixgbe_tx_buffer *); | |
845 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); | |
846 | void ixgbe_write_eitr(struct ixgbe_q_vector *); | |
847 | int ixgbe_poll(struct napi_struct *napi, int budget); | |
848 | int ethtool_ioctl(struct ifreq *ifr); | |
849 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
850 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
851 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
852 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
853 | union ixgbe_atr_hash_dword input, | |
854 | union ixgbe_atr_hash_dword common, | |
855 | u8 queue); | |
856 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
857 | union ixgbe_atr_input *input_mask); | |
858 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
859 | union ixgbe_atr_input *input, | |
860 | u16 soft_id, u8 queue); | |
861 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
862 | union ixgbe_atr_input *input, | |
863 | u16 soft_id); | |
864 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
865 | union ixgbe_atr_input *mask); | |
5ccc921a | 866 | void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 867 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a | 868 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
8af3c33f | 869 | #endif |
5ccc921a JP |
870 | int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
871 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); | |
872 | void ixgbe_do_reset(struct net_device *netdev); | |
1210982b | 873 | #ifdef CONFIG_IXGBE_HWMON |
5ccc921a JP |
874 | void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
875 | int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 876 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 | 877 | #ifdef IXGBE_FCOE |
5ccc921a JP |
878 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); |
879 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, | |
880 | u8 *hdr_len); | |
881 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
882 | union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); | |
883 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
884 | struct scatterlist *sgl, unsigned int sgc); | |
885 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
886 | struct scatterlist *sgl, unsigned int sgc); | |
887 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
888 | int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
889 | void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
890 | int ixgbe_fcoe_enable(struct net_device *netdev); | |
891 | int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 | 892 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a JP |
893 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); |
894 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
6ee16520 | 895 | #endif /* CONFIG_IXGBE_DCB */ |
5ccc921a JP |
896 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
897 | int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, | |
898 | struct netdev_fcoe_hbainfo *info); | |
899 | u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); | |
eacd73f7 | 900 | #endif /* IXGBE_FCOE */ |
00949167 | 901 | #ifdef CONFIG_DEBUG_FS |
5ccc921a JP |
902 | void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); |
903 | void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
904 | void ixgbe_dbg_init(void); | |
905 | void ixgbe_dbg_exit(void); | |
33243fb0 JP |
906 | #else |
907 | static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} | |
908 | static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} | |
909 | static inline void ixgbe_dbg_init(void) {} | |
910 | static inline void ixgbe_dbg_exit(void) {} | |
00949167 | 911 | #endif /* CONFIG_DEBUG_FS */ |
b2d96e0a AD |
912 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
913 | { | |
914 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
915 | } | |
916 | ||
5ccc921a | 917 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter); |
9966d1ee | 918 | void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); |
5ccc921a JP |
919 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); |
920 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
921 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); | |
eda183c2 | 922 | void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb); |
93501d48 JK |
923 | int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); |
924 | int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); | |
5ccc921a JP |
925 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); |
926 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); | |
927 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); | |
da36b647 GR |
928 | #ifdef CONFIG_PCI_IOV |
929 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); | |
930 | #endif | |
3a6a4eda | 931 | |
2a47fa45 JF |
932 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
933 | struct ixgbe_adapter *adapter, | |
934 | struct ixgbe_ring *tx_ring); | |
9a799d71 | 935 | #endif /* _IXGBE_H_ */ |