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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
434c5e39 | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGBE_H_ | |
30 | #define _IXGBE_H_ | |
31 | ||
f62bbb5e | 32 | #include <linux/bitops.h> |
9a799d71 AK |
33 | #include <linux/types.h> |
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
b25ebfd2 | 36 | #include <linux/cpumask.h> |
6fabd715 | 37 | #include <linux/aer.h> |
f62bbb5e | 38 | #include <linux/if_vlan.h> |
6cb562d6 | 39 | #include <linux/jiffies.h> |
9a799d71 | 40 | |
74d23cc7 | 41 | #include <linux/timecounter.h> |
3a6a4eda JK |
42 | #include <linux/net_tstamp.h> |
43 | #include <linux/ptp_clock_kernel.h> | |
3a6a4eda | 44 | |
9a799d71 AK |
45 | #include "ixgbe_type.h" |
46 | #include "ixgbe_common.h" | |
2f90b865 | 47 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
48 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
49 | #define IXGBE_FCOE | |
50 | #include "ixgbe_fcoe.h" | |
51 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 52 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
53 | #include <linux/dca.h> |
54 | #endif | |
9a799d71 | 55 | |
076bb0c8 | 56 | #include <net/busy_poll.h> |
5a85e737 | 57 | |
e0d1095a | 58 | #ifdef CONFIG_NET_RX_BUSY_POLL |
b4640030 | 59 | #define BP_EXTENDED_STATS |
7e15b90f | 60 | #endif |
849c4542 ET |
61 | /* common prefix used by pr_<> macros */ |
62 | #undef pr_fmt | |
63 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
64 | |
65 | /* TX/RX descriptor defines */ | |
6bacb300 | 66 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 67 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
68 | #define IXGBE_MAX_TXD 4096 |
69 | #define IXGBE_MIN_TXD 64 | |
70 | ||
fb44519d | 71 | #if (PAGE_SIZE < 8192) |
6bacb300 | 72 | #define IXGBE_DEFAULT_RXD 512 |
fb44519d AB |
73 | #else |
74 | #define IXGBE_DEFAULT_RXD 128 | |
75 | #endif | |
9a799d71 AK |
76 | #define IXGBE_MAX_RXD 4096 |
77 | #define IXGBE_MIN_RXD 64 | |
78 | ||
5b7f000f DS |
79 | #define IXGBE_ETH_P_LLDP 0x88CC |
80 | ||
9a799d71 | 81 | /* flow control */ |
2b9ade93 | 82 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 83 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 84 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 85 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 86 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
87 | #define IXGBE_MIN_FCPAUSE 0 |
88 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
89 | ||
90 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 91 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
92 | #define IXGBE_RXBUFFER_2K 2048 |
93 | #define IXGBE_RXBUFFER_3K 3072 | |
94 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 95 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 96 | |
13958070 | 97 | /* |
252562c2 AD |
98 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
99 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
100 | * this adds up to 448 bytes of extra data. | |
101 | * | |
102 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
103 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 104 | */ |
252562c2 | 105 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 | 106 | |
9a799d71 AK |
107 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
108 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
109 | ||
472148c3 AD |
110 | enum ixgbe_tx_flags { |
111 | /* cmd_type flags */ | |
112 | IXGBE_TX_FLAGS_HW_VLAN = 0x01, | |
113 | IXGBE_TX_FLAGS_TSO = 0x02, | |
114 | IXGBE_TX_FLAGS_TSTAMP = 0x04, | |
115 | ||
116 | /* olinfo flags */ | |
117 | IXGBE_TX_FLAGS_CC = 0x08, | |
118 | IXGBE_TX_FLAGS_IPV4 = 0x10, | |
119 | IXGBE_TX_FLAGS_CSUM = 0x20, | |
120 | ||
121 | /* software defined flags */ | |
122 | IXGBE_TX_FLAGS_SW_VLAN = 0x40, | |
123 | IXGBE_TX_FLAGS_FCOE = 0x80, | |
124 | }; | |
125 | ||
126 | /* VLAN info */ | |
9a799d71 | 127 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
128 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
129 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
130 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
131 | ||
7f870475 GR |
132 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
133 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
134 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
135 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 136 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 137 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
138 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
139 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
140 | |
141 | struct vf_data_storage { | |
142 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
143 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
144 | u16 num_vf_mc_hashes; | |
145 | u16 default_vf_vlan_id; | |
146 | u16 vlans_enabled; | |
7f870475 | 147 | bool clear_to_send; |
7f01648a | 148 | bool pf_set_mac; |
7f01648a GR |
149 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
150 | u16 pf_qos; | |
ff4ab206 | 151 | u16 tx_rate; |
de4c7f65 GR |
152 | u16 vlan_count; |
153 | u8 spoofchk_enabled; | |
e65ce0d3 | 154 | bool rss_query_enabled; |
54011e4d | 155 | u8 trusted; |
8443c1a4 | 156 | int xcast_mode; |
374c65d6 | 157 | unsigned int vf_api; |
7f870475 GR |
158 | }; |
159 | ||
8443c1a4 HS |
160 | enum ixgbevf_xcast_modes { |
161 | IXGBEVF_XCAST_MODE_NONE = 0, | |
162 | IXGBEVF_XCAST_MODE_MULTI, | |
163 | IXGBEVF_XCAST_MODE_ALLMULTI, | |
164 | }; | |
165 | ||
a1cbb15c GR |
166 | struct vf_macvlans { |
167 | struct list_head l; | |
168 | int vf; | |
a1cbb15c GR |
169 | bool free; |
170 | bool is_macvlan; | |
171 | u8 vf_macvlan[ETH_ALEN]; | |
172 | }; | |
173 | ||
a535c30e AD |
174 | #define IXGBE_MAX_TXD_PWR 14 |
175 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
176 | ||
177 | /* Tx Descriptors needed, worst case */ | |
178 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
990a3158 | 179 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
a535c30e | 180 | |
9a799d71 AK |
181 | /* wrapper around a pointer to a socket buffer, |
182 | * so a DMA handle can be stored along with the buffer */ | |
183 | struct ixgbe_tx_buffer { | |
d3d00239 | 184 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 185 | unsigned long time_stamp; |
fd0db0ed AD |
186 | struct sk_buff *skb; |
187 | unsigned int bytecount; | |
188 | unsigned short gso_segs; | |
244e27ad | 189 | __be16 protocol; |
729739b7 AD |
190 | DEFINE_DMA_UNMAP_ADDR(dma); |
191 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 192 | u32 tx_flags; |
9a799d71 AK |
193 | }; |
194 | ||
195 | struct ixgbe_rx_buffer { | |
196 | struct sk_buff *skb; | |
197 | dma_addr_t dma; | |
198 | struct page *page; | |
762f4c57 | 199 | unsigned int page_offset; |
9a799d71 AK |
200 | }; |
201 | ||
202 | struct ixgbe_queue_stats { | |
203 | u64 packets; | |
204 | u64 bytes; | |
b4640030 | 205 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
206 | u64 yields; |
207 | u64 misses; | |
208 | u64 cleaned; | |
b4640030 | 209 | #endif /* BP_EXTENDED_STATS */ |
9a799d71 AK |
210 | }; |
211 | ||
5b7da515 AD |
212 | struct ixgbe_tx_queue_stats { |
213 | u64 restart_queue; | |
214 | u64 tx_busy; | |
c84d324c | 215 | u64 tx_done_old; |
5b7da515 AD |
216 | }; |
217 | ||
218 | struct ixgbe_rx_queue_stats { | |
219 | u64 rsc_count; | |
220 | u64 rsc_flush; | |
221 | u64 non_eop_descs; | |
222 | u64 alloc_rx_page_failed; | |
223 | u64 alloc_rx_buff_failed; | |
8a0da21b | 224 | u64 csum_err; |
5b7da515 AD |
225 | }; |
226 | ||
a9763f3c MR |
227 | #define IXGBE_TS_HDR_LEN 8 |
228 | ||
f800326d | 229 | enum ixgbe_ring_state_t { |
7d637bcc | 230 | __IXGBE_TX_FDIR_INIT_DONE, |
fd786b7b | 231 | __IXGBE_TX_XPS_INIT_DONE, |
7d637bcc | 232 | __IXGBE_TX_DETECT_HANG, |
c84d324c | 233 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 234 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 235 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
57efd44c | 236 | __IXGBE_RX_FCOE, |
7d637bcc AD |
237 | }; |
238 | ||
2a47fa45 JF |
239 | struct ixgbe_fwd_adapter { |
240 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
241 | struct net_device *netdev; | |
242 | struct ixgbe_adapter *real_adapter; | |
243 | unsigned int tx_base_queue; | |
244 | unsigned int rx_base_queue; | |
245 | int pool; | |
246 | }; | |
247 | ||
7d637bcc AD |
248 | #define check_for_tx_hang(ring) \ |
249 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
250 | #define set_check_for_tx_hang(ring) \ | |
251 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
252 | #define clear_check_for_tx_hang(ring) \ | |
253 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
254 | #define ring_is_rsc_enabled(ring) \ | |
255 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
256 | #define set_ring_rsc_enabled(ring) \ | |
257 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
258 | #define clear_ring_rsc_enabled(ring) \ | |
259 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 260 | struct ixgbe_ring { |
efe3d3c8 | 261 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
262 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
263 | struct net_device *netdev; /* netdev ring belongs to */ | |
264 | struct device *dev; /* device for DMA mapping */ | |
2a47fa45 | 265 | struct ixgbe_fwd_adapter *l2_accel_priv; |
9a799d71 | 266 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
267 | union { |
268 | struct ixgbe_tx_buffer *tx_buffer_info; | |
269 | struct ixgbe_rx_buffer *rx_buffer_info; | |
270 | }; | |
7d637bcc | 271 | unsigned long state; |
bd198058 | 272 | u8 __iomem *tail; |
d3ee4294 AD |
273 | dma_addr_t dma; /* phys. address of descriptor ring */ |
274 | unsigned int size; /* length in bytes */ | |
bd198058 | 275 | |
ae540af1 | 276 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
277 | |
278 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
279 | u8 reg_idx; /* holds the special value that gets |
280 | * the hardware register offset | |
281 | * associated with this ring, which is | |
282 | * different for DCB and RSS modes | |
283 | */ | |
d3ee4294 AD |
284 | u16 next_to_use; |
285 | u16 next_to_clean; | |
286 | ||
a9763f3c MR |
287 | unsigned long last_rx_timestamp; |
288 | ||
f800326d | 289 | union { |
d3ee4294 | 290 | u16 next_to_alloc; |
f800326d AD |
291 | struct { |
292 | u8 atr_sample_rate; | |
293 | u8 atr_count; | |
294 | }; | |
f800326d | 295 | }; |
9a799d71 | 296 | |
bd198058 | 297 | u8 dcb_tc; |
9a799d71 | 298 | struct ixgbe_queue_stats stats; |
de1036b1 | 299 | struct u64_stats_sync syncp; |
5b7da515 AD |
300 | union { |
301 | struct ixgbe_tx_queue_stats tx_stats; | |
302 | struct ixgbe_rx_queue_stats rx_stats; | |
303 | }; | |
7ca3bc58 | 304 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 305 | |
c7e4358a SN |
306 | enum ixgbe_ring_f_enum { |
307 | RING_F_NONE = 0, | |
7f870475 | 308 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 309 | RING_F_RSS, |
c4cf55e5 | 310 | RING_F_FDIR, |
0331a832 YZ |
311 | #ifdef IXGBE_FCOE |
312 | RING_F_FCOE, | |
313 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
314 | |
315 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
316 | }; | |
317 | ||
0f9b232b DS |
318 | #define IXGBE_MAX_RSS_INDICES 16 |
319 | #define IXGBE_MAX_RSS_INDICES_X550 64 | |
320 | #define IXGBE_MAX_VMDQ_INDICES 64 | |
321 | #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ | |
322 | #define IXGBE_MAX_FCOE_INDICES 8 | |
323 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
324 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
325 | #define IXGBE_MAX_L2A_QUEUES 4 | |
326 | #define IXGBE_BAD_L2A_QUEUE 3 | |
327 | #define IXGBE_MAX_MACVLANS 31 | |
328 | #define IXGBE_MAX_DCBMACVLANS 8 | |
2a47fa45 | 329 | |
021230d4 | 330 | struct ixgbe_ring_feature { |
c087663e AD |
331 | u16 limit; /* upper limit on feature indices */ |
332 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
333 | u16 mask; /* Mask used for feature to ring mapping */ |
334 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 335 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 336 | |
73079ea0 AD |
337 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
338 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
339 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
340 | ||
f800326d AD |
341 | /* |
342 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
343 | * this is twice the size of a half page we need to double the page order | |
344 | * for FCoE enabled Rx queues. | |
345 | */ | |
09816fbe | 346 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 347 | { |
09816fbe AD |
348 | #ifdef IXGBE_FCOE |
349 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
350 | return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : | |
351 | IXGBE_RXBUFFER_3K; | |
352 | #endif | |
353 | return IXGBE_RXBUFFER_2K; | |
f800326d | 354 | } |
09816fbe AD |
355 | |
356 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
357 | { | |
358 | #ifdef IXGBE_FCOE | |
359 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
360 | return (PAGE_SIZE < 8192) ? 1 : 0; | |
f800326d | 361 | #endif |
09816fbe AD |
362 | return 0; |
363 | } | |
f800326d | 364 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 365 | |
08c8833b | 366 | struct ixgbe_ring_container { |
efe3d3c8 | 367 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
368 | unsigned int total_bytes; /* total bytes processed this int */ |
369 | unsigned int total_packets; /* total packets processed this int */ | |
370 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
371 | u8 count; /* total number of rings in vector */ |
372 | u8 itr; /* current ITR setting for ring */ | |
373 | }; | |
021230d4 | 374 | |
a557928e AD |
375 | /* iterator for handling rings in ring container */ |
376 | #define ixgbe_for_each_ring(pos, head) \ | |
377 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
378 | ||
2f90b865 | 379 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
e7cf745b | 380 | ? 8 : 1) |
2f90b865 AD |
381 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS |
382 | ||
49c7ffbe | 383 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
384 | * but we only use one per queue-specific vector. |
385 | */ | |
386 | struct ixgbe_q_vector { | |
387 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
388 | #ifdef CONFIG_IXGBE_DCA |
389 | int cpu; /* CPU for DCA */ | |
390 | #endif | |
d5bf4f67 ET |
391 | u16 v_idx; /* index of q_vector within array, also used for |
392 | * finding the bit in EICR and friends that | |
393 | * represents the vector for this ring */ | |
394 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 395 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
396 | |
397 | struct napi_struct napi; | |
de88eeeb AD |
398 | cpumask_t affinity_mask; |
399 | int numa_node; | |
400 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 401 | char name[IFNAMSIZ + 9]; |
de88eeeb | 402 | |
e0d1095a | 403 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 | 404 | atomic_t state; |
e0d1095a | 405 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 406 | |
de88eeeb AD |
407 | /* for dynamic allocation of rings associated with this q_vector */ |
408 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 409 | }; |
adc81090 | 410 | |
e0d1095a | 411 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 AD |
412 | enum ixgbe_qv_state_t { |
413 | IXGBE_QV_STATE_IDLE = 0, | |
414 | IXGBE_QV_STATE_NAPI, | |
415 | IXGBE_QV_STATE_POLL, | |
416 | IXGBE_QV_STATE_DISABLE | |
417 | }; | |
418 | ||
5a85e737 ET |
419 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
420 | { | |
adc81090 AD |
421 | /* reset state to idle */ |
422 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
423 | } |
424 | ||
425 | /* called from the device poll routine to get ownership of a q_vector */ | |
426 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
427 | { | |
adc81090 AD |
428 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
429 | IXGBE_QV_STATE_NAPI); | |
b4640030 | 430 | #ifdef BP_EXTENDED_STATS |
adc81090 | 431 | if (rc != IXGBE_QV_STATE_IDLE) |
7e15b90f ET |
432 | q_vector->tx.ring->stats.yields++; |
433 | #endif | |
adc81090 AD |
434 | |
435 | return rc == IXGBE_QV_STATE_IDLE; | |
5a85e737 ET |
436 | } |
437 | ||
438 | /* returns true is someone tried to get the qv while napi had it */ | |
adc81090 | 439 | static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) |
5a85e737 | 440 | { |
adc81090 AD |
441 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); |
442 | ||
443 | /* flush any outstanding Rx frames */ | |
444 | if (q_vector->napi.gro_list) | |
445 | napi_gro_flush(&q_vector->napi, false); | |
446 | ||
447 | /* reset state to idle */ | |
448 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
449 | } |
450 | ||
451 | /* called from ixgbe_low_latency_poll() */ | |
452 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
453 | { | |
adc81090 AD |
454 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
455 | IXGBE_QV_STATE_POLL); | |
b4640030 | 456 | #ifdef BP_EXTENDED_STATS |
adc81090 AD |
457 | if (rc != IXGBE_QV_STATE_IDLE) |
458 | q_vector->tx.ring->stats.yields++; | |
7e15b90f | 459 | #endif |
adc81090 | 460 | return rc == IXGBE_QV_STATE_IDLE; |
5a85e737 ET |
461 | } |
462 | ||
463 | /* returns true if someone tried to get the qv while it was locked */ | |
adc81090 | 464 | static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) |
5a85e737 | 465 | { |
adc81090 AD |
466 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); |
467 | ||
468 | /* reset state to idle */ | |
469 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
470 | } |
471 | ||
472 | /* true if a socket is polling, even if it did not get the lock */ | |
b4640030 | 473 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 | 474 | { |
adc81090 | 475 | return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; |
5a85e737 | 476 | } |
27d9ce4f JK |
477 | |
478 | /* false if QV is currently owned */ | |
479 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
480 | { | |
adc81090 AD |
481 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
482 | IXGBE_QV_STATE_DISABLE); | |
483 | ||
484 | return rc == IXGBE_QV_STATE_IDLE; | |
27d9ce4f JK |
485 | } |
486 | ||
e0d1095a | 487 | #else /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 ET |
488 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
489 | { | |
490 | } | |
491 | ||
492 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
493 | { | |
494 | return true; | |
495 | } | |
496 | ||
497 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
498 | { | |
499 | return false; | |
500 | } | |
501 | ||
502 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
503 | { | |
504 | return false; | |
505 | } | |
506 | ||
507 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
508 | { | |
509 | return false; | |
510 | } | |
511 | ||
b4640030 | 512 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 ET |
513 | { |
514 | return false; | |
515 | } | |
27d9ce4f JK |
516 | |
517 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
518 | { | |
519 | return true; | |
520 | } | |
521 | ||
e0d1095a | 522 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 523 | |
3ca8bc6d DS |
524 | #ifdef CONFIG_IXGBE_HWMON |
525 | ||
526 | #define IXGBE_HWMON_TYPE_LOC 0 | |
527 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
528 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
529 | #define IXGBE_HWMON_TYPE_MAX 3 | |
530 | ||
531 | struct hwmon_attr { | |
532 | struct device_attribute dev_attr; | |
533 | struct ixgbe_hw *hw; | |
534 | struct ixgbe_thermal_diode_data *sensor; | |
535 | char name[12]; | |
536 | }; | |
537 | ||
538 | struct hwmon_buff { | |
03b77d81 GR |
539 | struct attribute_group group; |
540 | const struct attribute_group *groups[2]; | |
541 | struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; | |
542 | struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; | |
3ca8bc6d DS |
543 | unsigned int n_hwmon; |
544 | }; | |
545 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 546 | |
d5bf4f67 ET |
547 | /* |
548 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
549 | * with the first 3 bits reserved 0 | |
9a799d71 | 550 | */ |
d5bf4f67 ET |
551 | #define IXGBE_MIN_RSC_ITR 24 |
552 | #define IXGBE_100K_ITR 40 | |
553 | #define IXGBE_20K_ITR 200 | |
8ac34f10 | 554 | #define IXGBE_12K_ITR 336 |
9a799d71 | 555 | |
f56e0cb1 AD |
556 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
557 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
558 | const u32 stat_err_bits) | |
559 | { | |
560 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
561 | } | |
562 | ||
7d4987de AD |
563 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
564 | { | |
565 | u16 ntc = ring->next_to_clean; | |
566 | u16 ntu = ring->next_to_use; | |
567 | ||
568 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
569 | } | |
9a799d71 | 570 | |
e4f74028 | 571 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 572 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 573 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 574 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 575 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 576 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 577 | |
c88887e0 | 578 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
579 | #ifdef IXGBE_FCOE |
580 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
581 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
582 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 583 | |
021230d4 AV |
584 | #define OTHER_VECTOR 1 |
585 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
586 | ||
e8e26350 | 587 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 588 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 589 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 590 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 591 | |
5d7daa35 JK |
592 | struct ixgbe_mac_addr { |
593 | u8 addr[ETH_ALEN]; | |
c9f53e63 | 594 | u16 pool; |
5d7daa35 JK |
595 | u16 state; /* bitmask */ |
596 | }; | |
c9f53e63 | 597 | |
5d7daa35 JK |
598 | #define IXGBE_MAC_STATE_DEFAULT 0x1 |
599 | #define IXGBE_MAC_STATE_MODIFIED 0x2 | |
600 | #define IXGBE_MAC_STATE_IN_USE 0x4 | |
601 | ||
49c7ffbe | 602 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 603 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 604 | |
8f15486d | 605 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
606 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
607 | ||
46646e61 AD |
608 | /* default to trying for four seconds */ |
609 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
58e7cd24 | 610 | #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ |
46646e61 | 611 | |
9a799d71 AK |
612 | /* board specific private data structure */ |
613 | struct ixgbe_adapter { | |
46646e61 AD |
614 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
615 | /* OS defined structs */ | |
616 | struct net_device *netdev; | |
617 | struct pci_dev *pdev; | |
618 | ||
e606bfe7 AD |
619 | unsigned long state; |
620 | ||
621 | /* Some features need tri-state capability, | |
622 | * thus the additional *_CAPABLE flags. | |
623 | */ | |
624 | u32 flags; | |
a16a0d2f | 625 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) |
a16a0d2f AD |
626 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) |
627 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) | |
628 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) | |
629 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) | |
a16a0d2f AD |
630 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) |
631 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) | |
632 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) | |
633 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) | |
634 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) | |
635 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) | |
636 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) | |
637 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) | |
638 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) | |
639 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) | |
640 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) | |
641 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) | |
642 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) | |
643 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) | |
644 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) | |
645 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) | |
67359c3c | 646 | #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) |
a9763f3c MR |
647 | #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) |
648 | #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) | |
e606bfe7 AD |
649 | |
650 | u32 flags2; | |
a16a0d2f | 651 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) |
e606bfe7 AD |
652 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) |
653 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 654 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
655 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
656 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 657 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 658 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
ef6afc0c AD |
659 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) |
660 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) | |
8fecf67c | 661 | #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) |
597f22d6 | 662 | #define IXGBE_FLAG2_PHY_INTERRUPT (u32)(1 << 11) |
67359c3c MR |
663 | #ifdef CONFIG_IXGBE_VXLAN |
664 | #define IXGBE_FLAG2_VXLAN_REREG_NEEDED BIT(12) | |
665 | #endif | |
d033d526 | 666 | |
46646e61 AD |
667 | /* Tx fast path data */ |
668 | int num_tx_queues; | |
669 | u16 tx_itr_setting; | |
bd198058 AD |
670 | u16 tx_work_limit; |
671 | ||
46646e61 AD |
672 | /* Rx fast path data */ |
673 | int num_rx_queues; | |
674 | u16 rx_itr_setting; | |
675 | ||
9a799d71 | 676 | /* TX */ |
4a0b9ca0 | 677 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 678 | |
7ca3bc58 JB |
679 | u64 restart_queue; |
680 | u64 lsc_int; | |
46646e61 | 681 | u32 tx_timeout_count; |
7ca3bc58 | 682 | |
9a799d71 | 683 | /* RX */ |
46646e61 | 684 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
685 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
686 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 687 | u64 hw_csum_rx_error; |
e8e26350 | 688 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
689 | u64 rsc_total_count; |
690 | u64 rsc_total_flush; | |
9a799d71 | 691 | u64 non_eop_descs; |
9a799d71 AK |
692 | u32 alloc_rx_page_failed; |
693 | u32 alloc_rx_buff_failed; | |
694 | ||
49c7ffbe | 695 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 696 | |
46646e61 AD |
697 | /* DCB parameters */ |
698 | struct ieee_pfc *ixgbe_ieee_pfc; | |
699 | struct ieee_ets *ixgbe_ieee_ets; | |
700 | struct ixgbe_dcb_config dcb_cfg; | |
701 | struct ixgbe_dcb_config temp_dcb_cfg; | |
702 | u8 dcb_set_bitmap; | |
703 | u8 dcbx_cap; | |
704 | enum ixgbe_fc_mode last_lfc_mode; | |
705 | ||
49c7ffbe AD |
706 | int num_q_vectors; /* current number of q_vectors for device */ |
707 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
708 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
709 | struct msix_entry *msix_entries; | |
9a799d71 | 710 | |
da4dd0f7 PWJ |
711 | u32 test_icr; |
712 | struct ixgbe_ring test_tx_ring; | |
713 | struct ixgbe_ring test_rx_ring; | |
714 | ||
9a799d71 AK |
715 | /* structs defined in ixgbe_hw.h */ |
716 | struct ixgbe_hw hw; | |
717 | u16 msg_enable; | |
718 | struct ixgbe_hw_stats stats; | |
021230d4 | 719 | |
9a799d71 | 720 | u64 tx_busy; |
30efa5a3 JB |
721 | unsigned int tx_ring_count; |
722 | unsigned int rx_ring_count; | |
cf8280ee JB |
723 | |
724 | u32 link_speed; | |
725 | bool link_up; | |
58e7cd24 | 726 | unsigned long sfp_poll_time; |
cf8280ee JB |
727 | unsigned long link_check_timeout; |
728 | ||
7086400d | 729 | struct timer_list service_timer; |
46646e61 AD |
730 | struct work_struct service_task; |
731 | ||
732 | struct hlist_head fdir_filter_list; | |
733 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
734 | union ixgbe_atr_input fdir_mask; | |
735 | int fdir_filter_count; | |
c4cf55e5 PWJ |
736 | u32 fdir_pballoc; |
737 | u32 atr_sample_rate; | |
738 | spinlock_t fdir_perfect_lock; | |
46646e61 | 739 | |
d0ed8937 YZ |
740 | #ifdef IXGBE_FCOE |
741 | struct ixgbe_fcoe fcoe; | |
742 | #endif /* IXGBE_FCOE */ | |
2a1a091c | 743 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
e8e26350 | 744 | u32 wol; |
46646e61 | 745 | |
aa2bacb6 DS |
746 | u16 bridge_mode; |
747 | ||
15e5209f ET |
748 | u16 eeprom_verh; |
749 | u16 eeprom_verl; | |
c23f5b6b | 750 | u16 eeprom_cap; |
7f870475 | 751 | |
119fc60a | 752 | u32 interrupt_event; |
46646e61 | 753 | u32 led_reg; |
1a6c14a2 | 754 | |
3a6a4eda JK |
755 | struct ptp_clock *ptp_clock; |
756 | struct ptp_clock_info ptp_caps; | |
891dc082 JK |
757 | struct work_struct ptp_tx_work; |
758 | struct sk_buff *ptp_tx_skb; | |
93501d48 | 759 | struct hwtstamp_config tstamp_config; |
891dc082 | 760 | unsigned long ptp_tx_start; |
3a6a4eda | 761 | unsigned long last_overflow_check; |
6cb562d6 | 762 | unsigned long last_rx_ptp_check; |
eda183c2 | 763 | unsigned long last_rx_timestamp; |
3a6a4eda | 764 | spinlock_t tmreg_lock; |
a9763f3c MR |
765 | struct cyclecounter hw_cc; |
766 | struct timecounter hw_tc; | |
3a6a4eda | 767 | u32 base_incval; |
a9763f3c MR |
768 | u32 tx_hwtstamp_timeouts; |
769 | u32 rx_hwtstamp_cleared; | |
770 | void (*ptp_setup_sdp)(struct ixgbe_adapter *); | |
3a6a4eda | 771 | |
7f870475 GR |
772 | /* SR-IOV */ |
773 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
774 | unsigned int num_vfs; | |
775 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 776 | int vf_rate_link_speed; |
a1cbb15c GR |
777 | struct vf_macvlans vf_mvs; |
778 | struct vf_macvlans *mv_list; | |
3e05334f | 779 | |
83c61fa9 GR |
780 | u32 timer_event_accumulator; |
781 | u32 vferr_refcount; | |
5d7daa35 | 782 | struct ixgbe_mac_addr *mac_table; |
67359c3c | 783 | #ifdef CONFIG_IXGBE_VXLAN |
3f207800 | 784 | u16 vxlan_port; |
67359c3c | 785 | #endif |
3ca8bc6d DS |
786 | struct kobject *info_kobj; |
787 | #ifdef CONFIG_IXGBE_HWMON | |
03b77d81 | 788 | struct hwmon_buff *ixgbe_hwmon_buff; |
3ca8bc6d | 789 | #endif /* CONFIG_IXGBE_HWMON */ |
00949167 CS |
790 | #ifdef CONFIG_DEBUG_FS |
791 | struct dentry *ixgbe_dbg_adapter; | |
792 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
793 | |
794 | u8 default_up; | |
2a47fa45 | 795 | unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ |
dfaf891d VZ |
796 | |
797 | /* maximum number of RETA entries among all devices supported by ixgbe | |
798 | * driver: currently it's x550 device in non-SRIOV mode | |
799 | */ | |
800 | #define IXGBE_MAX_RETA_ENTRIES 512 | |
801 | u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; | |
802 | ||
803 | #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ | |
804 | u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)]; | |
3e05334f AD |
805 | }; |
806 | ||
0f9b232b DS |
807 | static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) |
808 | { | |
809 | switch (adapter->hw.mac.type) { | |
810 | case ixgbe_mac_82598EB: | |
811 | case ixgbe_mac_82599EB: | |
812 | case ixgbe_mac_X540: | |
813 | return IXGBE_MAX_RSS_INDICES; | |
814 | case ixgbe_mac_X550: | |
815 | case ixgbe_mac_X550EM_x: | |
816 | return IXGBE_MAX_RSS_INDICES_X550; | |
817 | default: | |
818 | return 0; | |
819 | } | |
820 | } | |
821 | ||
3e05334f AD |
822 | struct ixgbe_fdir_filter { |
823 | struct hlist_node fdir_node; | |
824 | union ixgbe_atr_input filter; | |
825 | u16 sw_idx; | |
826 | u16 action; | |
9a799d71 AK |
827 | }; |
828 | ||
70e5576c | 829 | enum ixgbe_state_t { |
9a799d71 AK |
830 | __IXGBE_TESTING, |
831 | __IXGBE_RESETTING, | |
c4900be0 | 832 | __IXGBE_DOWN, |
41c62843 | 833 | __IXGBE_DISABLED, |
09f40aed | 834 | __IXGBE_REMOVING, |
7086400d | 835 | __IXGBE_SERVICE_SCHED, |
58cf663f | 836 | __IXGBE_SERVICE_INITED, |
7086400d | 837 | __IXGBE_IN_SFP_INIT, |
8fecf67c | 838 | __IXGBE_PTP_RUNNING, |
151b260c | 839 | __IXGBE_PTP_TX_IN_PROGRESS, |
9a799d71 AK |
840 | }; |
841 | ||
4c1975d7 AD |
842 | struct ixgbe_cb { |
843 | union { /* Union defining head/tail partner */ | |
844 | struct sk_buff *head; | |
845 | struct sk_buff *tail; | |
846 | }; | |
aa80175a | 847 | dma_addr_t dma; |
4c1975d7 | 848 | u16 append_cnt; |
f800326d | 849 | bool page_released; |
aa80175a | 850 | }; |
4c1975d7 | 851 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 852 | |
9a799d71 | 853 | enum ixgbe_boards { |
3957d63d | 854 | board_82598, |
e8e26350 | 855 | board_82599, |
fe15e8e1 | 856 | board_X540, |
6a14ee0c DS |
857 | board_X550, |
858 | board_X550EM_x, | |
9a799d71 AK |
859 | }; |
860 | ||
3957d63d | 861 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 862 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 863 | extern struct ixgbe_info ixgbe_X540_info; |
6a14ee0c DS |
864 | extern struct ixgbe_info ixgbe_X550_info; |
865 | extern struct ixgbe_info ixgbe_X550EM_x_info; | |
7a6b6f51 | 866 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 867 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 | 868 | #endif |
9a799d71 AK |
869 | |
870 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 871 | extern const char ixgbe_driver_version[]; |
8af3c33f | 872 | #ifdef IXGBE_FCOE |
ea81875a | 873 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 874 | #endif /* IXGBE_FCOE */ |
9a799d71 | 875 | |
5ccc921a JP |
876 | void ixgbe_up(struct ixgbe_adapter *adapter); |
877 | void ixgbe_down(struct ixgbe_adapter *adapter); | |
878 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); | |
879 | void ixgbe_reset(struct ixgbe_adapter *adapter); | |
880 | void ixgbe_set_ethtool_ops(struct net_device *netdev); | |
881 | int ixgbe_setup_rx_resources(struct ixgbe_ring *); | |
882 | int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
883 | void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
884 | void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
885 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
886 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
887 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); | |
888 | void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
889 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); | |
890 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
8e2813f5 | 891 | u16 subdevice_id); |
5d7daa35 JK |
892 | #ifdef CONFIG_PCI_IOV |
893 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); | |
894 | #endif | |
895 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, | |
c9f53e63 | 896 | const u8 *addr, u16 queue); |
5d7daa35 | 897 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, |
c9f53e63 | 898 | const u8 *addr, u16 queue); |
5ccc921a JP |
899 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
900 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, | |
901 | struct ixgbe_ring *); | |
902 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, | |
903 | struct ixgbe_tx_buffer *); | |
904 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); | |
905 | void ixgbe_write_eitr(struct ixgbe_q_vector *); | |
906 | int ixgbe_poll(struct napi_struct *napi, int budget); | |
907 | int ethtool_ioctl(struct ifreq *ifr); | |
908 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
909 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
910 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
911 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
912 | union ixgbe_atr_hash_dword input, | |
913 | union ixgbe_atr_hash_dword common, | |
914 | u8 queue); | |
915 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
916 | union ixgbe_atr_input *input_mask); | |
917 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
918 | union ixgbe_atr_input *input, | |
919 | u16 soft_id, u8 queue); | |
920 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
921 | union ixgbe_atr_input *input, | |
922 | u16 soft_id); | |
923 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
924 | union ixgbe_atr_input *mask); | |
5ccc921a | 925 | void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 926 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a | 927 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
8af3c33f | 928 | #endif |
5ccc921a JP |
929 | int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
930 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); | |
931 | void ixgbe_do_reset(struct net_device *netdev); | |
1210982b | 932 | #ifdef CONFIG_IXGBE_HWMON |
5ccc921a JP |
933 | void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
934 | int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 935 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 | 936 | #ifdef IXGBE_FCOE |
5ccc921a JP |
937 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); |
938 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, | |
939 | u8 *hdr_len); | |
940 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
941 | union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); | |
942 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
943 | struct scatterlist *sgl, unsigned int sgc); | |
944 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
945 | struct scatterlist *sgl, unsigned int sgc); | |
946 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
947 | int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
948 | void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
949 | int ixgbe_fcoe_enable(struct net_device *netdev); | |
950 | int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 | 951 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a JP |
952 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); |
953 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
6ee16520 | 954 | #endif /* CONFIG_IXGBE_DCB */ |
5ccc921a JP |
955 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
956 | int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, | |
957 | struct netdev_fcoe_hbainfo *info); | |
958 | u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); | |
eacd73f7 | 959 | #endif /* IXGBE_FCOE */ |
00949167 | 960 | #ifdef CONFIG_DEBUG_FS |
5ccc921a JP |
961 | void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); |
962 | void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
963 | void ixgbe_dbg_init(void); | |
964 | void ixgbe_dbg_exit(void); | |
33243fb0 JP |
965 | #else |
966 | static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} | |
967 | static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} | |
968 | static inline void ixgbe_dbg_init(void) {} | |
969 | static inline void ixgbe_dbg_exit(void) {} | |
00949167 | 970 | #endif /* CONFIG_DEBUG_FS */ |
b2d96e0a AD |
971 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
972 | { | |
973 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
974 | } | |
975 | ||
5ccc921a | 976 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter); |
9966d1ee | 977 | void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); |
5ccc921a JP |
978 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); |
979 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
980 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); | |
a9763f3c MR |
981 | void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); |
982 | void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); | |
983 | static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, | |
984 | union ixgbe_adv_rx_desc *rx_desc, | |
985 | struct sk_buff *skb) | |
986 | { | |
987 | if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { | |
988 | ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); | |
989 | return; | |
990 | } | |
991 | ||
992 | if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) | |
993 | return; | |
994 | ||
995 | ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); | |
996 | ||
997 | /* Update the last_rx_timestamp timer in order to enable watchdog check | |
998 | * for error case of latched timestamp on a dropped packet. | |
999 | */ | |
1000 | rx_ring->last_rx_timestamp = jiffies; | |
1001 | } | |
1002 | ||
93501d48 JK |
1003 | int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); |
1004 | int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); | |
5ccc921a JP |
1005 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); |
1006 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); | |
a9763f3c | 1007 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); |
da36b647 GR |
1008 | #ifdef CONFIG_PCI_IOV |
1009 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); | |
1010 | #endif | |
3a6a4eda | 1011 | |
2a47fa45 JF |
1012 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
1013 | struct ixgbe_adapter *adapter, | |
1014 | struct ixgbe_ring *tx_ring); | |
7f276efb | 1015 | u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); |
1c7cf078 | 1016 | void ixgbe_store_reta(struct ixgbe_adapter *adapter); |
9a799d71 | 1017 | #endif /* _IXGBE_H_ */ |