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ixgbe: Fix bogus error message
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
59224555 56#define IXGBE_DEFAULT_TX_WORK 256
9a799d71
AK		 57#define IXGBE_MAX_TXD 4096
58#define IXGBE_MIN_TXD 64
59
6bacb300 60#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 61#define IXGBE_MAX_RXD 4096
62#define IXGBE_MIN_RXD 64
63
9a799d71 64/* flow control */
2b9ade93 65#define IXGBE_MIN_FCRTL 0x40
9a799d71 66#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 67#define IXGBE_MIN_FCRTH 0x600
9a799d71 68#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
13958070 74#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
919e78a6 75#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 76
13958070
AD		 77/*
78 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
79 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
80 * this adds up to 512 bytes of extra data meaning the smallest allocation
81 * we could have is 1K.
82 * i.e. RXBUFFER_512 --> size-1024 slab
83 */
84#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 85
86#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
87
9a799d71
AK		 88/* How many Rx Buffers do we bundle into one write to the hardware ? */
89#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
90
91#define IXGBE_TX_FLAGS_CSUM (u32)(1)
66f32a8b
AD		 92#define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
93#define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
94#define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
95#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
96#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
97#define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
7f9643fd 98#define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
9a799d71 99#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
66f32a8b
AD		 100#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
101#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
9a799d71
AK		 102#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
103
7f870475
GR		 104#define IXGBE_MAX_VF_MC_ENTRIES 30
105#define IXGBE_MAX_VF_FUNCTIONS 64
106#define IXGBE_MAX_VFTA_ENTRIES 128
107#define MAX_EMULATION_MAC_ADDRS 16
a1cbb15c 108#define IXGBE_MAX_PF_MACVLANS 15
7f870475 109#define VMDQ_P(p) ((p) + adapter->num_vfs)
83c61fa9
GR		 110#define IXGBE_82599_VF_DEVICE_ID 0x10ED
111#define IXGBE_X540_VF_DEVICE_ID 0x1515
7f870475
GR		 112
113struct vf_data_storage {
114 unsigned char vf_mac_addresses[ETH_ALEN];
115 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
116 u16 num_vf_mc_hashes;
117 u16 default_vf_vlan_id;
118 u16 vlans_enabled;
7f870475 119 bool clear_to_send;
7f01648a 120 bool pf_set_mac;
7f01648a
GR		 121 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
122 u16 pf_qos;
ff4ab206 123 u16 tx_rate;
de4c7f65
GR		 124 u16 vlan_count;
125 u8 spoofchk_enabled;
c6bda30a 126 struct pci_dev *vfdev;
7f870475
GR		 127};
128
a1cbb15c
GR		 129struct vf_macvlans {
130 struct list_head l;
131 int vf;
132 int rar_entry;
133 bool free;
134 bool is_macvlan;
135 u8 vf_macvlan[ETH_ALEN];
136};
137
a535c30e
AD		 138#define IXGBE_MAX_TXD_PWR 14
139#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
140
141/* Tx Descriptors needed, worst case */
142#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
143#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
144
9a799d71
AK		 145/* wrapper around a pointer to a socket buffer,
146 * so a DMA handle can be stored along with the buffer */
147struct ixgbe_tx_buffer {
d3d00239 148 union ixgbe_adv_tx_desc *next_to_watch;
9a799d71 149 unsigned long time_stamp;
fd0db0ed
AD		 150 struct sk_buff *skb;
151 unsigned int bytecount;
152 unsigned short gso_segs;
244e27ad 153 __be16 protocol;
729739b7
AD		 154 DEFINE_DMA_UNMAP_ADDR(dma);
155 DEFINE_DMA_UNMAP_LEN(len);
d3d00239 156 u32 tx_flags;
9a799d71
AK		 157};
158
159struct ixgbe_rx_buffer {
160 struct sk_buff *skb;
161 dma_addr_t dma;
162 struct page *page;
762f4c57 163 unsigned int page_offset;
9a799d71
AK		 164};
165
166struct ixgbe_queue_stats {
167 u64 packets;
168 u64 bytes;
169};
170
5b7da515
AD		 171struct ixgbe_tx_queue_stats {
172 u64 restart_queue;
173 u64 tx_busy;
c84d324c 174 u64 tx_done_old;
5b7da515
AD		 175};
176
177struct ixgbe_rx_queue_stats {
178 u64 rsc_count;
179 u64 rsc_flush;
180 u64 non_eop_descs;
181 u64 alloc_rx_page_failed;
182 u64 alloc_rx_buff_failed;
8a0da21b 183 u64 csum_err;
5b7da515
AD		 184};
185
f800326d 186enum ixgbe_ring_state_t {
7d637bcc
AD		 187 __IXGBE_TX_FDIR_INIT_DONE,
188 __IXGBE_TX_DETECT_HANG,
c84d324c 189 __IXGBE_HANG_CHECK_ARMED,
7d637bcc 190 __IXGBE_RX_RSC_ENABLED,
8a0da21b 191 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
f800326d 192 __IXGBE_RX_FCOE_BUFSZ,
7d637bcc
AD		 193};
194
7d637bcc
AD		 195#define check_for_tx_hang(ring) \
196 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
197#define set_check_for_tx_hang(ring) \
198 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
199#define clear_check_for_tx_hang(ring) \
200 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
201#define ring_is_rsc_enabled(ring) \
202 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
203#define set_ring_rsc_enabled(ring) \
204 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
205#define clear_ring_rsc_enabled(ring) \
206 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 207struct ixgbe_ring {
efe3d3c8 208 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
d3ee4294
AD		 209 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
210 struct net_device *netdev; /* netdev ring belongs to */
211 struct device *dev; /* device for DMA mapping */
9a799d71 212 void *desc; /* descriptor ring memory */
9a799d71
AK		 213 union {
214 struct ixgbe_tx_buffer *tx_buffer_info;
215 struct ixgbe_rx_buffer *rx_buffer_info;
216 };
7d637bcc 217 unsigned long state;
bd198058 218 u8 __iomem *tail;
d3ee4294
AD		 219 dma_addr_t dma; /* phys. address of descriptor ring */
220 unsigned int size; /* length in bytes */
bd198058 221
ae540af1 222 u16 count; /* amount of descriptors */
ae540af1
JB		 223
224 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 225 u8 reg_idx; /* holds the special value that gets
226 * the hardware register offset
227 * associated with this ring, which is
228 * different for DCB and RSS modes
229 */
d3ee4294
AD		 230 u16 next_to_use;
231 u16 next_to_clean;
232
f800326d 233 union {
d3ee4294 234 u16 next_to_alloc;
f800326d
AD		 235 struct {
236 u8 atr_sample_rate;
237 u8 atr_count;
238 };
f800326d 239 };
9a799d71 240
bd198058 241 u8 dcb_tc;
9a799d71 242 struct ixgbe_queue_stats stats;
de1036b1 243 struct u64_stats_sync syncp;
5b7da515
AD		 244 union {
245 struct ixgbe_tx_queue_stats tx_stats;
246 struct ixgbe_rx_queue_stats rx_stats;
247 };
7ca3bc58 248} ____cacheline_internodealigned_in_smp;
9a799d71 249
c7e4358a
SN		 250enum ixgbe_ring_f_enum {
251 RING_F_NONE = 0,
7f870475 252 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 253 RING_F_RSS,
c4cf55e5 254 RING_F_FDIR,
0331a832
YZ		 255#ifdef IXGBE_FCOE
256 RING_F_FCOE,
257#endif /* IXGBE_FCOE */
c7e4358a
SN		 258
259 RING_F_ARRAY_SIZE /* must be last in enum set */
260};
261
021230d4 262#define IXGBE_MAX_RSS_INDICES 16
7f870475 263#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 264#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 265#ifdef IXGBE_FCOE
266#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 267#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
268#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
269#else
270#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
271#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 272#endif /* IXGBE_FCOE */
021230d4
AV		 273struct ixgbe_ring_feature {
274 int indices;
275 int mask;
7ca3bc58 276} ____cacheline_internodealigned_in_smp;
021230d4 277
f800326d
AD		 278/*
279 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
280 * this is twice the size of a half page we need to double the page order
281 * for FCoE enabled Rx queues.
282 */
283#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
284static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
285{
286 return test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0;
287}
288#else
289#define ixgbe_rx_pg_order(_ring) 0
290#endif
291#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
292#define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
293
08c8833b 294struct ixgbe_ring_container {
efe3d3c8 295 struct ixgbe_ring *ring; /* pointer to linked list of rings */
bd198058
AD		 296 unsigned int total_bytes; /* total bytes processed this int */
297 unsigned int total_packets; /* total packets processed this int */
298 u16 work_limit; /* total work allowed per interrupt */
08c8833b
AD		 299 u8 count; /* total number of rings in vector */
300 u8 itr; /* current ITR setting for ring */
301};
021230d4 302
a557928e
AD		 303/* iterator for handling rings in ring container */
304#define ixgbe_for_each_ring(pos, head) \
305 for (pos = (head).ring; pos != NULL; pos = pos->next)
306
2f90b865
AD		 307#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
308 ? 8 : 1)
309#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
310
021230d4
AV		 311/* MAX_MSIX_Q_VECTORS of these are allocated,
312 * but we only use one per queue-specific vector.
313 */
314struct ixgbe_q_vector {
315 struct ixgbe_adapter *adapter;
33cf09c9
AD		 316#ifdef CONFIG_IXGBE_DCA
317 int cpu; /* CPU for DCA */
318#endif
d5bf4f67
ET		 319 u16 v_idx; /* index of q_vector within array, also used for
320 * finding the bit in EICR and friends that
321 * represents the vector for this ring */
322 u16 itr; /* Interrupt throttle rate written to EITR */
08c8833b 323 struct ixgbe_ring_container rx, tx;
d5bf4f67
ET		 324
325 struct napi_struct napi;
de88eeeb
AD		 326 cpumask_t affinity_mask;
327 int numa_node;
328 struct rcu_head rcu; /* to avoid race with update stats on free */
d0759ebb 329 char name[IFNAMSIZ + 9];
de88eeeb
AD		 330
331 /* for dynamic allocation of rings associated with this q_vector */
332 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
021230d4 333};
3ca8bc6d
DS		 334#ifdef CONFIG_IXGBE_HWMON
335
336#define IXGBE_HWMON_TYPE_LOC 0
337#define IXGBE_HWMON_TYPE_TEMP 1
338#define IXGBE_HWMON_TYPE_CAUTION 2
339#define IXGBE_HWMON_TYPE_MAX 3
340
341struct hwmon_attr {
342 struct device_attribute dev_attr;
343 struct ixgbe_hw *hw;
344 struct ixgbe_thermal_diode_data *sensor;
345 char name[12];
346};
347
348struct hwmon_buff {
349 struct device *device;
350 struct hwmon_attr *hwmon_list;
351 unsigned int n_hwmon;
352};
353#endif /* CONFIG_IXGBE_HWMON */
021230d4 354
d5bf4f67
ET		 355/*
356 * microsecond values for various ITR rates shifted by 2 to fit itr register
357 * with the first 3 bits reserved 0
9a799d71 358 */
d5bf4f67
ET		 359#define IXGBE_MIN_RSC_ITR 24
360#define IXGBE_100K_ITR 40
361#define IXGBE_20K_ITR 200
362#define IXGBE_10K_ITR 400
363#define IXGBE_8K_ITR 500
9a799d71 364
f56e0cb1
AD		 365/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
366static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
367 const u32 stat_err_bits)
368{
369 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
370}
371
7d4987de
AD		 372static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
373{
374 u16 ntc = ring->next_to_clean;
375 u16 ntu = ring->next_to_use;
376
377 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
378}
9a799d71 379
e4f74028 380#define IXGBE_RX_DESC(R, i) \
31f05a2d 381 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
e4f74028 382#define IXGBE_TX_DESC(R, i) \
31f05a2d 383 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
e4f74028 384#define IXGBE_TX_CTXTDESC(R, i) \
31f05a2d 385 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 386
387#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 388#ifdef IXGBE_FCOE
389/* Use 3K as the baby jumbo frame size for FCoE */
390#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
391#endif /* IXGBE_FCOE */
9a799d71 392
021230d4
AV		 393#define OTHER_VECTOR 1
394#define NON_Q_VECTORS (OTHER_VECTOR)
395
e8e26350
PW		 396#define MAX_MSIX_VECTORS_82599 64
397#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 398#define MAX_MSIX_VECTORS_82598 18
399#define MAX_MSIX_Q_VECTORS_82598 16
400
e8e26350
PW		 401#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
402#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 403
8f15486d 404#define MIN_MSIX_Q_VECTORS 1
021230d4
AV		 405#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
406
46646e61
AD		 407/* default to trying for four seconds */
408#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
409
9a799d71
AK		 410/* board specific private data structure */
411struct ixgbe_adapter {
46646e61
AD		 412 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
413 /* OS defined structs */
414 struct net_device *netdev;
415 struct pci_dev *pdev;
416
e606bfe7
AD		 417 unsigned long state;
418
419 /* Some features need tri-state capability,
420 * thus the additional *_CAPABLE flags.
421 */
422 u32 flags;
e606bfe7
AD		 423#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
424#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
425#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
426#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
427#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
428#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
429#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
430#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
431#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
432#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
433#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
434#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
435#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
436#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
437#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
438#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
439#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
440#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
441#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
7086400d
AD		 442#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
443#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
444#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
445#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
446#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
447#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
448#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
e606bfe7
AD		 449
450 u32 flags2;
451#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
452#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
453#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
f0f9778d 454#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
7086400d
AD		 455#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
456#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
c83c6cbd 457#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
d034acf1 458#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
ef6afc0c
AD		 459#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
460#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
d033d526 461
46646e61
AD		 462 /* Tx fast path data */
463 int num_tx_queues;
464 u16 tx_itr_setting;
bd198058
AD		 465 u16 tx_work_limit;
466
46646e61
AD		 467 /* Rx fast path data */
468 int num_rx_queues;
469 u16 rx_itr_setting;
470
9a799d71 471 /* TX */
4a0b9ca0 472 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
9a799d71 473
7ca3bc58
JB		 474 u64 restart_queue;
475 u64 lsc_int;
46646e61 476 u32 tx_timeout_count;
7ca3bc58 477
9a799d71 478 /* RX */
46646e61 479 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
7f870475
GR		 480 int num_rx_pools; /* == num_rx_queues in 82598 */
481 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 482 u64 hw_csum_rx_error;
e8e26350 483 u64 hw_rx_no_dma_resources;
46646e61
AD		 484 u64 rsc_total_count;
485 u64 rsc_total_flush;
9a799d71 486 u64 non_eop_descs;
9a799d71
AK		 487 u32 alloc_rx_page_failed;
488 u32 alloc_rx_buff_failed;
489
46646e61 490 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
9a799d71 491
46646e61
AD		 492 /* DCB parameters */
493 struct ieee_pfc *ixgbe_ieee_pfc;
494 struct ieee_ets *ixgbe_ieee_ets;
495 struct ixgbe_dcb_config dcb_cfg;
496 struct ixgbe_dcb_config temp_dcb_cfg;
497 u8 dcb_set_bitmap;
498 u8 dcbx_cap;
499 enum ixgbe_fc_mode last_lfc_mode;
500
501 int num_msix_vectors;
502 int max_msix_q_vectors; /* true count of q_vectors for device */
503 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
504 struct msix_entry *msix_entries;
9a799d71 505
da4dd0f7
PWJ		 506 u32 test_icr;
507 struct ixgbe_ring test_tx_ring;
508 struct ixgbe_ring test_rx_ring;
509
9a799d71
AK		 510 /* structs defined in ixgbe_hw.h */
511 struct ixgbe_hw hw;
512 u16 msg_enable;
513 struct ixgbe_hw_stats stats;
021230d4 514
9a799d71 515 u64 tx_busy;
30efa5a3
JB		 516 unsigned int tx_ring_count;
517 unsigned int rx_ring_count;
cf8280ee
JB		 518
519 u32 link_speed;
520 bool link_up;
521 unsigned long link_check_timeout;
522
7086400d 523 struct timer_list service_timer;
46646e61
AD		 524 struct work_struct service_task;
525
526 struct hlist_head fdir_filter_list;
527 unsigned long fdir_overflow; /* number of times ATR was backed off */
528 union ixgbe_atr_input fdir_mask;
529 int fdir_filter_count;
c4cf55e5
PWJ		 530 u32 fdir_pballoc;
531 u32 atr_sample_rate;
532 spinlock_t fdir_perfect_lock;
46646e61 533
d0ed8937
YZ		 534#ifdef IXGBE_FCOE
535 struct ixgbe_fcoe fcoe;
536#endif /* IXGBE_FCOE */
e8e26350 537 u32 wol;
46646e61 538
46646e61
AD		 539 u16 bd_number;
540
15e5209f
ET		 541 u16 eeprom_verh;
542 u16 eeprom_verl;
c23f5b6b 543 u16 eeprom_cap;
7f870475 544
119fc60a 545 u32 interrupt_event;
46646e61 546 u32 led_reg;
1a6c14a2 547
7f870475
GR		 548 /* SR-IOV */
549 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
550 unsigned int num_vfs;
551 struct vf_data_storage *vfinfo;
ff4ab206 552 int vf_rate_link_speed;
a1cbb15c
GR		 553 struct vf_macvlans vf_mvs;
554 struct vf_macvlans *mv_list;
3e05334f 555
83c61fa9
GR		 556 u32 timer_event_accumulator;
557 u32 vferr_refcount;
3ca8bc6d
DS		 558 struct kobject *info_kobj;
559#ifdef CONFIG_IXGBE_HWMON
560 struct hwmon_buff ixgbe_hwmon_buff;
561#endif /* CONFIG_IXGBE_HWMON */
3e05334f
AD		 562};
563
564struct ixgbe_fdir_filter {
565 struct hlist_node fdir_node;
566 union ixgbe_atr_input filter;
567 u16 sw_idx;
568 u16 action;
9a799d71
AK		 569};
570
70e5576c 571enum ixgbe_state_t {
9a799d71
AK		 572 __IXGBE_TESTING,
573 __IXGBE_RESETTING,
c4900be0 574 __IXGBE_DOWN,
7086400d
AD		 575 __IXGBE_SERVICE_SCHED,
576 __IXGBE_IN_SFP_INIT,
9a799d71
AK		 577};
578
4c1975d7
AD		 579struct ixgbe_cb {
580 union { /* Union defining head/tail partner */
581 struct sk_buff *head;
582 struct sk_buff *tail;
583 };
aa80175a 584 dma_addr_t dma;
4c1975d7 585 u16 append_cnt;
f800326d 586 bool page_released;
aa80175a 587};
4c1975d7 588#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
aa80175a 589
9a799d71 590enum ixgbe_boards {
3957d63d 591 board_82598,
e8e26350 592 board_82599,
fe15e8e1 593 board_X540,
9a799d71
AK		 594};
595
3957d63d 596extern struct ixgbe_info ixgbe_82598_info;
e8e26350 597extern struct ixgbe_info ixgbe_82599_info;
fe15e8e1 598extern struct ixgbe_info ixgbe_X540_info;
7a6b6f51 599#ifdef CONFIG_IXGBE_DCB
32953543 600extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865 601#endif
9a799d71
AK		 602
603extern char ixgbe_driver_name[];
9c8eb720 604extern const char ixgbe_driver_version[];
8af3c33f 605#ifdef IXGBE_FCOE
ea81875a 606extern char ixgbe_default_device_descr[];
8af3c33f 607#endif /* IXGBE_FCOE */
9a799d71 608
c7ccde0f 609extern void ixgbe_up(struct ixgbe_adapter *adapter);
9a799d71 610extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 611extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 612extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 613extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 614extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
615extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
616extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
617extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 618extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
619extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
2d39d576
YZ		 620extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
621 struct ixgbe_ring *);
b4617240 622extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 623extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
8e2813f5
JK		 624extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
625 u16 subdevice_id);
7a921c93 626extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 627extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 628 struct ixgbe_adapter *,
629 struct ixgbe_ring *);
b6ec895e 630extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 631 struct ixgbe_tx_buffer *);
fc77dc3c 632extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a 633extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
8af3c33f 634extern int ixgbe_poll(struct napi_struct *napi, int budget);
fe49f04a 635extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772 636extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
c04f6ca8
AD		 637extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
638extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
ffff4772 639extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 640 union ixgbe_atr_hash_dword input,
641 union ixgbe_atr_hash_dword common,
ffff4772 642 u8 queue);
c04f6ca8
AD		 643extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
644 union ixgbe_atr_input *input_mask);
645extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
646 union ixgbe_atr_input *input,
647 u16 soft_id, u8 queue);
648extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
649 union ixgbe_atr_input *input,
650 u16 soft_id);
651extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
652 union ixgbe_atr_input *mask);
7f870475 653extern void ixgbe_set_rx_mode(struct net_device *netdev);
8af3c33f 654#ifdef CONFIG_IXGBE_DCB
3ebe8fde 655extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
e5b64635 656extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
8af3c33f 657#endif
897ab156 658extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
082757af 659extern void ixgbe_do_reset(struct net_device *netdev);
3ca8bc6d
DS		 660extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
661extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
eacd73f7
YZ		 662#ifdef IXGBE_FCOE
663extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
fd0db0ed
AD		 664extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
665 struct ixgbe_tx_buffer *first,
244e27ad 666 u8 *hdr_len);
332d4a7d
YZ		 667extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
668extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
ff886dfc 669 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 670 struct sk_buff *skb);
332d4a7d
YZ		 671extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
672 struct scatterlist *sgl, unsigned int sgc);
68a683cf
YZ		 673extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
674 struct scatterlist *sgl, unsigned int sgc);
332d4a7d 675extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 676extern int ixgbe_fcoe_enable(struct net_device *netdev);
677extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 678#ifdef CONFIG_IXGBE_DCB
679extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
680extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
681#endif /* CONFIG_IXGBE_DCB */
61a1fa10 682extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
ea81875a
NP		 683extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
684 struct netdev_fcoe_hbainfo *info);
eacd73f7 685#endif /* IXGBE_FCOE */
9a799d71 686
b2d96e0a
AD		 687static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
688{
689 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
690}
691
9a799d71 692#endif /* _IXGBE_H_ */
Linux 6.x block layer and io_uring tree(s)