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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
434c5e39 | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _IXGBE_H_ | |
29 | #define _IXGBE_H_ | |
30 | ||
f62bbb5e | 31 | #include <linux/bitops.h> |
9a799d71 AK |
32 | #include <linux/types.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/netdevice.h> | |
b25ebfd2 | 35 | #include <linux/cpumask.h> |
6fabd715 | 36 | #include <linux/aer.h> |
f62bbb5e | 37 | #include <linux/if_vlan.h> |
6cb562d6 | 38 | #include <linux/jiffies.h> |
9a799d71 | 39 | |
3a6a4eda JK |
40 | #include <linux/clocksource.h> |
41 | #include <linux/net_tstamp.h> | |
42 | #include <linux/ptp_clock_kernel.h> | |
3a6a4eda | 43 | |
9a799d71 AK |
44 | #include "ixgbe_type.h" |
45 | #include "ixgbe_common.h" | |
2f90b865 | 46 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
47 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
48 | #define IXGBE_FCOE | |
49 | #include "ixgbe_fcoe.h" | |
50 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 51 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
52 | #include <linux/dca.h> |
53 | #endif | |
9a799d71 | 54 | |
076bb0c8 | 55 | #include <net/busy_poll.h> |
5a85e737 | 56 | |
e0d1095a | 57 | #ifdef CONFIG_NET_RX_BUSY_POLL |
b4640030 | 58 | #define BP_EXTENDED_STATS |
7e15b90f | 59 | #endif |
849c4542 ET |
60 | /* common prefix used by pr_<> macros */ |
61 | #undef pr_fmt | |
62 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
63 | |
64 | /* TX/RX descriptor defines */ | |
6bacb300 | 65 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 66 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
67 | #define IXGBE_MAX_TXD 4096 |
68 | #define IXGBE_MIN_TXD 64 | |
69 | ||
fb44519d | 70 | #if (PAGE_SIZE < 8192) |
6bacb300 | 71 | #define IXGBE_DEFAULT_RXD 512 |
fb44519d AB |
72 | #else |
73 | #define IXGBE_DEFAULT_RXD 128 | |
74 | #endif | |
9a799d71 AK |
75 | #define IXGBE_MAX_RXD 4096 |
76 | #define IXGBE_MIN_RXD 64 | |
77 | ||
9a799d71 | 78 | /* flow control */ |
2b9ade93 | 79 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 80 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 81 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 82 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 83 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
84 | #define IXGBE_MIN_FCPAUSE 0 |
85 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
86 | ||
87 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 88 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
89 | #define IXGBE_RXBUFFER_2K 2048 |
90 | #define IXGBE_RXBUFFER_3K 3072 | |
91 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 92 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 93 | |
13958070 | 94 | /* |
252562c2 AD |
95 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
96 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
97 | * this adds up to 448 bytes of extra data. | |
98 | * | |
99 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
100 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 101 | */ |
252562c2 | 102 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 | 103 | |
9a799d71 AK |
104 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
105 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
106 | ||
472148c3 AD |
107 | enum ixgbe_tx_flags { |
108 | /* cmd_type flags */ | |
109 | IXGBE_TX_FLAGS_HW_VLAN = 0x01, | |
110 | IXGBE_TX_FLAGS_TSO = 0x02, | |
111 | IXGBE_TX_FLAGS_TSTAMP = 0x04, | |
112 | ||
113 | /* olinfo flags */ | |
114 | IXGBE_TX_FLAGS_CC = 0x08, | |
115 | IXGBE_TX_FLAGS_IPV4 = 0x10, | |
116 | IXGBE_TX_FLAGS_CSUM = 0x20, | |
117 | ||
118 | /* software defined flags */ | |
119 | IXGBE_TX_FLAGS_SW_VLAN = 0x40, | |
120 | IXGBE_TX_FLAGS_FCOE = 0x80, | |
121 | }; | |
122 | ||
123 | /* VLAN info */ | |
9a799d71 | 124 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
125 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
126 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
127 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
128 | ||
7f870475 GR |
129 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
130 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
131 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
132 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 133 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 134 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
135 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
136 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
137 | |
138 | struct vf_data_storage { | |
139 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
140 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
141 | u16 num_vf_mc_hashes; | |
142 | u16 default_vf_vlan_id; | |
143 | u16 vlans_enabled; | |
7f870475 | 144 | bool clear_to_send; |
7f01648a | 145 | bool pf_set_mac; |
7f01648a GR |
146 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
147 | u16 pf_qos; | |
ff4ab206 | 148 | u16 tx_rate; |
de4c7f65 GR |
149 | u16 vlan_count; |
150 | u8 spoofchk_enabled; | |
374c65d6 | 151 | unsigned int vf_api; |
7f870475 GR |
152 | }; |
153 | ||
a1cbb15c GR |
154 | struct vf_macvlans { |
155 | struct list_head l; | |
156 | int vf; | |
157 | int rar_entry; | |
158 | bool free; | |
159 | bool is_macvlan; | |
160 | u8 vf_macvlan[ETH_ALEN]; | |
161 | }; | |
162 | ||
a535c30e AD |
163 | #define IXGBE_MAX_TXD_PWR 14 |
164 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
165 | ||
166 | /* Tx Descriptors needed, worst case */ | |
167 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
990a3158 | 168 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
a535c30e | 169 | |
9a799d71 AK |
170 | /* wrapper around a pointer to a socket buffer, |
171 | * so a DMA handle can be stored along with the buffer */ | |
172 | struct ixgbe_tx_buffer { | |
d3d00239 | 173 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 174 | unsigned long time_stamp; |
fd0db0ed AD |
175 | struct sk_buff *skb; |
176 | unsigned int bytecount; | |
177 | unsigned short gso_segs; | |
244e27ad | 178 | __be16 protocol; |
729739b7 AD |
179 | DEFINE_DMA_UNMAP_ADDR(dma); |
180 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 181 | u32 tx_flags; |
9a799d71 AK |
182 | }; |
183 | ||
184 | struct ixgbe_rx_buffer { | |
185 | struct sk_buff *skb; | |
186 | dma_addr_t dma; | |
187 | struct page *page; | |
762f4c57 | 188 | unsigned int page_offset; |
9a799d71 AK |
189 | }; |
190 | ||
191 | struct ixgbe_queue_stats { | |
192 | u64 packets; | |
193 | u64 bytes; | |
b4640030 | 194 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
195 | u64 yields; |
196 | u64 misses; | |
197 | u64 cleaned; | |
b4640030 | 198 | #endif /* BP_EXTENDED_STATS */ |
9a799d71 AK |
199 | }; |
200 | ||
5b7da515 AD |
201 | struct ixgbe_tx_queue_stats { |
202 | u64 restart_queue; | |
203 | u64 tx_busy; | |
c84d324c | 204 | u64 tx_done_old; |
5b7da515 AD |
205 | }; |
206 | ||
207 | struct ixgbe_rx_queue_stats { | |
208 | u64 rsc_count; | |
209 | u64 rsc_flush; | |
210 | u64 non_eop_descs; | |
211 | u64 alloc_rx_page_failed; | |
212 | u64 alloc_rx_buff_failed; | |
8a0da21b | 213 | u64 csum_err; |
5b7da515 AD |
214 | }; |
215 | ||
f800326d | 216 | enum ixgbe_ring_state_t { |
7d637bcc | 217 | __IXGBE_TX_FDIR_INIT_DONE, |
fd786b7b | 218 | __IXGBE_TX_XPS_INIT_DONE, |
7d637bcc | 219 | __IXGBE_TX_DETECT_HANG, |
c84d324c | 220 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 221 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 222 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
57efd44c | 223 | __IXGBE_RX_FCOE, |
7d637bcc AD |
224 | }; |
225 | ||
2a47fa45 JF |
226 | struct ixgbe_fwd_adapter { |
227 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
228 | struct net_device *netdev; | |
229 | struct ixgbe_adapter *real_adapter; | |
230 | unsigned int tx_base_queue; | |
231 | unsigned int rx_base_queue; | |
232 | int pool; | |
233 | }; | |
234 | ||
7d637bcc AD |
235 | #define check_for_tx_hang(ring) \ |
236 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
237 | #define set_check_for_tx_hang(ring) \ | |
238 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
239 | #define clear_check_for_tx_hang(ring) \ | |
240 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
241 | #define ring_is_rsc_enabled(ring) \ | |
242 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
243 | #define set_ring_rsc_enabled(ring) \ | |
244 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
245 | #define clear_ring_rsc_enabled(ring) \ | |
246 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 247 | struct ixgbe_ring { |
efe3d3c8 | 248 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
249 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
250 | struct net_device *netdev; /* netdev ring belongs to */ | |
251 | struct device *dev; /* device for DMA mapping */ | |
2a47fa45 | 252 | struct ixgbe_fwd_adapter *l2_accel_priv; |
9a799d71 | 253 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
254 | union { |
255 | struct ixgbe_tx_buffer *tx_buffer_info; | |
256 | struct ixgbe_rx_buffer *rx_buffer_info; | |
257 | }; | |
6cb562d6 | 258 | unsigned long last_rx_timestamp; |
7d637bcc | 259 | unsigned long state; |
bd198058 | 260 | u8 __iomem *tail; |
d3ee4294 AD |
261 | dma_addr_t dma; /* phys. address of descriptor ring */ |
262 | unsigned int size; /* length in bytes */ | |
bd198058 | 263 | |
ae540af1 | 264 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
265 | |
266 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
267 | u8 reg_idx; /* holds the special value that gets |
268 | * the hardware register offset | |
269 | * associated with this ring, which is | |
270 | * different for DCB and RSS modes | |
271 | */ | |
d3ee4294 AD |
272 | u16 next_to_use; |
273 | u16 next_to_clean; | |
274 | ||
f800326d | 275 | union { |
d3ee4294 | 276 | u16 next_to_alloc; |
f800326d AD |
277 | struct { |
278 | u8 atr_sample_rate; | |
279 | u8 atr_count; | |
280 | }; | |
f800326d | 281 | }; |
9a799d71 | 282 | |
bd198058 | 283 | u8 dcb_tc; |
9a799d71 | 284 | struct ixgbe_queue_stats stats; |
de1036b1 | 285 | struct u64_stats_sync syncp; |
5b7da515 AD |
286 | union { |
287 | struct ixgbe_tx_queue_stats tx_stats; | |
288 | struct ixgbe_rx_queue_stats rx_stats; | |
289 | }; | |
7ca3bc58 | 290 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 291 | |
c7e4358a SN |
292 | enum ixgbe_ring_f_enum { |
293 | RING_F_NONE = 0, | |
7f870475 | 294 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 295 | RING_F_RSS, |
c4cf55e5 | 296 | RING_F_FDIR, |
0331a832 YZ |
297 | #ifdef IXGBE_FCOE |
298 | RING_F_FCOE, | |
299 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
300 | |
301 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
302 | }; | |
303 | ||
021230d4 | 304 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 305 | #define IXGBE_MAX_VMDQ_INDICES 64 |
d3cb9869 | 306 | #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ |
0331a832 | 307 | #define IXGBE_MAX_FCOE_INDICES 8 |
d3cb9869 AD |
308 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) |
309 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
2a47fa45 JF |
310 | #define IXGBE_MAX_L2A_QUEUES 4 |
311 | #define IXGBE_MAX_L2A_QUEUES 4 | |
312 | #define IXGBE_BAD_L2A_QUEUE 3 | |
313 | #define IXGBE_MAX_MACVLANS 31 | |
314 | #define IXGBE_MAX_DCBMACVLANS 8 | |
315 | ||
021230d4 | 316 | struct ixgbe_ring_feature { |
c087663e AD |
317 | u16 limit; /* upper limit on feature indices */ |
318 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
319 | u16 mask; /* Mask used for feature to ring mapping */ |
320 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 321 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 322 | |
73079ea0 AD |
323 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
324 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
325 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
326 | ||
f800326d AD |
327 | /* |
328 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
329 | * this is twice the size of a half page we need to double the page order | |
330 | * for FCoE enabled Rx queues. | |
331 | */ | |
09816fbe | 332 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 333 | { |
09816fbe AD |
334 | #ifdef IXGBE_FCOE |
335 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
336 | return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : | |
337 | IXGBE_RXBUFFER_3K; | |
338 | #endif | |
339 | return IXGBE_RXBUFFER_2K; | |
f800326d | 340 | } |
09816fbe AD |
341 | |
342 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
343 | { | |
344 | #ifdef IXGBE_FCOE | |
345 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
346 | return (PAGE_SIZE < 8192) ? 1 : 0; | |
f800326d | 347 | #endif |
09816fbe AD |
348 | return 0; |
349 | } | |
f800326d | 350 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 351 | |
08c8833b | 352 | struct ixgbe_ring_container { |
efe3d3c8 | 353 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
354 | unsigned int total_bytes; /* total bytes processed this int */ |
355 | unsigned int total_packets; /* total packets processed this int */ | |
356 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
357 | u8 count; /* total number of rings in vector */ |
358 | u8 itr; /* current ITR setting for ring */ | |
359 | }; | |
021230d4 | 360 | |
a557928e AD |
361 | /* iterator for handling rings in ring container */ |
362 | #define ixgbe_for_each_ring(pos, head) \ | |
363 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
364 | ||
2f90b865 AD |
365 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
366 | ? 8 : 1) | |
367 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS | |
368 | ||
49c7ffbe | 369 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
370 | * but we only use one per queue-specific vector. |
371 | */ | |
372 | struct ixgbe_q_vector { | |
373 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
374 | #ifdef CONFIG_IXGBE_DCA |
375 | int cpu; /* CPU for DCA */ | |
376 | #endif | |
d5bf4f67 ET |
377 | u16 v_idx; /* index of q_vector within array, also used for |
378 | * finding the bit in EICR and friends that | |
379 | * represents the vector for this ring */ | |
380 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 381 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
382 | |
383 | struct napi_struct napi; | |
de88eeeb AD |
384 | cpumask_t affinity_mask; |
385 | int numa_node; | |
386 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 387 | char name[IFNAMSIZ + 9]; |
de88eeeb | 388 | |
e0d1095a | 389 | #ifdef CONFIG_NET_RX_BUSY_POLL |
5a85e737 ET |
390 | unsigned int state; |
391 | #define IXGBE_QV_STATE_IDLE 0 | |
27d9ce4f JK |
392 | #define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */ |
393 | #define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */ | |
394 | #define IXGBE_QV_STATE_DISABLED 4 /* QV is disabled */ | |
395 | #define IXGBE_QV_OWNED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL) | |
396 | #define IXGBE_QV_LOCKED (IXGBE_QV_OWNED | IXGBE_QV_STATE_DISABLED) | |
397 | #define IXGBE_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ | |
398 | #define IXGBE_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ | |
5a85e737 ET |
399 | #define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD) |
400 | #define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD) | |
401 | spinlock_t lock; | |
e0d1095a | 402 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 403 | |
de88eeeb AD |
404 | /* for dynamic allocation of rings associated with this q_vector */ |
405 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 406 | }; |
e0d1095a | 407 | #ifdef CONFIG_NET_RX_BUSY_POLL |
5a85e737 ET |
408 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
409 | { | |
410 | ||
411 | spin_lock_init(&q_vector->lock); | |
412 | q_vector->state = IXGBE_QV_STATE_IDLE; | |
413 | } | |
414 | ||
415 | /* called from the device poll routine to get ownership of a q_vector */ | |
416 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
417 | { | |
418 | int rc = true; | |
27d9ce4f | 419 | spin_lock_bh(&q_vector->lock); |
5a85e737 ET |
420 | if (q_vector->state & IXGBE_QV_LOCKED) { |
421 | WARN_ON(q_vector->state & IXGBE_QV_STATE_NAPI); | |
422 | q_vector->state |= IXGBE_QV_STATE_NAPI_YIELD; | |
423 | rc = false; | |
b4640030 | 424 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
425 | q_vector->tx.ring->stats.yields++; |
426 | #endif | |
78d820e8 | 427 | } else { |
5a85e737 ET |
428 | /* we don't care if someone yielded */ |
429 | q_vector->state = IXGBE_QV_STATE_NAPI; | |
78d820e8 | 430 | } |
27d9ce4f | 431 | spin_unlock_bh(&q_vector->lock); |
5a85e737 ET |
432 | return rc; |
433 | } | |
434 | ||
435 | /* returns true is someone tried to get the qv while napi had it */ | |
436 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
437 | { | |
438 | int rc = false; | |
27d9ce4f | 439 | spin_lock_bh(&q_vector->lock); |
5a85e737 ET |
440 | WARN_ON(q_vector->state & (IXGBE_QV_STATE_POLL | |
441 | IXGBE_QV_STATE_NAPI_YIELD)); | |
442 | ||
443 | if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) | |
444 | rc = true; | |
27d9ce4f JK |
445 | /* will reset state to idle, unless QV is disabled */ |
446 | q_vector->state &= IXGBE_QV_STATE_DISABLED; | |
447 | spin_unlock_bh(&q_vector->lock); | |
5a85e737 ET |
448 | return rc; |
449 | } | |
450 | ||
451 | /* called from ixgbe_low_latency_poll() */ | |
452 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
453 | { | |
454 | int rc = true; | |
455 | spin_lock_bh(&q_vector->lock); | |
456 | if ((q_vector->state & IXGBE_QV_LOCKED)) { | |
457 | q_vector->state |= IXGBE_QV_STATE_POLL_YIELD; | |
458 | rc = false; | |
b4640030 | 459 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
460 | q_vector->rx.ring->stats.yields++; |
461 | #endif | |
78d820e8 | 462 | } else { |
5a85e737 ET |
463 | /* preserve yield marks */ |
464 | q_vector->state |= IXGBE_QV_STATE_POLL; | |
78d820e8 | 465 | } |
5a85e737 ET |
466 | spin_unlock_bh(&q_vector->lock); |
467 | return rc; | |
468 | } | |
469 | ||
470 | /* returns true if someone tried to get the qv while it was locked */ | |
471 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
472 | { | |
473 | int rc = false; | |
474 | spin_lock_bh(&q_vector->lock); | |
475 | WARN_ON(q_vector->state & (IXGBE_QV_STATE_NAPI)); | |
476 | ||
477 | if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) | |
478 | rc = true; | |
27d9ce4f JK |
479 | /* will reset state to idle, unless QV is disabled */ |
480 | q_vector->state &= IXGBE_QV_STATE_DISABLED; | |
5a85e737 ET |
481 | spin_unlock_bh(&q_vector->lock); |
482 | return rc; | |
483 | } | |
484 | ||
485 | /* true if a socket is polling, even if it did not get the lock */ | |
b4640030 | 486 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 | 487 | { |
27d9ce4f | 488 | WARN_ON(!(q_vector->state & IXGBE_QV_OWNED)); |
5a85e737 ET |
489 | return q_vector->state & IXGBE_QV_USER_PEND; |
490 | } | |
27d9ce4f JK |
491 | |
492 | /* false if QV is currently owned */ | |
493 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
494 | { | |
495 | int rc = true; | |
496 | spin_lock_bh(&q_vector->lock); | |
497 | if (q_vector->state & IXGBE_QV_OWNED) | |
498 | rc = false; | |
499 | q_vector->state |= IXGBE_QV_STATE_DISABLED; | |
500 | spin_unlock_bh(&q_vector->lock); | |
501 | ||
502 | return rc; | |
503 | } | |
504 | ||
e0d1095a | 505 | #else /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 ET |
506 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
507 | { | |
508 | } | |
509 | ||
510 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
511 | { | |
512 | return true; | |
513 | } | |
514 | ||
515 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
516 | { | |
517 | return false; | |
518 | } | |
519 | ||
520 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
521 | { | |
522 | return false; | |
523 | } | |
524 | ||
525 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
526 | { | |
527 | return false; | |
528 | } | |
529 | ||
b4640030 | 530 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 ET |
531 | { |
532 | return false; | |
533 | } | |
27d9ce4f JK |
534 | |
535 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
536 | { | |
537 | return true; | |
538 | } | |
539 | ||
e0d1095a | 540 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 541 | |
3ca8bc6d DS |
542 | #ifdef CONFIG_IXGBE_HWMON |
543 | ||
544 | #define IXGBE_HWMON_TYPE_LOC 0 | |
545 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
546 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
547 | #define IXGBE_HWMON_TYPE_MAX 3 | |
548 | ||
549 | struct hwmon_attr { | |
550 | struct device_attribute dev_attr; | |
551 | struct ixgbe_hw *hw; | |
552 | struct ixgbe_thermal_diode_data *sensor; | |
553 | char name[12]; | |
554 | }; | |
555 | ||
556 | struct hwmon_buff { | |
03b77d81 GR |
557 | struct attribute_group group; |
558 | const struct attribute_group *groups[2]; | |
559 | struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; | |
560 | struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; | |
3ca8bc6d DS |
561 | unsigned int n_hwmon; |
562 | }; | |
563 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 564 | |
d5bf4f67 ET |
565 | /* |
566 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
567 | * with the first 3 bits reserved 0 | |
9a799d71 | 568 | */ |
d5bf4f67 ET |
569 | #define IXGBE_MIN_RSC_ITR 24 |
570 | #define IXGBE_100K_ITR 40 | |
571 | #define IXGBE_20K_ITR 200 | |
572 | #define IXGBE_10K_ITR 400 | |
573 | #define IXGBE_8K_ITR 500 | |
9a799d71 | 574 | |
f56e0cb1 AD |
575 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
576 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
577 | const u32 stat_err_bits) | |
578 | { | |
579 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
580 | } | |
581 | ||
7d4987de AD |
582 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
583 | { | |
584 | u16 ntc = ring->next_to_clean; | |
585 | u16 ntu = ring->next_to_use; | |
586 | ||
587 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
588 | } | |
9a799d71 | 589 | |
84227bcd MR |
590 | static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value) |
591 | { | |
592 | writel(value, ring->tail); | |
593 | } | |
594 | ||
e4f74028 | 595 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 596 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 597 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 598 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 599 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 600 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 601 | |
c88887e0 | 602 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
603 | #ifdef IXGBE_FCOE |
604 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
605 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
606 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 607 | |
021230d4 AV |
608 | #define OTHER_VECTOR 1 |
609 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
610 | ||
e8e26350 | 611 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 612 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 613 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 614 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 615 | |
49c7ffbe | 616 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 617 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 618 | |
8f15486d | 619 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
620 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
621 | ||
46646e61 AD |
622 | /* default to trying for four seconds */ |
623 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
624 | ||
9a799d71 AK |
625 | /* board specific private data structure */ |
626 | struct ixgbe_adapter { | |
46646e61 AD |
627 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
628 | /* OS defined structs */ | |
629 | struct net_device *netdev; | |
630 | struct pci_dev *pdev; | |
631 | ||
e606bfe7 AD |
632 | unsigned long state; |
633 | ||
634 | /* Some features need tri-state capability, | |
635 | * thus the additional *_CAPABLE flags. | |
636 | */ | |
637 | u32 flags; | |
a16a0d2f AD |
638 | #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0) |
639 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) | |
640 | #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2) | |
641 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) | |
642 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) | |
643 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) | |
644 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) | |
645 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) | |
646 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) | |
647 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) | |
648 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) | |
649 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) | |
650 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) | |
651 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) | |
652 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) | |
653 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) | |
654 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) | |
655 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) | |
656 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) | |
657 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) | |
658 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) | |
659 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) | |
660 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) | |
661 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) | |
e606bfe7 AD |
662 | |
663 | u32 flags2; | |
a16a0d2f | 664 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) |
e606bfe7 AD |
665 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) |
666 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 667 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
668 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
669 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 670 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 671 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
ef6afc0c AD |
672 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) |
673 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) | |
8fecf67c JK |
674 | #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) |
675 | #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11) | |
d033d526 | 676 | |
46646e61 AD |
677 | /* Tx fast path data */ |
678 | int num_tx_queues; | |
679 | u16 tx_itr_setting; | |
bd198058 AD |
680 | u16 tx_work_limit; |
681 | ||
46646e61 AD |
682 | /* Rx fast path data */ |
683 | int num_rx_queues; | |
684 | u16 rx_itr_setting; | |
685 | ||
9a799d71 | 686 | /* TX */ |
4a0b9ca0 | 687 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 688 | |
7ca3bc58 JB |
689 | u64 restart_queue; |
690 | u64 lsc_int; | |
46646e61 | 691 | u32 tx_timeout_count; |
7ca3bc58 | 692 | |
9a799d71 | 693 | /* RX */ |
46646e61 | 694 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
695 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
696 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 697 | u64 hw_csum_rx_error; |
e8e26350 | 698 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
699 | u64 rsc_total_count; |
700 | u64 rsc_total_flush; | |
9a799d71 | 701 | u64 non_eop_descs; |
9a799d71 AK |
702 | u32 alloc_rx_page_failed; |
703 | u32 alloc_rx_buff_failed; | |
704 | ||
49c7ffbe | 705 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 706 | |
46646e61 AD |
707 | /* DCB parameters */ |
708 | struct ieee_pfc *ixgbe_ieee_pfc; | |
709 | struct ieee_ets *ixgbe_ieee_ets; | |
710 | struct ixgbe_dcb_config dcb_cfg; | |
711 | struct ixgbe_dcb_config temp_dcb_cfg; | |
712 | u8 dcb_set_bitmap; | |
713 | u8 dcbx_cap; | |
714 | enum ixgbe_fc_mode last_lfc_mode; | |
715 | ||
49c7ffbe AD |
716 | int num_q_vectors; /* current number of q_vectors for device */ |
717 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
718 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
719 | struct msix_entry *msix_entries; | |
9a799d71 | 720 | |
da4dd0f7 PWJ |
721 | u32 test_icr; |
722 | struct ixgbe_ring test_tx_ring; | |
723 | struct ixgbe_ring test_rx_ring; | |
724 | ||
9a799d71 AK |
725 | /* structs defined in ixgbe_hw.h */ |
726 | struct ixgbe_hw hw; | |
727 | u16 msg_enable; | |
728 | struct ixgbe_hw_stats stats; | |
021230d4 | 729 | |
9a799d71 | 730 | u64 tx_busy; |
30efa5a3 JB |
731 | unsigned int tx_ring_count; |
732 | unsigned int rx_ring_count; | |
cf8280ee JB |
733 | |
734 | u32 link_speed; | |
735 | bool link_up; | |
736 | unsigned long link_check_timeout; | |
737 | ||
7086400d | 738 | struct timer_list service_timer; |
46646e61 AD |
739 | struct work_struct service_task; |
740 | ||
741 | struct hlist_head fdir_filter_list; | |
742 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
743 | union ixgbe_atr_input fdir_mask; | |
744 | int fdir_filter_count; | |
c4cf55e5 PWJ |
745 | u32 fdir_pballoc; |
746 | u32 atr_sample_rate; | |
747 | spinlock_t fdir_perfect_lock; | |
46646e61 | 748 | |
d0ed8937 YZ |
749 | #ifdef IXGBE_FCOE |
750 | struct ixgbe_fcoe fcoe; | |
751 | #endif /* IXGBE_FCOE */ | |
2a1a091c | 752 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
e8e26350 | 753 | u32 wol; |
46646e61 | 754 | |
46646e61 AD |
755 | u16 bd_number; |
756 | ||
15e5209f ET |
757 | u16 eeprom_verh; |
758 | u16 eeprom_verl; | |
c23f5b6b | 759 | u16 eeprom_cap; |
7f870475 | 760 | |
119fc60a | 761 | u32 interrupt_event; |
46646e61 | 762 | u32 led_reg; |
1a6c14a2 | 763 | |
3a6a4eda JK |
764 | struct ptp_clock *ptp_clock; |
765 | struct ptp_clock_info ptp_caps; | |
891dc082 JK |
766 | struct work_struct ptp_tx_work; |
767 | struct sk_buff *ptp_tx_skb; | |
768 | unsigned long ptp_tx_start; | |
3a6a4eda | 769 | unsigned long last_overflow_check; |
6cb562d6 | 770 | unsigned long last_rx_ptp_check; |
3a6a4eda JK |
771 | spinlock_t tmreg_lock; |
772 | struct cyclecounter cc; | |
773 | struct timecounter tc; | |
774 | u32 base_incval; | |
3a6a4eda | 775 | |
7f870475 GR |
776 | /* SR-IOV */ |
777 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
778 | unsigned int num_vfs; | |
779 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 780 | int vf_rate_link_speed; |
a1cbb15c GR |
781 | struct vf_macvlans vf_mvs; |
782 | struct vf_macvlans *mv_list; | |
3e05334f | 783 | |
83c61fa9 GR |
784 | u32 timer_event_accumulator; |
785 | u32 vferr_refcount; | |
3ca8bc6d DS |
786 | struct kobject *info_kobj; |
787 | #ifdef CONFIG_IXGBE_HWMON | |
03b77d81 | 788 | struct hwmon_buff *ixgbe_hwmon_buff; |
3ca8bc6d | 789 | #endif /* CONFIG_IXGBE_HWMON */ |
00949167 CS |
790 | #ifdef CONFIG_DEBUG_FS |
791 | struct dentry *ixgbe_dbg_adapter; | |
792 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
793 | |
794 | u8 default_up; | |
2a47fa45 | 795 | unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ |
3e05334f AD |
796 | }; |
797 | ||
798 | struct ixgbe_fdir_filter { | |
799 | struct hlist_node fdir_node; | |
800 | union ixgbe_atr_input filter; | |
801 | u16 sw_idx; | |
802 | u16 action; | |
9a799d71 AK |
803 | }; |
804 | ||
70e5576c | 805 | enum ixgbe_state_t { |
9a799d71 AK |
806 | __IXGBE_TESTING, |
807 | __IXGBE_RESETTING, | |
c4900be0 | 808 | __IXGBE_DOWN, |
09f40aed | 809 | __IXGBE_REMOVING, |
7086400d AD |
810 | __IXGBE_SERVICE_SCHED, |
811 | __IXGBE_IN_SFP_INIT, | |
8fecf67c | 812 | __IXGBE_PTP_RUNNING, |
9a799d71 AK |
813 | }; |
814 | ||
4c1975d7 AD |
815 | struct ixgbe_cb { |
816 | union { /* Union defining head/tail partner */ | |
817 | struct sk_buff *head; | |
818 | struct sk_buff *tail; | |
819 | }; | |
aa80175a | 820 | dma_addr_t dma; |
4c1975d7 | 821 | u16 append_cnt; |
f800326d | 822 | bool page_released; |
aa80175a | 823 | }; |
4c1975d7 | 824 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 825 | |
9a799d71 | 826 | enum ixgbe_boards { |
3957d63d | 827 | board_82598, |
e8e26350 | 828 | board_82599, |
fe15e8e1 | 829 | board_X540, |
9a799d71 AK |
830 | }; |
831 | ||
3957d63d | 832 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 833 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 834 | extern struct ixgbe_info ixgbe_X540_info; |
7a6b6f51 | 835 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 836 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 | 837 | #endif |
9a799d71 AK |
838 | |
839 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 840 | extern const char ixgbe_driver_version[]; |
8af3c33f | 841 | #ifdef IXGBE_FCOE |
ea81875a | 842 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 843 | #endif /* IXGBE_FCOE */ |
9a799d71 | 844 | |
5ccc921a JP |
845 | void ixgbe_up(struct ixgbe_adapter *adapter); |
846 | void ixgbe_down(struct ixgbe_adapter *adapter); | |
847 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); | |
848 | void ixgbe_reset(struct ixgbe_adapter *adapter); | |
849 | void ixgbe_set_ethtool_ops(struct net_device *netdev); | |
850 | int ixgbe_setup_rx_resources(struct ixgbe_ring *); | |
851 | int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
852 | void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
853 | void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
854 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
855 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
856 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); | |
857 | void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
858 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); | |
859 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
8e2813f5 | 860 | u16 subdevice_id); |
5ccc921a JP |
861 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
862 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, | |
863 | struct ixgbe_ring *); | |
864 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, | |
865 | struct ixgbe_tx_buffer *); | |
866 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); | |
867 | void ixgbe_write_eitr(struct ixgbe_q_vector *); | |
868 | int ixgbe_poll(struct napi_struct *napi, int budget); | |
869 | int ethtool_ioctl(struct ifreq *ifr); | |
870 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
871 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
872 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
873 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
874 | union ixgbe_atr_hash_dword input, | |
875 | union ixgbe_atr_hash_dword common, | |
876 | u8 queue); | |
877 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
878 | union ixgbe_atr_input *input_mask); | |
879 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
880 | union ixgbe_atr_input *input, | |
881 | u16 soft_id, u8 queue); | |
882 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
883 | union ixgbe_atr_input *input, | |
884 | u16 soft_id); | |
885 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
886 | union ixgbe_atr_input *mask); | |
5ccc921a | 887 | void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 888 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a | 889 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
8af3c33f | 890 | #endif |
5ccc921a JP |
891 | int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
892 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); | |
893 | void ixgbe_do_reset(struct net_device *netdev); | |
1210982b | 894 | #ifdef CONFIG_IXGBE_HWMON |
5ccc921a JP |
895 | void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
896 | int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 897 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 | 898 | #ifdef IXGBE_FCOE |
5ccc921a JP |
899 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); |
900 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, | |
901 | u8 *hdr_len); | |
902 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
903 | union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); | |
904 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
905 | struct scatterlist *sgl, unsigned int sgc); | |
906 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
907 | struct scatterlist *sgl, unsigned int sgc); | |
908 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
909 | int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
910 | void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
911 | int ixgbe_fcoe_enable(struct net_device *netdev); | |
912 | int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 | 913 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a JP |
914 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); |
915 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
6ee16520 | 916 | #endif /* CONFIG_IXGBE_DCB */ |
5ccc921a JP |
917 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
918 | int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, | |
919 | struct netdev_fcoe_hbainfo *info); | |
920 | u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); | |
eacd73f7 | 921 | #endif /* IXGBE_FCOE */ |
00949167 | 922 | #ifdef CONFIG_DEBUG_FS |
5ccc921a JP |
923 | void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); |
924 | void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
925 | void ixgbe_dbg_init(void); | |
926 | void ixgbe_dbg_exit(void); | |
33243fb0 JP |
927 | #else |
928 | static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} | |
929 | static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} | |
930 | static inline void ixgbe_dbg_init(void) {} | |
931 | static inline void ixgbe_dbg_exit(void) {} | |
00949167 | 932 | #endif /* CONFIG_DEBUG_FS */ |
b2d96e0a AD |
933 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
934 | { | |
935 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
936 | } | |
937 | ||
5ccc921a JP |
938 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter); |
939 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); | |
940 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
941 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); | |
942 | void __ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector, | |
943 | struct sk_buff *skb); | |
39dfb71b AD |
944 | static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, |
945 | union ixgbe_adv_rx_desc *rx_desc, | |
946 | struct sk_buff *skb) | |
947 | { | |
948 | if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) | |
949 | return; | |
950 | ||
951 | __ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, skb); | |
952 | ||
953 | /* | |
954 | * Update the last_rx_timestamp timer in order to enable watchdog check | |
955 | * for error case of latched timestamp on a dropped packet. | |
956 | */ | |
957 | rx_ring->last_rx_timestamp = jiffies; | |
958 | } | |
959 | ||
5ccc921a JP |
960 | int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, struct ifreq *ifr, |
961 | int cmd); | |
962 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); | |
963 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); | |
964 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); | |
da36b647 GR |
965 | #ifdef CONFIG_PCI_IOV |
966 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); | |
967 | #endif | |
3a6a4eda | 968 | |
2a47fa45 JF |
969 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
970 | struct ixgbe_adapter *adapter, | |
971 | struct ixgbe_ring *tx_ring); | |
9a799d71 | 972 | #endif /* _IXGBE_H_ */ |