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ixgbe - DDP last user buffer - error to warn
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
9a799d71
AK		 56#define IXGBE_MAX_TXD 4096
57#define IXGBE_MIN_TXD 64
58
6bacb300 59#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 60#define IXGBE_MAX_RXD 4096
61#define IXGBE_MIN_RXD 64
62
9a799d71 63/* flow control */
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71 65#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 66#define IXGBE_MIN_FCRTH 0x600
9a799d71 67#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 68#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 69#define IXGBE_MIN_FCPAUSE 0
70#define IXGBE_MAX_FCPAUSE 0xFFFF
71
72/* Supported Rx Buffer Sizes */
13958070 73#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 74#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 75#define IXGBE_RXBUFFER_4096 4096
76#define IXGBE_RXBUFFER_8192 8192
32344a39 77#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 78
13958070
AD		 79/*
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
85 */
86#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 87
88#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
89
9a799d71
AK		 90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 97#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 99#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 100#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 101#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
102
0a924578
PWJ		 103#define IXGBE_MAX_RSC_INT_RATE 162760
104
7f870475
GR		 105#define IXGBE_MAX_VF_MC_ENTRIES 30
106#define IXGBE_MAX_VF_FUNCTIONS 64
107#define IXGBE_MAX_VFTA_ENTRIES 128
108#define MAX_EMULATION_MAC_ADDRS 16
a1cbb15c 109#define IXGBE_MAX_PF_MACVLANS 15
7f870475
GR		 110#define VMDQ_P(p) ((p) + adapter->num_vfs)
111
112struct vf_data_storage {
113 unsigned char vf_mac_addresses[ETH_ALEN];
114 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
115 u16 num_vf_mc_hashes;
116 u16 default_vf_vlan_id;
117 u16 vlans_enabled;
7f870475 118 bool clear_to_send;
7f01648a 119 bool pf_set_mac;
7f01648a
GR		 120 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
121 u16 pf_qos;
ff4ab206 122 u16 tx_rate;
7f870475
GR		 123};
124
a1cbb15c
GR		 125struct vf_macvlans {
126 struct list_head l;
127 int vf;
128 int rar_entry;
129 bool free;
130 bool is_macvlan;
131 u8 vf_macvlan[ETH_ALEN];
132};
133
a535c30e
AD		 134#define IXGBE_MAX_TXD_PWR 14
135#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
136
137/* Tx Descriptors needed, worst case */
138#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
139#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
140
9a799d71
AK		 141/* wrapper around a pointer to a socket buffer,
142 * so a DMA handle can be stored along with the buffer */
143struct ixgbe_tx_buffer {
144 struct sk_buff *skb;
145 dma_addr_t dma;
146 unsigned long time_stamp;
147 u16 length;
148 u16 next_to_watch;
8ad494b0
AD		 149 unsigned int bytecount;
150 u16 gso_segs;
151 u8 mapped_as_page;
9a799d71
AK		 152};
153
154struct ixgbe_rx_buffer {
155 struct sk_buff *skb;
156 dma_addr_t dma;
157 struct page *page;
158 dma_addr_t page_dma;
762f4c57 159 unsigned int page_offset;
9a799d71
AK		 160};
161
162struct ixgbe_queue_stats {
163 u64 packets;
164 u64 bytes;
165};
166
5b7da515
AD		 167struct ixgbe_tx_queue_stats {
168 u64 restart_queue;
169 u64 tx_busy;
c84d324c
JF		 170 u64 completed;
171 u64 tx_done_old;
5b7da515
AD		 172};
173
174struct ixgbe_rx_queue_stats {
175 u64 rsc_count;
176 u64 rsc_flush;
177 u64 non_eop_descs;
178 u64 alloc_rx_page_failed;
179 u64 alloc_rx_buff_failed;
180};
181
7d637bcc
AD		 182enum ixbge_ring_state_t {
183 __IXGBE_TX_FDIR_INIT_DONE,
184 __IXGBE_TX_DETECT_HANG,
c84d324c 185 __IXGBE_HANG_CHECK_ARMED,
7d637bcc
AD		 186 __IXGBE_RX_PS_ENABLED,
187 __IXGBE_RX_RSC_ENABLED,
188};
189
190#define ring_is_ps_enabled(ring) \
191 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
192#define set_ring_ps_enabled(ring) \
193 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
194#define clear_ring_ps_enabled(ring) \
195 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
196#define check_for_tx_hang(ring) \
197 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
198#define set_check_for_tx_hang(ring) \
199 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
200#define clear_check_for_tx_hang(ring) \
201 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
202#define ring_is_rsc_enabled(ring) \
203 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
204#define set_ring_rsc_enabled(ring) \
205 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
206#define clear_ring_rsc_enabled(ring) \
207 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 208struct ixgbe_ring {
9a799d71 209 void *desc; /* descriptor ring memory */
b6ec895e 210 struct device *dev; /* device for DMA mapping */
fc77dc3c 211 struct net_device *netdev; /* netdev ring belongs to */
9a799d71
AK		 212 union {
213 struct ixgbe_tx_buffer *tx_buffer_info;
214 struct ixgbe_rx_buffer *rx_buffer_info;
215 };
7d637bcc 216 unsigned long state;
bd198058
AD		 217 u8 __iomem *tail;
218
ae540af1
JB		 219 u16 count; /* amount of descriptors */
220 u16 rx_buf_len;
ae540af1
JB		 221
222 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 223 u8 reg_idx; /* holds the special value that gets
224 * the hardware register offset
225 * associated with this ring, which is
226 * different for DCB and RSS modes
227 */
bd198058
AD		 228 u8 atr_sample_rate;
229 u8 atr_count;
9a799d71 230
bd198058
AD		 231 u16 next_to_use;
232 u16 next_to_clean;
9a799d71 233
bd198058 234 u8 dcb_tc;
9a799d71 235 struct ixgbe_queue_stats stats;
de1036b1 236 struct u64_stats_sync syncp;
5b7da515
AD		 237 union {
238 struct ixgbe_tx_queue_stats tx_stats;
239 struct ixgbe_rx_queue_stats rx_stats;
240 };
5b7da515 241 int numa_node;
ae540af1
JB		 242 unsigned int size; /* length in bytes */
243 dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b 244 struct rcu_head rcu;
33cf09c9 245 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
7ca3bc58 246} ____cacheline_internodealigned_in_smp;
9a799d71 247
c7e4358a
SN		 248enum ixgbe_ring_f_enum {
249 RING_F_NONE = 0,
7f870475 250 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 251 RING_F_RSS,
c4cf55e5 252 RING_F_FDIR,
0331a832
YZ		 253#ifdef IXGBE_FCOE
254 RING_F_FCOE,
255#endif /* IXGBE_FCOE */
c7e4358a
SN		 256
257 RING_F_ARRAY_SIZE /* must be last in enum set */
258};
259
021230d4 260#define IXGBE_MAX_RSS_INDICES 16
7f870475 261#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 262#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 263#ifdef IXGBE_FCOE
264#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 265#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
266#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
267#else
268#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
269#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 270#endif /* IXGBE_FCOE */
021230d4
AV		 271struct ixgbe_ring_feature {
272 int indices;
273 int mask;
7ca3bc58 274} ____cacheline_internodealigned_in_smp;
021230d4 275
08c8833b
AD		 276struct ixgbe_ring_container {
277#if MAX_RX_QUEUES > MAX_TX_QUEUES
278 DECLARE_BITMAP(idx, MAX_RX_QUEUES);
279#else
280 DECLARE_BITMAP(idx, MAX_TX_QUEUES);
281#endif
bd198058
AD		 282 unsigned int total_bytes; /* total bytes processed this int */
283 unsigned int total_packets; /* total packets processed this int */
284 u16 work_limit; /* total work allowed per interrupt */
08c8833b
AD		 285 u8 count; /* total number of rings in vector */
286 u8 itr; /* current ITR setting for ring */
287};
021230d4 288
2f90b865
AD		 289#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
290 ? 8 : 1)
291#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
292
021230d4
AV		 293/* MAX_MSIX_Q_VECTORS of these are allocated,
294 * but we only use one per queue-specific vector.
295 */
296struct ixgbe_q_vector {
297 struct ixgbe_adapter *adapter;
fe49f04a
AD		 298 unsigned int v_idx; /* index of q_vector within array, also used for
299 * finding the bit in EICR and friends that
300 * represents the vector for this ring */
33cf09c9
AD		 301#ifdef CONFIG_IXGBE_DCA
302 int cpu; /* CPU for DCA */
303#endif
021230d4 304 struct napi_struct napi;
08c8833b 305 struct ixgbe_ring_container rx, tx;
021230d4 306 u32 eitr;
b25ebfd2 307 cpumask_var_t affinity_mask;
d0759ebb 308 char name[IFNAMSIZ + 9];
021230d4
AV		 309};
310
9a799d71 311/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 312 * And yes, it's the same math going both ways. The lowest value
313 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 314 */
315#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 316 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 317#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
318
7d4987de
AD		 319static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
320{
321 u16 ntc = ring->next_to_clean;
322 u16 ntu = ring->next_to_use;
323
324 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
325}
9a799d71
AK		 326
327#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 328 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 329#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 330 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 331#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 332 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 333
334#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 335#ifdef IXGBE_FCOE
336/* Use 3K as the baby jumbo frame size for FCoE */
337#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
338#endif /* IXGBE_FCOE */
9a799d71 339
021230d4
AV		 340#define OTHER_VECTOR 1
341#define NON_Q_VECTORS (OTHER_VECTOR)
342
e8e26350
PW		 343#define MAX_MSIX_VECTORS_82599 64
344#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 345#define MAX_MSIX_VECTORS_82598 18
346#define MAX_MSIX_Q_VECTORS_82598 16
347
e8e26350
PW		 348#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
349#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 350
021230d4 351#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 352#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
353
9a799d71
AK		 354/* board specific private data structure */
355struct ixgbe_adapter {
e606bfe7
AD		 356 unsigned long state;
357
358 /* Some features need tri-state capability,
359 * thus the additional *_CAPABLE flags.
360 */
361 u32 flags;
362#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
363#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
364#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
365#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
366#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
367#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
368#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
369#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
370#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
371#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
372#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
373#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
374#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
375#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
376#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
377#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
378#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
379#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
380#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
381#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
7086400d
AD		 382#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
383#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
384#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
385#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
386#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
387#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
388#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
e606bfe7
AD		 389
390 u32 flags2;
391#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
392#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
393#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
f0f9778d 394#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
7086400d
AD		 395#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
396#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
c83c6cbd 397#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
d034acf1 398#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
e606bfe7 399
f62bbb5e 400 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71 401 u16 bd_number;
7a921c93 402 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
d033d526
JF		 403
404 /* DCB parameters */
405 struct ieee_pfc *ixgbe_ieee_pfc;
406 struct ieee_ets *ixgbe_ieee_ets;
2f90b865
AD		 407 struct ixgbe_dcb_config dcb_cfg;
408 struct ixgbe_dcb_config temp_dcb_cfg;
409 u8 dcb_set_bitmap;
3032309b 410 u8 dcbx_cap;
264857b8 411 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 412
f494e8fa 413 /* Interrupt Throttle Rate */
f7554a2b
NS		 414 u32 rx_itr_setting;
415 u32 tx_itr_setting;
f494e8fa
AV		 416 u16 eitr_low;
417 u16 eitr_high;
418
bd198058
AD		 419 /* Work limits */
420 u16 tx_work_limit;
421
9a799d71 422 /* TX */
4a0b9ca0 423 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 424 int num_tx_queues;
9a799d71
AK		 425 u32 tx_timeout_count;
426 bool detect_tx_hung;
427
7ca3bc58
JB		 428 u64 restart_queue;
429 u64 lsc_int;
430
9a799d71 431 /* RX */
4a0b9ca0 432 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 433 int num_rx_queues;
7f870475
GR		 434 int num_rx_pools; /* == num_rx_queues in 82598 */
435 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 436 u64 hw_csum_rx_error;
e8e26350 437 u64 hw_rx_no_dma_resources;
9a799d71 438 u64 non_eop_descs;
021230d4 439 int num_msix_vectors;
eb7f139c 440 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 441 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 442 struct msix_entry *msix_entries;
443
9a799d71
AK		 444 u32 alloc_rx_page_failed;
445 u32 alloc_rx_buff_failed;
446
96b0e0f6
JB		 447/* default to trying for four seconds */
448#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 449
450 /* OS defined structs */
451 struct net_device *netdev;
452 struct pci_dev *pdev;
9a799d71 453
da4dd0f7
PWJ		 454 u32 test_icr;
455 struct ixgbe_ring test_tx_ring;
456 struct ixgbe_ring test_rx_ring;
457
9a799d71
AK		 458 /* structs defined in ixgbe_hw.h */
459 struct ixgbe_hw hw;
460 u16 msg_enable;
461 struct ixgbe_hw_stats stats;
021230d4
AV		 462
463 /* Interrupt Throttle Rate */
f7554a2b
NS		 464 u32 rx_eitr_param;
465 u32 tx_eitr_param;
9a799d71 466
9a799d71 467 u64 tx_busy;
30efa5a3
JB		 468 unsigned int tx_ring_count;
469 unsigned int rx_ring_count;
cf8280ee
JB		 470
471 u32 link_speed;
472 bool link_up;
473 unsigned long link_check_timeout;
474
7086400d 475 struct work_struct service_task;
7086400d 476 struct timer_list service_timer;
c4cf55e5
PWJ		 477 u32 fdir_pballoc;
478 u32 atr_sample_rate;
d034acf1 479 unsigned long fdir_overflow; /* number of times ATR was backed off */
c4cf55e5 480 spinlock_t fdir_perfect_lock;
d0ed8937
YZ		 481#ifdef IXGBE_FCOE
482 struct ixgbe_fcoe fcoe;
483#endif /* IXGBE_FCOE */
94b982b2
MC		 484 u64 rsc_total_count;
485 u64 rsc_total_flush;
e8e26350 486 u32 wol;
34b0368c 487 u16 eeprom_version;
7f870475 488
1a6c14a2 489 int node;
66e6961c 490 u32 led_reg;
119fc60a 491 u32 interrupt_event;
d0759ebb 492 char lsc_int_name[IFNAMSIZ + 9];
1a6c14a2 493
7f870475
GR		 494 /* SR-IOV */
495 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
496 unsigned int num_vfs;
497 struct vf_data_storage *vfinfo;
ff4ab206 498 int vf_rate_link_speed;
a1cbb15c
GR		 499 struct vf_macvlans vf_mvs;
500 struct vf_macvlans *mv_list;
501 bool antispoofing_enabled;
3e05334f
AD		 502
503 struct hlist_head fdir_filter_list;
504 union ixgbe_atr_input fdir_mask;
505 int fdir_filter_count;
506};
507
508struct ixgbe_fdir_filter {
509 struct hlist_node fdir_node;
510 union ixgbe_atr_input filter;
511 u16 sw_idx;
512 u16 action;
9a799d71
AK		 513};
514
515enum ixbge_state_t {
516 __IXGBE_TESTING,
517 __IXGBE_RESETTING,
c4900be0 518 __IXGBE_DOWN,
7086400d
AD		 519 __IXGBE_SERVICE_SCHED,
520 __IXGBE_IN_SFP_INIT,
9a799d71
AK		 521};
522
aa80175a
AD		 523struct ixgbe_rsc_cb {
524 dma_addr_t dma;
525 u16 skb_cnt;
526 bool delay_unmap;
527};
528#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
529
9a799d71 530enum ixgbe_boards {
3957d63d 531 board_82598,
e8e26350 532 board_82599,
fe15e8e1 533 board_X540,
9a799d71
AK		 534};
535
3957d63d 536extern struct ixgbe_info ixgbe_82598_info;
e8e26350 537extern struct ixgbe_info ixgbe_82599_info;
fe15e8e1 538extern struct ixgbe_info ixgbe_X540_info;
7a6b6f51 539#ifdef CONFIG_IXGBE_DCB
32953543 540extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 541extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
542 struct ixgbe_dcb_config *dst_dcb_cfg,
543 int tc_max);
544#endif
9a799d71
AK		 545
546extern char ixgbe_driver_name[];
9c8eb720 547extern const char ixgbe_driver_version[];
9a799d71
AK		 548
549extern int ixgbe_up(struct ixgbe_adapter *adapter);
550extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 551extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 552extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 553extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 554extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
555extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
556extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
557extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 558extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
559extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
2d39d576
YZ		 560extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
561 struct ixgbe_ring *);
b4617240 562extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 563extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 564extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 565extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 566 struct ixgbe_adapter *,
567 struct ixgbe_ring *);
b6ec895e 568extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 569 struct ixgbe_tx_buffer *);
fc77dc3c 570extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a
AD		 571extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
572extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772 573extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
c04f6ca8
AD		 574extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
575extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
ffff4772 576extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 577 union ixgbe_atr_hash_dword input,
578 union ixgbe_atr_hash_dword common,
ffff4772 579 u8 queue);
c04f6ca8
AD		 580extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
581 union ixgbe_atr_input *input_mask);
582extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
583 union ixgbe_atr_input *input,
584 u16 soft_id, u8 queue);
585extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
586 union ixgbe_atr_input *input,
587 u16 soft_id);
588extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
589 union ixgbe_atr_input *mask);
7f870475 590extern void ixgbe_set_rx_mode(struct net_device *netdev);
e5b64635 591extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
897ab156 592extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
082757af 593extern void ixgbe_do_reset(struct net_device *netdev);
eacd73f7
YZ		 594#ifdef IXGBE_FCOE
595extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
897ab156 596extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
eacd73f7 597 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 598extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
599extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
ff886dfc
AD		 600 union ixgbe_adv_rx_desc *rx_desc,
601 struct sk_buff *skb,
602 u32 staterr);
332d4a7d
YZ		 603extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
604 struct scatterlist *sgl, unsigned int sgc);
68a683cf
YZ		 605extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
606 struct scatterlist *sgl, unsigned int sgc);
332d4a7d 607extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 608extern int ixgbe_fcoe_enable(struct net_device *netdev);
609extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 610#ifdef CONFIG_IXGBE_DCB
611extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
612extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
613#endif /* CONFIG_IXGBE_DCB */
61a1fa10 614extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 615#endif /* IXGBE_FCOE */
9a799d71
AK		 616
617#endif /* _IXGBE_H_ */
Linux 6.x block layer and io_uring tree(s)