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i40evf: Change vf driver string to reflect all products i40evf supports
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
CommitLineData
7f12ad74
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
ecc6a239 4 * Copyright(c) 2013 - 2016 Intel Corporation.
7f12ad74
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
7f12ad74
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
7ed3f5f0 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
7ed3f5f0 29
7f12ad74 30#include "i40evf.h"
206812b5 31#include "i40e_prototype.h"
7f12ad74
GR		 32
33static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35{
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41}
42
43#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45/**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52{
53 if (tx_buffer->skb) {
a42e7a36 54 dev_kfree_skb_any(tx_buffer->skb);
7f12ad74
GR		 55 if (dma_unmap_len(tx_buffer, len))
56 dma_unmap_single(ring->dev,
57 dma_unmap_addr(tx_buffer, dma),
58 dma_unmap_len(tx_buffer, len),
59 DMA_TO_DEVICE);
60 } else if (dma_unmap_len(tx_buffer, len)) {
61 dma_unmap_page(ring->dev,
62 dma_unmap_addr(tx_buffer, dma),
63 dma_unmap_len(tx_buffer, len),
64 DMA_TO_DEVICE);
65 }
a42e7a36
KP		 66
67 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
68 kfree(tx_buffer->raw_buf);
69
7f12ad74
GR		 70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74}
75
76/**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81{
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
108}
109
110/**
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
113 *
114 * Free all transmit software resources
115 **/
116void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117{
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
121
122 if (tx_ring->desc) {
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
126 }
127}
128
a68de58d 129/**
9c6c1259
KP		 130 * i40evf_get_tx_pending - how many Tx descriptors not processed
131 * @tx_ring: the ring of descriptors
a68de58d 132 *
9c6c1259
KP		 133 * Since there is no access to the ring head register
134 * in XL710, we need to use our local copies
a68de58d 135 **/
9c6c1259 136u32 i40evf_get_tx_pending(struct i40e_ring *ring)
a68de58d 137{
9c6c1259 138 u32 head, tail;
a68de58d 139
9c6c1259
KP		 140 head = i40e_get_head(ring);
141 tail = readl(ring->tail);
142
143 if (head != tail)
144 return (head < tail) ?
145 tail - head : (tail + ring->count - head);
146
147 return 0;
a68de58d
JB		 148}
149
c29af37f
ASJ		 150#define WB_STRIDE 0x3
151
7f12ad74
GR		 152/**
153 * i40e_clean_tx_irq - Reclaim resources after transmit completes
154 * @tx_ring: tx ring to clean
155 * @budget: how many cleans we're allowed
156 *
157 * Returns true if there's any budget left (e.g. the clean is finished)
158 **/
159static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
160{
161 u16 i = tx_ring->next_to_clean;
162 struct i40e_tx_buffer *tx_buf;
1943d8ba 163 struct i40e_tx_desc *tx_head;
7f12ad74
GR		 164 struct i40e_tx_desc *tx_desc;
165 unsigned int total_packets = 0;
166 unsigned int total_bytes = 0;
167
168 tx_buf = &tx_ring->tx_bi[i];
169 tx_desc = I40E_TX_DESC(tx_ring, i);
170 i -= tx_ring->count;
171
1943d8ba
JB		 172 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
173
7f12ad74
GR		 174 do {
175 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
176
177 /* if next_to_watch is not set then there is no work pending */
178 if (!eop_desc)
179 break;
180
181 /* prevent any other reads prior to eop_desc */
182 read_barrier_depends();
183
1943d8ba
JB		 184 /* we have caught up to head, no work left to do */
185 if (tx_head == tx_desc)
7f12ad74
GR		 186 break;
187
188 /* clear next_to_watch to prevent false hangs */
189 tx_buf->next_to_watch = NULL;
190
191 /* update the statistics for this packet */
192 total_bytes += tx_buf->bytecount;
193 total_packets += tx_buf->gso_segs;
194
195 /* free the skb */
196 dev_kfree_skb_any(tx_buf->skb);
197
198 /* unmap skb header data */
199 dma_unmap_single(tx_ring->dev,
200 dma_unmap_addr(tx_buf, dma),
201 dma_unmap_len(tx_buf, len),
202 DMA_TO_DEVICE);
203
204 /* clear tx_buffer data */
205 tx_buf->skb = NULL;
206 dma_unmap_len_set(tx_buf, len, 0);
207
208 /* unmap remaining buffers */
209 while (tx_desc != eop_desc) {
210
211 tx_buf++;
212 tx_desc++;
213 i++;
214 if (unlikely(!i)) {
215 i -= tx_ring->count;
216 tx_buf = tx_ring->tx_bi;
217 tx_desc = I40E_TX_DESC(tx_ring, 0);
218 }
219
220 /* unmap any remaining paged data */
221 if (dma_unmap_len(tx_buf, len)) {
222 dma_unmap_page(tx_ring->dev,
223 dma_unmap_addr(tx_buf, dma),
224 dma_unmap_len(tx_buf, len),
225 DMA_TO_DEVICE);
226 dma_unmap_len_set(tx_buf, len, 0);
227 }
228 }
229
230 /* move us one more past the eop_desc for start of next pkt */
231 tx_buf++;
232 tx_desc++;
233 i++;
234 if (unlikely(!i)) {
235 i -= tx_ring->count;
236 tx_buf = tx_ring->tx_bi;
237 tx_desc = I40E_TX_DESC(tx_ring, 0);
238 }
239
016890b9
JB		 240 prefetch(tx_desc);
241
7f12ad74
GR		 242 /* update budget accounting */
243 budget--;
244 } while (likely(budget));
245
246 i += tx_ring->count;
247 tx_ring->next_to_clean = i;
248 u64_stats_update_begin(&tx_ring->syncp);
249 tx_ring->stats.bytes += total_bytes;
250 tx_ring->stats.packets += total_packets;
251 u64_stats_update_end(&tx_ring->syncp);
252 tx_ring->q_vector->tx.total_bytes += total_bytes;
253 tx_ring->q_vector->tx.total_packets += total_packets;
254
f6d83d13
ASJ		 255 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
256 unsigned int j = 0;
257 /* check to see if there are < 4 descriptors
258 * waiting to be written back, then kick the hardware to force
259 * them to be written back in case we stay in NAPI.
260 * In this mode on X722 we do not enable Interrupt.
261 */
262 j = i40evf_get_tx_pending(tx_ring);
263
264 if (budget &&
265 ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
266 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
267 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
268 tx_ring->arm_wb = true;
269 }
270
7f12ad74
GR		 271 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
272 tx_ring->queue_index),
273 total_packets, total_bytes);
274
275#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
276 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
277 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
278 /* Make sure that anybody stopping the queue after this
279 * sees the new next_to_clean.
280 */
281 smp_mb();
282 if (__netif_subqueue_stopped(tx_ring->netdev,
283 tx_ring->queue_index) &&
284 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
285 netif_wake_subqueue(tx_ring->netdev,
286 tx_ring->queue_index);
287 ++tx_ring->tx_stats.restart_queue;
288 }
289 }
290
b03a8c1f 291 return !!budget;
7f12ad74
GR		 292}
293
c29af37f 294/**
ecc6a239 295 * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
c29af37f 296 * @vsi: the VSI we care about
ecc6a239 297 * @q_vector: the vector on which to enable writeback
c29af37f
ASJ		 298 *
299 **/
ecc6a239
ASJ		 300static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
301 struct i40e_q_vector *q_vector)
c29af37f 302{
8e0764b4 303 u16 flags = q_vector->tx.ring[0].flags;
ecc6a239 304 u32 val;
8e0764b4 305
ecc6a239
ASJ		 306 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
307 return;
308
309 if (q_vector->arm_wb_state)
310 return;
311
312 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
313 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
314
315 wr32(&vsi->back->hw,
316 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
317 vsi->base_vector - 1), val);
318 q_vector->arm_wb_state = true;
319}
320
321/**
322 * i40evf_force_wb - Issue SW Interrupt so HW does a wb
323 * @vsi: the VSI we care about
324 * @q_vector: the vector on which to force writeback
325 *
326 **/
327void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
328{
329 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
330 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
331 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
332 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
333 /* allow 00 to be written to the index */;
334
335 wr32(&vsi->back->hw,
336 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
337 val);
c29af37f
ASJ		 338}
339
7f12ad74
GR		 340/**
341 * i40e_set_new_dynamic_itr - Find new ITR level
342 * @rc: structure containing ring performance data
343 *
8f5e39ce
JB		 344 * Returns true if ITR changed, false if not
345 *
7f12ad74
GR		 346 * Stores a new ITR value based on packets and byte counts during
347 * the last interrupt. The advantage of per interrupt computation
348 * is faster updates and more accurate ITR for the current traffic
349 * pattern. Constants in this function were computed based on
350 * theoretical maximum wire speed and thresholds were set based on
351 * testing data as well as attempting to minimize response time
352 * while increasing bulk throughput.
353 **/
8f5e39ce 354static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
7f12ad74
GR		 355{
356 enum i40e_latency_range new_latency_range = rc->latency_range;
c56625d5 357 struct i40e_q_vector *qv = rc->ring->q_vector;
7f12ad74
GR		 358 u32 new_itr = rc->itr;
359 int bytes_per_int;
51cc6d9f 360 int usecs;
7f12ad74
GR		 361
362 if (rc->total_packets == 0 || !rc->itr)
8f5e39ce 363 return false;
7f12ad74
GR		 364
365 /* simple throttlerate management
c56625d5 366 * 0-10MB/s lowest (50000 ints/s)
7f12ad74 367 * 10-20MB/s low (20000 ints/s)
c56625d5
JB		 368 * 20-1249MB/s bulk (18000 ints/s)
369 * > 40000 Rx packets per second (8000 ints/s)
51cc6d9f
JB		 370 *
371 * The math works out because the divisor is in 10^(-6) which
372 * turns the bytes/us input value into MB/s values, but
373 * make sure to use usecs, as the register values written
ee2319cf
JB		 374 * are in 2 usec increments in the ITR registers, and make sure
375 * to use the smoothed values that the countdown timer gives us.
7f12ad74 376 */
ee2319cf 377 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
51cc6d9f 378 bytes_per_int = rc->total_bytes / usecs;
ee2319cf 379
de32e3ef 380 switch (new_latency_range) {
7f12ad74
GR		 381 case I40E_LOWEST_LATENCY:
382 if (bytes_per_int > 10)
383 new_latency_range = I40E_LOW_LATENCY;
384 break;
385 case I40E_LOW_LATENCY:
386 if (bytes_per_int > 20)
387 new_latency_range = I40E_BULK_LATENCY;
388 else if (bytes_per_int <= 10)
389 new_latency_range = I40E_LOWEST_LATENCY;
390 break;
391 case I40E_BULK_LATENCY:
c56625d5 392 case I40E_ULTRA_LATENCY:
de32e3ef
CW		 393 default:
394 if (bytes_per_int <= 20)
395 new_latency_range = I40E_LOW_LATENCY;
7f12ad74
GR		 396 break;
397 }
c56625d5
JB		 398
399 /* this is to adjust RX more aggressively when streaming small
400 * packets. The value of 40000 was picked as it is just beyond
401 * what the hardware can receive per second if in low latency
402 * mode.
403 */
404#define RX_ULTRA_PACKET_RATE 40000
405
406 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
407 (&qv->rx == rc))
408 new_latency_range = I40E_ULTRA_LATENCY;
409
de32e3ef 410 rc->latency_range = new_latency_range;
7f12ad74
GR		 411
412 switch (new_latency_range) {
413 case I40E_LOWEST_LATENCY:
c56625d5 414 new_itr = I40E_ITR_50K;
7f12ad74
GR		 415 break;
416 case I40E_LOW_LATENCY:
417 new_itr = I40E_ITR_20K;
418 break;
419 case I40E_BULK_LATENCY:
c56625d5
JB		 420 new_itr = I40E_ITR_18K;
421 break;
422 case I40E_ULTRA_LATENCY:
7f12ad74
GR		 423 new_itr = I40E_ITR_8K;
424 break;
425 default:
426 break;
427 }
428
7f12ad74
GR		 429 rc->total_bytes = 0;
430 rc->total_packets = 0;
8f5e39ce
JB		 431
432 if (new_itr != rc->itr) {
433 rc->itr = new_itr;
434 return true;
435 }
436
437 return false;
7f12ad74
GR		 438}
439
4eeb1fff 440/**
7f12ad74
GR		 441 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
442 * @tx_ring: the tx ring to set up
443 *
444 * Return 0 on success, negative on error
445 **/
446int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
447{
448 struct device *dev = tx_ring->dev;
449 int bi_size;
450
451 if (!dev)
452 return -ENOMEM;
453
67c818a1
MW		 454 /* warn if we are about to overwrite the pointer */
455 WARN_ON(tx_ring->tx_bi);
7f12ad74
GR		 456 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
457 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
458 if (!tx_ring->tx_bi)
459 goto err;
460
461 /* round up to nearest 4K */
462 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 463 /* add u32 for head writeback, align after this takes care of
464 * guaranteeing this is at least one cache line in size
465 */
466 tx_ring->size += sizeof(u32);
7f12ad74
GR		 467 tx_ring->size = ALIGN(tx_ring->size, 4096);
468 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
469 &tx_ring->dma, GFP_KERNEL);
470 if (!tx_ring->desc) {
471 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
472 tx_ring->size);
473 goto err;
474 }
475
476 tx_ring->next_to_use = 0;
477 tx_ring->next_to_clean = 0;
478 return 0;
479
480err:
481 kfree(tx_ring->tx_bi);
482 tx_ring->tx_bi = NULL;
483 return -ENOMEM;
484}
485
486/**
487 * i40evf_clean_rx_ring - Free Rx buffers
488 * @rx_ring: ring to be cleaned
489 **/
490void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
491{
492 struct device *dev = rx_ring->dev;
493 struct i40e_rx_buffer *rx_bi;
494 unsigned long bi_size;
495 u16 i;
496
497 /* ring already cleared, nothing to do */
498 if (!rx_ring->rx_bi)
499 return;
500
a132af24
MW		 501 if (ring_is_ps_enabled(rx_ring)) {
502 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
503
504 rx_bi = &rx_ring->rx_bi[0];
505 if (rx_bi->hdr_buf) {
506 dma_free_coherent(dev,
507 bufsz,
508 rx_bi->hdr_buf,
509 rx_bi->dma);
510 for (i = 0; i < rx_ring->count; i++) {
511 rx_bi = &rx_ring->rx_bi[i];
512 rx_bi->dma = 0;
37a2973a 513 rx_bi->hdr_buf = NULL;
a132af24
MW		 514 }
515 }
516 }
7f12ad74
GR		 517 /* Free all the Rx ring sk_buffs */
518 for (i = 0; i < rx_ring->count; i++) {
519 rx_bi = &rx_ring->rx_bi[i];
520 if (rx_bi->dma) {
521 dma_unmap_single(dev,
522 rx_bi->dma,
523 rx_ring->rx_buf_len,
524 DMA_FROM_DEVICE);
525 rx_bi->dma = 0;
526 }
527 if (rx_bi->skb) {
528 dev_kfree_skb(rx_bi->skb);
529 rx_bi->skb = NULL;
530 }
531 if (rx_bi->page) {
532 if (rx_bi->page_dma) {
533 dma_unmap_page(dev,
534 rx_bi->page_dma,
535 PAGE_SIZE / 2,
536 DMA_FROM_DEVICE);
537 rx_bi->page_dma = 0;
538 }
539 __free_page(rx_bi->page);
540 rx_bi->page = NULL;
541 rx_bi->page_offset = 0;
542 }
543 }
544
545 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
546 memset(rx_ring->rx_bi, 0, bi_size);
547
548 /* Zero out the descriptor ring */
549 memset(rx_ring->desc, 0, rx_ring->size);
550
551 rx_ring->next_to_clean = 0;
552 rx_ring->next_to_use = 0;
553}
554
555/**
556 * i40evf_free_rx_resources - Free Rx resources
557 * @rx_ring: ring to clean the resources from
558 *
559 * Free all receive software resources
560 **/
561void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
562{
563 i40evf_clean_rx_ring(rx_ring);
564 kfree(rx_ring->rx_bi);
565 rx_ring->rx_bi = NULL;
566
567 if (rx_ring->desc) {
568 dma_free_coherent(rx_ring->dev, rx_ring->size,
569 rx_ring->desc, rx_ring->dma);
570 rx_ring->desc = NULL;
571 }
572}
573
a132af24
MW		 574/**
575 * i40evf_alloc_rx_headers - allocate rx header buffers
576 * @rx_ring: ring to alloc buffers
577 *
578 * Allocate rx header buffers for the entire ring. As these are static,
579 * this is only called when setting up a new ring.
580 **/
581void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
582{
583 struct device *dev = rx_ring->dev;
584 struct i40e_rx_buffer *rx_bi;
585 dma_addr_t dma;
586 void *buffer;
587 int buf_size;
588 int i;
589
590 if (rx_ring->rx_bi[0].hdr_buf)
591 return;
592 /* Make sure the buffers don't cross cache line boundaries. */
593 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
594 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
595 &dma, GFP_KERNEL);
596 if (!buffer)
597 return;
598 for (i = 0; i < rx_ring->count; i++) {
599 rx_bi = &rx_ring->rx_bi[i];
600 rx_bi->dma = dma + (i * buf_size);
601 rx_bi->hdr_buf = buffer + (i * buf_size);
602 }
603}
604
7f12ad74
GR		 605/**
606 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
607 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
608 *
609 * Returns 0 on success, negative on failure
610 **/
611int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
612{
613 struct device *dev = rx_ring->dev;
614 int bi_size;
615
67c818a1
MW		 616 /* warn if we are about to overwrite the pointer */
617 WARN_ON(rx_ring->rx_bi);
7f12ad74
GR		 618 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
619 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
620 if (!rx_ring->rx_bi)
621 goto err;
622
f217d6ca 623 u64_stats_init(&rx_ring->syncp);
638702bd 624
7f12ad74
GR		 625 /* Round up to nearest 4K */
626 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
627 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
628 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
629 rx_ring->size = ALIGN(rx_ring->size, 4096);
630 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
631 &rx_ring->dma, GFP_KERNEL);
632
633 if (!rx_ring->desc) {
634 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
635 rx_ring->size);
636 goto err;
637 }
638
639 rx_ring->next_to_clean = 0;
640 rx_ring->next_to_use = 0;
641
642 return 0;
643err:
644 kfree(rx_ring->rx_bi);
645 rx_ring->rx_bi = NULL;
646 return -ENOMEM;
647}
648
649/**
650 * i40e_release_rx_desc - Store the new tail and head values
651 * @rx_ring: ring to bump
652 * @val: new head index
653 **/
654static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
655{
656 rx_ring->next_to_use = val;
657 /* Force memory writes to complete before letting h/w
658 * know there are new descriptors to fetch. (Only
659 * applicable for weak-ordered memory model archs,
660 * such as IA-64).
661 */
662 wmb();
663 writel(val, rx_ring->tail);
664}
665
666/**
a132af24
MW		 667 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
668 * @rx_ring: ring to place buffers on
669 * @cleaned_count: number of buffers to replace
670 **/
671void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
672{
673 u16 i = rx_ring->next_to_use;
674 union i40e_rx_desc *rx_desc;
675 struct i40e_rx_buffer *bi;
676
677 /* do nothing if no valid netdev defined */
678 if (!rx_ring->netdev || !cleaned_count)
679 return;
680
681 while (cleaned_count--) {
682 rx_desc = I40E_RX_DESC(rx_ring, i);
683 bi = &rx_ring->rx_bi[i];
684
685 if (bi->skb) /* desc is in use */
686 goto no_buffers;
687 if (!bi->page) {
688 bi->page = alloc_page(GFP_ATOMIC);
689 if (!bi->page) {
690 rx_ring->rx_stats.alloc_page_failed++;
691 goto no_buffers;
692 }
693 }
694
695 if (!bi->page_dma) {
696 /* use a half page if we're re-using */
697 bi->page_offset ^= PAGE_SIZE / 2;
698 bi->page_dma = dma_map_page(rx_ring->dev,
699 bi->page,
700 bi->page_offset,
701 PAGE_SIZE / 2,
702 DMA_FROM_DEVICE);
703 if (dma_mapping_error(rx_ring->dev,
704 bi->page_dma)) {
705 rx_ring->rx_stats.alloc_page_failed++;
706 bi->page_dma = 0;
707 goto no_buffers;
708 }
709 }
710
711 dma_sync_single_range_for_device(rx_ring->dev,
3578fa0a
JB		 712 rx_ring->rx_bi[0].dma,
713 i * rx_ring->rx_hdr_len,
a132af24
MW		 714 rx_ring->rx_hdr_len,
715 DMA_FROM_DEVICE);
716 /* Refresh the desc even if buffer_addrs didn't change
717 * because each write-back erases this info.
718 */
719 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
720 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
721 i++;
722 if (i == rx_ring->count)
723 i = 0;
724 }
725
726no_buffers:
727 if (rx_ring->next_to_use != i)
728 i40e_release_rx_desc(rx_ring, i);
729}
730
731/**
732 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
7f12ad74
GR		 733 * @rx_ring: ring to place buffers on
734 * @cleaned_count: number of buffers to replace
735 **/
a132af24 736void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
7f12ad74
GR		 737{
738 u16 i = rx_ring->next_to_use;
739 union i40e_rx_desc *rx_desc;
740 struct i40e_rx_buffer *bi;
741 struct sk_buff *skb;
742
743 /* do nothing if no valid netdev defined */
744 if (!rx_ring->netdev || !cleaned_count)
745 return;
746
747 while (cleaned_count--) {
748 rx_desc = I40E_RX_DESC(rx_ring, i);
749 bi = &rx_ring->rx_bi[i];
750 skb = bi->skb;
751
752 if (!skb) {
753 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
754 rx_ring->rx_buf_len);
755 if (!skb) {
756 rx_ring->rx_stats.alloc_buff_failed++;
757 goto no_buffers;
758 }
759 /* initialize queue mapping */
760 skb_record_rx_queue(skb, rx_ring->queue_index);
761 bi->skb = skb;
762 }
763
764 if (!bi->dma) {
765 bi->dma = dma_map_single(rx_ring->dev,
766 skb->data,
767 rx_ring->rx_buf_len,
768 DMA_FROM_DEVICE);
769 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
770 rx_ring->rx_stats.alloc_buff_failed++;
771 bi->dma = 0;
772 goto no_buffers;
773 }
774 }
775
a132af24
MW		 776 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
777 rx_desc->read.hdr_addr = 0;
7f12ad74
GR		 778 i++;
779 if (i == rx_ring->count)
780 i = 0;
781 }
782
783no_buffers:
784 if (rx_ring->next_to_use != i)
785 i40e_release_rx_desc(rx_ring, i);
786}
787
788/**
789 * i40e_receive_skb - Send a completed packet up the stack
790 * @rx_ring: rx ring in play
791 * @skb: packet to send up
792 * @vlan_tag: vlan tag for packet
793 **/
794static void i40e_receive_skb(struct i40e_ring *rx_ring,
795 struct sk_buff *skb, u16 vlan_tag)
796{
797 struct i40e_q_vector *q_vector = rx_ring->q_vector;
7f12ad74
GR		 798
799 if (vlan_tag & VLAN_VID_MASK)
800 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
801
8b650359 802 napi_gro_receive(&q_vector->napi, skb);
7f12ad74
GR		 803}
804
805/**
806 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
807 * @vsi: the VSI we care about
808 * @skb: skb currently being received and modified
809 * @rx_status: status value of last descriptor in packet
810 * @rx_error: error value of last descriptor in packet
811 * @rx_ptype: ptype value of last descriptor in packet
812 **/
813static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
814 struct sk_buff *skb,
815 u32 rx_status,
816 u32 rx_error,
817 u16 rx_ptype)
818{
8a3c91cc
JB		 819 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
820 bool ipv4 = false, ipv6 = false;
7f12ad74
GR		 821 bool ipv4_tunnel, ipv6_tunnel;
822 __wsum rx_udp_csum;
7f12ad74 823 struct iphdr *iph;
8a3c91cc 824 __sum16 csum;
7f12ad74 825
f8faaa40
ASJ		 826 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
827 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
828 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
829 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
7f12ad74 830
7f12ad74
GR		 831 skb->ip_summed = CHECKSUM_NONE;
832
833 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 834 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
835 return;
836
837 /* did the hardware decode the packet and checksum? */
41a1d04b 838 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
8a3c91cc
JB		 839 return;
840
841 /* both known and outer_ip must be set for the below code to work */
842 if (!(decoded.known && decoded.outer_ip))
7f12ad74
GR		 843 return;
844
8a3c91cc
JB		 845 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
846 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
847 ipv4 = true;
848 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
849 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
850 ipv6 = true;
851
852 if (ipv4 &&
41a1d04b
JB		 853 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
854 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
8a3c91cc
JB		 855 goto checksum_fail;
856
ddf1d0d7 857 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 858 if (ipv6 &&
41a1d04b 859 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
8a3c91cc 860 /* don't increment checksum err here, non-fatal err */
7f12ad74
GR		 861 return;
862
8a3c91cc 863 /* there was some L4 error, count error and punt packet to the stack */
41a1d04b 864 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
8a3c91cc
JB		 865 goto checksum_fail;
866
867 /* handle packets that were not able to be checksummed due
868 * to arrival speed, in this case the stack can compute
869 * the csum.
870 */
41a1d04b 871 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
7f12ad74 872 return;
7f12ad74 873
8a3c91cc
JB		 874 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
875 * it in the driver, hardware does not do it for us.
876 * Since L3L4P bit was set we assume a valid IHL value (>=5)
877 * so the total length of IPv4 header is IHL*4 bytes
878 * The UDP_0 bit *may* bet set if the *inner* header is UDP
879 */
818f2e7b 880 if (ipv4_tunnel) {
7f12ad74
GR		 881 skb->transport_header = skb->mac_header +
882 sizeof(struct ethhdr) +
883 (ip_hdr(skb)->ihl * 4);
884
885 /* Add 4 bytes for VLAN tagged packets */
886 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
887 skb->protocol == htons(ETH_P_8021AD))
888 ? VLAN_HLEN : 0;
889
818f2e7b
ASJ		 890 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
891 (udp_hdr(skb)->check != 0)) {
892 rx_udp_csum = udp_csum(skb);
893 iph = ip_hdr(skb);
894 csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
895 (skb->len -
896 skb_transport_offset(skb)),
897 IPPROTO_UDP, rx_udp_csum);
7f12ad74 898
818f2e7b
ASJ		 899 if (udp_hdr(skb)->check != csum)
900 goto checksum_fail;
901
902 } /* else its GRE and so no outer UDP header */
7f12ad74
GR		 903 }
904
905 skb->ip_summed = CHECKSUM_UNNECESSARY;
407fa085 906 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 907
908 return;
909
910checksum_fail:
911 vsi->back->hw_csum_rx_error++;
7f12ad74
GR		 912}
913
914/**
857942fd 915 * i40e_ptype_to_htype - get a hash type
206812b5
JB		 916 * @ptype: the ptype value from the descriptor
917 *
918 * Returns a hash type to be used by skb_set_hash
919 **/
857942fd 920static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
206812b5
JB		 921{
922 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
923
924 if (!decoded.known)
925 return PKT_HASH_TYPE_NONE;
926
927 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
928 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
929 return PKT_HASH_TYPE_L4;
930 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
931 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
932 return PKT_HASH_TYPE_L3;
933 else
934 return PKT_HASH_TYPE_L2;
935}
936
857942fd
ASJ		 937/**
938 * i40e_rx_hash - set the hash value in the skb
939 * @ring: descriptor ring
940 * @rx_desc: specific descriptor
941 **/
942static inline void i40e_rx_hash(struct i40e_ring *ring,
943 union i40e_rx_desc *rx_desc,
944 struct sk_buff *skb,
945 u8 rx_ptype)
946{
947 u32 hash;
948 const __le64 rss_mask =
949 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
950 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
951
952 if (ring->netdev->features & NETIF_F_RXHASH)
953 return;
954
955 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
956 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
957 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
958 }
959}
960
7f12ad74 961/**
a132af24 962 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
7f12ad74
GR		 963 * @rx_ring: rx ring to clean
964 * @budget: how many cleans we're allowed
965 *
966 * Returns true if there's any budget left (e.g. the clean is finished)
967 **/
a132af24 968static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
7f12ad74
GR		 969{
970 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
971 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
972 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
27ca2753 973 const int current_node = numa_mem_id();
7f12ad74
GR		 974 struct i40e_vsi *vsi = rx_ring->vsi;
975 u16 i = rx_ring->next_to_clean;
976 union i40e_rx_desc *rx_desc;
977 u32 rx_error, rx_status;
206812b5 978 u8 rx_ptype;
7f12ad74 979 u64 qword;
7f12ad74 980
a132af24 981 do {
7f12ad74
GR		 982 struct i40e_rx_buffer *rx_bi;
983 struct sk_buff *skb;
984 u16 vlan_tag;
a132af24
MW		 985 /* return some buffers to hardware, one at a time is too slow */
986 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
987 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
988 cleaned_count = 0;
989 }
990
991 i = rx_ring->next_to_clean;
992 rx_desc = I40E_RX_DESC(rx_ring, i);
993 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
994 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
995 I40E_RXD_QW1_STATUS_SHIFT;
996
41a1d04b 997 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 998 break;
999
1000 /* This memory barrier is needed to keep us from reading
1001 * any other fields out of the rx_desc until we know the
1002 * DD bit is set.
1003 */
67317166 1004 dma_rmb();
7f12ad74
GR		 1005 rx_bi = &rx_ring->rx_bi[i];
1006 skb = rx_bi->skb;
a132af24
MW		 1007 if (likely(!skb)) {
1008 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1009 rx_ring->rx_hdr_len);
8b6ed9c2 1010 if (!skb) {
a132af24 1011 rx_ring->rx_stats.alloc_buff_failed++;
8b6ed9c2
JB		 1012 break;
1013 }
1014
a132af24
MW		 1015 /* initialize queue mapping */
1016 skb_record_rx_queue(skb, rx_ring->queue_index);
1017 /* we are reusing so sync this buffer for CPU use */
1018 dma_sync_single_range_for_cpu(rx_ring->dev,
3578fa0a
JB		 1019 rx_ring->rx_bi[0].dma,
1020 i * rx_ring->rx_hdr_len,
a132af24
MW		 1021 rx_ring->rx_hdr_len,
1022 DMA_FROM_DEVICE);
1023 }
7f12ad74
GR		 1024 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1025 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1026 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1027 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1028 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1029 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1030
1031 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1032 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b
JB		 1033 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1034 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
7f12ad74
GR		 1035
1036 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1037 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 1038 prefetch(rx_bi->page);
7f12ad74 1039 rx_bi->skb = NULL;
a132af24
MW		 1040 cleaned_count++;
1041 if (rx_hbo || rx_sph) {
1042 int len;
6995b36c 1043
7f12ad74
GR		 1044 if (rx_hbo)
1045 len = I40E_RX_HDR_SIZE;
7f12ad74 1046 else
a132af24
MW		 1047 len = rx_header_len;
1048 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1049 } else if (skb->len == 0) {
1050 int len;
1051
1052 len = (rx_packet_len > skb_headlen(skb) ?
1053 skb_headlen(skb) : rx_packet_len);
1054 memcpy(__skb_put(skb, len),
1055 rx_bi->page + rx_bi->page_offset,
1056 len);
1057 rx_bi->page_offset += len;
1058 rx_packet_len -= len;
7f12ad74
GR		 1059 }
1060
1061 /* Get the rest of the data if this was a header split */
a132af24 1062 if (rx_packet_len) {
7f12ad74
GR		 1063 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1064 rx_bi->page,
1065 rx_bi->page_offset,
1066 rx_packet_len);
1067
1068 skb->len += rx_packet_len;
1069 skb->data_len += rx_packet_len;
1070 skb->truesize += rx_packet_len;
1071
1072 if ((page_count(rx_bi->page) == 1) &&
1073 (page_to_nid(rx_bi->page) == current_node))
1074 get_page(rx_bi->page);
1075 else
1076 rx_bi->page = NULL;
1077
1078 dma_unmap_page(rx_ring->dev,
1079 rx_bi->page_dma,
1080 PAGE_SIZE / 2,
1081 DMA_FROM_DEVICE);
1082 rx_bi->page_dma = 0;
1083 }
a132af24 1084 I40E_RX_INCREMENT(rx_ring, i);
7f12ad74
GR		 1085
1086 if (unlikely(
41a1d04b 1087 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
7f12ad74
GR		 1088 struct i40e_rx_buffer *next_buffer;
1089
1090 next_buffer = &rx_ring->rx_bi[i];
a132af24 1091 next_buffer->skb = skb;
7f12ad74 1092 rx_ring->rx_stats.non_eop_descs++;
a132af24 1093 continue;
7f12ad74
GR		 1094 }
1095
1096 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1097 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
7f12ad74 1098 dev_kfree_skb_any(skb);
a132af24 1099 continue;
7f12ad74
GR		 1100 }
1101
857942fd
ASJ		 1102 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1103
7f12ad74
GR		 1104 /* probably a little skewed due to removing CRC */
1105 total_rx_bytes += skb->len;
1106 total_rx_packets++;
1107
1108 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1109
1110 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1111
41a1d04b 1112 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
7f12ad74
GR		 1113 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1114 : 0;
a132af24
MW		 1115#ifdef I40E_FCOE
1116 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1117 dev_kfree_skb_any(skb);
1118 continue;
1119 }
1120#endif
7f12ad74
GR		 1121 i40e_receive_skb(rx_ring, skb, vlan_tag);
1122
7f12ad74 1123 rx_desc->wb.qword1.status_error_len = 0;
7f12ad74 1124
a132af24
MW		 1125 } while (likely(total_rx_packets < budget));
1126
1127 u64_stats_update_begin(&rx_ring->syncp);
1128 rx_ring->stats.packets += total_rx_packets;
1129 rx_ring->stats.bytes += total_rx_bytes;
1130 u64_stats_update_end(&rx_ring->syncp);
1131 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1132 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1133
1134 return total_rx_packets;
1135}
1136
1137/**
1138 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1139 * @rx_ring: rx ring to clean
1140 * @budget: how many cleans we're allowed
1141 *
1142 * Returns number of packets cleaned
1143 **/
1144static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1145{
1146 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1147 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1148 struct i40e_vsi *vsi = rx_ring->vsi;
1149 union i40e_rx_desc *rx_desc;
1150 u32 rx_error, rx_status;
1151 u16 rx_packet_len;
1152 u8 rx_ptype;
1153 u64 qword;
1154 u16 i;
1155
1156 do {
1157 struct i40e_rx_buffer *rx_bi;
1158 struct sk_buff *skb;
1159 u16 vlan_tag;
7f12ad74
GR		 1160 /* return some buffers to hardware, one at a time is too slow */
1161 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1162 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
7f12ad74
GR		 1163 cleaned_count = 0;
1164 }
1165
a132af24
MW		 1166 i = rx_ring->next_to_clean;
1167 rx_desc = I40E_RX_DESC(rx_ring, i);
7f12ad74
GR		 1168 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1169 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1170 I40E_RXD_QW1_STATUS_SHIFT;
1171
41a1d04b 1172 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1173 break;
1174
1175 /* This memory barrier is needed to keep us from reading
1176 * any other fields out of the rx_desc until we know the
1177 * DD bit is set.
1178 */
67317166 1179 dma_rmb();
a132af24
MW		 1180
1181 rx_bi = &rx_ring->rx_bi[i];
1182 skb = rx_bi->skb;
1183 prefetch(skb->data);
1184
1185 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1186 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1187
1188 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1189 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b 1190 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
a132af24
MW		 1191
1192 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1193 I40E_RXD_QW1_PTYPE_SHIFT;
1194 rx_bi->skb = NULL;
1195 cleaned_count++;
1196
1197 /* Get the header and possibly the whole packet
1198 * If this is an skb from previous receive dma will be 0
1199 */
1200 skb_put(skb, rx_packet_len);
1201 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1202 DMA_FROM_DEVICE);
1203 rx_bi->dma = 0;
1204
1205 I40E_RX_INCREMENT(rx_ring, i);
1206
1207 if (unlikely(
41a1d04b 1208 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
a132af24
MW		 1209 rx_ring->rx_stats.non_eop_descs++;
1210 continue;
1211 }
1212
1213 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1214 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
a132af24 1215 dev_kfree_skb_any(skb);
a132af24
MW		 1216 continue;
1217 }
1218
857942fd 1219 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
a132af24
MW		 1220 /* probably a little skewed due to removing CRC */
1221 total_rx_bytes += skb->len;
1222 total_rx_packets++;
1223
1224 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1225
1226 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1227
41a1d04b 1228 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
a132af24
MW		 1229 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1230 : 0;
1231 i40e_receive_skb(rx_ring, skb, vlan_tag);
1232
a132af24
MW		 1233 rx_desc->wb.qword1.status_error_len = 0;
1234 } while (likely(total_rx_packets < budget));
7f12ad74 1235
7f12ad74
GR		 1236 u64_stats_update_begin(&rx_ring->syncp);
1237 rx_ring->stats.packets += total_rx_packets;
1238 rx_ring->stats.bytes += total_rx_bytes;
1239 u64_stats_update_end(&rx_ring->syncp);
1240 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1241 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1242
a132af24 1243 return total_rx_packets;
7f12ad74
GR		 1244}
1245
8f5e39ce
JB		 1246static u32 i40e_buildreg_itr(const int type, const u16 itr)
1247{
1248 u32 val;
1249
1250 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1251 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1252 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1253 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1254
1255 return val;
1256}
1257
1258/* a small macro to shorten up some long lines */
1259#define INTREG I40E_VFINT_DYN_CTLN1
1260
de32e3ef
CW		 1261/**
1262 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1263 * @vsi: the VSI we care about
1264 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1265 *
1266 **/
1267static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1268 struct i40e_q_vector *q_vector)
1269{
1270 struct i40e_hw *hw = &vsi->back->hw;
8f5e39ce
JB		 1271 bool rx = false, tx = false;
1272 u32 rxval, txval;
de32e3ef 1273 int vector;
de32e3ef
CW		 1274
1275 vector = (q_vector->v_idx + vsi->base_vector);
ee2319cf
JB		 1276
1277 /* avoid dynamic calculation if in countdown mode OR if
1278 * all dynamic is disabled
1279 */
8f5e39ce
JB		 1280 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1281
ee2319cf
JB		 1282 if (q_vector->itr_countdown > 0 ||
1283 (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1284 !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1285 goto enable_int;
1286 }
1287
de32e3ef 1288 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
8f5e39ce
JB		 1289 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1290 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
de32e3ef 1291 }
4eeb1fff 1292
de32e3ef 1293 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
8f5e39ce
JB		 1294 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1295 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1296 }
4eeb1fff 1297
8f5e39ce
JB		 1298 if (rx || tx) {
1299 /* get the higher of the two ITR adjustments and
1300 * use the same value for both ITR registers
1301 * when in adaptive mode (Rx and/or Tx)
1302 */
1303 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1304
1305 q_vector->tx.itr = q_vector->rx.itr = itr;
1306 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1307 tx = true;
1308 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1309 rx = true;
de32e3ef 1310 }
8f5e39ce
JB		 1311
1312 /* only need to enable the interrupt once, but need
1313 * to possibly update both ITR values
1314 */
1315 if (rx) {
1316 /* set the INTENA_MSK_MASK so that this first write
1317 * won't actually enable the interrupt, instead just
1318 * updating the ITR (it's bit 31 PF and VF)
1319 */
1320 rxval |= BIT(31);
1321 /* don't check _DOWN because interrupt isn't being enabled */
1322 wr32(hw, INTREG(vector - 1), rxval);
1323 }
1324
ee2319cf 1325enable_int:
8f5e39ce
JB		 1326 if (!test_bit(__I40E_DOWN, &vsi->state))
1327 wr32(hw, INTREG(vector - 1), txval);
ee2319cf
JB		 1328
1329 if (q_vector->itr_countdown)
1330 q_vector->itr_countdown--;
1331 else
1332 q_vector->itr_countdown = ITR_COUNTDOWN_START;
de32e3ef
CW		 1333}
1334
7f12ad74
GR		 1335/**
1336 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1337 * @napi: napi struct with our devices info in it
1338 * @budget: amount of work driver is allowed to do this pass, in packets
1339 *
1340 * This function will clean all queues associated with a q_vector.
1341 *
1342 * Returns the amount of work done
1343 **/
1344int i40evf_napi_poll(struct napi_struct *napi, int budget)
1345{
1346 struct i40e_q_vector *q_vector =
1347 container_of(napi, struct i40e_q_vector, napi);
1348 struct i40e_vsi *vsi = q_vector->vsi;
1349 struct i40e_ring *ring;
1350 bool clean_complete = true;
c29af37f 1351 bool arm_wb = false;
7f12ad74 1352 int budget_per_ring;
32b3e08f 1353 int work_done = 0;
7f12ad74
GR		 1354
1355 if (test_bit(__I40E_DOWN, &vsi->state)) {
1356 napi_complete(napi);
1357 return 0;
1358 }
1359
1360 /* Since the actual Tx work is minimal, we can give the Tx a larger
1361 * budget and be more aggressive about cleaning up the Tx descriptors.
1362 */
c29af37f 1363 i40e_for_each_ring(ring, q_vector->tx) {
7f12ad74 1364 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
44cdb791 1365 arm_wb = arm_wb || ring->arm_wb;
0deda868 1366 ring->arm_wb = false;
c29af37f 1367 }
7f12ad74 1368
c67caceb
AD		 1369 /* Handle case where we are called by netpoll with a budget of 0 */
1370 if (budget <= 0)
1371 goto tx_only;
1372
7f12ad74
GR		 1373 /* We attempt to distribute budget to each Rx queue fairly, but don't
1374 * allow the budget to go below 1 because that would exit polling early.
1375 */
1376 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1377
a132af24 1378 i40e_for_each_ring(ring, q_vector->rx) {
32b3e08f
JB		 1379 int cleaned;
1380
a132af24
MW		 1381 if (ring_is_ps_enabled(ring))
1382 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1383 else
1384 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
32b3e08f
JB		 1385
1386 work_done += cleaned;
a132af24
MW		 1387 /* if we didn't clean as many as budgeted, we must be done */
1388 clean_complete &= (budget_per_ring != cleaned);
1389 }
7f12ad74
GR		 1390
1391 /* If work not completed, return budget and polling will return */
c29af37f 1392 if (!clean_complete) {
c67caceb 1393tx_only:
164c9f54
ASJ		 1394 if (arm_wb) {
1395 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
ecc6a239 1396 i40e_enable_wb_on_itr(vsi, q_vector);
164c9f54 1397 }
7f12ad74 1398 return budget;
c29af37f 1399 }
7f12ad74 1400
8e0764b4
ASJ		 1401 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1402 q_vector->arm_wb_state = false;
1403
7f12ad74 1404 /* Work is done so exit the polling mode and re-enable the interrupt */
32b3e08f 1405 napi_complete_done(napi, work_done);
de32e3ef 1406 i40e_update_enable_itr(vsi, q_vector);
7f12ad74
GR		 1407 return 0;
1408}
1409
1410/**
3e587cf3 1411 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
7f12ad74
GR		 1412 * @skb: send buffer
1413 * @tx_ring: ring to send buffer on
1414 * @flags: the tx flags to be set
1415 *
1416 * Checks the skb and set up correspondingly several generic transmit flags
1417 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1418 *
1419 * Returns error code indicate the frame should be dropped upon error and the
1420 * otherwise returns 0 to indicate the flags has been set properly.
1421 **/
3e587cf3
JB		 1422static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1423 struct i40e_ring *tx_ring,
1424 u32 *flags)
7f12ad74
GR		 1425{
1426 __be16 protocol = skb->protocol;
1427 u32 tx_flags = 0;
1428
31eaaccf
GR		 1429 if (protocol == htons(ETH_P_8021Q) &&
1430 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1431 /* When HW VLAN acceleration is turned off by the user the
1432 * stack sets the protocol to 8021q so that the driver
1433 * can take any steps required to support the SW only
1434 * VLAN handling. In our case the driver doesn't need
1435 * to take any further steps so just set the protocol
1436 * to the encapsulated ethertype.
1437 */
1438 skb->protocol = vlan_get_protocol(skb);
1439 goto out;
1440 }
1441
7f12ad74 1442 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 1443 if (skb_vlan_tag_present(skb)) {
1444 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
7f12ad74
GR		 1445 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1446 /* else if it is a SW VLAN, check the next protocol and store the tag */
1447 } else if (protocol == htons(ETH_P_8021Q)) {
1448 struct vlan_hdr *vhdr, _vhdr;
6995b36c 1449
7f12ad74
GR		 1450 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1451 if (!vhdr)
1452 return -EINVAL;
1453
1454 protocol = vhdr->h_vlan_encapsulated_proto;
1455 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1456 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1457 }
1458
31eaaccf 1459out:
7f12ad74
GR		 1460 *flags = tx_flags;
1461 return 0;
1462}
1463
1464/**
1465 * i40e_tso - set up the tso context descriptor
1466 * @tx_ring: ptr to the ring to send
1467 * @skb: ptr to the skb we're sending
7f12ad74 1468 * @hdr_len: ptr to the size of the packet header
9c883bd3 1469 * @cd_type_cmd_tso_mss: Quad Word 1
7f12ad74
GR		 1470 *
1471 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1472 **/
1473static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
9c883bd3 1474 u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
7f12ad74
GR		 1475{
1476 u32 cd_cmd, cd_tso_len, cd_mss;
fe6d4aa4 1477 struct ipv6hdr *ipv6h;
7f12ad74
GR		 1478 struct tcphdr *tcph;
1479 struct iphdr *iph;
1480 u32 l4len;
1481 int err;
7f12ad74 1482
e9f6563d
SN		 1483 if (skb->ip_summed != CHECKSUM_PARTIAL)
1484 return 0;
1485
7f12ad74
GR		 1486 if (!skb_is_gso(skb))
1487 return 0;
1488
fe6d4aa4
FR		 1489 err = skb_cow_head(skb, 0);
1490 if (err < 0)
1491 return err;
7f12ad74 1492
85e76d03
AS		 1493 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1494 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1495
1496 if (iph->version == 4) {
7f12ad74
GR		 1497 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1498 iph->tot_len = 0;
1499 iph->check = 0;
1500 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1501 0, IPPROTO_TCP, 0);
85e76d03 1502 } else if (ipv6h->version == 6) {
7f12ad74
GR		 1503 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1504 ipv6h->payload_len = 0;
1505 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1506 0, IPPROTO_TCP, 0);
1507 }
1508
1509 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1510 *hdr_len = (skb->encapsulation
1511 ? (skb_inner_transport_header(skb) - skb->data)
1512 : skb_transport_offset(skb)) + l4len;
1513
1514 /* find the field values */
1515 cd_cmd = I40E_TX_CTX_DESC_TSO;
1516 cd_tso_len = skb->len - *hdr_len;
1517 cd_mss = skb_shinfo(skb)->gso_size;
1518 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1519 ((u64)cd_tso_len <<
1520 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1521 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1522 return 1;
1523}
1524
1525/**
1526 * i40e_tx_enable_csum - Enable Tx checksum offloads
1527 * @skb: send buffer
89232c3b 1528 * @tx_flags: pointer to Tx flags currently set
7f12ad74
GR		 1529 * @td_cmd: Tx descriptor command bits to set
1530 * @td_offset: Tx descriptor header offsets to set
1531 * @cd_tunneling: ptr to context desc bits
1532 **/
89232c3b 1533static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
7f12ad74
GR		 1534 u32 *td_cmd, u32 *td_offset,
1535 struct i40e_ring *tx_ring,
1536 u32 *cd_tunneling)
1537{
1538 struct ipv6hdr *this_ipv6_hdr;
1539 unsigned int this_tcp_hdrlen;
1540 struct iphdr *this_ip_hdr;
1541 u32 network_hdr_len;
1542 u8 l4_hdr = 0;
527274c7
ASJ		 1543 struct udphdr *oudph;
1544 struct iphdr *oiph;
45991204 1545 u32 l4_tunnel = 0;
7f12ad74
GR		 1546
1547 if (skb->encapsulation) {
45991204
ASJ		 1548 switch (ip_hdr(skb)->protocol) {
1549 case IPPROTO_UDP:
527274c7
ASJ		 1550 oudph = udp_hdr(skb);
1551 oiph = ip_hdr(skb);
45991204 1552 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
89232c3b 1553 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
45991204
ASJ		 1554 break;
1555 default:
1556 return;
1557 }
7f12ad74
GR		 1558 network_hdr_len = skb_inner_network_header_len(skb);
1559 this_ip_hdr = inner_ip_hdr(skb);
1560 this_ipv6_hdr = inner_ipv6_hdr(skb);
1561 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1562
89232c3b
ASJ		 1563 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1564 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1565 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1566 ip_hdr(skb)->check = 0;
1567 } else {
1568 *cd_tunneling |=
1569 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1570 }
89232c3b 1571 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
85e76d03 1572 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
89232c3b 1573 if (*tx_flags & I40E_TX_FLAGS_TSO)
7f12ad74 1574 ip_hdr(skb)->check = 0;
7f12ad74
GR		 1575 }
1576
1577 /* Now set the ctx descriptor fields */
1578 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
45991204
ASJ		 1579 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1580 l4_tunnel |
7f12ad74
GR		 1581 ((skb_inner_network_offset(skb) -
1582 skb_transport_offset(skb)) >> 1) <<
1583 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
85e76d03 1584 if (this_ip_hdr->version == 6) {
89232c3b
ASJ		 1585 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1586 *tx_flags |= I40E_TX_FLAGS_IPV6;
85e76d03
AS		 1587 }
1588
527274c7
ASJ		 1589 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1590 (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING) &&
1591 (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1592 oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1593 oiph->daddr,
1594 (skb->len - skb_transport_offset(skb)),
1595 IPPROTO_UDP, 0);
1596 *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1597 }
7f12ad74
GR		 1598 } else {
1599 network_hdr_len = skb_network_header_len(skb);
1600 this_ip_hdr = ip_hdr(skb);
1601 this_ipv6_hdr = ipv6_hdr(skb);
1602 this_tcp_hdrlen = tcp_hdrlen(skb);
1603 }
1604
1605 /* Enable IP checksum offloads */
89232c3b 1606 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
7f12ad74
GR		 1607 l4_hdr = this_ip_hdr->protocol;
1608 /* the stack computes the IP header already, the only time we
1609 * need the hardware to recompute it is in the case of TSO.
1610 */
89232c3b 1611 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1612 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1613 this_ip_hdr->check = 0;
1614 } else {
1615 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1616 }
1617 /* Now set the td_offset for IP header length */
1618 *td_offset = (network_hdr_len >> 2) <<
1619 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
89232c3b 1620 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
7f12ad74
GR		 1621 l4_hdr = this_ipv6_hdr->nexthdr;
1622 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1623 /* Now set the td_offset for IP header length */
1624 *td_offset = (network_hdr_len >> 2) <<
1625 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1626 }
1627 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1628 *td_offset |= (skb_network_offset(skb) >> 1) <<
1629 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1630
1631 /* Enable L4 checksum offloads */
1632 switch (l4_hdr) {
1633 case IPPROTO_TCP:
1634 /* enable checksum offloads */
1635 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1636 *td_offset |= (this_tcp_hdrlen >> 2) <<
1637 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1638 break;
1639 case IPPROTO_SCTP:
1640 /* enable SCTP checksum offload */
1641 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1642 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1643 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1644 break;
1645 case IPPROTO_UDP:
1646 /* enable UDP checksum offload */
1647 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1648 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1649 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1650 break;
1651 default:
1652 break;
1653 }
1654}
1655
1656/**
1657 * i40e_create_tx_ctx Build the Tx context descriptor
1658 * @tx_ring: ring to create the descriptor on
1659 * @cd_type_cmd_tso_mss: Quad Word 1
1660 * @cd_tunneling: Quad Word 0 - bits 0-31
1661 * @cd_l2tag2: Quad Word 0 - bits 32-63
1662 **/
1663static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1664 const u64 cd_type_cmd_tso_mss,
1665 const u32 cd_tunneling, const u32 cd_l2tag2)
1666{
1667 struct i40e_tx_context_desc *context_desc;
1668 int i = tx_ring->next_to_use;
1669
ff40dd5d
JB		 1670 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1671 !cd_tunneling && !cd_l2tag2)
7f12ad74
GR		 1672 return;
1673
1674 /* grab the next descriptor */
1675 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1676
1677 i++;
1678 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1679
1680 /* cpu_to_le32 and assign to struct fields */
1681 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1682 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 1683 context_desc->rsvd = cpu_to_le16(0);
7f12ad74
GR		 1684 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1685}
1686
4eeb1fff 1687/**
71da6197
AS		 1688 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1689 * @skb: send buffer
1690 * @tx_flags: collected send information
71da6197
AS		 1691 *
1692 * Note: Our HW can't scatter-gather more than 8 fragments to build
1693 * a packet on the wire and so we need to figure out the cases where we
1694 * need to linearize the skb.
1695 **/
30520831 1696static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
71da6197
AS		 1697{
1698 struct skb_frag_struct *frag;
1699 bool linearize = false;
1700 unsigned int size = 0;
1701 u16 num_frags;
1702 u16 gso_segs;
1703
1704 num_frags = skb_shinfo(skb)->nr_frags;
1705 gso_segs = skb_shinfo(skb)->gso_segs;
1706
1707 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
30520831 1708 u16 j = 0;
71da6197
AS		 1709
1710 if (num_frags < (I40E_MAX_BUFFER_TXD))
1711 goto linearize_chk_done;
1712 /* try the simple math, if we have too many frags per segment */
1713 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1714 I40E_MAX_BUFFER_TXD) {
1715 linearize = true;
1716 goto linearize_chk_done;
1717 }
1718 frag = &skb_shinfo(skb)->frags[0];
71da6197
AS		 1719 /* we might still have more fragments per segment */
1720 do {
1721 size += skb_frag_size(frag);
1722 frag++; j++;
30520831
ASJ		 1723 if ((size >= skb_shinfo(skb)->gso_size) &&
1724 (j < I40E_MAX_BUFFER_TXD)) {
1725 size = (size % skb_shinfo(skb)->gso_size);
1726 j = (size) ? 1 : 0;
1727 }
71da6197 1728 if (j == I40E_MAX_BUFFER_TXD) {
30520831
ASJ		 1729 linearize = true;
1730 break;
71da6197
AS		 1731 }
1732 num_frags--;
1733 } while (num_frags);
1734 } else {
1735 if (num_frags >= I40E_MAX_BUFFER_TXD)
1736 linearize = true;
1737 }
1738
1739linearize_chk_done:
1740 return linearize;
1741}
1742
8f6a2b05
JB		 1743/**
1744 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1745 * @tx_ring: the ring to be checked
1746 * @size: the size buffer we want to assure is available
1747 *
1748 * Returns -EBUSY if a stop is needed, else 0
1749 **/
1750static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1751{
1752 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1753 /* Memory barrier before checking head and tail */
1754 smp_mb();
1755
1756 /* Check again in a case another CPU has just made room available. */
1757 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1758 return -EBUSY;
1759
1760 /* A reprieve! - use start_queue because it doesn't call schedule */
1761 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1762 ++tx_ring->tx_stats.restart_queue;
1763 return 0;
1764}
1765
1766/**
1767 * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1768 * @tx_ring: the ring to be checked
1769 * @size: the size buffer we want to assure is available
1770 *
1771 * Returns 0 if stop is not needed
1772 **/
3e587cf3 1773static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
8f6a2b05
JB		 1774{
1775 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1776 return 0;
1777 return __i40evf_maybe_stop_tx(tx_ring, size);
1778}
1779
7f12ad74 1780/**
3e587cf3 1781 * i40evf_tx_map - Build the Tx descriptor
7f12ad74
GR		 1782 * @tx_ring: ring to send buffer on
1783 * @skb: send buffer
1784 * @first: first buffer info buffer to use
1785 * @tx_flags: collected send information
1786 * @hdr_len: size of the packet header
1787 * @td_cmd: the command field in the descriptor
1788 * @td_offset: offset for checksum or crc
1789 **/
3e587cf3
JB		 1790static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1791 struct i40e_tx_buffer *first, u32 tx_flags,
1792 const u8 hdr_len, u32 td_cmd, u32 td_offset)
7f12ad74
GR		 1793{
1794 unsigned int data_len = skb->data_len;
1795 unsigned int size = skb_headlen(skb);
1796 struct skb_frag_struct *frag;
1797 struct i40e_tx_buffer *tx_bi;
1798 struct i40e_tx_desc *tx_desc;
1799 u16 i = tx_ring->next_to_use;
1800 u32 td_tag = 0;
1801 dma_addr_t dma;
1802 u16 gso_segs;
6a7fded7
ASJ		 1803 u16 desc_count = 0;
1804 bool tail_bump = true;
1805 bool do_rs = false;
7f12ad74
GR		 1806
1807 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1808 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1809 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1810 I40E_TX_FLAGS_VLAN_SHIFT;
1811 }
1812
1813 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1814 gso_segs = skb_shinfo(skb)->gso_segs;
1815 else
1816 gso_segs = 1;
1817
1818 /* multiply data chunks by size of headers */
1819 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1820 first->gso_segs = gso_segs;
1821 first->skb = skb;
1822 first->tx_flags = tx_flags;
1823
1824 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1825
1826 tx_desc = I40E_TX_DESC(tx_ring, i);
1827 tx_bi = first;
1828
1829 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1830 if (dma_mapping_error(tx_ring->dev, dma))
1831 goto dma_error;
1832
1833 /* record length, and DMA address */
1834 dma_unmap_len_set(tx_bi, len, size);
1835 dma_unmap_addr_set(tx_bi, dma, dma);
1836
1837 tx_desc->buffer_addr = cpu_to_le64(dma);
1838
1839 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1840 tx_desc->cmd_type_offset_bsz =
1841 build_ctob(td_cmd, td_offset,
1842 I40E_MAX_DATA_PER_TXD, td_tag);
1843
1844 tx_desc++;
1845 i++;
6a7fded7
ASJ		 1846 desc_count++;
1847
7f12ad74
GR		 1848 if (i == tx_ring->count) {
1849 tx_desc = I40E_TX_DESC(tx_ring, 0);
1850 i = 0;
1851 }
1852
1853 dma += I40E_MAX_DATA_PER_TXD;
1854 size -= I40E_MAX_DATA_PER_TXD;
1855
1856 tx_desc->buffer_addr = cpu_to_le64(dma);
1857 }
1858
1859 if (likely(!data_len))
1860 break;
1861
1862 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1863 size, td_tag);
1864
1865 tx_desc++;
1866 i++;
6a7fded7
ASJ		 1867 desc_count++;
1868
7f12ad74
GR		 1869 if (i == tx_ring->count) {
1870 tx_desc = I40E_TX_DESC(tx_ring, 0);
1871 i = 0;
1872 }
1873
1874 size = skb_frag_size(frag);
1875 data_len -= size;
1876
1877 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1878 DMA_TO_DEVICE);
1879
1880 tx_bi = &tx_ring->tx_bi[i];
1881 }
1882
7f12ad74
GR		 1883 /* set next_to_watch value indicating a packet is present */
1884 first->next_to_watch = tx_desc;
1885
1886 i++;
1887 if (i == tx_ring->count)
1888 i = 0;
1889
1890 tx_ring->next_to_use = i;
1891
6a7fded7
ASJ		 1892 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1893 tx_ring->queue_index),
1894 first->bytecount);
8f6a2b05 1895 i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
6a7fded7
ASJ		 1896
1897 /* Algorithm to optimize tail and RS bit setting:
1898 * if xmit_more is supported
1899 * if xmit_more is true
1900 * do not update tail and do not mark RS bit.
1901 * if xmit_more is false and last xmit_more was false
1902 * if every packet spanned less than 4 desc
1903 * then set RS bit on 4th packet and update tail
1904 * on every packet
1905 * else
1906 * update tail and set RS bit on every packet.
1907 * if xmit_more is false and last_xmit_more was true
1908 * update tail and set RS bit.
6a7fded7
ASJ		 1909 *
1910 * Optimization: wmb to be issued only in case of tail update.
1911 * Also optimize the Descriptor WB path for RS bit with the same
1912 * algorithm.
1913 *
1914 * Note: If there are less than 4 packets
1915 * pending and interrupts were disabled the service task will
1916 * trigger a force WB.
1917 */
1918 if (skb->xmit_more &&
1919 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1920 tx_ring->queue_index))) {
1921 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1922 tail_bump = false;
1923 } else if (!skb->xmit_more &&
1924 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1925 tx_ring->queue_index)) &&
1926 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1927 (tx_ring->packet_stride < WB_STRIDE) &&
1928 (desc_count < WB_STRIDE)) {
1929 tx_ring->packet_stride++;
1930 } else {
1931 tx_ring->packet_stride = 0;
1932 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1933 do_rs = true;
1934 }
1935 if (do_rs)
1936 tx_ring->packet_stride = 0;
1937
1938 tx_desc->cmd_type_offset_bsz =
1939 build_ctob(td_cmd, td_offset, size, td_tag) |
1940 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1941 I40E_TX_DESC_CMD_EOP) <<
1942 I40E_TXD_QW1_CMD_SHIFT);
1943
7f12ad74 1944 /* notify HW of packet */
6a7fded7 1945 if (!tail_bump)
489ce7a4 1946 prefetchw(tx_desc + 1);
7f12ad74 1947
6a7fded7
ASJ		 1948 if (tail_bump) {
1949 /* Force memory writes to complete before letting h/w
1950 * know there are new descriptors to fetch. (Only
1951 * applicable for weak-ordered memory model archs,
1952 * such as IA-64).
1953 */
1954 wmb();
1955 writel(i, tx_ring->tail);
1956 }
1957
7f12ad74
GR		 1958 return;
1959
1960dma_error:
1961 dev_info(tx_ring->dev, "TX DMA map failed\n");
1962
1963 /* clear dma mappings for failed tx_bi map */
1964 for (;;) {
1965 tx_bi = &tx_ring->tx_bi[i];
1966 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1967 if (tx_bi == first)
1968 break;
1969 if (i == 0)
1970 i = tx_ring->count;
1971 i--;
1972 }
1973
1974 tx_ring->next_to_use = i;
1975}
1976
7f12ad74 1977/**
3e587cf3 1978 * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
7f12ad74
GR		 1979 * @skb: send buffer
1980 * @tx_ring: ring to send buffer on
1981 *
1982 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1983 * there is not enough descriptors available in this ring since we need at least
1984 * one descriptor.
1985 **/
3e587cf3
JB		 1986static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1987 struct i40e_ring *tx_ring)
7f12ad74 1988{
7f12ad74 1989 unsigned int f;
7f12ad74
GR		 1990 int count = 0;
1991
1992 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1993 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 1994 * + 4 desc gap to avoid the cache line where head is,
7f12ad74
GR		 1995 * + 1 desc for context descriptor,
1996 * otherwise try next time
1997 */
7f12ad74
GR		 1998 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1999 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 2000
7f12ad74 2001 count += TXD_USE_COUNT(skb_headlen(skb));
8f6a2b05 2002 if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
7f12ad74
GR		 2003 tx_ring->tx_stats.tx_busy++;
2004 return 0;
2005 }
2006 return count;
2007}
2008
2009/**
2010 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2011 * @skb: send buffer
2012 * @tx_ring: ring to send buffer on
2013 *
2014 * Returns NETDEV_TX_OK if sent, else an error code
2015 **/
2016static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2017 struct i40e_ring *tx_ring)
2018{
2019 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2020 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2021 struct i40e_tx_buffer *first;
2022 u32 td_offset = 0;
2023 u32 tx_flags = 0;
2024 __be16 protocol;
2025 u32 td_cmd = 0;
2026 u8 hdr_len = 0;
2027 int tso;
6995b36c 2028
b74118f0
JB		 2029 /* prefetch the data, we'll need it later */
2030 prefetch(skb->data);
2031
3e587cf3 2032 if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
7f12ad74
GR		 2033 return NETDEV_TX_BUSY;
2034
2035 /* prepare the xmit flags */
3e587cf3 2036 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
7f12ad74
GR		 2037 goto out_drop;
2038
2039 /* obtain protocol of skb */
a12c4158 2040 protocol = vlan_get_protocol(skb);
7f12ad74
GR		 2041
2042 /* record the location of the first descriptor for this packet */
2043 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2044
2045 /* setup IPv4/IPv6 offloads */
2046 if (protocol == htons(ETH_P_IP))
2047 tx_flags |= I40E_TX_FLAGS_IPV4;
2048 else if (protocol == htons(ETH_P_IPV6))
2049 tx_flags |= I40E_TX_FLAGS_IPV6;
2050
9c883bd3 2051 tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
7f12ad74
GR		 2052
2053 if (tso < 0)
2054 goto out_drop;
2055 else if (tso)
2056 tx_flags |= I40E_TX_FLAGS_TSO;
2057
2fc3d715 2058 if (i40e_chk_linearize(skb, tx_flags)) {
71da6197
AS		 2059 if (skb_linearize(skb))
2060 goto out_drop;
2fc3d715
ASJ		 2061 tx_ring->tx_stats.tx_linearize++;
2062 }
7f12ad74
GR		 2063 skb_tx_timestamp(skb);
2064
2065 /* always enable CRC insertion offload */
2066 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2067
2068 /* Always offload the checksum, since it's in the data descriptor */
2069 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2070 tx_flags |= I40E_TX_FLAGS_CSUM;
2071
89232c3b 2072 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
7f12ad74
GR		 2073 tx_ring, &cd_tunneling);
2074 }
2075
2076 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2077 cd_tunneling, cd_l2tag2);
2078
3e587cf3
JB		 2079 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2080 td_cmd, td_offset);
7f12ad74 2081
7f12ad74
GR		 2082 return NETDEV_TX_OK;
2083
2084out_drop:
2085 dev_kfree_skb_any(skb);
2086 return NETDEV_TX_OK;
2087}
2088
2089/**
2090 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2091 * @skb: send buffer
2092 * @netdev: network interface device structure
2093 *
2094 * Returns NETDEV_TX_OK if sent, else an error code
2095 **/
2096netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2097{
2098 struct i40evf_adapter *adapter = netdev_priv(netdev);
0dd438d8 2099 struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
7f12ad74
GR		 2100
2101 /* hardware can't handle really short frames, hardware padding works
2102 * beyond this point
2103 */
2104 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2105 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2106 return NETDEV_TX_OK;
2107 skb->len = I40E_MIN_TX_LEN;
2108 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2109 }
2110
2111 return i40e_xmit_frame_ring(skb, tx_ring);
2112}
Linux 6.x block layer and io_uring tree(s)