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i40evf: allocate queue vectors dynamically
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
CommitLineData
7f12ad74
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
af1a2a9c 4 * Copyright(c) 2013 - 2014 Intel Corporation.
7f12ad74
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
7f12ad74
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
7ed3f5f0 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
7ed3f5f0 29
7f12ad74 30#include "i40evf.h"
206812b5 31#include "i40e_prototype.h"
7f12ad74
GR		 32
33static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35{
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41}
42
43#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45/**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52{
53 if (tx_buffer->skb) {
49d7d933
ASJ		 54 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
55 kfree(tx_buffer->raw_buf);
56 else
57 dev_kfree_skb_any(tx_buffer->skb);
58
7f12ad74
GR		 59 if (dma_unmap_len(tx_buffer, len))
60 dma_unmap_single(ring->dev,
61 dma_unmap_addr(tx_buffer, dma),
62 dma_unmap_len(tx_buffer, len),
63 DMA_TO_DEVICE);
64 } else if (dma_unmap_len(tx_buffer, len)) {
65 dma_unmap_page(ring->dev,
66 dma_unmap_addr(tx_buffer, dma),
67 dma_unmap_len(tx_buffer, len),
68 DMA_TO_DEVICE);
69 }
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74}
75
76/**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81{
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
108}
109
110/**
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
113 *
114 * Free all transmit software resources
115 **/
116void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117{
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
121
122 if (tx_ring->desc) {
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
126 }
127}
128
a68de58d
JB		 129/**
130 * i40e_get_head - Retrieve head from head writeback
131 * @tx_ring: tx ring to fetch head of
132 *
133 * Returns value of Tx ring head based on value stored
134 * in head write-back location
135 **/
136static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
137{
138 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
139
140 return le32_to_cpu(*(volatile __le32 *)head);
141}
142
c29af37f
ASJ		 143#define WB_STRIDE 0x3
144
7f12ad74
GR		 145/**
146 * i40e_clean_tx_irq - Reclaim resources after transmit completes
147 * @tx_ring: tx ring to clean
148 * @budget: how many cleans we're allowed
149 *
150 * Returns true if there's any budget left (e.g. the clean is finished)
151 **/
152static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
153{
154 u16 i = tx_ring->next_to_clean;
155 struct i40e_tx_buffer *tx_buf;
1943d8ba 156 struct i40e_tx_desc *tx_head;
7f12ad74
GR		 157 struct i40e_tx_desc *tx_desc;
158 unsigned int total_packets = 0;
159 unsigned int total_bytes = 0;
160
161 tx_buf = &tx_ring->tx_bi[i];
162 tx_desc = I40E_TX_DESC(tx_ring, i);
163 i -= tx_ring->count;
164
1943d8ba
JB		 165 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
166
7f12ad74
GR		 167 do {
168 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
169
170 /* if next_to_watch is not set then there is no work pending */
171 if (!eop_desc)
172 break;
173
174 /* prevent any other reads prior to eop_desc */
175 read_barrier_depends();
176
1943d8ba
JB		 177 /* we have caught up to head, no work left to do */
178 if (tx_head == tx_desc)
7f12ad74
GR		 179 break;
180
181 /* clear next_to_watch to prevent false hangs */
182 tx_buf->next_to_watch = NULL;
183
184 /* update the statistics for this packet */
185 total_bytes += tx_buf->bytecount;
186 total_packets += tx_buf->gso_segs;
187
188 /* free the skb */
189 dev_kfree_skb_any(tx_buf->skb);
190
191 /* unmap skb header data */
192 dma_unmap_single(tx_ring->dev,
193 dma_unmap_addr(tx_buf, dma),
194 dma_unmap_len(tx_buf, len),
195 DMA_TO_DEVICE);
196
197 /* clear tx_buffer data */
198 tx_buf->skb = NULL;
199 dma_unmap_len_set(tx_buf, len, 0);
200
201 /* unmap remaining buffers */
202 while (tx_desc != eop_desc) {
203
204 tx_buf++;
205 tx_desc++;
206 i++;
207 if (unlikely(!i)) {
208 i -= tx_ring->count;
209 tx_buf = tx_ring->tx_bi;
210 tx_desc = I40E_TX_DESC(tx_ring, 0);
211 }
212
213 /* unmap any remaining paged data */
214 if (dma_unmap_len(tx_buf, len)) {
215 dma_unmap_page(tx_ring->dev,
216 dma_unmap_addr(tx_buf, dma),
217 dma_unmap_len(tx_buf, len),
218 DMA_TO_DEVICE);
219 dma_unmap_len_set(tx_buf, len, 0);
220 }
221 }
222
223 /* move us one more past the eop_desc for start of next pkt */
224 tx_buf++;
225 tx_desc++;
226 i++;
227 if (unlikely(!i)) {
228 i -= tx_ring->count;
229 tx_buf = tx_ring->tx_bi;
230 tx_desc = I40E_TX_DESC(tx_ring, 0);
231 }
232
016890b9
JB		 233 prefetch(tx_desc);
234
7f12ad74
GR		 235 /* update budget accounting */
236 budget--;
237 } while (likely(budget));
238
239 i += tx_ring->count;
240 tx_ring->next_to_clean = i;
241 u64_stats_update_begin(&tx_ring->syncp);
242 tx_ring->stats.bytes += total_bytes;
243 tx_ring->stats.packets += total_packets;
244 u64_stats_update_end(&tx_ring->syncp);
245 tx_ring->q_vector->tx.total_bytes += total_bytes;
246 tx_ring->q_vector->tx.total_packets += total_packets;
247
7f12ad74
GR		 248 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
249 tx_ring->queue_index),
250 total_packets, total_bytes);
251
252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
254 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
255 /* Make sure that anybody stopping the queue after this
256 * sees the new next_to_clean.
257 */
258 smp_mb();
259 if (__netif_subqueue_stopped(tx_ring->netdev,
260 tx_ring->queue_index) &&
261 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
262 netif_wake_subqueue(tx_ring->netdev,
263 tx_ring->queue_index);
264 ++tx_ring->tx_stats.restart_queue;
265 }
266 }
267
b03a8c1f 268 return !!budget;
7f12ad74
GR		 269}
270
c29af37f 271/**
b03a8c1f 272 * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
c29af37f
ASJ		 273 * @vsi: the VSI we care about
274 * @q_vector: the vector on which to force writeback
275 *
276 **/
b03a8c1f 277static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
c29af37f 278{
8e0764b4
ASJ		 279 u16 flags = q_vector->tx.ring[0].flags;
280
281 if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
282 u32 val;
283
284 if (q_vector->arm_wb_state)
285 return;
286
287 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
288
289 wr32(&vsi->back->hw,
290 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
291 vsi->base_vector - 1),
292 val);
293 q_vector->arm_wb_state = true;
294 } else {
295 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
296 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
297 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
298 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
299 /* allow 00 to be written to the index */
300
301 wr32(&vsi->back->hw,
302 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
303 vsi->base_vector - 1), val);
304 }
c29af37f
ASJ		 305}
306
7f12ad74
GR		 307/**
308 * i40e_set_new_dynamic_itr - Find new ITR level
309 * @rc: structure containing ring performance data
310 *
8f5e39ce
JB		 311 * Returns true if ITR changed, false if not
312 *
7f12ad74
GR		 313 * Stores a new ITR value based on packets and byte counts during
314 * the last interrupt. The advantage of per interrupt computation
315 * is faster updates and more accurate ITR for the current traffic
316 * pattern. Constants in this function were computed based on
317 * theoretical maximum wire speed and thresholds were set based on
318 * testing data as well as attempting to minimize response time
319 * while increasing bulk throughput.
320 **/
8f5e39ce 321static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
7f12ad74
GR		 322{
323 enum i40e_latency_range new_latency_range = rc->latency_range;
c56625d5 324 struct i40e_q_vector *qv = rc->ring->q_vector;
7f12ad74
GR		 325 u32 new_itr = rc->itr;
326 int bytes_per_int;
51cc6d9f 327 int usecs;
7f12ad74
GR		 328
329 if (rc->total_packets == 0 || !rc->itr)
8f5e39ce 330 return false;
7f12ad74
GR		 331
332 /* simple throttlerate management
c56625d5 333 * 0-10MB/s lowest (50000 ints/s)
7f12ad74 334 * 10-20MB/s low (20000 ints/s)
c56625d5
JB		 335 * 20-1249MB/s bulk (18000 ints/s)
336 * > 40000 Rx packets per second (8000 ints/s)
51cc6d9f
JB		 337 *
338 * The math works out because the divisor is in 10^(-6) which
339 * turns the bytes/us input value into MB/s values, but
340 * make sure to use usecs, as the register values written
ee2319cf
JB		 341 * are in 2 usec increments in the ITR registers, and make sure
342 * to use the smoothed values that the countdown timer gives us.
7f12ad74 343 */
ee2319cf 344 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
51cc6d9f 345 bytes_per_int = rc->total_bytes / usecs;
ee2319cf 346
de32e3ef 347 switch (new_latency_range) {
7f12ad74
GR		 348 case I40E_LOWEST_LATENCY:
349 if (bytes_per_int > 10)
350 new_latency_range = I40E_LOW_LATENCY;
351 break;
352 case I40E_LOW_LATENCY:
353 if (bytes_per_int > 20)
354 new_latency_range = I40E_BULK_LATENCY;
355 else if (bytes_per_int <= 10)
356 new_latency_range = I40E_LOWEST_LATENCY;
357 break;
358 case I40E_BULK_LATENCY:
c56625d5 359 case I40E_ULTRA_LATENCY:
de32e3ef
CW		 360 default:
361 if (bytes_per_int <= 20)
362 new_latency_range = I40E_LOW_LATENCY;
7f12ad74
GR		 363 break;
364 }
c56625d5
JB		 365
366 /* this is to adjust RX more aggressively when streaming small
367 * packets. The value of 40000 was picked as it is just beyond
368 * what the hardware can receive per second if in low latency
369 * mode.
370 */
371#define RX_ULTRA_PACKET_RATE 40000
372
373 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
374 (&qv->rx == rc))
375 new_latency_range = I40E_ULTRA_LATENCY;
376
de32e3ef 377 rc->latency_range = new_latency_range;
7f12ad74
GR		 378
379 switch (new_latency_range) {
380 case I40E_LOWEST_LATENCY:
c56625d5 381 new_itr = I40E_ITR_50K;
7f12ad74
GR		 382 break;
383 case I40E_LOW_LATENCY:
384 new_itr = I40E_ITR_20K;
385 break;
386 case I40E_BULK_LATENCY:
c56625d5
JB		 387 new_itr = I40E_ITR_18K;
388 break;
389 case I40E_ULTRA_LATENCY:
7f12ad74
GR		 390 new_itr = I40E_ITR_8K;
391 break;
392 default:
393 break;
394 }
395
7f12ad74
GR		 396 rc->total_bytes = 0;
397 rc->total_packets = 0;
8f5e39ce
JB		 398
399 if (new_itr != rc->itr) {
400 rc->itr = new_itr;
401 return true;
402 }
403
404 return false;
7f12ad74
GR		 405}
406
de32e3ef 407/*
7f12ad74
GR		 408 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
409 * @tx_ring: the tx ring to set up
410 *
411 * Return 0 on success, negative on error
412 **/
413int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
414{
415 struct device *dev = tx_ring->dev;
416 int bi_size;
417
418 if (!dev)
419 return -ENOMEM;
420
67c818a1
MW		 421 /* warn if we are about to overwrite the pointer */
422 WARN_ON(tx_ring->tx_bi);
7f12ad74
GR		 423 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
424 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
425 if (!tx_ring->tx_bi)
426 goto err;
427
428 /* round up to nearest 4K */
429 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 430 /* add u32 for head writeback, align after this takes care of
431 * guaranteeing this is at least one cache line in size
432 */
433 tx_ring->size += sizeof(u32);
7f12ad74
GR		 434 tx_ring->size = ALIGN(tx_ring->size, 4096);
435 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
436 &tx_ring->dma, GFP_KERNEL);
437 if (!tx_ring->desc) {
438 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
439 tx_ring->size);
440 goto err;
441 }
442
443 tx_ring->next_to_use = 0;
444 tx_ring->next_to_clean = 0;
445 return 0;
446
447err:
448 kfree(tx_ring->tx_bi);
449 tx_ring->tx_bi = NULL;
450 return -ENOMEM;
451}
452
453/**
454 * i40evf_clean_rx_ring - Free Rx buffers
455 * @rx_ring: ring to be cleaned
456 **/
457void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
458{
459 struct device *dev = rx_ring->dev;
460 struct i40e_rx_buffer *rx_bi;
461 unsigned long bi_size;
462 u16 i;
463
464 /* ring already cleared, nothing to do */
465 if (!rx_ring->rx_bi)
466 return;
467
a132af24
MW		 468 if (ring_is_ps_enabled(rx_ring)) {
469 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
470
471 rx_bi = &rx_ring->rx_bi[0];
472 if (rx_bi->hdr_buf) {
473 dma_free_coherent(dev,
474 bufsz,
475 rx_bi->hdr_buf,
476 rx_bi->dma);
477 for (i = 0; i < rx_ring->count; i++) {
478 rx_bi = &rx_ring->rx_bi[i];
479 rx_bi->dma = 0;
37a2973a 480 rx_bi->hdr_buf = NULL;
a132af24
MW		 481 }
482 }
483 }
7f12ad74
GR		 484 /* Free all the Rx ring sk_buffs */
485 for (i = 0; i < rx_ring->count; i++) {
486 rx_bi = &rx_ring->rx_bi[i];
487 if (rx_bi->dma) {
488 dma_unmap_single(dev,
489 rx_bi->dma,
490 rx_ring->rx_buf_len,
491 DMA_FROM_DEVICE);
492 rx_bi->dma = 0;
493 }
494 if (rx_bi->skb) {
495 dev_kfree_skb(rx_bi->skb);
496 rx_bi->skb = NULL;
497 }
498 if (rx_bi->page) {
499 if (rx_bi->page_dma) {
500 dma_unmap_page(dev,
501 rx_bi->page_dma,
502 PAGE_SIZE / 2,
503 DMA_FROM_DEVICE);
504 rx_bi->page_dma = 0;
505 }
506 __free_page(rx_bi->page);
507 rx_bi->page = NULL;
508 rx_bi->page_offset = 0;
509 }
510 }
511
512 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
513 memset(rx_ring->rx_bi, 0, bi_size);
514
515 /* Zero out the descriptor ring */
516 memset(rx_ring->desc, 0, rx_ring->size);
517
518 rx_ring->next_to_clean = 0;
519 rx_ring->next_to_use = 0;
520}
521
522/**
523 * i40evf_free_rx_resources - Free Rx resources
524 * @rx_ring: ring to clean the resources from
525 *
526 * Free all receive software resources
527 **/
528void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
529{
530 i40evf_clean_rx_ring(rx_ring);
531 kfree(rx_ring->rx_bi);
532 rx_ring->rx_bi = NULL;
533
534 if (rx_ring->desc) {
535 dma_free_coherent(rx_ring->dev, rx_ring->size,
536 rx_ring->desc, rx_ring->dma);
537 rx_ring->desc = NULL;
538 }
539}
540
a132af24
MW		 541/**
542 * i40evf_alloc_rx_headers - allocate rx header buffers
543 * @rx_ring: ring to alloc buffers
544 *
545 * Allocate rx header buffers for the entire ring. As these are static,
546 * this is only called when setting up a new ring.
547 **/
548void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
549{
550 struct device *dev = rx_ring->dev;
551 struct i40e_rx_buffer *rx_bi;
552 dma_addr_t dma;
553 void *buffer;
554 int buf_size;
555 int i;
556
557 if (rx_ring->rx_bi[0].hdr_buf)
558 return;
559 /* Make sure the buffers don't cross cache line boundaries. */
560 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
561 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
562 &dma, GFP_KERNEL);
563 if (!buffer)
564 return;
565 for (i = 0; i < rx_ring->count; i++) {
566 rx_bi = &rx_ring->rx_bi[i];
567 rx_bi->dma = dma + (i * buf_size);
568 rx_bi->hdr_buf = buffer + (i * buf_size);
569 }
570}
571
7f12ad74
GR		 572/**
573 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
574 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
575 *
576 * Returns 0 on success, negative on failure
577 **/
578int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
579{
580 struct device *dev = rx_ring->dev;
581 int bi_size;
582
67c818a1
MW		 583 /* warn if we are about to overwrite the pointer */
584 WARN_ON(rx_ring->rx_bi);
7f12ad74
GR		 585 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
586 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
587 if (!rx_ring->rx_bi)
588 goto err;
589
f217d6ca 590 u64_stats_init(&rx_ring->syncp);
638702bd 591
7f12ad74
GR		 592 /* Round up to nearest 4K */
593 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
594 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
595 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
596 rx_ring->size = ALIGN(rx_ring->size, 4096);
597 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
598 &rx_ring->dma, GFP_KERNEL);
599
600 if (!rx_ring->desc) {
601 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
602 rx_ring->size);
603 goto err;
604 }
605
606 rx_ring->next_to_clean = 0;
607 rx_ring->next_to_use = 0;
608
609 return 0;
610err:
611 kfree(rx_ring->rx_bi);
612 rx_ring->rx_bi = NULL;
613 return -ENOMEM;
614}
615
616/**
617 * i40e_release_rx_desc - Store the new tail and head values
618 * @rx_ring: ring to bump
619 * @val: new head index
620 **/
621static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
622{
623 rx_ring->next_to_use = val;
624 /* Force memory writes to complete before letting h/w
625 * know there are new descriptors to fetch. (Only
626 * applicable for weak-ordered memory model archs,
627 * such as IA-64).
628 */
629 wmb();
630 writel(val, rx_ring->tail);
631}
632
633/**
a132af24
MW		 634 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
635 * @rx_ring: ring to place buffers on
636 * @cleaned_count: number of buffers to replace
637 **/
638void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
639{
640 u16 i = rx_ring->next_to_use;
641 union i40e_rx_desc *rx_desc;
642 struct i40e_rx_buffer *bi;
643
644 /* do nothing if no valid netdev defined */
645 if (!rx_ring->netdev || !cleaned_count)
646 return;
647
648 while (cleaned_count--) {
649 rx_desc = I40E_RX_DESC(rx_ring, i);
650 bi = &rx_ring->rx_bi[i];
651
652 if (bi->skb) /* desc is in use */
653 goto no_buffers;
654 if (!bi->page) {
655 bi->page = alloc_page(GFP_ATOMIC);
656 if (!bi->page) {
657 rx_ring->rx_stats.alloc_page_failed++;
658 goto no_buffers;
659 }
660 }
661
662 if (!bi->page_dma) {
663 /* use a half page if we're re-using */
664 bi->page_offset ^= PAGE_SIZE / 2;
665 bi->page_dma = dma_map_page(rx_ring->dev,
666 bi->page,
667 bi->page_offset,
668 PAGE_SIZE / 2,
669 DMA_FROM_DEVICE);
670 if (dma_mapping_error(rx_ring->dev,
671 bi->page_dma)) {
672 rx_ring->rx_stats.alloc_page_failed++;
673 bi->page_dma = 0;
674 goto no_buffers;
675 }
676 }
677
678 dma_sync_single_range_for_device(rx_ring->dev,
679 bi->dma,
680 0,
681 rx_ring->rx_hdr_len,
682 DMA_FROM_DEVICE);
683 /* Refresh the desc even if buffer_addrs didn't change
684 * because each write-back erases this info.
685 */
686 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
687 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
688 i++;
689 if (i == rx_ring->count)
690 i = 0;
691 }
692
693no_buffers:
694 if (rx_ring->next_to_use != i)
695 i40e_release_rx_desc(rx_ring, i);
696}
697
698/**
699 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
7f12ad74
GR		 700 * @rx_ring: ring to place buffers on
701 * @cleaned_count: number of buffers to replace
702 **/
a132af24 703void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
7f12ad74
GR		 704{
705 u16 i = rx_ring->next_to_use;
706 union i40e_rx_desc *rx_desc;
707 struct i40e_rx_buffer *bi;
708 struct sk_buff *skb;
709
710 /* do nothing if no valid netdev defined */
711 if (!rx_ring->netdev || !cleaned_count)
712 return;
713
714 while (cleaned_count--) {
715 rx_desc = I40E_RX_DESC(rx_ring, i);
716 bi = &rx_ring->rx_bi[i];
717 skb = bi->skb;
718
719 if (!skb) {
720 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
721 rx_ring->rx_buf_len);
722 if (!skb) {
723 rx_ring->rx_stats.alloc_buff_failed++;
724 goto no_buffers;
725 }
726 /* initialize queue mapping */
727 skb_record_rx_queue(skb, rx_ring->queue_index);
728 bi->skb = skb;
729 }
730
731 if (!bi->dma) {
732 bi->dma = dma_map_single(rx_ring->dev,
733 skb->data,
734 rx_ring->rx_buf_len,
735 DMA_FROM_DEVICE);
736 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
737 rx_ring->rx_stats.alloc_buff_failed++;
738 bi->dma = 0;
739 goto no_buffers;
740 }
741 }
742
a132af24
MW		 743 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
744 rx_desc->read.hdr_addr = 0;
7f12ad74
GR		 745 i++;
746 if (i == rx_ring->count)
747 i = 0;
748 }
749
750no_buffers:
751 if (rx_ring->next_to_use != i)
752 i40e_release_rx_desc(rx_ring, i);
753}
754
755/**
756 * i40e_receive_skb - Send a completed packet up the stack
757 * @rx_ring: rx ring in play
758 * @skb: packet to send up
759 * @vlan_tag: vlan tag for packet
760 **/
761static void i40e_receive_skb(struct i40e_ring *rx_ring,
762 struct sk_buff *skb, u16 vlan_tag)
763{
764 struct i40e_q_vector *q_vector = rx_ring->q_vector;
7f12ad74
GR		 765
766 if (vlan_tag & VLAN_VID_MASK)
767 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
768
8b650359 769 napi_gro_receive(&q_vector->napi, skb);
7f12ad74
GR		 770}
771
772/**
773 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
774 * @vsi: the VSI we care about
775 * @skb: skb currently being received and modified
776 * @rx_status: status value of last descriptor in packet
777 * @rx_error: error value of last descriptor in packet
778 * @rx_ptype: ptype value of last descriptor in packet
779 **/
780static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
781 struct sk_buff *skb,
782 u32 rx_status,
783 u32 rx_error,
784 u16 rx_ptype)
785{
8a3c91cc
JB		 786 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
787 bool ipv4 = false, ipv6 = false;
7f12ad74
GR		 788 bool ipv4_tunnel, ipv6_tunnel;
789 __wsum rx_udp_csum;
7f12ad74 790 struct iphdr *iph;
8a3c91cc 791 __sum16 csum;
7f12ad74 792
f8faaa40
ASJ		 793 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
794 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
795 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
796 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
7f12ad74 797
7f12ad74
GR		 798 skb->ip_summed = CHECKSUM_NONE;
799
800 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 801 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
802 return;
803
804 /* did the hardware decode the packet and checksum? */
41a1d04b 805 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
8a3c91cc
JB		 806 return;
807
808 /* both known and outer_ip must be set for the below code to work */
809 if (!(decoded.known && decoded.outer_ip))
7f12ad74
GR		 810 return;
811
8a3c91cc
JB		 812 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
813 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
814 ipv4 = true;
815 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
816 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
817 ipv6 = true;
818
819 if (ipv4 &&
41a1d04b
JB		 820 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
821 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
8a3c91cc
JB		 822 goto checksum_fail;
823
ddf1d0d7 824 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 825 if (ipv6 &&
41a1d04b 826 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
8a3c91cc 827 /* don't increment checksum err here, non-fatal err */
7f12ad74
GR		 828 return;
829
8a3c91cc 830 /* there was some L4 error, count error and punt packet to the stack */
41a1d04b 831 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
8a3c91cc
JB		 832 goto checksum_fail;
833
834 /* handle packets that were not able to be checksummed due
835 * to arrival speed, in this case the stack can compute
836 * the csum.
837 */
41a1d04b 838 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
7f12ad74 839 return;
7f12ad74 840
8a3c91cc
JB		 841 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
842 * it in the driver, hardware does not do it for us.
843 * Since L3L4P bit was set we assume a valid IHL value (>=5)
844 * so the total length of IPv4 header is IHL*4 bytes
845 * The UDP_0 bit *may* bet set if the *inner* header is UDP
846 */
818f2e7b 847 if (ipv4_tunnel) {
7f12ad74
GR		 848 skb->transport_header = skb->mac_header +
849 sizeof(struct ethhdr) +
850 (ip_hdr(skb)->ihl * 4);
851
852 /* Add 4 bytes for VLAN tagged packets */
853 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
854 skb->protocol == htons(ETH_P_8021AD))
855 ? VLAN_HLEN : 0;
856
818f2e7b
ASJ		 857 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
858 (udp_hdr(skb)->check != 0)) {
859 rx_udp_csum = udp_csum(skb);
860 iph = ip_hdr(skb);
861 csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
862 (skb->len -
863 skb_transport_offset(skb)),
864 IPPROTO_UDP, rx_udp_csum);
7f12ad74 865
818f2e7b
ASJ		 866 if (udp_hdr(skb)->check != csum)
867 goto checksum_fail;
868
869 } /* else its GRE and so no outer UDP header */
7f12ad74
GR		 870 }
871
872 skb->ip_summed = CHECKSUM_UNNECESSARY;
407fa085 873 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 874
875 return;
876
877checksum_fail:
878 vsi->back->hw_csum_rx_error++;
7f12ad74
GR		 879}
880
881/**
882 * i40e_rx_hash - returns the hash value from the Rx descriptor
883 * @ring: descriptor ring
884 * @rx_desc: specific descriptor
885 **/
886static inline u32 i40e_rx_hash(struct i40e_ring *ring,
887 union i40e_rx_desc *rx_desc)
888{
889 const __le64 rss_mask =
890 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
891 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
892
893 if ((ring->netdev->features & NETIF_F_RXHASH) &&
894 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
895 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
896 else
897 return 0;
898}
899
206812b5
JB		 900/**
901 * i40e_ptype_to_hash - get a hash type
902 * @ptype: the ptype value from the descriptor
903 *
904 * Returns a hash type to be used by skb_set_hash
905 **/
906static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
907{
908 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
909
910 if (!decoded.known)
911 return PKT_HASH_TYPE_NONE;
912
913 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
914 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
915 return PKT_HASH_TYPE_L4;
916 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
917 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
918 return PKT_HASH_TYPE_L3;
919 else
920 return PKT_HASH_TYPE_L2;
921}
922
7f12ad74 923/**
a132af24 924 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
7f12ad74
GR		 925 * @rx_ring: rx ring to clean
926 * @budget: how many cleans we're allowed
927 *
928 * Returns true if there's any budget left (e.g. the clean is finished)
929 **/
a132af24 930static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
7f12ad74
GR		 931{
932 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
933 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
934 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
27ca2753 935 const int current_node = numa_mem_id();
7f12ad74
GR		 936 struct i40e_vsi *vsi = rx_ring->vsi;
937 u16 i = rx_ring->next_to_clean;
938 union i40e_rx_desc *rx_desc;
939 u32 rx_error, rx_status;
206812b5 940 u8 rx_ptype;
7f12ad74 941 u64 qword;
7f12ad74 942
a132af24 943 do {
7f12ad74
GR		 944 struct i40e_rx_buffer *rx_bi;
945 struct sk_buff *skb;
946 u16 vlan_tag;
a132af24
MW		 947 /* return some buffers to hardware, one at a time is too slow */
948 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
949 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
950 cleaned_count = 0;
951 }
952
953 i = rx_ring->next_to_clean;
954 rx_desc = I40E_RX_DESC(rx_ring, i);
955 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
956 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
957 I40E_RXD_QW1_STATUS_SHIFT;
958
41a1d04b 959 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 960 break;
961
962 /* This memory barrier is needed to keep us from reading
963 * any other fields out of the rx_desc until we know the
964 * DD bit is set.
965 */
67317166 966 dma_rmb();
7f12ad74
GR		 967 rx_bi = &rx_ring->rx_bi[i];
968 skb = rx_bi->skb;
a132af24
MW		 969 if (likely(!skb)) {
970 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
971 rx_ring->rx_hdr_len);
8b6ed9c2 972 if (!skb) {
a132af24 973 rx_ring->rx_stats.alloc_buff_failed++;
8b6ed9c2
JB		 974 break;
975 }
976
a132af24
MW		 977 /* initialize queue mapping */
978 skb_record_rx_queue(skb, rx_ring->queue_index);
979 /* we are reusing so sync this buffer for CPU use */
980 dma_sync_single_range_for_cpu(rx_ring->dev,
981 rx_bi->dma,
982 0,
983 rx_ring->rx_hdr_len,
984 DMA_FROM_DEVICE);
985 }
7f12ad74
GR		 986 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
987 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
988 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
989 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
990 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
991 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
992
993 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
994 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b
JB		 995 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
996 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
7f12ad74
GR		 997
998 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
999 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 1000 prefetch(rx_bi->page);
7f12ad74 1001 rx_bi->skb = NULL;
a132af24
MW		 1002 cleaned_count++;
1003 if (rx_hbo || rx_sph) {
1004 int len;
6995b36c 1005
7f12ad74
GR		 1006 if (rx_hbo)
1007 len = I40E_RX_HDR_SIZE;
7f12ad74 1008 else
a132af24
MW		 1009 len = rx_header_len;
1010 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1011 } else if (skb->len == 0) {
1012 int len;
1013
1014 len = (rx_packet_len > skb_headlen(skb) ?
1015 skb_headlen(skb) : rx_packet_len);
1016 memcpy(__skb_put(skb, len),
1017 rx_bi->page + rx_bi->page_offset,
1018 len);
1019 rx_bi->page_offset += len;
1020 rx_packet_len -= len;
7f12ad74
GR		 1021 }
1022
1023 /* Get the rest of the data if this was a header split */
a132af24 1024 if (rx_packet_len) {
7f12ad74
GR		 1025 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1026 rx_bi->page,
1027 rx_bi->page_offset,
1028 rx_packet_len);
1029
1030 skb->len += rx_packet_len;
1031 skb->data_len += rx_packet_len;
1032 skb->truesize += rx_packet_len;
1033
1034 if ((page_count(rx_bi->page) == 1) &&
1035 (page_to_nid(rx_bi->page) == current_node))
1036 get_page(rx_bi->page);
1037 else
1038 rx_bi->page = NULL;
1039
1040 dma_unmap_page(rx_ring->dev,
1041 rx_bi->page_dma,
1042 PAGE_SIZE / 2,
1043 DMA_FROM_DEVICE);
1044 rx_bi->page_dma = 0;
1045 }
a132af24 1046 I40E_RX_INCREMENT(rx_ring, i);
7f12ad74
GR		 1047
1048 if (unlikely(
41a1d04b 1049 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
7f12ad74
GR		 1050 struct i40e_rx_buffer *next_buffer;
1051
1052 next_buffer = &rx_ring->rx_bi[i];
a132af24 1053 next_buffer->skb = skb;
7f12ad74 1054 rx_ring->rx_stats.non_eop_descs++;
a132af24 1055 continue;
7f12ad74
GR		 1056 }
1057
1058 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1059 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
7f12ad74 1060 dev_kfree_skb_any(skb);
a132af24 1061 continue;
7f12ad74
GR		 1062 }
1063
206812b5
JB		 1064 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1065 i40e_ptype_to_hash(rx_ptype));
7f12ad74
GR		 1066 /* probably a little skewed due to removing CRC */
1067 total_rx_bytes += skb->len;
1068 total_rx_packets++;
1069
1070 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1071
1072 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1073
41a1d04b 1074 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
7f12ad74
GR		 1075 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1076 : 0;
a132af24
MW		 1077#ifdef I40E_FCOE
1078 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1079 dev_kfree_skb_any(skb);
1080 continue;
1081 }
1082#endif
7f12ad74
GR		 1083 i40e_receive_skb(rx_ring, skb, vlan_tag);
1084
7f12ad74 1085 rx_desc->wb.qword1.status_error_len = 0;
7f12ad74 1086
a132af24
MW		 1087 } while (likely(total_rx_packets < budget));
1088
1089 u64_stats_update_begin(&rx_ring->syncp);
1090 rx_ring->stats.packets += total_rx_packets;
1091 rx_ring->stats.bytes += total_rx_bytes;
1092 u64_stats_update_end(&rx_ring->syncp);
1093 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1094 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1095
1096 return total_rx_packets;
1097}
1098
1099/**
1100 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1101 * @rx_ring: rx ring to clean
1102 * @budget: how many cleans we're allowed
1103 *
1104 * Returns number of packets cleaned
1105 **/
1106static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1107{
1108 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1109 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1110 struct i40e_vsi *vsi = rx_ring->vsi;
1111 union i40e_rx_desc *rx_desc;
1112 u32 rx_error, rx_status;
1113 u16 rx_packet_len;
1114 u8 rx_ptype;
1115 u64 qword;
1116 u16 i;
1117
1118 do {
1119 struct i40e_rx_buffer *rx_bi;
1120 struct sk_buff *skb;
1121 u16 vlan_tag;
7f12ad74
GR		 1122 /* return some buffers to hardware, one at a time is too slow */
1123 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1124 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
7f12ad74
GR		 1125 cleaned_count = 0;
1126 }
1127
a132af24
MW		 1128 i = rx_ring->next_to_clean;
1129 rx_desc = I40E_RX_DESC(rx_ring, i);
7f12ad74
GR		 1130 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1131 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1132 I40E_RXD_QW1_STATUS_SHIFT;
1133
41a1d04b 1134 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1135 break;
1136
1137 /* This memory barrier is needed to keep us from reading
1138 * any other fields out of the rx_desc until we know the
1139 * DD bit is set.
1140 */
67317166 1141 dma_rmb();
a132af24
MW		 1142
1143 rx_bi = &rx_ring->rx_bi[i];
1144 skb = rx_bi->skb;
1145 prefetch(skb->data);
1146
1147 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1148 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1149
1150 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1151 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b 1152 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
a132af24
MW		 1153
1154 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1155 I40E_RXD_QW1_PTYPE_SHIFT;
1156 rx_bi->skb = NULL;
1157 cleaned_count++;
1158
1159 /* Get the header and possibly the whole packet
1160 * If this is an skb from previous receive dma will be 0
1161 */
1162 skb_put(skb, rx_packet_len);
1163 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1164 DMA_FROM_DEVICE);
1165 rx_bi->dma = 0;
1166
1167 I40E_RX_INCREMENT(rx_ring, i);
1168
1169 if (unlikely(
41a1d04b 1170 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
a132af24
MW		 1171 rx_ring->rx_stats.non_eop_descs++;
1172 continue;
1173 }
1174
1175 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1176 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
a132af24 1177 dev_kfree_skb_any(skb);
a132af24
MW		 1178 continue;
1179 }
1180
1181 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1182 i40e_ptype_to_hash(rx_ptype));
1183 /* probably a little skewed due to removing CRC */
1184 total_rx_bytes += skb->len;
1185 total_rx_packets++;
1186
1187 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1188
1189 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1190
41a1d04b 1191 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
a132af24
MW		 1192 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1193 : 0;
1194 i40e_receive_skb(rx_ring, skb, vlan_tag);
1195
a132af24
MW		 1196 rx_desc->wb.qword1.status_error_len = 0;
1197 } while (likely(total_rx_packets < budget));
7f12ad74 1198
7f12ad74
GR		 1199 u64_stats_update_begin(&rx_ring->syncp);
1200 rx_ring->stats.packets += total_rx_packets;
1201 rx_ring->stats.bytes += total_rx_bytes;
1202 u64_stats_update_end(&rx_ring->syncp);
1203 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1204 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1205
a132af24 1206 return total_rx_packets;
7f12ad74
GR		 1207}
1208
8f5e39ce
JB		 1209static u32 i40e_buildreg_itr(const int type, const u16 itr)
1210{
1211 u32 val;
1212
1213 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1214 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1215 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1216 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1217
1218 return val;
1219}
1220
1221/* a small macro to shorten up some long lines */
1222#define INTREG I40E_VFINT_DYN_CTLN1
1223
de32e3ef
CW		 1224/**
1225 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1226 * @vsi: the VSI we care about
1227 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1228 *
1229 **/
1230static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1231 struct i40e_q_vector *q_vector)
1232{
1233 struct i40e_hw *hw = &vsi->back->hw;
8f5e39ce
JB		 1234 bool rx = false, tx = false;
1235 u32 rxval, txval;
de32e3ef 1236 int vector;
de32e3ef
CW		 1237
1238 vector = (q_vector->v_idx + vsi->base_vector);
ee2319cf
JB		 1239
1240 /* avoid dynamic calculation if in countdown mode OR if
1241 * all dynamic is disabled
1242 */
8f5e39ce
JB		 1243 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1244
ee2319cf
JB		 1245 if (q_vector->itr_countdown > 0 ||
1246 (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1247 !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1248 goto enable_int;
1249 }
1250
de32e3ef 1251 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
8f5e39ce
JB		 1252 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1253 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
de32e3ef
CW		 1254 }
1255 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
8f5e39ce
JB		 1256 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1257 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1258 }
1259 if (rx || tx) {
1260 /* get the higher of the two ITR adjustments and
1261 * use the same value for both ITR registers
1262 * when in adaptive mode (Rx and/or Tx)
1263 */
1264 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1265
1266 q_vector->tx.itr = q_vector->rx.itr = itr;
1267 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1268 tx = true;
1269 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1270 rx = true;
de32e3ef 1271 }
8f5e39ce
JB		 1272
1273 /* only need to enable the interrupt once, but need
1274 * to possibly update both ITR values
1275 */
1276 if (rx) {
1277 /* set the INTENA_MSK_MASK so that this first write
1278 * won't actually enable the interrupt, instead just
1279 * updating the ITR (it's bit 31 PF and VF)
1280 */
1281 rxval |= BIT(31);
1282 /* don't check _DOWN because interrupt isn't being enabled */
1283 wr32(hw, INTREG(vector - 1), rxval);
1284 }
1285
ee2319cf 1286enable_int:
8f5e39ce
JB		 1287 if (!test_bit(__I40E_DOWN, &vsi->state))
1288 wr32(hw, INTREG(vector - 1), txval);
ee2319cf
JB		 1289
1290 if (q_vector->itr_countdown)
1291 q_vector->itr_countdown--;
1292 else
1293 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1294
de32e3ef
CW		 1295}
1296
7f12ad74
GR		 1297/**
1298 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1299 * @napi: napi struct with our devices info in it
1300 * @budget: amount of work driver is allowed to do this pass, in packets
1301 *
1302 * This function will clean all queues associated with a q_vector.
1303 *
1304 * Returns the amount of work done
1305 **/
1306int i40evf_napi_poll(struct napi_struct *napi, int budget)
1307{
1308 struct i40e_q_vector *q_vector =
1309 container_of(napi, struct i40e_q_vector, napi);
1310 struct i40e_vsi *vsi = q_vector->vsi;
1311 struct i40e_ring *ring;
1312 bool clean_complete = true;
c29af37f 1313 bool arm_wb = false;
7f12ad74 1314 int budget_per_ring;
32b3e08f 1315 int work_done = 0;
7f12ad74
GR		 1316
1317 if (test_bit(__I40E_DOWN, &vsi->state)) {
1318 napi_complete(napi);
1319 return 0;
1320 }
1321
1322 /* Since the actual Tx work is minimal, we can give the Tx a larger
1323 * budget and be more aggressive about cleaning up the Tx descriptors.
1324 */
c29af37f 1325 i40e_for_each_ring(ring, q_vector->tx) {
7f12ad74 1326 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
c29af37f 1327 arm_wb |= ring->arm_wb;
0deda868 1328 ring->arm_wb = false;
c29af37f 1329 }
7f12ad74 1330
c67caceb
AD		 1331 /* Handle case where we are called by netpoll with a budget of 0 */
1332 if (budget <= 0)
1333 goto tx_only;
1334
7f12ad74
GR		 1335 /* We attempt to distribute budget to each Rx queue fairly, but don't
1336 * allow the budget to go below 1 because that would exit polling early.
1337 */
1338 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1339
a132af24 1340 i40e_for_each_ring(ring, q_vector->rx) {
32b3e08f
JB		 1341 int cleaned;
1342
a132af24
MW		 1343 if (ring_is_ps_enabled(ring))
1344 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1345 else
1346 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
32b3e08f
JB		 1347
1348 work_done += cleaned;
a132af24
MW		 1349 /* if we didn't clean as many as budgeted, we must be done */
1350 clean_complete &= (budget_per_ring != cleaned);
1351 }
7f12ad74
GR		 1352
1353 /* If work not completed, return budget and polling will return */
c29af37f 1354 if (!clean_complete) {
c67caceb 1355tx_only:
164c9f54
ASJ		 1356 if (arm_wb) {
1357 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
b03a8c1f 1358 i40evf_force_wb(vsi, q_vector);
164c9f54 1359 }
7f12ad74 1360 return budget;
c29af37f 1361 }
7f12ad74 1362
8e0764b4
ASJ		 1363 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1364 q_vector->arm_wb_state = false;
1365
7f12ad74 1366 /* Work is done so exit the polling mode and re-enable the interrupt */
32b3e08f 1367 napi_complete_done(napi, work_done);
de32e3ef 1368 i40e_update_enable_itr(vsi, q_vector);
7f12ad74
GR		 1369 return 0;
1370}
1371
1372/**
3e587cf3 1373 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
7f12ad74
GR		 1374 * @skb: send buffer
1375 * @tx_ring: ring to send buffer on
1376 * @flags: the tx flags to be set
1377 *
1378 * Checks the skb and set up correspondingly several generic transmit flags
1379 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1380 *
1381 * Returns error code indicate the frame should be dropped upon error and the
1382 * otherwise returns 0 to indicate the flags has been set properly.
1383 **/
3e587cf3
JB		 1384static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1385 struct i40e_ring *tx_ring,
1386 u32 *flags)
7f12ad74
GR		 1387{
1388 __be16 protocol = skb->protocol;
1389 u32 tx_flags = 0;
1390
31eaaccf
GR		 1391 if (protocol == htons(ETH_P_8021Q) &&
1392 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1393 /* When HW VLAN acceleration is turned off by the user the
1394 * stack sets the protocol to 8021q so that the driver
1395 * can take any steps required to support the SW only
1396 * VLAN handling. In our case the driver doesn't need
1397 * to take any further steps so just set the protocol
1398 * to the encapsulated ethertype.
1399 */
1400 skb->protocol = vlan_get_protocol(skb);
1401 goto out;
1402 }
1403
7f12ad74 1404 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 1405 if (skb_vlan_tag_present(skb)) {
1406 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
7f12ad74
GR		 1407 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1408 /* else if it is a SW VLAN, check the next protocol and store the tag */
1409 } else if (protocol == htons(ETH_P_8021Q)) {
1410 struct vlan_hdr *vhdr, _vhdr;
6995b36c 1411
7f12ad74
GR		 1412 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1413 if (!vhdr)
1414 return -EINVAL;
1415
1416 protocol = vhdr->h_vlan_encapsulated_proto;
1417 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1418 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1419 }
1420
31eaaccf 1421out:
7f12ad74
GR		 1422 *flags = tx_flags;
1423 return 0;
1424}
1425
1426/**
1427 * i40e_tso - set up the tso context descriptor
1428 * @tx_ring: ptr to the ring to send
1429 * @skb: ptr to the skb we're sending
7f12ad74 1430 * @hdr_len: ptr to the size of the packet header
9c883bd3 1431 * @cd_type_cmd_tso_mss: Quad Word 1
7f12ad74
GR		 1432 *
1433 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1434 **/
1435static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
9c883bd3 1436 u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
7f12ad74
GR		 1437{
1438 u32 cd_cmd, cd_tso_len, cd_mss;
fe6d4aa4 1439 struct ipv6hdr *ipv6h;
7f12ad74
GR		 1440 struct tcphdr *tcph;
1441 struct iphdr *iph;
1442 u32 l4len;
1443 int err;
7f12ad74
GR		 1444
1445 if (!skb_is_gso(skb))
1446 return 0;
1447
fe6d4aa4
FR		 1448 err = skb_cow_head(skb, 0);
1449 if (err < 0)
1450 return err;
7f12ad74 1451
85e76d03
AS		 1452 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1453 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1454
1455 if (iph->version == 4) {
7f12ad74
GR		 1456 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1457 iph->tot_len = 0;
1458 iph->check = 0;
1459 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1460 0, IPPROTO_TCP, 0);
85e76d03 1461 } else if (ipv6h->version == 6) {
7f12ad74
GR		 1462 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1463 ipv6h->payload_len = 0;
1464 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1465 0, IPPROTO_TCP, 0);
1466 }
1467
1468 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1469 *hdr_len = (skb->encapsulation
1470 ? (skb_inner_transport_header(skb) - skb->data)
1471 : skb_transport_offset(skb)) + l4len;
1472
1473 /* find the field values */
1474 cd_cmd = I40E_TX_CTX_DESC_TSO;
1475 cd_tso_len = skb->len - *hdr_len;
1476 cd_mss = skb_shinfo(skb)->gso_size;
1477 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1478 ((u64)cd_tso_len <<
1479 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1480 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1481 return 1;
1482}
1483
1484/**
1485 * i40e_tx_enable_csum - Enable Tx checksum offloads
1486 * @skb: send buffer
89232c3b 1487 * @tx_flags: pointer to Tx flags currently set
7f12ad74
GR		 1488 * @td_cmd: Tx descriptor command bits to set
1489 * @td_offset: Tx descriptor header offsets to set
1490 * @cd_tunneling: ptr to context desc bits
1491 **/
89232c3b 1492static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
7f12ad74
GR		 1493 u32 *td_cmd, u32 *td_offset,
1494 struct i40e_ring *tx_ring,
1495 u32 *cd_tunneling)
1496{
1497 struct ipv6hdr *this_ipv6_hdr;
1498 unsigned int this_tcp_hdrlen;
1499 struct iphdr *this_ip_hdr;
1500 u32 network_hdr_len;
1501 u8 l4_hdr = 0;
527274c7
ASJ		 1502 struct udphdr *oudph;
1503 struct iphdr *oiph;
45991204 1504 u32 l4_tunnel = 0;
7f12ad74
GR		 1505
1506 if (skb->encapsulation) {
45991204
ASJ		 1507 switch (ip_hdr(skb)->protocol) {
1508 case IPPROTO_UDP:
527274c7
ASJ		 1509 oudph = udp_hdr(skb);
1510 oiph = ip_hdr(skb);
45991204 1511 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
89232c3b 1512 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
45991204
ASJ		 1513 break;
1514 default:
1515 return;
1516 }
7f12ad74
GR		 1517 network_hdr_len = skb_inner_network_header_len(skb);
1518 this_ip_hdr = inner_ip_hdr(skb);
1519 this_ipv6_hdr = inner_ipv6_hdr(skb);
1520 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1521
89232c3b
ASJ		 1522 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1523 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1524 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1525 ip_hdr(skb)->check = 0;
1526 } else {
1527 *cd_tunneling |=
1528 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1529 }
89232c3b 1530 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
85e76d03 1531 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
89232c3b 1532 if (*tx_flags & I40E_TX_FLAGS_TSO)
7f12ad74 1533 ip_hdr(skb)->check = 0;
7f12ad74
GR		 1534 }
1535
1536 /* Now set the ctx descriptor fields */
1537 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
45991204
ASJ		 1538 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1539 l4_tunnel |
7f12ad74
GR		 1540 ((skb_inner_network_offset(skb) -
1541 skb_transport_offset(skb)) >> 1) <<
1542 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
85e76d03 1543 if (this_ip_hdr->version == 6) {
89232c3b
ASJ		 1544 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1545 *tx_flags |= I40E_TX_FLAGS_IPV6;
85e76d03
AS		 1546 }
1547
7f12ad74 1548
527274c7
ASJ		 1549 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1550 (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING) &&
1551 (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1552 oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1553 oiph->daddr,
1554 (skb->len - skb_transport_offset(skb)),
1555 IPPROTO_UDP, 0);
1556 *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1557 }
7f12ad74
GR		 1558 } else {
1559 network_hdr_len = skb_network_header_len(skb);
1560 this_ip_hdr = ip_hdr(skb);
1561 this_ipv6_hdr = ipv6_hdr(skb);
1562 this_tcp_hdrlen = tcp_hdrlen(skb);
1563 }
1564
1565 /* Enable IP checksum offloads */
89232c3b 1566 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
7f12ad74
GR		 1567 l4_hdr = this_ip_hdr->protocol;
1568 /* the stack computes the IP header already, the only time we
1569 * need the hardware to recompute it is in the case of TSO.
1570 */
89232c3b 1571 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1572 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1573 this_ip_hdr->check = 0;
1574 } else {
1575 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1576 }
1577 /* Now set the td_offset for IP header length */
1578 *td_offset = (network_hdr_len >> 2) <<
1579 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
89232c3b 1580 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
7f12ad74
GR		 1581 l4_hdr = this_ipv6_hdr->nexthdr;
1582 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1583 /* Now set the td_offset for IP header length */
1584 *td_offset = (network_hdr_len >> 2) <<
1585 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1586 }
1587 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1588 *td_offset |= (skb_network_offset(skb) >> 1) <<
1589 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1590
1591 /* Enable L4 checksum offloads */
1592 switch (l4_hdr) {
1593 case IPPROTO_TCP:
1594 /* enable checksum offloads */
1595 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1596 *td_offset |= (this_tcp_hdrlen >> 2) <<
1597 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1598 break;
1599 case IPPROTO_SCTP:
1600 /* enable SCTP checksum offload */
1601 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1602 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1603 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1604 break;
1605 case IPPROTO_UDP:
1606 /* enable UDP checksum offload */
1607 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1608 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1609 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1610 break;
1611 default:
1612 break;
1613 }
1614}
1615
1616/**
1617 * i40e_create_tx_ctx Build the Tx context descriptor
1618 * @tx_ring: ring to create the descriptor on
1619 * @cd_type_cmd_tso_mss: Quad Word 1
1620 * @cd_tunneling: Quad Word 0 - bits 0-31
1621 * @cd_l2tag2: Quad Word 0 - bits 32-63
1622 **/
1623static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1624 const u64 cd_type_cmd_tso_mss,
1625 const u32 cd_tunneling, const u32 cd_l2tag2)
1626{
1627 struct i40e_tx_context_desc *context_desc;
1628 int i = tx_ring->next_to_use;
1629
ff40dd5d
JB		 1630 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1631 !cd_tunneling && !cd_l2tag2)
7f12ad74
GR		 1632 return;
1633
1634 /* grab the next descriptor */
1635 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1636
1637 i++;
1638 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1639
1640 /* cpu_to_le32 and assign to struct fields */
1641 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1642 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 1643 context_desc->rsvd = cpu_to_le16(0);
7f12ad74
GR		 1644 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1645}
1646
71da6197
AS		 1647 /**
1648 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1649 * @skb: send buffer
1650 * @tx_flags: collected send information
71da6197
AS		 1651 *
1652 * Note: Our HW can't scatter-gather more than 8 fragments to build
1653 * a packet on the wire and so we need to figure out the cases where we
1654 * need to linearize the skb.
1655 **/
30520831 1656static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
71da6197
AS		 1657{
1658 struct skb_frag_struct *frag;
1659 bool linearize = false;
1660 unsigned int size = 0;
1661 u16 num_frags;
1662 u16 gso_segs;
1663
1664 num_frags = skb_shinfo(skb)->nr_frags;
1665 gso_segs = skb_shinfo(skb)->gso_segs;
1666
1667 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
30520831 1668 u16 j = 0;
71da6197
AS		 1669
1670 if (num_frags < (I40E_MAX_BUFFER_TXD))
1671 goto linearize_chk_done;
1672 /* try the simple math, if we have too many frags per segment */
1673 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1674 I40E_MAX_BUFFER_TXD) {
1675 linearize = true;
1676 goto linearize_chk_done;
1677 }
1678 frag = &skb_shinfo(skb)->frags[0];
71da6197
AS		 1679 /* we might still have more fragments per segment */
1680 do {
1681 size += skb_frag_size(frag);
1682 frag++; j++;
30520831
ASJ		 1683 if ((size >= skb_shinfo(skb)->gso_size) &&
1684 (j < I40E_MAX_BUFFER_TXD)) {
1685 size = (size % skb_shinfo(skb)->gso_size);
1686 j = (size) ? 1 : 0;
1687 }
71da6197 1688 if (j == I40E_MAX_BUFFER_TXD) {
30520831
ASJ		 1689 linearize = true;
1690 break;
71da6197
AS		 1691 }
1692 num_frags--;
1693 } while (num_frags);
1694 } else {
1695 if (num_frags >= I40E_MAX_BUFFER_TXD)
1696 linearize = true;
1697 }
1698
1699linearize_chk_done:
1700 return linearize;
1701}
1702
8f6a2b05
JB		 1703/**
1704 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1705 * @tx_ring: the ring to be checked
1706 * @size: the size buffer we want to assure is available
1707 *
1708 * Returns -EBUSY if a stop is needed, else 0
1709 **/
1710static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1711{
1712 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1713 /* Memory barrier before checking head and tail */
1714 smp_mb();
1715
1716 /* Check again in a case another CPU has just made room available. */
1717 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1718 return -EBUSY;
1719
1720 /* A reprieve! - use start_queue because it doesn't call schedule */
1721 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1722 ++tx_ring->tx_stats.restart_queue;
1723 return 0;
1724}
1725
1726/**
1727 * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1728 * @tx_ring: the ring to be checked
1729 * @size: the size buffer we want to assure is available
1730 *
1731 * Returns 0 if stop is not needed
1732 **/
3e587cf3 1733static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
8f6a2b05
JB		 1734{
1735 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1736 return 0;
1737 return __i40evf_maybe_stop_tx(tx_ring, size);
1738}
1739
7f12ad74 1740/**
3e587cf3 1741 * i40evf_tx_map - Build the Tx descriptor
7f12ad74
GR		 1742 * @tx_ring: ring to send buffer on
1743 * @skb: send buffer
1744 * @first: first buffer info buffer to use
1745 * @tx_flags: collected send information
1746 * @hdr_len: size of the packet header
1747 * @td_cmd: the command field in the descriptor
1748 * @td_offset: offset for checksum or crc
1749 **/
3e587cf3
JB		 1750static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1751 struct i40e_tx_buffer *first, u32 tx_flags,
1752 const u8 hdr_len, u32 td_cmd, u32 td_offset)
7f12ad74
GR		 1753{
1754 unsigned int data_len = skb->data_len;
1755 unsigned int size = skb_headlen(skb);
1756 struct skb_frag_struct *frag;
1757 struct i40e_tx_buffer *tx_bi;
1758 struct i40e_tx_desc *tx_desc;
1759 u16 i = tx_ring->next_to_use;
1760 u32 td_tag = 0;
1761 dma_addr_t dma;
1762 u16 gso_segs;
6a7fded7
ASJ		 1763 u16 desc_count = 0;
1764 bool tail_bump = true;
1765 bool do_rs = false;
7f12ad74
GR		 1766
1767 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1768 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1769 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1770 I40E_TX_FLAGS_VLAN_SHIFT;
1771 }
1772
1773 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1774 gso_segs = skb_shinfo(skb)->gso_segs;
1775 else
1776 gso_segs = 1;
1777
1778 /* multiply data chunks by size of headers */
1779 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1780 first->gso_segs = gso_segs;
1781 first->skb = skb;
1782 first->tx_flags = tx_flags;
1783
1784 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1785
1786 tx_desc = I40E_TX_DESC(tx_ring, i);
1787 tx_bi = first;
1788
1789 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1790 if (dma_mapping_error(tx_ring->dev, dma))
1791 goto dma_error;
1792
1793 /* record length, and DMA address */
1794 dma_unmap_len_set(tx_bi, len, size);
1795 dma_unmap_addr_set(tx_bi, dma, dma);
1796
1797 tx_desc->buffer_addr = cpu_to_le64(dma);
1798
1799 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1800 tx_desc->cmd_type_offset_bsz =
1801 build_ctob(td_cmd, td_offset,
1802 I40E_MAX_DATA_PER_TXD, td_tag);
1803
1804 tx_desc++;
1805 i++;
6a7fded7
ASJ		 1806 desc_count++;
1807
7f12ad74
GR		 1808 if (i == tx_ring->count) {
1809 tx_desc = I40E_TX_DESC(tx_ring, 0);
1810 i = 0;
1811 }
1812
1813 dma += I40E_MAX_DATA_PER_TXD;
1814 size -= I40E_MAX_DATA_PER_TXD;
1815
1816 tx_desc->buffer_addr = cpu_to_le64(dma);
1817 }
1818
1819 if (likely(!data_len))
1820 break;
1821
1822 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1823 size, td_tag);
1824
1825 tx_desc++;
1826 i++;
6a7fded7
ASJ		 1827 desc_count++;
1828
7f12ad74
GR		 1829 if (i == tx_ring->count) {
1830 tx_desc = I40E_TX_DESC(tx_ring, 0);
1831 i = 0;
1832 }
1833
1834 size = skb_frag_size(frag);
1835 data_len -= size;
1836
1837 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1838 DMA_TO_DEVICE);
1839
1840 tx_bi = &tx_ring->tx_bi[i];
1841 }
1842
1943d8ba 1843#define WB_STRIDE 0x3
7f12ad74
GR		 1844 /* set next_to_watch value indicating a packet is present */
1845 first->next_to_watch = tx_desc;
1846
1847 i++;
1848 if (i == tx_ring->count)
1849 i = 0;
1850
1851 tx_ring->next_to_use = i;
1852
6a7fded7
ASJ		 1853 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1854 tx_ring->queue_index),
1855 first->bytecount);
8f6a2b05 1856 i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
6a7fded7
ASJ		 1857
1858 /* Algorithm to optimize tail and RS bit setting:
1859 * if xmit_more is supported
1860 * if xmit_more is true
1861 * do not update tail and do not mark RS bit.
1862 * if xmit_more is false and last xmit_more was false
1863 * if every packet spanned less than 4 desc
1864 * then set RS bit on 4th packet and update tail
1865 * on every packet
1866 * else
1867 * update tail and set RS bit on every packet.
1868 * if xmit_more is false and last_xmit_more was true
1869 * update tail and set RS bit.
1870 * else (kernel < 3.18)
1871 * if every packet spanned less than 4 desc
1872 * then set RS bit on 4th packet and update tail
1873 * on every packet
1874 * else
1875 * set RS bit on EOP for every packet and update tail
1876 *
1877 * Optimization: wmb to be issued only in case of tail update.
1878 * Also optimize the Descriptor WB path for RS bit with the same
1879 * algorithm.
1880 *
1881 * Note: If there are less than 4 packets
1882 * pending and interrupts were disabled the service task will
1883 * trigger a force WB.
1884 */
1885 if (skb->xmit_more &&
1886 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1887 tx_ring->queue_index))) {
1888 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1889 tail_bump = false;
1890 } else if (!skb->xmit_more &&
1891 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1892 tx_ring->queue_index)) &&
1893 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1894 (tx_ring->packet_stride < WB_STRIDE) &&
1895 (desc_count < WB_STRIDE)) {
1896 tx_ring->packet_stride++;
1897 } else {
1898 tx_ring->packet_stride = 0;
1899 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1900 do_rs = true;
1901 }
1902 if (do_rs)
1903 tx_ring->packet_stride = 0;
1904
1905 tx_desc->cmd_type_offset_bsz =
1906 build_ctob(td_cmd, td_offset, size, td_tag) |
1907 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1908 I40E_TX_DESC_CMD_EOP) <<
1909 I40E_TXD_QW1_CMD_SHIFT);
1910
7f12ad74 1911 /* notify HW of packet */
6a7fded7 1912 if (!tail_bump)
489ce7a4 1913 prefetchw(tx_desc + 1);
7f12ad74 1914
6a7fded7
ASJ		 1915 if (tail_bump) {
1916 /* Force memory writes to complete before letting h/w
1917 * know there are new descriptors to fetch. (Only
1918 * applicable for weak-ordered memory model archs,
1919 * such as IA-64).
1920 */
1921 wmb();
1922 writel(i, tx_ring->tail);
1923 }
1924
7f12ad74
GR		 1925 return;
1926
1927dma_error:
1928 dev_info(tx_ring->dev, "TX DMA map failed\n");
1929
1930 /* clear dma mappings for failed tx_bi map */
1931 for (;;) {
1932 tx_bi = &tx_ring->tx_bi[i];
1933 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1934 if (tx_bi == first)
1935 break;
1936 if (i == 0)
1937 i = tx_ring->count;
1938 i--;
1939 }
1940
1941 tx_ring->next_to_use = i;
1942}
1943
7f12ad74 1944/**
3e587cf3 1945 * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
7f12ad74
GR		 1946 * @skb: send buffer
1947 * @tx_ring: ring to send buffer on
1948 *
1949 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1950 * there is not enough descriptors available in this ring since we need at least
1951 * one descriptor.
1952 **/
3e587cf3
JB		 1953static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1954 struct i40e_ring *tx_ring)
7f12ad74 1955{
7f12ad74 1956 unsigned int f;
7f12ad74
GR		 1957 int count = 0;
1958
1959 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1960 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 1961 * + 4 desc gap to avoid the cache line where head is,
7f12ad74
GR		 1962 * + 1 desc for context descriptor,
1963 * otherwise try next time
1964 */
7f12ad74
GR		 1965 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1966 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 1967
7f12ad74 1968 count += TXD_USE_COUNT(skb_headlen(skb));
8f6a2b05 1969 if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
7f12ad74
GR		 1970 tx_ring->tx_stats.tx_busy++;
1971 return 0;
1972 }
1973 return count;
1974}
1975
1976/**
1977 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1978 * @skb: send buffer
1979 * @tx_ring: ring to send buffer on
1980 *
1981 * Returns NETDEV_TX_OK if sent, else an error code
1982 **/
1983static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1984 struct i40e_ring *tx_ring)
1985{
1986 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1987 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1988 struct i40e_tx_buffer *first;
1989 u32 td_offset = 0;
1990 u32 tx_flags = 0;
1991 __be16 protocol;
1992 u32 td_cmd = 0;
1993 u8 hdr_len = 0;
1994 int tso;
6995b36c 1995
b74118f0
JB		 1996 /* prefetch the data, we'll need it later */
1997 prefetch(skb->data);
1998
3e587cf3 1999 if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
7f12ad74
GR		 2000 return NETDEV_TX_BUSY;
2001
2002 /* prepare the xmit flags */
3e587cf3 2003 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
7f12ad74
GR		 2004 goto out_drop;
2005
2006 /* obtain protocol of skb */
a12c4158 2007 protocol = vlan_get_protocol(skb);
7f12ad74
GR		 2008
2009 /* record the location of the first descriptor for this packet */
2010 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2011
2012 /* setup IPv4/IPv6 offloads */
2013 if (protocol == htons(ETH_P_IP))
2014 tx_flags |= I40E_TX_FLAGS_IPV4;
2015 else if (protocol == htons(ETH_P_IPV6))
2016 tx_flags |= I40E_TX_FLAGS_IPV6;
2017
9c883bd3 2018 tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
7f12ad74
GR		 2019
2020 if (tso < 0)
2021 goto out_drop;
2022 else if (tso)
2023 tx_flags |= I40E_TX_FLAGS_TSO;
2024
2fc3d715 2025 if (i40e_chk_linearize(skb, tx_flags)) {
71da6197
AS		 2026 if (skb_linearize(skb))
2027 goto out_drop;
2fc3d715
ASJ		 2028 tx_ring->tx_stats.tx_linearize++;
2029 }
7f12ad74
GR		 2030 skb_tx_timestamp(skb);
2031
2032 /* always enable CRC insertion offload */
2033 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2034
2035 /* Always offload the checksum, since it's in the data descriptor */
2036 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2037 tx_flags |= I40E_TX_FLAGS_CSUM;
2038
89232c3b 2039 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
7f12ad74
GR		 2040 tx_ring, &cd_tunneling);
2041 }
2042
2043 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2044 cd_tunneling, cd_l2tag2);
2045
3e587cf3
JB		 2046 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2047 td_cmd, td_offset);
7f12ad74 2048
7f12ad74
GR		 2049 return NETDEV_TX_OK;
2050
2051out_drop:
2052 dev_kfree_skb_any(skb);
2053 return NETDEV_TX_OK;
2054}
2055
2056/**
2057 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2058 * @skb: send buffer
2059 * @netdev: network interface device structure
2060 *
2061 * Returns NETDEV_TX_OK if sent, else an error code
2062 **/
2063netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2064{
2065 struct i40evf_adapter *adapter = netdev_priv(netdev);
2066 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
2067
2068 /* hardware can't handle really short frames, hardware padding works
2069 * beyond this point
2070 */
2071 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2072 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2073 return NETDEV_TX_OK;
2074 skb->len = I40E_MIN_TX_LEN;
2075 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2076 }
2077
2078 return i40e_xmit_frame_ring(skb, tx_ring);
2079}
Linux 6.x block layer and io_uring tree(s)