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i40e/i40evf: don't lose interrupts
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
CommitLineData
7f12ad74
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
ecc6a239 4 * Copyright(c) 2013 - 2016 Intel Corporation.
7f12ad74
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
7f12ad74
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
7ed3f5f0 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
7ed3f5f0 29
7f12ad74 30#include "i40evf.h"
206812b5 31#include "i40e_prototype.h"
7f12ad74
GR		 32
33static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35{
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41}
42
43#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45/**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52{
53 if (tx_buffer->skb) {
a42e7a36 54 dev_kfree_skb_any(tx_buffer->skb);
7f12ad74
GR		 55 if (dma_unmap_len(tx_buffer, len))
56 dma_unmap_single(ring->dev,
57 dma_unmap_addr(tx_buffer, dma),
58 dma_unmap_len(tx_buffer, len),
59 DMA_TO_DEVICE);
60 } else if (dma_unmap_len(tx_buffer, len)) {
61 dma_unmap_page(ring->dev,
62 dma_unmap_addr(tx_buffer, dma),
63 dma_unmap_len(tx_buffer, len),
64 DMA_TO_DEVICE);
65 }
a42e7a36
KP		 66
67 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
68 kfree(tx_buffer->raw_buf);
69
7f12ad74
GR		 70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74}
75
76/**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81{
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
108}
109
110/**
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
113 *
114 * Free all transmit software resources
115 **/
116void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117{
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
121
122 if (tx_ring->desc) {
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
126 }
127}
128
a68de58d 129/**
9c6c1259
KP		 130 * i40evf_get_tx_pending - how many Tx descriptors not processed
131 * @tx_ring: the ring of descriptors
a68de58d 132 *
9c6c1259
KP		 133 * Since there is no access to the ring head register
134 * in XL710, we need to use our local copies
a68de58d 135 **/
9c6c1259 136u32 i40evf_get_tx_pending(struct i40e_ring *ring)
a68de58d 137{
9c6c1259 138 u32 head, tail;
a68de58d 139
9c6c1259
KP		 140 head = i40e_get_head(ring);
141 tail = readl(ring->tail);
142
143 if (head != tail)
144 return (head < tail) ?
145 tail - head : (tail + ring->count - head);
146
147 return 0;
a68de58d
JB		 148}
149
c29af37f
ASJ		 150#define WB_STRIDE 0x3
151
7f12ad74
GR		 152/**
153 * i40e_clean_tx_irq - Reclaim resources after transmit completes
154 * @tx_ring: tx ring to clean
155 * @budget: how many cleans we're allowed
156 *
157 * Returns true if there's any budget left (e.g. the clean is finished)
158 **/
159static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
160{
161 u16 i = tx_ring->next_to_clean;
162 struct i40e_tx_buffer *tx_buf;
1943d8ba 163 struct i40e_tx_desc *tx_head;
7f12ad74
GR		 164 struct i40e_tx_desc *tx_desc;
165 unsigned int total_packets = 0;
166 unsigned int total_bytes = 0;
167
168 tx_buf = &tx_ring->tx_bi[i];
169 tx_desc = I40E_TX_DESC(tx_ring, i);
170 i -= tx_ring->count;
171
1943d8ba
JB		 172 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
173
7f12ad74
GR		 174 do {
175 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
176
177 /* if next_to_watch is not set then there is no work pending */
178 if (!eop_desc)
179 break;
180
181 /* prevent any other reads prior to eop_desc */
182 read_barrier_depends();
183
1943d8ba
JB		 184 /* we have caught up to head, no work left to do */
185 if (tx_head == tx_desc)
7f12ad74
GR		 186 break;
187
188 /* clear next_to_watch to prevent false hangs */
189 tx_buf->next_to_watch = NULL;
190
191 /* update the statistics for this packet */
192 total_bytes += tx_buf->bytecount;
193 total_packets += tx_buf->gso_segs;
194
195 /* free the skb */
196 dev_kfree_skb_any(tx_buf->skb);
197
198 /* unmap skb header data */
199 dma_unmap_single(tx_ring->dev,
200 dma_unmap_addr(tx_buf, dma),
201 dma_unmap_len(tx_buf, len),
202 DMA_TO_DEVICE);
203
204 /* clear tx_buffer data */
205 tx_buf->skb = NULL;
206 dma_unmap_len_set(tx_buf, len, 0);
207
208 /* unmap remaining buffers */
209 while (tx_desc != eop_desc) {
210
211 tx_buf++;
212 tx_desc++;
213 i++;
214 if (unlikely(!i)) {
215 i -= tx_ring->count;
216 tx_buf = tx_ring->tx_bi;
217 tx_desc = I40E_TX_DESC(tx_ring, 0);
218 }
219
220 /* unmap any remaining paged data */
221 if (dma_unmap_len(tx_buf, len)) {
222 dma_unmap_page(tx_ring->dev,
223 dma_unmap_addr(tx_buf, dma),
224 dma_unmap_len(tx_buf, len),
225 DMA_TO_DEVICE);
226 dma_unmap_len_set(tx_buf, len, 0);
227 }
228 }
229
230 /* move us one more past the eop_desc for start of next pkt */
231 tx_buf++;
232 tx_desc++;
233 i++;
234 if (unlikely(!i)) {
235 i -= tx_ring->count;
236 tx_buf = tx_ring->tx_bi;
237 tx_desc = I40E_TX_DESC(tx_ring, 0);
238 }
239
016890b9
JB		 240 prefetch(tx_desc);
241
7f12ad74
GR		 242 /* update budget accounting */
243 budget--;
244 } while (likely(budget));
245
246 i += tx_ring->count;
247 tx_ring->next_to_clean = i;
248 u64_stats_update_begin(&tx_ring->syncp);
249 tx_ring->stats.bytes += total_bytes;
250 tx_ring->stats.packets += total_packets;
251 u64_stats_update_end(&tx_ring->syncp);
252 tx_ring->q_vector->tx.total_bytes += total_bytes;
253 tx_ring->q_vector->tx.total_packets += total_packets;
254
f6d83d13
ASJ		 255 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
256 unsigned int j = 0;
257 /* check to see if there are < 4 descriptors
258 * waiting to be written back, then kick the hardware to force
259 * them to be written back in case we stay in NAPI.
260 * In this mode on X722 we do not enable Interrupt.
261 */
262 j = i40evf_get_tx_pending(tx_ring);
263
264 if (budget &&
265 ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
266 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
267 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
268 tx_ring->arm_wb = true;
269 }
270
7f12ad74
GR		 271 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
272 tx_ring->queue_index),
273 total_packets, total_bytes);
274
275#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
276 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
277 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
278 /* Make sure that anybody stopping the queue after this
279 * sees the new next_to_clean.
280 */
281 smp_mb();
282 if (__netif_subqueue_stopped(tx_ring->netdev,
283 tx_ring->queue_index) &&
284 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
285 netif_wake_subqueue(tx_ring->netdev,
286 tx_ring->queue_index);
287 ++tx_ring->tx_stats.restart_queue;
288 }
289 }
290
b03a8c1f 291 return !!budget;
7f12ad74
GR		 292}
293
c29af37f 294/**
ecc6a239 295 * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
c29af37f 296 * @vsi: the VSI we care about
ecc6a239 297 * @q_vector: the vector on which to enable writeback
c29af37f
ASJ		 298 *
299 **/
ecc6a239
ASJ		 300static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
301 struct i40e_q_vector *q_vector)
c29af37f 302{
8e0764b4 303 u16 flags = q_vector->tx.ring[0].flags;
ecc6a239 304 u32 val;
8e0764b4 305
ecc6a239
ASJ		 306 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
307 return;
308
309 if (q_vector->arm_wb_state)
310 return;
311
312 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
313 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
314
315 wr32(&vsi->back->hw,
316 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
317 vsi->base_vector - 1), val);
318 q_vector->arm_wb_state = true;
319}
320
321/**
322 * i40evf_force_wb - Issue SW Interrupt so HW does a wb
323 * @vsi: the VSI we care about
324 * @q_vector: the vector on which to force writeback
325 *
326 **/
327void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
328{
329 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
330 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
331 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
332 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
333 /* allow 00 to be written to the index */;
334
335 wr32(&vsi->back->hw,
336 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
337 val);
c29af37f
ASJ		 338}
339
7f12ad74
GR		 340/**
341 * i40e_set_new_dynamic_itr - Find new ITR level
342 * @rc: structure containing ring performance data
343 *
8f5e39ce
JB		 344 * Returns true if ITR changed, false if not
345 *
7f12ad74
GR		 346 * Stores a new ITR value based on packets and byte counts during
347 * the last interrupt. The advantage of per interrupt computation
348 * is faster updates and more accurate ITR for the current traffic
349 * pattern. Constants in this function were computed based on
350 * theoretical maximum wire speed and thresholds were set based on
351 * testing data as well as attempting to minimize response time
352 * while increasing bulk throughput.
353 **/
8f5e39ce 354static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
7f12ad74
GR		 355{
356 enum i40e_latency_range new_latency_range = rc->latency_range;
c56625d5 357 struct i40e_q_vector *qv = rc->ring->q_vector;
7f12ad74
GR		 358 u32 new_itr = rc->itr;
359 int bytes_per_int;
51cc6d9f 360 int usecs;
7f12ad74
GR		 361
362 if (rc->total_packets == 0 || !rc->itr)
8f5e39ce 363 return false;
7f12ad74
GR		 364
365 /* simple throttlerate management
c56625d5 366 * 0-10MB/s lowest (50000 ints/s)
7f12ad74 367 * 10-20MB/s low (20000 ints/s)
c56625d5
JB		 368 * 20-1249MB/s bulk (18000 ints/s)
369 * > 40000 Rx packets per second (8000 ints/s)
51cc6d9f
JB		 370 *
371 * The math works out because the divisor is in 10^(-6) which
372 * turns the bytes/us input value into MB/s values, but
373 * make sure to use usecs, as the register values written
ee2319cf
JB		 374 * are in 2 usec increments in the ITR registers, and make sure
375 * to use the smoothed values that the countdown timer gives us.
7f12ad74 376 */
ee2319cf 377 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
51cc6d9f 378 bytes_per_int = rc->total_bytes / usecs;
ee2319cf 379
de32e3ef 380 switch (new_latency_range) {
7f12ad74
GR		 381 case I40E_LOWEST_LATENCY:
382 if (bytes_per_int > 10)
383 new_latency_range = I40E_LOW_LATENCY;
384 break;
385 case I40E_LOW_LATENCY:
386 if (bytes_per_int > 20)
387 new_latency_range = I40E_BULK_LATENCY;
388 else if (bytes_per_int <= 10)
389 new_latency_range = I40E_LOWEST_LATENCY;
390 break;
391 case I40E_BULK_LATENCY:
c56625d5 392 case I40E_ULTRA_LATENCY:
de32e3ef
CW		 393 default:
394 if (bytes_per_int <= 20)
395 new_latency_range = I40E_LOW_LATENCY;
7f12ad74
GR		 396 break;
397 }
c56625d5
JB		 398
399 /* this is to adjust RX more aggressively when streaming small
400 * packets. The value of 40000 was picked as it is just beyond
401 * what the hardware can receive per second if in low latency
402 * mode.
403 */
404#define RX_ULTRA_PACKET_RATE 40000
405
406 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
407 (&qv->rx == rc))
408 new_latency_range = I40E_ULTRA_LATENCY;
409
de32e3ef 410 rc->latency_range = new_latency_range;
7f12ad74
GR		 411
412 switch (new_latency_range) {
413 case I40E_LOWEST_LATENCY:
c56625d5 414 new_itr = I40E_ITR_50K;
7f12ad74
GR		 415 break;
416 case I40E_LOW_LATENCY:
417 new_itr = I40E_ITR_20K;
418 break;
419 case I40E_BULK_LATENCY:
c56625d5
JB		 420 new_itr = I40E_ITR_18K;
421 break;
422 case I40E_ULTRA_LATENCY:
7f12ad74
GR		 423 new_itr = I40E_ITR_8K;
424 break;
425 default:
426 break;
427 }
428
7f12ad74
GR		 429 rc->total_bytes = 0;
430 rc->total_packets = 0;
8f5e39ce
JB		 431
432 if (new_itr != rc->itr) {
433 rc->itr = new_itr;
434 return true;
435 }
436
437 return false;
7f12ad74
GR		 438}
439
4eeb1fff 440/**
7f12ad74
GR		 441 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
442 * @tx_ring: the tx ring to set up
443 *
444 * Return 0 on success, negative on error
445 **/
446int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
447{
448 struct device *dev = tx_ring->dev;
449 int bi_size;
450
451 if (!dev)
452 return -ENOMEM;
453
67c818a1
MW		 454 /* warn if we are about to overwrite the pointer */
455 WARN_ON(tx_ring->tx_bi);
7f12ad74
GR		 456 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
457 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
458 if (!tx_ring->tx_bi)
459 goto err;
460
461 /* round up to nearest 4K */
462 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 463 /* add u32 for head writeback, align after this takes care of
464 * guaranteeing this is at least one cache line in size
465 */
466 tx_ring->size += sizeof(u32);
7f12ad74
GR		 467 tx_ring->size = ALIGN(tx_ring->size, 4096);
468 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
469 &tx_ring->dma, GFP_KERNEL);
470 if (!tx_ring->desc) {
471 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
472 tx_ring->size);
473 goto err;
474 }
475
476 tx_ring->next_to_use = 0;
477 tx_ring->next_to_clean = 0;
478 return 0;
479
480err:
481 kfree(tx_ring->tx_bi);
482 tx_ring->tx_bi = NULL;
483 return -ENOMEM;
484}
485
486/**
487 * i40evf_clean_rx_ring - Free Rx buffers
488 * @rx_ring: ring to be cleaned
489 **/
490void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
491{
492 struct device *dev = rx_ring->dev;
493 struct i40e_rx_buffer *rx_bi;
494 unsigned long bi_size;
495 u16 i;
496
497 /* ring already cleared, nothing to do */
498 if (!rx_ring->rx_bi)
499 return;
500
a132af24
MW		 501 if (ring_is_ps_enabled(rx_ring)) {
502 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
503
504 rx_bi = &rx_ring->rx_bi[0];
505 if (rx_bi->hdr_buf) {
506 dma_free_coherent(dev,
507 bufsz,
508 rx_bi->hdr_buf,
509 rx_bi->dma);
510 for (i = 0; i < rx_ring->count; i++) {
511 rx_bi = &rx_ring->rx_bi[i];
512 rx_bi->dma = 0;
37a2973a 513 rx_bi->hdr_buf = NULL;
a132af24
MW		 514 }
515 }
516 }
7f12ad74
GR		 517 /* Free all the Rx ring sk_buffs */
518 for (i = 0; i < rx_ring->count; i++) {
519 rx_bi = &rx_ring->rx_bi[i];
520 if (rx_bi->dma) {
521 dma_unmap_single(dev,
522 rx_bi->dma,
523 rx_ring->rx_buf_len,
524 DMA_FROM_DEVICE);
525 rx_bi->dma = 0;
526 }
527 if (rx_bi->skb) {
528 dev_kfree_skb(rx_bi->skb);
529 rx_bi->skb = NULL;
530 }
531 if (rx_bi->page) {
532 if (rx_bi->page_dma) {
533 dma_unmap_page(dev,
534 rx_bi->page_dma,
535 PAGE_SIZE / 2,
536 DMA_FROM_DEVICE);
537 rx_bi->page_dma = 0;
538 }
539 __free_page(rx_bi->page);
540 rx_bi->page = NULL;
541 rx_bi->page_offset = 0;
542 }
543 }
544
545 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
546 memset(rx_ring->rx_bi, 0, bi_size);
547
548 /* Zero out the descriptor ring */
549 memset(rx_ring->desc, 0, rx_ring->size);
550
551 rx_ring->next_to_clean = 0;
552 rx_ring->next_to_use = 0;
553}
554
555/**
556 * i40evf_free_rx_resources - Free Rx resources
557 * @rx_ring: ring to clean the resources from
558 *
559 * Free all receive software resources
560 **/
561void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
562{
563 i40evf_clean_rx_ring(rx_ring);
564 kfree(rx_ring->rx_bi);
565 rx_ring->rx_bi = NULL;
566
567 if (rx_ring->desc) {
568 dma_free_coherent(rx_ring->dev, rx_ring->size,
569 rx_ring->desc, rx_ring->dma);
570 rx_ring->desc = NULL;
571 }
572}
573
a132af24
MW		 574/**
575 * i40evf_alloc_rx_headers - allocate rx header buffers
576 * @rx_ring: ring to alloc buffers
577 *
578 * Allocate rx header buffers for the entire ring. As these are static,
579 * this is only called when setting up a new ring.
580 **/
581void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
582{
583 struct device *dev = rx_ring->dev;
584 struct i40e_rx_buffer *rx_bi;
585 dma_addr_t dma;
586 void *buffer;
587 int buf_size;
588 int i;
589
590 if (rx_ring->rx_bi[0].hdr_buf)
591 return;
592 /* Make sure the buffers don't cross cache line boundaries. */
593 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
594 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
595 &dma, GFP_KERNEL);
596 if (!buffer)
597 return;
598 for (i = 0; i < rx_ring->count; i++) {
599 rx_bi = &rx_ring->rx_bi[i];
600 rx_bi->dma = dma + (i * buf_size);
601 rx_bi->hdr_buf = buffer + (i * buf_size);
602 }
603}
604
7f12ad74
GR		 605/**
606 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
607 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
608 *
609 * Returns 0 on success, negative on failure
610 **/
611int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
612{
613 struct device *dev = rx_ring->dev;
614 int bi_size;
615
67c818a1
MW		 616 /* warn if we are about to overwrite the pointer */
617 WARN_ON(rx_ring->rx_bi);
7f12ad74
GR		 618 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
619 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
620 if (!rx_ring->rx_bi)
621 goto err;
622
f217d6ca 623 u64_stats_init(&rx_ring->syncp);
638702bd 624
7f12ad74
GR		 625 /* Round up to nearest 4K */
626 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
627 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
628 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
629 rx_ring->size = ALIGN(rx_ring->size, 4096);
630 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
631 &rx_ring->dma, GFP_KERNEL);
632
633 if (!rx_ring->desc) {
634 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
635 rx_ring->size);
636 goto err;
637 }
638
639 rx_ring->next_to_clean = 0;
640 rx_ring->next_to_use = 0;
641
642 return 0;
643err:
644 kfree(rx_ring->rx_bi);
645 rx_ring->rx_bi = NULL;
646 return -ENOMEM;
647}
648
649/**
650 * i40e_release_rx_desc - Store the new tail and head values
651 * @rx_ring: ring to bump
652 * @val: new head index
653 **/
654static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
655{
656 rx_ring->next_to_use = val;
657 /* Force memory writes to complete before letting h/w
658 * know there are new descriptors to fetch. (Only
659 * applicable for weak-ordered memory model archs,
660 * such as IA-64).
661 */
662 wmb();
663 writel(val, rx_ring->tail);
664}
665
666/**
a132af24
MW		 667 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
668 * @rx_ring: ring to place buffers on
669 * @cleaned_count: number of buffers to replace
670 **/
671void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
672{
673 u16 i = rx_ring->next_to_use;
674 union i40e_rx_desc *rx_desc;
675 struct i40e_rx_buffer *bi;
676
677 /* do nothing if no valid netdev defined */
678 if (!rx_ring->netdev || !cleaned_count)
679 return;
680
681 while (cleaned_count--) {
682 rx_desc = I40E_RX_DESC(rx_ring, i);
683 bi = &rx_ring->rx_bi[i];
684
685 if (bi->skb) /* desc is in use */
686 goto no_buffers;
687 if (!bi->page) {
688 bi->page = alloc_page(GFP_ATOMIC);
689 if (!bi->page) {
690 rx_ring->rx_stats.alloc_page_failed++;
691 goto no_buffers;
692 }
693 }
694
695 if (!bi->page_dma) {
696 /* use a half page if we're re-using */
697 bi->page_offset ^= PAGE_SIZE / 2;
698 bi->page_dma = dma_map_page(rx_ring->dev,
699 bi->page,
700 bi->page_offset,
701 PAGE_SIZE / 2,
702 DMA_FROM_DEVICE);
703 if (dma_mapping_error(rx_ring->dev,
704 bi->page_dma)) {
705 rx_ring->rx_stats.alloc_page_failed++;
706 bi->page_dma = 0;
707 goto no_buffers;
708 }
709 }
710
711 dma_sync_single_range_for_device(rx_ring->dev,
3578fa0a
JB		 712 rx_ring->rx_bi[0].dma,
713 i * rx_ring->rx_hdr_len,
a132af24
MW		 714 rx_ring->rx_hdr_len,
715 DMA_FROM_DEVICE);
716 /* Refresh the desc even if buffer_addrs didn't change
717 * because each write-back erases this info.
718 */
719 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
720 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
721 i++;
722 if (i == rx_ring->count)
723 i = 0;
724 }
725
726no_buffers:
727 if (rx_ring->next_to_use != i)
728 i40e_release_rx_desc(rx_ring, i);
729}
730
731/**
732 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
7f12ad74
GR		 733 * @rx_ring: ring to place buffers on
734 * @cleaned_count: number of buffers to replace
735 **/
a132af24 736void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
7f12ad74
GR		 737{
738 u16 i = rx_ring->next_to_use;
739 union i40e_rx_desc *rx_desc;
740 struct i40e_rx_buffer *bi;
741 struct sk_buff *skb;
742
743 /* do nothing if no valid netdev defined */
744 if (!rx_ring->netdev || !cleaned_count)
745 return;
746
747 while (cleaned_count--) {
748 rx_desc = I40E_RX_DESC(rx_ring, i);
749 bi = &rx_ring->rx_bi[i];
750 skb = bi->skb;
751
752 if (!skb) {
753 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
754 rx_ring->rx_buf_len);
755 if (!skb) {
756 rx_ring->rx_stats.alloc_buff_failed++;
757 goto no_buffers;
758 }
759 /* initialize queue mapping */
760 skb_record_rx_queue(skb, rx_ring->queue_index);
761 bi->skb = skb;
762 }
763
764 if (!bi->dma) {
765 bi->dma = dma_map_single(rx_ring->dev,
766 skb->data,
767 rx_ring->rx_buf_len,
768 DMA_FROM_DEVICE);
769 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
770 rx_ring->rx_stats.alloc_buff_failed++;
771 bi->dma = 0;
772 goto no_buffers;
773 }
774 }
775
a132af24
MW		 776 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
777 rx_desc->read.hdr_addr = 0;
7f12ad74
GR		 778 i++;
779 if (i == rx_ring->count)
780 i = 0;
781 }
782
783no_buffers:
784 if (rx_ring->next_to_use != i)
785 i40e_release_rx_desc(rx_ring, i);
786}
787
788/**
789 * i40e_receive_skb - Send a completed packet up the stack
790 * @rx_ring: rx ring in play
791 * @skb: packet to send up
792 * @vlan_tag: vlan tag for packet
793 **/
794static void i40e_receive_skb(struct i40e_ring *rx_ring,
795 struct sk_buff *skb, u16 vlan_tag)
796{
797 struct i40e_q_vector *q_vector = rx_ring->q_vector;
7f12ad74
GR		 798
799 if (vlan_tag & VLAN_VID_MASK)
800 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
801
8b650359 802 napi_gro_receive(&q_vector->napi, skb);
7f12ad74
GR		 803}
804
805/**
806 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
807 * @vsi: the VSI we care about
808 * @skb: skb currently being received and modified
809 * @rx_status: status value of last descriptor in packet
810 * @rx_error: error value of last descriptor in packet
811 * @rx_ptype: ptype value of last descriptor in packet
812 **/
813static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
814 struct sk_buff *skb,
815 u32 rx_status,
816 u32 rx_error,
817 u16 rx_ptype)
818{
8a3c91cc
JB		 819 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
820 bool ipv4 = false, ipv6 = false;
7f12ad74
GR		 821 bool ipv4_tunnel, ipv6_tunnel;
822 __wsum rx_udp_csum;
7f12ad74 823 struct iphdr *iph;
8a3c91cc 824 __sum16 csum;
7f12ad74 825
f8faaa40
ASJ		 826 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
827 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
828 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
829 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
7f12ad74 830
7f12ad74
GR		 831 skb->ip_summed = CHECKSUM_NONE;
832
833 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 834 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
835 return;
836
837 /* did the hardware decode the packet and checksum? */
41a1d04b 838 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
8a3c91cc
JB		 839 return;
840
841 /* both known and outer_ip must be set for the below code to work */
842 if (!(decoded.known && decoded.outer_ip))
7f12ad74
GR		 843 return;
844
8a3c91cc
JB		 845 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
846 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
847 ipv4 = true;
848 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
849 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
850 ipv6 = true;
851
852 if (ipv4 &&
41a1d04b
JB		 853 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
854 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
8a3c91cc
JB		 855 goto checksum_fail;
856
ddf1d0d7 857 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 858 if (ipv6 &&
41a1d04b 859 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
8a3c91cc 860 /* don't increment checksum err here, non-fatal err */
7f12ad74
GR		 861 return;
862
8a3c91cc 863 /* there was some L4 error, count error and punt packet to the stack */
41a1d04b 864 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
8a3c91cc
JB		 865 goto checksum_fail;
866
867 /* handle packets that were not able to be checksummed due
868 * to arrival speed, in this case the stack can compute
869 * the csum.
870 */
41a1d04b 871 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
7f12ad74 872 return;
7f12ad74 873
8a3c91cc
JB		 874 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
875 * it in the driver, hardware does not do it for us.
876 * Since L3L4P bit was set we assume a valid IHL value (>=5)
877 * so the total length of IPv4 header is IHL*4 bytes
878 * The UDP_0 bit *may* bet set if the *inner* header is UDP
879 */
818f2e7b 880 if (ipv4_tunnel) {
7f12ad74
GR		 881 skb->transport_header = skb->mac_header +
882 sizeof(struct ethhdr) +
883 (ip_hdr(skb)->ihl * 4);
884
885 /* Add 4 bytes for VLAN tagged packets */
886 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
887 skb->protocol == htons(ETH_P_8021AD))
888 ? VLAN_HLEN : 0;
889
818f2e7b
ASJ		 890 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
891 (udp_hdr(skb)->check != 0)) {
892 rx_udp_csum = udp_csum(skb);
893 iph = ip_hdr(skb);
894 csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
895 (skb->len -
896 skb_transport_offset(skb)),
897 IPPROTO_UDP, rx_udp_csum);
7f12ad74 898
818f2e7b
ASJ		 899 if (udp_hdr(skb)->check != csum)
900 goto checksum_fail;
901
902 } /* else its GRE and so no outer UDP header */
7f12ad74
GR		 903 }
904
905 skb->ip_summed = CHECKSUM_UNNECESSARY;
407fa085 906 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 907
908 return;
909
910checksum_fail:
911 vsi->back->hw_csum_rx_error++;
7f12ad74
GR		 912}
913
914/**
857942fd 915 * i40e_ptype_to_htype - get a hash type
206812b5
JB		 916 * @ptype: the ptype value from the descriptor
917 *
918 * Returns a hash type to be used by skb_set_hash
919 **/
857942fd 920static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
206812b5
JB		 921{
922 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
923
924 if (!decoded.known)
925 return PKT_HASH_TYPE_NONE;
926
927 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
928 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
929 return PKT_HASH_TYPE_L4;
930 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
931 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
932 return PKT_HASH_TYPE_L3;
933 else
934 return PKT_HASH_TYPE_L2;
935}
936
857942fd
ASJ		 937/**
938 * i40e_rx_hash - set the hash value in the skb
939 * @ring: descriptor ring
940 * @rx_desc: specific descriptor
941 **/
942static inline void i40e_rx_hash(struct i40e_ring *ring,
943 union i40e_rx_desc *rx_desc,
944 struct sk_buff *skb,
945 u8 rx_ptype)
946{
947 u32 hash;
948 const __le64 rss_mask =
949 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
950 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
951
952 if (ring->netdev->features & NETIF_F_RXHASH)
953 return;
954
955 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
956 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
957 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
958 }
959}
960
7f12ad74 961/**
a132af24 962 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
7f12ad74
GR		 963 * @rx_ring: rx ring to clean
964 * @budget: how many cleans we're allowed
965 *
966 * Returns true if there's any budget left (e.g. the clean is finished)
967 **/
a132af24 968static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
7f12ad74
GR		 969{
970 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
971 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
972 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
27ca2753 973 const int current_node = numa_mem_id();
7f12ad74
GR		 974 struct i40e_vsi *vsi = rx_ring->vsi;
975 u16 i = rx_ring->next_to_clean;
976 union i40e_rx_desc *rx_desc;
977 u32 rx_error, rx_status;
206812b5 978 u8 rx_ptype;
7f12ad74 979 u64 qword;
7f12ad74 980
a132af24 981 do {
7f12ad74
GR		 982 struct i40e_rx_buffer *rx_bi;
983 struct sk_buff *skb;
984 u16 vlan_tag;
a132af24
MW		 985 /* return some buffers to hardware, one at a time is too slow */
986 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
987 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
988 cleaned_count = 0;
989 }
990
991 i = rx_ring->next_to_clean;
992 rx_desc = I40E_RX_DESC(rx_ring, i);
993 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
994 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
995 I40E_RXD_QW1_STATUS_SHIFT;
996
41a1d04b 997 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 998 break;
999
1000 /* This memory barrier is needed to keep us from reading
1001 * any other fields out of the rx_desc until we know the
1002 * DD bit is set.
1003 */
67317166 1004 dma_rmb();
7f12ad74
GR		 1005 rx_bi = &rx_ring->rx_bi[i];
1006 skb = rx_bi->skb;
a132af24
MW		 1007 if (likely(!skb)) {
1008 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1009 rx_ring->rx_hdr_len);
8b6ed9c2 1010 if (!skb) {
a132af24 1011 rx_ring->rx_stats.alloc_buff_failed++;
8b6ed9c2
JB		 1012 break;
1013 }
1014
a132af24
MW		 1015 /* initialize queue mapping */
1016 skb_record_rx_queue(skb, rx_ring->queue_index);
1017 /* we are reusing so sync this buffer for CPU use */
1018 dma_sync_single_range_for_cpu(rx_ring->dev,
3578fa0a
JB		 1019 rx_ring->rx_bi[0].dma,
1020 i * rx_ring->rx_hdr_len,
a132af24
MW		 1021 rx_ring->rx_hdr_len,
1022 DMA_FROM_DEVICE);
1023 }
7f12ad74
GR		 1024 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1025 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1026 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1027 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1028 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1029 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1030
1031 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1032 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b
JB		 1033 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1034 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
7f12ad74
GR		 1035
1036 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1037 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 1038 prefetch(rx_bi->page);
7f12ad74 1039 rx_bi->skb = NULL;
a132af24
MW		 1040 cleaned_count++;
1041 if (rx_hbo || rx_sph) {
1042 int len;
6995b36c 1043
7f12ad74
GR		 1044 if (rx_hbo)
1045 len = I40E_RX_HDR_SIZE;
7f12ad74 1046 else
a132af24
MW		 1047 len = rx_header_len;
1048 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1049 } else if (skb->len == 0) {
1050 int len;
1051
1052 len = (rx_packet_len > skb_headlen(skb) ?
1053 skb_headlen(skb) : rx_packet_len);
1054 memcpy(__skb_put(skb, len),
1055 rx_bi->page + rx_bi->page_offset,
1056 len);
1057 rx_bi->page_offset += len;
1058 rx_packet_len -= len;
7f12ad74
GR		 1059 }
1060
1061 /* Get the rest of the data if this was a header split */
a132af24 1062 if (rx_packet_len) {
7f12ad74
GR		 1063 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1064 rx_bi->page,
1065 rx_bi->page_offset,
1066 rx_packet_len);
1067
1068 skb->len += rx_packet_len;
1069 skb->data_len += rx_packet_len;
1070 skb->truesize += rx_packet_len;
1071
1072 if ((page_count(rx_bi->page) == 1) &&
1073 (page_to_nid(rx_bi->page) == current_node))
1074 get_page(rx_bi->page);
1075 else
1076 rx_bi->page = NULL;
1077
1078 dma_unmap_page(rx_ring->dev,
1079 rx_bi->page_dma,
1080 PAGE_SIZE / 2,
1081 DMA_FROM_DEVICE);
1082 rx_bi->page_dma = 0;
1083 }
a132af24 1084 I40E_RX_INCREMENT(rx_ring, i);
7f12ad74
GR		 1085
1086 if (unlikely(
41a1d04b 1087 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
7f12ad74
GR		 1088 struct i40e_rx_buffer *next_buffer;
1089
1090 next_buffer = &rx_ring->rx_bi[i];
a132af24 1091 next_buffer->skb = skb;
7f12ad74 1092 rx_ring->rx_stats.non_eop_descs++;
a132af24 1093 continue;
7f12ad74
GR		 1094 }
1095
1096 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1097 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
7f12ad74 1098 dev_kfree_skb_any(skb);
a132af24 1099 continue;
7f12ad74
GR		 1100 }
1101
857942fd
ASJ		 1102 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1103
7f12ad74
GR		 1104 /* probably a little skewed due to removing CRC */
1105 total_rx_bytes += skb->len;
1106 total_rx_packets++;
1107
1108 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1109
1110 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1111
41a1d04b 1112 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
7f12ad74
GR		 1113 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1114 : 0;
a132af24
MW		 1115#ifdef I40E_FCOE
1116 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1117 dev_kfree_skb_any(skb);
1118 continue;
1119 }
1120#endif
7f12ad74
GR		 1121 i40e_receive_skb(rx_ring, skb, vlan_tag);
1122
7f12ad74 1123 rx_desc->wb.qword1.status_error_len = 0;
7f12ad74 1124
a132af24
MW		 1125 } while (likely(total_rx_packets < budget));
1126
1127 u64_stats_update_begin(&rx_ring->syncp);
1128 rx_ring->stats.packets += total_rx_packets;
1129 rx_ring->stats.bytes += total_rx_bytes;
1130 u64_stats_update_end(&rx_ring->syncp);
1131 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1132 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1133
1134 return total_rx_packets;
1135}
1136
1137/**
1138 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1139 * @rx_ring: rx ring to clean
1140 * @budget: how many cleans we're allowed
1141 *
1142 * Returns number of packets cleaned
1143 **/
1144static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1145{
1146 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1147 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1148 struct i40e_vsi *vsi = rx_ring->vsi;
1149 union i40e_rx_desc *rx_desc;
1150 u32 rx_error, rx_status;
1151 u16 rx_packet_len;
1152 u8 rx_ptype;
1153 u64 qword;
1154 u16 i;
1155
1156 do {
1157 struct i40e_rx_buffer *rx_bi;
1158 struct sk_buff *skb;
1159 u16 vlan_tag;
7f12ad74
GR		 1160 /* return some buffers to hardware, one at a time is too slow */
1161 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1162 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
7f12ad74
GR		 1163 cleaned_count = 0;
1164 }
1165
a132af24
MW		 1166 i = rx_ring->next_to_clean;
1167 rx_desc = I40E_RX_DESC(rx_ring, i);
7f12ad74
GR		 1168 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1169 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1170 I40E_RXD_QW1_STATUS_SHIFT;
1171
41a1d04b 1172 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1173 break;
1174
1175 /* This memory barrier is needed to keep us from reading
1176 * any other fields out of the rx_desc until we know the
1177 * DD bit is set.
1178 */
67317166 1179 dma_rmb();
a132af24
MW		 1180
1181 rx_bi = &rx_ring->rx_bi[i];
1182 skb = rx_bi->skb;
1183 prefetch(skb->data);
1184
1185 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1186 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1187
1188 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1189 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b 1190 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
a132af24
MW		 1191
1192 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1193 I40E_RXD_QW1_PTYPE_SHIFT;
1194 rx_bi->skb = NULL;
1195 cleaned_count++;
1196
1197 /* Get the header and possibly the whole packet
1198 * If this is an skb from previous receive dma will be 0
1199 */
1200 skb_put(skb, rx_packet_len);
1201 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1202 DMA_FROM_DEVICE);
1203 rx_bi->dma = 0;
1204
1205 I40E_RX_INCREMENT(rx_ring, i);
1206
1207 if (unlikely(
41a1d04b 1208 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
a132af24
MW		 1209 rx_ring->rx_stats.non_eop_descs++;
1210 continue;
1211 }
1212
1213 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1214 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
a132af24 1215 dev_kfree_skb_any(skb);
a132af24
MW		 1216 continue;
1217 }
1218
857942fd 1219 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
a132af24
MW		 1220 /* probably a little skewed due to removing CRC */
1221 total_rx_bytes += skb->len;
1222 total_rx_packets++;
1223
1224 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1225
1226 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1227
41a1d04b 1228 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
a132af24
MW		 1229 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1230 : 0;
1231 i40e_receive_skb(rx_ring, skb, vlan_tag);
1232
a132af24
MW		 1233 rx_desc->wb.qword1.status_error_len = 0;
1234 } while (likely(total_rx_packets < budget));
7f12ad74 1235
7f12ad74
GR		 1236 u64_stats_update_begin(&rx_ring->syncp);
1237 rx_ring->stats.packets += total_rx_packets;
1238 rx_ring->stats.bytes += total_rx_bytes;
1239 u64_stats_update_end(&rx_ring->syncp);
1240 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1241 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1242
a132af24 1243 return total_rx_packets;
7f12ad74
GR		 1244}
1245
8f5e39ce
JB		 1246static u32 i40e_buildreg_itr(const int type, const u16 itr)
1247{
1248 u32 val;
1249
1250 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
40d72a50
JB		 1251 /* Don't clear PBA because that can cause lost interrupts that
1252 * came in while we were cleaning/polling
1253 */
8f5e39ce
JB		 1254 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1255 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1256
1257 return val;
1258}
1259
1260/* a small macro to shorten up some long lines */
1261#define INTREG I40E_VFINT_DYN_CTLN1
1262
de32e3ef
CW		 1263/**
1264 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1265 * @vsi: the VSI we care about
1266 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1267 *
1268 **/
1269static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1270 struct i40e_q_vector *q_vector)
1271{
1272 struct i40e_hw *hw = &vsi->back->hw;
8f5e39ce
JB		 1273 bool rx = false, tx = false;
1274 u32 rxval, txval;
de32e3ef 1275 int vector;
de32e3ef
CW		 1276
1277 vector = (q_vector->v_idx + vsi->base_vector);
ee2319cf
JB		 1278
1279 /* avoid dynamic calculation if in countdown mode OR if
1280 * all dynamic is disabled
1281 */
8f5e39ce
JB		 1282 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1283
ee2319cf
JB		 1284 if (q_vector->itr_countdown > 0 ||
1285 (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1286 !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1287 goto enable_int;
1288 }
1289
de32e3ef 1290 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
8f5e39ce
JB		 1291 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1292 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
de32e3ef 1293 }
4eeb1fff 1294
de32e3ef 1295 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
8f5e39ce
JB		 1296 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1297 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1298 }
4eeb1fff 1299
8f5e39ce
JB		 1300 if (rx || tx) {
1301 /* get the higher of the two ITR adjustments and
1302 * use the same value for both ITR registers
1303 * when in adaptive mode (Rx and/or Tx)
1304 */
1305 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1306
1307 q_vector->tx.itr = q_vector->rx.itr = itr;
1308 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1309 tx = true;
1310 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1311 rx = true;
de32e3ef 1312 }
8f5e39ce
JB		 1313
1314 /* only need to enable the interrupt once, but need
1315 * to possibly update both ITR values
1316 */
1317 if (rx) {
1318 /* set the INTENA_MSK_MASK so that this first write
1319 * won't actually enable the interrupt, instead just
1320 * updating the ITR (it's bit 31 PF and VF)
1321 */
1322 rxval |= BIT(31);
1323 /* don't check _DOWN because interrupt isn't being enabled */
1324 wr32(hw, INTREG(vector - 1), rxval);
1325 }
1326
ee2319cf 1327enable_int:
8f5e39ce
JB		 1328 if (!test_bit(__I40E_DOWN, &vsi->state))
1329 wr32(hw, INTREG(vector - 1), txval);
ee2319cf
JB		 1330
1331 if (q_vector->itr_countdown)
1332 q_vector->itr_countdown--;
1333 else
1334 q_vector->itr_countdown = ITR_COUNTDOWN_START;
de32e3ef
CW		 1335}
1336
7f12ad74
GR		 1337/**
1338 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1339 * @napi: napi struct with our devices info in it
1340 * @budget: amount of work driver is allowed to do this pass, in packets
1341 *
1342 * This function will clean all queues associated with a q_vector.
1343 *
1344 * Returns the amount of work done
1345 **/
1346int i40evf_napi_poll(struct napi_struct *napi, int budget)
1347{
1348 struct i40e_q_vector *q_vector =
1349 container_of(napi, struct i40e_q_vector, napi);
1350 struct i40e_vsi *vsi = q_vector->vsi;
1351 struct i40e_ring *ring;
1352 bool clean_complete = true;
c29af37f 1353 bool arm_wb = false;
7f12ad74 1354 int budget_per_ring;
32b3e08f 1355 int work_done = 0;
7f12ad74
GR		 1356
1357 if (test_bit(__I40E_DOWN, &vsi->state)) {
1358 napi_complete(napi);
1359 return 0;
1360 }
1361
1362 /* Since the actual Tx work is minimal, we can give the Tx a larger
1363 * budget and be more aggressive about cleaning up the Tx descriptors.
1364 */
c29af37f 1365 i40e_for_each_ring(ring, q_vector->tx) {
7f12ad74 1366 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
44cdb791 1367 arm_wb = arm_wb || ring->arm_wb;
0deda868 1368 ring->arm_wb = false;
c29af37f 1369 }
7f12ad74 1370
c67caceb
AD		 1371 /* Handle case where we are called by netpoll with a budget of 0 */
1372 if (budget <= 0)
1373 goto tx_only;
1374
7f12ad74
GR		 1375 /* We attempt to distribute budget to each Rx queue fairly, but don't
1376 * allow the budget to go below 1 because that would exit polling early.
1377 */
1378 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1379
a132af24 1380 i40e_for_each_ring(ring, q_vector->rx) {
32b3e08f
JB		 1381 int cleaned;
1382
a132af24
MW		 1383 if (ring_is_ps_enabled(ring))
1384 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1385 else
1386 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
32b3e08f
JB		 1387
1388 work_done += cleaned;
a132af24
MW		 1389 /* if we didn't clean as many as budgeted, we must be done */
1390 clean_complete &= (budget_per_ring != cleaned);
1391 }
7f12ad74
GR		 1392
1393 /* If work not completed, return budget and polling will return */
c29af37f 1394 if (!clean_complete) {
c67caceb 1395tx_only:
164c9f54
ASJ		 1396 if (arm_wb) {
1397 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
ecc6a239 1398 i40e_enable_wb_on_itr(vsi, q_vector);
164c9f54 1399 }
7f12ad74 1400 return budget;
c29af37f 1401 }
7f12ad74 1402
8e0764b4
ASJ		 1403 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1404 q_vector->arm_wb_state = false;
1405
7f12ad74 1406 /* Work is done so exit the polling mode and re-enable the interrupt */
32b3e08f 1407 napi_complete_done(napi, work_done);
de32e3ef 1408 i40e_update_enable_itr(vsi, q_vector);
7f12ad74
GR		 1409 return 0;
1410}
1411
1412/**
3e587cf3 1413 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
7f12ad74
GR		 1414 * @skb: send buffer
1415 * @tx_ring: ring to send buffer on
1416 * @flags: the tx flags to be set
1417 *
1418 * Checks the skb and set up correspondingly several generic transmit flags
1419 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1420 *
1421 * Returns error code indicate the frame should be dropped upon error and the
1422 * otherwise returns 0 to indicate the flags has been set properly.
1423 **/
3e587cf3
JB		 1424static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1425 struct i40e_ring *tx_ring,
1426 u32 *flags)
7f12ad74
GR		 1427{
1428 __be16 protocol = skb->protocol;
1429 u32 tx_flags = 0;
1430
31eaaccf
GR		 1431 if (protocol == htons(ETH_P_8021Q) &&
1432 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1433 /* When HW VLAN acceleration is turned off by the user the
1434 * stack sets the protocol to 8021q so that the driver
1435 * can take any steps required to support the SW only
1436 * VLAN handling. In our case the driver doesn't need
1437 * to take any further steps so just set the protocol
1438 * to the encapsulated ethertype.
1439 */
1440 skb->protocol = vlan_get_protocol(skb);
1441 goto out;
1442 }
1443
7f12ad74 1444 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 1445 if (skb_vlan_tag_present(skb)) {
1446 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
7f12ad74
GR		 1447 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1448 /* else if it is a SW VLAN, check the next protocol and store the tag */
1449 } else if (protocol == htons(ETH_P_8021Q)) {
1450 struct vlan_hdr *vhdr, _vhdr;
6995b36c 1451
7f12ad74
GR		 1452 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1453 if (!vhdr)
1454 return -EINVAL;
1455
1456 protocol = vhdr->h_vlan_encapsulated_proto;
1457 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1458 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1459 }
1460
31eaaccf 1461out:
7f12ad74
GR		 1462 *flags = tx_flags;
1463 return 0;
1464}
1465
1466/**
1467 * i40e_tso - set up the tso context descriptor
1468 * @tx_ring: ptr to the ring to send
1469 * @skb: ptr to the skb we're sending
7f12ad74 1470 * @hdr_len: ptr to the size of the packet header
9c883bd3 1471 * @cd_type_cmd_tso_mss: Quad Word 1
7f12ad74
GR		 1472 *
1473 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1474 **/
1475static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
9c883bd3 1476 u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
7f12ad74
GR		 1477{
1478 u32 cd_cmd, cd_tso_len, cd_mss;
fe6d4aa4 1479 struct ipv6hdr *ipv6h;
7f12ad74
GR		 1480 struct tcphdr *tcph;
1481 struct iphdr *iph;
1482 u32 l4len;
1483 int err;
7f12ad74 1484
e9f6563d
SN		 1485 if (skb->ip_summed != CHECKSUM_PARTIAL)
1486 return 0;
1487
7f12ad74
GR		 1488 if (!skb_is_gso(skb))
1489 return 0;
1490
fe6d4aa4
FR		 1491 err = skb_cow_head(skb, 0);
1492 if (err < 0)
1493 return err;
7f12ad74 1494
85e76d03
AS		 1495 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1496 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1497
1498 if (iph->version == 4) {
7f12ad74
GR		 1499 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1500 iph->tot_len = 0;
1501 iph->check = 0;
1502 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1503 0, IPPROTO_TCP, 0);
85e76d03 1504 } else if (ipv6h->version == 6) {
7f12ad74
GR		 1505 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1506 ipv6h->payload_len = 0;
1507 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1508 0, IPPROTO_TCP, 0);
1509 }
1510
1511 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1512 *hdr_len = (skb->encapsulation
1513 ? (skb_inner_transport_header(skb) - skb->data)
1514 : skb_transport_offset(skb)) + l4len;
1515
1516 /* find the field values */
1517 cd_cmd = I40E_TX_CTX_DESC_TSO;
1518 cd_tso_len = skb->len - *hdr_len;
1519 cd_mss = skb_shinfo(skb)->gso_size;
1520 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1521 ((u64)cd_tso_len <<
1522 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1523 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1524 return 1;
1525}
1526
1527/**
1528 * i40e_tx_enable_csum - Enable Tx checksum offloads
1529 * @skb: send buffer
89232c3b 1530 * @tx_flags: pointer to Tx flags currently set
7f12ad74
GR		 1531 * @td_cmd: Tx descriptor command bits to set
1532 * @td_offset: Tx descriptor header offsets to set
1533 * @cd_tunneling: ptr to context desc bits
1534 **/
89232c3b 1535static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
7f12ad74
GR		 1536 u32 *td_cmd, u32 *td_offset,
1537 struct i40e_ring *tx_ring,
1538 u32 *cd_tunneling)
1539{
1540 struct ipv6hdr *this_ipv6_hdr;
1541 unsigned int this_tcp_hdrlen;
1542 struct iphdr *this_ip_hdr;
1543 u32 network_hdr_len;
1544 u8 l4_hdr = 0;
527274c7
ASJ		 1545 struct udphdr *oudph;
1546 struct iphdr *oiph;
45991204 1547 u32 l4_tunnel = 0;
7f12ad74
GR		 1548
1549 if (skb->encapsulation) {
45991204
ASJ		 1550 switch (ip_hdr(skb)->protocol) {
1551 case IPPROTO_UDP:
527274c7
ASJ		 1552 oudph = udp_hdr(skb);
1553 oiph = ip_hdr(skb);
45991204 1554 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
89232c3b 1555 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
45991204
ASJ		 1556 break;
1557 default:
1558 return;
1559 }
7f12ad74
GR		 1560 network_hdr_len = skb_inner_network_header_len(skb);
1561 this_ip_hdr = inner_ip_hdr(skb);
1562 this_ipv6_hdr = inner_ipv6_hdr(skb);
1563 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1564
89232c3b
ASJ		 1565 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1566 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1567 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1568 ip_hdr(skb)->check = 0;
1569 } else {
1570 *cd_tunneling |=
1571 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1572 }
89232c3b 1573 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
85e76d03 1574 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
89232c3b 1575 if (*tx_flags & I40E_TX_FLAGS_TSO)
7f12ad74 1576 ip_hdr(skb)->check = 0;
7f12ad74
GR		 1577 }
1578
1579 /* Now set the ctx descriptor fields */
1580 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
45991204
ASJ		 1581 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1582 l4_tunnel |
7f12ad74
GR		 1583 ((skb_inner_network_offset(skb) -
1584 skb_transport_offset(skb)) >> 1) <<
1585 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
85e76d03 1586 if (this_ip_hdr->version == 6) {
89232c3b
ASJ		 1587 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1588 *tx_flags |= I40E_TX_FLAGS_IPV6;
85e76d03
AS		 1589 }
1590
527274c7
ASJ		 1591 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1592 (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING) &&
1593 (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1594 oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1595 oiph->daddr,
1596 (skb->len - skb_transport_offset(skb)),
1597 IPPROTO_UDP, 0);
1598 *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1599 }
7f12ad74
GR		 1600 } else {
1601 network_hdr_len = skb_network_header_len(skb);
1602 this_ip_hdr = ip_hdr(skb);
1603 this_ipv6_hdr = ipv6_hdr(skb);
1604 this_tcp_hdrlen = tcp_hdrlen(skb);
1605 }
1606
1607 /* Enable IP checksum offloads */
89232c3b 1608 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
7f12ad74
GR		 1609 l4_hdr = this_ip_hdr->protocol;
1610 /* the stack computes the IP header already, the only time we
1611 * need the hardware to recompute it is in the case of TSO.
1612 */
89232c3b 1613 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1614 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1615 this_ip_hdr->check = 0;
1616 } else {
1617 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1618 }
1619 /* Now set the td_offset for IP header length */
1620 *td_offset = (network_hdr_len >> 2) <<
1621 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
89232c3b 1622 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
7f12ad74
GR		 1623 l4_hdr = this_ipv6_hdr->nexthdr;
1624 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1625 /* Now set the td_offset for IP header length */
1626 *td_offset = (network_hdr_len >> 2) <<
1627 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1628 }
1629 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1630 *td_offset |= (skb_network_offset(skb) >> 1) <<
1631 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1632
1633 /* Enable L4 checksum offloads */
1634 switch (l4_hdr) {
1635 case IPPROTO_TCP:
1636 /* enable checksum offloads */
1637 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1638 *td_offset |= (this_tcp_hdrlen >> 2) <<
1639 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1640 break;
1641 case IPPROTO_SCTP:
1642 /* enable SCTP checksum offload */
1643 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1644 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1645 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1646 break;
1647 case IPPROTO_UDP:
1648 /* enable UDP checksum offload */
1649 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1650 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1651 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1652 break;
1653 default:
1654 break;
1655 }
1656}
1657
1658/**
1659 * i40e_create_tx_ctx Build the Tx context descriptor
1660 * @tx_ring: ring to create the descriptor on
1661 * @cd_type_cmd_tso_mss: Quad Word 1
1662 * @cd_tunneling: Quad Word 0 - bits 0-31
1663 * @cd_l2tag2: Quad Word 0 - bits 32-63
1664 **/
1665static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1666 const u64 cd_type_cmd_tso_mss,
1667 const u32 cd_tunneling, const u32 cd_l2tag2)
1668{
1669 struct i40e_tx_context_desc *context_desc;
1670 int i = tx_ring->next_to_use;
1671
ff40dd5d
JB		 1672 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1673 !cd_tunneling && !cd_l2tag2)
7f12ad74
GR		 1674 return;
1675
1676 /* grab the next descriptor */
1677 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1678
1679 i++;
1680 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1681
1682 /* cpu_to_le32 and assign to struct fields */
1683 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1684 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 1685 context_desc->rsvd = cpu_to_le16(0);
7f12ad74
GR		 1686 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1687}
1688
4eeb1fff 1689/**
71da6197
AS		 1690 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1691 * @skb: send buffer
1692 * @tx_flags: collected send information
71da6197
AS		 1693 *
1694 * Note: Our HW can't scatter-gather more than 8 fragments to build
1695 * a packet on the wire and so we need to figure out the cases where we
1696 * need to linearize the skb.
1697 **/
30520831 1698static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
71da6197
AS		 1699{
1700 struct skb_frag_struct *frag;
1701 bool linearize = false;
1702 unsigned int size = 0;
1703 u16 num_frags;
1704 u16 gso_segs;
1705
1706 num_frags = skb_shinfo(skb)->nr_frags;
1707 gso_segs = skb_shinfo(skb)->gso_segs;
1708
1709 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
30520831 1710 u16 j = 0;
71da6197
AS		 1711
1712 if (num_frags < (I40E_MAX_BUFFER_TXD))
1713 goto linearize_chk_done;
1714 /* try the simple math, if we have too many frags per segment */
1715 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1716 I40E_MAX_BUFFER_TXD) {
1717 linearize = true;
1718 goto linearize_chk_done;
1719 }
1720 frag = &skb_shinfo(skb)->frags[0];
71da6197
AS		 1721 /* we might still have more fragments per segment */
1722 do {
1723 size += skb_frag_size(frag);
1724 frag++; j++;
30520831
ASJ		 1725 if ((size >= skb_shinfo(skb)->gso_size) &&
1726 (j < I40E_MAX_BUFFER_TXD)) {
1727 size = (size % skb_shinfo(skb)->gso_size);
1728 j = (size) ? 1 : 0;
1729 }
71da6197 1730 if (j == I40E_MAX_BUFFER_TXD) {
30520831
ASJ		 1731 linearize = true;
1732 break;
71da6197
AS		 1733 }
1734 num_frags--;
1735 } while (num_frags);
1736 } else {
1737 if (num_frags >= I40E_MAX_BUFFER_TXD)
1738 linearize = true;
1739 }
1740
1741linearize_chk_done:
1742 return linearize;
1743}
1744
8f6a2b05
JB		 1745/**
1746 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1747 * @tx_ring: the ring to be checked
1748 * @size: the size buffer we want to assure is available
1749 *
1750 * Returns -EBUSY if a stop is needed, else 0
1751 **/
1752static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1753{
1754 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1755 /* Memory barrier before checking head and tail */
1756 smp_mb();
1757
1758 /* Check again in a case another CPU has just made room available. */
1759 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1760 return -EBUSY;
1761
1762 /* A reprieve! - use start_queue because it doesn't call schedule */
1763 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1764 ++tx_ring->tx_stats.restart_queue;
1765 return 0;
1766}
1767
1768/**
1769 * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1770 * @tx_ring: the ring to be checked
1771 * @size: the size buffer we want to assure is available
1772 *
1773 * Returns 0 if stop is not needed
1774 **/
3e587cf3 1775static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
8f6a2b05
JB		 1776{
1777 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1778 return 0;
1779 return __i40evf_maybe_stop_tx(tx_ring, size);
1780}
1781
7f12ad74 1782/**
3e587cf3 1783 * i40evf_tx_map - Build the Tx descriptor
7f12ad74
GR		 1784 * @tx_ring: ring to send buffer on
1785 * @skb: send buffer
1786 * @first: first buffer info buffer to use
1787 * @tx_flags: collected send information
1788 * @hdr_len: size of the packet header
1789 * @td_cmd: the command field in the descriptor
1790 * @td_offset: offset for checksum or crc
1791 **/
3e587cf3
JB		 1792static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1793 struct i40e_tx_buffer *first, u32 tx_flags,
1794 const u8 hdr_len, u32 td_cmd, u32 td_offset)
7f12ad74
GR		 1795{
1796 unsigned int data_len = skb->data_len;
1797 unsigned int size = skb_headlen(skb);
1798 struct skb_frag_struct *frag;
1799 struct i40e_tx_buffer *tx_bi;
1800 struct i40e_tx_desc *tx_desc;
1801 u16 i = tx_ring->next_to_use;
1802 u32 td_tag = 0;
1803 dma_addr_t dma;
1804 u16 gso_segs;
6a7fded7
ASJ		 1805 u16 desc_count = 0;
1806 bool tail_bump = true;
1807 bool do_rs = false;
7f12ad74
GR		 1808
1809 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1810 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1811 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1812 I40E_TX_FLAGS_VLAN_SHIFT;
1813 }
1814
1815 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1816 gso_segs = skb_shinfo(skb)->gso_segs;
1817 else
1818 gso_segs = 1;
1819
1820 /* multiply data chunks by size of headers */
1821 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1822 first->gso_segs = gso_segs;
1823 first->skb = skb;
1824 first->tx_flags = tx_flags;
1825
1826 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1827
1828 tx_desc = I40E_TX_DESC(tx_ring, i);
1829 tx_bi = first;
1830
1831 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1832 if (dma_mapping_error(tx_ring->dev, dma))
1833 goto dma_error;
1834
1835 /* record length, and DMA address */
1836 dma_unmap_len_set(tx_bi, len, size);
1837 dma_unmap_addr_set(tx_bi, dma, dma);
1838
1839 tx_desc->buffer_addr = cpu_to_le64(dma);
1840
1841 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1842 tx_desc->cmd_type_offset_bsz =
1843 build_ctob(td_cmd, td_offset,
1844 I40E_MAX_DATA_PER_TXD, td_tag);
1845
1846 tx_desc++;
1847 i++;
6a7fded7
ASJ		 1848 desc_count++;
1849
7f12ad74
GR		 1850 if (i == tx_ring->count) {
1851 tx_desc = I40E_TX_DESC(tx_ring, 0);
1852 i = 0;
1853 }
1854
1855 dma += I40E_MAX_DATA_PER_TXD;
1856 size -= I40E_MAX_DATA_PER_TXD;
1857
1858 tx_desc->buffer_addr = cpu_to_le64(dma);
1859 }
1860
1861 if (likely(!data_len))
1862 break;
1863
1864 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1865 size, td_tag);
1866
1867 tx_desc++;
1868 i++;
6a7fded7
ASJ		 1869 desc_count++;
1870
7f12ad74
GR		 1871 if (i == tx_ring->count) {
1872 tx_desc = I40E_TX_DESC(tx_ring, 0);
1873 i = 0;
1874 }
1875
1876 size = skb_frag_size(frag);
1877 data_len -= size;
1878
1879 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1880 DMA_TO_DEVICE);
1881
1882 tx_bi = &tx_ring->tx_bi[i];
1883 }
1884
7f12ad74
GR		 1885 /* set next_to_watch value indicating a packet is present */
1886 first->next_to_watch = tx_desc;
1887
1888 i++;
1889 if (i == tx_ring->count)
1890 i = 0;
1891
1892 tx_ring->next_to_use = i;
1893
6a7fded7
ASJ		 1894 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1895 tx_ring->queue_index),
1896 first->bytecount);
8f6a2b05 1897 i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
6a7fded7
ASJ		 1898
1899 /* Algorithm to optimize tail and RS bit setting:
1900 * if xmit_more is supported
1901 * if xmit_more is true
1902 * do not update tail and do not mark RS bit.
1903 * if xmit_more is false and last xmit_more was false
1904 * if every packet spanned less than 4 desc
1905 * then set RS bit on 4th packet and update tail
1906 * on every packet
1907 * else
1908 * update tail and set RS bit on every packet.
1909 * if xmit_more is false and last_xmit_more was true
1910 * update tail and set RS bit.
6a7fded7
ASJ		 1911 *
1912 * Optimization: wmb to be issued only in case of tail update.
1913 * Also optimize the Descriptor WB path for RS bit with the same
1914 * algorithm.
1915 *
1916 * Note: If there are less than 4 packets
1917 * pending and interrupts were disabled the service task will
1918 * trigger a force WB.
1919 */
1920 if (skb->xmit_more &&
1921 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1922 tx_ring->queue_index))) {
1923 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1924 tail_bump = false;
1925 } else if (!skb->xmit_more &&
1926 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1927 tx_ring->queue_index)) &&
1928 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1929 (tx_ring->packet_stride < WB_STRIDE) &&
1930 (desc_count < WB_STRIDE)) {
1931 tx_ring->packet_stride++;
1932 } else {
1933 tx_ring->packet_stride = 0;
1934 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1935 do_rs = true;
1936 }
1937 if (do_rs)
1938 tx_ring->packet_stride = 0;
1939
1940 tx_desc->cmd_type_offset_bsz =
1941 build_ctob(td_cmd, td_offset, size, td_tag) |
1942 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1943 I40E_TX_DESC_CMD_EOP) <<
1944 I40E_TXD_QW1_CMD_SHIFT);
1945
7f12ad74 1946 /* notify HW of packet */
6a7fded7 1947 if (!tail_bump)
489ce7a4 1948 prefetchw(tx_desc + 1);
7f12ad74 1949
6a7fded7
ASJ		 1950 if (tail_bump) {
1951 /* Force memory writes to complete before letting h/w
1952 * know there are new descriptors to fetch. (Only
1953 * applicable for weak-ordered memory model archs,
1954 * such as IA-64).
1955 */
1956 wmb();
1957 writel(i, tx_ring->tail);
1958 }
1959
7f12ad74
GR		 1960 return;
1961
1962dma_error:
1963 dev_info(tx_ring->dev, "TX DMA map failed\n");
1964
1965 /* clear dma mappings for failed tx_bi map */
1966 for (;;) {
1967 tx_bi = &tx_ring->tx_bi[i];
1968 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1969 if (tx_bi == first)
1970 break;
1971 if (i == 0)
1972 i = tx_ring->count;
1973 i--;
1974 }
1975
1976 tx_ring->next_to_use = i;
1977}
1978
7f12ad74 1979/**
3e587cf3 1980 * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
7f12ad74
GR		 1981 * @skb: send buffer
1982 * @tx_ring: ring to send buffer on
1983 *
1984 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1985 * there is not enough descriptors available in this ring since we need at least
1986 * one descriptor.
1987 **/
3e587cf3
JB		 1988static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1989 struct i40e_ring *tx_ring)
7f12ad74 1990{
7f12ad74 1991 unsigned int f;
7f12ad74
GR		 1992 int count = 0;
1993
1994 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1995 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 1996 * + 4 desc gap to avoid the cache line where head is,
7f12ad74
GR		 1997 * + 1 desc for context descriptor,
1998 * otherwise try next time
1999 */
7f12ad74
GR		 2000 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2001 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 2002
7f12ad74 2003 count += TXD_USE_COUNT(skb_headlen(skb));
8f6a2b05 2004 if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
7f12ad74
GR		 2005 tx_ring->tx_stats.tx_busy++;
2006 return 0;
2007 }
2008 return count;
2009}
2010
2011/**
2012 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2013 * @skb: send buffer
2014 * @tx_ring: ring to send buffer on
2015 *
2016 * Returns NETDEV_TX_OK if sent, else an error code
2017 **/
2018static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2019 struct i40e_ring *tx_ring)
2020{
2021 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2022 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2023 struct i40e_tx_buffer *first;
2024 u32 td_offset = 0;
2025 u32 tx_flags = 0;
2026 __be16 protocol;
2027 u32 td_cmd = 0;
2028 u8 hdr_len = 0;
2029 int tso;
6995b36c 2030
b74118f0
JB		 2031 /* prefetch the data, we'll need it later */
2032 prefetch(skb->data);
2033
3e587cf3 2034 if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
7f12ad74
GR		 2035 return NETDEV_TX_BUSY;
2036
2037 /* prepare the xmit flags */
3e587cf3 2038 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
7f12ad74
GR		 2039 goto out_drop;
2040
2041 /* obtain protocol of skb */
a12c4158 2042 protocol = vlan_get_protocol(skb);
7f12ad74
GR		 2043
2044 /* record the location of the first descriptor for this packet */
2045 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2046
2047 /* setup IPv4/IPv6 offloads */
2048 if (protocol == htons(ETH_P_IP))
2049 tx_flags |= I40E_TX_FLAGS_IPV4;
2050 else if (protocol == htons(ETH_P_IPV6))
2051 tx_flags |= I40E_TX_FLAGS_IPV6;
2052
9c883bd3 2053 tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
7f12ad74
GR		 2054
2055 if (tso < 0)
2056 goto out_drop;
2057 else if (tso)
2058 tx_flags |= I40E_TX_FLAGS_TSO;
2059
2fc3d715 2060 if (i40e_chk_linearize(skb, tx_flags)) {
71da6197
AS		 2061 if (skb_linearize(skb))
2062 goto out_drop;
2fc3d715
ASJ		 2063 tx_ring->tx_stats.tx_linearize++;
2064 }
7f12ad74
GR		 2065 skb_tx_timestamp(skb);
2066
2067 /* always enable CRC insertion offload */
2068 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2069
2070 /* Always offload the checksum, since it's in the data descriptor */
2071 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2072 tx_flags |= I40E_TX_FLAGS_CSUM;
2073
89232c3b 2074 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
7f12ad74
GR		 2075 tx_ring, &cd_tunneling);
2076 }
2077
2078 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2079 cd_tunneling, cd_l2tag2);
2080
3e587cf3
JB		 2081 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2082 td_cmd, td_offset);
7f12ad74 2083
7f12ad74
GR		 2084 return NETDEV_TX_OK;
2085
2086out_drop:
2087 dev_kfree_skb_any(skb);
2088 return NETDEV_TX_OK;
2089}
2090
2091/**
2092 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2093 * @skb: send buffer
2094 * @netdev: network interface device structure
2095 *
2096 * Returns NETDEV_TX_OK if sent, else an error code
2097 **/
2098netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2099{
2100 struct i40evf_adapter *adapter = netdev_priv(netdev);
0dd438d8 2101 struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
7f12ad74
GR		 2102
2103 /* hardware can't handle really short frames, hardware padding works
2104 * beyond this point
2105 */
2106 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2107 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2108 return NETDEV_TX_OK;
2109 skb->len = I40E_MIN_TX_LEN;
2110 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2111 }
2112
2113 return i40e_xmit_frame_ring(skb, tx_ring);
2114}
Linux 6.x block layer and io_uring tree(s)