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i40e: Bump version
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
CommitLineData
7f12ad74
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 *
22 ******************************************************************************/
23
24#include "i40evf.h"
25
26static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
27 u32 td_tag)
28{
29 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
30 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
31 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
32 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
33 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
34}
35
36#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
37
38/**
39 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
40 * @ring: the ring that owns the buffer
41 * @tx_buffer: the buffer to free
42 **/
43static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
44 struct i40e_tx_buffer *tx_buffer)
45{
46 if (tx_buffer->skb) {
47 dev_kfree_skb_any(tx_buffer->skb);
48 if (dma_unmap_len(tx_buffer, len))
49 dma_unmap_single(ring->dev,
50 dma_unmap_addr(tx_buffer, dma),
51 dma_unmap_len(tx_buffer, len),
52 DMA_TO_DEVICE);
53 } else if (dma_unmap_len(tx_buffer, len)) {
54 dma_unmap_page(ring->dev,
55 dma_unmap_addr(tx_buffer, dma),
56 dma_unmap_len(tx_buffer, len),
57 DMA_TO_DEVICE);
58 }
59 tx_buffer->next_to_watch = NULL;
60 tx_buffer->skb = NULL;
61 dma_unmap_len_set(tx_buffer, len, 0);
62 /* tx_buffer must be completely set up in the transmit path */
63}
64
65/**
66 * i40evf_clean_tx_ring - Free any empty Tx buffers
67 * @tx_ring: ring to be cleaned
68 **/
69void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
70{
71 unsigned long bi_size;
72 u16 i;
73
74 /* ring already cleared, nothing to do */
75 if (!tx_ring->tx_bi)
76 return;
77
78 /* Free all the Tx ring sk_buffs */
79 for (i = 0; i < tx_ring->count; i++)
80 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
81
82 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
83 memset(tx_ring->tx_bi, 0, bi_size);
84
85 /* Zero out the descriptor ring */
86 memset(tx_ring->desc, 0, tx_ring->size);
87
88 tx_ring->next_to_use = 0;
89 tx_ring->next_to_clean = 0;
90
91 if (!tx_ring->netdev)
92 return;
93
94 /* cleanup Tx queue statistics */
95 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
96 tx_ring->queue_index));
97}
98
99/**
100 * i40evf_free_tx_resources - Free Tx resources per queue
101 * @tx_ring: Tx descriptor ring for a specific queue
102 *
103 * Free all transmit software resources
104 **/
105void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
106{
107 i40evf_clean_tx_ring(tx_ring);
108 kfree(tx_ring->tx_bi);
109 tx_ring->tx_bi = NULL;
110
111 if (tx_ring->desc) {
112 dma_free_coherent(tx_ring->dev, tx_ring->size,
113 tx_ring->desc, tx_ring->dma);
114 tx_ring->desc = NULL;
115 }
116}
117
118/**
119 * i40e_get_tx_pending - how many tx descriptors not processed
120 * @tx_ring: the ring of descriptors
121 *
122 * Since there is no access to the ring head register
123 * in XL710, we need to use our local copies
124 **/
125static u32 i40e_get_tx_pending(struct i40e_ring *ring)
126{
127 u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
128 ? ring->next_to_use
129 : ring->next_to_use + ring->count);
130 return ntu - ring->next_to_clean;
131}
132
133/**
134 * i40e_check_tx_hang - Is there a hang in the Tx queue
135 * @tx_ring: the ring of descriptors
136 **/
137static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
138{
139 u32 tx_pending = i40e_get_tx_pending(tx_ring);
140 bool ret = false;
141
142 clear_check_for_tx_hang(tx_ring);
143
144 /* Check for a hung queue, but be thorough. This verifies
145 * that a transmit has been completed since the previous
146 * check AND there is at least one packet pending. The
147 * ARMED bit is set to indicate a potential hang. The
148 * bit is cleared if a pause frame is received to remove
149 * false hang detection due to PFC or 802.3x frames. By
150 * requiring this to fail twice we avoid races with
151 * PFC clearing the ARMED bit and conditions where we
152 * run the check_tx_hang logic with a transmit completion
153 * pending but without time to complete it yet.
154 */
155 if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
156 tx_pending) {
157 /* make sure it is true for two checks in a row */
158 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
159 &tx_ring->state);
160 } else {
161 /* update completed stats and disarm the hang check */
162 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
163 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
164 }
165
166 return ret;
167}
168
169/**
170 * i40e_clean_tx_irq - Reclaim resources after transmit completes
171 * @tx_ring: tx ring to clean
172 * @budget: how many cleans we're allowed
173 *
174 * Returns true if there's any budget left (e.g. the clean is finished)
175 **/
176static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
177{
178 u16 i = tx_ring->next_to_clean;
179 struct i40e_tx_buffer *tx_buf;
180 struct i40e_tx_desc *tx_desc;
181 unsigned int total_packets = 0;
182 unsigned int total_bytes = 0;
183
184 tx_buf = &tx_ring->tx_bi[i];
185 tx_desc = I40E_TX_DESC(tx_ring, i);
186 i -= tx_ring->count;
187
188 do {
189 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
190
191 /* if next_to_watch is not set then there is no work pending */
192 if (!eop_desc)
193 break;
194
195 /* prevent any other reads prior to eop_desc */
196 read_barrier_depends();
197
198 /* if the descriptor isn't done, no work yet to do */
199 if (!(eop_desc->cmd_type_offset_bsz &
200 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
201 break;
202
203 /* clear next_to_watch to prevent false hangs */
204 tx_buf->next_to_watch = NULL;
205
206 /* update the statistics for this packet */
207 total_bytes += tx_buf->bytecount;
208 total_packets += tx_buf->gso_segs;
209
210 /* free the skb */
211 dev_kfree_skb_any(tx_buf->skb);
212
213 /* unmap skb header data */
214 dma_unmap_single(tx_ring->dev,
215 dma_unmap_addr(tx_buf, dma),
216 dma_unmap_len(tx_buf, len),
217 DMA_TO_DEVICE);
218
219 /* clear tx_buffer data */
220 tx_buf->skb = NULL;
221 dma_unmap_len_set(tx_buf, len, 0);
222
223 /* unmap remaining buffers */
224 while (tx_desc != eop_desc) {
225
226 tx_buf++;
227 tx_desc++;
228 i++;
229 if (unlikely(!i)) {
230 i -= tx_ring->count;
231 tx_buf = tx_ring->tx_bi;
232 tx_desc = I40E_TX_DESC(tx_ring, 0);
233 }
234
235 /* unmap any remaining paged data */
236 if (dma_unmap_len(tx_buf, len)) {
237 dma_unmap_page(tx_ring->dev,
238 dma_unmap_addr(tx_buf, dma),
239 dma_unmap_len(tx_buf, len),
240 DMA_TO_DEVICE);
241 dma_unmap_len_set(tx_buf, len, 0);
242 }
243 }
244
245 /* move us one more past the eop_desc for start of next pkt */
246 tx_buf++;
247 tx_desc++;
248 i++;
249 if (unlikely(!i)) {
250 i -= tx_ring->count;
251 tx_buf = tx_ring->tx_bi;
252 tx_desc = I40E_TX_DESC(tx_ring, 0);
253 }
254
255 /* update budget accounting */
256 budget--;
257 } while (likely(budget));
258
259 i += tx_ring->count;
260 tx_ring->next_to_clean = i;
261 u64_stats_update_begin(&tx_ring->syncp);
262 tx_ring->stats.bytes += total_bytes;
263 tx_ring->stats.packets += total_packets;
264 u64_stats_update_end(&tx_ring->syncp);
265 tx_ring->q_vector->tx.total_bytes += total_bytes;
266 tx_ring->q_vector->tx.total_packets += total_packets;
267
268 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
269 /* schedule immediate reset if we believe we hung */
270 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
271 " VSI <%d>\n"
272 " Tx Queue <%d>\n"
273 " next_to_use <%x>\n"
274 " next_to_clean <%x>\n",
275 tx_ring->vsi->seid,
276 tx_ring->queue_index,
277 tx_ring->next_to_use, i);
278 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
279 " time_stamp <%lx>\n"
280 " jiffies <%lx>\n",
281 tx_ring->tx_bi[i].time_stamp, jiffies);
282
283 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
284
285 dev_info(tx_ring->dev,
286 "tx hang detected on queue %d, resetting adapter\n",
287 tx_ring->queue_index);
288
289 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
290
291 /* the adapter is about to reset, no point in enabling stuff */
292 return true;
293 }
294
295 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
296 tx_ring->queue_index),
297 total_packets, total_bytes);
298
299#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
300 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
301 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
302 /* Make sure that anybody stopping the queue after this
303 * sees the new next_to_clean.
304 */
305 smp_mb();
306 if (__netif_subqueue_stopped(tx_ring->netdev,
307 tx_ring->queue_index) &&
308 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
309 netif_wake_subqueue(tx_ring->netdev,
310 tx_ring->queue_index);
311 ++tx_ring->tx_stats.restart_queue;
312 }
313 }
314
315 return budget > 0;
316}
317
318/**
319 * i40e_set_new_dynamic_itr - Find new ITR level
320 * @rc: structure containing ring performance data
321 *
322 * Stores a new ITR value based on packets and byte counts during
323 * the last interrupt. The advantage of per interrupt computation
324 * is faster updates and more accurate ITR for the current traffic
325 * pattern. Constants in this function were computed based on
326 * theoretical maximum wire speed and thresholds were set based on
327 * testing data as well as attempting to minimize response time
328 * while increasing bulk throughput.
329 **/
330static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
331{
332 enum i40e_latency_range new_latency_range = rc->latency_range;
333 u32 new_itr = rc->itr;
334 int bytes_per_int;
335
336 if (rc->total_packets == 0 || !rc->itr)
337 return;
338
339 /* simple throttlerate management
340 * 0-10MB/s lowest (100000 ints/s)
341 * 10-20MB/s low (20000 ints/s)
342 * 20-1249MB/s bulk (8000 ints/s)
343 */
344 bytes_per_int = rc->total_bytes / rc->itr;
345 switch (rc->itr) {
346 case I40E_LOWEST_LATENCY:
347 if (bytes_per_int > 10)
348 new_latency_range = I40E_LOW_LATENCY;
349 break;
350 case I40E_LOW_LATENCY:
351 if (bytes_per_int > 20)
352 new_latency_range = I40E_BULK_LATENCY;
353 else if (bytes_per_int <= 10)
354 new_latency_range = I40E_LOWEST_LATENCY;
355 break;
356 case I40E_BULK_LATENCY:
357 if (bytes_per_int <= 20)
358 rc->latency_range = I40E_LOW_LATENCY;
359 break;
360 }
361
362 switch (new_latency_range) {
363 case I40E_LOWEST_LATENCY:
364 new_itr = I40E_ITR_100K;
365 break;
366 case I40E_LOW_LATENCY:
367 new_itr = I40E_ITR_20K;
368 break;
369 case I40E_BULK_LATENCY:
370 new_itr = I40E_ITR_8K;
371 break;
372 default:
373 break;
374 }
375
376 if (new_itr != rc->itr) {
377 /* do an exponential smoothing */
378 new_itr = (10 * new_itr * rc->itr) /
379 ((9 * new_itr) + rc->itr);
380 rc->itr = new_itr & I40E_MAX_ITR;
381 }
382
383 rc->total_bytes = 0;
384 rc->total_packets = 0;
385}
386
387/**
388 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
389 * @q_vector: the vector to adjust
390 **/
391static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
392{
393 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
394 struct i40e_hw *hw = &q_vector->vsi->back->hw;
395 u32 reg_addr;
396 u16 old_itr;
397
398 reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
399 old_itr = q_vector->rx.itr;
400 i40e_set_new_dynamic_itr(&q_vector->rx);
401 if (old_itr != q_vector->rx.itr)
402 wr32(hw, reg_addr, q_vector->rx.itr);
403
404 reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
405 old_itr = q_vector->tx.itr;
406 i40e_set_new_dynamic_itr(&q_vector->tx);
407 if (old_itr != q_vector->tx.itr)
408 wr32(hw, reg_addr, q_vector->tx.itr);
409}
410
411/**
412 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
413 * @tx_ring: the tx ring to set up
414 *
415 * Return 0 on success, negative on error
416 **/
417int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
418{
419 struct device *dev = tx_ring->dev;
420 int bi_size;
421
422 if (!dev)
423 return -ENOMEM;
424
425 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
426 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
427 if (!tx_ring->tx_bi)
428 goto err;
429
430 /* round up to nearest 4K */
431 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
432 tx_ring->size = ALIGN(tx_ring->size, 4096);
433 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
434 &tx_ring->dma, GFP_KERNEL);
435 if (!tx_ring->desc) {
436 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
437 tx_ring->size);
438 goto err;
439 }
440
441 tx_ring->next_to_use = 0;
442 tx_ring->next_to_clean = 0;
443 return 0;
444
445err:
446 kfree(tx_ring->tx_bi);
447 tx_ring->tx_bi = NULL;
448 return -ENOMEM;
449}
450
451/**
452 * i40evf_clean_rx_ring - Free Rx buffers
453 * @rx_ring: ring to be cleaned
454 **/
455void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
456{
457 struct device *dev = rx_ring->dev;
458 struct i40e_rx_buffer *rx_bi;
459 unsigned long bi_size;
460 u16 i;
461
462 /* ring already cleared, nothing to do */
463 if (!rx_ring->rx_bi)
464 return;
465
466 /* Free all the Rx ring sk_buffs */
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_bi = &rx_ring->rx_bi[i];
469 if (rx_bi->dma) {
470 dma_unmap_single(dev,
471 rx_bi->dma,
472 rx_ring->rx_buf_len,
473 DMA_FROM_DEVICE);
474 rx_bi->dma = 0;
475 }
476 if (rx_bi->skb) {
477 dev_kfree_skb(rx_bi->skb);
478 rx_bi->skb = NULL;
479 }
480 if (rx_bi->page) {
481 if (rx_bi->page_dma) {
482 dma_unmap_page(dev,
483 rx_bi->page_dma,
484 PAGE_SIZE / 2,
485 DMA_FROM_DEVICE);
486 rx_bi->page_dma = 0;
487 }
488 __free_page(rx_bi->page);
489 rx_bi->page = NULL;
490 rx_bi->page_offset = 0;
491 }
492 }
493
494 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
495 memset(rx_ring->rx_bi, 0, bi_size);
496
497 /* Zero out the descriptor ring */
498 memset(rx_ring->desc, 0, rx_ring->size);
499
500 rx_ring->next_to_clean = 0;
501 rx_ring->next_to_use = 0;
502}
503
504/**
505 * i40evf_free_rx_resources - Free Rx resources
506 * @rx_ring: ring to clean the resources from
507 *
508 * Free all receive software resources
509 **/
510void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
511{
512 i40evf_clean_rx_ring(rx_ring);
513 kfree(rx_ring->rx_bi);
514 rx_ring->rx_bi = NULL;
515
516 if (rx_ring->desc) {
517 dma_free_coherent(rx_ring->dev, rx_ring->size,
518 rx_ring->desc, rx_ring->dma);
519 rx_ring->desc = NULL;
520 }
521}
522
523/**
524 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
525 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
526 *
527 * Returns 0 on success, negative on failure
528 **/
529int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
530{
531 struct device *dev = rx_ring->dev;
532 int bi_size;
533
534 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
535 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
536 if (!rx_ring->rx_bi)
537 goto err;
538
539 /* Round up to nearest 4K */
540 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
541 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
542 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
543 rx_ring->size = ALIGN(rx_ring->size, 4096);
544 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
545 &rx_ring->dma, GFP_KERNEL);
546
547 if (!rx_ring->desc) {
548 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
549 rx_ring->size);
550 goto err;
551 }
552
553 rx_ring->next_to_clean = 0;
554 rx_ring->next_to_use = 0;
555
556 return 0;
557err:
558 kfree(rx_ring->rx_bi);
559 rx_ring->rx_bi = NULL;
560 return -ENOMEM;
561}
562
563/**
564 * i40e_release_rx_desc - Store the new tail and head values
565 * @rx_ring: ring to bump
566 * @val: new head index
567 **/
568static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
569{
570 rx_ring->next_to_use = val;
571 /* Force memory writes to complete before letting h/w
572 * know there are new descriptors to fetch. (Only
573 * applicable for weak-ordered memory model archs,
574 * such as IA-64).
575 */
576 wmb();
577 writel(val, rx_ring->tail);
578}
579
580/**
581 * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
582 * @rx_ring: ring to place buffers on
583 * @cleaned_count: number of buffers to replace
584 **/
585void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
586{
587 u16 i = rx_ring->next_to_use;
588 union i40e_rx_desc *rx_desc;
589 struct i40e_rx_buffer *bi;
590 struct sk_buff *skb;
591
592 /* do nothing if no valid netdev defined */
593 if (!rx_ring->netdev || !cleaned_count)
594 return;
595
596 while (cleaned_count--) {
597 rx_desc = I40E_RX_DESC(rx_ring, i);
598 bi = &rx_ring->rx_bi[i];
599 skb = bi->skb;
600
601 if (!skb) {
602 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
603 rx_ring->rx_buf_len);
604 if (!skb) {
605 rx_ring->rx_stats.alloc_buff_failed++;
606 goto no_buffers;
607 }
608 /* initialize queue mapping */
609 skb_record_rx_queue(skb, rx_ring->queue_index);
610 bi->skb = skb;
611 }
612
613 if (!bi->dma) {
614 bi->dma = dma_map_single(rx_ring->dev,
615 skb->data,
616 rx_ring->rx_buf_len,
617 DMA_FROM_DEVICE);
618 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
619 rx_ring->rx_stats.alloc_buff_failed++;
620 bi->dma = 0;
621 goto no_buffers;
622 }
623 }
624
625 if (ring_is_ps_enabled(rx_ring)) {
626 if (!bi->page) {
627 bi->page = alloc_page(GFP_ATOMIC);
628 if (!bi->page) {
629 rx_ring->rx_stats.alloc_page_failed++;
630 goto no_buffers;
631 }
632 }
633
634 if (!bi->page_dma) {
635 /* use a half page if we're re-using */
636 bi->page_offset ^= PAGE_SIZE / 2;
637 bi->page_dma = dma_map_page(rx_ring->dev,
638 bi->page,
639 bi->page_offset,
640 PAGE_SIZE / 2,
641 DMA_FROM_DEVICE);
642 if (dma_mapping_error(rx_ring->dev,
643 bi->page_dma)) {
644 rx_ring->rx_stats.alloc_page_failed++;
645 bi->page_dma = 0;
646 goto no_buffers;
647 }
648 }
649
650 /* Refresh the desc even if buffer_addrs didn't change
651 * because each write-back erases this info.
652 */
653 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
654 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
655 } else {
656 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
657 rx_desc->read.hdr_addr = 0;
658 }
659 i++;
660 if (i == rx_ring->count)
661 i = 0;
662 }
663
664no_buffers:
665 if (rx_ring->next_to_use != i)
666 i40e_release_rx_desc(rx_ring, i);
667}
668
669/**
670 * i40e_receive_skb - Send a completed packet up the stack
671 * @rx_ring: rx ring in play
672 * @skb: packet to send up
673 * @vlan_tag: vlan tag for packet
674 **/
675static void i40e_receive_skb(struct i40e_ring *rx_ring,
676 struct sk_buff *skb, u16 vlan_tag)
677{
678 struct i40e_q_vector *q_vector = rx_ring->q_vector;
679 struct i40e_vsi *vsi = rx_ring->vsi;
680 u64 flags = vsi->back->flags;
681
682 if (vlan_tag & VLAN_VID_MASK)
683 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
684
685 if (flags & I40E_FLAG_IN_NETPOLL)
686 netif_rx(skb);
687 else
688 napi_gro_receive(&q_vector->napi, skb);
689}
690
691/**
692 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
693 * @vsi: the VSI we care about
694 * @skb: skb currently being received and modified
695 * @rx_status: status value of last descriptor in packet
696 * @rx_error: error value of last descriptor in packet
697 * @rx_ptype: ptype value of last descriptor in packet
698 **/
699static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
700 struct sk_buff *skb,
701 u32 rx_status,
702 u32 rx_error,
703 u16 rx_ptype)
704{
705 bool ipv4_tunnel, ipv6_tunnel;
706 __wsum rx_udp_csum;
707 __sum16 csum;
708 struct iphdr *iph;
709
710 ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
711 (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
712 ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
713 (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
714
715 skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
716 skb->ip_summed = CHECKSUM_NONE;
717
718 /* Rx csum enabled and ip headers found? */
719 if (!(vsi->netdev->features & NETIF_F_RXCSUM &&
720 rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
721 return;
722
723 /* likely incorrect csum if alternate IP extention headers found */
724 if (rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
725 return;
726
727 /* IP or L4 or outmost IP checksum error */
728 if (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
729 (1 << I40E_RX_DESC_ERROR_L4E_SHIFT) |
730 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))) {
731 vsi->back->hw_csum_rx_error++;
732 return;
733 }
734
735 if (ipv4_tunnel &&
736 !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
737 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
738 * it in the driver, hardware does not do it for us.
739 * Since L3L4P bit was set we assume a valid IHL value (>=5)
740 * so the total length of IPv4 header is IHL*4 bytes
741 */
742 skb->transport_header = skb->mac_header +
743 sizeof(struct ethhdr) +
744 (ip_hdr(skb)->ihl * 4);
745
746 /* Add 4 bytes for VLAN tagged packets */
747 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
748 skb->protocol == htons(ETH_P_8021AD))
749 ? VLAN_HLEN : 0;
750
751 rx_udp_csum = udp_csum(skb);
752 iph = ip_hdr(skb);
753 csum = csum_tcpudp_magic(
754 iph->saddr, iph->daddr,
755 (skb->len - skb_transport_offset(skb)),
756 IPPROTO_UDP, rx_udp_csum);
757
758 if (udp_hdr(skb)->check != csum) {
759 vsi->back->hw_csum_rx_error++;
760 return;
761 }
762 }
763
764 skb->ip_summed = CHECKSUM_UNNECESSARY;
765}
766
767/**
768 * i40e_rx_hash - returns the hash value from the Rx descriptor
769 * @ring: descriptor ring
770 * @rx_desc: specific descriptor
771 **/
772static inline u32 i40e_rx_hash(struct i40e_ring *ring,
773 union i40e_rx_desc *rx_desc)
774{
775 const __le64 rss_mask =
776 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
777 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
778
779 if ((ring->netdev->features & NETIF_F_RXHASH) &&
780 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
781 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
782 else
783 return 0;
784}
785
786/**
787 * i40e_clean_rx_irq - Reclaim resources after receive completes
788 * @rx_ring: rx ring to clean
789 * @budget: how many cleans we're allowed
790 *
791 * Returns true if there's any budget left (e.g. the clean is finished)
792 **/
793static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
794{
795 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
796 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
797 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
798 const int current_node = numa_node_id();
799 struct i40e_vsi *vsi = rx_ring->vsi;
800 u16 i = rx_ring->next_to_clean;
801 union i40e_rx_desc *rx_desc;
802 u32 rx_error, rx_status;
803 u64 qword;
804 u16 rx_ptype;
805
806 rx_desc = I40E_RX_DESC(rx_ring, i);
807 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
808 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK)
809 >> I40E_RXD_QW1_STATUS_SHIFT;
810
811 while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
812 union i40e_rx_desc *next_rxd;
813 struct i40e_rx_buffer *rx_bi;
814 struct sk_buff *skb;
815 u16 vlan_tag;
816 rx_bi = &rx_ring->rx_bi[i];
817 skb = rx_bi->skb;
818 prefetch(skb->data);
819
820 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
821 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
822 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
823 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
824 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
825 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
826
827 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
828 I40E_RXD_QW1_ERROR_SHIFT;
829 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
830 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
831
832 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
833 I40E_RXD_QW1_PTYPE_SHIFT;
834 rx_bi->skb = NULL;
835
836 /* This memory barrier is needed to keep us from reading
837 * any other fields out of the rx_desc until we know the
838 * STATUS_DD bit is set
839 */
840 rmb();
841
842 /* Get the header and possibly the whole packet
843 * If this is an skb from previous receive dma will be 0
844 */
845 if (rx_bi->dma) {
846 u16 len;
847
848 if (rx_hbo)
849 len = I40E_RX_HDR_SIZE;
850 else if (rx_sph)
851 len = rx_header_len;
852 else if (rx_packet_len)
853 len = rx_packet_len; /* 1buf/no split found */
854 else
855 len = rx_header_len; /* split always mode */
856
857 skb_put(skb, len);
858 dma_unmap_single(rx_ring->dev,
859 rx_bi->dma,
860 rx_ring->rx_buf_len,
861 DMA_FROM_DEVICE);
862 rx_bi->dma = 0;
863 }
864
865 /* Get the rest of the data if this was a header split */
866 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
867
868 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
869 rx_bi->page,
870 rx_bi->page_offset,
871 rx_packet_len);
872
873 skb->len += rx_packet_len;
874 skb->data_len += rx_packet_len;
875 skb->truesize += rx_packet_len;
876
877 if ((page_count(rx_bi->page) == 1) &&
878 (page_to_nid(rx_bi->page) == current_node))
879 get_page(rx_bi->page);
880 else
881 rx_bi->page = NULL;
882
883 dma_unmap_page(rx_ring->dev,
884 rx_bi->page_dma,
885 PAGE_SIZE / 2,
886 DMA_FROM_DEVICE);
887 rx_bi->page_dma = 0;
888 }
889 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
890
891 if (unlikely(
892 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
893 struct i40e_rx_buffer *next_buffer;
894
895 next_buffer = &rx_ring->rx_bi[i];
896
897 if (ring_is_ps_enabled(rx_ring)) {
898 rx_bi->skb = next_buffer->skb;
899 rx_bi->dma = next_buffer->dma;
900 next_buffer->skb = skb;
901 next_buffer->dma = 0;
902 }
903 rx_ring->rx_stats.non_eop_descs++;
904 goto next_desc;
905 }
906
907 /* ERR_MASK will only have valid bits if EOP set */
908 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
909 dev_kfree_skb_any(skb);
910 goto next_desc;
911 }
912
913 skb->rxhash = i40e_rx_hash(rx_ring, rx_desc);
914 /* probably a little skewed due to removing CRC */
915 total_rx_bytes += skb->len;
916 total_rx_packets++;
917
918 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
919
920 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
921
922 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
923 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
924 : 0;
925 i40e_receive_skb(rx_ring, skb, vlan_tag);
926
927 rx_ring->netdev->last_rx = jiffies;
928 budget--;
929next_desc:
930 rx_desc->wb.qword1.status_error_len = 0;
931 if (!budget)
932 break;
933
934 cleaned_count++;
935 /* return some buffers to hardware, one at a time is too slow */
936 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
937 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
938 cleaned_count = 0;
939 }
940
941 /* use prefetched values */
942 rx_desc = next_rxd;
943 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
944 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
945 I40E_RXD_QW1_STATUS_SHIFT;
946 }
947
948 rx_ring->next_to_clean = i;
949 u64_stats_update_begin(&rx_ring->syncp);
950 rx_ring->stats.packets += total_rx_packets;
951 rx_ring->stats.bytes += total_rx_bytes;
952 u64_stats_update_end(&rx_ring->syncp);
953 rx_ring->q_vector->rx.total_packets += total_rx_packets;
954 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
955
956 if (cleaned_count)
957 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
958
959 return budget > 0;
960}
961
962/**
963 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
964 * @napi: napi struct with our devices info in it
965 * @budget: amount of work driver is allowed to do this pass, in packets
966 *
967 * This function will clean all queues associated with a q_vector.
968 *
969 * Returns the amount of work done
970 **/
971int i40evf_napi_poll(struct napi_struct *napi, int budget)
972{
973 struct i40e_q_vector *q_vector =
974 container_of(napi, struct i40e_q_vector, napi);
975 struct i40e_vsi *vsi = q_vector->vsi;
976 struct i40e_ring *ring;
977 bool clean_complete = true;
978 int budget_per_ring;
979
980 if (test_bit(__I40E_DOWN, &vsi->state)) {
981 napi_complete(napi);
982 return 0;
983 }
984
985 /* Since the actual Tx work is minimal, we can give the Tx a larger
986 * budget and be more aggressive about cleaning up the Tx descriptors.
987 */
988 i40e_for_each_ring(ring, q_vector->tx)
989 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
990
991 /* We attempt to distribute budget to each Rx queue fairly, but don't
992 * allow the budget to go below 1 because that would exit polling early.
993 */
994 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
995
996 i40e_for_each_ring(ring, q_vector->rx)
997 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
998
999 /* If work not completed, return budget and polling will return */
1000 if (!clean_complete)
1001 return budget;
1002
1003 /* Work is done so exit the polling mode and re-enable the interrupt */
1004 napi_complete(napi);
1005 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1006 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1007 i40e_update_dynamic_itr(q_vector);
1008
1009 if (!test_bit(__I40E_DOWN, &vsi->state))
1010 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1011
1012 return 0;
1013}
1014
1015/**
1016 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1017 * @skb: send buffer
1018 * @tx_ring: ring to send buffer on
1019 * @flags: the tx flags to be set
1020 *
1021 * Checks the skb and set up correspondingly several generic transmit flags
1022 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1023 *
1024 * Returns error code indicate the frame should be dropped upon error and the
1025 * otherwise returns 0 to indicate the flags has been set properly.
1026 **/
1027static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1028 struct i40e_ring *tx_ring,
1029 u32 *flags)
1030{
1031 __be16 protocol = skb->protocol;
1032 u32 tx_flags = 0;
1033
1034 /* if we have a HW VLAN tag being added, default to the HW one */
1035 if (vlan_tx_tag_present(skb)) {
1036 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1037 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1038 /* else if it is a SW VLAN, check the next protocol and store the tag */
1039 } else if (protocol == htons(ETH_P_8021Q)) {
1040 struct vlan_hdr *vhdr, _vhdr;
1041 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1042 if (!vhdr)
1043 return -EINVAL;
1044
1045 protocol = vhdr->h_vlan_encapsulated_proto;
1046 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1047 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1048 }
1049
1050 *flags = tx_flags;
1051 return 0;
1052}
1053
1054/**
1055 * i40e_tso - set up the tso context descriptor
1056 * @tx_ring: ptr to the ring to send
1057 * @skb: ptr to the skb we're sending
1058 * @tx_flags: the collected send information
1059 * @protocol: the send protocol
1060 * @hdr_len: ptr to the size of the packet header
1061 * @cd_tunneling: ptr to context descriptor bits
1062 *
1063 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1064 **/
1065static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1066 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1067 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1068{
1069 u32 cd_cmd, cd_tso_len, cd_mss;
1070 struct tcphdr *tcph;
1071 struct iphdr *iph;
1072 u32 l4len;
1073 int err;
1074 struct ipv6hdr *ipv6h;
1075
1076 if (!skb_is_gso(skb))
1077 return 0;
1078
1079 if (skb_header_cloned(skb)) {
1080 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1081 if (err)
1082 return err;
1083 }
1084
1085 if (protocol == htons(ETH_P_IP)) {
1086 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1087 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1088 iph->tot_len = 0;
1089 iph->check = 0;
1090 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1091 0, IPPROTO_TCP, 0);
1092 } else if (skb_is_gso_v6(skb)) {
1093
1094 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1095 : ipv6_hdr(skb);
1096 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1097 ipv6h->payload_len = 0;
1098 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1099 0, IPPROTO_TCP, 0);
1100 }
1101
1102 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1103 *hdr_len = (skb->encapsulation
1104 ? (skb_inner_transport_header(skb) - skb->data)
1105 : skb_transport_offset(skb)) + l4len;
1106
1107 /* find the field values */
1108 cd_cmd = I40E_TX_CTX_DESC_TSO;
1109 cd_tso_len = skb->len - *hdr_len;
1110 cd_mss = skb_shinfo(skb)->gso_size;
1111 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1112 ((u64)cd_tso_len <<
1113 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1114 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1115 return 1;
1116}
1117
1118/**
1119 * i40e_tx_enable_csum - Enable Tx checksum offloads
1120 * @skb: send buffer
1121 * @tx_flags: Tx flags currently set
1122 * @td_cmd: Tx descriptor command bits to set
1123 * @td_offset: Tx descriptor header offsets to set
1124 * @cd_tunneling: ptr to context desc bits
1125 **/
1126static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1127 u32 *td_cmd, u32 *td_offset,
1128 struct i40e_ring *tx_ring,
1129 u32 *cd_tunneling)
1130{
1131 struct ipv6hdr *this_ipv6_hdr;
1132 unsigned int this_tcp_hdrlen;
1133 struct iphdr *this_ip_hdr;
1134 u32 network_hdr_len;
1135 u8 l4_hdr = 0;
1136
1137 if (skb->encapsulation) {
1138 network_hdr_len = skb_inner_network_header_len(skb);
1139 this_ip_hdr = inner_ip_hdr(skb);
1140 this_ipv6_hdr = inner_ipv6_hdr(skb);
1141 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1142
1143 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1144
1145 if (tx_flags & I40E_TX_FLAGS_TSO) {
1146 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1147 ip_hdr(skb)->check = 0;
1148 } else {
1149 *cd_tunneling |=
1150 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1151 }
1152 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1153 if (tx_flags & I40E_TX_FLAGS_TSO) {
1154 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1155 ip_hdr(skb)->check = 0;
1156 } else {
1157 *cd_tunneling |=
1158 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1159 }
1160 }
1161
1162 /* Now set the ctx descriptor fields */
1163 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1164 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1165 I40E_TXD_CTX_UDP_TUNNELING |
1166 ((skb_inner_network_offset(skb) -
1167 skb_transport_offset(skb)) >> 1) <<
1168 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1169
1170 } else {
1171 network_hdr_len = skb_network_header_len(skb);
1172 this_ip_hdr = ip_hdr(skb);
1173 this_ipv6_hdr = ipv6_hdr(skb);
1174 this_tcp_hdrlen = tcp_hdrlen(skb);
1175 }
1176
1177 /* Enable IP checksum offloads */
1178 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1179 l4_hdr = this_ip_hdr->protocol;
1180 /* the stack computes the IP header already, the only time we
1181 * need the hardware to recompute it is in the case of TSO.
1182 */
1183 if (tx_flags & I40E_TX_FLAGS_TSO) {
1184 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1185 this_ip_hdr->check = 0;
1186 } else {
1187 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1188 }
1189 /* Now set the td_offset for IP header length */
1190 *td_offset = (network_hdr_len >> 2) <<
1191 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1192 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1193 l4_hdr = this_ipv6_hdr->nexthdr;
1194 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1195 /* Now set the td_offset for IP header length */
1196 *td_offset = (network_hdr_len >> 2) <<
1197 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1198 }
1199 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1200 *td_offset |= (skb_network_offset(skb) >> 1) <<
1201 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1202
1203 /* Enable L4 checksum offloads */
1204 switch (l4_hdr) {
1205 case IPPROTO_TCP:
1206 /* enable checksum offloads */
1207 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1208 *td_offset |= (this_tcp_hdrlen >> 2) <<
1209 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1210 break;
1211 case IPPROTO_SCTP:
1212 /* enable SCTP checksum offload */
1213 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1214 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1215 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1216 break;
1217 case IPPROTO_UDP:
1218 /* enable UDP checksum offload */
1219 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1220 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1221 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1222 break;
1223 default:
1224 break;
1225 }
1226}
1227
1228/**
1229 * i40e_create_tx_ctx Build the Tx context descriptor
1230 * @tx_ring: ring to create the descriptor on
1231 * @cd_type_cmd_tso_mss: Quad Word 1
1232 * @cd_tunneling: Quad Word 0 - bits 0-31
1233 * @cd_l2tag2: Quad Word 0 - bits 32-63
1234 **/
1235static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1236 const u64 cd_type_cmd_tso_mss,
1237 const u32 cd_tunneling, const u32 cd_l2tag2)
1238{
1239 struct i40e_tx_context_desc *context_desc;
1240 int i = tx_ring->next_to_use;
1241
1242 if (!cd_type_cmd_tso_mss && !cd_tunneling && !cd_l2tag2)
1243 return;
1244
1245 /* grab the next descriptor */
1246 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1247
1248 i++;
1249 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1250
1251 /* cpu_to_le32 and assign to struct fields */
1252 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1253 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1254 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1255}
1256
1257/**
1258 * i40e_tx_map - Build the Tx descriptor
1259 * @tx_ring: ring to send buffer on
1260 * @skb: send buffer
1261 * @first: first buffer info buffer to use
1262 * @tx_flags: collected send information
1263 * @hdr_len: size of the packet header
1264 * @td_cmd: the command field in the descriptor
1265 * @td_offset: offset for checksum or crc
1266 **/
1267static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1268 struct i40e_tx_buffer *first, u32 tx_flags,
1269 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1270{
1271 unsigned int data_len = skb->data_len;
1272 unsigned int size = skb_headlen(skb);
1273 struct skb_frag_struct *frag;
1274 struct i40e_tx_buffer *tx_bi;
1275 struct i40e_tx_desc *tx_desc;
1276 u16 i = tx_ring->next_to_use;
1277 u32 td_tag = 0;
1278 dma_addr_t dma;
1279 u16 gso_segs;
1280
1281 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1282 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1283 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1284 I40E_TX_FLAGS_VLAN_SHIFT;
1285 }
1286
1287 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1288 gso_segs = skb_shinfo(skb)->gso_segs;
1289 else
1290 gso_segs = 1;
1291
1292 /* multiply data chunks by size of headers */
1293 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1294 first->gso_segs = gso_segs;
1295 first->skb = skb;
1296 first->tx_flags = tx_flags;
1297
1298 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1299
1300 tx_desc = I40E_TX_DESC(tx_ring, i);
1301 tx_bi = first;
1302
1303 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1304 if (dma_mapping_error(tx_ring->dev, dma))
1305 goto dma_error;
1306
1307 /* record length, and DMA address */
1308 dma_unmap_len_set(tx_bi, len, size);
1309 dma_unmap_addr_set(tx_bi, dma, dma);
1310
1311 tx_desc->buffer_addr = cpu_to_le64(dma);
1312
1313 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1314 tx_desc->cmd_type_offset_bsz =
1315 build_ctob(td_cmd, td_offset,
1316 I40E_MAX_DATA_PER_TXD, td_tag);
1317
1318 tx_desc++;
1319 i++;
1320 if (i == tx_ring->count) {
1321 tx_desc = I40E_TX_DESC(tx_ring, 0);
1322 i = 0;
1323 }
1324
1325 dma += I40E_MAX_DATA_PER_TXD;
1326 size -= I40E_MAX_DATA_PER_TXD;
1327
1328 tx_desc->buffer_addr = cpu_to_le64(dma);
1329 }
1330
1331 if (likely(!data_len))
1332 break;
1333
1334 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1335 size, td_tag);
1336
1337 tx_desc++;
1338 i++;
1339 if (i == tx_ring->count) {
1340 tx_desc = I40E_TX_DESC(tx_ring, 0);
1341 i = 0;
1342 }
1343
1344 size = skb_frag_size(frag);
1345 data_len -= size;
1346
1347 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1348 DMA_TO_DEVICE);
1349
1350 tx_bi = &tx_ring->tx_bi[i];
1351 }
1352
1353 tx_desc->cmd_type_offset_bsz =
1354 build_ctob(td_cmd, td_offset, size, td_tag) |
1355 cpu_to_le64((u64)I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT);
1356
1357 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1358 tx_ring->queue_index),
1359 first->bytecount);
1360
1361 /* set the timestamp */
1362 first->time_stamp = jiffies;
1363
1364 /* Force memory writes to complete before letting h/w
1365 * know there are new descriptors to fetch. (Only
1366 * applicable for weak-ordered memory model archs,
1367 * such as IA-64).
1368 */
1369 wmb();
1370
1371 /* set next_to_watch value indicating a packet is present */
1372 first->next_to_watch = tx_desc;
1373
1374 i++;
1375 if (i == tx_ring->count)
1376 i = 0;
1377
1378 tx_ring->next_to_use = i;
1379
1380 /* notify HW of packet */
1381 writel(i, tx_ring->tail);
1382
1383 return;
1384
1385dma_error:
1386 dev_info(tx_ring->dev, "TX DMA map failed\n");
1387
1388 /* clear dma mappings for failed tx_bi map */
1389 for (;;) {
1390 tx_bi = &tx_ring->tx_bi[i];
1391 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1392 if (tx_bi == first)
1393 break;
1394 if (i == 0)
1395 i = tx_ring->count;
1396 i--;
1397 }
1398
1399 tx_ring->next_to_use = i;
1400}
1401
1402/**
1403 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1404 * @tx_ring: the ring to be checked
1405 * @size: the size buffer we want to assure is available
1406 *
1407 * Returns -EBUSY if a stop is needed, else 0
1408 **/
1409static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1410{
1411 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1412 /* Memory barrier before checking head and tail */
1413 smp_mb();
1414
1415 /* Check again in a case another CPU has just made room available. */
1416 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1417 return -EBUSY;
1418
1419 /* A reprieve! - use start_queue because it doesn't call schedule */
1420 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1421 ++tx_ring->tx_stats.restart_queue;
1422 return 0;
1423}
1424
1425/**
1426 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1427 * @tx_ring: the ring to be checked
1428 * @size: the size buffer we want to assure is available
1429 *
1430 * Returns 0 if stop is not needed
1431 **/
1432static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1433{
1434 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1435 return 0;
1436 return __i40e_maybe_stop_tx(tx_ring, size);
1437}
1438
1439/**
1440 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1441 * @skb: send buffer
1442 * @tx_ring: ring to send buffer on
1443 *
1444 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1445 * there is not enough descriptors available in this ring since we need at least
1446 * one descriptor.
1447 **/
1448static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1449 struct i40e_ring *tx_ring)
1450{
1451#if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1452 unsigned int f;
1453#endif
1454 int count = 0;
1455
1456 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1457 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1458 * + 2 desc gap to keep tail from touching head,
1459 * + 1 desc for context descriptor,
1460 * otherwise try next time
1461 */
1462#if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1463 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1464 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1465#else
1466 count += skb_shinfo(skb)->nr_frags;
1467#endif
1468 count += TXD_USE_COUNT(skb_headlen(skb));
1469 if (i40e_maybe_stop_tx(tx_ring, count + 3)) {
1470 tx_ring->tx_stats.tx_busy++;
1471 return 0;
1472 }
1473 return count;
1474}
1475
1476/**
1477 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1478 * @skb: send buffer
1479 * @tx_ring: ring to send buffer on
1480 *
1481 * Returns NETDEV_TX_OK if sent, else an error code
1482 **/
1483static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1484 struct i40e_ring *tx_ring)
1485{
1486 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1487 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1488 struct i40e_tx_buffer *first;
1489 u32 td_offset = 0;
1490 u32 tx_flags = 0;
1491 __be16 protocol;
1492 u32 td_cmd = 0;
1493 u8 hdr_len = 0;
1494 int tso;
1495 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1496 return NETDEV_TX_BUSY;
1497
1498 /* prepare the xmit flags */
1499 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1500 goto out_drop;
1501
1502 /* obtain protocol of skb */
1503 protocol = skb->protocol;
1504
1505 /* record the location of the first descriptor for this packet */
1506 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1507
1508 /* setup IPv4/IPv6 offloads */
1509 if (protocol == htons(ETH_P_IP))
1510 tx_flags |= I40E_TX_FLAGS_IPV4;
1511 else if (protocol == htons(ETH_P_IPV6))
1512 tx_flags |= I40E_TX_FLAGS_IPV6;
1513
1514 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1515 &cd_type_cmd_tso_mss, &cd_tunneling);
1516
1517 if (tso < 0)
1518 goto out_drop;
1519 else if (tso)
1520 tx_flags |= I40E_TX_FLAGS_TSO;
1521
1522 skb_tx_timestamp(skb);
1523
1524 /* always enable CRC insertion offload */
1525 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1526
1527 /* Always offload the checksum, since it's in the data descriptor */
1528 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1529 tx_flags |= I40E_TX_FLAGS_CSUM;
1530
1531 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1532 tx_ring, &cd_tunneling);
1533 }
1534
1535 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1536 cd_tunneling, cd_l2tag2);
1537
1538 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1539 td_cmd, td_offset);
1540
1541 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1542
1543 return NETDEV_TX_OK;
1544
1545out_drop:
1546 dev_kfree_skb_any(skb);
1547 return NETDEV_TX_OK;
1548}
1549
1550/**
1551 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1552 * @skb: send buffer
1553 * @netdev: network interface device structure
1554 *
1555 * Returns NETDEV_TX_OK if sent, else an error code
1556 **/
1557netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1558{
1559 struct i40evf_adapter *adapter = netdev_priv(netdev);
1560 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1561
1562 /* hardware can't handle really short frames, hardware padding works
1563 * beyond this point
1564 */
1565 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1566 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1567 return NETDEV_TX_OK;
1568 skb->len = I40E_MIN_TX_LEN;
1569 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1570 }
1571
1572 return i40e_xmit_frame_ring(skb, tx_ring);
1573}
Linux 6.x block layer and io_uring tree(s)