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rocker: sparse: fix dynamic allocation on stack warning
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
CommitLineData
7f12ad74
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
af1a2a9c 4 * Copyright(c) 2013 - 2014 Intel Corporation.
7f12ad74
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
7f12ad74
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
7ed3f5f0 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
7ed3f5f0 29
7f12ad74 30#include "i40evf.h"
206812b5 31#include "i40e_prototype.h"
7f12ad74
GR		 32
33static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35{
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41}
42
43#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45/**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52{
53 if (tx_buffer->skb) {
49d7d933
ASJ		 54 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
55 kfree(tx_buffer->raw_buf);
56 else
57 dev_kfree_skb_any(tx_buffer->skb);
58
7f12ad74
GR		 59 if (dma_unmap_len(tx_buffer, len))
60 dma_unmap_single(ring->dev,
61 dma_unmap_addr(tx_buffer, dma),
62 dma_unmap_len(tx_buffer, len),
63 DMA_TO_DEVICE);
64 } else if (dma_unmap_len(tx_buffer, len)) {
65 dma_unmap_page(ring->dev,
66 dma_unmap_addr(tx_buffer, dma),
67 dma_unmap_len(tx_buffer, len),
68 DMA_TO_DEVICE);
69 }
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74}
75
76/**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81{
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
108}
109
110/**
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
113 *
114 * Free all transmit software resources
115 **/
116void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117{
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
121
122 if (tx_ring->desc) {
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
126 }
127}
128
a68de58d
JB		 129/**
130 * i40e_get_head - Retrieve head from head writeback
131 * @tx_ring: tx ring to fetch head of
132 *
133 * Returns value of Tx ring head based on value stored
134 * in head write-back location
135 **/
136static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
137{
138 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
139
140 return le32_to_cpu(*(volatile __le32 *)head);
141}
142
7f12ad74
GR		 143/**
144 * i40e_get_tx_pending - how many tx descriptors not processed
145 * @tx_ring: the ring of descriptors
146 *
147 * Since there is no access to the ring head register
148 * in XL710, we need to use our local copies
149 **/
150static u32 i40e_get_tx_pending(struct i40e_ring *ring)
151{
a68de58d
JB		 152 u32 head, tail;
153
154 head = i40e_get_head(ring);
155 tail = readl(ring->tail);
156
157 if (head != tail)
158 return (head < tail) ?
159 tail - head : (tail + ring->count - head);
160
161 return 0;
7f12ad74
GR		 162}
163
164/**
165 * i40e_check_tx_hang - Is there a hang in the Tx queue
166 * @tx_ring: the ring of descriptors
167 **/
168static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
169{
a68de58d
JB		 170 u32 tx_done = tx_ring->stats.packets;
171 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
7f12ad74
GR		 172 u32 tx_pending = i40e_get_tx_pending(tx_ring);
173 bool ret = false;
174
175 clear_check_for_tx_hang(tx_ring);
176
177 /* Check for a hung queue, but be thorough. This verifies
178 * that a transmit has been completed since the previous
179 * check AND there is at least one packet pending. The
180 * ARMED bit is set to indicate a potential hang. The
181 * bit is cleared if a pause frame is received to remove
182 * false hang detection due to PFC or 802.3x frames. By
183 * requiring this to fail twice we avoid races with
184 * PFC clearing the ARMED bit and conditions where we
185 * run the check_tx_hang logic with a transmit completion
186 * pending but without time to complete it yet.
187 */
a68de58d 188 if ((tx_done_old == tx_done) && tx_pending) {
7f12ad74
GR		 189 /* make sure it is true for two checks in a row */
190 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
191 &tx_ring->state);
a68de58d
JB		 192 } else if (tx_done_old == tx_done &&
193 (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
7f12ad74 194 /* update completed stats and disarm the hang check */
a68de58d 195 tx_ring->tx_stats.tx_done_old = tx_done;
7f12ad74
GR		 196 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
197 }
198
199 return ret;
200}
201
c29af37f
ASJ		 202#define WB_STRIDE 0x3
203
7f12ad74
GR		 204/**
205 * i40e_clean_tx_irq - Reclaim resources after transmit completes
206 * @tx_ring: tx ring to clean
207 * @budget: how many cleans we're allowed
208 *
209 * Returns true if there's any budget left (e.g. the clean is finished)
210 **/
211static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
212{
213 u16 i = tx_ring->next_to_clean;
214 struct i40e_tx_buffer *tx_buf;
1943d8ba 215 struct i40e_tx_desc *tx_head;
7f12ad74
GR		 216 struct i40e_tx_desc *tx_desc;
217 unsigned int total_packets = 0;
218 unsigned int total_bytes = 0;
219
220 tx_buf = &tx_ring->tx_bi[i];
221 tx_desc = I40E_TX_DESC(tx_ring, i);
222 i -= tx_ring->count;
223
1943d8ba
JB		 224 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
225
7f12ad74
GR		 226 do {
227 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
228
229 /* if next_to_watch is not set then there is no work pending */
230 if (!eop_desc)
231 break;
232
233 /* prevent any other reads prior to eop_desc */
234 read_barrier_depends();
235
1943d8ba
JB		 236 /* we have caught up to head, no work left to do */
237 if (tx_head == tx_desc)
7f12ad74
GR		 238 break;
239
240 /* clear next_to_watch to prevent false hangs */
241 tx_buf->next_to_watch = NULL;
242
243 /* update the statistics for this packet */
244 total_bytes += tx_buf->bytecount;
245 total_packets += tx_buf->gso_segs;
246
247 /* free the skb */
248 dev_kfree_skb_any(tx_buf->skb);
249
250 /* unmap skb header data */
251 dma_unmap_single(tx_ring->dev,
252 dma_unmap_addr(tx_buf, dma),
253 dma_unmap_len(tx_buf, len),
254 DMA_TO_DEVICE);
255
256 /* clear tx_buffer data */
257 tx_buf->skb = NULL;
258 dma_unmap_len_set(tx_buf, len, 0);
259
260 /* unmap remaining buffers */
261 while (tx_desc != eop_desc) {
262
263 tx_buf++;
264 tx_desc++;
265 i++;
266 if (unlikely(!i)) {
267 i -= tx_ring->count;
268 tx_buf = tx_ring->tx_bi;
269 tx_desc = I40E_TX_DESC(tx_ring, 0);
270 }
271
272 /* unmap any remaining paged data */
273 if (dma_unmap_len(tx_buf, len)) {
274 dma_unmap_page(tx_ring->dev,
275 dma_unmap_addr(tx_buf, dma),
276 dma_unmap_len(tx_buf, len),
277 DMA_TO_DEVICE);
278 dma_unmap_len_set(tx_buf, len, 0);
279 }
280 }
281
282 /* move us one more past the eop_desc for start of next pkt */
283 tx_buf++;
284 tx_desc++;
285 i++;
286 if (unlikely(!i)) {
287 i -= tx_ring->count;
288 tx_buf = tx_ring->tx_bi;
289 tx_desc = I40E_TX_DESC(tx_ring, 0);
290 }
291
292 /* update budget accounting */
293 budget--;
294 } while (likely(budget));
295
296 i += tx_ring->count;
297 tx_ring->next_to_clean = i;
298 u64_stats_update_begin(&tx_ring->syncp);
299 tx_ring->stats.bytes += total_bytes;
300 tx_ring->stats.packets += total_packets;
301 u64_stats_update_end(&tx_ring->syncp);
302 tx_ring->q_vector->tx.total_bytes += total_bytes;
303 tx_ring->q_vector->tx.total_packets += total_packets;
304
c29af37f
ASJ		 305 if (budget &&
306 !((i & WB_STRIDE) == WB_STRIDE) &&
307 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
308 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
309 tx_ring->arm_wb = true;
310 else
311 tx_ring->arm_wb = false;
312
7f12ad74
GR		 313 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
314 /* schedule immediate reset if we believe we hung */
315 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
316 " VSI <%d>\n"
317 " Tx Queue <%d>\n"
318 " next_to_use <%x>\n"
319 " next_to_clean <%x>\n",
320 tx_ring->vsi->seid,
321 tx_ring->queue_index,
322 tx_ring->next_to_use, i);
323 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
324 " time_stamp <%lx>\n"
325 " jiffies <%lx>\n",
326 tx_ring->tx_bi[i].time_stamp, jiffies);
327
328 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
329
330 dev_info(tx_ring->dev,
331 "tx hang detected on queue %d, resetting adapter\n",
332 tx_ring->queue_index);
333
334 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
335
336 /* the adapter is about to reset, no point in enabling stuff */
337 return true;
338 }
339
340 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
341 tx_ring->queue_index),
342 total_packets, total_bytes);
343
344#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
345 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
346 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
347 /* Make sure that anybody stopping the queue after this
348 * sees the new next_to_clean.
349 */
350 smp_mb();
351 if (__netif_subqueue_stopped(tx_ring->netdev,
352 tx_ring->queue_index) &&
353 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
354 netif_wake_subqueue(tx_ring->netdev,
355 tx_ring->queue_index);
356 ++tx_ring->tx_stats.restart_queue;
357 }
358 }
359
360 return budget > 0;
361}
362
c29af37f
ASJ		 363/**
364 * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
365 * @vsi: the VSI we care about
366 * @q_vector: the vector on which to force writeback
367 *
368 **/
369static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
370{
371 u32 val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
372 I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
373 I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
374 /* allow 00 to be written to the index */
375
376 wr32(&vsi->back->hw,
377 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
378 val);
379}
380
7f12ad74
GR		 381/**
382 * i40e_set_new_dynamic_itr - Find new ITR level
383 * @rc: structure containing ring performance data
384 *
385 * Stores a new ITR value based on packets and byte counts during
386 * the last interrupt. The advantage of per interrupt computation
387 * is faster updates and more accurate ITR for the current traffic
388 * pattern. Constants in this function were computed based on
389 * theoretical maximum wire speed and thresholds were set based on
390 * testing data as well as attempting to minimize response time
391 * while increasing bulk throughput.
392 **/
393static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
394{
395 enum i40e_latency_range new_latency_range = rc->latency_range;
396 u32 new_itr = rc->itr;
397 int bytes_per_int;
398
399 if (rc->total_packets == 0 || !rc->itr)
400 return;
401
402 /* simple throttlerate management
403 * 0-10MB/s lowest (100000 ints/s)
404 * 10-20MB/s low (20000 ints/s)
405 * 20-1249MB/s bulk (8000 ints/s)
406 */
407 bytes_per_int = rc->total_bytes / rc->itr;
408 switch (rc->itr) {
409 case I40E_LOWEST_LATENCY:
410 if (bytes_per_int > 10)
411 new_latency_range = I40E_LOW_LATENCY;
412 break;
413 case I40E_LOW_LATENCY:
414 if (bytes_per_int > 20)
415 new_latency_range = I40E_BULK_LATENCY;
416 else if (bytes_per_int <= 10)
417 new_latency_range = I40E_LOWEST_LATENCY;
418 break;
419 case I40E_BULK_LATENCY:
420 if (bytes_per_int <= 20)
421 rc->latency_range = I40E_LOW_LATENCY;
422 break;
423 }
424
425 switch (new_latency_range) {
426 case I40E_LOWEST_LATENCY:
427 new_itr = I40E_ITR_100K;
428 break;
429 case I40E_LOW_LATENCY:
430 new_itr = I40E_ITR_20K;
431 break;
432 case I40E_BULK_LATENCY:
433 new_itr = I40E_ITR_8K;
434 break;
435 default:
436 break;
437 }
438
439 if (new_itr != rc->itr) {
440 /* do an exponential smoothing */
441 new_itr = (10 * new_itr * rc->itr) /
442 ((9 * new_itr) + rc->itr);
443 rc->itr = new_itr & I40E_MAX_ITR;
444 }
445
446 rc->total_bytes = 0;
447 rc->total_packets = 0;
448}
449
450/**
451 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
452 * @q_vector: the vector to adjust
453 **/
454static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
455{
456 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
457 struct i40e_hw *hw = &q_vector->vsi->back->hw;
458 u32 reg_addr;
459 u16 old_itr;
460
461 reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
462 old_itr = q_vector->rx.itr;
463 i40e_set_new_dynamic_itr(&q_vector->rx);
464 if (old_itr != q_vector->rx.itr)
465 wr32(hw, reg_addr, q_vector->rx.itr);
466
467 reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
468 old_itr = q_vector->tx.itr;
469 i40e_set_new_dynamic_itr(&q_vector->tx);
470 if (old_itr != q_vector->tx.itr)
471 wr32(hw, reg_addr, q_vector->tx.itr);
472}
473
474/**
475 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
476 * @tx_ring: the tx ring to set up
477 *
478 * Return 0 on success, negative on error
479 **/
480int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
481{
482 struct device *dev = tx_ring->dev;
483 int bi_size;
484
485 if (!dev)
486 return -ENOMEM;
487
488 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
489 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
490 if (!tx_ring->tx_bi)
491 goto err;
492
493 /* round up to nearest 4K */
494 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 495 /* add u32 for head writeback, align after this takes care of
496 * guaranteeing this is at least one cache line in size
497 */
498 tx_ring->size += sizeof(u32);
7f12ad74
GR		 499 tx_ring->size = ALIGN(tx_ring->size, 4096);
500 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
501 &tx_ring->dma, GFP_KERNEL);
502 if (!tx_ring->desc) {
503 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
504 tx_ring->size);
505 goto err;
506 }
507
508 tx_ring->next_to_use = 0;
509 tx_ring->next_to_clean = 0;
510 return 0;
511
512err:
513 kfree(tx_ring->tx_bi);
514 tx_ring->tx_bi = NULL;
515 return -ENOMEM;
516}
517
518/**
519 * i40evf_clean_rx_ring - Free Rx buffers
520 * @rx_ring: ring to be cleaned
521 **/
522void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
523{
524 struct device *dev = rx_ring->dev;
525 struct i40e_rx_buffer *rx_bi;
526 unsigned long bi_size;
527 u16 i;
528
529 /* ring already cleared, nothing to do */
530 if (!rx_ring->rx_bi)
531 return;
532
a132af24
MW		 533 if (ring_is_ps_enabled(rx_ring)) {
534 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
535
536 rx_bi = &rx_ring->rx_bi[0];
537 if (rx_bi->hdr_buf) {
538 dma_free_coherent(dev,
539 bufsz,
540 rx_bi->hdr_buf,
541 rx_bi->dma);
542 for (i = 0; i < rx_ring->count; i++) {
543 rx_bi = &rx_ring->rx_bi[i];
544 rx_bi->dma = 0;
545 rx_bi->hdr_buf = 0;
546 }
547 }
548 }
7f12ad74
GR		 549 /* Free all the Rx ring sk_buffs */
550 for (i = 0; i < rx_ring->count; i++) {
551 rx_bi = &rx_ring->rx_bi[i];
552 if (rx_bi->dma) {
553 dma_unmap_single(dev,
554 rx_bi->dma,
555 rx_ring->rx_buf_len,
556 DMA_FROM_DEVICE);
557 rx_bi->dma = 0;
558 }
559 if (rx_bi->skb) {
560 dev_kfree_skb(rx_bi->skb);
561 rx_bi->skb = NULL;
562 }
563 if (rx_bi->page) {
564 if (rx_bi->page_dma) {
565 dma_unmap_page(dev,
566 rx_bi->page_dma,
567 PAGE_SIZE / 2,
568 DMA_FROM_DEVICE);
569 rx_bi->page_dma = 0;
570 }
571 __free_page(rx_bi->page);
572 rx_bi->page = NULL;
573 rx_bi->page_offset = 0;
574 }
575 }
576
577 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
578 memset(rx_ring->rx_bi, 0, bi_size);
579
580 /* Zero out the descriptor ring */
581 memset(rx_ring->desc, 0, rx_ring->size);
582
583 rx_ring->next_to_clean = 0;
584 rx_ring->next_to_use = 0;
585}
586
587/**
588 * i40evf_free_rx_resources - Free Rx resources
589 * @rx_ring: ring to clean the resources from
590 *
591 * Free all receive software resources
592 **/
593void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
594{
595 i40evf_clean_rx_ring(rx_ring);
596 kfree(rx_ring->rx_bi);
597 rx_ring->rx_bi = NULL;
598
599 if (rx_ring->desc) {
600 dma_free_coherent(rx_ring->dev, rx_ring->size,
601 rx_ring->desc, rx_ring->dma);
602 rx_ring->desc = NULL;
603 }
604}
605
a132af24
MW		 606/**
607 * i40evf_alloc_rx_headers - allocate rx header buffers
608 * @rx_ring: ring to alloc buffers
609 *
610 * Allocate rx header buffers for the entire ring. As these are static,
611 * this is only called when setting up a new ring.
612 **/
613void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
614{
615 struct device *dev = rx_ring->dev;
616 struct i40e_rx_buffer *rx_bi;
617 dma_addr_t dma;
618 void *buffer;
619 int buf_size;
620 int i;
621
622 if (rx_ring->rx_bi[0].hdr_buf)
623 return;
624 /* Make sure the buffers don't cross cache line boundaries. */
625 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
626 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
627 &dma, GFP_KERNEL);
628 if (!buffer)
629 return;
630 for (i = 0; i < rx_ring->count; i++) {
631 rx_bi = &rx_ring->rx_bi[i];
632 rx_bi->dma = dma + (i * buf_size);
633 rx_bi->hdr_buf = buffer + (i * buf_size);
634 }
635}
636
7f12ad74
GR		 637/**
638 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
639 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
640 *
641 * Returns 0 on success, negative on failure
642 **/
643int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
644{
645 struct device *dev = rx_ring->dev;
646 int bi_size;
647
648 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
649 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
650 if (!rx_ring->rx_bi)
651 goto err;
652
f217d6ca 653 u64_stats_init(&rx_ring->syncp);
638702bd 654
7f12ad74
GR		 655 /* Round up to nearest 4K */
656 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
657 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
658 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
659 rx_ring->size = ALIGN(rx_ring->size, 4096);
660 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
661 &rx_ring->dma, GFP_KERNEL);
662
663 if (!rx_ring->desc) {
664 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
665 rx_ring->size);
666 goto err;
667 }
668
669 rx_ring->next_to_clean = 0;
670 rx_ring->next_to_use = 0;
671
672 return 0;
673err:
674 kfree(rx_ring->rx_bi);
675 rx_ring->rx_bi = NULL;
676 return -ENOMEM;
677}
678
679/**
680 * i40e_release_rx_desc - Store the new tail and head values
681 * @rx_ring: ring to bump
682 * @val: new head index
683 **/
684static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
685{
686 rx_ring->next_to_use = val;
687 /* Force memory writes to complete before letting h/w
688 * know there are new descriptors to fetch. (Only
689 * applicable for weak-ordered memory model archs,
690 * such as IA-64).
691 */
692 wmb();
693 writel(val, rx_ring->tail);
694}
695
696/**
a132af24
MW		 697 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
698 * @rx_ring: ring to place buffers on
699 * @cleaned_count: number of buffers to replace
700 **/
701void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
702{
703 u16 i = rx_ring->next_to_use;
704 union i40e_rx_desc *rx_desc;
705 struct i40e_rx_buffer *bi;
706
707 /* do nothing if no valid netdev defined */
708 if (!rx_ring->netdev || !cleaned_count)
709 return;
710
711 while (cleaned_count--) {
712 rx_desc = I40E_RX_DESC(rx_ring, i);
713 bi = &rx_ring->rx_bi[i];
714
715 if (bi->skb) /* desc is in use */
716 goto no_buffers;
717 if (!bi->page) {
718 bi->page = alloc_page(GFP_ATOMIC);
719 if (!bi->page) {
720 rx_ring->rx_stats.alloc_page_failed++;
721 goto no_buffers;
722 }
723 }
724
725 if (!bi->page_dma) {
726 /* use a half page if we're re-using */
727 bi->page_offset ^= PAGE_SIZE / 2;
728 bi->page_dma = dma_map_page(rx_ring->dev,
729 bi->page,
730 bi->page_offset,
731 PAGE_SIZE / 2,
732 DMA_FROM_DEVICE);
733 if (dma_mapping_error(rx_ring->dev,
734 bi->page_dma)) {
735 rx_ring->rx_stats.alloc_page_failed++;
736 bi->page_dma = 0;
737 goto no_buffers;
738 }
739 }
740
741 dma_sync_single_range_for_device(rx_ring->dev,
742 bi->dma,
743 0,
744 rx_ring->rx_hdr_len,
745 DMA_FROM_DEVICE);
746 /* Refresh the desc even if buffer_addrs didn't change
747 * because each write-back erases this info.
748 */
749 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
750 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
751 i++;
752 if (i == rx_ring->count)
753 i = 0;
754 }
755
756no_buffers:
757 if (rx_ring->next_to_use != i)
758 i40e_release_rx_desc(rx_ring, i);
759}
760
761/**
762 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
7f12ad74
GR		 763 * @rx_ring: ring to place buffers on
764 * @cleaned_count: number of buffers to replace
765 **/
a132af24 766void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
7f12ad74
GR		 767{
768 u16 i = rx_ring->next_to_use;
769 union i40e_rx_desc *rx_desc;
770 struct i40e_rx_buffer *bi;
771 struct sk_buff *skb;
772
773 /* do nothing if no valid netdev defined */
774 if (!rx_ring->netdev || !cleaned_count)
775 return;
776
777 while (cleaned_count--) {
778 rx_desc = I40E_RX_DESC(rx_ring, i);
779 bi = &rx_ring->rx_bi[i];
780 skb = bi->skb;
781
782 if (!skb) {
783 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
784 rx_ring->rx_buf_len);
785 if (!skb) {
786 rx_ring->rx_stats.alloc_buff_failed++;
787 goto no_buffers;
788 }
789 /* initialize queue mapping */
790 skb_record_rx_queue(skb, rx_ring->queue_index);
791 bi->skb = skb;
792 }
793
794 if (!bi->dma) {
795 bi->dma = dma_map_single(rx_ring->dev,
796 skb->data,
797 rx_ring->rx_buf_len,
798 DMA_FROM_DEVICE);
799 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
800 rx_ring->rx_stats.alloc_buff_failed++;
801 bi->dma = 0;
802 goto no_buffers;
803 }
804 }
805
a132af24
MW		 806 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
807 rx_desc->read.hdr_addr = 0;
7f12ad74
GR		 808 i++;
809 if (i == rx_ring->count)
810 i = 0;
811 }
812
813no_buffers:
814 if (rx_ring->next_to_use != i)
815 i40e_release_rx_desc(rx_ring, i);
816}
817
818/**
819 * i40e_receive_skb - Send a completed packet up the stack
820 * @rx_ring: rx ring in play
821 * @skb: packet to send up
822 * @vlan_tag: vlan tag for packet
823 **/
824static void i40e_receive_skb(struct i40e_ring *rx_ring,
825 struct sk_buff *skb, u16 vlan_tag)
826{
827 struct i40e_q_vector *q_vector = rx_ring->q_vector;
828 struct i40e_vsi *vsi = rx_ring->vsi;
829 u64 flags = vsi->back->flags;
830
831 if (vlan_tag & VLAN_VID_MASK)
832 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
833
834 if (flags & I40E_FLAG_IN_NETPOLL)
835 netif_rx(skb);
836 else
837 napi_gro_receive(&q_vector->napi, skb);
838}
839
840/**
841 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
842 * @vsi: the VSI we care about
843 * @skb: skb currently being received and modified
844 * @rx_status: status value of last descriptor in packet
845 * @rx_error: error value of last descriptor in packet
846 * @rx_ptype: ptype value of last descriptor in packet
847 **/
848static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
849 struct sk_buff *skb,
850 u32 rx_status,
851 u32 rx_error,
852 u16 rx_ptype)
853{
8a3c91cc
JB		 854 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
855 bool ipv4 = false, ipv6 = false;
7f12ad74
GR		 856 bool ipv4_tunnel, ipv6_tunnel;
857 __wsum rx_udp_csum;
7f12ad74 858 struct iphdr *iph;
8a3c91cc 859 __sum16 csum;
7f12ad74 860
f8faaa40
ASJ		 861 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
862 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
863 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
864 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
7f12ad74 865
7f12ad74
GR		 866 skb->ip_summed = CHECKSUM_NONE;
867
868 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 869 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
870 return;
871
872 /* did the hardware decode the packet and checksum? */
873 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
874 return;
875
876 /* both known and outer_ip must be set for the below code to work */
877 if (!(decoded.known && decoded.outer_ip))
7f12ad74
GR		 878 return;
879
8a3c91cc
JB		 880 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
881 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
882 ipv4 = true;
883 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
884 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
885 ipv6 = true;
886
887 if (ipv4 &&
888 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
889 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
890 goto checksum_fail;
891
ddf1d0d7 892 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 893 if (ipv6 &&
8a3c91cc
JB		 894 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
895 /* don't increment checksum err here, non-fatal err */
7f12ad74
GR		 896 return;
897
8a3c91cc
JB		 898 /* there was some L4 error, count error and punt packet to the stack */
899 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
900 goto checksum_fail;
901
902 /* handle packets that were not able to be checksummed due
903 * to arrival speed, in this case the stack can compute
904 * the csum.
905 */
906 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
7f12ad74 907 return;
7f12ad74 908
8a3c91cc
JB		 909 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
910 * it in the driver, hardware does not do it for us.
911 * Since L3L4P bit was set we assume a valid IHL value (>=5)
912 * so the total length of IPv4 header is IHL*4 bytes
913 * The UDP_0 bit *may* bet set if the *inner* header is UDP
914 */
7f12ad74 915 if (ipv4_tunnel &&
8a3c91cc 916 (decoded.inner_prot != I40E_RX_PTYPE_INNER_PROT_UDP) &&
7f12ad74 917 !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
7f12ad74
GR		 918 skb->transport_header = skb->mac_header +
919 sizeof(struct ethhdr) +
920 (ip_hdr(skb)->ihl * 4);
921
922 /* Add 4 bytes for VLAN tagged packets */
923 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
924 skb->protocol == htons(ETH_P_8021AD))
925 ? VLAN_HLEN : 0;
926
927 rx_udp_csum = udp_csum(skb);
928 iph = ip_hdr(skb);
929 csum = csum_tcpudp_magic(
930 iph->saddr, iph->daddr,
931 (skb->len - skb_transport_offset(skb)),
932 IPPROTO_UDP, rx_udp_csum);
933
8a3c91cc
JB		 934 if (udp_hdr(skb)->check != csum)
935 goto checksum_fail;
7f12ad74
GR		 936 }
937
938 skb->ip_summed = CHECKSUM_UNNECESSARY;
407fa085 939 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 940
941 return;
942
943checksum_fail:
944 vsi->back->hw_csum_rx_error++;
7f12ad74
GR		 945}
946
947/**
948 * i40e_rx_hash - returns the hash value from the Rx descriptor
949 * @ring: descriptor ring
950 * @rx_desc: specific descriptor
951 **/
952static inline u32 i40e_rx_hash(struct i40e_ring *ring,
953 union i40e_rx_desc *rx_desc)
954{
955 const __le64 rss_mask =
956 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
957 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
958
959 if ((ring->netdev->features & NETIF_F_RXHASH) &&
960 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
961 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
962 else
963 return 0;
964}
965
206812b5
JB		 966/**
967 * i40e_ptype_to_hash - get a hash type
968 * @ptype: the ptype value from the descriptor
969 *
970 * Returns a hash type to be used by skb_set_hash
971 **/
972static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
973{
974 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
975
976 if (!decoded.known)
977 return PKT_HASH_TYPE_NONE;
978
979 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
980 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
981 return PKT_HASH_TYPE_L4;
982 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
983 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
984 return PKT_HASH_TYPE_L3;
985 else
986 return PKT_HASH_TYPE_L2;
987}
988
7f12ad74 989/**
a132af24 990 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
7f12ad74
GR		 991 * @rx_ring: rx ring to clean
992 * @budget: how many cleans we're allowed
993 *
994 * Returns true if there's any budget left (e.g. the clean is finished)
995 **/
a132af24 996static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
7f12ad74
GR		 997{
998 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
999 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1000 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1001 const int current_node = numa_node_id();
1002 struct i40e_vsi *vsi = rx_ring->vsi;
1003 u16 i = rx_ring->next_to_clean;
1004 union i40e_rx_desc *rx_desc;
1005 u32 rx_error, rx_status;
206812b5 1006 u8 rx_ptype;
7f12ad74 1007 u64 qword;
7f12ad74 1008
a132af24 1009 do {
7f12ad74
GR		 1010 struct i40e_rx_buffer *rx_bi;
1011 struct sk_buff *skb;
1012 u16 vlan_tag;
a132af24
MW		 1013 /* return some buffers to hardware, one at a time is too slow */
1014 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1015 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1016 cleaned_count = 0;
1017 }
1018
1019 i = rx_ring->next_to_clean;
1020 rx_desc = I40E_RX_DESC(rx_ring, i);
1021 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1022 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1023 I40E_RXD_QW1_STATUS_SHIFT;
1024
1025 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1026 break;
1027
1028 /* This memory barrier is needed to keep us from reading
1029 * any other fields out of the rx_desc until we know the
1030 * DD bit is set.
1031 */
1032 rmb();
7f12ad74
GR		 1033 rx_bi = &rx_ring->rx_bi[i];
1034 skb = rx_bi->skb;
a132af24
MW		 1035 if (likely(!skb)) {
1036 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1037 rx_ring->rx_hdr_len);
1038 if (!skb)
1039 rx_ring->rx_stats.alloc_buff_failed++;
1040 /* initialize queue mapping */
1041 skb_record_rx_queue(skb, rx_ring->queue_index);
1042 /* we are reusing so sync this buffer for CPU use */
1043 dma_sync_single_range_for_cpu(rx_ring->dev,
1044 rx_bi->dma,
1045 0,
1046 rx_ring->rx_hdr_len,
1047 DMA_FROM_DEVICE);
1048 }
7f12ad74
GR		 1049 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1050 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1051 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1052 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1053 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1054 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1055
1056 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1057 I40E_RXD_QW1_ERROR_SHIFT;
1058 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1059 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1060
1061 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1062 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 1063 prefetch(rx_bi->page);
7f12ad74 1064 rx_bi->skb = NULL;
a132af24
MW		 1065 cleaned_count++;
1066 if (rx_hbo || rx_sph) {
1067 int len;
7f12ad74
GR		 1068 if (rx_hbo)
1069 len = I40E_RX_HDR_SIZE;
7f12ad74 1070 else
a132af24
MW		 1071 len = rx_header_len;
1072 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1073 } else if (skb->len == 0) {
1074 int len;
1075
1076 len = (rx_packet_len > skb_headlen(skb) ?
1077 skb_headlen(skb) : rx_packet_len);
1078 memcpy(__skb_put(skb, len),
1079 rx_bi->page + rx_bi->page_offset,
1080 len);
1081 rx_bi->page_offset += len;
1082 rx_packet_len -= len;
7f12ad74
GR		 1083 }
1084
1085 /* Get the rest of the data if this was a header split */
a132af24 1086 if (rx_packet_len) {
7f12ad74
GR		 1087 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1088 rx_bi->page,
1089 rx_bi->page_offset,
1090 rx_packet_len);
1091
1092 skb->len += rx_packet_len;
1093 skb->data_len += rx_packet_len;
1094 skb->truesize += rx_packet_len;
1095
1096 if ((page_count(rx_bi->page) == 1) &&
1097 (page_to_nid(rx_bi->page) == current_node))
1098 get_page(rx_bi->page);
1099 else
1100 rx_bi->page = NULL;
1101
1102 dma_unmap_page(rx_ring->dev,
1103 rx_bi->page_dma,
1104 PAGE_SIZE / 2,
1105 DMA_FROM_DEVICE);
1106 rx_bi->page_dma = 0;
1107 }
a132af24 1108 I40E_RX_INCREMENT(rx_ring, i);
7f12ad74
GR		 1109
1110 if (unlikely(
1111 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1112 struct i40e_rx_buffer *next_buffer;
1113
1114 next_buffer = &rx_ring->rx_bi[i];
a132af24 1115 next_buffer->skb = skb;
7f12ad74 1116 rx_ring->rx_stats.non_eop_descs++;
a132af24 1117 continue;
7f12ad74
GR		 1118 }
1119
1120 /* ERR_MASK will only have valid bits if EOP set */
1121 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1122 dev_kfree_skb_any(skb);
8a3c91cc
JB		 1123 /* TODO: shouldn't we increment a counter indicating the
1124 * drop?
1125 */
a132af24 1126 continue;
7f12ad74
GR		 1127 }
1128
206812b5
JB		 1129 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1130 i40e_ptype_to_hash(rx_ptype));
7f12ad74
GR		 1131 /* probably a little skewed due to removing CRC */
1132 total_rx_bytes += skb->len;
1133 total_rx_packets++;
1134
1135 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1136
1137 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1138
1139 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1140 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1141 : 0;
a132af24
MW		 1142#ifdef I40E_FCOE
1143 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1144 dev_kfree_skb_any(skb);
1145 continue;
1146 }
1147#endif
1148 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
7f12ad74
GR		 1149 i40e_receive_skb(rx_ring, skb, vlan_tag);
1150
1151 rx_ring->netdev->last_rx = jiffies;
7f12ad74 1152 rx_desc->wb.qword1.status_error_len = 0;
7f12ad74 1153
a132af24
MW		 1154 } while (likely(total_rx_packets < budget));
1155
1156 u64_stats_update_begin(&rx_ring->syncp);
1157 rx_ring->stats.packets += total_rx_packets;
1158 rx_ring->stats.bytes += total_rx_bytes;
1159 u64_stats_update_end(&rx_ring->syncp);
1160 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1161 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1162
1163 return total_rx_packets;
1164}
1165
1166/**
1167 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1168 * @rx_ring: rx ring to clean
1169 * @budget: how many cleans we're allowed
1170 *
1171 * Returns number of packets cleaned
1172 **/
1173static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1174{
1175 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1176 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1177 struct i40e_vsi *vsi = rx_ring->vsi;
1178 union i40e_rx_desc *rx_desc;
1179 u32 rx_error, rx_status;
1180 u16 rx_packet_len;
1181 u8 rx_ptype;
1182 u64 qword;
1183 u16 i;
1184
1185 do {
1186 struct i40e_rx_buffer *rx_bi;
1187 struct sk_buff *skb;
1188 u16 vlan_tag;
7f12ad74
GR		 1189 /* return some buffers to hardware, one at a time is too slow */
1190 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1191 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
7f12ad74
GR		 1192 cleaned_count = 0;
1193 }
1194
a132af24
MW		 1195 i = rx_ring->next_to_clean;
1196 rx_desc = I40E_RX_DESC(rx_ring, i);
7f12ad74
GR		 1197 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1198 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1199 I40E_RXD_QW1_STATUS_SHIFT;
1200
1201 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1202 break;
1203
1204 /* This memory barrier is needed to keep us from reading
1205 * any other fields out of the rx_desc until we know the
1206 * DD bit is set.
1207 */
1208 rmb();
1209
1210 rx_bi = &rx_ring->rx_bi[i];
1211 skb = rx_bi->skb;
1212 prefetch(skb->data);
1213
1214 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1215 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1216
1217 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1218 I40E_RXD_QW1_ERROR_SHIFT;
1219 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1220
1221 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1222 I40E_RXD_QW1_PTYPE_SHIFT;
1223 rx_bi->skb = NULL;
1224 cleaned_count++;
1225
1226 /* Get the header and possibly the whole packet
1227 * If this is an skb from previous receive dma will be 0
1228 */
1229 skb_put(skb, rx_packet_len);
1230 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1231 DMA_FROM_DEVICE);
1232 rx_bi->dma = 0;
1233
1234 I40E_RX_INCREMENT(rx_ring, i);
1235
1236 if (unlikely(
1237 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1238 rx_ring->rx_stats.non_eop_descs++;
1239 continue;
1240 }
1241
1242 /* ERR_MASK will only have valid bits if EOP set */
1243 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1244 dev_kfree_skb_any(skb);
1245 /* TODO: shouldn't we increment a counter indicating the
1246 * drop?
1247 */
1248 continue;
1249 }
1250
1251 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1252 i40e_ptype_to_hash(rx_ptype));
1253 /* probably a little skewed due to removing CRC */
1254 total_rx_bytes += skb->len;
1255 total_rx_packets++;
1256
1257 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1258
1259 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1260
1261 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1262 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1263 : 0;
1264 i40e_receive_skb(rx_ring, skb, vlan_tag);
1265
1266 rx_ring->netdev->last_rx = jiffies;
1267 rx_desc->wb.qword1.status_error_len = 0;
1268 } while (likely(total_rx_packets < budget));
7f12ad74 1269
7f12ad74
GR		 1270 u64_stats_update_begin(&rx_ring->syncp);
1271 rx_ring->stats.packets += total_rx_packets;
1272 rx_ring->stats.bytes += total_rx_bytes;
1273 u64_stats_update_end(&rx_ring->syncp);
1274 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1275 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1276
a132af24 1277 return total_rx_packets;
7f12ad74
GR		 1278}
1279
1280/**
1281 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1282 * @napi: napi struct with our devices info in it
1283 * @budget: amount of work driver is allowed to do this pass, in packets
1284 *
1285 * This function will clean all queues associated with a q_vector.
1286 *
1287 * Returns the amount of work done
1288 **/
1289int i40evf_napi_poll(struct napi_struct *napi, int budget)
1290{
1291 struct i40e_q_vector *q_vector =
1292 container_of(napi, struct i40e_q_vector, napi);
1293 struct i40e_vsi *vsi = q_vector->vsi;
1294 struct i40e_ring *ring;
1295 bool clean_complete = true;
c29af37f 1296 bool arm_wb = false;
7f12ad74 1297 int budget_per_ring;
a132af24 1298 int cleaned;
7f12ad74
GR		 1299
1300 if (test_bit(__I40E_DOWN, &vsi->state)) {
1301 napi_complete(napi);
1302 return 0;
1303 }
1304
1305 /* Since the actual Tx work is minimal, we can give the Tx a larger
1306 * budget and be more aggressive about cleaning up the Tx descriptors.
1307 */
c29af37f 1308 i40e_for_each_ring(ring, q_vector->tx) {
7f12ad74 1309 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
c29af37f
ASJ		 1310 arm_wb |= ring->arm_wb;
1311 }
7f12ad74
GR		 1312
1313 /* We attempt to distribute budget to each Rx queue fairly, but don't
1314 * allow the budget to go below 1 because that would exit polling early.
1315 */
1316 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1317
a132af24
MW		 1318 i40e_for_each_ring(ring, q_vector->rx) {
1319 if (ring_is_ps_enabled(ring))
1320 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1321 else
1322 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1323 /* if we didn't clean as many as budgeted, we must be done */
1324 clean_complete &= (budget_per_ring != cleaned);
1325 }
7f12ad74
GR		 1326
1327 /* If work not completed, return budget and polling will return */
c29af37f
ASJ		 1328 if (!clean_complete) {
1329 if (arm_wb)
1330 i40e_force_wb(vsi, q_vector);
7f12ad74 1331 return budget;
c29af37f 1332 }
7f12ad74
GR		 1333
1334 /* Work is done so exit the polling mode and re-enable the interrupt */
1335 napi_complete(napi);
1336 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1337 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1338 i40e_update_dynamic_itr(q_vector);
1339
1340 if (!test_bit(__I40E_DOWN, &vsi->state))
1341 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1342
1343 return 0;
1344}
1345
1346/**
1347 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1348 * @skb: send buffer
1349 * @tx_ring: ring to send buffer on
1350 * @flags: the tx flags to be set
1351 *
1352 * Checks the skb and set up correspondingly several generic transmit flags
1353 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1354 *
1355 * Returns error code indicate the frame should be dropped upon error and the
1356 * otherwise returns 0 to indicate the flags has been set properly.
1357 **/
1358static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1359 struct i40e_ring *tx_ring,
1360 u32 *flags)
1361{
1362 __be16 protocol = skb->protocol;
1363 u32 tx_flags = 0;
1364
1365 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 1366 if (skb_vlan_tag_present(skb)) {
1367 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
7f12ad74
GR		 1368 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1369 /* else if it is a SW VLAN, check the next protocol and store the tag */
1370 } else if (protocol == htons(ETH_P_8021Q)) {
1371 struct vlan_hdr *vhdr, _vhdr;
1372 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1373 if (!vhdr)
1374 return -EINVAL;
1375
1376 protocol = vhdr->h_vlan_encapsulated_proto;
1377 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1378 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1379 }
1380
1381 *flags = tx_flags;
1382 return 0;
1383}
1384
1385/**
1386 * i40e_tso - set up the tso context descriptor
1387 * @tx_ring: ptr to the ring to send
1388 * @skb: ptr to the skb we're sending
1389 * @tx_flags: the collected send information
1390 * @protocol: the send protocol
1391 * @hdr_len: ptr to the size of the packet header
1392 * @cd_tunneling: ptr to context descriptor bits
1393 *
1394 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1395 **/
1396static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1397 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1398 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1399{
1400 u32 cd_cmd, cd_tso_len, cd_mss;
fe6d4aa4 1401 struct ipv6hdr *ipv6h;
7f12ad74
GR		 1402 struct tcphdr *tcph;
1403 struct iphdr *iph;
1404 u32 l4len;
1405 int err;
7f12ad74
GR		 1406
1407 if (!skb_is_gso(skb))
1408 return 0;
1409
fe6d4aa4
FR		 1410 err = skb_cow_head(skb, 0);
1411 if (err < 0)
1412 return err;
7f12ad74 1413
85e76d03
AS		 1414 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1415 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1416
1417 if (iph->version == 4) {
7f12ad74
GR		 1418 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1419 iph->tot_len = 0;
1420 iph->check = 0;
1421 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1422 0, IPPROTO_TCP, 0);
85e76d03 1423 } else if (ipv6h->version == 6) {
7f12ad74
GR		 1424 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1425 ipv6h->payload_len = 0;
1426 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1427 0, IPPROTO_TCP, 0);
1428 }
1429
1430 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1431 *hdr_len = (skb->encapsulation
1432 ? (skb_inner_transport_header(skb) - skb->data)
1433 : skb_transport_offset(skb)) + l4len;
1434
1435 /* find the field values */
1436 cd_cmd = I40E_TX_CTX_DESC_TSO;
1437 cd_tso_len = skb->len - *hdr_len;
1438 cd_mss = skb_shinfo(skb)->gso_size;
1439 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1440 ((u64)cd_tso_len <<
1441 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1442 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1443 return 1;
1444}
1445
1446/**
1447 * i40e_tx_enable_csum - Enable Tx checksum offloads
1448 * @skb: send buffer
1449 * @tx_flags: Tx flags currently set
1450 * @td_cmd: Tx descriptor command bits to set
1451 * @td_offset: Tx descriptor header offsets to set
1452 * @cd_tunneling: ptr to context desc bits
1453 **/
1454static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1455 u32 *td_cmd, u32 *td_offset,
1456 struct i40e_ring *tx_ring,
1457 u32 *cd_tunneling)
1458{
1459 struct ipv6hdr *this_ipv6_hdr;
1460 unsigned int this_tcp_hdrlen;
1461 struct iphdr *this_ip_hdr;
1462 u32 network_hdr_len;
1463 u8 l4_hdr = 0;
1464
1465 if (skb->encapsulation) {
1466 network_hdr_len = skb_inner_network_header_len(skb);
1467 this_ip_hdr = inner_ip_hdr(skb);
1468 this_ipv6_hdr = inner_ipv6_hdr(skb);
1469 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1470
1471 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1472
1473 if (tx_flags & I40E_TX_FLAGS_TSO) {
1474 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1475 ip_hdr(skb)->check = 0;
1476 } else {
1477 *cd_tunneling |=
1478 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1479 }
1480 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
85e76d03
AS		 1481 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1482 if (tx_flags & I40E_TX_FLAGS_TSO)
7f12ad74 1483 ip_hdr(skb)->check = 0;
7f12ad74
GR		 1484 }
1485
1486 /* Now set the ctx descriptor fields */
1487 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1488 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1489 I40E_TXD_CTX_UDP_TUNNELING |
1490 ((skb_inner_network_offset(skb) -
1491 skb_transport_offset(skb)) >> 1) <<
1492 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
85e76d03
AS		 1493 if (this_ip_hdr->version == 6) {
1494 tx_flags &= ~I40E_TX_FLAGS_IPV4;
1495 tx_flags |= I40E_TX_FLAGS_IPV6;
1496 }
1497
7f12ad74
GR		 1498
1499 } else {
1500 network_hdr_len = skb_network_header_len(skb);
1501 this_ip_hdr = ip_hdr(skb);
1502 this_ipv6_hdr = ipv6_hdr(skb);
1503 this_tcp_hdrlen = tcp_hdrlen(skb);
1504 }
1505
1506 /* Enable IP checksum offloads */
1507 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1508 l4_hdr = this_ip_hdr->protocol;
1509 /* the stack computes the IP header already, the only time we
1510 * need the hardware to recompute it is in the case of TSO.
1511 */
1512 if (tx_flags & I40E_TX_FLAGS_TSO) {
1513 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1514 this_ip_hdr->check = 0;
1515 } else {
1516 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1517 }
1518 /* Now set the td_offset for IP header length */
1519 *td_offset = (network_hdr_len >> 2) <<
1520 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1521 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1522 l4_hdr = this_ipv6_hdr->nexthdr;
1523 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1524 /* Now set the td_offset for IP header length */
1525 *td_offset = (network_hdr_len >> 2) <<
1526 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1527 }
1528 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1529 *td_offset |= (skb_network_offset(skb) >> 1) <<
1530 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1531
1532 /* Enable L4 checksum offloads */
1533 switch (l4_hdr) {
1534 case IPPROTO_TCP:
1535 /* enable checksum offloads */
1536 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1537 *td_offset |= (this_tcp_hdrlen >> 2) <<
1538 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1539 break;
1540 case IPPROTO_SCTP:
1541 /* enable SCTP checksum offload */
1542 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1543 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1544 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1545 break;
1546 case IPPROTO_UDP:
1547 /* enable UDP checksum offload */
1548 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1549 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1550 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1551 break;
1552 default:
1553 break;
1554 }
1555}
1556
1557/**
1558 * i40e_create_tx_ctx Build the Tx context descriptor
1559 * @tx_ring: ring to create the descriptor on
1560 * @cd_type_cmd_tso_mss: Quad Word 1
1561 * @cd_tunneling: Quad Word 0 - bits 0-31
1562 * @cd_l2tag2: Quad Word 0 - bits 32-63
1563 **/
1564static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1565 const u64 cd_type_cmd_tso_mss,
1566 const u32 cd_tunneling, const u32 cd_l2tag2)
1567{
1568 struct i40e_tx_context_desc *context_desc;
1569 int i = tx_ring->next_to_use;
1570
ff40dd5d
JB		 1571 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1572 !cd_tunneling && !cd_l2tag2)
7f12ad74
GR		 1573 return;
1574
1575 /* grab the next descriptor */
1576 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1577
1578 i++;
1579 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1580
1581 /* cpu_to_le32 and assign to struct fields */
1582 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1583 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 1584 context_desc->rsvd = cpu_to_le16(0);
7f12ad74
GR		 1585 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1586}
1587
71da6197
AS		 1588 /**
1589 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1590 * @skb: send buffer
1591 * @tx_flags: collected send information
1592 * @hdr_len: size of the packet header
1593 *
1594 * Note: Our HW can't scatter-gather more than 8 fragments to build
1595 * a packet on the wire and so we need to figure out the cases where we
1596 * need to linearize the skb.
1597 **/
1598static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags,
1599 const u8 hdr_len)
1600{
1601 struct skb_frag_struct *frag;
1602 bool linearize = false;
1603 unsigned int size = 0;
1604 u16 num_frags;
1605 u16 gso_segs;
1606
1607 num_frags = skb_shinfo(skb)->nr_frags;
1608 gso_segs = skb_shinfo(skb)->gso_segs;
1609
1610 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1611 u16 j = 1;
1612
1613 if (num_frags < (I40E_MAX_BUFFER_TXD))
1614 goto linearize_chk_done;
1615 /* try the simple math, if we have too many frags per segment */
1616 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1617 I40E_MAX_BUFFER_TXD) {
1618 linearize = true;
1619 goto linearize_chk_done;
1620 }
1621 frag = &skb_shinfo(skb)->frags[0];
1622 size = hdr_len;
1623 /* we might still have more fragments per segment */
1624 do {
1625 size += skb_frag_size(frag);
1626 frag++; j++;
1627 if (j == I40E_MAX_BUFFER_TXD) {
1628 if (size < skb_shinfo(skb)->gso_size) {
1629 linearize = true;
1630 break;
1631 }
1632 j = 1;
1633 size -= skb_shinfo(skb)->gso_size;
1634 if (size)
1635 j++;
1636 size += hdr_len;
1637 }
1638 num_frags--;
1639 } while (num_frags);
1640 } else {
1641 if (num_frags >= I40E_MAX_BUFFER_TXD)
1642 linearize = true;
1643 }
1644
1645linearize_chk_done:
1646 return linearize;
1647}
1648
7f12ad74
GR		 1649/**
1650 * i40e_tx_map - Build the Tx descriptor
1651 * @tx_ring: ring to send buffer on
1652 * @skb: send buffer
1653 * @first: first buffer info buffer to use
1654 * @tx_flags: collected send information
1655 * @hdr_len: size of the packet header
1656 * @td_cmd: the command field in the descriptor
1657 * @td_offset: offset for checksum or crc
1658 **/
1659static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1660 struct i40e_tx_buffer *first, u32 tx_flags,
1661 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1662{
1663 unsigned int data_len = skb->data_len;
1664 unsigned int size = skb_headlen(skb);
1665 struct skb_frag_struct *frag;
1666 struct i40e_tx_buffer *tx_bi;
1667 struct i40e_tx_desc *tx_desc;
1668 u16 i = tx_ring->next_to_use;
1669 u32 td_tag = 0;
1670 dma_addr_t dma;
1671 u16 gso_segs;
1672
1673 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1674 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1675 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1676 I40E_TX_FLAGS_VLAN_SHIFT;
1677 }
1678
1679 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1680 gso_segs = skb_shinfo(skb)->gso_segs;
1681 else
1682 gso_segs = 1;
1683
1684 /* multiply data chunks by size of headers */
1685 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1686 first->gso_segs = gso_segs;
1687 first->skb = skb;
1688 first->tx_flags = tx_flags;
1689
1690 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1691
1692 tx_desc = I40E_TX_DESC(tx_ring, i);
1693 tx_bi = first;
1694
1695 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1696 if (dma_mapping_error(tx_ring->dev, dma))
1697 goto dma_error;
1698
1699 /* record length, and DMA address */
1700 dma_unmap_len_set(tx_bi, len, size);
1701 dma_unmap_addr_set(tx_bi, dma, dma);
1702
1703 tx_desc->buffer_addr = cpu_to_le64(dma);
1704
1705 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1706 tx_desc->cmd_type_offset_bsz =
1707 build_ctob(td_cmd, td_offset,
1708 I40E_MAX_DATA_PER_TXD, td_tag);
1709
1710 tx_desc++;
1711 i++;
1712 if (i == tx_ring->count) {
1713 tx_desc = I40E_TX_DESC(tx_ring, 0);
1714 i = 0;
1715 }
1716
1717 dma += I40E_MAX_DATA_PER_TXD;
1718 size -= I40E_MAX_DATA_PER_TXD;
1719
1720 tx_desc->buffer_addr = cpu_to_le64(dma);
1721 }
1722
1723 if (likely(!data_len))
1724 break;
1725
1726 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1727 size, td_tag);
1728
1729 tx_desc++;
1730 i++;
1731 if (i == tx_ring->count) {
1732 tx_desc = I40E_TX_DESC(tx_ring, 0);
1733 i = 0;
1734 }
1735
1736 size = skb_frag_size(frag);
1737 data_len -= size;
1738
1739 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1740 DMA_TO_DEVICE);
1741
1742 tx_bi = &tx_ring->tx_bi[i];
1743 }
1744
1943d8ba
JB		 1745 /* Place RS bit on last descriptor of any packet that spans across the
1746 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1747 */
1748#define WB_STRIDE 0x3
1749 if (((i & WB_STRIDE) != WB_STRIDE) &&
1750 (first <= &tx_ring->tx_bi[i]) &&
1751 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1752 tx_desc->cmd_type_offset_bsz =
1753 build_ctob(td_cmd, td_offset, size, td_tag) |
1754 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1755 I40E_TXD_QW1_CMD_SHIFT);
1756 } else {
1757 tx_desc->cmd_type_offset_bsz =
1758 build_ctob(td_cmd, td_offset, size, td_tag) |
1759 cpu_to_le64((u64)I40E_TXD_CMD <<
1760 I40E_TXD_QW1_CMD_SHIFT);
1761 }
7f12ad74
GR		 1762
1763 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1764 tx_ring->queue_index),
1765 first->bytecount);
1766
1767 /* set the timestamp */
1768 first->time_stamp = jiffies;
1769
1770 /* Force memory writes to complete before letting h/w
1771 * know there are new descriptors to fetch. (Only
1772 * applicable for weak-ordered memory model archs,
1773 * such as IA-64).
1774 */
1775 wmb();
1776
1777 /* set next_to_watch value indicating a packet is present */
1778 first->next_to_watch = tx_desc;
1779
1780 i++;
1781 if (i == tx_ring->count)
1782 i = 0;
1783
1784 tx_ring->next_to_use = i;
1785
1786 /* notify HW of packet */
1787 writel(i, tx_ring->tail);
1788
1789 return;
1790
1791dma_error:
1792 dev_info(tx_ring->dev, "TX DMA map failed\n");
1793
1794 /* clear dma mappings for failed tx_bi map */
1795 for (;;) {
1796 tx_bi = &tx_ring->tx_bi[i];
1797 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1798 if (tx_bi == first)
1799 break;
1800 if (i == 0)
1801 i = tx_ring->count;
1802 i--;
1803 }
1804
1805 tx_ring->next_to_use = i;
1806}
1807
1808/**
1809 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1810 * @tx_ring: the ring to be checked
1811 * @size: the size buffer we want to assure is available
1812 *
1813 * Returns -EBUSY if a stop is needed, else 0
1814 **/
1815static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1816{
1817 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1818 /* Memory barrier before checking head and tail */
1819 smp_mb();
1820
1821 /* Check again in a case another CPU has just made room available. */
1822 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1823 return -EBUSY;
1824
1825 /* A reprieve! - use start_queue because it doesn't call schedule */
1826 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1827 ++tx_ring->tx_stats.restart_queue;
1828 return 0;
1829}
1830
1831/**
1832 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1833 * @tx_ring: the ring to be checked
1834 * @size: the size buffer we want to assure is available
1835 *
1836 * Returns 0 if stop is not needed
1837 **/
1838static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1839{
1840 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1841 return 0;
1842 return __i40e_maybe_stop_tx(tx_ring, size);
1843}
1844
1845/**
1846 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1847 * @skb: send buffer
1848 * @tx_ring: ring to send buffer on
1849 *
1850 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1851 * there is not enough descriptors available in this ring since we need at least
1852 * one descriptor.
1853 **/
1854static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1855 struct i40e_ring *tx_ring)
1856{
7f12ad74 1857 unsigned int f;
7f12ad74
GR		 1858 int count = 0;
1859
1860 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1861 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 1862 * + 4 desc gap to avoid the cache line where head is,
7f12ad74
GR		 1863 * + 1 desc for context descriptor,
1864 * otherwise try next time
1865 */
7f12ad74
GR		 1866 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1867 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 1868
7f12ad74 1869 count += TXD_USE_COUNT(skb_headlen(skb));
be560521 1870 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
7f12ad74
GR		 1871 tx_ring->tx_stats.tx_busy++;
1872 return 0;
1873 }
1874 return count;
1875}
1876
1877/**
1878 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1879 * @skb: send buffer
1880 * @tx_ring: ring to send buffer on
1881 *
1882 * Returns NETDEV_TX_OK if sent, else an error code
1883 **/
1884static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1885 struct i40e_ring *tx_ring)
1886{
1887 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1888 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1889 struct i40e_tx_buffer *first;
1890 u32 td_offset = 0;
1891 u32 tx_flags = 0;
1892 __be16 protocol;
1893 u32 td_cmd = 0;
1894 u8 hdr_len = 0;
1895 int tso;
1896 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1897 return NETDEV_TX_BUSY;
1898
1899 /* prepare the xmit flags */
1900 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1901 goto out_drop;
1902
1903 /* obtain protocol of skb */
a12c4158 1904 protocol = vlan_get_protocol(skb);
7f12ad74
GR		 1905
1906 /* record the location of the first descriptor for this packet */
1907 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1908
1909 /* setup IPv4/IPv6 offloads */
1910 if (protocol == htons(ETH_P_IP))
1911 tx_flags |= I40E_TX_FLAGS_IPV4;
1912 else if (protocol == htons(ETH_P_IPV6))
1913 tx_flags |= I40E_TX_FLAGS_IPV6;
1914
1915 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1916 &cd_type_cmd_tso_mss, &cd_tunneling);
1917
1918 if (tso < 0)
1919 goto out_drop;
1920 else if (tso)
1921 tx_flags |= I40E_TX_FLAGS_TSO;
1922
71da6197
AS		 1923 if (i40e_chk_linearize(skb, tx_flags, hdr_len))
1924 if (skb_linearize(skb))
1925 goto out_drop;
1926
7f12ad74
GR		 1927 skb_tx_timestamp(skb);
1928
1929 /* always enable CRC insertion offload */
1930 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1931
1932 /* Always offload the checksum, since it's in the data descriptor */
1933 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1934 tx_flags |= I40E_TX_FLAGS_CSUM;
1935
1936 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1937 tx_ring, &cd_tunneling);
1938 }
1939
1940 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1941 cd_tunneling, cd_l2tag2);
1942
1943 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1944 td_cmd, td_offset);
1945
1946 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1947
1948 return NETDEV_TX_OK;
1949
1950out_drop:
1951 dev_kfree_skb_any(skb);
1952 return NETDEV_TX_OK;
1953}
1954
1955/**
1956 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1957 * @skb: send buffer
1958 * @netdev: network interface device structure
1959 *
1960 * Returns NETDEV_TX_OK if sent, else an error code
1961 **/
1962netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1963{
1964 struct i40evf_adapter *adapter = netdev_priv(netdev);
1965 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1966
1967 /* hardware can't handle really short frames, hardware padding works
1968 * beyond this point
1969 */
1970 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1971 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1972 return NETDEV_TX_OK;
1973 skb->len = I40E_MIN_TX_LEN;
1974 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1975 }
1976
1977 return i40e_xmit_frame_ring(skb, tx_ring);
1978}
Linux 6.x block layer and io_uring tree(s)