[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_txrx.h

/*******************************************************************************
 *
 * Intel Ethernet Controller XL710 Family Linux Driver
 * Copyright(c) 2013 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 ******************************************************************************/

/* Interrupt Throttling and Rate Limiting (storm control) Goodies */

#define I40E_MAX_ITR               0x07FF
#define I40E_MIN_ITR               0x0001
#define I40E_ITR_USEC_RESOLUTION   2
#define I40E_MAX_IRATE             0x03F
#define I40E_MIN_IRATE             0x001
#define I40E_IRATE_USEC_RESOLUTION 4
#define I40E_ITR_100K              0x0005
#define I40E_ITR_20K               0x0019
#define I40E_ITR_8K                0x003E
#define I40E_ITR_4K                0x007A
#define I40E_ITR_RX_DEF            I40E_ITR_8K
#define I40E_ITR_TX_DEF            I40E_ITR_4K
#define I40E_ITR_DYNAMIC           0x8000  /* use top bit as a flag */
#define I40E_MIN_INT_RATE          250     /* ~= 1000000 / (I40E_MAX_ITR * 2) */
#define I40E_MAX_INT_RATE          500000  /* == 1000000 / (I40E_MIN_ITR * 2) */
#define I40E_DEFAULT_IRQ_WORK      256
#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)

#define I40E_QUEUE_END_OF_LIST 0x7FF

#define I40E_ITR_NONE  3
#define I40E_RX_ITR    0
#define I40E_TX_ITR    1
#define I40E_PE_ITR    2
/* Supported Rx Buffer Sizes */
#define I40E_RXBUFFER_512   512    /* Used for packet split */
#define I40E_RXBUFFER_2048  2048
#define I40E_RXBUFFER_3072  3072   /* For FCoE MTU of 2158 */
#define I40E_RXBUFFER_4096  4096
#define I40E_RXBUFFER_8192  8192
#define I40E_MAX_RXBUFFER   9728  /* largest size for single descriptor */

/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
 * this adds up to 512 bytes of extra data meaning the smallest allocation
 * we could have is 1K.
 * i.e. RXBUFFER_512 --> size-1024 slab
 */
#define I40E_RX_HDR_SIZE  I40E_RXBUFFER_512

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define I40E_RX_BUFFER_WRITE	16	/* Must be power of 2 */
#define I40E_RX_NEXT_DESC(r, i, n)		\
	do {					\
		(i)++;				\
		if ((i) == (r)->count)		\
			i = 0;			\
		(n) = I40E_RX_DESC((r), (i));	\
	} while (0)

#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n)		\
	do {						\
		I40E_RX_NEXT_DESC((r), (i), (n));	\
		prefetch((n));				\
	} while (0)

#define i40e_rx_desc i40e_32byte_rx_desc

#define I40E_MIN_TX_LEN		17
#define I40E_MAX_DATA_PER_TXD	16383	/* aka 16kB - 1 */

/* Tx Descriptors needed, worst case */
#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)

#define I40E_TX_FLAGS_CSUM		(u32)(1)
#define I40E_TX_FLAGS_HW_VLAN		(u32)(1 << 1)
#define I40E_TX_FLAGS_SW_VLAN		(u32)(1 << 2)
#define I40E_TX_FLAGS_TSO		(u32)(1 << 3)
#define I40E_TX_FLAGS_IPV4		(u32)(1 << 4)
#define I40E_TX_FLAGS_IPV6		(u32)(1 << 5)
#define I40E_TX_FLAGS_FCCRC		(u32)(1 << 6)
#define I40E_TX_FLAGS_FSO		(u32)(1 << 7)
#define I40E_TX_FLAGS_TXSW		(u32)(1 << 8)
#define I40E_TX_FLAGS_MAPPED_AS_PAGE	(u32)(1 << 9)
#define I40E_TX_FLAGS_VLAN_MASK		0xffff0000
#define I40E_TX_FLAGS_VLAN_PRIO_MASK	0xe0000000
#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT	29
#define I40E_TX_FLAGS_VLAN_SHIFT	16

struct i40e_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u32 tx_flags;
	struct i40e_tx_desc *next_to_watch;
	unsigned int bytecount;
	u16 gso_segs;
	u8 mapped_as_page;
};

struct i40e_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	unsigned int page_offset;
};

struct i40e_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 tx_busy;
	u64 completed;
	u64 tx_done_old;
};

struct i40e_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 non_eop_descs;
	u64 alloc_rx_page_failed;
	u64 alloc_rx_buff_failed;
};

enum i40e_ring_state_t {
	__I40E_TX_FDIR_INIT_DONE,
	__I40E_TX_XPS_INIT_DONE,
	__I40E_TX_DETECT_HANG,
	__I40E_HANG_CHECK_ARMED,
	__I40E_RX_PS_ENABLED,
	__I40E_RX_LRO_ENABLED,
	__I40E_RX_16BYTE_DESC_ENABLED,
};

#define ring_is_ps_enabled(ring) \
	test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
#define set_ring_ps_enabled(ring) \
	set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
#define clear_ring_ps_enabled(ring) \
	clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
#define check_for_tx_hang(ring) \
	test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
#define set_check_for_tx_hang(ring) \
	set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
#define clear_check_for_tx_hang(ring) \
	clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
#define ring_is_lro_enabled(ring) \
	test_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
#define set_ring_lro_enabled(ring) \
	set_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
#define clear_ring_lro_enabled(ring) \
	clear_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
#define ring_is_16byte_desc_enabled(ring) \
	test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
#define set_ring_16byte_desc_enabled(ring) \
	set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
#define clear_ring_16byte_desc_enabled(ring) \
	clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)

/* struct that defines a descriptor ring, associated with a VSI */
struct i40e_ring {
	void *desc;			/* Descriptor ring memory */
	struct device *dev;		/* Used for DMA mapping */
	struct net_device *netdev;	/* netdev ring maps to */
	union {
		struct i40e_tx_buffer *tx_bi;
		struct i40e_rx_buffer *rx_bi;
	};
	unsigned long state;
	u16 queue_index;		/* Queue number of ring */
	u8 dcb_tc;			/* Traffic class of ring */
	u8 __iomem *tail;

	u16 count;			/* Number of descriptors */
	u16 reg_idx;			/* HW register index of the ring */
	u16 rx_hdr_len;
	u16 rx_buf_len;
	u8  dtype;
#define I40E_RX_DTYPE_NO_SPLIT      0
#define I40E_RX_DTYPE_SPLIT_ALWAYS  1
#define I40E_RX_DTYPE_HEADER_SPLIT  2
	u8  hsplit;
#define I40E_RX_SPLIT_L2      0x1
#define I40E_RX_SPLIT_IP      0x2
#define I40E_RX_SPLIT_TCP_UDP 0x4
#define I40E_RX_SPLIT_SCTP    0x8

	/* used in interrupt processing */
	u16 next_to_use;
	u16 next_to_clean;

	u8 atr_sample_rate;
	u8 atr_count;

	bool ring_active;		/* is ring online or not */

	/* stats structs */
	union {
		struct i40e_tx_queue_stats tx_stats;
		struct i40e_rx_queue_stats rx_stats;
	};

	unsigned int size;		/* length of descriptor ring in bytes */
	dma_addr_t dma;			/* physical address of ring */

	struct i40e_vsi *vsi;		/* Backreference to associated VSI */
	struct i40e_q_vector *q_vector;	/* Backreference to associated vector */
} ____cacheline_internodealigned_in_smp;

enum i40e_latency_range {
	I40E_LOWEST_LATENCY = 0,
	I40E_LOW_LATENCY = 1,
	I40E_BULK_LATENCY = 2,
};

struct i40e_ring_container {
#define I40E_MAX_RINGPAIR_PER_VECTOR 8
	/* array of pointers to rings */
	struct i40e_ring *ring[I40E_MAX_RINGPAIR_PER_VECTOR];
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 count;
	enum i40e_latency_range latency_range;
	u16 itr;
};

void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
void i40e_free_tx_resources(struct i40e_ring *tx_ring);
void i40e_free_rx_resources(struct i40e_ring *rx_ring);
int i40e_napi_poll(struct napi_struct *napi, int budget);
Commit	Line	Data
7daa6bf3 JB	1	/*******************************************************************************
	2	*
	3	* Intel Ethernet Controller XL710 Family Linux Driver
	4	* Copyright(c) 2013 Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	*
	19	* The full GNU General Public License is included in this distribution in
	20	* the file called "COPYING".
	21	*
	22	* Contact Information:
	23	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25	*
	26	******************************************************************************/
	27
	28	/* Interrupt Throttling and Rate Limiting (storm control) Goodies */
	29
	30	#define I40E_MAX_ITR 0x07FF
	31	#define I40E_MIN_ITR 0x0001
	32	#define I40E_ITR_USEC_RESOLUTION 2
	33	#define I40E_MAX_IRATE 0x03F
	34	#define I40E_MIN_IRATE 0x001
	35	#define I40E_IRATE_USEC_RESOLUTION 4
	36	#define I40E_ITR_100K 0x0005
	37	#define I40E_ITR_20K 0x0019
	38	#define I40E_ITR_8K 0x003E
	39	#define I40E_ITR_4K 0x007A
	40	#define I40E_ITR_RX_DEF I40E_ITR_8K
	41	#define I40E_ITR_TX_DEF I40E_ITR_4K
	42	#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
	43	#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */
	44	#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */
	45	#define I40E_DEFAULT_IRQ_WORK 256
	46	#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
	47	#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
	48	#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
	49
	50	#define I40E_QUEUE_END_OF_LIST 0x7FF
	51
	52	#define I40E_ITR_NONE 3
	53	#define I40E_RX_ITR 0
	54	#define I40E_TX_ITR 1
	55	#define I40E_PE_ITR 2
	56	/* Supported Rx Buffer Sizes */
	57	#define I40E_RXBUFFER_512 512 /* Used for packet split */
	58	#define I40E_RXBUFFER_2048 2048
	59	#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */
	60	#define I40E_RXBUFFER_4096 4096
	61	#define I40E_RXBUFFER_8192 8192
	62	#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */
	63
	64	/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
65	* reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
66	* this adds up to 512 bytes of extra data meaning the smallest allocation
67	* we could have is 1K.
68	* i.e. RXBUFFER_512 --> size-1024 slab
69	*/
70	#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512
71
72	/* How many Rx Buffers do we bundle into one write to the hardware ? */
73	#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
74	#define I40E_RX_NEXT_DESC(r, i, n) \
75	do { \
76	(i)++; \
77	if ((i) == (r)->count) \
78	i = 0; \
79	(n) = I40E_RX_DESC((r), (i)); \
80	} while (0)
81
82	#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
83	do { \
84	I40E_RX_NEXT_DESC((r), (i), (n)); \
85	prefetch((n)); \
86	} while (0)
87
88	#define i40e_rx_desc i40e_32byte_rx_desc
89
90	#define I40E_MIN_TX_LEN 17
91	#define I40E_MAX_DATA_PER_TXD 16383 /* aka 16kB - 1 */
92
93	/* Tx Descriptors needed, worst case */
94	#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
95	#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
96
97	#define I40E_TX_FLAGS_CSUM (u32)(1)
98	#define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1)
99	#define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2)
100	#define I40E_TX_FLAGS_TSO (u32)(1 << 3)
101	#define I40E_TX_FLAGS_IPV4 (u32)(1 << 4)
102	#define I40E_TX_FLAGS_IPV6 (u32)(1 << 5)
103	#define I40E_TX_FLAGS_FCCRC (u32)(1 << 6)
104	#define I40E_TX_FLAGS_FSO (u32)(1 << 7)
105	#define I40E_TX_FLAGS_TXSW (u32)(1 << 8)
106	#define I40E_TX_FLAGS_MAPPED_AS_PAGE (u32)(1 << 9)
107	#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000
108	#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
109	#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29
110	#define I40E_TX_FLAGS_VLAN_SHIFT 16
111
112	struct i40e_tx_buffer {
113	struct sk_buff *skb;
114	dma_addr_t dma;
115	unsigned long time_stamp;
116	u16 length;
117	u32 tx_flags;
118	struct i40e_tx_desc *next_to_watch;
119	unsigned int bytecount;
120	u16 gso_segs;
121	u8 mapped_as_page;
122	};
123
124	struct i40e_rx_buffer {
125	struct sk_buff *skb;
126	dma_addr_t dma;
127	struct page *page;
128	dma_addr_t page_dma;
129	unsigned int page_offset;
130	};
131
132	struct i40e_tx_queue_stats {
133	u64 packets;
134	u64 bytes;
135	u64 restart_queue;
136	u64 tx_busy;
137	u64 completed;
138	u64 tx_done_old;
139	};
140
141	struct i40e_rx_queue_stats {
142	u64 packets;
143	u64 bytes;
144	u64 non_eop_descs;
145	u64 alloc_rx_page_failed;
146	u64 alloc_rx_buff_failed;
147	};
148
149	enum i40e_ring_state_t {
150	__I40E_TX_FDIR_INIT_DONE,
151	__I40E_TX_XPS_INIT_DONE,
152	__I40E_TX_DETECT_HANG,
153	__I40E_HANG_CHECK_ARMED,
154	__I40E_RX_PS_ENABLED,
155	__I40E_RX_LRO_ENABLED,
156	__I40E_RX_16BYTE_DESC_ENABLED,
157	};
158
159	#define ring_is_ps_enabled(ring) \
160	test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
161	#define set_ring_ps_enabled(ring) \
162	set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
163	#define clear_ring_ps_enabled(ring) \
164	clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
165	#define check_for_tx_hang(ring) \
166	test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
167	#define set_check_for_tx_hang(ring) \
168	set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
169	#define clear_check_for_tx_hang(ring) \
170	clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
171	#define ring_is_lro_enabled(ring) \
172	test_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
173	#define set_ring_lro_enabled(ring) \
174	set_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
175	#define clear_ring_lro_enabled(ring) \
176	clear_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
177	#define ring_is_16byte_desc_enabled(ring) \
178	test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
179	#define set_ring_16byte_desc_enabled(ring) \
180	set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
181	#define clear_ring_16byte_desc_enabled(ring) \
182	clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
183
184	/* struct that defines a descriptor ring, associated with a VSI */
185	struct i40e_ring {
186	void desc; / Descriptor ring memory */
187	struct device dev; / Used for DMA mapping */
188	struct net_device netdev; / netdev ring maps to */
189	union {
190	struct i40e_tx_buffer *tx_bi;
191	struct i40e_rx_buffer *rx_bi;
192	};
193	unsigned long state;
194	u16 queue_index; /* Queue number of ring */
195	u8 dcb_tc; /* Traffic class of ring */
196	u8 __iomem *tail;
197
198	u16 count; /* Number of descriptors */
199	u16 reg_idx; /* HW register index of the ring */
200	u16 rx_hdr_len;
201	u16 rx_buf_len;
202	u8 dtype;
203	#define I40E_RX_DTYPE_NO_SPLIT 0
204	#define I40E_RX_DTYPE_SPLIT_ALWAYS 1
205	#define I40E_RX_DTYPE_HEADER_SPLIT 2
206	u8 hsplit;
207	#define I40E_RX_SPLIT_L2 0x1
208	#define I40E_RX_SPLIT_IP 0x2
209	#define I40E_RX_SPLIT_TCP_UDP 0x4
210	#define I40E_RX_SPLIT_SCTP 0x8
211
212	/* used in interrupt processing */
213	u16 next_to_use;
214	u16 next_to_clean;
215
216	u8 atr_sample_rate;
217	u8 atr_count;
218
219	bool ring_active; /* is ring online or not */
220
221	/* stats structs */
222	union {
223	struct i40e_tx_queue_stats tx_stats;
224	struct i40e_rx_queue_stats rx_stats;
225	};
226
227	unsigned int size; /* length of descriptor ring in bytes */
228	dma_addr_t dma; /* physical address of ring */
229
230	struct i40e_vsi vsi; / Backreference to associated VSI */
231	struct i40e_q_vector q_vector; / Backreference to associated vector */
232	} ____cacheline_internodealigned_in_smp;
233
234	enum i40e_latency_range {
235	I40E_LOWEST_LATENCY = 0,
236	I40E_LOW_LATENCY = 1,
237	I40E_BULK_LATENCY = 2,
238	};
239
240	struct i40e_ring_container {
241	#define I40E_MAX_RINGPAIR_PER_VECTOR 8
242	/* array of pointers to rings */
243	struct i40e_ring *ring[I40E_MAX_RINGPAIR_PER_VECTOR];
244	unsigned int total_bytes; /* total bytes processed this int */
245	unsigned int total_packets; /* total packets processed this int */
246	u16 count;
247	enum i40e_latency_range latency_range;
248	u16 itr;
249	};
250
251	void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
252	netdev_tx_t i40e_lan_xmit_frame(struct sk_buff skb, struct net_device netdev);
253	void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
254	void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
255	int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
256	int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
257	void i40e_free_tx_resources(struct i40e_ring *tx_ring);
258	void i40e_free_rx_resources(struct i40e_ring *rx_ring);
259	int i40e_napi_poll(struct napi_struct *napi, int budget);