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[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
ded7b9a3 42#define DRV_VERSION_BUILD 46
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
83
84#define I40E_MAX_VF_COUNT 128
85static int debug = -1;
86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
90MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/**
95 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
96 * @hw: pointer to the HW structure
97 * @mem: ptr to mem struct to fill out
98 * @size: size of memory requested
99 * @alignment: what to align the allocation to
100 **/
101int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
102 u64 size, u32 alignment)
103{
104 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
105
106 mem->size = ALIGN(size, alignment);
107 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
108 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 109 if (!mem->va)
110 return -ENOMEM;
41c445ff 111
93bc73b8 112 return 0;
41c445ff
JB		 113}
114
115/**
116 * i40e_free_dma_mem_d - OS specific memory free for shared code
117 * @hw: pointer to the HW structure
118 * @mem: ptr to mem struct to free
119 **/
120int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
125 mem->va = NULL;
126 mem->pa = 0;
127 mem->size = 0;
128
129 return 0;
130}
131
132/**
133 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
134 * @hw: pointer to the HW structure
135 * @mem: ptr to mem struct to fill out
136 * @size: size of memory requested
137 **/
138int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
139 u32 size)
140{
141 mem->size = size;
142 mem->va = kzalloc(size, GFP_KERNEL);
143
93bc73b8
JB		 144 if (!mem->va)
145 return -ENOMEM;
41c445ff 146
93bc73b8 147 return 0;
41c445ff
JB		 148}
149
150/**
151 * i40e_free_virt_mem_d - OS specific memory free for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to free
154 **/
155int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
156{
157 /* it's ok to kfree a NULL pointer */
158 kfree(mem->va);
159 mem->va = NULL;
160 mem->size = 0;
161
162 return 0;
163}
164
165/**
166 * i40e_get_lump - find a lump of free generic resource
167 * @pf: board private structure
168 * @pile: the pile of resource to search
169 * @needed: the number of items needed
170 * @id: an owner id to stick on the items assigned
171 *
172 * Returns the base item index of the lump, or negative for error
173 *
174 * The search_hint trick and lack of advanced fit-finding only work
175 * because we're highly likely to have all the same size lump requests.
176 * Linear search time and any fragmentation should be minimal.
177 **/
178static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
179 u16 needed, u16 id)
180{
181 int ret = -ENOMEM;
ddf434ac 182 int i, j;
41c445ff
JB		 183
184 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
185 dev_info(&pf->pdev->dev,
186 "param err: pile=%p needed=%d id=0x%04x\n",
187 pile, needed, id);
188 return -EINVAL;
189 }
190
191 /* start the linear search with an imperfect hint */
192 i = pile->search_hint;
ddf434ac 193 while (i < pile->num_entries) {
41c445ff
JB		 194 /* skip already allocated entries */
195 if (pile->list[i] & I40E_PILE_VALID_BIT) {
196 i++;
197 continue;
198 }
199
200 /* do we have enough in this lump? */
201 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
202 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
203 break;
204 }
205
206 if (j == needed) {
207 /* there was enough, so assign it to the requestor */
208 for (j = 0; j < needed; j++)
209 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
210 ret = i;
211 pile->search_hint = i + j;
ddf434ac 212 break;
41c445ff
JB		 213 } else {
214 /* not enough, so skip over it and continue looking */
215 i += j;
216 }
217 }
218
219 return ret;
220}
221
222/**
223 * i40e_put_lump - return a lump of generic resource
224 * @pile: the pile of resource to search
225 * @index: the base item index
226 * @id: the owner id of the items assigned
227 *
228 * Returns the count of items in the lump
229 **/
230static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
231{
232 int valid_id = (id | I40E_PILE_VALID_BIT);
233 int count = 0;
234 int i;
235
236 if (!pile || index >= pile->num_entries)
237 return -EINVAL;
238
239 for (i = index;
240 i < pile->num_entries && pile->list[i] == valid_id;
241 i++) {
242 pile->list[i] = 0;
243 count++;
244 }
245
246 if (count && index < pile->search_hint)
247 pile->search_hint = index;
248
249 return count;
250}
251
252/**
253 * i40e_service_event_schedule - Schedule the service task to wake up
254 * @pf: board private structure
255 *
256 * If not already scheduled, this puts the task into the work queue
257 **/
258static void i40e_service_event_schedule(struct i40e_pf *pf)
259{
260 if (!test_bit(__I40E_DOWN, &pf->state) &&
261 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
262 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
263 schedule_work(&pf->service_task);
264}
265
266/**
267 * i40e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 *
270 * If any port has noticed a Tx timeout, it is likely that the whole
271 * device is munged, not just the one netdev port, so go for the full
272 * reset.
273 **/
274static void i40e_tx_timeout(struct net_device *netdev)
275{
276 struct i40e_netdev_priv *np = netdev_priv(netdev);
277 struct i40e_vsi *vsi = np->vsi;
278 struct i40e_pf *pf = vsi->back;
279
280 pf->tx_timeout_count++;
281
282 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
283 pf->tx_timeout_recovery_level = 0;
284 pf->tx_timeout_last_recovery = jiffies;
285 netdev_info(netdev, "tx_timeout recovery level %d\n",
286 pf->tx_timeout_recovery_level);
287
288 switch (pf->tx_timeout_recovery_level) {
289 case 0:
290 /* disable and re-enable queues for the VSI */
291 if (in_interrupt()) {
292 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
293 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
294 } else {
295 i40e_vsi_reinit_locked(vsi);
296 }
297 break;
298 case 1:
299 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
300 break;
301 case 2:
302 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
303 break;
304 case 3:
305 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
306 break;
307 default:
308 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 309 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 310 i40e_down(vsi);
311 break;
312 }
313 i40e_service_event_schedule(pf);
314 pf->tx_timeout_recovery_level++;
315}
316
317/**
318 * i40e_release_rx_desc - Store the new tail and head values
319 * @rx_ring: ring to bump
320 * @val: new head index
321 **/
322static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
323{
324 rx_ring->next_to_use = val;
325
326 /* Force memory writes to complete before letting h/w
327 * know there are new descriptors to fetch. (Only
328 * applicable for weak-ordered memory model archs,
329 * such as IA-64).
330 */
331 wmb();
332 writel(val, rx_ring->tail);
333}
334
335/**
336 * i40e_get_vsi_stats_struct - Get System Network Statistics
337 * @vsi: the VSI we care about
338 *
339 * Returns the address of the device statistics structure.
340 * The statistics are actually updated from the service task.
341 **/
342struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
343{
344 return &vsi->net_stats;
345}
346
347/**
348 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
349 * @netdev: network interface device structure
350 *
351 * Returns the address of the device statistics structure.
352 * The statistics are actually updated from the service task.
353 **/
354static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
355 struct net_device *netdev,
980e9b11 356 struct rtnl_link_stats64 *stats)
41c445ff
JB		 357{
358 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 359 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 360 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 361 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
362 int i;
363
bc7d338f
ASJ		 364 if (test_bit(__I40E_DOWN, &vsi->state))
365 return stats;
366
3c325ced
JB		 367 if (!vsi->tx_rings)
368 return stats;
369
980e9b11
AD		 370 rcu_read_lock();
371 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 372 u64 bytes, packets;
373 unsigned int start;
374
375 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
376 if (!tx_ring)
377 continue;
378
379 do {
57a7744e 380 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 381 packets = tx_ring->stats.packets;
382 bytes = tx_ring->stats.bytes;
57a7744e 383 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 384
385 stats->tx_packets += packets;
386 stats->tx_bytes += bytes;
387 rx_ring = &tx_ring[1];
388
389 do {
57a7744e 390 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 391 packets = rx_ring->stats.packets;
392 bytes = rx_ring->stats.bytes;
57a7744e 393 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 394
980e9b11
AD		 395 stats->rx_packets += packets;
396 stats->rx_bytes += bytes;
397 }
398 rcu_read_unlock();
399
400 /* following stats updated by ixgbe_watchdog_task() */
401 stats->multicast = vsi_stats->multicast;
402 stats->tx_errors = vsi_stats->tx_errors;
403 stats->tx_dropped = vsi_stats->tx_dropped;
404 stats->rx_errors = vsi_stats->rx_errors;
405 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
406 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 407
980e9b11 408 return stats;
41c445ff
JB		 409}
410
411/**
412 * i40e_vsi_reset_stats - Resets all stats of the given vsi
413 * @vsi: the VSI to have its stats reset
414 **/
415void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
416{
417 struct rtnl_link_stats64 *ns;
418 int i;
419
420 if (!vsi)
421 return;
422
423 ns = i40e_get_vsi_stats_struct(vsi);
424 memset(ns, 0, sizeof(*ns));
425 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
426 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
427 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 428 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 429 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 430 memset(&vsi->rx_rings[i]->stats, 0 ,
431 sizeof(vsi->rx_rings[i]->stats));
432 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
433 sizeof(vsi->rx_rings[i]->rx_stats));
434 memset(&vsi->tx_rings[i]->stats, 0 ,
435 sizeof(vsi->tx_rings[i]->stats));
436 memset(&vsi->tx_rings[i]->tx_stats, 0,
437 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 438 }
8e9dca53 439 }
41c445ff
JB		 440 vsi->stat_offsets_loaded = false;
441}
442
443/**
444 * i40e_pf_reset_stats - Reset all of the stats for the given pf
445 * @pf: the PF to be reset
446 **/
447void i40e_pf_reset_stats(struct i40e_pf *pf)
448{
449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
452}
453
454/**
455 * i40e_stat_update48 - read and update a 48 bit stat from the chip
456 * @hw: ptr to the hardware info
457 * @hireg: the high 32 bit reg to read
458 * @loreg: the low 32 bit reg to read
459 * @offset_loaded: has the initial offset been loaded yet
460 * @offset: ptr to current offset value
461 * @stat: ptr to the stat
462 *
463 * Since the device stats are not reset at PFReset, they likely will not
464 * be zeroed when the driver starts. We'll save the first values read
465 * and use them as offsets to be subtracted from the raw values in order
466 * to report stats that count from zero. In the process, we also manage
467 * the potential roll-over.
468 **/
469static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
470 bool offset_loaded, u64 *offset, u64 *stat)
471{
472 u64 new_data;
473
ab60085e 474 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 475 new_data = rd32(hw, loreg);
476 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
477 } else {
478 new_data = rd64(hw, loreg);
479 }
480 if (!offset_loaded)
481 *offset = new_data;
482 if (likely(new_data >= *offset))
483 *stat = new_data - *offset;
484 else
485 *stat = (new_data + ((u64)1 << 48)) - *offset;
486 *stat &= 0xFFFFFFFFFFFFULL;
487}
488
489/**
490 * i40e_stat_update32 - read and update a 32 bit stat from the chip
491 * @hw: ptr to the hardware info
492 * @reg: the hw reg to read
493 * @offset_loaded: has the initial offset been loaded yet
494 * @offset: ptr to current offset value
495 * @stat: ptr to the stat
496 **/
497static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
498 bool offset_loaded, u64 *offset, u64 *stat)
499{
500 u32 new_data;
501
502 new_data = rd32(hw, reg);
503 if (!offset_loaded)
504 *offset = new_data;
505 if (likely(new_data >= *offset))
506 *stat = (u32)(new_data - *offset);
507 else
508 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
509}
510
511/**
512 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
513 * @vsi: the VSI to be updated
514 **/
515void i40e_update_eth_stats(struct i40e_vsi *vsi)
516{
517 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
518 struct i40e_pf *pf = vsi->back;
519 struct i40e_hw *hw = &pf->hw;
520 struct i40e_eth_stats *oes;
521 struct i40e_eth_stats *es; /* device's eth stats */
522
523 es = &vsi->eth_stats;
524 oes = &vsi->eth_stats_offsets;
525
526 /* Gather up the stats that the hw collects */
527 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->tx_errors, &es->tx_errors);
530 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
531 vsi->stat_offsets_loaded,
532 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 533 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
534 vsi->stat_offsets_loaded,
535 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
536 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
537 vsi->stat_offsets_loaded,
538 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 539
540 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
541 I40E_GLV_GORCL(stat_idx),
542 vsi->stat_offsets_loaded,
543 &oes->rx_bytes, &es->rx_bytes);
544 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
545 I40E_GLV_UPRCL(stat_idx),
546 vsi->stat_offsets_loaded,
547 &oes->rx_unicast, &es->rx_unicast);
548 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
549 I40E_GLV_MPRCL(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->rx_multicast, &es->rx_multicast);
552 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
553 I40E_GLV_BPRCL(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->rx_broadcast, &es->rx_broadcast);
556
557 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
558 I40E_GLV_GOTCL(stat_idx),
559 vsi->stat_offsets_loaded,
560 &oes->tx_bytes, &es->tx_bytes);
561 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
562 I40E_GLV_UPTCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->tx_unicast, &es->tx_unicast);
565 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
566 I40E_GLV_MPTCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->tx_multicast, &es->tx_multicast);
569 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
570 I40E_GLV_BPTCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->tx_broadcast, &es->tx_broadcast);
573 vsi->stat_offsets_loaded = true;
574}
575
576/**
577 * i40e_update_veb_stats - Update Switch component statistics
578 * @veb: the VEB being updated
579 **/
580static void i40e_update_veb_stats(struct i40e_veb *veb)
581{
582 struct i40e_pf *pf = veb->pf;
583 struct i40e_hw *hw = &pf->hw;
584 struct i40e_eth_stats *oes;
585 struct i40e_eth_stats *es; /* device's eth stats */
586 int idx = 0;
587
588 idx = veb->stats_idx;
589 es = &veb->stats;
590 oes = &veb->stats_offsets;
591
592 /* Gather up the stats that the hw collects */
593 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
594 veb->stat_offsets_loaded,
595 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 596 if (hw->revision_id > 0)
597 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
598 veb->stat_offsets_loaded,
599 &oes->rx_unknown_protocol,
600 &es->rx_unknown_protocol);
41c445ff
JB		 601 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_bytes, &es->rx_bytes);
604 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->rx_unicast, &es->rx_unicast);
607 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
608 veb->stat_offsets_loaded,
609 &oes->rx_multicast, &es->rx_multicast);
610 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
611 veb->stat_offsets_loaded,
612 &oes->rx_broadcast, &es->rx_broadcast);
613
614 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_bytes, &es->tx_bytes);
617 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->tx_unicast, &es->tx_unicast);
620 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
621 veb->stat_offsets_loaded,
622 &oes->tx_multicast, &es->tx_multicast);
623 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
624 veb->stat_offsets_loaded,
625 &oes->tx_broadcast, &es->tx_broadcast);
626 veb->stat_offsets_loaded = true;
627}
628
629/**
630 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
631 * @pf: the corresponding PF
632 *
633 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
634 **/
635static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
636{
637 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
638 struct i40e_hw_port_stats *nsd = &pf->stats;
639 struct i40e_hw *hw = &pf->hw;
640 u64 xoff = 0;
641 u16 i, v;
642
643 if ((hw->fc.current_mode != I40E_FC_FULL) &&
644 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
645 return;
646
647 xoff = nsd->link_xoff_rx;
648 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
649 pf->stat_offsets_loaded,
650 &osd->link_xoff_rx, &nsd->link_xoff_rx);
651
652 /* No new LFC xoff rx */
653 if (!(nsd->link_xoff_rx - xoff))
654 return;
655
656 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
657 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
658 struct i40e_vsi *vsi = pf->vsi[v];
659
660 if (!vsi)
661 continue;
662
663 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 664 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 665 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
666 }
667 }
668}
669
670/**
671 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
672 * @pf: the corresponding PF
673 *
674 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
675 **/
676static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
677{
678 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
679 struct i40e_hw_port_stats *nsd = &pf->stats;
680 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
681 struct i40e_dcbx_config *dcb_cfg;
682 struct i40e_hw *hw = &pf->hw;
683 u16 i, v;
684 u8 tc;
685
686 dcb_cfg = &hw->local_dcbx_config;
687
688 /* See if DCB enabled with PFC TC */
689 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
690 !(dcb_cfg->pfc.pfcenable)) {
691 i40e_update_link_xoff_rx(pf);
692 return;
693 }
694
695 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
696 u64 prio_xoff = nsd->priority_xoff_rx[i];
697 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
698 pf->stat_offsets_loaded,
699 &osd->priority_xoff_rx[i],
700 &nsd->priority_xoff_rx[i]);
701
702 /* No new PFC xoff rx */
703 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
704 continue;
705 /* Get the TC for given priority */
706 tc = dcb_cfg->etscfg.prioritytable[i];
707 xoff[tc] = true;
708 }
709
710 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
711 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
712 struct i40e_vsi *vsi = pf->vsi[v];
713
714 if (!vsi)
715 continue;
716
717 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 718 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 719
720 tc = ring->dcb_tc;
721 if (xoff[tc])
722 clear_bit(__I40E_HANG_CHECK_ARMED,
723 &ring->state);
724 }
725 }
726}
727
728/**
7812fddc 729 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 730 * @vsi: the VSI to be updated
731 *
732 * There are a few instances where we store the same stat in a
733 * couple of different structs. This is partly because we have
734 * the netdev stats that need to be filled out, which is slightly
735 * different from the "eth_stats" defined by the chip and used in
7812fddc 736 * VF communications. We sort it out here.
41c445ff 737 **/
7812fddc 738static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 739{
740 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 741 struct rtnl_link_stats64 *ons;
742 struct rtnl_link_stats64 *ns; /* netdev stats */
743 struct i40e_eth_stats *oes;
744 struct i40e_eth_stats *es; /* device's eth stats */
745 u32 tx_restart, tx_busy;
746 u32 rx_page, rx_buf;
747 u64 rx_p, rx_b;
748 u64 tx_p, tx_b;
41c445ff
JB		 749 u16 q;
750
751 if (test_bit(__I40E_DOWN, &vsi->state) ||
752 test_bit(__I40E_CONFIG_BUSY, &pf->state))
753 return;
754
755 ns = i40e_get_vsi_stats_struct(vsi);
756 ons = &vsi->net_stats_offsets;
757 es = &vsi->eth_stats;
758 oes = &vsi->eth_stats_offsets;
759
760 /* Gather up the netdev and vsi stats that the driver collects
761 * on the fly during packet processing
762 */
763 rx_b = rx_p = 0;
764 tx_b = tx_p = 0;
765 tx_restart = tx_busy = 0;
766 rx_page = 0;
767 rx_buf = 0;
980e9b11 768 rcu_read_lock();
41c445ff
JB		 769 for (q = 0; q < vsi->num_queue_pairs; q++) {
770 struct i40e_ring *p;
980e9b11
AD		 771 u64 bytes, packets;
772 unsigned int start;
773
774 /* locate Tx ring */
775 p = ACCESS_ONCE(vsi->tx_rings[q]);
776
777 do {
57a7744e 778 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 779 packets = p->stats.packets;
780 bytes = p->stats.bytes;
57a7744e 781 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 782 tx_b += bytes;
783 tx_p += packets;
784 tx_restart += p->tx_stats.restart_queue;
785 tx_busy += p->tx_stats.tx_busy;
41c445ff 786
980e9b11
AD		 787 /* Rx queue is part of the same block as Tx queue */
788 p = &p[1];
789 do {
57a7744e 790 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 791 packets = p->stats.packets;
792 bytes = p->stats.bytes;
57a7744e 793 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 794 rx_b += bytes;
795 rx_p += packets;
420136cc
MW		 796 rx_buf += p->rx_stats.alloc_buff_failed;
797 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 798 }
980e9b11 799 rcu_read_unlock();
41c445ff
JB		 800 vsi->tx_restart = tx_restart;
801 vsi->tx_busy = tx_busy;
802 vsi->rx_page_failed = rx_page;
803 vsi->rx_buf_failed = rx_buf;
804
805 ns->rx_packets = rx_p;
806 ns->rx_bytes = rx_b;
807 ns->tx_packets = tx_p;
808 ns->tx_bytes = tx_b;
809
41c445ff 810 /* update netdev stats from eth stats */
7812fddc 811 i40e_update_eth_stats(vsi);
41c445ff
JB		 812 ons->tx_errors = oes->tx_errors;
813 ns->tx_errors = es->tx_errors;
814 ons->multicast = oes->rx_multicast;
815 ns->multicast = es->rx_multicast;
41a9e55c
SN		 816 ons->rx_dropped = oes->rx_discards;
817 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 818 ons->tx_dropped = oes->tx_discards;
819 ns->tx_dropped = es->tx_discards;
820
7812fddc 821 /* pull in a couple PF stats if this is the main vsi */
41c445ff 822 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 823 ns->rx_crc_errors = pf->stats.crc_errors;
824 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
825 ns->rx_length_errors = pf->stats.rx_length_errors;
826 }
827}
41c445ff 828
7812fddc
SN		 829/**
830 * i40e_update_pf_stats - Update the pf statistics counters.
831 * @pf: the PF to be updated
832 **/
833static void i40e_update_pf_stats(struct i40e_pf *pf)
834{
835 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
836 struct i40e_hw_port_stats *nsd = &pf->stats;
837 struct i40e_hw *hw = &pf->hw;
838 u32 val;
839 int i;
41c445ff 840
7812fddc
SN		 841 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
842 I40E_GLPRT_GORCL(hw->port),
843 pf->stat_offsets_loaded,
844 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
845 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
846 I40E_GLPRT_GOTCL(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
849 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
850 pf->stat_offsets_loaded,
851 &osd->eth.rx_discards,
852 &nsd->eth.rx_discards);
853 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
854 pf->stat_offsets_loaded,
855 &osd->eth.tx_discards,
856 &nsd->eth.tx_discards);
532d283d
SN		 857
858 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
859 I40E_GLPRT_UPRCL(hw->port),
860 pf->stat_offsets_loaded,
861 &osd->eth.rx_unicast,
862 &nsd->eth.rx_unicast);
7812fddc
SN		 863 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
864 I40E_GLPRT_MPRCL(hw->port),
865 pf->stat_offsets_loaded,
866 &osd->eth.rx_multicast,
867 &nsd->eth.rx_multicast);
532d283d
SN		 868 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
869 I40E_GLPRT_BPRCL(hw->port),
870 pf->stat_offsets_loaded,
871 &osd->eth.rx_broadcast,
872 &nsd->eth.rx_broadcast);
873 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
874 I40E_GLPRT_UPTCL(hw->port),
875 pf->stat_offsets_loaded,
876 &osd->eth.tx_unicast,
877 &nsd->eth.tx_unicast);
878 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
879 I40E_GLPRT_MPTCL(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->eth.tx_multicast,
882 &nsd->eth.tx_multicast);
883 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
884 I40E_GLPRT_BPTCL(hw->port),
885 pf->stat_offsets_loaded,
886 &osd->eth.tx_broadcast,
887 &nsd->eth.tx_broadcast);
41c445ff 888
7812fddc
SN		 889 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
890 pf->stat_offsets_loaded,
891 &osd->tx_dropped_link_down,
892 &nsd->tx_dropped_link_down);
41c445ff 893
7812fddc
SN		 894 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
895 pf->stat_offsets_loaded,
896 &osd->crc_errors, &nsd->crc_errors);
41c445ff 897
7812fddc
SN		 898 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
899 pf->stat_offsets_loaded,
900 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 901
7812fddc
SN		 902 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
903 pf->stat_offsets_loaded,
904 &osd->mac_local_faults,
905 &nsd->mac_local_faults);
906 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
907 pf->stat_offsets_loaded,
908 &osd->mac_remote_faults,
909 &nsd->mac_remote_faults);
41c445ff 910
7812fddc
SN		 911 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->rx_length_errors,
914 &nsd->rx_length_errors);
41c445ff 915
7812fddc
SN		 916 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->link_xon_rx, &nsd->link_xon_rx);
919 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
920 pf->stat_offsets_loaded,
921 &osd->link_xon_tx, &nsd->link_xon_tx);
922 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
923 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 926
7812fddc
SN		 927 for (i = 0; i < 8; i++) {
928 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 929 pf->stat_offsets_loaded,
7812fddc
SN		 930 &osd->priority_xon_rx[i],
931 &nsd->priority_xon_rx[i]);
932 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 933 pf->stat_offsets_loaded,
7812fddc
SN		 934 &osd->priority_xon_tx[i],
935 &nsd->priority_xon_tx[i]);
936 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 937 pf->stat_offsets_loaded,
7812fddc
SN		 938 &osd->priority_xoff_tx[i],
939 &nsd->priority_xoff_tx[i]);
940 i40e_stat_update32(hw,
941 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
41c445ff 942 pf->stat_offsets_loaded,
7812fddc
SN		 943 &osd->priority_xon_2_xoff[i],
944 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 945 }
946
7812fddc
SN		 947 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
948 I40E_GLPRT_PRC64L(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->rx_size_64, &nsd->rx_size_64);
951 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
952 I40E_GLPRT_PRC127L(hw->port),
953 pf->stat_offsets_loaded,
954 &osd->rx_size_127, &nsd->rx_size_127);
955 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
956 I40E_GLPRT_PRC255L(hw->port),
957 pf->stat_offsets_loaded,
958 &osd->rx_size_255, &nsd->rx_size_255);
959 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
960 I40E_GLPRT_PRC511L(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->rx_size_511, &nsd->rx_size_511);
963 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
964 I40E_GLPRT_PRC1023L(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_size_1023, &nsd->rx_size_1023);
967 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
968 I40E_GLPRT_PRC1522L(hw->port),
969 pf->stat_offsets_loaded,
970 &osd->rx_size_1522, &nsd->rx_size_1522);
971 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
972 I40E_GLPRT_PRC9522L(hw->port),
973 pf->stat_offsets_loaded,
974 &osd->rx_size_big, &nsd->rx_size_big);
975
976 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
977 I40E_GLPRT_PTC64L(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->tx_size_64, &nsd->tx_size_64);
980 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
981 I40E_GLPRT_PTC127L(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->tx_size_127, &nsd->tx_size_127);
984 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
985 I40E_GLPRT_PTC255L(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->tx_size_255, &nsd->tx_size_255);
988 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
989 I40E_GLPRT_PTC511L(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->tx_size_511, &nsd->tx_size_511);
992 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
993 I40E_GLPRT_PTC1023L(hw->port),
994 pf->stat_offsets_loaded,
995 &osd->tx_size_1023, &nsd->tx_size_1023);
996 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
997 I40E_GLPRT_PTC1522L(hw->port),
998 pf->stat_offsets_loaded,
999 &osd->tx_size_1522, &nsd->tx_size_1522);
1000 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1001 I40E_GLPRT_PTC9522L(hw->port),
1002 pf->stat_offsets_loaded,
1003 &osd->tx_size_big, &nsd->tx_size_big);
1004
1005 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1006 pf->stat_offsets_loaded,
1007 &osd->rx_undersize, &nsd->rx_undersize);
1008 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1009 pf->stat_offsets_loaded,
1010 &osd->rx_fragments, &nsd->rx_fragments);
1011 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1012 pf->stat_offsets_loaded,
1013 &osd->rx_oversize, &nsd->rx_oversize);
1014 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->rx_jabber, &nsd->rx_jabber);
1017
1018 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1019 nsd->tx_lpi_status =
1020 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1021 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1022 nsd->rx_lpi_status =
1023 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1024 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1025 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1026 pf->stat_offsets_loaded,
1027 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1028 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1029 pf->stat_offsets_loaded,
1030 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1031
41c445ff
JB		 1032 pf->stat_offsets_loaded = true;
1033}
1034
7812fddc
SN		 1035/**
1036 * i40e_update_stats - Update the various statistics counters.
1037 * @vsi: the VSI to be updated
1038 *
1039 * Update the various stats for this VSI and its related entities.
1040 **/
1041void i40e_update_stats(struct i40e_vsi *vsi)
1042{
1043 struct i40e_pf *pf = vsi->back;
1044
1045 if (vsi == pf->vsi[pf->lan_vsi])
1046 i40e_update_pf_stats(pf);
1047
1048 i40e_update_vsi_stats(vsi);
1049}
1050
41c445ff
JB		 1051/**
1052 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1053 * @vsi: the VSI to be searched
1054 * @macaddr: the MAC address
1055 * @vlan: the vlan
1056 * @is_vf: make sure its a vf filter, else doesn't matter
1057 * @is_netdev: make sure its a netdev filter, else doesn't matter
1058 *
1059 * Returns ptr to the filter object or NULL
1060 **/
1061static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1062 u8 *macaddr, s16 vlan,
1063 bool is_vf, bool is_netdev)
1064{
1065 struct i40e_mac_filter *f;
1066
1067 if (!vsi || !macaddr)
1068 return NULL;
1069
1070 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1071 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1072 (vlan == f->vlan) &&
1073 (!is_vf || f->is_vf) &&
1074 (!is_netdev || f->is_netdev))
1075 return f;
1076 }
1077 return NULL;
1078}
1079
1080/**
1081 * i40e_find_mac - Find a mac addr in the macvlan filters list
1082 * @vsi: the VSI to be searched
1083 * @macaddr: the MAC address we are searching for
1084 * @is_vf: make sure its a vf filter, else doesn't matter
1085 * @is_netdev: make sure its a netdev filter, else doesn't matter
1086 *
1087 * Returns the first filter with the provided MAC address or NULL if
1088 * MAC address was not found
1089 **/
1090struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1091 bool is_vf, bool is_netdev)
1092{
1093 struct i40e_mac_filter *f;
1094
1095 if (!vsi || !macaddr)
1096 return NULL;
1097
1098 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1099 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1100 (!is_vf || f->is_vf) &&
1101 (!is_netdev || f->is_netdev))
1102 return f;
1103 }
1104 return NULL;
1105}
1106
1107/**
1108 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1109 * @vsi: the VSI to be searched
1110 *
1111 * Returns true if VSI is in vlan mode or false otherwise
1112 **/
1113bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1114{
1115 struct i40e_mac_filter *f;
1116
1117 /* Only -1 for all the filters denotes not in vlan mode
1118 * so we have to go through all the list in order to make sure
1119 */
1120 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1121 if (f->vlan >= 0)
1122 return true;
1123 }
1124
1125 return false;
1126}
1127
1128/**
1129 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1130 * @vsi: the VSI to be searched
1131 * @macaddr: the mac address to be filtered
1132 * @is_vf: true if it is a vf
1133 * @is_netdev: true if it is a netdev
1134 *
1135 * Goes through all the macvlan filters and adds a
1136 * macvlan filter for each unique vlan that already exists
1137 *
1138 * Returns first filter found on success, else NULL
1139 **/
1140struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1141 bool is_vf, bool is_netdev)
1142{
1143 struct i40e_mac_filter *f;
1144
1145 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1146 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1147 is_vf, is_netdev)) {
1148 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1149 is_vf, is_netdev))
41c445ff
JB		 1150 return NULL;
1151 }
1152 }
1153
1154 return list_first_entry_or_null(&vsi->mac_filter_list,
1155 struct i40e_mac_filter, list);
1156}
1157
1158/**
1159 * i40e_add_filter - Add a mac/vlan filter to the VSI
1160 * @vsi: the VSI to be searched
1161 * @macaddr: the MAC address
1162 * @vlan: the vlan
1163 * @is_vf: make sure its a vf filter, else doesn't matter
1164 * @is_netdev: make sure its a netdev filter, else doesn't matter
1165 *
1166 * Returns ptr to the filter object or NULL when no memory available.
1167 **/
1168struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1169 u8 *macaddr, s16 vlan,
1170 bool is_vf, bool is_netdev)
1171{
1172 struct i40e_mac_filter *f;
1173
1174 if (!vsi || !macaddr)
1175 return NULL;
1176
1177 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1178 if (!f) {
1179 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1180 if (!f)
1181 goto add_filter_out;
1182
1183 memcpy(f->macaddr, macaddr, ETH_ALEN);
1184 f->vlan = vlan;
1185 f->changed = true;
1186
1187 INIT_LIST_HEAD(&f->list);
1188 list_add(&f->list, &vsi->mac_filter_list);
1189 }
1190
1191 /* increment counter and add a new flag if needed */
1192 if (is_vf) {
1193 if (!f->is_vf) {
1194 f->is_vf = true;
1195 f->counter++;
1196 }
1197 } else if (is_netdev) {
1198 if (!f->is_netdev) {
1199 f->is_netdev = true;
1200 f->counter++;
1201 }
1202 } else {
1203 f->counter++;
1204 }
1205
1206 /* changed tells sync_filters_subtask to
1207 * push the filter down to the firmware
1208 */
1209 if (f->changed) {
1210 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1211 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1212 }
1213
1214add_filter_out:
1215 return f;
1216}
1217
1218/**
1219 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1220 * @vsi: the VSI to be searched
1221 * @macaddr: the MAC address
1222 * @vlan: the vlan
1223 * @is_vf: make sure it's a vf filter, else doesn't matter
1224 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1225 **/
1226void i40e_del_filter(struct i40e_vsi *vsi,
1227 u8 *macaddr, s16 vlan,
1228 bool is_vf, bool is_netdev)
1229{
1230 struct i40e_mac_filter *f;
1231
1232 if (!vsi || !macaddr)
1233 return;
1234
1235 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1236 if (!f || f->counter == 0)
1237 return;
1238
1239 if (is_vf) {
1240 if (f->is_vf) {
1241 f->is_vf = false;
1242 f->counter--;
1243 }
1244 } else if (is_netdev) {
1245 if (f->is_netdev) {
1246 f->is_netdev = false;
1247 f->counter--;
1248 }
1249 } else {
1250 /* make sure we don't remove a filter in use by vf or netdev */
1251 int min_f = 0;
1252 min_f += (f->is_vf ? 1 : 0);
1253 min_f += (f->is_netdev ? 1 : 0);
1254
1255 if (f->counter > min_f)
1256 f->counter--;
1257 }
1258
1259 /* counter == 0 tells sync_filters_subtask to
1260 * remove the filter from the firmware's list
1261 */
1262 if (f->counter == 0) {
1263 f->changed = true;
1264 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1265 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1266 }
1267}
1268
1269/**
1270 * i40e_set_mac - NDO callback to set mac address
1271 * @netdev: network interface device structure
1272 * @p: pointer to an address structure
1273 *
1274 * Returns 0 on success, negative on failure
1275 **/
1276static int i40e_set_mac(struct net_device *netdev, void *p)
1277{
1278 struct i40e_netdev_priv *np = netdev_priv(netdev);
1279 struct i40e_vsi *vsi = np->vsi;
1280 struct sockaddr *addr = p;
1281 struct i40e_mac_filter *f;
1282
1283 if (!is_valid_ether_addr(addr->sa_data))
1284 return -EADDRNOTAVAIL;
1285
1286 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1287
1288 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1289 return 0;
1290
80f6428f
ASJ		 1291 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1292 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1293 return -EADDRNOTAVAIL;
1294
41c445ff
JB		 1295 if (vsi->type == I40E_VSI_MAIN) {
1296 i40e_status ret;
1297 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1298 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1299 addr->sa_data, NULL);
1300 if (ret) {
1301 netdev_info(netdev,
1302 "Addr change for Main VSI failed: %d\n",
1303 ret);
1304 return -EADDRNOTAVAIL;
1305 }
1306
1307 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1308 }
1309
1310 /* In order to be sure to not drop any packets, add the new address
1311 * then delete the old one.
1312 */
1313 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1314 if (!f)
1315 return -ENOMEM;
1316
1317 i40e_sync_vsi_filters(vsi);
1318 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1319 i40e_sync_vsi_filters(vsi);
1320
1321 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1322
1323 return 0;
1324}
1325
1326/**
1327 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1328 * @vsi: the VSI being setup
1329 * @ctxt: VSI context structure
1330 * @enabled_tc: Enabled TCs bitmap
1331 * @is_add: True if called before Add VSI
1332 *
1333 * Setup VSI queue mapping for enabled traffic classes.
1334 **/
1335static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1336 struct i40e_vsi_context *ctxt,
1337 u8 enabled_tc,
1338 bool is_add)
1339{
1340 struct i40e_pf *pf = vsi->back;
1341 u16 sections = 0;
1342 u8 netdev_tc = 0;
1343 u16 numtc = 0;
1344 u16 qcount;
1345 u8 offset;
1346 u16 qmap;
1347 int i;
4e3b35b0 1348 u16 num_tc_qps = 0;
41c445ff
JB		 1349
1350 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1351 offset = 0;
1352
1353 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1354 /* Find numtc from enabled TC bitmap */
1355 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1356 if (enabled_tc & (1 << i)) /* TC is enabled */
1357 numtc++;
1358 }
1359 if (!numtc) {
1360 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1361 numtc = 1;
1362 }
1363 } else {
1364 /* At least TC0 is enabled in case of non-DCB case */
1365 numtc = 1;
1366 }
1367
1368 vsi->tc_config.numtc = numtc;
1369 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1370 /* Number of queues per enabled TC */
1371 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1372 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1373
1374 /* Setup queue offset/count for all TCs for given VSI */
1375 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1376 /* See if the given TC is enabled for the given VSI */
1377 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1378 int pow, num_qps;
1379
41c445ff
JB		 1380 switch (vsi->type) {
1381 case I40E_VSI_MAIN:
4e3b35b0 1382 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1383 break;
1384 case I40E_VSI_FDIR:
1385 case I40E_VSI_SRIOV:
1386 case I40E_VSI_VMDQ2:
1387 default:
4e3b35b0 1388 qcount = num_tc_qps;
41c445ff
JB		 1389 WARN_ON(i != 0);
1390 break;
1391 }
4e3b35b0
NP		 1392 vsi->tc_config.tc_info[i].qoffset = offset;
1393 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1394
1395 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1396 num_qps = qcount;
41c445ff 1397 pow = 0;
4e3b35b0 1398 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1399 pow++;
1400 num_qps >>= 1;
1401 }
1402
1403 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1404 qmap =
1405 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1406 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1407
4e3b35b0 1408 offset += qcount;
41c445ff
JB		 1409 } else {
1410 /* TC is not enabled so set the offset to
1411 * default queue and allocate one queue
1412 * for the given TC.
1413 */
1414 vsi->tc_config.tc_info[i].qoffset = 0;
1415 vsi->tc_config.tc_info[i].qcount = 1;
1416 vsi->tc_config.tc_info[i].netdev_tc = 0;
1417
1418 qmap = 0;
1419 }
1420 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1421 }
1422
1423 /* Set actual Tx/Rx queue pairs */
1424 vsi->num_queue_pairs = offset;
1425
1426 /* Scheduler section valid can only be set for ADD VSI */
1427 if (is_add) {
1428 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1429
1430 ctxt->info.up_enable_bits = enabled_tc;
1431 }
1432 if (vsi->type == I40E_VSI_SRIOV) {
1433 ctxt->info.mapping_flags |=
1434 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1435 for (i = 0; i < vsi->num_queue_pairs; i++)
1436 ctxt->info.queue_mapping[i] =
1437 cpu_to_le16(vsi->base_queue + i);
1438 } else {
1439 ctxt->info.mapping_flags |=
1440 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1441 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1442 }
1443 ctxt->info.valid_sections |= cpu_to_le16(sections);
1444}
1445
1446/**
1447 * i40e_set_rx_mode - NDO callback to set the netdev filters
1448 * @netdev: network interface device structure
1449 **/
1450static void i40e_set_rx_mode(struct net_device *netdev)
1451{
1452 struct i40e_netdev_priv *np = netdev_priv(netdev);
1453 struct i40e_mac_filter *f, *ftmp;
1454 struct i40e_vsi *vsi = np->vsi;
1455 struct netdev_hw_addr *uca;
1456 struct netdev_hw_addr *mca;
1457 struct netdev_hw_addr *ha;
1458
1459 /* add addr if not already in the filter list */
1460 netdev_for_each_uc_addr(uca, netdev) {
1461 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1462 if (i40e_is_vsi_in_vlan(vsi))
1463 i40e_put_mac_in_vlan(vsi, uca->addr,
1464 false, true);
1465 else
1466 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1467 false, true);
1468 }
1469 }
1470
1471 netdev_for_each_mc_addr(mca, netdev) {
1472 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1473 if (i40e_is_vsi_in_vlan(vsi))
1474 i40e_put_mac_in_vlan(vsi, mca->addr,
1475 false, true);
1476 else
1477 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1478 false, true);
1479 }
1480 }
1481
1482 /* remove filter if not in netdev list */
1483 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1484 bool found = false;
1485
1486 if (!f->is_netdev)
1487 continue;
1488
1489 if (is_multicast_ether_addr(f->macaddr)) {
1490 netdev_for_each_mc_addr(mca, netdev) {
1491 if (ether_addr_equal(mca->addr, f->macaddr)) {
1492 found = true;
1493 break;
1494 }
1495 }
1496 } else {
1497 netdev_for_each_uc_addr(uca, netdev) {
1498 if (ether_addr_equal(uca->addr, f->macaddr)) {
1499 found = true;
1500 break;
1501 }
1502 }
1503
1504 for_each_dev_addr(netdev, ha) {
1505 if (ether_addr_equal(ha->addr, f->macaddr)) {
1506 found = true;
1507 break;
1508 }
1509 }
1510 }
1511 if (!found)
1512 i40e_del_filter(
1513 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1514 }
1515
1516 /* check for other flag changes */
1517 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1518 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1519 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1520 }
1521}
1522
1523/**
1524 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1525 * @vsi: ptr to the VSI
1526 *
1527 * Push any outstanding VSI filter changes through the AdminQ.
1528 *
1529 * Returns 0 or error value
1530 **/
1531int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1532{
1533 struct i40e_mac_filter *f, *ftmp;
1534 bool promisc_forced_on = false;
1535 bool add_happened = false;
1536 int filter_list_len = 0;
1537 u32 changed_flags = 0;
dcae29be 1538 i40e_status aq_ret = 0;
41c445ff
JB		 1539 struct i40e_pf *pf;
1540 int num_add = 0;
1541 int num_del = 0;
1542 u16 cmd_flags;
1543
1544 /* empty array typed pointers, kcalloc later */
1545 struct i40e_aqc_add_macvlan_element_data *add_list;
1546 struct i40e_aqc_remove_macvlan_element_data *del_list;
1547
1548 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1549 usleep_range(1000, 2000);
1550 pf = vsi->back;
1551
1552 if (vsi->netdev) {
1553 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1554 vsi->current_netdev_flags = vsi->netdev->flags;
1555 }
1556
1557 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1558 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1559
1560 filter_list_len = pf->hw.aq.asq_buf_size /
1561 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1562 del_list = kcalloc(filter_list_len,
1563 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1564 GFP_KERNEL);
1565 if (!del_list)
1566 return -ENOMEM;
1567
1568 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1569 if (!f->changed)
1570 continue;
1571
1572 if (f->counter != 0)
1573 continue;
1574 f->changed = false;
1575 cmd_flags = 0;
1576
1577 /* add to delete list */
1578 memcpy(del_list[num_del].mac_addr,
1579 f->macaddr, ETH_ALEN);
1580 del_list[num_del].vlan_tag =
1581 cpu_to_le16((u16)(f->vlan ==
1582 I40E_VLAN_ANY ? 0 : f->vlan));
1583
41c445ff
JB		 1584 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1585 del_list[num_del].flags = cmd_flags;
1586 num_del++;
1587
1588 /* unlink from filter list */
1589 list_del(&f->list);
1590 kfree(f);
1591
1592 /* flush a full buffer */
1593 if (num_del == filter_list_len) {
dcae29be 1594 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1595 vsi->seid, del_list, num_del,
1596 NULL);
1597 num_del = 0;
1598 memset(del_list, 0, sizeof(*del_list));
1599
dcae29be 1600 if (aq_ret)
41c445ff
JB		 1601 dev_info(&pf->pdev->dev,
1602 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1603 aq_ret,
41c445ff
JB		 1604 pf->hw.aq.asq_last_status);
1605 }
1606 }
1607 if (num_del) {
dcae29be 1608 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1609 del_list, num_del, NULL);
1610 num_del = 0;
1611
dcae29be 1612 if (aq_ret)
41c445ff
JB		 1613 dev_info(&pf->pdev->dev,
1614 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1615 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1616 }
1617
1618 kfree(del_list);
1619 del_list = NULL;
1620
1621 /* do all the adds now */
1622 filter_list_len = pf->hw.aq.asq_buf_size /
1623 sizeof(struct i40e_aqc_add_macvlan_element_data),
1624 add_list = kcalloc(filter_list_len,
1625 sizeof(struct i40e_aqc_add_macvlan_element_data),
1626 GFP_KERNEL);
1627 if (!add_list)
1628 return -ENOMEM;
1629
1630 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1631 if (!f->changed)
1632 continue;
1633
1634 if (f->counter == 0)
1635 continue;
1636 f->changed = false;
1637 add_happened = true;
1638 cmd_flags = 0;
1639
1640 /* add to add array */
1641 memcpy(add_list[num_add].mac_addr,
1642 f->macaddr, ETH_ALEN);
1643 add_list[num_add].vlan_tag =
1644 cpu_to_le16(
1645 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1646 add_list[num_add].queue_number = 0;
1647
1648 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1649 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1650 num_add++;
1651
1652 /* flush a full buffer */
1653 if (num_add == filter_list_len) {
dcae29be
JB		 1654 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1655 add_list, num_add,
1656 NULL);
41c445ff
JB		 1657 num_add = 0;
1658
dcae29be 1659 if (aq_ret)
41c445ff
JB		 1660 break;
1661 memset(add_list, 0, sizeof(*add_list));
1662 }
1663 }
1664 if (num_add) {
dcae29be
JB		 1665 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1666 add_list, num_add, NULL);
41c445ff
JB		 1667 num_add = 0;
1668 }
1669 kfree(add_list);
1670 add_list = NULL;
1671
dcae29be 1672 if (add_happened && (!aq_ret)) {
41c445ff 1673 /* do nothing */;
dcae29be 1674 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1675 dev_info(&pf->pdev->dev,
1676 "add filter failed, err %d, aq_err %d\n",
dcae29be 1677 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1678 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1679 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1680 &vsi->state)) {
1681 promisc_forced_on = true;
1682 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1683 &vsi->state);
1684 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1685 }
1686 }
1687 }
1688
1689 /* check for changes in promiscuous modes */
1690 if (changed_flags & IFF_ALLMULTI) {
1691 bool cur_multipromisc;
1692 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1693 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1694 vsi->seid,
1695 cur_multipromisc,
1696 NULL);
1697 if (aq_ret)
41c445ff
JB		 1698 dev_info(&pf->pdev->dev,
1699 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1700 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1701 }
1702 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1703 bool cur_promisc;
1704 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1705 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1706 &vsi->state));
dcae29be
JB		 1707 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1708 vsi->seid,
1709 cur_promisc, NULL);
1710 if (aq_ret)
41c445ff
JB		 1711 dev_info(&pf->pdev->dev,
1712 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1713 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1714 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1715 vsi->seid,
1716 cur_promisc, NULL);
1717 if (aq_ret)
1718 dev_info(&pf->pdev->dev,
1719 "set brdcast promisc failed, err %d, aq_err %d\n",
1720 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1721 }
1722
1723 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1724 return 0;
1725}
1726
1727/**
1728 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1729 * @pf: board private structure
1730 **/
1731static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1732{
1733 int v;
1734
1735 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1736 return;
1737 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1738
1739 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1740 if (pf->vsi[v] &&
1741 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1742 i40e_sync_vsi_filters(pf->vsi[v]);
1743 }
1744}
1745
1746/**
1747 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1748 * @netdev: network interface device structure
1749 * @new_mtu: new value for maximum frame size
1750 *
1751 * Returns 0 on success, negative on failure
1752 **/
1753static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1754{
1755 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1756 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1757 struct i40e_vsi *vsi = np->vsi;
1758
1759 /* MTU < 68 is an error and causes problems on some kernels */
1760 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1761 return -EINVAL;
1762
1763 netdev_info(netdev, "changing MTU from %d to %d\n",
1764 netdev->mtu, new_mtu);
1765 netdev->mtu = new_mtu;
1766 if (netif_running(netdev))
1767 i40e_vsi_reinit_locked(vsi);
1768
1769 return 0;
1770}
1771
beb0dff1
JK		 1772/**
1773 * i40e_ioctl - Access the hwtstamp interface
1774 * @netdev: network interface device structure
1775 * @ifr: interface request data
1776 * @cmd: ioctl command
1777 **/
1778int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1779{
1780 struct i40e_netdev_priv *np = netdev_priv(netdev);
1781 struct i40e_pf *pf = np->vsi->back;
1782
1783 switch (cmd) {
1784 case SIOCGHWTSTAMP:
1785 return i40e_ptp_get_ts_config(pf, ifr);
1786 case SIOCSHWTSTAMP:
1787 return i40e_ptp_set_ts_config(pf, ifr);
1788 default:
1789 return -EOPNOTSUPP;
1790 }
1791}
1792
41c445ff
JB		 1793/**
1794 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1795 * @vsi: the vsi being adjusted
1796 **/
1797void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1798{
1799 struct i40e_vsi_context ctxt;
1800 i40e_status ret;
1801
1802 if ((vsi->info.valid_sections &
1803 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1804 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1805 return; /* already enabled */
1806
1807 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1808 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1809 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1810
1811 ctxt.seid = vsi->seid;
1812 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1813 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1814 if (ret) {
1815 dev_info(&vsi->back->pdev->dev,
1816 "%s: update vsi failed, aq_err=%d\n",
1817 __func__, vsi->back->hw.aq.asq_last_status);
1818 }
1819}
1820
1821/**
1822 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1823 * @vsi: the vsi being adjusted
1824 **/
1825void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1826{
1827 struct i40e_vsi_context ctxt;
1828 i40e_status ret;
1829
1830 if ((vsi->info.valid_sections &
1831 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1832 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1833 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1834 return; /* already disabled */
1835
1836 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1837 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1838 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1839
1840 ctxt.seid = vsi->seid;
1841 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1842 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1843 if (ret) {
1844 dev_info(&vsi->back->pdev->dev,
1845 "%s: update vsi failed, aq_err=%d\n",
1846 __func__, vsi->back->hw.aq.asq_last_status);
1847 }
1848}
1849
1850/**
1851 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1852 * @netdev: network interface to be adjusted
1853 * @features: netdev features to test if VLAN offload is enabled or not
1854 **/
1855static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1856{
1857 struct i40e_netdev_priv *np = netdev_priv(netdev);
1858 struct i40e_vsi *vsi = np->vsi;
1859
1860 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1861 i40e_vlan_stripping_enable(vsi);
1862 else
1863 i40e_vlan_stripping_disable(vsi);
1864}
1865
1866/**
1867 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1868 * @vsi: the vsi being configured
1869 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1870 **/
1871int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1872{
1873 struct i40e_mac_filter *f, *add_f;
1874 bool is_netdev, is_vf;
41c445ff
JB		 1875
1876 is_vf = (vsi->type == I40E_VSI_SRIOV);
1877 is_netdev = !!(vsi->netdev);
1878
1879 if (is_netdev) {
1880 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1881 is_vf, is_netdev);
1882 if (!add_f) {
1883 dev_info(&vsi->back->pdev->dev,
1884 "Could not add vlan filter %d for %pM\n",
1885 vid, vsi->netdev->dev_addr);
1886 return -ENOMEM;
1887 }
1888 }
1889
1890 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1891 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1892 if (!add_f) {
1893 dev_info(&vsi->back->pdev->dev,
1894 "Could not add vlan filter %d for %pM\n",
1895 vid, f->macaddr);
1896 return -ENOMEM;
1897 }
1898 }
1899
41c445ff
JB		 1900 /* Now if we add a vlan tag, make sure to check if it is the first
1901 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1902 * with 0, so we now accept untagged and specified tagged traffic
1903 * (and not any taged and untagged)
1904 */
1905 if (vid > 0) {
1906 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1907 I40E_VLAN_ANY,
1908 is_vf, is_netdev)) {
1909 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1910 I40E_VLAN_ANY, is_vf, is_netdev);
1911 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1912 is_vf, is_netdev);
1913 if (!add_f) {
1914 dev_info(&vsi->back->pdev->dev,
1915 "Could not add filter 0 for %pM\n",
1916 vsi->netdev->dev_addr);
1917 return -ENOMEM;
1918 }
1919 }
8d82a7c5 1920 }
41c445ff 1921
8d82a7c5
GR		 1922 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1923 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1924 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1925 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1926 is_vf, is_netdev)) {
1927 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1928 is_vf, is_netdev);
1929 add_f = i40e_add_filter(vsi, f->macaddr,
1930 0, is_vf, is_netdev);
1931 if (!add_f) {
1932 dev_info(&vsi->back->pdev->dev,
1933 "Could not add filter 0 for %pM\n",
1934 f->macaddr);
1935 return -ENOMEM;
1936 }
1937 }
1938 }
41c445ff
JB		 1939 }
1940
80f6428f
ASJ		 1941 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1942 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1943 return 0;
1944
1945 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1946}
1947
1948/**
1949 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1950 * @vsi: the vsi being configured
1951 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1952 *
1953 * Return: 0 on success or negative otherwise
41c445ff
JB		 1954 **/
1955int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1956{
1957 struct net_device *netdev = vsi->netdev;
1958 struct i40e_mac_filter *f, *add_f;
1959 bool is_vf, is_netdev;
1960 int filter_count = 0;
41c445ff
JB		 1961
1962 is_vf = (vsi->type == I40E_VSI_SRIOV);
1963 is_netdev = !!(netdev);
1964
1965 if (is_netdev)
1966 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1967
1968 list_for_each_entry(f, &vsi->mac_filter_list, list)
1969 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1970
41c445ff
JB		 1971 /* go through all the filters for this VSI and if there is only
1972 * vid == 0 it means there are no other filters, so vid 0 must
1973 * be replaced with -1. This signifies that we should from now
1974 * on accept any traffic (with any tag present, or untagged)
1975 */
1976 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1977 if (is_netdev) {
1978 if (f->vlan &&
1979 ether_addr_equal(netdev->dev_addr, f->macaddr))
1980 filter_count++;
1981 }
1982
1983 if (f->vlan)
1984 filter_count++;
1985 }
1986
1987 if (!filter_count && is_netdev) {
1988 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1989 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1990 is_vf, is_netdev);
1991 if (!f) {
1992 dev_info(&vsi->back->pdev->dev,
1993 "Could not add filter %d for %pM\n",
1994 I40E_VLAN_ANY, netdev->dev_addr);
1995 return -ENOMEM;
1996 }
1997 }
1998
1999 if (!filter_count) {
2000 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2001 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2002 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2003 is_vf, is_netdev);
2004 if (!add_f) {
2005 dev_info(&vsi->back->pdev->dev,
2006 "Could not add filter %d for %pM\n",
2007 I40E_VLAN_ANY, f->macaddr);
2008 return -ENOMEM;
2009 }
2010 }
2011 }
2012
80f6428f
ASJ		 2013 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2014 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2015 return 0;
2016
41c445ff
JB		 2017 return i40e_sync_vsi_filters(vsi);
2018}
2019
2020/**
2021 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2022 * @netdev: network interface to be adjusted
2023 * @vid: vlan id to be added
078b5876
JB		 2024 *
2025 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 2026 **/
2027static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2028 __always_unused __be16 proto, u16 vid)
2029{
2030 struct i40e_netdev_priv *np = netdev_priv(netdev);
2031 struct i40e_vsi *vsi = np->vsi;
078b5876 2032 int ret = 0;
41c445ff
JB		 2033
2034 if (vid > 4095)
078b5876
JB		 2035 return -EINVAL;
2036
2037 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2038
6982d429
ASJ		 2039 /* If the network stack called us with vid = 0 then
2040 * it is asking to receive priority tagged packets with
2041 * vlan id 0. Our HW receives them by default when configured
2042 * to receive untagged packets so there is no need to add an
2043 * extra filter for vlan 0 tagged packets.
41c445ff 2044 */
6982d429
ASJ		 2045 if (vid)
2046 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2047
078b5876
JB		 2048 if (!ret && (vid < VLAN_N_VID))
2049 set_bit(vid, vsi->active_vlans);
41c445ff 2050
078b5876 2051 return ret;
41c445ff
JB		 2052}
2053
2054/**
2055 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2056 * @netdev: network interface to be adjusted
2057 * @vid: vlan id to be removed
078b5876 2058 *
fdfd943e 2059 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2060 **/
2061static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2062 __always_unused __be16 proto, u16 vid)
2063{
2064 struct i40e_netdev_priv *np = netdev_priv(netdev);
2065 struct i40e_vsi *vsi = np->vsi;
2066
078b5876
JB		 2067 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2068
41c445ff
JB		 2069 /* return code is ignored as there is nothing a user
2070 * can do about failure to remove and a log message was
078b5876 2071 * already printed from the other function
41c445ff
JB		 2072 */
2073 i40e_vsi_kill_vlan(vsi, vid);
2074
2075 clear_bit(vid, vsi->active_vlans);
078b5876 2076
41c445ff
JB		 2077 return 0;
2078}
2079
2080/**
2081 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2082 * @vsi: the vsi being brought back up
2083 **/
2084static void i40e_restore_vlan(struct i40e_vsi *vsi)
2085{
2086 u16 vid;
2087
2088 if (!vsi->netdev)
2089 return;
2090
2091 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2092
2093 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2094 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2095 vid);
2096}
2097
2098/**
2099 * i40e_vsi_add_pvid - Add pvid for the VSI
2100 * @vsi: the vsi being adjusted
2101 * @vid: the vlan id to set as a PVID
2102 **/
dcae29be 2103int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2104{
2105 struct i40e_vsi_context ctxt;
dcae29be 2106 i40e_status aq_ret;
41c445ff
JB		 2107
2108 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2109 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2110 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2111 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2112 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2113
2114 ctxt.seid = vsi->seid;
2115 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2116 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2117 if (aq_ret) {
41c445ff
JB		 2118 dev_info(&vsi->back->pdev->dev,
2119 "%s: update vsi failed, aq_err=%d\n",
2120 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2121 return -ENOENT;
41c445ff
JB		 2122 }
2123
dcae29be 2124 return 0;
41c445ff
JB		 2125}
2126
2127/**
2128 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2129 * @vsi: the vsi being adjusted
2130 *
2131 * Just use the vlan_rx_register() service to put it back to normal
2132 **/
2133void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2134{
6c12fcbf
GR		 2135 i40e_vlan_stripping_disable(vsi);
2136
41c445ff 2137 vsi->info.pvid = 0;
41c445ff
JB		 2138}
2139
2140/**
2141 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2142 * @vsi: ptr to the VSI
2143 *
2144 * If this function returns with an error, then it's possible one or
2145 * more of the rings is populated (while the rest are not). It is the
2146 * callers duty to clean those orphaned rings.
2147 *
2148 * Return 0 on success, negative on failure
2149 **/
2150static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2151{
2152 int i, err = 0;
2153
2154 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2155 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2156
2157 return err;
2158}
2159
2160/**
2161 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2162 * @vsi: ptr to the VSI
2163 *
2164 * Free VSI's transmit software resources
2165 **/
2166static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2167{
2168 int i;
2169
8e9dca53
GR		 2170 if (!vsi->tx_rings)
2171 return;
2172
41c445ff 2173 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2174 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2175 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2176}
2177
2178/**
2179 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2180 * @vsi: ptr to the VSI
2181 *
2182 * If this function returns with an error, then it's possible one or
2183 * more of the rings is populated (while the rest are not). It is the
2184 * callers duty to clean those orphaned rings.
2185 *
2186 * Return 0 on success, negative on failure
2187 **/
2188static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2189{
2190 int i, err = 0;
2191
2192 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2193 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2194 return err;
2195}
2196
2197/**
2198 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2199 * @vsi: ptr to the VSI
2200 *
2201 * Free all receive software resources
2202 **/
2203static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2204{
2205 int i;
2206
8e9dca53
GR		 2207 if (!vsi->rx_rings)
2208 return;
2209
41c445ff 2210 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2211 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2212 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2213}
2214
2215/**
2216 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2217 * @ring: The Tx ring to configure
2218 *
2219 * Configure the Tx descriptor ring in the HMC context.
2220 **/
2221static int i40e_configure_tx_ring(struct i40e_ring *ring)
2222{
2223 struct i40e_vsi *vsi = ring->vsi;
2224 u16 pf_q = vsi->base_queue + ring->queue_index;
2225 struct i40e_hw *hw = &vsi->back->hw;
2226 struct i40e_hmc_obj_txq tx_ctx;
2227 i40e_status err = 0;
2228 u32 qtx_ctl = 0;
2229
2230 /* some ATR related tx ring init */
60ea5f83 2231 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2232 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2233 ring->atr_count = 0;
2234 } else {
2235 ring->atr_sample_rate = 0;
2236 }
2237
2238 /* initialize XPS */
2239 if (ring->q_vector && ring->netdev &&
4e3b35b0 2240 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2241 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2242 netif_set_xps_queue(ring->netdev,
2243 &ring->q_vector->affinity_mask,
2244 ring->queue_index);
2245
2246 /* clear the context structure first */
2247 memset(&tx_ctx, 0, sizeof(tx_ctx));
2248
2249 tx_ctx.new_context = 1;
2250 tx_ctx.base = (ring->dma / 128);
2251 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2252 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2253 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2254 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2255 /* FDIR VSI tx ring can still use RS bit and writebacks */
2256 if (vsi->type != I40E_VSI_FDIR)
2257 tx_ctx.head_wb_ena = 1;
2258 tx_ctx.head_wb_addr = ring->dma +
2259 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2260
2261 /* As part of VSI creation/update, FW allocates certain
2262 * Tx arbitration queue sets for each TC enabled for
2263 * the VSI. The FW returns the handles to these queue
2264 * sets as part of the response buffer to Add VSI,
2265 * Update VSI, etc. AQ commands. It is expected that
2266 * these queue set handles be associated with the Tx
2267 * queues by the driver as part of the TX queue context
2268 * initialization. This has to be done regardless of
2269 * DCB as by default everything is mapped to TC0.
2270 */
2271 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2272 tx_ctx.rdylist_act = 0;
2273
2274 /* clear the context in the HMC */
2275 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2276 if (err) {
2277 dev_info(&vsi->back->pdev->dev,
2278 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2279 ring->queue_index, pf_q, err);
2280 return -ENOMEM;
2281 }
2282
2283 /* set the context in the HMC */
2284 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2285 if (err) {
2286 dev_info(&vsi->back->pdev->dev,
2287 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2288 ring->queue_index, pf_q, err);
2289 return -ENOMEM;
2290 }
2291
2292 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2293 if (vsi->type == I40E_VSI_VMDQ2)
2294 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2295 else
2296 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2297 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2298 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2299 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2300 i40e_flush(hw);
2301
2302 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2303
2304 /* cache tail off for easier writes later */
2305 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2306
2307 return 0;
2308}
2309
2310/**
2311 * i40e_configure_rx_ring - Configure a receive ring context
2312 * @ring: The Rx ring to configure
2313 *
2314 * Configure the Rx descriptor ring in the HMC context.
2315 **/
2316static int i40e_configure_rx_ring(struct i40e_ring *ring)
2317{
2318 struct i40e_vsi *vsi = ring->vsi;
2319 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2320 u16 pf_q = vsi->base_queue + ring->queue_index;
2321 struct i40e_hw *hw = &vsi->back->hw;
2322 struct i40e_hmc_obj_rxq rx_ctx;
2323 i40e_status err = 0;
2324
2325 ring->state = 0;
2326
2327 /* clear the context structure first */
2328 memset(&rx_ctx, 0, sizeof(rx_ctx));
2329
2330 ring->rx_buf_len = vsi->rx_buf_len;
2331 ring->rx_hdr_len = vsi->rx_hdr_len;
2332
2333 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2334 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2335
2336 rx_ctx.base = (ring->dma / 128);
2337 rx_ctx.qlen = ring->count;
2338
2339 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2340 set_ring_16byte_desc_enabled(ring);
2341 rx_ctx.dsize = 0;
2342 } else {
2343 rx_ctx.dsize = 1;
2344 }
2345
2346 rx_ctx.dtype = vsi->dtype;
2347 if (vsi->dtype) {
2348 set_ring_ps_enabled(ring);
2349 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2350 I40E_RX_SPLIT_IP |
2351 I40E_RX_SPLIT_TCP_UDP |
2352 I40E_RX_SPLIT_SCTP;
2353 } else {
2354 rx_ctx.hsplit_0 = 0;
2355 }
2356
2357 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2358 (chain_len * ring->rx_buf_len));
2359 rx_ctx.tphrdesc_ena = 1;
2360 rx_ctx.tphwdesc_ena = 1;
2361 rx_ctx.tphdata_ena = 1;
2362 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2363 if (hw->revision_id == 0)
2364 rx_ctx.lrxqthresh = 0;
2365 else
2366 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2367 rx_ctx.crcstrip = 1;
2368 rx_ctx.l2tsel = 1;
2369 rx_ctx.showiv = 1;
acb3676b
CS		 2370 /* set the prefena field to 1 because the manual says to */
2371 rx_ctx.prefena = 1;
41c445ff
JB		 2372
2373 /* clear the context in the HMC */
2374 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2375 if (err) {
2376 dev_info(&vsi->back->pdev->dev,
2377 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2378 ring->queue_index, pf_q, err);
2379 return -ENOMEM;
2380 }
2381
2382 /* set the context in the HMC */
2383 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2384 if (err) {
2385 dev_info(&vsi->back->pdev->dev,
2386 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2387 ring->queue_index, pf_q, err);
2388 return -ENOMEM;
2389 }
2390
2391 /* cache tail for quicker writes, and clear the reg before use */
2392 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2393 writel(0, ring->tail);
2394
2395 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2396
2397 return 0;
2398}
2399
2400/**
2401 * i40e_vsi_configure_tx - Configure the VSI for Tx
2402 * @vsi: VSI structure describing this set of rings and resources
2403 *
2404 * Configure the Tx VSI for operation.
2405 **/
2406static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2407{
2408 int err = 0;
2409 u16 i;
2410
9f65e15b
AD		 2411 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2412 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2413
2414 return err;
2415}
2416
2417/**
2418 * i40e_vsi_configure_rx - Configure the VSI for Rx
2419 * @vsi: the VSI being configured
2420 *
2421 * Configure the Rx VSI for operation.
2422 **/
2423static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2424{
2425 int err = 0;
2426 u16 i;
2427
2428 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2429 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2430 + ETH_FCS_LEN + VLAN_HLEN;
2431 else
2432 vsi->max_frame = I40E_RXBUFFER_2048;
2433
2434 /* figure out correct receive buffer length */
2435 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2436 I40E_FLAG_RX_PS_ENABLED)) {
2437 case I40E_FLAG_RX_1BUF_ENABLED:
2438 vsi->rx_hdr_len = 0;
2439 vsi->rx_buf_len = vsi->max_frame;
2440 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2441 break;
2442 case I40E_FLAG_RX_PS_ENABLED:
2443 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2444 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2445 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2446 break;
2447 default:
2448 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2449 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2450 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2451 break;
2452 }
2453
2454 /* round up for the chip's needs */
2455 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2456 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2457 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2458 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2459
2460 /* set up individual rings */
2461 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2462 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2463
2464 return err;
2465}
2466
2467/**
2468 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2469 * @vsi: ptr to the VSI
2470 **/
2471static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2472{
e7046ee1 2473 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2474 u16 qoffset, qcount;
2475 int i, n;
2476
2477 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2478 return;
2479
2480 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2481 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2482 continue;
2483
2484 qoffset = vsi->tc_config.tc_info[n].qoffset;
2485 qcount = vsi->tc_config.tc_info[n].qcount;
2486 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2487 rx_ring = vsi->rx_rings[i];
2488 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2489 rx_ring->dcb_tc = n;
2490 tx_ring->dcb_tc = n;
2491 }
2492 }
2493}
2494
2495/**
2496 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2497 * @vsi: ptr to the VSI
2498 **/
2499static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2500{
2501 if (vsi->netdev)
2502 i40e_set_rx_mode(vsi->netdev);
2503}
2504
17a73f6b
JG		 2505/**
2506 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2507 * @vsi: Pointer to the targeted VSI
2508 *
2509 * This function replays the hlist on the hw where all the SB Flow Director
2510 * filters were saved.
2511 **/
2512static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2513{
2514 struct i40e_fdir_filter *filter;
2515 struct i40e_pf *pf = vsi->back;
2516 struct hlist_node *node;
2517
55a5e60b
ASJ		 2518 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2519 return;
2520
17a73f6b
JG		 2521 hlist_for_each_entry_safe(filter, node,
2522 &pf->fdir_filter_list, fdir_node) {
2523 i40e_add_del_fdir(vsi, filter, true);
2524 }
2525}
2526
41c445ff
JB		 2527/**
2528 * i40e_vsi_configure - Set up the VSI for action
2529 * @vsi: the VSI being configured
2530 **/
2531static int i40e_vsi_configure(struct i40e_vsi *vsi)
2532{
2533 int err;
2534
2535 i40e_set_vsi_rx_mode(vsi);
2536 i40e_restore_vlan(vsi);
2537 i40e_vsi_config_dcb_rings(vsi);
2538 err = i40e_vsi_configure_tx(vsi);
2539 if (!err)
2540 err = i40e_vsi_configure_rx(vsi);
2541
2542 return err;
2543}
2544
2545/**
2546 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2547 * @vsi: the VSI being configured
2548 **/
2549static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2550{
2551 struct i40e_pf *pf = vsi->back;
2552 struct i40e_q_vector *q_vector;
2553 struct i40e_hw *hw = &pf->hw;
2554 u16 vector;
2555 int i, q;
2556 u32 val;
2557 u32 qp;
2558
2559 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2560 * and PFINT_LNKLSTn registers, e.g.:
2561 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2562 */
2563 qp = vsi->base_queue;
2564 vector = vsi->base_vector;
493fb300
AD		 2565 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2566 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2567 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2568 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2569 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2570 q_vector->rx.itr);
2571 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2572 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2573 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2574 q_vector->tx.itr);
2575
2576 /* Linked list for the queuepairs assigned to this vector */
2577 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2578 for (q = 0; q < q_vector->num_ringpairs; q++) {
2579 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2580 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2581 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2582 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2583 (I40E_QUEUE_TYPE_TX
2584 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2585
2586 wr32(hw, I40E_QINT_RQCTL(qp), val);
2587
2588 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2589 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2590 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2591 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2592 (I40E_QUEUE_TYPE_RX
2593 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2594
2595 /* Terminate the linked list */
2596 if (q == (q_vector->num_ringpairs - 1))
2597 val |= (I40E_QUEUE_END_OF_LIST
2598 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2599
2600 wr32(hw, I40E_QINT_TQCTL(qp), val);
2601 qp++;
2602 }
2603 }
2604
2605 i40e_flush(hw);
2606}
2607
2608/**
2609 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2610 * @hw: ptr to the hardware info
2611 **/
2612static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2613{
2614 u32 val;
2615
2616 /* clear things first */
2617 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2618 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2619
2620 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2621 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2622 I40E_PFINT_ICR0_ENA_GRST_MASK |
2623 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2624 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2625 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2626 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2627 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2628 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2629
2630 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2631
2632 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2633 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2634 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2635
2636 /* OTHER_ITR_IDX = 0 */
2637 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2638}
2639
2640/**
2641 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2642 * @vsi: the VSI being configured
2643 **/
2644static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2645{
493fb300 2646 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2647 struct i40e_pf *pf = vsi->back;
2648 struct i40e_hw *hw = &pf->hw;
2649 u32 val;
2650
2651 /* set the ITR configuration */
2652 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2653 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2654 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2655 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2656 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2657 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2658
2659 i40e_enable_misc_int_causes(hw);
2660
2661 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2662 wr32(hw, I40E_PFINT_LNKLST0, 0);
2663
f29eaa3d 2664 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2665 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2666 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2667 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2668
2669 wr32(hw, I40E_QINT_RQCTL(0), val);
2670
2671 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2672 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2673 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2674
2675 wr32(hw, I40E_QINT_TQCTL(0), val);
2676 i40e_flush(hw);
2677}
2678
2ef28cfb
MW		 2679/**
2680 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2681 * @pf: board private structure
2682 **/
2683void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2684{
2685 struct i40e_hw *hw = &pf->hw;
2686
2687 wr32(hw, I40E_PFINT_DYN_CTL0,
2688 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2689 i40e_flush(hw);
2690}
2691
41c445ff
JB		 2692/**
2693 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2694 * @pf: board private structure
2695 **/
116a57d4 2696void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2697{
2698 struct i40e_hw *hw = &pf->hw;
2699 u32 val;
2700
2701 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2702 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2703 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2704
2705 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2706 i40e_flush(hw);
2707}
2708
2709/**
2710 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2711 * @vsi: pointer to a vsi
2712 * @vector: enable a particular Hw Interrupt vector
2713 **/
2714void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2715{
2716 struct i40e_pf *pf = vsi->back;
2717 struct i40e_hw *hw = &pf->hw;
2718 u32 val;
2719
2720 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2721 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2722 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2723 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2724 /* skip the flush */
41c445ff
JB		 2725}
2726
2727/**
2728 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2729 * @irq: interrupt number
2730 * @data: pointer to a q_vector
2731 **/
2732static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2733{
2734 struct i40e_q_vector *q_vector = data;
2735
cd0b6fa6 2736 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2737 return IRQ_HANDLED;
2738
2739 napi_schedule(&q_vector->napi);
2740
2741 return IRQ_HANDLED;
2742}
2743
41c445ff
JB		 2744/**
2745 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2746 * @vsi: the VSI being configured
2747 * @basename: name for the vector
2748 *
2749 * Allocates MSI-X vectors and requests interrupts from the kernel.
2750 **/
2751static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2752{
2753 int q_vectors = vsi->num_q_vectors;
2754 struct i40e_pf *pf = vsi->back;
2755 int base = vsi->base_vector;
2756 int rx_int_idx = 0;
2757 int tx_int_idx = 0;
2758 int vector, err;
2759
2760 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2761 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2762
cd0b6fa6 2763 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2764 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2765 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2766 tx_int_idx++;
cd0b6fa6 2767 } else if (q_vector->rx.ring) {
41c445ff
JB		 2768 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2769 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2770 } else if (q_vector->tx.ring) {
41c445ff
JB		 2771 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2772 "%s-%s-%d", basename, "tx", tx_int_idx++);
2773 } else {
2774 /* skip this unused q_vector */
2775 continue;
2776 }
2777 err = request_irq(pf->msix_entries[base + vector].vector,
2778 vsi->irq_handler,
2779 0,
2780 q_vector->name,
2781 q_vector);
2782 if (err) {
2783 dev_info(&pf->pdev->dev,
2784 "%s: request_irq failed, error: %d\n",
2785 __func__, err);
2786 goto free_queue_irqs;
2787 }
2788 /* assign the mask for this irq */
2789 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2790 &q_vector->affinity_mask);
2791 }
2792
2793 return 0;
2794
2795free_queue_irqs:
2796 while (vector) {
2797 vector--;
2798 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2799 NULL);
2800 free_irq(pf->msix_entries[base + vector].vector,
2801 &(vsi->q_vectors[vector]));
2802 }
2803 return err;
2804}
2805
2806/**
2807 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2808 * @vsi: the VSI being un-configured
2809 **/
2810static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2811{
2812 struct i40e_pf *pf = vsi->back;
2813 struct i40e_hw *hw = &pf->hw;
2814 int base = vsi->base_vector;
2815 int i;
2816
2817 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2818 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2819 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2820 }
2821
2822 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2823 for (i = vsi->base_vector;
2824 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2825 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2826
2827 i40e_flush(hw);
2828 for (i = 0; i < vsi->num_q_vectors; i++)
2829 synchronize_irq(pf->msix_entries[i + base].vector);
2830 } else {
2831 /* Legacy and MSI mode - this stops all interrupt handling */
2832 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2833 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2834 i40e_flush(hw);
2835 synchronize_irq(pf->pdev->irq);
2836 }
2837}
2838
2839/**
2840 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2841 * @vsi: the VSI being configured
2842 **/
2843static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2844{
2845 struct i40e_pf *pf = vsi->back;
2846 int i;
2847
2848 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2849 for (i = vsi->base_vector;
2850 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2851 i40e_irq_dynamic_enable(vsi, i);
2852 } else {
2853 i40e_irq_dynamic_enable_icr0(pf);
2854 }
2855
1022cb6c 2856 i40e_flush(&pf->hw);
41c445ff
JB		 2857 return 0;
2858}
2859
2860/**
2861 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2862 * @pf: board private structure
2863 **/
2864static void i40e_stop_misc_vector(struct i40e_pf *pf)
2865{
2866 /* Disable ICR 0 */
2867 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2868 i40e_flush(&pf->hw);
2869}
2870
2871/**
2872 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2873 * @irq: interrupt number
2874 * @data: pointer to a q_vector
2875 *
2876 * This is the handler used for all MSI/Legacy interrupts, and deals
2877 * with both queue and non-queue interrupts. This is also used in
2878 * MSIX mode to handle the non-queue interrupts.
2879 **/
2880static irqreturn_t i40e_intr(int irq, void *data)
2881{
2882 struct i40e_pf *pf = (struct i40e_pf *)data;
2883 struct i40e_hw *hw = &pf->hw;
5e823066 2884 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2885 u32 icr0, icr0_remaining;
2886 u32 val, ena_mask;
2887
2888 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2889 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2890
116a57d4
SN		 2891 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2892 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2893 goto enable_intr;
41c445ff 2894
cd92e72f
SN		 2895 /* if interrupt but no bits showing, must be SWINT */
2896 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2897 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2898 pf->sw_int_count++;
2899
41c445ff
JB		 2900 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2901 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2902
2903 /* temporarily disable queue cause for NAPI processing */
2904 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2905 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2906 wr32(hw, I40E_QINT_RQCTL(0), qval);
2907
2908 qval = rd32(hw, I40E_QINT_TQCTL(0));
2909 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2910 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2911
2912 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2913 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2914 }
2915
2916 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2917 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2918 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2919 }
2920
2921 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2922 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2923 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2924 }
2925
2926 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2927 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2928 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2929 }
2930
2931 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2932 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2933 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2934 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2935 val = rd32(hw, I40E_GLGEN_RSTAT);
2936 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2937 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2938 if (val == I40E_RESET_CORER) {
41c445ff 2939 pf->corer_count++;
4eb3f768 2940 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2941 pf->globr_count++;
4eb3f768 2942 } else if (val == I40E_RESET_EMPR) {
41c445ff 2943 pf->empr_count++;
4eb3f768
SN		 2944 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2945 }
41c445ff
JB		 2946 }
2947
9c010ee0
ASJ		 2948 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2949 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2950 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2951 }
2952
beb0dff1
JK		 2953 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2954 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2955
2956 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 2957 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 2958 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 2959 }
beb0dff1
JK		 2960 }
2961
41c445ff
JB		 2962 /* If a critical error is pending we have no choice but to reset the
2963 * device.
2964 * Report and mask out any remaining unexpected interrupts.
2965 */
2966 icr0_remaining = icr0 & ena_mask;
2967 if (icr0_remaining) {
2968 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2969 icr0_remaining);
9c010ee0 2970 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2971 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2972 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2973 dev_info(&pf->pdev->dev, "device will be reset\n");
2974 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2975 i40e_service_event_schedule(pf);
41c445ff
JB		 2976 }
2977 ena_mask &= ~icr0_remaining;
2978 }
5e823066 2979 ret = IRQ_HANDLED;
41c445ff 2980
5e823066 2981enable_intr:
41c445ff
JB		 2982 /* re-enable interrupt causes */
2983 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2984 if (!test_bit(__I40E_DOWN, &pf->state)) {
2985 i40e_service_event_schedule(pf);
2986 i40e_irq_dynamic_enable_icr0(pf);
2987 }
2988
5e823066 2989 return ret;
41c445ff
JB		 2990}
2991
cbf61325
ASJ		 2992/**
2993 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2994 * @tx_ring: tx ring to clean
2995 * @budget: how many cleans we're allowed
2996 *
2997 * Returns true if there's any budget left (e.g. the clean is finished)
2998 **/
2999static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3000{
3001 struct i40e_vsi *vsi = tx_ring->vsi;
3002 u16 i = tx_ring->next_to_clean;
3003 struct i40e_tx_buffer *tx_buf;
3004 struct i40e_tx_desc *tx_desc;
3005
3006 tx_buf = &tx_ring->tx_bi[i];
3007 tx_desc = I40E_TX_DESC(tx_ring, i);
3008 i -= tx_ring->count;
3009
3010 do {
3011 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3012
3013 /* if next_to_watch is not set then there is no work pending */
3014 if (!eop_desc)
3015 break;
3016
3017 /* prevent any other reads prior to eop_desc */
3018 read_barrier_depends();
3019
3020 /* if the descriptor isn't done, no work yet to do */
3021 if (!(eop_desc->cmd_type_offset_bsz &
3022 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3023 break;
3024
3025 /* clear next_to_watch to prevent false hangs */
3026 tx_buf->next_to_watch = NULL;
3027
3028 /* unmap skb header data */
3029 dma_unmap_single(tx_ring->dev,
3030 dma_unmap_addr(tx_buf, dma),
3031 dma_unmap_len(tx_buf, len),
3032 DMA_TO_DEVICE);
3033
3034 dma_unmap_len_set(tx_buf, len, 0);
3035
3036
3037 /* move to the next desc and buffer to clean */
3038 tx_buf++;
3039 tx_desc++;
3040 i++;
3041 if (unlikely(!i)) {
3042 i -= tx_ring->count;
3043 tx_buf = tx_ring->tx_bi;
3044 tx_desc = I40E_TX_DESC(tx_ring, 0);
3045 }
3046
3047 /* update budget accounting */
3048 budget--;
3049 } while (likely(budget));
3050
3051 i += tx_ring->count;
3052 tx_ring->next_to_clean = i;
3053
3054 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3055 i40e_irq_dynamic_enable(vsi,
3056 tx_ring->q_vector->v_idx + vsi->base_vector);
3057 }
3058 return budget > 0;
3059}
3060
3061/**
3062 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3063 * @irq: interrupt number
3064 * @data: pointer to a q_vector
3065 **/
3066static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3067{
3068 struct i40e_q_vector *q_vector = data;
3069 struct i40e_vsi *vsi;
3070
3071 if (!q_vector->tx.ring)
3072 return IRQ_HANDLED;
3073
3074 vsi = q_vector->tx.ring->vsi;
3075 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3076
3077 return IRQ_HANDLED;
3078}
3079
41c445ff 3080/**
cd0b6fa6 3081 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3082 * @vsi: the VSI being configured
3083 * @v_idx: vector index
cd0b6fa6 3084 * @qp_idx: queue pair index
41c445ff 3085 **/
cd0b6fa6 3086static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3087{
493fb300 3088 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3089 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3090 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3091
3092 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3093 tx_ring->next = q_vector->tx.ring;
3094 q_vector->tx.ring = tx_ring;
41c445ff 3095 q_vector->tx.count++;
cd0b6fa6
AD		 3096
3097 rx_ring->q_vector = q_vector;
3098 rx_ring->next = q_vector->rx.ring;
3099 q_vector->rx.ring = rx_ring;
3100 q_vector->rx.count++;
41c445ff
JB		 3101}
3102
3103/**
3104 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3105 * @vsi: the VSI being configured
3106 *
3107 * This function maps descriptor rings to the queue-specific vectors
3108 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3109 * one vector per queue pair, but on a constrained vector budget, we
3110 * group the queue pairs as "efficiently" as possible.
3111 **/
3112static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3113{
3114 int qp_remaining = vsi->num_queue_pairs;
3115 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3116 int num_ringpairs;
41c445ff
JB		 3117 int v_start = 0;
3118 int qp_idx = 0;
3119
3120 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3121 * group them so there are multiple queues per vector.
3122 */
3123 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3124 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3125
3126 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3127
3128 q_vector->num_ringpairs = num_ringpairs;
3129
3130 q_vector->rx.count = 0;
3131 q_vector->tx.count = 0;
3132 q_vector->rx.ring = NULL;
3133 q_vector->tx.ring = NULL;
3134
3135 while (num_ringpairs--) {
3136 map_vector_to_qp(vsi, v_start, qp_idx);
3137 qp_idx++;
3138 qp_remaining--;
41c445ff
JB		 3139 }
3140 }
3141}
3142
3143/**
3144 * i40e_vsi_request_irq - Request IRQ from the OS
3145 * @vsi: the VSI being configured
3146 * @basename: name for the vector
3147 **/
3148static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3149{
3150 struct i40e_pf *pf = vsi->back;
3151 int err;
3152
3153 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3154 err = i40e_vsi_request_irq_msix(vsi, basename);
3155 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3156 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3157 pf->misc_int_name, pf);
3158 else
3159 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3160 pf->misc_int_name, pf);
3161
3162 if (err)
3163 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3164
3165 return err;
3166}
3167
3168#ifdef CONFIG_NET_POLL_CONTROLLER
3169/**
3170 * i40e_netpoll - A Polling 'interrupt'handler
3171 * @netdev: network interface device structure
3172 *
3173 * This is used by netconsole to send skbs without having to re-enable
3174 * interrupts. It's not called while the normal interrupt routine is executing.
3175 **/
3176static void i40e_netpoll(struct net_device *netdev)
3177{
3178 struct i40e_netdev_priv *np = netdev_priv(netdev);
3179 struct i40e_vsi *vsi = np->vsi;
3180 struct i40e_pf *pf = vsi->back;
3181 int i;
3182
3183 /* if interface is down do nothing */
3184 if (test_bit(__I40E_DOWN, &vsi->state))
3185 return;
3186
3187 pf->flags |= I40E_FLAG_IN_NETPOLL;
3188 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3189 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3190 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3191 } else {
3192 i40e_intr(pf->pdev->irq, netdev);
3193 }
3194 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3195}
3196#endif
3197
3198/**
3199 * i40e_vsi_control_tx - Start or stop a VSI's rings
3200 * @vsi: the VSI being configured
3201 * @enable: start or stop the rings
3202 **/
3203static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3204{
3205 struct i40e_pf *pf = vsi->back;
3206 struct i40e_hw *hw = &pf->hw;
3207 int i, j, pf_q;
3208 u32 tx_reg;
3209
3210 pf_q = vsi->base_queue;
3211 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3212
3213 /* warn the TX unit of coming changes */
3214 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3215 if (!enable)
3216 udelay(10);
3217
6c5ef620 3218 for (j = 0; j < 50; j++) {
41c445ff 3219 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3220 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3221 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3222 break;
3223 usleep_range(1000, 2000);
3224 }
fda972f6 3225 /* Skip if the queue is already in the requested state */
7c122007 3226 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3227 continue;
41c445ff
JB		 3228
3229 /* turn on/off the queue */
c5c9eb9e
SN		 3230 if (enable) {
3231 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3232 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3233 } else {
41c445ff 3234 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3235 }
41c445ff
JB		 3236
3237 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3238
3239 /* wait for the change to finish */
3240 for (j = 0; j < 10; j++) {
3241 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
7c122007
CS		 3242 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3243 break;
41c445ff
JB		 3244
3245 udelay(10);
3246 }
3247 if (j >= 10) {
3248 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3249 pf_q, (enable ? "en" : "dis"));
3250 return -ETIMEDOUT;
3251 }
3252 }
3253
7134f9ce
JB		 3254 if (hw->revision_id == 0)
3255 mdelay(50);
3256
41c445ff
JB		 3257 return 0;
3258}
3259
3260/**
3261 * i40e_vsi_control_rx - Start or stop a VSI's rings
3262 * @vsi: the VSI being configured
3263 * @enable: start or stop the rings
3264 **/
3265static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3266{
3267 struct i40e_pf *pf = vsi->back;
3268 struct i40e_hw *hw = &pf->hw;
3269 int i, j, pf_q;
3270 u32 rx_reg;
3271
3272 pf_q = vsi->base_queue;
3273 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3274 for (j = 0; j < 50; j++) {
41c445ff 3275 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3276 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3277 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3278 break;
3279 usleep_range(1000, 2000);
3280 }
41c445ff 3281
7c122007
CS		 3282 /* Skip if the queue is already in the requested state */
3283 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3284 continue;
41c445ff
JB		 3285
3286 /* turn on/off the queue */
3287 if (enable)
6c5ef620 3288 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3289 else
6c5ef620 3290 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3291 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3292
3293 /* wait for the change to finish */
3294 for (j = 0; j < 10; j++) {
3295 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3296
7c122007
CS		 3297 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3298 break;
41c445ff
JB		 3299
3300 udelay(10);
3301 }
3302 if (j >= 10) {
3303 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3304 pf_q, (enable ? "en" : "dis"));
3305 return -ETIMEDOUT;
3306 }
3307 }
3308
3309 return 0;
3310}
3311
3312/**
3313 * i40e_vsi_control_rings - Start or stop a VSI's rings
3314 * @vsi: the VSI being configured
3315 * @enable: start or stop the rings
3316 **/
fc18eaa0 3317int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3318{
3b867b28 3319 int ret = 0;
41c445ff
JB		 3320
3321 /* do rx first for enable and last for disable */
3322 if (request) {
3323 ret = i40e_vsi_control_rx(vsi, request);
3324 if (ret)
3325 return ret;
3326 ret = i40e_vsi_control_tx(vsi, request);
3327 } else {
3b867b28
ASJ		 3328 /* Ignore return value, we need to shutdown whatever we can */
3329 i40e_vsi_control_tx(vsi, request);
3330 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3331 }
3332
3333 return ret;
3334}
3335
3336/**
3337 * i40e_vsi_free_irq - Free the irq association with the OS
3338 * @vsi: the VSI being configured
3339 **/
3340static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3341{
3342 struct i40e_pf *pf = vsi->back;
3343 struct i40e_hw *hw = &pf->hw;
3344 int base = vsi->base_vector;
3345 u32 val, qp;
3346 int i;
3347
3348 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3349 if (!vsi->q_vectors)
3350 return;
3351
3352 for (i = 0; i < vsi->num_q_vectors; i++) {
3353 u16 vector = i + base;
3354
3355 /* free only the irqs that were actually requested */
78681b1f
SN		 3356 if (!vsi->q_vectors[i] ||
3357 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3358 continue;
3359
3360 /* clear the affinity_mask in the IRQ descriptor */
3361 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3362 NULL);
3363 free_irq(pf->msix_entries[vector].vector,
493fb300 3364 vsi->q_vectors[i]);
41c445ff
JB		 3365
3366 /* Tear down the interrupt queue link list
3367 *
3368 * We know that they come in pairs and always
3369 * the Rx first, then the Tx. To clear the
3370 * link list, stick the EOL value into the
3371 * next_q field of the registers.
3372 */
3373 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3374 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3375 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3376 val |= I40E_QUEUE_END_OF_LIST
3377 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3378 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3379
3380 while (qp != I40E_QUEUE_END_OF_LIST) {
3381 u32 next;
3382
3383 val = rd32(hw, I40E_QINT_RQCTL(qp));
3384
3385 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3386 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3387 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3388 I40E_QINT_RQCTL_INTEVENT_MASK);
3389
3390 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3391 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3392
3393 wr32(hw, I40E_QINT_RQCTL(qp), val);
3394
3395 val = rd32(hw, I40E_QINT_TQCTL(qp));
3396
3397 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3398 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3399
3400 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3401 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3402 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3403 I40E_QINT_TQCTL_INTEVENT_MASK);
3404
3405 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3406 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3407
3408 wr32(hw, I40E_QINT_TQCTL(qp), val);
3409 qp = next;
3410 }
3411 }
3412 } else {
3413 free_irq(pf->pdev->irq, pf);
3414
3415 val = rd32(hw, I40E_PFINT_LNKLST0);
3416 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3417 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3418 val |= I40E_QUEUE_END_OF_LIST
3419 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3420 wr32(hw, I40E_PFINT_LNKLST0, val);
3421
3422 val = rd32(hw, I40E_QINT_RQCTL(qp));
3423 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3424 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3425 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3426 I40E_QINT_RQCTL_INTEVENT_MASK);
3427
3428 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3429 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3430
3431 wr32(hw, I40E_QINT_RQCTL(qp), val);
3432
3433 val = rd32(hw, I40E_QINT_TQCTL(qp));
3434
3435 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3436 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3437 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3438 I40E_QINT_TQCTL_INTEVENT_MASK);
3439
3440 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3441 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3442
3443 wr32(hw, I40E_QINT_TQCTL(qp), val);
3444 }
3445}
3446
493fb300
AD		 3447/**
3448 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3449 * @vsi: the VSI being configured
3450 * @v_idx: Index of vector to be freed
3451 *
3452 * This function frees the memory allocated to the q_vector. In addition if
3453 * NAPI is enabled it will delete any references to the NAPI struct prior
3454 * to freeing the q_vector.
3455 **/
3456static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3457{
3458 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3459 struct i40e_ring *ring;
493fb300
AD		 3460
3461 if (!q_vector)
3462 return;
3463
3464 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3465 i40e_for_each_ring(ring, q_vector->tx)
3466 ring->q_vector = NULL;
3467
3468 i40e_for_each_ring(ring, q_vector->rx)
3469 ring->q_vector = NULL;
493fb300
AD		 3470
3471 /* only VSI w/ an associated netdev is set up w/ NAPI */
3472 if (vsi->netdev)
3473 netif_napi_del(&q_vector->napi);
3474
3475 vsi->q_vectors[v_idx] = NULL;
3476
3477 kfree_rcu(q_vector, rcu);
3478}
3479
41c445ff
JB		 3480/**
3481 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3482 * @vsi: the VSI being un-configured
3483 *
3484 * This frees the memory allocated to the q_vectors and
3485 * deletes references to the NAPI struct.
3486 **/
3487static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3488{
3489 int v_idx;
3490
493fb300
AD		 3491 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3492 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3493}
3494
3495/**
3496 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3497 * @pf: board private structure
3498 **/
3499static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3500{
3501 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3502 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3503 pci_disable_msix(pf->pdev);
3504 kfree(pf->msix_entries);
3505 pf->msix_entries = NULL;
3506 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3507 pci_disable_msi(pf->pdev);
3508 }
3509 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3510}
3511
3512/**
3513 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3514 * @pf: board private structure
3515 *
3516 * We go through and clear interrupt specific resources and reset the structure
3517 * to pre-load conditions
3518 **/
3519static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3520{
3521 int i;
3522
3523 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3524 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3525 if (pf->vsi[i])
3526 i40e_vsi_free_q_vectors(pf->vsi[i]);
3527 i40e_reset_interrupt_capability(pf);
3528}
3529
3530/**
3531 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3532 * @vsi: the VSI being configured
3533 **/
3534static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3535{
3536 int q_idx;
3537
3538 if (!vsi->netdev)
3539 return;
3540
3541 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3542 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3543}
3544
3545/**
3546 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3547 * @vsi: the VSI being configured
3548 **/
3549static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3550{
3551 int q_idx;
3552
3553 if (!vsi->netdev)
3554 return;
3555
3556 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3557 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3558}
3559
90ef8d47
SN		 3560/**
3561 * i40e_vsi_close - Shut down a VSI
3562 * @vsi: the vsi to be quelled
3563 **/
3564static void i40e_vsi_close(struct i40e_vsi *vsi)
3565{
3566 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3567 i40e_down(vsi);
3568 i40e_vsi_free_irq(vsi);
3569 i40e_vsi_free_tx_resources(vsi);
3570 i40e_vsi_free_rx_resources(vsi);
3571}
3572
41c445ff
JB		 3573/**
3574 * i40e_quiesce_vsi - Pause a given VSI
3575 * @vsi: the VSI being paused
3576 **/
3577static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3578{
3579 if (test_bit(__I40E_DOWN, &vsi->state))
3580 return;
3581
3582 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3583 if (vsi->netdev && netif_running(vsi->netdev)) {
3584 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3585 } else {
90ef8d47 3586 i40e_vsi_close(vsi);
41c445ff
JB		 3587 }
3588}
3589
3590/**
3591 * i40e_unquiesce_vsi - Resume a given VSI
3592 * @vsi: the VSI being resumed
3593 **/
3594static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3595{
3596 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3597 return;
3598
3599 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3600 if (vsi->netdev && netif_running(vsi->netdev))
3601 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3602 else
8276f757 3603 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3604}
3605
3606/**
3607 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3608 * @pf: the PF
3609 **/
3610static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3611{
3612 int v;
3613
3614 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3615 if (pf->vsi[v])
3616 i40e_quiesce_vsi(pf->vsi[v]);
3617 }
3618}
3619
3620/**
3621 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3622 * @pf: the PF
3623 **/
3624static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3625{
3626 int v;
3627
3628 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3629 if (pf->vsi[v])
3630 i40e_unquiesce_vsi(pf->vsi[v]);
3631 }
3632}
3633
3634/**
3635 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3636 * @dcbcfg: the corresponding DCBx configuration structure
3637 *
3638 * Return the number of TCs from given DCBx configuration
3639 **/
3640static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3641{
078b5876
JB		 3642 u8 num_tc = 0;
3643 int i;
41c445ff
JB		 3644
3645 /* Scan the ETS Config Priority Table to find
3646 * traffic class enabled for a given priority
3647 * and use the traffic class index to get the
3648 * number of traffic classes enabled
3649 */
3650 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3651 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3652 num_tc = dcbcfg->etscfg.prioritytable[i];
3653 }
3654
3655 /* Traffic class index starts from zero so
3656 * increment to return the actual count
3657 */
078b5876 3658 return num_tc + 1;
41c445ff
JB		 3659}
3660
3661/**
3662 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3663 * @dcbcfg: the corresponding DCBx configuration structure
3664 *
3665 * Query the current DCB configuration and return the number of
3666 * traffic classes enabled from the given DCBX config
3667 **/
3668static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3669{
3670 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3671 u8 enabled_tc = 1;
3672 u8 i;
3673
3674 for (i = 0; i < num_tc; i++)
3675 enabled_tc |= 1 << i;
3676
3677 return enabled_tc;
3678}
3679
3680/**
3681 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3682 * @pf: PF being queried
3683 *
3684 * Return number of traffic classes enabled for the given PF
3685 **/
3686static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3687{
3688 struct i40e_hw *hw = &pf->hw;
3689 u8 i, enabled_tc;
3690 u8 num_tc = 0;
3691 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3692
3693 /* If DCB is not enabled then always in single TC */
3694 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3695 return 1;
3696
3697 /* MFP mode return count of enabled TCs for this PF */
3698 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3699 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3700 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3701 if (enabled_tc & (1 << i))
3702 num_tc++;
3703 }
3704 return num_tc;
3705 }
3706
3707 /* SFP mode will be enabled for all TCs on port */
3708 return i40e_dcb_get_num_tc(dcbcfg);
3709}
3710
3711/**
3712 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3713 * @pf: PF being queried
3714 *
3715 * Return a bitmap for first enabled traffic class for this PF.
3716 **/
3717static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3718{
3719 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3720 u8 i = 0;
3721
3722 if (!enabled_tc)
3723 return 0x1; /* TC0 */
3724
3725 /* Find the first enabled TC */
3726 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3727 if (enabled_tc & (1 << i))
3728 break;
3729 }
3730
3731 return 1 << i;
3732}
3733
3734/**
3735 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3736 * @pf: PF being queried
3737 *
3738 * Return a bitmap for enabled traffic classes for this PF.
3739 **/
3740static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3741{
3742 /* If DCB is not enabled for this PF then just return default TC */
3743 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3744 return i40e_pf_get_default_tc(pf);
3745
3746 /* MFP mode will have enabled TCs set by FW */
3747 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3748 return pf->hw.func_caps.enabled_tcmap;
3749
3750 /* SFP mode we want PF to be enabled for all TCs */
3751 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3752}
3753
3754/**
3755 * i40e_vsi_get_bw_info - Query VSI BW Information
3756 * @vsi: the VSI being queried
3757 *
3758 * Returns 0 on success, negative value on failure
3759 **/
3760static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3761{
3762 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3763 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3764 struct i40e_pf *pf = vsi->back;
3765 struct i40e_hw *hw = &pf->hw;
dcae29be 3766 i40e_status aq_ret;
41c445ff 3767 u32 tc_bw_max;
41c445ff
JB		 3768 int i;
3769
3770 /* Get the VSI level BW configuration */
dcae29be
JB		 3771 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3772 if (aq_ret) {
41c445ff
JB		 3773 dev_info(&pf->pdev->dev,
3774 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3775 aq_ret, pf->hw.aq.asq_last_status);
3776 return -EINVAL;
41c445ff
JB		 3777 }
3778
3779 /* Get the VSI level BW configuration per TC */
dcae29be 3780 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3781 NULL);
dcae29be 3782 if (aq_ret) {
41c445ff
JB		 3783 dev_info(&pf->pdev->dev,
3784 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3785 aq_ret, pf->hw.aq.asq_last_status);
3786 return -EINVAL;
41c445ff
JB		 3787 }
3788
3789 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3790 dev_info(&pf->pdev->dev,
3791 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3792 bw_config.tc_valid_bits,
3793 bw_ets_config.tc_valid_bits);
3794 /* Still continuing */
3795 }
3796
3797 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3798 vsi->bw_max_quanta = bw_config.max_bw;
3799 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3800 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3801 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3802 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3803 vsi->bw_ets_limit_credits[i] =
3804 le16_to_cpu(bw_ets_config.credits[i]);
3805 /* 3 bits out of 4 for each TC */
3806 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3807 }
078b5876 3808
dcae29be 3809 return 0;
41c445ff
JB		 3810}
3811
3812/**
3813 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3814 * @vsi: the VSI being configured
3815 * @enabled_tc: TC bitmap
3816 * @bw_credits: BW shared credits per TC
3817 *
3818 * Returns 0 on success, negative value on failure
3819 **/
dcae29be 3820static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3821 u8 *bw_share)
3822{
3823 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3824 i40e_status aq_ret;
3825 int i;
41c445ff
JB		 3826
3827 bw_data.tc_valid_bits = enabled_tc;
3828 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3829 bw_data.tc_bw_credits[i] = bw_share[i];
3830
dcae29be
JB		 3831 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3832 NULL);
3833 if (aq_ret) {
41c445ff 3834 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3835 "AQ command Config VSI BW allocation per TC failed = %d\n",
3836 vsi->back->hw.aq.asq_last_status);
dcae29be 3837 return -EINVAL;
41c445ff
JB		 3838 }
3839
3840 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3841 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3842
dcae29be 3843 return 0;
41c445ff
JB		 3844}
3845
3846/**
3847 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3848 * @vsi: the VSI being configured
3849 * @enabled_tc: TC map to be enabled
3850 *
3851 **/
3852static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3853{
3854 struct net_device *netdev = vsi->netdev;
3855 struct i40e_pf *pf = vsi->back;
3856 struct i40e_hw *hw = &pf->hw;
3857 u8 netdev_tc = 0;
3858 int i;
3859 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3860
3861 if (!netdev)
3862 return;
3863
3864 if (!enabled_tc) {
3865 netdev_reset_tc(netdev);
3866 return;
3867 }
3868
3869 /* Set up actual enabled TCs on the VSI */
3870 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3871 return;
3872
3873 /* set per TC queues for the VSI */
3874 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3875 /* Only set TC queues for enabled tcs
3876 *
3877 * e.g. For a VSI that has TC0 and TC3 enabled the
3878 * enabled_tc bitmap would be 0x00001001; the driver
3879 * will set the numtc for netdev as 2 that will be
3880 * referenced by the netdev layer as TC 0 and 1.
3881 */
3882 if (vsi->tc_config.enabled_tc & (1 << i))
3883 netdev_set_tc_queue(netdev,
3884 vsi->tc_config.tc_info[i].netdev_tc,
3885 vsi->tc_config.tc_info[i].qcount,
3886 vsi->tc_config.tc_info[i].qoffset);
3887 }
3888
3889 /* Assign UP2TC map for the VSI */
3890 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3891 /* Get the actual TC# for the UP */
3892 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3893 /* Get the mapped netdev TC# for the UP */
3894 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3895 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3896 }
3897}
3898
3899/**
3900 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3901 * @vsi: the VSI being configured
3902 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3903 **/
3904static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3905 struct i40e_vsi_context *ctxt)
3906{
3907 /* copy just the sections touched not the entire info
3908 * since not all sections are valid as returned by
3909 * update vsi params
3910 */
3911 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3912 memcpy(&vsi->info.queue_mapping,
3913 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3914 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3915 sizeof(vsi->info.tc_mapping));
3916}
3917
3918/**
3919 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3920 * @vsi: VSI to be configured
3921 * @enabled_tc: TC bitmap
3922 *
3923 * This configures a particular VSI for TCs that are mapped to the
3924 * given TC bitmap. It uses default bandwidth share for TCs across
3925 * VSIs to configure TC for a particular VSI.
3926 *
3927 * NOTE:
3928 * It is expected that the VSI queues have been quisced before calling
3929 * this function.
3930 **/
3931static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3932{
3933 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3934 struct i40e_vsi_context ctxt;
3935 int ret = 0;
3936 int i;
3937
3938 /* Check if enabled_tc is same as existing or new TCs */
3939 if (vsi->tc_config.enabled_tc == enabled_tc)
3940 return ret;
3941
3942 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3943 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3944 if (enabled_tc & (1 << i))
3945 bw_share[i] = 1;
3946 }
3947
3948 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3949 if (ret) {
3950 dev_info(&vsi->back->pdev->dev,
3951 "Failed configuring TC map %d for VSI %d\n",
3952 enabled_tc, vsi->seid);
3953 goto out;
3954 }
3955
3956 /* Update Queue Pairs Mapping for currently enabled UPs */
3957 ctxt.seid = vsi->seid;
3958 ctxt.pf_num = vsi->back->hw.pf_id;
3959 ctxt.vf_num = 0;
3960 ctxt.uplink_seid = vsi->uplink_seid;
3961 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3962 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3963
3964 /* Update the VSI after updating the VSI queue-mapping information */
3965 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3966 if (ret) {
3967 dev_info(&vsi->back->pdev->dev,
3968 "update vsi failed, aq_err=%d\n",
3969 vsi->back->hw.aq.asq_last_status);
3970 goto out;
3971 }
3972 /* update the local VSI info with updated queue map */
3973 i40e_vsi_update_queue_map(vsi, &ctxt);
3974 vsi->info.valid_sections = 0;
3975
3976 /* Update current VSI BW information */
3977 ret = i40e_vsi_get_bw_info(vsi);
3978 if (ret) {
3979 dev_info(&vsi->back->pdev->dev,
3980 "Failed updating vsi bw info, aq_err=%d\n",
3981 vsi->back->hw.aq.asq_last_status);
3982 goto out;
3983 }
3984
3985 /* Update the netdev TC setup */
3986 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3987out:
3988 return ret;
3989}
3990
4e3b35b0
NP		 3991/**
3992 * i40e_veb_config_tc - Configure TCs for given VEB
3993 * @veb: given VEB
3994 * @enabled_tc: TC bitmap
3995 *
3996 * Configures given TC bitmap for VEB (switching) element
3997 **/
3998int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3999{
4000 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4001 struct i40e_pf *pf = veb->pf;
4002 int ret = 0;
4003 int i;
4004
4005 /* No TCs or already enabled TCs just return */
4006 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4007 return ret;
4008
4009 bw_data.tc_valid_bits = enabled_tc;
4010 /* bw_data.absolute_credits is not set (relative) */
4011
4012 /* Enable ETS TCs with equal BW Share for now */
4013 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4014 if (enabled_tc & (1 << i))
4015 bw_data.tc_bw_share_credits[i] = 1;
4016 }
4017
4018 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4019 &bw_data, NULL);
4020 if (ret) {
4021 dev_info(&pf->pdev->dev,
4022 "veb bw config failed, aq_err=%d\n",
4023 pf->hw.aq.asq_last_status);
4024 goto out;
4025 }
4026
4027 /* Update the BW information */
4028 ret = i40e_veb_get_bw_info(veb);
4029 if (ret) {
4030 dev_info(&pf->pdev->dev,
4031 "Failed getting veb bw config, aq_err=%d\n",
4032 pf->hw.aq.asq_last_status);
4033 }
4034
4035out:
4036 return ret;
4037}
4038
4039#ifdef CONFIG_I40E_DCB
4040/**
4041 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4042 * @pf: PF struct
4043 *
4044 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4045 * the caller would've quiesce all the VSIs before calling
4046 * this function
4047 **/
4048static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4049{
4050 u8 tc_map = 0;
4051 int ret;
4052 u8 v;
4053
4054 /* Enable the TCs available on PF to all VEBs */
4055 tc_map = i40e_pf_get_tc_map(pf);
4056 for (v = 0; v < I40E_MAX_VEB; v++) {
4057 if (!pf->veb[v])
4058 continue;
4059 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4060 if (ret) {
4061 dev_info(&pf->pdev->dev,
4062 "Failed configuring TC for VEB seid=%d\n",
4063 pf->veb[v]->seid);
4064 /* Will try to configure as many components */
4065 }
4066 }
4067
4068 /* Update each VSI */
4069 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4070 if (!pf->vsi[v])
4071 continue;
4072
4073 /* - Enable all TCs for the LAN VSI
4074 * - For all others keep them at TC0 for now
4075 */
4076 if (v == pf->lan_vsi)
4077 tc_map = i40e_pf_get_tc_map(pf);
4078 else
4079 tc_map = i40e_pf_get_default_tc(pf);
4080
4081 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4082 if (ret) {
4083 dev_info(&pf->pdev->dev,
4084 "Failed configuring TC for VSI seid=%d\n",
4085 pf->vsi[v]->seid);
4086 /* Will try to configure as many components */
4087 } else {
0672a091
NP		 4088 /* Re-configure VSI vectors based on updated TC map */
4089 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4090 if (pf->vsi[v]->netdev)
4091 i40e_dcbnl_set_all(pf->vsi[v]);
4092 }
4093 }
4094}
4095
4096/**
4097 * i40e_init_pf_dcb - Initialize DCB configuration
4098 * @pf: PF being configured
4099 *
4100 * Query the current DCB configuration and cache it
4101 * in the hardware structure
4102 **/
4103static int i40e_init_pf_dcb(struct i40e_pf *pf)
4104{
4105 struct i40e_hw *hw = &pf->hw;
4106 int err = 0;
4107
4108 if (pf->hw.func_caps.npar_enable)
4109 goto out;
4110
4111 /* Get the initial DCB configuration */
4112 err = i40e_init_dcb(hw);
4113 if (!err) {
4114 /* Device/Function is not DCBX capable */
4115 if ((!hw->func_caps.dcb) ||
4116 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4117 dev_info(&pf->pdev->dev,
4118 "DCBX offload is not supported or is disabled for this PF.\n");
4119
4120 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4121 goto out;
4122
4123 } else {
4124 /* When status is not DISABLED then DCBX in FW */
4125 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4126 DCB_CAP_DCBX_VER_IEEE;
4127 pf->flags |= I40E_FLAG_DCB_ENABLED;
4128 }
014269ff
NP		 4129 } else {
4130 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4131 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4132 }
4133
4134out:
4135 return err;
4136}
4137#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4138#define SPEED_SIZE 14
4139#define FC_SIZE 8
4140/**
4141 * i40e_print_link_message - print link up or down
4142 * @vsi: the VSI for which link needs a message
4143 */
4144static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4145{
4146 char speed[SPEED_SIZE] = "Unknown";
4147 char fc[FC_SIZE] = "RX/TX";
4148
4149 if (!isup) {
4150 netdev_info(vsi->netdev, "NIC Link is Down\n");
4151 return;
4152 }
4153
4154 switch (vsi->back->hw.phy.link_info.link_speed) {
4155 case I40E_LINK_SPEED_40GB:
4156 strncpy(speed, "40 Gbps", SPEED_SIZE);
4157 break;
4158 case I40E_LINK_SPEED_10GB:
4159 strncpy(speed, "10 Gbps", SPEED_SIZE);
4160 break;
4161 case I40E_LINK_SPEED_1GB:
4162 strncpy(speed, "1000 Mbps", SPEED_SIZE);
4163 break;
4164 default:
4165 break;
4166 }
4167
4168 switch (vsi->back->hw.fc.current_mode) {
4169 case I40E_FC_FULL:
4170 strncpy(fc, "RX/TX", FC_SIZE);
4171 break;
4172 case I40E_FC_TX_PAUSE:
4173 strncpy(fc, "TX", FC_SIZE);
4174 break;
4175 case I40E_FC_RX_PAUSE:
4176 strncpy(fc, "RX", FC_SIZE);
4177 break;
4178 default:
4179 strncpy(fc, "None", FC_SIZE);
4180 break;
4181 }
4182
4183 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4184 speed, fc);
4185}
4e3b35b0 4186
41c445ff
JB		 4187/**
4188 * i40e_up_complete - Finish the last steps of bringing up a connection
4189 * @vsi: the VSI being configured
4190 **/
4191static int i40e_up_complete(struct i40e_vsi *vsi)
4192{
4193 struct i40e_pf *pf = vsi->back;
4194 int err;
4195
4196 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4197 i40e_vsi_configure_msix(vsi);
4198 else
4199 i40e_configure_msi_and_legacy(vsi);
4200
4201 /* start rings */
4202 err = i40e_vsi_control_rings(vsi, true);
4203 if (err)
4204 return err;
4205
4206 clear_bit(__I40E_DOWN, &vsi->state);
4207 i40e_napi_enable_all(vsi);
4208 i40e_vsi_enable_irq(vsi);
4209
4210 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4211 (vsi->netdev)) {
cf05ed08 4212 i40e_print_link_message(vsi, true);
41c445ff
JB		 4213 netif_tx_start_all_queues(vsi->netdev);
4214 netif_carrier_on(vsi->netdev);
6d779b41 4215 } else if (vsi->netdev) {
cf05ed08 4216 i40e_print_link_message(vsi, false);
41c445ff 4217 }
ca64fa4e
ASJ		 4218
4219 /* replay FDIR SB filters */
4220 if (vsi->type == I40E_VSI_FDIR)
4221 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4222 i40e_service_event_schedule(pf);
4223
4224 return 0;
4225}
4226
4227/**
4228 * i40e_vsi_reinit_locked - Reset the VSI
4229 * @vsi: the VSI being configured
4230 *
4231 * Rebuild the ring structs after some configuration
4232 * has changed, e.g. MTU size.
4233 **/
4234static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4235{
4236 struct i40e_pf *pf = vsi->back;
4237
4238 WARN_ON(in_interrupt());
4239 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4240 usleep_range(1000, 2000);
4241 i40e_down(vsi);
4242
4243 /* Give a VF some time to respond to the reset. The
4244 * two second wait is based upon the watchdog cycle in
4245 * the VF driver.
4246 */
4247 if (vsi->type == I40E_VSI_SRIOV)
4248 msleep(2000);
4249 i40e_up(vsi);
4250 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4251}
4252
4253/**
4254 * i40e_up - Bring the connection back up after being down
4255 * @vsi: the VSI being configured
4256 **/
4257int i40e_up(struct i40e_vsi *vsi)
4258{
4259 int err;
4260
4261 err = i40e_vsi_configure(vsi);
4262 if (!err)
4263 err = i40e_up_complete(vsi);
4264
4265 return err;
4266}
4267
4268/**
4269 * i40e_down - Shutdown the connection processing
4270 * @vsi: the VSI being stopped
4271 **/
4272void i40e_down(struct i40e_vsi *vsi)
4273{
4274 int i;
4275
4276 /* It is assumed that the caller of this function
4277 * sets the vsi->state __I40E_DOWN bit.
4278 */
4279 if (vsi->netdev) {
4280 netif_carrier_off(vsi->netdev);
4281 netif_tx_disable(vsi->netdev);
4282 }
4283 i40e_vsi_disable_irq(vsi);
4284 i40e_vsi_control_rings(vsi, false);
4285 i40e_napi_disable_all(vsi);
4286
4287 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4288 i40e_clean_tx_ring(vsi->tx_rings[i]);
4289 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4290 }
4291}
4292
4293/**
4294 * i40e_setup_tc - configure multiple traffic classes
4295 * @netdev: net device to configure
4296 * @tc: number of traffic classes to enable
4297 **/
4298static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4299{
4300 struct i40e_netdev_priv *np = netdev_priv(netdev);
4301 struct i40e_vsi *vsi = np->vsi;
4302 struct i40e_pf *pf = vsi->back;
4303 u8 enabled_tc = 0;
4304 int ret = -EINVAL;
4305 int i;
4306
4307 /* Check if DCB enabled to continue */
4308 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4309 netdev_info(netdev, "DCB is not enabled for adapter\n");
4310 goto exit;
4311 }
4312
4313 /* Check if MFP enabled */
4314 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4315 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4316 goto exit;
4317 }
4318
4319 /* Check whether tc count is within enabled limit */
4320 if (tc > i40e_pf_get_num_tc(pf)) {
4321 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4322 goto exit;
4323 }
4324
4325 /* Generate TC map for number of tc requested */
4326 for (i = 0; i < tc; i++)
4327 enabled_tc |= (1 << i);
4328
4329 /* Requesting same TC configuration as already enabled */
4330 if (enabled_tc == vsi->tc_config.enabled_tc)
4331 return 0;
4332
4333 /* Quiesce VSI queues */
4334 i40e_quiesce_vsi(vsi);
4335
4336 /* Configure VSI for enabled TCs */
4337 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4338 if (ret) {
4339 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4340 vsi->seid);
4341 goto exit;
4342 }
4343
4344 /* Unquiesce VSI */
4345 i40e_unquiesce_vsi(vsi);
4346
4347exit:
4348 return ret;
4349}
4350
4351/**
4352 * i40e_open - Called when a network interface is made active
4353 * @netdev: network interface device structure
4354 *
4355 * The open entry point is called when a network interface is made
4356 * active by the system (IFF_UP). At this point all resources needed
4357 * for transmit and receive operations are allocated, the interrupt
4358 * handler is registered with the OS, the netdev watchdog subtask is
4359 * enabled, and the stack is notified that the interface is ready.
4360 *
4361 * Returns 0 on success, negative value on failure
4362 **/
4363static int i40e_open(struct net_device *netdev)
4364{
4365 struct i40e_netdev_priv *np = netdev_priv(netdev);
4366 struct i40e_vsi *vsi = np->vsi;
4367 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4368 int err;
4369
4eb3f768
SN		 4370 /* disallow open during test or if eeprom is broken */
4371 if (test_bit(__I40E_TESTING, &pf->state) ||
4372 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4373 return -EBUSY;
4374
4375 netif_carrier_off(netdev);
4376
6c167f58
EK		 4377 err = i40e_vsi_open(vsi);
4378 if (err)
4379 return err;
4380
059dab69
JB		 4381 /* configure global TSO hardware offload settings */
4382 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4383 TCP_FLAG_FIN) >> 16);
4384 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4385 TCP_FLAG_FIN |
4386 TCP_FLAG_CWR) >> 16);
4387 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4388
6c167f58
EK		 4389#ifdef CONFIG_I40E_VXLAN
4390 vxlan_get_rx_port(netdev);
4391#endif
4392
4393 return 0;
4394}
4395
4396/**
4397 * i40e_vsi_open -
4398 * @vsi: the VSI to open
4399 *
4400 * Finish initialization of the VSI.
4401 *
4402 * Returns 0 on success, negative value on failure
4403 **/
4404int i40e_vsi_open(struct i40e_vsi *vsi)
4405{
4406 struct i40e_pf *pf = vsi->back;
4407 char int_name[IFNAMSIZ];
4408 int err;
4409
41c445ff
JB		 4410 /* allocate descriptors */
4411 err = i40e_vsi_setup_tx_resources(vsi);
4412 if (err)
4413 goto err_setup_tx;
4414 err = i40e_vsi_setup_rx_resources(vsi);
4415 if (err)
4416 goto err_setup_rx;
4417
4418 err = i40e_vsi_configure(vsi);
4419 if (err)
4420 goto err_setup_rx;
4421
c22e3c6c
SN		 4422 if (vsi->netdev) {
4423 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4424 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4425 err = i40e_vsi_request_irq(vsi, int_name);
4426 if (err)
4427 goto err_setup_rx;
4428
4429 /* Notify the stack of the actual queue counts. */
4430 err = netif_set_real_num_tx_queues(vsi->netdev,
4431 vsi->num_queue_pairs);
4432 if (err)
4433 goto err_set_queues;
4434
4435 err = netif_set_real_num_rx_queues(vsi->netdev,
4436 vsi->num_queue_pairs);
4437 if (err)
4438 goto err_set_queues;
8a9eb7d3
SN		 4439
4440 } else if (vsi->type == I40E_VSI_FDIR) {
4441 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4442 dev_driver_string(&pf->pdev->dev));
4443 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4444 } else {
ce9ccb17 4445 err = -EINVAL;
6c167f58
EK		 4446 goto err_setup_rx;
4447 }
25946ddb 4448
41c445ff
JB		 4449 err = i40e_up_complete(vsi);
4450 if (err)
4451 goto err_up_complete;
4452
41c445ff
JB		 4453 return 0;
4454
4455err_up_complete:
4456 i40e_down(vsi);
25946ddb 4457err_set_queues:
41c445ff
JB		 4458 i40e_vsi_free_irq(vsi);
4459err_setup_rx:
4460 i40e_vsi_free_rx_resources(vsi);
4461err_setup_tx:
4462 i40e_vsi_free_tx_resources(vsi);
4463 if (vsi == pf->vsi[pf->lan_vsi])
4464 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4465
4466 return err;
4467}
4468
17a73f6b
JG		 4469/**
4470 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4471 * @pf: Pointer to pf
4472 *
4473 * This function destroys the hlist where all the Flow Director
4474 * filters were saved.
4475 **/
4476static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4477{
4478 struct i40e_fdir_filter *filter;
4479 struct hlist_node *node2;
4480
4481 hlist_for_each_entry_safe(filter, node2,
4482 &pf->fdir_filter_list, fdir_node) {
4483 hlist_del(&filter->fdir_node);
4484 kfree(filter);
4485 }
4486 pf->fdir_pf_active_filters = 0;
4487}
4488
41c445ff
JB		 4489/**
4490 * i40e_close - Disables a network interface
4491 * @netdev: network interface device structure
4492 *
4493 * The close entry point is called when an interface is de-activated
4494 * by the OS. The hardware is still under the driver's control, but
4495 * this netdev interface is disabled.
4496 *
4497 * Returns 0, this is not allowed to fail
4498 **/
4499static int i40e_close(struct net_device *netdev)
4500{
4501 struct i40e_netdev_priv *np = netdev_priv(netdev);
4502 struct i40e_vsi *vsi = np->vsi;
4503
90ef8d47 4504 i40e_vsi_close(vsi);
41c445ff
JB		 4505
4506 return 0;
4507}
4508
4509/**
4510 * i40e_do_reset - Start a PF or Core Reset sequence
4511 * @pf: board private structure
4512 * @reset_flags: which reset is requested
4513 *
4514 * The essential difference in resets is that the PF Reset
4515 * doesn't clear the packet buffers, doesn't reset the PE
4516 * firmware, and doesn't bother the other PFs on the chip.
4517 **/
4518void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4519{
4520 u32 val;
4521
4522 WARN_ON(in_interrupt());
4523
263fc48f
MW		 4524 if (i40e_check_asq_alive(&pf->hw))
4525 i40e_vc_notify_reset(pf);
4526
41c445ff
JB		 4527 /* do the biggest reset indicated */
4528 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4529
4530 /* Request a Global Reset
4531 *
4532 * This will start the chip's countdown to the actual full
4533 * chip reset event, and a warning interrupt to be sent
4534 * to all PFs, including the requestor. Our handler
4535 * for the warning interrupt will deal with the shutdown
4536 * and recovery of the switch setup.
4537 */
69bfb110 4538 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4539 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4540 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4541 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4542
4543 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4544
4545 /* Request a Core Reset
4546 *
4547 * Same as Global Reset, except does *not* include the MAC/PHY
4548 */
69bfb110 4549 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4550 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4551 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4552 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4553 i40e_flush(&pf->hw);
4554
7823fe34
SN		 4555 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4556
4557 /* Request a Firmware Reset
4558 *
4559 * Same as Global reset, plus restarting the
4560 * embedded firmware engine.
4561 */
4562 /* enable EMP Reset */
4563 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4564 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4565 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4566
4567 /* force the reset */
4568 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4569 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4570 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4571 i40e_flush(&pf->hw);
4572
41c445ff
JB		 4573 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4574
4575 /* Request a PF Reset
4576 *
4577 * Resets only the PF-specific registers
4578 *
4579 * This goes directly to the tear-down and rebuild of
4580 * the switch, since we need to do all the recovery as
4581 * for the Core Reset.
4582 */
69bfb110 4583 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4584 i40e_handle_reset_warning(pf);
4585
4586 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4587 int v;
4588
4589 /* Find the VSI(s) that requested a re-init */
4590 dev_info(&pf->pdev->dev,
4591 "VSI reinit requested\n");
4592 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4593 struct i40e_vsi *vsi = pf->vsi[v];
4594 if (vsi != NULL &&
4595 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4596 i40e_vsi_reinit_locked(pf->vsi[v]);
4597 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4598 }
4599 }
4600
4601 /* no further action needed, so return now */
4602 return;
4603 } else {
4604 dev_info(&pf->pdev->dev,
4605 "bad reset request 0x%08x\n", reset_flags);
4606 return;
4607 }
4608}
4609
4e3b35b0
NP		 4610#ifdef CONFIG_I40E_DCB
4611/**
4612 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4613 * @pf: board private structure
4614 * @old_cfg: current DCB config
4615 * @new_cfg: new DCB config
4616 **/
4617bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4618 struct i40e_dcbx_config *old_cfg,
4619 struct i40e_dcbx_config *new_cfg)
4620{
4621 bool need_reconfig = false;
4622
4623 /* Check if ETS configuration has changed */
4624 if (memcmp(&new_cfg->etscfg,
4625 &old_cfg->etscfg,
4626 sizeof(new_cfg->etscfg))) {
4627 /* If Priority Table has changed reconfig is needed */
4628 if (memcmp(&new_cfg->etscfg.prioritytable,
4629 &old_cfg->etscfg.prioritytable,
4630 sizeof(new_cfg->etscfg.prioritytable))) {
4631 need_reconfig = true;
69bfb110 4632 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4633 }
4634
4635 if (memcmp(&new_cfg->etscfg.tcbwtable,
4636 &old_cfg->etscfg.tcbwtable,
4637 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4638 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4639
4640 if (memcmp(&new_cfg->etscfg.tsatable,
4641 &old_cfg->etscfg.tsatable,
4642 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4643 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4644 }
4645
4646 /* Check if PFC configuration has changed */
4647 if (memcmp(&new_cfg->pfc,
4648 &old_cfg->pfc,
4649 sizeof(new_cfg->pfc))) {
4650 need_reconfig = true;
69bfb110 4651 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4652 }
4653
4654 /* Check if APP Table has changed */
4655 if (memcmp(&new_cfg->app,
4656 &old_cfg->app,
3d9667a9 4657 sizeof(new_cfg->app))) {
4e3b35b0 4658 need_reconfig = true;
69bfb110 4659 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4660 }
4e3b35b0
NP		 4661
4662 return need_reconfig;
4663}
4664
4665/**
4666 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4667 * @pf: board private structure
4668 * @e: event info posted on ARQ
4669 **/
4670static int i40e_handle_lldp_event(struct i40e_pf *pf,
4671 struct i40e_arq_event_info *e)
4672{
4673 struct i40e_aqc_lldp_get_mib *mib =
4674 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4675 struct i40e_hw *hw = &pf->hw;
4676 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4677 struct i40e_dcbx_config tmp_dcbx_cfg;
4678 bool need_reconfig = false;
4679 int ret = 0;
4680 u8 type;
4681
4682 /* Ignore if event is not for Nearest Bridge */
4683 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4684 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4685 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4686 return ret;
4687
4688 /* Check MIB Type and return if event for Remote MIB update */
4689 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4690 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4691 /* Update the remote cached instance and return */
4692 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4693 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4694 &hw->remote_dcbx_config);
4695 goto exit;
4696 }
4697
4698 /* Convert/store the DCBX data from LLDPDU temporarily */
4699 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4700 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4701 if (ret) {
4702 /* Error in LLDPDU parsing return */
4703 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4704 goto exit;
4705 }
4706
4707 /* No change detected in DCBX configs */
4708 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4709 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4710 goto exit;
4711 }
4712
4713 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4714
4715 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4716
4717 /* Overwrite the new configuration */
4718 *dcbx_cfg = tmp_dcbx_cfg;
4719
4720 if (!need_reconfig)
4721 goto exit;
4722
4723 /* Reconfiguration needed quiesce all VSIs */
4724 i40e_pf_quiesce_all_vsi(pf);
4725
4726 /* Changes in configuration update VEB/VSI */
4727 i40e_dcb_reconfigure(pf);
4728
4729 i40e_pf_unquiesce_all_vsi(pf);
4730exit:
4731 return ret;
4732}
4733#endif /* CONFIG_I40E_DCB */
4734
23326186
ASJ		 4735/**
4736 * i40e_do_reset_safe - Protected reset path for userland calls.
4737 * @pf: board private structure
4738 * @reset_flags: which reset is requested
4739 *
4740 **/
4741void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4742{
4743 rtnl_lock();
4744 i40e_do_reset(pf, reset_flags);
4745 rtnl_unlock();
4746}
4747
41c445ff
JB		 4748/**
4749 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4750 * @pf: board private structure
4751 * @e: event info posted on ARQ
4752 *
4753 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4754 * and VF queues
4755 **/
4756static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4757 struct i40e_arq_event_info *e)
4758{
4759 struct i40e_aqc_lan_overflow *data =
4760 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4761 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4762 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4763 struct i40e_hw *hw = &pf->hw;
4764 struct i40e_vf *vf;
4765 u16 vf_id;
4766
69bfb110
JB		 4767 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4768 queue, qtx_ctl);
41c445ff
JB		 4769
4770 /* Queue belongs to VF, find the VF and issue VF reset */
4771 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4772 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4773 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4774 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4775 vf_id -= hw->func_caps.vf_base_id;
4776 vf = &pf->vf[vf_id];
4777 i40e_vc_notify_vf_reset(vf);
4778 /* Allow VF to process pending reset notification */
4779 msleep(20);
4780 i40e_reset_vf(vf, false);
4781 }
4782}
4783
4784/**
4785 * i40e_service_event_complete - Finish up the service event
4786 * @pf: board private structure
4787 **/
4788static void i40e_service_event_complete(struct i40e_pf *pf)
4789{
4790 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4791
4792 /* flush memory to make sure state is correct before next watchog */
4793 smp_mb__before_clear_bit();
4794 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4795}
4796
55a5e60b
ASJ		 4797/**
4798 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4799 * @pf: board private structure
4800 **/
4801int i40e_get_current_fd_count(struct i40e_pf *pf)
4802{
4803 int val, fcnt_prog;
4804 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4805 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4806 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4807 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4808 return fcnt_prog;
4809}
4810
4811/**
4812 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4813 * @pf: board private structure
4814 **/
4815void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4816{
4817 u32 fcnt_prog, fcnt_avail;
4818
4819 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4820 * to re-enable
4821 */
4822 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4823 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4824 return;
4825 fcnt_prog = i40e_get_current_fd_count(pf);
89132783 4826 fcnt_avail = i40e_get_fd_cnt_all(pf);
55a5e60b
ASJ		 4827 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4828 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4829 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4830 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4831 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4832 }
4833 }
4834 /* Wait for some more space to be available to turn on ATR */
4835 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4836 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4837 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4838 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4839 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4840 }
4841 }
4842}
4843
41c445ff
JB		 4844/**
4845 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4846 * @pf: board private structure
4847 **/
4848static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4849{
4850 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4851 return;
4852
41c445ff
JB		 4853 /* if interface is down do nothing */
4854 if (test_bit(__I40E_DOWN, &pf->state))
4855 return;
55a5e60b
ASJ		 4856 i40e_fdir_check_and_reenable(pf);
4857
4858 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4859 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4860 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4861}
4862
4863/**
4864 * i40e_vsi_link_event - notify VSI of a link event
4865 * @vsi: vsi to be notified
4866 * @link_up: link up or down
4867 **/
4868static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4869{
4870 if (!vsi)
4871 return;
4872
4873 switch (vsi->type) {
4874 case I40E_VSI_MAIN:
4875 if (!vsi->netdev || !vsi->netdev_registered)
4876 break;
4877
4878 if (link_up) {
4879 netif_carrier_on(vsi->netdev);
4880 netif_tx_wake_all_queues(vsi->netdev);
4881 } else {
4882 netif_carrier_off(vsi->netdev);
4883 netif_tx_stop_all_queues(vsi->netdev);
4884 }
4885 break;
4886
4887 case I40E_VSI_SRIOV:
4888 break;
4889
4890 case I40E_VSI_VMDQ2:
4891 case I40E_VSI_CTRL:
4892 case I40E_VSI_MIRROR:
4893 default:
4894 /* there is no notification for other VSIs */
4895 break;
4896 }
4897}
4898
4899/**
4900 * i40e_veb_link_event - notify elements on the veb of a link event
4901 * @veb: veb to be notified
4902 * @link_up: link up or down
4903 **/
4904static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4905{
4906 struct i40e_pf *pf;
4907 int i;
4908
4909 if (!veb || !veb->pf)
4910 return;
4911 pf = veb->pf;
4912
4913 /* depth first... */
4914 for (i = 0; i < I40E_MAX_VEB; i++)
4915 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4916 i40e_veb_link_event(pf->veb[i], link_up);
4917
4918 /* ... now the local VSIs */
4919 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4920 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4921 i40e_vsi_link_event(pf->vsi[i], link_up);
4922}
4923
4924/**
4925 * i40e_link_event - Update netif_carrier status
4926 * @pf: board private structure
4927 **/
4928static void i40e_link_event(struct i40e_pf *pf)
4929{
4930 bool new_link, old_link;
4931
4932 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4933 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4934
4935 if (new_link == old_link)
4936 return;
6d779b41 4937 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 4938 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 4939
4940 /* Notify the base of the switch tree connected to
4941 * the link. Floating VEBs are not notified.
4942 */
4943 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4944 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4945 else
4946 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4947
4948 if (pf->vf)
4949 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4950
4951 if (pf->flags & I40E_FLAG_PTP)
4952 i40e_ptp_set_increment(pf);
41c445ff
JB		 4953}
4954
4955/**
4956 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4957 * @pf: board private structure
4958 *
4959 * Set the per-queue flags to request a check for stuck queues in the irq
4960 * clean functions, then force interrupts to be sure the irq clean is called.
4961 **/
4962static void i40e_check_hang_subtask(struct i40e_pf *pf)
4963{
4964 int i, v;
4965
4966 /* If we're down or resetting, just bail */
4967 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4968 return;
4969
4970 /* for each VSI/netdev
4971 * for each Tx queue
4972 * set the check flag
4973 * for each q_vector
4974 * force an interrupt
4975 */
4976 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4977 struct i40e_vsi *vsi = pf->vsi[v];
4978 int armed = 0;
4979
4980 if (!pf->vsi[v] ||
4981 test_bit(__I40E_DOWN, &vsi->state) ||
4982 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4983 continue;
4984
4985 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4986 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4987 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4988 &vsi->tx_rings[i]->state))
41c445ff
JB		 4989 armed++;
4990 }
4991
4992 if (armed) {
4993 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4994 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4995 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4996 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4997 } else {
4998 u16 vec = vsi->base_vector - 1;
4999 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5000 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5001 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5002 wr32(&vsi->back->hw,
5003 I40E_PFINT_DYN_CTLN(vec), val);
5004 }
5005 i40e_flush(&vsi->back->hw);
5006 }
5007 }
5008}
5009
5010/**
5011 * i40e_watchdog_subtask - Check and bring link up
5012 * @pf: board private structure
5013 **/
5014static void i40e_watchdog_subtask(struct i40e_pf *pf)
5015{
5016 int i;
5017
5018 /* if interface is down do nothing */
5019 if (test_bit(__I40E_DOWN, &pf->state) ||
5020 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5021 return;
5022
5023 /* Update the stats for active netdevs so the network stack
5024 * can look at updated numbers whenever it cares to
5025 */
5026 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
5027 if (pf->vsi[i] && pf->vsi[i]->netdev)
5028 i40e_update_stats(pf->vsi[i]);
5029
5030 /* Update the stats for the active switching components */
5031 for (i = 0; i < I40E_MAX_VEB; i++)
5032 if (pf->veb[i])
5033 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5034
5035 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5036}
5037
5038/**
5039 * i40e_reset_subtask - Set up for resetting the device and driver
5040 * @pf: board private structure
5041 **/
5042static void i40e_reset_subtask(struct i40e_pf *pf)
5043{
5044 u32 reset_flags = 0;
5045
23326186 5046 rtnl_lock();
41c445ff
JB		 5047 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5048 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5049 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5050 }
5051 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5052 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5053 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5054 }
5055 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5056 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5057 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5058 }
5059 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5060 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5061 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5062 }
5063
5064 /* If there's a recovery already waiting, it takes
5065 * precedence before starting a new reset sequence.
5066 */
5067 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5068 i40e_handle_reset_warning(pf);
23326186 5069 goto unlock;
41c445ff
JB		 5070 }
5071
5072 /* If we're already down or resetting, just bail */
5073 if (reset_flags &&
5074 !test_bit(__I40E_DOWN, &pf->state) &&
5075 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5076 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5077
5078unlock:
5079 rtnl_unlock();
41c445ff
JB		 5080}
5081
5082/**
5083 * i40e_handle_link_event - Handle link event
5084 * @pf: board private structure
5085 * @e: event info posted on ARQ
5086 **/
5087static void i40e_handle_link_event(struct i40e_pf *pf,
5088 struct i40e_arq_event_info *e)
5089{
5090 struct i40e_hw *hw = &pf->hw;
5091 struct i40e_aqc_get_link_status *status =
5092 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5093 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5094
5095 /* save off old link status information */
5096 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5097 sizeof(pf->hw.phy.link_info_old));
5098
5099 /* update link status */
5100 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5101 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5102 hw_link_info->link_info = status->link_info;
5103 hw_link_info->an_info = status->an_info;
5104 hw_link_info->ext_info = status->ext_info;
5105 hw_link_info->lse_enable =
5106 le16_to_cpu(status->command_flags) &
5107 I40E_AQ_LSE_ENABLE;
5108
5109 /* process the event */
5110 i40e_link_event(pf);
5111
5112 /* Do a new status request to re-enable LSE reporting
5113 * and load new status information into the hw struct,
5114 * then see if the status changed while processing the
5115 * initial event.
5116 */
5117 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5118 i40e_link_event(pf);
5119}
5120
5121/**
5122 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5123 * @pf: board private structure
5124 **/
5125static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5126{
5127 struct i40e_arq_event_info event;
5128 struct i40e_hw *hw = &pf->hw;
5129 u16 pending, i = 0;
5130 i40e_status ret;
5131 u16 opcode;
5132 u32 val;
5133
5134 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5135 return;
5136
3197ce22 5137 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5138 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5139 if (!event.msg_buf)
5140 return;
5141
5142 do {
2f019123 5143 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5144 ret = i40e_clean_arq_element(hw, &event, &pending);
5145 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5146 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5147 break;
5148 } else if (ret) {
5149 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5150 break;
5151 }
5152
5153 opcode = le16_to_cpu(event.desc.opcode);
5154 switch (opcode) {
5155
5156 case i40e_aqc_opc_get_link_status:
5157 i40e_handle_link_event(pf, &event);
5158 break;
5159 case i40e_aqc_opc_send_msg_to_pf:
5160 ret = i40e_vc_process_vf_msg(pf,
5161 le16_to_cpu(event.desc.retval),
5162 le32_to_cpu(event.desc.cookie_high),
5163 le32_to_cpu(event.desc.cookie_low),
5164 event.msg_buf,
5165 event.msg_size);
5166 break;
5167 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5168 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5169#ifdef CONFIG_I40E_DCB
5170 rtnl_lock();
5171 ret = i40e_handle_lldp_event(pf, &event);
5172 rtnl_unlock();
5173#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5174 break;
5175 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5176 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5177 i40e_handle_lan_overflow_event(pf, &event);
5178 break;
0467bc91
SN		 5179 case i40e_aqc_opc_send_msg_to_peer:
5180 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5181 break;
41c445ff
JB		 5182 default:
5183 dev_info(&pf->pdev->dev,
0467bc91
SN		 5184 "ARQ Error: Unknown event 0x%04x received\n",
5185 opcode);
41c445ff
JB		 5186 break;
5187 }
5188 } while (pending && (i++ < pf->adminq_work_limit));
5189
5190 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5191 /* re-enable Admin queue interrupt cause */
5192 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5193 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5194 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5195 i40e_flush(hw);
5196
5197 kfree(event.msg_buf);
5198}
5199
4eb3f768
SN		 5200/**
5201 * i40e_verify_eeprom - make sure eeprom is good to use
5202 * @pf: board private structure
5203 **/
5204static void i40e_verify_eeprom(struct i40e_pf *pf)
5205{
5206 int err;
5207
5208 err = i40e_diag_eeprom_test(&pf->hw);
5209 if (err) {
5210 /* retry in case of garbage read */
5211 err = i40e_diag_eeprom_test(&pf->hw);
5212 if (err) {
5213 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5214 err);
5215 set_bit(__I40E_BAD_EEPROM, &pf->state);
5216 }
5217 }
5218
5219 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5220 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5221 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5222 }
5223}
5224
41c445ff
JB		 5225/**
5226 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5227 * @veb: pointer to the VEB instance
5228 *
5229 * This is a recursive function that first builds the attached VSIs then
5230 * recurses in to build the next layer of VEB. We track the connections
5231 * through our own index numbers because the seid's from the HW could
5232 * change across the reset.
5233 **/
5234static int i40e_reconstitute_veb(struct i40e_veb *veb)
5235{
5236 struct i40e_vsi *ctl_vsi = NULL;
5237 struct i40e_pf *pf = veb->pf;
5238 int v, veb_idx;
5239 int ret;
5240
5241 /* build VSI that owns this VEB, temporarily attached to base VEB */
5242 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5243 if (pf->vsi[v] &&
5244 pf->vsi[v]->veb_idx == veb->idx &&
5245 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5246 ctl_vsi = pf->vsi[v];
5247 break;
5248 }
5249 }
5250 if (!ctl_vsi) {
5251 dev_info(&pf->pdev->dev,
5252 "missing owner VSI for veb_idx %d\n", veb->idx);
5253 ret = -ENOENT;
5254 goto end_reconstitute;
5255 }
5256 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5257 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5258 ret = i40e_add_vsi(ctl_vsi);
5259 if (ret) {
5260 dev_info(&pf->pdev->dev,
5261 "rebuild of owner VSI failed: %d\n", ret);
5262 goto end_reconstitute;
5263 }
5264 i40e_vsi_reset_stats(ctl_vsi);
5265
5266 /* create the VEB in the switch and move the VSI onto the VEB */
5267 ret = i40e_add_veb(veb, ctl_vsi);
5268 if (ret)
5269 goto end_reconstitute;
5270
5271 /* create the remaining VSIs attached to this VEB */
5272 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5273 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5274 continue;
5275
5276 if (pf->vsi[v]->veb_idx == veb->idx) {
5277 struct i40e_vsi *vsi = pf->vsi[v];
5278 vsi->uplink_seid = veb->seid;
5279 ret = i40e_add_vsi(vsi);
5280 if (ret) {
5281 dev_info(&pf->pdev->dev,
5282 "rebuild of vsi_idx %d failed: %d\n",
5283 v, ret);
5284 goto end_reconstitute;
5285 }
5286 i40e_vsi_reset_stats(vsi);
5287 }
5288 }
5289
5290 /* create any VEBs attached to this VEB - RECURSION */
5291 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5292 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5293 pf->veb[veb_idx]->uplink_seid = veb->seid;
5294 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5295 if (ret)
5296 break;
5297 }
5298 }
5299
5300end_reconstitute:
5301 return ret;
5302}
5303
5304/**
5305 * i40e_get_capabilities - get info about the HW
5306 * @pf: the PF struct
5307 **/
5308static int i40e_get_capabilities(struct i40e_pf *pf)
5309{
5310 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5311 u16 data_size;
5312 int buf_len;
5313 int err;
5314
5315 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5316 do {
5317 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5318 if (!cap_buf)
5319 return -ENOMEM;
5320
5321 /* this loads the data into the hw struct for us */
5322 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5323 &data_size,
5324 i40e_aqc_opc_list_func_capabilities,
5325 NULL);
5326 /* data loaded, buffer no longer needed */
5327 kfree(cap_buf);
5328
5329 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5330 /* retry with a larger buffer */
5331 buf_len = data_size;
5332 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5333 dev_info(&pf->pdev->dev,
5334 "capability discovery failed: aq=%d\n",
5335 pf->hw.aq.asq_last_status);
5336 return -ENODEV;
5337 }
5338 } while (err);
5339
ac71b7ba
ASJ		 5340 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5341 (pf->hw.aq.fw_maj_ver < 2)) {
5342 pf->hw.func_caps.num_msix_vectors++;
5343 pf->hw.func_caps.num_msix_vectors_vf++;
5344 }
5345
41c445ff
JB		 5346 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5347 dev_info(&pf->pdev->dev,
5348 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5349 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5350 pf->hw.func_caps.num_msix_vectors,
5351 pf->hw.func_caps.num_msix_vectors_vf,
5352 pf->hw.func_caps.fd_filters_guaranteed,
5353 pf->hw.func_caps.fd_filters_best_effort,
5354 pf->hw.func_caps.num_tx_qp,
5355 pf->hw.func_caps.num_vsis);
5356
7134f9ce
JB		 5357#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5358 + pf->hw.func_caps.num_vfs)
5359 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5360 dev_info(&pf->pdev->dev,
5361 "got num_vsis %d, setting num_vsis to %d\n",
5362 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5363 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5364 }
5365
41c445ff
JB		 5366 return 0;
5367}
5368
cbf61325
ASJ		 5369static int i40e_vsi_clear(struct i40e_vsi *vsi);
5370
41c445ff 5371/**
cbf61325 5372 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5373 * @pf: board private structure
5374 **/
cbf61325 5375static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5376{
5377 struct i40e_vsi *vsi;
8a9eb7d3 5378 int i;
41c445ff 5379
cbf61325 5380 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5381 return;
5382
cbf61325 5383 /* find existing VSI and see if it needs configuring */
41c445ff 5384 vsi = NULL;
cbf61325
ASJ		 5385 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5386 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5387 vsi = pf->vsi[i];
cbf61325
ASJ		 5388 break;
5389 }
5390 }
5391
5392 /* create a new VSI if none exists */
41c445ff 5393 if (!vsi) {
cbf61325
ASJ		 5394 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5395 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5396 if (!vsi) {
5397 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5398 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5399 return;
41c445ff 5400 }
41c445ff 5401 }
cbf61325 5402
8a9eb7d3 5403 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5404}
5405
5406/**
5407 * i40e_fdir_teardown - release the Flow Director resources
5408 * @pf: board private structure
5409 **/
5410static void i40e_fdir_teardown(struct i40e_pf *pf)
5411{
5412 int i;
5413
17a73f6b 5414 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5415 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5416 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5417 i40e_vsi_release(pf->vsi[i]);
5418 break;
5419 }
5420 }
5421}
5422
5423/**
f650a38b 5424 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5425 * @pf: board private structure
5426 *
f650a38b
ASJ		 5427 * Close up the VFs and other things in prep for pf Reset.
5428 **/
5429static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5430{
41c445ff
JB		 5431 struct i40e_hw *hw = &pf->hw;
5432 i40e_status ret;
5433 u32 v;
5434
5435 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5436 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5437 return 0;
41c445ff 5438
69bfb110 5439 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5440
41c445ff
JB		 5441 /* quiesce the VSIs and their queues that are not already DOWN */
5442 i40e_pf_quiesce_all_vsi(pf);
5443
5444 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5445 if (pf->vsi[v])
5446 pf->vsi[v]->seid = 0;
5447 }
5448
5449 i40e_shutdown_adminq(&pf->hw);
5450
f650a38b
ASJ		 5451 /* call shutdown HMC */
5452 ret = i40e_shutdown_lan_hmc(hw);
5453 if (ret) {
5454 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5455 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5456 }
5457 return ret;
5458}
5459
44033fac
JB		 5460/**
5461 * i40e_send_version - update firmware with driver version
5462 * @pf: PF struct
5463 */
5464static void i40e_send_version(struct i40e_pf *pf)
5465{
5466 struct i40e_driver_version dv;
5467
5468 dv.major_version = DRV_VERSION_MAJOR;
5469 dv.minor_version = DRV_VERSION_MINOR;
5470 dv.build_version = DRV_VERSION_BUILD;
5471 dv.subbuild_version = 0;
5472 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
5473 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5474}
5475
f650a38b 5476/**
4dda12e6 5477 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5478 * @pf: board private structure
bc7d338f 5479 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5480 **/
bc7d338f 5481static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5482{
f650a38b
ASJ		 5483 struct i40e_hw *hw = &pf->hw;
5484 i40e_status ret;
5485 u32 v;
5486
41c445ff
JB		 5487 /* Now we wait for GRST to settle out.
5488 * We don't have to delete the VEBs or VSIs from the hw switch
5489 * because the reset will make them disappear.
5490 */
5491 ret = i40e_pf_reset(hw);
b5565400 5492 if (ret) {
41c445ff 5493 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5494 goto end_core_reset;
5495 }
41c445ff
JB		 5496 pf->pfr_count++;
5497
5498 if (test_bit(__I40E_DOWN, &pf->state))
5499 goto end_core_reset;
69bfb110 5500 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5501
5502 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5503 ret = i40e_init_adminq(&pf->hw);
5504 if (ret) {
5505 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5506 goto end_core_reset;
5507 }
5508
4eb3f768
SN		 5509 /* re-verify the eeprom if we just had an EMP reset */
5510 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5511 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5512 i40e_verify_eeprom(pf);
5513 }
5514
41c445ff
JB		 5515 ret = i40e_get_capabilities(pf);
5516 if (ret) {
5517 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5518 ret);
5519 goto end_core_reset;
5520 }
5521
41c445ff
JB		 5522 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5523 hw->func_caps.num_rx_qp,
5524 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5525 if (ret) {
5526 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5527 goto end_core_reset;
5528 }
5529 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5530 if (ret) {
5531 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5532 goto end_core_reset;
5533 }
5534
4e3b35b0
NP		 5535#ifdef CONFIG_I40E_DCB
5536 ret = i40e_init_pf_dcb(pf);
5537 if (ret) {
5538 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5539 goto end_core_reset;
5540 }
5541#endif /* CONFIG_I40E_DCB */
5542
41c445ff 5543 /* do basic switch setup */
bc7d338f 5544 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5545 if (ret)
5546 goto end_core_reset;
5547
5548 /* Rebuild the VSIs and VEBs that existed before reset.
5549 * They are still in our local switch element arrays, so only
5550 * need to rebuild the switch model in the HW.
5551 *
5552 * If there were VEBs but the reconstitution failed, we'll try
5553 * try to recover minimal use by getting the basic PF VSI working.
5554 */
5555 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5556 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5557 /* find the one VEB connected to the MAC, and find orphans */
5558 for (v = 0; v < I40E_MAX_VEB; v++) {
5559 if (!pf->veb[v])
5560 continue;
5561
5562 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5563 pf->veb[v]->uplink_seid == 0) {
5564 ret = i40e_reconstitute_veb(pf->veb[v]);
5565
5566 if (!ret)
5567 continue;
5568
5569 /* If Main VEB failed, we're in deep doodoo,
5570 * so give up rebuilding the switch and set up
5571 * for minimal rebuild of PF VSI.
5572 * If orphan failed, we'll report the error
5573 * but try to keep going.
5574 */
5575 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5576 dev_info(&pf->pdev->dev,
5577 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5578 ret);
5579 pf->vsi[pf->lan_vsi]->uplink_seid
5580 = pf->mac_seid;
5581 break;
5582 } else if (pf->veb[v]->uplink_seid == 0) {
5583 dev_info(&pf->pdev->dev,
5584 "rebuild of orphan VEB failed: %d\n",
5585 ret);
5586 }
5587 }
5588 }
5589 }
5590
5591 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5592 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5593 /* no VEB, so rebuild only the Main VSI */
5594 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5595 if (ret) {
5596 dev_info(&pf->pdev->dev,
5597 "rebuild of Main VSI failed: %d\n", ret);
5598 goto end_core_reset;
5599 }
5600 }
5601
5602 /* reinit the misc interrupt */
5603 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5604 ret = i40e_setup_misc_vector(pf);
5605
5606 /* restart the VSIs that were rebuilt and running before the reset */
5607 i40e_pf_unquiesce_all_vsi(pf);
5608
69f64b2b
MW		 5609 if (pf->num_alloc_vfs) {
5610 for (v = 0; v < pf->num_alloc_vfs; v++)
5611 i40e_reset_vf(&pf->vf[v], true);
5612 }
5613
41c445ff 5614 /* tell the firmware that we're starting */
44033fac 5615 i40e_send_version(pf);
41c445ff 5616
69bfb110 5617 dev_info(&pf->pdev->dev, "reset complete\n");
41c445ff
JB		 5618
5619end_core_reset:
5620 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5621}
5622
f650a38b
ASJ		 5623/**
5624 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5625 * @pf: board private structure
5626 *
5627 * Close up the VFs and other things in prep for a Core Reset,
5628 * then get ready to rebuild the world.
5629 **/
5630static void i40e_handle_reset_warning(struct i40e_pf *pf)
5631{
5632 i40e_status ret;
5633
5634 ret = i40e_prep_for_reset(pf);
5635 if (!ret)
bc7d338f 5636 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5637}
5638
41c445ff
JB		 5639/**
5640 * i40e_handle_mdd_event
5641 * @pf: pointer to the pf structure
5642 *
5643 * Called from the MDD irq handler to identify possibly malicious vfs
5644 **/
5645static void i40e_handle_mdd_event(struct i40e_pf *pf)
5646{
5647 struct i40e_hw *hw = &pf->hw;
5648 bool mdd_detected = false;
5649 struct i40e_vf *vf;
5650 u32 reg;
5651 int i;
5652
5653 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5654 return;
5655
5656 /* find what triggered the MDD event */
5657 reg = rd32(hw, I40E_GL_MDET_TX);
5658 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5659 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5660 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5661 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5662 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5663 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5664 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5665 dev_info(&pf->pdev->dev,
f29eaa3d 5666 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5667 event, queue, func);
5668 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5669 mdd_detected = true;
5670 }
5671 reg = rd32(hw, I40E_GL_MDET_RX);
5672 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5673 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5674 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5675 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5676 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5677 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5678 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5679 dev_info(&pf->pdev->dev,
f29eaa3d 5680 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5681 event, queue, func);
5682 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5683 mdd_detected = true;
5684 }
5685
5686 /* see if one of the VFs needs its hand slapped */
5687 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5688 vf = &(pf->vf[i]);
5689 reg = rd32(hw, I40E_VP_MDET_TX(i));
5690 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5691 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5692 vf->num_mdd_events++;
5693 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5694 }
5695
5696 reg = rd32(hw, I40E_VP_MDET_RX(i));
5697 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5698 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5699 vf->num_mdd_events++;
5700 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5701 }
5702
5703 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5704 dev_info(&pf->pdev->dev,
5705 "Too many MDD events on VF %d, disabled\n", i);
5706 dev_info(&pf->pdev->dev,
5707 "Use PF Control I/F to re-enable the VF\n");
5708 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5709 }
5710 }
5711
5712 /* re-enable mdd interrupt cause */
5713 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5714 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5715 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5716 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5717 i40e_flush(hw);
5718}
5719
a1c9a9d9
JK		 5720#ifdef CONFIG_I40E_VXLAN
5721/**
5722 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5723 * @pf: board private structure
5724 **/
5725static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5726{
a1c9a9d9
JK		 5727 struct i40e_hw *hw = &pf->hw;
5728 i40e_status ret;
5729 u8 filter_index;
5730 __be16 port;
5731 int i;
5732
5733 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5734 return;
5735
5736 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5737
5738 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5739 if (pf->pending_vxlan_bitmap & (1 << i)) {
5740 pf->pending_vxlan_bitmap &= ~(1 << i);
5741 port = pf->vxlan_ports[i];
5742 ret = port ?
5743 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5744 I40E_AQC_TUNNEL_TYPE_VXLAN,
5745 &filter_index, NULL)
5746 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5747
5748 if (ret) {
5749 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5750 port ? "adding" : "deleting",
5751 ntohs(port), port ? i : i);
5752
5753 pf->vxlan_ports[i] = 0;
5754 } else {
5755 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5756 port ? "Added" : "Deleted",
5757 ntohs(port), port ? i : filter_index);
5758 }
5759 }
5760 }
5761}
5762
5763#endif
41c445ff
JB		 5764/**
5765 * i40e_service_task - Run the driver's async subtasks
5766 * @work: pointer to work_struct containing our data
5767 **/
5768static void i40e_service_task(struct work_struct *work)
5769{
5770 struct i40e_pf *pf = container_of(work,
5771 struct i40e_pf,
5772 service_task);
5773 unsigned long start_time = jiffies;
5774
5775 i40e_reset_subtask(pf);
5776 i40e_handle_mdd_event(pf);
5777 i40e_vc_process_vflr_event(pf);
5778 i40e_watchdog_subtask(pf);
5779 i40e_fdir_reinit_subtask(pf);
5780 i40e_check_hang_subtask(pf);
5781 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5782#ifdef CONFIG_I40E_VXLAN
5783 i40e_sync_vxlan_filters_subtask(pf);
5784#endif
41c445ff
JB		 5785 i40e_clean_adminq_subtask(pf);
5786
5787 i40e_service_event_complete(pf);
5788
5789 /* If the tasks have taken longer than one timer cycle or there
5790 * is more work to be done, reschedule the service task now
5791 * rather than wait for the timer to tick again.
5792 */
5793 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5794 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5795 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5796 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5797 i40e_service_event_schedule(pf);
5798}
5799
5800/**
5801 * i40e_service_timer - timer callback
5802 * @data: pointer to PF struct
5803 **/
5804static void i40e_service_timer(unsigned long data)
5805{
5806 struct i40e_pf *pf = (struct i40e_pf *)data;
5807
5808 mod_timer(&pf->service_timer,
5809 round_jiffies(jiffies + pf->service_timer_period));
5810 i40e_service_event_schedule(pf);
5811}
5812
5813/**
5814 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5815 * @vsi: the VSI being configured
5816 **/
5817static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5818{
5819 struct i40e_pf *pf = vsi->back;
5820
5821 switch (vsi->type) {
5822 case I40E_VSI_MAIN:
5823 vsi->alloc_queue_pairs = pf->num_lan_qps;
5824 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5825 I40E_REQ_DESCRIPTOR_MULTIPLE);
5826 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5827 vsi->num_q_vectors = pf->num_lan_msix;
5828 else
5829 vsi->num_q_vectors = 1;
5830
5831 break;
5832
5833 case I40E_VSI_FDIR:
5834 vsi->alloc_queue_pairs = 1;
5835 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5836 I40E_REQ_DESCRIPTOR_MULTIPLE);
5837 vsi->num_q_vectors = 1;
5838 break;
5839
5840 case I40E_VSI_VMDQ2:
5841 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5842 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5843 I40E_REQ_DESCRIPTOR_MULTIPLE);
5844 vsi->num_q_vectors = pf->num_vmdq_msix;
5845 break;
5846
5847 case I40E_VSI_SRIOV:
5848 vsi->alloc_queue_pairs = pf->num_vf_qps;
5849 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5850 I40E_REQ_DESCRIPTOR_MULTIPLE);
5851 break;
5852
5853 default:
5854 WARN_ON(1);
5855 return -ENODATA;
5856 }
5857
5858 return 0;
5859}
5860
f650a38b
ASJ		 5861/**
5862 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5863 * @type: VSI pointer
bc7d338f 5864 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5865 *
5866 * On error: returns error code (negative)
5867 * On success: returns 0
5868 **/
bc7d338f 5869static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5870{
5871 int size;
5872 int ret = 0;
5873
ac6c5e3d 5874 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5875 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5876 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5877 if (!vsi->tx_rings)
5878 return -ENOMEM;
f650a38b
ASJ		 5879 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5880
bc7d338f
ASJ		 5881 if (alloc_qvectors) {
5882 /* allocate memory for q_vector pointers */
5883 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5884 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5885 if (!vsi->q_vectors) {
5886 ret = -ENOMEM;
5887 goto err_vectors;
5888 }
f650a38b
ASJ		 5889 }
5890 return ret;
5891
5892err_vectors:
5893 kfree(vsi->tx_rings);
5894 return ret;
5895}
5896
41c445ff
JB		 5897/**
5898 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5899 * @pf: board private structure
5900 * @type: type of VSI
5901 *
5902 * On error: returns error code (negative)
5903 * On success: returns vsi index in PF (positive)
5904 **/
5905static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5906{
5907 int ret = -ENODEV;
5908 struct i40e_vsi *vsi;
5909 int vsi_idx;
5910 int i;
5911
5912 /* Need to protect the allocation of the VSIs at the PF level */
5913 mutex_lock(&pf->switch_mutex);
5914
5915 /* VSI list may be fragmented if VSI creation/destruction has
5916 * been happening. We can afford to do a quick scan to look
5917 * for any free VSIs in the list.
5918 *
5919 * find next empty vsi slot, looping back around if necessary
5920 */
5921 i = pf->next_vsi;
5922 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5923 i++;
5924 if (i >= pf->hw.func_caps.num_vsis) {
5925 i = 0;
5926 while (i < pf->next_vsi && pf->vsi[i])
5927 i++;
5928 }
5929
5930 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5931 vsi_idx = i; /* Found one! */
5932 } else {
5933 ret = -ENODEV;
493fb300 5934 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5935 }
5936 pf->next_vsi = ++i;
5937
5938 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5939 if (!vsi) {
5940 ret = -ENOMEM;
493fb300 5941 goto unlock_pf;
41c445ff
JB		 5942 }
5943 vsi->type = type;
5944 vsi->back = pf;
5945 set_bit(__I40E_DOWN, &vsi->state);
5946 vsi->flags = 0;
5947 vsi->idx = vsi_idx;
5948 vsi->rx_itr_setting = pf->rx_itr_default;
5949 vsi->tx_itr_setting = pf->tx_itr_default;
5950 vsi->netdev_registered = false;
5951 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5952 INIT_LIST_HEAD(&vsi->mac_filter_list);
5953
9f65e15b
AD		 5954 ret = i40e_set_num_rings_in_vsi(vsi);
5955 if (ret)
5956 goto err_rings;
5957
bc7d338f 5958 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5959 if (ret)
9f65e15b 5960 goto err_rings;
493fb300 5961
41c445ff
JB		 5962 /* Setup default MSIX irq handler for VSI */
5963 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5964
5965 pf->vsi[vsi_idx] = vsi;
5966 ret = vsi_idx;
493fb300
AD		 5967 goto unlock_pf;
5968
9f65e15b 5969err_rings:
493fb300
AD		 5970 pf->next_vsi = i - 1;
5971 kfree(vsi);
5972unlock_pf:
41c445ff
JB		 5973 mutex_unlock(&pf->switch_mutex);
5974 return ret;
5975}
5976
f650a38b
ASJ		 5977/**
5978 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5979 * @type: VSI pointer
bc7d338f 5980 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5981 *
5982 * On error: returns error code (negative)
5983 * On success: returns 0
5984 **/
bc7d338f 5985static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5986{
5987 /* free the ring and vector containers */
bc7d338f
ASJ		 5988 if (free_qvectors) {
5989 kfree(vsi->q_vectors);
5990 vsi->q_vectors = NULL;
5991 }
f650a38b
ASJ		 5992 kfree(vsi->tx_rings);
5993 vsi->tx_rings = NULL;
5994 vsi->rx_rings = NULL;
5995}
5996
41c445ff
JB		 5997/**
5998 * i40e_vsi_clear - Deallocate the VSI provided
5999 * @vsi: the VSI being un-configured
6000 **/
6001static int i40e_vsi_clear(struct i40e_vsi *vsi)
6002{
6003 struct i40e_pf *pf;
6004
6005 if (!vsi)
6006 return 0;
6007
6008 if (!vsi->back)
6009 goto free_vsi;
6010 pf = vsi->back;
6011
6012 mutex_lock(&pf->switch_mutex);
6013 if (!pf->vsi[vsi->idx]) {
6014 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6015 vsi->idx, vsi->idx, vsi, vsi->type);
6016 goto unlock_vsi;
6017 }
6018
6019 if (pf->vsi[vsi->idx] != vsi) {
6020 dev_err(&pf->pdev->dev,
6021 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6022 pf->vsi[vsi->idx]->idx,
6023 pf->vsi[vsi->idx],
6024 pf->vsi[vsi->idx]->type,
6025 vsi->idx, vsi, vsi->type);
6026 goto unlock_vsi;
6027 }
6028
6029 /* updates the pf for this cleared vsi */
6030 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6031 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6032
bc7d338f 6033 i40e_vsi_free_arrays(vsi, true);
493fb300 6034
41c445ff
JB		 6035 pf->vsi[vsi->idx] = NULL;
6036 if (vsi->idx < pf->next_vsi)
6037 pf->next_vsi = vsi->idx;
6038
6039unlock_vsi:
6040 mutex_unlock(&pf->switch_mutex);
6041free_vsi:
6042 kfree(vsi);
6043
6044 return 0;
6045}
6046
9f65e15b
AD		 6047/**
6048 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6049 * @vsi: the VSI being cleaned
6050 **/
be1d5eea 6051static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6052{
6053 int i;
6054
8e9dca53 6055 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6056 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6057 kfree_rcu(vsi->tx_rings[i], rcu);
6058 vsi->tx_rings[i] = NULL;
6059 vsi->rx_rings[i] = NULL;
6060 }
be1d5eea 6061 }
9f65e15b
AD		 6062}
6063
41c445ff
JB		 6064/**
6065 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6066 * @vsi: the VSI being configured
6067 **/
6068static int i40e_alloc_rings(struct i40e_vsi *vsi)
6069{
e7046ee1 6070 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6071 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6072 int i;
6073
41c445ff 6074 /* Set basic values in the rings to be used later during open() */
d7397644 6075 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6076 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6077 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6078 if (!tx_ring)
6079 goto err_out;
41c445ff
JB		 6080
6081 tx_ring->queue_index = i;
6082 tx_ring->reg_idx = vsi->base_queue + i;
6083 tx_ring->ring_active = false;
6084 tx_ring->vsi = vsi;
6085 tx_ring->netdev = vsi->netdev;
6086 tx_ring->dev = &pf->pdev->dev;
6087 tx_ring->count = vsi->num_desc;
6088 tx_ring->size = 0;
6089 tx_ring->dcb_tc = 0;
9f65e15b 6090 vsi->tx_rings[i] = tx_ring;
41c445ff 6091
9f65e15b 6092 rx_ring = &tx_ring[1];
41c445ff
JB		 6093 rx_ring->queue_index = i;
6094 rx_ring->reg_idx = vsi->base_queue + i;
6095 rx_ring->ring_active = false;
6096 rx_ring->vsi = vsi;
6097 rx_ring->netdev = vsi->netdev;
6098 rx_ring->dev = &pf->pdev->dev;
6099 rx_ring->count = vsi->num_desc;
6100 rx_ring->size = 0;
6101 rx_ring->dcb_tc = 0;
6102 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6103 set_ring_16byte_desc_enabled(rx_ring);
6104 else
6105 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6106 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6107 }
6108
6109 return 0;
9f65e15b
AD		 6110
6111err_out:
6112 i40e_vsi_clear_rings(vsi);
6113 return -ENOMEM;
41c445ff
JB		 6114}
6115
6116/**
6117 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6118 * @pf: board private structure
6119 * @vectors: the number of MSI-X vectors to request
6120 *
6121 * Returns the number of vectors reserved, or error
6122 **/
6123static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6124{
7b37f376
AG		 6125 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6126 I40E_MIN_MSIX, vectors);
6127 if (vectors < 0) {
41c445ff 6128 dev_info(&pf->pdev->dev,
7b37f376 6129 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6130 vectors = 0;
6131 }
6132
7b37f376
AG		 6133 pf->num_msix_entries = vectors;
6134
41c445ff
JB		 6135 return vectors;
6136}
6137
6138/**
6139 * i40e_init_msix - Setup the MSIX capability
6140 * @pf: board private structure
6141 *
6142 * Work with the OS to set up the MSIX vectors needed.
6143 *
6144 * Returns 0 on success, negative on failure
6145 **/
6146static int i40e_init_msix(struct i40e_pf *pf)
6147{
6148 i40e_status err = 0;
6149 struct i40e_hw *hw = &pf->hw;
6150 int v_budget, i;
6151 int vec;
6152
6153 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6154 return -ENODEV;
6155
6156 /* The number of vectors we'll request will be comprised of:
6157 * - Add 1 for "other" cause for Admin Queue events, etc.
6158 * - The number of LAN queue pairs
f8ff1464
ASJ		 6159 * - Queues being used for RSS.
6160 * We don't need as many as max_rss_size vectors.
6161 * use rss_size instead in the calculation since that
6162 * is governed by number of cpus in the system.
6163 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6164 * - The number of VMDq pairs
6165 * Once we count this up, try the request.
6166 *
6167 * If we can't get what we want, we'll simplify to nearly nothing
6168 * and try again. If that still fails, we punt.
6169 */
f8ff1464 6170 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6171 pf->num_vmdq_msix = pf->num_vmdq_qps;
6172 v_budget = 1 + pf->num_lan_msix;
6173 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6174 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6175 v_budget++;
6176
6177 /* Scale down if necessary, and the rings will share vectors */
6178 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6179
6180 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6181 GFP_KERNEL);
6182 if (!pf->msix_entries)
6183 return -ENOMEM;
6184
6185 for (i = 0; i < v_budget; i++)
6186 pf->msix_entries[i].entry = i;
6187 vec = i40e_reserve_msix_vectors(pf, v_budget);
6188 if (vec < I40E_MIN_MSIX) {
6189 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6190 kfree(pf->msix_entries);
6191 pf->msix_entries = NULL;
6192 return -ENODEV;
6193
6194 } else if (vec == I40E_MIN_MSIX) {
6195 /* Adjust for minimal MSIX use */
77fa28be 6196 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6197 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6198 pf->num_vmdq_vsis = 0;
6199 pf->num_vmdq_qps = 0;
6200 pf->num_vmdq_msix = 0;
6201 pf->num_lan_qps = 1;
6202 pf->num_lan_msix = 1;
6203
6204 } else if (vec != v_budget) {
6205 /* Scale vector usage down */
6206 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6207 vec--; /* reserve the misc vector */
6208
6209 /* partition out the remaining vectors */
6210 switch (vec) {
6211 case 2:
6212 pf->num_vmdq_vsis = 1;
6213 pf->num_lan_msix = 1;
6214 break;
6215 case 3:
6216 pf->num_vmdq_vsis = 1;
6217 pf->num_lan_msix = 2;
6218 break;
6219 default:
6220 pf->num_lan_msix = min_t(int, (vec / 2),
6221 pf->num_lan_qps);
6222 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6223 I40E_DEFAULT_NUM_VMDQ_VSI);
6224 break;
6225 }
6226 }
6227
6228 return err;
6229}
6230
493fb300 6231/**
90e04070 6232 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6233 * @vsi: the VSI being configured
6234 * @v_idx: index of the vector in the vsi struct
6235 *
6236 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6237 **/
90e04070 6238static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6239{
6240 struct i40e_q_vector *q_vector;
6241
6242 /* allocate q_vector */
6243 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6244 if (!q_vector)
6245 return -ENOMEM;
6246
6247 q_vector->vsi = vsi;
6248 q_vector->v_idx = v_idx;
6249 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6250 if (vsi->netdev)
6251 netif_napi_add(vsi->netdev, &q_vector->napi,
6252 i40e_napi_poll, vsi->work_limit);
6253
cd0b6fa6
AD		 6254 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6255 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6256
493fb300
AD		 6257 /* tie q_vector and vsi together */
6258 vsi->q_vectors[v_idx] = q_vector;
6259
6260 return 0;
6261}
6262
41c445ff 6263/**
90e04070 6264 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6265 * @vsi: the VSI being configured
6266 *
6267 * We allocate one q_vector per queue interrupt. If allocation fails we
6268 * return -ENOMEM.
6269 **/
90e04070 6270static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6271{
6272 struct i40e_pf *pf = vsi->back;
6273 int v_idx, num_q_vectors;
493fb300 6274 int err;
41c445ff
JB		 6275
6276 /* if not MSIX, give the one vector only to the LAN VSI */
6277 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6278 num_q_vectors = vsi->num_q_vectors;
6279 else if (vsi == pf->vsi[pf->lan_vsi])
6280 num_q_vectors = 1;
6281 else
6282 return -EINVAL;
6283
41c445ff 6284 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6285 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6286 if (err)
6287 goto err_out;
41c445ff
JB		 6288 }
6289
6290 return 0;
493fb300
AD		 6291
6292err_out:
6293 while (v_idx--)
6294 i40e_free_q_vector(vsi, v_idx);
6295
6296 return err;
41c445ff
JB		 6297}
6298
6299/**
6300 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6301 * @pf: board private structure to initialize
6302 **/
6303static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6304{
6305 int err = 0;
6306
6307 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6308 err = i40e_init_msix(pf);
6309 if (err) {
60ea5f83
JB		 6310 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6311 I40E_FLAG_RSS_ENABLED |
6312 I40E_FLAG_DCB_ENABLED |
6313 I40E_FLAG_SRIOV_ENABLED |
6314 I40E_FLAG_FD_SB_ENABLED |
6315 I40E_FLAG_FD_ATR_ENABLED |
6316 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6317
6318 /* rework the queue expectations without MSIX */
6319 i40e_determine_queue_usage(pf);
6320 }
6321 }
6322
6323 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6324 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6325 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6326 err = pci_enable_msi(pf->pdev);
6327 if (err) {
958a3e3b 6328 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6329 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6330 }
6331 }
6332
958a3e3b 6333 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6334 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6335
41c445ff
JB		 6336 /* track first vector for misc interrupts */
6337 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6338}
6339
6340/**
6341 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6342 * @pf: board private structure
6343 *
6344 * This sets up the handler for MSIX 0, which is used to manage the
6345 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6346 * when in MSI or Legacy interrupt mode.
6347 **/
6348static int i40e_setup_misc_vector(struct i40e_pf *pf)
6349{
6350 struct i40e_hw *hw = &pf->hw;
6351 int err = 0;
6352
6353 /* Only request the irq if this is the first time through, and
6354 * not when we're rebuilding after a Reset
6355 */
6356 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6357 err = request_irq(pf->msix_entries[0].vector,
6358 i40e_intr, 0, pf->misc_int_name, pf);
6359 if (err) {
6360 dev_info(&pf->pdev->dev,
77fa28be
CS		 6361 "request_irq for %s failed: %d\n",
6362 pf->misc_int_name, err);
41c445ff
JB		 6363 return -EFAULT;
6364 }
6365 }
6366
6367 i40e_enable_misc_int_causes(hw);
6368
6369 /* associate no queues to the misc vector */
6370 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6371 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6372
6373 i40e_flush(hw);
6374
6375 i40e_irq_dynamic_enable_icr0(pf);
6376
6377 return err;
6378}
6379
6380/**
6381 * i40e_config_rss - Prepare for RSS if used
6382 * @pf: board private structure
6383 **/
6384static int i40e_config_rss(struct i40e_pf *pf)
6385{
41c445ff
JB		 6386 /* Set of random keys generated using kernel random number generator */
6387 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6388 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6389 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6390 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6391 struct i40e_hw *hw = &pf->hw;
6392 u32 lut = 0;
6393 int i, j;
6394 u64 hena;
41c445ff
JB		 6395
6396 /* Fill out hash function seed */
6397 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6398 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6399
6400 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6401 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6402 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6403 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6404 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6405 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6406
6407 /* Populate the LUT with max no. of queues in round robin fashion */
6408 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6409
6410 /* The assumption is that lan qp count will be the highest
6411 * qp count for any PF VSI that needs RSS.
6412 * If multiple VSIs need RSS support, all the qp counts
6413 * for those VSIs should be a power of 2 for RSS to work.
6414 * If LAN VSI is the only consumer for RSS then this requirement
6415 * is not necessary.
6416 */
6417 if (j == pf->rss_size)
6418 j = 0;
6419 /* lut = 4-byte sliding window of 4 lut entries */
6420 lut = (lut << 8) | (j &
6421 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6422 /* On i = 3, we have 4 entries in lut; write to the register */
6423 if ((i & 3) == 3)
6424 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6425 }
6426 i40e_flush(hw);
6427
6428 return 0;
6429}
6430
f8ff1464
ASJ		 6431/**
6432 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6433 * @pf: board private structure
6434 * @queue_count: the requested queue count for rss.
6435 *
6436 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6437 * count which may be different from the requested queue count.
6438 **/
6439int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6440{
6441 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6442 return 0;
6443
6444 queue_count = min_t(int, queue_count, pf->rss_size_max);
6445 queue_count = rounddown_pow_of_two(queue_count);
6446
6447 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6448 i40e_prep_for_reset(pf);
6449
f8ff1464
ASJ		 6450 pf->rss_size = queue_count;
6451
6452 i40e_reset_and_rebuild(pf, true);
6453 i40e_config_rss(pf);
6454 }
6455 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6456 return pf->rss_size;
6457}
6458
41c445ff
JB		 6459/**
6460 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6461 * @pf: board private structure to initialize
6462 *
6463 * i40e_sw_init initializes the Adapter private data structure.
6464 * Fields are initialized based on PCI device information and
6465 * OS network device settings (MTU size).
6466 **/
6467static int i40e_sw_init(struct i40e_pf *pf)
6468{
6469 int err = 0;
6470 int size;
6471
6472 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6473 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6474 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6475 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6476 if (I40E_DEBUG_USER & debug)
6477 pf->hw.debug_mask = debug;
6478 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6479 I40E_DEFAULT_MSG_ENABLE);
6480 }
6481
6482 /* Set default capability flags */
6483 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6484 I40E_FLAG_MSI_ENABLED |
6485 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6486 I40E_FLAG_RX_1BUF_ENABLED;
6487
ca99eb99
MW		 6488 /* Set default ITR */
6489 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6490 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6491
7134f9ce
JB		 6492 /* Depending on PF configurations, it is possible that the RSS
6493 * maximum might end up larger than the available queues
6494 */
41c445ff 6495 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6496 pf->rss_size_max = min_t(int, pf->rss_size_max,
6497 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6498 if (pf->hw.func_caps.rss) {
6499 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6500 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6501 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6502 } else {
6503 pf->rss_size = 1;
6504 }
6505
2050bc65
CS		 6506 /* MFP mode enabled */
6507 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6508 pf->flags |= I40E_FLAG_MFP_ENABLED;
6509 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6510 }
6511
cbf61325
ASJ		 6512 /* FW/NVM is not yet fixed in this regard */
6513 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6514 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6515 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6516 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6517 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6518 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6519 } else {
6520 dev_info(&pf->pdev->dev,
0b67584f 6521 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6522 }
cbf61325
ASJ		 6523 pf->fdir_pf_filter_count =
6524 pf->hw.func_caps.fd_filters_guaranteed;
6525 pf->hw.fdir_shared_filter_count =
6526 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6527 }
6528
6529 if (pf->hw.func_caps.vmdq) {
6530 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6531 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6532 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6533 }
6534
41c445ff
JB		 6535#ifdef CONFIG_PCI_IOV
6536 if (pf->hw.func_caps.num_vfs) {
6537 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6538 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6539 pf->num_req_vfs = min_t(int,
6540 pf->hw.func_caps.num_vfs,
6541 I40E_MAX_VF_COUNT);
6542 }
6543#endif /* CONFIG_PCI_IOV */
6544 pf->eeprom_version = 0xDEAD;
6545 pf->lan_veb = I40E_NO_VEB;
6546 pf->lan_vsi = I40E_NO_VSI;
6547
6548 /* set up queue assignment tracking */
6549 size = sizeof(struct i40e_lump_tracking)
6550 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6551 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6552 if (!pf->qp_pile) {
6553 err = -ENOMEM;
6554 goto sw_init_done;
6555 }
6556 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6557 pf->qp_pile->search_hint = 0;
6558
6559 /* set up vector assignment tracking */
6560 size = sizeof(struct i40e_lump_tracking)
6561 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6562 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6563 if (!pf->irq_pile) {
6564 kfree(pf->qp_pile);
6565 err = -ENOMEM;
6566 goto sw_init_done;
6567 }
6568 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6569 pf->irq_pile->search_hint = 0;
6570
6571 mutex_init(&pf->switch_mutex);
6572
6573sw_init_done:
6574 return err;
6575}
6576
7c3c288b
ASJ		 6577/**
6578 * i40e_set_ntuple - set the ntuple feature flag and take action
6579 * @pf: board private structure to initialize
6580 * @features: the feature set that the stack is suggesting
6581 *
6582 * returns a bool to indicate if reset needs to happen
6583 **/
6584bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6585{
6586 bool need_reset = false;
6587
6588 /* Check if Flow Director n-tuple support was enabled or disabled. If
6589 * the state changed, we need to reset.
6590 */
6591 if (features & NETIF_F_NTUPLE) {
6592 /* Enable filters and mark for reset */
6593 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6594 need_reset = true;
6595 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6596 } else {
6597 /* turn off filters, mark for reset and clear SW filter list */
6598 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6599 need_reset = true;
6600 i40e_fdir_filter_exit(pf);
6601 }
6602 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6603 /* if ATR was disabled it can be re-enabled. */
6604 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6605 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6606 }
6607 return need_reset;
6608}
6609
41c445ff
JB		 6610/**
6611 * i40e_set_features - set the netdev feature flags
6612 * @netdev: ptr to the netdev being adjusted
6613 * @features: the feature set that the stack is suggesting
6614 **/
6615static int i40e_set_features(struct net_device *netdev,
6616 netdev_features_t features)
6617{
6618 struct i40e_netdev_priv *np = netdev_priv(netdev);
6619 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6620 struct i40e_pf *pf = vsi->back;
6621 bool need_reset;
41c445ff
JB		 6622
6623 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6624 i40e_vlan_stripping_enable(vsi);
6625 else
6626 i40e_vlan_stripping_disable(vsi);
6627
7c3c288b
ASJ		 6628 need_reset = i40e_set_ntuple(pf, features);
6629
6630 if (need_reset)
6631 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6632
41c445ff
JB		 6633 return 0;
6634}
6635
a1c9a9d9
JK		 6636#ifdef CONFIG_I40E_VXLAN
6637/**
6638 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6639 * @pf: board private structure
6640 * @port: The UDP port to look up
6641 *
6642 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6643 **/
6644static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6645{
6646 u8 i;
6647
6648 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6649 if (pf->vxlan_ports[i] == port)
6650 return i;
6651 }
6652
6653 return i;
6654}
6655
6656/**
6657 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6658 * @netdev: This physical port's netdev
6659 * @sa_family: Socket Family that VXLAN is notifying us about
6660 * @port: New UDP port number that VXLAN started listening to
6661 **/
6662static void i40e_add_vxlan_port(struct net_device *netdev,
6663 sa_family_t sa_family, __be16 port)
6664{
6665 struct i40e_netdev_priv *np = netdev_priv(netdev);
6666 struct i40e_vsi *vsi = np->vsi;
6667 struct i40e_pf *pf = vsi->back;
6668 u8 next_idx;
6669 u8 idx;
6670
6671 if (sa_family == AF_INET6)
6672 return;
6673
6674 idx = i40e_get_vxlan_port_idx(pf, port);
6675
6676 /* Check if port already exists */
6677 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6678 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6679 return;
6680 }
6681
6682 /* Now check if there is space to add the new port */
6683 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6684
6685 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6686 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6687 ntohs(port));
6688 return;
6689 }
6690
6691 /* New port: add it and mark its index in the bitmap */
6692 pf->vxlan_ports[next_idx] = port;
6693 pf->pending_vxlan_bitmap |= (1 << next_idx);
6694
6695 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6696}
6697
6698/**
6699 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6700 * @netdev: This physical port's netdev
6701 * @sa_family: Socket Family that VXLAN is notifying us about
6702 * @port: UDP port number that VXLAN stopped listening to
6703 **/
6704static void i40e_del_vxlan_port(struct net_device *netdev,
6705 sa_family_t sa_family, __be16 port)
6706{
6707 struct i40e_netdev_priv *np = netdev_priv(netdev);
6708 struct i40e_vsi *vsi = np->vsi;
6709 struct i40e_pf *pf = vsi->back;
6710 u8 idx;
6711
6712 if (sa_family == AF_INET6)
6713 return;
6714
6715 idx = i40e_get_vxlan_port_idx(pf, port);
6716
6717 /* Check if port already exists */
6718 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6719 /* if port exists, set it to 0 (mark for deletion)
6720 * and make it pending
6721 */
6722 pf->vxlan_ports[idx] = 0;
6723
6724 pf->pending_vxlan_bitmap |= (1 << idx);
6725
6726 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6727 } else {
6728 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6729 ntohs(port));
6730 }
6731}
6732
6733#endif
4ba0dea5
GR		 6734#ifdef HAVE_FDB_OPS
6735#ifdef USE_CONST_DEV_UC_CHAR
6736static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6737 struct net_device *dev,
6738 const unsigned char *addr,
6739 u16 flags)
6740#else
6741static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6742 struct net_device *dev,
6743 unsigned char *addr,
6744 u16 flags)
6745#endif
6746{
6747 struct i40e_netdev_priv *np = netdev_priv(dev);
6748 struct i40e_pf *pf = np->vsi->back;
6749 int err = 0;
6750
6751 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6752 return -EOPNOTSUPP;
6753
6754 /* Hardware does not support aging addresses so if a
6755 * ndm_state is given only allow permanent addresses
6756 */
6757 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6758 netdev_info(dev, "FDB only supports static addresses\n");
6759 return -EINVAL;
6760 }
6761
6762 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6763 err = dev_uc_add_excl(dev, addr);
6764 else if (is_multicast_ether_addr(addr))
6765 err = dev_mc_add_excl(dev, addr);
6766 else
6767 err = -EINVAL;
6768
6769 /* Only return duplicate errors if NLM_F_EXCL is set */
6770 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6771 err = 0;
6772
6773 return err;
6774}
6775
6776#ifndef USE_DEFAULT_FDB_DEL_DUMP
6777#ifdef USE_CONST_DEV_UC_CHAR
6778static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6779 struct net_device *dev,
6780 const unsigned char *addr)
6781#else
6782static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6783 struct net_device *dev,
6784 unsigned char *addr)
6785#endif
6786{
6787 struct i40e_netdev_priv *np = netdev_priv(dev);
6788 struct i40e_pf *pf = np->vsi->back;
6789 int err = -EOPNOTSUPP;
6790
6791 if (ndm->ndm_state & NUD_PERMANENT) {
6792 netdev_info(dev, "FDB only supports static addresses\n");
6793 return -EINVAL;
6794 }
6795
6796 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6797 if (is_unicast_ether_addr(addr))
6798 err = dev_uc_del(dev, addr);
6799 else if (is_multicast_ether_addr(addr))
6800 err = dev_mc_del(dev, addr);
6801 else
6802 err = -EINVAL;
6803 }
6804
6805 return err;
6806}
6807
6808static int i40e_ndo_fdb_dump(struct sk_buff *skb,
6809 struct netlink_callback *cb,
6810 struct net_device *dev,
6811 int idx)
6812{
6813 struct i40e_netdev_priv *np = netdev_priv(dev);
6814 struct i40e_pf *pf = np->vsi->back;
6815
6816 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
6817 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6818
6819 return idx;
6820}
6821
6822#endif /* USE_DEFAULT_FDB_DEL_DUMP */
6823#endif /* HAVE_FDB_OPS */
41c445ff
JB		 6824static const struct net_device_ops i40e_netdev_ops = {
6825 .ndo_open = i40e_open,
6826 .ndo_stop = i40e_close,
6827 .ndo_start_xmit = i40e_lan_xmit_frame,
6828 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6829 .ndo_set_rx_mode = i40e_set_rx_mode,
6830 .ndo_validate_addr = eth_validate_addr,
6831 .ndo_set_mac_address = i40e_set_mac,
6832 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6833 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6834 .ndo_tx_timeout = i40e_tx_timeout,
6835 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6836 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6837#ifdef CONFIG_NET_POLL_CONTROLLER
6838 .ndo_poll_controller = i40e_netpoll,
6839#endif
6840 .ndo_setup_tc = i40e_setup_tc,
6841 .ndo_set_features = i40e_set_features,
6842 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6843 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 6844 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 6845 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6846 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6847#ifdef CONFIG_I40E_VXLAN
6848 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6849 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6850#endif
4ba0dea5
GR		 6851#ifdef HAVE_FDB_OPS
6852 .ndo_fdb_add = i40e_ndo_fdb_add,
6853#ifndef USE_DEFAULT_FDB_DEL_DUMP
6854 .ndo_fdb_del = i40e_ndo_fdb_del,
6855 .ndo_fdb_dump = i40e_ndo_fdb_dump,
6856#endif
6857#endif
41c445ff
JB		 6858};
6859
6860/**
6861 * i40e_config_netdev - Setup the netdev flags
6862 * @vsi: the VSI being configured
6863 *
6864 * Returns 0 on success, negative value on failure
6865 **/
6866static int i40e_config_netdev(struct i40e_vsi *vsi)
6867{
1a10370a 6868 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6869 struct i40e_pf *pf = vsi->back;
6870 struct i40e_hw *hw = &pf->hw;
6871 struct i40e_netdev_priv *np;
6872 struct net_device *netdev;
6873 u8 mac_addr[ETH_ALEN];
6874 int etherdev_size;
6875
6876 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6877 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6878 if (!netdev)
6879 return -ENOMEM;
6880
6881 vsi->netdev = netdev;
6882 np = netdev_priv(netdev);
6883 np->vsi = vsi;
6884
d70e941b 6885 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6886 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6887 NETIF_F_TSO;
41c445ff
JB		 6888
6889 netdev->features = NETIF_F_SG |
6890 NETIF_F_IP_CSUM |
6891 NETIF_F_SCTP_CSUM |
6892 NETIF_F_HIGHDMA |
6893 NETIF_F_GSO_UDP_TUNNEL |
6894 NETIF_F_HW_VLAN_CTAG_TX |
6895 NETIF_F_HW_VLAN_CTAG_RX |
6896 NETIF_F_HW_VLAN_CTAG_FILTER |
6897 NETIF_F_IPV6_CSUM |
6898 NETIF_F_TSO |
059dab69 6899 NETIF_F_TSO_ECN |
41c445ff
JB		 6900 NETIF_F_TSO6 |
6901 NETIF_F_RXCSUM |
6902 NETIF_F_RXHASH |
6903 0;
6904
2e86a0b6
ASJ		 6905 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
6906 netdev->features |= NETIF_F_NTUPLE;
6907
41c445ff
JB		 6908 /* copy netdev features into list of user selectable features */
6909 netdev->hw_features |= netdev->features;
6910
6911 if (vsi->type == I40E_VSI_MAIN) {
6912 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6913 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6914 } else {
6915 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6916 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6917 pf->vsi[pf->lan_vsi]->netdev->name);
6918 random_ether_addr(mac_addr);
6919 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6920 }
1a10370a 6921 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6922
6923 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6924 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6925 /* vlan gets same features (except vlan offload)
6926 * after any tweaks for specific VSI types
6927 */
6928 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6929 NETIF_F_HW_VLAN_CTAG_RX |
6930 NETIF_F_HW_VLAN_CTAG_FILTER);
6931 netdev->priv_flags |= IFF_UNICAST_FLT;
6932 netdev->priv_flags |= IFF_SUPP_NOFCS;
6933 /* Setup netdev TC information */
6934 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6935
6936 netdev->netdev_ops = &i40e_netdev_ops;
6937 netdev->watchdog_timeo = 5 * HZ;
6938 i40e_set_ethtool_ops(netdev);
6939
6940 return 0;
6941}
6942
6943/**
6944 * i40e_vsi_delete - Delete a VSI from the switch
6945 * @vsi: the VSI being removed
6946 *
6947 * Returns 0 on success, negative value on failure
6948 **/
6949static void i40e_vsi_delete(struct i40e_vsi *vsi)
6950{
6951 /* remove default VSI is not allowed */
6952 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6953 return;
6954
41c445ff 6955 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 6956}
6957
6958/**
6959 * i40e_add_vsi - Add a VSI to the switch
6960 * @vsi: the VSI being configured
6961 *
6962 * This initializes a VSI context depending on the VSI type to be added and
6963 * passes it down to the add_vsi aq command.
6964 **/
6965static int i40e_add_vsi(struct i40e_vsi *vsi)
6966{
6967 int ret = -ENODEV;
6968 struct i40e_mac_filter *f, *ftmp;
6969 struct i40e_pf *pf = vsi->back;
6970 struct i40e_hw *hw = &pf->hw;
6971 struct i40e_vsi_context ctxt;
6972 u8 enabled_tc = 0x1; /* TC0 enabled */
6973 int f_count = 0;
6974
6975 memset(&ctxt, 0, sizeof(ctxt));
6976 switch (vsi->type) {
6977 case I40E_VSI_MAIN:
6978 /* The PF's main VSI is already setup as part of the
6979 * device initialization, so we'll not bother with
6980 * the add_vsi call, but we will retrieve the current
6981 * VSI context.
6982 */
6983 ctxt.seid = pf->main_vsi_seid;
6984 ctxt.pf_num = pf->hw.pf_id;
6985 ctxt.vf_num = 0;
6986 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6987 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6988 if (ret) {
6989 dev_info(&pf->pdev->dev,
6990 "couldn't get pf vsi config, err %d, aq_err %d\n",
6991 ret, pf->hw.aq.asq_last_status);
6992 return -ENOENT;
6993 }
6994 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6995 vsi->info.valid_sections = 0;
6996
6997 vsi->seid = ctxt.seid;
6998 vsi->id = ctxt.vsi_number;
6999
7000 enabled_tc = i40e_pf_get_tc_map(pf);
7001
7002 /* MFP mode setup queue map and update VSI */
7003 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7004 memset(&ctxt, 0, sizeof(ctxt));
7005 ctxt.seid = pf->main_vsi_seid;
7006 ctxt.pf_num = pf->hw.pf_id;
7007 ctxt.vf_num = 0;
7008 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7009 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7010 if (ret) {
7011 dev_info(&pf->pdev->dev,
7012 "update vsi failed, aq_err=%d\n",
7013 pf->hw.aq.asq_last_status);
7014 ret = -ENOENT;
7015 goto err;
7016 }
7017 /* update the local VSI info queue map */
7018 i40e_vsi_update_queue_map(vsi, &ctxt);
7019 vsi->info.valid_sections = 0;
7020 } else {
7021 /* Default/Main VSI is only enabled for TC0
7022 * reconfigure it to enable all TCs that are
7023 * available on the port in SFP mode.
7024 */
7025 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7026 if (ret) {
7027 dev_info(&pf->pdev->dev,
7028 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7029 enabled_tc, ret,
7030 pf->hw.aq.asq_last_status);
7031 ret = -ENOENT;
7032 }
7033 }
7034 break;
7035
7036 case I40E_VSI_FDIR:
cbf61325
ASJ		 7037 ctxt.pf_num = hw->pf_id;
7038 ctxt.vf_num = 0;
7039 ctxt.uplink_seid = vsi->uplink_seid;
7040 ctxt.connection_type = 0x1; /* regular data port */
7041 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7042 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7043 break;
7044
7045 case I40E_VSI_VMDQ2:
7046 ctxt.pf_num = hw->pf_id;
7047 ctxt.vf_num = 0;
7048 ctxt.uplink_seid = vsi->uplink_seid;
7049 ctxt.connection_type = 0x1; /* regular data port */
7050 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7051
7052 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7053
7054 /* This VSI is connected to VEB so the switch_id
7055 * should be set to zero by default.
7056 */
7057 ctxt.info.switch_id = 0;
7058 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
7059 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7060
7061 /* Setup the VSI tx/rx queue map for TC0 only for now */
7062 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7063 break;
7064
7065 case I40E_VSI_SRIOV:
7066 ctxt.pf_num = hw->pf_id;
7067 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7068 ctxt.uplink_seid = vsi->uplink_seid;
7069 ctxt.connection_type = 0x1; /* regular data port */
7070 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7071
7072 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7073
7074 /* This VSI is connected to VEB so the switch_id
7075 * should be set to zero by default.
7076 */
7077 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7078
7079 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7080 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
7081 /* Setup the VSI tx/rx queue map for TC0 only for now */
7082 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7083 break;
7084
7085 default:
7086 return -ENODEV;
7087 }
7088
7089 if (vsi->type != I40E_VSI_MAIN) {
7090 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7091 if (ret) {
7092 dev_info(&vsi->back->pdev->dev,
7093 "add vsi failed, aq_err=%d\n",
7094 vsi->back->hw.aq.asq_last_status);
7095 ret = -ENOENT;
7096 goto err;
7097 }
7098 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7099 vsi->info.valid_sections = 0;
7100 vsi->seid = ctxt.seid;
7101 vsi->id = ctxt.vsi_number;
7102 }
7103
7104 /* If macvlan filters already exist, force them to get loaded */
7105 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7106 f->changed = true;
7107 f_count++;
7108 }
7109 if (f_count) {
7110 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7111 pf->flags |= I40E_FLAG_FILTER_SYNC;
7112 }
7113
7114 /* Update VSI BW information */
7115 ret = i40e_vsi_get_bw_info(vsi);
7116 if (ret) {
7117 dev_info(&pf->pdev->dev,
7118 "couldn't get vsi bw info, err %d, aq_err %d\n",
7119 ret, pf->hw.aq.asq_last_status);
7120 /* VSI is already added so not tearing that up */
7121 ret = 0;
7122 }
7123
7124err:
7125 return ret;
7126}
7127
7128/**
7129 * i40e_vsi_release - Delete a VSI and free its resources
7130 * @vsi: the VSI being removed
7131 *
7132 * Returns 0 on success or < 0 on error
7133 **/
7134int i40e_vsi_release(struct i40e_vsi *vsi)
7135{
7136 struct i40e_mac_filter *f, *ftmp;
7137 struct i40e_veb *veb = NULL;
7138 struct i40e_pf *pf;
7139 u16 uplink_seid;
7140 int i, n;
7141
7142 pf = vsi->back;
7143
7144 /* release of a VEB-owner or last VSI is not allowed */
7145 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7146 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7147 vsi->seid, vsi->uplink_seid);
7148 return -ENODEV;
7149 }
7150 if (vsi == pf->vsi[pf->lan_vsi] &&
7151 !test_bit(__I40E_DOWN, &pf->state)) {
7152 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7153 return -ENODEV;
7154 }
7155
7156 uplink_seid = vsi->uplink_seid;
7157 if (vsi->type != I40E_VSI_SRIOV) {
7158 if (vsi->netdev_registered) {
7159 vsi->netdev_registered = false;
7160 if (vsi->netdev) {
7161 /* results in a call to i40e_close() */
7162 unregister_netdev(vsi->netdev);
41c445ff
JB		 7163 }
7164 } else {
90ef8d47 7165 i40e_vsi_close(vsi);
41c445ff
JB		 7166 }
7167 i40e_vsi_disable_irq(vsi);
7168 }
7169
7170 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7171 i40e_del_filter(vsi, f->macaddr, f->vlan,
7172 f->is_vf, f->is_netdev);
7173 i40e_sync_vsi_filters(vsi);
7174
7175 i40e_vsi_delete(vsi);
7176 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7177 if (vsi->netdev) {
7178 free_netdev(vsi->netdev);
7179 vsi->netdev = NULL;
7180 }
41c445ff
JB		 7181 i40e_vsi_clear_rings(vsi);
7182 i40e_vsi_clear(vsi);
7183
7184 /* If this was the last thing on the VEB, except for the
7185 * controlling VSI, remove the VEB, which puts the controlling
7186 * VSI onto the next level down in the switch.
7187 *
7188 * Well, okay, there's one more exception here: don't remove
7189 * the orphan VEBs yet. We'll wait for an explicit remove request
7190 * from up the network stack.
7191 */
7192 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7193 if (pf->vsi[i] &&
7194 pf->vsi[i]->uplink_seid == uplink_seid &&
7195 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7196 n++; /* count the VSIs */
7197 }
7198 }
7199 for (i = 0; i < I40E_MAX_VEB; i++) {
7200 if (!pf->veb[i])
7201 continue;
7202 if (pf->veb[i]->uplink_seid == uplink_seid)
7203 n++; /* count the VEBs */
7204 if (pf->veb[i]->seid == uplink_seid)
7205 veb = pf->veb[i];
7206 }
7207 if (n == 0 && veb && veb->uplink_seid != 0)
7208 i40e_veb_release(veb);
7209
7210 return 0;
7211}
7212
7213/**
7214 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7215 * @vsi: ptr to the VSI
7216 *
7217 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7218 * corresponding SW VSI structure and initializes num_queue_pairs for the
7219 * newly allocated VSI.
7220 *
7221 * Returns 0 on success or negative on failure
7222 **/
7223static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7224{
7225 int ret = -ENOENT;
7226 struct i40e_pf *pf = vsi->back;
7227
493fb300 7228 if (vsi->q_vectors[0]) {
41c445ff
JB		 7229 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7230 vsi->seid);
7231 return -EEXIST;
7232 }
7233
7234 if (vsi->base_vector) {
f29eaa3d 7235 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7236 vsi->seid, vsi->base_vector);
7237 return -EEXIST;
7238 }
7239
90e04070 7240 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7241 if (ret) {
7242 dev_info(&pf->pdev->dev,
7243 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7244 vsi->num_q_vectors, vsi->seid, ret);
7245 vsi->num_q_vectors = 0;
7246 goto vector_setup_out;
7247 }
7248
958a3e3b
SN		 7249 if (vsi->num_q_vectors)
7250 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7251 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7252 if (vsi->base_vector < 0) {
7253 dev_info(&pf->pdev->dev,
f29eaa3d 7254 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7255 vsi->seid, vsi->base_vector);
7256 i40e_vsi_free_q_vectors(vsi);
7257 ret = -ENOENT;
7258 goto vector_setup_out;
7259 }
7260
7261vector_setup_out:
7262 return ret;
7263}
7264
bc7d338f
ASJ		 7265/**
7266 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7267 * @vsi: pointer to the vsi.
7268 *
7269 * This re-allocates a vsi's queue resources.
7270 *
7271 * Returns pointer to the successfully allocated and configured VSI sw struct
7272 * on success, otherwise returns NULL on failure.
7273 **/
7274static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7275{
7276 struct i40e_pf *pf = vsi->back;
7277 u8 enabled_tc;
7278 int ret;
7279
7280 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7281 i40e_vsi_clear_rings(vsi);
7282
7283 i40e_vsi_free_arrays(vsi, false);
7284 i40e_set_num_rings_in_vsi(vsi);
7285 ret = i40e_vsi_alloc_arrays(vsi, false);
7286 if (ret)
7287 goto err_vsi;
7288
7289 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7290 if (ret < 0) {
7291 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7292 vsi->seid, ret);
7293 goto err_vsi;
7294 }
7295 vsi->base_queue = ret;
7296
7297 /* Update the FW view of the VSI. Force a reset of TC and queue
7298 * layout configurations.
7299 */
7300 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7301 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7302 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7303 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7304
7305 /* assign it some queues */
7306 ret = i40e_alloc_rings(vsi);
7307 if (ret)
7308 goto err_rings;
7309
7310 /* map all of the rings to the q_vectors */
7311 i40e_vsi_map_rings_to_vectors(vsi);
7312 return vsi;
7313
7314err_rings:
7315 i40e_vsi_free_q_vectors(vsi);
7316 if (vsi->netdev_registered) {
7317 vsi->netdev_registered = false;
7318 unregister_netdev(vsi->netdev);
7319 free_netdev(vsi->netdev);
7320 vsi->netdev = NULL;
7321 }
7322 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7323err_vsi:
7324 i40e_vsi_clear(vsi);
7325 return NULL;
7326}
7327
41c445ff
JB		 7328/**
7329 * i40e_vsi_setup - Set up a VSI by a given type
7330 * @pf: board private structure
7331 * @type: VSI type
7332 * @uplink_seid: the switch element to link to
7333 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7334 *
7335 * This allocates the sw VSI structure and its queue resources, then add a VSI
7336 * to the identified VEB.
7337 *
7338 * Returns pointer to the successfully allocated and configure VSI sw struct on
7339 * success, otherwise returns NULL on failure.
7340 **/
7341struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7342 u16 uplink_seid, u32 param1)
7343{
7344 struct i40e_vsi *vsi = NULL;
7345 struct i40e_veb *veb = NULL;
7346 int ret, i;
7347 int v_idx;
7348
7349 /* The requested uplink_seid must be either
7350 * - the PF's port seid
7351 * no VEB is needed because this is the PF
7352 * or this is a Flow Director special case VSI
7353 * - seid of an existing VEB
7354 * - seid of a VSI that owns an existing VEB
7355 * - seid of a VSI that doesn't own a VEB
7356 * a new VEB is created and the VSI becomes the owner
7357 * - seid of the PF VSI, which is what creates the first VEB
7358 * this is a special case of the previous
7359 *
7360 * Find which uplink_seid we were given and create a new VEB if needed
7361 */
7362 for (i = 0; i < I40E_MAX_VEB; i++) {
7363 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7364 veb = pf->veb[i];
7365 break;
7366 }
7367 }
7368
7369 if (!veb && uplink_seid != pf->mac_seid) {
7370
7371 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7372 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7373 vsi = pf->vsi[i];
7374 break;
7375 }
7376 }
7377 if (!vsi) {
7378 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7379 uplink_seid);
7380 return NULL;
7381 }
7382
7383 if (vsi->uplink_seid == pf->mac_seid)
7384 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7385 vsi->tc_config.enabled_tc);
7386 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7387 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7388 vsi->tc_config.enabled_tc);
7389
7390 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7391 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7392 veb = pf->veb[i];
7393 }
7394 if (!veb) {
7395 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7396 return NULL;
7397 }
7398
7399 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7400 uplink_seid = veb->seid;
7401 }
7402
7403 /* get vsi sw struct */
7404 v_idx = i40e_vsi_mem_alloc(pf, type);
7405 if (v_idx < 0)
7406 goto err_alloc;
7407 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7408 if (!vsi)
7409 goto err_alloc;
41c445ff
JB		 7410 vsi->type = type;
7411 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7412
7413 if (type == I40E_VSI_MAIN)
7414 pf->lan_vsi = v_idx;
7415 else if (type == I40E_VSI_SRIOV)
7416 vsi->vf_id = param1;
7417 /* assign it some queues */
cbf61325
ASJ		 7418 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7419 vsi->idx);
41c445ff
JB		 7420 if (ret < 0) {
7421 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7422 vsi->seid, ret);
7423 goto err_vsi;
7424 }
7425 vsi->base_queue = ret;
7426
7427 /* get a VSI from the hardware */
7428 vsi->uplink_seid = uplink_seid;
7429 ret = i40e_add_vsi(vsi);
7430 if (ret)
7431 goto err_vsi;
7432
7433 switch (vsi->type) {
7434 /* setup the netdev if needed */
7435 case I40E_VSI_MAIN:
7436 case I40E_VSI_VMDQ2:
7437 ret = i40e_config_netdev(vsi);
7438 if (ret)
7439 goto err_netdev;
7440 ret = register_netdev(vsi->netdev);
7441 if (ret)
7442 goto err_netdev;
7443 vsi->netdev_registered = true;
7444 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7445#ifdef CONFIG_I40E_DCB
7446 /* Setup DCB netlink interface */
7447 i40e_dcbnl_setup(vsi);
7448#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7449 /* fall through */
7450
7451 case I40E_VSI_FDIR:
7452 /* set up vectors and rings if needed */
7453 ret = i40e_vsi_setup_vectors(vsi);
7454 if (ret)
7455 goto err_msix;
7456
7457 ret = i40e_alloc_rings(vsi);
7458 if (ret)
7459 goto err_rings;
7460
7461 /* map all of the rings to the q_vectors */
7462 i40e_vsi_map_rings_to_vectors(vsi);
7463
7464 i40e_vsi_reset_stats(vsi);
7465 break;
7466
7467 default:
7468 /* no netdev or rings for the other VSI types */
7469 break;
7470 }
7471
7472 return vsi;
7473
7474err_rings:
7475 i40e_vsi_free_q_vectors(vsi);
7476err_msix:
7477 if (vsi->netdev_registered) {
7478 vsi->netdev_registered = false;
7479 unregister_netdev(vsi->netdev);
7480 free_netdev(vsi->netdev);
7481 vsi->netdev = NULL;
7482 }
7483err_netdev:
7484 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7485err_vsi:
7486 i40e_vsi_clear(vsi);
7487err_alloc:
7488 return NULL;
7489}
7490
7491/**
7492 * i40e_veb_get_bw_info - Query VEB BW information
7493 * @veb: the veb to query
7494 *
7495 * Query the Tx scheduler BW configuration data for given VEB
7496 **/
7497static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7498{
7499 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7500 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7501 struct i40e_pf *pf = veb->pf;
7502 struct i40e_hw *hw = &pf->hw;
7503 u32 tc_bw_max;
7504 int ret = 0;
7505 int i;
7506
7507 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7508 &bw_data, NULL);
7509 if (ret) {
7510 dev_info(&pf->pdev->dev,
7511 "query veb bw config failed, aq_err=%d\n",
7512 hw->aq.asq_last_status);
7513 goto out;
7514 }
7515
7516 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7517 &ets_data, NULL);
7518 if (ret) {
7519 dev_info(&pf->pdev->dev,
7520 "query veb bw ets config failed, aq_err=%d\n",
7521 hw->aq.asq_last_status);
7522 goto out;
7523 }
7524
7525 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7526 veb->bw_max_quanta = ets_data.tc_bw_max;
7527 veb->is_abs_credits = bw_data.absolute_credits_enable;
7528 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7529 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7530 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7531 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7532 veb->bw_tc_limit_credits[i] =
7533 le16_to_cpu(bw_data.tc_bw_limits[i]);
7534 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7535 }
7536
7537out:
7538 return ret;
7539}
7540
7541/**
7542 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7543 * @pf: board private structure
7544 *
7545 * On error: returns error code (negative)
7546 * On success: returns vsi index in PF (positive)
7547 **/
7548static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7549{
7550 int ret = -ENOENT;
7551 struct i40e_veb *veb;
7552 int i;
7553
7554 /* Need to protect the allocation of switch elements at the PF level */
7555 mutex_lock(&pf->switch_mutex);
7556
7557 /* VEB list may be fragmented if VEB creation/destruction has
7558 * been happening. We can afford to do a quick scan to look
7559 * for any free slots in the list.
7560 *
7561 * find next empty veb slot, looping back around if necessary
7562 */
7563 i = 0;
7564 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7565 i++;
7566 if (i >= I40E_MAX_VEB) {
7567 ret = -ENOMEM;
7568 goto err_alloc_veb; /* out of VEB slots! */
7569 }
7570
7571 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7572 if (!veb) {
7573 ret = -ENOMEM;
7574 goto err_alloc_veb;
7575 }
7576 veb->pf = pf;
7577 veb->idx = i;
7578 veb->enabled_tc = 1;
7579
7580 pf->veb[i] = veb;
7581 ret = i;
7582err_alloc_veb:
7583 mutex_unlock(&pf->switch_mutex);
7584 return ret;
7585}
7586
7587/**
7588 * i40e_switch_branch_release - Delete a branch of the switch tree
7589 * @branch: where to start deleting
7590 *
7591 * This uses recursion to find the tips of the branch to be
7592 * removed, deleting until we get back to and can delete this VEB.
7593 **/
7594static void i40e_switch_branch_release(struct i40e_veb *branch)
7595{
7596 struct i40e_pf *pf = branch->pf;
7597 u16 branch_seid = branch->seid;
7598 u16 veb_idx = branch->idx;
7599 int i;
7600
7601 /* release any VEBs on this VEB - RECURSION */
7602 for (i = 0; i < I40E_MAX_VEB; i++) {
7603 if (!pf->veb[i])
7604 continue;
7605 if (pf->veb[i]->uplink_seid == branch->seid)
7606 i40e_switch_branch_release(pf->veb[i]);
7607 }
7608
7609 /* Release the VSIs on this VEB, but not the owner VSI.
7610 *
7611 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7612 * the VEB itself, so don't use (*branch) after this loop.
7613 */
7614 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7615 if (!pf->vsi[i])
7616 continue;
7617 if (pf->vsi[i]->uplink_seid == branch_seid &&
7618 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7619 i40e_vsi_release(pf->vsi[i]);
7620 }
7621 }
7622
7623 /* There's one corner case where the VEB might not have been
7624 * removed, so double check it here and remove it if needed.
7625 * This case happens if the veb was created from the debugfs
7626 * commands and no VSIs were added to it.
7627 */
7628 if (pf->veb[veb_idx])
7629 i40e_veb_release(pf->veb[veb_idx]);
7630}
7631
7632/**
7633 * i40e_veb_clear - remove veb struct
7634 * @veb: the veb to remove
7635 **/
7636static void i40e_veb_clear(struct i40e_veb *veb)
7637{
7638 if (!veb)
7639 return;
7640
7641 if (veb->pf) {
7642 struct i40e_pf *pf = veb->pf;
7643
7644 mutex_lock(&pf->switch_mutex);
7645 if (pf->veb[veb->idx] == veb)
7646 pf->veb[veb->idx] = NULL;
7647 mutex_unlock(&pf->switch_mutex);
7648 }
7649
7650 kfree(veb);
7651}
7652
7653/**
7654 * i40e_veb_release - Delete a VEB and free its resources
7655 * @veb: the VEB being removed
7656 **/
7657void i40e_veb_release(struct i40e_veb *veb)
7658{
7659 struct i40e_vsi *vsi = NULL;
7660 struct i40e_pf *pf;
7661 int i, n = 0;
7662
7663 pf = veb->pf;
7664
7665 /* find the remaining VSI and check for extras */
7666 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7667 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7668 n++;
7669 vsi = pf->vsi[i];
7670 }
7671 }
7672 if (n != 1) {
7673 dev_info(&pf->pdev->dev,
7674 "can't remove VEB %d with %d VSIs left\n",
7675 veb->seid, n);
7676 return;
7677 }
7678
7679 /* move the remaining VSI to uplink veb */
7680 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7681 if (veb->uplink_seid) {
7682 vsi->uplink_seid = veb->uplink_seid;
7683 if (veb->uplink_seid == pf->mac_seid)
7684 vsi->veb_idx = I40E_NO_VEB;
7685 else
7686 vsi->veb_idx = veb->veb_idx;
7687 } else {
7688 /* floating VEB */
7689 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7690 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7691 }
7692
7693 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7694 i40e_veb_clear(veb);
41c445ff
JB		 7695}
7696
7697/**
7698 * i40e_add_veb - create the VEB in the switch
7699 * @veb: the VEB to be instantiated
7700 * @vsi: the controlling VSI
7701 **/
7702static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7703{
56747264 7704 bool is_default = false;
e1c51b95 7705 bool is_cloud = false;
41c445ff
JB		 7706 int ret;
7707
7708 /* get a VEB from the hardware */
7709 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7710 veb->enabled_tc, is_default,
7711 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7712 if (ret) {
7713 dev_info(&veb->pf->pdev->dev,
7714 "couldn't add VEB, err %d, aq_err %d\n",
7715 ret, veb->pf->hw.aq.asq_last_status);
7716 return -EPERM;
7717 }
7718
7719 /* get statistics counter */
7720 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7721 &veb->stats_idx, NULL, NULL, NULL);
7722 if (ret) {
7723 dev_info(&veb->pf->pdev->dev,
7724 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7725 ret, veb->pf->hw.aq.asq_last_status);
7726 return -EPERM;
7727 }
7728 ret = i40e_veb_get_bw_info(veb);
7729 if (ret) {
7730 dev_info(&veb->pf->pdev->dev,
7731 "couldn't get VEB bw info, err %d, aq_err %d\n",
7732 ret, veb->pf->hw.aq.asq_last_status);
7733 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7734 return -ENOENT;
7735 }
7736
7737 vsi->uplink_seid = veb->seid;
7738 vsi->veb_idx = veb->idx;
7739 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7740
7741 return 0;
7742}
7743
7744/**
7745 * i40e_veb_setup - Set up a VEB
7746 * @pf: board private structure
7747 * @flags: VEB setup flags
7748 * @uplink_seid: the switch element to link to
7749 * @vsi_seid: the initial VSI seid
7750 * @enabled_tc: Enabled TC bit-map
7751 *
7752 * This allocates the sw VEB structure and links it into the switch
7753 * It is possible and legal for this to be a duplicate of an already
7754 * existing VEB. It is also possible for both uplink and vsi seids
7755 * to be zero, in order to create a floating VEB.
7756 *
7757 * Returns pointer to the successfully allocated VEB sw struct on
7758 * success, otherwise returns NULL on failure.
7759 **/
7760struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7761 u16 uplink_seid, u16 vsi_seid,
7762 u8 enabled_tc)
7763{
7764 struct i40e_veb *veb, *uplink_veb = NULL;
7765 int vsi_idx, veb_idx;
7766 int ret;
7767
7768 /* if one seid is 0, the other must be 0 to create a floating relay */
7769 if ((uplink_seid == 0 || vsi_seid == 0) &&
7770 (uplink_seid + vsi_seid != 0)) {
7771 dev_info(&pf->pdev->dev,
7772 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7773 uplink_seid, vsi_seid);
7774 return NULL;
7775 }
7776
7777 /* make sure there is such a vsi and uplink */
7778 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7779 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7780 break;
7781 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7782 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7783 vsi_seid);
7784 return NULL;
7785 }
7786
7787 if (uplink_seid && uplink_seid != pf->mac_seid) {
7788 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7789 if (pf->veb[veb_idx] &&
7790 pf->veb[veb_idx]->seid == uplink_seid) {
7791 uplink_veb = pf->veb[veb_idx];
7792 break;
7793 }
7794 }
7795 if (!uplink_veb) {
7796 dev_info(&pf->pdev->dev,
7797 "uplink seid %d not found\n", uplink_seid);
7798 return NULL;
7799 }
7800 }
7801
7802 /* get veb sw struct */
7803 veb_idx = i40e_veb_mem_alloc(pf);
7804 if (veb_idx < 0)
7805 goto err_alloc;
7806 veb = pf->veb[veb_idx];
7807 veb->flags = flags;
7808 veb->uplink_seid = uplink_seid;
7809 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7810 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7811
7812 /* create the VEB in the switch */
7813 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7814 if (ret)
7815 goto err_veb;
1bb8b935
SN		 7816 if (vsi_idx == pf->lan_vsi)
7817 pf->lan_veb = veb->idx;
41c445ff
JB		 7818
7819 return veb;
7820
7821err_veb:
7822 i40e_veb_clear(veb);
7823err_alloc:
7824 return NULL;
7825}
7826
7827/**
7828 * i40e_setup_pf_switch_element - set pf vars based on switch type
7829 * @pf: board private structure
7830 * @ele: element we are building info from
7831 * @num_reported: total number of elements
7832 * @printconfig: should we print the contents
7833 *
7834 * helper function to assist in extracting a few useful SEID values.
7835 **/
7836static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7837 struct i40e_aqc_switch_config_element_resp *ele,
7838 u16 num_reported, bool printconfig)
7839{
7840 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7841 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7842 u8 element_type = ele->element_type;
7843 u16 seid = le16_to_cpu(ele->seid);
7844
7845 if (printconfig)
7846 dev_info(&pf->pdev->dev,
7847 "type=%d seid=%d uplink=%d downlink=%d\n",
7848 element_type, seid, uplink_seid, downlink_seid);
7849
7850 switch (element_type) {
7851 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7852 pf->mac_seid = seid;
7853 break;
7854 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7855 /* Main VEB? */
7856 if (uplink_seid != pf->mac_seid)
7857 break;
7858 if (pf->lan_veb == I40E_NO_VEB) {
7859 int v;
7860
7861 /* find existing or else empty VEB */
7862 for (v = 0; v < I40E_MAX_VEB; v++) {
7863 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7864 pf->lan_veb = v;
7865 break;
7866 }
7867 }
7868 if (pf->lan_veb == I40E_NO_VEB) {
7869 v = i40e_veb_mem_alloc(pf);
7870 if (v < 0)
7871 break;
7872 pf->lan_veb = v;
7873 }
7874 }
7875
7876 pf->veb[pf->lan_veb]->seid = seid;
7877 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7878 pf->veb[pf->lan_veb]->pf = pf;
7879 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7880 break;
7881 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7882 if (num_reported != 1)
7883 break;
7884 /* This is immediately after a reset so we can assume this is
7885 * the PF's VSI
7886 */
7887 pf->mac_seid = uplink_seid;
7888 pf->pf_seid = downlink_seid;
7889 pf->main_vsi_seid = seid;
7890 if (printconfig)
7891 dev_info(&pf->pdev->dev,
7892 "pf_seid=%d main_vsi_seid=%d\n",
7893 pf->pf_seid, pf->main_vsi_seid);
7894 break;
7895 case I40E_SWITCH_ELEMENT_TYPE_PF:
7896 case I40E_SWITCH_ELEMENT_TYPE_VF:
7897 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7898 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7899 case I40E_SWITCH_ELEMENT_TYPE_PE:
7900 case I40E_SWITCH_ELEMENT_TYPE_PA:
7901 /* ignore these for now */
7902 break;
7903 default:
7904 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7905 element_type, seid);
7906 break;
7907 }
7908}
7909
7910/**
7911 * i40e_fetch_switch_configuration - Get switch config from firmware
7912 * @pf: board private structure
7913 * @printconfig: should we print the contents
7914 *
7915 * Get the current switch configuration from the device and
7916 * extract a few useful SEID values.
7917 **/
7918int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7919{
7920 struct i40e_aqc_get_switch_config_resp *sw_config;
7921 u16 next_seid = 0;
7922 int ret = 0;
7923 u8 *aq_buf;
7924 int i;
7925
7926 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7927 if (!aq_buf)
7928 return -ENOMEM;
7929
7930 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7931 do {
7932 u16 num_reported, num_total;
7933
7934 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7935 I40E_AQ_LARGE_BUF,
7936 &next_seid, NULL);
7937 if (ret) {
7938 dev_info(&pf->pdev->dev,
7939 "get switch config failed %d aq_err=%x\n",
7940 ret, pf->hw.aq.asq_last_status);
7941 kfree(aq_buf);
7942 return -ENOENT;
7943 }
7944
7945 num_reported = le16_to_cpu(sw_config->header.num_reported);
7946 num_total = le16_to_cpu(sw_config->header.num_total);
7947
7948 if (printconfig)
7949 dev_info(&pf->pdev->dev,
7950 "header: %d reported %d total\n",
7951 num_reported, num_total);
7952
7953 if (num_reported) {
7954 int sz = sizeof(*sw_config) * num_reported;
7955
7956 kfree(pf->sw_config);
7957 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7958 if (pf->sw_config)
7959 memcpy(pf->sw_config, sw_config, sz);
7960 }
7961
7962 for (i = 0; i < num_reported; i++) {
7963 struct i40e_aqc_switch_config_element_resp *ele =
7964 &sw_config->element[i];
7965
7966 i40e_setup_pf_switch_element(pf, ele, num_reported,
7967 printconfig);
7968 }
7969 } while (next_seid != 0);
7970
7971 kfree(aq_buf);
7972 return ret;
7973}
7974
7975/**
7976 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7977 * @pf: board private structure
bc7d338f 7978 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7979 *
7980 * Returns 0 on success, negative value on failure
7981 **/
bc7d338f 7982static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7983{
895106a5 7984 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7985 int ret;
7986
7987 /* find out what's out there already */
7988 ret = i40e_fetch_switch_configuration(pf, false);
7989 if (ret) {
7990 dev_info(&pf->pdev->dev,
7991 "couldn't fetch switch config, err %d, aq_err %d\n",
7992 ret, pf->hw.aq.asq_last_status);
7993 return ret;
7994 }
7995 i40e_pf_reset_stats(pf);
7996
41c445ff 7997 /* first time setup */
bc7d338f 7998 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7999 struct i40e_vsi *vsi = NULL;
8000 u16 uplink_seid;
8001
8002 /* Set up the PF VSI associated with the PF's main VSI
8003 * that is already in the HW switch
8004 */
8005 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8006 uplink_seid = pf->veb[pf->lan_veb]->seid;
8007 else
8008 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8009 if (pf->lan_vsi == I40E_NO_VSI)
8010 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8011 else if (reinit)
8012 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8013 if (!vsi) {
8014 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8015 i40e_fdir_teardown(pf);
8016 return -EAGAIN;
8017 }
41c445ff
JB		 8018 } else {
8019 /* force a reset of TC and queue layout configurations */
8020 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8021 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8022 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8023 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8024 }
8025 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8026
cbf61325
ASJ		 8027 i40e_fdir_sb_setup(pf);
8028
41c445ff
JB		 8029 /* Setup static PF queue filter control settings */
8030 ret = i40e_setup_pf_filter_control(pf);
8031 if (ret) {
8032 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8033 ret);
8034 /* Failure here should not stop continuing other steps */
8035 }
8036
8037 /* enable RSS in the HW, even for only one queue, as the stack can use
8038 * the hash
8039 */
8040 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8041 i40e_config_rss(pf);
8042
8043 /* fill in link information and enable LSE reporting */
8044 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
8045 i40e_link_event(pf);
8046
d52c20b7 8047 /* Initialize user-specific link properties */
41c445ff
JB		 8048 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8049 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 8050 /* requested_mode is set in probe or by ethtool */
8051 if (!pf->fc_autoneg_status)
8052 goto no_autoneg;
8053
8054 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
8055 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 8056 pf->hw.fc.current_mode = I40E_FC_FULL;
8057 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
8058 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
8059 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
8060 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
8061 else
d52c20b7
JB		 8062 pf->hw.fc.current_mode = I40E_FC_NONE;
8063
8064 /* sync the flow control settings with the auto-neg values */
8065 switch (pf->hw.fc.current_mode) {
8066 case I40E_FC_FULL:
8067 txfc = 1;
8068 rxfc = 1;
8069 break;
8070 case I40E_FC_TX_PAUSE:
8071 txfc = 1;
8072 rxfc = 0;
8073 break;
8074 case I40E_FC_RX_PAUSE:
8075 txfc = 0;
8076 rxfc = 1;
8077 break;
8078 case I40E_FC_NONE:
8079 case I40E_FC_DEFAULT:
8080 txfc = 0;
8081 rxfc = 0;
8082 break;
8083 case I40E_FC_PFC:
8084 /* TBD */
8085 break;
8086 /* no default case, we have to handle all possibilities here */
8087 }
8088
8089 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8090
8091 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8092 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8093 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8094
8095 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8096
d52c20b7
JB		 8097 goto fc_complete;
8098
8099no_autoneg:
8100 /* disable L2 flow control, user can turn it on if they wish */
8101 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8102 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8103 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8104
8105fc_complete:
beb0dff1
JK		 8106 i40e_ptp_init(pf);
8107
41c445ff
JB		 8108 return ret;
8109}
8110
41c445ff
JB		 8111/**
8112 * i40e_determine_queue_usage - Work out queue distribution
8113 * @pf: board private structure
8114 **/
8115static void i40e_determine_queue_usage(struct i40e_pf *pf)
8116{
41c445ff
JB		 8117 int queues_left;
8118
8119 pf->num_lan_qps = 0;
41c445ff
JB		 8120
8121 /* Find the max queues to be put into basic use. We'll always be
8122 * using TC0, whether or not DCB is running, and TC0 will get the
8123 * big RSS set.
8124 */
8125 queues_left = pf->hw.func_caps.num_tx_qp;
8126
cbf61325
ASJ		 8127 if ((queues_left == 1) ||
8128 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
8129 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
8130 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 8131 /* one qp for PF, no queues for anything else */
8132 queues_left = 0;
8133 pf->rss_size = pf->num_lan_qps = 1;
8134
8135 /* make sure all the fancies are disabled */
60ea5f83
JB		 8136 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8137 I40E_FLAG_FD_SB_ENABLED |
8138 I40E_FLAG_FD_ATR_ENABLED |
8139 I40E_FLAG_DCB_ENABLED |
8140 I40E_FLAG_SRIOV_ENABLED |
8141 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8142 } else {
cbf61325
ASJ		 8143 /* Not enough queues for all TCs */
8144 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
8145 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
8146 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8147 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8148 }
8149 pf->num_lan_qps = pf->rss_size_max;
8150 queues_left -= pf->num_lan_qps;
8151 }
8152
8153 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8154 if (queues_left > 1) {
8155 queues_left -= 1; /* save 1 queue for FD */
8156 } else {
8157 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8158 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8159 }
41c445ff
JB		 8160 }
8161
8162 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8163 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8164 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8165 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8166 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8167 }
8168
8169 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8170 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8171 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8172 (queues_left / pf->num_vmdq_qps));
8173 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8174 }
8175
f8ff1464 8176 pf->queues_left = queues_left;
41c445ff
JB		 8177}
8178
8179/**
8180 * i40e_setup_pf_filter_control - Setup PF static filter control
8181 * @pf: PF to be setup
8182 *
8183 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8184 * settings. If PE/FCoE are enabled then it will also set the per PF
8185 * based filter sizes required for them. It also enables Flow director,
8186 * ethertype and macvlan type filter settings for the pf.
8187 *
8188 * Returns 0 on success, negative on failure
8189 **/
8190static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8191{
8192 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8193
8194 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8195
8196 /* Flow Director is enabled */
60ea5f83 8197 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8198 settings->enable_fdir = true;
8199
8200 /* Ethtype and MACVLAN filters enabled for PF */
8201 settings->enable_ethtype = true;
8202 settings->enable_macvlan = true;
8203
8204 if (i40e_set_filter_control(&pf->hw, settings))
8205 return -ENOENT;
8206
8207 return 0;
8208}
8209
0c22b3dd
JB		 8210#define INFO_STRING_LEN 255
8211static void i40e_print_features(struct i40e_pf *pf)
8212{
8213 struct i40e_hw *hw = &pf->hw;
8214 char *buf, *string;
8215
8216 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8217 if (!string) {
8218 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8219 return;
8220 }
8221
8222 buf = string;
8223
8224 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8225#ifdef CONFIG_PCI_IOV
8226 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8227#endif
8228 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8229 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8230
8231 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8232 buf += sprintf(buf, "RSS ");
8233 buf += sprintf(buf, "FDir ");
8234 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
8235 buf += sprintf(buf, "ATR ");
8236 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
8237 buf += sprintf(buf, "NTUPLE ");
8238 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8239 buf += sprintf(buf, "DCB ");
8240 if (pf->flags & I40E_FLAG_PTP)
8241 buf += sprintf(buf, "PTP ");
8242
8243 BUG_ON(buf > (string + INFO_STRING_LEN));
8244 dev_info(&pf->pdev->dev, "%s\n", string);
8245 kfree(string);
8246}
8247
41c445ff
JB		 8248/**
8249 * i40e_probe - Device initialization routine
8250 * @pdev: PCI device information struct
8251 * @ent: entry in i40e_pci_tbl
8252 *
8253 * i40e_probe initializes a pf identified by a pci_dev structure.
8254 * The OS initialization, configuring of the pf private structure,
8255 * and a hardware reset occur.
8256 *
8257 * Returns 0 on success, negative on failure
8258 **/
8259static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8260{
41c445ff
JB		 8261 struct i40e_pf *pf;
8262 struct i40e_hw *hw;
93cd765b 8263 static u16 pfs_found;
d4dfb81a 8264 u16 link_status;
41c445ff
JB		 8265 int err = 0;
8266 u32 len;
8a9eb7d3 8267 u32 i;
41c445ff
JB		 8268
8269 err = pci_enable_device_mem(pdev);
8270 if (err)
8271 return err;
8272
8273 /* set up for high or low dma */
6494294f 8274 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8275 if (err) {
e3e3bfdd
JS		 8276 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8277 if (err) {
8278 dev_err(&pdev->dev,
8279 "DMA configuration failed: 0x%x\n", err);
8280 goto err_dma;
8281 }
41c445ff
JB		 8282 }
8283
8284 /* set up pci connections */
8285 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8286 IORESOURCE_MEM), i40e_driver_name);
8287 if (err) {
8288 dev_info(&pdev->dev,
8289 "pci_request_selected_regions failed %d\n", err);
8290 goto err_pci_reg;
8291 }
8292
8293 pci_enable_pcie_error_reporting(pdev);
8294 pci_set_master(pdev);
8295
8296 /* Now that we have a PCI connection, we need to do the
8297 * low level device setup. This is primarily setting up
8298 * the Admin Queue structures and then querying for the
8299 * device's current profile information.
8300 */
8301 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8302 if (!pf) {
8303 err = -ENOMEM;
8304 goto err_pf_alloc;
8305 }
8306 pf->next_vsi = 0;
8307 pf->pdev = pdev;
8308 set_bit(__I40E_DOWN, &pf->state);
8309
8310 hw = &pf->hw;
8311 hw->back = pf;
8312 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8313 pci_resource_len(pdev, 0));
8314 if (!hw->hw_addr) {
8315 err = -EIO;
8316 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8317 (unsigned int)pci_resource_start(pdev, 0),
8318 (unsigned int)pci_resource_len(pdev, 0), err);
8319 goto err_ioremap;
8320 }
8321 hw->vendor_id = pdev->vendor;
8322 hw->device_id = pdev->device;
8323 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8324 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8325 hw->subsystem_device_id = pdev->subsystem_device;
8326 hw->bus.device = PCI_SLOT(pdev->devfn);
8327 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8328 pf->instance = pfs_found;
41c445ff 8329
7134f9ce
JB		 8330 /* do a special CORER for clearing PXE mode once at init */
8331 if (hw->revision_id == 0 &&
8332 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8333 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8334 i40e_flush(hw);
8335 msleep(200);
8336 pf->corer_count++;
8337
8338 i40e_clear_pxe_mode(hw);
8339 }
8340
41c445ff
JB		 8341 /* Reset here to make sure all is clean and to define PF 'n' */
8342 err = i40e_pf_reset(hw);
8343 if (err) {
8344 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8345 goto err_pf_reset;
8346 }
8347 pf->pfr_count++;
8348
8349 hw->aq.num_arq_entries = I40E_AQ_LEN;
8350 hw->aq.num_asq_entries = I40E_AQ_LEN;
8351 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8352 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8353 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8354 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8355 "%s-pf%d:misc",
8356 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8357
8358 err = i40e_init_shared_code(hw);
8359 if (err) {
8360 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8361 goto err_pf_reset;
8362 }
8363
d52c20b7
JB		 8364 /* set up a default setting for link flow control */
8365 pf->hw.fc.requested_mode = I40E_FC_NONE;
8366
41c445ff
JB		 8367 err = i40e_init_adminq(hw);
8368 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8369 if (err) {
8370 dev_info(&pdev->dev,
8371 "init_adminq failed: %d expecting API %02x.%02x\n",
8372 err,
8373 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8374 goto err_pf_reset;
8375 }
8376
4eb3f768
SN		 8377 i40e_verify_eeprom(pf);
8378
2c5fe33b
JB		 8379 /* Rev 0 hardware was never productized */
8380 if (hw->revision_id < 1)
8381 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
8382
6ff4ef86 8383 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8384 err = i40e_get_capabilities(pf);
8385 if (err)
8386 goto err_adminq_setup;
8387
8388 err = i40e_sw_init(pf);
8389 if (err) {
8390 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8391 goto err_sw_init;
8392 }
8393
8394 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8395 hw->func_caps.num_rx_qp,
8396 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8397 if (err) {
8398 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8399 goto err_init_lan_hmc;
8400 }
8401
8402 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8403 if (err) {
8404 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8405 err = -ENOENT;
8406 goto err_configure_lan_hmc;
8407 }
8408
8409 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8410 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8411 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8412 err = -EIO;
8413 goto err_mac_addr;
8414 }
8415 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8416 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8417
8418 pci_set_drvdata(pdev, pf);
8419 pci_save_state(pdev);
4e3b35b0
NP		 8420#ifdef CONFIG_I40E_DCB
8421 err = i40e_init_pf_dcb(pf);
8422 if (err) {
8423 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8424 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
014269ff 8425 /* Continue without DCB enabled */
4e3b35b0
NP		 8426 }
8427#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8428
8429 /* set up periodic task facility */
8430 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8431 pf->service_timer_period = HZ;
8432
8433 INIT_WORK(&pf->service_task, i40e_service_task);
8434 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8435 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8436 pf->link_check_timeout = jiffies;
8437
8e2773ae
SN		 8438 /* WoL defaults to disabled */
8439 pf->wol_en = false;
8440 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8441
41c445ff
JB		 8442 /* set up the main switch operations */
8443 i40e_determine_queue_usage(pf);
8444 i40e_init_interrupt_scheme(pf);
8445
8446 /* Set up the *vsi struct based on the number of VSIs in the HW,
8447 * and set up our local tracking of the MAIN PF vsi.
8448 */
8449 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8450 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8451 if (!pf->vsi) {
8452 err = -ENOMEM;
41c445ff 8453 goto err_switch_setup;
ed87ac09 8454 }
41c445ff 8455
bc7d338f 8456 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8457 if (err) {
8458 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8459 goto err_vsis;
8460 }
8a9eb7d3
SN		 8461 /* if FDIR VSI was set up, start it now */
8462 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8463 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8464 i40e_vsi_open(pf->vsi[i]);
8465 break;
8466 }
8467 }
41c445ff
JB		 8468
8469 /* The main driver is (mostly) up and happy. We need to set this state
8470 * before setting up the misc vector or we get a race and the vector
8471 * ends up disabled forever.
8472 */
8473 clear_bit(__I40E_DOWN, &pf->state);
8474
8475 /* In case of MSIX we are going to setup the misc vector right here
8476 * to handle admin queue events etc. In case of legacy and MSI
8477 * the misc functionality and queue processing is combined in
8478 * the same vector and that gets setup at open.
8479 */
8480 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8481 err = i40e_setup_misc_vector(pf);
8482 if (err) {
8483 dev_info(&pdev->dev,
8484 "setup of misc vector failed: %d\n", err);
8485 goto err_vsis;
8486 }
8487 }
8488
df805f62 8489#ifdef CONFIG_PCI_IOV
41c445ff
JB		 8490 /* prep for VF support */
8491 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8492 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8493 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8494 u32 val;
8495
8496 /* disable link interrupts for VFs */
8497 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8498 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8499 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8500 i40e_flush(hw);
4aeec010
MW		 8501
8502 if (pci_num_vf(pdev)) {
8503 dev_info(&pdev->dev,
8504 "Active VFs found, allocating resources.\n");
8505 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8506 if (err)
8507 dev_info(&pdev->dev,
8508 "Error %d allocating resources for existing VFs\n",
8509 err);
8510 }
41c445ff 8511 }
df805f62 8512#endif /* CONFIG_PCI_IOV */
41c445ff 8513
93cd765b
ASJ		 8514 pfs_found++;
8515
41c445ff
JB		 8516 i40e_dbg_pf_init(pf);
8517
8518 /* tell the firmware that we're starting */
44033fac 8519 i40e_send_version(pf);
41c445ff
JB		 8520
8521 /* since everything's happy, start the service_task timer */
8522 mod_timer(&pf->service_timer,
8523 round_jiffies(jiffies + pf->service_timer_period));
8524
d4dfb81a
CS		 8525 /* Get the negotiated link width and speed from PCI config space */
8526 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8527
8528 i40e_set_pci_config_data(hw, link_status);
8529
69bfb110 8530 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8531 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8532 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8533 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8534 "Unknown"),
8535 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8536 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8537 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8538 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8539 "Unknown"));
8540
8541 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8542 hw->bus.speed < i40e_bus_speed_8000) {
8543 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8544 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8545 }
8546
0c22b3dd
JB		 8547 /* print a string summarizing features */
8548 i40e_print_features(pf);
8549
41c445ff
JB		 8550 return 0;
8551
8552 /* Unwind what we've done if something failed in the setup */
8553err_vsis:
8554 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8555 i40e_clear_interrupt_scheme(pf);
8556 kfree(pf->vsi);
04b03013
SN		 8557err_switch_setup:
8558 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8559 del_timer_sync(&pf->service_timer);
8560err_mac_addr:
8561err_configure_lan_hmc:
8562 (void)i40e_shutdown_lan_hmc(hw);
8563err_init_lan_hmc:
8564 kfree(pf->qp_pile);
8565 kfree(pf->irq_pile);
8566err_sw_init:
8567err_adminq_setup:
8568 (void)i40e_shutdown_adminq(hw);
8569err_pf_reset:
8570 iounmap(hw->hw_addr);
8571err_ioremap:
8572 kfree(pf);
8573err_pf_alloc:
8574 pci_disable_pcie_error_reporting(pdev);
8575 pci_release_selected_regions(pdev,
8576 pci_select_bars(pdev, IORESOURCE_MEM));
8577err_pci_reg:
8578err_dma:
8579 pci_disable_device(pdev);
8580 return err;
8581}
8582
8583/**
8584 * i40e_remove - Device removal routine
8585 * @pdev: PCI device information struct
8586 *
8587 * i40e_remove is called by the PCI subsystem to alert the driver
8588 * that is should release a PCI device. This could be caused by a
8589 * Hot-Plug event, or because the driver is going to be removed from
8590 * memory.
8591 **/
8592static void i40e_remove(struct pci_dev *pdev)
8593{
8594 struct i40e_pf *pf = pci_get_drvdata(pdev);
8595 i40e_status ret_code;
8596 u32 reg;
8597 int i;
8598
8599 i40e_dbg_pf_exit(pf);
8600
beb0dff1
JK		 8601 i40e_ptp_stop(pf);
8602
41c445ff
JB		 8603 /* no more scheduling of any task */
8604 set_bit(__I40E_DOWN, &pf->state);
8605 del_timer_sync(&pf->service_timer);
8606 cancel_work_sync(&pf->service_task);
8607
eb2d80bc
MW		 8608 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8609 i40e_free_vfs(pf);
8610 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8611 }
8612
41c445ff
JB		 8613 i40e_fdir_teardown(pf);
8614
8615 /* If there is a switch structure or any orphans, remove them.
8616 * This will leave only the PF's VSI remaining.
8617 */
8618 for (i = 0; i < I40E_MAX_VEB; i++) {
8619 if (!pf->veb[i])
8620 continue;
8621
8622 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8623 pf->veb[i]->uplink_seid == 0)
8624 i40e_switch_branch_release(pf->veb[i]);
8625 }
8626
8627 /* Now we can shutdown the PF's VSI, just before we kill
8628 * adminq and hmc.
8629 */
8630 if (pf->vsi[pf->lan_vsi])
8631 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8632
8633 i40e_stop_misc_vector(pf);
8634 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8635 synchronize_irq(pf->msix_entries[0].vector);
8636 free_irq(pf->msix_entries[0].vector, pf);
8637 }
8638
8639 /* shutdown and destroy the HMC */
8640 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8641 if (ret_code)
8642 dev_warn(&pdev->dev,
8643 "Failed to destroy the HMC resources: %d\n", ret_code);
8644
8645 /* shutdown the adminq */
41c445ff
JB		 8646 ret_code = i40e_shutdown_adminq(&pf->hw);
8647 if (ret_code)
8648 dev_warn(&pdev->dev,
8649 "Failed to destroy the Admin Queue resources: %d\n",
8650 ret_code);
8651
8652 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8653 i40e_clear_interrupt_scheme(pf);
8654 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8655 if (pf->vsi[i]) {
8656 i40e_vsi_clear_rings(pf->vsi[i]);
8657 i40e_vsi_clear(pf->vsi[i]);
8658 pf->vsi[i] = NULL;
8659 }
8660 }
8661
8662 for (i = 0; i < I40E_MAX_VEB; i++) {
8663 kfree(pf->veb[i]);
8664 pf->veb[i] = NULL;
8665 }
8666
8667 kfree(pf->qp_pile);
8668 kfree(pf->irq_pile);
8669 kfree(pf->sw_config);
8670 kfree(pf->vsi);
8671
8672 /* force a PF reset to clean anything leftover */
8673 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8674 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8675 i40e_flush(&pf->hw);
8676
8677 iounmap(pf->hw.hw_addr);
8678 kfree(pf);
8679 pci_release_selected_regions(pdev,
8680 pci_select_bars(pdev, IORESOURCE_MEM));
8681
8682 pci_disable_pcie_error_reporting(pdev);
8683 pci_disable_device(pdev);
8684}
8685
8686/**
8687 * i40e_pci_error_detected - warning that something funky happened in PCI land
8688 * @pdev: PCI device information struct
8689 *
8690 * Called to warn that something happened and the error handling steps
8691 * are in progress. Allows the driver to quiesce things, be ready for
8692 * remediation.
8693 **/
8694static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8695 enum pci_channel_state error)
8696{
8697 struct i40e_pf *pf = pci_get_drvdata(pdev);
8698
8699 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8700
8701 /* shutdown all operations */
9007bccd
SN		 8702 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8703 rtnl_lock();
8704 i40e_prep_for_reset(pf);
8705 rtnl_unlock();
8706 }
41c445ff
JB		 8707
8708 /* Request a slot reset */
8709 return PCI_ERS_RESULT_NEED_RESET;
8710}
8711
8712/**
8713 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8714 * @pdev: PCI device information struct
8715 *
8716 * Called to find if the driver can work with the device now that
8717 * the pci slot has been reset. If a basic connection seems good
8718 * (registers are readable and have sane content) then return a
8719 * happy little PCI_ERS_RESULT_xxx.
8720 **/
8721static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8722{
8723 struct i40e_pf *pf = pci_get_drvdata(pdev);
8724 pci_ers_result_t result;
8725 int err;
8726 u32 reg;
8727
8728 dev_info(&pdev->dev, "%s\n", __func__);
8729 if (pci_enable_device_mem(pdev)) {
8730 dev_info(&pdev->dev,
8731 "Cannot re-enable PCI device after reset.\n");
8732 result = PCI_ERS_RESULT_DISCONNECT;
8733 } else {
8734 pci_set_master(pdev);
8735 pci_restore_state(pdev);
8736 pci_save_state(pdev);
8737 pci_wake_from_d3(pdev, false);
8738
8739 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8740 if (reg == 0)
8741 result = PCI_ERS_RESULT_RECOVERED;
8742 else
8743 result = PCI_ERS_RESULT_DISCONNECT;
8744 }
8745
8746 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8747 if (err) {
8748 dev_info(&pdev->dev,
8749 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8750 err);
8751 /* non-fatal, continue */
8752 }
8753
8754 return result;
8755}
8756
8757/**
8758 * i40e_pci_error_resume - restart operations after PCI error recovery
8759 * @pdev: PCI device information struct
8760 *
8761 * Called to allow the driver to bring things back up after PCI error
8762 * and/or reset recovery has finished.
8763 **/
8764static void i40e_pci_error_resume(struct pci_dev *pdev)
8765{
8766 struct i40e_pf *pf = pci_get_drvdata(pdev);
8767
8768 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8769 if (test_bit(__I40E_SUSPENDED, &pf->state))
8770 return;
8771
8772 rtnl_lock();
41c445ff 8773 i40e_handle_reset_warning(pf);
9007bccd
SN		 8774 rtnl_lock();
8775}
8776
8777/**
8778 * i40e_shutdown - PCI callback for shutting down
8779 * @pdev: PCI device information struct
8780 **/
8781static void i40e_shutdown(struct pci_dev *pdev)
8782{
8783 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8784 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8785
8786 set_bit(__I40E_SUSPENDED, &pf->state);
8787 set_bit(__I40E_DOWN, &pf->state);
8788 rtnl_lock();
8789 i40e_prep_for_reset(pf);
8790 rtnl_unlock();
8791
8e2773ae
SN		 8792 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8793 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8794
9007bccd 8795 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8796 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8797 pci_set_power_state(pdev, PCI_D3hot);
8798 }
8799}
8800
8801#ifdef CONFIG_PM
8802/**
8803 * i40e_suspend - PCI callback for moving to D3
8804 * @pdev: PCI device information struct
8805 **/
8806static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8807{
8808 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8809 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8810
8811 set_bit(__I40E_SUSPENDED, &pf->state);
8812 set_bit(__I40E_DOWN, &pf->state);
8813 rtnl_lock();
8814 i40e_prep_for_reset(pf);
8815 rtnl_unlock();
8816
8e2773ae
SN		 8817 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8818 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8819
8820 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8821 pci_set_power_state(pdev, PCI_D3hot);
8822
8823 return 0;
41c445ff
JB		 8824}
8825
9007bccd
SN		 8826/**
8827 * i40e_resume - PCI callback for waking up from D3
8828 * @pdev: PCI device information struct
8829 **/
8830static int i40e_resume(struct pci_dev *pdev)
8831{
8832 struct i40e_pf *pf = pci_get_drvdata(pdev);
8833 u32 err;
8834
8835 pci_set_power_state(pdev, PCI_D0);
8836 pci_restore_state(pdev);
8837 /* pci_restore_state() clears dev->state_saves, so
8838 * call pci_save_state() again to restore it.
8839 */
8840 pci_save_state(pdev);
8841
8842 err = pci_enable_device_mem(pdev);
8843 if (err) {
8844 dev_err(&pdev->dev,
8845 "%s: Cannot enable PCI device from suspend\n",
8846 __func__);
8847 return err;
8848 }
8849 pci_set_master(pdev);
8850
8851 /* no wakeup events while running */
8852 pci_wake_from_d3(pdev, false);
8853
8854 /* handling the reset will rebuild the device state */
8855 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8856 clear_bit(__I40E_DOWN, &pf->state);
8857 rtnl_lock();
8858 i40e_reset_and_rebuild(pf, false);
8859 rtnl_unlock();
8860 }
8861
8862 return 0;
8863}
8864
8865#endif
41c445ff
JB		 8866static const struct pci_error_handlers i40e_err_handler = {
8867 .error_detected = i40e_pci_error_detected,
8868 .slot_reset = i40e_pci_error_slot_reset,
8869 .resume = i40e_pci_error_resume,
8870};
8871
8872static struct pci_driver i40e_driver = {
8873 .name = i40e_driver_name,
8874 .id_table = i40e_pci_tbl,
8875 .probe = i40e_probe,
8876 .remove = i40e_remove,
9007bccd
SN		 8877#ifdef CONFIG_PM
8878 .suspend = i40e_suspend,
8879 .resume = i40e_resume,
8880#endif
8881 .shutdown = i40e_shutdown,
41c445ff
JB		 8882 .err_handler = &i40e_err_handler,
8883 .sriov_configure = i40e_pci_sriov_configure,
8884};
8885
8886/**
8887 * i40e_init_module - Driver registration routine
8888 *
8889 * i40e_init_module is the first routine called when the driver is
8890 * loaded. All it does is register with the PCI subsystem.
8891 **/
8892static int __init i40e_init_module(void)
8893{
8894 pr_info("%s: %s - version %s\n", i40e_driver_name,
8895 i40e_driver_string, i40e_driver_version_str);
8896 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8897 i40e_dbg_init();
8898 return pci_register_driver(&i40e_driver);
8899}
8900module_init(i40e_init_module);
8901
8902/**
8903 * i40e_exit_module - Driver exit cleanup routine
8904 *
8905 * i40e_exit_module is called just before the driver is removed
8906 * from memory.
8907 **/
8908static void __exit i40e_exit_module(void)
8909{
8910 pci_unregister_driver(&i40e_driver);
8911 i40e_dbg_exit();
8912}
8913module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)