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i40e: scale msix vector use when more cores than vectors
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db
CS		 40#define DRV_VERSION_MAJOR 1
41#define DRV_VERSION_MINOR 0
e8720db1 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_pf_reset_stats - Reset all of the stats for the given pf
454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
922 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->eth.tx_discards,
925 &nsd->eth.tx_discards);
41c445ff 926
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
928 I40E_GLPRT_UPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_unicast,
931 &nsd->eth.rx_unicast);
7812fddc
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
933 I40E_GLPRT_MPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_multicast,
936 &nsd->eth.rx_multicast);
532d283d
SN		 937 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
938 I40E_GLPRT_BPRCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.rx_broadcast,
941 &nsd->eth.rx_broadcast);
942 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
943 I40E_GLPRT_UPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_unicast,
946 &nsd->eth.tx_unicast);
947 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
948 I40E_GLPRT_MPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_multicast,
951 &nsd->eth.tx_multicast);
952 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
953 I40E_GLPRT_BPTCL(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->eth.tx_broadcast,
956 &nsd->eth.tx_broadcast);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->tx_dropped_link_down,
961 &nsd->tx_dropped_link_down);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->crc_errors, &nsd->crc_errors);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 970
7812fddc
SN		 971 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_local_faults,
974 &nsd->mac_local_faults);
975 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->mac_remote_faults,
978 &nsd->mac_remote_faults);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_length_errors,
983 &nsd->rx_length_errors);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_rx, &nsd->link_xon_rx);
988 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xon_tx, &nsd->link_xon_tx);
991 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
992 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 995
7812fddc
SN		 996 for (i = 0; i < 8; i++) {
997 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_rx[i],
1000 &nsd->priority_xon_rx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xon_tx[i],
1004 &nsd->priority_xon_tx[i]);
1005 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xoff_tx[i],
1008 &nsd->priority_xoff_tx[i]);
1009 i40e_stat_update32(hw,
1010 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1011 pf->stat_offsets_loaded,
7812fddc
SN		 1012 &osd->priority_xon_2_xoff[i],
1013 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1014 }
1015
7812fddc
SN		 1016 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1017 I40E_GLPRT_PRC64L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_64, &nsd->rx_size_64);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1021 I40E_GLPRT_PRC127L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_127, &nsd->rx_size_127);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1025 I40E_GLPRT_PRC255L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_255, &nsd->rx_size_255);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1029 I40E_GLPRT_PRC511L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_511, &nsd->rx_size_511);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1033 I40E_GLPRT_PRC1023L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1023, &nsd->rx_size_1023);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1037 I40E_GLPRT_PRC1522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_1522, &nsd->rx_size_1522);
1040 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1041 I40E_GLPRT_PRC9522L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_size_big, &nsd->rx_size_big);
1044
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1046 I40E_GLPRT_PTC64L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_64, &nsd->tx_size_64);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1050 I40E_GLPRT_PTC127L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_127, &nsd->tx_size_127);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1054 I40E_GLPRT_PTC255L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_255, &nsd->tx_size_255);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1058 I40E_GLPRT_PTC511L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_511, &nsd->tx_size_511);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1062 I40E_GLPRT_PTC1023L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1023, &nsd->tx_size_1023);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1066 I40E_GLPRT_PTC1522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_1522, &nsd->tx_size_1522);
1069 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1070 I40E_GLPRT_PTC9522L(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->tx_size_big, &nsd->tx_size_big);
1073
1074 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1075 pf->stat_offsets_loaded,
1076 &osd->rx_undersize, &nsd->rx_undersize);
1077 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_fragments, &nsd->rx_fragments);
1080 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_oversize, &nsd->rx_oversize);
1083 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_jabber, &nsd->rx_jabber);
1086
433c47de
ASJ		 1087 /* FDIR stats */
1088 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1089 pf->stat_offsets_loaded,
1090 &osd->fd_atr_match, &nsd->fd_atr_match);
1091 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1092 pf->stat_offsets_loaded,
1093 &osd->fd_sb_match, &nsd->fd_sb_match);
1094
7812fddc
SN		 1095 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1096 nsd->tx_lpi_status =
1097 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1098 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1099 nsd->rx_lpi_status =
1100 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1101 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1102 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1103 pf->stat_offsets_loaded,
1104 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1105 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1106 pf->stat_offsets_loaded,
1107 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1108
41c445ff
JB		 1109 pf->stat_offsets_loaded = true;
1110}
1111
7812fddc
SN		 1112/**
1113 * i40e_update_stats - Update the various statistics counters.
1114 * @vsi: the VSI to be updated
1115 *
1116 * Update the various stats for this VSI and its related entities.
1117 **/
1118void i40e_update_stats(struct i40e_vsi *vsi)
1119{
1120 struct i40e_pf *pf = vsi->back;
1121
1122 if (vsi == pf->vsi[pf->lan_vsi])
1123 i40e_update_pf_stats(pf);
1124
1125 i40e_update_vsi_stats(vsi);
38e00438
VD		 1126#ifdef I40E_FCOE
1127 i40e_update_fcoe_stats(vsi);
1128#endif
7812fddc
SN		 1129}
1130
41c445ff
JB		 1131/**
1132 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1133 * @vsi: the VSI to be searched
1134 * @macaddr: the MAC address
1135 * @vlan: the vlan
1136 * @is_vf: make sure its a vf filter, else doesn't matter
1137 * @is_netdev: make sure its a netdev filter, else doesn't matter
1138 *
1139 * Returns ptr to the filter object or NULL
1140 **/
1141static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1142 u8 *macaddr, s16 vlan,
1143 bool is_vf, bool is_netdev)
1144{
1145 struct i40e_mac_filter *f;
1146
1147 if (!vsi || !macaddr)
1148 return NULL;
1149
1150 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1151 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1152 (vlan == f->vlan) &&
1153 (!is_vf || f->is_vf) &&
1154 (!is_netdev || f->is_netdev))
1155 return f;
1156 }
1157 return NULL;
1158}
1159
1160/**
1161 * i40e_find_mac - Find a mac addr in the macvlan filters list
1162 * @vsi: the VSI to be searched
1163 * @macaddr: the MAC address we are searching for
1164 * @is_vf: make sure its a vf filter, else doesn't matter
1165 * @is_netdev: make sure its a netdev filter, else doesn't matter
1166 *
1167 * Returns the first filter with the provided MAC address or NULL if
1168 * MAC address was not found
1169 **/
1170struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1171 bool is_vf, bool is_netdev)
1172{
1173 struct i40e_mac_filter *f;
1174
1175 if (!vsi || !macaddr)
1176 return NULL;
1177
1178 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1179 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1180 (!is_vf || f->is_vf) &&
1181 (!is_netdev || f->is_netdev))
1182 return f;
1183 }
1184 return NULL;
1185}
1186
1187/**
1188 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1189 * @vsi: the VSI to be searched
1190 *
1191 * Returns true if VSI is in vlan mode or false otherwise
1192 **/
1193bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1194{
1195 struct i40e_mac_filter *f;
1196
1197 /* Only -1 for all the filters denotes not in vlan mode
1198 * so we have to go through all the list in order to make sure
1199 */
1200 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1201 if (f->vlan >= 0)
1202 return true;
1203 }
1204
1205 return false;
1206}
1207
1208/**
1209 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1210 * @vsi: the VSI to be searched
1211 * @macaddr: the mac address to be filtered
1212 * @is_vf: true if it is a vf
1213 * @is_netdev: true if it is a netdev
1214 *
1215 * Goes through all the macvlan filters and adds a
1216 * macvlan filter for each unique vlan that already exists
1217 *
1218 * Returns first filter found on success, else NULL
1219 **/
1220struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1221 bool is_vf, bool is_netdev)
1222{
1223 struct i40e_mac_filter *f;
1224
1225 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1226 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1227 is_vf, is_netdev)) {
1228 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1229 is_vf, is_netdev))
41c445ff
JB		 1230 return NULL;
1231 }
1232 }
1233
1234 return list_first_entry_or_null(&vsi->mac_filter_list,
1235 struct i40e_mac_filter, list);
1236}
1237
8c27d42e
GR		 1238/**
1239 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1240 * @vsi: the PF Main VSI - inappropriate for any other VSI
1241 * @macaddr: the MAC address
30650cc5
SN		 1242 *
1243 * Some older firmware configurations set up a default promiscuous VLAN
1244 * filter that needs to be removed.
8c27d42e 1245 **/
30650cc5 1246static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1247{
1248 struct i40e_aqc_remove_macvlan_element_data element;
1249 struct i40e_pf *pf = vsi->back;
1250 i40e_status aq_ret;
1251
1252 /* Only appropriate for the PF main VSI */
1253 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1254 return -EINVAL;
8c27d42e 1255
30650cc5 1256 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1257 ether_addr_copy(element.mac_addr, macaddr);
1258 element.vlan_tag = 0;
1259 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1260 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1261 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1262 if (aq_ret)
30650cc5
SN		 1263 return -ENOENT;
1264
1265 return 0;
8c27d42e
GR		 1266}
1267
41c445ff
JB		 1268/**
1269 * i40e_add_filter - Add a mac/vlan filter to the VSI
1270 * @vsi: the VSI to be searched
1271 * @macaddr: the MAC address
1272 * @vlan: the vlan
1273 * @is_vf: make sure its a vf filter, else doesn't matter
1274 * @is_netdev: make sure its a netdev filter, else doesn't matter
1275 *
1276 * Returns ptr to the filter object or NULL when no memory available.
1277 **/
1278struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1279 u8 *macaddr, s16 vlan,
1280 bool is_vf, bool is_netdev)
1281{
1282 struct i40e_mac_filter *f;
1283
1284 if (!vsi || !macaddr)
1285 return NULL;
1286
1287 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1288 if (!f) {
1289 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1290 if (!f)
1291 goto add_filter_out;
1292
9a173901 1293 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1294 f->vlan = vlan;
1295 f->changed = true;
1296
1297 INIT_LIST_HEAD(&f->list);
1298 list_add(&f->list, &vsi->mac_filter_list);
1299 }
1300
1301 /* increment counter and add a new flag if needed */
1302 if (is_vf) {
1303 if (!f->is_vf) {
1304 f->is_vf = true;
1305 f->counter++;
1306 }
1307 } else if (is_netdev) {
1308 if (!f->is_netdev) {
1309 f->is_netdev = true;
1310 f->counter++;
1311 }
1312 } else {
1313 f->counter++;
1314 }
1315
1316 /* changed tells sync_filters_subtask to
1317 * push the filter down to the firmware
1318 */
1319 if (f->changed) {
1320 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1321 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1322 }
1323
1324add_filter_out:
1325 return f;
1326}
1327
1328/**
1329 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1330 * @vsi: the VSI to be searched
1331 * @macaddr: the MAC address
1332 * @vlan: the vlan
1333 * @is_vf: make sure it's a vf filter, else doesn't matter
1334 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1335 **/
1336void i40e_del_filter(struct i40e_vsi *vsi,
1337 u8 *macaddr, s16 vlan,
1338 bool is_vf, bool is_netdev)
1339{
1340 struct i40e_mac_filter *f;
1341
1342 if (!vsi || !macaddr)
1343 return;
1344
1345 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1346 if (!f || f->counter == 0)
1347 return;
1348
1349 if (is_vf) {
1350 if (f->is_vf) {
1351 f->is_vf = false;
1352 f->counter--;
1353 }
1354 } else if (is_netdev) {
1355 if (f->is_netdev) {
1356 f->is_netdev = false;
1357 f->counter--;
1358 }
1359 } else {
1360 /* make sure we don't remove a filter in use by vf or netdev */
1361 int min_f = 0;
1362 min_f += (f->is_vf ? 1 : 0);
1363 min_f += (f->is_netdev ? 1 : 0);
1364
1365 if (f->counter > min_f)
1366 f->counter--;
1367 }
1368
1369 /* counter == 0 tells sync_filters_subtask to
1370 * remove the filter from the firmware's list
1371 */
1372 if (f->counter == 0) {
1373 f->changed = true;
1374 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1375 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1376 }
1377}
1378
1379/**
1380 * i40e_set_mac - NDO callback to set mac address
1381 * @netdev: network interface device structure
1382 * @p: pointer to an address structure
1383 *
1384 * Returns 0 on success, negative on failure
1385 **/
38e00438
VD		 1386#ifdef I40E_FCOE
1387int i40e_set_mac(struct net_device *netdev, void *p)
1388#else
41c445ff 1389static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1390#endif
41c445ff
JB		 1391{
1392 struct i40e_netdev_priv *np = netdev_priv(netdev);
1393 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1394 struct i40e_pf *pf = vsi->back;
1395 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1396 struct sockaddr *addr = p;
1397 struct i40e_mac_filter *f;
1398
1399 if (!is_valid_ether_addr(addr->sa_data))
1400 return -EADDRNOTAVAIL;
1401
30650cc5
SN		 1402 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1403 netdev_info(netdev, "already using mac address %pM\n",
1404 addr->sa_data);
1405 return 0;
1406 }
41c445ff 1407
80f6428f
ASJ		 1408 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1409 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1410 return -EADDRNOTAVAIL;
1411
30650cc5
SN		 1412 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1413 netdev_info(netdev, "returning to hw mac address %pM\n",
1414 hw->mac.addr);
1415 else
1416 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1417
41c445ff
JB		 1418 if (vsi->type == I40E_VSI_MAIN) {
1419 i40e_status ret;
1420 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1421 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1422 addr->sa_data, NULL);
1423 if (ret) {
1424 netdev_info(netdev,
1425 "Addr change for Main VSI failed: %d\n",
1426 ret);
1427 return -EADDRNOTAVAIL;
1428 }
41c445ff
JB		 1429 }
1430
30650cc5
SN		 1431 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1432 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1433
30650cc5
SN		 1434 memset(&element, 0, sizeof(element));
1435 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1436 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1437 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1438 } else {
6c8ad1ba
SN		 1439 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1440 false, false);
6c8ad1ba 1441 }
41c445ff 1442
30650cc5
SN		 1443 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1444 struct i40e_aqc_add_macvlan_element_data element;
1445
1446 memset(&element, 0, sizeof(element));
1447 ether_addr_copy(element.mac_addr, hw->mac.addr);
1448 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1449 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1450 } else {
1451 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1452 false, false);
1453 if (f)
1454 f->is_laa = true;
1455 }
1456
1457 i40e_sync_vsi_filters(vsi);
1458 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1459
1460 return 0;
1461}
1462
1463/**
1464 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1465 * @vsi: the VSI being setup
1466 * @ctxt: VSI context structure
1467 * @enabled_tc: Enabled TCs bitmap
1468 * @is_add: True if called before Add VSI
1469 *
1470 * Setup VSI queue mapping for enabled traffic classes.
1471 **/
38e00438
VD		 1472#ifdef I40E_FCOE
1473void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
1477#else
41c445ff
JB		 1478static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1479 struct i40e_vsi_context *ctxt,
1480 u8 enabled_tc,
1481 bool is_add)
38e00438 1482#endif
41c445ff
JB		 1483{
1484 struct i40e_pf *pf = vsi->back;
1485 u16 sections = 0;
1486 u8 netdev_tc = 0;
1487 u16 numtc = 0;
1488 u16 qcount;
1489 u8 offset;
1490 u16 qmap;
1491 int i;
4e3b35b0 1492 u16 num_tc_qps = 0;
41c445ff
JB		 1493
1494 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1495 offset = 0;
1496
1497 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1498 /* Find numtc from enabled TC bitmap */
1499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1500 if (enabled_tc & (1 << i)) /* TC is enabled */
1501 numtc++;
1502 }
1503 if (!numtc) {
1504 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1505 numtc = 1;
1506 }
1507 } else {
1508 /* At least TC0 is enabled in case of non-DCB case */
1509 numtc = 1;
1510 }
1511
1512 vsi->tc_config.numtc = numtc;
1513 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1514 /* Number of queues per enabled TC */
eb051afe 1515 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1516 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1517
1518 /* Setup queue offset/count for all TCs for given VSI */
1519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1520 /* See if the given TC is enabled for the given VSI */
1521 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1522 int pow, num_qps;
1523
41c445ff
JB		 1524 switch (vsi->type) {
1525 case I40E_VSI_MAIN:
4e3b35b0 1526 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1527 break;
38e00438
VD		 1528#ifdef I40E_FCOE
1529 case I40E_VSI_FCOE:
1530 qcount = num_tc_qps;
1531 break;
1532#endif
41c445ff
JB		 1533 case I40E_VSI_FDIR:
1534 case I40E_VSI_SRIOV:
1535 case I40E_VSI_VMDQ2:
1536 default:
4e3b35b0 1537 qcount = num_tc_qps;
41c445ff
JB		 1538 WARN_ON(i != 0);
1539 break;
1540 }
4e3b35b0
NP		 1541 vsi->tc_config.tc_info[i].qoffset = offset;
1542 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1543
1544 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1545 num_qps = qcount;
41c445ff 1546 pow = 0;
4e3b35b0 1547 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1548 pow++;
1549 num_qps >>= 1;
1550 }
1551
1552 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1553 qmap =
1554 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1555 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1556
4e3b35b0 1557 offset += qcount;
41c445ff
JB		 1558 } else {
1559 /* TC is not enabled so set the offset to
1560 * default queue and allocate one queue
1561 * for the given TC.
1562 */
1563 vsi->tc_config.tc_info[i].qoffset = 0;
1564 vsi->tc_config.tc_info[i].qcount = 1;
1565 vsi->tc_config.tc_info[i].netdev_tc = 0;
1566
1567 qmap = 0;
1568 }
1569 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1570 }
1571
1572 /* Set actual Tx/Rx queue pairs */
1573 vsi->num_queue_pairs = offset;
1574
1575 /* Scheduler section valid can only be set for ADD VSI */
1576 if (is_add) {
1577 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1578
1579 ctxt->info.up_enable_bits = enabled_tc;
1580 }
1581 if (vsi->type == I40E_VSI_SRIOV) {
1582 ctxt->info.mapping_flags |=
1583 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1584 for (i = 0; i < vsi->num_queue_pairs; i++)
1585 ctxt->info.queue_mapping[i] =
1586 cpu_to_le16(vsi->base_queue + i);
1587 } else {
1588 ctxt->info.mapping_flags |=
1589 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1590 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1591 }
1592 ctxt->info.valid_sections |= cpu_to_le16(sections);
1593}
1594
1595/**
1596 * i40e_set_rx_mode - NDO callback to set the netdev filters
1597 * @netdev: network interface device structure
1598 **/
38e00438
VD		 1599#ifdef I40E_FCOE
1600void i40e_set_rx_mode(struct net_device *netdev)
1601#else
41c445ff 1602static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1603#endif
41c445ff
JB		 1604{
1605 struct i40e_netdev_priv *np = netdev_priv(netdev);
1606 struct i40e_mac_filter *f, *ftmp;
1607 struct i40e_vsi *vsi = np->vsi;
1608 struct netdev_hw_addr *uca;
1609 struct netdev_hw_addr *mca;
1610 struct netdev_hw_addr *ha;
1611
1612 /* add addr if not already in the filter list */
1613 netdev_for_each_uc_addr(uca, netdev) {
1614 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1615 if (i40e_is_vsi_in_vlan(vsi))
1616 i40e_put_mac_in_vlan(vsi, uca->addr,
1617 false, true);
1618 else
1619 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1620 false, true);
1621 }
1622 }
1623
1624 netdev_for_each_mc_addr(mca, netdev) {
1625 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1626 if (i40e_is_vsi_in_vlan(vsi))
1627 i40e_put_mac_in_vlan(vsi, mca->addr,
1628 false, true);
1629 else
1630 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1631 false, true);
1632 }
1633 }
1634
1635 /* remove filter if not in netdev list */
1636 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1637 bool found = false;
1638
1639 if (!f->is_netdev)
1640 continue;
1641
1642 if (is_multicast_ether_addr(f->macaddr)) {
1643 netdev_for_each_mc_addr(mca, netdev) {
1644 if (ether_addr_equal(mca->addr, f->macaddr)) {
1645 found = true;
1646 break;
1647 }
1648 }
1649 } else {
1650 netdev_for_each_uc_addr(uca, netdev) {
1651 if (ether_addr_equal(uca->addr, f->macaddr)) {
1652 found = true;
1653 break;
1654 }
1655 }
1656
1657 for_each_dev_addr(netdev, ha) {
1658 if (ether_addr_equal(ha->addr, f->macaddr)) {
1659 found = true;
1660 break;
1661 }
1662 }
1663 }
1664 if (!found)
1665 i40e_del_filter(
1666 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1667 }
1668
1669 /* check for other flag changes */
1670 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1671 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1672 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1673 }
1674}
1675
1676/**
1677 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1678 * @vsi: ptr to the VSI
1679 *
1680 * Push any outstanding VSI filter changes through the AdminQ.
1681 *
1682 * Returns 0 or error value
1683 **/
1684int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1685{
1686 struct i40e_mac_filter *f, *ftmp;
1687 bool promisc_forced_on = false;
1688 bool add_happened = false;
1689 int filter_list_len = 0;
1690 u32 changed_flags = 0;
dcae29be 1691 i40e_status aq_ret = 0;
41c445ff
JB		 1692 struct i40e_pf *pf;
1693 int num_add = 0;
1694 int num_del = 0;
1695 u16 cmd_flags;
1696
1697 /* empty array typed pointers, kcalloc later */
1698 struct i40e_aqc_add_macvlan_element_data *add_list;
1699 struct i40e_aqc_remove_macvlan_element_data *del_list;
1700
1701 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1702 usleep_range(1000, 2000);
1703 pf = vsi->back;
1704
1705 if (vsi->netdev) {
1706 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1707 vsi->current_netdev_flags = vsi->netdev->flags;
1708 }
1709
1710 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1711 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1712
1713 filter_list_len = pf->hw.aq.asq_buf_size /
1714 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1715 del_list = kcalloc(filter_list_len,
1716 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1717 GFP_KERNEL);
1718 if (!del_list)
1719 return -ENOMEM;
1720
1721 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1722 if (!f->changed)
1723 continue;
1724
1725 if (f->counter != 0)
1726 continue;
1727 f->changed = false;
1728 cmd_flags = 0;
1729
1730 /* add to delete list */
9a173901 1731 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1732 del_list[num_del].vlan_tag =
1733 cpu_to_le16((u16)(f->vlan ==
1734 I40E_VLAN_ANY ? 0 : f->vlan));
1735
41c445ff
JB		 1736 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1737 del_list[num_del].flags = cmd_flags;
1738 num_del++;
1739
1740 /* unlink from filter list */
1741 list_del(&f->list);
1742 kfree(f);
1743
1744 /* flush a full buffer */
1745 if (num_del == filter_list_len) {
dcae29be 1746 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1747 vsi->seid, del_list, num_del,
1748 NULL);
1749 num_del = 0;
1750 memset(del_list, 0, sizeof(*del_list));
1751
fdfe9cbe
SN		 1752 if (aq_ret &&
1753 pf->hw.aq.asq_last_status !=
1754 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1755 dev_info(&pf->pdev->dev,
1756 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1757 aq_ret,
41c445ff
JB		 1758 pf->hw.aq.asq_last_status);
1759 }
1760 }
1761 if (num_del) {
dcae29be 1762 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1763 del_list, num_del, NULL);
1764 num_del = 0;
1765
fdfe9cbe
SN		 1766 if (aq_ret &&
1767 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1768 dev_info(&pf->pdev->dev,
1769 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1770 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1771 }
1772
1773 kfree(del_list);
1774 del_list = NULL;
1775
1776 /* do all the adds now */
1777 filter_list_len = pf->hw.aq.asq_buf_size /
1778 sizeof(struct i40e_aqc_add_macvlan_element_data),
1779 add_list = kcalloc(filter_list_len,
1780 sizeof(struct i40e_aqc_add_macvlan_element_data),
1781 GFP_KERNEL);
1782 if (!add_list)
1783 return -ENOMEM;
1784
1785 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1786 if (!f->changed)
1787 continue;
1788
1789 if (f->counter == 0)
1790 continue;
1791 f->changed = false;
1792 add_happened = true;
1793 cmd_flags = 0;
1794
1795 /* add to add array */
9a173901 1796 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1797 add_list[num_add].vlan_tag =
1798 cpu_to_le16(
1799 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1800 add_list[num_add].queue_number = 0;
1801
1802 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1803 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1804 num_add++;
1805
1806 /* flush a full buffer */
1807 if (num_add == filter_list_len) {
dcae29be
JB		 1808 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1809 add_list, num_add,
1810 NULL);
41c445ff
JB		 1811 num_add = 0;
1812
dcae29be 1813 if (aq_ret)
41c445ff
JB		 1814 break;
1815 memset(add_list, 0, sizeof(*add_list));
1816 }
1817 }
1818 if (num_add) {
dcae29be
JB		 1819 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1820 add_list, num_add, NULL);
41c445ff
JB		 1821 num_add = 0;
1822 }
1823 kfree(add_list);
1824 add_list = NULL;
1825
30650cc5
SN		 1826 if (add_happened && aq_ret &&
1827 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1828 dev_info(&pf->pdev->dev,
1829 "add filter failed, err %d, aq_err %d\n",
dcae29be 1830 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1831 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1832 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1833 &vsi->state)) {
1834 promisc_forced_on = true;
1835 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1836 &vsi->state);
1837 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1838 }
1839 }
1840 }
1841
1842 /* check for changes in promiscuous modes */
1843 if (changed_flags & IFF_ALLMULTI) {
1844 bool cur_multipromisc;
1845 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1846 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1847 vsi->seid,
1848 cur_multipromisc,
1849 NULL);
1850 if (aq_ret)
41c445ff
JB		 1851 dev_info(&pf->pdev->dev,
1852 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1853 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1854 }
1855 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1856 bool cur_promisc;
1857 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1858 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1859 &vsi->state));
dcae29be
JB		 1860 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1861 vsi->seid,
1862 cur_promisc, NULL);
1863 if (aq_ret)
41c445ff
JB		 1864 dev_info(&pf->pdev->dev,
1865 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1866 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1867 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1868 vsi->seid,
1869 cur_promisc, NULL);
1870 if (aq_ret)
1871 dev_info(&pf->pdev->dev,
1872 "set brdcast promisc failed, err %d, aq_err %d\n",
1873 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1874 }
1875
1876 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1877 return 0;
1878}
1879
1880/**
1881 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1882 * @pf: board private structure
1883 **/
1884static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1885{
1886 int v;
1887
1888 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1889 return;
1890 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1891
505682cd 1892 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1893 if (pf->vsi[v] &&
1894 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1895 i40e_sync_vsi_filters(pf->vsi[v]);
1896 }
1897}
1898
1899/**
1900 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1901 * @netdev: network interface device structure
1902 * @new_mtu: new value for maximum frame size
1903 *
1904 * Returns 0 on success, negative on failure
1905 **/
1906static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1907{
1908 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1909 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1910 struct i40e_vsi *vsi = np->vsi;
1911
1912 /* MTU < 68 is an error and causes problems on some kernels */
1913 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1914 return -EINVAL;
1915
1916 netdev_info(netdev, "changing MTU from %d to %d\n",
1917 netdev->mtu, new_mtu);
1918 netdev->mtu = new_mtu;
1919 if (netif_running(netdev))
1920 i40e_vsi_reinit_locked(vsi);
1921
1922 return 0;
1923}
1924
beb0dff1
JK		 1925/**
1926 * i40e_ioctl - Access the hwtstamp interface
1927 * @netdev: network interface device structure
1928 * @ifr: interface request data
1929 * @cmd: ioctl command
1930 **/
1931int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1932{
1933 struct i40e_netdev_priv *np = netdev_priv(netdev);
1934 struct i40e_pf *pf = np->vsi->back;
1935
1936 switch (cmd) {
1937 case SIOCGHWTSTAMP:
1938 return i40e_ptp_get_ts_config(pf, ifr);
1939 case SIOCSHWTSTAMP:
1940 return i40e_ptp_set_ts_config(pf, ifr);
1941 default:
1942 return -EOPNOTSUPP;
1943 }
1944}
1945
41c445ff
JB		 1946/**
1947 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1948 * @vsi: the vsi being adjusted
1949 **/
1950void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1951{
1952 struct i40e_vsi_context ctxt;
1953 i40e_status ret;
1954
1955 if ((vsi->info.valid_sections &
1956 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1957 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1958 return; /* already enabled */
1959
1960 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1961 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1962 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1963
1964 ctxt.seid = vsi->seid;
1965 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1966 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1967 if (ret) {
1968 dev_info(&vsi->back->pdev->dev,
1969 "%s: update vsi failed, aq_err=%d\n",
1970 __func__, vsi->back->hw.aq.asq_last_status);
1971 }
1972}
1973
1974/**
1975 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1976 * @vsi: the vsi being adjusted
1977 **/
1978void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1979{
1980 struct i40e_vsi_context ctxt;
1981 i40e_status ret;
1982
1983 if ((vsi->info.valid_sections &
1984 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1985 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1986 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1987 return; /* already disabled */
1988
1989 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1990 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1991 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1992
1993 ctxt.seid = vsi->seid;
1994 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1995 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1996 if (ret) {
1997 dev_info(&vsi->back->pdev->dev,
1998 "%s: update vsi failed, aq_err=%d\n",
1999 __func__, vsi->back->hw.aq.asq_last_status);
2000 }
2001}
2002
2003/**
2004 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2005 * @netdev: network interface to be adjusted
2006 * @features: netdev features to test if VLAN offload is enabled or not
2007 **/
2008static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2009{
2010 struct i40e_netdev_priv *np = netdev_priv(netdev);
2011 struct i40e_vsi *vsi = np->vsi;
2012
2013 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2014 i40e_vlan_stripping_enable(vsi);
2015 else
2016 i40e_vlan_stripping_disable(vsi);
2017}
2018
2019/**
2020 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2021 * @vsi: the vsi being configured
2022 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2023 **/
2024int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2025{
2026 struct i40e_mac_filter *f, *add_f;
2027 bool is_netdev, is_vf;
41c445ff
JB		 2028
2029 is_vf = (vsi->type == I40E_VSI_SRIOV);
2030 is_netdev = !!(vsi->netdev);
2031
2032 if (is_netdev) {
2033 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2034 is_vf, is_netdev);
2035 if (!add_f) {
2036 dev_info(&vsi->back->pdev->dev,
2037 "Could not add vlan filter %d for %pM\n",
2038 vid, vsi->netdev->dev_addr);
2039 return -ENOMEM;
2040 }
2041 }
2042
2043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2044 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2045 if (!add_f) {
2046 dev_info(&vsi->back->pdev->dev,
2047 "Could not add vlan filter %d for %pM\n",
2048 vid, f->macaddr);
2049 return -ENOMEM;
2050 }
2051 }
2052
41c445ff
JB		 2053 /* Now if we add a vlan tag, make sure to check if it is the first
2054 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2055 * with 0, so we now accept untagged and specified tagged traffic
2056 * (and not any taged and untagged)
2057 */
2058 if (vid > 0) {
2059 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2060 I40E_VLAN_ANY,
2061 is_vf, is_netdev)) {
2062 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2063 I40E_VLAN_ANY, is_vf, is_netdev);
2064 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2065 is_vf, is_netdev);
2066 if (!add_f) {
2067 dev_info(&vsi->back->pdev->dev,
2068 "Could not add filter 0 for %pM\n",
2069 vsi->netdev->dev_addr);
2070 return -ENOMEM;
2071 }
2072 }
8d82a7c5 2073 }
41c445ff 2074
8d82a7c5
GR		 2075 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2076 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2077 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2078 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2079 is_vf, is_netdev)) {
2080 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2081 is_vf, is_netdev);
2082 add_f = i40e_add_filter(vsi, f->macaddr,
2083 0, is_vf, is_netdev);
2084 if (!add_f) {
2085 dev_info(&vsi->back->pdev->dev,
2086 "Could not add filter 0 for %pM\n",
2087 f->macaddr);
2088 return -ENOMEM;
2089 }
2090 }
2091 }
41c445ff
JB		 2092 }
2093
80f6428f
ASJ		 2094 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2095 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2096 return 0;
2097
2098 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2099}
2100
2101/**
2102 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2103 * @vsi: the vsi being configured
2104 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2105 *
2106 * Return: 0 on success or negative otherwise
41c445ff
JB		 2107 **/
2108int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2109{
2110 struct net_device *netdev = vsi->netdev;
2111 struct i40e_mac_filter *f, *add_f;
2112 bool is_vf, is_netdev;
2113 int filter_count = 0;
41c445ff
JB		 2114
2115 is_vf = (vsi->type == I40E_VSI_SRIOV);
2116 is_netdev = !!(netdev);
2117
2118 if (is_netdev)
2119 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2120
2121 list_for_each_entry(f, &vsi->mac_filter_list, list)
2122 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2123
41c445ff
JB		 2124 /* go through all the filters for this VSI and if there is only
2125 * vid == 0 it means there are no other filters, so vid 0 must
2126 * be replaced with -1. This signifies that we should from now
2127 * on accept any traffic (with any tag present, or untagged)
2128 */
2129 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2130 if (is_netdev) {
2131 if (f->vlan &&
2132 ether_addr_equal(netdev->dev_addr, f->macaddr))
2133 filter_count++;
2134 }
2135
2136 if (f->vlan)
2137 filter_count++;
2138 }
2139
2140 if (!filter_count && is_netdev) {
2141 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2142 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2143 is_vf, is_netdev);
2144 if (!f) {
2145 dev_info(&vsi->back->pdev->dev,
2146 "Could not add filter %d for %pM\n",
2147 I40E_VLAN_ANY, netdev->dev_addr);
2148 return -ENOMEM;
2149 }
2150 }
2151
2152 if (!filter_count) {
2153 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2154 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2155 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2156 is_vf, is_netdev);
2157 if (!add_f) {
2158 dev_info(&vsi->back->pdev->dev,
2159 "Could not add filter %d for %pM\n",
2160 I40E_VLAN_ANY, f->macaddr);
2161 return -ENOMEM;
2162 }
2163 }
2164 }
2165
80f6428f
ASJ		 2166 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2167 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2168 return 0;
2169
41c445ff
JB		 2170 return i40e_sync_vsi_filters(vsi);
2171}
2172
2173/**
2174 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2175 * @netdev: network interface to be adjusted
2176 * @vid: vlan id to be added
078b5876
JB		 2177 *
2178 * net_device_ops implementation for adding vlan ids
41c445ff 2179 **/
38e00438
VD		 2180#ifdef I40E_FCOE
2181int i40e_vlan_rx_add_vid(struct net_device *netdev,
2182 __always_unused __be16 proto, u16 vid)
2183#else
41c445ff
JB		 2184static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2185 __always_unused __be16 proto, u16 vid)
38e00438 2186#endif
41c445ff
JB		 2187{
2188 struct i40e_netdev_priv *np = netdev_priv(netdev);
2189 struct i40e_vsi *vsi = np->vsi;
078b5876 2190 int ret = 0;
41c445ff
JB		 2191
2192 if (vid > 4095)
078b5876
JB		 2193 return -EINVAL;
2194
2195 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2196
6982d429
ASJ		 2197 /* If the network stack called us with vid = 0 then
2198 * it is asking to receive priority tagged packets with
2199 * vlan id 0. Our HW receives them by default when configured
2200 * to receive untagged packets so there is no need to add an
2201 * extra filter for vlan 0 tagged packets.
41c445ff 2202 */
6982d429
ASJ		 2203 if (vid)
2204 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2205
078b5876
JB		 2206 if (!ret && (vid < VLAN_N_VID))
2207 set_bit(vid, vsi->active_vlans);
41c445ff 2208
078b5876 2209 return ret;
41c445ff
JB		 2210}
2211
2212/**
2213 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2214 * @netdev: network interface to be adjusted
2215 * @vid: vlan id to be removed
078b5876 2216 *
fdfd943e 2217 * net_device_ops implementation for removing vlan ids
41c445ff 2218 **/
38e00438
VD		 2219#ifdef I40E_FCOE
2220int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2221 __always_unused __be16 proto, u16 vid)
2222#else
41c445ff
JB		 2223static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2224 __always_unused __be16 proto, u16 vid)
38e00438 2225#endif
41c445ff
JB		 2226{
2227 struct i40e_netdev_priv *np = netdev_priv(netdev);
2228 struct i40e_vsi *vsi = np->vsi;
2229
078b5876
JB		 2230 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2231
41c445ff
JB		 2232 /* return code is ignored as there is nothing a user
2233 * can do about failure to remove and a log message was
078b5876 2234 * already printed from the other function
41c445ff
JB		 2235 */
2236 i40e_vsi_kill_vlan(vsi, vid);
2237
2238 clear_bit(vid, vsi->active_vlans);
078b5876 2239
41c445ff
JB		 2240 return 0;
2241}
2242
2243/**
2244 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2245 * @vsi: the vsi being brought back up
2246 **/
2247static void i40e_restore_vlan(struct i40e_vsi *vsi)
2248{
2249 u16 vid;
2250
2251 if (!vsi->netdev)
2252 return;
2253
2254 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2255
2256 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2257 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2258 vid);
2259}
2260
2261/**
2262 * i40e_vsi_add_pvid - Add pvid for the VSI
2263 * @vsi: the vsi being adjusted
2264 * @vid: the vlan id to set as a PVID
2265 **/
dcae29be 2266int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2267{
2268 struct i40e_vsi_context ctxt;
dcae29be 2269 i40e_status aq_ret;
41c445ff
JB		 2270
2271 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2272 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2273 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2274 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2275 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2276
2277 ctxt.seid = vsi->seid;
2278 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2279 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2280 if (aq_ret) {
41c445ff
JB		 2281 dev_info(&vsi->back->pdev->dev,
2282 "%s: update vsi failed, aq_err=%d\n",
2283 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2284 return -ENOENT;
41c445ff
JB		 2285 }
2286
dcae29be 2287 return 0;
41c445ff
JB		 2288}
2289
2290/**
2291 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2292 * @vsi: the vsi being adjusted
2293 *
2294 * Just use the vlan_rx_register() service to put it back to normal
2295 **/
2296void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2297{
6c12fcbf
GR		 2298 i40e_vlan_stripping_disable(vsi);
2299
41c445ff 2300 vsi->info.pvid = 0;
41c445ff
JB		 2301}
2302
2303/**
2304 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2305 * @vsi: ptr to the VSI
2306 *
2307 * If this function returns with an error, then it's possible one or
2308 * more of the rings is populated (while the rest are not). It is the
2309 * callers duty to clean those orphaned rings.
2310 *
2311 * Return 0 on success, negative on failure
2312 **/
2313static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2314{
2315 int i, err = 0;
2316
2317 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2318 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2319
2320 return err;
2321}
2322
2323/**
2324 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2325 * @vsi: ptr to the VSI
2326 *
2327 * Free VSI's transmit software resources
2328 **/
2329static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2330{
2331 int i;
2332
8e9dca53
GR		 2333 if (!vsi->tx_rings)
2334 return;
2335
41c445ff 2336 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2337 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2338 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2343 * @vsi: ptr to the VSI
2344 *
2345 * If this function returns with an error, then it's possible one or
2346 * more of the rings is populated (while the rest are not). It is the
2347 * callers duty to clean those orphaned rings.
2348 *
2349 * Return 0 on success, negative on failure
2350 **/
2351static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2352{
2353 int i, err = 0;
2354
2355 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2356 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2357#ifdef I40E_FCOE
2358 i40e_fcoe_setup_ddp_resources(vsi);
2359#endif
41c445ff
JB		 2360 return err;
2361}
2362
2363/**
2364 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2365 * @vsi: ptr to the VSI
2366 *
2367 * Free all receive software resources
2368 **/
2369static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2370{
2371 int i;
2372
8e9dca53
GR		 2373 if (!vsi->rx_rings)
2374 return;
2375
41c445ff 2376 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2377 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2378 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2379#ifdef I40E_FCOE
2380 i40e_fcoe_free_ddp_resources(vsi);
2381#endif
41c445ff
JB		 2382}
2383
2384/**
2385 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2386 * @ring: The Tx ring to configure
2387 *
2388 * Configure the Tx descriptor ring in the HMC context.
2389 **/
2390static int i40e_configure_tx_ring(struct i40e_ring *ring)
2391{
2392 struct i40e_vsi *vsi = ring->vsi;
2393 u16 pf_q = vsi->base_queue + ring->queue_index;
2394 struct i40e_hw *hw = &vsi->back->hw;
2395 struct i40e_hmc_obj_txq tx_ctx;
2396 i40e_status err = 0;
2397 u32 qtx_ctl = 0;
2398
2399 /* some ATR related tx ring init */
60ea5f83 2400 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2401 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2402 ring->atr_count = 0;
2403 } else {
2404 ring->atr_sample_rate = 0;
2405 }
2406
2407 /* initialize XPS */
2408 if (ring->q_vector && ring->netdev &&
4e3b35b0 2409 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2410 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2411 netif_set_xps_queue(ring->netdev,
2412 &ring->q_vector->affinity_mask,
2413 ring->queue_index);
2414
2415 /* clear the context structure first */
2416 memset(&tx_ctx, 0, sizeof(tx_ctx));
2417
2418 tx_ctx.new_context = 1;
2419 tx_ctx.base = (ring->dma / 128);
2420 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2421 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2422 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2423#ifdef I40E_FCOE
2424 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2425#endif
beb0dff1 2426 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2427 /* FDIR VSI tx ring can still use RS bit and writebacks */
2428 if (vsi->type != I40E_VSI_FDIR)
2429 tx_ctx.head_wb_ena = 1;
2430 tx_ctx.head_wb_addr = ring->dma +
2431 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2432
2433 /* As part of VSI creation/update, FW allocates certain
2434 * Tx arbitration queue sets for each TC enabled for
2435 * the VSI. The FW returns the handles to these queue
2436 * sets as part of the response buffer to Add VSI,
2437 * Update VSI, etc. AQ commands. It is expected that
2438 * these queue set handles be associated with the Tx
2439 * queues by the driver as part of the TX queue context
2440 * initialization. This has to be done regardless of
2441 * DCB as by default everything is mapped to TC0.
2442 */
2443 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2444 tx_ctx.rdylist_act = 0;
2445
2446 /* clear the context in the HMC */
2447 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2448 if (err) {
2449 dev_info(&vsi->back->pdev->dev,
2450 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2451 ring->queue_index, pf_q, err);
2452 return -ENOMEM;
2453 }
2454
2455 /* set the context in the HMC */
2456 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2457 if (err) {
2458 dev_info(&vsi->back->pdev->dev,
2459 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2460 ring->queue_index, pf_q, err);
2461 return -ENOMEM;
2462 }
2463
2464 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2465 if (vsi->type == I40E_VSI_VMDQ2)
2466 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2467 else
2468 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2469 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2470 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2471 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2472 i40e_flush(hw);
2473
2474 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2475
2476 /* cache tail off for easier writes later */
2477 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2478
2479 return 0;
2480}
2481
2482/**
2483 * i40e_configure_rx_ring - Configure a receive ring context
2484 * @ring: The Rx ring to configure
2485 *
2486 * Configure the Rx descriptor ring in the HMC context.
2487 **/
2488static int i40e_configure_rx_ring(struct i40e_ring *ring)
2489{
2490 struct i40e_vsi *vsi = ring->vsi;
2491 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2492 u16 pf_q = vsi->base_queue + ring->queue_index;
2493 struct i40e_hw *hw = &vsi->back->hw;
2494 struct i40e_hmc_obj_rxq rx_ctx;
2495 i40e_status err = 0;
2496
2497 ring->state = 0;
2498
2499 /* clear the context structure first */
2500 memset(&rx_ctx, 0, sizeof(rx_ctx));
2501
2502 ring->rx_buf_len = vsi->rx_buf_len;
2503 ring->rx_hdr_len = vsi->rx_hdr_len;
2504
2505 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2506 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2507
2508 rx_ctx.base = (ring->dma / 128);
2509 rx_ctx.qlen = ring->count;
2510
2511 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2512 set_ring_16byte_desc_enabled(ring);
2513 rx_ctx.dsize = 0;
2514 } else {
2515 rx_ctx.dsize = 1;
2516 }
2517
2518 rx_ctx.dtype = vsi->dtype;
2519 if (vsi->dtype) {
2520 set_ring_ps_enabled(ring);
2521 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2522 I40E_RX_SPLIT_IP |
2523 I40E_RX_SPLIT_TCP_UDP |
2524 I40E_RX_SPLIT_SCTP;
2525 } else {
2526 rx_ctx.hsplit_0 = 0;
2527 }
2528
2529 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2530 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2531 if (hw->revision_id == 0)
2532 rx_ctx.lrxqthresh = 0;
2533 else
2534 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2535 rx_ctx.crcstrip = 1;
2536 rx_ctx.l2tsel = 1;
2537 rx_ctx.showiv = 1;
38e00438
VD		 2538#ifdef I40E_FCOE
2539 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2540#endif
acb3676b
CS		 2541 /* set the prefena field to 1 because the manual says to */
2542 rx_ctx.prefena = 1;
41c445ff
JB		 2543
2544 /* clear the context in the HMC */
2545 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2546 if (err) {
2547 dev_info(&vsi->back->pdev->dev,
2548 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2549 ring->queue_index, pf_q, err);
2550 return -ENOMEM;
2551 }
2552
2553 /* set the context in the HMC */
2554 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2555 if (err) {
2556 dev_info(&vsi->back->pdev->dev,
2557 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2558 ring->queue_index, pf_q, err);
2559 return -ENOMEM;
2560 }
2561
2562 /* cache tail for quicker writes, and clear the reg before use */
2563 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2564 writel(0, ring->tail);
2565
2566 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2567
2568 return 0;
2569}
2570
2571/**
2572 * i40e_vsi_configure_tx - Configure the VSI for Tx
2573 * @vsi: VSI structure describing this set of rings and resources
2574 *
2575 * Configure the Tx VSI for operation.
2576 **/
2577static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2578{
2579 int err = 0;
2580 u16 i;
2581
9f65e15b
AD		 2582 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2583 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2584
2585 return err;
2586}
2587
2588/**
2589 * i40e_vsi_configure_rx - Configure the VSI for Rx
2590 * @vsi: the VSI being configured
2591 *
2592 * Configure the Rx VSI for operation.
2593 **/
2594static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2595{
2596 int err = 0;
2597 u16 i;
2598
2599 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2600 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2601 + ETH_FCS_LEN + VLAN_HLEN;
2602 else
2603 vsi->max_frame = I40E_RXBUFFER_2048;
2604
2605 /* figure out correct receive buffer length */
2606 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2607 I40E_FLAG_RX_PS_ENABLED)) {
2608 case I40E_FLAG_RX_1BUF_ENABLED:
2609 vsi->rx_hdr_len = 0;
2610 vsi->rx_buf_len = vsi->max_frame;
2611 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2612 break;
2613 case I40E_FLAG_RX_PS_ENABLED:
2614 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2615 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2616 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2617 break;
2618 default:
2619 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2620 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2621 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2622 break;
2623 }
2624
38e00438
VD		 2625#ifdef I40E_FCOE
2626 /* setup rx buffer for FCoE */
2627 if ((vsi->type == I40E_VSI_FCOE) &&
2628 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2629 vsi->rx_hdr_len = 0;
2630 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2631 vsi->max_frame = I40E_RXBUFFER_3072;
2632 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2633 }
2634
2635#endif /* I40E_FCOE */
41c445ff
JB		 2636 /* round up for the chip's needs */
2637 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2638 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2639 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2640 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2641
2642 /* set up individual rings */
2643 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2644 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2645
2646 return err;
2647}
2648
2649/**
2650 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2651 * @vsi: ptr to the VSI
2652 **/
2653static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2654{
e7046ee1 2655 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2656 u16 qoffset, qcount;
2657 int i, n;
2658
2659 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2660 return;
2661
2662 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2663 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2664 continue;
2665
2666 qoffset = vsi->tc_config.tc_info[n].qoffset;
2667 qcount = vsi->tc_config.tc_info[n].qcount;
2668 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2669 rx_ring = vsi->rx_rings[i];
2670 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2671 rx_ring->dcb_tc = n;
2672 tx_ring->dcb_tc = n;
2673 }
2674 }
2675}
2676
2677/**
2678 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2679 * @vsi: ptr to the VSI
2680 **/
2681static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2682{
2683 if (vsi->netdev)
2684 i40e_set_rx_mode(vsi->netdev);
2685}
2686
17a73f6b
JG		 2687/**
2688 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2689 * @vsi: Pointer to the targeted VSI
2690 *
2691 * This function replays the hlist on the hw where all the SB Flow Director
2692 * filters were saved.
2693 **/
2694static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2695{
2696 struct i40e_fdir_filter *filter;
2697 struct i40e_pf *pf = vsi->back;
2698 struct hlist_node *node;
2699
55a5e60b
ASJ		 2700 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2701 return;
2702
17a73f6b
JG		 2703 hlist_for_each_entry_safe(filter, node,
2704 &pf->fdir_filter_list, fdir_node) {
2705 i40e_add_del_fdir(vsi, filter, true);
2706 }
2707}
2708
41c445ff
JB		 2709/**
2710 * i40e_vsi_configure - Set up the VSI for action
2711 * @vsi: the VSI being configured
2712 **/
2713static int i40e_vsi_configure(struct i40e_vsi *vsi)
2714{
2715 int err;
2716
2717 i40e_set_vsi_rx_mode(vsi);
2718 i40e_restore_vlan(vsi);
2719 i40e_vsi_config_dcb_rings(vsi);
2720 err = i40e_vsi_configure_tx(vsi);
2721 if (!err)
2722 err = i40e_vsi_configure_rx(vsi);
2723
2724 return err;
2725}
2726
2727/**
2728 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2729 * @vsi: the VSI being configured
2730 **/
2731static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2732{
2733 struct i40e_pf *pf = vsi->back;
2734 struct i40e_q_vector *q_vector;
2735 struct i40e_hw *hw = &pf->hw;
2736 u16 vector;
2737 int i, q;
2738 u32 val;
2739 u32 qp;
2740
2741 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2742 * and PFINT_LNKLSTn registers, e.g.:
2743 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2744 */
2745 qp = vsi->base_queue;
2746 vector = vsi->base_vector;
493fb300
AD		 2747 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2748 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2749 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2750 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2751 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2752 q_vector->rx.itr);
2753 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2754 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2755 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2756 q_vector->tx.itr);
2757
2758 /* Linked list for the queuepairs assigned to this vector */
2759 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2760 for (q = 0; q < q_vector->num_ringpairs; q++) {
2761 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2762 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2763 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2764 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2765 (I40E_QUEUE_TYPE_TX
2766 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2767
2768 wr32(hw, I40E_QINT_RQCTL(qp), val);
2769
2770 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2771 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2772 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2773 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2774 (I40E_QUEUE_TYPE_RX
2775 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2776
2777 /* Terminate the linked list */
2778 if (q == (q_vector->num_ringpairs - 1))
2779 val |= (I40E_QUEUE_END_OF_LIST
2780 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2781
2782 wr32(hw, I40E_QINT_TQCTL(qp), val);
2783 qp++;
2784 }
2785 }
2786
2787 i40e_flush(hw);
2788}
2789
2790/**
2791 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2792 * @hw: ptr to the hardware info
2793 **/
2794static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2795{
2796 u32 val;
2797
2798 /* clear things first */
2799 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2800 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2801
2802 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2803 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2804 I40E_PFINT_ICR0_ENA_GRST_MASK |
2805 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2806 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2807 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2808 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2809 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2810 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2811
2812 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2813
2814 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2815 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2816 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2817
2818 /* OTHER_ITR_IDX = 0 */
2819 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2820}
2821
2822/**
2823 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2824 * @vsi: the VSI being configured
2825 **/
2826static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2827{
493fb300 2828 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2829 struct i40e_pf *pf = vsi->back;
2830 struct i40e_hw *hw = &pf->hw;
2831 u32 val;
2832
2833 /* set the ITR configuration */
2834 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2835 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2836 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2837 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2838 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2839 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2840
2841 i40e_enable_misc_int_causes(hw);
2842
2843 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2844 wr32(hw, I40E_PFINT_LNKLST0, 0);
2845
f29eaa3d 2846 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2847 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2848 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2849 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2850
2851 wr32(hw, I40E_QINT_RQCTL(0), val);
2852
2853 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2854 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2855 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2856
2857 wr32(hw, I40E_QINT_TQCTL(0), val);
2858 i40e_flush(hw);
2859}
2860
2ef28cfb
MW		 2861/**
2862 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2863 * @pf: board private structure
2864 **/
2865void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2866{
2867 struct i40e_hw *hw = &pf->hw;
2868
2869 wr32(hw, I40E_PFINT_DYN_CTL0,
2870 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2871 i40e_flush(hw);
2872}
2873
41c445ff
JB		 2874/**
2875 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2876 * @pf: board private structure
2877 **/
116a57d4 2878void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2879{
2880 struct i40e_hw *hw = &pf->hw;
2881 u32 val;
2882
2883 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2884 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2885 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2886
2887 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2888 i40e_flush(hw);
2889}
2890
2891/**
2892 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2893 * @vsi: pointer to a vsi
2894 * @vector: enable a particular Hw Interrupt vector
2895 **/
2896void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2897{
2898 struct i40e_pf *pf = vsi->back;
2899 struct i40e_hw *hw = &pf->hw;
2900 u32 val;
2901
2902 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2903 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2904 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2905 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2906 /* skip the flush */
41c445ff
JB		 2907}
2908
5c2cebda
CW		 2909/**
2910 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2911 * @vsi: pointer to a vsi
2912 * @vector: enable a particular Hw Interrupt vector
2913 **/
2914void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2915{
2916 struct i40e_pf *pf = vsi->back;
2917 struct i40e_hw *hw = &pf->hw;
2918 u32 val;
2919
2920 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2921 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2922 i40e_flush(hw);
2923}
2924
41c445ff
JB		 2925/**
2926 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2927 * @irq: interrupt number
2928 * @data: pointer to a q_vector
2929 **/
2930static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2931{
2932 struct i40e_q_vector *q_vector = data;
2933
cd0b6fa6 2934 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2935 return IRQ_HANDLED;
2936
2937 napi_schedule(&q_vector->napi);
2938
2939 return IRQ_HANDLED;
2940}
2941
41c445ff
JB		 2942/**
2943 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2944 * @vsi: the VSI being configured
2945 * @basename: name for the vector
2946 *
2947 * Allocates MSI-X vectors and requests interrupts from the kernel.
2948 **/
2949static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2950{
2951 int q_vectors = vsi->num_q_vectors;
2952 struct i40e_pf *pf = vsi->back;
2953 int base = vsi->base_vector;
2954 int rx_int_idx = 0;
2955 int tx_int_idx = 0;
2956 int vector, err;
2957
2958 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2959 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2960
cd0b6fa6 2961 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2962 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2963 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2964 tx_int_idx++;
cd0b6fa6 2965 } else if (q_vector->rx.ring) {
41c445ff
JB		 2966 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2967 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2968 } else if (q_vector->tx.ring) {
41c445ff
JB		 2969 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2970 "%s-%s-%d", basename, "tx", tx_int_idx++);
2971 } else {
2972 /* skip this unused q_vector */
2973 continue;
2974 }
2975 err = request_irq(pf->msix_entries[base + vector].vector,
2976 vsi->irq_handler,
2977 0,
2978 q_vector->name,
2979 q_vector);
2980 if (err) {
2981 dev_info(&pf->pdev->dev,
2982 "%s: request_irq failed, error: %d\n",
2983 __func__, err);
2984 goto free_queue_irqs;
2985 }
2986 /* assign the mask for this irq */
2987 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2988 &q_vector->affinity_mask);
2989 }
2990
63741846 2991 vsi->irqs_ready = true;
41c445ff
JB		 2992 return 0;
2993
2994free_queue_irqs:
2995 while (vector) {
2996 vector--;
2997 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2998 NULL);
2999 free_irq(pf->msix_entries[base + vector].vector,
3000 &(vsi->q_vectors[vector]));
3001 }
3002 return err;
3003}
3004
3005/**
3006 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3007 * @vsi: the VSI being un-configured
3008 **/
3009static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3010{
3011 struct i40e_pf *pf = vsi->back;
3012 struct i40e_hw *hw = &pf->hw;
3013 int base = vsi->base_vector;
3014 int i;
3015
3016 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3017 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3018 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3019 }
3020
3021 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3022 for (i = vsi->base_vector;
3023 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3024 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3025
3026 i40e_flush(hw);
3027 for (i = 0; i < vsi->num_q_vectors; i++)
3028 synchronize_irq(pf->msix_entries[i + base].vector);
3029 } else {
3030 /* Legacy and MSI mode - this stops all interrupt handling */
3031 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3032 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3033 i40e_flush(hw);
3034 synchronize_irq(pf->pdev->irq);
3035 }
3036}
3037
3038/**
3039 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3040 * @vsi: the VSI being configured
3041 **/
3042static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3043{
3044 struct i40e_pf *pf = vsi->back;
3045 int i;
3046
3047 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3048 for (i = vsi->base_vector;
3049 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3050 i40e_irq_dynamic_enable(vsi, i);
3051 } else {
3052 i40e_irq_dynamic_enable_icr0(pf);
3053 }
3054
1022cb6c 3055 i40e_flush(&pf->hw);
41c445ff
JB		 3056 return 0;
3057}
3058
3059/**
3060 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3061 * @pf: board private structure
3062 **/
3063static void i40e_stop_misc_vector(struct i40e_pf *pf)
3064{
3065 /* Disable ICR 0 */
3066 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3067 i40e_flush(&pf->hw);
3068}
3069
3070/**
3071 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3072 * @irq: interrupt number
3073 * @data: pointer to a q_vector
3074 *
3075 * This is the handler used for all MSI/Legacy interrupts, and deals
3076 * with both queue and non-queue interrupts. This is also used in
3077 * MSIX mode to handle the non-queue interrupts.
3078 **/
3079static irqreturn_t i40e_intr(int irq, void *data)
3080{
3081 struct i40e_pf *pf = (struct i40e_pf *)data;
3082 struct i40e_hw *hw = &pf->hw;
5e823066 3083 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3084 u32 icr0, icr0_remaining;
3085 u32 val, ena_mask;
3086
3087 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3088 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3089
116a57d4
SN		 3090 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3091 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3092 goto enable_intr;
41c445ff 3093
cd92e72f
SN		 3094 /* if interrupt but no bits showing, must be SWINT */
3095 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3096 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3097 pf->sw_int_count++;
3098
41c445ff
JB		 3099 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3100 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3101
3102 /* temporarily disable queue cause for NAPI processing */
3103 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3104 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3105 wr32(hw, I40E_QINT_RQCTL(0), qval);
3106
3107 qval = rd32(hw, I40E_QINT_TQCTL(0));
3108 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3109 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3110
3111 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3112 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3113 }
3114
3115 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3116 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3117 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3118 }
3119
3120 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3121 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3122 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3123 }
3124
3125 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3126 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3127 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3128 }
3129
3130 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3131 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3132 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3133 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3134 val = rd32(hw, I40E_GLGEN_RSTAT);
3135 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3136 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3137 if (val == I40E_RESET_CORER) {
41c445ff 3138 pf->corer_count++;
4eb3f768 3139 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3140 pf->globr_count++;
4eb3f768 3141 } else if (val == I40E_RESET_EMPR) {
41c445ff 3142 pf->empr_count++;
4eb3f768
SN		 3143 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3144 }
41c445ff
JB		 3145 }
3146
9c010ee0
ASJ		 3147 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3148 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3149 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3150 }
3151
beb0dff1
JK		 3152 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3153 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3154
3155 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3156 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3157 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3158 }
beb0dff1
JK		 3159 }
3160
41c445ff
JB		 3161 /* If a critical error is pending we have no choice but to reset the
3162 * device.
3163 * Report and mask out any remaining unexpected interrupts.
3164 */
3165 icr0_remaining = icr0 & ena_mask;
3166 if (icr0_remaining) {
3167 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3168 icr0_remaining);
9c010ee0 3169 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3170 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3171 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3172 dev_info(&pf->pdev->dev, "device will be reset\n");
3173 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3174 i40e_service_event_schedule(pf);
41c445ff
JB		 3175 }
3176 ena_mask &= ~icr0_remaining;
3177 }
5e823066 3178 ret = IRQ_HANDLED;
41c445ff 3179
5e823066 3180enable_intr:
41c445ff
JB		 3181 /* re-enable interrupt causes */
3182 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3183 if (!test_bit(__I40E_DOWN, &pf->state)) {
3184 i40e_service_event_schedule(pf);
3185 i40e_irq_dynamic_enable_icr0(pf);
3186 }
3187
5e823066 3188 return ret;
41c445ff
JB		 3189}
3190
cbf61325
ASJ		 3191/**
3192 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3193 * @tx_ring: tx ring to clean
3194 * @budget: how many cleans we're allowed
3195 *
3196 * Returns true if there's any budget left (e.g. the clean is finished)
3197 **/
3198static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3199{
3200 struct i40e_vsi *vsi = tx_ring->vsi;
3201 u16 i = tx_ring->next_to_clean;
3202 struct i40e_tx_buffer *tx_buf;
3203 struct i40e_tx_desc *tx_desc;
3204
3205 tx_buf = &tx_ring->tx_bi[i];
3206 tx_desc = I40E_TX_DESC(tx_ring, i);
3207 i -= tx_ring->count;
3208
3209 do {
3210 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3211
3212 /* if next_to_watch is not set then there is no work pending */
3213 if (!eop_desc)
3214 break;
3215
3216 /* prevent any other reads prior to eop_desc */
3217 read_barrier_depends();
3218
3219 /* if the descriptor isn't done, no work yet to do */
3220 if (!(eop_desc->cmd_type_offset_bsz &
3221 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3222 break;
3223
3224 /* clear next_to_watch to prevent false hangs */
3225 tx_buf->next_to_watch = NULL;
3226
49d7d933
ASJ		 3227 tx_desc->buffer_addr = 0;
3228 tx_desc->cmd_type_offset_bsz = 0;
3229 /* move past filter desc */
3230 tx_buf++;
3231 tx_desc++;
3232 i++;
3233 if (unlikely(!i)) {
3234 i -= tx_ring->count;
3235 tx_buf = tx_ring->tx_bi;
3236 tx_desc = I40E_TX_DESC(tx_ring, 0);
3237 }
cbf61325
ASJ		 3238 /* unmap skb header data */
3239 dma_unmap_single(tx_ring->dev,
3240 dma_unmap_addr(tx_buf, dma),
3241 dma_unmap_len(tx_buf, len),
3242 DMA_TO_DEVICE);
49d7d933
ASJ		 3243 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3244 kfree(tx_buf->raw_buf);
cbf61325 3245
49d7d933
ASJ		 3246 tx_buf->raw_buf = NULL;
3247 tx_buf->tx_flags = 0;
3248 tx_buf->next_to_watch = NULL;
cbf61325 3249 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3250 tx_desc->buffer_addr = 0;
3251 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3252
49d7d933 3253 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3254 tx_buf++;
3255 tx_desc++;
3256 i++;
3257 if (unlikely(!i)) {
3258 i -= tx_ring->count;
3259 tx_buf = tx_ring->tx_bi;
3260 tx_desc = I40E_TX_DESC(tx_ring, 0);
3261 }
3262
3263 /* update budget accounting */
3264 budget--;
3265 } while (likely(budget));
3266
3267 i += tx_ring->count;
3268 tx_ring->next_to_clean = i;
3269
3270 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3271 i40e_irq_dynamic_enable(vsi,
3272 tx_ring->q_vector->v_idx + vsi->base_vector);
3273 }
3274 return budget > 0;
3275}
3276
3277/**
3278 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3279 * @irq: interrupt number
3280 * @data: pointer to a q_vector
3281 **/
3282static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3283{
3284 struct i40e_q_vector *q_vector = data;
3285 struct i40e_vsi *vsi;
3286
3287 if (!q_vector->tx.ring)
3288 return IRQ_HANDLED;
3289
3290 vsi = q_vector->tx.ring->vsi;
3291 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3292
3293 return IRQ_HANDLED;
3294}
3295
41c445ff 3296/**
cd0b6fa6 3297 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3298 * @vsi: the VSI being configured
3299 * @v_idx: vector index
cd0b6fa6 3300 * @qp_idx: queue pair index
41c445ff 3301 **/
cd0b6fa6 3302static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3303{
493fb300 3304 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3305 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3306 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3307
3308 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3309 tx_ring->next = q_vector->tx.ring;
3310 q_vector->tx.ring = tx_ring;
41c445ff 3311 q_vector->tx.count++;
cd0b6fa6
AD		 3312
3313 rx_ring->q_vector = q_vector;
3314 rx_ring->next = q_vector->rx.ring;
3315 q_vector->rx.ring = rx_ring;
3316 q_vector->rx.count++;
41c445ff
JB		 3317}
3318
3319/**
3320 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3321 * @vsi: the VSI being configured
3322 *
3323 * This function maps descriptor rings to the queue-specific vectors
3324 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3325 * one vector per queue pair, but on a constrained vector budget, we
3326 * group the queue pairs as "efficiently" as possible.
3327 **/
3328static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3329{
3330 int qp_remaining = vsi->num_queue_pairs;
3331 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3332 int num_ringpairs;
41c445ff
JB		 3333 int v_start = 0;
3334 int qp_idx = 0;
3335
3336 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3337 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3338 * It is also important to go through all the vectors available to be
3339 * sure that if we don't use all the vectors, that the remaining vectors
3340 * are cleared. This is especially important when decreasing the
3341 * number of queues in use.
41c445ff 3342 */
70114ec4 3343 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3344 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3345
3346 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3347
3348 q_vector->num_ringpairs = num_ringpairs;
3349
3350 q_vector->rx.count = 0;
3351 q_vector->tx.count = 0;
3352 q_vector->rx.ring = NULL;
3353 q_vector->tx.ring = NULL;
3354
3355 while (num_ringpairs--) {
3356 map_vector_to_qp(vsi, v_start, qp_idx);
3357 qp_idx++;
3358 qp_remaining--;
41c445ff
JB		 3359 }
3360 }
3361}
3362
3363/**
3364 * i40e_vsi_request_irq - Request IRQ from the OS
3365 * @vsi: the VSI being configured
3366 * @basename: name for the vector
3367 **/
3368static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3369{
3370 struct i40e_pf *pf = vsi->back;
3371 int err;
3372
3373 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3374 err = i40e_vsi_request_irq_msix(vsi, basename);
3375 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3376 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3377 pf->misc_int_name, pf);
3378 else
3379 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3380 pf->misc_int_name, pf);
3381
3382 if (err)
3383 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3384
3385 return err;
3386}
3387
3388#ifdef CONFIG_NET_POLL_CONTROLLER
3389/**
3390 * i40e_netpoll - A Polling 'interrupt'handler
3391 * @netdev: network interface device structure
3392 *
3393 * This is used by netconsole to send skbs without having to re-enable
3394 * interrupts. It's not called while the normal interrupt routine is executing.
3395 **/
38e00438
VD		 3396#ifdef I40E_FCOE
3397void i40e_netpoll(struct net_device *netdev)
3398#else
41c445ff 3399static void i40e_netpoll(struct net_device *netdev)
38e00438 3400#endif
41c445ff
JB		 3401{
3402 struct i40e_netdev_priv *np = netdev_priv(netdev);
3403 struct i40e_vsi *vsi = np->vsi;
3404 struct i40e_pf *pf = vsi->back;
3405 int i;
3406
3407 /* if interface is down do nothing */
3408 if (test_bit(__I40E_DOWN, &vsi->state))
3409 return;
3410
3411 pf->flags |= I40E_FLAG_IN_NETPOLL;
3412 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3413 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3414 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3415 } else {
3416 i40e_intr(pf->pdev->irq, netdev);
3417 }
3418 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3419}
3420#endif
3421
23527308
NP		 3422/**
3423 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3424 * @pf: the PF being configured
3425 * @pf_q: the PF queue
3426 * @enable: enable or disable state of the queue
3427 *
3428 * This routine will wait for the given Tx queue of the PF to reach the
3429 * enabled or disabled state.
3430 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3431 * multiple retries; else will return 0 in case of success.
3432 **/
3433static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3434{
3435 int i;
3436 u32 tx_reg;
3437
3438 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3439 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3440 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3441 break;
3442
f98a2006 3443 usleep_range(10, 20);
23527308
NP		 3444 }
3445 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3446 return -ETIMEDOUT;
3447
3448 return 0;
3449}
3450
41c445ff
JB		 3451/**
3452 * i40e_vsi_control_tx - Start or stop a VSI's rings
3453 * @vsi: the VSI being configured
3454 * @enable: start or stop the rings
3455 **/
3456static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3457{
3458 struct i40e_pf *pf = vsi->back;
3459 struct i40e_hw *hw = &pf->hw;
23527308 3460 int i, j, pf_q, ret = 0;
41c445ff
JB		 3461 u32 tx_reg;
3462
3463 pf_q = vsi->base_queue;
3464 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3465
3466 /* warn the TX unit of coming changes */
3467 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3468 if (!enable)
f98a2006 3469 usleep_range(10, 20);
351499ab 3470
6c5ef620 3471 for (j = 0; j < 50; j++) {
41c445ff 3472 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3473 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3474 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3475 break;
3476 usleep_range(1000, 2000);
3477 }
fda972f6 3478 /* Skip if the queue is already in the requested state */
7c122007 3479 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3480 continue;
41c445ff
JB		 3481
3482 /* turn on/off the queue */
c5c9eb9e
SN		 3483 if (enable) {
3484 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3485 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3486 } else {
41c445ff 3487 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3488 }
41c445ff
JB		 3489
3490 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3491
3492 /* wait for the change to finish */
23527308
NP		 3493 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3494 if (ret) {
3495 dev_info(&pf->pdev->dev,
3496 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3497 __func__, vsi->seid, pf_q,
3498 (enable ? "en" : "dis"));
3499 break;
41c445ff
JB		 3500 }
3501 }
3502
7134f9ce
JB		 3503 if (hw->revision_id == 0)
3504 mdelay(50);
23527308
NP		 3505 return ret;
3506}
3507
3508/**
3509 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3510 * @pf: the PF being configured
3511 * @pf_q: the PF queue
3512 * @enable: enable or disable state of the queue
3513 *
3514 * This routine will wait for the given Rx queue of the PF to reach the
3515 * enabled or disabled state.
3516 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3517 * multiple retries; else will return 0 in case of success.
3518 **/
3519static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3520{
3521 int i;
3522 u32 rx_reg;
3523
3524 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3525 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3526 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3527 break;
3528
f98a2006 3529 usleep_range(10, 20);
23527308
NP		 3530 }
3531 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3532 return -ETIMEDOUT;
7134f9ce 3533
41c445ff
JB		 3534 return 0;
3535}
3536
3537/**
3538 * i40e_vsi_control_rx - Start or stop a VSI's rings
3539 * @vsi: the VSI being configured
3540 * @enable: start or stop the rings
3541 **/
3542static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3543{
3544 struct i40e_pf *pf = vsi->back;
3545 struct i40e_hw *hw = &pf->hw;
23527308 3546 int i, j, pf_q, ret = 0;
41c445ff
JB		 3547 u32 rx_reg;
3548
3549 pf_q = vsi->base_queue;
3550 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3551 for (j = 0; j < 50; j++) {
41c445ff 3552 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3553 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3554 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3555 break;
3556 usleep_range(1000, 2000);
3557 }
41c445ff 3558
7c122007
CS		 3559 /* Skip if the queue is already in the requested state */
3560 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3561 continue;
41c445ff
JB		 3562
3563 /* turn on/off the queue */
3564 if (enable)
6c5ef620 3565 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3566 else
6c5ef620 3567 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3568 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3569
3570 /* wait for the change to finish */
23527308
NP		 3571 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3572 if (ret) {
3573 dev_info(&pf->pdev->dev,
3574 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3575 __func__, vsi->seid, pf_q,
3576 (enable ? "en" : "dis"));
3577 break;
41c445ff
JB		 3578 }
3579 }
3580
23527308 3581 return ret;
41c445ff
JB		 3582}
3583
3584/**
3585 * i40e_vsi_control_rings - Start or stop a VSI's rings
3586 * @vsi: the VSI being configured
3587 * @enable: start or stop the rings
3588 **/
fc18eaa0 3589int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3590{
3b867b28 3591 int ret = 0;
41c445ff
JB		 3592
3593 /* do rx first for enable and last for disable */
3594 if (request) {
3595 ret = i40e_vsi_control_rx(vsi, request);
3596 if (ret)
3597 return ret;
3598 ret = i40e_vsi_control_tx(vsi, request);
3599 } else {
3b867b28
ASJ		 3600 /* Ignore return value, we need to shutdown whatever we can */
3601 i40e_vsi_control_tx(vsi, request);
3602 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3603 }
3604
3605 return ret;
3606}
3607
3608/**
3609 * i40e_vsi_free_irq - Free the irq association with the OS
3610 * @vsi: the VSI being configured
3611 **/
3612static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3613{
3614 struct i40e_pf *pf = vsi->back;
3615 struct i40e_hw *hw = &pf->hw;
3616 int base = vsi->base_vector;
3617 u32 val, qp;
3618 int i;
3619
3620 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3621 if (!vsi->q_vectors)
3622 return;
3623
63741846
SN		 3624 if (!vsi->irqs_ready)
3625 return;
3626
3627 vsi->irqs_ready = false;
41c445ff
JB		 3628 for (i = 0; i < vsi->num_q_vectors; i++) {
3629 u16 vector = i + base;
3630
3631 /* free only the irqs that were actually requested */
78681b1f
SN		 3632 if (!vsi->q_vectors[i] ||
3633 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3634 continue;
3635
3636 /* clear the affinity_mask in the IRQ descriptor */
3637 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3638 NULL);
3639 free_irq(pf->msix_entries[vector].vector,
493fb300 3640 vsi->q_vectors[i]);
41c445ff
JB		 3641
3642 /* Tear down the interrupt queue link list
3643 *
3644 * We know that they come in pairs and always
3645 * the Rx first, then the Tx. To clear the
3646 * link list, stick the EOL value into the
3647 * next_q field of the registers.
3648 */
3649 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3650 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3651 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3652 val |= I40E_QUEUE_END_OF_LIST
3653 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3654 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3655
3656 while (qp != I40E_QUEUE_END_OF_LIST) {
3657 u32 next;
3658
3659 val = rd32(hw, I40E_QINT_RQCTL(qp));
3660
3661 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3662 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3663 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3664 I40E_QINT_RQCTL_INTEVENT_MASK);
3665
3666 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3667 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3668
3669 wr32(hw, I40E_QINT_RQCTL(qp), val);
3670
3671 val = rd32(hw, I40E_QINT_TQCTL(qp));
3672
3673 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3674 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3675
3676 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3677 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3678 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3679 I40E_QINT_TQCTL_INTEVENT_MASK);
3680
3681 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3682 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3683
3684 wr32(hw, I40E_QINT_TQCTL(qp), val);
3685 qp = next;
3686 }
3687 }
3688 } else {
3689 free_irq(pf->pdev->irq, pf);
3690
3691 val = rd32(hw, I40E_PFINT_LNKLST0);
3692 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3693 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3694 val |= I40E_QUEUE_END_OF_LIST
3695 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3696 wr32(hw, I40E_PFINT_LNKLST0, val);
3697
3698 val = rd32(hw, I40E_QINT_RQCTL(qp));
3699 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3700 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3701 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3702 I40E_QINT_RQCTL_INTEVENT_MASK);
3703
3704 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3705 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3706
3707 wr32(hw, I40E_QINT_RQCTL(qp), val);
3708
3709 val = rd32(hw, I40E_QINT_TQCTL(qp));
3710
3711 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3712 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3713 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3714 I40E_QINT_TQCTL_INTEVENT_MASK);
3715
3716 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3717 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3718
3719 wr32(hw, I40E_QINT_TQCTL(qp), val);
3720 }
3721}
3722
493fb300
AD		 3723/**
3724 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3725 * @vsi: the VSI being configured
3726 * @v_idx: Index of vector to be freed
3727 *
3728 * This function frees the memory allocated to the q_vector. In addition if
3729 * NAPI is enabled it will delete any references to the NAPI struct prior
3730 * to freeing the q_vector.
3731 **/
3732static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3733{
3734 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3735 struct i40e_ring *ring;
493fb300
AD		 3736
3737 if (!q_vector)
3738 return;
3739
3740 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3741 i40e_for_each_ring(ring, q_vector->tx)
3742 ring->q_vector = NULL;
3743
3744 i40e_for_each_ring(ring, q_vector->rx)
3745 ring->q_vector = NULL;
493fb300
AD		 3746
3747 /* only VSI w/ an associated netdev is set up w/ NAPI */
3748 if (vsi->netdev)
3749 netif_napi_del(&q_vector->napi);
3750
3751 vsi->q_vectors[v_idx] = NULL;
3752
3753 kfree_rcu(q_vector, rcu);
3754}
3755
41c445ff
JB		 3756/**
3757 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3758 * @vsi: the VSI being un-configured
3759 *
3760 * This frees the memory allocated to the q_vectors and
3761 * deletes references to the NAPI struct.
3762 **/
3763static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3764{
3765 int v_idx;
3766
493fb300
AD		 3767 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3768 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3769}
3770
3771/**
3772 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3773 * @pf: board private structure
3774 **/
3775static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3776{
3777 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3778 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3779 pci_disable_msix(pf->pdev);
3780 kfree(pf->msix_entries);
3781 pf->msix_entries = NULL;
3782 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3783 pci_disable_msi(pf->pdev);
3784 }
3785 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3786}
3787
3788/**
3789 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3790 * @pf: board private structure
3791 *
3792 * We go through and clear interrupt specific resources and reset the structure
3793 * to pre-load conditions
3794 **/
3795static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3796{
3797 int i;
3798
3799 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3800 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3801 if (pf->vsi[i])
3802 i40e_vsi_free_q_vectors(pf->vsi[i]);
3803 i40e_reset_interrupt_capability(pf);
3804}
3805
3806/**
3807 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3808 * @vsi: the VSI being configured
3809 **/
3810static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3811{
3812 int q_idx;
3813
3814 if (!vsi->netdev)
3815 return;
3816
3817 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3818 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3819}
3820
3821/**
3822 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3823 * @vsi: the VSI being configured
3824 **/
3825static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3826{
3827 int q_idx;
3828
3829 if (!vsi->netdev)
3830 return;
3831
3832 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3833 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3834}
3835
90ef8d47
SN		 3836/**
3837 * i40e_vsi_close - Shut down a VSI
3838 * @vsi: the vsi to be quelled
3839 **/
3840static void i40e_vsi_close(struct i40e_vsi *vsi)
3841{
3842 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3843 i40e_down(vsi);
3844 i40e_vsi_free_irq(vsi);
3845 i40e_vsi_free_tx_resources(vsi);
3846 i40e_vsi_free_rx_resources(vsi);
3847}
3848
41c445ff
JB		 3849/**
3850 * i40e_quiesce_vsi - Pause a given VSI
3851 * @vsi: the VSI being paused
3852 **/
3853static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3854{
3855 if (test_bit(__I40E_DOWN, &vsi->state))
3856 return;
3857
3858 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3859 if (vsi->netdev && netif_running(vsi->netdev)) {
3860 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3861 } else {
90ef8d47 3862 i40e_vsi_close(vsi);
41c445ff
JB		 3863 }
3864}
3865
3866/**
3867 * i40e_unquiesce_vsi - Resume a given VSI
3868 * @vsi: the VSI being resumed
3869 **/
3870static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3871{
3872 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3873 return;
3874
3875 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3876 if (vsi->netdev && netif_running(vsi->netdev))
3877 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3878 else
8276f757 3879 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3880}
3881
3882/**
3883 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3884 * @pf: the PF
3885 **/
3886static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3887{
3888 int v;
3889
505682cd 3890 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3891 if (pf->vsi[v])
3892 i40e_quiesce_vsi(pf->vsi[v]);
3893 }
3894}
3895
3896/**
3897 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3898 * @pf: the PF
3899 **/
3900static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3901{
3902 int v;
3903
505682cd 3904 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3905 if (pf->vsi[v])
3906 i40e_unquiesce_vsi(pf->vsi[v]);
3907 }
3908}
3909
3910/**
3911 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3912 * @dcbcfg: the corresponding DCBx configuration structure
3913 *
3914 * Return the number of TCs from given DCBx configuration
3915 **/
3916static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3917{
078b5876
JB		 3918 u8 num_tc = 0;
3919 int i;
41c445ff
JB		 3920
3921 /* Scan the ETS Config Priority Table to find
3922 * traffic class enabled for a given priority
3923 * and use the traffic class index to get the
3924 * number of traffic classes enabled
3925 */
3926 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3927 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3928 num_tc = dcbcfg->etscfg.prioritytable[i];
3929 }
3930
3931 /* Traffic class index starts from zero so
3932 * increment to return the actual count
3933 */
078b5876 3934 return num_tc + 1;
41c445ff
JB		 3935}
3936
3937/**
3938 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3939 * @dcbcfg: the corresponding DCBx configuration structure
3940 *
3941 * Query the current DCB configuration and return the number of
3942 * traffic classes enabled from the given DCBX config
3943 **/
3944static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3945{
3946 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3947 u8 enabled_tc = 1;
3948 u8 i;
3949
3950 for (i = 0; i < num_tc; i++)
3951 enabled_tc |= 1 << i;
3952
3953 return enabled_tc;
3954}
3955
3956/**
3957 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3958 * @pf: PF being queried
3959 *
3960 * Return number of traffic classes enabled for the given PF
3961 **/
3962static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3963{
3964 struct i40e_hw *hw = &pf->hw;
3965 u8 i, enabled_tc;
3966 u8 num_tc = 0;
3967 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3968
3969 /* If DCB is not enabled then always in single TC */
3970 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3971 return 1;
3972
3973 /* MFP mode return count of enabled TCs for this PF */
3974 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3975 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3976 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3977 if (enabled_tc & (1 << i))
3978 num_tc++;
3979 }
3980 return num_tc;
3981 }
3982
3983 /* SFP mode will be enabled for all TCs on port */
3984 return i40e_dcb_get_num_tc(dcbcfg);
3985}
3986
3987/**
3988 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3989 * @pf: PF being queried
3990 *
3991 * Return a bitmap for first enabled traffic class for this PF.
3992 **/
3993static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3994{
3995 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3996 u8 i = 0;
3997
3998 if (!enabled_tc)
3999 return 0x1; /* TC0 */
4000
4001 /* Find the first enabled TC */
4002 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4003 if (enabled_tc & (1 << i))
4004 break;
4005 }
4006
4007 return 1 << i;
4008}
4009
4010/**
4011 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4012 * @pf: PF being queried
4013 *
4014 * Return a bitmap for enabled traffic classes for this PF.
4015 **/
4016static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4017{
4018 /* If DCB is not enabled for this PF then just return default TC */
4019 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4020 return i40e_pf_get_default_tc(pf);
4021
4022 /* MFP mode will have enabled TCs set by FW */
4023 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4024 return pf->hw.func_caps.enabled_tcmap;
4025
4026 /* SFP mode we want PF to be enabled for all TCs */
4027 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4028}
4029
4030/**
4031 * i40e_vsi_get_bw_info - Query VSI BW Information
4032 * @vsi: the VSI being queried
4033 *
4034 * Returns 0 on success, negative value on failure
4035 **/
4036static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4037{
4038 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4039 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4040 struct i40e_pf *pf = vsi->back;
4041 struct i40e_hw *hw = &pf->hw;
dcae29be 4042 i40e_status aq_ret;
41c445ff 4043 u32 tc_bw_max;
41c445ff
JB		 4044 int i;
4045
4046 /* Get the VSI level BW configuration */
dcae29be
JB		 4047 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4048 if (aq_ret) {
41c445ff
JB		 4049 dev_info(&pf->pdev->dev,
4050 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4051 aq_ret, pf->hw.aq.asq_last_status);
4052 return -EINVAL;
41c445ff
JB		 4053 }
4054
4055 /* Get the VSI level BW configuration per TC */
dcae29be 4056 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4057 NULL);
dcae29be 4058 if (aq_ret) {
41c445ff
JB		 4059 dev_info(&pf->pdev->dev,
4060 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4061 aq_ret, pf->hw.aq.asq_last_status);
4062 return -EINVAL;
41c445ff
JB		 4063 }
4064
4065 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4066 dev_info(&pf->pdev->dev,
4067 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4068 bw_config.tc_valid_bits,
4069 bw_ets_config.tc_valid_bits);
4070 /* Still continuing */
4071 }
4072
4073 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4074 vsi->bw_max_quanta = bw_config.max_bw;
4075 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4076 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4077 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4078 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4079 vsi->bw_ets_limit_credits[i] =
4080 le16_to_cpu(bw_ets_config.credits[i]);
4081 /* 3 bits out of 4 for each TC */
4082 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4083 }
078b5876 4084
dcae29be 4085 return 0;
41c445ff
JB		 4086}
4087
4088/**
4089 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4090 * @vsi: the VSI being configured
4091 * @enabled_tc: TC bitmap
4092 * @bw_credits: BW shared credits per TC
4093 *
4094 * Returns 0 on success, negative value on failure
4095 **/
dcae29be 4096static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4097 u8 *bw_share)
4098{
4099 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4100 i40e_status aq_ret;
4101 int i;
41c445ff
JB		 4102
4103 bw_data.tc_valid_bits = enabled_tc;
4104 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4105 bw_data.tc_bw_credits[i] = bw_share[i];
4106
dcae29be
JB		 4107 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4108 NULL);
4109 if (aq_ret) {
41c445ff 4110 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4111 "AQ command Config VSI BW allocation per TC failed = %d\n",
4112 vsi->back->hw.aq.asq_last_status);
dcae29be 4113 return -EINVAL;
41c445ff
JB		 4114 }
4115
4116 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4117 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4118
dcae29be 4119 return 0;
41c445ff
JB		 4120}
4121
4122/**
4123 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4124 * @vsi: the VSI being configured
4125 * @enabled_tc: TC map to be enabled
4126 *
4127 **/
4128static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4129{
4130 struct net_device *netdev = vsi->netdev;
4131 struct i40e_pf *pf = vsi->back;
4132 struct i40e_hw *hw = &pf->hw;
4133 u8 netdev_tc = 0;
4134 int i;
4135 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4136
4137 if (!netdev)
4138 return;
4139
4140 if (!enabled_tc) {
4141 netdev_reset_tc(netdev);
4142 return;
4143 }
4144
4145 /* Set up actual enabled TCs on the VSI */
4146 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4147 return;
4148
4149 /* set per TC queues for the VSI */
4150 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4151 /* Only set TC queues for enabled tcs
4152 *
4153 * e.g. For a VSI that has TC0 and TC3 enabled the
4154 * enabled_tc bitmap would be 0x00001001; the driver
4155 * will set the numtc for netdev as 2 that will be
4156 * referenced by the netdev layer as TC 0 and 1.
4157 */
4158 if (vsi->tc_config.enabled_tc & (1 << i))
4159 netdev_set_tc_queue(netdev,
4160 vsi->tc_config.tc_info[i].netdev_tc,
4161 vsi->tc_config.tc_info[i].qcount,
4162 vsi->tc_config.tc_info[i].qoffset);
4163 }
4164
4165 /* Assign UP2TC map for the VSI */
4166 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4167 /* Get the actual TC# for the UP */
4168 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4169 /* Get the mapped netdev TC# for the UP */
4170 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4171 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4172 }
4173}
4174
4175/**
4176 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4177 * @vsi: the VSI being configured
4178 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4179 **/
4180static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4181 struct i40e_vsi_context *ctxt)
4182{
4183 /* copy just the sections touched not the entire info
4184 * since not all sections are valid as returned by
4185 * update vsi params
4186 */
4187 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4188 memcpy(&vsi->info.queue_mapping,
4189 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4190 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4191 sizeof(vsi->info.tc_mapping));
4192}
4193
4194/**
4195 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4196 * @vsi: VSI to be configured
4197 * @enabled_tc: TC bitmap
4198 *
4199 * This configures a particular VSI for TCs that are mapped to the
4200 * given TC bitmap. It uses default bandwidth share for TCs across
4201 * VSIs to configure TC for a particular VSI.
4202 *
4203 * NOTE:
4204 * It is expected that the VSI queues have been quisced before calling
4205 * this function.
4206 **/
4207static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4208{
4209 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4210 struct i40e_vsi_context ctxt;
4211 int ret = 0;
4212 int i;
4213
4214 /* Check if enabled_tc is same as existing or new TCs */
4215 if (vsi->tc_config.enabled_tc == enabled_tc)
4216 return ret;
4217
4218 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4219 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4220 if (enabled_tc & (1 << i))
4221 bw_share[i] = 1;
4222 }
4223
4224 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4225 if (ret) {
4226 dev_info(&vsi->back->pdev->dev,
4227 "Failed configuring TC map %d for VSI %d\n",
4228 enabled_tc, vsi->seid);
4229 goto out;
4230 }
4231
4232 /* Update Queue Pairs Mapping for currently enabled UPs */
4233 ctxt.seid = vsi->seid;
4234 ctxt.pf_num = vsi->back->hw.pf_id;
4235 ctxt.vf_num = 0;
4236 ctxt.uplink_seid = vsi->uplink_seid;
4237 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4238 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4239
4240 /* Update the VSI after updating the VSI queue-mapping information */
4241 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4242 if (ret) {
4243 dev_info(&vsi->back->pdev->dev,
4244 "update vsi failed, aq_err=%d\n",
4245 vsi->back->hw.aq.asq_last_status);
4246 goto out;
4247 }
4248 /* update the local VSI info with updated queue map */
4249 i40e_vsi_update_queue_map(vsi, &ctxt);
4250 vsi->info.valid_sections = 0;
4251
4252 /* Update current VSI BW information */
4253 ret = i40e_vsi_get_bw_info(vsi);
4254 if (ret) {
4255 dev_info(&vsi->back->pdev->dev,
4256 "Failed updating vsi bw info, aq_err=%d\n",
4257 vsi->back->hw.aq.asq_last_status);
4258 goto out;
4259 }
4260
4261 /* Update the netdev TC setup */
4262 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4263out:
4264 return ret;
4265}
4266
4e3b35b0
NP		 4267/**
4268 * i40e_veb_config_tc - Configure TCs for given VEB
4269 * @veb: given VEB
4270 * @enabled_tc: TC bitmap
4271 *
4272 * Configures given TC bitmap for VEB (switching) element
4273 **/
4274int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4275{
4276 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4277 struct i40e_pf *pf = veb->pf;
4278 int ret = 0;
4279 int i;
4280
4281 /* No TCs or already enabled TCs just return */
4282 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4283 return ret;
4284
4285 bw_data.tc_valid_bits = enabled_tc;
4286 /* bw_data.absolute_credits is not set (relative) */
4287
4288 /* Enable ETS TCs with equal BW Share for now */
4289 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4290 if (enabled_tc & (1 << i))
4291 bw_data.tc_bw_share_credits[i] = 1;
4292 }
4293
4294 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4295 &bw_data, NULL);
4296 if (ret) {
4297 dev_info(&pf->pdev->dev,
4298 "veb bw config failed, aq_err=%d\n",
4299 pf->hw.aq.asq_last_status);
4300 goto out;
4301 }
4302
4303 /* Update the BW information */
4304 ret = i40e_veb_get_bw_info(veb);
4305 if (ret) {
4306 dev_info(&pf->pdev->dev,
4307 "Failed getting veb bw config, aq_err=%d\n",
4308 pf->hw.aq.asq_last_status);
4309 }
4310
4311out:
4312 return ret;
4313}
4314
4315#ifdef CONFIG_I40E_DCB
4316/**
4317 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4318 * @pf: PF struct
4319 *
4320 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4321 * the caller would've quiesce all the VSIs before calling
4322 * this function
4323 **/
4324static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4325{
4326 u8 tc_map = 0;
4327 int ret;
4328 u8 v;
4329
4330 /* Enable the TCs available on PF to all VEBs */
4331 tc_map = i40e_pf_get_tc_map(pf);
4332 for (v = 0; v < I40E_MAX_VEB; v++) {
4333 if (!pf->veb[v])
4334 continue;
4335 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4336 if (ret) {
4337 dev_info(&pf->pdev->dev,
4338 "Failed configuring TC for VEB seid=%d\n",
4339 pf->veb[v]->seid);
4340 /* Will try to configure as many components */
4341 }
4342 }
4343
4344 /* Update each VSI */
505682cd 4345 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4346 if (!pf->vsi[v])
4347 continue;
4348
4349 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4350#ifdef I40E_FCOE
4351 * - For FCoE VSI only enable the TC configured
4352 * as per the APP TLV
4353#endif
4e3b35b0
NP		 4354 * - For all others keep them at TC0 for now
4355 */
4356 if (v == pf->lan_vsi)
4357 tc_map = i40e_pf_get_tc_map(pf);
4358 else
4359 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4360#ifdef I40E_FCOE
4361 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4362 tc_map = i40e_get_fcoe_tc_map(pf);
4363#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4364
4365 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4366 if (ret) {
4367 dev_info(&pf->pdev->dev,
4368 "Failed configuring TC for VSI seid=%d\n",
4369 pf->vsi[v]->seid);
4370 /* Will try to configure as many components */
4371 } else {
0672a091
NP		 4372 /* Re-configure VSI vectors based on updated TC map */
4373 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4374 if (pf->vsi[v]->netdev)
4375 i40e_dcbnl_set_all(pf->vsi[v]);
4376 }
4377 }
4378}
4379
4380/**
4381 * i40e_init_pf_dcb - Initialize DCB configuration
4382 * @pf: PF being configured
4383 *
4384 * Query the current DCB configuration and cache it
4385 * in the hardware structure
4386 **/
4387static int i40e_init_pf_dcb(struct i40e_pf *pf)
4388{
4389 struct i40e_hw *hw = &pf->hw;
4390 int err = 0;
4391
4392 if (pf->hw.func_caps.npar_enable)
4393 goto out;
4394
4395 /* Get the initial DCB configuration */
4396 err = i40e_init_dcb(hw);
4397 if (!err) {
4398 /* Device/Function is not DCBX capable */
4399 if ((!hw->func_caps.dcb) ||
4400 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4401 dev_info(&pf->pdev->dev,
4402 "DCBX offload is not supported or is disabled for this PF.\n");
4403
4404 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4405 goto out;
4406
4407 } else {
4408 /* When status is not DISABLED then DCBX in FW */
4409 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4410 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4411
4412 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4413 /* Enable DCB tagging only when more than one TC */
4414 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4415 pf->flags |= I40E_FLAG_DCB_ENABLED;
4e3b35b0 4416 }
014269ff
NP		 4417 } else {
4418 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4419 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4420 }
4421
4422out:
4423 return err;
4424}
4425#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4426#define SPEED_SIZE 14
4427#define FC_SIZE 8
4428/**
4429 * i40e_print_link_message - print link up or down
4430 * @vsi: the VSI for which link needs a message
4431 */
4432static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4433{
4434 char speed[SPEED_SIZE] = "Unknown";
4435 char fc[FC_SIZE] = "RX/TX";
4436
4437 if (!isup) {
4438 netdev_info(vsi->netdev, "NIC Link is Down\n");
4439 return;
4440 }
4441
4442 switch (vsi->back->hw.phy.link_info.link_speed) {
4443 case I40E_LINK_SPEED_40GB:
35a7d804 4444 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4445 break;
4446 case I40E_LINK_SPEED_10GB:
35a7d804 4447 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4448 break;
4449 case I40E_LINK_SPEED_1GB:
35a7d804 4450 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4451 break;
5960d33f
MW		 4452 case I40E_LINK_SPEED_100MB:
4453 strncpy(speed, "100 Mbps", SPEED_SIZE);
4454 break;
cf05ed08
JB		 4455 default:
4456 break;
4457 }
4458
4459 switch (vsi->back->hw.fc.current_mode) {
4460 case I40E_FC_FULL:
35a7d804 4461 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4462 break;
4463 case I40E_FC_TX_PAUSE:
35a7d804 4464 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4465 break;
4466 case I40E_FC_RX_PAUSE:
35a7d804 4467 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4468 break;
4469 default:
35a7d804 4470 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4471 break;
4472 }
4473
4474 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4475 speed, fc);
4476}
4e3b35b0 4477
41c445ff
JB		 4478/**
4479 * i40e_up_complete - Finish the last steps of bringing up a connection
4480 * @vsi: the VSI being configured
4481 **/
4482static int i40e_up_complete(struct i40e_vsi *vsi)
4483{
4484 struct i40e_pf *pf = vsi->back;
4485 int err;
4486
4487 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4488 i40e_vsi_configure_msix(vsi);
4489 else
4490 i40e_configure_msi_and_legacy(vsi);
4491
4492 /* start rings */
4493 err = i40e_vsi_control_rings(vsi, true);
4494 if (err)
4495 return err;
4496
4497 clear_bit(__I40E_DOWN, &vsi->state);
4498 i40e_napi_enable_all(vsi);
4499 i40e_vsi_enable_irq(vsi);
4500
4501 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4502 (vsi->netdev)) {
cf05ed08 4503 i40e_print_link_message(vsi, true);
41c445ff
JB		 4504 netif_tx_start_all_queues(vsi->netdev);
4505 netif_carrier_on(vsi->netdev);
6d779b41 4506 } else if (vsi->netdev) {
cf05ed08 4507 i40e_print_link_message(vsi, false);
7b592f61
CW		 4508 /* need to check for qualified module here*/
4509 if ((pf->hw.phy.link_info.link_info &
4510 I40E_AQ_MEDIA_AVAILABLE) &&
4511 (!(pf->hw.phy.link_info.an_info &
4512 I40E_AQ_QUALIFIED_MODULE)))
4513 netdev_err(vsi->netdev,
4514 "the driver failed to link because an unqualified module was detected.");
41c445ff 4515 }
ca64fa4e
ASJ		 4516
4517 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4518 if (vsi->type == I40E_VSI_FDIR) {
4519 /* reset fd counters */
4520 pf->fd_add_err = pf->fd_atr_cnt = 0;
4521 if (pf->fd_tcp_rule > 0) {
4522 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4523 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4524 pf->fd_tcp_rule = 0;
4525 }
ca64fa4e 4526 i40e_fdir_filter_restore(vsi);
1e1be8f6 4527 }
41c445ff
JB		 4528 i40e_service_event_schedule(pf);
4529
4530 return 0;
4531}
4532
4533/**
4534 * i40e_vsi_reinit_locked - Reset the VSI
4535 * @vsi: the VSI being configured
4536 *
4537 * Rebuild the ring structs after some configuration
4538 * has changed, e.g. MTU size.
4539 **/
4540static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4541{
4542 struct i40e_pf *pf = vsi->back;
4543
4544 WARN_ON(in_interrupt());
4545 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4546 usleep_range(1000, 2000);
4547 i40e_down(vsi);
4548
4549 /* Give a VF some time to respond to the reset. The
4550 * two second wait is based upon the watchdog cycle in
4551 * the VF driver.
4552 */
4553 if (vsi->type == I40E_VSI_SRIOV)
4554 msleep(2000);
4555 i40e_up(vsi);
4556 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4557}
4558
4559/**
4560 * i40e_up - Bring the connection back up after being down
4561 * @vsi: the VSI being configured
4562 **/
4563int i40e_up(struct i40e_vsi *vsi)
4564{
4565 int err;
4566
4567 err = i40e_vsi_configure(vsi);
4568 if (!err)
4569 err = i40e_up_complete(vsi);
4570
4571 return err;
4572}
4573
4574/**
4575 * i40e_down - Shutdown the connection processing
4576 * @vsi: the VSI being stopped
4577 **/
4578void i40e_down(struct i40e_vsi *vsi)
4579{
4580 int i;
4581
4582 /* It is assumed that the caller of this function
4583 * sets the vsi->state __I40E_DOWN bit.
4584 */
4585 if (vsi->netdev) {
4586 netif_carrier_off(vsi->netdev);
4587 netif_tx_disable(vsi->netdev);
4588 }
4589 i40e_vsi_disable_irq(vsi);
4590 i40e_vsi_control_rings(vsi, false);
4591 i40e_napi_disable_all(vsi);
4592
4593 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4594 i40e_clean_tx_ring(vsi->tx_rings[i]);
4595 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4596 }
4597}
4598
4599/**
4600 * i40e_setup_tc - configure multiple traffic classes
4601 * @netdev: net device to configure
4602 * @tc: number of traffic classes to enable
4603 **/
38e00438
VD		 4604#ifdef I40E_FCOE
4605int i40e_setup_tc(struct net_device *netdev, u8 tc)
4606#else
41c445ff 4607static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4608#endif
41c445ff
JB		 4609{
4610 struct i40e_netdev_priv *np = netdev_priv(netdev);
4611 struct i40e_vsi *vsi = np->vsi;
4612 struct i40e_pf *pf = vsi->back;
4613 u8 enabled_tc = 0;
4614 int ret = -EINVAL;
4615 int i;
4616
4617 /* Check if DCB enabled to continue */
4618 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4619 netdev_info(netdev, "DCB is not enabled for adapter\n");
4620 goto exit;
4621 }
4622
4623 /* Check if MFP enabled */
4624 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4625 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4626 goto exit;
4627 }
4628
4629 /* Check whether tc count is within enabled limit */
4630 if (tc > i40e_pf_get_num_tc(pf)) {
4631 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4632 goto exit;
4633 }
4634
4635 /* Generate TC map for number of tc requested */
4636 for (i = 0; i < tc; i++)
4637 enabled_tc |= (1 << i);
4638
4639 /* Requesting same TC configuration as already enabled */
4640 if (enabled_tc == vsi->tc_config.enabled_tc)
4641 return 0;
4642
4643 /* Quiesce VSI queues */
4644 i40e_quiesce_vsi(vsi);
4645
4646 /* Configure VSI for enabled TCs */
4647 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4648 if (ret) {
4649 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4650 vsi->seid);
4651 goto exit;
4652 }
4653
4654 /* Unquiesce VSI */
4655 i40e_unquiesce_vsi(vsi);
4656
4657exit:
4658 return ret;
4659}
4660
4661/**
4662 * i40e_open - Called when a network interface is made active
4663 * @netdev: network interface device structure
4664 *
4665 * The open entry point is called when a network interface is made
4666 * active by the system (IFF_UP). At this point all resources needed
4667 * for transmit and receive operations are allocated, the interrupt
4668 * handler is registered with the OS, the netdev watchdog subtask is
4669 * enabled, and the stack is notified that the interface is ready.
4670 *
4671 * Returns 0 on success, negative value on failure
4672 **/
38e00438
VD		 4673#ifdef I40E_FCOE
4674int i40e_open(struct net_device *netdev)
4675#else
41c445ff 4676static int i40e_open(struct net_device *netdev)
38e00438 4677#endif
41c445ff
JB		 4678{
4679 struct i40e_netdev_priv *np = netdev_priv(netdev);
4680 struct i40e_vsi *vsi = np->vsi;
4681 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4682 int err;
4683
4eb3f768
SN		 4684 /* disallow open during test or if eeprom is broken */
4685 if (test_bit(__I40E_TESTING, &pf->state) ||
4686 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4687 return -EBUSY;
4688
4689 netif_carrier_off(netdev);
4690
6c167f58
EK		 4691 err = i40e_vsi_open(vsi);
4692 if (err)
4693 return err;
4694
059dab69
JB		 4695 /* configure global TSO hardware offload settings */
4696 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4697 TCP_FLAG_FIN) >> 16);
4698 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4699 TCP_FLAG_FIN |
4700 TCP_FLAG_CWR) >> 16);
4701 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4702
6c167f58
EK		 4703#ifdef CONFIG_I40E_VXLAN
4704 vxlan_get_rx_port(netdev);
4705#endif
4706
4707 return 0;
4708}
4709
4710/**
4711 * i40e_vsi_open -
4712 * @vsi: the VSI to open
4713 *
4714 * Finish initialization of the VSI.
4715 *
4716 * Returns 0 on success, negative value on failure
4717 **/
4718int i40e_vsi_open(struct i40e_vsi *vsi)
4719{
4720 struct i40e_pf *pf = vsi->back;
4721 char int_name[IFNAMSIZ];
4722 int err;
4723
41c445ff
JB		 4724 /* allocate descriptors */
4725 err = i40e_vsi_setup_tx_resources(vsi);
4726 if (err)
4727 goto err_setup_tx;
4728 err = i40e_vsi_setup_rx_resources(vsi);
4729 if (err)
4730 goto err_setup_rx;
4731
4732 err = i40e_vsi_configure(vsi);
4733 if (err)
4734 goto err_setup_rx;
4735
c22e3c6c
SN		 4736 if (vsi->netdev) {
4737 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4738 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4739 err = i40e_vsi_request_irq(vsi, int_name);
4740 if (err)
4741 goto err_setup_rx;
41c445ff 4742
c22e3c6c
SN		 4743 /* Notify the stack of the actual queue counts. */
4744 err = netif_set_real_num_tx_queues(vsi->netdev,
4745 vsi->num_queue_pairs);
4746 if (err)
4747 goto err_set_queues;
25946ddb 4748
c22e3c6c
SN		 4749 err = netif_set_real_num_rx_queues(vsi->netdev,
4750 vsi->num_queue_pairs);
4751 if (err)
4752 goto err_set_queues;
8a9eb7d3
SN		 4753
4754 } else if (vsi->type == I40E_VSI_FDIR) {
4755 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4756 dev_driver_string(&pf->pdev->dev));
4757 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4758 } else {
ce9ccb17 4759 err = -EINVAL;
6c167f58
EK		 4760 goto err_setup_rx;
4761 }
25946ddb 4762
41c445ff
JB		 4763 err = i40e_up_complete(vsi);
4764 if (err)
4765 goto err_up_complete;
4766
41c445ff
JB		 4767 return 0;
4768
4769err_up_complete:
4770 i40e_down(vsi);
25946ddb 4771err_set_queues:
41c445ff
JB		 4772 i40e_vsi_free_irq(vsi);
4773err_setup_rx:
4774 i40e_vsi_free_rx_resources(vsi);
4775err_setup_tx:
4776 i40e_vsi_free_tx_resources(vsi);
4777 if (vsi == pf->vsi[pf->lan_vsi])
4778 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4779
4780 return err;
4781}
4782
17a73f6b
JG		 4783/**
4784 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4785 * @pf: Pointer to pf
4786 *
4787 * This function destroys the hlist where all the Flow Director
4788 * filters were saved.
4789 **/
4790static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4791{
4792 struct i40e_fdir_filter *filter;
4793 struct hlist_node *node2;
4794
4795 hlist_for_each_entry_safe(filter, node2,
4796 &pf->fdir_filter_list, fdir_node) {
4797 hlist_del(&filter->fdir_node);
4798 kfree(filter);
4799 }
4800 pf->fdir_pf_active_filters = 0;
4801}
4802
41c445ff
JB		 4803/**
4804 * i40e_close - Disables a network interface
4805 * @netdev: network interface device structure
4806 *
4807 * The close entry point is called when an interface is de-activated
4808 * by the OS. The hardware is still under the driver's control, but
4809 * this netdev interface is disabled.
4810 *
4811 * Returns 0, this is not allowed to fail
4812 **/
38e00438
VD		 4813#ifdef I40E_FCOE
4814int i40e_close(struct net_device *netdev)
4815#else
41c445ff 4816static int i40e_close(struct net_device *netdev)
38e00438 4817#endif
41c445ff
JB		 4818{
4819 struct i40e_netdev_priv *np = netdev_priv(netdev);
4820 struct i40e_vsi *vsi = np->vsi;
4821
90ef8d47 4822 i40e_vsi_close(vsi);
41c445ff
JB		 4823
4824 return 0;
4825}
4826
4827/**
4828 * i40e_do_reset - Start a PF or Core Reset sequence
4829 * @pf: board private structure
4830 * @reset_flags: which reset is requested
4831 *
4832 * The essential difference in resets is that the PF Reset
4833 * doesn't clear the packet buffers, doesn't reset the PE
4834 * firmware, and doesn't bother the other PFs on the chip.
4835 **/
4836void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4837{
4838 u32 val;
4839
4840 WARN_ON(in_interrupt());
4841
263fc48f
MW		 4842 if (i40e_check_asq_alive(&pf->hw))
4843 i40e_vc_notify_reset(pf);
4844
41c445ff
JB		 4845 /* do the biggest reset indicated */
4846 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4847
4848 /* Request a Global Reset
4849 *
4850 * This will start the chip's countdown to the actual full
4851 * chip reset event, and a warning interrupt to be sent
4852 * to all PFs, including the requestor. Our handler
4853 * for the warning interrupt will deal with the shutdown
4854 * and recovery of the switch setup.
4855 */
69bfb110 4856 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4857 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4858 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4859 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4860
4861 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4862
4863 /* Request a Core Reset
4864 *
4865 * Same as Global Reset, except does *not* include the MAC/PHY
4866 */
69bfb110 4867 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4868 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4869 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4870 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4871 i40e_flush(&pf->hw);
4872
7823fe34
SN		 4873 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4874
4875 /* Request a Firmware Reset
4876 *
4877 * Same as Global reset, plus restarting the
4878 * embedded firmware engine.
4879 */
4880 /* enable EMP Reset */
4881 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4882 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4883 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4884
4885 /* force the reset */
4886 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4887 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4888 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4889 i40e_flush(&pf->hw);
4890
41c445ff
JB		 4891 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4892
4893 /* Request a PF Reset
4894 *
4895 * Resets only the PF-specific registers
4896 *
4897 * This goes directly to the tear-down and rebuild of
4898 * the switch, since we need to do all the recovery as
4899 * for the Core Reset.
4900 */
69bfb110 4901 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4902 i40e_handle_reset_warning(pf);
4903
4904 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4905 int v;
4906
4907 /* Find the VSI(s) that requested a re-init */
4908 dev_info(&pf->pdev->dev,
4909 "VSI reinit requested\n");
505682cd 4910 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4911 struct i40e_vsi *vsi = pf->vsi[v];
4912 if (vsi != NULL &&
4913 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4914 i40e_vsi_reinit_locked(pf->vsi[v]);
4915 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4916 }
4917 }
4918
b5d06f05
NP		 4919 /* no further action needed, so return now */
4920 return;
4921 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4922 int v;
4923
4924 /* Find the VSI(s) that needs to be brought down */
4925 dev_info(&pf->pdev->dev, "VSI down requested\n");
4926 for (v = 0; v < pf->num_alloc_vsi; v++) {
4927 struct i40e_vsi *vsi = pf->vsi[v];
4928 if (vsi != NULL &&
4929 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4930 set_bit(__I40E_DOWN, &vsi->state);
4931 i40e_down(vsi);
4932 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4933 }
4934 }
4935
41c445ff
JB		 4936 /* no further action needed, so return now */
4937 return;
4938 } else {
4939 dev_info(&pf->pdev->dev,
4940 "bad reset request 0x%08x\n", reset_flags);
4941 return;
4942 }
4943}
4944
4e3b35b0
NP		 4945#ifdef CONFIG_I40E_DCB
4946/**
4947 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4948 * @pf: board private structure
4949 * @old_cfg: current DCB config
4950 * @new_cfg: new DCB config
4951 **/
4952bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4953 struct i40e_dcbx_config *old_cfg,
4954 struct i40e_dcbx_config *new_cfg)
4955{
4956 bool need_reconfig = false;
4957
4958 /* Check if ETS configuration has changed */
4959 if (memcmp(&new_cfg->etscfg,
4960 &old_cfg->etscfg,
4961 sizeof(new_cfg->etscfg))) {
4962 /* If Priority Table has changed reconfig is needed */
4963 if (memcmp(&new_cfg->etscfg.prioritytable,
4964 &old_cfg->etscfg.prioritytable,
4965 sizeof(new_cfg->etscfg.prioritytable))) {
4966 need_reconfig = true;
69bfb110 4967 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4968 }
4969
4970 if (memcmp(&new_cfg->etscfg.tcbwtable,
4971 &old_cfg->etscfg.tcbwtable,
4972 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4973 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4974
4975 if (memcmp(&new_cfg->etscfg.tsatable,
4976 &old_cfg->etscfg.tsatable,
4977 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4978 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4979 }
4980
4981 /* Check if PFC configuration has changed */
4982 if (memcmp(&new_cfg->pfc,
4983 &old_cfg->pfc,
4984 sizeof(new_cfg->pfc))) {
4985 need_reconfig = true;
69bfb110 4986 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4987 }
4988
4989 /* Check if APP Table has changed */
4990 if (memcmp(&new_cfg->app,
4991 &old_cfg->app,
3d9667a9 4992 sizeof(new_cfg->app))) {
4e3b35b0 4993 need_reconfig = true;
69bfb110 4994 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4995 }
4e3b35b0
NP		 4996
4997 return need_reconfig;
4998}
4999
5000/**
5001 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5002 * @pf: board private structure
5003 * @e: event info posted on ARQ
5004 **/
5005static int i40e_handle_lldp_event(struct i40e_pf *pf,
5006 struct i40e_arq_event_info *e)
5007{
5008 struct i40e_aqc_lldp_get_mib *mib =
5009 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5010 struct i40e_hw *hw = &pf->hw;
5011 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
5012 struct i40e_dcbx_config tmp_dcbx_cfg;
5013 bool need_reconfig = false;
5014 int ret = 0;
5015 u8 type;
5016
4d9b6043
NP		 5017 /* Not DCB capable or capability disabled */
5018 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5019 return ret;
5020
4e3b35b0
NP		 5021 /* Ignore if event is not for Nearest Bridge */
5022 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5023 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
5024 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5025 return ret;
5026
5027 /* Check MIB Type and return if event for Remote MIB update */
5028 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
5029 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5030 /* Update the remote cached instance and return */
5031 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5032 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5033 &hw->remote_dcbx_config);
5034 goto exit;
5035 }
5036
5037 /* Convert/store the DCBX data from LLDPDU temporarily */
5038 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
5039 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
5040 if (ret) {
5041 /* Error in LLDPDU parsing return */
5042 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
5043 goto exit;
5044 }
5045
5046 /* No change detected in DCBX configs */
5047 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5048 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5049 goto exit;
5050 }
5051
5052 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
5053
5054 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
5055
5056 /* Overwrite the new configuration */
5057 *dcbx_cfg = tmp_dcbx_cfg;
5058
5059 if (!need_reconfig)
5060 goto exit;
5061
4d9b6043
NP		 5062 /* Enable DCB tagging only when more than one TC */
5063 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5064 pf->flags |= I40E_FLAG_DCB_ENABLED;
5065 else
5066 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5067
4e3b35b0
NP		 5068 /* Reconfiguration needed quiesce all VSIs */
5069 i40e_pf_quiesce_all_vsi(pf);
5070
5071 /* Changes in configuration update VEB/VSI */
5072 i40e_dcb_reconfigure(pf);
5073
5074 i40e_pf_unquiesce_all_vsi(pf);
5075exit:
5076 return ret;
5077}
5078#endif /* CONFIG_I40E_DCB */
5079
23326186
ASJ		 5080/**
5081 * i40e_do_reset_safe - Protected reset path for userland calls.
5082 * @pf: board private structure
5083 * @reset_flags: which reset is requested
5084 *
5085 **/
5086void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5087{
5088 rtnl_lock();
5089 i40e_do_reset(pf, reset_flags);
5090 rtnl_unlock();
5091}
5092
41c445ff
JB		 5093/**
5094 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5095 * @pf: board private structure
5096 * @e: event info posted on ARQ
5097 *
5098 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5099 * and VF queues
5100 **/
5101static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5102 struct i40e_arq_event_info *e)
5103{
5104 struct i40e_aqc_lan_overflow *data =
5105 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5106 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5107 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5108 struct i40e_hw *hw = &pf->hw;
5109 struct i40e_vf *vf;
5110 u16 vf_id;
5111
69bfb110
JB		 5112 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5113 queue, qtx_ctl);
41c445ff
JB		 5114
5115 /* Queue belongs to VF, find the VF and issue VF reset */
5116 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5117 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5118 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5119 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5120 vf_id -= hw->func_caps.vf_base_id;
5121 vf = &pf->vf[vf_id];
5122 i40e_vc_notify_vf_reset(vf);
5123 /* Allow VF to process pending reset notification */
5124 msleep(20);
5125 i40e_reset_vf(vf, false);
5126 }
5127}
5128
5129/**
5130 * i40e_service_event_complete - Finish up the service event
5131 * @pf: board private structure
5132 **/
5133static void i40e_service_event_complete(struct i40e_pf *pf)
5134{
5135 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5136
5137 /* flush memory to make sure state is correct before next watchog */
4e857c58 5138 smp_mb__before_atomic();
41c445ff
JB		 5139 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5140}
5141
55a5e60b 5142/**
12957388
ASJ		 5143 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5144 * @pf: board private structure
5145 **/
5146int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5147{
5148 int val, fcnt_prog;
5149
5150 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5151 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5152 return fcnt_prog;
5153}
5154
5155/**
5156 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5157 * @pf: board private structure
5158 **/
5159int i40e_get_current_fd_count(struct i40e_pf *pf)
5160{
5161 int val, fcnt_prog;
5162 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5163 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5164 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5165 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5166 return fcnt_prog;
5167}
1e1be8f6 5168
55a5e60b
ASJ		 5169/**
5170 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5171 * @pf: board private structure
5172 **/
5173void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5174{
5175 u32 fcnt_prog, fcnt_avail;
5176
1e1be8f6
ASJ		 5177 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5178 return;
5179
55a5e60b
ASJ		 5180 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5181 * to re-enable
5182 */
12957388
ASJ		 5183 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5184 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5185 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5186 (pf->fd_add_err == 0) ||
5187 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5188 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5189 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5190 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5191 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5192 }
5193 }
5194 /* Wait for some more space to be available to turn on ATR */
5195 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5196 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5197 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5198 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5199 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5200 }
5201 }
5202}
5203
1e1be8f6
ASJ		 5204#define I40E_MIN_FD_FLUSH_INTERVAL 10
5205/**
5206 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5207 * @pf: board private structure
5208 **/
5209static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5210{
5211 int flush_wait_retry = 50;
5212 int reg;
5213
1790ed0c
AA		 5214 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5215 return;
5216
1e1be8f6
ASJ		 5217 if (time_after(jiffies, pf->fd_flush_timestamp +
5218 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5219 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5220 pf->fd_flush_timestamp = jiffies;
5221 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5222 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5223 /* flush all filters */
5224 wr32(&pf->hw, I40E_PFQF_CTL_1,
5225 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5226 i40e_flush(&pf->hw);
60793f4a 5227 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5228 pf->fd_add_err = 0;
5229 do {
5230 /* Check FD flush status every 5-6msec */
5231 usleep_range(5000, 6000);
5232 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5233 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5234 break;
5235 } while (flush_wait_retry--);
5236 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5237 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5238 } else {
5239 /* replay sideband filters */
5240 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5241
5242 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5243 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5244 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5245 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5246 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5247 }
5248 }
5249}
5250
5251/**
5252 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5253 * @pf: board private structure
5254 **/
5255int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5256{
5257 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5258}
5259
5260/* We can see up to 256 filter programming desc in transit if the filters are
5261 * being applied really fast; before we see the first
5262 * filter miss error on Rx queue 0. Accumulating enough error messages before
5263 * reacting will make sure we don't cause flush too often.
5264 */
5265#define I40E_MAX_FD_PROGRAM_ERROR 256
5266
41c445ff
JB		 5267/**
5268 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5269 * @pf: board private structure
5270 **/
5271static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5272{
41c445ff 5273
41c445ff
JB		 5274 /* if interface is down do nothing */
5275 if (test_bit(__I40E_DOWN, &pf->state))
5276 return;
1e1be8f6 5277
1790ed0c
AA		 5278 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5279 return;
5280
1e1be8f6
ASJ		 5281 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5282 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5283 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5284 i40e_fdir_flush_and_replay(pf);
5285
55a5e60b
ASJ		 5286 i40e_fdir_check_and_reenable(pf);
5287
41c445ff
JB		 5288}
5289
5290/**
5291 * i40e_vsi_link_event - notify VSI of a link event
5292 * @vsi: vsi to be notified
5293 * @link_up: link up or down
5294 **/
5295static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5296{
32b5b811 5297 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5298 return;
5299
5300 switch (vsi->type) {
5301 case I40E_VSI_MAIN:
38e00438
VD		 5302#ifdef I40E_FCOE
5303 case I40E_VSI_FCOE:
5304#endif
41c445ff
JB		 5305 if (!vsi->netdev || !vsi->netdev_registered)
5306 break;
5307
5308 if (link_up) {
5309 netif_carrier_on(vsi->netdev);
5310 netif_tx_wake_all_queues(vsi->netdev);
5311 } else {
5312 netif_carrier_off(vsi->netdev);
5313 netif_tx_stop_all_queues(vsi->netdev);
5314 }
5315 break;
5316
5317 case I40E_VSI_SRIOV:
5318 break;
5319
5320 case I40E_VSI_VMDQ2:
5321 case I40E_VSI_CTRL:
5322 case I40E_VSI_MIRROR:
5323 default:
5324 /* there is no notification for other VSIs */
5325 break;
5326 }
5327}
5328
5329/**
5330 * i40e_veb_link_event - notify elements on the veb of a link event
5331 * @veb: veb to be notified
5332 * @link_up: link up or down
5333 **/
5334static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5335{
5336 struct i40e_pf *pf;
5337 int i;
5338
5339 if (!veb || !veb->pf)
5340 return;
5341 pf = veb->pf;
5342
5343 /* depth first... */
5344 for (i = 0; i < I40E_MAX_VEB; i++)
5345 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5346 i40e_veb_link_event(pf->veb[i], link_up);
5347
5348 /* ... now the local VSIs */
505682cd 5349 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5350 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5351 i40e_vsi_link_event(pf->vsi[i], link_up);
5352}
5353
5354/**
5355 * i40e_link_event - Update netif_carrier status
5356 * @pf: board private structure
5357 **/
5358static void i40e_link_event(struct i40e_pf *pf)
5359{
5360 bool new_link, old_link;
320684cd 5361 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
41c445ff 5362
1e701e09
JB		 5363 /* set this to force the get_link_status call to refresh state */
5364 pf->hw.phy.get_link_info = true;
5365
41c445ff 5366 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5367 new_link = i40e_get_link_status(&pf->hw);
41c445ff 5368
1e701e09 5369 if (new_link == old_link &&
320684cd
MW		 5370 (test_bit(__I40E_DOWN, &vsi->state) ||
5371 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5372 return;
320684cd
MW		 5373
5374 if (!test_bit(__I40E_DOWN, &vsi->state))
5375 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5376
5377 /* Notify the base of the switch tree connected to
5378 * the link. Floating VEBs are not notified.
5379 */
5380 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5381 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5382 else
320684cd 5383 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5384
5385 if (pf->vf)
5386 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5387
5388 if (pf->flags & I40E_FLAG_PTP)
5389 i40e_ptp_set_increment(pf);
41c445ff
JB		 5390}
5391
5392/**
5393 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5394 * @pf: board private structure
5395 *
5396 * Set the per-queue flags to request a check for stuck queues in the irq
5397 * clean functions, then force interrupts to be sure the irq clean is called.
5398 **/
5399static void i40e_check_hang_subtask(struct i40e_pf *pf)
5400{
5401 int i, v;
5402
5403 /* If we're down or resetting, just bail */
5404 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5405 return;
5406
5407 /* for each VSI/netdev
5408 * for each Tx queue
5409 * set the check flag
5410 * for each q_vector
5411 * force an interrupt
5412 */
505682cd 5413 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5414 struct i40e_vsi *vsi = pf->vsi[v];
5415 int armed = 0;
5416
5417 if (!pf->vsi[v] ||
5418 test_bit(__I40E_DOWN, &vsi->state) ||
5419 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5420 continue;
5421
5422 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5423 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5424 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5425 &vsi->tx_rings[i]->state))
41c445ff
JB		 5426 armed++;
5427 }
5428
5429 if (armed) {
5430 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5431 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5432 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5433 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5434 } else {
5435 u16 vec = vsi->base_vector - 1;
5436 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5437 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5438 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5439 wr32(&vsi->back->hw,
5440 I40E_PFINT_DYN_CTLN(vec), val);
5441 }
5442 i40e_flush(&vsi->back->hw);
5443 }
5444 }
5445}
5446
5447/**
5448 * i40e_watchdog_subtask - Check and bring link up
5449 * @pf: board private structure
5450 **/
5451static void i40e_watchdog_subtask(struct i40e_pf *pf)
5452{
5453 int i;
5454
5455 /* if interface is down do nothing */
5456 if (test_bit(__I40E_DOWN, &pf->state) ||
5457 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5458 return;
5459
5460 /* Update the stats for active netdevs so the network stack
5461 * can look at updated numbers whenever it cares to
5462 */
505682cd 5463 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5464 if (pf->vsi[i] && pf->vsi[i]->netdev)
5465 i40e_update_stats(pf->vsi[i]);
5466
5467 /* Update the stats for the active switching components */
5468 for (i = 0; i < I40E_MAX_VEB; i++)
5469 if (pf->veb[i])
5470 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5471
5472 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5473}
5474
5475/**
5476 * i40e_reset_subtask - Set up for resetting the device and driver
5477 * @pf: board private structure
5478 **/
5479static void i40e_reset_subtask(struct i40e_pf *pf)
5480{
5481 u32 reset_flags = 0;
5482
23326186 5483 rtnl_lock();
41c445ff
JB		 5484 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5485 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5486 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5487 }
5488 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5489 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5490 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5491 }
5492 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5493 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5494 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5495 }
5496 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5497 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5498 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5499 }
b5d06f05
NP		 5500 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5501 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5502 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5503 }
41c445ff
JB		 5504
5505 /* If there's a recovery already waiting, it takes
5506 * precedence before starting a new reset sequence.
5507 */
5508 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5509 i40e_handle_reset_warning(pf);
23326186 5510 goto unlock;
41c445ff
JB		 5511 }
5512
5513 /* If we're already down or resetting, just bail */
5514 if (reset_flags &&
5515 !test_bit(__I40E_DOWN, &pf->state) &&
5516 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5517 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5518
5519unlock:
5520 rtnl_unlock();
41c445ff
JB		 5521}
5522
5523/**
5524 * i40e_handle_link_event - Handle link event
5525 * @pf: board private structure
5526 * @e: event info posted on ARQ
5527 **/
5528static void i40e_handle_link_event(struct i40e_pf *pf,
5529 struct i40e_arq_event_info *e)
5530{
5531 struct i40e_hw *hw = &pf->hw;
5532 struct i40e_aqc_get_link_status *status =
5533 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5534 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5535
5536 /* save off old link status information */
5537 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5538 sizeof(pf->hw.phy.link_info_old));
5539
1e701e09
JB		 5540 /* Do a new status request to re-enable LSE reporting
5541 * and load new status information into the hw struct
5542 * This completely ignores any state information
5543 * in the ARQ event info, instead choosing to always
5544 * issue the AQ update link status command.
5545 */
5546 i40e_link_event(pf);
5547
7b592f61
CW		 5548 /* check for unqualified module, if link is down */
5549 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5550 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5551 (!(status->link_info & I40E_AQ_LINK_UP)))
5552 dev_err(&pf->pdev->dev,
5553 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5554}
5555
5556/**
5557 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5558 * @pf: board private structure
5559 **/
5560static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5561{
5562 struct i40e_arq_event_info event;
5563 struct i40e_hw *hw = &pf->hw;
5564 u16 pending, i = 0;
5565 i40e_status ret;
5566 u16 opcode;
86df242b 5567 u32 oldval;
41c445ff
JB		 5568 u32 val;
5569
a316f651
ASJ		 5570 /* Do not run clean AQ when PF reset fails */
5571 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5572 return;
5573
86df242b
SN		 5574 /* check for error indications */
5575 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5576 oldval = val;
5577 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5578 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5579 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5580 }
5581 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5582 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5583 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5584 }
5585 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5586 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5587 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5588 }
5589 if (oldval != val)
5590 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5591
5592 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5593 oldval = val;
5594 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5595 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5596 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5597 }
5598 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5599 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5600 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5601 }
5602 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5603 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5604 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5605 }
5606 if (oldval != val)
5607 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5608
3197ce22 5609 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5610 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5611 if (!event.msg_buf)
5612 return;
5613
5614 do {
2f019123 5615 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff 5616 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5617 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5618 break;
56497978 5619 else if (ret) {
41c445ff
JB		 5620 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5621 break;
5622 }
5623
5624 opcode = le16_to_cpu(event.desc.opcode);
5625 switch (opcode) {
5626
5627 case i40e_aqc_opc_get_link_status:
5628 i40e_handle_link_event(pf, &event);
5629 break;
5630 case i40e_aqc_opc_send_msg_to_pf:
5631 ret = i40e_vc_process_vf_msg(pf,
5632 le16_to_cpu(event.desc.retval),
5633 le32_to_cpu(event.desc.cookie_high),
5634 le32_to_cpu(event.desc.cookie_low),
5635 event.msg_buf,
5636 event.msg_size);
5637 break;
5638 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5639 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5640#ifdef CONFIG_I40E_DCB
5641 rtnl_lock();
5642 ret = i40e_handle_lldp_event(pf, &event);
5643 rtnl_unlock();
5644#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5645 break;
5646 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5647 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5648 i40e_handle_lan_overflow_event(pf, &event);
5649 break;
0467bc91
SN		 5650 case i40e_aqc_opc_send_msg_to_peer:
5651 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5652 break;
41c445ff
JB		 5653 default:
5654 dev_info(&pf->pdev->dev,
0467bc91
SN		 5655 "ARQ Error: Unknown event 0x%04x received\n",
5656 opcode);
41c445ff
JB		 5657 break;
5658 }
5659 } while (pending && (i++ < pf->adminq_work_limit));
5660
5661 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5662 /* re-enable Admin queue interrupt cause */
5663 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5664 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5665 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5666 i40e_flush(hw);
5667
5668 kfree(event.msg_buf);
5669}
5670
4eb3f768
SN		 5671/**
5672 * i40e_verify_eeprom - make sure eeprom is good to use
5673 * @pf: board private structure
5674 **/
5675static void i40e_verify_eeprom(struct i40e_pf *pf)
5676{
5677 int err;
5678
5679 err = i40e_diag_eeprom_test(&pf->hw);
5680 if (err) {
5681 /* retry in case of garbage read */
5682 err = i40e_diag_eeprom_test(&pf->hw);
5683 if (err) {
5684 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5685 err);
5686 set_bit(__I40E_BAD_EEPROM, &pf->state);
5687 }
5688 }
5689
5690 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5691 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5692 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5693 }
5694}
5695
41c445ff
JB		 5696/**
5697 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5698 * @veb: pointer to the VEB instance
5699 *
5700 * This is a recursive function that first builds the attached VSIs then
5701 * recurses in to build the next layer of VEB. We track the connections
5702 * through our own index numbers because the seid's from the HW could
5703 * change across the reset.
5704 **/
5705static int i40e_reconstitute_veb(struct i40e_veb *veb)
5706{
5707 struct i40e_vsi *ctl_vsi = NULL;
5708 struct i40e_pf *pf = veb->pf;
5709 int v, veb_idx;
5710 int ret;
5711
5712 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5713 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5714 if (pf->vsi[v] &&
5715 pf->vsi[v]->veb_idx == veb->idx &&
5716 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5717 ctl_vsi = pf->vsi[v];
5718 break;
5719 }
5720 }
5721 if (!ctl_vsi) {
5722 dev_info(&pf->pdev->dev,
5723 "missing owner VSI for veb_idx %d\n", veb->idx);
5724 ret = -ENOENT;
5725 goto end_reconstitute;
5726 }
5727 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5728 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5729 ret = i40e_add_vsi(ctl_vsi);
5730 if (ret) {
5731 dev_info(&pf->pdev->dev,
5732 "rebuild of owner VSI failed: %d\n", ret);
5733 goto end_reconstitute;
5734 }
5735 i40e_vsi_reset_stats(ctl_vsi);
5736
5737 /* create the VEB in the switch and move the VSI onto the VEB */
5738 ret = i40e_add_veb(veb, ctl_vsi);
5739 if (ret)
5740 goto end_reconstitute;
5741
5742 /* create the remaining VSIs attached to this VEB */
505682cd 5743 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5744 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5745 continue;
5746
5747 if (pf->vsi[v]->veb_idx == veb->idx) {
5748 struct i40e_vsi *vsi = pf->vsi[v];
5749 vsi->uplink_seid = veb->seid;
5750 ret = i40e_add_vsi(vsi);
5751 if (ret) {
5752 dev_info(&pf->pdev->dev,
5753 "rebuild of vsi_idx %d failed: %d\n",
5754 v, ret);
5755 goto end_reconstitute;
5756 }
5757 i40e_vsi_reset_stats(vsi);
5758 }
5759 }
5760
5761 /* create any VEBs attached to this VEB - RECURSION */
5762 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5763 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5764 pf->veb[veb_idx]->uplink_seid = veb->seid;
5765 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5766 if (ret)
5767 break;
5768 }
5769 }
5770
5771end_reconstitute:
5772 return ret;
5773}
5774
5775/**
5776 * i40e_get_capabilities - get info about the HW
5777 * @pf: the PF struct
5778 **/
5779static int i40e_get_capabilities(struct i40e_pf *pf)
5780{
5781 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5782 u16 data_size;
5783 int buf_len;
5784 int err;
5785
5786 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5787 do {
5788 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5789 if (!cap_buf)
5790 return -ENOMEM;
5791
5792 /* this loads the data into the hw struct for us */
5793 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5794 &data_size,
5795 i40e_aqc_opc_list_func_capabilities,
5796 NULL);
5797 /* data loaded, buffer no longer needed */
5798 kfree(cap_buf);
5799
5800 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5801 /* retry with a larger buffer */
5802 buf_len = data_size;
5803 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5804 dev_info(&pf->pdev->dev,
5805 "capability discovery failed: aq=%d\n",
5806 pf->hw.aq.asq_last_status);
5807 return -ENODEV;
5808 }
5809 } while (err);
5810
ac71b7ba
ASJ		 5811 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5812 (pf->hw.aq.fw_maj_ver < 2)) {
5813 pf->hw.func_caps.num_msix_vectors++;
5814 pf->hw.func_caps.num_msix_vectors_vf++;
5815 }
5816
41c445ff
JB		 5817 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5818 dev_info(&pf->pdev->dev,
5819 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5820 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5821 pf->hw.func_caps.num_msix_vectors,
5822 pf->hw.func_caps.num_msix_vectors_vf,
5823 pf->hw.func_caps.fd_filters_guaranteed,
5824 pf->hw.func_caps.fd_filters_best_effort,
5825 pf->hw.func_caps.num_tx_qp,
5826 pf->hw.func_caps.num_vsis);
5827
7134f9ce
JB		 5828#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5829 + pf->hw.func_caps.num_vfs)
5830 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5831 dev_info(&pf->pdev->dev,
5832 "got num_vsis %d, setting num_vsis to %d\n",
5833 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5834 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5835 }
5836
41c445ff
JB		 5837 return 0;
5838}
5839
cbf61325
ASJ		 5840static int i40e_vsi_clear(struct i40e_vsi *vsi);
5841
41c445ff 5842/**
cbf61325 5843 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5844 * @pf: board private structure
5845 **/
cbf61325 5846static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5847{
5848 struct i40e_vsi *vsi;
8a9eb7d3 5849 int i;
41c445ff 5850
407e063c
JB		 5851 /* quick workaround for an NVM issue that leaves a critical register
5852 * uninitialized
5853 */
5854 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5855 static const u32 hkey[] = {
5856 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5857 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5858 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5859 0x95b3a76d};
5860
5861 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5862 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5863 }
5864
cbf61325 5865 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5866 return;
5867
cbf61325 5868 /* find existing VSI and see if it needs configuring */
41c445ff 5869 vsi = NULL;
505682cd 5870 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5871 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5872 vsi = pf->vsi[i];
cbf61325
ASJ		 5873 break;
5874 }
5875 }
5876
5877 /* create a new VSI if none exists */
41c445ff 5878 if (!vsi) {
cbf61325
ASJ		 5879 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5880 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5881 if (!vsi) {
5882 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5883 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5884 return;
41c445ff 5885 }
cbf61325 5886 }
41c445ff 5887
8a9eb7d3 5888 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5889}
5890
5891/**
5892 * i40e_fdir_teardown - release the Flow Director resources
5893 * @pf: board private structure
5894 **/
5895static void i40e_fdir_teardown(struct i40e_pf *pf)
5896{
5897 int i;
5898
17a73f6b 5899 i40e_fdir_filter_exit(pf);
505682cd 5900 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5901 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5902 i40e_vsi_release(pf->vsi[i]);
5903 break;
5904 }
5905 }
5906}
5907
5908/**
f650a38b 5909 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5910 * @pf: board private structure
5911 *
f650a38b
ASJ		 5912 * Close up the VFs and other things in prep for pf Reset.
5913 **/
23cfbe07 5914static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5915{
41c445ff 5916 struct i40e_hw *hw = &pf->hw;
60442dea 5917 i40e_status ret = 0;
41c445ff
JB		 5918 u32 v;
5919
5920 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5921 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 5922 return;
41c445ff 5923
69bfb110 5924 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5925
41c445ff
JB		 5926 /* quiesce the VSIs and their queues that are not already DOWN */
5927 i40e_pf_quiesce_all_vsi(pf);
5928
505682cd 5929 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5930 if (pf->vsi[v])
5931 pf->vsi[v]->seid = 0;
5932 }
5933
5934 i40e_shutdown_adminq(&pf->hw);
5935
f650a38b 5936 /* call shutdown HMC */
60442dea
SN		 5937 if (hw->hmc.hmc_obj) {
5938 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 5939 if (ret)
60442dea
SN		 5940 dev_warn(&pf->pdev->dev,
5941 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 5942 }
f650a38b
ASJ		 5943}
5944
44033fac
JB		 5945/**
5946 * i40e_send_version - update firmware with driver version
5947 * @pf: PF struct
5948 */
5949static void i40e_send_version(struct i40e_pf *pf)
5950{
5951 struct i40e_driver_version dv;
5952
5953 dv.major_version = DRV_VERSION_MAJOR;
5954 dv.minor_version = DRV_VERSION_MINOR;
5955 dv.build_version = DRV_VERSION_BUILD;
5956 dv.subbuild_version = 0;
35a7d804 5957 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 5958 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5959}
5960
f650a38b 5961/**
4dda12e6 5962 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5963 * @pf: board private structure
bc7d338f 5964 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5965 **/
bc7d338f 5966static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5967{
f650a38b 5968 struct i40e_hw *hw = &pf->hw;
cafa2ee6 5969 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 5970 i40e_status ret;
5971 u32 v;
5972
41c445ff
JB		 5973 /* Now we wait for GRST to settle out.
5974 * We don't have to delete the VEBs or VSIs from the hw switch
5975 * because the reset will make them disappear.
5976 */
5977 ret = i40e_pf_reset(hw);
b5565400 5978 if (ret) {
41c445ff 5979 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 5980 set_bit(__I40E_RESET_FAILED, &pf->state);
5981 goto clear_recovery;
b5565400 5982 }
41c445ff
JB		 5983 pf->pfr_count++;
5984
5985 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 5986 goto clear_recovery;
69bfb110 5987 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5988
5989 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5990 ret = i40e_init_adminq(&pf->hw);
5991 if (ret) {
5992 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 5993 goto clear_recovery;
41c445ff
JB		 5994 }
5995
4eb3f768
SN		 5996 /* re-verify the eeprom if we just had an EMP reset */
5997 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5998 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5999 i40e_verify_eeprom(pf);
6000 }
6001
e78ac4bf 6002 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6003 ret = i40e_get_capabilities(pf);
6004 if (ret) {
6005 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6006 ret);
6007 goto end_core_reset;
6008 }
6009
41c445ff
JB		 6010 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6011 hw->func_caps.num_rx_qp,
6012 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6013 if (ret) {
6014 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6015 goto end_core_reset;
6016 }
6017 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6018 if (ret) {
6019 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6020 goto end_core_reset;
6021 }
6022
4e3b35b0
NP		 6023#ifdef CONFIG_I40E_DCB
6024 ret = i40e_init_pf_dcb(pf);
6025 if (ret) {
6026 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
6027 goto end_core_reset;
6028 }
6029#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6030#ifdef I40E_FCOE
6031 ret = i40e_init_pf_fcoe(pf);
6032 if (ret)
6033 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6034
38e00438 6035#endif
41c445ff 6036 /* do basic switch setup */
bc7d338f 6037 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6038 if (ret)
6039 goto end_core_reset;
6040
7e2453fe
JB		 6041 /* driver is only interested in link up/down and module qualification
6042 * reports from firmware
6043 */
6044 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6045 I40E_AQ_EVENT_LINK_UPDOWN |
6046 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6047 if (ret)
6048 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6049
cafa2ee6
ASJ		 6050 /* make sure our flow control settings are restored */
6051 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6052 if (ret)
6053 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6054
41c445ff
JB		 6055 /* Rebuild the VSIs and VEBs that existed before reset.
6056 * They are still in our local switch element arrays, so only
6057 * need to rebuild the switch model in the HW.
6058 *
6059 * If there were VEBs but the reconstitution failed, we'll try
6060 * try to recover minimal use by getting the basic PF VSI working.
6061 */
6062 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6063 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6064 /* find the one VEB connected to the MAC, and find orphans */
6065 for (v = 0; v < I40E_MAX_VEB; v++) {
6066 if (!pf->veb[v])
6067 continue;
6068
6069 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6070 pf->veb[v]->uplink_seid == 0) {
6071 ret = i40e_reconstitute_veb(pf->veb[v]);
6072
6073 if (!ret)
6074 continue;
6075
6076 /* If Main VEB failed, we're in deep doodoo,
6077 * so give up rebuilding the switch and set up
6078 * for minimal rebuild of PF VSI.
6079 * If orphan failed, we'll report the error
6080 * but try to keep going.
6081 */
6082 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6083 dev_info(&pf->pdev->dev,
6084 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6085 ret);
6086 pf->vsi[pf->lan_vsi]->uplink_seid
6087 = pf->mac_seid;
6088 break;
6089 } else if (pf->veb[v]->uplink_seid == 0) {
6090 dev_info(&pf->pdev->dev,
6091 "rebuild of orphan VEB failed: %d\n",
6092 ret);
6093 }
6094 }
6095 }
6096 }
6097
6098 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6099 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6100 /* no VEB, so rebuild only the Main VSI */
6101 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6102 if (ret) {
6103 dev_info(&pf->pdev->dev,
6104 "rebuild of Main VSI failed: %d\n", ret);
6105 goto end_core_reset;
6106 }
6107 }
6108
cafa2ee6
ASJ		 6109 msleep(75);
6110 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6111 if (ret) {
6112 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6113 pf->hw.aq.asq_last_status);
6114 }
6115
41c445ff
JB		 6116 /* reinit the misc interrupt */
6117 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6118 ret = i40e_setup_misc_vector(pf);
6119
6120 /* restart the VSIs that were rebuilt and running before the reset */
6121 i40e_pf_unquiesce_all_vsi(pf);
6122
69f64b2b
MW		 6123 if (pf->num_alloc_vfs) {
6124 for (v = 0; v < pf->num_alloc_vfs; v++)
6125 i40e_reset_vf(&pf->vf[v], true);
6126 }
6127
41c445ff 6128 /* tell the firmware that we're starting */
44033fac 6129 i40e_send_version(pf);
41c445ff
JB		 6130
6131end_core_reset:
a316f651
ASJ		 6132 clear_bit(__I40E_RESET_FAILED, &pf->state);
6133clear_recovery:
41c445ff
JB		 6134 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6135}
6136
f650a38b
ASJ		 6137/**
6138 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6139 * @pf: board private structure
6140 *
6141 * Close up the VFs and other things in prep for a Core Reset,
6142 * then get ready to rebuild the world.
6143 **/
6144static void i40e_handle_reset_warning(struct i40e_pf *pf)
6145{
23cfbe07
SN		 6146 i40e_prep_for_reset(pf);
6147 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6148}
6149
41c445ff
JB		 6150/**
6151 * i40e_handle_mdd_event
6152 * @pf: pointer to the pf structure
6153 *
6154 * Called from the MDD irq handler to identify possibly malicious vfs
6155 **/
6156static void i40e_handle_mdd_event(struct i40e_pf *pf)
6157{
6158 struct i40e_hw *hw = &pf->hw;
6159 bool mdd_detected = false;
df430b12 6160 bool pf_mdd_detected = false;
41c445ff
JB		 6161 struct i40e_vf *vf;
6162 u32 reg;
6163 int i;
6164
6165 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6166 return;
6167
6168 /* find what triggered the MDD event */
6169 reg = rd32(hw, I40E_GL_MDET_TX);
6170 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6171 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6172 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6173 u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6174 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6175 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a
ASJ		 6176 I40E_GL_MDET_TX_EVENT_SHIFT;
6177 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6178 I40E_GL_MDET_TX_QUEUE_SHIFT;
faf32978
JB		 6179 if (netif_msg_tx_err(pf))
6180 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6181 event, queue, pf_num, vf_num);
41c445ff
JB		 6182 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6183 mdd_detected = true;
6184 }
6185 reg = rd32(hw, I40E_GL_MDET_RX);
6186 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6187 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6188 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6189 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a
ASJ		 6190 I40E_GL_MDET_RX_EVENT_SHIFT;
6191 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6192 I40E_GL_MDET_RX_QUEUE_SHIFT;
faf32978
JB		 6193 if (netif_msg_rx_err(pf))
6194 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6195 event, queue, func);
41c445ff
JB		 6196 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6197 mdd_detected = true;
6198 }
6199
df430b12
NP		 6200 if (mdd_detected) {
6201 reg = rd32(hw, I40E_PF_MDET_TX);
6202 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6203 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6204 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6205 pf_mdd_detected = true;
6206 }
6207 reg = rd32(hw, I40E_PF_MDET_RX);
6208 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6209 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6210 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6211 pf_mdd_detected = true;
6212 }
6213 /* Queue belongs to the PF, initiate a reset */
6214 if (pf_mdd_detected) {
6215 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6216 i40e_service_event_schedule(pf);
6217 }
6218 }
6219
41c445ff
JB		 6220 /* see if one of the VFs needs its hand slapped */
6221 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6222 vf = &(pf->vf[i]);
6223 reg = rd32(hw, I40E_VP_MDET_TX(i));
6224 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6225 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6226 vf->num_mdd_events++;
faf32978
JB		 6227 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6228 i);
41c445ff
JB		 6229 }
6230
6231 reg = rd32(hw, I40E_VP_MDET_RX(i));
6232 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6233 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6234 vf->num_mdd_events++;
faf32978
JB		 6235 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6236 i);
41c445ff
JB		 6237 }
6238
6239 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6240 dev_info(&pf->pdev->dev,
6241 "Too many MDD events on VF %d, disabled\n", i);
6242 dev_info(&pf->pdev->dev,
6243 "Use PF Control I/F to re-enable the VF\n");
6244 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6245 }
6246 }
6247
6248 /* re-enable mdd interrupt cause */
6249 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6250 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6251 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6252 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6253 i40e_flush(hw);
6254}
6255
a1c9a9d9
JK		 6256#ifdef CONFIG_I40E_VXLAN
6257/**
6258 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6259 * @pf: board private structure
6260 **/
6261static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6262{
a1c9a9d9
JK		 6263 struct i40e_hw *hw = &pf->hw;
6264 i40e_status ret;
6265 u8 filter_index;
6266 __be16 port;
6267 int i;
6268
6269 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6270 return;
6271
6272 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6273
6274 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6275 if (pf->pending_vxlan_bitmap & (1 << i)) {
6276 pf->pending_vxlan_bitmap &= ~(1 << i);
6277 port = pf->vxlan_ports[i];
6278 ret = port ?
6279 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6280 I40E_AQC_TUNNEL_TYPE_VXLAN,
6281 &filter_index, NULL)
6282 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6283
6284 if (ret) {
6285 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6286 port ? "adding" : "deleting",
6287 ntohs(port), port ? i : i);
6288
6289 pf->vxlan_ports[i] = 0;
6290 } else {
6291 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6292 port ? "Added" : "Deleted",
6293 ntohs(port), port ? i : filter_index);
6294 }
6295 }
6296 }
6297}
6298
6299#endif
41c445ff
JB		 6300/**
6301 * i40e_service_task - Run the driver's async subtasks
6302 * @work: pointer to work_struct containing our data
6303 **/
6304static void i40e_service_task(struct work_struct *work)
6305{
6306 struct i40e_pf *pf = container_of(work,
6307 struct i40e_pf,
6308 service_task);
6309 unsigned long start_time = jiffies;
6310
e57a2fea
SN		 6311 /* don't bother with service tasks if a reset is in progress */
6312 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6313 i40e_service_event_complete(pf);
6314 return;
6315 }
6316
41c445ff
JB		 6317 i40e_reset_subtask(pf);
6318 i40e_handle_mdd_event(pf);
6319 i40e_vc_process_vflr_event(pf);
6320 i40e_watchdog_subtask(pf);
6321 i40e_fdir_reinit_subtask(pf);
6322 i40e_check_hang_subtask(pf);
6323 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6324#ifdef CONFIG_I40E_VXLAN
6325 i40e_sync_vxlan_filters_subtask(pf);
6326#endif
41c445ff
JB		 6327 i40e_clean_adminq_subtask(pf);
6328
1e701e09
JB		 6329 i40e_link_event(pf);
6330
41c445ff
JB		 6331 i40e_service_event_complete(pf);
6332
6333 /* If the tasks have taken longer than one timer cycle or there
6334 * is more work to be done, reschedule the service task now
6335 * rather than wait for the timer to tick again.
6336 */
6337 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6338 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6339 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6340 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6341 i40e_service_event_schedule(pf);
6342}
6343
6344/**
6345 * i40e_service_timer - timer callback
6346 * @data: pointer to PF struct
6347 **/
6348static void i40e_service_timer(unsigned long data)
6349{
6350 struct i40e_pf *pf = (struct i40e_pf *)data;
6351
6352 mod_timer(&pf->service_timer,
6353 round_jiffies(jiffies + pf->service_timer_period));
6354 i40e_service_event_schedule(pf);
6355}
6356
6357/**
6358 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6359 * @vsi: the VSI being configured
6360 **/
6361static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6362{
6363 struct i40e_pf *pf = vsi->back;
6364
6365 switch (vsi->type) {
6366 case I40E_VSI_MAIN:
6367 vsi->alloc_queue_pairs = pf->num_lan_qps;
6368 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6369 I40E_REQ_DESCRIPTOR_MULTIPLE);
6370 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6371 vsi->num_q_vectors = pf->num_lan_msix;
6372 else
6373 vsi->num_q_vectors = 1;
6374
6375 break;
6376
6377 case I40E_VSI_FDIR:
6378 vsi->alloc_queue_pairs = 1;
6379 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6380 I40E_REQ_DESCRIPTOR_MULTIPLE);
6381 vsi->num_q_vectors = 1;
6382 break;
6383
6384 case I40E_VSI_VMDQ2:
6385 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6386 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6387 I40E_REQ_DESCRIPTOR_MULTIPLE);
6388 vsi->num_q_vectors = pf->num_vmdq_msix;
6389 break;
6390
6391 case I40E_VSI_SRIOV:
6392 vsi->alloc_queue_pairs = pf->num_vf_qps;
6393 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6394 I40E_REQ_DESCRIPTOR_MULTIPLE);
6395 break;
6396
38e00438
VD		 6397#ifdef I40E_FCOE
6398 case I40E_VSI_FCOE:
6399 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6400 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6401 I40E_REQ_DESCRIPTOR_MULTIPLE);
6402 vsi->num_q_vectors = pf->num_fcoe_msix;
6403 break;
6404
6405#endif /* I40E_FCOE */
41c445ff
JB		 6406 default:
6407 WARN_ON(1);
6408 return -ENODATA;
6409 }
6410
6411 return 0;
6412}
6413
f650a38b
ASJ		 6414/**
6415 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6416 * @type: VSI pointer
bc7d338f 6417 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6418 *
6419 * On error: returns error code (negative)
6420 * On success: returns 0
6421 **/
bc7d338f 6422static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6423{
6424 int size;
6425 int ret = 0;
6426
ac6c5e3d 6427 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6428 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6429 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6430 if (!vsi->tx_rings)
6431 return -ENOMEM;
f650a38b
ASJ		 6432 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6433
bc7d338f
ASJ		 6434 if (alloc_qvectors) {
6435 /* allocate memory for q_vector pointers */
f57e4fbd 6436 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6437 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6438 if (!vsi->q_vectors) {
6439 ret = -ENOMEM;
6440 goto err_vectors;
6441 }
f650a38b
ASJ		 6442 }
6443 return ret;
6444
6445err_vectors:
6446 kfree(vsi->tx_rings);
6447 return ret;
6448}
6449
41c445ff
JB		 6450/**
6451 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6452 * @pf: board private structure
6453 * @type: type of VSI
6454 *
6455 * On error: returns error code (negative)
6456 * On success: returns vsi index in PF (positive)
6457 **/
6458static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6459{
6460 int ret = -ENODEV;
6461 struct i40e_vsi *vsi;
6462 int vsi_idx;
6463 int i;
6464
6465 /* Need to protect the allocation of the VSIs at the PF level */
6466 mutex_lock(&pf->switch_mutex);
6467
6468 /* VSI list may be fragmented if VSI creation/destruction has
6469 * been happening. We can afford to do a quick scan to look
6470 * for any free VSIs in the list.
6471 *
6472 * find next empty vsi slot, looping back around if necessary
6473 */
6474 i = pf->next_vsi;
505682cd 6475 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6476 i++;
505682cd 6477 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6478 i = 0;
6479 while (i < pf->next_vsi && pf->vsi[i])
6480 i++;
6481 }
6482
505682cd 6483 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6484 vsi_idx = i; /* Found one! */
6485 } else {
6486 ret = -ENODEV;
493fb300 6487 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6488 }
6489 pf->next_vsi = ++i;
6490
6491 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6492 if (!vsi) {
6493 ret = -ENOMEM;
493fb300 6494 goto unlock_pf;
41c445ff
JB		 6495 }
6496 vsi->type = type;
6497 vsi->back = pf;
6498 set_bit(__I40E_DOWN, &vsi->state);
6499 vsi->flags = 0;
6500 vsi->idx = vsi_idx;
6501 vsi->rx_itr_setting = pf->rx_itr_default;
6502 vsi->tx_itr_setting = pf->tx_itr_default;
6503 vsi->netdev_registered = false;
6504 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6505 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6506 vsi->irqs_ready = false;
41c445ff 6507
9f65e15b
AD		 6508 ret = i40e_set_num_rings_in_vsi(vsi);
6509 if (ret)
6510 goto err_rings;
6511
bc7d338f 6512 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6513 if (ret)
9f65e15b 6514 goto err_rings;
493fb300 6515
41c445ff
JB		 6516 /* Setup default MSIX irq handler for VSI */
6517 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6518
6519 pf->vsi[vsi_idx] = vsi;
6520 ret = vsi_idx;
493fb300
AD		 6521 goto unlock_pf;
6522
9f65e15b 6523err_rings:
493fb300
AD		 6524 pf->next_vsi = i - 1;
6525 kfree(vsi);
6526unlock_pf:
41c445ff
JB		 6527 mutex_unlock(&pf->switch_mutex);
6528 return ret;
6529}
6530
f650a38b
ASJ		 6531/**
6532 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6533 * @type: VSI pointer
bc7d338f 6534 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6535 *
6536 * On error: returns error code (negative)
6537 * On success: returns 0
6538 **/
bc7d338f 6539static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6540{
6541 /* free the ring and vector containers */
bc7d338f
ASJ		 6542 if (free_qvectors) {
6543 kfree(vsi->q_vectors);
6544 vsi->q_vectors = NULL;
6545 }
f650a38b
ASJ		 6546 kfree(vsi->tx_rings);
6547 vsi->tx_rings = NULL;
6548 vsi->rx_rings = NULL;
6549}
6550
41c445ff
JB		 6551/**
6552 * i40e_vsi_clear - Deallocate the VSI provided
6553 * @vsi: the VSI being un-configured
6554 **/
6555static int i40e_vsi_clear(struct i40e_vsi *vsi)
6556{
6557 struct i40e_pf *pf;
6558
6559 if (!vsi)
6560 return 0;
6561
6562 if (!vsi->back)
6563 goto free_vsi;
6564 pf = vsi->back;
6565
6566 mutex_lock(&pf->switch_mutex);
6567 if (!pf->vsi[vsi->idx]) {
6568 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6569 vsi->idx, vsi->idx, vsi, vsi->type);
6570 goto unlock_vsi;
6571 }
6572
6573 if (pf->vsi[vsi->idx] != vsi) {
6574 dev_err(&pf->pdev->dev,
6575 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6576 pf->vsi[vsi->idx]->idx,
6577 pf->vsi[vsi->idx],
6578 pf->vsi[vsi->idx]->type,
6579 vsi->idx, vsi, vsi->type);
6580 goto unlock_vsi;
6581 }
6582
6583 /* updates the pf for this cleared vsi */
6584 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6585 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6586
bc7d338f 6587 i40e_vsi_free_arrays(vsi, true);
493fb300 6588
41c445ff
JB		 6589 pf->vsi[vsi->idx] = NULL;
6590 if (vsi->idx < pf->next_vsi)
6591 pf->next_vsi = vsi->idx;
6592
6593unlock_vsi:
6594 mutex_unlock(&pf->switch_mutex);
6595free_vsi:
6596 kfree(vsi);
6597
6598 return 0;
6599}
6600
9f65e15b
AD		 6601/**
6602 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6603 * @vsi: the VSI being cleaned
6604 **/
be1d5eea 6605static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6606{
6607 int i;
6608
8e9dca53 6609 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6610 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6611 kfree_rcu(vsi->tx_rings[i], rcu);
6612 vsi->tx_rings[i] = NULL;
6613 vsi->rx_rings[i] = NULL;
6614 }
be1d5eea 6615 }
9f65e15b
AD		 6616}
6617
41c445ff
JB		 6618/**
6619 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6620 * @vsi: the VSI being configured
6621 **/
6622static int i40e_alloc_rings(struct i40e_vsi *vsi)
6623{
e7046ee1 6624 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6625 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6626 int i;
6627
41c445ff 6628 /* Set basic values in the rings to be used later during open() */
d7397644 6629 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6630 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6631 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6632 if (!tx_ring)
6633 goto err_out;
41c445ff
JB		 6634
6635 tx_ring->queue_index = i;
6636 tx_ring->reg_idx = vsi->base_queue + i;
6637 tx_ring->ring_active = false;
6638 tx_ring->vsi = vsi;
6639 tx_ring->netdev = vsi->netdev;
6640 tx_ring->dev = &pf->pdev->dev;
6641 tx_ring->count = vsi->num_desc;
6642 tx_ring->size = 0;
6643 tx_ring->dcb_tc = 0;
9f65e15b 6644 vsi->tx_rings[i] = tx_ring;
41c445ff 6645
9f65e15b 6646 rx_ring = &tx_ring[1];
41c445ff
JB		 6647 rx_ring->queue_index = i;
6648 rx_ring->reg_idx = vsi->base_queue + i;
6649 rx_ring->ring_active = false;
6650 rx_ring->vsi = vsi;
6651 rx_ring->netdev = vsi->netdev;
6652 rx_ring->dev = &pf->pdev->dev;
6653 rx_ring->count = vsi->num_desc;
6654 rx_ring->size = 0;
6655 rx_ring->dcb_tc = 0;
6656 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6657 set_ring_16byte_desc_enabled(rx_ring);
6658 else
6659 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6660 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6661 }
6662
6663 return 0;
9f65e15b
AD		 6664
6665err_out:
6666 i40e_vsi_clear_rings(vsi);
6667 return -ENOMEM;
41c445ff
JB		 6668}
6669
6670/**
6671 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6672 * @pf: board private structure
6673 * @vectors: the number of MSI-X vectors to request
6674 *
6675 * Returns the number of vectors reserved, or error
6676 **/
6677static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6678{
7b37f376
AG		 6679 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6680 I40E_MIN_MSIX, vectors);
6681 if (vectors < 0) {
41c445ff 6682 dev_info(&pf->pdev->dev,
7b37f376 6683 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6684 vectors = 0;
6685 }
6686
6687 return vectors;
6688}
6689
6690/**
6691 * i40e_init_msix - Setup the MSIX capability
6692 * @pf: board private structure
6693 *
6694 * Work with the OS to set up the MSIX vectors needed.
6695 *
6696 * Returns 0 on success, negative on failure
6697 **/
6698static int i40e_init_msix(struct i40e_pf *pf)
6699{
6700 i40e_status err = 0;
6701 struct i40e_hw *hw = &pf->hw;
c135b0de 6702 int other_vecs = 0;
41c445ff
JB		 6703 int v_budget, i;
6704 int vec;
6705
6706 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6707 return -ENODEV;
6708
6709 /* The number of vectors we'll request will be comprised of:
6710 * - Add 1 for "other" cause for Admin Queue events, etc.
6711 * - The number of LAN queue pairs
f8ff1464
ASJ		 6712 * - Queues being used for RSS.
6713 * We don't need as many as max_rss_size vectors.
6714 * use rss_size instead in the calculation since that
6715 * is governed by number of cpus in the system.
6716 * - assumes symmetric Tx/Rx pairing
41c445ff 6717 * - The number of VMDq pairs
38e00438
VD		 6718#ifdef I40E_FCOE
6719 * - The number of FCOE qps.
6720#endif
41c445ff
JB		 6721 * Once we count this up, try the request.
6722 *
6723 * If we can't get what we want, we'll simplify to nearly nothing
6724 * and try again. If that still fails, we punt.
6725 */
f8ff1464 6726 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff 6727 pf->num_vmdq_msix = pf->num_vmdq_qps;
c135b0de
SN		 6728 other_vecs = 1;
6729 other_vecs += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6730 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
c135b0de 6731 other_vecs++;
41c445ff 6732
38e00438
VD		 6733#ifdef I40E_FCOE
6734 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6735 pf->num_fcoe_msix = pf->num_fcoe_qps;
6736 v_budget += pf->num_fcoe_msix;
6737 }
6738
6739#endif
41c445ff 6740 /* Scale down if necessary, and the rings will share vectors */
c135b0de
SN		 6741 pf->num_lan_msix = min_t(int, pf->num_lan_msix,
6742 (hw->func_caps.num_msix_vectors - other_vecs));
6743 v_budget = pf->num_lan_msix + other_vecs;
41c445ff
JB		 6744
6745 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6746 GFP_KERNEL);
6747 if (!pf->msix_entries)
6748 return -ENOMEM;
6749
6750 for (i = 0; i < v_budget; i++)
6751 pf->msix_entries[i].entry = i;
6752 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6753
6754 if (vec != v_budget) {
6755 /* If we have limited resources, we will start with no vectors
6756 * for the special features and then allocate vectors to some
6757 * of these features based on the policy and at the end disable
6758 * the features that did not get any vectors.
6759 */
38e00438
VD		 6760#ifdef I40E_FCOE
6761 pf->num_fcoe_qps = 0;
6762 pf->num_fcoe_msix = 0;
6763#endif
a34977ba
ASJ		 6764 pf->num_vmdq_msix = 0;
6765 }
6766
41c445ff
JB		 6767 if (vec < I40E_MIN_MSIX) {
6768 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6769 kfree(pf->msix_entries);
6770 pf->msix_entries = NULL;
6771 return -ENODEV;
6772
6773 } else if (vec == I40E_MIN_MSIX) {
6774 /* Adjust for minimal MSIX use */
41c445ff
JB		 6775 pf->num_vmdq_vsis = 0;
6776 pf->num_vmdq_qps = 0;
41c445ff
JB		 6777 pf->num_lan_qps = 1;
6778 pf->num_lan_msix = 1;
6779
6780 } else if (vec != v_budget) {
a34977ba
ASJ		 6781 /* reserve the misc vector */
6782 vec--;
6783
41c445ff
JB		 6784 /* Scale vector usage down */
6785 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6786 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6787
6788 /* partition out the remaining vectors */
6789 switch (vec) {
6790 case 2:
41c445ff
JB		 6791 pf->num_lan_msix = 1;
6792 break;
6793 case 3:
38e00438
VD		 6794#ifdef I40E_FCOE
6795 /* give one vector to FCoE */
6796 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6797 pf->num_lan_msix = 1;
6798 pf->num_fcoe_msix = 1;
6799 }
6800#else
41c445ff 6801 pf->num_lan_msix = 2;
38e00438 6802#endif
41c445ff
JB		 6803 break;
6804 default:
38e00438
VD		 6805#ifdef I40E_FCOE
6806 /* give one vector to FCoE */
6807 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6808 pf->num_fcoe_msix = 1;
6809 vec--;
6810 }
6811#endif
41c445ff
JB		 6812 pf->num_lan_msix = min_t(int, (vec / 2),
6813 pf->num_lan_qps);
6814 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6815 I40E_DEFAULT_NUM_VMDQ_VSI);
6816 break;
6817 }
6818 }
6819
a34977ba
ASJ		 6820 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6821 (pf->num_vmdq_msix == 0)) {
6822 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6823 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6824 }
38e00438
VD		 6825#ifdef I40E_FCOE
6826
6827 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
6828 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
6829 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
6830 }
6831#endif
41c445ff
JB		 6832 return err;
6833}
6834
493fb300 6835/**
90e04070 6836 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6837 * @vsi: the VSI being configured
6838 * @v_idx: index of the vector in the vsi struct
6839 *
6840 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6841 **/
90e04070 6842static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6843{
6844 struct i40e_q_vector *q_vector;
6845
6846 /* allocate q_vector */
6847 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6848 if (!q_vector)
6849 return -ENOMEM;
6850
6851 q_vector->vsi = vsi;
6852 q_vector->v_idx = v_idx;
6853 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6854 if (vsi->netdev)
6855 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6856 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6857
cd0b6fa6
AD		 6858 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6859 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6860
493fb300
AD		 6861 /* tie q_vector and vsi together */
6862 vsi->q_vectors[v_idx] = q_vector;
6863
6864 return 0;
6865}
6866
41c445ff 6867/**
90e04070 6868 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6869 * @vsi: the VSI being configured
6870 *
6871 * We allocate one q_vector per queue interrupt. If allocation fails we
6872 * return -ENOMEM.
6873 **/
90e04070 6874static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6875{
6876 struct i40e_pf *pf = vsi->back;
6877 int v_idx, num_q_vectors;
493fb300 6878 int err;
41c445ff
JB		 6879
6880 /* if not MSIX, give the one vector only to the LAN VSI */
6881 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6882 num_q_vectors = vsi->num_q_vectors;
6883 else if (vsi == pf->vsi[pf->lan_vsi])
6884 num_q_vectors = 1;
6885 else
6886 return -EINVAL;
6887
41c445ff 6888 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6889 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6890 if (err)
6891 goto err_out;
41c445ff
JB		 6892 }
6893
6894 return 0;
493fb300
AD		 6895
6896err_out:
6897 while (v_idx--)
6898 i40e_free_q_vector(vsi, v_idx);
6899
6900 return err;
41c445ff
JB		 6901}
6902
6903/**
6904 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6905 * @pf: board private structure to initialize
6906 **/
6907static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6908{
6909 int err = 0;
6910
6911 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6912 err = i40e_init_msix(pf);
6913 if (err) {
60ea5f83 6914 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 6915#ifdef I40E_FCOE
6916 I40E_FLAG_FCOE_ENABLED |
6917#endif
60ea5f83 6918 I40E_FLAG_RSS_ENABLED |
4d9b6043 6919 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6920 I40E_FLAG_SRIOV_ENABLED |
6921 I40E_FLAG_FD_SB_ENABLED |
6922 I40E_FLAG_FD_ATR_ENABLED |
6923 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6924
6925 /* rework the queue expectations without MSIX */
6926 i40e_determine_queue_usage(pf);
6927 }
6928 }
6929
6930 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6931 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6932 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6933 err = pci_enable_msi(pf->pdev);
6934 if (err) {
958a3e3b 6935 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6936 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6937 }
6938 }
6939
958a3e3b 6940 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6941 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6942
41c445ff
JB		 6943 /* track first vector for misc interrupts */
6944 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6945}
6946
6947/**
6948 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6949 * @pf: board private structure
6950 *
6951 * This sets up the handler for MSIX 0, which is used to manage the
6952 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6953 * when in MSI or Legacy interrupt mode.
6954 **/
6955static int i40e_setup_misc_vector(struct i40e_pf *pf)
6956{
6957 struct i40e_hw *hw = &pf->hw;
6958 int err = 0;
6959
6960 /* Only request the irq if this is the first time through, and
6961 * not when we're rebuilding after a Reset
6962 */
6963 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6964 err = request_irq(pf->msix_entries[0].vector,
6965 i40e_intr, 0, pf->misc_int_name, pf);
6966 if (err) {
6967 dev_info(&pf->pdev->dev,
77fa28be
CS		 6968 "request_irq for %s failed: %d\n",
6969 pf->misc_int_name, err);
41c445ff
JB		 6970 return -EFAULT;
6971 }
6972 }
6973
6974 i40e_enable_misc_int_causes(hw);
6975
6976 /* associate no queues to the misc vector */
6977 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6978 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6979
6980 i40e_flush(hw);
6981
6982 i40e_irq_dynamic_enable_icr0(pf);
6983
6984 return err;
6985}
6986
6987/**
6988 * i40e_config_rss - Prepare for RSS if used
6989 * @pf: board private structure
6990 **/
6991static int i40e_config_rss(struct i40e_pf *pf)
6992{
41c445ff
JB		 6993 /* Set of random keys generated using kernel random number generator */
6994 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6995 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6996 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6997 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6998 struct i40e_hw *hw = &pf->hw;
6999 u32 lut = 0;
7000 int i, j;
7001 u64 hena;
e157ea30 7002 u32 reg_val;
41c445ff
JB		 7003
7004 /* Fill out hash function seed */
7005 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7006 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
7007
7008 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7009 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7010 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7011 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7012 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7013 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7014
e157ea30
CW		 7015 /* Check capability and Set table size and register per hw expectation*/
7016 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7017 if (hw->func_caps.rss_table_size == 512) {
7018 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7019 pf->rss_table_size = 512;
7020 } else {
7021 pf->rss_table_size = 128;
7022 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7023 }
7024 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7025
41c445ff 7026 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7027 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7028
7029 /* The assumption is that lan qp count will be the highest
7030 * qp count for any PF VSI that needs RSS.
7031 * If multiple VSIs need RSS support, all the qp counts
7032 * for those VSIs should be a power of 2 for RSS to work.
7033 * If LAN VSI is the only consumer for RSS then this requirement
7034 * is not necessary.
7035 */
7036 if (j == pf->rss_size)
7037 j = 0;
7038 /* lut = 4-byte sliding window of 4 lut entries */
7039 lut = (lut << 8) | (j &
7040 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7041 /* On i = 3, we have 4 entries in lut; write to the register */
7042 if ((i & 3) == 3)
7043 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7044 }
7045 i40e_flush(hw);
7046
7047 return 0;
7048}
7049
f8ff1464
ASJ		 7050/**
7051 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7052 * @pf: board private structure
7053 * @queue_count: the requested queue count for rss.
7054 *
7055 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7056 * count which may be different from the requested queue count.
7057 **/
7058int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7059{
7060 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7061 return 0;
7062
7063 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 7064
7065 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 7066 i40e_prep_for_reset(pf);
7067
f8ff1464
ASJ		 7068 pf->rss_size = queue_count;
7069
7070 i40e_reset_and_rebuild(pf, true);
7071 i40e_config_rss(pf);
7072 }
7073 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7074 return pf->rss_size;
7075}
7076
41c445ff
JB		 7077/**
7078 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7079 * @pf: board private structure to initialize
7080 *
7081 * i40e_sw_init initializes the Adapter private data structure.
7082 * Fields are initialized based on PCI device information and
7083 * OS network device settings (MTU size).
7084 **/
7085static int i40e_sw_init(struct i40e_pf *pf)
7086{
7087 int err = 0;
7088 int size;
7089
7090 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7091 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7092 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7093 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7094 if (I40E_DEBUG_USER & debug)
7095 pf->hw.debug_mask = debug;
7096 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7097 I40E_DEFAULT_MSG_ENABLE);
7098 }
7099
7100 /* Set default capability flags */
7101 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7102 I40E_FLAG_MSI_ENABLED |
7103 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 7104 I40E_FLAG_RX_1BUF_ENABLED;
7105
ca99eb99
MW		 7106 /* Set default ITR */
7107 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7108 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7109
7134f9ce
JB		 7110 /* Depending on PF configurations, it is possible that the RSS
7111 * maximum might end up larger than the available queues
7112 */
41c445ff 7113 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7114 pf->rss_size = 1;
7134f9ce
JB		 7115 pf->rss_size_max = min_t(int, pf->rss_size_max,
7116 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7117 if (pf->hw.func_caps.rss) {
7118 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7119 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7120 }
7121
2050bc65
CS		 7122 /* MFP mode enabled */
7123 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7124 pf->flags |= I40E_FLAG_MFP_ENABLED;
7125 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
7126 }
7127
cbf61325
ASJ		 7128 /* FW/NVM is not yet fixed in this regard */
7129 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7130 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7131 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7132 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7133 /* Setup a counter for fd_atr per pf */
7134 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7135 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7136 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7137 /* Setup a counter for fd_sb per pf */
7138 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7139 } else {
7140 dev_info(&pf->pdev->dev,
0b67584f 7141 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7142 }
cbf61325
ASJ		 7143 pf->fdir_pf_filter_count =
7144 pf->hw.func_caps.fd_filters_guaranteed;
7145 pf->hw.fdir_shared_filter_count =
7146 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7147 }
7148
7149 if (pf->hw.func_caps.vmdq) {
7150 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7151 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7152 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7153 }
7154
38e00438
VD		 7155#ifdef I40E_FCOE
7156 err = i40e_init_pf_fcoe(pf);
7157 if (err)
7158 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7159
7160#endif /* I40E_FCOE */
41c445ff
JB		 7161#ifdef CONFIG_PCI_IOV
7162 if (pf->hw.func_caps.num_vfs) {
7163 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7164 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7165 pf->num_req_vfs = min_t(int,
7166 pf->hw.func_caps.num_vfs,
7167 I40E_MAX_VF_COUNT);
7168 }
7169#endif /* CONFIG_PCI_IOV */
7170 pf->eeprom_version = 0xDEAD;
7171 pf->lan_veb = I40E_NO_VEB;
7172 pf->lan_vsi = I40E_NO_VSI;
7173
7174 /* set up queue assignment tracking */
7175 size = sizeof(struct i40e_lump_tracking)
7176 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7177 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7178 if (!pf->qp_pile) {
7179 err = -ENOMEM;
7180 goto sw_init_done;
7181 }
7182 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7183 pf->qp_pile->search_hint = 0;
7184
7185 /* set up vector assignment tracking */
7186 size = sizeof(struct i40e_lump_tracking)
7187 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7188 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7189 if (!pf->irq_pile) {
7190 kfree(pf->qp_pile);
7191 err = -ENOMEM;
7192 goto sw_init_done;
7193 }
7194 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7195 pf->irq_pile->search_hint = 0;
7196
327fe04b
ASJ		 7197 pf->tx_timeout_recovery_level = 1;
7198
41c445ff
JB		 7199 mutex_init(&pf->switch_mutex);
7200
7201sw_init_done:
7202 return err;
7203}
7204
7c3c288b
ASJ		 7205/**
7206 * i40e_set_ntuple - set the ntuple feature flag and take action
7207 * @pf: board private structure to initialize
7208 * @features: the feature set that the stack is suggesting
7209 *
7210 * returns a bool to indicate if reset needs to happen
7211 **/
7212bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7213{
7214 bool need_reset = false;
7215
7216 /* Check if Flow Director n-tuple support was enabled or disabled. If
7217 * the state changed, we need to reset.
7218 */
7219 if (features & NETIF_F_NTUPLE) {
7220 /* Enable filters and mark for reset */
7221 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7222 need_reset = true;
7223 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7224 } else {
7225 /* turn off filters, mark for reset and clear SW filter list */
7226 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7227 need_reset = true;
7228 i40e_fdir_filter_exit(pf);
7229 }
7230 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7231 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7232 /* reset fd counters */
7233 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7234 pf->fdir_pf_active_filters = 0;
7235 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7236 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7237 /* if ATR was auto disabled it can be re-enabled. */
7238 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7239 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7240 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7241 }
7242 return need_reset;
7243}
7244
41c445ff
JB		 7245/**
7246 * i40e_set_features - set the netdev feature flags
7247 * @netdev: ptr to the netdev being adjusted
7248 * @features: the feature set that the stack is suggesting
7249 **/
7250static int i40e_set_features(struct net_device *netdev,
7251 netdev_features_t features)
7252{
7253 struct i40e_netdev_priv *np = netdev_priv(netdev);
7254 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7255 struct i40e_pf *pf = vsi->back;
7256 bool need_reset;
41c445ff
JB		 7257
7258 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7259 i40e_vlan_stripping_enable(vsi);
7260 else
7261 i40e_vlan_stripping_disable(vsi);
7262
7c3c288b
ASJ		 7263 need_reset = i40e_set_ntuple(pf, features);
7264
7265 if (need_reset)
7266 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7267
41c445ff
JB		 7268 return 0;
7269}
7270
a1c9a9d9
JK		 7271#ifdef CONFIG_I40E_VXLAN
7272/**
7273 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7274 * @pf: board private structure
7275 * @port: The UDP port to look up
7276 *
7277 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7278 **/
7279static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7280{
7281 u8 i;
7282
7283 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7284 if (pf->vxlan_ports[i] == port)
7285 return i;
7286 }
7287
7288 return i;
7289}
7290
7291/**
7292 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7293 * @netdev: This physical port's netdev
7294 * @sa_family: Socket Family that VXLAN is notifying us about
7295 * @port: New UDP port number that VXLAN started listening to
7296 **/
7297static void i40e_add_vxlan_port(struct net_device *netdev,
7298 sa_family_t sa_family, __be16 port)
7299{
7300 struct i40e_netdev_priv *np = netdev_priv(netdev);
7301 struct i40e_vsi *vsi = np->vsi;
7302 struct i40e_pf *pf = vsi->back;
7303 u8 next_idx;
7304 u8 idx;
7305
7306 if (sa_family == AF_INET6)
7307 return;
7308
7309 idx = i40e_get_vxlan_port_idx(pf, port);
7310
7311 /* Check if port already exists */
7312 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7313 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7314 return;
7315 }
7316
7317 /* Now check if there is space to add the new port */
7318 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7319
7320 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7321 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7322 ntohs(port));
7323 return;
7324 }
7325
7326 /* New port: add it and mark its index in the bitmap */
7327 pf->vxlan_ports[next_idx] = port;
7328 pf->pending_vxlan_bitmap |= (1 << next_idx);
7329
7330 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7331}
7332
7333/**
7334 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7335 * @netdev: This physical port's netdev
7336 * @sa_family: Socket Family that VXLAN is notifying us about
7337 * @port: UDP port number that VXLAN stopped listening to
7338 **/
7339static void i40e_del_vxlan_port(struct net_device *netdev,
7340 sa_family_t sa_family, __be16 port)
7341{
7342 struct i40e_netdev_priv *np = netdev_priv(netdev);
7343 struct i40e_vsi *vsi = np->vsi;
7344 struct i40e_pf *pf = vsi->back;
7345 u8 idx;
7346
7347 if (sa_family == AF_INET6)
7348 return;
7349
7350 idx = i40e_get_vxlan_port_idx(pf, port);
7351
7352 /* Check if port already exists */
7353 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7354 /* if port exists, set it to 0 (mark for deletion)
7355 * and make it pending
7356 */
7357 pf->vxlan_ports[idx] = 0;
7358
7359 pf->pending_vxlan_bitmap |= (1 << idx);
7360
7361 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7362 } else {
7363 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7364 ntohs(port));
7365 }
7366}
7367
7368#endif
1f224ad2
NP		 7369static int i40e_get_phys_port_id(struct net_device *netdev,
7370 struct netdev_phys_port_id *ppid)
7371{
7372 struct i40e_netdev_priv *np = netdev_priv(netdev);
7373 struct i40e_pf *pf = np->vsi->back;
7374 struct i40e_hw *hw = &pf->hw;
7375
7376 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7377 return -EOPNOTSUPP;
7378
7379 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7380 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7381
7382 return 0;
7383}
7384
4ba0dea5
GR		 7385#ifdef HAVE_FDB_OPS
7386#ifdef USE_CONST_DEV_UC_CHAR
7387static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7388 struct net_device *dev,
7389 const unsigned char *addr,
7390 u16 flags)
7391#else
7392static int i40e_ndo_fdb_add(struct ndmsg *ndm,
7393 struct net_device *dev,
7394 unsigned char *addr,
7395 u16 flags)
7396#endif
7397{
7398 struct i40e_netdev_priv *np = netdev_priv(dev);
7399 struct i40e_pf *pf = np->vsi->back;
7400 int err = 0;
7401
7402 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7403 return -EOPNOTSUPP;
7404
7405 /* Hardware does not support aging addresses so if a
7406 * ndm_state is given only allow permanent addresses
7407 */
7408 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7409 netdev_info(dev, "FDB only supports static addresses\n");
7410 return -EINVAL;
7411 }
7412
7413 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7414 err = dev_uc_add_excl(dev, addr);
7415 else if (is_multicast_ether_addr(addr))
7416 err = dev_mc_add_excl(dev, addr);
7417 else
7418 err = -EINVAL;
7419
7420 /* Only return duplicate errors if NLM_F_EXCL is set */
7421 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7422 err = 0;
7423
7424 return err;
7425}
7426
7427#ifndef USE_DEFAULT_FDB_DEL_DUMP
7428#ifdef USE_CONST_DEV_UC_CHAR
7429static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7430 struct net_device *dev,
7431 const unsigned char *addr)
7432#else
7433static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7434 struct net_device *dev,
7435 unsigned char *addr)
7436#endif
7437{
7438 struct i40e_netdev_priv *np = netdev_priv(dev);
7439 struct i40e_pf *pf = np->vsi->back;
7440 int err = -EOPNOTSUPP;
7441
7442 if (ndm->ndm_state & NUD_PERMANENT) {
7443 netdev_info(dev, "FDB only supports static addresses\n");
7444 return -EINVAL;
7445 }
7446
7447 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7448 if (is_unicast_ether_addr(addr))
7449 err = dev_uc_del(dev, addr);
7450 else if (is_multicast_ether_addr(addr))
7451 err = dev_mc_del(dev, addr);
7452 else
7453 err = -EINVAL;
7454 }
7455
7456 return err;
7457}
7458
7459static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7460 struct netlink_callback *cb,
7461 struct net_device *dev,
5d5eacb3 7462 struct net_device *filter_dev,
4ba0dea5
GR		 7463 int idx)
7464{
7465 struct i40e_netdev_priv *np = netdev_priv(dev);
7466 struct i40e_pf *pf = np->vsi->back;
7467
7468 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
5d5eacb3 7469 idx = ndo_dflt_fdb_dump(skb, cb, dev, filter_dev, idx);
4ba0dea5
GR		 7470
7471 return idx;
7472}
7473
7474#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7475#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7476static const struct net_device_ops i40e_netdev_ops = {
7477 .ndo_open = i40e_open,
7478 .ndo_stop = i40e_close,
7479 .ndo_start_xmit = i40e_lan_xmit_frame,
7480 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7481 .ndo_set_rx_mode = i40e_set_rx_mode,
7482 .ndo_validate_addr = eth_validate_addr,
7483 .ndo_set_mac_address = i40e_set_mac,
7484 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7485 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7486 .ndo_tx_timeout = i40e_tx_timeout,
7487 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7488 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7489#ifdef CONFIG_NET_POLL_CONTROLLER
7490 .ndo_poll_controller = i40e_netpoll,
7491#endif
7492 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7493#ifdef I40E_FCOE
7494 .ndo_fcoe_enable = i40e_fcoe_enable,
7495 .ndo_fcoe_disable = i40e_fcoe_disable,
7496#endif
41c445ff
JB		 7497 .ndo_set_features = i40e_set_features,
7498 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7499 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7500 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7501 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7502 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7503 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7504#ifdef CONFIG_I40E_VXLAN
7505 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7506 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7507#endif
1f224ad2 7508 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5
GR		 7509#ifdef HAVE_FDB_OPS
7510 .ndo_fdb_add = i40e_ndo_fdb_add,
7511#ifndef USE_DEFAULT_FDB_DEL_DUMP
7512 .ndo_fdb_del = i40e_ndo_fdb_del,
7513 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7514#endif
7515#endif
41c445ff
JB		 7516};
7517
7518/**
7519 * i40e_config_netdev - Setup the netdev flags
7520 * @vsi: the VSI being configured
7521 *
7522 * Returns 0 on success, negative value on failure
7523 **/
7524static int i40e_config_netdev(struct i40e_vsi *vsi)
7525{
1a10370a 7526 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7527 struct i40e_pf *pf = vsi->back;
7528 struct i40e_hw *hw = &pf->hw;
7529 struct i40e_netdev_priv *np;
7530 struct net_device *netdev;
7531 u8 mac_addr[ETH_ALEN];
7532 int etherdev_size;
7533
7534 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7535 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7536 if (!netdev)
7537 return -ENOMEM;
7538
7539 vsi->netdev = netdev;
7540 np = netdev_priv(netdev);
7541 np->vsi = vsi;
7542
d70e941b 7543 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7544 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7545 NETIF_F_TSO;
41c445ff
JB		 7546
7547 netdev->features = NETIF_F_SG |
7548 NETIF_F_IP_CSUM |
7549 NETIF_F_SCTP_CSUM |
7550 NETIF_F_HIGHDMA |
7551 NETIF_F_GSO_UDP_TUNNEL |
7552 NETIF_F_HW_VLAN_CTAG_TX |
7553 NETIF_F_HW_VLAN_CTAG_RX |
7554 NETIF_F_HW_VLAN_CTAG_FILTER |
7555 NETIF_F_IPV6_CSUM |
7556 NETIF_F_TSO |
059dab69 7557 NETIF_F_TSO_ECN |
41c445ff
JB		 7558 NETIF_F_TSO6 |
7559 NETIF_F_RXCSUM |
7560 NETIF_F_RXHASH |
7561 0;
7562
2e86a0b6
ASJ		 7563 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7564 netdev->features |= NETIF_F_NTUPLE;
7565
41c445ff
JB		 7566 /* copy netdev features into list of user selectable features */
7567 netdev->hw_features |= netdev->features;
7568
7569 if (vsi->type == I40E_VSI_MAIN) {
7570 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7571 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 7572 /* The following steps are necessary to prevent reception
7573 * of tagged packets - some older NVM configurations load a
7574 * default a MAC-VLAN filter that accepts any tagged packet
7575 * which must be replaced by a normal filter.
8c27d42e 7576 */
30650cc5
SN		 7577 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
7578 i40e_add_filter(vsi, mac_addr,
7579 I40E_VLAN_ANY, false, true);
41c445ff
JB		 7580 } else {
7581 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7582 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7583 pf->vsi[pf->lan_vsi]->netdev->name);
7584 random_ether_addr(mac_addr);
7585 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7586 }
1a10370a 7587 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7588
9a173901
GR		 7589 ether_addr_copy(netdev->dev_addr, mac_addr);
7590 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7591 /* vlan gets same features (except vlan offload)
7592 * after any tweaks for specific VSI types
7593 */
7594 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7595 NETIF_F_HW_VLAN_CTAG_RX |
7596 NETIF_F_HW_VLAN_CTAG_FILTER);
7597 netdev->priv_flags |= IFF_UNICAST_FLT;
7598 netdev->priv_flags |= IFF_SUPP_NOFCS;
7599 /* Setup netdev TC information */
7600 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7601
7602 netdev->netdev_ops = &i40e_netdev_ops;
7603 netdev->watchdog_timeo = 5 * HZ;
7604 i40e_set_ethtool_ops(netdev);
38e00438
VD		 7605#ifdef I40E_FCOE
7606 i40e_fcoe_config_netdev(netdev, vsi);
7607#endif
41c445ff
JB		 7608
7609 return 0;
7610}
7611
7612/**
7613 * i40e_vsi_delete - Delete a VSI from the switch
7614 * @vsi: the VSI being removed
7615 *
7616 * Returns 0 on success, negative value on failure
7617 **/
7618static void i40e_vsi_delete(struct i40e_vsi *vsi)
7619{
7620 /* remove default VSI is not allowed */
7621 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7622 return;
7623
41c445ff 7624 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7625}
7626
7627/**
7628 * i40e_add_vsi - Add a VSI to the switch
7629 * @vsi: the VSI being configured
7630 *
7631 * This initializes a VSI context depending on the VSI type to be added and
7632 * passes it down to the add_vsi aq command.
7633 **/
7634static int i40e_add_vsi(struct i40e_vsi *vsi)
7635{
7636 int ret = -ENODEV;
7637 struct i40e_mac_filter *f, *ftmp;
7638 struct i40e_pf *pf = vsi->back;
7639 struct i40e_hw *hw = &pf->hw;
7640 struct i40e_vsi_context ctxt;
7641 u8 enabled_tc = 0x1; /* TC0 enabled */
7642 int f_count = 0;
7643
7644 memset(&ctxt, 0, sizeof(ctxt));
7645 switch (vsi->type) {
7646 case I40E_VSI_MAIN:
7647 /* The PF's main VSI is already setup as part of the
7648 * device initialization, so we'll not bother with
7649 * the add_vsi call, but we will retrieve the current
7650 * VSI context.
7651 */
7652 ctxt.seid = pf->main_vsi_seid;
7653 ctxt.pf_num = pf->hw.pf_id;
7654 ctxt.vf_num = 0;
7655 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7656 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7657 if (ret) {
7658 dev_info(&pf->pdev->dev,
7659 "couldn't get pf vsi config, err %d, aq_err %d\n",
7660 ret, pf->hw.aq.asq_last_status);
7661 return -ENOENT;
7662 }
7663 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7664 vsi->info.valid_sections = 0;
7665
7666 vsi->seid = ctxt.seid;
7667 vsi->id = ctxt.vsi_number;
7668
7669 enabled_tc = i40e_pf_get_tc_map(pf);
7670
7671 /* MFP mode setup queue map and update VSI */
7672 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7673 memset(&ctxt, 0, sizeof(ctxt));
7674 ctxt.seid = pf->main_vsi_seid;
7675 ctxt.pf_num = pf->hw.pf_id;
7676 ctxt.vf_num = 0;
7677 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7678 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7679 if (ret) {
7680 dev_info(&pf->pdev->dev,
7681 "update vsi failed, aq_err=%d\n",
7682 pf->hw.aq.asq_last_status);
7683 ret = -ENOENT;
7684 goto err;
7685 }
7686 /* update the local VSI info queue map */
7687 i40e_vsi_update_queue_map(vsi, &ctxt);
7688 vsi->info.valid_sections = 0;
7689 } else {
7690 /* Default/Main VSI is only enabled for TC0
7691 * reconfigure it to enable all TCs that are
7692 * available on the port in SFP mode.
7693 */
7694 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7695 if (ret) {
7696 dev_info(&pf->pdev->dev,
7697 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7698 enabled_tc, ret,
7699 pf->hw.aq.asq_last_status);
7700 ret = -ENOENT;
7701 }
7702 }
7703 break;
7704
7705 case I40E_VSI_FDIR:
cbf61325
ASJ		 7706 ctxt.pf_num = hw->pf_id;
7707 ctxt.vf_num = 0;
7708 ctxt.uplink_seid = vsi->uplink_seid;
7709 ctxt.connection_type = 0x1; /* regular data port */
7710 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7711 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7712 break;
7713
7714 case I40E_VSI_VMDQ2:
7715 ctxt.pf_num = hw->pf_id;
7716 ctxt.vf_num = 0;
7717 ctxt.uplink_seid = vsi->uplink_seid;
7718 ctxt.connection_type = 0x1; /* regular data port */
7719 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7720
7721 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7722
7723 /* This VSI is connected to VEB so the switch_id
7724 * should be set to zero by default.
7725 */
7726 ctxt.info.switch_id = 0;
41c445ff
JB		 7727 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7728
7729 /* Setup the VSI tx/rx queue map for TC0 only for now */
7730 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7731 break;
7732
7733 case I40E_VSI_SRIOV:
7734 ctxt.pf_num = hw->pf_id;
7735 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7736 ctxt.uplink_seid = vsi->uplink_seid;
7737 ctxt.connection_type = 0x1; /* regular data port */
7738 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7739
7740 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7741
7742 /* This VSI is connected to VEB so the switch_id
7743 * should be set to zero by default.
7744 */
7745 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7746
7747 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7748 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7749 if (pf->vf[vsi->vf_id].spoofchk) {
7750 ctxt.info.valid_sections |=
7751 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7752 ctxt.info.sec_flags |=
7753 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7754 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7755 }
41c445ff
JB		 7756 /* Setup the VSI tx/rx queue map for TC0 only for now */
7757 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7758 break;
7759
38e00438
VD		 7760#ifdef I40E_FCOE
7761 case I40E_VSI_FCOE:
7762 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
7763 if (ret) {
7764 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
7765 return ret;
7766 }
7767 break;
7768
7769#endif /* I40E_FCOE */
41c445ff
JB		 7770 default:
7771 return -ENODEV;
7772 }
7773
7774 if (vsi->type != I40E_VSI_MAIN) {
7775 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7776 if (ret) {
7777 dev_info(&vsi->back->pdev->dev,
7778 "add vsi failed, aq_err=%d\n",
7779 vsi->back->hw.aq.asq_last_status);
7780 ret = -ENOENT;
7781 goto err;
7782 }
7783 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7784 vsi->info.valid_sections = 0;
7785 vsi->seid = ctxt.seid;
7786 vsi->id = ctxt.vsi_number;
7787 }
7788
7789 /* If macvlan filters already exist, force them to get loaded */
7790 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7791 f->changed = true;
7792 f_count++;
6252c7e4
SN		 7793
7794 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 7795 struct i40e_aqc_remove_macvlan_element_data element;
7796
7797 memset(&element, 0, sizeof(element));
7798 ether_addr_copy(element.mac_addr, f->macaddr);
7799 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7800 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
7801 &element, 1, NULL);
7802 if (ret) {
7803 /* some older FW has a different default */
7804 element.flags |=
7805 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7806 i40e_aq_remove_macvlan(hw, vsi->seid,
7807 &element, 1, NULL);
7808 }
7809
7810 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 7811 I40E_AQC_WRITE_TYPE_LAA_WOL,
7812 f->macaddr, NULL);
7813 }
41c445ff
JB		 7814 }
7815 if (f_count) {
7816 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7817 pf->flags |= I40E_FLAG_FILTER_SYNC;
7818 }
7819
7820 /* Update VSI BW information */
7821 ret = i40e_vsi_get_bw_info(vsi);
7822 if (ret) {
7823 dev_info(&pf->pdev->dev,
7824 "couldn't get vsi bw info, err %d, aq_err %d\n",
7825 ret, pf->hw.aq.asq_last_status);
7826 /* VSI is already added so not tearing that up */
7827 ret = 0;
7828 }
7829
7830err:
7831 return ret;
7832}
7833
7834/**
7835 * i40e_vsi_release - Delete a VSI and free its resources
7836 * @vsi: the VSI being removed
7837 *
7838 * Returns 0 on success or < 0 on error
7839 **/
7840int i40e_vsi_release(struct i40e_vsi *vsi)
7841{
7842 struct i40e_mac_filter *f, *ftmp;
7843 struct i40e_veb *veb = NULL;
7844 struct i40e_pf *pf;
7845 u16 uplink_seid;
7846 int i, n;
7847
7848 pf = vsi->back;
7849
7850 /* release of a VEB-owner or last VSI is not allowed */
7851 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7852 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7853 vsi->seid, vsi->uplink_seid);
7854 return -ENODEV;
7855 }
7856 if (vsi == pf->vsi[pf->lan_vsi] &&
7857 !test_bit(__I40E_DOWN, &pf->state)) {
7858 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7859 return -ENODEV;
7860 }
7861
7862 uplink_seid = vsi->uplink_seid;
7863 if (vsi->type != I40E_VSI_SRIOV) {
7864 if (vsi->netdev_registered) {
7865 vsi->netdev_registered = false;
7866 if (vsi->netdev) {
7867 /* results in a call to i40e_close() */
7868 unregister_netdev(vsi->netdev);
41c445ff
JB		 7869 }
7870 } else {
90ef8d47 7871 i40e_vsi_close(vsi);
41c445ff
JB		 7872 }
7873 i40e_vsi_disable_irq(vsi);
7874 }
7875
7876 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7877 i40e_del_filter(vsi, f->macaddr, f->vlan,
7878 f->is_vf, f->is_netdev);
7879 i40e_sync_vsi_filters(vsi);
7880
7881 i40e_vsi_delete(vsi);
7882 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7883 if (vsi->netdev) {
7884 free_netdev(vsi->netdev);
7885 vsi->netdev = NULL;
7886 }
41c445ff
JB		 7887 i40e_vsi_clear_rings(vsi);
7888 i40e_vsi_clear(vsi);
7889
7890 /* If this was the last thing on the VEB, except for the
7891 * controlling VSI, remove the VEB, which puts the controlling
7892 * VSI onto the next level down in the switch.
7893 *
7894 * Well, okay, there's one more exception here: don't remove
7895 * the orphan VEBs yet. We'll wait for an explicit remove request
7896 * from up the network stack.
7897 */
505682cd 7898 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7899 if (pf->vsi[i] &&
7900 pf->vsi[i]->uplink_seid == uplink_seid &&
7901 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7902 n++; /* count the VSIs */
7903 }
7904 }
7905 for (i = 0; i < I40E_MAX_VEB; i++) {
7906 if (!pf->veb[i])
7907 continue;
7908 if (pf->veb[i]->uplink_seid == uplink_seid)
7909 n++; /* count the VEBs */
7910 if (pf->veb[i]->seid == uplink_seid)
7911 veb = pf->veb[i];
7912 }
7913 if (n == 0 && veb && veb->uplink_seid != 0)
7914 i40e_veb_release(veb);
7915
7916 return 0;
7917}
7918
7919/**
7920 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7921 * @vsi: ptr to the VSI
7922 *
7923 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7924 * corresponding SW VSI structure and initializes num_queue_pairs for the
7925 * newly allocated VSI.
7926 *
7927 * Returns 0 on success or negative on failure
7928 **/
7929static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7930{
7931 int ret = -ENOENT;
7932 struct i40e_pf *pf = vsi->back;
7933
493fb300 7934 if (vsi->q_vectors[0]) {
41c445ff
JB		 7935 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7936 vsi->seid);
7937 return -EEXIST;
7938 }
7939
7940 if (vsi->base_vector) {
f29eaa3d 7941 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7942 vsi->seid, vsi->base_vector);
7943 return -EEXIST;
7944 }
7945
90e04070 7946 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7947 if (ret) {
7948 dev_info(&pf->pdev->dev,
7949 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7950 vsi->num_q_vectors, vsi->seid, ret);
7951 vsi->num_q_vectors = 0;
7952 goto vector_setup_out;
7953 }
7954
958a3e3b
SN		 7955 if (vsi->num_q_vectors)
7956 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7957 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7958 if (vsi->base_vector < 0) {
7959 dev_info(&pf->pdev->dev,
f29eaa3d 7960 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7961 vsi->seid, vsi->base_vector);
7962 i40e_vsi_free_q_vectors(vsi);
7963 ret = -ENOENT;
7964 goto vector_setup_out;
7965 }
7966
7967vector_setup_out:
7968 return ret;
7969}
7970
bc7d338f
ASJ		 7971/**
7972 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7973 * @vsi: pointer to the vsi.
7974 *
7975 * This re-allocates a vsi's queue resources.
7976 *
7977 * Returns pointer to the successfully allocated and configured VSI sw struct
7978 * on success, otherwise returns NULL on failure.
7979 **/
7980static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7981{
7982 struct i40e_pf *pf = vsi->back;
7983 u8 enabled_tc;
7984 int ret;
7985
7986 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7987 i40e_vsi_clear_rings(vsi);
7988
7989 i40e_vsi_free_arrays(vsi, false);
7990 i40e_set_num_rings_in_vsi(vsi);
7991 ret = i40e_vsi_alloc_arrays(vsi, false);
7992 if (ret)
7993 goto err_vsi;
7994
7995 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7996 if (ret < 0) {
7997 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7998 vsi->seid, ret);
7999 goto err_vsi;
8000 }
8001 vsi->base_queue = ret;
8002
8003 /* Update the FW view of the VSI. Force a reset of TC and queue
8004 * layout configurations.
8005 */
8006 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8007 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8008 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8009 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8010
8011 /* assign it some queues */
8012 ret = i40e_alloc_rings(vsi);
8013 if (ret)
8014 goto err_rings;
8015
8016 /* map all of the rings to the q_vectors */
8017 i40e_vsi_map_rings_to_vectors(vsi);
8018 return vsi;
8019
8020err_rings:
8021 i40e_vsi_free_q_vectors(vsi);
8022 if (vsi->netdev_registered) {
8023 vsi->netdev_registered = false;
8024 unregister_netdev(vsi->netdev);
8025 free_netdev(vsi->netdev);
8026 vsi->netdev = NULL;
8027 }
8028 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8029err_vsi:
8030 i40e_vsi_clear(vsi);
8031 return NULL;
8032}
8033
41c445ff
JB		 8034/**
8035 * i40e_vsi_setup - Set up a VSI by a given type
8036 * @pf: board private structure
8037 * @type: VSI type
8038 * @uplink_seid: the switch element to link to
8039 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8040 *
8041 * This allocates the sw VSI structure and its queue resources, then add a VSI
8042 * to the identified VEB.
8043 *
8044 * Returns pointer to the successfully allocated and configure VSI sw struct on
8045 * success, otherwise returns NULL on failure.
8046 **/
8047struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8048 u16 uplink_seid, u32 param1)
8049{
8050 struct i40e_vsi *vsi = NULL;
8051 struct i40e_veb *veb = NULL;
8052 int ret, i;
8053 int v_idx;
8054
8055 /* The requested uplink_seid must be either
8056 * - the PF's port seid
8057 * no VEB is needed because this is the PF
8058 * or this is a Flow Director special case VSI
8059 * - seid of an existing VEB
8060 * - seid of a VSI that owns an existing VEB
8061 * - seid of a VSI that doesn't own a VEB
8062 * a new VEB is created and the VSI becomes the owner
8063 * - seid of the PF VSI, which is what creates the first VEB
8064 * this is a special case of the previous
8065 *
8066 * Find which uplink_seid we were given and create a new VEB if needed
8067 */
8068 for (i = 0; i < I40E_MAX_VEB; i++) {
8069 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8070 veb = pf->veb[i];
8071 break;
8072 }
8073 }
8074
8075 if (!veb && uplink_seid != pf->mac_seid) {
8076
505682cd 8077 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8078 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8079 vsi = pf->vsi[i];
8080 break;
8081 }
8082 }
8083 if (!vsi) {
8084 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8085 uplink_seid);
8086 return NULL;
8087 }
8088
8089 if (vsi->uplink_seid == pf->mac_seid)
8090 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8091 vsi->tc_config.enabled_tc);
8092 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8093 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8094 vsi->tc_config.enabled_tc);
8095
8096 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8097 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8098 veb = pf->veb[i];
8099 }
8100 if (!veb) {
8101 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8102 return NULL;
8103 }
8104
8105 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8106 uplink_seid = veb->seid;
8107 }
8108
8109 /* get vsi sw struct */
8110 v_idx = i40e_vsi_mem_alloc(pf, type);
8111 if (v_idx < 0)
8112 goto err_alloc;
8113 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8114 if (!vsi)
8115 goto err_alloc;
41c445ff
JB		 8116 vsi->type = type;
8117 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8118
8119 if (type == I40E_VSI_MAIN)
8120 pf->lan_vsi = v_idx;
8121 else if (type == I40E_VSI_SRIOV)
8122 vsi->vf_id = param1;
8123 /* assign it some queues */
cbf61325
ASJ		 8124 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8125 vsi->idx);
41c445ff
JB		 8126 if (ret < 0) {
8127 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
8128 vsi->seid, ret);
8129 goto err_vsi;
8130 }
8131 vsi->base_queue = ret;
8132
8133 /* get a VSI from the hardware */
8134 vsi->uplink_seid = uplink_seid;
8135 ret = i40e_add_vsi(vsi);
8136 if (ret)
8137 goto err_vsi;
8138
8139 switch (vsi->type) {
8140 /* setup the netdev if needed */
8141 case I40E_VSI_MAIN:
8142 case I40E_VSI_VMDQ2:
38e00438 8143 case I40E_VSI_FCOE:
41c445ff
JB		 8144 ret = i40e_config_netdev(vsi);
8145 if (ret)
8146 goto err_netdev;
8147 ret = register_netdev(vsi->netdev);
8148 if (ret)
8149 goto err_netdev;
8150 vsi->netdev_registered = true;
8151 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8152#ifdef CONFIG_I40E_DCB
8153 /* Setup DCB netlink interface */
8154 i40e_dcbnl_setup(vsi);
8155#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8156 /* fall through */
8157
8158 case I40E_VSI_FDIR:
8159 /* set up vectors and rings if needed */
8160 ret = i40e_vsi_setup_vectors(vsi);
8161 if (ret)
8162 goto err_msix;
8163
8164 ret = i40e_alloc_rings(vsi);
8165 if (ret)
8166 goto err_rings;
8167
8168 /* map all of the rings to the q_vectors */
8169 i40e_vsi_map_rings_to_vectors(vsi);
8170
8171 i40e_vsi_reset_stats(vsi);
8172 break;
8173
8174 default:
8175 /* no netdev or rings for the other VSI types */
8176 break;
8177 }
8178
8179 return vsi;
8180
8181err_rings:
8182 i40e_vsi_free_q_vectors(vsi);
8183err_msix:
8184 if (vsi->netdev_registered) {
8185 vsi->netdev_registered = false;
8186 unregister_netdev(vsi->netdev);
8187 free_netdev(vsi->netdev);
8188 vsi->netdev = NULL;
8189 }
8190err_netdev:
8191 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8192err_vsi:
8193 i40e_vsi_clear(vsi);
8194err_alloc:
8195 return NULL;
8196}
8197
8198/**
8199 * i40e_veb_get_bw_info - Query VEB BW information
8200 * @veb: the veb to query
8201 *
8202 * Query the Tx scheduler BW configuration data for given VEB
8203 **/
8204static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8205{
8206 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8207 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8208 struct i40e_pf *pf = veb->pf;
8209 struct i40e_hw *hw = &pf->hw;
8210 u32 tc_bw_max;
8211 int ret = 0;
8212 int i;
8213
8214 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8215 &bw_data, NULL);
8216 if (ret) {
8217 dev_info(&pf->pdev->dev,
8218 "query veb bw config failed, aq_err=%d\n",
8219 hw->aq.asq_last_status);
8220 goto out;
8221 }
8222
8223 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8224 &ets_data, NULL);
8225 if (ret) {
8226 dev_info(&pf->pdev->dev,
8227 "query veb bw ets config failed, aq_err=%d\n",
8228 hw->aq.asq_last_status);
8229 goto out;
8230 }
8231
8232 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8233 veb->bw_max_quanta = ets_data.tc_bw_max;
8234 veb->is_abs_credits = bw_data.absolute_credits_enable;
8235 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8236 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8237 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8238 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8239 veb->bw_tc_limit_credits[i] =
8240 le16_to_cpu(bw_data.tc_bw_limits[i]);
8241 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8242 }
8243
8244out:
8245 return ret;
8246}
8247
8248/**
8249 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8250 * @pf: board private structure
8251 *
8252 * On error: returns error code (negative)
8253 * On success: returns vsi index in PF (positive)
8254 **/
8255static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8256{
8257 int ret = -ENOENT;
8258 struct i40e_veb *veb;
8259 int i;
8260
8261 /* Need to protect the allocation of switch elements at the PF level */
8262 mutex_lock(&pf->switch_mutex);
8263
8264 /* VEB list may be fragmented if VEB creation/destruction has
8265 * been happening. We can afford to do a quick scan to look
8266 * for any free slots in the list.
8267 *
8268 * find next empty veb slot, looping back around if necessary
8269 */
8270 i = 0;
8271 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8272 i++;
8273 if (i >= I40E_MAX_VEB) {
8274 ret = -ENOMEM;
8275 goto err_alloc_veb; /* out of VEB slots! */
8276 }
8277
8278 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8279 if (!veb) {
8280 ret = -ENOMEM;
8281 goto err_alloc_veb;
8282 }
8283 veb->pf = pf;
8284 veb->idx = i;
8285 veb->enabled_tc = 1;
8286
8287 pf->veb[i] = veb;
8288 ret = i;
8289err_alloc_veb:
8290 mutex_unlock(&pf->switch_mutex);
8291 return ret;
8292}
8293
8294/**
8295 * i40e_switch_branch_release - Delete a branch of the switch tree
8296 * @branch: where to start deleting
8297 *
8298 * This uses recursion to find the tips of the branch to be
8299 * removed, deleting until we get back to and can delete this VEB.
8300 **/
8301static void i40e_switch_branch_release(struct i40e_veb *branch)
8302{
8303 struct i40e_pf *pf = branch->pf;
8304 u16 branch_seid = branch->seid;
8305 u16 veb_idx = branch->idx;
8306 int i;
8307
8308 /* release any VEBs on this VEB - RECURSION */
8309 for (i = 0; i < I40E_MAX_VEB; i++) {
8310 if (!pf->veb[i])
8311 continue;
8312 if (pf->veb[i]->uplink_seid == branch->seid)
8313 i40e_switch_branch_release(pf->veb[i]);
8314 }
8315
8316 /* Release the VSIs on this VEB, but not the owner VSI.
8317 *
8318 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8319 * the VEB itself, so don't use (*branch) after this loop.
8320 */
505682cd 8321 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8322 if (!pf->vsi[i])
8323 continue;
8324 if (pf->vsi[i]->uplink_seid == branch_seid &&
8325 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8326 i40e_vsi_release(pf->vsi[i]);
8327 }
8328 }
8329
8330 /* There's one corner case where the VEB might not have been
8331 * removed, so double check it here and remove it if needed.
8332 * This case happens if the veb was created from the debugfs
8333 * commands and no VSIs were added to it.
8334 */
8335 if (pf->veb[veb_idx])
8336 i40e_veb_release(pf->veb[veb_idx]);
8337}
8338
8339/**
8340 * i40e_veb_clear - remove veb struct
8341 * @veb: the veb to remove
8342 **/
8343static void i40e_veb_clear(struct i40e_veb *veb)
8344{
8345 if (!veb)
8346 return;
8347
8348 if (veb->pf) {
8349 struct i40e_pf *pf = veb->pf;
8350
8351 mutex_lock(&pf->switch_mutex);
8352 if (pf->veb[veb->idx] == veb)
8353 pf->veb[veb->idx] = NULL;
8354 mutex_unlock(&pf->switch_mutex);
8355 }
8356
8357 kfree(veb);
8358}
8359
8360/**
8361 * i40e_veb_release - Delete a VEB and free its resources
8362 * @veb: the VEB being removed
8363 **/
8364void i40e_veb_release(struct i40e_veb *veb)
8365{
8366 struct i40e_vsi *vsi = NULL;
8367 struct i40e_pf *pf;
8368 int i, n = 0;
8369
8370 pf = veb->pf;
8371
8372 /* find the remaining VSI and check for extras */
505682cd 8373 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8374 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8375 n++;
8376 vsi = pf->vsi[i];
8377 }
8378 }
8379 if (n != 1) {
8380 dev_info(&pf->pdev->dev,
8381 "can't remove VEB %d with %d VSIs left\n",
8382 veb->seid, n);
8383 return;
8384 }
8385
8386 /* move the remaining VSI to uplink veb */
8387 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8388 if (veb->uplink_seid) {
8389 vsi->uplink_seid = veb->uplink_seid;
8390 if (veb->uplink_seid == pf->mac_seid)
8391 vsi->veb_idx = I40E_NO_VEB;
8392 else
8393 vsi->veb_idx = veb->veb_idx;
8394 } else {
8395 /* floating VEB */
8396 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8397 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8398 }
8399
8400 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8401 i40e_veb_clear(veb);
41c445ff
JB		 8402}
8403
8404/**
8405 * i40e_add_veb - create the VEB in the switch
8406 * @veb: the VEB to be instantiated
8407 * @vsi: the controlling VSI
8408 **/
8409static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8410{
56747264 8411 bool is_default = false;
e1c51b95 8412 bool is_cloud = false;
41c445ff
JB		 8413 int ret;
8414
8415 /* get a VEB from the hardware */
8416 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8417 veb->enabled_tc, is_default,
8418 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8419 if (ret) {
8420 dev_info(&veb->pf->pdev->dev,
8421 "couldn't add VEB, err %d, aq_err %d\n",
8422 ret, veb->pf->hw.aq.asq_last_status);
8423 return -EPERM;
8424 }
8425
8426 /* get statistics counter */
8427 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8428 &veb->stats_idx, NULL, NULL, NULL);
8429 if (ret) {
8430 dev_info(&veb->pf->pdev->dev,
8431 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8432 ret, veb->pf->hw.aq.asq_last_status);
8433 return -EPERM;
8434 }
8435 ret = i40e_veb_get_bw_info(veb);
8436 if (ret) {
8437 dev_info(&veb->pf->pdev->dev,
8438 "couldn't get VEB bw info, err %d, aq_err %d\n",
8439 ret, veb->pf->hw.aq.asq_last_status);
8440 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8441 return -ENOENT;
8442 }
8443
8444 vsi->uplink_seid = veb->seid;
8445 vsi->veb_idx = veb->idx;
8446 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8447
8448 return 0;
8449}
8450
8451/**
8452 * i40e_veb_setup - Set up a VEB
8453 * @pf: board private structure
8454 * @flags: VEB setup flags
8455 * @uplink_seid: the switch element to link to
8456 * @vsi_seid: the initial VSI seid
8457 * @enabled_tc: Enabled TC bit-map
8458 *
8459 * This allocates the sw VEB structure and links it into the switch
8460 * It is possible and legal for this to be a duplicate of an already
8461 * existing VEB. It is also possible for both uplink and vsi seids
8462 * to be zero, in order to create a floating VEB.
8463 *
8464 * Returns pointer to the successfully allocated VEB sw struct on
8465 * success, otherwise returns NULL on failure.
8466 **/
8467struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8468 u16 uplink_seid, u16 vsi_seid,
8469 u8 enabled_tc)
8470{
8471 struct i40e_veb *veb, *uplink_veb = NULL;
8472 int vsi_idx, veb_idx;
8473 int ret;
8474
8475 /* if one seid is 0, the other must be 0 to create a floating relay */
8476 if ((uplink_seid == 0 || vsi_seid == 0) &&
8477 (uplink_seid + vsi_seid != 0)) {
8478 dev_info(&pf->pdev->dev,
8479 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8480 uplink_seid, vsi_seid);
8481 return NULL;
8482 }
8483
8484 /* make sure there is such a vsi and uplink */
505682cd 8485 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8486 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8487 break;
505682cd 8488 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8489 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8490 vsi_seid);
8491 return NULL;
8492 }
8493
8494 if (uplink_seid && uplink_seid != pf->mac_seid) {
8495 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8496 if (pf->veb[veb_idx] &&
8497 pf->veb[veb_idx]->seid == uplink_seid) {
8498 uplink_veb = pf->veb[veb_idx];
8499 break;
8500 }
8501 }
8502 if (!uplink_veb) {
8503 dev_info(&pf->pdev->dev,
8504 "uplink seid %d not found\n", uplink_seid);
8505 return NULL;
8506 }
8507 }
8508
8509 /* get veb sw struct */
8510 veb_idx = i40e_veb_mem_alloc(pf);
8511 if (veb_idx < 0)
8512 goto err_alloc;
8513 veb = pf->veb[veb_idx];
8514 veb->flags = flags;
8515 veb->uplink_seid = uplink_seid;
8516 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8517 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8518
8519 /* create the VEB in the switch */
8520 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8521 if (ret)
8522 goto err_veb;
1bb8b935
SN		 8523 if (vsi_idx == pf->lan_vsi)
8524 pf->lan_veb = veb->idx;
41c445ff
JB		 8525
8526 return veb;
8527
8528err_veb:
8529 i40e_veb_clear(veb);
8530err_alloc:
8531 return NULL;
8532}
8533
8534/**
8535 * i40e_setup_pf_switch_element - set pf vars based on switch type
8536 * @pf: board private structure
8537 * @ele: element we are building info from
8538 * @num_reported: total number of elements
8539 * @printconfig: should we print the contents
8540 *
8541 * helper function to assist in extracting a few useful SEID values.
8542 **/
8543static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8544 struct i40e_aqc_switch_config_element_resp *ele,
8545 u16 num_reported, bool printconfig)
8546{
8547 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8548 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8549 u8 element_type = ele->element_type;
8550 u16 seid = le16_to_cpu(ele->seid);
8551
8552 if (printconfig)
8553 dev_info(&pf->pdev->dev,
8554 "type=%d seid=%d uplink=%d downlink=%d\n",
8555 element_type, seid, uplink_seid, downlink_seid);
8556
8557 switch (element_type) {
8558 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8559 pf->mac_seid = seid;
8560 break;
8561 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8562 /* Main VEB? */
8563 if (uplink_seid != pf->mac_seid)
8564 break;
8565 if (pf->lan_veb == I40E_NO_VEB) {
8566 int v;
8567
8568 /* find existing or else empty VEB */
8569 for (v = 0; v < I40E_MAX_VEB; v++) {
8570 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8571 pf->lan_veb = v;
8572 break;
8573 }
8574 }
8575 if (pf->lan_veb == I40E_NO_VEB) {
8576 v = i40e_veb_mem_alloc(pf);
8577 if (v < 0)
8578 break;
8579 pf->lan_veb = v;
8580 }
8581 }
8582
8583 pf->veb[pf->lan_veb]->seid = seid;
8584 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8585 pf->veb[pf->lan_veb]->pf = pf;
8586 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8587 break;
8588 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8589 if (num_reported != 1)
8590 break;
8591 /* This is immediately after a reset so we can assume this is
8592 * the PF's VSI
8593 */
8594 pf->mac_seid = uplink_seid;
8595 pf->pf_seid = downlink_seid;
8596 pf->main_vsi_seid = seid;
8597 if (printconfig)
8598 dev_info(&pf->pdev->dev,
8599 "pf_seid=%d main_vsi_seid=%d\n",
8600 pf->pf_seid, pf->main_vsi_seid);
8601 break;
8602 case I40E_SWITCH_ELEMENT_TYPE_PF:
8603 case I40E_SWITCH_ELEMENT_TYPE_VF:
8604 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8605 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8606 case I40E_SWITCH_ELEMENT_TYPE_PE:
8607 case I40E_SWITCH_ELEMENT_TYPE_PA:
8608 /* ignore these for now */
8609 break;
8610 default:
8611 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8612 element_type, seid);
8613 break;
8614 }
8615}
8616
8617/**
8618 * i40e_fetch_switch_configuration - Get switch config from firmware
8619 * @pf: board private structure
8620 * @printconfig: should we print the contents
8621 *
8622 * Get the current switch configuration from the device and
8623 * extract a few useful SEID values.
8624 **/
8625int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8626{
8627 struct i40e_aqc_get_switch_config_resp *sw_config;
8628 u16 next_seid = 0;
8629 int ret = 0;
8630 u8 *aq_buf;
8631 int i;
8632
8633 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8634 if (!aq_buf)
8635 return -ENOMEM;
8636
8637 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8638 do {
8639 u16 num_reported, num_total;
8640
8641 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8642 I40E_AQ_LARGE_BUF,
8643 &next_seid, NULL);
8644 if (ret) {
8645 dev_info(&pf->pdev->dev,
8646 "get switch config failed %d aq_err=%x\n",
8647 ret, pf->hw.aq.asq_last_status);
8648 kfree(aq_buf);
8649 return -ENOENT;
8650 }
8651
8652 num_reported = le16_to_cpu(sw_config->header.num_reported);
8653 num_total = le16_to_cpu(sw_config->header.num_total);
8654
8655 if (printconfig)
8656 dev_info(&pf->pdev->dev,
8657 "header: %d reported %d total\n",
8658 num_reported, num_total);
8659
41c445ff
JB		 8660 for (i = 0; i < num_reported; i++) {
8661 struct i40e_aqc_switch_config_element_resp *ele =
8662 &sw_config->element[i];
8663
8664 i40e_setup_pf_switch_element(pf, ele, num_reported,
8665 printconfig);
8666 }
8667 } while (next_seid != 0);
8668
8669 kfree(aq_buf);
8670 return ret;
8671}
8672
8673/**
8674 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8675 * @pf: board private structure
bc7d338f 8676 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8677 *
8678 * Returns 0 on success, negative value on failure
8679 **/
bc7d338f 8680static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 8681{
8682 int ret;
8683
8684 /* find out what's out there already */
8685 ret = i40e_fetch_switch_configuration(pf, false);
8686 if (ret) {
8687 dev_info(&pf->pdev->dev,
8688 "couldn't fetch switch config, err %d, aq_err %d\n",
8689 ret, pf->hw.aq.asq_last_status);
8690 return ret;
8691 }
8692 i40e_pf_reset_stats(pf);
8693
41c445ff 8694 /* first time setup */
bc7d338f 8695 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8696 struct i40e_vsi *vsi = NULL;
8697 u16 uplink_seid;
8698
8699 /* Set up the PF VSI associated with the PF's main VSI
8700 * that is already in the HW switch
8701 */
8702 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8703 uplink_seid = pf->veb[pf->lan_veb]->seid;
8704 else
8705 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8706 if (pf->lan_vsi == I40E_NO_VSI)
8707 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8708 else if (reinit)
8709 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8710 if (!vsi) {
8711 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8712 i40e_fdir_teardown(pf);
8713 return -EAGAIN;
8714 }
41c445ff
JB		 8715 } else {
8716 /* force a reset of TC and queue layout configurations */
8717 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8718 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8719 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8720 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8721 }
8722 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8723
cbf61325
ASJ		 8724 i40e_fdir_sb_setup(pf);
8725
41c445ff
JB		 8726 /* Setup static PF queue filter control settings */
8727 ret = i40e_setup_pf_filter_control(pf);
8728 if (ret) {
8729 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8730 ret);
8731 /* Failure here should not stop continuing other steps */
8732 }
8733
8734 /* enable RSS in the HW, even for only one queue, as the stack can use
8735 * the hash
8736 */
8737 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8738 i40e_config_rss(pf);
8739
8740 /* fill in link information and enable LSE reporting */
a34a6711
MW		 8741 i40e_update_link_info(&pf->hw, true);
8742 i40e_link_event(pf);
8743
8744 /* Initialize user-specific link properties */
8745 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8746 I40E_AQ_AN_COMPLETED) ? true : false);
8747
8748 /* fill in link information and enable LSE reporting */
8109e123 8749 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 8750 i40e_link_event(pf);
8751
d52c20b7 8752 /* Initialize user-specific link properties */
41c445ff
JB		 8753 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8754 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 8755
beb0dff1
JK		 8756 i40e_ptp_init(pf);
8757
41c445ff
JB		 8758 return ret;
8759}
8760
41c445ff
JB		 8761/**
8762 * i40e_determine_queue_usage - Work out queue distribution
8763 * @pf: board private structure
8764 **/
8765static void i40e_determine_queue_usage(struct i40e_pf *pf)
8766{
41c445ff
JB		 8767 int queues_left;
8768
8769 pf->num_lan_qps = 0;
38e00438
VD		 8770#ifdef I40E_FCOE
8771 pf->num_fcoe_qps = 0;
8772#endif
41c445ff
JB		 8773
8774 /* Find the max queues to be put into basic use. We'll always be
8775 * using TC0, whether or not DCB is running, and TC0 will get the
8776 * big RSS set.
8777 */
8778 queues_left = pf->hw.func_caps.num_tx_qp;
8779
cbf61325 8780 if ((queues_left == 1) ||
9aa7e935 8781 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8782 /* one qp for PF, no queues for anything else */
8783 queues_left = 0;
8784 pf->rss_size = pf->num_lan_qps = 1;
8785
8786 /* make sure all the fancies are disabled */
60ea5f83 8787 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8788#ifdef I40E_FCOE
8789 I40E_FLAG_FCOE_ENABLED |
8790#endif
60ea5f83
JB		 8791 I40E_FLAG_FD_SB_ENABLED |
8792 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8793 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8794 I40E_FLAG_SRIOV_ENABLED |
8795 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8796 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8797 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8798 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8799 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8800 /* one qp for PF */
8801 pf->rss_size = pf->num_lan_qps = 1;
8802 queues_left -= pf->num_lan_qps;
8803
8804 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8805#ifdef I40E_FCOE
8806 I40E_FLAG_FCOE_ENABLED |
8807#endif
9aa7e935
FZ		 8808 I40E_FLAG_FD_SB_ENABLED |
8809 I40E_FLAG_FD_ATR_ENABLED |
8810 I40E_FLAG_DCB_ENABLED |
8811 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8812 } else {
cbf61325 8813 /* Not enough queues for all TCs */
4d9b6043 8814 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8815 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8816 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8817 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8818 }
8819 pf->num_lan_qps = pf->rss_size_max;
8820 queues_left -= pf->num_lan_qps;
8821 }
8822
38e00438
VD		 8823#ifdef I40E_FCOE
8824 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
8825 if (I40E_DEFAULT_FCOE <= queues_left) {
8826 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
8827 } else if (I40E_MINIMUM_FCOE <= queues_left) {
8828 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
8829 } else {
8830 pf->num_fcoe_qps = 0;
8831 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
8832 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
8833 }
8834
8835 queues_left -= pf->num_fcoe_qps;
8836 }
8837
8838#endif
cbf61325
ASJ		 8839 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8840 if (queues_left > 1) {
8841 queues_left -= 1; /* save 1 queue for FD */
8842 } else {
8843 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8844 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8845 }
41c445ff
JB		 8846 }
8847
8848 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8849 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8850 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8851 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8852 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8853 }
8854
8855 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8856 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8857 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8858 (queues_left / pf->num_vmdq_qps));
8859 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8860 }
8861
f8ff1464 8862 pf->queues_left = queues_left;
38e00438
VD		 8863#ifdef I40E_FCOE
8864 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
8865#endif
41c445ff
JB		 8866}
8867
8868/**
8869 * i40e_setup_pf_filter_control - Setup PF static filter control
8870 * @pf: PF to be setup
8871 *
8872 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8873 * settings. If PE/FCoE are enabled then it will also set the per PF
8874 * based filter sizes required for them. It also enables Flow director,
8875 * ethertype and macvlan type filter settings for the pf.
8876 *
8877 * Returns 0 on success, negative on failure
8878 **/
8879static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8880{
8881 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8882
8883 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8884
8885 /* Flow Director is enabled */
60ea5f83 8886 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8887 settings->enable_fdir = true;
8888
8889 /* Ethtype and MACVLAN filters enabled for PF */
8890 settings->enable_ethtype = true;
8891 settings->enable_macvlan = true;
8892
8893 if (i40e_set_filter_control(&pf->hw, settings))
8894 return -ENOENT;
8895
8896 return 0;
8897}
8898
0c22b3dd
JB		 8899#define INFO_STRING_LEN 255
8900static void i40e_print_features(struct i40e_pf *pf)
8901{
8902 struct i40e_hw *hw = &pf->hw;
8903 char *buf, *string;
8904
8905 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8906 if (!string) {
8907 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8908 return;
8909 }
8910
8911 buf = string;
8912
8913 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8914#ifdef CONFIG_PCI_IOV
8915 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8916#endif
8917 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8918 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8919
8920 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8921 buf += sprintf(buf, "RSS ");
0c22b3dd 8922 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8923 buf += sprintf(buf, "FD_ATR ");
8924 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8925 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8926 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8927 }
4d9b6043 8928 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8929 buf += sprintf(buf, "DCB ");
8930 if (pf->flags & I40E_FLAG_PTP)
8931 buf += sprintf(buf, "PTP ");
38e00438
VD		 8932#ifdef I40E_FCOE
8933 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
8934 buf += sprintf(buf, "FCOE ");
8935#endif
0c22b3dd
JB		 8936
8937 BUG_ON(buf > (string + INFO_STRING_LEN));
8938 dev_info(&pf->pdev->dev, "%s\n", string);
8939 kfree(string);
8940}
8941
41c445ff
JB		 8942/**
8943 * i40e_probe - Device initialization routine
8944 * @pdev: PCI device information struct
8945 * @ent: entry in i40e_pci_tbl
8946 *
8947 * i40e_probe initializes a pf identified by a pci_dev structure.
8948 * The OS initialization, configuring of the pf private structure,
8949 * and a hardware reset occur.
8950 *
8951 * Returns 0 on success, negative on failure
8952 **/
8953static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8954{
41c445ff
JB		 8955 struct i40e_pf *pf;
8956 struct i40e_hw *hw;
93cd765b 8957 static u16 pfs_found;
d4dfb81a 8958 u16 link_status;
41c445ff
JB		 8959 int err = 0;
8960 u32 len;
8a9eb7d3 8961 u32 i;
41c445ff
JB		 8962
8963 err = pci_enable_device_mem(pdev);
8964 if (err)
8965 return err;
8966
8967 /* set up for high or low dma */
6494294f 8968 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8969 if (err) {
e3e3bfdd
JS		 8970 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8971 if (err) {
8972 dev_err(&pdev->dev,
8973 "DMA configuration failed: 0x%x\n", err);
8974 goto err_dma;
8975 }
41c445ff
JB		 8976 }
8977
8978 /* set up pci connections */
8979 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8980 IORESOURCE_MEM), i40e_driver_name);
8981 if (err) {
8982 dev_info(&pdev->dev,
8983 "pci_request_selected_regions failed %d\n", err);
8984 goto err_pci_reg;
8985 }
8986
8987 pci_enable_pcie_error_reporting(pdev);
8988 pci_set_master(pdev);
8989
8990 /* Now that we have a PCI connection, we need to do the
8991 * low level device setup. This is primarily setting up
8992 * the Admin Queue structures and then querying for the
8993 * device's current profile information.
8994 */
8995 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8996 if (!pf) {
8997 err = -ENOMEM;
8998 goto err_pf_alloc;
8999 }
9000 pf->next_vsi = 0;
9001 pf->pdev = pdev;
9002 set_bit(__I40E_DOWN, &pf->state);
9003
9004 hw = &pf->hw;
9005 hw->back = pf;
9006 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9007 pci_resource_len(pdev, 0));
9008 if (!hw->hw_addr) {
9009 err = -EIO;
9010 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9011 (unsigned int)pci_resource_start(pdev, 0),
9012 (unsigned int)pci_resource_len(pdev, 0), err);
9013 goto err_ioremap;
9014 }
9015 hw->vendor_id = pdev->vendor;
9016 hw->device_id = pdev->device;
9017 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9018 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9019 hw->subsystem_device_id = pdev->subsystem_device;
9020 hw->bus.device = PCI_SLOT(pdev->devfn);
9021 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9022 pf->instance = pfs_found;
41c445ff 9023
7134f9ce
JB		 9024 /* do a special CORER for clearing PXE mode once at init */
9025 if (hw->revision_id == 0 &&
9026 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9027 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9028 i40e_flush(hw);
9029 msleep(200);
9030 pf->corer_count++;
9031
9032 i40e_clear_pxe_mode(hw);
9033 }
9034
41c445ff 9035 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9036 i40e_clear_hw(hw);
41c445ff
JB		 9037 err = i40e_pf_reset(hw);
9038 if (err) {
9039 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9040 goto err_pf_reset;
9041 }
9042 pf->pfr_count++;
9043
9044 hw->aq.num_arq_entries = I40E_AQ_LEN;
9045 hw->aq.num_asq_entries = I40E_AQ_LEN;
9046 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9047 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9048 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
9049 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
9050 "%s-pf%d:misc",
9051 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
9052
9053 err = i40e_init_shared_code(hw);
9054 if (err) {
9055 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9056 goto err_pf_reset;
9057 }
9058
d52c20b7
JB		 9059 /* set up a default setting for link flow control */
9060 pf->hw.fc.requested_mode = I40E_FC_NONE;
9061
41c445ff
JB		 9062 err = i40e_init_adminq(hw);
9063 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9064 if (err) {
9065 dev_info(&pdev->dev,
7aa67613 9066 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9067 goto err_pf_reset;
9068 }
9069
7aa67613
CS		 9070 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9071 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9072 dev_info(&pdev->dev,
7aa67613
CS		 9073 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9074 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9075 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9076 dev_info(&pdev->dev,
7aa67613 9077 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9078
9079
4eb3f768
SN		 9080 i40e_verify_eeprom(pf);
9081
2c5fe33b
JB		 9082 /* Rev 0 hardware was never productized */
9083 if (hw->revision_id < 1)
9084 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9085
6ff4ef86 9086 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9087 err = i40e_get_capabilities(pf);
9088 if (err)
9089 goto err_adminq_setup;
9090
9091 err = i40e_sw_init(pf);
9092 if (err) {
9093 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9094 goto err_sw_init;
9095 }
9096
9097 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9098 hw->func_caps.num_rx_qp,
9099 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9100 if (err) {
9101 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9102 goto err_init_lan_hmc;
9103 }
9104
9105 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9106 if (err) {
9107 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9108 err = -ENOENT;
9109 goto err_configure_lan_hmc;
9110 }
9111
9112 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9113 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9114 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9115 err = -EIO;
9116 goto err_mac_addr;
9117 }
9118 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9119 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9120 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9121 if (is_valid_ether_addr(hw->mac.port_addr))
9122 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9123#ifdef I40E_FCOE
9124 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9125 if (err)
9126 dev_info(&pdev->dev,
9127 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9128 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9129 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9130 hw->mac.san_addr);
9131 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9132 }
9133 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9134#endif /* I40E_FCOE */
41c445ff
JB		 9135
9136 pci_set_drvdata(pdev, pf);
9137 pci_save_state(pdev);
4e3b35b0
NP		 9138#ifdef CONFIG_I40E_DCB
9139 err = i40e_init_pf_dcb(pf);
9140 if (err) {
9141 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 9142 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9143 /* Continue without DCB enabled */
4e3b35b0
NP		 9144 }
9145#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9146
9147 /* set up periodic task facility */
9148 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9149 pf->service_timer_period = HZ;
9150
9151 INIT_WORK(&pf->service_task, i40e_service_task);
9152 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9153 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9154 pf->link_check_timeout = jiffies;
9155
8e2773ae
SN		 9156 /* WoL defaults to disabled */
9157 pf->wol_en = false;
9158 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9159
41c445ff
JB		 9160 /* set up the main switch operations */
9161 i40e_determine_queue_usage(pf);
9162 i40e_init_interrupt_scheme(pf);
9163
505682cd
MW		 9164 /* The number of VSIs reported by the FW is the minimum guaranteed
9165 * to us; HW supports far more and we share the remaining pool with
9166 * the other PFs. We allocate space for more than the guarantee with
9167 * the understanding that we might not get them all later.
41c445ff 9168 */
505682cd
MW		 9169 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9170 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9171 else
9172 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9173
9174 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9175 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9176 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9177 if (!pf->vsi) {
9178 err = -ENOMEM;
41c445ff 9179 goto err_switch_setup;
ed87ac09 9180 }
41c445ff 9181
bc7d338f 9182 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9183 if (err) {
9184 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9185 goto err_vsis;
9186 }
8a9eb7d3 9187 /* if FDIR VSI was set up, start it now */
505682cd 9188 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9189 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9190 i40e_vsi_open(pf->vsi[i]);
9191 break;
9192 }
9193 }
41c445ff 9194
7e2453fe
JB		 9195 /* driver is only interested in link up/down and module qualification
9196 * reports from firmware
9197 */
9198 err = i40e_aq_set_phy_int_mask(&pf->hw,
9199 I40E_AQ_EVENT_LINK_UPDOWN |
9200 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9201 if (err)
9202 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9203
cafa2ee6
ASJ		 9204 msleep(75);
9205 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9206 if (err) {
9207 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9208 pf->hw.aq.asq_last_status);
9209 }
9210
41c445ff
JB		 9211 /* The main driver is (mostly) up and happy. We need to set this state
9212 * before setting up the misc vector or we get a race and the vector
9213 * ends up disabled forever.
9214 */
9215 clear_bit(__I40E_DOWN, &pf->state);
9216
9217 /* In case of MSIX we are going to setup the misc vector right here
9218 * to handle admin queue events etc. In case of legacy and MSI
9219 * the misc functionality and queue processing is combined in
9220 * the same vector and that gets setup at open.
9221 */
9222 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9223 err = i40e_setup_misc_vector(pf);
9224 if (err) {
9225 dev_info(&pdev->dev,
9226 "setup of misc vector failed: %d\n", err);
9227 goto err_vsis;
9228 }
9229 }
9230
df805f62 9231#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9232 /* prep for VF support */
9233 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9234 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9235 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9236 u32 val;
9237
9238 /* disable link interrupts for VFs */
9239 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9240 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9241 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9242 i40e_flush(hw);
4aeec010
MW		 9243
9244 if (pci_num_vf(pdev)) {
9245 dev_info(&pdev->dev,
9246 "Active VFs found, allocating resources.\n");
9247 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9248 if (err)
9249 dev_info(&pdev->dev,
9250 "Error %d allocating resources for existing VFs\n",
9251 err);
9252 }
41c445ff 9253 }
df805f62 9254#endif /* CONFIG_PCI_IOV */
41c445ff 9255
93cd765b
ASJ		 9256 pfs_found++;
9257
41c445ff
JB		 9258 i40e_dbg_pf_init(pf);
9259
9260 /* tell the firmware that we're starting */
44033fac 9261 i40e_send_version(pf);
41c445ff
JB		 9262
9263 /* since everything's happy, start the service_task timer */
9264 mod_timer(&pf->service_timer,
9265 round_jiffies(jiffies + pf->service_timer_period));
9266
38e00438
VD		 9267#ifdef I40E_FCOE
9268 /* create FCoE interface */
9269 i40e_fcoe_vsi_setup(pf);
9270
9271#endif
d4dfb81a
CS		 9272 /* Get the negotiated link width and speed from PCI config space */
9273 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9274
9275 i40e_set_pci_config_data(hw, link_status);
9276
69bfb110 9277 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9278 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9279 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9280 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9281 "Unknown"),
9282 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9283 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9284 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9285 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9286 "Unknown"));
9287
9288 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9289 hw->bus.speed < i40e_bus_speed_8000) {
9290 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9291 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9292 }
9293
0c22b3dd
JB		 9294 /* print a string summarizing features */
9295 i40e_print_features(pf);
9296
41c445ff
JB		 9297 return 0;
9298
9299 /* Unwind what we've done if something failed in the setup */
9300err_vsis:
9301 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9302 i40e_clear_interrupt_scheme(pf);
9303 kfree(pf->vsi);
04b03013
SN		 9304err_switch_setup:
9305 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9306 del_timer_sync(&pf->service_timer);
9307err_mac_addr:
9308err_configure_lan_hmc:
9309 (void)i40e_shutdown_lan_hmc(hw);
9310err_init_lan_hmc:
9311 kfree(pf->qp_pile);
9312 kfree(pf->irq_pile);
9313err_sw_init:
9314err_adminq_setup:
9315 (void)i40e_shutdown_adminq(hw);
9316err_pf_reset:
9317 iounmap(hw->hw_addr);
9318err_ioremap:
9319 kfree(pf);
9320err_pf_alloc:
9321 pci_disable_pcie_error_reporting(pdev);
9322 pci_release_selected_regions(pdev,
9323 pci_select_bars(pdev, IORESOURCE_MEM));
9324err_pci_reg:
9325err_dma:
9326 pci_disable_device(pdev);
9327 return err;
9328}
9329
9330/**
9331 * i40e_remove - Device removal routine
9332 * @pdev: PCI device information struct
9333 *
9334 * i40e_remove is called by the PCI subsystem to alert the driver
9335 * that is should release a PCI device. This could be caused by a
9336 * Hot-Plug event, or because the driver is going to be removed from
9337 * memory.
9338 **/
9339static void i40e_remove(struct pci_dev *pdev)
9340{
9341 struct i40e_pf *pf = pci_get_drvdata(pdev);
9342 i40e_status ret_code;
41c445ff
JB		 9343 int i;
9344
9345 i40e_dbg_pf_exit(pf);
9346
beb0dff1
JK		 9347 i40e_ptp_stop(pf);
9348
41c445ff
JB		 9349 /* no more scheduling of any task */
9350 set_bit(__I40E_DOWN, &pf->state);
9351 del_timer_sync(&pf->service_timer);
9352 cancel_work_sync(&pf->service_task);
9353
eb2d80bc
MW		 9354 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9355 i40e_free_vfs(pf);
9356 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9357 }
9358
41c445ff
JB		 9359 i40e_fdir_teardown(pf);
9360
9361 /* If there is a switch structure or any orphans, remove them.
9362 * This will leave only the PF's VSI remaining.
9363 */
9364 for (i = 0; i < I40E_MAX_VEB; i++) {
9365 if (!pf->veb[i])
9366 continue;
9367
9368 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9369 pf->veb[i]->uplink_seid == 0)
9370 i40e_switch_branch_release(pf->veb[i]);
9371 }
9372
9373 /* Now we can shutdown the PF's VSI, just before we kill
9374 * adminq and hmc.
9375 */
9376 if (pf->vsi[pf->lan_vsi])
9377 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9378
9379 i40e_stop_misc_vector(pf);
9380 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9381 synchronize_irq(pf->msix_entries[0].vector);
9382 free_irq(pf->msix_entries[0].vector, pf);
9383 }
9384
9385 /* shutdown and destroy the HMC */
60442dea
SN		 9386 if (pf->hw.hmc.hmc_obj) {
9387 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9388 if (ret_code)
9389 dev_warn(&pdev->dev,
9390 "Failed to destroy the HMC resources: %d\n",
9391 ret_code);
9392 }
41c445ff
JB		 9393
9394 /* shutdown the adminq */
41c445ff
JB		 9395 ret_code = i40e_shutdown_adminq(&pf->hw);
9396 if (ret_code)
9397 dev_warn(&pdev->dev,
9398 "Failed to destroy the Admin Queue resources: %d\n",
9399 ret_code);
9400
9401 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9402 i40e_clear_interrupt_scheme(pf);
505682cd 9403 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9404 if (pf->vsi[i]) {
9405 i40e_vsi_clear_rings(pf->vsi[i]);
9406 i40e_vsi_clear(pf->vsi[i]);
9407 pf->vsi[i] = NULL;
9408 }
9409 }
9410
9411 for (i = 0; i < I40E_MAX_VEB; i++) {
9412 kfree(pf->veb[i]);
9413 pf->veb[i] = NULL;
9414 }
9415
9416 kfree(pf->qp_pile);
9417 kfree(pf->irq_pile);
41c445ff
JB		 9418 kfree(pf->vsi);
9419
41c445ff
JB		 9420 iounmap(pf->hw.hw_addr);
9421 kfree(pf);
9422 pci_release_selected_regions(pdev,
9423 pci_select_bars(pdev, IORESOURCE_MEM));
9424
9425 pci_disable_pcie_error_reporting(pdev);
9426 pci_disable_device(pdev);
9427}
9428
9429/**
9430 * i40e_pci_error_detected - warning that something funky happened in PCI land
9431 * @pdev: PCI device information struct
9432 *
9433 * Called to warn that something happened and the error handling steps
9434 * are in progress. Allows the driver to quiesce things, be ready for
9435 * remediation.
9436 **/
9437static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9438 enum pci_channel_state error)
9439{
9440 struct i40e_pf *pf = pci_get_drvdata(pdev);
9441
9442 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9443
9444 /* shutdown all operations */
9007bccd
SN		 9445 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9446 rtnl_lock();
9447 i40e_prep_for_reset(pf);
9448 rtnl_unlock();
9449 }
41c445ff
JB		 9450
9451 /* Request a slot reset */
9452 return PCI_ERS_RESULT_NEED_RESET;
9453}
9454
9455/**
9456 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9457 * @pdev: PCI device information struct
9458 *
9459 * Called to find if the driver can work with the device now that
9460 * the pci slot has been reset. If a basic connection seems good
9461 * (registers are readable and have sane content) then return a
9462 * happy little PCI_ERS_RESULT_xxx.
9463 **/
9464static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9465{
9466 struct i40e_pf *pf = pci_get_drvdata(pdev);
9467 pci_ers_result_t result;
9468 int err;
9469 u32 reg;
9470
9471 dev_info(&pdev->dev, "%s\n", __func__);
9472 if (pci_enable_device_mem(pdev)) {
9473 dev_info(&pdev->dev,
9474 "Cannot re-enable PCI device after reset.\n");
9475 result = PCI_ERS_RESULT_DISCONNECT;
9476 } else {
9477 pci_set_master(pdev);
9478 pci_restore_state(pdev);
9479 pci_save_state(pdev);
9480 pci_wake_from_d3(pdev, false);
9481
9482 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9483 if (reg == 0)
9484 result = PCI_ERS_RESULT_RECOVERED;
9485 else
9486 result = PCI_ERS_RESULT_DISCONNECT;
9487 }
9488
9489 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9490 if (err) {
9491 dev_info(&pdev->dev,
9492 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9493 err);
9494 /* non-fatal, continue */
9495 }
9496
9497 return result;
9498}
9499
9500/**
9501 * i40e_pci_error_resume - restart operations after PCI error recovery
9502 * @pdev: PCI device information struct
9503 *
9504 * Called to allow the driver to bring things back up after PCI error
9505 * and/or reset recovery has finished.
9506 **/
9507static void i40e_pci_error_resume(struct pci_dev *pdev)
9508{
9509 struct i40e_pf *pf = pci_get_drvdata(pdev);
9510
9511 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9512 if (test_bit(__I40E_SUSPENDED, &pf->state))
9513 return;
9514
9515 rtnl_lock();
41c445ff 9516 i40e_handle_reset_warning(pf);
9007bccd
SN		 9517 rtnl_lock();
9518}
9519
9520/**
9521 * i40e_shutdown - PCI callback for shutting down
9522 * @pdev: PCI device information struct
9523 **/
9524static void i40e_shutdown(struct pci_dev *pdev)
9525{
9526 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9527 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9528
9529 set_bit(__I40E_SUSPENDED, &pf->state);
9530 set_bit(__I40E_DOWN, &pf->state);
9531 rtnl_lock();
9532 i40e_prep_for_reset(pf);
9533 rtnl_unlock();
9534
8e2773ae
SN		 9535 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9536 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9537
9007bccd 9538 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9539 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9540 pci_set_power_state(pdev, PCI_D3hot);
9541 }
9542}
9543
9544#ifdef CONFIG_PM
9545/**
9546 * i40e_suspend - PCI callback for moving to D3
9547 * @pdev: PCI device information struct
9548 **/
9549static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9550{
9551 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9552 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9553
9554 set_bit(__I40E_SUSPENDED, &pf->state);
9555 set_bit(__I40E_DOWN, &pf->state);
9556 rtnl_lock();
9557 i40e_prep_for_reset(pf);
9558 rtnl_unlock();
9559
8e2773ae
SN		 9560 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9561 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9562
9563 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9564 pci_set_power_state(pdev, PCI_D3hot);
9565
9566 return 0;
41c445ff
JB		 9567}
9568
9007bccd
SN		 9569/**
9570 * i40e_resume - PCI callback for waking up from D3
9571 * @pdev: PCI device information struct
9572 **/
9573static int i40e_resume(struct pci_dev *pdev)
9574{
9575 struct i40e_pf *pf = pci_get_drvdata(pdev);
9576 u32 err;
9577
9578 pci_set_power_state(pdev, PCI_D0);
9579 pci_restore_state(pdev);
9580 /* pci_restore_state() clears dev->state_saves, so
9581 * call pci_save_state() again to restore it.
9582 */
9583 pci_save_state(pdev);
9584
9585 err = pci_enable_device_mem(pdev);
9586 if (err) {
9587 dev_err(&pdev->dev,
9588 "%s: Cannot enable PCI device from suspend\n",
9589 __func__);
9590 return err;
9591 }
9592 pci_set_master(pdev);
9593
9594 /* no wakeup events while running */
9595 pci_wake_from_d3(pdev, false);
9596
9597 /* handling the reset will rebuild the device state */
9598 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9599 clear_bit(__I40E_DOWN, &pf->state);
9600 rtnl_lock();
9601 i40e_reset_and_rebuild(pf, false);
9602 rtnl_unlock();
9603 }
9604
9605 return 0;
9606}
9607
9608#endif
41c445ff
JB		 9609static const struct pci_error_handlers i40e_err_handler = {
9610 .error_detected = i40e_pci_error_detected,
9611 .slot_reset = i40e_pci_error_slot_reset,
9612 .resume = i40e_pci_error_resume,
9613};
9614
9615static struct pci_driver i40e_driver = {
9616 .name = i40e_driver_name,
9617 .id_table = i40e_pci_tbl,
9618 .probe = i40e_probe,
9619 .remove = i40e_remove,
9007bccd
SN		 9620#ifdef CONFIG_PM
9621 .suspend = i40e_suspend,
9622 .resume = i40e_resume,
9623#endif
9624 .shutdown = i40e_shutdown,
41c445ff
JB		 9625 .err_handler = &i40e_err_handler,
9626 .sriov_configure = i40e_pci_sriov_configure,
9627};
9628
9629/**
9630 * i40e_init_module - Driver registration routine
9631 *
9632 * i40e_init_module is the first routine called when the driver is
9633 * loaded. All it does is register with the PCI subsystem.
9634 **/
9635static int __init i40e_init_module(void)
9636{
9637 pr_info("%s: %s - version %s\n", i40e_driver_name,
9638 i40e_driver_string, i40e_driver_version_str);
9639 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9640 i40e_dbg_init();
9641 return pci_register_driver(&i40e_driver);
9642}
9643module_init(i40e_init_module);
9644
9645/**
9646 * i40e_exit_module - Driver exit cleanup routine
9647 *
9648 * i40e_exit_module is called just before the driver is removed
9649 * from memory.
9650 **/
9651static void __exit i40e_exit_module(void)
9652{
9653 pci_unregister_driver(&i40e_driver);
9654 i40e_dbg_exit();
9655}
9656module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)