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i40e/i40evf: update AdminQ API
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
acb3676b 42#define DRV_VERSION_BUILD 41
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
83
84#define I40E_MAX_VF_COUNT 128
85static int debug = -1;
86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
90MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/**
95 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
96 * @hw: pointer to the HW structure
97 * @mem: ptr to mem struct to fill out
98 * @size: size of memory requested
99 * @alignment: what to align the allocation to
100 **/
101int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
102 u64 size, u32 alignment)
103{
104 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
105
106 mem->size = ALIGN(size, alignment);
107 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
108 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 109 if (!mem->va)
110 return -ENOMEM;
41c445ff 111
93bc73b8 112 return 0;
41c445ff
JB		 113}
114
115/**
116 * i40e_free_dma_mem_d - OS specific memory free for shared code
117 * @hw: pointer to the HW structure
118 * @mem: ptr to mem struct to free
119 **/
120int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
125 mem->va = NULL;
126 mem->pa = 0;
127 mem->size = 0;
128
129 return 0;
130}
131
132/**
133 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
134 * @hw: pointer to the HW structure
135 * @mem: ptr to mem struct to fill out
136 * @size: size of memory requested
137 **/
138int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
139 u32 size)
140{
141 mem->size = size;
142 mem->va = kzalloc(size, GFP_KERNEL);
143
93bc73b8
JB		 144 if (!mem->va)
145 return -ENOMEM;
41c445ff 146
93bc73b8 147 return 0;
41c445ff
JB		 148}
149
150/**
151 * i40e_free_virt_mem_d - OS specific memory free for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to free
154 **/
155int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
156{
157 /* it's ok to kfree a NULL pointer */
158 kfree(mem->va);
159 mem->va = NULL;
160 mem->size = 0;
161
162 return 0;
163}
164
165/**
166 * i40e_get_lump - find a lump of free generic resource
167 * @pf: board private structure
168 * @pile: the pile of resource to search
169 * @needed: the number of items needed
170 * @id: an owner id to stick on the items assigned
171 *
172 * Returns the base item index of the lump, or negative for error
173 *
174 * The search_hint trick and lack of advanced fit-finding only work
175 * because we're highly likely to have all the same size lump requests.
176 * Linear search time and any fragmentation should be minimal.
177 **/
178static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
179 u16 needed, u16 id)
180{
181 int ret = -ENOMEM;
ddf434ac 182 int i, j;
41c445ff
JB		 183
184 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
185 dev_info(&pf->pdev->dev,
186 "param err: pile=%p needed=%d id=0x%04x\n",
187 pile, needed, id);
188 return -EINVAL;
189 }
190
191 /* start the linear search with an imperfect hint */
192 i = pile->search_hint;
ddf434ac 193 while (i < pile->num_entries) {
41c445ff
JB		 194 /* skip already allocated entries */
195 if (pile->list[i] & I40E_PILE_VALID_BIT) {
196 i++;
197 continue;
198 }
199
200 /* do we have enough in this lump? */
201 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
202 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
203 break;
204 }
205
206 if (j == needed) {
207 /* there was enough, so assign it to the requestor */
208 for (j = 0; j < needed; j++)
209 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
210 ret = i;
211 pile->search_hint = i + j;
ddf434ac 212 break;
41c445ff
JB		 213 } else {
214 /* not enough, so skip over it and continue looking */
215 i += j;
216 }
217 }
218
219 return ret;
220}
221
222/**
223 * i40e_put_lump - return a lump of generic resource
224 * @pile: the pile of resource to search
225 * @index: the base item index
226 * @id: the owner id of the items assigned
227 *
228 * Returns the count of items in the lump
229 **/
230static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
231{
232 int valid_id = (id | I40E_PILE_VALID_BIT);
233 int count = 0;
234 int i;
235
236 if (!pile || index >= pile->num_entries)
237 return -EINVAL;
238
239 for (i = index;
240 i < pile->num_entries && pile->list[i] == valid_id;
241 i++) {
242 pile->list[i] = 0;
243 count++;
244 }
245
246 if (count && index < pile->search_hint)
247 pile->search_hint = index;
248
249 return count;
250}
251
252/**
253 * i40e_service_event_schedule - Schedule the service task to wake up
254 * @pf: board private structure
255 *
256 * If not already scheduled, this puts the task into the work queue
257 **/
258static void i40e_service_event_schedule(struct i40e_pf *pf)
259{
260 if (!test_bit(__I40E_DOWN, &pf->state) &&
261 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
262 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
263 schedule_work(&pf->service_task);
264}
265
266/**
267 * i40e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 *
270 * If any port has noticed a Tx timeout, it is likely that the whole
271 * device is munged, not just the one netdev port, so go for the full
272 * reset.
273 **/
274static void i40e_tx_timeout(struct net_device *netdev)
275{
276 struct i40e_netdev_priv *np = netdev_priv(netdev);
277 struct i40e_vsi *vsi = np->vsi;
278 struct i40e_pf *pf = vsi->back;
279
280 pf->tx_timeout_count++;
281
282 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
283 pf->tx_timeout_recovery_level = 0;
284 pf->tx_timeout_last_recovery = jiffies;
285 netdev_info(netdev, "tx_timeout recovery level %d\n",
286 pf->tx_timeout_recovery_level);
287
288 switch (pf->tx_timeout_recovery_level) {
289 case 0:
290 /* disable and re-enable queues for the VSI */
291 if (in_interrupt()) {
292 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
293 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
294 } else {
295 i40e_vsi_reinit_locked(vsi);
296 }
297 break;
298 case 1:
299 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
300 break;
301 case 2:
302 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
303 break;
304 case 3:
305 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
306 break;
307 default:
308 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 309 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 310 i40e_down(vsi);
311 break;
312 }
313 i40e_service_event_schedule(pf);
314 pf->tx_timeout_recovery_level++;
315}
316
317/**
318 * i40e_release_rx_desc - Store the new tail and head values
319 * @rx_ring: ring to bump
320 * @val: new head index
321 **/
322static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
323{
324 rx_ring->next_to_use = val;
325
326 /* Force memory writes to complete before letting h/w
327 * know there are new descriptors to fetch. (Only
328 * applicable for weak-ordered memory model archs,
329 * such as IA-64).
330 */
331 wmb();
332 writel(val, rx_ring->tail);
333}
334
335/**
336 * i40e_get_vsi_stats_struct - Get System Network Statistics
337 * @vsi: the VSI we care about
338 *
339 * Returns the address of the device statistics structure.
340 * The statistics are actually updated from the service task.
341 **/
342struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
343{
344 return &vsi->net_stats;
345}
346
347/**
348 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
349 * @netdev: network interface device structure
350 *
351 * Returns the address of the device statistics structure.
352 * The statistics are actually updated from the service task.
353 **/
354static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
355 struct net_device *netdev,
980e9b11 356 struct rtnl_link_stats64 *stats)
41c445ff
JB		 357{
358 struct i40e_netdev_priv *np = netdev_priv(netdev);
359 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 360 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
361 int i;
362
bc7d338f
ASJ		 363 if (test_bit(__I40E_DOWN, &vsi->state))
364 return stats;
365
3c325ced
JB		 366 if (!vsi->tx_rings)
367 return stats;
368
980e9b11
AD		 369 rcu_read_lock();
370 for (i = 0; i < vsi->num_queue_pairs; i++) {
371 struct i40e_ring *tx_ring, *rx_ring;
372 u64 bytes, packets;
373 unsigned int start;
374
375 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
376 if (!tx_ring)
377 continue;
378
379 do {
57a7744e 380 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 381 packets = tx_ring->stats.packets;
382 bytes = tx_ring->stats.bytes;
57a7744e 383 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 384
385 stats->tx_packets += packets;
386 stats->tx_bytes += bytes;
387 rx_ring = &tx_ring[1];
388
389 do {
57a7744e 390 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 391 packets = rx_ring->stats.packets;
392 bytes = rx_ring->stats.bytes;
57a7744e 393 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 394
980e9b11
AD		 395 stats->rx_packets += packets;
396 stats->rx_bytes += bytes;
397 }
398 rcu_read_unlock();
399
400 /* following stats updated by ixgbe_watchdog_task() */
401 stats->multicast = vsi_stats->multicast;
402 stats->tx_errors = vsi_stats->tx_errors;
403 stats->tx_dropped = vsi_stats->tx_dropped;
404 stats->rx_errors = vsi_stats->rx_errors;
405 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
406 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 407
980e9b11 408 return stats;
41c445ff
JB		 409}
410
411/**
412 * i40e_vsi_reset_stats - Resets all stats of the given vsi
413 * @vsi: the VSI to have its stats reset
414 **/
415void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
416{
417 struct rtnl_link_stats64 *ns;
418 int i;
419
420 if (!vsi)
421 return;
422
423 ns = i40e_get_vsi_stats_struct(vsi);
424 memset(ns, 0, sizeof(*ns));
425 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
426 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
427 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 428 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 429 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 430 memset(&vsi->rx_rings[i]->stats, 0 ,
431 sizeof(vsi->rx_rings[i]->stats));
432 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
433 sizeof(vsi->rx_rings[i]->rx_stats));
434 memset(&vsi->tx_rings[i]->stats, 0 ,
435 sizeof(vsi->tx_rings[i]->stats));
436 memset(&vsi->tx_rings[i]->tx_stats, 0,
437 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 438 }
8e9dca53 439 }
41c445ff
JB		 440 vsi->stat_offsets_loaded = false;
441}
442
443/**
444 * i40e_pf_reset_stats - Reset all of the stats for the given pf
445 * @pf: the PF to be reset
446 **/
447void i40e_pf_reset_stats(struct i40e_pf *pf)
448{
449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
452}
453
454/**
455 * i40e_stat_update48 - read and update a 48 bit stat from the chip
456 * @hw: ptr to the hardware info
457 * @hireg: the high 32 bit reg to read
458 * @loreg: the low 32 bit reg to read
459 * @offset_loaded: has the initial offset been loaded yet
460 * @offset: ptr to current offset value
461 * @stat: ptr to the stat
462 *
463 * Since the device stats are not reset at PFReset, they likely will not
464 * be zeroed when the driver starts. We'll save the first values read
465 * and use them as offsets to be subtracted from the raw values in order
466 * to report stats that count from zero. In the process, we also manage
467 * the potential roll-over.
468 **/
469static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
470 bool offset_loaded, u64 *offset, u64 *stat)
471{
472 u64 new_data;
473
ab60085e 474 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 475 new_data = rd32(hw, loreg);
476 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
477 } else {
478 new_data = rd64(hw, loreg);
479 }
480 if (!offset_loaded)
481 *offset = new_data;
482 if (likely(new_data >= *offset))
483 *stat = new_data - *offset;
484 else
485 *stat = (new_data + ((u64)1 << 48)) - *offset;
486 *stat &= 0xFFFFFFFFFFFFULL;
487}
488
489/**
490 * i40e_stat_update32 - read and update a 32 bit stat from the chip
491 * @hw: ptr to the hardware info
492 * @reg: the hw reg to read
493 * @offset_loaded: has the initial offset been loaded yet
494 * @offset: ptr to current offset value
495 * @stat: ptr to the stat
496 **/
497static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
498 bool offset_loaded, u64 *offset, u64 *stat)
499{
500 u32 new_data;
501
502 new_data = rd32(hw, reg);
503 if (!offset_loaded)
504 *offset = new_data;
505 if (likely(new_data >= *offset))
506 *stat = (u32)(new_data - *offset);
507 else
508 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
509}
510
511/**
512 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
513 * @vsi: the VSI to be updated
514 **/
515void i40e_update_eth_stats(struct i40e_vsi *vsi)
516{
517 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
518 struct i40e_pf *pf = vsi->back;
519 struct i40e_hw *hw = &pf->hw;
520 struct i40e_eth_stats *oes;
521 struct i40e_eth_stats *es; /* device's eth stats */
522
523 es = &vsi->eth_stats;
524 oes = &vsi->eth_stats_offsets;
525
526 /* Gather up the stats that the hw collects */
527 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->tx_errors, &es->tx_errors);
530 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
531 vsi->stat_offsets_loaded,
532 &oes->rx_discards, &es->rx_discards);
533
534 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
535 I40E_GLV_GORCL(stat_idx),
536 vsi->stat_offsets_loaded,
537 &oes->rx_bytes, &es->rx_bytes);
538 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
539 I40E_GLV_UPRCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_unicast, &es->rx_unicast);
542 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
543 I40E_GLV_MPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_multicast, &es->rx_multicast);
546 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
547 I40E_GLV_BPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_broadcast, &es->rx_broadcast);
550
551 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
552 I40E_GLV_GOTCL(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->tx_bytes, &es->tx_bytes);
555 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
556 I40E_GLV_UPTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_unicast, &es->tx_unicast);
559 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
560 I40E_GLV_MPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_multicast, &es->tx_multicast);
563 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
564 I40E_GLV_BPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_broadcast, &es->tx_broadcast);
567 vsi->stat_offsets_loaded = true;
568}
569
570/**
571 * i40e_update_veb_stats - Update Switch component statistics
572 * @veb: the VEB being updated
573 **/
574static void i40e_update_veb_stats(struct i40e_veb *veb)
575{
576 struct i40e_pf *pf = veb->pf;
577 struct i40e_hw *hw = &pf->hw;
578 struct i40e_eth_stats *oes;
579 struct i40e_eth_stats *es; /* device's eth stats */
580 int idx = 0;
581
582 idx = veb->stats_idx;
583 es = &veb->stats;
584 oes = &veb->stats_offsets;
585
586 /* Gather up the stats that the hw collects */
587 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
588 veb->stat_offsets_loaded,
589 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 590 if (hw->revision_id > 0)
591 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
592 veb->stat_offsets_loaded,
593 &oes->rx_unknown_protocol,
594 &es->rx_unknown_protocol);
41c445ff
JB		 595 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_bytes, &es->rx_bytes);
598 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_unicast, &es->rx_unicast);
601 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_multicast, &es->rx_multicast);
604 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->rx_broadcast, &es->rx_broadcast);
607
608 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_bytes, &es->tx_bytes);
611 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_unicast, &es->tx_unicast);
614 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_multicast, &es->tx_multicast);
617 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->tx_broadcast, &es->tx_broadcast);
620 veb->stat_offsets_loaded = true;
621}
622
623/**
624 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
625 * @pf: the corresponding PF
626 *
627 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
628 **/
629static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
630{
631 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
632 struct i40e_hw_port_stats *nsd = &pf->stats;
633 struct i40e_hw *hw = &pf->hw;
634 u64 xoff = 0;
635 u16 i, v;
636
637 if ((hw->fc.current_mode != I40E_FC_FULL) &&
638 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
639 return;
640
641 xoff = nsd->link_xoff_rx;
642 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
643 pf->stat_offsets_loaded,
644 &osd->link_xoff_rx, &nsd->link_xoff_rx);
645
646 /* No new LFC xoff rx */
647 if (!(nsd->link_xoff_rx - xoff))
648 return;
649
650 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
651 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
652 struct i40e_vsi *vsi = pf->vsi[v];
653
654 if (!vsi)
655 continue;
656
657 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 658 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 659 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
660 }
661 }
662}
663
664/**
665 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
666 * @pf: the corresponding PF
667 *
668 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
669 **/
670static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
671{
672 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
673 struct i40e_hw_port_stats *nsd = &pf->stats;
674 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
675 struct i40e_dcbx_config *dcb_cfg;
676 struct i40e_hw *hw = &pf->hw;
677 u16 i, v;
678 u8 tc;
679
680 dcb_cfg = &hw->local_dcbx_config;
681
682 /* See if DCB enabled with PFC TC */
683 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
684 !(dcb_cfg->pfc.pfcenable)) {
685 i40e_update_link_xoff_rx(pf);
686 return;
687 }
688
689 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
690 u64 prio_xoff = nsd->priority_xoff_rx[i];
691 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
692 pf->stat_offsets_loaded,
693 &osd->priority_xoff_rx[i],
694 &nsd->priority_xoff_rx[i]);
695
696 /* No new PFC xoff rx */
697 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
698 continue;
699 /* Get the TC for given priority */
700 tc = dcb_cfg->etscfg.prioritytable[i];
701 xoff[tc] = true;
702 }
703
704 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
705 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
706 struct i40e_vsi *vsi = pf->vsi[v];
707
708 if (!vsi)
709 continue;
710
711 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 712 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 713
714 tc = ring->dcb_tc;
715 if (xoff[tc])
716 clear_bit(__I40E_HANG_CHECK_ARMED,
717 &ring->state);
718 }
719 }
720}
721
722/**
723 * i40e_update_stats - Update the board statistics counters.
724 * @vsi: the VSI to be updated
725 *
726 * There are a few instances where we store the same stat in a
727 * couple of different structs. This is partly because we have
728 * the netdev stats that need to be filled out, which is slightly
729 * different from the "eth_stats" defined by the chip and used in
730 * VF communications. We sort it all out here in a central place.
731 **/
732void i40e_update_stats(struct i40e_vsi *vsi)
733{
734 struct i40e_pf *pf = vsi->back;
735 struct i40e_hw *hw = &pf->hw;
736 struct rtnl_link_stats64 *ons;
737 struct rtnl_link_stats64 *ns; /* netdev stats */
738 struct i40e_eth_stats *oes;
739 struct i40e_eth_stats *es; /* device's eth stats */
740 u32 tx_restart, tx_busy;
741 u32 rx_page, rx_buf;
742 u64 rx_p, rx_b;
743 u64 tx_p, tx_b;
bee5af7e 744 u32 val;
41c445ff
JB		 745 int i;
746 u16 q;
747
748 if (test_bit(__I40E_DOWN, &vsi->state) ||
749 test_bit(__I40E_CONFIG_BUSY, &pf->state))
750 return;
751
752 ns = i40e_get_vsi_stats_struct(vsi);
753 ons = &vsi->net_stats_offsets;
754 es = &vsi->eth_stats;
755 oes = &vsi->eth_stats_offsets;
756
757 /* Gather up the netdev and vsi stats that the driver collects
758 * on the fly during packet processing
759 */
760 rx_b = rx_p = 0;
761 tx_b = tx_p = 0;
762 tx_restart = tx_busy = 0;
763 rx_page = 0;
764 rx_buf = 0;
980e9b11 765 rcu_read_lock();
41c445ff
JB		 766 for (q = 0; q < vsi->num_queue_pairs; q++) {
767 struct i40e_ring *p;
980e9b11
AD		 768 u64 bytes, packets;
769 unsigned int start;
770
771 /* locate Tx ring */
772 p = ACCESS_ONCE(vsi->tx_rings[q]);
773
774 do {
57a7744e 775 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 776 packets = p->stats.packets;
777 bytes = p->stats.bytes;
57a7744e 778 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 779 tx_b += bytes;
780 tx_p += packets;
781 tx_restart += p->tx_stats.restart_queue;
782 tx_busy += p->tx_stats.tx_busy;
41c445ff 783
980e9b11
AD		 784 /* Rx queue is part of the same block as Tx queue */
785 p = &p[1];
786 do {
57a7744e 787 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 788 packets = p->stats.packets;
789 bytes = p->stats.bytes;
57a7744e 790 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 791 rx_b += bytes;
792 rx_p += packets;
420136cc
MW		 793 rx_buf += p->rx_stats.alloc_buff_failed;
794 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 795 }
980e9b11 796 rcu_read_unlock();
41c445ff
JB		 797 vsi->tx_restart = tx_restart;
798 vsi->tx_busy = tx_busy;
799 vsi->rx_page_failed = rx_page;
800 vsi->rx_buf_failed = rx_buf;
801
802 ns->rx_packets = rx_p;
803 ns->rx_bytes = rx_b;
804 ns->tx_packets = tx_p;
805 ns->tx_bytes = tx_b;
806
807 i40e_update_eth_stats(vsi);
808 /* update netdev stats from eth stats */
809 ons->rx_errors = oes->rx_errors;
810 ns->rx_errors = es->rx_errors;
811 ons->tx_errors = oes->tx_errors;
812 ns->tx_errors = es->tx_errors;
813 ons->multicast = oes->rx_multicast;
814 ns->multicast = es->rx_multicast;
815 ons->tx_dropped = oes->tx_discards;
816 ns->tx_dropped = es->tx_discards;
817
818 /* Get the port data only if this is the main PF VSI */
819 if (vsi == pf->vsi[pf->lan_vsi]) {
820 struct i40e_hw_port_stats *nsd = &pf->stats;
821 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
822
823 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
824 I40E_GLPRT_GORCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
827 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
828 I40E_GLPRT_GOTCL(hw->port),
829 pf->stat_offsets_loaded,
830 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
831 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.rx_discards,
834 &nsd->eth.rx_discards);
835 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
836 pf->stat_offsets_loaded,
837 &osd->eth.tx_discards,
838 &nsd->eth.tx_discards);
839 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
840 I40E_GLPRT_MPRCL(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->eth.rx_multicast,
843 &nsd->eth.rx_multicast);
844
845 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
846 pf->stat_offsets_loaded,
847 &osd->tx_dropped_link_down,
848 &nsd->tx_dropped_link_down);
849
850 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->crc_errors, &nsd->crc_errors);
853 ns->rx_crc_errors = nsd->crc_errors;
854
855 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
856 pf->stat_offsets_loaded,
857 &osd->illegal_bytes, &nsd->illegal_bytes);
858 ns->rx_errors = nsd->crc_errors
859 + nsd->illegal_bytes;
860
861 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_local_faults,
864 &nsd->mac_local_faults);
865 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
866 pf->stat_offsets_loaded,
867 &osd->mac_remote_faults,
868 &nsd->mac_remote_faults);
869
870 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
871 pf->stat_offsets_loaded,
872 &osd->rx_length_errors,
873 &nsd->rx_length_errors);
874 ns->rx_length_errors = nsd->rx_length_errors;
875
876 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
877 pf->stat_offsets_loaded,
878 &osd->link_xon_rx, &nsd->link_xon_rx);
879 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xon_tx, &nsd->link_xon_tx);
882 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
883 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
884 pf->stat_offsets_loaded,
885 &osd->link_xoff_tx, &nsd->link_xoff_tx);
886
887 for (i = 0; i < 8; i++) {
888 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_rx[i],
891 &nsd->priority_xon_rx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xon_tx[i],
895 &nsd->priority_xon_tx[i]);
896 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
897 pf->stat_offsets_loaded,
898 &osd->priority_xoff_tx[i],
899 &nsd->priority_xoff_tx[i]);
900 i40e_stat_update32(hw,
901 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
902 pf->stat_offsets_loaded,
903 &osd->priority_xon_2_xoff[i],
904 &nsd->priority_xon_2_xoff[i]);
905 }
906
907 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
908 I40E_GLPRT_PRC64L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_64, &nsd->rx_size_64);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
912 I40E_GLPRT_PRC127L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_127, &nsd->rx_size_127);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
916 I40E_GLPRT_PRC255L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_255, &nsd->rx_size_255);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
920 I40E_GLPRT_PRC511L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_511, &nsd->rx_size_511);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
924 I40E_GLPRT_PRC1023L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1023, &nsd->rx_size_1023);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
928 I40E_GLPRT_PRC1522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_1522, &nsd->rx_size_1522);
931 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
932 I40E_GLPRT_PRC9522L(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->rx_size_big, &nsd->rx_size_big);
935
936 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
937 I40E_GLPRT_PTC64L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_64, &nsd->tx_size_64);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
941 I40E_GLPRT_PTC127L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_127, &nsd->tx_size_127);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
945 I40E_GLPRT_PTC255L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_255, &nsd->tx_size_255);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
949 I40E_GLPRT_PTC511L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_511, &nsd->tx_size_511);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
953 I40E_GLPRT_PTC1023L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1023, &nsd->tx_size_1023);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
957 I40E_GLPRT_PTC1522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_1522, &nsd->tx_size_1522);
960 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
961 I40E_GLPRT_PTC9522L(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->tx_size_big, &nsd->tx_size_big);
964
965 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->rx_undersize, &nsd->rx_undersize);
968 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
969 pf->stat_offsets_loaded,
970 &osd->rx_fragments, &nsd->rx_fragments);
971 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->rx_oversize, &nsd->rx_oversize);
974 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->rx_jabber, &nsd->rx_jabber);
bee5af7e
ASJ		 977
978 val = rd32(hw, I40E_PRTPM_EEE_STAT);
979 nsd->tx_lpi_status =
980 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
981 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
982 nsd->rx_lpi_status =
983 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
984 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
985 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
986 pf->stat_offsets_loaded,
987 &osd->tx_lpi_count, &nsd->tx_lpi_count);
988 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
989 pf->stat_offsets_loaded,
990 &osd->rx_lpi_count, &nsd->rx_lpi_count);
41c445ff
JB		 991 }
992
993 pf->stat_offsets_loaded = true;
994}
995
996/**
997 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
998 * @vsi: the VSI to be searched
999 * @macaddr: the MAC address
1000 * @vlan: the vlan
1001 * @is_vf: make sure its a vf filter, else doesn't matter
1002 * @is_netdev: make sure its a netdev filter, else doesn't matter
1003 *
1004 * Returns ptr to the filter object or NULL
1005 **/
1006static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1007 u8 *macaddr, s16 vlan,
1008 bool is_vf, bool is_netdev)
1009{
1010 struct i40e_mac_filter *f;
1011
1012 if (!vsi || !macaddr)
1013 return NULL;
1014
1015 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1016 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1017 (vlan == f->vlan) &&
1018 (!is_vf || f->is_vf) &&
1019 (!is_netdev || f->is_netdev))
1020 return f;
1021 }
1022 return NULL;
1023}
1024
1025/**
1026 * i40e_find_mac - Find a mac addr in the macvlan filters list
1027 * @vsi: the VSI to be searched
1028 * @macaddr: the MAC address we are searching for
1029 * @is_vf: make sure its a vf filter, else doesn't matter
1030 * @is_netdev: make sure its a netdev filter, else doesn't matter
1031 *
1032 * Returns the first filter with the provided MAC address or NULL if
1033 * MAC address was not found
1034 **/
1035struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1036 bool is_vf, bool is_netdev)
1037{
1038 struct i40e_mac_filter *f;
1039
1040 if (!vsi || !macaddr)
1041 return NULL;
1042
1043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1044 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1045 (!is_vf || f->is_vf) &&
1046 (!is_netdev || f->is_netdev))
1047 return f;
1048 }
1049 return NULL;
1050}
1051
1052/**
1053 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1054 * @vsi: the VSI to be searched
1055 *
1056 * Returns true if VSI is in vlan mode or false otherwise
1057 **/
1058bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1059{
1060 struct i40e_mac_filter *f;
1061
1062 /* Only -1 for all the filters denotes not in vlan mode
1063 * so we have to go through all the list in order to make sure
1064 */
1065 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1066 if (f->vlan >= 0)
1067 return true;
1068 }
1069
1070 return false;
1071}
1072
1073/**
1074 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1075 * @vsi: the VSI to be searched
1076 * @macaddr: the mac address to be filtered
1077 * @is_vf: true if it is a vf
1078 * @is_netdev: true if it is a netdev
1079 *
1080 * Goes through all the macvlan filters and adds a
1081 * macvlan filter for each unique vlan that already exists
1082 *
1083 * Returns first filter found on success, else NULL
1084 **/
1085struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1086 bool is_vf, bool is_netdev)
1087{
1088 struct i40e_mac_filter *f;
1089
1090 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1091 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1092 is_vf, is_netdev)) {
1093 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1094 is_vf, is_netdev))
41c445ff
JB		 1095 return NULL;
1096 }
1097 }
1098
1099 return list_first_entry_or_null(&vsi->mac_filter_list,
1100 struct i40e_mac_filter, list);
1101}
1102
1103/**
1104 * i40e_add_filter - Add a mac/vlan filter to the VSI
1105 * @vsi: the VSI to be searched
1106 * @macaddr: the MAC address
1107 * @vlan: the vlan
1108 * @is_vf: make sure its a vf filter, else doesn't matter
1109 * @is_netdev: make sure its a netdev filter, else doesn't matter
1110 *
1111 * Returns ptr to the filter object or NULL when no memory available.
1112 **/
1113struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1114 u8 *macaddr, s16 vlan,
1115 bool is_vf, bool is_netdev)
1116{
1117 struct i40e_mac_filter *f;
1118
1119 if (!vsi || !macaddr)
1120 return NULL;
1121
1122 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1123 if (!f) {
1124 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1125 if (!f)
1126 goto add_filter_out;
1127
1128 memcpy(f->macaddr, macaddr, ETH_ALEN);
1129 f->vlan = vlan;
1130 f->changed = true;
1131
1132 INIT_LIST_HEAD(&f->list);
1133 list_add(&f->list, &vsi->mac_filter_list);
1134 }
1135
1136 /* increment counter and add a new flag if needed */
1137 if (is_vf) {
1138 if (!f->is_vf) {
1139 f->is_vf = true;
1140 f->counter++;
1141 }
1142 } else if (is_netdev) {
1143 if (!f->is_netdev) {
1144 f->is_netdev = true;
1145 f->counter++;
1146 }
1147 } else {
1148 f->counter++;
1149 }
1150
1151 /* changed tells sync_filters_subtask to
1152 * push the filter down to the firmware
1153 */
1154 if (f->changed) {
1155 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1156 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1157 }
1158
1159add_filter_out:
1160 return f;
1161}
1162
1163/**
1164 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1165 * @vsi: the VSI to be searched
1166 * @macaddr: the MAC address
1167 * @vlan: the vlan
1168 * @is_vf: make sure it's a vf filter, else doesn't matter
1169 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1170 **/
1171void i40e_del_filter(struct i40e_vsi *vsi,
1172 u8 *macaddr, s16 vlan,
1173 bool is_vf, bool is_netdev)
1174{
1175 struct i40e_mac_filter *f;
1176
1177 if (!vsi || !macaddr)
1178 return;
1179
1180 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1181 if (!f || f->counter == 0)
1182 return;
1183
1184 if (is_vf) {
1185 if (f->is_vf) {
1186 f->is_vf = false;
1187 f->counter--;
1188 }
1189 } else if (is_netdev) {
1190 if (f->is_netdev) {
1191 f->is_netdev = false;
1192 f->counter--;
1193 }
1194 } else {
1195 /* make sure we don't remove a filter in use by vf or netdev */
1196 int min_f = 0;
1197 min_f += (f->is_vf ? 1 : 0);
1198 min_f += (f->is_netdev ? 1 : 0);
1199
1200 if (f->counter > min_f)
1201 f->counter--;
1202 }
1203
1204 /* counter == 0 tells sync_filters_subtask to
1205 * remove the filter from the firmware's list
1206 */
1207 if (f->counter == 0) {
1208 f->changed = true;
1209 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1210 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1211 }
1212}
1213
1214/**
1215 * i40e_set_mac - NDO callback to set mac address
1216 * @netdev: network interface device structure
1217 * @p: pointer to an address structure
1218 *
1219 * Returns 0 on success, negative on failure
1220 **/
1221static int i40e_set_mac(struct net_device *netdev, void *p)
1222{
1223 struct i40e_netdev_priv *np = netdev_priv(netdev);
1224 struct i40e_vsi *vsi = np->vsi;
1225 struct sockaddr *addr = p;
1226 struct i40e_mac_filter *f;
1227
1228 if (!is_valid_ether_addr(addr->sa_data))
1229 return -EADDRNOTAVAIL;
1230
1231 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1232
1233 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1234 return 0;
1235
80f6428f
ASJ		 1236 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1237 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1238 return -EADDRNOTAVAIL;
1239
41c445ff
JB		 1240 if (vsi->type == I40E_VSI_MAIN) {
1241 i40e_status ret;
1242 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1243 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1244 addr->sa_data, NULL);
1245 if (ret) {
1246 netdev_info(netdev,
1247 "Addr change for Main VSI failed: %d\n",
1248 ret);
1249 return -EADDRNOTAVAIL;
1250 }
1251
1252 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1253 }
1254
1255 /* In order to be sure to not drop any packets, add the new address
1256 * then delete the old one.
1257 */
1258 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1259 if (!f)
1260 return -ENOMEM;
1261
1262 i40e_sync_vsi_filters(vsi);
1263 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1264 i40e_sync_vsi_filters(vsi);
1265
1266 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1267
1268 return 0;
1269}
1270
1271/**
1272 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1273 * @vsi: the VSI being setup
1274 * @ctxt: VSI context structure
1275 * @enabled_tc: Enabled TCs bitmap
1276 * @is_add: True if called before Add VSI
1277 *
1278 * Setup VSI queue mapping for enabled traffic classes.
1279 **/
1280static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1281 struct i40e_vsi_context *ctxt,
1282 u8 enabled_tc,
1283 bool is_add)
1284{
1285 struct i40e_pf *pf = vsi->back;
1286 u16 sections = 0;
1287 u8 netdev_tc = 0;
1288 u16 numtc = 0;
1289 u16 qcount;
1290 u8 offset;
1291 u16 qmap;
1292 int i;
4e3b35b0 1293 u16 num_tc_qps = 0;
41c445ff
JB		 1294
1295 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1296 offset = 0;
1297
1298 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1299 /* Find numtc from enabled TC bitmap */
1300 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1301 if (enabled_tc & (1 << i)) /* TC is enabled */
1302 numtc++;
1303 }
1304 if (!numtc) {
1305 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1306 numtc = 1;
1307 }
1308 } else {
1309 /* At least TC0 is enabled in case of non-DCB case */
1310 numtc = 1;
1311 }
1312
1313 vsi->tc_config.numtc = numtc;
1314 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1315 /* Number of queues per enabled TC */
1316 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1317 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1318
1319 /* Setup queue offset/count for all TCs for given VSI */
1320 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1321 /* See if the given TC is enabled for the given VSI */
1322 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1323 int pow, num_qps;
1324
41c445ff
JB		 1325 switch (vsi->type) {
1326 case I40E_VSI_MAIN:
4e3b35b0 1327 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1328 break;
1329 case I40E_VSI_FDIR:
1330 case I40E_VSI_SRIOV:
1331 case I40E_VSI_VMDQ2:
1332 default:
4e3b35b0 1333 qcount = num_tc_qps;
41c445ff
JB		 1334 WARN_ON(i != 0);
1335 break;
1336 }
4e3b35b0
NP		 1337 vsi->tc_config.tc_info[i].qoffset = offset;
1338 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1339
1340 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1341 num_qps = qcount;
41c445ff 1342 pow = 0;
4e3b35b0 1343 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1344 pow++;
1345 num_qps >>= 1;
1346 }
1347
1348 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1349 qmap =
1350 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1351 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1352
4e3b35b0 1353 offset += qcount;
41c445ff
JB		 1354 } else {
1355 /* TC is not enabled so set the offset to
1356 * default queue and allocate one queue
1357 * for the given TC.
1358 */
1359 vsi->tc_config.tc_info[i].qoffset = 0;
1360 vsi->tc_config.tc_info[i].qcount = 1;
1361 vsi->tc_config.tc_info[i].netdev_tc = 0;
1362
1363 qmap = 0;
1364 }
1365 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1366 }
1367
1368 /* Set actual Tx/Rx queue pairs */
1369 vsi->num_queue_pairs = offset;
1370
1371 /* Scheduler section valid can only be set for ADD VSI */
1372 if (is_add) {
1373 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1374
1375 ctxt->info.up_enable_bits = enabled_tc;
1376 }
1377 if (vsi->type == I40E_VSI_SRIOV) {
1378 ctxt->info.mapping_flags |=
1379 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1380 for (i = 0; i < vsi->num_queue_pairs; i++)
1381 ctxt->info.queue_mapping[i] =
1382 cpu_to_le16(vsi->base_queue + i);
1383 } else {
1384 ctxt->info.mapping_flags |=
1385 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1386 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1387 }
1388 ctxt->info.valid_sections |= cpu_to_le16(sections);
1389}
1390
1391/**
1392 * i40e_set_rx_mode - NDO callback to set the netdev filters
1393 * @netdev: network interface device structure
1394 **/
1395static void i40e_set_rx_mode(struct net_device *netdev)
1396{
1397 struct i40e_netdev_priv *np = netdev_priv(netdev);
1398 struct i40e_mac_filter *f, *ftmp;
1399 struct i40e_vsi *vsi = np->vsi;
1400 struct netdev_hw_addr *uca;
1401 struct netdev_hw_addr *mca;
1402 struct netdev_hw_addr *ha;
1403
1404 /* add addr if not already in the filter list */
1405 netdev_for_each_uc_addr(uca, netdev) {
1406 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1407 if (i40e_is_vsi_in_vlan(vsi))
1408 i40e_put_mac_in_vlan(vsi, uca->addr,
1409 false, true);
1410 else
1411 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1412 false, true);
1413 }
1414 }
1415
1416 netdev_for_each_mc_addr(mca, netdev) {
1417 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1418 if (i40e_is_vsi_in_vlan(vsi))
1419 i40e_put_mac_in_vlan(vsi, mca->addr,
1420 false, true);
1421 else
1422 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1423 false, true);
1424 }
1425 }
1426
1427 /* remove filter if not in netdev list */
1428 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1429 bool found = false;
1430
1431 if (!f->is_netdev)
1432 continue;
1433
1434 if (is_multicast_ether_addr(f->macaddr)) {
1435 netdev_for_each_mc_addr(mca, netdev) {
1436 if (ether_addr_equal(mca->addr, f->macaddr)) {
1437 found = true;
1438 break;
1439 }
1440 }
1441 } else {
1442 netdev_for_each_uc_addr(uca, netdev) {
1443 if (ether_addr_equal(uca->addr, f->macaddr)) {
1444 found = true;
1445 break;
1446 }
1447 }
1448
1449 for_each_dev_addr(netdev, ha) {
1450 if (ether_addr_equal(ha->addr, f->macaddr)) {
1451 found = true;
1452 break;
1453 }
1454 }
1455 }
1456 if (!found)
1457 i40e_del_filter(
1458 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1459 }
1460
1461 /* check for other flag changes */
1462 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1463 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1464 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1465 }
1466}
1467
1468/**
1469 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1470 * @vsi: ptr to the VSI
1471 *
1472 * Push any outstanding VSI filter changes through the AdminQ.
1473 *
1474 * Returns 0 or error value
1475 **/
1476int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1477{
1478 struct i40e_mac_filter *f, *ftmp;
1479 bool promisc_forced_on = false;
1480 bool add_happened = false;
1481 int filter_list_len = 0;
1482 u32 changed_flags = 0;
dcae29be 1483 i40e_status aq_ret = 0;
41c445ff
JB		 1484 struct i40e_pf *pf;
1485 int num_add = 0;
1486 int num_del = 0;
1487 u16 cmd_flags;
1488
1489 /* empty array typed pointers, kcalloc later */
1490 struct i40e_aqc_add_macvlan_element_data *add_list;
1491 struct i40e_aqc_remove_macvlan_element_data *del_list;
1492
1493 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1494 usleep_range(1000, 2000);
1495 pf = vsi->back;
1496
1497 if (vsi->netdev) {
1498 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1499 vsi->current_netdev_flags = vsi->netdev->flags;
1500 }
1501
1502 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1503 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1504
1505 filter_list_len = pf->hw.aq.asq_buf_size /
1506 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1507 del_list = kcalloc(filter_list_len,
1508 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1509 GFP_KERNEL);
1510 if (!del_list)
1511 return -ENOMEM;
1512
1513 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1514 if (!f->changed)
1515 continue;
1516
1517 if (f->counter != 0)
1518 continue;
1519 f->changed = false;
1520 cmd_flags = 0;
1521
1522 /* add to delete list */
1523 memcpy(del_list[num_del].mac_addr,
1524 f->macaddr, ETH_ALEN);
1525 del_list[num_del].vlan_tag =
1526 cpu_to_le16((u16)(f->vlan ==
1527 I40E_VLAN_ANY ? 0 : f->vlan));
1528
41c445ff
JB		 1529 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1530 del_list[num_del].flags = cmd_flags;
1531 num_del++;
1532
1533 /* unlink from filter list */
1534 list_del(&f->list);
1535 kfree(f);
1536
1537 /* flush a full buffer */
1538 if (num_del == filter_list_len) {
dcae29be 1539 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1540 vsi->seid, del_list, num_del,
1541 NULL);
1542 num_del = 0;
1543 memset(del_list, 0, sizeof(*del_list));
1544
dcae29be 1545 if (aq_ret)
41c445ff
JB		 1546 dev_info(&pf->pdev->dev,
1547 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1548 aq_ret,
41c445ff
JB		 1549 pf->hw.aq.asq_last_status);
1550 }
1551 }
1552 if (num_del) {
dcae29be 1553 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1554 del_list, num_del, NULL);
1555 num_del = 0;
1556
dcae29be 1557 if (aq_ret)
41c445ff
JB		 1558 dev_info(&pf->pdev->dev,
1559 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1560 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1561 }
1562
1563 kfree(del_list);
1564 del_list = NULL;
1565
1566 /* do all the adds now */
1567 filter_list_len = pf->hw.aq.asq_buf_size /
1568 sizeof(struct i40e_aqc_add_macvlan_element_data),
1569 add_list = kcalloc(filter_list_len,
1570 sizeof(struct i40e_aqc_add_macvlan_element_data),
1571 GFP_KERNEL);
1572 if (!add_list)
1573 return -ENOMEM;
1574
1575 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1576 if (!f->changed)
1577 continue;
1578
1579 if (f->counter == 0)
1580 continue;
1581 f->changed = false;
1582 add_happened = true;
1583 cmd_flags = 0;
1584
1585 /* add to add array */
1586 memcpy(add_list[num_add].mac_addr,
1587 f->macaddr, ETH_ALEN);
1588 add_list[num_add].vlan_tag =
1589 cpu_to_le16(
1590 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1591 add_list[num_add].queue_number = 0;
1592
1593 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1594 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1595 num_add++;
1596
1597 /* flush a full buffer */
1598 if (num_add == filter_list_len) {
dcae29be
JB		 1599 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1600 add_list, num_add,
1601 NULL);
41c445ff
JB		 1602 num_add = 0;
1603
dcae29be 1604 if (aq_ret)
41c445ff
JB		 1605 break;
1606 memset(add_list, 0, sizeof(*add_list));
1607 }
1608 }
1609 if (num_add) {
dcae29be
JB		 1610 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1611 add_list, num_add, NULL);
41c445ff
JB		 1612 num_add = 0;
1613 }
1614 kfree(add_list);
1615 add_list = NULL;
1616
dcae29be 1617 if (add_happened && (!aq_ret)) {
41c445ff 1618 /* do nothing */;
dcae29be 1619 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1620 dev_info(&pf->pdev->dev,
1621 "add filter failed, err %d, aq_err %d\n",
dcae29be 1622 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1623 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1624 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1625 &vsi->state)) {
1626 promisc_forced_on = true;
1627 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1628 &vsi->state);
1629 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1630 }
1631 }
1632 }
1633
1634 /* check for changes in promiscuous modes */
1635 if (changed_flags & IFF_ALLMULTI) {
1636 bool cur_multipromisc;
1637 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1638 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1639 vsi->seid,
1640 cur_multipromisc,
1641 NULL);
1642 if (aq_ret)
41c445ff
JB		 1643 dev_info(&pf->pdev->dev,
1644 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1645 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1646 }
1647 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1648 bool cur_promisc;
1649 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1650 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1651 &vsi->state));
dcae29be
JB		 1652 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1653 vsi->seid,
1654 cur_promisc, NULL);
1655 if (aq_ret)
41c445ff
JB		 1656 dev_info(&pf->pdev->dev,
1657 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1658 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1659 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1660 vsi->seid,
1661 cur_promisc, NULL);
1662 if (aq_ret)
1663 dev_info(&pf->pdev->dev,
1664 "set brdcast promisc failed, err %d, aq_err %d\n",
1665 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1666 }
1667
1668 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1669 return 0;
1670}
1671
1672/**
1673 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1674 * @pf: board private structure
1675 **/
1676static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1677{
1678 int v;
1679
1680 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1681 return;
1682 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1683
1684 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1685 if (pf->vsi[v] &&
1686 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1687 i40e_sync_vsi_filters(pf->vsi[v]);
1688 }
1689}
1690
1691/**
1692 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1693 * @netdev: network interface device structure
1694 * @new_mtu: new value for maximum frame size
1695 *
1696 * Returns 0 on success, negative on failure
1697 **/
1698static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1699{
1700 struct i40e_netdev_priv *np = netdev_priv(netdev);
1701 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1702 struct i40e_vsi *vsi = np->vsi;
1703
1704 /* MTU < 68 is an error and causes problems on some kernels */
1705 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1706 return -EINVAL;
1707
1708 netdev_info(netdev, "changing MTU from %d to %d\n",
1709 netdev->mtu, new_mtu);
1710 netdev->mtu = new_mtu;
1711 if (netif_running(netdev))
1712 i40e_vsi_reinit_locked(vsi);
1713
1714 return 0;
1715}
1716
beb0dff1
JK		 1717/**
1718 * i40e_ioctl - Access the hwtstamp interface
1719 * @netdev: network interface device structure
1720 * @ifr: interface request data
1721 * @cmd: ioctl command
1722 **/
1723int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1724{
1725 struct i40e_netdev_priv *np = netdev_priv(netdev);
1726 struct i40e_pf *pf = np->vsi->back;
1727
1728 switch (cmd) {
1729 case SIOCGHWTSTAMP:
1730 return i40e_ptp_get_ts_config(pf, ifr);
1731 case SIOCSHWTSTAMP:
1732 return i40e_ptp_set_ts_config(pf, ifr);
1733 default:
1734 return -EOPNOTSUPP;
1735 }
1736}
1737
41c445ff
JB		 1738/**
1739 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1740 * @vsi: the vsi being adjusted
1741 **/
1742void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1743{
1744 struct i40e_vsi_context ctxt;
1745 i40e_status ret;
1746
1747 if ((vsi->info.valid_sections &
1748 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1749 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1750 return; /* already enabled */
1751
1752 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1753 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1754 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1755
1756 ctxt.seid = vsi->seid;
1757 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1758 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1759 if (ret) {
1760 dev_info(&vsi->back->pdev->dev,
1761 "%s: update vsi failed, aq_err=%d\n",
1762 __func__, vsi->back->hw.aq.asq_last_status);
1763 }
1764}
1765
1766/**
1767 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1768 * @vsi: the vsi being adjusted
1769 **/
1770void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1771{
1772 struct i40e_vsi_context ctxt;
1773 i40e_status ret;
1774
1775 if ((vsi->info.valid_sections &
1776 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1777 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1778 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1779 return; /* already disabled */
1780
1781 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1782 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1783 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1784
1785 ctxt.seid = vsi->seid;
1786 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1787 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1788 if (ret) {
1789 dev_info(&vsi->back->pdev->dev,
1790 "%s: update vsi failed, aq_err=%d\n",
1791 __func__, vsi->back->hw.aq.asq_last_status);
1792 }
1793}
1794
1795/**
1796 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1797 * @netdev: network interface to be adjusted
1798 * @features: netdev features to test if VLAN offload is enabled or not
1799 **/
1800static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1801{
1802 struct i40e_netdev_priv *np = netdev_priv(netdev);
1803 struct i40e_vsi *vsi = np->vsi;
1804
1805 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1806 i40e_vlan_stripping_enable(vsi);
1807 else
1808 i40e_vlan_stripping_disable(vsi);
1809}
1810
1811/**
1812 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1813 * @vsi: the vsi being configured
1814 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1815 **/
1816int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1817{
1818 struct i40e_mac_filter *f, *add_f;
1819 bool is_netdev, is_vf;
41c445ff
JB		 1820
1821 is_vf = (vsi->type == I40E_VSI_SRIOV);
1822 is_netdev = !!(vsi->netdev);
1823
1824 if (is_netdev) {
1825 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1826 is_vf, is_netdev);
1827 if (!add_f) {
1828 dev_info(&vsi->back->pdev->dev,
1829 "Could not add vlan filter %d for %pM\n",
1830 vid, vsi->netdev->dev_addr);
1831 return -ENOMEM;
1832 }
1833 }
1834
1835 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1836 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1837 if (!add_f) {
1838 dev_info(&vsi->back->pdev->dev,
1839 "Could not add vlan filter %d for %pM\n",
1840 vid, f->macaddr);
1841 return -ENOMEM;
1842 }
1843 }
1844
41c445ff
JB		 1845 /* Now if we add a vlan tag, make sure to check if it is the first
1846 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1847 * with 0, so we now accept untagged and specified tagged traffic
1848 * (and not any taged and untagged)
1849 */
1850 if (vid > 0) {
1851 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1852 I40E_VLAN_ANY,
1853 is_vf, is_netdev)) {
1854 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1855 I40E_VLAN_ANY, is_vf, is_netdev);
1856 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1857 is_vf, is_netdev);
1858 if (!add_f) {
1859 dev_info(&vsi->back->pdev->dev,
1860 "Could not add filter 0 for %pM\n",
1861 vsi->netdev->dev_addr);
1862 return -ENOMEM;
1863 }
1864 }
8d82a7c5 1865 }
41c445ff 1866
8d82a7c5
GR		 1867 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1868 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1869 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1870 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1871 is_vf, is_netdev)) {
1872 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1873 is_vf, is_netdev);
1874 add_f = i40e_add_filter(vsi, f->macaddr,
1875 0, is_vf, is_netdev);
1876 if (!add_f) {
1877 dev_info(&vsi->back->pdev->dev,
1878 "Could not add filter 0 for %pM\n",
1879 f->macaddr);
1880 return -ENOMEM;
1881 }
1882 }
1883 }
41c445ff
JB		 1884 }
1885
80f6428f
ASJ		 1886 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1887 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1888 return 0;
1889
1890 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1891}
1892
1893/**
1894 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1895 * @vsi: the vsi being configured
1896 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1897 *
1898 * Return: 0 on success or negative otherwise
41c445ff
JB		 1899 **/
1900int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1901{
1902 struct net_device *netdev = vsi->netdev;
1903 struct i40e_mac_filter *f, *add_f;
1904 bool is_vf, is_netdev;
1905 int filter_count = 0;
41c445ff
JB		 1906
1907 is_vf = (vsi->type == I40E_VSI_SRIOV);
1908 is_netdev = !!(netdev);
1909
1910 if (is_netdev)
1911 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1912
1913 list_for_each_entry(f, &vsi->mac_filter_list, list)
1914 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1915
41c445ff
JB		 1916 /* go through all the filters for this VSI and if there is only
1917 * vid == 0 it means there are no other filters, so vid 0 must
1918 * be replaced with -1. This signifies that we should from now
1919 * on accept any traffic (with any tag present, or untagged)
1920 */
1921 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1922 if (is_netdev) {
1923 if (f->vlan &&
1924 ether_addr_equal(netdev->dev_addr, f->macaddr))
1925 filter_count++;
1926 }
1927
1928 if (f->vlan)
1929 filter_count++;
1930 }
1931
1932 if (!filter_count && is_netdev) {
1933 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1934 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1935 is_vf, is_netdev);
1936 if (!f) {
1937 dev_info(&vsi->back->pdev->dev,
1938 "Could not add filter %d for %pM\n",
1939 I40E_VLAN_ANY, netdev->dev_addr);
1940 return -ENOMEM;
1941 }
1942 }
1943
1944 if (!filter_count) {
1945 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1946 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1947 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1948 is_vf, is_netdev);
1949 if (!add_f) {
1950 dev_info(&vsi->back->pdev->dev,
1951 "Could not add filter %d for %pM\n",
1952 I40E_VLAN_ANY, f->macaddr);
1953 return -ENOMEM;
1954 }
1955 }
1956 }
1957
80f6428f
ASJ		 1958 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1959 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1960 return 0;
1961
41c445ff
JB		 1962 return i40e_sync_vsi_filters(vsi);
1963}
1964
1965/**
1966 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1967 * @netdev: network interface to be adjusted
1968 * @vid: vlan id to be added
078b5876
JB		 1969 *
1970 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1971 **/
1972static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1973 __always_unused __be16 proto, u16 vid)
1974{
1975 struct i40e_netdev_priv *np = netdev_priv(netdev);
1976 struct i40e_vsi *vsi = np->vsi;
078b5876 1977 int ret = 0;
41c445ff
JB		 1978
1979 if (vid > 4095)
078b5876
JB		 1980 return -EINVAL;
1981
1982 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1983
6982d429
ASJ		 1984 /* If the network stack called us with vid = 0 then
1985 * it is asking to receive priority tagged packets with
1986 * vlan id 0. Our HW receives them by default when configured
1987 * to receive untagged packets so there is no need to add an
1988 * extra filter for vlan 0 tagged packets.
41c445ff 1989 */
6982d429
ASJ		 1990 if (vid)
1991 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 1992
078b5876
JB		 1993 if (!ret && (vid < VLAN_N_VID))
1994 set_bit(vid, vsi->active_vlans);
41c445ff 1995
078b5876 1996 return ret;
41c445ff
JB		 1997}
1998
1999/**
2000 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2001 * @netdev: network interface to be adjusted
2002 * @vid: vlan id to be removed
078b5876 2003 *
fdfd943e 2004 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2005 **/
2006static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2007 __always_unused __be16 proto, u16 vid)
2008{
2009 struct i40e_netdev_priv *np = netdev_priv(netdev);
2010 struct i40e_vsi *vsi = np->vsi;
2011
078b5876
JB		 2012 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2013
41c445ff
JB		 2014 /* return code is ignored as there is nothing a user
2015 * can do about failure to remove and a log message was
078b5876 2016 * already printed from the other function
41c445ff
JB		 2017 */
2018 i40e_vsi_kill_vlan(vsi, vid);
2019
2020 clear_bit(vid, vsi->active_vlans);
078b5876 2021
41c445ff
JB		 2022 return 0;
2023}
2024
2025/**
2026 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2027 * @vsi: the vsi being brought back up
2028 **/
2029static void i40e_restore_vlan(struct i40e_vsi *vsi)
2030{
2031 u16 vid;
2032
2033 if (!vsi->netdev)
2034 return;
2035
2036 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2037
2038 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2039 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2040 vid);
2041}
2042
2043/**
2044 * i40e_vsi_add_pvid - Add pvid for the VSI
2045 * @vsi: the vsi being adjusted
2046 * @vid: the vlan id to set as a PVID
2047 **/
dcae29be 2048int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2049{
2050 struct i40e_vsi_context ctxt;
dcae29be 2051 i40e_status aq_ret;
41c445ff
JB		 2052
2053 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2054 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2055 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2056 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2057 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2058
2059 ctxt.seid = vsi->seid;
2060 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2061 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2062 if (aq_ret) {
41c445ff
JB		 2063 dev_info(&vsi->back->pdev->dev,
2064 "%s: update vsi failed, aq_err=%d\n",
2065 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2066 return -ENOENT;
41c445ff
JB		 2067 }
2068
dcae29be 2069 return 0;
41c445ff
JB		 2070}
2071
2072/**
2073 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2074 * @vsi: the vsi being adjusted
2075 *
2076 * Just use the vlan_rx_register() service to put it back to normal
2077 **/
2078void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2079{
6c12fcbf
GR		 2080 i40e_vlan_stripping_disable(vsi);
2081
41c445ff 2082 vsi->info.pvid = 0;
41c445ff
JB		 2083}
2084
2085/**
2086 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2087 * @vsi: ptr to the VSI
2088 *
2089 * If this function returns with an error, then it's possible one or
2090 * more of the rings is populated (while the rest are not). It is the
2091 * callers duty to clean those orphaned rings.
2092 *
2093 * Return 0 on success, negative on failure
2094 **/
2095static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2096{
2097 int i, err = 0;
2098
2099 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2100 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2101
2102 return err;
2103}
2104
2105/**
2106 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2107 * @vsi: ptr to the VSI
2108 *
2109 * Free VSI's transmit software resources
2110 **/
2111static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2112{
2113 int i;
2114
8e9dca53
GR		 2115 if (!vsi->tx_rings)
2116 return;
2117
41c445ff 2118 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2119 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2120 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2121}
2122
2123/**
2124 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2125 * @vsi: ptr to the VSI
2126 *
2127 * If this function returns with an error, then it's possible one or
2128 * more of the rings is populated (while the rest are not). It is the
2129 * callers duty to clean those orphaned rings.
2130 *
2131 * Return 0 on success, negative on failure
2132 **/
2133static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2134{
2135 int i, err = 0;
2136
2137 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2138 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2139 return err;
2140}
2141
2142/**
2143 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2144 * @vsi: ptr to the VSI
2145 *
2146 * Free all receive software resources
2147 **/
2148static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2149{
2150 int i;
2151
8e9dca53
GR		 2152 if (!vsi->rx_rings)
2153 return;
2154
41c445ff 2155 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2156 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2157 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2158}
2159
2160/**
2161 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2162 * @ring: The Tx ring to configure
2163 *
2164 * Configure the Tx descriptor ring in the HMC context.
2165 **/
2166static int i40e_configure_tx_ring(struct i40e_ring *ring)
2167{
2168 struct i40e_vsi *vsi = ring->vsi;
2169 u16 pf_q = vsi->base_queue + ring->queue_index;
2170 struct i40e_hw *hw = &vsi->back->hw;
2171 struct i40e_hmc_obj_txq tx_ctx;
2172 i40e_status err = 0;
2173 u32 qtx_ctl = 0;
2174
2175 /* some ATR related tx ring init */
60ea5f83 2176 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2177 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2178 ring->atr_count = 0;
2179 } else {
2180 ring->atr_sample_rate = 0;
2181 }
2182
2183 /* initialize XPS */
2184 if (ring->q_vector && ring->netdev &&
4e3b35b0 2185 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2186 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2187 netif_set_xps_queue(ring->netdev,
2188 &ring->q_vector->affinity_mask,
2189 ring->queue_index);
2190
2191 /* clear the context structure first */
2192 memset(&tx_ctx, 0, sizeof(tx_ctx));
2193
2194 tx_ctx.new_context = 1;
2195 tx_ctx.base = (ring->dma / 128);
2196 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2197 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2198 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2199 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2200 /* FDIR VSI tx ring can still use RS bit and writebacks */
2201 if (vsi->type != I40E_VSI_FDIR)
2202 tx_ctx.head_wb_ena = 1;
2203 tx_ctx.head_wb_addr = ring->dma +
2204 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2205
2206 /* As part of VSI creation/update, FW allocates certain
2207 * Tx arbitration queue sets for each TC enabled for
2208 * the VSI. The FW returns the handles to these queue
2209 * sets as part of the response buffer to Add VSI,
2210 * Update VSI, etc. AQ commands. It is expected that
2211 * these queue set handles be associated with the Tx
2212 * queues by the driver as part of the TX queue context
2213 * initialization. This has to be done regardless of
2214 * DCB as by default everything is mapped to TC0.
2215 */
2216 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2217 tx_ctx.rdylist_act = 0;
2218
2219 /* clear the context in the HMC */
2220 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2221 if (err) {
2222 dev_info(&vsi->back->pdev->dev,
2223 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2224 ring->queue_index, pf_q, err);
2225 return -ENOMEM;
2226 }
2227
2228 /* set the context in the HMC */
2229 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2230 if (err) {
2231 dev_info(&vsi->back->pdev->dev,
2232 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2233 ring->queue_index, pf_q, err);
2234 return -ENOMEM;
2235 }
2236
2237 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2238 if (vsi->type == I40E_VSI_VMDQ2)
2239 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2240 else
2241 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2242 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2243 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2244 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2245 i40e_flush(hw);
2246
2247 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2248
2249 /* cache tail off for easier writes later */
2250 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2251
2252 return 0;
2253}
2254
2255/**
2256 * i40e_configure_rx_ring - Configure a receive ring context
2257 * @ring: The Rx ring to configure
2258 *
2259 * Configure the Rx descriptor ring in the HMC context.
2260 **/
2261static int i40e_configure_rx_ring(struct i40e_ring *ring)
2262{
2263 struct i40e_vsi *vsi = ring->vsi;
2264 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2265 u16 pf_q = vsi->base_queue + ring->queue_index;
2266 struct i40e_hw *hw = &vsi->back->hw;
2267 struct i40e_hmc_obj_rxq rx_ctx;
2268 i40e_status err = 0;
2269
2270 ring->state = 0;
2271
2272 /* clear the context structure first */
2273 memset(&rx_ctx, 0, sizeof(rx_ctx));
2274
2275 ring->rx_buf_len = vsi->rx_buf_len;
2276 ring->rx_hdr_len = vsi->rx_hdr_len;
2277
2278 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2279 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2280
2281 rx_ctx.base = (ring->dma / 128);
2282 rx_ctx.qlen = ring->count;
2283
2284 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2285 set_ring_16byte_desc_enabled(ring);
2286 rx_ctx.dsize = 0;
2287 } else {
2288 rx_ctx.dsize = 1;
2289 }
2290
2291 rx_ctx.dtype = vsi->dtype;
2292 if (vsi->dtype) {
2293 set_ring_ps_enabled(ring);
2294 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2295 I40E_RX_SPLIT_IP |
2296 I40E_RX_SPLIT_TCP_UDP |
2297 I40E_RX_SPLIT_SCTP;
2298 } else {
2299 rx_ctx.hsplit_0 = 0;
2300 }
2301
2302 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2303 (chain_len * ring->rx_buf_len));
2304 rx_ctx.tphrdesc_ena = 1;
2305 rx_ctx.tphwdesc_ena = 1;
2306 rx_ctx.tphdata_ena = 1;
2307 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2308 if (hw->revision_id == 0)
2309 rx_ctx.lrxqthresh = 0;
2310 else
2311 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2312 rx_ctx.crcstrip = 1;
2313 rx_ctx.l2tsel = 1;
2314 rx_ctx.showiv = 1;
acb3676b
CS		 2315 /* set the prefena field to 1 because the manual says to */
2316 rx_ctx.prefena = 1;
41c445ff
JB		 2317
2318 /* clear the context in the HMC */
2319 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2320 if (err) {
2321 dev_info(&vsi->back->pdev->dev,
2322 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2323 ring->queue_index, pf_q, err);
2324 return -ENOMEM;
2325 }
2326
2327 /* set the context in the HMC */
2328 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2329 if (err) {
2330 dev_info(&vsi->back->pdev->dev,
2331 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2332 ring->queue_index, pf_q, err);
2333 return -ENOMEM;
2334 }
2335
2336 /* cache tail for quicker writes, and clear the reg before use */
2337 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2338 writel(0, ring->tail);
2339
2340 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2341
2342 return 0;
2343}
2344
2345/**
2346 * i40e_vsi_configure_tx - Configure the VSI for Tx
2347 * @vsi: VSI structure describing this set of rings and resources
2348 *
2349 * Configure the Tx VSI for operation.
2350 **/
2351static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2352{
2353 int err = 0;
2354 u16 i;
2355
9f65e15b
AD		 2356 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2357 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2358
2359 return err;
2360}
2361
2362/**
2363 * i40e_vsi_configure_rx - Configure the VSI for Rx
2364 * @vsi: the VSI being configured
2365 *
2366 * Configure the Rx VSI for operation.
2367 **/
2368static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2369{
2370 int err = 0;
2371 u16 i;
2372
2373 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2374 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2375 + ETH_FCS_LEN + VLAN_HLEN;
2376 else
2377 vsi->max_frame = I40E_RXBUFFER_2048;
2378
2379 /* figure out correct receive buffer length */
2380 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2381 I40E_FLAG_RX_PS_ENABLED)) {
2382 case I40E_FLAG_RX_1BUF_ENABLED:
2383 vsi->rx_hdr_len = 0;
2384 vsi->rx_buf_len = vsi->max_frame;
2385 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2386 break;
2387 case I40E_FLAG_RX_PS_ENABLED:
2388 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2389 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2390 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2391 break;
2392 default:
2393 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2394 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2395 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2396 break;
2397 }
2398
2399 /* round up for the chip's needs */
2400 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2401 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2402 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2403 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2404
2405 /* set up individual rings */
2406 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2407 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2408
2409 return err;
2410}
2411
2412/**
2413 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2414 * @vsi: ptr to the VSI
2415 **/
2416static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2417{
2418 u16 qoffset, qcount;
2419 int i, n;
2420
2421 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2422 return;
2423
2424 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2425 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2426 continue;
2427
2428 qoffset = vsi->tc_config.tc_info[n].qoffset;
2429 qcount = vsi->tc_config.tc_info[n].qcount;
2430 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2431 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2432 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2433 rx_ring->dcb_tc = n;
2434 tx_ring->dcb_tc = n;
2435 }
2436 }
2437}
2438
2439/**
2440 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2441 * @vsi: ptr to the VSI
2442 **/
2443static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2444{
2445 if (vsi->netdev)
2446 i40e_set_rx_mode(vsi->netdev);
2447}
2448
17a73f6b
JG		 2449/**
2450 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2451 * @vsi: Pointer to the targeted VSI
2452 *
2453 * This function replays the hlist on the hw where all the SB Flow Director
2454 * filters were saved.
2455 **/
2456static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2457{
2458 struct i40e_fdir_filter *filter;
2459 struct i40e_pf *pf = vsi->back;
2460 struct hlist_node *node;
2461
55a5e60b
ASJ		 2462 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2463 return;
2464
17a73f6b
JG		 2465 hlist_for_each_entry_safe(filter, node,
2466 &pf->fdir_filter_list, fdir_node) {
2467 i40e_add_del_fdir(vsi, filter, true);
2468 }
2469}
2470
41c445ff
JB		 2471/**
2472 * i40e_vsi_configure - Set up the VSI for action
2473 * @vsi: the VSI being configured
2474 **/
2475static int i40e_vsi_configure(struct i40e_vsi *vsi)
2476{
2477 int err;
2478
2479 i40e_set_vsi_rx_mode(vsi);
2480 i40e_restore_vlan(vsi);
2481 i40e_vsi_config_dcb_rings(vsi);
2482 err = i40e_vsi_configure_tx(vsi);
2483 if (!err)
2484 err = i40e_vsi_configure_rx(vsi);
2485
2486 return err;
2487}
2488
2489/**
2490 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2491 * @vsi: the VSI being configured
2492 **/
2493static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2494{
2495 struct i40e_pf *pf = vsi->back;
2496 struct i40e_q_vector *q_vector;
2497 struct i40e_hw *hw = &pf->hw;
2498 u16 vector;
2499 int i, q;
2500 u32 val;
2501 u32 qp;
2502
2503 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2504 * and PFINT_LNKLSTn registers, e.g.:
2505 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2506 */
2507 qp = vsi->base_queue;
2508 vector = vsi->base_vector;
493fb300
AD		 2509 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2510 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2511 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2512 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2513 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2514 q_vector->rx.itr);
2515 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2516 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2517 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2518 q_vector->tx.itr);
2519
2520 /* Linked list for the queuepairs assigned to this vector */
2521 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2522 for (q = 0; q < q_vector->num_ringpairs; q++) {
2523 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2524 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2525 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2526 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2527 (I40E_QUEUE_TYPE_TX
2528 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2529
2530 wr32(hw, I40E_QINT_RQCTL(qp), val);
2531
2532 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2533 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2534 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2535 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2536 (I40E_QUEUE_TYPE_RX
2537 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2538
2539 /* Terminate the linked list */
2540 if (q == (q_vector->num_ringpairs - 1))
2541 val |= (I40E_QUEUE_END_OF_LIST
2542 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2543
2544 wr32(hw, I40E_QINT_TQCTL(qp), val);
2545 qp++;
2546 }
2547 }
2548
2549 i40e_flush(hw);
2550}
2551
2552/**
2553 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2554 * @hw: ptr to the hardware info
2555 **/
2556static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2557{
2558 u32 val;
2559
2560 /* clear things first */
2561 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2562 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2563
2564 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2565 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2566 I40E_PFINT_ICR0_ENA_GRST_MASK |
2567 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2568 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2569 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2570 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2571 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2572 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2573 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2574
2575 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2576
2577 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2578 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2579 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2580
2581 /* OTHER_ITR_IDX = 0 */
2582 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2583}
2584
2585/**
2586 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2587 * @vsi: the VSI being configured
2588 **/
2589static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2590{
493fb300 2591 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2592 struct i40e_pf *pf = vsi->back;
2593 struct i40e_hw *hw = &pf->hw;
2594 u32 val;
2595
2596 /* set the ITR configuration */
2597 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2598 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2599 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2600 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2601 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2602 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2603
2604 i40e_enable_misc_int_causes(hw);
2605
2606 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2607 wr32(hw, I40E_PFINT_LNKLST0, 0);
2608
f29eaa3d 2609 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2610 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2611 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2612 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2613
2614 wr32(hw, I40E_QINT_RQCTL(0), val);
2615
2616 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2617 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2618 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2619
2620 wr32(hw, I40E_QINT_TQCTL(0), val);
2621 i40e_flush(hw);
2622}
2623
2ef28cfb
MW		 2624/**
2625 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2626 * @pf: board private structure
2627 **/
2628void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2629{
2630 struct i40e_hw *hw = &pf->hw;
2631
2632 wr32(hw, I40E_PFINT_DYN_CTL0,
2633 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2634 i40e_flush(hw);
2635}
2636
41c445ff
JB		 2637/**
2638 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2639 * @pf: board private structure
2640 **/
116a57d4 2641void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2642{
2643 struct i40e_hw *hw = &pf->hw;
2644 u32 val;
2645
2646 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2647 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2648 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2649
2650 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2651 i40e_flush(hw);
2652}
2653
2654/**
2655 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2656 * @vsi: pointer to a vsi
2657 * @vector: enable a particular Hw Interrupt vector
2658 **/
2659void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2660{
2661 struct i40e_pf *pf = vsi->back;
2662 struct i40e_hw *hw = &pf->hw;
2663 u32 val;
2664
2665 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2666 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2667 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2668 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2669 /* skip the flush */
41c445ff
JB		 2670}
2671
2672/**
2673 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2674 * @irq: interrupt number
2675 * @data: pointer to a q_vector
2676 **/
2677static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2678{
2679 struct i40e_q_vector *q_vector = data;
2680
cd0b6fa6 2681 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2682 return IRQ_HANDLED;
2683
2684 napi_schedule(&q_vector->napi);
2685
2686 return IRQ_HANDLED;
2687}
2688
41c445ff
JB		 2689/**
2690 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2691 * @vsi: the VSI being configured
2692 * @basename: name for the vector
2693 *
2694 * Allocates MSI-X vectors and requests interrupts from the kernel.
2695 **/
2696static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2697{
2698 int q_vectors = vsi->num_q_vectors;
2699 struct i40e_pf *pf = vsi->back;
2700 int base = vsi->base_vector;
2701 int rx_int_idx = 0;
2702 int tx_int_idx = 0;
2703 int vector, err;
2704
2705 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2706 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2707
cd0b6fa6 2708 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2709 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2710 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2711 tx_int_idx++;
cd0b6fa6 2712 } else if (q_vector->rx.ring) {
41c445ff
JB		 2713 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2714 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2715 } else if (q_vector->tx.ring) {
41c445ff
JB		 2716 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2717 "%s-%s-%d", basename, "tx", tx_int_idx++);
2718 } else {
2719 /* skip this unused q_vector */
2720 continue;
2721 }
2722 err = request_irq(pf->msix_entries[base + vector].vector,
2723 vsi->irq_handler,
2724 0,
2725 q_vector->name,
2726 q_vector);
2727 if (err) {
2728 dev_info(&pf->pdev->dev,
2729 "%s: request_irq failed, error: %d\n",
2730 __func__, err);
2731 goto free_queue_irqs;
2732 }
2733 /* assign the mask for this irq */
2734 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2735 &q_vector->affinity_mask);
2736 }
2737
2738 return 0;
2739
2740free_queue_irqs:
2741 while (vector) {
2742 vector--;
2743 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2744 NULL);
2745 free_irq(pf->msix_entries[base + vector].vector,
2746 &(vsi->q_vectors[vector]));
2747 }
2748 return err;
2749}
2750
2751/**
2752 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2753 * @vsi: the VSI being un-configured
2754 **/
2755static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2756{
2757 struct i40e_pf *pf = vsi->back;
2758 struct i40e_hw *hw = &pf->hw;
2759 int base = vsi->base_vector;
2760 int i;
2761
2762 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2763 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2764 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2765 }
2766
2767 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2768 for (i = vsi->base_vector;
2769 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2770 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2771
2772 i40e_flush(hw);
2773 for (i = 0; i < vsi->num_q_vectors; i++)
2774 synchronize_irq(pf->msix_entries[i + base].vector);
2775 } else {
2776 /* Legacy and MSI mode - this stops all interrupt handling */
2777 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2778 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2779 i40e_flush(hw);
2780 synchronize_irq(pf->pdev->irq);
2781 }
2782}
2783
2784/**
2785 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2786 * @vsi: the VSI being configured
2787 **/
2788static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2789{
2790 struct i40e_pf *pf = vsi->back;
2791 int i;
2792
2793 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2794 for (i = vsi->base_vector;
2795 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2796 i40e_irq_dynamic_enable(vsi, i);
2797 } else {
2798 i40e_irq_dynamic_enable_icr0(pf);
2799 }
2800
1022cb6c 2801 i40e_flush(&pf->hw);
41c445ff
JB		 2802 return 0;
2803}
2804
2805/**
2806 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2807 * @pf: board private structure
2808 **/
2809static void i40e_stop_misc_vector(struct i40e_pf *pf)
2810{
2811 /* Disable ICR 0 */
2812 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2813 i40e_flush(&pf->hw);
2814}
2815
2816/**
2817 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2818 * @irq: interrupt number
2819 * @data: pointer to a q_vector
2820 *
2821 * This is the handler used for all MSI/Legacy interrupts, and deals
2822 * with both queue and non-queue interrupts. This is also used in
2823 * MSIX mode to handle the non-queue interrupts.
2824 **/
2825static irqreturn_t i40e_intr(int irq, void *data)
2826{
2827 struct i40e_pf *pf = (struct i40e_pf *)data;
2828 struct i40e_hw *hw = &pf->hw;
5e823066 2829 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2830 u32 icr0, icr0_remaining;
2831 u32 val, ena_mask;
2832
2833 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2834 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2835
116a57d4
SN		 2836 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2837 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2838 goto enable_intr;
41c445ff 2839
cd92e72f
SN		 2840 /* if interrupt but no bits showing, must be SWINT */
2841 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2842 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2843 pf->sw_int_count++;
2844
41c445ff
JB		 2845 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2846 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2847
2848 /* temporarily disable queue cause for NAPI processing */
2849 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2850 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2851 wr32(hw, I40E_QINT_RQCTL(0), qval);
2852
2853 qval = rd32(hw, I40E_QINT_TQCTL(0));
2854 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2855 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2856
2857 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2858 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2859 }
2860
2861 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2862 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2863 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2864 }
2865
2866 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2867 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2868 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2869 }
2870
2871 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2872 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2873 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2874 }
2875
2876 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2877 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2878 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2879 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2880 val = rd32(hw, I40E_GLGEN_RSTAT);
2881 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2882 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2883 if (val == I40E_RESET_CORER) {
41c445ff 2884 pf->corer_count++;
4eb3f768 2885 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2886 pf->globr_count++;
4eb3f768 2887 } else if (val == I40E_RESET_EMPR) {
41c445ff 2888 pf->empr_count++;
4eb3f768
SN		 2889 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2890 }
41c445ff
JB		 2891 }
2892
9c010ee0
ASJ		 2893 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2894 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2895 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2896 }
2897
beb0dff1
JK		 2898 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2899 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2900
2901 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2902 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2903 i40e_ptp_tx_hwtstamp(pf);
2904 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2905 }
2906
2907 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2908 }
2909
41c445ff
JB		 2910 /* If a critical error is pending we have no choice but to reset the
2911 * device.
2912 * Report and mask out any remaining unexpected interrupts.
2913 */
2914 icr0_remaining = icr0 & ena_mask;
2915 if (icr0_remaining) {
2916 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2917 icr0_remaining);
9c010ee0 2918 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2919 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2920 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2921 dev_info(&pf->pdev->dev, "device will be reset\n");
2922 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2923 i40e_service_event_schedule(pf);
41c445ff
JB		 2924 }
2925 ena_mask &= ~icr0_remaining;
2926 }
5e823066 2927 ret = IRQ_HANDLED;
41c445ff 2928
5e823066 2929enable_intr:
41c445ff
JB		 2930 /* re-enable interrupt causes */
2931 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2932 if (!test_bit(__I40E_DOWN, &pf->state)) {
2933 i40e_service_event_schedule(pf);
2934 i40e_irq_dynamic_enable_icr0(pf);
2935 }
2936
5e823066 2937 return ret;
41c445ff
JB		 2938}
2939
cbf61325
ASJ		 2940/**
2941 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2942 * @tx_ring: tx ring to clean
2943 * @budget: how many cleans we're allowed
2944 *
2945 * Returns true if there's any budget left (e.g. the clean is finished)
2946 **/
2947static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2948{
2949 struct i40e_vsi *vsi = tx_ring->vsi;
2950 u16 i = tx_ring->next_to_clean;
2951 struct i40e_tx_buffer *tx_buf;
2952 struct i40e_tx_desc *tx_desc;
2953
2954 tx_buf = &tx_ring->tx_bi[i];
2955 tx_desc = I40E_TX_DESC(tx_ring, i);
2956 i -= tx_ring->count;
2957
2958 do {
2959 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2960
2961 /* if next_to_watch is not set then there is no work pending */
2962 if (!eop_desc)
2963 break;
2964
2965 /* prevent any other reads prior to eop_desc */
2966 read_barrier_depends();
2967
2968 /* if the descriptor isn't done, no work yet to do */
2969 if (!(eop_desc->cmd_type_offset_bsz &
2970 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2971 break;
2972
2973 /* clear next_to_watch to prevent false hangs */
2974 tx_buf->next_to_watch = NULL;
2975
2976 /* unmap skb header data */
2977 dma_unmap_single(tx_ring->dev,
2978 dma_unmap_addr(tx_buf, dma),
2979 dma_unmap_len(tx_buf, len),
2980 DMA_TO_DEVICE);
2981
2982 dma_unmap_len_set(tx_buf, len, 0);
2983
2984
2985 /* move to the next desc and buffer to clean */
2986 tx_buf++;
2987 tx_desc++;
2988 i++;
2989 if (unlikely(!i)) {
2990 i -= tx_ring->count;
2991 tx_buf = tx_ring->tx_bi;
2992 tx_desc = I40E_TX_DESC(tx_ring, 0);
2993 }
2994
2995 /* update budget accounting */
2996 budget--;
2997 } while (likely(budget));
2998
2999 i += tx_ring->count;
3000 tx_ring->next_to_clean = i;
3001
3002 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3003 i40e_irq_dynamic_enable(vsi,
3004 tx_ring->q_vector->v_idx + vsi->base_vector);
3005 }
3006 return budget > 0;
3007}
3008
3009/**
3010 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3011 * @irq: interrupt number
3012 * @data: pointer to a q_vector
3013 **/
3014static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3015{
3016 struct i40e_q_vector *q_vector = data;
3017 struct i40e_vsi *vsi;
3018
3019 if (!q_vector->tx.ring)
3020 return IRQ_HANDLED;
3021
3022 vsi = q_vector->tx.ring->vsi;
3023 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3024
3025 return IRQ_HANDLED;
3026}
3027
41c445ff 3028/**
cd0b6fa6 3029 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3030 * @vsi: the VSI being configured
3031 * @v_idx: vector index
cd0b6fa6 3032 * @qp_idx: queue pair index
41c445ff 3033 **/
cd0b6fa6 3034static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3035{
493fb300 3036 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3037 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3038 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3039
3040 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3041 tx_ring->next = q_vector->tx.ring;
3042 q_vector->tx.ring = tx_ring;
41c445ff 3043 q_vector->tx.count++;
cd0b6fa6
AD		 3044
3045 rx_ring->q_vector = q_vector;
3046 rx_ring->next = q_vector->rx.ring;
3047 q_vector->rx.ring = rx_ring;
3048 q_vector->rx.count++;
41c445ff
JB		 3049}
3050
3051/**
3052 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3053 * @vsi: the VSI being configured
3054 *
3055 * This function maps descriptor rings to the queue-specific vectors
3056 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3057 * one vector per queue pair, but on a constrained vector budget, we
3058 * group the queue pairs as "efficiently" as possible.
3059 **/
3060static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3061{
3062 int qp_remaining = vsi->num_queue_pairs;
3063 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3064 int num_ringpairs;
41c445ff
JB		 3065 int v_start = 0;
3066 int qp_idx = 0;
3067
3068 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3069 * group them so there are multiple queues per vector.
3070 */
3071 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3072 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3073
3074 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3075
3076 q_vector->num_ringpairs = num_ringpairs;
3077
3078 q_vector->rx.count = 0;
3079 q_vector->tx.count = 0;
3080 q_vector->rx.ring = NULL;
3081 q_vector->tx.ring = NULL;
3082
3083 while (num_ringpairs--) {
3084 map_vector_to_qp(vsi, v_start, qp_idx);
3085 qp_idx++;
3086 qp_remaining--;
41c445ff
JB		 3087 }
3088 }
3089}
3090
3091/**
3092 * i40e_vsi_request_irq - Request IRQ from the OS
3093 * @vsi: the VSI being configured
3094 * @basename: name for the vector
3095 **/
3096static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3097{
3098 struct i40e_pf *pf = vsi->back;
3099 int err;
3100
3101 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3102 err = i40e_vsi_request_irq_msix(vsi, basename);
3103 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3104 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3105 pf->misc_int_name, pf);
3106 else
3107 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3108 pf->misc_int_name, pf);
3109
3110 if (err)
3111 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3112
3113 return err;
3114}
3115
3116#ifdef CONFIG_NET_POLL_CONTROLLER
3117/**
3118 * i40e_netpoll - A Polling 'interrupt'handler
3119 * @netdev: network interface device structure
3120 *
3121 * This is used by netconsole to send skbs without having to re-enable
3122 * interrupts. It's not called while the normal interrupt routine is executing.
3123 **/
3124static void i40e_netpoll(struct net_device *netdev)
3125{
3126 struct i40e_netdev_priv *np = netdev_priv(netdev);
3127 struct i40e_vsi *vsi = np->vsi;
3128 struct i40e_pf *pf = vsi->back;
3129 int i;
3130
3131 /* if interface is down do nothing */
3132 if (test_bit(__I40E_DOWN, &vsi->state))
3133 return;
3134
3135 pf->flags |= I40E_FLAG_IN_NETPOLL;
3136 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3137 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3138 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3139 } else {
3140 i40e_intr(pf->pdev->irq, netdev);
3141 }
3142 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3143}
3144#endif
3145
3146/**
3147 * i40e_vsi_control_tx - Start or stop a VSI's rings
3148 * @vsi: the VSI being configured
3149 * @enable: start or stop the rings
3150 **/
3151static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3152{
3153 struct i40e_pf *pf = vsi->back;
3154 struct i40e_hw *hw = &pf->hw;
3155 int i, j, pf_q;
3156 u32 tx_reg;
3157
3158 pf_q = vsi->base_queue;
3159 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3160 for (j = 0; j < 50; j++) {
41c445ff 3161 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3162 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3163 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3164 break;
3165 usleep_range(1000, 2000);
3166 }
fda972f6
MW		 3167 /* Skip if the queue is already in the requested state */
3168 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3169 continue;
3170 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3171 continue;
41c445ff
JB		 3172
3173 /* turn on/off the queue */
c5c9eb9e
SN		 3174 if (enable) {
3175 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3176 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3177 } else {
41c445ff 3178 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3179 }
41c445ff
JB		 3180
3181 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3182
3183 /* wait for the change to finish */
3184 for (j = 0; j < 10; j++) {
3185 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3186 if (enable) {
3187 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3188 break;
3189 } else {
3190 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3191 break;
3192 }
3193
3194 udelay(10);
3195 }
3196 if (j >= 10) {
3197 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3198 pf_q, (enable ? "en" : "dis"));
3199 return -ETIMEDOUT;
3200 }
3201 }
3202
7134f9ce
JB		 3203 if (hw->revision_id == 0)
3204 mdelay(50);
3205
41c445ff
JB		 3206 return 0;
3207}
3208
3209/**
3210 * i40e_vsi_control_rx - Start or stop a VSI's rings
3211 * @vsi: the VSI being configured
3212 * @enable: start or stop the rings
3213 **/
3214static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3215{
3216 struct i40e_pf *pf = vsi->back;
3217 struct i40e_hw *hw = &pf->hw;
3218 int i, j, pf_q;
3219 u32 rx_reg;
3220
3221 pf_q = vsi->base_queue;
3222 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3223 for (j = 0; j < 50; j++) {
41c445ff 3224 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3225 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3226 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3227 break;
3228 usleep_range(1000, 2000);
3229 }
41c445ff
JB		 3230
3231 if (enable) {
3232 /* is STAT set ? */
3233 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3234 continue;
3235 } else {
3236 /* is !STAT set ? */
3237 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3238 continue;
3239 }
3240
3241 /* turn on/off the queue */
3242 if (enable)
6c5ef620 3243 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3244 else
6c5ef620 3245 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3246 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3247
3248 /* wait for the change to finish */
3249 for (j = 0; j < 10; j++) {
3250 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3251
3252 if (enable) {
3253 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3254 break;
3255 } else {
3256 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3257 break;
3258 }
3259
3260 udelay(10);
3261 }
3262 if (j >= 10) {
3263 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3264 pf_q, (enable ? "en" : "dis"));
3265 return -ETIMEDOUT;
3266 }
3267 }
3268
3269 return 0;
3270}
3271
3272/**
3273 * i40e_vsi_control_rings - Start or stop a VSI's rings
3274 * @vsi: the VSI being configured
3275 * @enable: start or stop the rings
3276 **/
fc18eaa0 3277int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3278{
3b867b28 3279 int ret = 0;
41c445ff
JB		 3280
3281 /* do rx first for enable and last for disable */
3282 if (request) {
3283 ret = i40e_vsi_control_rx(vsi, request);
3284 if (ret)
3285 return ret;
3286 ret = i40e_vsi_control_tx(vsi, request);
3287 } else {
3b867b28
ASJ		 3288 /* Ignore return value, we need to shutdown whatever we can */
3289 i40e_vsi_control_tx(vsi, request);
3290 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3291 }
3292
3293 return ret;
3294}
3295
3296/**
3297 * i40e_vsi_free_irq - Free the irq association with the OS
3298 * @vsi: the VSI being configured
3299 **/
3300static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3301{
3302 struct i40e_pf *pf = vsi->back;
3303 struct i40e_hw *hw = &pf->hw;
3304 int base = vsi->base_vector;
3305 u32 val, qp;
3306 int i;
3307
3308 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3309 if (!vsi->q_vectors)
3310 return;
3311
3312 for (i = 0; i < vsi->num_q_vectors; i++) {
3313 u16 vector = i + base;
3314
3315 /* free only the irqs that were actually requested */
78681b1f
SN		 3316 if (!vsi->q_vectors[i] ||
3317 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3318 continue;
3319
3320 /* clear the affinity_mask in the IRQ descriptor */
3321 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3322 NULL);
3323 free_irq(pf->msix_entries[vector].vector,
493fb300 3324 vsi->q_vectors[i]);
41c445ff
JB		 3325
3326 /* Tear down the interrupt queue link list
3327 *
3328 * We know that they come in pairs and always
3329 * the Rx first, then the Tx. To clear the
3330 * link list, stick the EOL value into the
3331 * next_q field of the registers.
3332 */
3333 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3334 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3335 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3336 val |= I40E_QUEUE_END_OF_LIST
3337 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3338 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3339
3340 while (qp != I40E_QUEUE_END_OF_LIST) {
3341 u32 next;
3342
3343 val = rd32(hw, I40E_QINT_RQCTL(qp));
3344
3345 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3346 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3347 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3348 I40E_QINT_RQCTL_INTEVENT_MASK);
3349
3350 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3351 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3352
3353 wr32(hw, I40E_QINT_RQCTL(qp), val);
3354
3355 val = rd32(hw, I40E_QINT_TQCTL(qp));
3356
3357 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3358 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3359
3360 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3361 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3362 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3363 I40E_QINT_TQCTL_INTEVENT_MASK);
3364
3365 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3366 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3367
3368 wr32(hw, I40E_QINT_TQCTL(qp), val);
3369 qp = next;
3370 }
3371 }
3372 } else {
3373 free_irq(pf->pdev->irq, pf);
3374
3375 val = rd32(hw, I40E_PFINT_LNKLST0);
3376 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3377 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3378 val |= I40E_QUEUE_END_OF_LIST
3379 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3380 wr32(hw, I40E_PFINT_LNKLST0, val);
3381
3382 val = rd32(hw, I40E_QINT_RQCTL(qp));
3383 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3384 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3385 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3386 I40E_QINT_RQCTL_INTEVENT_MASK);
3387
3388 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3389 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3390
3391 wr32(hw, I40E_QINT_RQCTL(qp), val);
3392
3393 val = rd32(hw, I40E_QINT_TQCTL(qp));
3394
3395 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3396 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3397 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3398 I40E_QINT_TQCTL_INTEVENT_MASK);
3399
3400 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3401 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3402
3403 wr32(hw, I40E_QINT_TQCTL(qp), val);
3404 }
3405}
3406
493fb300
AD		 3407/**
3408 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3409 * @vsi: the VSI being configured
3410 * @v_idx: Index of vector to be freed
3411 *
3412 * This function frees the memory allocated to the q_vector. In addition if
3413 * NAPI is enabled it will delete any references to the NAPI struct prior
3414 * to freeing the q_vector.
3415 **/
3416static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3417{
3418 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3419 struct i40e_ring *ring;
493fb300
AD		 3420
3421 if (!q_vector)
3422 return;
3423
3424 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3425 i40e_for_each_ring(ring, q_vector->tx)
3426 ring->q_vector = NULL;
3427
3428 i40e_for_each_ring(ring, q_vector->rx)
3429 ring->q_vector = NULL;
493fb300
AD		 3430
3431 /* only VSI w/ an associated netdev is set up w/ NAPI */
3432 if (vsi->netdev)
3433 netif_napi_del(&q_vector->napi);
3434
3435 vsi->q_vectors[v_idx] = NULL;
3436
3437 kfree_rcu(q_vector, rcu);
3438}
3439
41c445ff
JB		 3440/**
3441 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3442 * @vsi: the VSI being un-configured
3443 *
3444 * This frees the memory allocated to the q_vectors and
3445 * deletes references to the NAPI struct.
3446 **/
3447static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3448{
3449 int v_idx;
3450
493fb300
AD		 3451 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3452 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3453}
3454
3455/**
3456 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3457 * @pf: board private structure
3458 **/
3459static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3460{
3461 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3462 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3463 pci_disable_msix(pf->pdev);
3464 kfree(pf->msix_entries);
3465 pf->msix_entries = NULL;
3466 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3467 pci_disable_msi(pf->pdev);
3468 }
3469 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3470}
3471
3472/**
3473 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3474 * @pf: board private structure
3475 *
3476 * We go through and clear interrupt specific resources and reset the structure
3477 * to pre-load conditions
3478 **/
3479static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3480{
3481 int i;
3482
3483 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3484 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3485 if (pf->vsi[i])
3486 i40e_vsi_free_q_vectors(pf->vsi[i]);
3487 i40e_reset_interrupt_capability(pf);
3488}
3489
3490/**
3491 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3492 * @vsi: the VSI being configured
3493 **/
3494static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3495{
3496 int q_idx;
3497
3498 if (!vsi->netdev)
3499 return;
3500
3501 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3502 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3503}
3504
3505/**
3506 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3507 * @vsi: the VSI being configured
3508 **/
3509static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3510{
3511 int q_idx;
3512
3513 if (!vsi->netdev)
3514 return;
3515
3516 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3517 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3518}
3519
3520/**
3521 * i40e_quiesce_vsi - Pause a given VSI
3522 * @vsi: the VSI being paused
3523 **/
3524static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3525{
3526 if (test_bit(__I40E_DOWN, &vsi->state))
3527 return;
3528
3529 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3530 if (vsi->netdev && netif_running(vsi->netdev)) {
3531 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3532 } else {
3533 set_bit(__I40E_DOWN, &vsi->state);
3534 i40e_down(vsi);
3535 }
3536}
3537
3538/**
3539 * i40e_unquiesce_vsi - Resume a given VSI
3540 * @vsi: the VSI being resumed
3541 **/
3542static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3543{
3544 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3545 return;
3546
3547 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3548 if (vsi->netdev && netif_running(vsi->netdev))
3549 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3550 else
3551 i40e_up(vsi); /* this clears the DOWN bit */
3552}
3553
3554/**
3555 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3556 * @pf: the PF
3557 **/
3558static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3559{
3560 int v;
3561
3562 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3563 if (pf->vsi[v])
3564 i40e_quiesce_vsi(pf->vsi[v]);
3565 }
3566}
3567
3568/**
3569 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3570 * @pf: the PF
3571 **/
3572static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3573{
3574 int v;
3575
3576 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3577 if (pf->vsi[v])
3578 i40e_unquiesce_vsi(pf->vsi[v]);
3579 }
3580}
3581
3582/**
3583 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3584 * @dcbcfg: the corresponding DCBx configuration structure
3585 *
3586 * Return the number of TCs from given DCBx configuration
3587 **/
3588static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3589{
078b5876
JB		 3590 u8 num_tc = 0;
3591 int i;
41c445ff
JB		 3592
3593 /* Scan the ETS Config Priority Table to find
3594 * traffic class enabled for a given priority
3595 * and use the traffic class index to get the
3596 * number of traffic classes enabled
3597 */
3598 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3599 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3600 num_tc = dcbcfg->etscfg.prioritytable[i];
3601 }
3602
3603 /* Traffic class index starts from zero so
3604 * increment to return the actual count
3605 */
078b5876 3606 return num_tc + 1;
41c445ff
JB		 3607}
3608
3609/**
3610 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3611 * @dcbcfg: the corresponding DCBx configuration structure
3612 *
3613 * Query the current DCB configuration and return the number of
3614 * traffic classes enabled from the given DCBX config
3615 **/
3616static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3617{
3618 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3619 u8 enabled_tc = 1;
3620 u8 i;
3621
3622 for (i = 0; i < num_tc; i++)
3623 enabled_tc |= 1 << i;
3624
3625 return enabled_tc;
3626}
3627
3628/**
3629 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3630 * @pf: PF being queried
3631 *
3632 * Return number of traffic classes enabled for the given PF
3633 **/
3634static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3635{
3636 struct i40e_hw *hw = &pf->hw;
3637 u8 i, enabled_tc;
3638 u8 num_tc = 0;
3639 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3640
3641 /* If DCB is not enabled then always in single TC */
3642 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3643 return 1;
3644
3645 /* MFP mode return count of enabled TCs for this PF */
3646 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3647 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3648 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3649 if (enabled_tc & (1 << i))
3650 num_tc++;
3651 }
3652 return num_tc;
3653 }
3654
3655 /* SFP mode will be enabled for all TCs on port */
3656 return i40e_dcb_get_num_tc(dcbcfg);
3657}
3658
3659/**
3660 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3661 * @pf: PF being queried
3662 *
3663 * Return a bitmap for first enabled traffic class for this PF.
3664 **/
3665static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3666{
3667 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3668 u8 i = 0;
3669
3670 if (!enabled_tc)
3671 return 0x1; /* TC0 */
3672
3673 /* Find the first enabled TC */
3674 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3675 if (enabled_tc & (1 << i))
3676 break;
3677 }
3678
3679 return 1 << i;
3680}
3681
3682/**
3683 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3684 * @pf: PF being queried
3685 *
3686 * Return a bitmap for enabled traffic classes for this PF.
3687 **/
3688static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3689{
3690 /* If DCB is not enabled for this PF then just return default TC */
3691 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3692 return i40e_pf_get_default_tc(pf);
3693
3694 /* MFP mode will have enabled TCs set by FW */
3695 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3696 return pf->hw.func_caps.enabled_tcmap;
3697
3698 /* SFP mode we want PF to be enabled for all TCs */
3699 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3700}
3701
3702/**
3703 * i40e_vsi_get_bw_info - Query VSI BW Information
3704 * @vsi: the VSI being queried
3705 *
3706 * Returns 0 on success, negative value on failure
3707 **/
3708static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3709{
3710 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3711 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3712 struct i40e_pf *pf = vsi->back;
3713 struct i40e_hw *hw = &pf->hw;
dcae29be 3714 i40e_status aq_ret;
41c445ff 3715 u32 tc_bw_max;
41c445ff
JB		 3716 int i;
3717
3718 /* Get the VSI level BW configuration */
dcae29be
JB		 3719 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3720 if (aq_ret) {
41c445ff
JB		 3721 dev_info(&pf->pdev->dev,
3722 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3723 aq_ret, pf->hw.aq.asq_last_status);
3724 return -EINVAL;
41c445ff
JB		 3725 }
3726
3727 /* Get the VSI level BW configuration per TC */
dcae29be 3728 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3729 NULL);
dcae29be 3730 if (aq_ret) {
41c445ff
JB		 3731 dev_info(&pf->pdev->dev,
3732 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3733 aq_ret, pf->hw.aq.asq_last_status);
3734 return -EINVAL;
41c445ff
JB		 3735 }
3736
3737 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3738 dev_info(&pf->pdev->dev,
3739 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3740 bw_config.tc_valid_bits,
3741 bw_ets_config.tc_valid_bits);
3742 /* Still continuing */
3743 }
3744
3745 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3746 vsi->bw_max_quanta = bw_config.max_bw;
3747 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3748 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3749 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3750 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3751 vsi->bw_ets_limit_credits[i] =
3752 le16_to_cpu(bw_ets_config.credits[i]);
3753 /* 3 bits out of 4 for each TC */
3754 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3755 }
078b5876 3756
dcae29be 3757 return 0;
41c445ff
JB		 3758}
3759
3760/**
3761 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3762 * @vsi: the VSI being configured
3763 * @enabled_tc: TC bitmap
3764 * @bw_credits: BW shared credits per TC
3765 *
3766 * Returns 0 on success, negative value on failure
3767 **/
dcae29be 3768static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3769 u8 *bw_share)
3770{
3771 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3772 i40e_status aq_ret;
3773 int i;
41c445ff
JB		 3774
3775 bw_data.tc_valid_bits = enabled_tc;
3776 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3777 bw_data.tc_bw_credits[i] = bw_share[i];
3778
dcae29be
JB		 3779 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3780 NULL);
3781 if (aq_ret) {
41c445ff 3782 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3783 "AQ command Config VSI BW allocation per TC failed = %d\n",
3784 vsi->back->hw.aq.asq_last_status);
dcae29be 3785 return -EINVAL;
41c445ff
JB		 3786 }
3787
3788 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3789 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3790
dcae29be 3791 return 0;
41c445ff
JB		 3792}
3793
3794/**
3795 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3796 * @vsi: the VSI being configured
3797 * @enabled_tc: TC map to be enabled
3798 *
3799 **/
3800static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3801{
3802 struct net_device *netdev = vsi->netdev;
3803 struct i40e_pf *pf = vsi->back;
3804 struct i40e_hw *hw = &pf->hw;
3805 u8 netdev_tc = 0;
3806 int i;
3807 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3808
3809 if (!netdev)
3810 return;
3811
3812 if (!enabled_tc) {
3813 netdev_reset_tc(netdev);
3814 return;
3815 }
3816
3817 /* Set up actual enabled TCs on the VSI */
3818 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3819 return;
3820
3821 /* set per TC queues for the VSI */
3822 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3823 /* Only set TC queues for enabled tcs
3824 *
3825 * e.g. For a VSI that has TC0 and TC3 enabled the
3826 * enabled_tc bitmap would be 0x00001001; the driver
3827 * will set the numtc for netdev as 2 that will be
3828 * referenced by the netdev layer as TC 0 and 1.
3829 */
3830 if (vsi->tc_config.enabled_tc & (1 << i))
3831 netdev_set_tc_queue(netdev,
3832 vsi->tc_config.tc_info[i].netdev_tc,
3833 vsi->tc_config.tc_info[i].qcount,
3834 vsi->tc_config.tc_info[i].qoffset);
3835 }
3836
3837 /* Assign UP2TC map for the VSI */
3838 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3839 /* Get the actual TC# for the UP */
3840 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3841 /* Get the mapped netdev TC# for the UP */
3842 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3843 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3844 }
3845}
3846
3847/**
3848 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3849 * @vsi: the VSI being configured
3850 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3851 **/
3852static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3853 struct i40e_vsi_context *ctxt)
3854{
3855 /* copy just the sections touched not the entire info
3856 * since not all sections are valid as returned by
3857 * update vsi params
3858 */
3859 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3860 memcpy(&vsi->info.queue_mapping,
3861 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3862 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3863 sizeof(vsi->info.tc_mapping));
3864}
3865
3866/**
3867 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3868 * @vsi: VSI to be configured
3869 * @enabled_tc: TC bitmap
3870 *
3871 * This configures a particular VSI for TCs that are mapped to the
3872 * given TC bitmap. It uses default bandwidth share for TCs across
3873 * VSIs to configure TC for a particular VSI.
3874 *
3875 * NOTE:
3876 * It is expected that the VSI queues have been quisced before calling
3877 * this function.
3878 **/
3879static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3880{
3881 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3882 struct i40e_vsi_context ctxt;
3883 int ret = 0;
3884 int i;
3885
3886 /* Check if enabled_tc is same as existing or new TCs */
3887 if (vsi->tc_config.enabled_tc == enabled_tc)
3888 return ret;
3889
3890 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3891 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3892 if (enabled_tc & (1 << i))
3893 bw_share[i] = 1;
3894 }
3895
3896 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3897 if (ret) {
3898 dev_info(&vsi->back->pdev->dev,
3899 "Failed configuring TC map %d for VSI %d\n",
3900 enabled_tc, vsi->seid);
3901 goto out;
3902 }
3903
3904 /* Update Queue Pairs Mapping for currently enabled UPs */
3905 ctxt.seid = vsi->seid;
3906 ctxt.pf_num = vsi->back->hw.pf_id;
3907 ctxt.vf_num = 0;
3908 ctxt.uplink_seid = vsi->uplink_seid;
3909 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3910 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3911
3912 /* Update the VSI after updating the VSI queue-mapping information */
3913 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3914 if (ret) {
3915 dev_info(&vsi->back->pdev->dev,
3916 "update vsi failed, aq_err=%d\n",
3917 vsi->back->hw.aq.asq_last_status);
3918 goto out;
3919 }
3920 /* update the local VSI info with updated queue map */
3921 i40e_vsi_update_queue_map(vsi, &ctxt);
3922 vsi->info.valid_sections = 0;
3923
3924 /* Update current VSI BW information */
3925 ret = i40e_vsi_get_bw_info(vsi);
3926 if (ret) {
3927 dev_info(&vsi->back->pdev->dev,
3928 "Failed updating vsi bw info, aq_err=%d\n",
3929 vsi->back->hw.aq.asq_last_status);
3930 goto out;
3931 }
3932
3933 /* Update the netdev TC setup */
3934 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3935out:
3936 return ret;
3937}
3938
4e3b35b0
NP		 3939/**
3940 * i40e_veb_config_tc - Configure TCs for given VEB
3941 * @veb: given VEB
3942 * @enabled_tc: TC bitmap
3943 *
3944 * Configures given TC bitmap for VEB (switching) element
3945 **/
3946int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3947{
3948 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3949 struct i40e_pf *pf = veb->pf;
3950 int ret = 0;
3951 int i;
3952
3953 /* No TCs or already enabled TCs just return */
3954 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3955 return ret;
3956
3957 bw_data.tc_valid_bits = enabled_tc;
3958 /* bw_data.absolute_credits is not set (relative) */
3959
3960 /* Enable ETS TCs with equal BW Share for now */
3961 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3962 if (enabled_tc & (1 << i))
3963 bw_data.tc_bw_share_credits[i] = 1;
3964 }
3965
3966 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3967 &bw_data, NULL);
3968 if (ret) {
3969 dev_info(&pf->pdev->dev,
3970 "veb bw config failed, aq_err=%d\n",
3971 pf->hw.aq.asq_last_status);
3972 goto out;
3973 }
3974
3975 /* Update the BW information */
3976 ret = i40e_veb_get_bw_info(veb);
3977 if (ret) {
3978 dev_info(&pf->pdev->dev,
3979 "Failed getting veb bw config, aq_err=%d\n",
3980 pf->hw.aq.asq_last_status);
3981 }
3982
3983out:
3984 return ret;
3985}
3986
3987#ifdef CONFIG_I40E_DCB
3988/**
3989 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
3990 * @pf: PF struct
3991 *
3992 * Reconfigure VEB/VSIs on a given PF; it is assumed that
3993 * the caller would've quiesce all the VSIs before calling
3994 * this function
3995 **/
3996static void i40e_dcb_reconfigure(struct i40e_pf *pf)
3997{
3998 u8 tc_map = 0;
3999 int ret;
4000 u8 v;
4001
4002 /* Enable the TCs available on PF to all VEBs */
4003 tc_map = i40e_pf_get_tc_map(pf);
4004 for (v = 0; v < I40E_MAX_VEB; v++) {
4005 if (!pf->veb[v])
4006 continue;
4007 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4008 if (ret) {
4009 dev_info(&pf->pdev->dev,
4010 "Failed configuring TC for VEB seid=%d\n",
4011 pf->veb[v]->seid);
4012 /* Will try to configure as many components */
4013 }
4014 }
4015
4016 /* Update each VSI */
4017 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4018 if (!pf->vsi[v])
4019 continue;
4020
4021 /* - Enable all TCs for the LAN VSI
4022 * - For all others keep them at TC0 for now
4023 */
4024 if (v == pf->lan_vsi)
4025 tc_map = i40e_pf_get_tc_map(pf);
4026 else
4027 tc_map = i40e_pf_get_default_tc(pf);
4028
4029 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4030 if (ret) {
4031 dev_info(&pf->pdev->dev,
4032 "Failed configuring TC for VSI seid=%d\n",
4033 pf->vsi[v]->seid);
4034 /* Will try to configure as many components */
4035 } else {
4036 if (pf->vsi[v]->netdev)
4037 i40e_dcbnl_set_all(pf->vsi[v]);
4038 }
4039 }
4040}
4041
4042/**
4043 * i40e_init_pf_dcb - Initialize DCB configuration
4044 * @pf: PF being configured
4045 *
4046 * Query the current DCB configuration and cache it
4047 * in the hardware structure
4048 **/
4049static int i40e_init_pf_dcb(struct i40e_pf *pf)
4050{
4051 struct i40e_hw *hw = &pf->hw;
4052 int err = 0;
4053
4054 if (pf->hw.func_caps.npar_enable)
4055 goto out;
4056
4057 /* Get the initial DCB configuration */
4058 err = i40e_init_dcb(hw);
4059 if (!err) {
4060 /* Device/Function is not DCBX capable */
4061 if ((!hw->func_caps.dcb) ||
4062 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4063 dev_info(&pf->pdev->dev,
4064 "DCBX offload is not supported or is disabled for this PF.\n");
4065
4066 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4067 goto out;
4068
4069 } else {
4070 /* When status is not DISABLED then DCBX in FW */
4071 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4072 DCB_CAP_DCBX_VER_IEEE;
4073 pf->flags |= I40E_FLAG_DCB_ENABLED;
4074 }
4075 }
4076
4077out:
4078 return err;
4079}
4080#endif /* CONFIG_I40E_DCB */
4081
41c445ff
JB		 4082/**
4083 * i40e_up_complete - Finish the last steps of bringing up a connection
4084 * @vsi: the VSI being configured
4085 **/
4086static int i40e_up_complete(struct i40e_vsi *vsi)
4087{
4088 struct i40e_pf *pf = vsi->back;
4089 int err;
4090
4091 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4092 i40e_vsi_configure_msix(vsi);
4093 else
4094 i40e_configure_msi_and_legacy(vsi);
4095
4096 /* start rings */
4097 err = i40e_vsi_control_rings(vsi, true);
4098 if (err)
4099 return err;
4100
4101 clear_bit(__I40E_DOWN, &vsi->state);
4102 i40e_napi_enable_all(vsi);
4103 i40e_vsi_enable_irq(vsi);
4104
4105 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4106 (vsi->netdev)) {
6d779b41 4107 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4108 netif_tx_start_all_queues(vsi->netdev);
4109 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4110 } else if (vsi->netdev) {
4111 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff 4112 }
ca64fa4e
ASJ		 4113
4114 /* replay FDIR SB filters */
4115 if (vsi->type == I40E_VSI_FDIR)
4116 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4117 i40e_service_event_schedule(pf);
4118
4119 return 0;
4120}
4121
4122/**
4123 * i40e_vsi_reinit_locked - Reset the VSI
4124 * @vsi: the VSI being configured
4125 *
4126 * Rebuild the ring structs after some configuration
4127 * has changed, e.g. MTU size.
4128 **/
4129static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4130{
4131 struct i40e_pf *pf = vsi->back;
4132
4133 WARN_ON(in_interrupt());
4134 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4135 usleep_range(1000, 2000);
4136 i40e_down(vsi);
4137
4138 /* Give a VF some time to respond to the reset. The
4139 * two second wait is based upon the watchdog cycle in
4140 * the VF driver.
4141 */
4142 if (vsi->type == I40E_VSI_SRIOV)
4143 msleep(2000);
4144 i40e_up(vsi);
4145 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4146}
4147
4148/**
4149 * i40e_up - Bring the connection back up after being down
4150 * @vsi: the VSI being configured
4151 **/
4152int i40e_up(struct i40e_vsi *vsi)
4153{
4154 int err;
4155
4156 err = i40e_vsi_configure(vsi);
4157 if (!err)
4158 err = i40e_up_complete(vsi);
4159
4160 return err;
4161}
4162
4163/**
4164 * i40e_down - Shutdown the connection processing
4165 * @vsi: the VSI being stopped
4166 **/
4167void i40e_down(struct i40e_vsi *vsi)
4168{
4169 int i;
4170
4171 /* It is assumed that the caller of this function
4172 * sets the vsi->state __I40E_DOWN bit.
4173 */
4174 if (vsi->netdev) {
4175 netif_carrier_off(vsi->netdev);
4176 netif_tx_disable(vsi->netdev);
4177 }
4178 i40e_vsi_disable_irq(vsi);
4179 i40e_vsi_control_rings(vsi, false);
4180 i40e_napi_disable_all(vsi);
4181
4182 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4183 i40e_clean_tx_ring(vsi->tx_rings[i]);
4184 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4185 }
4186}
4187
4188/**
4189 * i40e_setup_tc - configure multiple traffic classes
4190 * @netdev: net device to configure
4191 * @tc: number of traffic classes to enable
4192 **/
4193static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4194{
4195 struct i40e_netdev_priv *np = netdev_priv(netdev);
4196 struct i40e_vsi *vsi = np->vsi;
4197 struct i40e_pf *pf = vsi->back;
4198 u8 enabled_tc = 0;
4199 int ret = -EINVAL;
4200 int i;
4201
4202 /* Check if DCB enabled to continue */
4203 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4204 netdev_info(netdev, "DCB is not enabled for adapter\n");
4205 goto exit;
4206 }
4207
4208 /* Check if MFP enabled */
4209 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4210 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4211 goto exit;
4212 }
4213
4214 /* Check whether tc count is within enabled limit */
4215 if (tc > i40e_pf_get_num_tc(pf)) {
4216 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4217 goto exit;
4218 }
4219
4220 /* Generate TC map for number of tc requested */
4221 for (i = 0; i < tc; i++)
4222 enabled_tc |= (1 << i);
4223
4224 /* Requesting same TC configuration as already enabled */
4225 if (enabled_tc == vsi->tc_config.enabled_tc)
4226 return 0;
4227
4228 /* Quiesce VSI queues */
4229 i40e_quiesce_vsi(vsi);
4230
4231 /* Configure VSI for enabled TCs */
4232 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4233 if (ret) {
4234 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4235 vsi->seid);
4236 goto exit;
4237 }
4238
4239 /* Unquiesce VSI */
4240 i40e_unquiesce_vsi(vsi);
4241
4242exit:
4243 return ret;
4244}
4245
4246/**
4247 * i40e_open - Called when a network interface is made active
4248 * @netdev: network interface device structure
4249 *
4250 * The open entry point is called when a network interface is made
4251 * active by the system (IFF_UP). At this point all resources needed
4252 * for transmit and receive operations are allocated, the interrupt
4253 * handler is registered with the OS, the netdev watchdog subtask is
4254 * enabled, and the stack is notified that the interface is ready.
4255 *
4256 * Returns 0 on success, negative value on failure
4257 **/
4258static int i40e_open(struct net_device *netdev)
4259{
4260 struct i40e_netdev_priv *np = netdev_priv(netdev);
4261 struct i40e_vsi *vsi = np->vsi;
4262 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4263 int err;
4264
4eb3f768
SN		 4265 /* disallow open during test or if eeprom is broken */
4266 if (test_bit(__I40E_TESTING, &pf->state) ||
4267 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4268 return -EBUSY;
4269
4270 netif_carrier_off(netdev);
4271
6c167f58
EK		 4272 err = i40e_vsi_open(vsi);
4273 if (err)
4274 return err;
4275
4276#ifdef CONFIG_I40E_VXLAN
4277 vxlan_get_rx_port(netdev);
4278#endif
4279
4280 return 0;
4281}
4282
4283/**
4284 * i40e_vsi_open -
4285 * @vsi: the VSI to open
4286 *
4287 * Finish initialization of the VSI.
4288 *
4289 * Returns 0 on success, negative value on failure
4290 **/
4291int i40e_vsi_open(struct i40e_vsi *vsi)
4292{
4293 struct i40e_pf *pf = vsi->back;
4294 char int_name[IFNAMSIZ];
4295 int err;
4296
41c445ff
JB		 4297 /* allocate descriptors */
4298 err = i40e_vsi_setup_tx_resources(vsi);
4299 if (err)
4300 goto err_setup_tx;
4301 err = i40e_vsi_setup_rx_resources(vsi);
4302 if (err)
4303 goto err_setup_rx;
4304
4305 err = i40e_vsi_configure(vsi);
4306 if (err)
4307 goto err_setup_rx;
4308
6c167f58
EK		 4309 if (!vsi->netdev) {
4310 err = EINVAL;
4311 goto err_setup_rx;
4312 }
41c445ff 4313 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
6c167f58 4314 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
41c445ff
JB		 4315 err = i40e_vsi_request_irq(vsi, int_name);
4316 if (err)
4317 goto err_setup_rx;
4318
25946ddb 4319 /* Notify the stack of the actual queue counts. */
6c167f58 4320 err = netif_set_real_num_tx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4321 if (err)
4322 goto err_set_queues;
4323
6c167f58 4324 err = netif_set_real_num_rx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4325 if (err)
4326 goto err_set_queues;
4327
41c445ff
JB		 4328 err = i40e_up_complete(vsi);
4329 if (err)
4330 goto err_up_complete;
4331
41c445ff
JB		 4332 return 0;
4333
4334err_up_complete:
4335 i40e_down(vsi);
25946ddb 4336err_set_queues:
41c445ff
JB		 4337 i40e_vsi_free_irq(vsi);
4338err_setup_rx:
4339 i40e_vsi_free_rx_resources(vsi);
4340err_setup_tx:
4341 i40e_vsi_free_tx_resources(vsi);
4342 if (vsi == pf->vsi[pf->lan_vsi])
4343 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4344
4345 return err;
4346}
4347
17a73f6b
JG		 4348/**
4349 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4350 * @pf: Pointer to pf
4351 *
4352 * This function destroys the hlist where all the Flow Director
4353 * filters were saved.
4354 **/
4355static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4356{
4357 struct i40e_fdir_filter *filter;
4358 struct hlist_node *node2;
4359
4360 hlist_for_each_entry_safe(filter, node2,
4361 &pf->fdir_filter_list, fdir_node) {
4362 hlist_del(&filter->fdir_node);
4363 kfree(filter);
4364 }
4365 pf->fdir_pf_active_filters = 0;
4366}
4367
41c445ff
JB		 4368/**
4369 * i40e_close - Disables a network interface
4370 * @netdev: network interface device structure
4371 *
4372 * The close entry point is called when an interface is de-activated
4373 * by the OS. The hardware is still under the driver's control, but
4374 * this netdev interface is disabled.
4375 *
4376 * Returns 0, this is not allowed to fail
4377 **/
4378static int i40e_close(struct net_device *netdev)
4379{
4380 struct i40e_netdev_priv *np = netdev_priv(netdev);
4381 struct i40e_vsi *vsi = np->vsi;
4382
4383 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4384 return 0;
4385
4386 i40e_down(vsi);
4387 i40e_vsi_free_irq(vsi);
4388
4389 i40e_vsi_free_tx_resources(vsi);
4390 i40e_vsi_free_rx_resources(vsi);
4391
4392 return 0;
4393}
4394
4395/**
4396 * i40e_do_reset - Start a PF or Core Reset sequence
4397 * @pf: board private structure
4398 * @reset_flags: which reset is requested
4399 *
4400 * The essential difference in resets is that the PF Reset
4401 * doesn't clear the packet buffers, doesn't reset the PE
4402 * firmware, and doesn't bother the other PFs on the chip.
4403 **/
4404void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4405{
4406 u32 val;
4407
4408 WARN_ON(in_interrupt());
4409
4410 /* do the biggest reset indicated */
4411 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4412
4413 /* Request a Global Reset
4414 *
4415 * This will start the chip's countdown to the actual full
4416 * chip reset event, and a warning interrupt to be sent
4417 * to all PFs, including the requestor. Our handler
4418 * for the warning interrupt will deal with the shutdown
4419 * and recovery of the switch setup.
4420 */
69bfb110 4421 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4422 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4423 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4424 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4425
4426 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4427
4428 /* Request a Core Reset
4429 *
4430 * Same as Global Reset, except does *not* include the MAC/PHY
4431 */
69bfb110 4432 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4433 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4434 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4435 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4436 i40e_flush(&pf->hw);
4437
7823fe34
SN		 4438 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4439
4440 /* Request a Firmware Reset
4441 *
4442 * Same as Global reset, plus restarting the
4443 * embedded firmware engine.
4444 */
4445 /* enable EMP Reset */
4446 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4447 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4448 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4449
4450 /* force the reset */
4451 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4452 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4453 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4454 i40e_flush(&pf->hw);
4455
41c445ff
JB		 4456 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4457
4458 /* Request a PF Reset
4459 *
4460 * Resets only the PF-specific registers
4461 *
4462 * This goes directly to the tear-down and rebuild of
4463 * the switch, since we need to do all the recovery as
4464 * for the Core Reset.
4465 */
69bfb110 4466 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4467 i40e_handle_reset_warning(pf);
4468
4469 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4470 int v;
4471
4472 /* Find the VSI(s) that requested a re-init */
4473 dev_info(&pf->pdev->dev,
4474 "VSI reinit requested\n");
4475 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4476 struct i40e_vsi *vsi = pf->vsi[v];
4477 if (vsi != NULL &&
4478 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4479 i40e_vsi_reinit_locked(pf->vsi[v]);
4480 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4481 }
4482 }
4483
4484 /* no further action needed, so return now */
4485 return;
4486 } else {
4487 dev_info(&pf->pdev->dev,
4488 "bad reset request 0x%08x\n", reset_flags);
4489 return;
4490 }
4491}
4492
4e3b35b0
NP		 4493#ifdef CONFIG_I40E_DCB
4494/**
4495 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4496 * @pf: board private structure
4497 * @old_cfg: current DCB config
4498 * @new_cfg: new DCB config
4499 **/
4500bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4501 struct i40e_dcbx_config *old_cfg,
4502 struct i40e_dcbx_config *new_cfg)
4503{
4504 bool need_reconfig = false;
4505
4506 /* Check if ETS configuration has changed */
4507 if (memcmp(&new_cfg->etscfg,
4508 &old_cfg->etscfg,
4509 sizeof(new_cfg->etscfg))) {
4510 /* If Priority Table has changed reconfig is needed */
4511 if (memcmp(&new_cfg->etscfg.prioritytable,
4512 &old_cfg->etscfg.prioritytable,
4513 sizeof(new_cfg->etscfg.prioritytable))) {
4514 need_reconfig = true;
69bfb110 4515 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4516 }
4517
4518 if (memcmp(&new_cfg->etscfg.tcbwtable,
4519 &old_cfg->etscfg.tcbwtable,
4520 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4521 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4522
4523 if (memcmp(&new_cfg->etscfg.tsatable,
4524 &old_cfg->etscfg.tsatable,
4525 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4526 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4527 }
4528
4529 /* Check if PFC configuration has changed */
4530 if (memcmp(&new_cfg->pfc,
4531 &old_cfg->pfc,
4532 sizeof(new_cfg->pfc))) {
4533 need_reconfig = true;
69bfb110 4534 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4535 }
4536
4537 /* Check if APP Table has changed */
4538 if (memcmp(&new_cfg->app,
4539 &old_cfg->app,
3d9667a9 4540 sizeof(new_cfg->app))) {
4e3b35b0 4541 need_reconfig = true;
69bfb110 4542 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4543 }
4e3b35b0
NP		 4544
4545 return need_reconfig;
4546}
4547
4548/**
4549 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4550 * @pf: board private structure
4551 * @e: event info posted on ARQ
4552 **/
4553static int i40e_handle_lldp_event(struct i40e_pf *pf,
4554 struct i40e_arq_event_info *e)
4555{
4556 struct i40e_aqc_lldp_get_mib *mib =
4557 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4558 struct i40e_hw *hw = &pf->hw;
4559 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4560 struct i40e_dcbx_config tmp_dcbx_cfg;
4561 bool need_reconfig = false;
4562 int ret = 0;
4563 u8 type;
4564
4565 /* Ignore if event is not for Nearest Bridge */
4566 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4567 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4568 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4569 return ret;
4570
4571 /* Check MIB Type and return if event for Remote MIB update */
4572 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4573 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4574 /* Update the remote cached instance and return */
4575 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4576 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4577 &hw->remote_dcbx_config);
4578 goto exit;
4579 }
4580
4581 /* Convert/store the DCBX data from LLDPDU temporarily */
4582 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4583 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4584 if (ret) {
4585 /* Error in LLDPDU parsing return */
4586 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4587 goto exit;
4588 }
4589
4590 /* No change detected in DCBX configs */
4591 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4592 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4593 goto exit;
4594 }
4595
4596 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4597
4598 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4599
4600 /* Overwrite the new configuration */
4601 *dcbx_cfg = tmp_dcbx_cfg;
4602
4603 if (!need_reconfig)
4604 goto exit;
4605
4606 /* Reconfiguration needed quiesce all VSIs */
4607 i40e_pf_quiesce_all_vsi(pf);
4608
4609 /* Changes in configuration update VEB/VSI */
4610 i40e_dcb_reconfigure(pf);
4611
4612 i40e_pf_unquiesce_all_vsi(pf);
4613exit:
4614 return ret;
4615}
4616#endif /* CONFIG_I40E_DCB */
4617
23326186
ASJ		 4618/**
4619 * i40e_do_reset_safe - Protected reset path for userland calls.
4620 * @pf: board private structure
4621 * @reset_flags: which reset is requested
4622 *
4623 **/
4624void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4625{
4626 rtnl_lock();
4627 i40e_do_reset(pf, reset_flags);
4628 rtnl_unlock();
4629}
4630
41c445ff
JB		 4631/**
4632 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4633 * @pf: board private structure
4634 * @e: event info posted on ARQ
4635 *
4636 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4637 * and VF queues
4638 **/
4639static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4640 struct i40e_arq_event_info *e)
4641{
4642 struct i40e_aqc_lan_overflow *data =
4643 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4644 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4645 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4646 struct i40e_hw *hw = &pf->hw;
4647 struct i40e_vf *vf;
4648 u16 vf_id;
4649
69bfb110
JB		 4650 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4651 queue, qtx_ctl);
41c445ff
JB		 4652
4653 /* Queue belongs to VF, find the VF and issue VF reset */
4654 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4655 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4656 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4657 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4658 vf_id -= hw->func_caps.vf_base_id;
4659 vf = &pf->vf[vf_id];
4660 i40e_vc_notify_vf_reset(vf);
4661 /* Allow VF to process pending reset notification */
4662 msleep(20);
4663 i40e_reset_vf(vf, false);
4664 }
4665}
4666
4667/**
4668 * i40e_service_event_complete - Finish up the service event
4669 * @pf: board private structure
4670 **/
4671static void i40e_service_event_complete(struct i40e_pf *pf)
4672{
4673 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4674
4675 /* flush memory to make sure state is correct before next watchog */
4676 smp_mb__before_clear_bit();
4677 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4678}
4679
55a5e60b
ASJ		 4680/**
4681 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4682 * @pf: board private structure
4683 **/
4684int i40e_get_current_fd_count(struct i40e_pf *pf)
4685{
4686 int val, fcnt_prog;
4687 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4688 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4689 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4690 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4691 return fcnt_prog;
4692}
4693
4694/**
4695 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4696 * @pf: board private structure
4697 **/
4698void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4699{
4700 u32 fcnt_prog, fcnt_avail;
4701
4702 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4703 * to re-enable
4704 */
4705 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4706 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4707 return;
4708 fcnt_prog = i40e_get_current_fd_count(pf);
4709 fcnt_avail = pf->hw.fdir_shared_filter_count +
4710 pf->fdir_pf_filter_count;
4711 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4712 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4713 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4714 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4715 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4716 }
4717 }
4718 /* Wait for some more space to be available to turn on ATR */
4719 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4720 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4721 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4722 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4723 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4724 }
4725 }
4726}
4727
41c445ff
JB		 4728/**
4729 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4730 * @pf: board private structure
4731 **/
4732static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4733{
4734 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4735 return;
4736
41c445ff
JB		 4737 /* if interface is down do nothing */
4738 if (test_bit(__I40E_DOWN, &pf->state))
4739 return;
55a5e60b
ASJ		 4740 i40e_fdir_check_and_reenable(pf);
4741
4742 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4743 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4744 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4745}
4746
4747/**
4748 * i40e_vsi_link_event - notify VSI of a link event
4749 * @vsi: vsi to be notified
4750 * @link_up: link up or down
4751 **/
4752static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4753{
4754 if (!vsi)
4755 return;
4756
4757 switch (vsi->type) {
4758 case I40E_VSI_MAIN:
4759 if (!vsi->netdev || !vsi->netdev_registered)
4760 break;
4761
4762 if (link_up) {
4763 netif_carrier_on(vsi->netdev);
4764 netif_tx_wake_all_queues(vsi->netdev);
4765 } else {
4766 netif_carrier_off(vsi->netdev);
4767 netif_tx_stop_all_queues(vsi->netdev);
4768 }
4769 break;
4770
4771 case I40E_VSI_SRIOV:
4772 break;
4773
4774 case I40E_VSI_VMDQ2:
4775 case I40E_VSI_CTRL:
4776 case I40E_VSI_MIRROR:
4777 default:
4778 /* there is no notification for other VSIs */
4779 break;
4780 }
4781}
4782
4783/**
4784 * i40e_veb_link_event - notify elements on the veb of a link event
4785 * @veb: veb to be notified
4786 * @link_up: link up or down
4787 **/
4788static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4789{
4790 struct i40e_pf *pf;
4791 int i;
4792
4793 if (!veb || !veb->pf)
4794 return;
4795 pf = veb->pf;
4796
4797 /* depth first... */
4798 for (i = 0; i < I40E_MAX_VEB; i++)
4799 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4800 i40e_veb_link_event(pf->veb[i], link_up);
4801
4802 /* ... now the local VSIs */
4803 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4804 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4805 i40e_vsi_link_event(pf->vsi[i], link_up);
4806}
4807
4808/**
4809 * i40e_link_event - Update netif_carrier status
4810 * @pf: board private structure
4811 **/
4812static void i40e_link_event(struct i40e_pf *pf)
4813{
4814 bool new_link, old_link;
4815
4816 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4817 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4818
4819 if (new_link == old_link)
4820 return;
4821
6d779b41
AS		 4822 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4823 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4824 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4825
4826 /* Notify the base of the switch tree connected to
4827 * the link. Floating VEBs are not notified.
4828 */
4829 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4830 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4831 else
4832 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4833
4834 if (pf->vf)
4835 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4836
4837 if (pf->flags & I40E_FLAG_PTP)
4838 i40e_ptp_set_increment(pf);
41c445ff
JB		 4839}
4840
4841/**
4842 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4843 * @pf: board private structure
4844 *
4845 * Set the per-queue flags to request a check for stuck queues in the irq
4846 * clean functions, then force interrupts to be sure the irq clean is called.
4847 **/
4848static void i40e_check_hang_subtask(struct i40e_pf *pf)
4849{
4850 int i, v;
4851
4852 /* If we're down or resetting, just bail */
4853 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4854 return;
4855
4856 /* for each VSI/netdev
4857 * for each Tx queue
4858 * set the check flag
4859 * for each q_vector
4860 * force an interrupt
4861 */
4862 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4863 struct i40e_vsi *vsi = pf->vsi[v];
4864 int armed = 0;
4865
4866 if (!pf->vsi[v] ||
4867 test_bit(__I40E_DOWN, &vsi->state) ||
4868 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4869 continue;
4870
4871 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4872 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4873 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4874 &vsi->tx_rings[i]->state))
41c445ff
JB		 4875 armed++;
4876 }
4877
4878 if (armed) {
4879 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4880 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4881 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4882 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4883 } else {
4884 u16 vec = vsi->base_vector - 1;
4885 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4886 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4887 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4888 wr32(&vsi->back->hw,
4889 I40E_PFINT_DYN_CTLN(vec), val);
4890 }
4891 i40e_flush(&vsi->back->hw);
4892 }
4893 }
4894}
4895
4896/**
4897 * i40e_watchdog_subtask - Check and bring link up
4898 * @pf: board private structure
4899 **/
4900static void i40e_watchdog_subtask(struct i40e_pf *pf)
4901{
4902 int i;
4903
4904 /* if interface is down do nothing */
4905 if (test_bit(__I40E_DOWN, &pf->state) ||
4906 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4907 return;
4908
4909 /* Update the stats for active netdevs so the network stack
4910 * can look at updated numbers whenever it cares to
4911 */
4912 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4913 if (pf->vsi[i] && pf->vsi[i]->netdev)
4914 i40e_update_stats(pf->vsi[i]);
4915
4916 /* Update the stats for the active switching components */
4917 for (i = 0; i < I40E_MAX_VEB; i++)
4918 if (pf->veb[i])
4919 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4920
4921 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4922}
4923
4924/**
4925 * i40e_reset_subtask - Set up for resetting the device and driver
4926 * @pf: board private structure
4927 **/
4928static void i40e_reset_subtask(struct i40e_pf *pf)
4929{
4930 u32 reset_flags = 0;
4931
23326186 4932 rtnl_lock();
41c445ff
JB		 4933 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4934 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4935 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4936 }
4937 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4938 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4939 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4940 }
4941 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4942 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4943 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4944 }
4945 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4946 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4947 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4948 }
4949
4950 /* If there's a recovery already waiting, it takes
4951 * precedence before starting a new reset sequence.
4952 */
4953 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4954 i40e_handle_reset_warning(pf);
23326186 4955 goto unlock;
41c445ff
JB		 4956 }
4957
4958 /* If we're already down or resetting, just bail */
4959 if (reset_flags &&
4960 !test_bit(__I40E_DOWN, &pf->state) &&
4961 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4962 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4963
4964unlock:
4965 rtnl_unlock();
41c445ff
JB		 4966}
4967
4968/**
4969 * i40e_handle_link_event - Handle link event
4970 * @pf: board private structure
4971 * @e: event info posted on ARQ
4972 **/
4973static void i40e_handle_link_event(struct i40e_pf *pf,
4974 struct i40e_arq_event_info *e)
4975{
4976 struct i40e_hw *hw = &pf->hw;
4977 struct i40e_aqc_get_link_status *status =
4978 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4979 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4980
4981 /* save off old link status information */
4982 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4983 sizeof(pf->hw.phy.link_info_old));
4984
4985 /* update link status */
4986 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4987 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4988 hw_link_info->link_info = status->link_info;
4989 hw_link_info->an_info = status->an_info;
4990 hw_link_info->ext_info = status->ext_info;
4991 hw_link_info->lse_enable =
4992 le16_to_cpu(status->command_flags) &
4993 I40E_AQ_LSE_ENABLE;
4994
4995 /* process the event */
4996 i40e_link_event(pf);
4997
4998 /* Do a new status request to re-enable LSE reporting
4999 * and load new status information into the hw struct,
5000 * then see if the status changed while processing the
5001 * initial event.
5002 */
5003 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5004 i40e_link_event(pf);
5005}
5006
5007/**
5008 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5009 * @pf: board private structure
5010 **/
5011static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5012{
5013 struct i40e_arq_event_info event;
5014 struct i40e_hw *hw = &pf->hw;
5015 u16 pending, i = 0;
5016 i40e_status ret;
5017 u16 opcode;
5018 u32 val;
5019
5020 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5021 return;
5022
3197ce22 5023 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5024 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5025 if (!event.msg_buf)
5026 return;
5027
5028 do {
2f019123 5029 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5030 ret = i40e_clean_arq_element(hw, &event, &pending);
5031 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5032 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5033 break;
5034 } else if (ret) {
5035 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5036 break;
5037 }
5038
5039 opcode = le16_to_cpu(event.desc.opcode);
5040 switch (opcode) {
5041
5042 case i40e_aqc_opc_get_link_status:
5043 i40e_handle_link_event(pf, &event);
5044 break;
5045 case i40e_aqc_opc_send_msg_to_pf:
5046 ret = i40e_vc_process_vf_msg(pf,
5047 le16_to_cpu(event.desc.retval),
5048 le32_to_cpu(event.desc.cookie_high),
5049 le32_to_cpu(event.desc.cookie_low),
5050 event.msg_buf,
5051 event.msg_size);
5052 break;
5053 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5054 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5055#ifdef CONFIG_I40E_DCB
5056 rtnl_lock();
5057 ret = i40e_handle_lldp_event(pf, &event);
5058 rtnl_unlock();
5059#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5060 break;
5061 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5062 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5063 i40e_handle_lan_overflow_event(pf, &event);
5064 break;
0467bc91
SN		 5065 case i40e_aqc_opc_send_msg_to_peer:
5066 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5067 break;
41c445ff
JB		 5068 default:
5069 dev_info(&pf->pdev->dev,
0467bc91
SN		 5070 "ARQ Error: Unknown event 0x%04x received\n",
5071 opcode);
41c445ff
JB		 5072 break;
5073 }
5074 } while (pending && (i++ < pf->adminq_work_limit));
5075
5076 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5077 /* re-enable Admin queue interrupt cause */
5078 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5079 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5080 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5081 i40e_flush(hw);
5082
5083 kfree(event.msg_buf);
5084}
5085
4eb3f768
SN		 5086/**
5087 * i40e_verify_eeprom - make sure eeprom is good to use
5088 * @pf: board private structure
5089 **/
5090static void i40e_verify_eeprom(struct i40e_pf *pf)
5091{
5092 int err;
5093
5094 err = i40e_diag_eeprom_test(&pf->hw);
5095 if (err) {
5096 /* retry in case of garbage read */
5097 err = i40e_diag_eeprom_test(&pf->hw);
5098 if (err) {
5099 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5100 err);
5101 set_bit(__I40E_BAD_EEPROM, &pf->state);
5102 }
5103 }
5104
5105 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5106 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5107 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5108 }
5109}
5110
41c445ff
JB		 5111/**
5112 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5113 * @veb: pointer to the VEB instance
5114 *
5115 * This is a recursive function that first builds the attached VSIs then
5116 * recurses in to build the next layer of VEB. We track the connections
5117 * through our own index numbers because the seid's from the HW could
5118 * change across the reset.
5119 **/
5120static int i40e_reconstitute_veb(struct i40e_veb *veb)
5121{
5122 struct i40e_vsi *ctl_vsi = NULL;
5123 struct i40e_pf *pf = veb->pf;
5124 int v, veb_idx;
5125 int ret;
5126
5127 /* build VSI that owns this VEB, temporarily attached to base VEB */
5128 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5129 if (pf->vsi[v] &&
5130 pf->vsi[v]->veb_idx == veb->idx &&
5131 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5132 ctl_vsi = pf->vsi[v];
5133 break;
5134 }
5135 }
5136 if (!ctl_vsi) {
5137 dev_info(&pf->pdev->dev,
5138 "missing owner VSI for veb_idx %d\n", veb->idx);
5139 ret = -ENOENT;
5140 goto end_reconstitute;
5141 }
5142 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5143 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5144 ret = i40e_add_vsi(ctl_vsi);
5145 if (ret) {
5146 dev_info(&pf->pdev->dev,
5147 "rebuild of owner VSI failed: %d\n", ret);
5148 goto end_reconstitute;
5149 }
5150 i40e_vsi_reset_stats(ctl_vsi);
5151
5152 /* create the VEB in the switch and move the VSI onto the VEB */
5153 ret = i40e_add_veb(veb, ctl_vsi);
5154 if (ret)
5155 goto end_reconstitute;
5156
5157 /* create the remaining VSIs attached to this VEB */
5158 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5159 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5160 continue;
5161
5162 if (pf->vsi[v]->veb_idx == veb->idx) {
5163 struct i40e_vsi *vsi = pf->vsi[v];
5164 vsi->uplink_seid = veb->seid;
5165 ret = i40e_add_vsi(vsi);
5166 if (ret) {
5167 dev_info(&pf->pdev->dev,
5168 "rebuild of vsi_idx %d failed: %d\n",
5169 v, ret);
5170 goto end_reconstitute;
5171 }
5172 i40e_vsi_reset_stats(vsi);
5173 }
5174 }
5175
5176 /* create any VEBs attached to this VEB - RECURSION */
5177 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5178 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5179 pf->veb[veb_idx]->uplink_seid = veb->seid;
5180 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5181 if (ret)
5182 break;
5183 }
5184 }
5185
5186end_reconstitute:
5187 return ret;
5188}
5189
5190/**
5191 * i40e_get_capabilities - get info about the HW
5192 * @pf: the PF struct
5193 **/
5194static int i40e_get_capabilities(struct i40e_pf *pf)
5195{
5196 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5197 u16 data_size;
5198 int buf_len;
5199 int err;
5200
5201 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5202 do {
5203 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5204 if (!cap_buf)
5205 return -ENOMEM;
5206
5207 /* this loads the data into the hw struct for us */
5208 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5209 &data_size,
5210 i40e_aqc_opc_list_func_capabilities,
5211 NULL);
5212 /* data loaded, buffer no longer needed */
5213 kfree(cap_buf);
5214
5215 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5216 /* retry with a larger buffer */
5217 buf_len = data_size;
5218 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5219 dev_info(&pf->pdev->dev,
5220 "capability discovery failed: aq=%d\n",
5221 pf->hw.aq.asq_last_status);
5222 return -ENODEV;
5223 }
5224 } while (err);
5225
ac71b7ba
ASJ		 5226 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5227 (pf->hw.aq.fw_maj_ver < 2)) {
5228 pf->hw.func_caps.num_msix_vectors++;
5229 pf->hw.func_caps.num_msix_vectors_vf++;
5230 }
5231
41c445ff
JB		 5232 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5233 dev_info(&pf->pdev->dev,
5234 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5235 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5236 pf->hw.func_caps.num_msix_vectors,
5237 pf->hw.func_caps.num_msix_vectors_vf,
5238 pf->hw.func_caps.fd_filters_guaranteed,
5239 pf->hw.func_caps.fd_filters_best_effort,
5240 pf->hw.func_caps.num_tx_qp,
5241 pf->hw.func_caps.num_vsis);
5242
7134f9ce
JB		 5243#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5244 + pf->hw.func_caps.num_vfs)
5245 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5246 dev_info(&pf->pdev->dev,
5247 "got num_vsis %d, setting num_vsis to %d\n",
5248 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5249 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5250 }
5251
41c445ff
JB		 5252 return 0;
5253}
5254
cbf61325
ASJ		 5255static int i40e_vsi_clear(struct i40e_vsi *vsi);
5256
41c445ff 5257/**
cbf61325 5258 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5259 * @pf: board private structure
5260 **/
cbf61325 5261static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5262{
5263 struct i40e_vsi *vsi;
5264 bool new_vsi = false;
5265 int err, i;
5266
cbf61325 5267 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5268 return;
5269
cbf61325 5270 /* find existing VSI and see if it needs configuring */
41c445ff 5271 vsi = NULL;
cbf61325
ASJ		 5272 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5273 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5274 vsi = pf->vsi[i];
cbf61325
ASJ		 5275 break;
5276 }
5277 }
5278
5279 /* create a new VSI if none exists */
41c445ff 5280 if (!vsi) {
cbf61325
ASJ		 5281 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5282 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5283 if (!vsi) {
5284 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
cbf61325 5285 goto err_vsi;
41c445ff
JB		 5286 }
5287 new_vsi = true;
5288 }
cbf61325 5289 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5290
5291 err = i40e_vsi_setup_tx_resources(vsi);
cbf61325
ASJ		 5292 if (err)
5293 goto err_setup_tx;
5294 err = i40e_vsi_setup_rx_resources(vsi);
5295 if (err)
5296 goto err_setup_rx;
5297
5298 if (new_vsi) {
41c445ff 5299 char int_name[IFNAMSIZ + 9];
cbf61325
ASJ		 5300 err = i40e_vsi_configure(vsi);
5301 if (err)
5302 goto err_setup_rx;
41c445ff
JB		 5303 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
5304 dev_driver_string(&pf->pdev->dev));
5305 err = i40e_vsi_request_irq(vsi, int_name);
cbf61325
ASJ		 5306 if (err)
5307 goto err_setup_rx;
41c445ff 5308 err = i40e_up_complete(vsi);
cbf61325
ASJ		 5309 if (err)
5310 goto err_up_complete;
17a73f6b 5311 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
cbf61325 5312 }
41c445ff 5313
cbf61325
ASJ		 5314 return;
5315
5316err_up_complete:
5317 i40e_down(vsi);
5318 i40e_vsi_free_irq(vsi);
5319err_setup_rx:
5320 i40e_vsi_free_rx_resources(vsi);
5321err_setup_tx:
5322 i40e_vsi_free_tx_resources(vsi);
5323err_vsi:
5324 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5325 i40e_vsi_clear(vsi);
41c445ff
JB		 5326}
5327
5328/**
5329 * i40e_fdir_teardown - release the Flow Director resources
5330 * @pf: board private structure
5331 **/
5332static void i40e_fdir_teardown(struct i40e_pf *pf)
5333{
5334 int i;
5335
17a73f6b 5336 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5337 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5338 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5339 i40e_vsi_release(pf->vsi[i]);
5340 break;
5341 }
5342 }
5343}
5344
5345/**
f650a38b 5346 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5347 * @pf: board private structure
5348 *
f650a38b
ASJ		 5349 * Close up the VFs and other things in prep for pf Reset.
5350 **/
5351static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5352{
41c445ff
JB		 5353 struct i40e_hw *hw = &pf->hw;
5354 i40e_status ret;
5355 u32 v;
5356
5357 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5358 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5359 return 0;
41c445ff 5360
69bfb110 5361 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5362
37f0be6d
ASJ		 5363 if (i40e_check_asq_alive(hw))
5364 i40e_vc_notify_reset(pf);
41c445ff
JB		 5365
5366 /* quiesce the VSIs and their queues that are not already DOWN */
5367 i40e_pf_quiesce_all_vsi(pf);
5368
5369 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5370 if (pf->vsi[v])
5371 pf->vsi[v]->seid = 0;
5372 }
5373
5374 i40e_shutdown_adminq(&pf->hw);
5375
f650a38b
ASJ		 5376 /* call shutdown HMC */
5377 ret = i40e_shutdown_lan_hmc(hw);
5378 if (ret) {
5379 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5380 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5381 }
5382 return ret;
5383}
5384
5385/**
4dda12e6 5386 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5387 * @pf: board private structure
bc7d338f 5388 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5389 **/
bc7d338f 5390static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 5391{
5392 struct i40e_driver_version dv;
5393 struct i40e_hw *hw = &pf->hw;
5394 i40e_status ret;
5395 u32 v;
5396
41c445ff
JB		 5397 /* Now we wait for GRST to settle out.
5398 * We don't have to delete the VEBs or VSIs from the hw switch
5399 * because the reset will make them disappear.
5400 */
5401 ret = i40e_pf_reset(hw);
5402 if (ret)
5403 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
5404 pf->pfr_count++;
5405
5406 if (test_bit(__I40E_DOWN, &pf->state))
5407 goto end_core_reset;
69bfb110 5408 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5409
5410 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5411 ret = i40e_init_adminq(&pf->hw);
5412 if (ret) {
5413 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5414 goto end_core_reset;
5415 }
5416
4eb3f768
SN		 5417 /* re-verify the eeprom if we just had an EMP reset */
5418 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5419 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5420 i40e_verify_eeprom(pf);
5421 }
5422
41c445ff
JB		 5423 ret = i40e_get_capabilities(pf);
5424 if (ret) {
5425 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5426 ret);
5427 goto end_core_reset;
5428 }
5429
41c445ff
JB		 5430 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5431 hw->func_caps.num_rx_qp,
5432 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5433 if (ret) {
5434 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5435 goto end_core_reset;
5436 }
5437 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5438 if (ret) {
5439 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5440 goto end_core_reset;
5441 }
5442
4e3b35b0
NP		 5443#ifdef CONFIG_I40E_DCB
5444 ret = i40e_init_pf_dcb(pf);
5445 if (ret) {
5446 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5447 goto end_core_reset;
5448 }
5449#endif /* CONFIG_I40E_DCB */
5450
41c445ff 5451 /* do basic switch setup */
bc7d338f 5452 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5453 if (ret)
5454 goto end_core_reset;
5455
5456 /* Rebuild the VSIs and VEBs that existed before reset.
5457 * They are still in our local switch element arrays, so only
5458 * need to rebuild the switch model in the HW.
5459 *
5460 * If there were VEBs but the reconstitution failed, we'll try
5461 * try to recover minimal use by getting the basic PF VSI working.
5462 */
5463 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5464 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5465 /* find the one VEB connected to the MAC, and find orphans */
5466 for (v = 0; v < I40E_MAX_VEB; v++) {
5467 if (!pf->veb[v])
5468 continue;
5469
5470 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5471 pf->veb[v]->uplink_seid == 0) {
5472 ret = i40e_reconstitute_veb(pf->veb[v]);
5473
5474 if (!ret)
5475 continue;
5476
5477 /* If Main VEB failed, we're in deep doodoo,
5478 * so give up rebuilding the switch and set up
5479 * for minimal rebuild of PF VSI.
5480 * If orphan failed, we'll report the error
5481 * but try to keep going.
5482 */
5483 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5484 dev_info(&pf->pdev->dev,
5485 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5486 ret);
5487 pf->vsi[pf->lan_vsi]->uplink_seid
5488 = pf->mac_seid;
5489 break;
5490 } else if (pf->veb[v]->uplink_seid == 0) {
5491 dev_info(&pf->pdev->dev,
5492 "rebuild of orphan VEB failed: %d\n",
5493 ret);
5494 }
5495 }
5496 }
5497 }
5498
5499 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5500 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5501 /* no VEB, so rebuild only the Main VSI */
5502 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5503 if (ret) {
5504 dev_info(&pf->pdev->dev,
5505 "rebuild of Main VSI failed: %d\n", ret);
5506 goto end_core_reset;
5507 }
5508 }
5509
5510 /* reinit the misc interrupt */
5511 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5512 ret = i40e_setup_misc_vector(pf);
5513
5514 /* restart the VSIs that were rebuilt and running before the reset */
5515 i40e_pf_unquiesce_all_vsi(pf);
5516
69f64b2b
MW		 5517 if (pf->num_alloc_vfs) {
5518 for (v = 0; v < pf->num_alloc_vfs; v++)
5519 i40e_reset_vf(&pf->vf[v], true);
5520 }
5521
41c445ff
JB		 5522 /* tell the firmware that we're starting */
5523 dv.major_version = DRV_VERSION_MAJOR;
5524 dv.minor_version = DRV_VERSION_MINOR;
5525 dv.build_version = DRV_VERSION_BUILD;
5526 dv.subbuild_version = 0;
5527 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5528
69bfb110 5529 dev_info(&pf->pdev->dev, "reset complete\n");
41c445ff
JB		 5530
5531end_core_reset:
5532 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5533}
5534
f650a38b
ASJ		 5535/**
5536 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5537 * @pf: board private structure
5538 *
5539 * Close up the VFs and other things in prep for a Core Reset,
5540 * then get ready to rebuild the world.
5541 **/
5542static void i40e_handle_reset_warning(struct i40e_pf *pf)
5543{
5544 i40e_status ret;
5545
5546 ret = i40e_prep_for_reset(pf);
5547 if (!ret)
bc7d338f 5548 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5549}
5550
41c445ff
JB		 5551/**
5552 * i40e_handle_mdd_event
5553 * @pf: pointer to the pf structure
5554 *
5555 * Called from the MDD irq handler to identify possibly malicious vfs
5556 **/
5557static void i40e_handle_mdd_event(struct i40e_pf *pf)
5558{
5559 struct i40e_hw *hw = &pf->hw;
5560 bool mdd_detected = false;
5561 struct i40e_vf *vf;
5562 u32 reg;
5563 int i;
5564
5565 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5566 return;
5567
5568 /* find what triggered the MDD event */
5569 reg = rd32(hw, I40E_GL_MDET_TX);
5570 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5571 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5572 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5573 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5574 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5575 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5576 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5577 dev_info(&pf->pdev->dev,
f29eaa3d 5578 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5579 event, queue, func);
5580 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5581 mdd_detected = true;
5582 }
5583 reg = rd32(hw, I40E_GL_MDET_RX);
5584 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5585 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5586 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5587 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5588 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5589 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5590 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5591 dev_info(&pf->pdev->dev,
f29eaa3d 5592 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5593 event, queue, func);
5594 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5595 mdd_detected = true;
5596 }
5597
5598 /* see if one of the VFs needs its hand slapped */
5599 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5600 vf = &(pf->vf[i]);
5601 reg = rd32(hw, I40E_VP_MDET_TX(i));
5602 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5603 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5604 vf->num_mdd_events++;
5605 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5606 }
5607
5608 reg = rd32(hw, I40E_VP_MDET_RX(i));
5609 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5610 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5611 vf->num_mdd_events++;
5612 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5613 }
5614
5615 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5616 dev_info(&pf->pdev->dev,
5617 "Too many MDD events on VF %d, disabled\n", i);
5618 dev_info(&pf->pdev->dev,
5619 "Use PF Control I/F to re-enable the VF\n");
5620 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5621 }
5622 }
5623
5624 /* re-enable mdd interrupt cause */
5625 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5626 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5627 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5628 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5629 i40e_flush(hw);
5630}
5631
a1c9a9d9
JK		 5632#ifdef CONFIG_I40E_VXLAN
5633/**
5634 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5635 * @pf: board private structure
5636 **/
5637static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5638{
5639 const int vxlan_hdr_qwords = 4;
5640 struct i40e_hw *hw = &pf->hw;
5641 i40e_status ret;
5642 u8 filter_index;
5643 __be16 port;
5644 int i;
5645
5646 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5647 return;
5648
5649 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5650
5651 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5652 if (pf->pending_vxlan_bitmap & (1 << i)) {
5653 pf->pending_vxlan_bitmap &= ~(1 << i);
5654 port = pf->vxlan_ports[i];
5655 ret = port ?
5656 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5657 vxlan_hdr_qwords,
5658 I40E_AQC_TUNNEL_TYPE_VXLAN,
5659 &filter_index, NULL)
5660 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5661
5662 if (ret) {
5663 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5664 port ? "adding" : "deleting",
5665 ntohs(port), port ? i : i);
5666
5667 pf->vxlan_ports[i] = 0;
5668 } else {
5669 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5670 port ? "Added" : "Deleted",
5671 ntohs(port), port ? i : filter_index);
5672 }
5673 }
5674 }
5675}
5676
5677#endif
41c445ff
JB		 5678/**
5679 * i40e_service_task - Run the driver's async subtasks
5680 * @work: pointer to work_struct containing our data
5681 **/
5682static void i40e_service_task(struct work_struct *work)
5683{
5684 struct i40e_pf *pf = container_of(work,
5685 struct i40e_pf,
5686 service_task);
5687 unsigned long start_time = jiffies;
5688
5689 i40e_reset_subtask(pf);
5690 i40e_handle_mdd_event(pf);
5691 i40e_vc_process_vflr_event(pf);
5692 i40e_watchdog_subtask(pf);
5693 i40e_fdir_reinit_subtask(pf);
5694 i40e_check_hang_subtask(pf);
5695 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5696#ifdef CONFIG_I40E_VXLAN
5697 i40e_sync_vxlan_filters_subtask(pf);
5698#endif
41c445ff
JB		 5699 i40e_clean_adminq_subtask(pf);
5700
5701 i40e_service_event_complete(pf);
5702
5703 /* If the tasks have taken longer than one timer cycle or there
5704 * is more work to be done, reschedule the service task now
5705 * rather than wait for the timer to tick again.
5706 */
5707 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5708 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5709 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5710 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5711 i40e_service_event_schedule(pf);
5712}
5713
5714/**
5715 * i40e_service_timer - timer callback
5716 * @data: pointer to PF struct
5717 **/
5718static void i40e_service_timer(unsigned long data)
5719{
5720 struct i40e_pf *pf = (struct i40e_pf *)data;
5721
5722 mod_timer(&pf->service_timer,
5723 round_jiffies(jiffies + pf->service_timer_period));
5724 i40e_service_event_schedule(pf);
5725}
5726
5727/**
5728 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5729 * @vsi: the VSI being configured
5730 **/
5731static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5732{
5733 struct i40e_pf *pf = vsi->back;
5734
5735 switch (vsi->type) {
5736 case I40E_VSI_MAIN:
5737 vsi->alloc_queue_pairs = pf->num_lan_qps;
5738 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5739 I40E_REQ_DESCRIPTOR_MULTIPLE);
5740 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5741 vsi->num_q_vectors = pf->num_lan_msix;
5742 else
5743 vsi->num_q_vectors = 1;
5744
5745 break;
5746
5747 case I40E_VSI_FDIR:
5748 vsi->alloc_queue_pairs = 1;
5749 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5750 I40E_REQ_DESCRIPTOR_MULTIPLE);
5751 vsi->num_q_vectors = 1;
5752 break;
5753
5754 case I40E_VSI_VMDQ2:
5755 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5756 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5757 I40E_REQ_DESCRIPTOR_MULTIPLE);
5758 vsi->num_q_vectors = pf->num_vmdq_msix;
5759 break;
5760
5761 case I40E_VSI_SRIOV:
5762 vsi->alloc_queue_pairs = pf->num_vf_qps;
5763 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5764 I40E_REQ_DESCRIPTOR_MULTIPLE);
5765 break;
5766
5767 default:
5768 WARN_ON(1);
5769 return -ENODATA;
5770 }
5771
5772 return 0;
5773}
5774
f650a38b
ASJ		 5775/**
5776 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5777 * @type: VSI pointer
bc7d338f 5778 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5779 *
5780 * On error: returns error code (negative)
5781 * On success: returns 0
5782 **/
bc7d338f 5783static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5784{
5785 int size;
5786 int ret = 0;
5787
ac6c5e3d 5788 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5789 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5790 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5791 if (!vsi->tx_rings)
5792 return -ENOMEM;
f650a38b
ASJ		 5793 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5794
bc7d338f
ASJ		 5795 if (alloc_qvectors) {
5796 /* allocate memory for q_vector pointers */
5797 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5798 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5799 if (!vsi->q_vectors) {
5800 ret = -ENOMEM;
5801 goto err_vectors;
5802 }
f650a38b
ASJ		 5803 }
5804 return ret;
5805
5806err_vectors:
5807 kfree(vsi->tx_rings);
5808 return ret;
5809}
5810
41c445ff
JB		 5811/**
5812 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5813 * @pf: board private structure
5814 * @type: type of VSI
5815 *
5816 * On error: returns error code (negative)
5817 * On success: returns vsi index in PF (positive)
5818 **/
5819static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5820{
5821 int ret = -ENODEV;
5822 struct i40e_vsi *vsi;
5823 int vsi_idx;
5824 int i;
5825
5826 /* Need to protect the allocation of the VSIs at the PF level */
5827 mutex_lock(&pf->switch_mutex);
5828
5829 /* VSI list may be fragmented if VSI creation/destruction has
5830 * been happening. We can afford to do a quick scan to look
5831 * for any free VSIs in the list.
5832 *
5833 * find next empty vsi slot, looping back around if necessary
5834 */
5835 i = pf->next_vsi;
5836 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5837 i++;
5838 if (i >= pf->hw.func_caps.num_vsis) {
5839 i = 0;
5840 while (i < pf->next_vsi && pf->vsi[i])
5841 i++;
5842 }
5843
5844 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5845 vsi_idx = i; /* Found one! */
5846 } else {
5847 ret = -ENODEV;
493fb300 5848 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5849 }
5850 pf->next_vsi = ++i;
5851
5852 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5853 if (!vsi) {
5854 ret = -ENOMEM;
493fb300 5855 goto unlock_pf;
41c445ff
JB		 5856 }
5857 vsi->type = type;
5858 vsi->back = pf;
5859 set_bit(__I40E_DOWN, &vsi->state);
5860 vsi->flags = 0;
5861 vsi->idx = vsi_idx;
5862 vsi->rx_itr_setting = pf->rx_itr_default;
5863 vsi->tx_itr_setting = pf->tx_itr_default;
5864 vsi->netdev_registered = false;
5865 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5866 INIT_LIST_HEAD(&vsi->mac_filter_list);
5867
9f65e15b
AD		 5868 ret = i40e_set_num_rings_in_vsi(vsi);
5869 if (ret)
5870 goto err_rings;
5871
bc7d338f 5872 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5873 if (ret)
9f65e15b 5874 goto err_rings;
493fb300 5875
41c445ff
JB		 5876 /* Setup default MSIX irq handler for VSI */
5877 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5878
5879 pf->vsi[vsi_idx] = vsi;
5880 ret = vsi_idx;
493fb300
AD		 5881 goto unlock_pf;
5882
9f65e15b 5883err_rings:
493fb300
AD		 5884 pf->next_vsi = i - 1;
5885 kfree(vsi);
5886unlock_pf:
41c445ff
JB		 5887 mutex_unlock(&pf->switch_mutex);
5888 return ret;
5889}
5890
f650a38b
ASJ		 5891/**
5892 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5893 * @type: VSI pointer
bc7d338f 5894 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5895 *
5896 * On error: returns error code (negative)
5897 * On success: returns 0
5898 **/
bc7d338f 5899static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5900{
5901 /* free the ring and vector containers */
bc7d338f
ASJ		 5902 if (free_qvectors) {
5903 kfree(vsi->q_vectors);
5904 vsi->q_vectors = NULL;
5905 }
f650a38b
ASJ		 5906 kfree(vsi->tx_rings);
5907 vsi->tx_rings = NULL;
5908 vsi->rx_rings = NULL;
5909}
5910
41c445ff
JB		 5911/**
5912 * i40e_vsi_clear - Deallocate the VSI provided
5913 * @vsi: the VSI being un-configured
5914 **/
5915static int i40e_vsi_clear(struct i40e_vsi *vsi)
5916{
5917 struct i40e_pf *pf;
5918
5919 if (!vsi)
5920 return 0;
5921
5922 if (!vsi->back)
5923 goto free_vsi;
5924 pf = vsi->back;
5925
5926 mutex_lock(&pf->switch_mutex);
5927 if (!pf->vsi[vsi->idx]) {
5928 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5929 vsi->idx, vsi->idx, vsi, vsi->type);
5930 goto unlock_vsi;
5931 }
5932
5933 if (pf->vsi[vsi->idx] != vsi) {
5934 dev_err(&pf->pdev->dev,
5935 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5936 pf->vsi[vsi->idx]->idx,
5937 pf->vsi[vsi->idx],
5938 pf->vsi[vsi->idx]->type,
5939 vsi->idx, vsi, vsi->type);
5940 goto unlock_vsi;
5941 }
5942
5943 /* updates the pf for this cleared vsi */
5944 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5945 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5946
bc7d338f 5947 i40e_vsi_free_arrays(vsi, true);
493fb300 5948
41c445ff
JB		 5949 pf->vsi[vsi->idx] = NULL;
5950 if (vsi->idx < pf->next_vsi)
5951 pf->next_vsi = vsi->idx;
5952
5953unlock_vsi:
5954 mutex_unlock(&pf->switch_mutex);
5955free_vsi:
5956 kfree(vsi);
5957
5958 return 0;
5959}
5960
9f65e15b
AD		 5961/**
5962 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5963 * @vsi: the VSI being cleaned
5964 **/
be1d5eea 5965static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5966{
5967 int i;
5968
8e9dca53 5969 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5970 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5971 kfree_rcu(vsi->tx_rings[i], rcu);
5972 vsi->tx_rings[i] = NULL;
5973 vsi->rx_rings[i] = NULL;
5974 }
be1d5eea 5975 }
9f65e15b
AD		 5976}
5977
41c445ff
JB		 5978/**
5979 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5980 * @vsi: the VSI being configured
5981 **/
5982static int i40e_alloc_rings(struct i40e_vsi *vsi)
5983{
5984 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5985 int i;
5986
41c445ff 5987 /* Set basic values in the rings to be used later during open() */
d7397644 5988 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5989 struct i40e_ring *tx_ring;
5990 struct i40e_ring *rx_ring;
5991
ac6c5e3d 5992 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5993 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5994 if (!tx_ring)
5995 goto err_out;
41c445ff
JB		 5996
5997 tx_ring->queue_index = i;
5998 tx_ring->reg_idx = vsi->base_queue + i;
5999 tx_ring->ring_active = false;
6000 tx_ring->vsi = vsi;
6001 tx_ring->netdev = vsi->netdev;
6002 tx_ring->dev = &pf->pdev->dev;
6003 tx_ring->count = vsi->num_desc;
6004 tx_ring->size = 0;
6005 tx_ring->dcb_tc = 0;
9f65e15b 6006 vsi->tx_rings[i] = tx_ring;
41c445ff 6007
9f65e15b 6008 rx_ring = &tx_ring[1];
41c445ff
JB		 6009 rx_ring->queue_index = i;
6010 rx_ring->reg_idx = vsi->base_queue + i;
6011 rx_ring->ring_active = false;
6012 rx_ring->vsi = vsi;
6013 rx_ring->netdev = vsi->netdev;
6014 rx_ring->dev = &pf->pdev->dev;
6015 rx_ring->count = vsi->num_desc;
6016 rx_ring->size = 0;
6017 rx_ring->dcb_tc = 0;
6018 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6019 set_ring_16byte_desc_enabled(rx_ring);
6020 else
6021 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6022 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6023 }
6024
6025 return 0;
9f65e15b
AD		 6026
6027err_out:
6028 i40e_vsi_clear_rings(vsi);
6029 return -ENOMEM;
41c445ff
JB		 6030}
6031
6032/**
6033 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6034 * @pf: board private structure
6035 * @vectors: the number of MSI-X vectors to request
6036 *
6037 * Returns the number of vectors reserved, or error
6038 **/
6039static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6040{
7b37f376
AG		 6041 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6042 I40E_MIN_MSIX, vectors);
6043 if (vectors < 0) {
41c445ff 6044 dev_info(&pf->pdev->dev,
7b37f376 6045 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6046 vectors = 0;
6047 }
6048
7b37f376
AG		 6049 pf->num_msix_entries = vectors;
6050
41c445ff
JB		 6051 return vectors;
6052}
6053
6054/**
6055 * i40e_init_msix - Setup the MSIX capability
6056 * @pf: board private structure
6057 *
6058 * Work with the OS to set up the MSIX vectors needed.
6059 *
6060 * Returns 0 on success, negative on failure
6061 **/
6062static int i40e_init_msix(struct i40e_pf *pf)
6063{
6064 i40e_status err = 0;
6065 struct i40e_hw *hw = &pf->hw;
6066 int v_budget, i;
6067 int vec;
6068
6069 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6070 return -ENODEV;
6071
6072 /* The number of vectors we'll request will be comprised of:
6073 * - Add 1 for "other" cause for Admin Queue events, etc.
6074 * - The number of LAN queue pairs
f8ff1464
ASJ		 6075 * - Queues being used for RSS.
6076 * We don't need as many as max_rss_size vectors.
6077 * use rss_size instead in the calculation since that
6078 * is governed by number of cpus in the system.
6079 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6080 * - The number of VMDq pairs
6081 * Once we count this up, try the request.
6082 *
6083 * If we can't get what we want, we'll simplify to nearly nothing
6084 * and try again. If that still fails, we punt.
6085 */
f8ff1464 6086 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6087 pf->num_vmdq_msix = pf->num_vmdq_qps;
6088 v_budget = 1 + pf->num_lan_msix;
6089 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6090 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6091 v_budget++;
6092
6093 /* Scale down if necessary, and the rings will share vectors */
6094 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6095
6096 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6097 GFP_KERNEL);
6098 if (!pf->msix_entries)
6099 return -ENOMEM;
6100
6101 for (i = 0; i < v_budget; i++)
6102 pf->msix_entries[i].entry = i;
6103 vec = i40e_reserve_msix_vectors(pf, v_budget);
6104 if (vec < I40E_MIN_MSIX) {
6105 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6106 kfree(pf->msix_entries);
6107 pf->msix_entries = NULL;
6108 return -ENODEV;
6109
6110 } else if (vec == I40E_MIN_MSIX) {
6111 /* Adjust for minimal MSIX use */
77fa28be 6112 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6113 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6114 pf->num_vmdq_vsis = 0;
6115 pf->num_vmdq_qps = 0;
6116 pf->num_vmdq_msix = 0;
6117 pf->num_lan_qps = 1;
6118 pf->num_lan_msix = 1;
6119
6120 } else if (vec != v_budget) {
6121 /* Scale vector usage down */
6122 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6123 vec--; /* reserve the misc vector */
6124
6125 /* partition out the remaining vectors */
6126 switch (vec) {
6127 case 2:
6128 pf->num_vmdq_vsis = 1;
6129 pf->num_lan_msix = 1;
6130 break;
6131 case 3:
6132 pf->num_vmdq_vsis = 1;
6133 pf->num_lan_msix = 2;
6134 break;
6135 default:
6136 pf->num_lan_msix = min_t(int, (vec / 2),
6137 pf->num_lan_qps);
6138 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6139 I40E_DEFAULT_NUM_VMDQ_VSI);
6140 break;
6141 }
6142 }
6143
6144 return err;
6145}
6146
493fb300 6147/**
90e04070 6148 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6149 * @vsi: the VSI being configured
6150 * @v_idx: index of the vector in the vsi struct
6151 *
6152 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6153 **/
90e04070 6154static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6155{
6156 struct i40e_q_vector *q_vector;
6157
6158 /* allocate q_vector */
6159 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6160 if (!q_vector)
6161 return -ENOMEM;
6162
6163 q_vector->vsi = vsi;
6164 q_vector->v_idx = v_idx;
6165 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6166 if (vsi->netdev)
6167 netif_napi_add(vsi->netdev, &q_vector->napi,
6168 i40e_napi_poll, vsi->work_limit);
6169
cd0b6fa6
AD		 6170 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6171 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6172
493fb300
AD		 6173 /* tie q_vector and vsi together */
6174 vsi->q_vectors[v_idx] = q_vector;
6175
6176 return 0;
6177}
6178
41c445ff 6179/**
90e04070 6180 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6181 * @vsi: the VSI being configured
6182 *
6183 * We allocate one q_vector per queue interrupt. If allocation fails we
6184 * return -ENOMEM.
6185 **/
90e04070 6186static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6187{
6188 struct i40e_pf *pf = vsi->back;
6189 int v_idx, num_q_vectors;
493fb300 6190 int err;
41c445ff
JB		 6191
6192 /* if not MSIX, give the one vector only to the LAN VSI */
6193 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6194 num_q_vectors = vsi->num_q_vectors;
6195 else if (vsi == pf->vsi[pf->lan_vsi])
6196 num_q_vectors = 1;
6197 else
6198 return -EINVAL;
6199
41c445ff 6200 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6201 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6202 if (err)
6203 goto err_out;
41c445ff
JB		 6204 }
6205
6206 return 0;
493fb300
AD		 6207
6208err_out:
6209 while (v_idx--)
6210 i40e_free_q_vector(vsi, v_idx);
6211
6212 return err;
41c445ff
JB		 6213}
6214
6215/**
6216 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6217 * @pf: board private structure to initialize
6218 **/
6219static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6220{
6221 int err = 0;
6222
6223 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6224 err = i40e_init_msix(pf);
6225 if (err) {
60ea5f83
JB		 6226 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6227 I40E_FLAG_RSS_ENABLED |
6228 I40E_FLAG_DCB_ENABLED |
6229 I40E_FLAG_SRIOV_ENABLED |
6230 I40E_FLAG_FD_SB_ENABLED |
6231 I40E_FLAG_FD_ATR_ENABLED |
6232 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6233
6234 /* rework the queue expectations without MSIX */
6235 i40e_determine_queue_usage(pf);
6236 }
6237 }
6238
6239 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6240 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6241 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6242 err = pci_enable_msi(pf->pdev);
6243 if (err) {
958a3e3b 6244 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6245 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6246 }
6247 }
6248
958a3e3b 6249 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6250 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6251
41c445ff
JB		 6252 /* track first vector for misc interrupts */
6253 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6254}
6255
6256/**
6257 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6258 * @pf: board private structure
6259 *
6260 * This sets up the handler for MSIX 0, which is used to manage the
6261 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6262 * when in MSI or Legacy interrupt mode.
6263 **/
6264static int i40e_setup_misc_vector(struct i40e_pf *pf)
6265{
6266 struct i40e_hw *hw = &pf->hw;
6267 int err = 0;
6268
6269 /* Only request the irq if this is the first time through, and
6270 * not when we're rebuilding after a Reset
6271 */
6272 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6273 err = request_irq(pf->msix_entries[0].vector,
6274 i40e_intr, 0, pf->misc_int_name, pf);
6275 if (err) {
6276 dev_info(&pf->pdev->dev,
77fa28be
CS		 6277 "request_irq for %s failed: %d\n",
6278 pf->misc_int_name, err);
41c445ff
JB		 6279 return -EFAULT;
6280 }
6281 }
6282
6283 i40e_enable_misc_int_causes(hw);
6284
6285 /* associate no queues to the misc vector */
6286 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6287 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6288
6289 i40e_flush(hw);
6290
6291 i40e_irq_dynamic_enable_icr0(pf);
6292
6293 return err;
6294}
6295
6296/**
6297 * i40e_config_rss - Prepare for RSS if used
6298 * @pf: board private structure
6299 **/
6300static int i40e_config_rss(struct i40e_pf *pf)
6301{
41c445ff
JB		 6302 /* Set of random keys generated using kernel random number generator */
6303 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6304 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6305 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6306 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6307 struct i40e_hw *hw = &pf->hw;
6308 u32 lut = 0;
6309 int i, j;
6310 u64 hena;
41c445ff
JB		 6311
6312 /* Fill out hash function seed */
6313 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6314 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6315
6316 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6317 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6318 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6319 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6320 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6321 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6322
6323 /* Populate the LUT with max no. of queues in round robin fashion */
6324 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6325
6326 /* The assumption is that lan qp count will be the highest
6327 * qp count for any PF VSI that needs RSS.
6328 * If multiple VSIs need RSS support, all the qp counts
6329 * for those VSIs should be a power of 2 for RSS to work.
6330 * If LAN VSI is the only consumer for RSS then this requirement
6331 * is not necessary.
6332 */
6333 if (j == pf->rss_size)
6334 j = 0;
6335 /* lut = 4-byte sliding window of 4 lut entries */
6336 lut = (lut << 8) | (j &
6337 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6338 /* On i = 3, we have 4 entries in lut; write to the register */
6339 if ((i & 3) == 3)
6340 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6341 }
6342 i40e_flush(hw);
6343
6344 return 0;
6345}
6346
f8ff1464
ASJ		 6347/**
6348 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6349 * @pf: board private structure
6350 * @queue_count: the requested queue count for rss.
6351 *
6352 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6353 * count which may be different from the requested queue count.
6354 **/
6355int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6356{
6357 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6358 return 0;
6359
6360 queue_count = min_t(int, queue_count, pf->rss_size_max);
6361 queue_count = rounddown_pow_of_two(queue_count);
6362
6363 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6364 i40e_prep_for_reset(pf);
6365
f8ff1464
ASJ		 6366 pf->rss_size = queue_count;
6367
6368 i40e_reset_and_rebuild(pf, true);
6369 i40e_config_rss(pf);
6370 }
6371 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6372 return pf->rss_size;
6373}
6374
41c445ff
JB		 6375/**
6376 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6377 * @pf: board private structure to initialize
6378 *
6379 * i40e_sw_init initializes the Adapter private data structure.
6380 * Fields are initialized based on PCI device information and
6381 * OS network device settings (MTU size).
6382 **/
6383static int i40e_sw_init(struct i40e_pf *pf)
6384{
6385 int err = 0;
6386 int size;
6387
6388 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6389 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6390 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6391 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6392 if (I40E_DEBUG_USER & debug)
6393 pf->hw.debug_mask = debug;
6394 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6395 I40E_DEFAULT_MSG_ENABLE);
6396 }
6397
6398 /* Set default capability flags */
6399 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6400 I40E_FLAG_MSI_ENABLED |
6401 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6402 I40E_FLAG_RX_1BUF_ENABLED;
6403
7134f9ce
JB		 6404 /* Depending on PF configurations, it is possible that the RSS
6405 * maximum might end up larger than the available queues
6406 */
41c445ff 6407 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6408 pf->rss_size_max = min_t(int, pf->rss_size_max,
6409 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6410 if (pf->hw.func_caps.rss) {
6411 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6412 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6413 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6414 } else {
6415 pf->rss_size = 1;
6416 }
6417
2050bc65
CS		 6418 /* MFP mode enabled */
6419 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6420 pf->flags |= I40E_FLAG_MFP_ENABLED;
6421 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6422 }
6423
cbf61325
ASJ		 6424 /* FW/NVM is not yet fixed in this regard */
6425 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6426 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6427 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6428 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6429 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6430 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6431 } else {
6432 dev_info(&pf->pdev->dev,
0b67584f 6433 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6434 }
cbf61325
ASJ		 6435 pf->fdir_pf_filter_count =
6436 pf->hw.func_caps.fd_filters_guaranteed;
6437 pf->hw.fdir_shared_filter_count =
6438 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6439 }
6440
6441 if (pf->hw.func_caps.vmdq) {
6442 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6443 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6444 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6445 }
6446
41c445ff
JB		 6447#ifdef CONFIG_PCI_IOV
6448 if (pf->hw.func_caps.num_vfs) {
6449 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6450 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6451 pf->num_req_vfs = min_t(int,
6452 pf->hw.func_caps.num_vfs,
6453 I40E_MAX_VF_COUNT);
6454 }
6455#endif /* CONFIG_PCI_IOV */
6456 pf->eeprom_version = 0xDEAD;
6457 pf->lan_veb = I40E_NO_VEB;
6458 pf->lan_vsi = I40E_NO_VSI;
6459
6460 /* set up queue assignment tracking */
6461 size = sizeof(struct i40e_lump_tracking)
6462 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6463 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6464 if (!pf->qp_pile) {
6465 err = -ENOMEM;
6466 goto sw_init_done;
6467 }
6468 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6469 pf->qp_pile->search_hint = 0;
6470
6471 /* set up vector assignment tracking */
6472 size = sizeof(struct i40e_lump_tracking)
6473 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6474 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6475 if (!pf->irq_pile) {
6476 kfree(pf->qp_pile);
6477 err = -ENOMEM;
6478 goto sw_init_done;
6479 }
6480 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6481 pf->irq_pile->search_hint = 0;
6482
6483 mutex_init(&pf->switch_mutex);
6484
6485sw_init_done:
6486 return err;
6487}
6488
7c3c288b
ASJ		 6489/**
6490 * i40e_set_ntuple - set the ntuple feature flag and take action
6491 * @pf: board private structure to initialize
6492 * @features: the feature set that the stack is suggesting
6493 *
6494 * returns a bool to indicate if reset needs to happen
6495 **/
6496bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6497{
6498 bool need_reset = false;
6499
6500 /* Check if Flow Director n-tuple support was enabled or disabled. If
6501 * the state changed, we need to reset.
6502 */
6503 if (features & NETIF_F_NTUPLE) {
6504 /* Enable filters and mark for reset */
6505 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6506 need_reset = true;
6507 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6508 } else {
6509 /* turn off filters, mark for reset and clear SW filter list */
6510 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6511 need_reset = true;
6512 i40e_fdir_filter_exit(pf);
6513 }
6514 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6515 /* if ATR was disabled it can be re-enabled. */
6516 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6517 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6518 }
6519 return need_reset;
6520}
6521
41c445ff
JB		 6522/**
6523 * i40e_set_features - set the netdev feature flags
6524 * @netdev: ptr to the netdev being adjusted
6525 * @features: the feature set that the stack is suggesting
6526 **/
6527static int i40e_set_features(struct net_device *netdev,
6528 netdev_features_t features)
6529{
6530 struct i40e_netdev_priv *np = netdev_priv(netdev);
6531 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6532 struct i40e_pf *pf = vsi->back;
6533 bool need_reset;
41c445ff
JB		 6534
6535 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6536 i40e_vlan_stripping_enable(vsi);
6537 else
6538 i40e_vlan_stripping_disable(vsi);
6539
7c3c288b
ASJ		 6540 need_reset = i40e_set_ntuple(pf, features);
6541
6542 if (need_reset)
6543 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6544
41c445ff
JB		 6545 return 0;
6546}
6547
a1c9a9d9
JK		 6548#ifdef CONFIG_I40E_VXLAN
6549/**
6550 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6551 * @pf: board private structure
6552 * @port: The UDP port to look up
6553 *
6554 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6555 **/
6556static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6557{
6558 u8 i;
6559
6560 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6561 if (pf->vxlan_ports[i] == port)
6562 return i;
6563 }
6564
6565 return i;
6566}
6567
6568/**
6569 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6570 * @netdev: This physical port's netdev
6571 * @sa_family: Socket Family that VXLAN is notifying us about
6572 * @port: New UDP port number that VXLAN started listening to
6573 **/
6574static void i40e_add_vxlan_port(struct net_device *netdev,
6575 sa_family_t sa_family, __be16 port)
6576{
6577 struct i40e_netdev_priv *np = netdev_priv(netdev);
6578 struct i40e_vsi *vsi = np->vsi;
6579 struct i40e_pf *pf = vsi->back;
6580 u8 next_idx;
6581 u8 idx;
6582
6583 if (sa_family == AF_INET6)
6584 return;
6585
6586 idx = i40e_get_vxlan_port_idx(pf, port);
6587
6588 /* Check if port already exists */
6589 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6590 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6591 return;
6592 }
6593
6594 /* Now check if there is space to add the new port */
6595 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6596
6597 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6598 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6599 ntohs(port));
6600 return;
6601 }
6602
6603 /* New port: add it and mark its index in the bitmap */
6604 pf->vxlan_ports[next_idx] = port;
6605 pf->pending_vxlan_bitmap |= (1 << next_idx);
6606
6607 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6608}
6609
6610/**
6611 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6612 * @netdev: This physical port's netdev
6613 * @sa_family: Socket Family that VXLAN is notifying us about
6614 * @port: UDP port number that VXLAN stopped listening to
6615 **/
6616static void i40e_del_vxlan_port(struct net_device *netdev,
6617 sa_family_t sa_family, __be16 port)
6618{
6619 struct i40e_netdev_priv *np = netdev_priv(netdev);
6620 struct i40e_vsi *vsi = np->vsi;
6621 struct i40e_pf *pf = vsi->back;
6622 u8 idx;
6623
6624 if (sa_family == AF_INET6)
6625 return;
6626
6627 idx = i40e_get_vxlan_port_idx(pf, port);
6628
6629 /* Check if port already exists */
6630 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6631 /* if port exists, set it to 0 (mark for deletion)
6632 * and make it pending
6633 */
6634 pf->vxlan_ports[idx] = 0;
6635
6636 pf->pending_vxlan_bitmap |= (1 << idx);
6637
6638 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6639 } else {
6640 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6641 ntohs(port));
6642 }
6643}
6644
6645#endif
4ba0dea5
GR		 6646#ifdef HAVE_FDB_OPS
6647#ifdef USE_CONST_DEV_UC_CHAR
6648static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6649 struct net_device *dev,
6650 const unsigned char *addr,
6651 u16 flags)
6652#else
6653static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6654 struct net_device *dev,
6655 unsigned char *addr,
6656 u16 flags)
6657#endif
6658{
6659 struct i40e_netdev_priv *np = netdev_priv(dev);
6660 struct i40e_pf *pf = np->vsi->back;
6661 int err = 0;
6662
6663 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6664 return -EOPNOTSUPP;
6665
6666 /* Hardware does not support aging addresses so if a
6667 * ndm_state is given only allow permanent addresses
6668 */
6669 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6670 netdev_info(dev, "FDB only supports static addresses\n");
6671 return -EINVAL;
6672 }
6673
6674 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6675 err = dev_uc_add_excl(dev, addr);
6676 else if (is_multicast_ether_addr(addr))
6677 err = dev_mc_add_excl(dev, addr);
6678 else
6679 err = -EINVAL;
6680
6681 /* Only return duplicate errors if NLM_F_EXCL is set */
6682 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6683 err = 0;
6684
6685 return err;
6686}
6687
6688#ifndef USE_DEFAULT_FDB_DEL_DUMP
6689#ifdef USE_CONST_DEV_UC_CHAR
6690static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6691 struct net_device *dev,
6692 const unsigned char *addr)
6693#else
6694static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6695 struct net_device *dev,
6696 unsigned char *addr)
6697#endif
6698{
6699 struct i40e_netdev_priv *np = netdev_priv(dev);
6700 struct i40e_pf *pf = np->vsi->back;
6701 int err = -EOPNOTSUPP;
6702
6703 if (ndm->ndm_state & NUD_PERMANENT) {
6704 netdev_info(dev, "FDB only supports static addresses\n");
6705 return -EINVAL;
6706 }
6707
6708 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6709 if (is_unicast_ether_addr(addr))
6710 err = dev_uc_del(dev, addr);
6711 else if (is_multicast_ether_addr(addr))
6712 err = dev_mc_del(dev, addr);
6713 else
6714 err = -EINVAL;
6715 }
6716
6717 return err;
6718}
6719
6720static int i40e_ndo_fdb_dump(struct sk_buff *skb,
6721 struct netlink_callback *cb,
6722 struct net_device *dev,
6723 int idx)
6724{
6725 struct i40e_netdev_priv *np = netdev_priv(dev);
6726 struct i40e_pf *pf = np->vsi->back;
6727
6728 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
6729 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6730
6731 return idx;
6732}
6733
6734#endif /* USE_DEFAULT_FDB_DEL_DUMP */
6735#endif /* HAVE_FDB_OPS */
41c445ff
JB		 6736static const struct net_device_ops i40e_netdev_ops = {
6737 .ndo_open = i40e_open,
6738 .ndo_stop = i40e_close,
6739 .ndo_start_xmit = i40e_lan_xmit_frame,
6740 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6741 .ndo_set_rx_mode = i40e_set_rx_mode,
6742 .ndo_validate_addr = eth_validate_addr,
6743 .ndo_set_mac_address = i40e_set_mac,
6744 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6745 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6746 .ndo_tx_timeout = i40e_tx_timeout,
6747 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6748 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6749#ifdef CONFIG_NET_POLL_CONTROLLER
6750 .ndo_poll_controller = i40e_netpoll,
6751#endif
6752 .ndo_setup_tc = i40e_setup_tc,
6753 .ndo_set_features = i40e_set_features,
6754 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6755 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6756 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6757 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6758 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6759#ifdef CONFIG_I40E_VXLAN
6760 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6761 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6762#endif
4ba0dea5
GR		 6763#ifdef HAVE_FDB_OPS
6764 .ndo_fdb_add = i40e_ndo_fdb_add,
6765#ifndef USE_DEFAULT_FDB_DEL_DUMP
6766 .ndo_fdb_del = i40e_ndo_fdb_del,
6767 .ndo_fdb_dump = i40e_ndo_fdb_dump,
6768#endif
6769#endif
41c445ff
JB		 6770};
6771
6772/**
6773 * i40e_config_netdev - Setup the netdev flags
6774 * @vsi: the VSI being configured
6775 *
6776 * Returns 0 on success, negative value on failure
6777 **/
6778static int i40e_config_netdev(struct i40e_vsi *vsi)
6779{
1a10370a 6780 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6781 struct i40e_pf *pf = vsi->back;
6782 struct i40e_hw *hw = &pf->hw;
6783 struct i40e_netdev_priv *np;
6784 struct net_device *netdev;
6785 u8 mac_addr[ETH_ALEN];
6786 int etherdev_size;
6787
6788 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6789 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6790 if (!netdev)
6791 return -ENOMEM;
6792
6793 vsi->netdev = netdev;
6794 np = netdev_priv(netdev);
6795 np->vsi = vsi;
6796
d70e941b 6797 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6798 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6799 NETIF_F_TSO;
41c445ff
JB		 6800
6801 netdev->features = NETIF_F_SG |
6802 NETIF_F_IP_CSUM |
6803 NETIF_F_SCTP_CSUM |
6804 NETIF_F_HIGHDMA |
6805 NETIF_F_GSO_UDP_TUNNEL |
6806 NETIF_F_HW_VLAN_CTAG_TX |
6807 NETIF_F_HW_VLAN_CTAG_RX |
6808 NETIF_F_HW_VLAN_CTAG_FILTER |
6809 NETIF_F_IPV6_CSUM |
6810 NETIF_F_TSO |
6811 NETIF_F_TSO6 |
6812 NETIF_F_RXCSUM |
7c3c288b 6813 NETIF_F_NTUPLE |
41c445ff
JB		 6814 NETIF_F_RXHASH |
6815 0;
6816
6817 /* copy netdev features into list of user selectable features */
6818 netdev->hw_features |= netdev->features;
6819
6820 if (vsi->type == I40E_VSI_MAIN) {
6821 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6822 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6823 } else {
6824 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6825 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6826 pf->vsi[pf->lan_vsi]->netdev->name);
6827 random_ether_addr(mac_addr);
6828 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6829 }
1a10370a 6830 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6831
6832 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6833 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6834 /* vlan gets same features (except vlan offload)
6835 * after any tweaks for specific VSI types
6836 */
6837 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6838 NETIF_F_HW_VLAN_CTAG_RX |
6839 NETIF_F_HW_VLAN_CTAG_FILTER);
6840 netdev->priv_flags |= IFF_UNICAST_FLT;
6841 netdev->priv_flags |= IFF_SUPP_NOFCS;
6842 /* Setup netdev TC information */
6843 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6844
6845 netdev->netdev_ops = &i40e_netdev_ops;
6846 netdev->watchdog_timeo = 5 * HZ;
6847 i40e_set_ethtool_ops(netdev);
6848
6849 return 0;
6850}
6851
6852/**
6853 * i40e_vsi_delete - Delete a VSI from the switch
6854 * @vsi: the VSI being removed
6855 *
6856 * Returns 0 on success, negative value on failure
6857 **/
6858static void i40e_vsi_delete(struct i40e_vsi *vsi)
6859{
6860 /* remove default VSI is not allowed */
6861 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6862 return;
6863
41c445ff
JB		 6864 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6865 return;
6866}
6867
6868/**
6869 * i40e_add_vsi - Add a VSI to the switch
6870 * @vsi: the VSI being configured
6871 *
6872 * This initializes a VSI context depending on the VSI type to be added and
6873 * passes it down to the add_vsi aq command.
6874 **/
6875static int i40e_add_vsi(struct i40e_vsi *vsi)
6876{
6877 int ret = -ENODEV;
6878 struct i40e_mac_filter *f, *ftmp;
6879 struct i40e_pf *pf = vsi->back;
6880 struct i40e_hw *hw = &pf->hw;
6881 struct i40e_vsi_context ctxt;
6882 u8 enabled_tc = 0x1; /* TC0 enabled */
6883 int f_count = 0;
6884
6885 memset(&ctxt, 0, sizeof(ctxt));
6886 switch (vsi->type) {
6887 case I40E_VSI_MAIN:
6888 /* The PF's main VSI is already setup as part of the
6889 * device initialization, so we'll not bother with
6890 * the add_vsi call, but we will retrieve the current
6891 * VSI context.
6892 */
6893 ctxt.seid = pf->main_vsi_seid;
6894 ctxt.pf_num = pf->hw.pf_id;
6895 ctxt.vf_num = 0;
6896 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6897 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6898 if (ret) {
6899 dev_info(&pf->pdev->dev,
6900 "couldn't get pf vsi config, err %d, aq_err %d\n",
6901 ret, pf->hw.aq.asq_last_status);
6902 return -ENOENT;
6903 }
6904 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6905 vsi->info.valid_sections = 0;
6906
6907 vsi->seid = ctxt.seid;
6908 vsi->id = ctxt.vsi_number;
6909
6910 enabled_tc = i40e_pf_get_tc_map(pf);
6911
6912 /* MFP mode setup queue map and update VSI */
6913 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6914 memset(&ctxt, 0, sizeof(ctxt));
6915 ctxt.seid = pf->main_vsi_seid;
6916 ctxt.pf_num = pf->hw.pf_id;
6917 ctxt.vf_num = 0;
6918 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6919 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6920 if (ret) {
6921 dev_info(&pf->pdev->dev,
6922 "update vsi failed, aq_err=%d\n",
6923 pf->hw.aq.asq_last_status);
6924 ret = -ENOENT;
6925 goto err;
6926 }
6927 /* update the local VSI info queue map */
6928 i40e_vsi_update_queue_map(vsi, &ctxt);
6929 vsi->info.valid_sections = 0;
6930 } else {
6931 /* Default/Main VSI is only enabled for TC0
6932 * reconfigure it to enable all TCs that are
6933 * available on the port in SFP mode.
6934 */
6935 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6936 if (ret) {
6937 dev_info(&pf->pdev->dev,
6938 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6939 enabled_tc, ret,
6940 pf->hw.aq.asq_last_status);
6941 ret = -ENOENT;
6942 }
6943 }
6944 break;
6945
6946 case I40E_VSI_FDIR:
cbf61325
ASJ		 6947 ctxt.pf_num = hw->pf_id;
6948 ctxt.vf_num = 0;
6949 ctxt.uplink_seid = vsi->uplink_seid;
6950 ctxt.connection_type = 0x1; /* regular data port */
6951 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6952 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6953 break;
6954
6955 case I40E_VSI_VMDQ2:
6956 ctxt.pf_num = hw->pf_id;
6957 ctxt.vf_num = 0;
6958 ctxt.uplink_seid = vsi->uplink_seid;
6959 ctxt.connection_type = 0x1; /* regular data port */
6960 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6961
6962 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6963
6964 /* This VSI is connected to VEB so the switch_id
6965 * should be set to zero by default.
6966 */
6967 ctxt.info.switch_id = 0;
6968 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6969 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6970
6971 /* Setup the VSI tx/rx queue map for TC0 only for now */
6972 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6973 break;
6974
6975 case I40E_VSI_SRIOV:
6976 ctxt.pf_num = hw->pf_id;
6977 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6978 ctxt.uplink_seid = vsi->uplink_seid;
6979 ctxt.connection_type = 0x1; /* regular data port */
6980 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6981
6982 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6983
6984 /* This VSI is connected to VEB so the switch_id
6985 * should be set to zero by default.
6986 */
6987 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6988
6989 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6990 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6991 /* Setup the VSI tx/rx queue map for TC0 only for now */
6992 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6993 break;
6994
6995 default:
6996 return -ENODEV;
6997 }
6998
6999 if (vsi->type != I40E_VSI_MAIN) {
7000 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7001 if (ret) {
7002 dev_info(&vsi->back->pdev->dev,
7003 "add vsi failed, aq_err=%d\n",
7004 vsi->back->hw.aq.asq_last_status);
7005 ret = -ENOENT;
7006 goto err;
7007 }
7008 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7009 vsi->info.valid_sections = 0;
7010 vsi->seid = ctxt.seid;
7011 vsi->id = ctxt.vsi_number;
7012 }
7013
7014 /* If macvlan filters already exist, force them to get loaded */
7015 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7016 f->changed = true;
7017 f_count++;
7018 }
7019 if (f_count) {
7020 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7021 pf->flags |= I40E_FLAG_FILTER_SYNC;
7022 }
7023
7024 /* Update VSI BW information */
7025 ret = i40e_vsi_get_bw_info(vsi);
7026 if (ret) {
7027 dev_info(&pf->pdev->dev,
7028 "couldn't get vsi bw info, err %d, aq_err %d\n",
7029 ret, pf->hw.aq.asq_last_status);
7030 /* VSI is already added so not tearing that up */
7031 ret = 0;
7032 }
7033
7034err:
7035 return ret;
7036}
7037
7038/**
7039 * i40e_vsi_release - Delete a VSI and free its resources
7040 * @vsi: the VSI being removed
7041 *
7042 * Returns 0 on success or < 0 on error
7043 **/
7044int i40e_vsi_release(struct i40e_vsi *vsi)
7045{
7046 struct i40e_mac_filter *f, *ftmp;
7047 struct i40e_veb *veb = NULL;
7048 struct i40e_pf *pf;
7049 u16 uplink_seid;
7050 int i, n;
7051
7052 pf = vsi->back;
7053
7054 /* release of a VEB-owner or last VSI is not allowed */
7055 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7056 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7057 vsi->seid, vsi->uplink_seid);
7058 return -ENODEV;
7059 }
7060 if (vsi == pf->vsi[pf->lan_vsi] &&
7061 !test_bit(__I40E_DOWN, &pf->state)) {
7062 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7063 return -ENODEV;
7064 }
7065
7066 uplink_seid = vsi->uplink_seid;
7067 if (vsi->type != I40E_VSI_SRIOV) {
7068 if (vsi->netdev_registered) {
7069 vsi->netdev_registered = false;
7070 if (vsi->netdev) {
7071 /* results in a call to i40e_close() */
7072 unregister_netdev(vsi->netdev);
41c445ff
JB		 7073 }
7074 } else {
7075 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
7076 i40e_down(vsi);
7077 i40e_vsi_free_irq(vsi);
7078 i40e_vsi_free_tx_resources(vsi);
7079 i40e_vsi_free_rx_resources(vsi);
7080 }
7081 i40e_vsi_disable_irq(vsi);
7082 }
7083
7084 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7085 i40e_del_filter(vsi, f->macaddr, f->vlan,
7086 f->is_vf, f->is_netdev);
7087 i40e_sync_vsi_filters(vsi);
7088
7089 i40e_vsi_delete(vsi);
7090 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7091 if (vsi->netdev) {
7092 free_netdev(vsi->netdev);
7093 vsi->netdev = NULL;
7094 }
41c445ff
JB		 7095 i40e_vsi_clear_rings(vsi);
7096 i40e_vsi_clear(vsi);
7097
7098 /* If this was the last thing on the VEB, except for the
7099 * controlling VSI, remove the VEB, which puts the controlling
7100 * VSI onto the next level down in the switch.
7101 *
7102 * Well, okay, there's one more exception here: don't remove
7103 * the orphan VEBs yet. We'll wait for an explicit remove request
7104 * from up the network stack.
7105 */
7106 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7107 if (pf->vsi[i] &&
7108 pf->vsi[i]->uplink_seid == uplink_seid &&
7109 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7110 n++; /* count the VSIs */
7111 }
7112 }
7113 for (i = 0; i < I40E_MAX_VEB; i++) {
7114 if (!pf->veb[i])
7115 continue;
7116 if (pf->veb[i]->uplink_seid == uplink_seid)
7117 n++; /* count the VEBs */
7118 if (pf->veb[i]->seid == uplink_seid)
7119 veb = pf->veb[i];
7120 }
7121 if (n == 0 && veb && veb->uplink_seid != 0)
7122 i40e_veb_release(veb);
7123
7124 return 0;
7125}
7126
7127/**
7128 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7129 * @vsi: ptr to the VSI
7130 *
7131 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7132 * corresponding SW VSI structure and initializes num_queue_pairs for the
7133 * newly allocated VSI.
7134 *
7135 * Returns 0 on success or negative on failure
7136 **/
7137static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7138{
7139 int ret = -ENOENT;
7140 struct i40e_pf *pf = vsi->back;
7141
493fb300 7142 if (vsi->q_vectors[0]) {
41c445ff
JB		 7143 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7144 vsi->seid);
7145 return -EEXIST;
7146 }
7147
7148 if (vsi->base_vector) {
f29eaa3d 7149 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7150 vsi->seid, vsi->base_vector);
7151 return -EEXIST;
7152 }
7153
90e04070 7154 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7155 if (ret) {
7156 dev_info(&pf->pdev->dev,
7157 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7158 vsi->num_q_vectors, vsi->seid, ret);
7159 vsi->num_q_vectors = 0;
7160 goto vector_setup_out;
7161 }
7162
958a3e3b
SN		 7163 if (vsi->num_q_vectors)
7164 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7165 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7166 if (vsi->base_vector < 0) {
7167 dev_info(&pf->pdev->dev,
f29eaa3d 7168 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7169 vsi->seid, vsi->base_vector);
7170 i40e_vsi_free_q_vectors(vsi);
7171 ret = -ENOENT;
7172 goto vector_setup_out;
7173 }
7174
7175vector_setup_out:
7176 return ret;
7177}
7178
bc7d338f
ASJ		 7179/**
7180 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7181 * @vsi: pointer to the vsi.
7182 *
7183 * This re-allocates a vsi's queue resources.
7184 *
7185 * Returns pointer to the successfully allocated and configured VSI sw struct
7186 * on success, otherwise returns NULL on failure.
7187 **/
7188static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7189{
7190 struct i40e_pf *pf = vsi->back;
7191 u8 enabled_tc;
7192 int ret;
7193
7194 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7195 i40e_vsi_clear_rings(vsi);
7196
7197 i40e_vsi_free_arrays(vsi, false);
7198 i40e_set_num_rings_in_vsi(vsi);
7199 ret = i40e_vsi_alloc_arrays(vsi, false);
7200 if (ret)
7201 goto err_vsi;
7202
7203 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7204 if (ret < 0) {
7205 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7206 vsi->seid, ret);
7207 goto err_vsi;
7208 }
7209 vsi->base_queue = ret;
7210
7211 /* Update the FW view of the VSI. Force a reset of TC and queue
7212 * layout configurations.
7213 */
7214 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7215 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7216 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7217 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7218
7219 /* assign it some queues */
7220 ret = i40e_alloc_rings(vsi);
7221 if (ret)
7222 goto err_rings;
7223
7224 /* map all of the rings to the q_vectors */
7225 i40e_vsi_map_rings_to_vectors(vsi);
7226 return vsi;
7227
7228err_rings:
7229 i40e_vsi_free_q_vectors(vsi);
7230 if (vsi->netdev_registered) {
7231 vsi->netdev_registered = false;
7232 unregister_netdev(vsi->netdev);
7233 free_netdev(vsi->netdev);
7234 vsi->netdev = NULL;
7235 }
7236 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7237err_vsi:
7238 i40e_vsi_clear(vsi);
7239 return NULL;
7240}
7241
41c445ff
JB		 7242/**
7243 * i40e_vsi_setup - Set up a VSI by a given type
7244 * @pf: board private structure
7245 * @type: VSI type
7246 * @uplink_seid: the switch element to link to
7247 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7248 *
7249 * This allocates the sw VSI structure and its queue resources, then add a VSI
7250 * to the identified VEB.
7251 *
7252 * Returns pointer to the successfully allocated and configure VSI sw struct on
7253 * success, otherwise returns NULL on failure.
7254 **/
7255struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7256 u16 uplink_seid, u32 param1)
7257{
7258 struct i40e_vsi *vsi = NULL;
7259 struct i40e_veb *veb = NULL;
7260 int ret, i;
7261 int v_idx;
7262
7263 /* The requested uplink_seid must be either
7264 * - the PF's port seid
7265 * no VEB is needed because this is the PF
7266 * or this is a Flow Director special case VSI
7267 * - seid of an existing VEB
7268 * - seid of a VSI that owns an existing VEB
7269 * - seid of a VSI that doesn't own a VEB
7270 * a new VEB is created and the VSI becomes the owner
7271 * - seid of the PF VSI, which is what creates the first VEB
7272 * this is a special case of the previous
7273 *
7274 * Find which uplink_seid we were given and create a new VEB if needed
7275 */
7276 for (i = 0; i < I40E_MAX_VEB; i++) {
7277 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7278 veb = pf->veb[i];
7279 break;
7280 }
7281 }
7282
7283 if (!veb && uplink_seid != pf->mac_seid) {
7284
7285 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7286 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7287 vsi = pf->vsi[i];
7288 break;
7289 }
7290 }
7291 if (!vsi) {
7292 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7293 uplink_seid);
7294 return NULL;
7295 }
7296
7297 if (vsi->uplink_seid == pf->mac_seid)
7298 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7299 vsi->tc_config.enabled_tc);
7300 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7301 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7302 vsi->tc_config.enabled_tc);
7303
7304 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7305 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7306 veb = pf->veb[i];
7307 }
7308 if (!veb) {
7309 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7310 return NULL;
7311 }
7312
7313 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7314 uplink_seid = veb->seid;
7315 }
7316
7317 /* get vsi sw struct */
7318 v_idx = i40e_vsi_mem_alloc(pf, type);
7319 if (v_idx < 0)
7320 goto err_alloc;
7321 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7322 if (!vsi)
7323 goto err_alloc;
41c445ff
JB		 7324 vsi->type = type;
7325 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7326
7327 if (type == I40E_VSI_MAIN)
7328 pf->lan_vsi = v_idx;
7329 else if (type == I40E_VSI_SRIOV)
7330 vsi->vf_id = param1;
7331 /* assign it some queues */
cbf61325
ASJ		 7332 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7333 vsi->idx);
41c445ff
JB		 7334 if (ret < 0) {
7335 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7336 vsi->seid, ret);
7337 goto err_vsi;
7338 }
7339 vsi->base_queue = ret;
7340
7341 /* get a VSI from the hardware */
7342 vsi->uplink_seid = uplink_seid;
7343 ret = i40e_add_vsi(vsi);
7344 if (ret)
7345 goto err_vsi;
7346
7347 switch (vsi->type) {
7348 /* setup the netdev if needed */
7349 case I40E_VSI_MAIN:
7350 case I40E_VSI_VMDQ2:
7351 ret = i40e_config_netdev(vsi);
7352 if (ret)
7353 goto err_netdev;
7354 ret = register_netdev(vsi->netdev);
7355 if (ret)
7356 goto err_netdev;
7357 vsi->netdev_registered = true;
7358 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7359#ifdef CONFIG_I40E_DCB
7360 /* Setup DCB netlink interface */
7361 i40e_dcbnl_setup(vsi);
7362#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7363 /* fall through */
7364
7365 case I40E_VSI_FDIR:
7366 /* set up vectors and rings if needed */
7367 ret = i40e_vsi_setup_vectors(vsi);
7368 if (ret)
7369 goto err_msix;
7370
7371 ret = i40e_alloc_rings(vsi);
7372 if (ret)
7373 goto err_rings;
7374
7375 /* map all of the rings to the q_vectors */
7376 i40e_vsi_map_rings_to_vectors(vsi);
7377
7378 i40e_vsi_reset_stats(vsi);
7379 break;
7380
7381 default:
7382 /* no netdev or rings for the other VSI types */
7383 break;
7384 }
7385
7386 return vsi;
7387
7388err_rings:
7389 i40e_vsi_free_q_vectors(vsi);
7390err_msix:
7391 if (vsi->netdev_registered) {
7392 vsi->netdev_registered = false;
7393 unregister_netdev(vsi->netdev);
7394 free_netdev(vsi->netdev);
7395 vsi->netdev = NULL;
7396 }
7397err_netdev:
7398 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7399err_vsi:
7400 i40e_vsi_clear(vsi);
7401err_alloc:
7402 return NULL;
7403}
7404
7405/**
7406 * i40e_veb_get_bw_info - Query VEB BW information
7407 * @veb: the veb to query
7408 *
7409 * Query the Tx scheduler BW configuration data for given VEB
7410 **/
7411static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7412{
7413 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7414 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7415 struct i40e_pf *pf = veb->pf;
7416 struct i40e_hw *hw = &pf->hw;
7417 u32 tc_bw_max;
7418 int ret = 0;
7419 int i;
7420
7421 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7422 &bw_data, NULL);
7423 if (ret) {
7424 dev_info(&pf->pdev->dev,
7425 "query veb bw config failed, aq_err=%d\n",
7426 hw->aq.asq_last_status);
7427 goto out;
7428 }
7429
7430 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7431 &ets_data, NULL);
7432 if (ret) {
7433 dev_info(&pf->pdev->dev,
7434 "query veb bw ets config failed, aq_err=%d\n",
7435 hw->aq.asq_last_status);
7436 goto out;
7437 }
7438
7439 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7440 veb->bw_max_quanta = ets_data.tc_bw_max;
7441 veb->is_abs_credits = bw_data.absolute_credits_enable;
7442 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7443 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7444 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7445 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7446 veb->bw_tc_limit_credits[i] =
7447 le16_to_cpu(bw_data.tc_bw_limits[i]);
7448 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7449 }
7450
7451out:
7452 return ret;
7453}
7454
7455/**
7456 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7457 * @pf: board private structure
7458 *
7459 * On error: returns error code (negative)
7460 * On success: returns vsi index in PF (positive)
7461 **/
7462static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7463{
7464 int ret = -ENOENT;
7465 struct i40e_veb *veb;
7466 int i;
7467
7468 /* Need to protect the allocation of switch elements at the PF level */
7469 mutex_lock(&pf->switch_mutex);
7470
7471 /* VEB list may be fragmented if VEB creation/destruction has
7472 * been happening. We can afford to do a quick scan to look
7473 * for any free slots in the list.
7474 *
7475 * find next empty veb slot, looping back around if necessary
7476 */
7477 i = 0;
7478 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7479 i++;
7480 if (i >= I40E_MAX_VEB) {
7481 ret = -ENOMEM;
7482 goto err_alloc_veb; /* out of VEB slots! */
7483 }
7484
7485 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7486 if (!veb) {
7487 ret = -ENOMEM;
7488 goto err_alloc_veb;
7489 }
7490 veb->pf = pf;
7491 veb->idx = i;
7492 veb->enabled_tc = 1;
7493
7494 pf->veb[i] = veb;
7495 ret = i;
7496err_alloc_veb:
7497 mutex_unlock(&pf->switch_mutex);
7498 return ret;
7499}
7500
7501/**
7502 * i40e_switch_branch_release - Delete a branch of the switch tree
7503 * @branch: where to start deleting
7504 *
7505 * This uses recursion to find the tips of the branch to be
7506 * removed, deleting until we get back to and can delete this VEB.
7507 **/
7508static void i40e_switch_branch_release(struct i40e_veb *branch)
7509{
7510 struct i40e_pf *pf = branch->pf;
7511 u16 branch_seid = branch->seid;
7512 u16 veb_idx = branch->idx;
7513 int i;
7514
7515 /* release any VEBs on this VEB - RECURSION */
7516 for (i = 0; i < I40E_MAX_VEB; i++) {
7517 if (!pf->veb[i])
7518 continue;
7519 if (pf->veb[i]->uplink_seid == branch->seid)
7520 i40e_switch_branch_release(pf->veb[i]);
7521 }
7522
7523 /* Release the VSIs on this VEB, but not the owner VSI.
7524 *
7525 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7526 * the VEB itself, so don't use (*branch) after this loop.
7527 */
7528 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7529 if (!pf->vsi[i])
7530 continue;
7531 if (pf->vsi[i]->uplink_seid == branch_seid &&
7532 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7533 i40e_vsi_release(pf->vsi[i]);
7534 }
7535 }
7536
7537 /* There's one corner case where the VEB might not have been
7538 * removed, so double check it here and remove it if needed.
7539 * This case happens if the veb was created from the debugfs
7540 * commands and no VSIs were added to it.
7541 */
7542 if (pf->veb[veb_idx])
7543 i40e_veb_release(pf->veb[veb_idx]);
7544}
7545
7546/**
7547 * i40e_veb_clear - remove veb struct
7548 * @veb: the veb to remove
7549 **/
7550static void i40e_veb_clear(struct i40e_veb *veb)
7551{
7552 if (!veb)
7553 return;
7554
7555 if (veb->pf) {
7556 struct i40e_pf *pf = veb->pf;
7557
7558 mutex_lock(&pf->switch_mutex);
7559 if (pf->veb[veb->idx] == veb)
7560 pf->veb[veb->idx] = NULL;
7561 mutex_unlock(&pf->switch_mutex);
7562 }
7563
7564 kfree(veb);
7565}
7566
7567/**
7568 * i40e_veb_release - Delete a VEB and free its resources
7569 * @veb: the VEB being removed
7570 **/
7571void i40e_veb_release(struct i40e_veb *veb)
7572{
7573 struct i40e_vsi *vsi = NULL;
7574 struct i40e_pf *pf;
7575 int i, n = 0;
7576
7577 pf = veb->pf;
7578
7579 /* find the remaining VSI and check for extras */
7580 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7581 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7582 n++;
7583 vsi = pf->vsi[i];
7584 }
7585 }
7586 if (n != 1) {
7587 dev_info(&pf->pdev->dev,
7588 "can't remove VEB %d with %d VSIs left\n",
7589 veb->seid, n);
7590 return;
7591 }
7592
7593 /* move the remaining VSI to uplink veb */
7594 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7595 if (veb->uplink_seid) {
7596 vsi->uplink_seid = veb->uplink_seid;
7597 if (veb->uplink_seid == pf->mac_seid)
7598 vsi->veb_idx = I40E_NO_VEB;
7599 else
7600 vsi->veb_idx = veb->veb_idx;
7601 } else {
7602 /* floating VEB */
7603 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7604 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7605 }
7606
7607 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7608 i40e_veb_clear(veb);
7609
7610 return;
7611}
7612
7613/**
7614 * i40e_add_veb - create the VEB in the switch
7615 * @veb: the VEB to be instantiated
7616 * @vsi: the controlling VSI
7617 **/
7618static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7619{
56747264 7620 bool is_default = false;
e1c51b95 7621 bool is_cloud = false;
41c445ff
JB		 7622 int ret;
7623
7624 /* get a VEB from the hardware */
7625 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7626 veb->enabled_tc, is_default,
7627 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7628 if (ret) {
7629 dev_info(&veb->pf->pdev->dev,
7630 "couldn't add VEB, err %d, aq_err %d\n",
7631 ret, veb->pf->hw.aq.asq_last_status);
7632 return -EPERM;
7633 }
7634
7635 /* get statistics counter */
7636 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7637 &veb->stats_idx, NULL, NULL, NULL);
7638 if (ret) {
7639 dev_info(&veb->pf->pdev->dev,
7640 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7641 ret, veb->pf->hw.aq.asq_last_status);
7642 return -EPERM;
7643 }
7644 ret = i40e_veb_get_bw_info(veb);
7645 if (ret) {
7646 dev_info(&veb->pf->pdev->dev,
7647 "couldn't get VEB bw info, err %d, aq_err %d\n",
7648 ret, veb->pf->hw.aq.asq_last_status);
7649 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7650 return -ENOENT;
7651 }
7652
7653 vsi->uplink_seid = veb->seid;
7654 vsi->veb_idx = veb->idx;
7655 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7656
7657 return 0;
7658}
7659
7660/**
7661 * i40e_veb_setup - Set up a VEB
7662 * @pf: board private structure
7663 * @flags: VEB setup flags
7664 * @uplink_seid: the switch element to link to
7665 * @vsi_seid: the initial VSI seid
7666 * @enabled_tc: Enabled TC bit-map
7667 *
7668 * This allocates the sw VEB structure and links it into the switch
7669 * It is possible and legal for this to be a duplicate of an already
7670 * existing VEB. It is also possible for both uplink and vsi seids
7671 * to be zero, in order to create a floating VEB.
7672 *
7673 * Returns pointer to the successfully allocated VEB sw struct on
7674 * success, otherwise returns NULL on failure.
7675 **/
7676struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7677 u16 uplink_seid, u16 vsi_seid,
7678 u8 enabled_tc)
7679{
7680 struct i40e_veb *veb, *uplink_veb = NULL;
7681 int vsi_idx, veb_idx;
7682 int ret;
7683
7684 /* if one seid is 0, the other must be 0 to create a floating relay */
7685 if ((uplink_seid == 0 || vsi_seid == 0) &&
7686 (uplink_seid + vsi_seid != 0)) {
7687 dev_info(&pf->pdev->dev,
7688 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7689 uplink_seid, vsi_seid);
7690 return NULL;
7691 }
7692
7693 /* make sure there is such a vsi and uplink */
7694 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7695 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7696 break;
7697 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7698 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7699 vsi_seid);
7700 return NULL;
7701 }
7702
7703 if (uplink_seid && uplink_seid != pf->mac_seid) {
7704 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7705 if (pf->veb[veb_idx] &&
7706 pf->veb[veb_idx]->seid == uplink_seid) {
7707 uplink_veb = pf->veb[veb_idx];
7708 break;
7709 }
7710 }
7711 if (!uplink_veb) {
7712 dev_info(&pf->pdev->dev,
7713 "uplink seid %d not found\n", uplink_seid);
7714 return NULL;
7715 }
7716 }
7717
7718 /* get veb sw struct */
7719 veb_idx = i40e_veb_mem_alloc(pf);
7720 if (veb_idx < 0)
7721 goto err_alloc;
7722 veb = pf->veb[veb_idx];
7723 veb->flags = flags;
7724 veb->uplink_seid = uplink_seid;
7725 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7726 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7727
7728 /* create the VEB in the switch */
7729 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7730 if (ret)
7731 goto err_veb;
7732
7733 return veb;
7734
7735err_veb:
7736 i40e_veb_clear(veb);
7737err_alloc:
7738 return NULL;
7739}
7740
7741/**
7742 * i40e_setup_pf_switch_element - set pf vars based on switch type
7743 * @pf: board private structure
7744 * @ele: element we are building info from
7745 * @num_reported: total number of elements
7746 * @printconfig: should we print the contents
7747 *
7748 * helper function to assist in extracting a few useful SEID values.
7749 **/
7750static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7751 struct i40e_aqc_switch_config_element_resp *ele,
7752 u16 num_reported, bool printconfig)
7753{
7754 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7755 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7756 u8 element_type = ele->element_type;
7757 u16 seid = le16_to_cpu(ele->seid);
7758
7759 if (printconfig)
7760 dev_info(&pf->pdev->dev,
7761 "type=%d seid=%d uplink=%d downlink=%d\n",
7762 element_type, seid, uplink_seid, downlink_seid);
7763
7764 switch (element_type) {
7765 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7766 pf->mac_seid = seid;
7767 break;
7768 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7769 /* Main VEB? */
7770 if (uplink_seid != pf->mac_seid)
7771 break;
7772 if (pf->lan_veb == I40E_NO_VEB) {
7773 int v;
7774
7775 /* find existing or else empty VEB */
7776 for (v = 0; v < I40E_MAX_VEB; v++) {
7777 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7778 pf->lan_veb = v;
7779 break;
7780 }
7781 }
7782 if (pf->lan_veb == I40E_NO_VEB) {
7783 v = i40e_veb_mem_alloc(pf);
7784 if (v < 0)
7785 break;
7786 pf->lan_veb = v;
7787 }
7788 }
7789
7790 pf->veb[pf->lan_veb]->seid = seid;
7791 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7792 pf->veb[pf->lan_veb]->pf = pf;
7793 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7794 break;
7795 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7796 if (num_reported != 1)
7797 break;
7798 /* This is immediately after a reset so we can assume this is
7799 * the PF's VSI
7800 */
7801 pf->mac_seid = uplink_seid;
7802 pf->pf_seid = downlink_seid;
7803 pf->main_vsi_seid = seid;
7804 if (printconfig)
7805 dev_info(&pf->pdev->dev,
7806 "pf_seid=%d main_vsi_seid=%d\n",
7807 pf->pf_seid, pf->main_vsi_seid);
7808 break;
7809 case I40E_SWITCH_ELEMENT_TYPE_PF:
7810 case I40E_SWITCH_ELEMENT_TYPE_VF:
7811 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7812 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7813 case I40E_SWITCH_ELEMENT_TYPE_PE:
7814 case I40E_SWITCH_ELEMENT_TYPE_PA:
7815 /* ignore these for now */
7816 break;
7817 default:
7818 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7819 element_type, seid);
7820 break;
7821 }
7822}
7823
7824/**
7825 * i40e_fetch_switch_configuration - Get switch config from firmware
7826 * @pf: board private structure
7827 * @printconfig: should we print the contents
7828 *
7829 * Get the current switch configuration from the device and
7830 * extract a few useful SEID values.
7831 **/
7832int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7833{
7834 struct i40e_aqc_get_switch_config_resp *sw_config;
7835 u16 next_seid = 0;
7836 int ret = 0;
7837 u8 *aq_buf;
7838 int i;
7839
7840 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7841 if (!aq_buf)
7842 return -ENOMEM;
7843
7844 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7845 do {
7846 u16 num_reported, num_total;
7847
7848 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7849 I40E_AQ_LARGE_BUF,
7850 &next_seid, NULL);
7851 if (ret) {
7852 dev_info(&pf->pdev->dev,
7853 "get switch config failed %d aq_err=%x\n",
7854 ret, pf->hw.aq.asq_last_status);
7855 kfree(aq_buf);
7856 return -ENOENT;
7857 }
7858
7859 num_reported = le16_to_cpu(sw_config->header.num_reported);
7860 num_total = le16_to_cpu(sw_config->header.num_total);
7861
7862 if (printconfig)
7863 dev_info(&pf->pdev->dev,
7864 "header: %d reported %d total\n",
7865 num_reported, num_total);
7866
7867 if (num_reported) {
7868 int sz = sizeof(*sw_config) * num_reported;
7869
7870 kfree(pf->sw_config);
7871 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7872 if (pf->sw_config)
7873 memcpy(pf->sw_config, sw_config, sz);
7874 }
7875
7876 for (i = 0; i < num_reported; i++) {
7877 struct i40e_aqc_switch_config_element_resp *ele =
7878 &sw_config->element[i];
7879
7880 i40e_setup_pf_switch_element(pf, ele, num_reported,
7881 printconfig);
7882 }
7883 } while (next_seid != 0);
7884
7885 kfree(aq_buf);
7886 return ret;
7887}
7888
7889/**
7890 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7891 * @pf: board private structure
bc7d338f 7892 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7893 *
7894 * Returns 0 on success, negative value on failure
7895 **/
bc7d338f 7896static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7897{
895106a5 7898 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7899 int ret;
7900
7901 /* find out what's out there already */
7902 ret = i40e_fetch_switch_configuration(pf, false);
7903 if (ret) {
7904 dev_info(&pf->pdev->dev,
7905 "couldn't fetch switch config, err %d, aq_err %d\n",
7906 ret, pf->hw.aq.asq_last_status);
7907 return ret;
7908 }
7909 i40e_pf_reset_stats(pf);
7910
41c445ff 7911 /* first time setup */
bc7d338f 7912 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7913 struct i40e_vsi *vsi = NULL;
7914 u16 uplink_seid;
7915
7916 /* Set up the PF VSI associated with the PF's main VSI
7917 * that is already in the HW switch
7918 */
7919 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7920 uplink_seid = pf->veb[pf->lan_veb]->seid;
7921 else
7922 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7923 if (pf->lan_vsi == I40E_NO_VSI)
7924 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7925 else if (reinit)
7926 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7927 if (!vsi) {
7928 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7929 i40e_fdir_teardown(pf);
7930 return -EAGAIN;
7931 }
41c445ff
JB		 7932 } else {
7933 /* force a reset of TC and queue layout configurations */
7934 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7935 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7936 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7937 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7938 }
7939 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7940
cbf61325
ASJ		 7941 i40e_fdir_sb_setup(pf);
7942
41c445ff
JB		 7943 /* Setup static PF queue filter control settings */
7944 ret = i40e_setup_pf_filter_control(pf);
7945 if (ret) {
7946 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7947 ret);
7948 /* Failure here should not stop continuing other steps */
7949 }
7950
7951 /* enable RSS in the HW, even for only one queue, as the stack can use
7952 * the hash
7953 */
7954 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7955 i40e_config_rss(pf);
7956
7957 /* fill in link information and enable LSE reporting */
7958 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7959 i40e_link_event(pf);
7960
d52c20b7 7961 /* Initialize user-specific link properties */
41c445ff
JB		 7962 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7963 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7964 /* requested_mode is set in probe or by ethtool */
7965 if (!pf->fc_autoneg_status)
7966 goto no_autoneg;
7967
7968 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7969 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7970 pf->hw.fc.current_mode = I40E_FC_FULL;
7971 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7972 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7973 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7974 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7975 else
d52c20b7
JB		 7976 pf->hw.fc.current_mode = I40E_FC_NONE;
7977
7978 /* sync the flow control settings with the auto-neg values */
7979 switch (pf->hw.fc.current_mode) {
7980 case I40E_FC_FULL:
7981 txfc = 1;
7982 rxfc = 1;
7983 break;
7984 case I40E_FC_TX_PAUSE:
7985 txfc = 1;
7986 rxfc = 0;
7987 break;
7988 case I40E_FC_RX_PAUSE:
7989 txfc = 0;
7990 rxfc = 1;
7991 break;
7992 case I40E_FC_NONE:
7993 case I40E_FC_DEFAULT:
7994 txfc = 0;
7995 rxfc = 0;
7996 break;
7997 case I40E_FC_PFC:
7998 /* TBD */
7999 break;
8000 /* no default case, we have to handle all possibilities here */
8001 }
8002
8003 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8004
8005 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8006 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8007 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8008
8009 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8010
d52c20b7
JB		 8011 goto fc_complete;
8012
8013no_autoneg:
8014 /* disable L2 flow control, user can turn it on if they wish */
8015 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8016 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8017 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8018
8019fc_complete:
beb0dff1
JK		 8020 i40e_ptp_init(pf);
8021
41c445ff
JB		 8022 return ret;
8023}
8024
41c445ff
JB		 8025/**
8026 * i40e_determine_queue_usage - Work out queue distribution
8027 * @pf: board private structure
8028 **/
8029static void i40e_determine_queue_usage(struct i40e_pf *pf)
8030{
41c445ff
JB		 8031 int queues_left;
8032
8033 pf->num_lan_qps = 0;
41c445ff
JB		 8034
8035 /* Find the max queues to be put into basic use. We'll always be
8036 * using TC0, whether or not DCB is running, and TC0 will get the
8037 * big RSS set.
8038 */
8039 queues_left = pf->hw.func_caps.num_tx_qp;
8040
cbf61325
ASJ		 8041 if ((queues_left == 1) ||
8042 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
8043 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
8044 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 8045 /* one qp for PF, no queues for anything else */
8046 queues_left = 0;
8047 pf->rss_size = pf->num_lan_qps = 1;
8048
8049 /* make sure all the fancies are disabled */
60ea5f83
JB		 8050 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8051 I40E_FLAG_FD_SB_ENABLED |
8052 I40E_FLAG_FD_ATR_ENABLED |
8053 I40E_FLAG_DCB_ENABLED |
8054 I40E_FLAG_SRIOV_ENABLED |
8055 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8056 } else {
cbf61325
ASJ		 8057 /* Not enough queues for all TCs */
8058 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
8059 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
8060 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8061 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8062 }
8063 pf->num_lan_qps = pf->rss_size_max;
8064 queues_left -= pf->num_lan_qps;
8065 }
8066
8067 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8068 if (queues_left > 1) {
8069 queues_left -= 1; /* save 1 queue for FD */
8070 } else {
8071 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8072 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8073 }
41c445ff
JB		 8074 }
8075
8076 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8077 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8078 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8079 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8080 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8081 }
8082
8083 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8084 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8085 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8086 (queues_left / pf->num_vmdq_qps));
8087 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8088 }
8089
f8ff1464 8090 pf->queues_left = queues_left;
41c445ff
JB		 8091 return;
8092}
8093
8094/**
8095 * i40e_setup_pf_filter_control - Setup PF static filter control
8096 * @pf: PF to be setup
8097 *
8098 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8099 * settings. If PE/FCoE are enabled then it will also set the per PF
8100 * based filter sizes required for them. It also enables Flow director,
8101 * ethertype and macvlan type filter settings for the pf.
8102 *
8103 * Returns 0 on success, negative on failure
8104 **/
8105static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8106{
8107 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8108
8109 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8110
8111 /* Flow Director is enabled */
60ea5f83 8112 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8113 settings->enable_fdir = true;
8114
8115 /* Ethtype and MACVLAN filters enabled for PF */
8116 settings->enable_ethtype = true;
8117 settings->enable_macvlan = true;
8118
8119 if (i40e_set_filter_control(&pf->hw, settings))
8120 return -ENOENT;
8121
8122 return 0;
8123}
8124
0c22b3dd
JB		 8125#define INFO_STRING_LEN 255
8126static void i40e_print_features(struct i40e_pf *pf)
8127{
8128 struct i40e_hw *hw = &pf->hw;
8129 char *buf, *string;
8130
8131 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8132 if (!string) {
8133 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8134 return;
8135 }
8136
8137 buf = string;
8138
8139 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8140#ifdef CONFIG_PCI_IOV
8141 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8142#endif
8143 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8144 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8145
8146 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8147 buf += sprintf(buf, "RSS ");
8148 buf += sprintf(buf, "FDir ");
8149 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
8150 buf += sprintf(buf, "ATR ");
8151 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
8152 buf += sprintf(buf, "NTUPLE ");
8153 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8154 buf += sprintf(buf, "DCB ");
8155 if (pf->flags & I40E_FLAG_PTP)
8156 buf += sprintf(buf, "PTP ");
8157
8158 BUG_ON(buf > (string + INFO_STRING_LEN));
8159 dev_info(&pf->pdev->dev, "%s\n", string);
8160 kfree(string);
8161}
8162
41c445ff
JB		 8163/**
8164 * i40e_probe - Device initialization routine
8165 * @pdev: PCI device information struct
8166 * @ent: entry in i40e_pci_tbl
8167 *
8168 * i40e_probe initializes a pf identified by a pci_dev structure.
8169 * The OS initialization, configuring of the pf private structure,
8170 * and a hardware reset occur.
8171 *
8172 * Returns 0 on success, negative on failure
8173 **/
8174static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8175{
8176 struct i40e_driver_version dv;
8177 struct i40e_pf *pf;
8178 struct i40e_hw *hw;
93cd765b 8179 static u16 pfs_found;
d4dfb81a 8180 u16 link_status;
41c445ff
JB		 8181 int err = 0;
8182 u32 len;
8183
8184 err = pci_enable_device_mem(pdev);
8185 if (err)
8186 return err;
8187
8188 /* set up for high or low dma */
6494294f 8189 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8190 if (err) {
e3e3bfdd
JS		 8191 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8192 if (err) {
8193 dev_err(&pdev->dev,
8194 "DMA configuration failed: 0x%x\n", err);
8195 goto err_dma;
8196 }
41c445ff
JB		 8197 }
8198
8199 /* set up pci connections */
8200 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8201 IORESOURCE_MEM), i40e_driver_name);
8202 if (err) {
8203 dev_info(&pdev->dev,
8204 "pci_request_selected_regions failed %d\n", err);
8205 goto err_pci_reg;
8206 }
8207
8208 pci_enable_pcie_error_reporting(pdev);
8209 pci_set_master(pdev);
8210
8211 /* Now that we have a PCI connection, we need to do the
8212 * low level device setup. This is primarily setting up
8213 * the Admin Queue structures and then querying for the
8214 * device's current profile information.
8215 */
8216 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8217 if (!pf) {
8218 err = -ENOMEM;
8219 goto err_pf_alloc;
8220 }
8221 pf->next_vsi = 0;
8222 pf->pdev = pdev;
8223 set_bit(__I40E_DOWN, &pf->state);
8224
8225 hw = &pf->hw;
8226 hw->back = pf;
8227 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8228 pci_resource_len(pdev, 0));
8229 if (!hw->hw_addr) {
8230 err = -EIO;
8231 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8232 (unsigned int)pci_resource_start(pdev, 0),
8233 (unsigned int)pci_resource_len(pdev, 0), err);
8234 goto err_ioremap;
8235 }
8236 hw->vendor_id = pdev->vendor;
8237 hw->device_id = pdev->device;
8238 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8239 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8240 hw->subsystem_device_id = pdev->subsystem_device;
8241 hw->bus.device = PCI_SLOT(pdev->devfn);
8242 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8243 pf->instance = pfs_found;
41c445ff 8244
7134f9ce
JB		 8245 /* do a special CORER for clearing PXE mode once at init */
8246 if (hw->revision_id == 0 &&
8247 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8248 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8249 i40e_flush(hw);
8250 msleep(200);
8251 pf->corer_count++;
8252
8253 i40e_clear_pxe_mode(hw);
8254 }
8255
41c445ff
JB		 8256 /* Reset here to make sure all is clean and to define PF 'n' */
8257 err = i40e_pf_reset(hw);
8258 if (err) {
8259 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8260 goto err_pf_reset;
8261 }
8262 pf->pfr_count++;
8263
8264 hw->aq.num_arq_entries = I40E_AQ_LEN;
8265 hw->aq.num_asq_entries = I40E_AQ_LEN;
8266 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8267 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8268 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8269 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8270 "%s-pf%d:misc",
8271 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8272
8273 err = i40e_init_shared_code(hw);
8274 if (err) {
8275 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8276 goto err_pf_reset;
8277 }
8278
d52c20b7
JB		 8279 /* set up a default setting for link flow control */
8280 pf->hw.fc.requested_mode = I40E_FC_NONE;
8281
41c445ff
JB		 8282 err = i40e_init_adminq(hw);
8283 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8284 if (err) {
8285 dev_info(&pdev->dev,
8286 "init_adminq failed: %d expecting API %02x.%02x\n",
8287 err,
8288 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8289 goto err_pf_reset;
8290 }
8291
4eb3f768
SN		 8292 i40e_verify_eeprom(pf);
8293
6ff4ef86 8294 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8295 err = i40e_get_capabilities(pf);
8296 if (err)
8297 goto err_adminq_setup;
8298
8299 err = i40e_sw_init(pf);
8300 if (err) {
8301 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8302 goto err_sw_init;
8303 }
8304
8305 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8306 hw->func_caps.num_rx_qp,
8307 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8308 if (err) {
8309 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8310 goto err_init_lan_hmc;
8311 }
8312
8313 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8314 if (err) {
8315 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8316 err = -ENOENT;
8317 goto err_configure_lan_hmc;
8318 }
8319
8320 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8321 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8322 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8323 err = -EIO;
8324 goto err_mac_addr;
8325 }
8326 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8327 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8328
8329 pci_set_drvdata(pdev, pf);
8330 pci_save_state(pdev);
4e3b35b0
NP		 8331#ifdef CONFIG_I40E_DCB
8332 err = i40e_init_pf_dcb(pf);
8333 if (err) {
8334 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8335 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8336 goto err_init_dcb;
8337 }
8338#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8339
8340 /* set up periodic task facility */
8341 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8342 pf->service_timer_period = HZ;
8343
8344 INIT_WORK(&pf->service_task, i40e_service_task);
8345 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8346 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8347 pf->link_check_timeout = jiffies;
8348
8e2773ae
SN		 8349 /* WoL defaults to disabled */
8350 pf->wol_en = false;
8351 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8352
41c445ff
JB		 8353 /* set up the main switch operations */
8354 i40e_determine_queue_usage(pf);
8355 i40e_init_interrupt_scheme(pf);
8356
8357 /* Set up the *vsi struct based on the number of VSIs in the HW,
8358 * and set up our local tracking of the MAIN PF vsi.
8359 */
8360 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8361 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8362 if (!pf->vsi) {
8363 err = -ENOMEM;
41c445ff 8364 goto err_switch_setup;
ed87ac09 8365 }
41c445ff 8366
bc7d338f 8367 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8368 if (err) {
8369 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8370 goto err_vsis;
8371 }
8372
8373 /* The main driver is (mostly) up and happy. We need to set this state
8374 * before setting up the misc vector or we get a race and the vector
8375 * ends up disabled forever.
8376 */
8377 clear_bit(__I40E_DOWN, &pf->state);
8378
8379 /* In case of MSIX we are going to setup the misc vector right here
8380 * to handle admin queue events etc. In case of legacy and MSI
8381 * the misc functionality and queue processing is combined in
8382 * the same vector and that gets setup at open.
8383 */
8384 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8385 err = i40e_setup_misc_vector(pf);
8386 if (err) {
8387 dev_info(&pdev->dev,
8388 "setup of misc vector failed: %d\n", err);
8389 goto err_vsis;
8390 }
8391 }
8392
8393 /* prep for VF support */
8394 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8395 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8396 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8397 u32 val;
8398
8399 /* disable link interrupts for VFs */
8400 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8401 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8402 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8403 i40e_flush(hw);
4aeec010
MW		 8404
8405 if (pci_num_vf(pdev)) {
8406 dev_info(&pdev->dev,
8407 "Active VFs found, allocating resources.\n");
8408 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8409 if (err)
8410 dev_info(&pdev->dev,
8411 "Error %d allocating resources for existing VFs\n",
8412 err);
8413 }
41c445ff
JB		 8414 }
8415
93cd765b
ASJ		 8416 pfs_found++;
8417
41c445ff
JB		 8418 i40e_dbg_pf_init(pf);
8419
8420 /* tell the firmware that we're starting */
8421 dv.major_version = DRV_VERSION_MAJOR;
8422 dv.minor_version = DRV_VERSION_MINOR;
8423 dv.build_version = DRV_VERSION_BUILD;
8424 dv.subbuild_version = 0;
8425 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
8426
8427 /* since everything's happy, start the service_task timer */
8428 mod_timer(&pf->service_timer,
8429 round_jiffies(jiffies + pf->service_timer_period));
8430
d4dfb81a
CS		 8431 /* Get the negotiated link width and speed from PCI config space */
8432 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8433
8434 i40e_set_pci_config_data(hw, link_status);
8435
69bfb110 8436 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8437 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8438 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8439 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8440 "Unknown"),
8441 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8442 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8443 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8444 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8445 "Unknown"));
8446
8447 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8448 hw->bus.speed < i40e_bus_speed_8000) {
8449 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8450 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8451 }
8452
0c22b3dd
JB		 8453 /* print a string summarizing features */
8454 i40e_print_features(pf);
8455
41c445ff
JB		 8456 return 0;
8457
8458 /* Unwind what we've done if something failed in the setup */
8459err_vsis:
8460 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8461 i40e_clear_interrupt_scheme(pf);
8462 kfree(pf->vsi);
04b03013
SN		 8463err_switch_setup:
8464 i40e_reset_interrupt_capability(pf);
41c445ff 8465 del_timer_sync(&pf->service_timer);
4e3b35b0
NP		 8466#ifdef CONFIG_I40E_DCB
8467err_init_dcb:
8468#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8469err_mac_addr:
8470err_configure_lan_hmc:
8471 (void)i40e_shutdown_lan_hmc(hw);
8472err_init_lan_hmc:
8473 kfree(pf->qp_pile);
8474 kfree(pf->irq_pile);
8475err_sw_init:
8476err_adminq_setup:
8477 (void)i40e_shutdown_adminq(hw);
8478err_pf_reset:
8479 iounmap(hw->hw_addr);
8480err_ioremap:
8481 kfree(pf);
8482err_pf_alloc:
8483 pci_disable_pcie_error_reporting(pdev);
8484 pci_release_selected_regions(pdev,
8485 pci_select_bars(pdev, IORESOURCE_MEM));
8486err_pci_reg:
8487err_dma:
8488 pci_disable_device(pdev);
8489 return err;
8490}
8491
8492/**
8493 * i40e_remove - Device removal routine
8494 * @pdev: PCI device information struct
8495 *
8496 * i40e_remove is called by the PCI subsystem to alert the driver
8497 * that is should release a PCI device. This could be caused by a
8498 * Hot-Plug event, or because the driver is going to be removed from
8499 * memory.
8500 **/
8501static void i40e_remove(struct pci_dev *pdev)
8502{
8503 struct i40e_pf *pf = pci_get_drvdata(pdev);
8504 i40e_status ret_code;
8505 u32 reg;
8506 int i;
8507
8508 i40e_dbg_pf_exit(pf);
8509
beb0dff1
JK		 8510 i40e_ptp_stop(pf);
8511
41c445ff
JB		 8512 /* no more scheduling of any task */
8513 set_bit(__I40E_DOWN, &pf->state);
8514 del_timer_sync(&pf->service_timer);
8515 cancel_work_sync(&pf->service_task);
8516
eb2d80bc
MW		 8517 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8518 i40e_free_vfs(pf);
8519 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8520 }
8521
41c445ff
JB		 8522 i40e_fdir_teardown(pf);
8523
8524 /* If there is a switch structure or any orphans, remove them.
8525 * This will leave only the PF's VSI remaining.
8526 */
8527 for (i = 0; i < I40E_MAX_VEB; i++) {
8528 if (!pf->veb[i])
8529 continue;
8530
8531 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8532 pf->veb[i]->uplink_seid == 0)
8533 i40e_switch_branch_release(pf->veb[i]);
8534 }
8535
8536 /* Now we can shutdown the PF's VSI, just before we kill
8537 * adminq and hmc.
8538 */
8539 if (pf->vsi[pf->lan_vsi])
8540 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8541
8542 i40e_stop_misc_vector(pf);
8543 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8544 synchronize_irq(pf->msix_entries[0].vector);
8545 free_irq(pf->msix_entries[0].vector, pf);
8546 }
8547
8548 /* shutdown and destroy the HMC */
8549 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8550 if (ret_code)
8551 dev_warn(&pdev->dev,
8552 "Failed to destroy the HMC resources: %d\n", ret_code);
8553
8554 /* shutdown the adminq */
41c445ff
JB		 8555 ret_code = i40e_shutdown_adminq(&pf->hw);
8556 if (ret_code)
8557 dev_warn(&pdev->dev,
8558 "Failed to destroy the Admin Queue resources: %d\n",
8559 ret_code);
8560
8561 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8562 i40e_clear_interrupt_scheme(pf);
8563 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8564 if (pf->vsi[i]) {
8565 i40e_vsi_clear_rings(pf->vsi[i]);
8566 i40e_vsi_clear(pf->vsi[i]);
8567 pf->vsi[i] = NULL;
8568 }
8569 }
8570
8571 for (i = 0; i < I40E_MAX_VEB; i++) {
8572 kfree(pf->veb[i]);
8573 pf->veb[i] = NULL;
8574 }
8575
8576 kfree(pf->qp_pile);
8577 kfree(pf->irq_pile);
8578 kfree(pf->sw_config);
8579 kfree(pf->vsi);
8580
8581 /* force a PF reset to clean anything leftover */
8582 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8583 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8584 i40e_flush(&pf->hw);
8585
8586 iounmap(pf->hw.hw_addr);
8587 kfree(pf);
8588 pci_release_selected_regions(pdev,
8589 pci_select_bars(pdev, IORESOURCE_MEM));
8590
8591 pci_disable_pcie_error_reporting(pdev);
8592 pci_disable_device(pdev);
8593}
8594
8595/**
8596 * i40e_pci_error_detected - warning that something funky happened in PCI land
8597 * @pdev: PCI device information struct
8598 *
8599 * Called to warn that something happened and the error handling steps
8600 * are in progress. Allows the driver to quiesce things, be ready for
8601 * remediation.
8602 **/
8603static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8604 enum pci_channel_state error)
8605{
8606 struct i40e_pf *pf = pci_get_drvdata(pdev);
8607
8608 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8609
8610 /* shutdown all operations */
9007bccd
SN		 8611 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8612 rtnl_lock();
8613 i40e_prep_for_reset(pf);
8614 rtnl_unlock();
8615 }
41c445ff
JB		 8616
8617 /* Request a slot reset */
8618 return PCI_ERS_RESULT_NEED_RESET;
8619}
8620
8621/**
8622 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8623 * @pdev: PCI device information struct
8624 *
8625 * Called to find if the driver can work with the device now that
8626 * the pci slot has been reset. If a basic connection seems good
8627 * (registers are readable and have sane content) then return a
8628 * happy little PCI_ERS_RESULT_xxx.
8629 **/
8630static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8631{
8632 struct i40e_pf *pf = pci_get_drvdata(pdev);
8633 pci_ers_result_t result;
8634 int err;
8635 u32 reg;
8636
8637 dev_info(&pdev->dev, "%s\n", __func__);
8638 if (pci_enable_device_mem(pdev)) {
8639 dev_info(&pdev->dev,
8640 "Cannot re-enable PCI device after reset.\n");
8641 result = PCI_ERS_RESULT_DISCONNECT;
8642 } else {
8643 pci_set_master(pdev);
8644 pci_restore_state(pdev);
8645 pci_save_state(pdev);
8646 pci_wake_from_d3(pdev, false);
8647
8648 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8649 if (reg == 0)
8650 result = PCI_ERS_RESULT_RECOVERED;
8651 else
8652 result = PCI_ERS_RESULT_DISCONNECT;
8653 }
8654
8655 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8656 if (err) {
8657 dev_info(&pdev->dev,
8658 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8659 err);
8660 /* non-fatal, continue */
8661 }
8662
8663 return result;
8664}
8665
8666/**
8667 * i40e_pci_error_resume - restart operations after PCI error recovery
8668 * @pdev: PCI device information struct
8669 *
8670 * Called to allow the driver to bring things back up after PCI error
8671 * and/or reset recovery has finished.
8672 **/
8673static void i40e_pci_error_resume(struct pci_dev *pdev)
8674{
8675 struct i40e_pf *pf = pci_get_drvdata(pdev);
8676
8677 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8678 if (test_bit(__I40E_SUSPENDED, &pf->state))
8679 return;
8680
8681 rtnl_lock();
41c445ff 8682 i40e_handle_reset_warning(pf);
9007bccd
SN		 8683 rtnl_lock();
8684}
8685
8686/**
8687 * i40e_shutdown - PCI callback for shutting down
8688 * @pdev: PCI device information struct
8689 **/
8690static void i40e_shutdown(struct pci_dev *pdev)
8691{
8692 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8693 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8694
8695 set_bit(__I40E_SUSPENDED, &pf->state);
8696 set_bit(__I40E_DOWN, &pf->state);
8697 rtnl_lock();
8698 i40e_prep_for_reset(pf);
8699 rtnl_unlock();
8700
8e2773ae
SN		 8701 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8702 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8703
9007bccd 8704 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8705 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8706 pci_set_power_state(pdev, PCI_D3hot);
8707 }
8708}
8709
8710#ifdef CONFIG_PM
8711/**
8712 * i40e_suspend - PCI callback for moving to D3
8713 * @pdev: PCI device information struct
8714 **/
8715static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8716{
8717 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8718 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8719
8720 set_bit(__I40E_SUSPENDED, &pf->state);
8721 set_bit(__I40E_DOWN, &pf->state);
8722 rtnl_lock();
8723 i40e_prep_for_reset(pf);
8724 rtnl_unlock();
8725
8e2773ae
SN		 8726 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8727 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8728
8729 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8730 pci_set_power_state(pdev, PCI_D3hot);
8731
8732 return 0;
41c445ff
JB		 8733}
8734
9007bccd
SN		 8735/**
8736 * i40e_resume - PCI callback for waking up from D3
8737 * @pdev: PCI device information struct
8738 **/
8739static int i40e_resume(struct pci_dev *pdev)
8740{
8741 struct i40e_pf *pf = pci_get_drvdata(pdev);
8742 u32 err;
8743
8744 pci_set_power_state(pdev, PCI_D0);
8745 pci_restore_state(pdev);
8746 /* pci_restore_state() clears dev->state_saves, so
8747 * call pci_save_state() again to restore it.
8748 */
8749 pci_save_state(pdev);
8750
8751 err = pci_enable_device_mem(pdev);
8752 if (err) {
8753 dev_err(&pdev->dev,
8754 "%s: Cannot enable PCI device from suspend\n",
8755 __func__);
8756 return err;
8757 }
8758 pci_set_master(pdev);
8759
8760 /* no wakeup events while running */
8761 pci_wake_from_d3(pdev, false);
8762
8763 /* handling the reset will rebuild the device state */
8764 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8765 clear_bit(__I40E_DOWN, &pf->state);
8766 rtnl_lock();
8767 i40e_reset_and_rebuild(pf, false);
8768 rtnl_unlock();
8769 }
8770
8771 return 0;
8772}
8773
8774#endif
41c445ff
JB		 8775static const struct pci_error_handlers i40e_err_handler = {
8776 .error_detected = i40e_pci_error_detected,
8777 .slot_reset = i40e_pci_error_slot_reset,
8778 .resume = i40e_pci_error_resume,
8779};
8780
8781static struct pci_driver i40e_driver = {
8782 .name = i40e_driver_name,
8783 .id_table = i40e_pci_tbl,
8784 .probe = i40e_probe,
8785 .remove = i40e_remove,
9007bccd
SN		 8786#ifdef CONFIG_PM
8787 .suspend = i40e_suspend,
8788 .resume = i40e_resume,
8789#endif
8790 .shutdown = i40e_shutdown,
41c445ff
JB		 8791 .err_handler = &i40e_err_handler,
8792 .sriov_configure = i40e_pci_sriov_configure,
8793};
8794
8795/**
8796 * i40e_init_module - Driver registration routine
8797 *
8798 * i40e_init_module is the first routine called when the driver is
8799 * loaded. All it does is register with the PCI subsystem.
8800 **/
8801static int __init i40e_init_module(void)
8802{
8803 pr_info("%s: %s - version %s\n", i40e_driver_name,
8804 i40e_driver_string, i40e_driver_version_str);
8805 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8806 i40e_dbg_init();
8807 return pci_register_driver(&i40e_driver);
8808}
8809module_init(i40e_init_module);
8810
8811/**
8812 * i40e_exit_module - Driver exit cleanup routine
8813 *
8814 * i40e_exit_module is called just before the driver is removed
8815 * from memory.
8816 **/
8817static void __exit i40e_exit_module(void)
8818{
8819 pci_unregister_driver(&i40e_driver);
8820 i40e_dbg_exit();
8821}
8822module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)