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i40e: remove unnecessary delay
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
14ad3759 41#define DRV_VERSION_BUILD 31
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 46static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 57static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 58static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 59
60/* i40e_pci_tbl - PCI Device ID Table
61 *
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 68 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
273static void i40e_tx_timeout(struct net_device *netdev)
274{
275 struct i40e_netdev_priv *np = netdev_priv(netdev);
276 struct i40e_vsi *vsi = np->vsi;
277 struct i40e_pf *pf = vsi->back;
278
279 pf->tx_timeout_count++;
280
281 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
282 pf->tx_timeout_recovery_level = 0;
283 pf->tx_timeout_last_recovery = jiffies;
284 netdev_info(netdev, "tx_timeout recovery level %d\n",
285 pf->tx_timeout_recovery_level);
286
287 switch (pf->tx_timeout_recovery_level) {
288 case 0:
289 /* disable and re-enable queues for the VSI */
290 if (in_interrupt()) {
291 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
292 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
293 } else {
294 i40e_vsi_reinit_locked(vsi);
295 }
296 break;
297 case 1:
298 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
299 break;
300 case 2:
301 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
302 break;
303 case 3:
304 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
305 break;
306 default:
307 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 308 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 309 i40e_down(vsi);
310 break;
311 }
312 i40e_service_event_schedule(pf);
313 pf->tx_timeout_recovery_level++;
314}
315
316/**
317 * i40e_release_rx_desc - Store the new tail and head values
318 * @rx_ring: ring to bump
319 * @val: new head index
320 **/
321static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
322{
323 rx_ring->next_to_use = val;
324
325 /* Force memory writes to complete before letting h/w
326 * know there are new descriptors to fetch. (Only
327 * applicable for weak-ordered memory model archs,
328 * such as IA-64).
329 */
330 wmb();
331 writel(val, rx_ring->tail);
332}
333
334/**
335 * i40e_get_vsi_stats_struct - Get System Network Statistics
336 * @vsi: the VSI we care about
337 *
338 * Returns the address of the device statistics structure.
339 * The statistics are actually updated from the service task.
340 **/
341struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
342{
343 return &vsi->net_stats;
344}
345
346/**
347 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
348 * @netdev: network interface device structure
349 *
350 * Returns the address of the device statistics structure.
351 * The statistics are actually updated from the service task.
352 **/
353static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
354 struct net_device *netdev,
980e9b11 355 struct rtnl_link_stats64 *stats)
41c445ff
JB		 356{
357 struct i40e_netdev_priv *np = netdev_priv(netdev);
358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
370 struct i40e_ring *tx_ring, *rx_ring;
371 u64 bytes, packets;
372 unsigned int start;
373
374 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
375 if (!tx_ring)
376 continue;
377
378 do {
379 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
380 packets = tx_ring->stats.packets;
381 bytes = tx_ring->stats.bytes;
382 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
383
384 stats->tx_packets += packets;
385 stats->tx_bytes += bytes;
386 rx_ring = &tx_ring[1];
387
388 do {
389 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
390 packets = rx_ring->stats.packets;
391 bytes = rx_ring->stats.bytes;
392 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 393
980e9b11
AD		 394 stats->rx_packets += packets;
395 stats->rx_bytes += bytes;
396 }
397 rcu_read_unlock();
398
399 /* following stats updated by ixgbe_watchdog_task() */
400 stats->multicast = vsi_stats->multicast;
401 stats->tx_errors = vsi_stats->tx_errors;
402 stats->tx_dropped = vsi_stats->tx_dropped;
403 stats->rx_errors = vsi_stats->rx_errors;
404 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
405 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 406
980e9b11 407 return stats;
41c445ff
JB		 408}
409
410/**
411 * i40e_vsi_reset_stats - Resets all stats of the given vsi
412 * @vsi: the VSI to have its stats reset
413 **/
414void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
415{
416 struct rtnl_link_stats64 *ns;
417 int i;
418
419 if (!vsi)
420 return;
421
422 ns = i40e_get_vsi_stats_struct(vsi);
423 memset(ns, 0, sizeof(*ns));
424 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
425 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
426 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 427 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 428 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 429 memset(&vsi->rx_rings[i]->stats, 0 ,
430 sizeof(vsi->rx_rings[i]->stats));
431 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
432 sizeof(vsi->rx_rings[i]->rx_stats));
433 memset(&vsi->tx_rings[i]->stats, 0 ,
434 sizeof(vsi->tx_rings[i]->stats));
435 memset(&vsi->tx_rings[i]->tx_stats, 0,
436 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 437 }
8e9dca53 438 }
41c445ff
JB		 439 vsi->stat_offsets_loaded = false;
440}
441
442/**
443 * i40e_pf_reset_stats - Reset all of the stats for the given pf
444 * @pf: the PF to be reset
445 **/
446void i40e_pf_reset_stats(struct i40e_pf *pf)
447{
448 memset(&pf->stats, 0, sizeof(pf->stats));
449 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
450 pf->stat_offsets_loaded = false;
451}
452
453/**
454 * i40e_stat_update48 - read and update a 48 bit stat from the chip
455 * @hw: ptr to the hardware info
456 * @hireg: the high 32 bit reg to read
457 * @loreg: the low 32 bit reg to read
458 * @offset_loaded: has the initial offset been loaded yet
459 * @offset: ptr to current offset value
460 * @stat: ptr to the stat
461 *
462 * Since the device stats are not reset at PFReset, they likely will not
463 * be zeroed when the driver starts. We'll save the first values read
464 * and use them as offsets to be subtracted from the raw values in order
465 * to report stats that count from zero. In the process, we also manage
466 * the potential roll-over.
467 **/
468static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
469 bool offset_loaded, u64 *offset, u64 *stat)
470{
471 u64 new_data;
472
ab60085e 473 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 474 new_data = rd32(hw, loreg);
475 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
476 } else {
477 new_data = rd64(hw, loreg);
478 }
479 if (!offset_loaded)
480 *offset = new_data;
481 if (likely(new_data >= *offset))
482 *stat = new_data - *offset;
483 else
484 *stat = (new_data + ((u64)1 << 48)) - *offset;
485 *stat &= 0xFFFFFFFFFFFFULL;
486}
487
488/**
489 * i40e_stat_update32 - read and update a 32 bit stat from the chip
490 * @hw: ptr to the hardware info
491 * @reg: the hw reg to read
492 * @offset_loaded: has the initial offset been loaded yet
493 * @offset: ptr to current offset value
494 * @stat: ptr to the stat
495 **/
496static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
497 bool offset_loaded, u64 *offset, u64 *stat)
498{
499 u32 new_data;
500
501 new_data = rd32(hw, reg);
502 if (!offset_loaded)
503 *offset = new_data;
504 if (likely(new_data >= *offset))
505 *stat = (u32)(new_data - *offset);
506 else
507 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
508}
509
510/**
511 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
512 * @vsi: the VSI to be updated
513 **/
514void i40e_update_eth_stats(struct i40e_vsi *vsi)
515{
516 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
517 struct i40e_pf *pf = vsi->back;
518 struct i40e_hw *hw = &pf->hw;
519 struct i40e_eth_stats *oes;
520 struct i40e_eth_stats *es; /* device's eth stats */
521
522 es = &vsi->eth_stats;
523 oes = &vsi->eth_stats_offsets;
524
525 /* Gather up the stats that the hw collects */
526 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
527 vsi->stat_offsets_loaded,
528 &oes->tx_errors, &es->tx_errors);
529 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
530 vsi->stat_offsets_loaded,
531 &oes->rx_discards, &es->rx_discards);
532
533 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
534 I40E_GLV_GORCL(stat_idx),
535 vsi->stat_offsets_loaded,
536 &oes->rx_bytes, &es->rx_bytes);
537 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
538 I40E_GLV_UPRCL(stat_idx),
539 vsi->stat_offsets_loaded,
540 &oes->rx_unicast, &es->rx_unicast);
541 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
542 I40E_GLV_MPRCL(stat_idx),
543 vsi->stat_offsets_loaded,
544 &oes->rx_multicast, &es->rx_multicast);
545 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
546 I40E_GLV_BPRCL(stat_idx),
547 vsi->stat_offsets_loaded,
548 &oes->rx_broadcast, &es->rx_broadcast);
549
550 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
551 I40E_GLV_GOTCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->tx_bytes, &es->tx_bytes);
554 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
555 I40E_GLV_UPTCL(stat_idx),
556 vsi->stat_offsets_loaded,
557 &oes->tx_unicast, &es->tx_unicast);
558 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
559 I40E_GLV_MPTCL(stat_idx),
560 vsi->stat_offsets_loaded,
561 &oes->tx_multicast, &es->tx_multicast);
562 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
563 I40E_GLV_BPTCL(stat_idx),
564 vsi->stat_offsets_loaded,
565 &oes->tx_broadcast, &es->tx_broadcast);
566 vsi->stat_offsets_loaded = true;
567}
568
569/**
570 * i40e_update_veb_stats - Update Switch component statistics
571 * @veb: the VEB being updated
572 **/
573static void i40e_update_veb_stats(struct i40e_veb *veb)
574{
575 struct i40e_pf *pf = veb->pf;
576 struct i40e_hw *hw = &pf->hw;
577 struct i40e_eth_stats *oes;
578 struct i40e_eth_stats *es; /* device's eth stats */
579 int idx = 0;
580
581 idx = veb->stats_idx;
582 es = &veb->stats;
583 oes = &veb->stats_offsets;
584
585 /* Gather up the stats that the hw collects */
586 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
587 veb->stat_offsets_loaded,
588 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 589 if (hw->revision_id > 0)
590 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
591 veb->stat_offsets_loaded,
592 &oes->rx_unknown_protocol,
593 &es->rx_unknown_protocol);
41c445ff
JB		 594 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
595 veb->stat_offsets_loaded,
596 &oes->rx_bytes, &es->rx_bytes);
597 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
598 veb->stat_offsets_loaded,
599 &oes->rx_unicast, &es->rx_unicast);
600 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
601 veb->stat_offsets_loaded,
602 &oes->rx_multicast, &es->rx_multicast);
603 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
604 veb->stat_offsets_loaded,
605 &oes->rx_broadcast, &es->rx_broadcast);
606
607 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
608 veb->stat_offsets_loaded,
609 &oes->tx_bytes, &es->tx_bytes);
610 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
611 veb->stat_offsets_loaded,
612 &oes->tx_unicast, &es->tx_unicast);
613 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
614 veb->stat_offsets_loaded,
615 &oes->tx_multicast, &es->tx_multicast);
616 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
617 veb->stat_offsets_loaded,
618 &oes->tx_broadcast, &es->tx_broadcast);
619 veb->stat_offsets_loaded = true;
620}
621
622/**
623 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
624 * @pf: the corresponding PF
625 *
626 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
627 **/
628static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
629{
630 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
631 struct i40e_hw_port_stats *nsd = &pf->stats;
632 struct i40e_hw *hw = &pf->hw;
633 u64 xoff = 0;
634 u16 i, v;
635
636 if ((hw->fc.current_mode != I40E_FC_FULL) &&
637 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
638 return;
639
640 xoff = nsd->link_xoff_rx;
641 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
642 pf->stat_offsets_loaded,
643 &osd->link_xoff_rx, &nsd->link_xoff_rx);
644
645 /* No new LFC xoff rx */
646 if (!(nsd->link_xoff_rx - xoff))
647 return;
648
649 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
650 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
651 struct i40e_vsi *vsi = pf->vsi[v];
652
653 if (!vsi)
654 continue;
655
656 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 657 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 658 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
659 }
660 }
661}
662
663/**
664 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
665 * @pf: the corresponding PF
666 *
667 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
668 **/
669static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
670{
671 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
672 struct i40e_hw_port_stats *nsd = &pf->stats;
673 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
674 struct i40e_dcbx_config *dcb_cfg;
675 struct i40e_hw *hw = &pf->hw;
676 u16 i, v;
677 u8 tc;
678
679 dcb_cfg = &hw->local_dcbx_config;
680
681 /* See if DCB enabled with PFC TC */
682 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
683 !(dcb_cfg->pfc.pfcenable)) {
684 i40e_update_link_xoff_rx(pf);
685 return;
686 }
687
688 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
689 u64 prio_xoff = nsd->priority_xoff_rx[i];
690 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
691 pf->stat_offsets_loaded,
692 &osd->priority_xoff_rx[i],
693 &nsd->priority_xoff_rx[i]);
694
695 /* No new PFC xoff rx */
696 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
697 continue;
698 /* Get the TC for given priority */
699 tc = dcb_cfg->etscfg.prioritytable[i];
700 xoff[tc] = true;
701 }
702
703 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
704 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
705 struct i40e_vsi *vsi = pf->vsi[v];
706
707 if (!vsi)
708 continue;
709
710 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 711 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 712
713 tc = ring->dcb_tc;
714 if (xoff[tc])
715 clear_bit(__I40E_HANG_CHECK_ARMED,
716 &ring->state);
717 }
718 }
719}
720
721/**
722 * i40e_update_stats - Update the board statistics counters.
723 * @vsi: the VSI to be updated
724 *
725 * There are a few instances where we store the same stat in a
726 * couple of different structs. This is partly because we have
727 * the netdev stats that need to be filled out, which is slightly
728 * different from the "eth_stats" defined by the chip and used in
729 * VF communications. We sort it all out here in a central place.
730 **/
731void i40e_update_stats(struct i40e_vsi *vsi)
732{
733 struct i40e_pf *pf = vsi->back;
734 struct i40e_hw *hw = &pf->hw;
735 struct rtnl_link_stats64 *ons;
736 struct rtnl_link_stats64 *ns; /* netdev stats */
737 struct i40e_eth_stats *oes;
738 struct i40e_eth_stats *es; /* device's eth stats */
739 u32 tx_restart, tx_busy;
740 u32 rx_page, rx_buf;
741 u64 rx_p, rx_b;
742 u64 tx_p, tx_b;
743 int i;
744 u16 q;
745
746 if (test_bit(__I40E_DOWN, &vsi->state) ||
747 test_bit(__I40E_CONFIG_BUSY, &pf->state))
748 return;
749
750 ns = i40e_get_vsi_stats_struct(vsi);
751 ons = &vsi->net_stats_offsets;
752 es = &vsi->eth_stats;
753 oes = &vsi->eth_stats_offsets;
754
755 /* Gather up the netdev and vsi stats that the driver collects
756 * on the fly during packet processing
757 */
758 rx_b = rx_p = 0;
759 tx_b = tx_p = 0;
760 tx_restart = tx_busy = 0;
761 rx_page = 0;
762 rx_buf = 0;
980e9b11 763 rcu_read_lock();
41c445ff
JB		 764 for (q = 0; q < vsi->num_queue_pairs; q++) {
765 struct i40e_ring *p;
980e9b11
AD		 766 u64 bytes, packets;
767 unsigned int start;
768
769 /* locate Tx ring */
770 p = ACCESS_ONCE(vsi->tx_rings[q]);
771
772 do {
773 start = u64_stats_fetch_begin_bh(&p->syncp);
774 packets = p->stats.packets;
775 bytes = p->stats.bytes;
776 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
777 tx_b += bytes;
778 tx_p += packets;
779 tx_restart += p->tx_stats.restart_queue;
780 tx_busy += p->tx_stats.tx_busy;
41c445ff 781
980e9b11
AD		 782 /* Rx queue is part of the same block as Tx queue */
783 p = &p[1];
784 do {
785 start = u64_stats_fetch_begin_bh(&p->syncp);
786 packets = p->stats.packets;
787 bytes = p->stats.bytes;
788 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
789 rx_b += bytes;
790 rx_p += packets;
420136cc
MW		 791 rx_buf += p->rx_stats.alloc_buff_failed;
792 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 793 }
980e9b11 794 rcu_read_unlock();
41c445ff
JB		 795 vsi->tx_restart = tx_restart;
796 vsi->tx_busy = tx_busy;
797 vsi->rx_page_failed = rx_page;
798 vsi->rx_buf_failed = rx_buf;
799
800 ns->rx_packets = rx_p;
801 ns->rx_bytes = rx_b;
802 ns->tx_packets = tx_p;
803 ns->tx_bytes = tx_b;
804
805 i40e_update_eth_stats(vsi);
806 /* update netdev stats from eth stats */
807 ons->rx_errors = oes->rx_errors;
808 ns->rx_errors = es->rx_errors;
809 ons->tx_errors = oes->tx_errors;
810 ns->tx_errors = es->tx_errors;
811 ons->multicast = oes->rx_multicast;
812 ns->multicast = es->rx_multicast;
813 ons->tx_dropped = oes->tx_discards;
814 ns->tx_dropped = es->tx_discards;
815
816 /* Get the port data only if this is the main PF VSI */
817 if (vsi == pf->vsi[pf->lan_vsi]) {
818 struct i40e_hw_port_stats *nsd = &pf->stats;
819 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
820
821 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
822 I40E_GLPRT_GORCL(hw->port),
823 pf->stat_offsets_loaded,
824 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
825 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
826 I40E_GLPRT_GOTCL(hw->port),
827 pf->stat_offsets_loaded,
828 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
829 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
830 pf->stat_offsets_loaded,
831 &osd->eth.rx_discards,
832 &nsd->eth.rx_discards);
833 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
834 pf->stat_offsets_loaded,
835 &osd->eth.tx_discards,
836 &nsd->eth.tx_discards);
837 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
838 I40E_GLPRT_MPRCL(hw->port),
839 pf->stat_offsets_loaded,
840 &osd->eth.rx_multicast,
841 &nsd->eth.rx_multicast);
842
843 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
844 pf->stat_offsets_loaded,
845 &osd->tx_dropped_link_down,
846 &nsd->tx_dropped_link_down);
847
848 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
849 pf->stat_offsets_loaded,
850 &osd->crc_errors, &nsd->crc_errors);
851 ns->rx_crc_errors = nsd->crc_errors;
852
853 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
854 pf->stat_offsets_loaded,
855 &osd->illegal_bytes, &nsd->illegal_bytes);
856 ns->rx_errors = nsd->crc_errors
857 + nsd->illegal_bytes;
858
859 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
860 pf->stat_offsets_loaded,
861 &osd->mac_local_faults,
862 &nsd->mac_local_faults);
863 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
864 pf->stat_offsets_loaded,
865 &osd->mac_remote_faults,
866 &nsd->mac_remote_faults);
867
868 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
869 pf->stat_offsets_loaded,
870 &osd->rx_length_errors,
871 &nsd->rx_length_errors);
872 ns->rx_length_errors = nsd->rx_length_errors;
873
874 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
875 pf->stat_offsets_loaded,
876 &osd->link_xon_rx, &nsd->link_xon_rx);
877 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
878 pf->stat_offsets_loaded,
879 &osd->link_xon_tx, &nsd->link_xon_tx);
880 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
881 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
882 pf->stat_offsets_loaded,
883 &osd->link_xoff_tx, &nsd->link_xoff_tx);
884
885 for (i = 0; i < 8; i++) {
886 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
887 pf->stat_offsets_loaded,
888 &osd->priority_xon_rx[i],
889 &nsd->priority_xon_rx[i]);
890 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
891 pf->stat_offsets_loaded,
892 &osd->priority_xon_tx[i],
893 &nsd->priority_xon_tx[i]);
894 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
895 pf->stat_offsets_loaded,
896 &osd->priority_xoff_tx[i],
897 &nsd->priority_xoff_tx[i]);
898 i40e_stat_update32(hw,
899 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
900 pf->stat_offsets_loaded,
901 &osd->priority_xon_2_xoff[i],
902 &nsd->priority_xon_2_xoff[i]);
903 }
904
905 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
906 I40E_GLPRT_PRC64L(hw->port),
907 pf->stat_offsets_loaded,
908 &osd->rx_size_64, &nsd->rx_size_64);
909 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
910 I40E_GLPRT_PRC127L(hw->port),
911 pf->stat_offsets_loaded,
912 &osd->rx_size_127, &nsd->rx_size_127);
913 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
914 I40E_GLPRT_PRC255L(hw->port),
915 pf->stat_offsets_loaded,
916 &osd->rx_size_255, &nsd->rx_size_255);
917 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
918 I40E_GLPRT_PRC511L(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->rx_size_511, &nsd->rx_size_511);
921 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
922 I40E_GLPRT_PRC1023L(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->rx_size_1023, &nsd->rx_size_1023);
925 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
926 I40E_GLPRT_PRC1522L(hw->port),
927 pf->stat_offsets_loaded,
928 &osd->rx_size_1522, &nsd->rx_size_1522);
929 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
930 I40E_GLPRT_PRC9522L(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->rx_size_big, &nsd->rx_size_big);
933
934 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
935 I40E_GLPRT_PTC64L(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->tx_size_64, &nsd->tx_size_64);
938 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
939 I40E_GLPRT_PTC127L(hw->port),
940 pf->stat_offsets_loaded,
941 &osd->tx_size_127, &nsd->tx_size_127);
942 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
943 I40E_GLPRT_PTC255L(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->tx_size_255, &nsd->tx_size_255);
946 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
947 I40E_GLPRT_PTC511L(hw->port),
948 pf->stat_offsets_loaded,
949 &osd->tx_size_511, &nsd->tx_size_511);
950 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
951 I40E_GLPRT_PTC1023L(hw->port),
952 pf->stat_offsets_loaded,
953 &osd->tx_size_1023, &nsd->tx_size_1023);
954 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
955 I40E_GLPRT_PTC1522L(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->tx_size_1522, &nsd->tx_size_1522);
958 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
959 I40E_GLPRT_PTC9522L(hw->port),
960 pf->stat_offsets_loaded,
961 &osd->tx_size_big, &nsd->tx_size_big);
962
963 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->rx_undersize, &nsd->rx_undersize);
966 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_fragments, &nsd->rx_fragments);
969 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
970 pf->stat_offsets_loaded,
971 &osd->rx_oversize, &nsd->rx_oversize);
972 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
973 pf->stat_offsets_loaded,
974 &osd->rx_jabber, &nsd->rx_jabber);
975 }
976
977 pf->stat_offsets_loaded = true;
978}
979
980/**
981 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
982 * @vsi: the VSI to be searched
983 * @macaddr: the MAC address
984 * @vlan: the vlan
985 * @is_vf: make sure its a vf filter, else doesn't matter
986 * @is_netdev: make sure its a netdev filter, else doesn't matter
987 *
988 * Returns ptr to the filter object or NULL
989 **/
990static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
991 u8 *macaddr, s16 vlan,
992 bool is_vf, bool is_netdev)
993{
994 struct i40e_mac_filter *f;
995
996 if (!vsi || !macaddr)
997 return NULL;
998
999 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1000 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1001 (vlan == f->vlan) &&
1002 (!is_vf || f->is_vf) &&
1003 (!is_netdev || f->is_netdev))
1004 return f;
1005 }
1006 return NULL;
1007}
1008
1009/**
1010 * i40e_find_mac - Find a mac addr in the macvlan filters list
1011 * @vsi: the VSI to be searched
1012 * @macaddr: the MAC address we are searching for
1013 * @is_vf: make sure its a vf filter, else doesn't matter
1014 * @is_netdev: make sure its a netdev filter, else doesn't matter
1015 *
1016 * Returns the first filter with the provided MAC address or NULL if
1017 * MAC address was not found
1018 **/
1019struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1020 bool is_vf, bool is_netdev)
1021{
1022 struct i40e_mac_filter *f;
1023
1024 if (!vsi || !macaddr)
1025 return NULL;
1026
1027 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1028 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1029 (!is_vf || f->is_vf) &&
1030 (!is_netdev || f->is_netdev))
1031 return f;
1032 }
1033 return NULL;
1034}
1035
1036/**
1037 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1038 * @vsi: the VSI to be searched
1039 *
1040 * Returns true if VSI is in vlan mode or false otherwise
1041 **/
1042bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1043{
1044 struct i40e_mac_filter *f;
1045
1046 /* Only -1 for all the filters denotes not in vlan mode
1047 * so we have to go through all the list in order to make sure
1048 */
1049 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1050 if (f->vlan >= 0)
1051 return true;
1052 }
1053
1054 return false;
1055}
1056
1057/**
1058 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1059 * @vsi: the VSI to be searched
1060 * @macaddr: the mac address to be filtered
1061 * @is_vf: true if it is a vf
1062 * @is_netdev: true if it is a netdev
1063 *
1064 * Goes through all the macvlan filters and adds a
1065 * macvlan filter for each unique vlan that already exists
1066 *
1067 * Returns first filter found on success, else NULL
1068 **/
1069struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1070 bool is_vf, bool is_netdev)
1071{
1072 struct i40e_mac_filter *f;
1073
1074 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1075 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev)) {
1077 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1078 is_vf, is_netdev))
41c445ff
JB		 1079 return NULL;
1080 }
1081 }
1082
1083 return list_first_entry_or_null(&vsi->mac_filter_list,
1084 struct i40e_mac_filter, list);
1085}
1086
1087/**
1088 * i40e_add_filter - Add a mac/vlan filter to the VSI
1089 * @vsi: the VSI to be searched
1090 * @macaddr: the MAC address
1091 * @vlan: the vlan
1092 * @is_vf: make sure its a vf filter, else doesn't matter
1093 * @is_netdev: make sure its a netdev filter, else doesn't matter
1094 *
1095 * Returns ptr to the filter object or NULL when no memory available.
1096 **/
1097struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1098 u8 *macaddr, s16 vlan,
1099 bool is_vf, bool is_netdev)
1100{
1101 struct i40e_mac_filter *f;
1102
1103 if (!vsi || !macaddr)
1104 return NULL;
1105
1106 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1107 if (!f) {
1108 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1109 if (!f)
1110 goto add_filter_out;
1111
1112 memcpy(f->macaddr, macaddr, ETH_ALEN);
1113 f->vlan = vlan;
1114 f->changed = true;
1115
1116 INIT_LIST_HEAD(&f->list);
1117 list_add(&f->list, &vsi->mac_filter_list);
1118 }
1119
1120 /* increment counter and add a new flag if needed */
1121 if (is_vf) {
1122 if (!f->is_vf) {
1123 f->is_vf = true;
1124 f->counter++;
1125 }
1126 } else if (is_netdev) {
1127 if (!f->is_netdev) {
1128 f->is_netdev = true;
1129 f->counter++;
1130 }
1131 } else {
1132 f->counter++;
1133 }
1134
1135 /* changed tells sync_filters_subtask to
1136 * push the filter down to the firmware
1137 */
1138 if (f->changed) {
1139 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1140 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1141 }
1142
1143add_filter_out:
1144 return f;
1145}
1146
1147/**
1148 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1149 * @vsi: the VSI to be searched
1150 * @macaddr: the MAC address
1151 * @vlan: the vlan
1152 * @is_vf: make sure it's a vf filter, else doesn't matter
1153 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1154 **/
1155void i40e_del_filter(struct i40e_vsi *vsi,
1156 u8 *macaddr, s16 vlan,
1157 bool is_vf, bool is_netdev)
1158{
1159 struct i40e_mac_filter *f;
1160
1161 if (!vsi || !macaddr)
1162 return;
1163
1164 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1165 if (!f || f->counter == 0)
1166 return;
1167
1168 if (is_vf) {
1169 if (f->is_vf) {
1170 f->is_vf = false;
1171 f->counter--;
1172 }
1173 } else if (is_netdev) {
1174 if (f->is_netdev) {
1175 f->is_netdev = false;
1176 f->counter--;
1177 }
1178 } else {
1179 /* make sure we don't remove a filter in use by vf or netdev */
1180 int min_f = 0;
1181 min_f += (f->is_vf ? 1 : 0);
1182 min_f += (f->is_netdev ? 1 : 0);
1183
1184 if (f->counter > min_f)
1185 f->counter--;
1186 }
1187
1188 /* counter == 0 tells sync_filters_subtask to
1189 * remove the filter from the firmware's list
1190 */
1191 if (f->counter == 0) {
1192 f->changed = true;
1193 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1194 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1195 }
1196}
1197
1198/**
1199 * i40e_set_mac - NDO callback to set mac address
1200 * @netdev: network interface device structure
1201 * @p: pointer to an address structure
1202 *
1203 * Returns 0 on success, negative on failure
1204 **/
1205static int i40e_set_mac(struct net_device *netdev, void *p)
1206{
1207 struct i40e_netdev_priv *np = netdev_priv(netdev);
1208 struct i40e_vsi *vsi = np->vsi;
1209 struct sockaddr *addr = p;
1210 struct i40e_mac_filter *f;
1211
1212 if (!is_valid_ether_addr(addr->sa_data))
1213 return -EADDRNOTAVAIL;
1214
1215 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1216
1217 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1218 return 0;
1219
80f6428f
ASJ		 1220 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1221 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1222 return -EADDRNOTAVAIL;
1223
41c445ff
JB		 1224 if (vsi->type == I40E_VSI_MAIN) {
1225 i40e_status ret;
1226 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1227 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1228 addr->sa_data, NULL);
1229 if (ret) {
1230 netdev_info(netdev,
1231 "Addr change for Main VSI failed: %d\n",
1232 ret);
1233 return -EADDRNOTAVAIL;
1234 }
1235
1236 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1237 }
1238
1239 /* In order to be sure to not drop any packets, add the new address
1240 * then delete the old one.
1241 */
1242 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1243 if (!f)
1244 return -ENOMEM;
1245
1246 i40e_sync_vsi_filters(vsi);
1247 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1248 i40e_sync_vsi_filters(vsi);
1249
1250 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1251
1252 return 0;
1253}
1254
1255/**
1256 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1257 * @vsi: the VSI being setup
1258 * @ctxt: VSI context structure
1259 * @enabled_tc: Enabled TCs bitmap
1260 * @is_add: True if called before Add VSI
1261 *
1262 * Setup VSI queue mapping for enabled traffic classes.
1263 **/
1264static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1265 struct i40e_vsi_context *ctxt,
1266 u8 enabled_tc,
1267 bool is_add)
1268{
1269 struct i40e_pf *pf = vsi->back;
1270 u16 sections = 0;
1271 u8 netdev_tc = 0;
1272 u16 numtc = 0;
1273 u16 qcount;
1274 u8 offset;
1275 u16 qmap;
1276 int i;
4e3b35b0 1277 u16 num_tc_qps = 0;
41c445ff
JB		 1278
1279 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1280 offset = 0;
1281
1282 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1283 /* Find numtc from enabled TC bitmap */
1284 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1285 if (enabled_tc & (1 << i)) /* TC is enabled */
1286 numtc++;
1287 }
1288 if (!numtc) {
1289 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1290 numtc = 1;
1291 }
1292 } else {
1293 /* At least TC0 is enabled in case of non-DCB case */
1294 numtc = 1;
1295 }
1296
1297 vsi->tc_config.numtc = numtc;
1298 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1299 /* Number of queues per enabled TC */
1300 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1301 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1302
1303 /* Setup queue offset/count for all TCs for given VSI */
1304 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1305 /* See if the given TC is enabled for the given VSI */
1306 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1307 int pow, num_qps;
1308
41c445ff
JB		 1309 switch (vsi->type) {
1310 case I40E_VSI_MAIN:
4e3b35b0 1311 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1312 break;
1313 case I40E_VSI_FDIR:
1314 case I40E_VSI_SRIOV:
1315 case I40E_VSI_VMDQ2:
1316 default:
4e3b35b0 1317 qcount = num_tc_qps;
41c445ff
JB		 1318 WARN_ON(i != 0);
1319 break;
1320 }
4e3b35b0
NP		 1321 vsi->tc_config.tc_info[i].qoffset = offset;
1322 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1323
1324 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1325 num_qps = qcount;
41c445ff 1326 pow = 0;
4e3b35b0 1327 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1328 pow++;
1329 num_qps >>= 1;
1330 }
1331
1332 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1333 qmap =
1334 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1335 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1336
4e3b35b0 1337 offset += qcount;
41c445ff
JB		 1338 } else {
1339 /* TC is not enabled so set the offset to
1340 * default queue and allocate one queue
1341 * for the given TC.
1342 */
1343 vsi->tc_config.tc_info[i].qoffset = 0;
1344 vsi->tc_config.tc_info[i].qcount = 1;
1345 vsi->tc_config.tc_info[i].netdev_tc = 0;
1346
1347 qmap = 0;
1348 }
1349 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1350 }
1351
1352 /* Set actual Tx/Rx queue pairs */
1353 vsi->num_queue_pairs = offset;
1354
1355 /* Scheduler section valid can only be set for ADD VSI */
1356 if (is_add) {
1357 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1358
1359 ctxt->info.up_enable_bits = enabled_tc;
1360 }
1361 if (vsi->type == I40E_VSI_SRIOV) {
1362 ctxt->info.mapping_flags |=
1363 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1364 for (i = 0; i < vsi->num_queue_pairs; i++)
1365 ctxt->info.queue_mapping[i] =
1366 cpu_to_le16(vsi->base_queue + i);
1367 } else {
1368 ctxt->info.mapping_flags |=
1369 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1370 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1371 }
1372 ctxt->info.valid_sections |= cpu_to_le16(sections);
1373}
1374
1375/**
1376 * i40e_set_rx_mode - NDO callback to set the netdev filters
1377 * @netdev: network interface device structure
1378 **/
1379static void i40e_set_rx_mode(struct net_device *netdev)
1380{
1381 struct i40e_netdev_priv *np = netdev_priv(netdev);
1382 struct i40e_mac_filter *f, *ftmp;
1383 struct i40e_vsi *vsi = np->vsi;
1384 struct netdev_hw_addr *uca;
1385 struct netdev_hw_addr *mca;
1386 struct netdev_hw_addr *ha;
1387
1388 /* add addr if not already in the filter list */
1389 netdev_for_each_uc_addr(uca, netdev) {
1390 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1391 if (i40e_is_vsi_in_vlan(vsi))
1392 i40e_put_mac_in_vlan(vsi, uca->addr,
1393 false, true);
1394 else
1395 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1396 false, true);
1397 }
1398 }
1399
1400 netdev_for_each_mc_addr(mca, netdev) {
1401 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1402 if (i40e_is_vsi_in_vlan(vsi))
1403 i40e_put_mac_in_vlan(vsi, mca->addr,
1404 false, true);
1405 else
1406 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1407 false, true);
1408 }
1409 }
1410
1411 /* remove filter if not in netdev list */
1412 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1413 bool found = false;
1414
1415 if (!f->is_netdev)
1416 continue;
1417
1418 if (is_multicast_ether_addr(f->macaddr)) {
1419 netdev_for_each_mc_addr(mca, netdev) {
1420 if (ether_addr_equal(mca->addr, f->macaddr)) {
1421 found = true;
1422 break;
1423 }
1424 }
1425 } else {
1426 netdev_for_each_uc_addr(uca, netdev) {
1427 if (ether_addr_equal(uca->addr, f->macaddr)) {
1428 found = true;
1429 break;
1430 }
1431 }
1432
1433 for_each_dev_addr(netdev, ha) {
1434 if (ether_addr_equal(ha->addr, f->macaddr)) {
1435 found = true;
1436 break;
1437 }
1438 }
1439 }
1440 if (!found)
1441 i40e_del_filter(
1442 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1443 }
1444
1445 /* check for other flag changes */
1446 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1447 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1448 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1449 }
1450}
1451
1452/**
1453 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1454 * @vsi: ptr to the VSI
1455 *
1456 * Push any outstanding VSI filter changes through the AdminQ.
1457 *
1458 * Returns 0 or error value
1459 **/
1460int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1461{
1462 struct i40e_mac_filter *f, *ftmp;
1463 bool promisc_forced_on = false;
1464 bool add_happened = false;
1465 int filter_list_len = 0;
1466 u32 changed_flags = 0;
dcae29be 1467 i40e_status aq_ret = 0;
41c445ff
JB		 1468 struct i40e_pf *pf;
1469 int num_add = 0;
1470 int num_del = 0;
1471 u16 cmd_flags;
1472
1473 /* empty array typed pointers, kcalloc later */
1474 struct i40e_aqc_add_macvlan_element_data *add_list;
1475 struct i40e_aqc_remove_macvlan_element_data *del_list;
1476
1477 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1478 usleep_range(1000, 2000);
1479 pf = vsi->back;
1480
1481 if (vsi->netdev) {
1482 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1483 vsi->current_netdev_flags = vsi->netdev->flags;
1484 }
1485
1486 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1487 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1488
1489 filter_list_len = pf->hw.aq.asq_buf_size /
1490 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1491 del_list = kcalloc(filter_list_len,
1492 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1493 GFP_KERNEL);
1494 if (!del_list)
1495 return -ENOMEM;
1496
1497 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1498 if (!f->changed)
1499 continue;
1500
1501 if (f->counter != 0)
1502 continue;
1503 f->changed = false;
1504 cmd_flags = 0;
1505
1506 /* add to delete list */
1507 memcpy(del_list[num_del].mac_addr,
1508 f->macaddr, ETH_ALEN);
1509 del_list[num_del].vlan_tag =
1510 cpu_to_le16((u16)(f->vlan ==
1511 I40E_VLAN_ANY ? 0 : f->vlan));
1512
41c445ff
JB		 1513 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1514 del_list[num_del].flags = cmd_flags;
1515 num_del++;
1516
1517 /* unlink from filter list */
1518 list_del(&f->list);
1519 kfree(f);
1520
1521 /* flush a full buffer */
1522 if (num_del == filter_list_len) {
dcae29be 1523 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1524 vsi->seid, del_list, num_del,
1525 NULL);
1526 num_del = 0;
1527 memset(del_list, 0, sizeof(*del_list));
1528
dcae29be 1529 if (aq_ret)
41c445ff
JB		 1530 dev_info(&pf->pdev->dev,
1531 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1532 aq_ret,
41c445ff
JB		 1533 pf->hw.aq.asq_last_status);
1534 }
1535 }
1536 if (num_del) {
dcae29be 1537 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1538 del_list, num_del, NULL);
1539 num_del = 0;
1540
dcae29be 1541 if (aq_ret)
41c445ff
JB		 1542 dev_info(&pf->pdev->dev,
1543 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1544 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1545 }
1546
1547 kfree(del_list);
1548 del_list = NULL;
1549
1550 /* do all the adds now */
1551 filter_list_len = pf->hw.aq.asq_buf_size /
1552 sizeof(struct i40e_aqc_add_macvlan_element_data),
1553 add_list = kcalloc(filter_list_len,
1554 sizeof(struct i40e_aqc_add_macvlan_element_data),
1555 GFP_KERNEL);
1556 if (!add_list)
1557 return -ENOMEM;
1558
1559 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1560 if (!f->changed)
1561 continue;
1562
1563 if (f->counter == 0)
1564 continue;
1565 f->changed = false;
1566 add_happened = true;
1567 cmd_flags = 0;
1568
1569 /* add to add array */
1570 memcpy(add_list[num_add].mac_addr,
1571 f->macaddr, ETH_ALEN);
1572 add_list[num_add].vlan_tag =
1573 cpu_to_le16(
1574 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1575 add_list[num_add].queue_number = 0;
1576
1577 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1578 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1579 num_add++;
1580
1581 /* flush a full buffer */
1582 if (num_add == filter_list_len) {
dcae29be
JB		 1583 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1584 add_list, num_add,
1585 NULL);
41c445ff
JB		 1586 num_add = 0;
1587
dcae29be 1588 if (aq_ret)
41c445ff
JB		 1589 break;
1590 memset(add_list, 0, sizeof(*add_list));
1591 }
1592 }
1593 if (num_add) {
dcae29be
JB		 1594 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1595 add_list, num_add, NULL);
41c445ff
JB		 1596 num_add = 0;
1597 }
1598 kfree(add_list);
1599 add_list = NULL;
1600
dcae29be 1601 if (add_happened && (!aq_ret)) {
41c445ff 1602 /* do nothing */;
dcae29be 1603 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1604 dev_info(&pf->pdev->dev,
1605 "add filter failed, err %d, aq_err %d\n",
dcae29be 1606 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1607 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1608 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1609 &vsi->state)) {
1610 promisc_forced_on = true;
1611 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1612 &vsi->state);
1613 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1614 }
1615 }
1616 }
1617
1618 /* check for changes in promiscuous modes */
1619 if (changed_flags & IFF_ALLMULTI) {
1620 bool cur_multipromisc;
1621 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1622 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1623 vsi->seid,
1624 cur_multipromisc,
1625 NULL);
1626 if (aq_ret)
41c445ff
JB		 1627 dev_info(&pf->pdev->dev,
1628 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1629 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1630 }
1631 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1632 bool cur_promisc;
1633 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1634 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1635 &vsi->state));
dcae29be
JB		 1636 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1637 vsi->seid,
1638 cur_promisc, NULL);
1639 if (aq_ret)
41c445ff
JB		 1640 dev_info(&pf->pdev->dev,
1641 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1642 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1643 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1644 vsi->seid,
1645 cur_promisc, NULL);
1646 if (aq_ret)
1647 dev_info(&pf->pdev->dev,
1648 "set brdcast promisc failed, err %d, aq_err %d\n",
1649 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1650 }
1651
1652 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1653 return 0;
1654}
1655
1656/**
1657 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1658 * @pf: board private structure
1659 **/
1660static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1661{
1662 int v;
1663
1664 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1665 return;
1666 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1667
1668 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1669 if (pf->vsi[v] &&
1670 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1671 i40e_sync_vsi_filters(pf->vsi[v]);
1672 }
1673}
1674
1675/**
1676 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1677 * @netdev: network interface device structure
1678 * @new_mtu: new value for maximum frame size
1679 *
1680 * Returns 0 on success, negative on failure
1681 **/
1682static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1683{
1684 struct i40e_netdev_priv *np = netdev_priv(netdev);
1685 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1686 struct i40e_vsi *vsi = np->vsi;
1687
1688 /* MTU < 68 is an error and causes problems on some kernels */
1689 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1690 return -EINVAL;
1691
1692 netdev_info(netdev, "changing MTU from %d to %d\n",
1693 netdev->mtu, new_mtu);
1694 netdev->mtu = new_mtu;
1695 if (netif_running(netdev))
1696 i40e_vsi_reinit_locked(vsi);
1697
1698 return 0;
1699}
1700
beb0dff1
JK		 1701/**
1702 * i40e_ioctl - Access the hwtstamp interface
1703 * @netdev: network interface device structure
1704 * @ifr: interface request data
1705 * @cmd: ioctl command
1706 **/
1707int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1708{
1709 struct i40e_netdev_priv *np = netdev_priv(netdev);
1710 struct i40e_pf *pf = np->vsi->back;
1711
1712 switch (cmd) {
1713 case SIOCGHWTSTAMP:
1714 return i40e_ptp_get_ts_config(pf, ifr);
1715 case SIOCSHWTSTAMP:
1716 return i40e_ptp_set_ts_config(pf, ifr);
1717 default:
1718 return -EOPNOTSUPP;
1719 }
1720}
1721
41c445ff
JB		 1722/**
1723 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1724 * @vsi: the vsi being adjusted
1725 **/
1726void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1727{
1728 struct i40e_vsi_context ctxt;
1729 i40e_status ret;
1730
1731 if ((vsi->info.valid_sections &
1732 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1733 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1734 return; /* already enabled */
1735
1736 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1737 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1738 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1739
1740 ctxt.seid = vsi->seid;
1741 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1742 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1743 if (ret) {
1744 dev_info(&vsi->back->pdev->dev,
1745 "%s: update vsi failed, aq_err=%d\n",
1746 __func__, vsi->back->hw.aq.asq_last_status);
1747 }
1748}
1749
1750/**
1751 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1752 * @vsi: the vsi being adjusted
1753 **/
1754void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1755{
1756 struct i40e_vsi_context ctxt;
1757 i40e_status ret;
1758
1759 if ((vsi->info.valid_sections &
1760 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1761 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1762 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1763 return; /* already disabled */
1764
1765 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1766 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1767 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1768
1769 ctxt.seid = vsi->seid;
1770 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1771 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1772 if (ret) {
1773 dev_info(&vsi->back->pdev->dev,
1774 "%s: update vsi failed, aq_err=%d\n",
1775 __func__, vsi->back->hw.aq.asq_last_status);
1776 }
1777}
1778
1779/**
1780 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1781 * @netdev: network interface to be adjusted
1782 * @features: netdev features to test if VLAN offload is enabled or not
1783 **/
1784static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1785{
1786 struct i40e_netdev_priv *np = netdev_priv(netdev);
1787 struct i40e_vsi *vsi = np->vsi;
1788
1789 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1790 i40e_vlan_stripping_enable(vsi);
1791 else
1792 i40e_vlan_stripping_disable(vsi);
1793}
1794
1795/**
1796 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1797 * @vsi: the vsi being configured
1798 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1799 **/
1800int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1801{
1802 struct i40e_mac_filter *f, *add_f;
1803 bool is_netdev, is_vf;
41c445ff
JB		 1804
1805 is_vf = (vsi->type == I40E_VSI_SRIOV);
1806 is_netdev = !!(vsi->netdev);
1807
1808 if (is_netdev) {
1809 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1810 is_vf, is_netdev);
1811 if (!add_f) {
1812 dev_info(&vsi->back->pdev->dev,
1813 "Could not add vlan filter %d for %pM\n",
1814 vid, vsi->netdev->dev_addr);
1815 return -ENOMEM;
1816 }
1817 }
1818
1819 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1820 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1821 if (!add_f) {
1822 dev_info(&vsi->back->pdev->dev,
1823 "Could not add vlan filter %d for %pM\n",
1824 vid, f->macaddr);
1825 return -ENOMEM;
1826 }
1827 }
1828
41c445ff
JB		 1829 /* Now if we add a vlan tag, make sure to check if it is the first
1830 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1831 * with 0, so we now accept untagged and specified tagged traffic
1832 * (and not any taged and untagged)
1833 */
1834 if (vid > 0) {
1835 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1836 I40E_VLAN_ANY,
1837 is_vf, is_netdev)) {
1838 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1839 I40E_VLAN_ANY, is_vf, is_netdev);
1840 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1841 is_vf, is_netdev);
1842 if (!add_f) {
1843 dev_info(&vsi->back->pdev->dev,
1844 "Could not add filter 0 for %pM\n",
1845 vsi->netdev->dev_addr);
1846 return -ENOMEM;
1847 }
1848 }
8d82a7c5 1849 }
41c445ff 1850
8d82a7c5
GR		 1851 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1852 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1853 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1854 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1855 is_vf, is_netdev)) {
1856 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1857 is_vf, is_netdev);
1858 add_f = i40e_add_filter(vsi, f->macaddr,
1859 0, is_vf, is_netdev);
1860 if (!add_f) {
1861 dev_info(&vsi->back->pdev->dev,
1862 "Could not add filter 0 for %pM\n",
1863 f->macaddr);
1864 return -ENOMEM;
1865 }
1866 }
1867 }
41c445ff
JB		 1868 }
1869
80f6428f
ASJ		 1870 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1871 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1872 return 0;
1873
1874 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1875}
1876
1877/**
1878 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1879 * @vsi: the vsi being configured
1880 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1881 *
1882 * Return: 0 on success or negative otherwise
41c445ff
JB		 1883 **/
1884int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1885{
1886 struct net_device *netdev = vsi->netdev;
1887 struct i40e_mac_filter *f, *add_f;
1888 bool is_vf, is_netdev;
1889 int filter_count = 0;
41c445ff
JB		 1890
1891 is_vf = (vsi->type == I40E_VSI_SRIOV);
1892 is_netdev = !!(netdev);
1893
1894 if (is_netdev)
1895 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1896
1897 list_for_each_entry(f, &vsi->mac_filter_list, list)
1898 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1899
41c445ff
JB		 1900 /* go through all the filters for this VSI and if there is only
1901 * vid == 0 it means there are no other filters, so vid 0 must
1902 * be replaced with -1. This signifies that we should from now
1903 * on accept any traffic (with any tag present, or untagged)
1904 */
1905 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1906 if (is_netdev) {
1907 if (f->vlan &&
1908 ether_addr_equal(netdev->dev_addr, f->macaddr))
1909 filter_count++;
1910 }
1911
1912 if (f->vlan)
1913 filter_count++;
1914 }
1915
1916 if (!filter_count && is_netdev) {
1917 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1918 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1919 is_vf, is_netdev);
1920 if (!f) {
1921 dev_info(&vsi->back->pdev->dev,
1922 "Could not add filter %d for %pM\n",
1923 I40E_VLAN_ANY, netdev->dev_addr);
1924 return -ENOMEM;
1925 }
1926 }
1927
1928 if (!filter_count) {
1929 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1930 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1931 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1932 is_vf, is_netdev);
1933 if (!add_f) {
1934 dev_info(&vsi->back->pdev->dev,
1935 "Could not add filter %d for %pM\n",
1936 I40E_VLAN_ANY, f->macaddr);
1937 return -ENOMEM;
1938 }
1939 }
1940 }
1941
80f6428f
ASJ		 1942 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1943 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1944 return 0;
1945
41c445ff
JB		 1946 return i40e_sync_vsi_filters(vsi);
1947}
1948
1949/**
1950 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1951 * @netdev: network interface to be adjusted
1952 * @vid: vlan id to be added
078b5876
JB		 1953 *
1954 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1955 **/
1956static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1957 __always_unused __be16 proto, u16 vid)
1958{
1959 struct i40e_netdev_priv *np = netdev_priv(netdev);
1960 struct i40e_vsi *vsi = np->vsi;
078b5876 1961 int ret = 0;
41c445ff
JB		 1962
1963 if (vid > 4095)
078b5876
JB		 1964 return -EINVAL;
1965
1966 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1967
41c445ff
JB		 1968 /* If the network stack called us with vid = 0, we should
1969 * indicate to i40e_vsi_add_vlan() that we want to receive
1970 * any traffic (i.e. with any vlan tag, or untagged)
1971 */
1972 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1973
078b5876
JB		 1974 if (!ret && (vid < VLAN_N_VID))
1975 set_bit(vid, vsi->active_vlans);
41c445ff 1976
078b5876 1977 return ret;
41c445ff
JB		 1978}
1979
1980/**
1981 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1982 * @netdev: network interface to be adjusted
1983 * @vid: vlan id to be removed
078b5876
JB		 1984 *
1985 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1986 **/
1987static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1988 __always_unused __be16 proto, u16 vid)
1989{
1990 struct i40e_netdev_priv *np = netdev_priv(netdev);
1991 struct i40e_vsi *vsi = np->vsi;
1992
078b5876
JB		 1993 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1994
41c445ff
JB		 1995 /* return code is ignored as there is nothing a user
1996 * can do about failure to remove and a log message was
078b5876 1997 * already printed from the other function
41c445ff
JB		 1998 */
1999 i40e_vsi_kill_vlan(vsi, vid);
2000
2001 clear_bit(vid, vsi->active_vlans);
078b5876 2002
41c445ff
JB		 2003 return 0;
2004}
2005
2006/**
2007 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2008 * @vsi: the vsi being brought back up
2009 **/
2010static void i40e_restore_vlan(struct i40e_vsi *vsi)
2011{
2012 u16 vid;
2013
2014 if (!vsi->netdev)
2015 return;
2016
2017 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2018
2019 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2020 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2021 vid);
2022}
2023
2024/**
2025 * i40e_vsi_add_pvid - Add pvid for the VSI
2026 * @vsi: the vsi being adjusted
2027 * @vid: the vlan id to set as a PVID
2028 **/
dcae29be 2029int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2030{
2031 struct i40e_vsi_context ctxt;
dcae29be 2032 i40e_status aq_ret;
41c445ff
JB		 2033
2034 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2035 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2036 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2037 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2038 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2039
2040 ctxt.seid = vsi->seid;
2041 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2042 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2043 if (aq_ret) {
41c445ff
JB		 2044 dev_info(&vsi->back->pdev->dev,
2045 "%s: update vsi failed, aq_err=%d\n",
2046 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2047 return -ENOENT;
41c445ff
JB		 2048 }
2049
dcae29be 2050 return 0;
41c445ff
JB		 2051}
2052
2053/**
2054 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2055 * @vsi: the vsi being adjusted
2056 *
2057 * Just use the vlan_rx_register() service to put it back to normal
2058 **/
2059void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2060{
6c12fcbf
GR		 2061 i40e_vlan_stripping_disable(vsi);
2062
41c445ff 2063 vsi->info.pvid = 0;
41c445ff
JB		 2064}
2065
2066/**
2067 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2068 * @vsi: ptr to the VSI
2069 *
2070 * If this function returns with an error, then it's possible one or
2071 * more of the rings is populated (while the rest are not). It is the
2072 * callers duty to clean those orphaned rings.
2073 *
2074 * Return 0 on success, negative on failure
2075 **/
2076static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2077{
2078 int i, err = 0;
2079
2080 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2081 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2082
2083 return err;
2084}
2085
2086/**
2087 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2088 * @vsi: ptr to the VSI
2089 *
2090 * Free VSI's transmit software resources
2091 **/
2092static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2093{
2094 int i;
2095
8e9dca53
GR		 2096 if (!vsi->tx_rings)
2097 return;
2098
41c445ff 2099 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2100 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2101 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2102}
2103
2104/**
2105 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2106 * @vsi: ptr to the VSI
2107 *
2108 * If this function returns with an error, then it's possible one or
2109 * more of the rings is populated (while the rest are not). It is the
2110 * callers duty to clean those orphaned rings.
2111 *
2112 * Return 0 on success, negative on failure
2113 **/
2114static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2115{
2116 int i, err = 0;
2117
2118 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2119 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2120 return err;
2121}
2122
2123/**
2124 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2125 * @vsi: ptr to the VSI
2126 *
2127 * Free all receive software resources
2128 **/
2129static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2130{
2131 int i;
2132
8e9dca53
GR		 2133 if (!vsi->rx_rings)
2134 return;
2135
41c445ff 2136 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2137 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2138 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2139}
2140
2141/**
2142 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2143 * @ring: The Tx ring to configure
2144 *
2145 * Configure the Tx descriptor ring in the HMC context.
2146 **/
2147static int i40e_configure_tx_ring(struct i40e_ring *ring)
2148{
2149 struct i40e_vsi *vsi = ring->vsi;
2150 u16 pf_q = vsi->base_queue + ring->queue_index;
2151 struct i40e_hw *hw = &vsi->back->hw;
2152 struct i40e_hmc_obj_txq tx_ctx;
2153 i40e_status err = 0;
2154 u32 qtx_ctl = 0;
2155
2156 /* some ATR related tx ring init */
60ea5f83 2157 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2158 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2159 ring->atr_count = 0;
2160 } else {
2161 ring->atr_sample_rate = 0;
2162 }
2163
2164 /* initialize XPS */
2165 if (ring->q_vector && ring->netdev &&
4e3b35b0 2166 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2167 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2168 netif_set_xps_queue(ring->netdev,
2169 &ring->q_vector->affinity_mask,
2170 ring->queue_index);
2171
2172 /* clear the context structure first */
2173 memset(&tx_ctx, 0, sizeof(tx_ctx));
2174
2175 tx_ctx.new_context = 1;
2176 tx_ctx.base = (ring->dma / 128);
2177 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2178 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2179 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2180 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
41c445ff
JB		 2181
2182 /* As part of VSI creation/update, FW allocates certain
2183 * Tx arbitration queue sets for each TC enabled for
2184 * the VSI. The FW returns the handles to these queue
2185 * sets as part of the response buffer to Add VSI,
2186 * Update VSI, etc. AQ commands. It is expected that
2187 * these queue set handles be associated with the Tx
2188 * queues by the driver as part of the TX queue context
2189 * initialization. This has to be done regardless of
2190 * DCB as by default everything is mapped to TC0.
2191 */
2192 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2193 tx_ctx.rdylist_act = 0;
2194
2195 /* clear the context in the HMC */
2196 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2197 if (err) {
2198 dev_info(&vsi->back->pdev->dev,
2199 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2200 ring->queue_index, pf_q, err);
2201 return -ENOMEM;
2202 }
2203
2204 /* set the context in the HMC */
2205 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2206 if (err) {
2207 dev_info(&vsi->back->pdev->dev,
2208 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2209 ring->queue_index, pf_q, err);
2210 return -ENOMEM;
2211 }
2212
2213 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2214 if (vsi->type == I40E_VSI_VMDQ2)
2215 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2216 else
2217 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2218 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2219 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2220 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2221 i40e_flush(hw);
2222
2223 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2224
2225 /* cache tail off for easier writes later */
2226 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2227
2228 return 0;
2229}
2230
2231/**
2232 * i40e_configure_rx_ring - Configure a receive ring context
2233 * @ring: The Rx ring to configure
2234 *
2235 * Configure the Rx descriptor ring in the HMC context.
2236 **/
2237static int i40e_configure_rx_ring(struct i40e_ring *ring)
2238{
2239 struct i40e_vsi *vsi = ring->vsi;
2240 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2241 u16 pf_q = vsi->base_queue + ring->queue_index;
2242 struct i40e_hw *hw = &vsi->back->hw;
2243 struct i40e_hmc_obj_rxq rx_ctx;
2244 i40e_status err = 0;
2245
2246 ring->state = 0;
2247
2248 /* clear the context structure first */
2249 memset(&rx_ctx, 0, sizeof(rx_ctx));
2250
2251 ring->rx_buf_len = vsi->rx_buf_len;
2252 ring->rx_hdr_len = vsi->rx_hdr_len;
2253
2254 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2255 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2256
2257 rx_ctx.base = (ring->dma / 128);
2258 rx_ctx.qlen = ring->count;
2259
2260 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2261 set_ring_16byte_desc_enabled(ring);
2262 rx_ctx.dsize = 0;
2263 } else {
2264 rx_ctx.dsize = 1;
2265 }
2266
2267 rx_ctx.dtype = vsi->dtype;
2268 if (vsi->dtype) {
2269 set_ring_ps_enabled(ring);
2270 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2271 I40E_RX_SPLIT_IP |
2272 I40E_RX_SPLIT_TCP_UDP |
2273 I40E_RX_SPLIT_SCTP;
2274 } else {
2275 rx_ctx.hsplit_0 = 0;
2276 }
2277
2278 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2279 (chain_len * ring->rx_buf_len));
2280 rx_ctx.tphrdesc_ena = 1;
2281 rx_ctx.tphwdesc_ena = 1;
2282 rx_ctx.tphdata_ena = 1;
2283 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2284 if (hw->revision_id == 0)
2285 rx_ctx.lrxqthresh = 0;
2286 else
2287 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2288 rx_ctx.crcstrip = 1;
2289 rx_ctx.l2tsel = 1;
2290 rx_ctx.showiv = 1;
2291
2292 /* clear the context in the HMC */
2293 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2294 if (err) {
2295 dev_info(&vsi->back->pdev->dev,
2296 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2297 ring->queue_index, pf_q, err);
2298 return -ENOMEM;
2299 }
2300
2301 /* set the context in the HMC */
2302 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2303 if (err) {
2304 dev_info(&vsi->back->pdev->dev,
2305 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2306 ring->queue_index, pf_q, err);
2307 return -ENOMEM;
2308 }
2309
2310 /* cache tail for quicker writes, and clear the reg before use */
2311 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2312 writel(0, ring->tail);
2313
2314 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2315
2316 return 0;
2317}
2318
2319/**
2320 * i40e_vsi_configure_tx - Configure the VSI for Tx
2321 * @vsi: VSI structure describing this set of rings and resources
2322 *
2323 * Configure the Tx VSI for operation.
2324 **/
2325static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2326{
2327 int err = 0;
2328 u16 i;
2329
9f65e15b
AD		 2330 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2331 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2332
2333 return err;
2334}
2335
2336/**
2337 * i40e_vsi_configure_rx - Configure the VSI for Rx
2338 * @vsi: the VSI being configured
2339 *
2340 * Configure the Rx VSI for operation.
2341 **/
2342static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2343{
2344 int err = 0;
2345 u16 i;
2346
2347 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2348 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2349 + ETH_FCS_LEN + VLAN_HLEN;
2350 else
2351 vsi->max_frame = I40E_RXBUFFER_2048;
2352
2353 /* figure out correct receive buffer length */
2354 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2355 I40E_FLAG_RX_PS_ENABLED)) {
2356 case I40E_FLAG_RX_1BUF_ENABLED:
2357 vsi->rx_hdr_len = 0;
2358 vsi->rx_buf_len = vsi->max_frame;
2359 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2360 break;
2361 case I40E_FLAG_RX_PS_ENABLED:
2362 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2363 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2364 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2365 break;
2366 default:
2367 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2368 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2369 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2370 break;
2371 }
2372
2373 /* round up for the chip's needs */
2374 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2375 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2376 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2377 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2378
2379 /* set up individual rings */
2380 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2381 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2382
2383 return err;
2384}
2385
2386/**
2387 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2388 * @vsi: ptr to the VSI
2389 **/
2390static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2391{
2392 u16 qoffset, qcount;
2393 int i, n;
2394
2395 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2396 return;
2397
2398 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2399 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2400 continue;
2401
2402 qoffset = vsi->tc_config.tc_info[n].qoffset;
2403 qcount = vsi->tc_config.tc_info[n].qcount;
2404 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2405 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2406 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2407 rx_ring->dcb_tc = n;
2408 tx_ring->dcb_tc = n;
2409 }
2410 }
2411}
2412
2413/**
2414 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2415 * @vsi: ptr to the VSI
2416 **/
2417static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2418{
2419 if (vsi->netdev)
2420 i40e_set_rx_mode(vsi->netdev);
2421}
2422
2423/**
2424 * i40e_vsi_configure - Set up the VSI for action
2425 * @vsi: the VSI being configured
2426 **/
2427static int i40e_vsi_configure(struct i40e_vsi *vsi)
2428{
2429 int err;
2430
2431 i40e_set_vsi_rx_mode(vsi);
2432 i40e_restore_vlan(vsi);
2433 i40e_vsi_config_dcb_rings(vsi);
2434 err = i40e_vsi_configure_tx(vsi);
2435 if (!err)
2436 err = i40e_vsi_configure_rx(vsi);
2437
2438 return err;
2439}
2440
2441/**
2442 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2443 * @vsi: the VSI being configured
2444 **/
2445static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2446{
2447 struct i40e_pf *pf = vsi->back;
2448 struct i40e_q_vector *q_vector;
2449 struct i40e_hw *hw = &pf->hw;
2450 u16 vector;
2451 int i, q;
2452 u32 val;
2453 u32 qp;
2454
2455 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2456 * and PFINT_LNKLSTn registers, e.g.:
2457 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2458 */
2459 qp = vsi->base_queue;
2460 vector = vsi->base_vector;
493fb300
AD		 2461 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2462 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2463 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2464 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2465 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2466 q_vector->rx.itr);
2467 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2468 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2469 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2470 q_vector->tx.itr);
2471
2472 /* Linked list for the queuepairs assigned to this vector */
2473 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2474 for (q = 0; q < q_vector->num_ringpairs; q++) {
2475 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2476 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2477 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2478 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2479 (I40E_QUEUE_TYPE_TX
2480 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2481
2482 wr32(hw, I40E_QINT_RQCTL(qp), val);
2483
2484 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2485 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2486 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2487 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2488 (I40E_QUEUE_TYPE_RX
2489 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2490
2491 /* Terminate the linked list */
2492 if (q == (q_vector->num_ringpairs - 1))
2493 val |= (I40E_QUEUE_END_OF_LIST
2494 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2495
2496 wr32(hw, I40E_QINT_TQCTL(qp), val);
2497 qp++;
2498 }
2499 }
2500
2501 i40e_flush(hw);
2502}
2503
2504/**
2505 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2506 * @hw: ptr to the hardware info
2507 **/
2508static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2509{
2510 u32 val;
2511
2512 /* clear things first */
2513 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2514 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2515
2516 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2517 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2518 I40E_PFINT_ICR0_ENA_GRST_MASK |
2519 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2520 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2521 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2522 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2523 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2524 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2525 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2526
2527 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2528
2529 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2530 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2531 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2532
2533 /* OTHER_ITR_IDX = 0 */
2534 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2535}
2536
2537/**
2538 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2539 * @vsi: the VSI being configured
2540 **/
2541static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2542{
493fb300 2543 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2544 struct i40e_pf *pf = vsi->back;
2545 struct i40e_hw *hw = &pf->hw;
2546 u32 val;
2547
2548 /* set the ITR configuration */
2549 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2550 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2551 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2552 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2553 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2554 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2555
2556 i40e_enable_misc_int_causes(hw);
2557
2558 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2559 wr32(hw, I40E_PFINT_LNKLST0, 0);
2560
2561 /* Associate the queue pair to the vector and enable the q int */
2562 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2563 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2564 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2565
2566 wr32(hw, I40E_QINT_RQCTL(0), val);
2567
2568 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2569 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2570 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2571
2572 wr32(hw, I40E_QINT_TQCTL(0), val);
2573 i40e_flush(hw);
2574}
2575
2ef28cfb
MW		 2576/**
2577 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2578 * @pf: board private structure
2579 **/
2580void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2581{
2582 struct i40e_hw *hw = &pf->hw;
2583
2584 wr32(hw, I40E_PFINT_DYN_CTL0,
2585 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2586 i40e_flush(hw);
2587}
2588
41c445ff
JB		 2589/**
2590 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2591 * @pf: board private structure
2592 **/
116a57d4 2593void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2594{
2595 struct i40e_hw *hw = &pf->hw;
2596 u32 val;
2597
2598 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2599 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2600 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2601
2602 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2603 i40e_flush(hw);
2604}
2605
2606/**
2607 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2608 * @vsi: pointer to a vsi
2609 * @vector: enable a particular Hw Interrupt vector
2610 **/
2611void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2612{
2613 struct i40e_pf *pf = vsi->back;
2614 struct i40e_hw *hw = &pf->hw;
2615 u32 val;
2616
2617 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2618 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2619 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2620 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2621 /* skip the flush */
41c445ff
JB		 2622}
2623
2624/**
2625 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2626 * @irq: interrupt number
2627 * @data: pointer to a q_vector
2628 **/
2629static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2630{
2631 struct i40e_q_vector *q_vector = data;
2632
cd0b6fa6 2633 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2634 return IRQ_HANDLED;
2635
2636 napi_schedule(&q_vector->napi);
2637
2638 return IRQ_HANDLED;
2639}
2640
41c445ff
JB		 2641/**
2642 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2643 * @vsi: the VSI being configured
2644 * @basename: name for the vector
2645 *
2646 * Allocates MSI-X vectors and requests interrupts from the kernel.
2647 **/
2648static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2649{
2650 int q_vectors = vsi->num_q_vectors;
2651 struct i40e_pf *pf = vsi->back;
2652 int base = vsi->base_vector;
2653 int rx_int_idx = 0;
2654 int tx_int_idx = 0;
2655 int vector, err;
2656
2657 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2658 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2659
cd0b6fa6 2660 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2661 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2662 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2663 tx_int_idx++;
cd0b6fa6 2664 } else if (q_vector->rx.ring) {
41c445ff
JB		 2665 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2666 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2667 } else if (q_vector->tx.ring) {
41c445ff
JB		 2668 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2669 "%s-%s-%d", basename, "tx", tx_int_idx++);
2670 } else {
2671 /* skip this unused q_vector */
2672 continue;
2673 }
2674 err = request_irq(pf->msix_entries[base + vector].vector,
2675 vsi->irq_handler,
2676 0,
2677 q_vector->name,
2678 q_vector);
2679 if (err) {
2680 dev_info(&pf->pdev->dev,
2681 "%s: request_irq failed, error: %d\n",
2682 __func__, err);
2683 goto free_queue_irqs;
2684 }
2685 /* assign the mask for this irq */
2686 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2687 &q_vector->affinity_mask);
2688 }
2689
2690 return 0;
2691
2692free_queue_irqs:
2693 while (vector) {
2694 vector--;
2695 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2696 NULL);
2697 free_irq(pf->msix_entries[base + vector].vector,
2698 &(vsi->q_vectors[vector]));
2699 }
2700 return err;
2701}
2702
2703/**
2704 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2705 * @vsi: the VSI being un-configured
2706 **/
2707static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2708{
2709 struct i40e_pf *pf = vsi->back;
2710 struct i40e_hw *hw = &pf->hw;
2711 int base = vsi->base_vector;
2712 int i;
2713
2714 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2715 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2716 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2717 }
2718
2719 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2720 for (i = vsi->base_vector;
2721 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2722 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2723
2724 i40e_flush(hw);
2725 for (i = 0; i < vsi->num_q_vectors; i++)
2726 synchronize_irq(pf->msix_entries[i + base].vector);
2727 } else {
2728 /* Legacy and MSI mode - this stops all interrupt handling */
2729 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2730 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2731 i40e_flush(hw);
2732 synchronize_irq(pf->pdev->irq);
2733 }
2734}
2735
2736/**
2737 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2738 * @vsi: the VSI being configured
2739 **/
2740static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2741{
2742 struct i40e_pf *pf = vsi->back;
2743 int i;
2744
2745 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2746 for (i = vsi->base_vector;
2747 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2748 i40e_irq_dynamic_enable(vsi, i);
2749 } else {
2750 i40e_irq_dynamic_enable_icr0(pf);
2751 }
2752
1022cb6c 2753 i40e_flush(&pf->hw);
41c445ff
JB		 2754 return 0;
2755}
2756
2757/**
2758 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2759 * @pf: board private structure
2760 **/
2761static void i40e_stop_misc_vector(struct i40e_pf *pf)
2762{
2763 /* Disable ICR 0 */
2764 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2765 i40e_flush(&pf->hw);
2766}
2767
2768/**
2769 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2770 * @irq: interrupt number
2771 * @data: pointer to a q_vector
2772 *
2773 * This is the handler used for all MSI/Legacy interrupts, and deals
2774 * with both queue and non-queue interrupts. This is also used in
2775 * MSIX mode to handle the non-queue interrupts.
2776 **/
2777static irqreturn_t i40e_intr(int irq, void *data)
2778{
2779 struct i40e_pf *pf = (struct i40e_pf *)data;
2780 struct i40e_hw *hw = &pf->hw;
5e823066 2781 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2782 u32 icr0, icr0_remaining;
2783 u32 val, ena_mask;
2784
2785 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2786 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2787
116a57d4
SN		 2788 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2789 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2790 goto enable_intr;
41c445ff 2791
cd92e72f
SN		 2792 /* if interrupt but no bits showing, must be SWINT */
2793 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2794 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2795 pf->sw_int_count++;
2796
41c445ff
JB		 2797 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2798 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2799
2800 /* temporarily disable queue cause for NAPI processing */
2801 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2802 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2803 wr32(hw, I40E_QINT_RQCTL(0), qval);
2804
2805 qval = rd32(hw, I40E_QINT_TQCTL(0));
2806 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2807 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2808
2809 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2810 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2811 }
2812
2813 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2814 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2815 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2816 }
2817
2818 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2819 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2820 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2821 }
2822
2823 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2824 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2825 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2826 }
2827
2828 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2829 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2830 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2831 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2832 val = rd32(hw, I40E_GLGEN_RSTAT);
2833 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2834 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2835 if (val == I40E_RESET_CORER)
41c445ff 2836 pf->corer_count++;
d52cf0a9 2837 else if (val == I40E_RESET_GLOBR)
41c445ff 2838 pf->globr_count++;
d52cf0a9 2839 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2840 pf->empr_count++;
2841 }
2842
9c010ee0
ASJ		 2843 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2844 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2845 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2846 }
2847
beb0dff1
JK		 2848 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2849 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2850
2851 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2852 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2853 i40e_ptp_tx_hwtstamp(pf);
2854 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2855 }
2856
2857 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2858 }
2859
41c445ff
JB		 2860 /* If a critical error is pending we have no choice but to reset the
2861 * device.
2862 * Report and mask out any remaining unexpected interrupts.
2863 */
2864 icr0_remaining = icr0 & ena_mask;
2865 if (icr0_remaining) {
2866 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2867 icr0_remaining);
9c010ee0 2868 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2869 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2870 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2871 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2872 dev_info(&pf->pdev->dev, "device will be reset\n");
2873 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2874 i40e_service_event_schedule(pf);
41c445ff
JB		 2875 }
2876 ena_mask &= ~icr0_remaining;
2877 }
5e823066 2878 ret = IRQ_HANDLED;
41c445ff 2879
5e823066 2880enable_intr:
41c445ff
JB		 2881 /* re-enable interrupt causes */
2882 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2883 if (!test_bit(__I40E_DOWN, &pf->state)) {
2884 i40e_service_event_schedule(pf);
2885 i40e_irq_dynamic_enable_icr0(pf);
2886 }
2887
5e823066 2888 return ret;
41c445ff
JB		 2889}
2890
cbf61325
ASJ		 2891/**
2892 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2893 * @tx_ring: tx ring to clean
2894 * @budget: how many cleans we're allowed
2895 *
2896 * Returns true if there's any budget left (e.g. the clean is finished)
2897 **/
2898static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2899{
2900 struct i40e_vsi *vsi = tx_ring->vsi;
2901 u16 i = tx_ring->next_to_clean;
2902 struct i40e_tx_buffer *tx_buf;
2903 struct i40e_tx_desc *tx_desc;
2904
2905 tx_buf = &tx_ring->tx_bi[i];
2906 tx_desc = I40E_TX_DESC(tx_ring, i);
2907 i -= tx_ring->count;
2908
2909 do {
2910 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2911
2912 /* if next_to_watch is not set then there is no work pending */
2913 if (!eop_desc)
2914 break;
2915
2916 /* prevent any other reads prior to eop_desc */
2917 read_barrier_depends();
2918
2919 /* if the descriptor isn't done, no work yet to do */
2920 if (!(eop_desc->cmd_type_offset_bsz &
2921 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2922 break;
2923
2924 /* clear next_to_watch to prevent false hangs */
2925 tx_buf->next_to_watch = NULL;
2926
2927 /* unmap skb header data */
2928 dma_unmap_single(tx_ring->dev,
2929 dma_unmap_addr(tx_buf, dma),
2930 dma_unmap_len(tx_buf, len),
2931 DMA_TO_DEVICE);
2932
2933 dma_unmap_len_set(tx_buf, len, 0);
2934
2935
2936 /* move to the next desc and buffer to clean */
2937 tx_buf++;
2938 tx_desc++;
2939 i++;
2940 if (unlikely(!i)) {
2941 i -= tx_ring->count;
2942 tx_buf = tx_ring->tx_bi;
2943 tx_desc = I40E_TX_DESC(tx_ring, 0);
2944 }
2945
2946 /* update budget accounting */
2947 budget--;
2948 } while (likely(budget));
2949
2950 i += tx_ring->count;
2951 tx_ring->next_to_clean = i;
2952
2953 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
2954 i40e_irq_dynamic_enable(vsi,
2955 tx_ring->q_vector->v_idx + vsi->base_vector);
2956 }
2957 return budget > 0;
2958}
2959
2960/**
2961 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
2962 * @irq: interrupt number
2963 * @data: pointer to a q_vector
2964 **/
2965static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
2966{
2967 struct i40e_q_vector *q_vector = data;
2968 struct i40e_vsi *vsi;
2969
2970 if (!q_vector->tx.ring)
2971 return IRQ_HANDLED;
2972
2973 vsi = q_vector->tx.ring->vsi;
2974 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
2975
2976 return IRQ_HANDLED;
2977}
2978
41c445ff 2979/**
cd0b6fa6 2980 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2981 * @vsi: the VSI being configured
2982 * @v_idx: vector index
cd0b6fa6 2983 * @qp_idx: queue pair index
41c445ff 2984 **/
cd0b6fa6 2985static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2986{
493fb300 2987 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2988 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2989 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2990
2991 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2992 tx_ring->next = q_vector->tx.ring;
2993 q_vector->tx.ring = tx_ring;
41c445ff 2994 q_vector->tx.count++;
cd0b6fa6
AD		 2995
2996 rx_ring->q_vector = q_vector;
2997 rx_ring->next = q_vector->rx.ring;
2998 q_vector->rx.ring = rx_ring;
2999 q_vector->rx.count++;
41c445ff
JB		 3000}
3001
3002/**
3003 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3004 * @vsi: the VSI being configured
3005 *
3006 * This function maps descriptor rings to the queue-specific vectors
3007 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3008 * one vector per queue pair, but on a constrained vector budget, we
3009 * group the queue pairs as "efficiently" as possible.
3010 **/
3011static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3012{
3013 int qp_remaining = vsi->num_queue_pairs;
3014 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3015 int num_ringpairs;
41c445ff
JB		 3016 int v_start = 0;
3017 int qp_idx = 0;
3018
3019 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3020 * group them so there are multiple queues per vector.
3021 */
3022 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3023 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3024
3025 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3026
3027 q_vector->num_ringpairs = num_ringpairs;
3028
3029 q_vector->rx.count = 0;
3030 q_vector->tx.count = 0;
3031 q_vector->rx.ring = NULL;
3032 q_vector->tx.ring = NULL;
3033
3034 while (num_ringpairs--) {
3035 map_vector_to_qp(vsi, v_start, qp_idx);
3036 qp_idx++;
3037 qp_remaining--;
41c445ff
JB		 3038 }
3039 }
3040}
3041
3042/**
3043 * i40e_vsi_request_irq - Request IRQ from the OS
3044 * @vsi: the VSI being configured
3045 * @basename: name for the vector
3046 **/
3047static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3048{
3049 struct i40e_pf *pf = vsi->back;
3050 int err;
3051
3052 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3053 err = i40e_vsi_request_irq_msix(vsi, basename);
3054 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3055 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3056 pf->misc_int_name, pf);
3057 else
3058 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3059 pf->misc_int_name, pf);
3060
3061 if (err)
3062 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3063
3064 return err;
3065}
3066
3067#ifdef CONFIG_NET_POLL_CONTROLLER
3068/**
3069 * i40e_netpoll - A Polling 'interrupt'handler
3070 * @netdev: network interface device structure
3071 *
3072 * This is used by netconsole to send skbs without having to re-enable
3073 * interrupts. It's not called while the normal interrupt routine is executing.
3074 **/
3075static void i40e_netpoll(struct net_device *netdev)
3076{
3077 struct i40e_netdev_priv *np = netdev_priv(netdev);
3078 struct i40e_vsi *vsi = np->vsi;
3079 struct i40e_pf *pf = vsi->back;
3080 int i;
3081
3082 /* if interface is down do nothing */
3083 if (test_bit(__I40E_DOWN, &vsi->state))
3084 return;
3085
3086 pf->flags |= I40E_FLAG_IN_NETPOLL;
3087 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3088 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3089 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3090 } else {
3091 i40e_intr(pf->pdev->irq, netdev);
3092 }
3093 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3094}
3095#endif
3096
3097/**
3098 * i40e_vsi_control_tx - Start or stop a VSI's rings
3099 * @vsi: the VSI being configured
3100 * @enable: start or stop the rings
3101 **/
3102static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3103{
3104 struct i40e_pf *pf = vsi->back;
3105 struct i40e_hw *hw = &pf->hw;
3106 int i, j, pf_q;
3107 u32 tx_reg;
3108
3109 pf_q = vsi->base_queue;
3110 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3111 j = 1000;
3112 do {
3113 usleep_range(1000, 2000);
3114 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3115 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
3116 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
3117
fda972f6
MW		 3118 /* Skip if the queue is already in the requested state */
3119 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3120 continue;
3121 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3122 continue;
41c445ff
JB		 3123
3124 /* turn on/off the queue */
c5c9eb9e
SN		 3125 if (enable) {
3126 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
41c445ff
JB		 3127 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3128 I40E_QTX_ENA_QENA_STAT_MASK;
c5c9eb9e 3129 } else {
41c445ff 3130 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3131 }
41c445ff
JB		 3132
3133 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3134
3135 /* wait for the change to finish */
3136 for (j = 0; j < 10; j++) {
3137 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3138 if (enable) {
3139 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3140 break;
3141 } else {
3142 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3143 break;
3144 }
3145
3146 udelay(10);
3147 }
3148 if (j >= 10) {
3149 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3150 pf_q, (enable ? "en" : "dis"));
3151 return -ETIMEDOUT;
3152 }
3153 }
3154
7134f9ce
JB		 3155 if (hw->revision_id == 0)
3156 mdelay(50);
3157
41c445ff
JB		 3158 return 0;
3159}
3160
3161/**
3162 * i40e_vsi_control_rx - Start or stop a VSI's rings
3163 * @vsi: the VSI being configured
3164 * @enable: start or stop the rings
3165 **/
3166static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3167{
3168 struct i40e_pf *pf = vsi->back;
3169 struct i40e_hw *hw = &pf->hw;
3170 int i, j, pf_q;
3171 u32 rx_reg;
3172
3173 pf_q = vsi->base_queue;
3174 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3175 j = 1000;
3176 do {
3177 usleep_range(1000, 2000);
3178 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3179 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3180 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3181
3182 if (enable) {
3183 /* is STAT set ? */
3184 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3185 continue;
3186 } else {
3187 /* is !STAT set ? */
3188 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3189 continue;
3190 }
3191
3192 /* turn on/off the queue */
3193 if (enable)
3194 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3195 I40E_QRX_ENA_QENA_STAT_MASK;
3196 else
3197 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3198 I40E_QRX_ENA_QENA_STAT_MASK);
3199 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3200
3201 /* wait for the change to finish */
3202 for (j = 0; j < 10; j++) {
3203 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3204
3205 if (enable) {
3206 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3207 break;
3208 } else {
3209 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3210 break;
3211 }
3212
3213 udelay(10);
3214 }
3215 if (j >= 10) {
3216 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3217 pf_q, (enable ? "en" : "dis"));
3218 return -ETIMEDOUT;
3219 }
3220 }
3221
3222 return 0;
3223}
3224
3225/**
3226 * i40e_vsi_control_rings - Start or stop a VSI's rings
3227 * @vsi: the VSI being configured
3228 * @enable: start or stop the rings
3229 **/
fc18eaa0 3230int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3231{
3b867b28 3232 int ret = 0;
41c445ff
JB		 3233
3234 /* do rx first for enable and last for disable */
3235 if (request) {
3236 ret = i40e_vsi_control_rx(vsi, request);
3237 if (ret)
3238 return ret;
3239 ret = i40e_vsi_control_tx(vsi, request);
3240 } else {
3b867b28
ASJ		 3241 /* Ignore return value, we need to shutdown whatever we can */
3242 i40e_vsi_control_tx(vsi, request);
3243 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3244 }
3245
3246 return ret;
3247}
3248
3249/**
3250 * i40e_vsi_free_irq - Free the irq association with the OS
3251 * @vsi: the VSI being configured
3252 **/
3253static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3254{
3255 struct i40e_pf *pf = vsi->back;
3256 struct i40e_hw *hw = &pf->hw;
3257 int base = vsi->base_vector;
3258 u32 val, qp;
3259 int i;
3260
3261 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3262 if (!vsi->q_vectors)
3263 return;
3264
3265 for (i = 0; i < vsi->num_q_vectors; i++) {
3266 u16 vector = i + base;
3267
3268 /* free only the irqs that were actually requested */
78681b1f
SN		 3269 if (!vsi->q_vectors[i] ||
3270 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3271 continue;
3272
3273 /* clear the affinity_mask in the IRQ descriptor */
3274 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3275 NULL);
3276 free_irq(pf->msix_entries[vector].vector,
493fb300 3277 vsi->q_vectors[i]);
41c445ff
JB		 3278
3279 /* Tear down the interrupt queue link list
3280 *
3281 * We know that they come in pairs and always
3282 * the Rx first, then the Tx. To clear the
3283 * link list, stick the EOL value into the
3284 * next_q field of the registers.
3285 */
3286 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3287 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3288 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3289 val |= I40E_QUEUE_END_OF_LIST
3290 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3291 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3292
3293 while (qp != I40E_QUEUE_END_OF_LIST) {
3294 u32 next;
3295
3296 val = rd32(hw, I40E_QINT_RQCTL(qp));
3297
3298 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3299 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3300 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3301 I40E_QINT_RQCTL_INTEVENT_MASK);
3302
3303 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3304 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3305
3306 wr32(hw, I40E_QINT_RQCTL(qp), val);
3307
3308 val = rd32(hw, I40E_QINT_TQCTL(qp));
3309
3310 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3311 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3312
3313 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3314 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3315 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3316 I40E_QINT_TQCTL_INTEVENT_MASK);
3317
3318 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3319 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3320
3321 wr32(hw, I40E_QINT_TQCTL(qp), val);
3322 qp = next;
3323 }
3324 }
3325 } else {
3326 free_irq(pf->pdev->irq, pf);
3327
3328 val = rd32(hw, I40E_PFINT_LNKLST0);
3329 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3330 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3331 val |= I40E_QUEUE_END_OF_LIST
3332 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3333 wr32(hw, I40E_PFINT_LNKLST0, val);
3334
3335 val = rd32(hw, I40E_QINT_RQCTL(qp));
3336 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3337 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3338 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3339 I40E_QINT_RQCTL_INTEVENT_MASK);
3340
3341 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3342 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3343
3344 wr32(hw, I40E_QINT_RQCTL(qp), val);
3345
3346 val = rd32(hw, I40E_QINT_TQCTL(qp));
3347
3348 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3349 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3350 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3351 I40E_QINT_TQCTL_INTEVENT_MASK);
3352
3353 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3354 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3355
3356 wr32(hw, I40E_QINT_TQCTL(qp), val);
3357 }
3358}
3359
493fb300
AD		 3360/**
3361 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3362 * @vsi: the VSI being configured
3363 * @v_idx: Index of vector to be freed
3364 *
3365 * This function frees the memory allocated to the q_vector. In addition if
3366 * NAPI is enabled it will delete any references to the NAPI struct prior
3367 * to freeing the q_vector.
3368 **/
3369static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3370{
3371 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3372 struct i40e_ring *ring;
493fb300
AD		 3373
3374 if (!q_vector)
3375 return;
3376
3377 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3378 i40e_for_each_ring(ring, q_vector->tx)
3379 ring->q_vector = NULL;
3380
3381 i40e_for_each_ring(ring, q_vector->rx)
3382 ring->q_vector = NULL;
493fb300
AD		 3383
3384 /* only VSI w/ an associated netdev is set up w/ NAPI */
3385 if (vsi->netdev)
3386 netif_napi_del(&q_vector->napi);
3387
3388 vsi->q_vectors[v_idx] = NULL;
3389
3390 kfree_rcu(q_vector, rcu);
3391}
3392
41c445ff
JB		 3393/**
3394 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3395 * @vsi: the VSI being un-configured
3396 *
3397 * This frees the memory allocated to the q_vectors and
3398 * deletes references to the NAPI struct.
3399 **/
3400static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3401{
3402 int v_idx;
3403
493fb300
AD		 3404 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3405 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3406}
3407
3408/**
3409 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3410 * @pf: board private structure
3411 **/
3412static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3413{
3414 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3415 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3416 pci_disable_msix(pf->pdev);
3417 kfree(pf->msix_entries);
3418 pf->msix_entries = NULL;
3419 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3420 pci_disable_msi(pf->pdev);
3421 }
3422 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3423}
3424
3425/**
3426 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3427 * @pf: board private structure
3428 *
3429 * We go through and clear interrupt specific resources and reset the structure
3430 * to pre-load conditions
3431 **/
3432static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3433{
3434 int i;
3435
3436 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3437 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3438 if (pf->vsi[i])
3439 i40e_vsi_free_q_vectors(pf->vsi[i]);
3440 i40e_reset_interrupt_capability(pf);
3441}
3442
3443/**
3444 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3445 * @vsi: the VSI being configured
3446 **/
3447static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3448{
3449 int q_idx;
3450
3451 if (!vsi->netdev)
3452 return;
3453
3454 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3455 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3456}
3457
3458/**
3459 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3460 * @vsi: the VSI being configured
3461 **/
3462static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3463{
3464 int q_idx;
3465
3466 if (!vsi->netdev)
3467 return;
3468
3469 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3470 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3471}
3472
3473/**
3474 * i40e_quiesce_vsi - Pause a given VSI
3475 * @vsi: the VSI being paused
3476 **/
3477static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3478{
3479 if (test_bit(__I40E_DOWN, &vsi->state))
3480 return;
3481
3482 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3483 if (vsi->netdev && netif_running(vsi->netdev)) {
3484 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3485 } else {
3486 set_bit(__I40E_DOWN, &vsi->state);
3487 i40e_down(vsi);
3488 }
3489}
3490
3491/**
3492 * i40e_unquiesce_vsi - Resume a given VSI
3493 * @vsi: the VSI being resumed
3494 **/
3495static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3496{
3497 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3498 return;
3499
3500 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3501 if (vsi->netdev && netif_running(vsi->netdev))
3502 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3503 else
3504 i40e_up(vsi); /* this clears the DOWN bit */
3505}
3506
3507/**
3508 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3509 * @pf: the PF
3510 **/
3511static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3512{
3513 int v;
3514
3515 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3516 if (pf->vsi[v])
3517 i40e_quiesce_vsi(pf->vsi[v]);
3518 }
3519}
3520
3521/**
3522 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3523 * @pf: the PF
3524 **/
3525static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3526{
3527 int v;
3528
3529 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3530 if (pf->vsi[v])
3531 i40e_unquiesce_vsi(pf->vsi[v]);
3532 }
3533}
3534
3535/**
3536 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3537 * @dcbcfg: the corresponding DCBx configuration structure
3538 *
3539 * Return the number of TCs from given DCBx configuration
3540 **/
3541static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3542{
078b5876
JB		 3543 u8 num_tc = 0;
3544 int i;
41c445ff
JB		 3545
3546 /* Scan the ETS Config Priority Table to find
3547 * traffic class enabled for a given priority
3548 * and use the traffic class index to get the
3549 * number of traffic classes enabled
3550 */
3551 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3552 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3553 num_tc = dcbcfg->etscfg.prioritytable[i];
3554 }
3555
3556 /* Traffic class index starts from zero so
3557 * increment to return the actual count
3558 */
078b5876 3559 return num_tc + 1;
41c445ff
JB		 3560}
3561
3562/**
3563 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3564 * @dcbcfg: the corresponding DCBx configuration structure
3565 *
3566 * Query the current DCB configuration and return the number of
3567 * traffic classes enabled from the given DCBX config
3568 **/
3569static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3570{
3571 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3572 u8 enabled_tc = 1;
3573 u8 i;
3574
3575 for (i = 0; i < num_tc; i++)
3576 enabled_tc |= 1 << i;
3577
3578 return enabled_tc;
3579}
3580
3581/**
3582 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3583 * @pf: PF being queried
3584 *
3585 * Return number of traffic classes enabled for the given PF
3586 **/
3587static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3588{
3589 struct i40e_hw *hw = &pf->hw;
3590 u8 i, enabled_tc;
3591 u8 num_tc = 0;
3592 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3593
3594 /* If DCB is not enabled then always in single TC */
3595 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3596 return 1;
3597
3598 /* MFP mode return count of enabled TCs for this PF */
3599 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3600 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3601 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3602 if (enabled_tc & (1 << i))
3603 num_tc++;
3604 }
3605 return num_tc;
3606 }
3607
3608 /* SFP mode will be enabled for all TCs on port */
3609 return i40e_dcb_get_num_tc(dcbcfg);
3610}
3611
3612/**
3613 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3614 * @pf: PF being queried
3615 *
3616 * Return a bitmap for first enabled traffic class for this PF.
3617 **/
3618static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3619{
3620 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3621 u8 i = 0;
3622
3623 if (!enabled_tc)
3624 return 0x1; /* TC0 */
3625
3626 /* Find the first enabled TC */
3627 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3628 if (enabled_tc & (1 << i))
3629 break;
3630 }
3631
3632 return 1 << i;
3633}
3634
3635/**
3636 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3637 * @pf: PF being queried
3638 *
3639 * Return a bitmap for enabled traffic classes for this PF.
3640 **/
3641static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3642{
3643 /* If DCB is not enabled for this PF then just return default TC */
3644 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3645 return i40e_pf_get_default_tc(pf);
3646
3647 /* MFP mode will have enabled TCs set by FW */
3648 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3649 return pf->hw.func_caps.enabled_tcmap;
3650
3651 /* SFP mode we want PF to be enabled for all TCs */
3652 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3653}
3654
3655/**
3656 * i40e_vsi_get_bw_info - Query VSI BW Information
3657 * @vsi: the VSI being queried
3658 *
3659 * Returns 0 on success, negative value on failure
3660 **/
3661static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3662{
3663 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3664 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3665 struct i40e_pf *pf = vsi->back;
3666 struct i40e_hw *hw = &pf->hw;
dcae29be 3667 i40e_status aq_ret;
41c445ff 3668 u32 tc_bw_max;
41c445ff
JB		 3669 int i;
3670
3671 /* Get the VSI level BW configuration */
dcae29be
JB		 3672 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3673 if (aq_ret) {
41c445ff
JB		 3674 dev_info(&pf->pdev->dev,
3675 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3676 aq_ret, pf->hw.aq.asq_last_status);
3677 return -EINVAL;
41c445ff
JB		 3678 }
3679
3680 /* Get the VSI level BW configuration per TC */
dcae29be 3681 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3682 NULL);
dcae29be 3683 if (aq_ret) {
41c445ff
JB		 3684 dev_info(&pf->pdev->dev,
3685 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3686 aq_ret, pf->hw.aq.asq_last_status);
3687 return -EINVAL;
41c445ff
JB		 3688 }
3689
3690 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3691 dev_info(&pf->pdev->dev,
3692 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3693 bw_config.tc_valid_bits,
3694 bw_ets_config.tc_valid_bits);
3695 /* Still continuing */
3696 }
3697
3698 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3699 vsi->bw_max_quanta = bw_config.max_bw;
3700 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3701 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3702 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3703 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3704 vsi->bw_ets_limit_credits[i] =
3705 le16_to_cpu(bw_ets_config.credits[i]);
3706 /* 3 bits out of 4 for each TC */
3707 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3708 }
078b5876 3709
dcae29be 3710 return 0;
41c445ff
JB		 3711}
3712
3713/**
3714 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3715 * @vsi: the VSI being configured
3716 * @enabled_tc: TC bitmap
3717 * @bw_credits: BW shared credits per TC
3718 *
3719 * Returns 0 on success, negative value on failure
3720 **/
dcae29be 3721static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3722 u8 *bw_share)
3723{
3724 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3725 i40e_status aq_ret;
3726 int i;
41c445ff
JB		 3727
3728 bw_data.tc_valid_bits = enabled_tc;
3729 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3730 bw_data.tc_bw_credits[i] = bw_share[i];
3731
dcae29be
JB		 3732 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3733 NULL);
3734 if (aq_ret) {
41c445ff
JB		 3735 dev_info(&vsi->back->pdev->dev,
3736 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3737 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3738 return -EINVAL;
41c445ff
JB		 3739 }
3740
3741 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3742 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3743
dcae29be 3744 return 0;
41c445ff
JB		 3745}
3746
3747/**
3748 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3749 * @vsi: the VSI being configured
3750 * @enabled_tc: TC map to be enabled
3751 *
3752 **/
3753static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3754{
3755 struct net_device *netdev = vsi->netdev;
3756 struct i40e_pf *pf = vsi->back;
3757 struct i40e_hw *hw = &pf->hw;
3758 u8 netdev_tc = 0;
3759 int i;
3760 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3761
3762 if (!netdev)
3763 return;
3764
3765 if (!enabled_tc) {
3766 netdev_reset_tc(netdev);
3767 return;
3768 }
3769
3770 /* Set up actual enabled TCs on the VSI */
3771 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3772 return;
3773
3774 /* set per TC queues for the VSI */
3775 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3776 /* Only set TC queues for enabled tcs
3777 *
3778 * e.g. For a VSI that has TC0 and TC3 enabled the
3779 * enabled_tc bitmap would be 0x00001001; the driver
3780 * will set the numtc for netdev as 2 that will be
3781 * referenced by the netdev layer as TC 0 and 1.
3782 */
3783 if (vsi->tc_config.enabled_tc & (1 << i))
3784 netdev_set_tc_queue(netdev,
3785 vsi->tc_config.tc_info[i].netdev_tc,
3786 vsi->tc_config.tc_info[i].qcount,
3787 vsi->tc_config.tc_info[i].qoffset);
3788 }
3789
3790 /* Assign UP2TC map for the VSI */
3791 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3792 /* Get the actual TC# for the UP */
3793 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3794 /* Get the mapped netdev TC# for the UP */
3795 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3796 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3797 }
3798}
3799
3800/**
3801 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3802 * @vsi: the VSI being configured
3803 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3804 **/
3805static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3806 struct i40e_vsi_context *ctxt)
3807{
3808 /* copy just the sections touched not the entire info
3809 * since not all sections are valid as returned by
3810 * update vsi params
3811 */
3812 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3813 memcpy(&vsi->info.queue_mapping,
3814 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3815 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3816 sizeof(vsi->info.tc_mapping));
3817}
3818
3819/**
3820 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3821 * @vsi: VSI to be configured
3822 * @enabled_tc: TC bitmap
3823 *
3824 * This configures a particular VSI for TCs that are mapped to the
3825 * given TC bitmap. It uses default bandwidth share for TCs across
3826 * VSIs to configure TC for a particular VSI.
3827 *
3828 * NOTE:
3829 * It is expected that the VSI queues have been quisced before calling
3830 * this function.
3831 **/
3832static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3833{
3834 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3835 struct i40e_vsi_context ctxt;
3836 int ret = 0;
3837 int i;
3838
3839 /* Check if enabled_tc is same as existing or new TCs */
3840 if (vsi->tc_config.enabled_tc == enabled_tc)
3841 return ret;
3842
3843 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3844 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3845 if (enabled_tc & (1 << i))
3846 bw_share[i] = 1;
3847 }
3848
3849 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3850 if (ret) {
3851 dev_info(&vsi->back->pdev->dev,
3852 "Failed configuring TC map %d for VSI %d\n",
3853 enabled_tc, vsi->seid);
3854 goto out;
3855 }
3856
3857 /* Update Queue Pairs Mapping for currently enabled UPs */
3858 ctxt.seid = vsi->seid;
3859 ctxt.pf_num = vsi->back->hw.pf_id;
3860 ctxt.vf_num = 0;
3861 ctxt.uplink_seid = vsi->uplink_seid;
3862 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3863 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3864
3865 /* Update the VSI after updating the VSI queue-mapping information */
3866 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3867 if (ret) {
3868 dev_info(&vsi->back->pdev->dev,
3869 "update vsi failed, aq_err=%d\n",
3870 vsi->back->hw.aq.asq_last_status);
3871 goto out;
3872 }
3873 /* update the local VSI info with updated queue map */
3874 i40e_vsi_update_queue_map(vsi, &ctxt);
3875 vsi->info.valid_sections = 0;
3876
3877 /* Update current VSI BW information */
3878 ret = i40e_vsi_get_bw_info(vsi);
3879 if (ret) {
3880 dev_info(&vsi->back->pdev->dev,
3881 "Failed updating vsi bw info, aq_err=%d\n",
3882 vsi->back->hw.aq.asq_last_status);
3883 goto out;
3884 }
3885
3886 /* Update the netdev TC setup */
3887 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3888out:
3889 return ret;
3890}
3891
4e3b35b0
NP		 3892/**
3893 * i40e_veb_config_tc - Configure TCs for given VEB
3894 * @veb: given VEB
3895 * @enabled_tc: TC bitmap
3896 *
3897 * Configures given TC bitmap for VEB (switching) element
3898 **/
3899int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3900{
3901 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3902 struct i40e_pf *pf = veb->pf;
3903 int ret = 0;
3904 int i;
3905
3906 /* No TCs or already enabled TCs just return */
3907 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3908 return ret;
3909
3910 bw_data.tc_valid_bits = enabled_tc;
3911 /* bw_data.absolute_credits is not set (relative) */
3912
3913 /* Enable ETS TCs with equal BW Share for now */
3914 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3915 if (enabled_tc & (1 << i))
3916 bw_data.tc_bw_share_credits[i] = 1;
3917 }
3918
3919 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3920 &bw_data, NULL);
3921 if (ret) {
3922 dev_info(&pf->pdev->dev,
3923 "veb bw config failed, aq_err=%d\n",
3924 pf->hw.aq.asq_last_status);
3925 goto out;
3926 }
3927
3928 /* Update the BW information */
3929 ret = i40e_veb_get_bw_info(veb);
3930 if (ret) {
3931 dev_info(&pf->pdev->dev,
3932 "Failed getting veb bw config, aq_err=%d\n",
3933 pf->hw.aq.asq_last_status);
3934 }
3935
3936out:
3937 return ret;
3938}
3939
3940#ifdef CONFIG_I40E_DCB
3941/**
3942 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
3943 * @pf: PF struct
3944 *
3945 * Reconfigure VEB/VSIs on a given PF; it is assumed that
3946 * the caller would've quiesce all the VSIs before calling
3947 * this function
3948 **/
3949static void i40e_dcb_reconfigure(struct i40e_pf *pf)
3950{
3951 u8 tc_map = 0;
3952 int ret;
3953 u8 v;
3954
3955 /* Enable the TCs available on PF to all VEBs */
3956 tc_map = i40e_pf_get_tc_map(pf);
3957 for (v = 0; v < I40E_MAX_VEB; v++) {
3958 if (!pf->veb[v])
3959 continue;
3960 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
3961 if (ret) {
3962 dev_info(&pf->pdev->dev,
3963 "Failed configuring TC for VEB seid=%d\n",
3964 pf->veb[v]->seid);
3965 /* Will try to configure as many components */
3966 }
3967 }
3968
3969 /* Update each VSI */
3970 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3971 if (!pf->vsi[v])
3972 continue;
3973
3974 /* - Enable all TCs for the LAN VSI
3975 * - For all others keep them at TC0 for now
3976 */
3977 if (v == pf->lan_vsi)
3978 tc_map = i40e_pf_get_tc_map(pf);
3979 else
3980 tc_map = i40e_pf_get_default_tc(pf);
3981
3982 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
3983 if (ret) {
3984 dev_info(&pf->pdev->dev,
3985 "Failed configuring TC for VSI seid=%d\n",
3986 pf->vsi[v]->seid);
3987 /* Will try to configure as many components */
3988 } else {
3989 if (pf->vsi[v]->netdev)
3990 i40e_dcbnl_set_all(pf->vsi[v]);
3991 }
3992 }
3993}
3994
3995/**
3996 * i40e_init_pf_dcb - Initialize DCB configuration
3997 * @pf: PF being configured
3998 *
3999 * Query the current DCB configuration and cache it
4000 * in the hardware structure
4001 **/
4002static int i40e_init_pf_dcb(struct i40e_pf *pf)
4003{
4004 struct i40e_hw *hw = &pf->hw;
4005 int err = 0;
4006
4007 if (pf->hw.func_caps.npar_enable)
4008 goto out;
4009
4010 /* Get the initial DCB configuration */
4011 err = i40e_init_dcb(hw);
4012 if (!err) {
4013 /* Device/Function is not DCBX capable */
4014 if ((!hw->func_caps.dcb) ||
4015 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4016 dev_info(&pf->pdev->dev,
4017 "DCBX offload is not supported or is disabled for this PF.\n");
4018
4019 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4020 goto out;
4021
4022 } else {
4023 /* When status is not DISABLED then DCBX in FW */
4024 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4025 DCB_CAP_DCBX_VER_IEEE;
4026 pf->flags |= I40E_FLAG_DCB_ENABLED;
4027 }
4028 }
4029
4030out:
4031 return err;
4032}
4033#endif /* CONFIG_I40E_DCB */
4034
41c445ff
JB		 4035/**
4036 * i40e_up_complete - Finish the last steps of bringing up a connection
4037 * @vsi: the VSI being configured
4038 **/
4039static int i40e_up_complete(struct i40e_vsi *vsi)
4040{
4041 struct i40e_pf *pf = vsi->back;
4042 int err;
4043
4044 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4045 i40e_vsi_configure_msix(vsi);
4046 else
4047 i40e_configure_msi_and_legacy(vsi);
4048
4049 /* start rings */
4050 err = i40e_vsi_control_rings(vsi, true);
4051 if (err)
4052 return err;
4053
4054 clear_bit(__I40E_DOWN, &vsi->state);
4055 i40e_napi_enable_all(vsi);
4056 i40e_vsi_enable_irq(vsi);
4057
4058 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4059 (vsi->netdev)) {
6d779b41 4060 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4061 netif_tx_start_all_queues(vsi->netdev);
4062 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4063 } else if (vsi->netdev) {
4064 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 4065 }
4066 i40e_service_event_schedule(pf);
4067
4068 return 0;
4069}
4070
4071/**
4072 * i40e_vsi_reinit_locked - Reset the VSI
4073 * @vsi: the VSI being configured
4074 *
4075 * Rebuild the ring structs after some configuration
4076 * has changed, e.g. MTU size.
4077 **/
4078static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4079{
4080 struct i40e_pf *pf = vsi->back;
4081
4082 WARN_ON(in_interrupt());
4083 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4084 usleep_range(1000, 2000);
4085 i40e_down(vsi);
4086
4087 /* Give a VF some time to respond to the reset. The
4088 * two second wait is based upon the watchdog cycle in
4089 * the VF driver.
4090 */
4091 if (vsi->type == I40E_VSI_SRIOV)
4092 msleep(2000);
4093 i40e_up(vsi);
4094 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4095}
4096
4097/**
4098 * i40e_up - Bring the connection back up after being down
4099 * @vsi: the VSI being configured
4100 **/
4101int i40e_up(struct i40e_vsi *vsi)
4102{
4103 int err;
4104
4105 err = i40e_vsi_configure(vsi);
4106 if (!err)
4107 err = i40e_up_complete(vsi);
4108
4109 return err;
4110}
4111
4112/**
4113 * i40e_down - Shutdown the connection processing
4114 * @vsi: the VSI being stopped
4115 **/
4116void i40e_down(struct i40e_vsi *vsi)
4117{
4118 int i;
4119
4120 /* It is assumed that the caller of this function
4121 * sets the vsi->state __I40E_DOWN bit.
4122 */
4123 if (vsi->netdev) {
4124 netif_carrier_off(vsi->netdev);
4125 netif_tx_disable(vsi->netdev);
4126 }
4127 i40e_vsi_disable_irq(vsi);
4128 i40e_vsi_control_rings(vsi, false);
4129 i40e_napi_disable_all(vsi);
4130
4131 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4132 i40e_clean_tx_ring(vsi->tx_rings[i]);
4133 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4134 }
4135}
4136
4137/**
4138 * i40e_setup_tc - configure multiple traffic classes
4139 * @netdev: net device to configure
4140 * @tc: number of traffic classes to enable
4141 **/
4142static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4143{
4144 struct i40e_netdev_priv *np = netdev_priv(netdev);
4145 struct i40e_vsi *vsi = np->vsi;
4146 struct i40e_pf *pf = vsi->back;
4147 u8 enabled_tc = 0;
4148 int ret = -EINVAL;
4149 int i;
4150
4151 /* Check if DCB enabled to continue */
4152 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4153 netdev_info(netdev, "DCB is not enabled for adapter\n");
4154 goto exit;
4155 }
4156
4157 /* Check if MFP enabled */
4158 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4159 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4160 goto exit;
4161 }
4162
4163 /* Check whether tc count is within enabled limit */
4164 if (tc > i40e_pf_get_num_tc(pf)) {
4165 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4166 goto exit;
4167 }
4168
4169 /* Generate TC map for number of tc requested */
4170 for (i = 0; i < tc; i++)
4171 enabled_tc |= (1 << i);
4172
4173 /* Requesting same TC configuration as already enabled */
4174 if (enabled_tc == vsi->tc_config.enabled_tc)
4175 return 0;
4176
4177 /* Quiesce VSI queues */
4178 i40e_quiesce_vsi(vsi);
4179
4180 /* Configure VSI for enabled TCs */
4181 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4182 if (ret) {
4183 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4184 vsi->seid);
4185 goto exit;
4186 }
4187
4188 /* Unquiesce VSI */
4189 i40e_unquiesce_vsi(vsi);
4190
4191exit:
4192 return ret;
4193}
4194
4195/**
4196 * i40e_open - Called when a network interface is made active
4197 * @netdev: network interface device structure
4198 *
4199 * The open entry point is called when a network interface is made
4200 * active by the system (IFF_UP). At this point all resources needed
4201 * for transmit and receive operations are allocated, the interrupt
4202 * handler is registered with the OS, the netdev watchdog subtask is
4203 * enabled, and the stack is notified that the interface is ready.
4204 *
4205 * Returns 0 on success, negative value on failure
4206 **/
4207static int i40e_open(struct net_device *netdev)
4208{
4209 struct i40e_netdev_priv *np = netdev_priv(netdev);
4210 struct i40e_vsi *vsi = np->vsi;
4211 struct i40e_pf *pf = vsi->back;
4212 char int_name[IFNAMSIZ];
4213 int err;
4214
4215 /* disallow open during test */
4216 if (test_bit(__I40E_TESTING, &pf->state))
4217 return -EBUSY;
4218
4219 netif_carrier_off(netdev);
4220
4221 /* allocate descriptors */
4222 err = i40e_vsi_setup_tx_resources(vsi);
4223 if (err)
4224 goto err_setup_tx;
4225 err = i40e_vsi_setup_rx_resources(vsi);
4226 if (err)
4227 goto err_setup_rx;
4228
4229 err = i40e_vsi_configure(vsi);
4230 if (err)
4231 goto err_setup_rx;
4232
4233 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4234 dev_driver_string(&pf->pdev->dev), netdev->name);
4235 err = i40e_vsi_request_irq(vsi, int_name);
4236 if (err)
4237 goto err_setup_rx;
4238
25946ddb 4239 /* Notify the stack of the actual queue counts. */
d7397644 4240 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4241 if (err)
4242 goto err_set_queues;
4243
d7397644 4244 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4245 if (err)
4246 goto err_set_queues;
4247
41c445ff
JB		 4248 err = i40e_up_complete(vsi);
4249 if (err)
4250 goto err_up_complete;
4251
a1c9a9d9
JK		 4252#ifdef CONFIG_I40E_VXLAN
4253 vxlan_get_rx_port(netdev);
4254#endif
41c445ff
JB		 4255
4256 return 0;
4257
4258err_up_complete:
4259 i40e_down(vsi);
25946ddb 4260err_set_queues:
41c445ff
JB		 4261 i40e_vsi_free_irq(vsi);
4262err_setup_rx:
4263 i40e_vsi_free_rx_resources(vsi);
4264err_setup_tx:
4265 i40e_vsi_free_tx_resources(vsi);
4266 if (vsi == pf->vsi[pf->lan_vsi])
4267 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4268
4269 return err;
4270}
4271
4272/**
4273 * i40e_close - Disables a network interface
4274 * @netdev: network interface device structure
4275 *
4276 * The close entry point is called when an interface is de-activated
4277 * by the OS. The hardware is still under the driver's control, but
4278 * this netdev interface is disabled.
4279 *
4280 * Returns 0, this is not allowed to fail
4281 **/
4282static int i40e_close(struct net_device *netdev)
4283{
4284 struct i40e_netdev_priv *np = netdev_priv(netdev);
4285 struct i40e_vsi *vsi = np->vsi;
4286
4287 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4288 return 0;
4289
4290 i40e_down(vsi);
4291 i40e_vsi_free_irq(vsi);
4292
4293 i40e_vsi_free_tx_resources(vsi);
4294 i40e_vsi_free_rx_resources(vsi);
4295
4296 return 0;
4297}
4298
4299/**
4300 * i40e_do_reset - Start a PF or Core Reset sequence
4301 * @pf: board private structure
4302 * @reset_flags: which reset is requested
4303 *
4304 * The essential difference in resets is that the PF Reset
4305 * doesn't clear the packet buffers, doesn't reset the PE
4306 * firmware, and doesn't bother the other PFs on the chip.
4307 **/
4308void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4309{
4310 u32 val;
4311
4312 WARN_ON(in_interrupt());
4313
4314 /* do the biggest reset indicated */
4315 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4316
4317 /* Request a Global Reset
4318 *
4319 * This will start the chip's countdown to the actual full
4320 * chip reset event, and a warning interrupt to be sent
4321 * to all PFs, including the requestor. Our handler
4322 * for the warning interrupt will deal with the shutdown
4323 * and recovery of the switch setup.
4324 */
4325 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4326 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4327 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4328 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4329
4330 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4331
4332 /* Request a Core Reset
4333 *
4334 * Same as Global Reset, except does *not* include the MAC/PHY
4335 */
4336 dev_info(&pf->pdev->dev, "CoreR requested\n");
4337 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4338 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4339 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4340 i40e_flush(&pf->hw);
4341
7823fe34
SN		 4342 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4343
4344 /* Request a Firmware Reset
4345 *
4346 * Same as Global reset, plus restarting the
4347 * embedded firmware engine.
4348 */
4349 /* enable EMP Reset */
4350 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4351 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4352 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4353
4354 /* force the reset */
4355 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4356 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4357 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4358 i40e_flush(&pf->hw);
4359
41c445ff
JB		 4360 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4361
4362 /* Request a PF Reset
4363 *
4364 * Resets only the PF-specific registers
4365 *
4366 * This goes directly to the tear-down and rebuild of
4367 * the switch, since we need to do all the recovery as
4368 * for the Core Reset.
4369 */
4370 dev_info(&pf->pdev->dev, "PFR requested\n");
4371 i40e_handle_reset_warning(pf);
4372
4373 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4374 int v;
4375
4376 /* Find the VSI(s) that requested a re-init */
4377 dev_info(&pf->pdev->dev,
4378 "VSI reinit requested\n");
4379 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4380 struct i40e_vsi *vsi = pf->vsi[v];
4381 if (vsi != NULL &&
4382 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4383 i40e_vsi_reinit_locked(pf->vsi[v]);
4384 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4385 }
4386 }
4387
4388 /* no further action needed, so return now */
4389 return;
4390 } else {
4391 dev_info(&pf->pdev->dev,
4392 "bad reset request 0x%08x\n", reset_flags);
4393 return;
4394 }
4395}
4396
4e3b35b0
NP		 4397#ifdef CONFIG_I40E_DCB
4398/**
4399 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4400 * @pf: board private structure
4401 * @old_cfg: current DCB config
4402 * @new_cfg: new DCB config
4403 **/
4404bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4405 struct i40e_dcbx_config *old_cfg,
4406 struct i40e_dcbx_config *new_cfg)
4407{
4408 bool need_reconfig = false;
4409
4410 /* Check if ETS configuration has changed */
4411 if (memcmp(&new_cfg->etscfg,
4412 &old_cfg->etscfg,
4413 sizeof(new_cfg->etscfg))) {
4414 /* If Priority Table has changed reconfig is needed */
4415 if (memcmp(&new_cfg->etscfg.prioritytable,
4416 &old_cfg->etscfg.prioritytable,
4417 sizeof(new_cfg->etscfg.prioritytable))) {
4418 need_reconfig = true;
4419 dev_info(&pf->pdev->dev, "ETS UP2TC changed.\n");
4420 }
4421
4422 if (memcmp(&new_cfg->etscfg.tcbwtable,
4423 &old_cfg->etscfg.tcbwtable,
4424 sizeof(new_cfg->etscfg.tcbwtable)))
4425 dev_info(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4426
4427 if (memcmp(&new_cfg->etscfg.tsatable,
4428 &old_cfg->etscfg.tsatable,
4429 sizeof(new_cfg->etscfg.tsatable)))
4430 dev_info(&pf->pdev->dev, "ETS TSA Table changed.\n");
4431 }
4432
4433 /* Check if PFC configuration has changed */
4434 if (memcmp(&new_cfg->pfc,
4435 &old_cfg->pfc,
4436 sizeof(new_cfg->pfc))) {
4437 need_reconfig = true;
4438 dev_info(&pf->pdev->dev, "PFC config change detected.\n");
4439 }
4440
4441 /* Check if APP Table has changed */
4442 if (memcmp(&new_cfg->app,
4443 &old_cfg->app,
3d9667a9 4444 sizeof(new_cfg->app))) {
4e3b35b0
NP		 4445 need_reconfig = true;
4446 dev_info(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4447 }
4e3b35b0
NP		 4448
4449 return need_reconfig;
4450}
4451
4452/**
4453 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4454 * @pf: board private structure
4455 * @e: event info posted on ARQ
4456 **/
4457static int i40e_handle_lldp_event(struct i40e_pf *pf,
4458 struct i40e_arq_event_info *e)
4459{
4460 struct i40e_aqc_lldp_get_mib *mib =
4461 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4462 struct i40e_hw *hw = &pf->hw;
4463 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4464 struct i40e_dcbx_config tmp_dcbx_cfg;
4465 bool need_reconfig = false;
4466 int ret = 0;
4467 u8 type;
4468
4469 /* Ignore if event is not for Nearest Bridge */
4470 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4471 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4472 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4473 return ret;
4474
4475 /* Check MIB Type and return if event for Remote MIB update */
4476 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4477 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4478 /* Update the remote cached instance and return */
4479 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4480 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4481 &hw->remote_dcbx_config);
4482 goto exit;
4483 }
4484
4485 /* Convert/store the DCBX data from LLDPDU temporarily */
4486 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4487 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4488 if (ret) {
4489 /* Error in LLDPDU parsing return */
4490 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4491 goto exit;
4492 }
4493
4494 /* No change detected in DCBX configs */
4495 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
4496 dev_info(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4497 goto exit;
4498 }
4499
4500 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4501
4502 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4503
4504 /* Overwrite the new configuration */
4505 *dcbx_cfg = tmp_dcbx_cfg;
4506
4507 if (!need_reconfig)
4508 goto exit;
4509
4510 /* Reconfiguration needed quiesce all VSIs */
4511 i40e_pf_quiesce_all_vsi(pf);
4512
4513 /* Changes in configuration update VEB/VSI */
4514 i40e_dcb_reconfigure(pf);
4515
4516 i40e_pf_unquiesce_all_vsi(pf);
4517exit:
4518 return ret;
4519}
4520#endif /* CONFIG_I40E_DCB */
4521
23326186
ASJ		 4522/**
4523 * i40e_do_reset_safe - Protected reset path for userland calls.
4524 * @pf: board private structure
4525 * @reset_flags: which reset is requested
4526 *
4527 **/
4528void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4529{
4530 rtnl_lock();
4531 i40e_do_reset(pf, reset_flags);
4532 rtnl_unlock();
4533}
4534
41c445ff
JB		 4535/**
4536 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4537 * @pf: board private structure
4538 * @e: event info posted on ARQ
4539 *
4540 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4541 * and VF queues
4542 **/
4543static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4544 struct i40e_arq_event_info *e)
4545{
4546 struct i40e_aqc_lan_overflow *data =
4547 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4548 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4549 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4550 struct i40e_hw *hw = &pf->hw;
4551 struct i40e_vf *vf;
4552 u16 vf_id;
4553
4554 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4555 __func__, queue, qtx_ctl);
4556
4557 /* Queue belongs to VF, find the VF and issue VF reset */
4558 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4559 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4560 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4561 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4562 vf_id -= hw->func_caps.vf_base_id;
4563 vf = &pf->vf[vf_id];
4564 i40e_vc_notify_vf_reset(vf);
4565 /* Allow VF to process pending reset notification */
4566 msleep(20);
4567 i40e_reset_vf(vf, false);
4568 }
4569}
4570
4571/**
4572 * i40e_service_event_complete - Finish up the service event
4573 * @pf: board private structure
4574 **/
4575static void i40e_service_event_complete(struct i40e_pf *pf)
4576{
4577 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4578
4579 /* flush memory to make sure state is correct before next watchog */
4580 smp_mb__before_clear_bit();
4581 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4582}
4583
4584/**
4585 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4586 * @pf: board private structure
4587 **/
4588static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4589{
4590 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4591 return;
4592
4593 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4594
4595 /* if interface is down do nothing */
4596 if (test_bit(__I40E_DOWN, &pf->state))
4597 return;
4598}
4599
4600/**
4601 * i40e_vsi_link_event - notify VSI of a link event
4602 * @vsi: vsi to be notified
4603 * @link_up: link up or down
4604 **/
4605static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4606{
4607 if (!vsi)
4608 return;
4609
4610 switch (vsi->type) {
4611 case I40E_VSI_MAIN:
4612 if (!vsi->netdev || !vsi->netdev_registered)
4613 break;
4614
4615 if (link_up) {
4616 netif_carrier_on(vsi->netdev);
4617 netif_tx_wake_all_queues(vsi->netdev);
4618 } else {
4619 netif_carrier_off(vsi->netdev);
4620 netif_tx_stop_all_queues(vsi->netdev);
4621 }
4622 break;
4623
4624 case I40E_VSI_SRIOV:
4625 break;
4626
4627 case I40E_VSI_VMDQ2:
4628 case I40E_VSI_CTRL:
4629 case I40E_VSI_MIRROR:
4630 default:
4631 /* there is no notification for other VSIs */
4632 break;
4633 }
4634}
4635
4636/**
4637 * i40e_veb_link_event - notify elements on the veb of a link event
4638 * @veb: veb to be notified
4639 * @link_up: link up or down
4640 **/
4641static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4642{
4643 struct i40e_pf *pf;
4644 int i;
4645
4646 if (!veb || !veb->pf)
4647 return;
4648 pf = veb->pf;
4649
4650 /* depth first... */
4651 for (i = 0; i < I40E_MAX_VEB; i++)
4652 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4653 i40e_veb_link_event(pf->veb[i], link_up);
4654
4655 /* ... now the local VSIs */
4656 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4657 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4658 i40e_vsi_link_event(pf->vsi[i], link_up);
4659}
4660
4661/**
4662 * i40e_link_event - Update netif_carrier status
4663 * @pf: board private structure
4664 **/
4665static void i40e_link_event(struct i40e_pf *pf)
4666{
4667 bool new_link, old_link;
4668
4669 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4670 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4671
4672 if (new_link == old_link)
4673 return;
4674
6d779b41
AS		 4675 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4676 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4677 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4678
4679 /* Notify the base of the switch tree connected to
4680 * the link. Floating VEBs are not notified.
4681 */
4682 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4683 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4684 else
4685 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4686
4687 if (pf->vf)
4688 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4689
4690 if (pf->flags & I40E_FLAG_PTP)
4691 i40e_ptp_set_increment(pf);
41c445ff
JB		 4692}
4693
4694/**
4695 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4696 * @pf: board private structure
4697 *
4698 * Set the per-queue flags to request a check for stuck queues in the irq
4699 * clean functions, then force interrupts to be sure the irq clean is called.
4700 **/
4701static void i40e_check_hang_subtask(struct i40e_pf *pf)
4702{
4703 int i, v;
4704
4705 /* If we're down or resetting, just bail */
4706 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4707 return;
4708
4709 /* for each VSI/netdev
4710 * for each Tx queue
4711 * set the check flag
4712 * for each q_vector
4713 * force an interrupt
4714 */
4715 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4716 struct i40e_vsi *vsi = pf->vsi[v];
4717 int armed = 0;
4718
4719 if (!pf->vsi[v] ||
4720 test_bit(__I40E_DOWN, &vsi->state) ||
4721 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4722 continue;
4723
4724 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4725 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4726 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4727 &vsi->tx_rings[i]->state))
41c445ff
JB		 4728 armed++;
4729 }
4730
4731 if (armed) {
4732 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4733 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4734 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4735 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4736 } else {
4737 u16 vec = vsi->base_vector - 1;
4738 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4739 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4740 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4741 wr32(&vsi->back->hw,
4742 I40E_PFINT_DYN_CTLN(vec), val);
4743 }
4744 i40e_flush(&vsi->back->hw);
4745 }
4746 }
4747}
4748
4749/**
4750 * i40e_watchdog_subtask - Check and bring link up
4751 * @pf: board private structure
4752 **/
4753static void i40e_watchdog_subtask(struct i40e_pf *pf)
4754{
4755 int i;
4756
4757 /* if interface is down do nothing */
4758 if (test_bit(__I40E_DOWN, &pf->state) ||
4759 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4760 return;
4761
4762 /* Update the stats for active netdevs so the network stack
4763 * can look at updated numbers whenever it cares to
4764 */
4765 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4766 if (pf->vsi[i] && pf->vsi[i]->netdev)
4767 i40e_update_stats(pf->vsi[i]);
4768
4769 /* Update the stats for the active switching components */
4770 for (i = 0; i < I40E_MAX_VEB; i++)
4771 if (pf->veb[i])
4772 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4773
4774 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4775}
4776
4777/**
4778 * i40e_reset_subtask - Set up for resetting the device and driver
4779 * @pf: board private structure
4780 **/
4781static void i40e_reset_subtask(struct i40e_pf *pf)
4782{
4783 u32 reset_flags = 0;
4784
23326186 4785 rtnl_lock();
41c445ff
JB		 4786 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4787 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4788 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4789 }
4790 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4791 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4792 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4793 }
4794 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4795 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4796 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4797 }
4798 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4799 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4800 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4801 }
4802
4803 /* If there's a recovery already waiting, it takes
4804 * precedence before starting a new reset sequence.
4805 */
4806 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4807 i40e_handle_reset_warning(pf);
23326186 4808 goto unlock;
41c445ff
JB		 4809 }
4810
4811 /* If we're already down or resetting, just bail */
4812 if (reset_flags &&
4813 !test_bit(__I40E_DOWN, &pf->state) &&
4814 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4815 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4816
4817unlock:
4818 rtnl_unlock();
41c445ff
JB		 4819}
4820
4821/**
4822 * i40e_handle_link_event - Handle link event
4823 * @pf: board private structure
4824 * @e: event info posted on ARQ
4825 **/
4826static void i40e_handle_link_event(struct i40e_pf *pf,
4827 struct i40e_arq_event_info *e)
4828{
4829 struct i40e_hw *hw = &pf->hw;
4830 struct i40e_aqc_get_link_status *status =
4831 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4832 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4833
4834 /* save off old link status information */
4835 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4836 sizeof(pf->hw.phy.link_info_old));
4837
4838 /* update link status */
4839 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4840 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4841 hw_link_info->link_info = status->link_info;
4842 hw_link_info->an_info = status->an_info;
4843 hw_link_info->ext_info = status->ext_info;
4844 hw_link_info->lse_enable =
4845 le16_to_cpu(status->command_flags) &
4846 I40E_AQ_LSE_ENABLE;
4847
4848 /* process the event */
4849 i40e_link_event(pf);
4850
4851 /* Do a new status request to re-enable LSE reporting
4852 * and load new status information into the hw struct,
4853 * then see if the status changed while processing the
4854 * initial event.
4855 */
4856 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4857 i40e_link_event(pf);
4858}
4859
4860/**
4861 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4862 * @pf: board private structure
4863 **/
4864static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4865{
4866 struct i40e_arq_event_info event;
4867 struct i40e_hw *hw = &pf->hw;
4868 u16 pending, i = 0;
4869 i40e_status ret;
4870 u16 opcode;
4871 u32 val;
4872
4873 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4874 return;
4875
3197ce22 4876 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4877 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4878 if (!event.msg_buf)
4879 return;
4880
4881 do {
2f019123 4882 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4883 ret = i40e_clean_arq_element(hw, &event, &pending);
4884 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4885 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4886 break;
4887 } else if (ret) {
4888 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4889 break;
4890 }
4891
4892 opcode = le16_to_cpu(event.desc.opcode);
4893 switch (opcode) {
4894
4895 case i40e_aqc_opc_get_link_status:
4896 i40e_handle_link_event(pf, &event);
4897 break;
4898 case i40e_aqc_opc_send_msg_to_pf:
4899 ret = i40e_vc_process_vf_msg(pf,
4900 le16_to_cpu(event.desc.retval),
4901 le32_to_cpu(event.desc.cookie_high),
4902 le32_to_cpu(event.desc.cookie_low),
4903 event.msg_buf,
4904 event.msg_size);
4905 break;
4906 case i40e_aqc_opc_lldp_update_mib:
4907 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 4908#ifdef CONFIG_I40E_DCB
4909 rtnl_lock();
4910 ret = i40e_handle_lldp_event(pf, &event);
4911 rtnl_unlock();
4912#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 4913 break;
4914 case i40e_aqc_opc_event_lan_overflow:
4915 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4916 i40e_handle_lan_overflow_event(pf, &event);
4917 break;
0467bc91
SN		 4918 case i40e_aqc_opc_send_msg_to_peer:
4919 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
4920 break;
41c445ff
JB		 4921 default:
4922 dev_info(&pf->pdev->dev,
0467bc91
SN		 4923 "ARQ Error: Unknown event 0x%04x received\n",
4924 opcode);
41c445ff
JB		 4925 break;
4926 }
4927 } while (pending && (i++ < pf->adminq_work_limit));
4928
4929 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4930 /* re-enable Admin queue interrupt cause */
4931 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4932 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4933 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4934 i40e_flush(hw);
4935
4936 kfree(event.msg_buf);
4937}
4938
4939/**
4940 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4941 * @veb: pointer to the VEB instance
4942 *
4943 * This is a recursive function that first builds the attached VSIs then
4944 * recurses in to build the next layer of VEB. We track the connections
4945 * through our own index numbers because the seid's from the HW could
4946 * change across the reset.
4947 **/
4948static int i40e_reconstitute_veb(struct i40e_veb *veb)
4949{
4950 struct i40e_vsi *ctl_vsi = NULL;
4951 struct i40e_pf *pf = veb->pf;
4952 int v, veb_idx;
4953 int ret;
4954
4955 /* build VSI that owns this VEB, temporarily attached to base VEB */
4956 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4957 if (pf->vsi[v] &&
4958 pf->vsi[v]->veb_idx == veb->idx &&
4959 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4960 ctl_vsi = pf->vsi[v];
4961 break;
4962 }
4963 }
4964 if (!ctl_vsi) {
4965 dev_info(&pf->pdev->dev,
4966 "missing owner VSI for veb_idx %d\n", veb->idx);
4967 ret = -ENOENT;
4968 goto end_reconstitute;
4969 }
4970 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4971 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4972 ret = i40e_add_vsi(ctl_vsi);
4973 if (ret) {
4974 dev_info(&pf->pdev->dev,
4975 "rebuild of owner VSI failed: %d\n", ret);
4976 goto end_reconstitute;
4977 }
4978 i40e_vsi_reset_stats(ctl_vsi);
4979
4980 /* create the VEB in the switch and move the VSI onto the VEB */
4981 ret = i40e_add_veb(veb, ctl_vsi);
4982 if (ret)
4983 goto end_reconstitute;
4984
4985 /* create the remaining VSIs attached to this VEB */
4986 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4987 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4988 continue;
4989
4990 if (pf->vsi[v]->veb_idx == veb->idx) {
4991 struct i40e_vsi *vsi = pf->vsi[v];
4992 vsi->uplink_seid = veb->seid;
4993 ret = i40e_add_vsi(vsi);
4994 if (ret) {
4995 dev_info(&pf->pdev->dev,
4996 "rebuild of vsi_idx %d failed: %d\n",
4997 v, ret);
4998 goto end_reconstitute;
4999 }
5000 i40e_vsi_reset_stats(vsi);
5001 }
5002 }
5003
5004 /* create any VEBs attached to this VEB - RECURSION */
5005 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5006 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5007 pf->veb[veb_idx]->uplink_seid = veb->seid;
5008 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5009 if (ret)
5010 break;
5011 }
5012 }
5013
5014end_reconstitute:
5015 return ret;
5016}
5017
5018/**
5019 * i40e_get_capabilities - get info about the HW
5020 * @pf: the PF struct
5021 **/
5022static int i40e_get_capabilities(struct i40e_pf *pf)
5023{
5024 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5025 u16 data_size;
5026 int buf_len;
5027 int err;
5028
5029 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5030 do {
5031 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5032 if (!cap_buf)
5033 return -ENOMEM;
5034
5035 /* this loads the data into the hw struct for us */
5036 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5037 &data_size,
5038 i40e_aqc_opc_list_func_capabilities,
5039 NULL);
5040 /* data loaded, buffer no longer needed */
5041 kfree(cap_buf);
5042
5043 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5044 /* retry with a larger buffer */
5045 buf_len = data_size;
5046 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5047 dev_info(&pf->pdev->dev,
5048 "capability discovery failed: aq=%d\n",
5049 pf->hw.aq.asq_last_status);
5050 return -ENODEV;
5051 }
5052 } while (err);
5053
d0b10249
JB		 5054 /* increment MSI-X count because current FW skips one */
5055 pf->hw.func_caps.num_msix_vectors++;
7134f9ce 5056
41c445ff
JB		 5057 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5058 dev_info(&pf->pdev->dev,
5059 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5060 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5061 pf->hw.func_caps.num_msix_vectors,
5062 pf->hw.func_caps.num_msix_vectors_vf,
5063 pf->hw.func_caps.fd_filters_guaranteed,
5064 pf->hw.func_caps.fd_filters_best_effort,
5065 pf->hw.func_caps.num_tx_qp,
5066 pf->hw.func_caps.num_vsis);
5067
7134f9ce
JB		 5068#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5069 + pf->hw.func_caps.num_vfs)
5070 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5071 dev_info(&pf->pdev->dev,
5072 "got num_vsis %d, setting num_vsis to %d\n",
5073 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5074 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5075 }
5076
41c445ff
JB		 5077 return 0;
5078}
5079
cbf61325
ASJ		 5080static int i40e_vsi_clear(struct i40e_vsi *vsi);
5081
41c445ff 5082/**
cbf61325 5083 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5084 * @pf: board private structure
5085 **/
cbf61325 5086static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5087{
5088 struct i40e_vsi *vsi;
5089 bool new_vsi = false;
5090 int err, i;
5091
cbf61325 5092 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5093 return;
5094
cbf61325 5095 /* find existing VSI and see if it needs configuring */
41c445ff 5096 vsi = NULL;
cbf61325
ASJ		 5097 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5098 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5099 vsi = pf->vsi[i];
cbf61325
ASJ		 5100 break;
5101 }
5102 }
5103
5104 /* create a new VSI if none exists */
41c445ff 5105 if (!vsi) {
cbf61325
ASJ		 5106 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5107 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5108 if (!vsi) {
5109 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
cbf61325 5110 goto err_vsi;
41c445ff
JB		 5111 }
5112 new_vsi = true;
5113 }
cbf61325 5114 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5115
5116 err = i40e_vsi_setup_tx_resources(vsi);
cbf61325
ASJ		 5117 if (err)
5118 goto err_setup_tx;
5119 err = i40e_vsi_setup_rx_resources(vsi);
5120 if (err)
5121 goto err_setup_rx;
5122
5123 if (new_vsi) {
41c445ff 5124 char int_name[IFNAMSIZ + 9];
cbf61325
ASJ		 5125 err = i40e_vsi_configure(vsi);
5126 if (err)
5127 goto err_setup_rx;
41c445ff
JB		 5128 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
5129 dev_driver_string(&pf->pdev->dev));
5130 err = i40e_vsi_request_irq(vsi, int_name);
cbf61325
ASJ		 5131 if (err)
5132 goto err_setup_rx;
41c445ff 5133 err = i40e_up_complete(vsi);
cbf61325
ASJ		 5134 if (err)
5135 goto err_up_complete;
5136 }
41c445ff
JB		 5137
5138 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
cbf61325
ASJ		 5139 return;
5140
5141err_up_complete:
5142 i40e_down(vsi);
5143 i40e_vsi_free_irq(vsi);
5144err_setup_rx:
5145 i40e_vsi_free_rx_resources(vsi);
5146err_setup_tx:
5147 i40e_vsi_free_tx_resources(vsi);
5148err_vsi:
5149 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5150 i40e_vsi_clear(vsi);
41c445ff
JB		 5151}
5152
5153/**
5154 * i40e_fdir_teardown - release the Flow Director resources
5155 * @pf: board private structure
5156 **/
5157static void i40e_fdir_teardown(struct i40e_pf *pf)
5158{
5159 int i;
5160
5161 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5162 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5163 i40e_vsi_release(pf->vsi[i]);
5164 break;
5165 }
5166 }
5167}
5168
5169/**
f650a38b 5170 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5171 * @pf: board private structure
5172 *
f650a38b
ASJ		 5173 * Close up the VFs and other things in prep for pf Reset.
5174 **/
5175static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5176{
41c445ff
JB		 5177 struct i40e_hw *hw = &pf->hw;
5178 i40e_status ret;
5179 u32 v;
5180
5181 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5182 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5183 return 0;
41c445ff
JB		 5184
5185 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
5186
37f0be6d
ASJ		 5187 if (i40e_check_asq_alive(hw))
5188 i40e_vc_notify_reset(pf);
41c445ff
JB		 5189
5190 /* quiesce the VSIs and their queues that are not already DOWN */
5191 i40e_pf_quiesce_all_vsi(pf);
5192
5193 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5194 if (pf->vsi[v])
5195 pf->vsi[v]->seid = 0;
5196 }
5197
5198 i40e_shutdown_adminq(&pf->hw);
5199
f650a38b
ASJ		 5200 /* call shutdown HMC */
5201 ret = i40e_shutdown_lan_hmc(hw);
5202 if (ret) {
5203 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5204 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5205 }
5206 return ret;
5207}
5208
5209/**
4dda12e6 5210 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5211 * @pf: board private structure
bc7d338f 5212 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5213 **/
bc7d338f 5214static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 5215{
5216 struct i40e_driver_version dv;
5217 struct i40e_hw *hw = &pf->hw;
5218 i40e_status ret;
5219 u32 v;
5220
41c445ff
JB		 5221 /* Now we wait for GRST to settle out.
5222 * We don't have to delete the VEBs or VSIs from the hw switch
5223 * because the reset will make them disappear.
5224 */
5225 ret = i40e_pf_reset(hw);
5226 if (ret)
5227 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
5228 pf->pfr_count++;
5229
5230 if (test_bit(__I40E_DOWN, &pf->state))
5231 goto end_core_reset;
5232 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
5233
5234 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5235 ret = i40e_init_adminq(&pf->hw);
5236 if (ret) {
5237 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5238 goto end_core_reset;
5239 }
5240
5241 ret = i40e_get_capabilities(pf);
5242 if (ret) {
5243 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5244 ret);
5245 goto end_core_reset;
5246 }
5247
41c445ff
JB		 5248 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5249 hw->func_caps.num_rx_qp,
5250 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5251 if (ret) {
5252 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5253 goto end_core_reset;
5254 }
5255 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5256 if (ret) {
5257 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5258 goto end_core_reset;
5259 }
5260
4e3b35b0
NP		 5261#ifdef CONFIG_I40E_DCB
5262 ret = i40e_init_pf_dcb(pf);
5263 if (ret) {
5264 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5265 goto end_core_reset;
5266 }
5267#endif /* CONFIG_I40E_DCB */
5268
41c445ff 5269 /* do basic switch setup */
bc7d338f 5270 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5271 if (ret)
5272 goto end_core_reset;
5273
5274 /* Rebuild the VSIs and VEBs that existed before reset.
5275 * They are still in our local switch element arrays, so only
5276 * need to rebuild the switch model in the HW.
5277 *
5278 * If there were VEBs but the reconstitution failed, we'll try
5279 * try to recover minimal use by getting the basic PF VSI working.
5280 */
5281 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
5282 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
5283 /* find the one VEB connected to the MAC, and find orphans */
5284 for (v = 0; v < I40E_MAX_VEB; v++) {
5285 if (!pf->veb[v])
5286 continue;
5287
5288 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5289 pf->veb[v]->uplink_seid == 0) {
5290 ret = i40e_reconstitute_veb(pf->veb[v]);
5291
5292 if (!ret)
5293 continue;
5294
5295 /* If Main VEB failed, we're in deep doodoo,
5296 * so give up rebuilding the switch and set up
5297 * for minimal rebuild of PF VSI.
5298 * If orphan failed, we'll report the error
5299 * but try to keep going.
5300 */
5301 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5302 dev_info(&pf->pdev->dev,
5303 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5304 ret);
5305 pf->vsi[pf->lan_vsi]->uplink_seid
5306 = pf->mac_seid;
5307 break;
5308 } else if (pf->veb[v]->uplink_seid == 0) {
5309 dev_info(&pf->pdev->dev,
5310 "rebuild of orphan VEB failed: %d\n",
5311 ret);
5312 }
5313 }
5314 }
5315 }
5316
5317 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5318 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5319 /* no VEB, so rebuild only the Main VSI */
5320 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5321 if (ret) {
5322 dev_info(&pf->pdev->dev,
5323 "rebuild of Main VSI failed: %d\n", ret);
5324 goto end_core_reset;
5325 }
5326 }
5327
5328 /* reinit the misc interrupt */
5329 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5330 ret = i40e_setup_misc_vector(pf);
5331
5332 /* restart the VSIs that were rebuilt and running before the reset */
5333 i40e_pf_unquiesce_all_vsi(pf);
5334
69f64b2b
MW		 5335 if (pf->num_alloc_vfs) {
5336 for (v = 0; v < pf->num_alloc_vfs; v++)
5337 i40e_reset_vf(&pf->vf[v], true);
5338 }
5339
41c445ff
JB		 5340 /* tell the firmware that we're starting */
5341 dv.major_version = DRV_VERSION_MAJOR;
5342 dv.minor_version = DRV_VERSION_MINOR;
5343 dv.build_version = DRV_VERSION_BUILD;
5344 dv.subbuild_version = 0;
5345 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5346
5347 dev_info(&pf->pdev->dev, "PF reset done\n");
5348
5349end_core_reset:
5350 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5351}
5352
f650a38b
ASJ		 5353/**
5354 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5355 * @pf: board private structure
5356 *
5357 * Close up the VFs and other things in prep for a Core Reset,
5358 * then get ready to rebuild the world.
5359 **/
5360static void i40e_handle_reset_warning(struct i40e_pf *pf)
5361{
5362 i40e_status ret;
5363
5364 ret = i40e_prep_for_reset(pf);
5365 if (!ret)
bc7d338f 5366 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5367}
5368
41c445ff
JB		 5369/**
5370 * i40e_handle_mdd_event
5371 * @pf: pointer to the pf structure
5372 *
5373 * Called from the MDD irq handler to identify possibly malicious vfs
5374 **/
5375static void i40e_handle_mdd_event(struct i40e_pf *pf)
5376{
5377 struct i40e_hw *hw = &pf->hw;
5378 bool mdd_detected = false;
5379 struct i40e_vf *vf;
5380 u32 reg;
5381 int i;
5382
5383 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5384 return;
5385
5386 /* find what triggered the MDD event */
5387 reg = rd32(hw, I40E_GL_MDET_TX);
5388 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5389 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5390 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5391 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5392 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5393 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5394 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5395 dev_info(&pf->pdev->dev,
5396 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
5397 event, queue, func);
5398 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5399 mdd_detected = true;
5400 }
5401 reg = rd32(hw, I40E_GL_MDET_RX);
5402 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5403 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5404 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5405 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5406 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5407 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5408 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5409 dev_info(&pf->pdev->dev,
5410 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
5411 event, queue, func);
5412 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5413 mdd_detected = true;
5414 }
5415
5416 /* see if one of the VFs needs its hand slapped */
5417 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5418 vf = &(pf->vf[i]);
5419 reg = rd32(hw, I40E_VP_MDET_TX(i));
5420 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5421 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5422 vf->num_mdd_events++;
5423 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5424 }
5425
5426 reg = rd32(hw, I40E_VP_MDET_RX(i));
5427 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5428 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5429 vf->num_mdd_events++;
5430 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5431 }
5432
5433 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5434 dev_info(&pf->pdev->dev,
5435 "Too many MDD events on VF %d, disabled\n", i);
5436 dev_info(&pf->pdev->dev,
5437 "Use PF Control I/F to re-enable the VF\n");
5438 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5439 }
5440 }
5441
5442 /* re-enable mdd interrupt cause */
5443 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5444 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5445 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5446 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5447 i40e_flush(hw);
5448}
5449
a1c9a9d9
JK		 5450#ifdef CONFIG_I40E_VXLAN
5451/**
5452 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5453 * @pf: board private structure
5454 **/
5455static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5456{
5457 const int vxlan_hdr_qwords = 4;
5458 struct i40e_hw *hw = &pf->hw;
5459 i40e_status ret;
5460 u8 filter_index;
5461 __be16 port;
5462 int i;
5463
5464 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5465 return;
5466
5467 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5468
5469 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5470 if (pf->pending_vxlan_bitmap & (1 << i)) {
5471 pf->pending_vxlan_bitmap &= ~(1 << i);
5472 port = pf->vxlan_ports[i];
5473 ret = port ?
5474 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5475 vxlan_hdr_qwords,
5476 I40E_AQC_TUNNEL_TYPE_VXLAN,
5477 &filter_index, NULL)
5478 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5479
5480 if (ret) {
5481 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5482 port ? "adding" : "deleting",
5483 ntohs(port), port ? i : i);
5484
5485 pf->vxlan_ports[i] = 0;
5486 } else {
5487 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5488 port ? "Added" : "Deleted",
5489 ntohs(port), port ? i : filter_index);
5490 }
5491 }
5492 }
5493}
5494
5495#endif
41c445ff
JB		 5496/**
5497 * i40e_service_task - Run the driver's async subtasks
5498 * @work: pointer to work_struct containing our data
5499 **/
5500static void i40e_service_task(struct work_struct *work)
5501{
5502 struct i40e_pf *pf = container_of(work,
5503 struct i40e_pf,
5504 service_task);
5505 unsigned long start_time = jiffies;
5506
5507 i40e_reset_subtask(pf);
5508 i40e_handle_mdd_event(pf);
5509 i40e_vc_process_vflr_event(pf);
5510 i40e_watchdog_subtask(pf);
5511 i40e_fdir_reinit_subtask(pf);
5512 i40e_check_hang_subtask(pf);
5513 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5514#ifdef CONFIG_I40E_VXLAN
5515 i40e_sync_vxlan_filters_subtask(pf);
5516#endif
41c445ff
JB		 5517 i40e_clean_adminq_subtask(pf);
5518
5519 i40e_service_event_complete(pf);
5520
5521 /* If the tasks have taken longer than one timer cycle or there
5522 * is more work to be done, reschedule the service task now
5523 * rather than wait for the timer to tick again.
5524 */
5525 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5526 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5527 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5528 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5529 i40e_service_event_schedule(pf);
5530}
5531
5532/**
5533 * i40e_service_timer - timer callback
5534 * @data: pointer to PF struct
5535 **/
5536static void i40e_service_timer(unsigned long data)
5537{
5538 struct i40e_pf *pf = (struct i40e_pf *)data;
5539
5540 mod_timer(&pf->service_timer,
5541 round_jiffies(jiffies + pf->service_timer_period));
5542 i40e_service_event_schedule(pf);
5543}
5544
5545/**
5546 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5547 * @vsi: the VSI being configured
5548 **/
5549static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5550{
5551 struct i40e_pf *pf = vsi->back;
5552
5553 switch (vsi->type) {
5554 case I40E_VSI_MAIN:
5555 vsi->alloc_queue_pairs = pf->num_lan_qps;
5556 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5557 I40E_REQ_DESCRIPTOR_MULTIPLE);
5558 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5559 vsi->num_q_vectors = pf->num_lan_msix;
5560 else
5561 vsi->num_q_vectors = 1;
5562
5563 break;
5564
5565 case I40E_VSI_FDIR:
5566 vsi->alloc_queue_pairs = 1;
5567 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5568 I40E_REQ_DESCRIPTOR_MULTIPLE);
5569 vsi->num_q_vectors = 1;
5570 break;
5571
5572 case I40E_VSI_VMDQ2:
5573 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5574 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5575 I40E_REQ_DESCRIPTOR_MULTIPLE);
5576 vsi->num_q_vectors = pf->num_vmdq_msix;
5577 break;
5578
5579 case I40E_VSI_SRIOV:
5580 vsi->alloc_queue_pairs = pf->num_vf_qps;
5581 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5582 I40E_REQ_DESCRIPTOR_MULTIPLE);
5583 break;
5584
5585 default:
5586 WARN_ON(1);
5587 return -ENODATA;
5588 }
5589
5590 return 0;
5591}
5592
f650a38b
ASJ		 5593/**
5594 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5595 * @type: VSI pointer
bc7d338f 5596 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5597 *
5598 * On error: returns error code (negative)
5599 * On success: returns 0
5600 **/
bc7d338f 5601static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5602{
5603 int size;
5604 int ret = 0;
5605
ac6c5e3d 5606 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5607 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5608 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5609 if (!vsi->tx_rings)
5610 return -ENOMEM;
f650a38b
ASJ		 5611 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5612
bc7d338f
ASJ		 5613 if (alloc_qvectors) {
5614 /* allocate memory for q_vector pointers */
5615 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5616 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5617 if (!vsi->q_vectors) {
5618 ret = -ENOMEM;
5619 goto err_vectors;
5620 }
f650a38b
ASJ		 5621 }
5622 return ret;
5623
5624err_vectors:
5625 kfree(vsi->tx_rings);
5626 return ret;
5627}
5628
41c445ff
JB		 5629/**
5630 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5631 * @pf: board private structure
5632 * @type: type of VSI
5633 *
5634 * On error: returns error code (negative)
5635 * On success: returns vsi index in PF (positive)
5636 **/
5637static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5638{
5639 int ret = -ENODEV;
5640 struct i40e_vsi *vsi;
5641 int vsi_idx;
5642 int i;
5643
5644 /* Need to protect the allocation of the VSIs at the PF level */
5645 mutex_lock(&pf->switch_mutex);
5646
5647 /* VSI list may be fragmented if VSI creation/destruction has
5648 * been happening. We can afford to do a quick scan to look
5649 * for any free VSIs in the list.
5650 *
5651 * find next empty vsi slot, looping back around if necessary
5652 */
5653 i = pf->next_vsi;
5654 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5655 i++;
5656 if (i >= pf->hw.func_caps.num_vsis) {
5657 i = 0;
5658 while (i < pf->next_vsi && pf->vsi[i])
5659 i++;
5660 }
5661
5662 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5663 vsi_idx = i; /* Found one! */
5664 } else {
5665 ret = -ENODEV;
493fb300 5666 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5667 }
5668 pf->next_vsi = ++i;
5669
5670 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5671 if (!vsi) {
5672 ret = -ENOMEM;
493fb300 5673 goto unlock_pf;
41c445ff
JB		 5674 }
5675 vsi->type = type;
5676 vsi->back = pf;
5677 set_bit(__I40E_DOWN, &vsi->state);
5678 vsi->flags = 0;
5679 vsi->idx = vsi_idx;
5680 vsi->rx_itr_setting = pf->rx_itr_default;
5681 vsi->tx_itr_setting = pf->tx_itr_default;
5682 vsi->netdev_registered = false;
5683 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5684 INIT_LIST_HEAD(&vsi->mac_filter_list);
5685
9f65e15b
AD		 5686 ret = i40e_set_num_rings_in_vsi(vsi);
5687 if (ret)
5688 goto err_rings;
5689
bc7d338f 5690 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5691 if (ret)
9f65e15b 5692 goto err_rings;
493fb300 5693
41c445ff
JB		 5694 /* Setup default MSIX irq handler for VSI */
5695 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5696
5697 pf->vsi[vsi_idx] = vsi;
5698 ret = vsi_idx;
493fb300
AD		 5699 goto unlock_pf;
5700
9f65e15b 5701err_rings:
493fb300
AD		 5702 pf->next_vsi = i - 1;
5703 kfree(vsi);
5704unlock_pf:
41c445ff
JB		 5705 mutex_unlock(&pf->switch_mutex);
5706 return ret;
5707}
5708
f650a38b
ASJ		 5709/**
5710 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5711 * @type: VSI pointer
bc7d338f 5712 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5713 *
5714 * On error: returns error code (negative)
5715 * On success: returns 0
5716 **/
bc7d338f 5717static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5718{
5719 /* free the ring and vector containers */
bc7d338f
ASJ		 5720 if (free_qvectors) {
5721 kfree(vsi->q_vectors);
5722 vsi->q_vectors = NULL;
5723 }
f650a38b
ASJ		 5724 kfree(vsi->tx_rings);
5725 vsi->tx_rings = NULL;
5726 vsi->rx_rings = NULL;
5727}
5728
41c445ff
JB		 5729/**
5730 * i40e_vsi_clear - Deallocate the VSI provided
5731 * @vsi: the VSI being un-configured
5732 **/
5733static int i40e_vsi_clear(struct i40e_vsi *vsi)
5734{
5735 struct i40e_pf *pf;
5736
5737 if (!vsi)
5738 return 0;
5739
5740 if (!vsi->back)
5741 goto free_vsi;
5742 pf = vsi->back;
5743
5744 mutex_lock(&pf->switch_mutex);
5745 if (!pf->vsi[vsi->idx]) {
5746 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5747 vsi->idx, vsi->idx, vsi, vsi->type);
5748 goto unlock_vsi;
5749 }
5750
5751 if (pf->vsi[vsi->idx] != vsi) {
5752 dev_err(&pf->pdev->dev,
5753 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5754 pf->vsi[vsi->idx]->idx,
5755 pf->vsi[vsi->idx],
5756 pf->vsi[vsi->idx]->type,
5757 vsi->idx, vsi, vsi->type);
5758 goto unlock_vsi;
5759 }
5760
5761 /* updates the pf for this cleared vsi */
5762 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5763 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5764
bc7d338f 5765 i40e_vsi_free_arrays(vsi, true);
493fb300 5766
41c445ff
JB		 5767 pf->vsi[vsi->idx] = NULL;
5768 if (vsi->idx < pf->next_vsi)
5769 pf->next_vsi = vsi->idx;
5770
5771unlock_vsi:
5772 mutex_unlock(&pf->switch_mutex);
5773free_vsi:
5774 kfree(vsi);
5775
5776 return 0;
5777}
5778
9f65e15b
AD		 5779/**
5780 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5781 * @vsi: the VSI being cleaned
5782 **/
be1d5eea 5783static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5784{
5785 int i;
5786
8e9dca53 5787 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5788 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5789 kfree_rcu(vsi->tx_rings[i], rcu);
5790 vsi->tx_rings[i] = NULL;
5791 vsi->rx_rings[i] = NULL;
5792 }
be1d5eea 5793 }
9f65e15b
AD		 5794}
5795
41c445ff
JB		 5796/**
5797 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5798 * @vsi: the VSI being configured
5799 **/
5800static int i40e_alloc_rings(struct i40e_vsi *vsi)
5801{
5802 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5803 int i;
5804
41c445ff 5805 /* Set basic values in the rings to be used later during open() */
d7397644 5806 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5807 struct i40e_ring *tx_ring;
5808 struct i40e_ring *rx_ring;
5809
ac6c5e3d 5810 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5811 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5812 if (!tx_ring)
5813 goto err_out;
41c445ff
JB		 5814
5815 tx_ring->queue_index = i;
5816 tx_ring->reg_idx = vsi->base_queue + i;
5817 tx_ring->ring_active = false;
5818 tx_ring->vsi = vsi;
5819 tx_ring->netdev = vsi->netdev;
5820 tx_ring->dev = &pf->pdev->dev;
5821 tx_ring->count = vsi->num_desc;
5822 tx_ring->size = 0;
5823 tx_ring->dcb_tc = 0;
9f65e15b 5824 vsi->tx_rings[i] = tx_ring;
41c445ff 5825
9f65e15b 5826 rx_ring = &tx_ring[1];
41c445ff
JB		 5827 rx_ring->queue_index = i;
5828 rx_ring->reg_idx = vsi->base_queue + i;
5829 rx_ring->ring_active = false;
5830 rx_ring->vsi = vsi;
5831 rx_ring->netdev = vsi->netdev;
5832 rx_ring->dev = &pf->pdev->dev;
5833 rx_ring->count = vsi->num_desc;
5834 rx_ring->size = 0;
5835 rx_ring->dcb_tc = 0;
5836 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5837 set_ring_16byte_desc_enabled(rx_ring);
5838 else
5839 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5840 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5841 }
5842
5843 return 0;
9f65e15b
AD		 5844
5845err_out:
5846 i40e_vsi_clear_rings(vsi);
5847 return -ENOMEM;
41c445ff
JB		 5848}
5849
5850/**
5851 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5852 * @pf: board private structure
5853 * @vectors: the number of MSI-X vectors to request
5854 *
5855 * Returns the number of vectors reserved, or error
5856 **/
5857static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5858{
7b37f376
AG		 5859 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
5860 I40E_MIN_MSIX, vectors);
5861 if (vectors < 0) {
41c445ff 5862 dev_info(&pf->pdev->dev,
7b37f376 5863 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 5864 vectors = 0;
5865 }
5866
7b37f376
AG		 5867 pf->num_msix_entries = vectors;
5868
41c445ff
JB		 5869 return vectors;
5870}
5871
5872/**
5873 * i40e_init_msix - Setup the MSIX capability
5874 * @pf: board private structure
5875 *
5876 * Work with the OS to set up the MSIX vectors needed.
5877 *
5878 * Returns 0 on success, negative on failure
5879 **/
5880static int i40e_init_msix(struct i40e_pf *pf)
5881{
5882 i40e_status err = 0;
5883 struct i40e_hw *hw = &pf->hw;
5884 int v_budget, i;
5885 int vec;
5886
5887 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5888 return -ENODEV;
5889
5890 /* The number of vectors we'll request will be comprised of:
5891 * - Add 1 for "other" cause for Admin Queue events, etc.
5892 * - The number of LAN queue pairs
f8ff1464
ASJ		 5893 * - Queues being used for RSS.
5894 * We don't need as many as max_rss_size vectors.
5895 * use rss_size instead in the calculation since that
5896 * is governed by number of cpus in the system.
5897 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5898 * - The number of VMDq pairs
5899 * Once we count this up, try the request.
5900 *
5901 * If we can't get what we want, we'll simplify to nearly nothing
5902 * and try again. If that still fails, we punt.
5903 */
f8ff1464 5904 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5905 pf->num_vmdq_msix = pf->num_vmdq_qps;
5906 v_budget = 1 + pf->num_lan_msix;
5907 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 5908 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 5909 v_budget++;
5910
5911 /* Scale down if necessary, and the rings will share vectors */
5912 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5913
5914 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5915 GFP_KERNEL);
5916 if (!pf->msix_entries)
5917 return -ENOMEM;
5918
5919 for (i = 0; i < v_budget; i++)
5920 pf->msix_entries[i].entry = i;
5921 vec = i40e_reserve_msix_vectors(pf, v_budget);
5922 if (vec < I40E_MIN_MSIX) {
5923 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5924 kfree(pf->msix_entries);
5925 pf->msix_entries = NULL;
5926 return -ENODEV;
5927
5928 } else if (vec == I40E_MIN_MSIX) {
5929 /* Adjust for minimal MSIX use */
5930 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5931 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5932 pf->num_vmdq_vsis = 0;
5933 pf->num_vmdq_qps = 0;
5934 pf->num_vmdq_msix = 0;
5935 pf->num_lan_qps = 1;
5936 pf->num_lan_msix = 1;
5937
5938 } else if (vec != v_budget) {
5939 /* Scale vector usage down */
5940 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5941 vec--; /* reserve the misc vector */
5942
5943 /* partition out the remaining vectors */
5944 switch (vec) {
5945 case 2:
5946 pf->num_vmdq_vsis = 1;
5947 pf->num_lan_msix = 1;
5948 break;
5949 case 3:
5950 pf->num_vmdq_vsis = 1;
5951 pf->num_lan_msix = 2;
5952 break;
5953 default:
5954 pf->num_lan_msix = min_t(int, (vec / 2),
5955 pf->num_lan_qps);
5956 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5957 I40E_DEFAULT_NUM_VMDQ_VSI);
5958 break;
5959 }
5960 }
5961
5962 return err;
5963}
5964
493fb300
AD		 5965/**
5966 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5967 * @vsi: the VSI being configured
5968 * @v_idx: index of the vector in the vsi struct
5969 *
5970 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5971 **/
5972static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5973{
5974 struct i40e_q_vector *q_vector;
5975
5976 /* allocate q_vector */
5977 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5978 if (!q_vector)
5979 return -ENOMEM;
5980
5981 q_vector->vsi = vsi;
5982 q_vector->v_idx = v_idx;
5983 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5984 if (vsi->netdev)
5985 netif_napi_add(vsi->netdev, &q_vector->napi,
5986 i40e_napi_poll, vsi->work_limit);
5987
cd0b6fa6
AD		 5988 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5989 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5990
493fb300
AD		 5991 /* tie q_vector and vsi together */
5992 vsi->q_vectors[v_idx] = q_vector;
5993
5994 return 0;
5995}
5996
41c445ff
JB		 5997/**
5998 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5999 * @vsi: the VSI being configured
6000 *
6001 * We allocate one q_vector per queue interrupt. If allocation fails we
6002 * return -ENOMEM.
6003 **/
6004static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
6005{
6006 struct i40e_pf *pf = vsi->back;
6007 int v_idx, num_q_vectors;
493fb300 6008 int err;
41c445ff
JB		 6009
6010 /* if not MSIX, give the one vector only to the LAN VSI */
6011 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6012 num_q_vectors = vsi->num_q_vectors;
6013 else if (vsi == pf->vsi[pf->lan_vsi])
6014 num_q_vectors = 1;
6015 else
6016 return -EINVAL;
6017
41c445ff 6018 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 6019 err = i40e_alloc_q_vector(vsi, v_idx);
6020 if (err)
6021 goto err_out;
41c445ff
JB		 6022 }
6023
6024 return 0;
493fb300
AD		 6025
6026err_out:
6027 while (v_idx--)
6028 i40e_free_q_vector(vsi, v_idx);
6029
6030 return err;
41c445ff
JB		 6031}
6032
6033/**
6034 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6035 * @pf: board private structure to initialize
6036 **/
6037static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6038{
6039 int err = 0;
6040
6041 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6042 err = i40e_init_msix(pf);
6043 if (err) {
60ea5f83
JB		 6044 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6045 I40E_FLAG_RSS_ENABLED |
6046 I40E_FLAG_DCB_ENABLED |
6047 I40E_FLAG_SRIOV_ENABLED |
6048 I40E_FLAG_FD_SB_ENABLED |
6049 I40E_FLAG_FD_ATR_ENABLED |
6050 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6051
6052 /* rework the queue expectations without MSIX */
6053 i40e_determine_queue_usage(pf);
6054 }
6055 }
6056
6057 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6058 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 6059 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 6060 err = pci_enable_msi(pf->pdev);
6061 if (err) {
958a3e3b 6062 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6063 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6064 }
6065 }
6066
958a3e3b
SN		 6067 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
6068 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
6069
41c445ff
JB		 6070 /* track first vector for misc interrupts */
6071 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6072}
6073
6074/**
6075 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6076 * @pf: board private structure
6077 *
6078 * This sets up the handler for MSIX 0, which is used to manage the
6079 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6080 * when in MSI or Legacy interrupt mode.
6081 **/
6082static int i40e_setup_misc_vector(struct i40e_pf *pf)
6083{
6084 struct i40e_hw *hw = &pf->hw;
6085 int err = 0;
6086
6087 /* Only request the irq if this is the first time through, and
6088 * not when we're rebuilding after a Reset
6089 */
6090 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6091 err = request_irq(pf->msix_entries[0].vector,
6092 i40e_intr, 0, pf->misc_int_name, pf);
6093 if (err) {
6094 dev_info(&pf->pdev->dev,
6095 "request_irq for msix_misc failed: %d\n", err);
6096 return -EFAULT;
6097 }
6098 }
6099
6100 i40e_enable_misc_int_causes(hw);
6101
6102 /* associate no queues to the misc vector */
6103 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6104 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6105
6106 i40e_flush(hw);
6107
6108 i40e_irq_dynamic_enable_icr0(pf);
6109
6110 return err;
6111}
6112
6113/**
6114 * i40e_config_rss - Prepare for RSS if used
6115 * @pf: board private structure
6116 **/
6117static int i40e_config_rss(struct i40e_pf *pf)
6118{
41c445ff
JB		 6119 /* Set of random keys generated using kernel random number generator */
6120 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6121 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6122 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6123 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6124 struct i40e_hw *hw = &pf->hw;
6125 u32 lut = 0;
6126 int i, j;
6127 u64 hena;
41c445ff
JB		 6128
6129 /* Fill out hash function seed */
6130 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6131 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6132
6133 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6134 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6135 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6136 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6137 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6138 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6139
6140 /* Populate the LUT with max no. of queues in round robin fashion */
6141 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6142
6143 /* The assumption is that lan qp count will be the highest
6144 * qp count for any PF VSI that needs RSS.
6145 * If multiple VSIs need RSS support, all the qp counts
6146 * for those VSIs should be a power of 2 for RSS to work.
6147 * If LAN VSI is the only consumer for RSS then this requirement
6148 * is not necessary.
6149 */
6150 if (j == pf->rss_size)
6151 j = 0;
6152 /* lut = 4-byte sliding window of 4 lut entries */
6153 lut = (lut << 8) | (j &
6154 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6155 /* On i = 3, we have 4 entries in lut; write to the register */
6156 if ((i & 3) == 3)
6157 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6158 }
6159 i40e_flush(hw);
6160
6161 return 0;
6162}
6163
f8ff1464
ASJ		 6164/**
6165 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6166 * @pf: board private structure
6167 * @queue_count: the requested queue count for rss.
6168 *
6169 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6170 * count which may be different from the requested queue count.
6171 **/
6172int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6173{
6174 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6175 return 0;
6176
6177 queue_count = min_t(int, queue_count, pf->rss_size_max);
6178 queue_count = rounddown_pow_of_two(queue_count);
6179
6180 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6181 i40e_prep_for_reset(pf);
6182
f8ff1464
ASJ		 6183 pf->rss_size = queue_count;
6184
6185 i40e_reset_and_rebuild(pf, true);
6186 i40e_config_rss(pf);
6187 }
6188 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6189 return pf->rss_size;
6190}
6191
41c445ff
JB		 6192/**
6193 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6194 * @pf: board private structure to initialize
6195 *
6196 * i40e_sw_init initializes the Adapter private data structure.
6197 * Fields are initialized based on PCI device information and
6198 * OS network device settings (MTU size).
6199 **/
6200static int i40e_sw_init(struct i40e_pf *pf)
6201{
6202 int err = 0;
6203 int size;
6204
6205 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6206 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6207 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6208 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6209 if (I40E_DEBUG_USER & debug)
6210 pf->hw.debug_mask = debug;
6211 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6212 I40E_DEFAULT_MSG_ENABLE);
6213 }
6214
6215 /* Set default capability flags */
6216 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6217 I40E_FLAG_MSI_ENABLED |
6218 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6219 I40E_FLAG_RX_1BUF_ENABLED;
6220
7134f9ce
JB		 6221 /* Depending on PF configurations, it is possible that the RSS
6222 * maximum might end up larger than the available queues
6223 */
41c445ff 6224 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6225 pf->rss_size_max = min_t(int, pf->rss_size_max,
6226 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6227 if (pf->hw.func_caps.rss) {
6228 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6229 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6230 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6231 } else {
6232 pf->rss_size = 1;
6233 }
6234
2050bc65
CS		 6235 /* MFP mode enabled */
6236 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6237 pf->flags |= I40E_FLAG_MFP_ENABLED;
6238 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6239 }
6240
cbf61325
ASJ		 6241 /* FW/NVM is not yet fixed in this regard */
6242 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6243 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6244 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6245 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6246 dev_info(&pf->pdev->dev,
6247 "Flow Director ATR mode Enabled\n");
6248 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6249 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 6250 dev_info(&pf->pdev->dev,
6251 "Flow Director Side Band mode Enabled\n");
cbf61325
ASJ		 6252 } else {
6253 dev_info(&pf->pdev->dev,
6254 "Flow Director Side Band mode Disabled in MFP mode\n");
41c445ff 6255 }
cbf61325
ASJ		 6256 pf->fdir_pf_filter_count =
6257 pf->hw.func_caps.fd_filters_guaranteed;
6258 pf->hw.fdir_shared_filter_count =
6259 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6260 }
6261
6262 if (pf->hw.func_caps.vmdq) {
6263 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6264 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6265 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6266 }
6267
41c445ff
JB		 6268#ifdef CONFIG_PCI_IOV
6269 if (pf->hw.func_caps.num_vfs) {
6270 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6271 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6272 pf->num_req_vfs = min_t(int,
6273 pf->hw.func_caps.num_vfs,
6274 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 6275 dev_info(&pf->pdev->dev,
6276 "Number of VFs being requested for PF[%d] = %d\n",
6277 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 6278 }
6279#endif /* CONFIG_PCI_IOV */
6280 pf->eeprom_version = 0xDEAD;
6281 pf->lan_veb = I40E_NO_VEB;
6282 pf->lan_vsi = I40E_NO_VSI;
6283
6284 /* set up queue assignment tracking */
6285 size = sizeof(struct i40e_lump_tracking)
6286 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6287 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6288 if (!pf->qp_pile) {
6289 err = -ENOMEM;
6290 goto sw_init_done;
6291 }
6292 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6293 pf->qp_pile->search_hint = 0;
6294
6295 /* set up vector assignment tracking */
6296 size = sizeof(struct i40e_lump_tracking)
6297 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6298 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6299 if (!pf->irq_pile) {
6300 kfree(pf->qp_pile);
6301 err = -ENOMEM;
6302 goto sw_init_done;
6303 }
6304 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6305 pf->irq_pile->search_hint = 0;
6306
6307 mutex_init(&pf->switch_mutex);
6308
6309sw_init_done:
6310 return err;
6311}
6312
6313/**
6314 * i40e_set_features - set the netdev feature flags
6315 * @netdev: ptr to the netdev being adjusted
6316 * @features: the feature set that the stack is suggesting
6317 **/
6318static int i40e_set_features(struct net_device *netdev,
6319 netdev_features_t features)
6320{
6321 struct i40e_netdev_priv *np = netdev_priv(netdev);
6322 struct i40e_vsi *vsi = np->vsi;
6323
6324 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6325 i40e_vlan_stripping_enable(vsi);
6326 else
6327 i40e_vlan_stripping_disable(vsi);
6328
6329 return 0;
6330}
6331
a1c9a9d9
JK		 6332#ifdef CONFIG_I40E_VXLAN
6333/**
6334 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6335 * @pf: board private structure
6336 * @port: The UDP port to look up
6337 *
6338 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6339 **/
6340static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6341{
6342 u8 i;
6343
6344 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6345 if (pf->vxlan_ports[i] == port)
6346 return i;
6347 }
6348
6349 return i;
6350}
6351
6352/**
6353 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6354 * @netdev: This physical port's netdev
6355 * @sa_family: Socket Family that VXLAN is notifying us about
6356 * @port: New UDP port number that VXLAN started listening to
6357 **/
6358static void i40e_add_vxlan_port(struct net_device *netdev,
6359 sa_family_t sa_family, __be16 port)
6360{
6361 struct i40e_netdev_priv *np = netdev_priv(netdev);
6362 struct i40e_vsi *vsi = np->vsi;
6363 struct i40e_pf *pf = vsi->back;
6364 u8 next_idx;
6365 u8 idx;
6366
6367 if (sa_family == AF_INET6)
6368 return;
6369
6370 idx = i40e_get_vxlan_port_idx(pf, port);
6371
6372 /* Check if port already exists */
6373 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6374 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6375 return;
6376 }
6377
6378 /* Now check if there is space to add the new port */
6379 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6380
6381 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6382 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6383 ntohs(port));
6384 return;
6385 }
6386
6387 /* New port: add it and mark its index in the bitmap */
6388 pf->vxlan_ports[next_idx] = port;
6389 pf->pending_vxlan_bitmap |= (1 << next_idx);
6390
6391 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6392}
6393
6394/**
6395 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6396 * @netdev: This physical port's netdev
6397 * @sa_family: Socket Family that VXLAN is notifying us about
6398 * @port: UDP port number that VXLAN stopped listening to
6399 **/
6400static void i40e_del_vxlan_port(struct net_device *netdev,
6401 sa_family_t sa_family, __be16 port)
6402{
6403 struct i40e_netdev_priv *np = netdev_priv(netdev);
6404 struct i40e_vsi *vsi = np->vsi;
6405 struct i40e_pf *pf = vsi->back;
6406 u8 idx;
6407
6408 if (sa_family == AF_INET6)
6409 return;
6410
6411 idx = i40e_get_vxlan_port_idx(pf, port);
6412
6413 /* Check if port already exists */
6414 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6415 /* if port exists, set it to 0 (mark for deletion)
6416 * and make it pending
6417 */
6418 pf->vxlan_ports[idx] = 0;
6419
6420 pf->pending_vxlan_bitmap |= (1 << idx);
6421
6422 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6423 } else {
6424 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6425 ntohs(port));
6426 }
6427}
6428
6429#endif
41c445ff
JB		 6430static const struct net_device_ops i40e_netdev_ops = {
6431 .ndo_open = i40e_open,
6432 .ndo_stop = i40e_close,
6433 .ndo_start_xmit = i40e_lan_xmit_frame,
6434 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6435 .ndo_set_rx_mode = i40e_set_rx_mode,
6436 .ndo_validate_addr = eth_validate_addr,
6437 .ndo_set_mac_address = i40e_set_mac,
6438 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6439 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6440 .ndo_tx_timeout = i40e_tx_timeout,
6441 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6442 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6443#ifdef CONFIG_NET_POLL_CONTROLLER
6444 .ndo_poll_controller = i40e_netpoll,
6445#endif
6446 .ndo_setup_tc = i40e_setup_tc,
6447 .ndo_set_features = i40e_set_features,
6448 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6449 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6450 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6451 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6452#ifdef CONFIG_I40E_VXLAN
6453 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6454 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6455#endif
41c445ff
JB		 6456};
6457
6458/**
6459 * i40e_config_netdev - Setup the netdev flags
6460 * @vsi: the VSI being configured
6461 *
6462 * Returns 0 on success, negative value on failure
6463 **/
6464static int i40e_config_netdev(struct i40e_vsi *vsi)
6465{
1a10370a 6466 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6467 struct i40e_pf *pf = vsi->back;
6468 struct i40e_hw *hw = &pf->hw;
6469 struct i40e_netdev_priv *np;
6470 struct net_device *netdev;
6471 u8 mac_addr[ETH_ALEN];
6472 int etherdev_size;
6473
6474 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6475 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6476 if (!netdev)
6477 return -ENOMEM;
6478
6479 vsi->netdev = netdev;
6480 np = netdev_priv(netdev);
6481 np->vsi = vsi;
6482
6483 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6484 NETIF_F_GSO_UDP_TUNNEL |
6485 NETIF_F_TSO |
6486 NETIF_F_SG;
6487
6488 netdev->features = NETIF_F_SG |
6489 NETIF_F_IP_CSUM |
6490 NETIF_F_SCTP_CSUM |
6491 NETIF_F_HIGHDMA |
6492 NETIF_F_GSO_UDP_TUNNEL |
6493 NETIF_F_HW_VLAN_CTAG_TX |
6494 NETIF_F_HW_VLAN_CTAG_RX |
6495 NETIF_F_HW_VLAN_CTAG_FILTER |
6496 NETIF_F_IPV6_CSUM |
6497 NETIF_F_TSO |
6498 NETIF_F_TSO6 |
6499 NETIF_F_RXCSUM |
6500 NETIF_F_RXHASH |
6501 0;
6502
6503 /* copy netdev features into list of user selectable features */
6504 netdev->hw_features |= netdev->features;
6505
6506 if (vsi->type == I40E_VSI_MAIN) {
6507 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6508 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6509 } else {
6510 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6511 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6512 pf->vsi[pf->lan_vsi]->netdev->name);
6513 random_ether_addr(mac_addr);
6514 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6515 }
1a10370a 6516 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6517
6518 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6519 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6520 /* vlan gets same features (except vlan offload)
6521 * after any tweaks for specific VSI types
6522 */
6523 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6524 NETIF_F_HW_VLAN_CTAG_RX |
6525 NETIF_F_HW_VLAN_CTAG_FILTER);
6526 netdev->priv_flags |= IFF_UNICAST_FLT;
6527 netdev->priv_flags |= IFF_SUPP_NOFCS;
6528 /* Setup netdev TC information */
6529 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6530
6531 netdev->netdev_ops = &i40e_netdev_ops;
6532 netdev->watchdog_timeo = 5 * HZ;
6533 i40e_set_ethtool_ops(netdev);
6534
6535 return 0;
6536}
6537
6538/**
6539 * i40e_vsi_delete - Delete a VSI from the switch
6540 * @vsi: the VSI being removed
6541 *
6542 * Returns 0 on success, negative value on failure
6543 **/
6544static void i40e_vsi_delete(struct i40e_vsi *vsi)
6545{
6546 /* remove default VSI is not allowed */
6547 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6548 return;
6549
41c445ff
JB		 6550 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6551 return;
6552}
6553
6554/**
6555 * i40e_add_vsi - Add a VSI to the switch
6556 * @vsi: the VSI being configured
6557 *
6558 * This initializes a VSI context depending on the VSI type to be added and
6559 * passes it down to the add_vsi aq command.
6560 **/
6561static int i40e_add_vsi(struct i40e_vsi *vsi)
6562{
6563 int ret = -ENODEV;
6564 struct i40e_mac_filter *f, *ftmp;
6565 struct i40e_pf *pf = vsi->back;
6566 struct i40e_hw *hw = &pf->hw;
6567 struct i40e_vsi_context ctxt;
6568 u8 enabled_tc = 0x1; /* TC0 enabled */
6569 int f_count = 0;
6570
6571 memset(&ctxt, 0, sizeof(ctxt));
6572 switch (vsi->type) {
6573 case I40E_VSI_MAIN:
6574 /* The PF's main VSI is already setup as part of the
6575 * device initialization, so we'll not bother with
6576 * the add_vsi call, but we will retrieve the current
6577 * VSI context.
6578 */
6579 ctxt.seid = pf->main_vsi_seid;
6580 ctxt.pf_num = pf->hw.pf_id;
6581 ctxt.vf_num = 0;
6582 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6583 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6584 if (ret) {
6585 dev_info(&pf->pdev->dev,
6586 "couldn't get pf vsi config, err %d, aq_err %d\n",
6587 ret, pf->hw.aq.asq_last_status);
6588 return -ENOENT;
6589 }
6590 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6591 vsi->info.valid_sections = 0;
6592
6593 vsi->seid = ctxt.seid;
6594 vsi->id = ctxt.vsi_number;
6595
6596 enabled_tc = i40e_pf_get_tc_map(pf);
6597
6598 /* MFP mode setup queue map and update VSI */
6599 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6600 memset(&ctxt, 0, sizeof(ctxt));
6601 ctxt.seid = pf->main_vsi_seid;
6602 ctxt.pf_num = pf->hw.pf_id;
6603 ctxt.vf_num = 0;
6604 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6605 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6606 if (ret) {
6607 dev_info(&pf->pdev->dev,
6608 "update vsi failed, aq_err=%d\n",
6609 pf->hw.aq.asq_last_status);
6610 ret = -ENOENT;
6611 goto err;
6612 }
6613 /* update the local VSI info queue map */
6614 i40e_vsi_update_queue_map(vsi, &ctxt);
6615 vsi->info.valid_sections = 0;
6616 } else {
6617 /* Default/Main VSI is only enabled for TC0
6618 * reconfigure it to enable all TCs that are
6619 * available on the port in SFP mode.
6620 */
6621 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6622 if (ret) {
6623 dev_info(&pf->pdev->dev,
6624 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6625 enabled_tc, ret,
6626 pf->hw.aq.asq_last_status);
6627 ret = -ENOENT;
6628 }
6629 }
6630 break;
6631
6632 case I40E_VSI_FDIR:
cbf61325
ASJ		 6633 ctxt.pf_num = hw->pf_id;
6634 ctxt.vf_num = 0;
6635 ctxt.uplink_seid = vsi->uplink_seid;
6636 ctxt.connection_type = 0x1; /* regular data port */
6637 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6638 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6639 break;
6640
6641 case I40E_VSI_VMDQ2:
6642 ctxt.pf_num = hw->pf_id;
6643 ctxt.vf_num = 0;
6644 ctxt.uplink_seid = vsi->uplink_seid;
6645 ctxt.connection_type = 0x1; /* regular data port */
6646 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6647
6648 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6649
6650 /* This VSI is connected to VEB so the switch_id
6651 * should be set to zero by default.
6652 */
6653 ctxt.info.switch_id = 0;
6654 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6655 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6656
6657 /* Setup the VSI tx/rx queue map for TC0 only for now */
6658 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6659 break;
6660
6661 case I40E_VSI_SRIOV:
6662 ctxt.pf_num = hw->pf_id;
6663 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6664 ctxt.uplink_seid = vsi->uplink_seid;
6665 ctxt.connection_type = 0x1; /* regular data port */
6666 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6667
6668 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6669
6670 /* This VSI is connected to VEB so the switch_id
6671 * should be set to zero by default.
6672 */
6673 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6674
6675 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6676 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6677 /* Setup the VSI tx/rx queue map for TC0 only for now */
6678 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6679 break;
6680
6681 default:
6682 return -ENODEV;
6683 }
6684
6685 if (vsi->type != I40E_VSI_MAIN) {
6686 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6687 if (ret) {
6688 dev_info(&vsi->back->pdev->dev,
6689 "add vsi failed, aq_err=%d\n",
6690 vsi->back->hw.aq.asq_last_status);
6691 ret = -ENOENT;
6692 goto err;
6693 }
6694 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6695 vsi->info.valid_sections = 0;
6696 vsi->seid = ctxt.seid;
6697 vsi->id = ctxt.vsi_number;
6698 }
6699
6700 /* If macvlan filters already exist, force them to get loaded */
6701 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6702 f->changed = true;
6703 f_count++;
6704 }
6705 if (f_count) {
6706 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6707 pf->flags |= I40E_FLAG_FILTER_SYNC;
6708 }
6709
6710 /* Update VSI BW information */
6711 ret = i40e_vsi_get_bw_info(vsi);
6712 if (ret) {
6713 dev_info(&pf->pdev->dev,
6714 "couldn't get vsi bw info, err %d, aq_err %d\n",
6715 ret, pf->hw.aq.asq_last_status);
6716 /* VSI is already added so not tearing that up */
6717 ret = 0;
6718 }
6719
6720err:
6721 return ret;
6722}
6723
6724/**
6725 * i40e_vsi_release - Delete a VSI and free its resources
6726 * @vsi: the VSI being removed
6727 *
6728 * Returns 0 on success or < 0 on error
6729 **/
6730int i40e_vsi_release(struct i40e_vsi *vsi)
6731{
6732 struct i40e_mac_filter *f, *ftmp;
6733 struct i40e_veb *veb = NULL;
6734 struct i40e_pf *pf;
6735 u16 uplink_seid;
6736 int i, n;
6737
6738 pf = vsi->back;
6739
6740 /* release of a VEB-owner or last VSI is not allowed */
6741 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6742 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6743 vsi->seid, vsi->uplink_seid);
6744 return -ENODEV;
6745 }
6746 if (vsi == pf->vsi[pf->lan_vsi] &&
6747 !test_bit(__I40E_DOWN, &pf->state)) {
6748 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6749 return -ENODEV;
6750 }
6751
6752 uplink_seid = vsi->uplink_seid;
6753 if (vsi->type != I40E_VSI_SRIOV) {
6754 if (vsi->netdev_registered) {
6755 vsi->netdev_registered = false;
6756 if (vsi->netdev) {
6757 /* results in a call to i40e_close() */
6758 unregister_netdev(vsi->netdev);
6759 free_netdev(vsi->netdev);
6760 vsi->netdev = NULL;
6761 }
6762 } else {
6763 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6764 i40e_down(vsi);
6765 i40e_vsi_free_irq(vsi);
6766 i40e_vsi_free_tx_resources(vsi);
6767 i40e_vsi_free_rx_resources(vsi);
6768 }
6769 i40e_vsi_disable_irq(vsi);
6770 }
6771
6772 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6773 i40e_del_filter(vsi, f->macaddr, f->vlan,
6774 f->is_vf, f->is_netdev);
6775 i40e_sync_vsi_filters(vsi);
6776
6777 i40e_vsi_delete(vsi);
6778 i40e_vsi_free_q_vectors(vsi);
6779 i40e_vsi_clear_rings(vsi);
6780 i40e_vsi_clear(vsi);
6781
6782 /* If this was the last thing on the VEB, except for the
6783 * controlling VSI, remove the VEB, which puts the controlling
6784 * VSI onto the next level down in the switch.
6785 *
6786 * Well, okay, there's one more exception here: don't remove
6787 * the orphan VEBs yet. We'll wait for an explicit remove request
6788 * from up the network stack.
6789 */
6790 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6791 if (pf->vsi[i] &&
6792 pf->vsi[i]->uplink_seid == uplink_seid &&
6793 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6794 n++; /* count the VSIs */
6795 }
6796 }
6797 for (i = 0; i < I40E_MAX_VEB; i++) {
6798 if (!pf->veb[i])
6799 continue;
6800 if (pf->veb[i]->uplink_seid == uplink_seid)
6801 n++; /* count the VEBs */
6802 if (pf->veb[i]->seid == uplink_seid)
6803 veb = pf->veb[i];
6804 }
6805 if (n == 0 && veb && veb->uplink_seid != 0)
6806 i40e_veb_release(veb);
6807
6808 return 0;
6809}
6810
6811/**
6812 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6813 * @vsi: ptr to the VSI
6814 *
6815 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6816 * corresponding SW VSI structure and initializes num_queue_pairs for the
6817 * newly allocated VSI.
6818 *
6819 * Returns 0 on success or negative on failure
6820 **/
6821static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6822{
6823 int ret = -ENOENT;
6824 struct i40e_pf *pf = vsi->back;
6825
493fb300 6826 if (vsi->q_vectors[0]) {
41c445ff
JB		 6827 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6828 vsi->seid);
6829 return -EEXIST;
6830 }
6831
6832 if (vsi->base_vector) {
6833 dev_info(&pf->pdev->dev,
6834 "VSI %d has non-zero base vector %d\n",
6835 vsi->seid, vsi->base_vector);
6836 return -EEXIST;
6837 }
6838
6839 ret = i40e_alloc_q_vectors(vsi);
6840 if (ret) {
6841 dev_info(&pf->pdev->dev,
6842 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6843 vsi->num_q_vectors, vsi->seid, ret);
6844 vsi->num_q_vectors = 0;
6845 goto vector_setup_out;
6846 }
6847
958a3e3b
SN		 6848 if (vsi->num_q_vectors)
6849 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6850 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6851 if (vsi->base_vector < 0) {
6852 dev_info(&pf->pdev->dev,
6853 "failed to get q tracking for VSI %d, err=%d\n",
6854 vsi->seid, vsi->base_vector);
6855 i40e_vsi_free_q_vectors(vsi);
6856 ret = -ENOENT;
6857 goto vector_setup_out;
6858 }
6859
6860vector_setup_out:
6861 return ret;
6862}
6863
bc7d338f
ASJ		 6864/**
6865 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6866 * @vsi: pointer to the vsi.
6867 *
6868 * This re-allocates a vsi's queue resources.
6869 *
6870 * Returns pointer to the successfully allocated and configured VSI sw struct
6871 * on success, otherwise returns NULL on failure.
6872 **/
6873static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6874{
6875 struct i40e_pf *pf = vsi->back;
6876 u8 enabled_tc;
6877 int ret;
6878
6879 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6880 i40e_vsi_clear_rings(vsi);
6881
6882 i40e_vsi_free_arrays(vsi, false);
6883 i40e_set_num_rings_in_vsi(vsi);
6884 ret = i40e_vsi_alloc_arrays(vsi, false);
6885 if (ret)
6886 goto err_vsi;
6887
6888 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6889 if (ret < 0) {
6890 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6891 vsi->seid, ret);
6892 goto err_vsi;
6893 }
6894 vsi->base_queue = ret;
6895
6896 /* Update the FW view of the VSI. Force a reset of TC and queue
6897 * layout configurations.
6898 */
6899 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6900 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6901 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6902 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6903
6904 /* assign it some queues */
6905 ret = i40e_alloc_rings(vsi);
6906 if (ret)
6907 goto err_rings;
6908
6909 /* map all of the rings to the q_vectors */
6910 i40e_vsi_map_rings_to_vectors(vsi);
6911 return vsi;
6912
6913err_rings:
6914 i40e_vsi_free_q_vectors(vsi);
6915 if (vsi->netdev_registered) {
6916 vsi->netdev_registered = false;
6917 unregister_netdev(vsi->netdev);
6918 free_netdev(vsi->netdev);
6919 vsi->netdev = NULL;
6920 }
6921 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6922err_vsi:
6923 i40e_vsi_clear(vsi);
6924 return NULL;
6925}
6926
41c445ff
JB		 6927/**
6928 * i40e_vsi_setup - Set up a VSI by a given type
6929 * @pf: board private structure
6930 * @type: VSI type
6931 * @uplink_seid: the switch element to link to
6932 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6933 *
6934 * This allocates the sw VSI structure and its queue resources, then add a VSI
6935 * to the identified VEB.
6936 *
6937 * Returns pointer to the successfully allocated and configure VSI sw struct on
6938 * success, otherwise returns NULL on failure.
6939 **/
6940struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6941 u16 uplink_seid, u32 param1)
6942{
6943 struct i40e_vsi *vsi = NULL;
6944 struct i40e_veb *veb = NULL;
6945 int ret, i;
6946 int v_idx;
6947
6948 /* The requested uplink_seid must be either
6949 * - the PF's port seid
6950 * no VEB is needed because this is the PF
6951 * or this is a Flow Director special case VSI
6952 * - seid of an existing VEB
6953 * - seid of a VSI that owns an existing VEB
6954 * - seid of a VSI that doesn't own a VEB
6955 * a new VEB is created and the VSI becomes the owner
6956 * - seid of the PF VSI, which is what creates the first VEB
6957 * this is a special case of the previous
6958 *
6959 * Find which uplink_seid we were given and create a new VEB if needed
6960 */
6961 for (i = 0; i < I40E_MAX_VEB; i++) {
6962 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6963 veb = pf->veb[i];
6964 break;
6965 }
6966 }
6967
6968 if (!veb && uplink_seid != pf->mac_seid) {
6969
6970 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6971 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6972 vsi = pf->vsi[i];
6973 break;
6974 }
6975 }
6976 if (!vsi) {
6977 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6978 uplink_seid);
6979 return NULL;
6980 }
6981
6982 if (vsi->uplink_seid == pf->mac_seid)
6983 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6984 vsi->tc_config.enabled_tc);
6985 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6986 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6987 vsi->tc_config.enabled_tc);
6988
6989 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6990 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6991 veb = pf->veb[i];
6992 }
6993 if (!veb) {
6994 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6995 return NULL;
6996 }
6997
6998 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6999 uplink_seid = veb->seid;
7000 }
7001
7002 /* get vsi sw struct */
7003 v_idx = i40e_vsi_mem_alloc(pf, type);
7004 if (v_idx < 0)
7005 goto err_alloc;
7006 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7007 if (!vsi)
7008 goto err_alloc;
41c445ff
JB		 7009 vsi->type = type;
7010 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7011
7012 if (type == I40E_VSI_MAIN)
7013 pf->lan_vsi = v_idx;
7014 else if (type == I40E_VSI_SRIOV)
7015 vsi->vf_id = param1;
7016 /* assign it some queues */
cbf61325
ASJ		 7017 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7018 vsi->idx);
41c445ff
JB		 7019 if (ret < 0) {
7020 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7021 vsi->seid, ret);
7022 goto err_vsi;
7023 }
7024 vsi->base_queue = ret;
7025
7026 /* get a VSI from the hardware */
7027 vsi->uplink_seid = uplink_seid;
7028 ret = i40e_add_vsi(vsi);
7029 if (ret)
7030 goto err_vsi;
7031
7032 switch (vsi->type) {
7033 /* setup the netdev if needed */
7034 case I40E_VSI_MAIN:
7035 case I40E_VSI_VMDQ2:
7036 ret = i40e_config_netdev(vsi);
7037 if (ret)
7038 goto err_netdev;
7039 ret = register_netdev(vsi->netdev);
7040 if (ret)
7041 goto err_netdev;
7042 vsi->netdev_registered = true;
7043 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7044#ifdef CONFIG_I40E_DCB
7045 /* Setup DCB netlink interface */
7046 i40e_dcbnl_setup(vsi);
7047#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7048 /* fall through */
7049
7050 case I40E_VSI_FDIR:
7051 /* set up vectors and rings if needed */
7052 ret = i40e_vsi_setup_vectors(vsi);
7053 if (ret)
7054 goto err_msix;
7055
7056 ret = i40e_alloc_rings(vsi);
7057 if (ret)
7058 goto err_rings;
7059
7060 /* map all of the rings to the q_vectors */
7061 i40e_vsi_map_rings_to_vectors(vsi);
7062
7063 i40e_vsi_reset_stats(vsi);
7064 break;
7065
7066 default:
7067 /* no netdev or rings for the other VSI types */
7068 break;
7069 }
7070
7071 return vsi;
7072
7073err_rings:
7074 i40e_vsi_free_q_vectors(vsi);
7075err_msix:
7076 if (vsi->netdev_registered) {
7077 vsi->netdev_registered = false;
7078 unregister_netdev(vsi->netdev);
7079 free_netdev(vsi->netdev);
7080 vsi->netdev = NULL;
7081 }
7082err_netdev:
7083 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7084err_vsi:
7085 i40e_vsi_clear(vsi);
7086err_alloc:
7087 return NULL;
7088}
7089
7090/**
7091 * i40e_veb_get_bw_info - Query VEB BW information
7092 * @veb: the veb to query
7093 *
7094 * Query the Tx scheduler BW configuration data for given VEB
7095 **/
7096static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7097{
7098 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7099 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7100 struct i40e_pf *pf = veb->pf;
7101 struct i40e_hw *hw = &pf->hw;
7102 u32 tc_bw_max;
7103 int ret = 0;
7104 int i;
7105
7106 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7107 &bw_data, NULL);
7108 if (ret) {
7109 dev_info(&pf->pdev->dev,
7110 "query veb bw config failed, aq_err=%d\n",
7111 hw->aq.asq_last_status);
7112 goto out;
7113 }
7114
7115 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7116 &ets_data, NULL);
7117 if (ret) {
7118 dev_info(&pf->pdev->dev,
7119 "query veb bw ets config failed, aq_err=%d\n",
7120 hw->aq.asq_last_status);
7121 goto out;
7122 }
7123
7124 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7125 veb->bw_max_quanta = ets_data.tc_bw_max;
7126 veb->is_abs_credits = bw_data.absolute_credits_enable;
7127 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7128 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7129 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7130 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7131 veb->bw_tc_limit_credits[i] =
7132 le16_to_cpu(bw_data.tc_bw_limits[i]);
7133 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7134 }
7135
7136out:
7137 return ret;
7138}
7139
7140/**
7141 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7142 * @pf: board private structure
7143 *
7144 * On error: returns error code (negative)
7145 * On success: returns vsi index in PF (positive)
7146 **/
7147static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7148{
7149 int ret = -ENOENT;
7150 struct i40e_veb *veb;
7151 int i;
7152
7153 /* Need to protect the allocation of switch elements at the PF level */
7154 mutex_lock(&pf->switch_mutex);
7155
7156 /* VEB list may be fragmented if VEB creation/destruction has
7157 * been happening. We can afford to do a quick scan to look
7158 * for any free slots in the list.
7159 *
7160 * find next empty veb slot, looping back around if necessary
7161 */
7162 i = 0;
7163 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7164 i++;
7165 if (i >= I40E_MAX_VEB) {
7166 ret = -ENOMEM;
7167 goto err_alloc_veb; /* out of VEB slots! */
7168 }
7169
7170 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7171 if (!veb) {
7172 ret = -ENOMEM;
7173 goto err_alloc_veb;
7174 }
7175 veb->pf = pf;
7176 veb->idx = i;
7177 veb->enabled_tc = 1;
7178
7179 pf->veb[i] = veb;
7180 ret = i;
7181err_alloc_veb:
7182 mutex_unlock(&pf->switch_mutex);
7183 return ret;
7184}
7185
7186/**
7187 * i40e_switch_branch_release - Delete a branch of the switch tree
7188 * @branch: where to start deleting
7189 *
7190 * This uses recursion to find the tips of the branch to be
7191 * removed, deleting until we get back to and can delete this VEB.
7192 **/
7193static void i40e_switch_branch_release(struct i40e_veb *branch)
7194{
7195 struct i40e_pf *pf = branch->pf;
7196 u16 branch_seid = branch->seid;
7197 u16 veb_idx = branch->idx;
7198 int i;
7199
7200 /* release any VEBs on this VEB - RECURSION */
7201 for (i = 0; i < I40E_MAX_VEB; i++) {
7202 if (!pf->veb[i])
7203 continue;
7204 if (pf->veb[i]->uplink_seid == branch->seid)
7205 i40e_switch_branch_release(pf->veb[i]);
7206 }
7207
7208 /* Release the VSIs on this VEB, but not the owner VSI.
7209 *
7210 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7211 * the VEB itself, so don't use (*branch) after this loop.
7212 */
7213 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7214 if (!pf->vsi[i])
7215 continue;
7216 if (pf->vsi[i]->uplink_seid == branch_seid &&
7217 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7218 i40e_vsi_release(pf->vsi[i]);
7219 }
7220 }
7221
7222 /* There's one corner case where the VEB might not have been
7223 * removed, so double check it here and remove it if needed.
7224 * This case happens if the veb was created from the debugfs
7225 * commands and no VSIs were added to it.
7226 */
7227 if (pf->veb[veb_idx])
7228 i40e_veb_release(pf->veb[veb_idx]);
7229}
7230
7231/**
7232 * i40e_veb_clear - remove veb struct
7233 * @veb: the veb to remove
7234 **/
7235static void i40e_veb_clear(struct i40e_veb *veb)
7236{
7237 if (!veb)
7238 return;
7239
7240 if (veb->pf) {
7241 struct i40e_pf *pf = veb->pf;
7242
7243 mutex_lock(&pf->switch_mutex);
7244 if (pf->veb[veb->idx] == veb)
7245 pf->veb[veb->idx] = NULL;
7246 mutex_unlock(&pf->switch_mutex);
7247 }
7248
7249 kfree(veb);
7250}
7251
7252/**
7253 * i40e_veb_release - Delete a VEB and free its resources
7254 * @veb: the VEB being removed
7255 **/
7256void i40e_veb_release(struct i40e_veb *veb)
7257{
7258 struct i40e_vsi *vsi = NULL;
7259 struct i40e_pf *pf;
7260 int i, n = 0;
7261
7262 pf = veb->pf;
7263
7264 /* find the remaining VSI and check for extras */
7265 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7266 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7267 n++;
7268 vsi = pf->vsi[i];
7269 }
7270 }
7271 if (n != 1) {
7272 dev_info(&pf->pdev->dev,
7273 "can't remove VEB %d with %d VSIs left\n",
7274 veb->seid, n);
7275 return;
7276 }
7277
7278 /* move the remaining VSI to uplink veb */
7279 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7280 if (veb->uplink_seid) {
7281 vsi->uplink_seid = veb->uplink_seid;
7282 if (veb->uplink_seid == pf->mac_seid)
7283 vsi->veb_idx = I40E_NO_VEB;
7284 else
7285 vsi->veb_idx = veb->veb_idx;
7286 } else {
7287 /* floating VEB */
7288 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7289 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7290 }
7291
7292 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7293 i40e_veb_clear(veb);
7294
7295 return;
7296}
7297
7298/**
7299 * i40e_add_veb - create the VEB in the switch
7300 * @veb: the VEB to be instantiated
7301 * @vsi: the controlling VSI
7302 **/
7303static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7304{
56747264 7305 bool is_default = false;
e1c51b95 7306 bool is_cloud = false;
41c445ff
JB		 7307 int ret;
7308
7309 /* get a VEB from the hardware */
7310 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7311 veb->enabled_tc, is_default,
7312 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7313 if (ret) {
7314 dev_info(&veb->pf->pdev->dev,
7315 "couldn't add VEB, err %d, aq_err %d\n",
7316 ret, veb->pf->hw.aq.asq_last_status);
7317 return -EPERM;
7318 }
7319
7320 /* get statistics counter */
7321 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7322 &veb->stats_idx, NULL, NULL, NULL);
7323 if (ret) {
7324 dev_info(&veb->pf->pdev->dev,
7325 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7326 ret, veb->pf->hw.aq.asq_last_status);
7327 return -EPERM;
7328 }
7329 ret = i40e_veb_get_bw_info(veb);
7330 if (ret) {
7331 dev_info(&veb->pf->pdev->dev,
7332 "couldn't get VEB bw info, err %d, aq_err %d\n",
7333 ret, veb->pf->hw.aq.asq_last_status);
7334 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7335 return -ENOENT;
7336 }
7337
7338 vsi->uplink_seid = veb->seid;
7339 vsi->veb_idx = veb->idx;
7340 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7341
7342 return 0;
7343}
7344
7345/**
7346 * i40e_veb_setup - Set up a VEB
7347 * @pf: board private structure
7348 * @flags: VEB setup flags
7349 * @uplink_seid: the switch element to link to
7350 * @vsi_seid: the initial VSI seid
7351 * @enabled_tc: Enabled TC bit-map
7352 *
7353 * This allocates the sw VEB structure and links it into the switch
7354 * It is possible and legal for this to be a duplicate of an already
7355 * existing VEB. It is also possible for both uplink and vsi seids
7356 * to be zero, in order to create a floating VEB.
7357 *
7358 * Returns pointer to the successfully allocated VEB sw struct on
7359 * success, otherwise returns NULL on failure.
7360 **/
7361struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7362 u16 uplink_seid, u16 vsi_seid,
7363 u8 enabled_tc)
7364{
7365 struct i40e_veb *veb, *uplink_veb = NULL;
7366 int vsi_idx, veb_idx;
7367 int ret;
7368
7369 /* if one seid is 0, the other must be 0 to create a floating relay */
7370 if ((uplink_seid == 0 || vsi_seid == 0) &&
7371 (uplink_seid + vsi_seid != 0)) {
7372 dev_info(&pf->pdev->dev,
7373 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7374 uplink_seid, vsi_seid);
7375 return NULL;
7376 }
7377
7378 /* make sure there is such a vsi and uplink */
7379 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7380 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7381 break;
7382 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7383 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7384 vsi_seid);
7385 return NULL;
7386 }
7387
7388 if (uplink_seid && uplink_seid != pf->mac_seid) {
7389 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7390 if (pf->veb[veb_idx] &&
7391 pf->veb[veb_idx]->seid == uplink_seid) {
7392 uplink_veb = pf->veb[veb_idx];
7393 break;
7394 }
7395 }
7396 if (!uplink_veb) {
7397 dev_info(&pf->pdev->dev,
7398 "uplink seid %d not found\n", uplink_seid);
7399 return NULL;
7400 }
7401 }
7402
7403 /* get veb sw struct */
7404 veb_idx = i40e_veb_mem_alloc(pf);
7405 if (veb_idx < 0)
7406 goto err_alloc;
7407 veb = pf->veb[veb_idx];
7408 veb->flags = flags;
7409 veb->uplink_seid = uplink_seid;
7410 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7411 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7412
7413 /* create the VEB in the switch */
7414 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7415 if (ret)
7416 goto err_veb;
7417
7418 return veb;
7419
7420err_veb:
7421 i40e_veb_clear(veb);
7422err_alloc:
7423 return NULL;
7424}
7425
7426/**
7427 * i40e_setup_pf_switch_element - set pf vars based on switch type
7428 * @pf: board private structure
7429 * @ele: element we are building info from
7430 * @num_reported: total number of elements
7431 * @printconfig: should we print the contents
7432 *
7433 * helper function to assist in extracting a few useful SEID values.
7434 **/
7435static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7436 struct i40e_aqc_switch_config_element_resp *ele,
7437 u16 num_reported, bool printconfig)
7438{
7439 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7440 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7441 u8 element_type = ele->element_type;
7442 u16 seid = le16_to_cpu(ele->seid);
7443
7444 if (printconfig)
7445 dev_info(&pf->pdev->dev,
7446 "type=%d seid=%d uplink=%d downlink=%d\n",
7447 element_type, seid, uplink_seid, downlink_seid);
7448
7449 switch (element_type) {
7450 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7451 pf->mac_seid = seid;
7452 break;
7453 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7454 /* Main VEB? */
7455 if (uplink_seid != pf->mac_seid)
7456 break;
7457 if (pf->lan_veb == I40E_NO_VEB) {
7458 int v;
7459
7460 /* find existing or else empty VEB */
7461 for (v = 0; v < I40E_MAX_VEB; v++) {
7462 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7463 pf->lan_veb = v;
7464 break;
7465 }
7466 }
7467 if (pf->lan_veb == I40E_NO_VEB) {
7468 v = i40e_veb_mem_alloc(pf);
7469 if (v < 0)
7470 break;
7471 pf->lan_veb = v;
7472 }
7473 }
7474
7475 pf->veb[pf->lan_veb]->seid = seid;
7476 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7477 pf->veb[pf->lan_veb]->pf = pf;
7478 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7479 break;
7480 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7481 if (num_reported != 1)
7482 break;
7483 /* This is immediately after a reset so we can assume this is
7484 * the PF's VSI
7485 */
7486 pf->mac_seid = uplink_seid;
7487 pf->pf_seid = downlink_seid;
7488 pf->main_vsi_seid = seid;
7489 if (printconfig)
7490 dev_info(&pf->pdev->dev,
7491 "pf_seid=%d main_vsi_seid=%d\n",
7492 pf->pf_seid, pf->main_vsi_seid);
7493 break;
7494 case I40E_SWITCH_ELEMENT_TYPE_PF:
7495 case I40E_SWITCH_ELEMENT_TYPE_VF:
7496 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7497 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7498 case I40E_SWITCH_ELEMENT_TYPE_PE:
7499 case I40E_SWITCH_ELEMENT_TYPE_PA:
7500 /* ignore these for now */
7501 break;
7502 default:
7503 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7504 element_type, seid);
7505 break;
7506 }
7507}
7508
7509/**
7510 * i40e_fetch_switch_configuration - Get switch config from firmware
7511 * @pf: board private structure
7512 * @printconfig: should we print the contents
7513 *
7514 * Get the current switch configuration from the device and
7515 * extract a few useful SEID values.
7516 **/
7517int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7518{
7519 struct i40e_aqc_get_switch_config_resp *sw_config;
7520 u16 next_seid = 0;
7521 int ret = 0;
7522 u8 *aq_buf;
7523 int i;
7524
7525 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7526 if (!aq_buf)
7527 return -ENOMEM;
7528
7529 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7530 do {
7531 u16 num_reported, num_total;
7532
7533 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7534 I40E_AQ_LARGE_BUF,
7535 &next_seid, NULL);
7536 if (ret) {
7537 dev_info(&pf->pdev->dev,
7538 "get switch config failed %d aq_err=%x\n",
7539 ret, pf->hw.aq.asq_last_status);
7540 kfree(aq_buf);
7541 return -ENOENT;
7542 }
7543
7544 num_reported = le16_to_cpu(sw_config->header.num_reported);
7545 num_total = le16_to_cpu(sw_config->header.num_total);
7546
7547 if (printconfig)
7548 dev_info(&pf->pdev->dev,
7549 "header: %d reported %d total\n",
7550 num_reported, num_total);
7551
7552 if (num_reported) {
7553 int sz = sizeof(*sw_config) * num_reported;
7554
7555 kfree(pf->sw_config);
7556 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7557 if (pf->sw_config)
7558 memcpy(pf->sw_config, sw_config, sz);
7559 }
7560
7561 for (i = 0; i < num_reported; i++) {
7562 struct i40e_aqc_switch_config_element_resp *ele =
7563 &sw_config->element[i];
7564
7565 i40e_setup_pf_switch_element(pf, ele, num_reported,
7566 printconfig);
7567 }
7568 } while (next_seid != 0);
7569
7570 kfree(aq_buf);
7571 return ret;
7572}
7573
7574/**
7575 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7576 * @pf: board private structure
bc7d338f 7577 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7578 *
7579 * Returns 0 on success, negative value on failure
7580 **/
bc7d338f 7581static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7582{
895106a5 7583 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7584 int ret;
7585
7586 /* find out what's out there already */
7587 ret = i40e_fetch_switch_configuration(pf, false);
7588 if (ret) {
7589 dev_info(&pf->pdev->dev,
7590 "couldn't fetch switch config, err %d, aq_err %d\n",
7591 ret, pf->hw.aq.asq_last_status);
7592 return ret;
7593 }
7594 i40e_pf_reset_stats(pf);
7595
41c445ff 7596 /* first time setup */
bc7d338f 7597 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7598 struct i40e_vsi *vsi = NULL;
7599 u16 uplink_seid;
7600
7601 /* Set up the PF VSI associated with the PF's main VSI
7602 * that is already in the HW switch
7603 */
7604 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7605 uplink_seid = pf->veb[pf->lan_veb]->seid;
7606 else
7607 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7608 if (pf->lan_vsi == I40E_NO_VSI)
7609 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7610 else if (reinit)
7611 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7612 if (!vsi) {
7613 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7614 i40e_fdir_teardown(pf);
7615 return -EAGAIN;
7616 }
41c445ff
JB		 7617 } else {
7618 /* force a reset of TC and queue layout configurations */
7619 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7620 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7621 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7622 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7623 }
7624 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7625
cbf61325
ASJ		 7626 i40e_fdir_sb_setup(pf);
7627
41c445ff
JB		 7628 /* Setup static PF queue filter control settings */
7629 ret = i40e_setup_pf_filter_control(pf);
7630 if (ret) {
7631 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7632 ret);
7633 /* Failure here should not stop continuing other steps */
7634 }
7635
7636 /* enable RSS in the HW, even for only one queue, as the stack can use
7637 * the hash
7638 */
7639 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7640 i40e_config_rss(pf);
7641
7642 /* fill in link information and enable LSE reporting */
7643 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7644 i40e_link_event(pf);
7645
d52c20b7 7646 /* Initialize user-specific link properties */
41c445ff
JB		 7647 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7648 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7649 /* requested_mode is set in probe or by ethtool */
7650 if (!pf->fc_autoneg_status)
7651 goto no_autoneg;
7652
7653 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7654 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7655 pf->hw.fc.current_mode = I40E_FC_FULL;
7656 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7657 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7658 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7659 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7660 else
d52c20b7
JB		 7661 pf->hw.fc.current_mode = I40E_FC_NONE;
7662
7663 /* sync the flow control settings with the auto-neg values */
7664 switch (pf->hw.fc.current_mode) {
7665 case I40E_FC_FULL:
7666 txfc = 1;
7667 rxfc = 1;
7668 break;
7669 case I40E_FC_TX_PAUSE:
7670 txfc = 1;
7671 rxfc = 0;
7672 break;
7673 case I40E_FC_RX_PAUSE:
7674 txfc = 0;
7675 rxfc = 1;
7676 break;
7677 case I40E_FC_NONE:
7678 case I40E_FC_DEFAULT:
7679 txfc = 0;
7680 rxfc = 0;
7681 break;
7682 case I40E_FC_PFC:
7683 /* TBD */
7684 break;
7685 /* no default case, we have to handle all possibilities here */
7686 }
7687
7688 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7689
7690 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7691 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7692 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7693
7694 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7695
d52c20b7
JB		 7696 goto fc_complete;
7697
7698no_autoneg:
7699 /* disable L2 flow control, user can turn it on if they wish */
7700 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7701 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7702 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7703
7704fc_complete:
beb0dff1
JK		 7705 i40e_ptp_init(pf);
7706
41c445ff
JB		 7707 return ret;
7708}
7709
41c445ff
JB		 7710/**
7711 * i40e_determine_queue_usage - Work out queue distribution
7712 * @pf: board private structure
7713 **/
7714static void i40e_determine_queue_usage(struct i40e_pf *pf)
7715{
41c445ff
JB		 7716 int queues_left;
7717
7718 pf->num_lan_qps = 0;
41c445ff
JB		 7719
7720 /* Find the max queues to be put into basic use. We'll always be
7721 * using TC0, whether or not DCB is running, and TC0 will get the
7722 * big RSS set.
7723 */
7724 queues_left = pf->hw.func_caps.num_tx_qp;
7725
cbf61325
ASJ		 7726 if ((queues_left == 1) ||
7727 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
7728 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
7729 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 7730 /* one qp for PF, no queues for anything else */
7731 queues_left = 0;
7732 pf->rss_size = pf->num_lan_qps = 1;
7733
7734 /* make sure all the fancies are disabled */
60ea5f83
JB		 7735 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
7736 I40E_FLAG_FD_SB_ENABLED |
7737 I40E_FLAG_FD_ATR_ENABLED |
7738 I40E_FLAG_DCB_ENABLED |
7739 I40E_FLAG_SRIOV_ENABLED |
7740 I40E_FLAG_VMDQ_ENABLED);
41c445ff 7741 } else {
cbf61325
ASJ		 7742 /* Not enough queues for all TCs */
7743 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
7744 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
7745 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
7746 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
7747 }
7748 pf->num_lan_qps = pf->rss_size_max;
7749 queues_left -= pf->num_lan_qps;
7750 }
7751
7752 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7753 if (queues_left > 1) {
7754 queues_left -= 1; /* save 1 queue for FD */
7755 } else {
7756 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7757 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
7758 }
41c445ff
JB		 7759 }
7760
7761 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7762 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 7763 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
7764 (queues_left / pf->num_vf_qps));
41c445ff
JB		 7765 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7766 }
7767
7768 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7769 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7770 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7771 (queues_left / pf->num_vmdq_qps));
7772 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7773 }
7774
f8ff1464 7775 pf->queues_left = queues_left;
41c445ff
JB		 7776 return;
7777}
7778
7779/**
7780 * i40e_setup_pf_filter_control - Setup PF static filter control
7781 * @pf: PF to be setup
7782 *
7783 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7784 * settings. If PE/FCoE are enabled then it will also set the per PF
7785 * based filter sizes required for them. It also enables Flow director,
7786 * ethertype and macvlan type filter settings for the pf.
7787 *
7788 * Returns 0 on success, negative on failure
7789 **/
7790static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7791{
7792 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7793
7794 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7795
7796 /* Flow Director is enabled */
60ea5f83 7797 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 7798 settings->enable_fdir = true;
7799
7800 /* Ethtype and MACVLAN filters enabled for PF */
7801 settings->enable_ethtype = true;
7802 settings->enable_macvlan = true;
7803
7804 if (i40e_set_filter_control(&pf->hw, settings))
7805 return -ENOENT;
7806
7807 return 0;
7808}
7809
7810/**
7811 * i40e_probe - Device initialization routine
7812 * @pdev: PCI device information struct
7813 * @ent: entry in i40e_pci_tbl
7814 *
7815 * i40e_probe initializes a pf identified by a pci_dev structure.
7816 * The OS initialization, configuring of the pf private structure,
7817 * and a hardware reset occur.
7818 *
7819 * Returns 0 on success, negative on failure
7820 **/
7821static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7822{
7823 struct i40e_driver_version dv;
7824 struct i40e_pf *pf;
7825 struct i40e_hw *hw;
93cd765b 7826 static u16 pfs_found;
d4dfb81a 7827 u16 link_status;
41c445ff
JB		 7828 int err = 0;
7829 u32 len;
7830
7831 err = pci_enable_device_mem(pdev);
7832 if (err)
7833 return err;
7834
7835 /* set up for high or low dma */
7836 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7837 /* coherent mask for the same size will always succeed if
7838 * dma_set_mask does
7839 */
7840 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7841 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7842 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7843 } else {
7844 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7845 err = -EIO;
7846 goto err_dma;
7847 }
7848
7849 /* set up pci connections */
7850 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7851 IORESOURCE_MEM), i40e_driver_name);
7852 if (err) {
7853 dev_info(&pdev->dev,
7854 "pci_request_selected_regions failed %d\n", err);
7855 goto err_pci_reg;
7856 }
7857
7858 pci_enable_pcie_error_reporting(pdev);
7859 pci_set_master(pdev);
7860
7861 /* Now that we have a PCI connection, we need to do the
7862 * low level device setup. This is primarily setting up
7863 * the Admin Queue structures and then querying for the
7864 * device's current profile information.
7865 */
7866 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7867 if (!pf) {
7868 err = -ENOMEM;
7869 goto err_pf_alloc;
7870 }
7871 pf->next_vsi = 0;
7872 pf->pdev = pdev;
7873 set_bit(__I40E_DOWN, &pf->state);
7874
7875 hw = &pf->hw;
7876 hw->back = pf;
7877 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7878 pci_resource_len(pdev, 0));
7879 if (!hw->hw_addr) {
7880 err = -EIO;
7881 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7882 (unsigned int)pci_resource_start(pdev, 0),
7883 (unsigned int)pci_resource_len(pdev, 0), err);
7884 goto err_ioremap;
7885 }
7886 hw->vendor_id = pdev->vendor;
7887 hw->device_id = pdev->device;
7888 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7889 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7890 hw->subsystem_device_id = pdev->subsystem_device;
7891 hw->bus.device = PCI_SLOT(pdev->devfn);
7892 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7893 pf->instance = pfs_found;
41c445ff 7894
7134f9ce
JB		 7895 /* do a special CORER for clearing PXE mode once at init */
7896 if (hw->revision_id == 0 &&
7897 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7898 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7899 i40e_flush(hw);
7900 msleep(200);
7901 pf->corer_count++;
7902
7903 i40e_clear_pxe_mode(hw);
7904 }
7905
41c445ff
JB		 7906 /* Reset here to make sure all is clean and to define PF 'n' */
7907 err = i40e_pf_reset(hw);
7908 if (err) {
7909 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7910 goto err_pf_reset;
7911 }
7912 pf->pfr_count++;
7913
7914 hw->aq.num_arq_entries = I40E_AQ_LEN;
7915 hw->aq.num_asq_entries = I40E_AQ_LEN;
7916 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7917 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7918 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7919 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7920 "%s-pf%d:misc",
7921 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7922
7923 err = i40e_init_shared_code(hw);
7924 if (err) {
7925 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7926 goto err_pf_reset;
7927 }
7928
d52c20b7
JB		 7929 /* set up a default setting for link flow control */
7930 pf->hw.fc.requested_mode = I40E_FC_NONE;
7931
41c445ff
JB		 7932 err = i40e_init_adminq(hw);
7933 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7934 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7935 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7936 dev_info(&pdev->dev,
7937 "warning: NVM version not supported, supported version: %02x.%02x\n",
7938 I40E_CURRENT_NVM_VERSION_HI,
7939 I40E_CURRENT_NVM_VERSION_LO);
7940 }
41c445ff
JB		 7941 if (err) {
7942 dev_info(&pdev->dev,
7943 "init_adminq failed: %d expecting API %02x.%02x\n",
7944 err,
7945 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7946 goto err_pf_reset;
7947 }
7948
6ff4ef86 7949 i40e_clear_pxe_mode(hw);
41c445ff
JB		 7950 err = i40e_get_capabilities(pf);
7951 if (err)
7952 goto err_adminq_setup;
7953
7954 err = i40e_sw_init(pf);
7955 if (err) {
7956 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7957 goto err_sw_init;
7958 }
7959
7960 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7961 hw->func_caps.num_rx_qp,
7962 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7963 if (err) {
7964 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7965 goto err_init_lan_hmc;
7966 }
7967
7968 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7969 if (err) {
7970 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7971 err = -ENOENT;
7972 goto err_configure_lan_hmc;
7973 }
7974
7975 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7976 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7977 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7978 err = -EIO;
7979 goto err_mac_addr;
7980 }
7981 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7982 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7983
7984 pci_set_drvdata(pdev, pf);
7985 pci_save_state(pdev);
4e3b35b0
NP		 7986#ifdef CONFIG_I40E_DCB
7987 err = i40e_init_pf_dcb(pf);
7988 if (err) {
7989 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
7990 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
7991 goto err_init_dcb;
7992 }
7993#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7994
7995 /* set up periodic task facility */
7996 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7997 pf->service_timer_period = HZ;
7998
7999 INIT_WORK(&pf->service_task, i40e_service_task);
8000 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8001 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8002 pf->link_check_timeout = jiffies;
8003
8e2773ae
SN		 8004 /* WoL defaults to disabled */
8005 pf->wol_en = false;
8006 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8007
41c445ff
JB		 8008 /* set up the main switch operations */
8009 i40e_determine_queue_usage(pf);
8010 i40e_init_interrupt_scheme(pf);
8011
8012 /* Set up the *vsi struct based on the number of VSIs in the HW,
8013 * and set up our local tracking of the MAIN PF vsi.
8014 */
8015 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8016 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8017 if (!pf->vsi) {
8018 err = -ENOMEM;
41c445ff 8019 goto err_switch_setup;
ed87ac09 8020 }
41c445ff 8021
bc7d338f 8022 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8023 if (err) {
8024 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8025 goto err_vsis;
8026 }
8027
8028 /* The main driver is (mostly) up and happy. We need to set this state
8029 * before setting up the misc vector or we get a race and the vector
8030 * ends up disabled forever.
8031 */
8032 clear_bit(__I40E_DOWN, &pf->state);
8033
8034 /* In case of MSIX we are going to setup the misc vector right here
8035 * to handle admin queue events etc. In case of legacy and MSI
8036 * the misc functionality and queue processing is combined in
8037 * the same vector and that gets setup at open.
8038 */
8039 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8040 err = i40e_setup_misc_vector(pf);
8041 if (err) {
8042 dev_info(&pdev->dev,
8043 "setup of misc vector failed: %d\n", err);
8044 goto err_vsis;
8045 }
8046 }
8047
8048 /* prep for VF support */
8049 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8050 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
8051 u32 val;
8052
8053 /* disable link interrupts for VFs */
8054 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8055 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8056 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8057 i40e_flush(hw);
4aeec010
MW		 8058
8059 if (pci_num_vf(pdev)) {
8060 dev_info(&pdev->dev,
8061 "Active VFs found, allocating resources.\n");
8062 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8063 if (err)
8064 dev_info(&pdev->dev,
8065 "Error %d allocating resources for existing VFs\n",
8066 err);
8067 }
41c445ff
JB		 8068 }
8069
93cd765b
ASJ		 8070 pfs_found++;
8071
41c445ff
JB		 8072 i40e_dbg_pf_init(pf);
8073
8074 /* tell the firmware that we're starting */
8075 dv.major_version = DRV_VERSION_MAJOR;
8076 dv.minor_version = DRV_VERSION_MINOR;
8077 dv.build_version = DRV_VERSION_BUILD;
8078 dv.subbuild_version = 0;
8079 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
8080
8081 /* since everything's happy, start the service_task timer */
8082 mod_timer(&pf->service_timer,
8083 round_jiffies(jiffies + pf->service_timer_period));
8084
d4dfb81a
CS		 8085 /* Get the negotiated link width and speed from PCI config space */
8086 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8087
8088 i40e_set_pci_config_data(hw, link_status);
8089
8090 dev_info(&pdev->dev, "PCI Express: %s %s\n",
8091 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8092 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8093 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8094 "Unknown"),
8095 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8096 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8097 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8098 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8099 "Unknown"));
8100
8101 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8102 hw->bus.speed < i40e_bus_speed_8000) {
8103 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8104 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8105 }
8106
41c445ff
JB		 8107 return 0;
8108
8109 /* Unwind what we've done if something failed in the setup */
8110err_vsis:
8111 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8112 i40e_clear_interrupt_scheme(pf);
8113 kfree(pf->vsi);
04b03013
SN		 8114err_switch_setup:
8115 i40e_reset_interrupt_capability(pf);
41c445ff 8116 del_timer_sync(&pf->service_timer);
4e3b35b0
NP		 8117#ifdef CONFIG_I40E_DCB
8118err_init_dcb:
8119#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8120err_mac_addr:
8121err_configure_lan_hmc:
8122 (void)i40e_shutdown_lan_hmc(hw);
8123err_init_lan_hmc:
8124 kfree(pf->qp_pile);
8125 kfree(pf->irq_pile);
8126err_sw_init:
8127err_adminq_setup:
8128 (void)i40e_shutdown_adminq(hw);
8129err_pf_reset:
8130 iounmap(hw->hw_addr);
8131err_ioremap:
8132 kfree(pf);
8133err_pf_alloc:
8134 pci_disable_pcie_error_reporting(pdev);
8135 pci_release_selected_regions(pdev,
8136 pci_select_bars(pdev, IORESOURCE_MEM));
8137err_pci_reg:
8138err_dma:
8139 pci_disable_device(pdev);
8140 return err;
8141}
8142
8143/**
8144 * i40e_remove - Device removal routine
8145 * @pdev: PCI device information struct
8146 *
8147 * i40e_remove is called by the PCI subsystem to alert the driver
8148 * that is should release a PCI device. This could be caused by a
8149 * Hot-Plug event, or because the driver is going to be removed from
8150 * memory.
8151 **/
8152static void i40e_remove(struct pci_dev *pdev)
8153{
8154 struct i40e_pf *pf = pci_get_drvdata(pdev);
8155 i40e_status ret_code;
8156 u32 reg;
8157 int i;
8158
8159 i40e_dbg_pf_exit(pf);
8160
beb0dff1
JK		 8161 i40e_ptp_stop(pf);
8162
41c445ff
JB		 8163 /* no more scheduling of any task */
8164 set_bit(__I40E_DOWN, &pf->state);
8165 del_timer_sync(&pf->service_timer);
8166 cancel_work_sync(&pf->service_task);
8167
eb2d80bc
MW		 8168 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8169 i40e_free_vfs(pf);
8170 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8171 }
8172
41c445ff
JB		 8173 i40e_fdir_teardown(pf);
8174
8175 /* If there is a switch structure or any orphans, remove them.
8176 * This will leave only the PF's VSI remaining.
8177 */
8178 for (i = 0; i < I40E_MAX_VEB; i++) {
8179 if (!pf->veb[i])
8180 continue;
8181
8182 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8183 pf->veb[i]->uplink_seid == 0)
8184 i40e_switch_branch_release(pf->veb[i]);
8185 }
8186
8187 /* Now we can shutdown the PF's VSI, just before we kill
8188 * adminq and hmc.
8189 */
8190 if (pf->vsi[pf->lan_vsi])
8191 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8192
8193 i40e_stop_misc_vector(pf);
8194 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8195 synchronize_irq(pf->msix_entries[0].vector);
8196 free_irq(pf->msix_entries[0].vector, pf);
8197 }
8198
8199 /* shutdown and destroy the HMC */
8200 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8201 if (ret_code)
8202 dev_warn(&pdev->dev,
8203 "Failed to destroy the HMC resources: %d\n", ret_code);
8204
8205 /* shutdown the adminq */
41c445ff
JB		 8206 ret_code = i40e_shutdown_adminq(&pf->hw);
8207 if (ret_code)
8208 dev_warn(&pdev->dev,
8209 "Failed to destroy the Admin Queue resources: %d\n",
8210 ret_code);
8211
8212 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8213 i40e_clear_interrupt_scheme(pf);
8214 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8215 if (pf->vsi[i]) {
8216 i40e_vsi_clear_rings(pf->vsi[i]);
8217 i40e_vsi_clear(pf->vsi[i]);
8218 pf->vsi[i] = NULL;
8219 }
8220 }
8221
8222 for (i = 0; i < I40E_MAX_VEB; i++) {
8223 kfree(pf->veb[i]);
8224 pf->veb[i] = NULL;
8225 }
8226
8227 kfree(pf->qp_pile);
8228 kfree(pf->irq_pile);
8229 kfree(pf->sw_config);
8230 kfree(pf->vsi);
8231
8232 /* force a PF reset to clean anything leftover */
8233 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8234 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8235 i40e_flush(&pf->hw);
8236
8237 iounmap(pf->hw.hw_addr);
8238 kfree(pf);
8239 pci_release_selected_regions(pdev,
8240 pci_select_bars(pdev, IORESOURCE_MEM));
8241
8242 pci_disable_pcie_error_reporting(pdev);
8243 pci_disable_device(pdev);
8244}
8245
8246/**
8247 * i40e_pci_error_detected - warning that something funky happened in PCI land
8248 * @pdev: PCI device information struct
8249 *
8250 * Called to warn that something happened and the error handling steps
8251 * are in progress. Allows the driver to quiesce things, be ready for
8252 * remediation.
8253 **/
8254static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8255 enum pci_channel_state error)
8256{
8257 struct i40e_pf *pf = pci_get_drvdata(pdev);
8258
8259 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8260
8261 /* shutdown all operations */
9007bccd
SN		 8262 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8263 rtnl_lock();
8264 i40e_prep_for_reset(pf);
8265 rtnl_unlock();
8266 }
41c445ff
JB		 8267
8268 /* Request a slot reset */
8269 return PCI_ERS_RESULT_NEED_RESET;
8270}
8271
8272/**
8273 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8274 * @pdev: PCI device information struct
8275 *
8276 * Called to find if the driver can work with the device now that
8277 * the pci slot has been reset. If a basic connection seems good
8278 * (registers are readable and have sane content) then return a
8279 * happy little PCI_ERS_RESULT_xxx.
8280 **/
8281static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8282{
8283 struct i40e_pf *pf = pci_get_drvdata(pdev);
8284 pci_ers_result_t result;
8285 int err;
8286 u32 reg;
8287
8288 dev_info(&pdev->dev, "%s\n", __func__);
8289 if (pci_enable_device_mem(pdev)) {
8290 dev_info(&pdev->dev,
8291 "Cannot re-enable PCI device after reset.\n");
8292 result = PCI_ERS_RESULT_DISCONNECT;
8293 } else {
8294 pci_set_master(pdev);
8295 pci_restore_state(pdev);
8296 pci_save_state(pdev);
8297 pci_wake_from_d3(pdev, false);
8298
8299 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8300 if (reg == 0)
8301 result = PCI_ERS_RESULT_RECOVERED;
8302 else
8303 result = PCI_ERS_RESULT_DISCONNECT;
8304 }
8305
8306 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8307 if (err) {
8308 dev_info(&pdev->dev,
8309 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8310 err);
8311 /* non-fatal, continue */
8312 }
8313
8314 return result;
8315}
8316
8317/**
8318 * i40e_pci_error_resume - restart operations after PCI error recovery
8319 * @pdev: PCI device information struct
8320 *
8321 * Called to allow the driver to bring things back up after PCI error
8322 * and/or reset recovery has finished.
8323 **/
8324static void i40e_pci_error_resume(struct pci_dev *pdev)
8325{
8326 struct i40e_pf *pf = pci_get_drvdata(pdev);
8327
8328 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8329 if (test_bit(__I40E_SUSPENDED, &pf->state))
8330 return;
8331
8332 rtnl_lock();
41c445ff 8333 i40e_handle_reset_warning(pf);
9007bccd
SN		 8334 rtnl_lock();
8335}
8336
8337/**
8338 * i40e_shutdown - PCI callback for shutting down
8339 * @pdev: PCI device information struct
8340 **/
8341static void i40e_shutdown(struct pci_dev *pdev)
8342{
8343 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8344 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8345
8346 set_bit(__I40E_SUSPENDED, &pf->state);
8347 set_bit(__I40E_DOWN, &pf->state);
8348 rtnl_lock();
8349 i40e_prep_for_reset(pf);
8350 rtnl_unlock();
8351
8e2773ae
SN		 8352 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8353 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8354
9007bccd 8355 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8356 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8357 pci_set_power_state(pdev, PCI_D3hot);
8358 }
8359}
8360
8361#ifdef CONFIG_PM
8362/**
8363 * i40e_suspend - PCI callback for moving to D3
8364 * @pdev: PCI device information struct
8365 **/
8366static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8367{
8368 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8369 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8370
8371 set_bit(__I40E_SUSPENDED, &pf->state);
8372 set_bit(__I40E_DOWN, &pf->state);
8373 rtnl_lock();
8374 i40e_prep_for_reset(pf);
8375 rtnl_unlock();
8376
8e2773ae
SN		 8377 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8378 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8379
8380 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8381 pci_set_power_state(pdev, PCI_D3hot);
8382
8383 return 0;
41c445ff
JB		 8384}
8385
9007bccd
SN		 8386/**
8387 * i40e_resume - PCI callback for waking up from D3
8388 * @pdev: PCI device information struct
8389 **/
8390static int i40e_resume(struct pci_dev *pdev)
8391{
8392 struct i40e_pf *pf = pci_get_drvdata(pdev);
8393 u32 err;
8394
8395 pci_set_power_state(pdev, PCI_D0);
8396 pci_restore_state(pdev);
8397 /* pci_restore_state() clears dev->state_saves, so
8398 * call pci_save_state() again to restore it.
8399 */
8400 pci_save_state(pdev);
8401
8402 err = pci_enable_device_mem(pdev);
8403 if (err) {
8404 dev_err(&pdev->dev,
8405 "%s: Cannot enable PCI device from suspend\n",
8406 __func__);
8407 return err;
8408 }
8409 pci_set_master(pdev);
8410
8411 /* no wakeup events while running */
8412 pci_wake_from_d3(pdev, false);
8413
8414 /* handling the reset will rebuild the device state */
8415 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8416 clear_bit(__I40E_DOWN, &pf->state);
8417 rtnl_lock();
8418 i40e_reset_and_rebuild(pf, false);
8419 rtnl_unlock();
8420 }
8421
8422 return 0;
8423}
8424
8425#endif
41c445ff
JB		 8426static const struct pci_error_handlers i40e_err_handler = {
8427 .error_detected = i40e_pci_error_detected,
8428 .slot_reset = i40e_pci_error_slot_reset,
8429 .resume = i40e_pci_error_resume,
8430};
8431
8432static struct pci_driver i40e_driver = {
8433 .name = i40e_driver_name,
8434 .id_table = i40e_pci_tbl,
8435 .probe = i40e_probe,
8436 .remove = i40e_remove,
9007bccd
SN		 8437#ifdef CONFIG_PM
8438 .suspend = i40e_suspend,
8439 .resume = i40e_resume,
8440#endif
8441 .shutdown = i40e_shutdown,
41c445ff
JB		 8442 .err_handler = &i40e_err_handler,
8443 .sriov_configure = i40e_pci_sriov_configure,
8444};
8445
8446/**
8447 * i40e_init_module - Driver registration routine
8448 *
8449 * i40e_init_module is the first routine called when the driver is
8450 * loaded. All it does is register with the PCI subsystem.
8451 **/
8452static int __init i40e_init_module(void)
8453{
8454 pr_info("%s: %s - version %s\n", i40e_driver_name,
8455 i40e_driver_string, i40e_driver_version_str);
8456 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8457 i40e_dbg_init();
8458 return pci_register_driver(&i40e_driver);
8459}
8460module_init(i40e_init_module);
8461
8462/**
8463 * i40e_exit_module - Driver exit cleanup routine
8464 *
8465 * i40e_exit_module is called just before the driver is removed
8466 * from memory.
8467 **/
8468static void __exit i40e_exit_module(void)
8469{
8470 pci_unregister_driver(&i40e_driver);
8471 i40e_dbg_exit();
8472}
8473module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)