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i40e/i40evf: ARQ copy desc data even for failed commands
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
e454d6bf 41#define DRV_VERSION_MINOR 4
4e776381 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 281 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 307 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
308 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 309 break;
310 }
311 i40e_service_event_schedule(pf);
312 pf->tx_timeout_recovery_level++;
313}
314
315/**
316 * i40e_release_rx_desc - Store the new tail and head values
317 * @rx_ring: ring to bump
318 * @val: new head index
319 **/
320static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
321{
322 rx_ring->next_to_use = val;
323
324 /* Force memory writes to complete before letting h/w
325 * know there are new descriptors to fetch. (Only
326 * applicable for weak-ordered memory model archs,
327 * such as IA-64).
328 */
329 wmb();
330 writel(val, rx_ring->tail);
331}
332
333/**
334 * i40e_get_vsi_stats_struct - Get System Network Statistics
335 * @vsi: the VSI we care about
336 *
337 * Returns the address of the device statistics structure.
338 * The statistics are actually updated from the service task.
339 **/
340struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
341{
342 return &vsi->net_stats;
343}
344
345/**
346 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
347 * @netdev: network interface device structure
348 *
349 * Returns the address of the device statistics structure.
350 * The statistics are actually updated from the service task.
351 **/
352static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
353 struct net_device *netdev,
980e9b11 354 struct rtnl_link_stats64 *stats)
41c445ff
JB		 355{
356 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 357 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
57a7744e 378 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
57a7744e 381 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
57a7744e 388 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
57a7744e 391 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
a5282f44 398 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 426 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 436 }
8e9dca53 437 }
41c445ff
JB		 438 vsi->stat_offsets_loaded = false;
439}
440
441/**
442 * i40e_pf_reset_stats - Reset all of the stats for the given pf
443 * @pf: the PF to be reset
444 **/
445void i40e_pf_reset_stats(struct i40e_pf *pf)
446{
e91fdf76
SN		 447 int i;
448
41c445ff
JB		 449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
e91fdf76
SN		 452
453 for (i = 0; i < I40E_MAX_VEB; i++) {
454 if (pf->veb[i]) {
455 memset(&pf->veb[i]->stats, 0,
456 sizeof(pf->veb[i]->stats));
457 memset(&pf->veb[i]->stats_offsets, 0,
458 sizeof(pf->veb[i]->stats_offsets));
459 pf->veb[i]->stat_offsets_loaded = false;
460 }
461 }
41c445ff
JB		 462}
463
464/**
465 * i40e_stat_update48 - read and update a 48 bit stat from the chip
466 * @hw: ptr to the hardware info
467 * @hireg: the high 32 bit reg to read
468 * @loreg: the low 32 bit reg to read
469 * @offset_loaded: has the initial offset been loaded yet
470 * @offset: ptr to current offset value
471 * @stat: ptr to the stat
472 *
473 * Since the device stats are not reset at PFReset, they likely will not
474 * be zeroed when the driver starts. We'll save the first values read
475 * and use them as offsets to be subtracted from the raw values in order
476 * to report stats that count from zero. In the process, we also manage
477 * the potential roll-over.
478 **/
479static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
480 bool offset_loaded, u64 *offset, u64 *stat)
481{
482 u64 new_data;
483
ab60085e 484 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 485 new_data = rd32(hw, loreg);
486 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
487 } else {
488 new_data = rd64(hw, loreg);
489 }
490 if (!offset_loaded)
491 *offset = new_data;
492 if (likely(new_data >= *offset))
493 *stat = new_data - *offset;
494 else
495 *stat = (new_data + ((u64)1 << 48)) - *offset;
496 *stat &= 0xFFFFFFFFFFFFULL;
497}
498
499/**
500 * i40e_stat_update32 - read and update a 32 bit stat from the chip
501 * @hw: ptr to the hardware info
502 * @reg: the hw reg to read
503 * @offset_loaded: has the initial offset been loaded yet
504 * @offset: ptr to current offset value
505 * @stat: ptr to the stat
506 **/
507static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
508 bool offset_loaded, u64 *offset, u64 *stat)
509{
510 u32 new_data;
511
512 new_data = rd32(hw, reg);
513 if (!offset_loaded)
514 *offset = new_data;
515 if (likely(new_data >= *offset))
516 *stat = (u32)(new_data - *offset);
517 else
518 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
519}
520
521/**
522 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
523 * @vsi: the VSI to be updated
524 **/
525void i40e_update_eth_stats(struct i40e_vsi *vsi)
526{
527 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
528 struct i40e_pf *pf = vsi->back;
529 struct i40e_hw *hw = &pf->hw;
530 struct i40e_eth_stats *oes;
531 struct i40e_eth_stats *es; /* device's eth stats */
532
533 es = &vsi->eth_stats;
534 oes = &vsi->eth_stats_offsets;
535
536 /* Gather up the stats that the hw collects */
537 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
538 vsi->stat_offsets_loaded,
539 &oes->tx_errors, &es->tx_errors);
540 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 543 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
546 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
547 vsi->stat_offsets_loaded,
548 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 549
550 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
551 I40E_GLV_GORCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_bytes, &es->rx_bytes);
554 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
555 I40E_GLV_UPRCL(stat_idx),
556 vsi->stat_offsets_loaded,
557 &oes->rx_unicast, &es->rx_unicast);
558 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
559 I40E_GLV_MPRCL(stat_idx),
560 vsi->stat_offsets_loaded,
561 &oes->rx_multicast, &es->rx_multicast);
562 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
563 I40E_GLV_BPRCL(stat_idx),
564 vsi->stat_offsets_loaded,
565 &oes->rx_broadcast, &es->rx_broadcast);
566
567 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
568 I40E_GLV_GOTCL(stat_idx),
569 vsi->stat_offsets_loaded,
570 &oes->tx_bytes, &es->tx_bytes);
571 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
572 I40E_GLV_UPTCL(stat_idx),
573 vsi->stat_offsets_loaded,
574 &oes->tx_unicast, &es->tx_unicast);
575 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
576 I40E_GLV_MPTCL(stat_idx),
577 vsi->stat_offsets_loaded,
578 &oes->tx_multicast, &es->tx_multicast);
579 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
580 I40E_GLV_BPTCL(stat_idx),
581 vsi->stat_offsets_loaded,
582 &oes->tx_broadcast, &es->tx_broadcast);
583 vsi->stat_offsets_loaded = true;
584}
585
586/**
587 * i40e_update_veb_stats - Update Switch component statistics
588 * @veb: the VEB being updated
589 **/
590static void i40e_update_veb_stats(struct i40e_veb *veb)
591{
592 struct i40e_pf *pf = veb->pf;
593 struct i40e_hw *hw = &pf->hw;
594 struct i40e_eth_stats *oes;
595 struct i40e_eth_stats *es; /* device's eth stats */
596 int idx = 0;
597
598 idx = veb->stats_idx;
599 es = &veb->stats;
600 oes = &veb->stats_offsets;
601
602 /* Gather up the stats that the hw collects */
603 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
604 veb->stat_offsets_loaded,
605 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 606 if (hw->revision_id > 0)
607 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
608 veb->stat_offsets_loaded,
609 &oes->rx_unknown_protocol,
610 &es->rx_unknown_protocol);
41c445ff
JB		 611 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->rx_bytes, &es->rx_bytes);
614 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->rx_unicast, &es->rx_unicast);
617 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->rx_multicast, &es->rx_multicast);
620 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
621 veb->stat_offsets_loaded,
622 &oes->rx_broadcast, &es->rx_broadcast);
623
624 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
625 veb->stat_offsets_loaded,
626 &oes->tx_bytes, &es->tx_bytes);
627 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
628 veb->stat_offsets_loaded,
629 &oes->tx_unicast, &es->tx_unicast);
630 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
631 veb->stat_offsets_loaded,
632 &oes->tx_multicast, &es->tx_multicast);
633 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
634 veb->stat_offsets_loaded,
635 &oes->tx_broadcast, &es->tx_broadcast);
636 veb->stat_offsets_loaded = true;
637}
638
639/**
640 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
641 * @pf: the corresponding PF
642 *
643 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
644 **/
645static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
646{
647 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
648 struct i40e_hw_port_stats *nsd = &pf->stats;
649 struct i40e_hw *hw = &pf->hw;
650 u64 xoff = 0;
651 u16 i, v;
652
653 if ((hw->fc.current_mode != I40E_FC_FULL) &&
654 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
655 return;
656
657 xoff = nsd->link_xoff_rx;
658 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
659 pf->stat_offsets_loaded,
660 &osd->link_xoff_rx, &nsd->link_xoff_rx);
661
662 /* No new LFC xoff rx */
663 if (!(nsd->link_xoff_rx - xoff))
664 return;
665
666 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 667 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 668 struct i40e_vsi *vsi = pf->vsi[v];
669
ddfda80f 670 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 671 continue;
672
673 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 674 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 675 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
676 }
677 }
678}
679
680/**
681 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
682 * @pf: the corresponding PF
683 *
684 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
685 **/
686static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
687{
688 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
689 struct i40e_hw_port_stats *nsd = &pf->stats;
690 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
691 struct i40e_dcbx_config *dcb_cfg;
692 struct i40e_hw *hw = &pf->hw;
693 u16 i, v;
694 u8 tc;
695
696 dcb_cfg = &hw->local_dcbx_config;
697
698 /* See if DCB enabled with PFC TC */
699 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
700 !(dcb_cfg->pfc.pfcenable)) {
701 i40e_update_link_xoff_rx(pf);
702 return;
703 }
704
705 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
706 u64 prio_xoff = nsd->priority_xoff_rx[i];
707 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
708 pf->stat_offsets_loaded,
709 &osd->priority_xoff_rx[i],
710 &nsd->priority_xoff_rx[i]);
711
712 /* No new PFC xoff rx */
713 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
714 continue;
715 /* Get the TC for given priority */
716 tc = dcb_cfg->etscfg.prioritytable[i];
717 xoff[tc] = true;
718 }
719
720 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 721 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 722 struct i40e_vsi *vsi = pf->vsi[v];
723
ddfda80f 724 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 725 continue;
726
727 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 728 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 729
730 tc = ring->dcb_tc;
731 if (xoff[tc])
732 clear_bit(__I40E_HANG_CHECK_ARMED,
733 &ring->state);
734 }
735 }
736}
737
738/**
7812fddc 739 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 740 * @vsi: the VSI to be updated
741 *
742 * There are a few instances where we store the same stat in a
743 * couple of different structs. This is partly because we have
744 * the netdev stats that need to be filled out, which is slightly
745 * different from the "eth_stats" defined by the chip and used in
7812fddc 746 * VF communications. We sort it out here.
41c445ff 747 **/
7812fddc 748static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 749{
750 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 751 struct rtnl_link_stats64 *ons;
752 struct rtnl_link_stats64 *ns; /* netdev stats */
753 struct i40e_eth_stats *oes;
754 struct i40e_eth_stats *es; /* device's eth stats */
755 u32 tx_restart, tx_busy;
756 u32 rx_page, rx_buf;
757 u64 rx_p, rx_b;
758 u64 tx_p, tx_b;
41c445ff
JB		 759 u16 q;
760
761 if (test_bit(__I40E_DOWN, &vsi->state) ||
762 test_bit(__I40E_CONFIG_BUSY, &pf->state))
763 return;
764
765 ns = i40e_get_vsi_stats_struct(vsi);
766 ons = &vsi->net_stats_offsets;
767 es = &vsi->eth_stats;
768 oes = &vsi->eth_stats_offsets;
769
770 /* Gather up the netdev and vsi stats that the driver collects
771 * on the fly during packet processing
772 */
773 rx_b = rx_p = 0;
774 tx_b = tx_p = 0;
775 tx_restart = tx_busy = 0;
776 rx_page = 0;
777 rx_buf = 0;
980e9b11 778 rcu_read_lock();
41c445ff
JB		 779 for (q = 0; q < vsi->num_queue_pairs; q++) {
780 struct i40e_ring *p;
980e9b11
AD		 781 u64 bytes, packets;
782 unsigned int start;
783
784 /* locate Tx ring */
785 p = ACCESS_ONCE(vsi->tx_rings[q]);
786
787 do {
57a7744e 788 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 789 packets = p->stats.packets;
790 bytes = p->stats.bytes;
57a7744e 791 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 792 tx_b += bytes;
793 tx_p += packets;
794 tx_restart += p->tx_stats.restart_queue;
795 tx_busy += p->tx_stats.tx_busy;
41c445ff 796
980e9b11
AD		 797 /* Rx queue is part of the same block as Tx queue */
798 p = &p[1];
799 do {
57a7744e 800 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 801 packets = p->stats.packets;
802 bytes = p->stats.bytes;
57a7744e 803 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 804 rx_b += bytes;
805 rx_p += packets;
420136cc
MW		 806 rx_buf += p->rx_stats.alloc_buff_failed;
807 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 808 }
980e9b11 809 rcu_read_unlock();
41c445ff
JB		 810 vsi->tx_restart = tx_restart;
811 vsi->tx_busy = tx_busy;
812 vsi->rx_page_failed = rx_page;
813 vsi->rx_buf_failed = rx_buf;
814
815 ns->rx_packets = rx_p;
816 ns->rx_bytes = rx_b;
817 ns->tx_packets = tx_p;
818 ns->tx_bytes = tx_b;
819
41c445ff 820 /* update netdev stats from eth stats */
7812fddc 821 i40e_update_eth_stats(vsi);
41c445ff
JB		 822 ons->tx_errors = oes->tx_errors;
823 ns->tx_errors = es->tx_errors;
824 ons->multicast = oes->rx_multicast;
825 ns->multicast = es->rx_multicast;
41a9e55c
SN		 826 ons->rx_dropped = oes->rx_discards;
827 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 828 ons->tx_dropped = oes->tx_discards;
829 ns->tx_dropped = es->tx_discards;
830
7812fddc 831 /* pull in a couple PF stats if this is the main vsi */
41c445ff 832 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 833 ns->rx_crc_errors = pf->stats.crc_errors;
834 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
835 ns->rx_length_errors = pf->stats.rx_length_errors;
836 }
837}
41c445ff 838
7812fddc
SN		 839/**
840 * i40e_update_pf_stats - Update the pf statistics counters.
841 * @pf: the PF to be updated
842 **/
843static void i40e_update_pf_stats(struct i40e_pf *pf)
844{
845 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
846 struct i40e_hw_port_stats *nsd = &pf->stats;
847 struct i40e_hw *hw = &pf->hw;
848 u32 val;
849 int i;
41c445ff 850
7812fddc
SN		 851 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
852 I40E_GLPRT_GORCL(hw->port),
853 pf->stat_offsets_loaded,
854 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
855 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
856 I40E_GLPRT_GOTCL(hw->port),
857 pf->stat_offsets_loaded,
858 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
859 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
860 pf->stat_offsets_loaded,
861 &osd->eth.rx_discards,
862 &nsd->eth.rx_discards);
863 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
864 pf->stat_offsets_loaded,
865 &osd->eth.tx_discards,
866 &nsd->eth.tx_discards);
41c445ff 867
532d283d
SN		 868 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
869 I40E_GLPRT_UPRCL(hw->port),
870 pf->stat_offsets_loaded,
871 &osd->eth.rx_unicast,
872 &nsd->eth.rx_unicast);
7812fddc
SN		 873 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
874 I40E_GLPRT_MPRCL(hw->port),
875 pf->stat_offsets_loaded,
876 &osd->eth.rx_multicast,
877 &nsd->eth.rx_multicast);
532d283d
SN		 878 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
879 I40E_GLPRT_BPRCL(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->eth.rx_broadcast,
882 &nsd->eth.rx_broadcast);
883 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
884 I40E_GLPRT_UPTCL(hw->port),
885 pf->stat_offsets_loaded,
886 &osd->eth.tx_unicast,
887 &nsd->eth.tx_unicast);
888 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
889 I40E_GLPRT_MPTCL(hw->port),
890 pf->stat_offsets_loaded,
891 &osd->eth.tx_multicast,
892 &nsd->eth.tx_multicast);
893 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
894 I40E_GLPRT_BPTCL(hw->port),
895 pf->stat_offsets_loaded,
896 &osd->eth.tx_broadcast,
897 &nsd->eth.tx_broadcast);
41c445ff 898
7812fddc
SN		 899 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
900 pf->stat_offsets_loaded,
901 &osd->tx_dropped_link_down,
902 &nsd->tx_dropped_link_down);
41c445ff 903
7812fddc
SN		 904 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->crc_errors, &nsd->crc_errors);
41c445ff 907
7812fddc
SN		 908 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 911
7812fddc
SN		 912 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->mac_local_faults,
915 &nsd->mac_local_faults);
916 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->mac_remote_faults,
919 &nsd->mac_remote_faults);
41c445ff 920
7812fddc
SN		 921 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
922 pf->stat_offsets_loaded,
923 &osd->rx_length_errors,
924 &nsd->rx_length_errors);
41c445ff 925
7812fddc
SN		 926 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
927 pf->stat_offsets_loaded,
928 &osd->link_xon_rx, &nsd->link_xon_rx);
929 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
930 pf->stat_offsets_loaded,
931 &osd->link_xon_tx, &nsd->link_xon_tx);
932 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
933 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 936
7812fddc
SN		 937 for (i = 0; i < 8; i++) {
938 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 939 pf->stat_offsets_loaded,
7812fddc
SN		 940 &osd->priority_xon_rx[i],
941 &nsd->priority_xon_rx[i]);
942 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 943 pf->stat_offsets_loaded,
7812fddc
SN		 944 &osd->priority_xon_tx[i],
945 &nsd->priority_xon_tx[i]);
946 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 947 pf->stat_offsets_loaded,
7812fddc
SN		 948 &osd->priority_xoff_tx[i],
949 &nsd->priority_xoff_tx[i]);
950 i40e_stat_update32(hw,
951 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 952 pf->stat_offsets_loaded,
7812fddc
SN		 953 &osd->priority_xon_2_xoff[i],
954 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 955 }
956
7812fddc
SN		 957 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
958 I40E_GLPRT_PRC64L(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->rx_size_64, &nsd->rx_size_64);
961 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
962 I40E_GLPRT_PRC127L(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->rx_size_127, &nsd->rx_size_127);
965 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
966 I40E_GLPRT_PRC255L(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_size_255, &nsd->rx_size_255);
969 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
970 I40E_GLPRT_PRC511L(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_size_511, &nsd->rx_size_511);
973 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
974 I40E_GLPRT_PRC1023L(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->rx_size_1023, &nsd->rx_size_1023);
977 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
978 I40E_GLPRT_PRC1522L(hw->port),
979 pf->stat_offsets_loaded,
980 &osd->rx_size_1522, &nsd->rx_size_1522);
981 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
982 I40E_GLPRT_PRC9522L(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->rx_size_big, &nsd->rx_size_big);
985
986 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
987 I40E_GLPRT_PTC64L(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->tx_size_64, &nsd->tx_size_64);
990 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
991 I40E_GLPRT_PTC127L(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->tx_size_127, &nsd->tx_size_127);
994 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
995 I40E_GLPRT_PTC255L(hw->port),
996 pf->stat_offsets_loaded,
997 &osd->tx_size_255, &nsd->tx_size_255);
998 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
999 I40E_GLPRT_PTC511L(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->tx_size_511, &nsd->tx_size_511);
1002 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1003 I40E_GLPRT_PTC1023L(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->tx_size_1023, &nsd->tx_size_1023);
1006 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1007 I40E_GLPRT_PTC1522L(hw->port),
1008 pf->stat_offsets_loaded,
1009 &osd->tx_size_1522, &nsd->tx_size_1522);
1010 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1011 I40E_GLPRT_PTC9522L(hw->port),
1012 pf->stat_offsets_loaded,
1013 &osd->tx_size_big, &nsd->tx_size_big);
1014
1015 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1016 pf->stat_offsets_loaded,
1017 &osd->rx_undersize, &nsd->rx_undersize);
1018 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1019 pf->stat_offsets_loaded,
1020 &osd->rx_fragments, &nsd->rx_fragments);
1021 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_oversize, &nsd->rx_oversize);
1024 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_jabber, &nsd->rx_jabber);
1027
433c47de
ASJ		 1028 /* FDIR stats */
1029 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1030 pf->stat_offsets_loaded,
1031 &osd->fd_atr_match, &nsd->fd_atr_match);
1032 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1033 pf->stat_offsets_loaded,
1034 &osd->fd_sb_match, &nsd->fd_sb_match);
1035
7812fddc
SN		 1036 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1037 nsd->tx_lpi_status =
1038 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1039 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1040 nsd->rx_lpi_status =
1041 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1042 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1043 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1044 pf->stat_offsets_loaded,
1045 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1046 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1047 pf->stat_offsets_loaded,
1048 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1049
41c445ff
JB		 1050 pf->stat_offsets_loaded = true;
1051}
1052
7812fddc
SN		 1053/**
1054 * i40e_update_stats - Update the various statistics counters.
1055 * @vsi: the VSI to be updated
1056 *
1057 * Update the various stats for this VSI and its related entities.
1058 **/
1059void i40e_update_stats(struct i40e_vsi *vsi)
1060{
1061 struct i40e_pf *pf = vsi->back;
1062
1063 if (vsi == pf->vsi[pf->lan_vsi])
1064 i40e_update_pf_stats(pf);
1065
1066 i40e_update_vsi_stats(vsi);
1067}
1068
41c445ff
JB		 1069/**
1070 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1071 * @vsi: the VSI to be searched
1072 * @macaddr: the MAC address
1073 * @vlan: the vlan
1074 * @is_vf: make sure its a vf filter, else doesn't matter
1075 * @is_netdev: make sure its a netdev filter, else doesn't matter
1076 *
1077 * Returns ptr to the filter object or NULL
1078 **/
1079static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1080 u8 *macaddr, s16 vlan,
1081 bool is_vf, bool is_netdev)
1082{
1083 struct i40e_mac_filter *f;
1084
1085 if (!vsi || !macaddr)
1086 return NULL;
1087
1088 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1089 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1090 (vlan == f->vlan) &&
1091 (!is_vf || f->is_vf) &&
1092 (!is_netdev || f->is_netdev))
1093 return f;
1094 }
1095 return NULL;
1096}
1097
1098/**
1099 * i40e_find_mac - Find a mac addr in the macvlan filters list
1100 * @vsi: the VSI to be searched
1101 * @macaddr: the MAC address we are searching for
1102 * @is_vf: make sure its a vf filter, else doesn't matter
1103 * @is_netdev: make sure its a netdev filter, else doesn't matter
1104 *
1105 * Returns the first filter with the provided MAC address or NULL if
1106 * MAC address was not found
1107 **/
1108struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1109 bool is_vf, bool is_netdev)
1110{
1111 struct i40e_mac_filter *f;
1112
1113 if (!vsi || !macaddr)
1114 return NULL;
1115
1116 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1117 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1118 (!is_vf || f->is_vf) &&
1119 (!is_netdev || f->is_netdev))
1120 return f;
1121 }
1122 return NULL;
1123}
1124
1125/**
1126 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1127 * @vsi: the VSI to be searched
1128 *
1129 * Returns true if VSI is in vlan mode or false otherwise
1130 **/
1131bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1132{
1133 struct i40e_mac_filter *f;
1134
1135 /* Only -1 for all the filters denotes not in vlan mode
1136 * so we have to go through all the list in order to make sure
1137 */
1138 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1139 if (f->vlan >= 0)
1140 return true;
1141 }
1142
1143 return false;
1144}
1145
1146/**
1147 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1148 * @vsi: the VSI to be searched
1149 * @macaddr: the mac address to be filtered
1150 * @is_vf: true if it is a vf
1151 * @is_netdev: true if it is a netdev
1152 *
1153 * Goes through all the macvlan filters and adds a
1154 * macvlan filter for each unique vlan that already exists
1155 *
1156 * Returns first filter found on success, else NULL
1157 **/
1158struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1159 bool is_vf, bool is_netdev)
1160{
1161 struct i40e_mac_filter *f;
1162
1163 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1164 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1165 is_vf, is_netdev)) {
1166 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1167 is_vf, is_netdev))
41c445ff
JB		 1168 return NULL;
1169 }
1170 }
1171
1172 return list_first_entry_or_null(&vsi->mac_filter_list,
1173 struct i40e_mac_filter, list);
1174}
1175
8c27d42e
GR		 1176/**
1177 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1178 * @vsi: the PF Main VSI - inappropriate for any other VSI
1179 * @macaddr: the MAC address
1180 **/
1181static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
1182{
1183 struct i40e_aqc_remove_macvlan_element_data element;
1184 struct i40e_pf *pf = vsi->back;
1185 i40e_status aq_ret;
1186
1187 /* Only appropriate for the PF main VSI */
1188 if (vsi->type != I40E_VSI_MAIN)
1189 return;
1190
1191 ether_addr_copy(element.mac_addr, macaddr);
1192 element.vlan_tag = 0;
1193 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1194 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1195 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1196 if (aq_ret)
1197 dev_err(&pf->pdev->dev, "Could not remove default MAC-VLAN\n");
1198}
1199
41c445ff
JB		 1200/**
1201 * i40e_add_filter - Add a mac/vlan filter to the VSI
1202 * @vsi: the VSI to be searched
1203 * @macaddr: the MAC address
1204 * @vlan: the vlan
1205 * @is_vf: make sure its a vf filter, else doesn't matter
1206 * @is_netdev: make sure its a netdev filter, else doesn't matter
1207 *
1208 * Returns ptr to the filter object or NULL when no memory available.
1209 **/
1210struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1211 u8 *macaddr, s16 vlan,
1212 bool is_vf, bool is_netdev)
1213{
1214 struct i40e_mac_filter *f;
1215
1216 if (!vsi || !macaddr)
1217 return NULL;
1218
1219 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1220 if (!f) {
1221 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1222 if (!f)
1223 goto add_filter_out;
1224
9a173901 1225 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1226 f->vlan = vlan;
1227 f->changed = true;
1228
1229 INIT_LIST_HEAD(&f->list);
1230 list_add(&f->list, &vsi->mac_filter_list);
1231 }
1232
1233 /* increment counter and add a new flag if needed */
1234 if (is_vf) {
1235 if (!f->is_vf) {
1236 f->is_vf = true;
1237 f->counter++;
1238 }
1239 } else if (is_netdev) {
1240 if (!f->is_netdev) {
1241 f->is_netdev = true;
1242 f->counter++;
1243 }
1244 } else {
1245 f->counter++;
1246 }
1247
1248 /* changed tells sync_filters_subtask to
1249 * push the filter down to the firmware
1250 */
1251 if (f->changed) {
1252 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1253 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1254 }
1255
1256add_filter_out:
1257 return f;
1258}
1259
1260/**
1261 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1262 * @vsi: the VSI to be searched
1263 * @macaddr: the MAC address
1264 * @vlan: the vlan
1265 * @is_vf: make sure it's a vf filter, else doesn't matter
1266 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1267 **/
1268void i40e_del_filter(struct i40e_vsi *vsi,
1269 u8 *macaddr, s16 vlan,
1270 bool is_vf, bool is_netdev)
1271{
1272 struct i40e_mac_filter *f;
1273
1274 if (!vsi || !macaddr)
1275 return;
1276
1277 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1278 if (!f || f->counter == 0)
1279 return;
1280
1281 if (is_vf) {
1282 if (f->is_vf) {
1283 f->is_vf = false;
1284 f->counter--;
1285 }
1286 } else if (is_netdev) {
1287 if (f->is_netdev) {
1288 f->is_netdev = false;
1289 f->counter--;
1290 }
1291 } else {
1292 /* make sure we don't remove a filter in use by vf or netdev */
1293 int min_f = 0;
1294 min_f += (f->is_vf ? 1 : 0);
1295 min_f += (f->is_netdev ? 1 : 0);
1296
1297 if (f->counter > min_f)
1298 f->counter--;
1299 }
1300
1301 /* counter == 0 tells sync_filters_subtask to
1302 * remove the filter from the firmware's list
1303 */
1304 if (f->counter == 0) {
1305 f->changed = true;
1306 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1307 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1308 }
1309}
1310
1311/**
1312 * i40e_set_mac - NDO callback to set mac address
1313 * @netdev: network interface device structure
1314 * @p: pointer to an address structure
1315 *
1316 * Returns 0 on success, negative on failure
1317 **/
1318static int i40e_set_mac(struct net_device *netdev, void *p)
1319{
1320 struct i40e_netdev_priv *np = netdev_priv(netdev);
1321 struct i40e_vsi *vsi = np->vsi;
1322 struct sockaddr *addr = p;
1323 struct i40e_mac_filter *f;
1324
1325 if (!is_valid_ether_addr(addr->sa_data))
1326 return -EADDRNOTAVAIL;
1327
1328 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1329
80f6428f
ASJ		 1330 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1331 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1332 return -EADDRNOTAVAIL;
1333
41c445ff
JB		 1334 if (vsi->type == I40E_VSI_MAIN) {
1335 i40e_status ret;
1336 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1337 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1338 addr->sa_data, NULL);
1339 if (ret) {
1340 netdev_info(netdev,
1341 "Addr change for Main VSI failed: %d\n",
1342 ret);
1343 return -EADDRNOTAVAIL;
1344 }
41c445ff
JB		 1345 }
1346
6252c7e4
SN		 1347 f = i40e_find_mac(vsi, addr->sa_data, false, true);
1348 if (!f) {
6c8ad1ba
SN		 1349 /* In order to be sure to not drop any packets, add the
1350 * new address first then delete the old one.
1351 */
1352 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1353 false, false);
1354 if (!f)
1355 return -ENOMEM;
1356
1357 i40e_sync_vsi_filters(vsi);
1358 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1359 false, false);
1360 i40e_sync_vsi_filters(vsi);
1361 }
41c445ff 1362
6252c7e4 1363 f->is_laa = true;
6c8ad1ba
SN		 1364 if (!ether_addr_equal(netdev->dev_addr, addr->sa_data))
1365 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1366
1367 return 0;
1368}
1369
1370/**
1371 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1372 * @vsi: the VSI being setup
1373 * @ctxt: VSI context structure
1374 * @enabled_tc: Enabled TCs bitmap
1375 * @is_add: True if called before Add VSI
1376 *
1377 * Setup VSI queue mapping for enabled traffic classes.
1378 **/
1379static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1380 struct i40e_vsi_context *ctxt,
1381 u8 enabled_tc,
1382 bool is_add)
1383{
1384 struct i40e_pf *pf = vsi->back;
1385 u16 sections = 0;
1386 u8 netdev_tc = 0;
1387 u16 numtc = 0;
1388 u16 qcount;
1389 u8 offset;
1390 u16 qmap;
1391 int i;
4e3b35b0 1392 u16 num_tc_qps = 0;
41c445ff
JB		 1393
1394 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1395 offset = 0;
1396
1397 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1398 /* Find numtc from enabled TC bitmap */
1399 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1400 if (enabled_tc & (1 << i)) /* TC is enabled */
1401 numtc++;
1402 }
1403 if (!numtc) {
1404 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1405 numtc = 1;
1406 }
1407 } else {
1408 /* At least TC0 is enabled in case of non-DCB case */
1409 numtc = 1;
1410 }
1411
1412 vsi->tc_config.numtc = numtc;
1413 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1414 /* Number of queues per enabled TC */
eb051afe 1415 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1416 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1417
1418 /* Setup queue offset/count for all TCs for given VSI */
1419 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1420 /* See if the given TC is enabled for the given VSI */
1421 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1422 int pow, num_qps;
1423
41c445ff
JB		 1424 switch (vsi->type) {
1425 case I40E_VSI_MAIN:
4e3b35b0 1426 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1427 break;
1428 case I40E_VSI_FDIR:
1429 case I40E_VSI_SRIOV:
1430 case I40E_VSI_VMDQ2:
1431 default:
4e3b35b0 1432 qcount = num_tc_qps;
41c445ff
JB		 1433 WARN_ON(i != 0);
1434 break;
1435 }
4e3b35b0
NP		 1436 vsi->tc_config.tc_info[i].qoffset = offset;
1437 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1438
1439 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1440 num_qps = qcount;
41c445ff 1441 pow = 0;
4e3b35b0 1442 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1443 pow++;
1444 num_qps >>= 1;
1445 }
1446
1447 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1448 qmap =
1449 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1450 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1451
4e3b35b0 1452 offset += qcount;
41c445ff
JB		 1453 } else {
1454 /* TC is not enabled so set the offset to
1455 * default queue and allocate one queue
1456 * for the given TC.
1457 */
1458 vsi->tc_config.tc_info[i].qoffset = 0;
1459 vsi->tc_config.tc_info[i].qcount = 1;
1460 vsi->tc_config.tc_info[i].netdev_tc = 0;
1461
1462 qmap = 0;
1463 }
1464 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1465 }
1466
1467 /* Set actual Tx/Rx queue pairs */
1468 vsi->num_queue_pairs = offset;
1469
1470 /* Scheduler section valid can only be set for ADD VSI */
1471 if (is_add) {
1472 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1473
1474 ctxt->info.up_enable_bits = enabled_tc;
1475 }
1476 if (vsi->type == I40E_VSI_SRIOV) {
1477 ctxt->info.mapping_flags |=
1478 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1479 for (i = 0; i < vsi->num_queue_pairs; i++)
1480 ctxt->info.queue_mapping[i] =
1481 cpu_to_le16(vsi->base_queue + i);
1482 } else {
1483 ctxt->info.mapping_flags |=
1484 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1485 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1486 }
1487 ctxt->info.valid_sections |= cpu_to_le16(sections);
1488}
1489
1490/**
1491 * i40e_set_rx_mode - NDO callback to set the netdev filters
1492 * @netdev: network interface device structure
1493 **/
1494static void i40e_set_rx_mode(struct net_device *netdev)
1495{
1496 struct i40e_netdev_priv *np = netdev_priv(netdev);
1497 struct i40e_mac_filter *f, *ftmp;
1498 struct i40e_vsi *vsi = np->vsi;
1499 struct netdev_hw_addr *uca;
1500 struct netdev_hw_addr *mca;
1501 struct netdev_hw_addr *ha;
1502
1503 /* add addr if not already in the filter list */
1504 netdev_for_each_uc_addr(uca, netdev) {
1505 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1506 if (i40e_is_vsi_in_vlan(vsi))
1507 i40e_put_mac_in_vlan(vsi, uca->addr,
1508 false, true);
1509 else
1510 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1511 false, true);
1512 }
1513 }
1514
1515 netdev_for_each_mc_addr(mca, netdev) {
1516 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1517 if (i40e_is_vsi_in_vlan(vsi))
1518 i40e_put_mac_in_vlan(vsi, mca->addr,
1519 false, true);
1520 else
1521 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1522 false, true);
1523 }
1524 }
1525
1526 /* remove filter if not in netdev list */
1527 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1528 bool found = false;
1529
1530 if (!f->is_netdev)
1531 continue;
1532
1533 if (is_multicast_ether_addr(f->macaddr)) {
1534 netdev_for_each_mc_addr(mca, netdev) {
1535 if (ether_addr_equal(mca->addr, f->macaddr)) {
1536 found = true;
1537 break;
1538 }
1539 }
1540 } else {
1541 netdev_for_each_uc_addr(uca, netdev) {
1542 if (ether_addr_equal(uca->addr, f->macaddr)) {
1543 found = true;
1544 break;
1545 }
1546 }
1547
1548 for_each_dev_addr(netdev, ha) {
1549 if (ether_addr_equal(ha->addr, f->macaddr)) {
1550 found = true;
1551 break;
1552 }
1553 }
1554 }
1555 if (!found)
1556 i40e_del_filter(
1557 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1558 }
1559
1560 /* check for other flag changes */
1561 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1562 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1563 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1564 }
1565}
1566
1567/**
1568 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1569 * @vsi: ptr to the VSI
1570 *
1571 * Push any outstanding VSI filter changes through the AdminQ.
1572 *
1573 * Returns 0 or error value
1574 **/
1575int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1576{
1577 struct i40e_mac_filter *f, *ftmp;
1578 bool promisc_forced_on = false;
1579 bool add_happened = false;
1580 int filter_list_len = 0;
1581 u32 changed_flags = 0;
dcae29be 1582 i40e_status aq_ret = 0;
41c445ff
JB		 1583 struct i40e_pf *pf;
1584 int num_add = 0;
1585 int num_del = 0;
1586 u16 cmd_flags;
1587
1588 /* empty array typed pointers, kcalloc later */
1589 struct i40e_aqc_add_macvlan_element_data *add_list;
1590 struct i40e_aqc_remove_macvlan_element_data *del_list;
1591
1592 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1593 usleep_range(1000, 2000);
1594 pf = vsi->back;
1595
1596 if (vsi->netdev) {
1597 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1598 vsi->current_netdev_flags = vsi->netdev->flags;
1599 }
1600
1601 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1602 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1603
1604 filter_list_len = pf->hw.aq.asq_buf_size /
1605 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1606 del_list = kcalloc(filter_list_len,
1607 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1608 GFP_KERNEL);
1609 if (!del_list)
1610 return -ENOMEM;
1611
1612 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1613 if (!f->changed)
1614 continue;
1615
1616 if (f->counter != 0)
1617 continue;
1618 f->changed = false;
1619 cmd_flags = 0;
1620
1621 /* add to delete list */
9a173901 1622 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1623 del_list[num_del].vlan_tag =
1624 cpu_to_le16((u16)(f->vlan ==
1625 I40E_VLAN_ANY ? 0 : f->vlan));
1626
41c445ff
JB		 1627 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1628 del_list[num_del].flags = cmd_flags;
1629 num_del++;
1630
1631 /* unlink from filter list */
1632 list_del(&f->list);
1633 kfree(f);
1634
1635 /* flush a full buffer */
1636 if (num_del == filter_list_len) {
dcae29be 1637 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1638 vsi->seid, del_list, num_del,
1639 NULL);
1640 num_del = 0;
1641 memset(del_list, 0, sizeof(*del_list));
1642
fdfe9cbe
SN		 1643 if (aq_ret &&
1644 pf->hw.aq.asq_last_status !=
1645 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1646 dev_info(&pf->pdev->dev,
1647 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1648 aq_ret,
41c445ff
JB		 1649 pf->hw.aq.asq_last_status);
1650 }
1651 }
1652 if (num_del) {
dcae29be 1653 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1654 del_list, num_del, NULL);
1655 num_del = 0;
1656
fdfe9cbe
SN		 1657 if (aq_ret &&
1658 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1659 dev_info(&pf->pdev->dev,
1660 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1661 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1662 }
1663
1664 kfree(del_list);
1665 del_list = NULL;
1666
1667 /* do all the adds now */
1668 filter_list_len = pf->hw.aq.asq_buf_size /
1669 sizeof(struct i40e_aqc_add_macvlan_element_data),
1670 add_list = kcalloc(filter_list_len,
1671 sizeof(struct i40e_aqc_add_macvlan_element_data),
1672 GFP_KERNEL);
1673 if (!add_list)
1674 return -ENOMEM;
1675
1676 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1677 if (!f->changed)
1678 continue;
1679
1680 if (f->counter == 0)
1681 continue;
1682 f->changed = false;
1683 add_happened = true;
1684 cmd_flags = 0;
1685
1686 /* add to add array */
9a173901 1687 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1688 add_list[num_add].vlan_tag =
1689 cpu_to_le16(
1690 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1691 add_list[num_add].queue_number = 0;
1692
1693 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1694 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1695 num_add++;
1696
1697 /* flush a full buffer */
1698 if (num_add == filter_list_len) {
dcae29be
JB		 1699 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1700 add_list, num_add,
1701 NULL);
41c445ff
JB		 1702 num_add = 0;
1703
dcae29be 1704 if (aq_ret)
41c445ff
JB		 1705 break;
1706 memset(add_list, 0, sizeof(*add_list));
1707 }
1708 }
1709 if (num_add) {
dcae29be
JB		 1710 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1711 add_list, num_add, NULL);
41c445ff
JB		 1712 num_add = 0;
1713 }
1714 kfree(add_list);
1715 add_list = NULL;
1716
dcae29be 1717 if (add_happened && (!aq_ret)) {
41c445ff 1718 /* do nothing */;
dcae29be 1719 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1720 dev_info(&pf->pdev->dev,
1721 "add filter failed, err %d, aq_err %d\n",
dcae29be 1722 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1723 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1724 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1725 &vsi->state)) {
1726 promisc_forced_on = true;
1727 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1728 &vsi->state);
1729 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1730 }
1731 }
1732 }
1733
1734 /* check for changes in promiscuous modes */
1735 if (changed_flags & IFF_ALLMULTI) {
1736 bool cur_multipromisc;
1737 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1738 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1739 vsi->seid,
1740 cur_multipromisc,
1741 NULL);
1742 if (aq_ret)
41c445ff
JB		 1743 dev_info(&pf->pdev->dev,
1744 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1745 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1746 }
1747 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1748 bool cur_promisc;
1749 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1750 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1751 &vsi->state));
dcae29be
JB		 1752 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1753 vsi->seid,
1754 cur_promisc, NULL);
1755 if (aq_ret)
41c445ff
JB		 1756 dev_info(&pf->pdev->dev,
1757 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1758 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1759 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1760 vsi->seid,
1761 cur_promisc, NULL);
1762 if (aq_ret)
1763 dev_info(&pf->pdev->dev,
1764 "set brdcast promisc failed, err %d, aq_err %d\n",
1765 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1766 }
1767
1768 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1769 return 0;
1770}
1771
1772/**
1773 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1774 * @pf: board private structure
1775 **/
1776static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1777{
1778 int v;
1779
1780 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1781 return;
1782 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1783
505682cd 1784 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1785 if (pf->vsi[v] &&
1786 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1787 i40e_sync_vsi_filters(pf->vsi[v]);
1788 }
1789}
1790
1791/**
1792 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1793 * @netdev: network interface device structure
1794 * @new_mtu: new value for maximum frame size
1795 *
1796 * Returns 0 on success, negative on failure
1797 **/
1798static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1799{
1800 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1801 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1802 struct i40e_vsi *vsi = np->vsi;
1803
1804 /* MTU < 68 is an error and causes problems on some kernels */
1805 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1806 return -EINVAL;
1807
1808 netdev_info(netdev, "changing MTU from %d to %d\n",
1809 netdev->mtu, new_mtu);
1810 netdev->mtu = new_mtu;
1811 if (netif_running(netdev))
1812 i40e_vsi_reinit_locked(vsi);
1813
1814 return 0;
1815}
1816
beb0dff1
JK		 1817/**
1818 * i40e_ioctl - Access the hwtstamp interface
1819 * @netdev: network interface device structure
1820 * @ifr: interface request data
1821 * @cmd: ioctl command
1822 **/
1823int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1824{
1825 struct i40e_netdev_priv *np = netdev_priv(netdev);
1826 struct i40e_pf *pf = np->vsi->back;
1827
1828 switch (cmd) {
1829 case SIOCGHWTSTAMP:
1830 return i40e_ptp_get_ts_config(pf, ifr);
1831 case SIOCSHWTSTAMP:
1832 return i40e_ptp_set_ts_config(pf, ifr);
1833 default:
1834 return -EOPNOTSUPP;
1835 }
1836}
1837
41c445ff
JB		 1838/**
1839 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1840 * @vsi: the vsi being adjusted
1841 **/
1842void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1843{
1844 struct i40e_vsi_context ctxt;
1845 i40e_status ret;
1846
1847 if ((vsi->info.valid_sections &
1848 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1849 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1850 return; /* already enabled */
1851
1852 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1853 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1854 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1855
1856 ctxt.seid = vsi->seid;
1857 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1858 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1859 if (ret) {
1860 dev_info(&vsi->back->pdev->dev,
1861 "%s: update vsi failed, aq_err=%d\n",
1862 __func__, vsi->back->hw.aq.asq_last_status);
1863 }
1864}
1865
1866/**
1867 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1868 * @vsi: the vsi being adjusted
1869 **/
1870void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1871{
1872 struct i40e_vsi_context ctxt;
1873 i40e_status ret;
1874
1875 if ((vsi->info.valid_sections &
1876 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1877 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1878 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1879 return; /* already disabled */
1880
1881 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1882 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1883 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1884
1885 ctxt.seid = vsi->seid;
1886 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1887 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1888 if (ret) {
1889 dev_info(&vsi->back->pdev->dev,
1890 "%s: update vsi failed, aq_err=%d\n",
1891 __func__, vsi->back->hw.aq.asq_last_status);
1892 }
1893}
1894
1895/**
1896 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1897 * @netdev: network interface to be adjusted
1898 * @features: netdev features to test if VLAN offload is enabled or not
1899 **/
1900static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1901{
1902 struct i40e_netdev_priv *np = netdev_priv(netdev);
1903 struct i40e_vsi *vsi = np->vsi;
1904
1905 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1906 i40e_vlan_stripping_enable(vsi);
1907 else
1908 i40e_vlan_stripping_disable(vsi);
1909}
1910
1911/**
1912 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1913 * @vsi: the vsi being configured
1914 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1915 **/
1916int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1917{
1918 struct i40e_mac_filter *f, *add_f;
1919 bool is_netdev, is_vf;
41c445ff
JB		 1920
1921 is_vf = (vsi->type == I40E_VSI_SRIOV);
1922 is_netdev = !!(vsi->netdev);
1923
1924 if (is_netdev) {
1925 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1926 is_vf, is_netdev);
1927 if (!add_f) {
1928 dev_info(&vsi->back->pdev->dev,
1929 "Could not add vlan filter %d for %pM\n",
1930 vid, vsi->netdev->dev_addr);
1931 return -ENOMEM;
1932 }
1933 }
1934
1935 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1936 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1937 if (!add_f) {
1938 dev_info(&vsi->back->pdev->dev,
1939 "Could not add vlan filter %d for %pM\n",
1940 vid, f->macaddr);
1941 return -ENOMEM;
1942 }
1943 }
1944
41c445ff
JB		 1945 /* Now if we add a vlan tag, make sure to check if it is the first
1946 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1947 * with 0, so we now accept untagged and specified tagged traffic
1948 * (and not any taged and untagged)
1949 */
1950 if (vid > 0) {
1951 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1952 I40E_VLAN_ANY,
1953 is_vf, is_netdev)) {
1954 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1955 I40E_VLAN_ANY, is_vf, is_netdev);
1956 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1957 is_vf, is_netdev);
1958 if (!add_f) {
1959 dev_info(&vsi->back->pdev->dev,
1960 "Could not add filter 0 for %pM\n",
1961 vsi->netdev->dev_addr);
1962 return -ENOMEM;
1963 }
1964 }
8d82a7c5 1965 }
41c445ff 1966
8d82a7c5
GR		 1967 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1968 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1969 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1970 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1971 is_vf, is_netdev)) {
1972 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1973 is_vf, is_netdev);
1974 add_f = i40e_add_filter(vsi, f->macaddr,
1975 0, is_vf, is_netdev);
1976 if (!add_f) {
1977 dev_info(&vsi->back->pdev->dev,
1978 "Could not add filter 0 for %pM\n",
1979 f->macaddr);
1980 return -ENOMEM;
1981 }
1982 }
1983 }
41c445ff
JB		 1984 }
1985
80f6428f
ASJ		 1986 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1987 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1988 return 0;
1989
1990 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1991}
1992
1993/**
1994 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1995 * @vsi: the vsi being configured
1996 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1997 *
1998 * Return: 0 on success or negative otherwise
41c445ff
JB		 1999 **/
2000int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2001{
2002 struct net_device *netdev = vsi->netdev;
2003 struct i40e_mac_filter *f, *add_f;
2004 bool is_vf, is_netdev;
2005 int filter_count = 0;
41c445ff
JB		 2006
2007 is_vf = (vsi->type == I40E_VSI_SRIOV);
2008 is_netdev = !!(netdev);
2009
2010 if (is_netdev)
2011 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2012
2013 list_for_each_entry(f, &vsi->mac_filter_list, list)
2014 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2015
41c445ff
JB		 2016 /* go through all the filters for this VSI and if there is only
2017 * vid == 0 it means there are no other filters, so vid 0 must
2018 * be replaced with -1. This signifies that we should from now
2019 * on accept any traffic (with any tag present, or untagged)
2020 */
2021 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2022 if (is_netdev) {
2023 if (f->vlan &&
2024 ether_addr_equal(netdev->dev_addr, f->macaddr))
2025 filter_count++;
2026 }
2027
2028 if (f->vlan)
2029 filter_count++;
2030 }
2031
2032 if (!filter_count && is_netdev) {
2033 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2034 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2035 is_vf, is_netdev);
2036 if (!f) {
2037 dev_info(&vsi->back->pdev->dev,
2038 "Could not add filter %d for %pM\n",
2039 I40E_VLAN_ANY, netdev->dev_addr);
2040 return -ENOMEM;
2041 }
2042 }
2043
2044 if (!filter_count) {
2045 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2046 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2047 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2048 is_vf, is_netdev);
2049 if (!add_f) {
2050 dev_info(&vsi->back->pdev->dev,
2051 "Could not add filter %d for %pM\n",
2052 I40E_VLAN_ANY, f->macaddr);
2053 return -ENOMEM;
2054 }
2055 }
2056 }
2057
80f6428f
ASJ		 2058 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2059 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2060 return 0;
2061
41c445ff
JB		 2062 return i40e_sync_vsi_filters(vsi);
2063}
2064
2065/**
2066 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2067 * @netdev: network interface to be adjusted
2068 * @vid: vlan id to be added
078b5876
JB		 2069 *
2070 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 2071 **/
2072static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2073 __always_unused __be16 proto, u16 vid)
2074{
2075 struct i40e_netdev_priv *np = netdev_priv(netdev);
2076 struct i40e_vsi *vsi = np->vsi;
078b5876 2077 int ret = 0;
41c445ff
JB		 2078
2079 if (vid > 4095)
078b5876
JB		 2080 return -EINVAL;
2081
2082 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2083
6982d429
ASJ		 2084 /* If the network stack called us with vid = 0 then
2085 * it is asking to receive priority tagged packets with
2086 * vlan id 0. Our HW receives them by default when configured
2087 * to receive untagged packets so there is no need to add an
2088 * extra filter for vlan 0 tagged packets.
41c445ff 2089 */
6982d429
ASJ		 2090 if (vid)
2091 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2092
078b5876
JB		 2093 if (!ret && (vid < VLAN_N_VID))
2094 set_bit(vid, vsi->active_vlans);
41c445ff 2095
078b5876 2096 return ret;
41c445ff
JB		 2097}
2098
2099/**
2100 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2101 * @netdev: network interface to be adjusted
2102 * @vid: vlan id to be removed
078b5876 2103 *
fdfd943e 2104 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2105 **/
2106static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2107 __always_unused __be16 proto, u16 vid)
2108{
2109 struct i40e_netdev_priv *np = netdev_priv(netdev);
2110 struct i40e_vsi *vsi = np->vsi;
2111
078b5876
JB		 2112 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2113
41c445ff
JB		 2114 /* return code is ignored as there is nothing a user
2115 * can do about failure to remove and a log message was
078b5876 2116 * already printed from the other function
41c445ff
JB		 2117 */
2118 i40e_vsi_kill_vlan(vsi, vid);
2119
2120 clear_bit(vid, vsi->active_vlans);
078b5876 2121
41c445ff
JB		 2122 return 0;
2123}
2124
2125/**
2126 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2127 * @vsi: the vsi being brought back up
2128 **/
2129static void i40e_restore_vlan(struct i40e_vsi *vsi)
2130{
2131 u16 vid;
2132
2133 if (!vsi->netdev)
2134 return;
2135
2136 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2137
2138 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2139 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2140 vid);
2141}
2142
2143/**
2144 * i40e_vsi_add_pvid - Add pvid for the VSI
2145 * @vsi: the vsi being adjusted
2146 * @vid: the vlan id to set as a PVID
2147 **/
dcae29be 2148int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2149{
2150 struct i40e_vsi_context ctxt;
dcae29be 2151 i40e_status aq_ret;
41c445ff
JB		 2152
2153 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2154 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2155 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2156 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2157 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2158
2159 ctxt.seid = vsi->seid;
2160 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2161 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2162 if (aq_ret) {
41c445ff
JB		 2163 dev_info(&vsi->back->pdev->dev,
2164 "%s: update vsi failed, aq_err=%d\n",
2165 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2166 return -ENOENT;
41c445ff
JB		 2167 }
2168
dcae29be 2169 return 0;
41c445ff
JB		 2170}
2171
2172/**
2173 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2174 * @vsi: the vsi being adjusted
2175 *
2176 * Just use the vlan_rx_register() service to put it back to normal
2177 **/
2178void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2179{
6c12fcbf
GR		 2180 i40e_vlan_stripping_disable(vsi);
2181
41c445ff 2182 vsi->info.pvid = 0;
41c445ff
JB		 2183}
2184
2185/**
2186 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2187 * @vsi: ptr to the VSI
2188 *
2189 * If this function returns with an error, then it's possible one or
2190 * more of the rings is populated (while the rest are not). It is the
2191 * callers duty to clean those orphaned rings.
2192 *
2193 * Return 0 on success, negative on failure
2194 **/
2195static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2196{
2197 int i, err = 0;
2198
2199 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2200 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2201
2202 return err;
2203}
2204
2205/**
2206 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2207 * @vsi: ptr to the VSI
2208 *
2209 * Free VSI's transmit software resources
2210 **/
2211static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2212{
2213 int i;
2214
8e9dca53
GR		 2215 if (!vsi->tx_rings)
2216 return;
2217
41c445ff 2218 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2219 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2220 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2221}
2222
2223/**
2224 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2225 * @vsi: ptr to the VSI
2226 *
2227 * If this function returns with an error, then it's possible one or
2228 * more of the rings is populated (while the rest are not). It is the
2229 * callers duty to clean those orphaned rings.
2230 *
2231 * Return 0 on success, negative on failure
2232 **/
2233static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2234{
2235 int i, err = 0;
2236
2237 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2238 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2239 return err;
2240}
2241
2242/**
2243 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2244 * @vsi: ptr to the VSI
2245 *
2246 * Free all receive software resources
2247 **/
2248static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2249{
2250 int i;
2251
8e9dca53
GR		 2252 if (!vsi->rx_rings)
2253 return;
2254
41c445ff 2255 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2256 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2257 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2258}
2259
2260/**
2261 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2262 * @ring: The Tx ring to configure
2263 *
2264 * Configure the Tx descriptor ring in the HMC context.
2265 **/
2266static int i40e_configure_tx_ring(struct i40e_ring *ring)
2267{
2268 struct i40e_vsi *vsi = ring->vsi;
2269 u16 pf_q = vsi->base_queue + ring->queue_index;
2270 struct i40e_hw *hw = &vsi->back->hw;
2271 struct i40e_hmc_obj_txq tx_ctx;
2272 i40e_status err = 0;
2273 u32 qtx_ctl = 0;
2274
2275 /* some ATR related tx ring init */
60ea5f83 2276 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2277 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2278 ring->atr_count = 0;
2279 } else {
2280 ring->atr_sample_rate = 0;
2281 }
2282
2283 /* initialize XPS */
2284 if (ring->q_vector && ring->netdev &&
4e3b35b0 2285 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2286 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2287 netif_set_xps_queue(ring->netdev,
2288 &ring->q_vector->affinity_mask,
2289 ring->queue_index);
2290
2291 /* clear the context structure first */
2292 memset(&tx_ctx, 0, sizeof(tx_ctx));
2293
2294 tx_ctx.new_context = 1;
2295 tx_ctx.base = (ring->dma / 128);
2296 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2297 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2298 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2299 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2300 /* FDIR VSI tx ring can still use RS bit and writebacks */
2301 if (vsi->type != I40E_VSI_FDIR)
2302 tx_ctx.head_wb_ena = 1;
2303 tx_ctx.head_wb_addr = ring->dma +
2304 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2305
2306 /* As part of VSI creation/update, FW allocates certain
2307 * Tx arbitration queue sets for each TC enabled for
2308 * the VSI. The FW returns the handles to these queue
2309 * sets as part of the response buffer to Add VSI,
2310 * Update VSI, etc. AQ commands. It is expected that
2311 * these queue set handles be associated with the Tx
2312 * queues by the driver as part of the TX queue context
2313 * initialization. This has to be done regardless of
2314 * DCB as by default everything is mapped to TC0.
2315 */
2316 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2317 tx_ctx.rdylist_act = 0;
2318
2319 /* clear the context in the HMC */
2320 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2321 if (err) {
2322 dev_info(&vsi->back->pdev->dev,
2323 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2324 ring->queue_index, pf_q, err);
2325 return -ENOMEM;
2326 }
2327
2328 /* set the context in the HMC */
2329 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2330 if (err) {
2331 dev_info(&vsi->back->pdev->dev,
2332 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2333 ring->queue_index, pf_q, err);
2334 return -ENOMEM;
2335 }
2336
2337 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2338 if (vsi->type == I40E_VSI_VMDQ2)
2339 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2340 else
2341 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2342 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2343 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2344 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2345 i40e_flush(hw);
2346
2347 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2348
2349 /* cache tail off for easier writes later */
2350 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2351
2352 return 0;
2353}
2354
2355/**
2356 * i40e_configure_rx_ring - Configure a receive ring context
2357 * @ring: The Rx ring to configure
2358 *
2359 * Configure the Rx descriptor ring in the HMC context.
2360 **/
2361static int i40e_configure_rx_ring(struct i40e_ring *ring)
2362{
2363 struct i40e_vsi *vsi = ring->vsi;
2364 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2365 u16 pf_q = vsi->base_queue + ring->queue_index;
2366 struct i40e_hw *hw = &vsi->back->hw;
2367 struct i40e_hmc_obj_rxq rx_ctx;
2368 i40e_status err = 0;
2369
2370 ring->state = 0;
2371
2372 /* clear the context structure first */
2373 memset(&rx_ctx, 0, sizeof(rx_ctx));
2374
2375 ring->rx_buf_len = vsi->rx_buf_len;
2376 ring->rx_hdr_len = vsi->rx_hdr_len;
2377
2378 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2379 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2380
2381 rx_ctx.base = (ring->dma / 128);
2382 rx_ctx.qlen = ring->count;
2383
2384 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2385 set_ring_16byte_desc_enabled(ring);
2386 rx_ctx.dsize = 0;
2387 } else {
2388 rx_ctx.dsize = 1;
2389 }
2390
2391 rx_ctx.dtype = vsi->dtype;
2392 if (vsi->dtype) {
2393 set_ring_ps_enabled(ring);
2394 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2395 I40E_RX_SPLIT_IP |
2396 I40E_RX_SPLIT_TCP_UDP |
2397 I40E_RX_SPLIT_SCTP;
2398 } else {
2399 rx_ctx.hsplit_0 = 0;
2400 }
2401
2402 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2403 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2404 if (hw->revision_id == 0)
2405 rx_ctx.lrxqthresh = 0;
2406 else
2407 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2408 rx_ctx.crcstrip = 1;
2409 rx_ctx.l2tsel = 1;
2410 rx_ctx.showiv = 1;
acb3676b
CS		 2411 /* set the prefena field to 1 because the manual says to */
2412 rx_ctx.prefena = 1;
41c445ff
JB		 2413
2414 /* clear the context in the HMC */
2415 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2416 if (err) {
2417 dev_info(&vsi->back->pdev->dev,
2418 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2419 ring->queue_index, pf_q, err);
2420 return -ENOMEM;
2421 }
2422
2423 /* set the context in the HMC */
2424 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2425 if (err) {
2426 dev_info(&vsi->back->pdev->dev,
2427 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2428 ring->queue_index, pf_q, err);
2429 return -ENOMEM;
2430 }
2431
2432 /* cache tail for quicker writes, and clear the reg before use */
2433 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2434 writel(0, ring->tail);
2435
2436 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2437
2438 return 0;
2439}
2440
2441/**
2442 * i40e_vsi_configure_tx - Configure the VSI for Tx
2443 * @vsi: VSI structure describing this set of rings and resources
2444 *
2445 * Configure the Tx VSI for operation.
2446 **/
2447static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2448{
2449 int err = 0;
2450 u16 i;
2451
9f65e15b
AD		 2452 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2453 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2454
2455 return err;
2456}
2457
2458/**
2459 * i40e_vsi_configure_rx - Configure the VSI for Rx
2460 * @vsi: the VSI being configured
2461 *
2462 * Configure the Rx VSI for operation.
2463 **/
2464static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2465{
2466 int err = 0;
2467 u16 i;
2468
2469 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2470 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2471 + ETH_FCS_LEN + VLAN_HLEN;
2472 else
2473 vsi->max_frame = I40E_RXBUFFER_2048;
2474
2475 /* figure out correct receive buffer length */
2476 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2477 I40E_FLAG_RX_PS_ENABLED)) {
2478 case I40E_FLAG_RX_1BUF_ENABLED:
2479 vsi->rx_hdr_len = 0;
2480 vsi->rx_buf_len = vsi->max_frame;
2481 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2482 break;
2483 case I40E_FLAG_RX_PS_ENABLED:
2484 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2485 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2486 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2487 break;
2488 default:
2489 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2490 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2491 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2492 break;
2493 }
2494
2495 /* round up for the chip's needs */
2496 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2497 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2498 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2499 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2500
2501 /* set up individual rings */
2502 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2503 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2504
2505 return err;
2506}
2507
2508/**
2509 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2510 * @vsi: ptr to the VSI
2511 **/
2512static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2513{
e7046ee1 2514 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2515 u16 qoffset, qcount;
2516 int i, n;
2517
2518 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2519 return;
2520
2521 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2522 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2523 continue;
2524
2525 qoffset = vsi->tc_config.tc_info[n].qoffset;
2526 qcount = vsi->tc_config.tc_info[n].qcount;
2527 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2528 rx_ring = vsi->rx_rings[i];
2529 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2530 rx_ring->dcb_tc = n;
2531 tx_ring->dcb_tc = n;
2532 }
2533 }
2534}
2535
2536/**
2537 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2538 * @vsi: ptr to the VSI
2539 **/
2540static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2541{
2542 if (vsi->netdev)
2543 i40e_set_rx_mode(vsi->netdev);
2544}
2545
17a73f6b
JG		 2546/**
2547 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2548 * @vsi: Pointer to the targeted VSI
2549 *
2550 * This function replays the hlist on the hw where all the SB Flow Director
2551 * filters were saved.
2552 **/
2553static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2554{
2555 struct i40e_fdir_filter *filter;
2556 struct i40e_pf *pf = vsi->back;
2557 struct hlist_node *node;
2558
55a5e60b
ASJ		 2559 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2560 return;
2561
17a73f6b
JG		 2562 hlist_for_each_entry_safe(filter, node,
2563 &pf->fdir_filter_list, fdir_node) {
2564 i40e_add_del_fdir(vsi, filter, true);
2565 }
2566}
2567
41c445ff
JB		 2568/**
2569 * i40e_vsi_configure - Set up the VSI for action
2570 * @vsi: the VSI being configured
2571 **/
2572static int i40e_vsi_configure(struct i40e_vsi *vsi)
2573{
2574 int err;
2575
2576 i40e_set_vsi_rx_mode(vsi);
2577 i40e_restore_vlan(vsi);
2578 i40e_vsi_config_dcb_rings(vsi);
2579 err = i40e_vsi_configure_tx(vsi);
2580 if (!err)
2581 err = i40e_vsi_configure_rx(vsi);
2582
2583 return err;
2584}
2585
2586/**
2587 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2588 * @vsi: the VSI being configured
2589 **/
2590static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2591{
2592 struct i40e_pf *pf = vsi->back;
2593 struct i40e_q_vector *q_vector;
2594 struct i40e_hw *hw = &pf->hw;
2595 u16 vector;
2596 int i, q;
2597 u32 val;
2598 u32 qp;
2599
2600 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2601 * and PFINT_LNKLSTn registers, e.g.:
2602 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2603 */
2604 qp = vsi->base_queue;
2605 vector = vsi->base_vector;
493fb300
AD		 2606 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2607 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2608 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2609 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2610 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2611 q_vector->rx.itr);
2612 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2613 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2614 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2615 q_vector->tx.itr);
2616
2617 /* Linked list for the queuepairs assigned to this vector */
2618 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2619 for (q = 0; q < q_vector->num_ringpairs; q++) {
2620 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2621 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2622 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2623 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2624 (I40E_QUEUE_TYPE_TX
2625 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2626
2627 wr32(hw, I40E_QINT_RQCTL(qp), val);
2628
2629 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2630 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2631 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2632 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2633 (I40E_QUEUE_TYPE_RX
2634 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2635
2636 /* Terminate the linked list */
2637 if (q == (q_vector->num_ringpairs - 1))
2638 val |= (I40E_QUEUE_END_OF_LIST
2639 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2640
2641 wr32(hw, I40E_QINT_TQCTL(qp), val);
2642 qp++;
2643 }
2644 }
2645
2646 i40e_flush(hw);
2647}
2648
2649/**
2650 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2651 * @hw: ptr to the hardware info
2652 **/
2653static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2654{
2655 u32 val;
2656
2657 /* clear things first */
2658 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2659 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2660
2661 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2662 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2663 I40E_PFINT_ICR0_ENA_GRST_MASK |
2664 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2665 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2666 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2667 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2668 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2669 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2670
2671 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2672
2673 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2674 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2675 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2676
2677 /* OTHER_ITR_IDX = 0 */
2678 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2679}
2680
2681/**
2682 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2683 * @vsi: the VSI being configured
2684 **/
2685static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2686{
493fb300 2687 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2688 struct i40e_pf *pf = vsi->back;
2689 struct i40e_hw *hw = &pf->hw;
2690 u32 val;
2691
2692 /* set the ITR configuration */
2693 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2694 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2695 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2696 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2697 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2698 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2699
2700 i40e_enable_misc_int_causes(hw);
2701
2702 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2703 wr32(hw, I40E_PFINT_LNKLST0, 0);
2704
f29eaa3d 2705 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2706 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2707 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2708 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2709
2710 wr32(hw, I40E_QINT_RQCTL(0), val);
2711
2712 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2713 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2714 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2715
2716 wr32(hw, I40E_QINT_TQCTL(0), val);
2717 i40e_flush(hw);
2718}
2719
2ef28cfb
MW		 2720/**
2721 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2722 * @pf: board private structure
2723 **/
2724void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2725{
2726 struct i40e_hw *hw = &pf->hw;
2727
2728 wr32(hw, I40E_PFINT_DYN_CTL0,
2729 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2730 i40e_flush(hw);
2731}
2732
41c445ff
JB		 2733/**
2734 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2735 * @pf: board private structure
2736 **/
116a57d4 2737void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2738{
2739 struct i40e_hw *hw = &pf->hw;
2740 u32 val;
2741
2742 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2743 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2744 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2745
2746 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2747 i40e_flush(hw);
2748}
2749
2750/**
2751 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2752 * @vsi: pointer to a vsi
2753 * @vector: enable a particular Hw Interrupt vector
2754 **/
2755void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2756{
2757 struct i40e_pf *pf = vsi->back;
2758 struct i40e_hw *hw = &pf->hw;
2759 u32 val;
2760
2761 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2762 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2763 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2764 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2765 /* skip the flush */
41c445ff
JB		 2766}
2767
5c2cebda
CW		 2768/**
2769 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2770 * @vsi: pointer to a vsi
2771 * @vector: enable a particular Hw Interrupt vector
2772 **/
2773void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2774{
2775 struct i40e_pf *pf = vsi->back;
2776 struct i40e_hw *hw = &pf->hw;
2777 u32 val;
2778
2779 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2780 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2781 i40e_flush(hw);
2782}
2783
41c445ff
JB		 2784/**
2785 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2786 * @irq: interrupt number
2787 * @data: pointer to a q_vector
2788 **/
2789static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2790{
2791 struct i40e_q_vector *q_vector = data;
2792
cd0b6fa6 2793 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2794 return IRQ_HANDLED;
2795
2796 napi_schedule(&q_vector->napi);
2797
2798 return IRQ_HANDLED;
2799}
2800
41c445ff
JB		 2801/**
2802 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2803 * @vsi: the VSI being configured
2804 * @basename: name for the vector
2805 *
2806 * Allocates MSI-X vectors and requests interrupts from the kernel.
2807 **/
2808static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2809{
2810 int q_vectors = vsi->num_q_vectors;
2811 struct i40e_pf *pf = vsi->back;
2812 int base = vsi->base_vector;
2813 int rx_int_idx = 0;
2814 int tx_int_idx = 0;
2815 int vector, err;
2816
2817 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2818 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2819
cd0b6fa6 2820 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2821 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2822 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2823 tx_int_idx++;
cd0b6fa6 2824 } else if (q_vector->rx.ring) {
41c445ff
JB		 2825 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2826 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2827 } else if (q_vector->tx.ring) {
41c445ff
JB		 2828 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2829 "%s-%s-%d", basename, "tx", tx_int_idx++);
2830 } else {
2831 /* skip this unused q_vector */
2832 continue;
2833 }
2834 err = request_irq(pf->msix_entries[base + vector].vector,
2835 vsi->irq_handler,
2836 0,
2837 q_vector->name,
2838 q_vector);
2839 if (err) {
2840 dev_info(&pf->pdev->dev,
2841 "%s: request_irq failed, error: %d\n",
2842 __func__, err);
2843 goto free_queue_irqs;
2844 }
2845 /* assign the mask for this irq */
2846 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2847 &q_vector->affinity_mask);
2848 }
2849
63741846 2850 vsi->irqs_ready = true;
41c445ff
JB		 2851 return 0;
2852
2853free_queue_irqs:
2854 while (vector) {
2855 vector--;
2856 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2857 NULL);
2858 free_irq(pf->msix_entries[base + vector].vector,
2859 &(vsi->q_vectors[vector]));
2860 }
2861 return err;
2862}
2863
2864/**
2865 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2866 * @vsi: the VSI being un-configured
2867 **/
2868static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2869{
2870 struct i40e_pf *pf = vsi->back;
2871 struct i40e_hw *hw = &pf->hw;
2872 int base = vsi->base_vector;
2873 int i;
2874
2875 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2876 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2877 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2878 }
2879
2880 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2881 for (i = vsi->base_vector;
2882 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2883 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2884
2885 i40e_flush(hw);
2886 for (i = 0; i < vsi->num_q_vectors; i++)
2887 synchronize_irq(pf->msix_entries[i + base].vector);
2888 } else {
2889 /* Legacy and MSI mode - this stops all interrupt handling */
2890 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2891 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2892 i40e_flush(hw);
2893 synchronize_irq(pf->pdev->irq);
2894 }
2895}
2896
2897/**
2898 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2899 * @vsi: the VSI being configured
2900 **/
2901static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2902{
2903 struct i40e_pf *pf = vsi->back;
2904 int i;
2905
2906 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2907 for (i = vsi->base_vector;
2908 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2909 i40e_irq_dynamic_enable(vsi, i);
2910 } else {
2911 i40e_irq_dynamic_enable_icr0(pf);
2912 }
2913
1022cb6c 2914 i40e_flush(&pf->hw);
41c445ff
JB		 2915 return 0;
2916}
2917
2918/**
2919 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2920 * @pf: board private structure
2921 **/
2922static void i40e_stop_misc_vector(struct i40e_pf *pf)
2923{
2924 /* Disable ICR 0 */
2925 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2926 i40e_flush(&pf->hw);
2927}
2928
2929/**
2930 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2931 * @irq: interrupt number
2932 * @data: pointer to a q_vector
2933 *
2934 * This is the handler used for all MSI/Legacy interrupts, and deals
2935 * with both queue and non-queue interrupts. This is also used in
2936 * MSIX mode to handle the non-queue interrupts.
2937 **/
2938static irqreturn_t i40e_intr(int irq, void *data)
2939{
2940 struct i40e_pf *pf = (struct i40e_pf *)data;
2941 struct i40e_hw *hw = &pf->hw;
5e823066 2942 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2943 u32 icr0, icr0_remaining;
2944 u32 val, ena_mask;
2945
2946 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2947 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2948
116a57d4
SN		 2949 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2950 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2951 goto enable_intr;
41c445ff 2952
cd92e72f
SN		 2953 /* if interrupt but no bits showing, must be SWINT */
2954 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2955 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2956 pf->sw_int_count++;
2957
41c445ff
JB		 2958 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2959 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2960
2961 /* temporarily disable queue cause for NAPI processing */
2962 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2963 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2964 wr32(hw, I40E_QINT_RQCTL(0), qval);
2965
2966 qval = rd32(hw, I40E_QINT_TQCTL(0));
2967 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2968 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2969
2970 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2971 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2972 }
2973
2974 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2975 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2976 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2977 }
2978
2979 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2980 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2981 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2982 }
2983
2984 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2985 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2986 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2987 }
2988
2989 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2990 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2991 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2992 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2993 val = rd32(hw, I40E_GLGEN_RSTAT);
2994 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2995 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2996 if (val == I40E_RESET_CORER) {
41c445ff 2997 pf->corer_count++;
4eb3f768 2998 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2999 pf->globr_count++;
4eb3f768 3000 } else if (val == I40E_RESET_EMPR) {
41c445ff 3001 pf->empr_count++;
4eb3f768
SN		 3002 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3003 }
41c445ff
JB		 3004 }
3005
9c010ee0
ASJ		 3006 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3007 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3008 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3009 }
3010
beb0dff1
JK		 3011 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3012 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3013
3014 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3015 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3016 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3017 }
beb0dff1
JK		 3018 }
3019
41c445ff
JB		 3020 /* If a critical error is pending we have no choice but to reset the
3021 * device.
3022 * Report and mask out any remaining unexpected interrupts.
3023 */
3024 icr0_remaining = icr0 & ena_mask;
3025 if (icr0_remaining) {
3026 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3027 icr0_remaining);
9c010ee0 3028 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3029 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3030 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3031 dev_info(&pf->pdev->dev, "device will be reset\n");
3032 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3033 i40e_service_event_schedule(pf);
41c445ff
JB		 3034 }
3035 ena_mask &= ~icr0_remaining;
3036 }
5e823066 3037 ret = IRQ_HANDLED;
41c445ff 3038
5e823066 3039enable_intr:
41c445ff
JB		 3040 /* re-enable interrupt causes */
3041 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3042 if (!test_bit(__I40E_DOWN, &pf->state)) {
3043 i40e_service_event_schedule(pf);
3044 i40e_irq_dynamic_enable_icr0(pf);
3045 }
3046
5e823066 3047 return ret;
41c445ff
JB		 3048}
3049
cbf61325
ASJ		 3050/**
3051 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3052 * @tx_ring: tx ring to clean
3053 * @budget: how many cleans we're allowed
3054 *
3055 * Returns true if there's any budget left (e.g. the clean is finished)
3056 **/
3057static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3058{
3059 struct i40e_vsi *vsi = tx_ring->vsi;
3060 u16 i = tx_ring->next_to_clean;
3061 struct i40e_tx_buffer *tx_buf;
3062 struct i40e_tx_desc *tx_desc;
3063
3064 tx_buf = &tx_ring->tx_bi[i];
3065 tx_desc = I40E_TX_DESC(tx_ring, i);
3066 i -= tx_ring->count;
3067
3068 do {
3069 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3070
3071 /* if next_to_watch is not set then there is no work pending */
3072 if (!eop_desc)
3073 break;
3074
3075 /* prevent any other reads prior to eop_desc */
3076 read_barrier_depends();
3077
3078 /* if the descriptor isn't done, no work yet to do */
3079 if (!(eop_desc->cmd_type_offset_bsz &
3080 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3081 break;
3082
3083 /* clear next_to_watch to prevent false hangs */
3084 tx_buf->next_to_watch = NULL;
3085
49d7d933
ASJ		 3086 tx_desc->buffer_addr = 0;
3087 tx_desc->cmd_type_offset_bsz = 0;
3088 /* move past filter desc */
3089 tx_buf++;
3090 tx_desc++;
3091 i++;
3092 if (unlikely(!i)) {
3093 i -= tx_ring->count;
3094 tx_buf = tx_ring->tx_bi;
3095 tx_desc = I40E_TX_DESC(tx_ring, 0);
3096 }
cbf61325
ASJ		 3097 /* unmap skb header data */
3098 dma_unmap_single(tx_ring->dev,
3099 dma_unmap_addr(tx_buf, dma),
3100 dma_unmap_len(tx_buf, len),
3101 DMA_TO_DEVICE);
49d7d933
ASJ		 3102 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3103 kfree(tx_buf->raw_buf);
cbf61325 3104
49d7d933
ASJ		 3105 tx_buf->raw_buf = NULL;
3106 tx_buf->tx_flags = 0;
3107 tx_buf->next_to_watch = NULL;
cbf61325 3108 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3109 tx_desc->buffer_addr = 0;
3110 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3111
49d7d933 3112 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3113 tx_buf++;
3114 tx_desc++;
3115 i++;
3116 if (unlikely(!i)) {
3117 i -= tx_ring->count;
3118 tx_buf = tx_ring->tx_bi;
3119 tx_desc = I40E_TX_DESC(tx_ring, 0);
3120 }
3121
3122 /* update budget accounting */
3123 budget--;
3124 } while (likely(budget));
3125
3126 i += tx_ring->count;
3127 tx_ring->next_to_clean = i;
3128
3129 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3130 i40e_irq_dynamic_enable(vsi,
3131 tx_ring->q_vector->v_idx + vsi->base_vector);
3132 }
3133 return budget > 0;
3134}
3135
3136/**
3137 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3138 * @irq: interrupt number
3139 * @data: pointer to a q_vector
3140 **/
3141static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3142{
3143 struct i40e_q_vector *q_vector = data;
3144 struct i40e_vsi *vsi;
3145
3146 if (!q_vector->tx.ring)
3147 return IRQ_HANDLED;
3148
3149 vsi = q_vector->tx.ring->vsi;
3150 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3151
3152 return IRQ_HANDLED;
3153}
3154
41c445ff 3155/**
cd0b6fa6 3156 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3157 * @vsi: the VSI being configured
3158 * @v_idx: vector index
cd0b6fa6 3159 * @qp_idx: queue pair index
41c445ff 3160 **/
cd0b6fa6 3161static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3162{
493fb300 3163 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3164 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3165 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3166
3167 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3168 tx_ring->next = q_vector->tx.ring;
3169 q_vector->tx.ring = tx_ring;
41c445ff 3170 q_vector->tx.count++;
cd0b6fa6
AD		 3171
3172 rx_ring->q_vector = q_vector;
3173 rx_ring->next = q_vector->rx.ring;
3174 q_vector->rx.ring = rx_ring;
3175 q_vector->rx.count++;
41c445ff
JB		 3176}
3177
3178/**
3179 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3180 * @vsi: the VSI being configured
3181 *
3182 * This function maps descriptor rings to the queue-specific vectors
3183 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3184 * one vector per queue pair, but on a constrained vector budget, we
3185 * group the queue pairs as "efficiently" as possible.
3186 **/
3187static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3188{
3189 int qp_remaining = vsi->num_queue_pairs;
3190 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3191 int num_ringpairs;
41c445ff
JB		 3192 int v_start = 0;
3193 int qp_idx = 0;
3194
3195 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3196 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3197 * It is also important to go through all the vectors available to be
3198 * sure that if we don't use all the vectors, that the remaining vectors
3199 * are cleared. This is especially important when decreasing the
3200 * number of queues in use.
41c445ff 3201 */
70114ec4 3202 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3203 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3204
3205 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3206
3207 q_vector->num_ringpairs = num_ringpairs;
3208
3209 q_vector->rx.count = 0;
3210 q_vector->tx.count = 0;
3211 q_vector->rx.ring = NULL;
3212 q_vector->tx.ring = NULL;
3213
3214 while (num_ringpairs--) {
3215 map_vector_to_qp(vsi, v_start, qp_idx);
3216 qp_idx++;
3217 qp_remaining--;
41c445ff
JB		 3218 }
3219 }
3220}
3221
3222/**
3223 * i40e_vsi_request_irq - Request IRQ from the OS
3224 * @vsi: the VSI being configured
3225 * @basename: name for the vector
3226 **/
3227static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3228{
3229 struct i40e_pf *pf = vsi->back;
3230 int err;
3231
3232 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3233 err = i40e_vsi_request_irq_msix(vsi, basename);
3234 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3235 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3236 pf->misc_int_name, pf);
3237 else
3238 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3239 pf->misc_int_name, pf);
3240
3241 if (err)
3242 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3243
3244 return err;
3245}
3246
3247#ifdef CONFIG_NET_POLL_CONTROLLER
3248/**
3249 * i40e_netpoll - A Polling 'interrupt'handler
3250 * @netdev: network interface device structure
3251 *
3252 * This is used by netconsole to send skbs without having to re-enable
3253 * interrupts. It's not called while the normal interrupt routine is executing.
3254 **/
3255static void i40e_netpoll(struct net_device *netdev)
3256{
3257 struct i40e_netdev_priv *np = netdev_priv(netdev);
3258 struct i40e_vsi *vsi = np->vsi;
3259 struct i40e_pf *pf = vsi->back;
3260 int i;
3261
3262 /* if interface is down do nothing */
3263 if (test_bit(__I40E_DOWN, &vsi->state))
3264 return;
3265
3266 pf->flags |= I40E_FLAG_IN_NETPOLL;
3267 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3268 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3269 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3270 } else {
3271 i40e_intr(pf->pdev->irq, netdev);
3272 }
3273 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3274}
3275#endif
3276
23527308
NP		 3277/**
3278 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3279 * @pf: the PF being configured
3280 * @pf_q: the PF queue
3281 * @enable: enable or disable state of the queue
3282 *
3283 * This routine will wait for the given Tx queue of the PF to reach the
3284 * enabled or disabled state.
3285 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3286 * multiple retries; else will return 0 in case of success.
3287 **/
3288static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3289{
3290 int i;
3291 u32 tx_reg;
3292
3293 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3294 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3295 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3296 break;
3297
3298 udelay(10);
3299 }
3300 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3301 return -ETIMEDOUT;
3302
3303 return 0;
3304}
3305
41c445ff
JB		 3306/**
3307 * i40e_vsi_control_tx - Start or stop a VSI's rings
3308 * @vsi: the VSI being configured
3309 * @enable: start or stop the rings
3310 **/
3311static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3312{
3313 struct i40e_pf *pf = vsi->back;
3314 struct i40e_hw *hw = &pf->hw;
23527308 3315 int i, j, pf_q, ret = 0;
41c445ff
JB		 3316 u32 tx_reg;
3317
3318 pf_q = vsi->base_queue;
3319 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3320
3321 /* warn the TX unit of coming changes */
3322 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3323 if (!enable)
3324 udelay(10);
3325
6c5ef620 3326 for (j = 0; j < 50; j++) {
41c445ff 3327 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3328 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3329 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3330 break;
3331 usleep_range(1000, 2000);
3332 }
fda972f6 3333 /* Skip if the queue is already in the requested state */
7c122007 3334 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3335 continue;
41c445ff
JB		 3336
3337 /* turn on/off the queue */
c5c9eb9e
SN		 3338 if (enable) {
3339 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3340 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3341 } else {
41c445ff 3342 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3343 }
41c445ff
JB		 3344
3345 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3346
3347 /* wait for the change to finish */
23527308
NP		 3348 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3349 if (ret) {
3350 dev_info(&pf->pdev->dev,
3351 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3352 __func__, vsi->seid, pf_q,
3353 (enable ? "en" : "dis"));
3354 break;
41c445ff
JB		 3355 }
3356 }
3357
7134f9ce
JB		 3358 if (hw->revision_id == 0)
3359 mdelay(50);
23527308
NP		 3360 return ret;
3361}
3362
3363/**
3364 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3365 * @pf: the PF being configured
3366 * @pf_q: the PF queue
3367 * @enable: enable or disable state of the queue
3368 *
3369 * This routine will wait for the given Rx queue of the PF to reach the
3370 * enabled or disabled state.
3371 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3372 * multiple retries; else will return 0 in case of success.
3373 **/
3374static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3375{
3376 int i;
3377 u32 rx_reg;
3378
3379 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3380 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3381 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3382 break;
3383
3384 udelay(10);
3385 }
3386 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3387 return -ETIMEDOUT;
7134f9ce 3388
41c445ff
JB		 3389 return 0;
3390}
3391
3392/**
3393 * i40e_vsi_control_rx - Start or stop a VSI's rings
3394 * @vsi: the VSI being configured
3395 * @enable: start or stop the rings
3396 **/
3397static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3398{
3399 struct i40e_pf *pf = vsi->back;
3400 struct i40e_hw *hw = &pf->hw;
23527308 3401 int i, j, pf_q, ret = 0;
41c445ff
JB		 3402 u32 rx_reg;
3403
3404 pf_q = vsi->base_queue;
3405 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3406 for (j = 0; j < 50; j++) {
41c445ff 3407 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3408 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3409 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3410 break;
3411 usleep_range(1000, 2000);
3412 }
41c445ff 3413
7c122007
CS		 3414 /* Skip if the queue is already in the requested state */
3415 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3416 continue;
41c445ff
JB		 3417
3418 /* turn on/off the queue */
3419 if (enable)
6c5ef620 3420 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3421 else
6c5ef620 3422 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3423 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3424
3425 /* wait for the change to finish */
23527308
NP		 3426 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3427 if (ret) {
3428 dev_info(&pf->pdev->dev,
3429 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3430 __func__, vsi->seid, pf_q,
3431 (enable ? "en" : "dis"));
3432 break;
41c445ff
JB		 3433 }
3434 }
3435
23527308 3436 return ret;
41c445ff
JB		 3437}
3438
3439/**
3440 * i40e_vsi_control_rings - Start or stop a VSI's rings
3441 * @vsi: the VSI being configured
3442 * @enable: start or stop the rings
3443 **/
fc18eaa0 3444int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3445{
3b867b28 3446 int ret = 0;
41c445ff
JB		 3447
3448 /* do rx first for enable and last for disable */
3449 if (request) {
3450 ret = i40e_vsi_control_rx(vsi, request);
3451 if (ret)
3452 return ret;
3453 ret = i40e_vsi_control_tx(vsi, request);
3454 } else {
3b867b28
ASJ		 3455 /* Ignore return value, we need to shutdown whatever we can */
3456 i40e_vsi_control_tx(vsi, request);
3457 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3458 }
3459
3460 return ret;
3461}
3462
3463/**
3464 * i40e_vsi_free_irq - Free the irq association with the OS
3465 * @vsi: the VSI being configured
3466 **/
3467static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3468{
3469 struct i40e_pf *pf = vsi->back;
3470 struct i40e_hw *hw = &pf->hw;
3471 int base = vsi->base_vector;
3472 u32 val, qp;
3473 int i;
3474
3475 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3476 if (!vsi->q_vectors)
3477 return;
3478
63741846
SN		 3479 if (!vsi->irqs_ready)
3480 return;
3481
3482 vsi->irqs_ready = false;
41c445ff
JB		 3483 for (i = 0; i < vsi->num_q_vectors; i++) {
3484 u16 vector = i + base;
3485
3486 /* free only the irqs that were actually requested */
78681b1f
SN		 3487 if (!vsi->q_vectors[i] ||
3488 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3489 continue;
3490
3491 /* clear the affinity_mask in the IRQ descriptor */
3492 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3493 NULL);
3494 free_irq(pf->msix_entries[vector].vector,
493fb300 3495 vsi->q_vectors[i]);
41c445ff
JB		 3496
3497 /* Tear down the interrupt queue link list
3498 *
3499 * We know that they come in pairs and always
3500 * the Rx first, then the Tx. To clear the
3501 * link list, stick the EOL value into the
3502 * next_q field of the registers.
3503 */
3504 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3505 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3506 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3507 val |= I40E_QUEUE_END_OF_LIST
3508 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3509 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3510
3511 while (qp != I40E_QUEUE_END_OF_LIST) {
3512 u32 next;
3513
3514 val = rd32(hw, I40E_QINT_RQCTL(qp));
3515
3516 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3517 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3518 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3519 I40E_QINT_RQCTL_INTEVENT_MASK);
3520
3521 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3522 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3523
3524 wr32(hw, I40E_QINT_RQCTL(qp), val);
3525
3526 val = rd32(hw, I40E_QINT_TQCTL(qp));
3527
3528 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3529 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3530
3531 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3532 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3533 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3534 I40E_QINT_TQCTL_INTEVENT_MASK);
3535
3536 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3537 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3538
3539 wr32(hw, I40E_QINT_TQCTL(qp), val);
3540 qp = next;
3541 }
3542 }
3543 } else {
3544 free_irq(pf->pdev->irq, pf);
3545
3546 val = rd32(hw, I40E_PFINT_LNKLST0);
3547 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3548 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3549 val |= I40E_QUEUE_END_OF_LIST
3550 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3551 wr32(hw, I40E_PFINT_LNKLST0, val);
3552
3553 val = rd32(hw, I40E_QINT_RQCTL(qp));
3554 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3555 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3556 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3557 I40E_QINT_RQCTL_INTEVENT_MASK);
3558
3559 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3560 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3561
3562 wr32(hw, I40E_QINT_RQCTL(qp), val);
3563
3564 val = rd32(hw, I40E_QINT_TQCTL(qp));
3565
3566 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3567 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3568 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3569 I40E_QINT_TQCTL_INTEVENT_MASK);
3570
3571 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3572 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3573
3574 wr32(hw, I40E_QINT_TQCTL(qp), val);
3575 }
3576}
3577
493fb300
AD		 3578/**
3579 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3580 * @vsi: the VSI being configured
3581 * @v_idx: Index of vector to be freed
3582 *
3583 * This function frees the memory allocated to the q_vector. In addition if
3584 * NAPI is enabled it will delete any references to the NAPI struct prior
3585 * to freeing the q_vector.
3586 **/
3587static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3588{
3589 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3590 struct i40e_ring *ring;
493fb300
AD		 3591
3592 if (!q_vector)
3593 return;
3594
3595 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3596 i40e_for_each_ring(ring, q_vector->tx)
3597 ring->q_vector = NULL;
3598
3599 i40e_for_each_ring(ring, q_vector->rx)
3600 ring->q_vector = NULL;
493fb300
AD		 3601
3602 /* only VSI w/ an associated netdev is set up w/ NAPI */
3603 if (vsi->netdev)
3604 netif_napi_del(&q_vector->napi);
3605
3606 vsi->q_vectors[v_idx] = NULL;
3607
3608 kfree_rcu(q_vector, rcu);
3609}
3610
41c445ff
JB		 3611/**
3612 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3613 * @vsi: the VSI being un-configured
3614 *
3615 * This frees the memory allocated to the q_vectors and
3616 * deletes references to the NAPI struct.
3617 **/
3618static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3619{
3620 int v_idx;
3621
493fb300
AD		 3622 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3623 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3624}
3625
3626/**
3627 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3628 * @pf: board private structure
3629 **/
3630static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3631{
3632 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3633 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3634 pci_disable_msix(pf->pdev);
3635 kfree(pf->msix_entries);
3636 pf->msix_entries = NULL;
3637 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3638 pci_disable_msi(pf->pdev);
3639 }
3640 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3641}
3642
3643/**
3644 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3645 * @pf: board private structure
3646 *
3647 * We go through and clear interrupt specific resources and reset the structure
3648 * to pre-load conditions
3649 **/
3650static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3651{
3652 int i;
3653
3654 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3655 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3656 if (pf->vsi[i])
3657 i40e_vsi_free_q_vectors(pf->vsi[i]);
3658 i40e_reset_interrupt_capability(pf);
3659}
3660
3661/**
3662 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3663 * @vsi: the VSI being configured
3664 **/
3665static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3666{
3667 int q_idx;
3668
3669 if (!vsi->netdev)
3670 return;
3671
3672 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3673 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3674}
3675
3676/**
3677 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3678 * @vsi: the VSI being configured
3679 **/
3680static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3681{
3682 int q_idx;
3683
3684 if (!vsi->netdev)
3685 return;
3686
3687 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3688 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3689}
3690
90ef8d47
SN		 3691/**
3692 * i40e_vsi_close - Shut down a VSI
3693 * @vsi: the vsi to be quelled
3694 **/
3695static void i40e_vsi_close(struct i40e_vsi *vsi)
3696{
3697 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3698 i40e_down(vsi);
3699 i40e_vsi_free_irq(vsi);
3700 i40e_vsi_free_tx_resources(vsi);
3701 i40e_vsi_free_rx_resources(vsi);
3702}
3703
41c445ff
JB		 3704/**
3705 * i40e_quiesce_vsi - Pause a given VSI
3706 * @vsi: the VSI being paused
3707 **/
3708static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3709{
3710 if (test_bit(__I40E_DOWN, &vsi->state))
3711 return;
3712
3713 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3714 if (vsi->netdev && netif_running(vsi->netdev)) {
3715 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3716 } else {
90ef8d47 3717 i40e_vsi_close(vsi);
41c445ff
JB		 3718 }
3719}
3720
3721/**
3722 * i40e_unquiesce_vsi - Resume a given VSI
3723 * @vsi: the VSI being resumed
3724 **/
3725static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3726{
3727 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3728 return;
3729
3730 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3731 if (vsi->netdev && netif_running(vsi->netdev))
3732 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3733 else
8276f757 3734 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3735}
3736
3737/**
3738 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3739 * @pf: the PF
3740 **/
3741static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3742{
3743 int v;
3744
505682cd 3745 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3746 if (pf->vsi[v])
3747 i40e_quiesce_vsi(pf->vsi[v]);
3748 }
3749}
3750
3751/**
3752 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3753 * @pf: the PF
3754 **/
3755static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3756{
3757 int v;
3758
505682cd 3759 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3760 if (pf->vsi[v])
3761 i40e_unquiesce_vsi(pf->vsi[v]);
3762 }
3763}
3764
3765/**
3766 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3767 * @dcbcfg: the corresponding DCBx configuration structure
3768 *
3769 * Return the number of TCs from given DCBx configuration
3770 **/
3771static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3772{
078b5876
JB		 3773 u8 num_tc = 0;
3774 int i;
41c445ff
JB		 3775
3776 /* Scan the ETS Config Priority Table to find
3777 * traffic class enabled for a given priority
3778 * and use the traffic class index to get the
3779 * number of traffic classes enabled
3780 */
3781 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3782 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3783 num_tc = dcbcfg->etscfg.prioritytable[i];
3784 }
3785
3786 /* Traffic class index starts from zero so
3787 * increment to return the actual count
3788 */
078b5876 3789 return num_tc + 1;
41c445ff
JB		 3790}
3791
3792/**
3793 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3794 * @dcbcfg: the corresponding DCBx configuration structure
3795 *
3796 * Query the current DCB configuration and return the number of
3797 * traffic classes enabled from the given DCBX config
3798 **/
3799static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3800{
3801 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3802 u8 enabled_tc = 1;
3803 u8 i;
3804
3805 for (i = 0; i < num_tc; i++)
3806 enabled_tc |= 1 << i;
3807
3808 return enabled_tc;
3809}
3810
3811/**
3812 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3813 * @pf: PF being queried
3814 *
3815 * Return number of traffic classes enabled for the given PF
3816 **/
3817static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3818{
3819 struct i40e_hw *hw = &pf->hw;
3820 u8 i, enabled_tc;
3821 u8 num_tc = 0;
3822 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3823
3824 /* If DCB is not enabled then always in single TC */
3825 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3826 return 1;
3827
3828 /* MFP mode return count of enabled TCs for this PF */
3829 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3830 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3831 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3832 if (enabled_tc & (1 << i))
3833 num_tc++;
3834 }
3835 return num_tc;
3836 }
3837
3838 /* SFP mode will be enabled for all TCs on port */
3839 return i40e_dcb_get_num_tc(dcbcfg);
3840}
3841
3842/**
3843 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3844 * @pf: PF being queried
3845 *
3846 * Return a bitmap for first enabled traffic class for this PF.
3847 **/
3848static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3849{
3850 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3851 u8 i = 0;
3852
3853 if (!enabled_tc)
3854 return 0x1; /* TC0 */
3855
3856 /* Find the first enabled TC */
3857 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3858 if (enabled_tc & (1 << i))
3859 break;
3860 }
3861
3862 return 1 << i;
3863}
3864
3865/**
3866 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3867 * @pf: PF being queried
3868 *
3869 * Return a bitmap for enabled traffic classes for this PF.
3870 **/
3871static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3872{
3873 /* If DCB is not enabled for this PF then just return default TC */
3874 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3875 return i40e_pf_get_default_tc(pf);
3876
3877 /* MFP mode will have enabled TCs set by FW */
3878 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3879 return pf->hw.func_caps.enabled_tcmap;
3880
3881 /* SFP mode we want PF to be enabled for all TCs */
3882 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3883}
3884
3885/**
3886 * i40e_vsi_get_bw_info - Query VSI BW Information
3887 * @vsi: the VSI being queried
3888 *
3889 * Returns 0 on success, negative value on failure
3890 **/
3891static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3892{
3893 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3894 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3895 struct i40e_pf *pf = vsi->back;
3896 struct i40e_hw *hw = &pf->hw;
dcae29be 3897 i40e_status aq_ret;
41c445ff 3898 u32 tc_bw_max;
41c445ff
JB		 3899 int i;
3900
3901 /* Get the VSI level BW configuration */
dcae29be
JB		 3902 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3903 if (aq_ret) {
41c445ff
JB		 3904 dev_info(&pf->pdev->dev,
3905 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3906 aq_ret, pf->hw.aq.asq_last_status);
3907 return -EINVAL;
41c445ff
JB		 3908 }
3909
3910 /* Get the VSI level BW configuration per TC */
dcae29be 3911 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3912 NULL);
dcae29be 3913 if (aq_ret) {
41c445ff
JB		 3914 dev_info(&pf->pdev->dev,
3915 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3916 aq_ret, pf->hw.aq.asq_last_status);
3917 return -EINVAL;
41c445ff
JB		 3918 }
3919
3920 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3921 dev_info(&pf->pdev->dev,
3922 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3923 bw_config.tc_valid_bits,
3924 bw_ets_config.tc_valid_bits);
3925 /* Still continuing */
3926 }
3927
3928 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3929 vsi->bw_max_quanta = bw_config.max_bw;
3930 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3931 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3932 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3933 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3934 vsi->bw_ets_limit_credits[i] =
3935 le16_to_cpu(bw_ets_config.credits[i]);
3936 /* 3 bits out of 4 for each TC */
3937 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3938 }
078b5876 3939
dcae29be 3940 return 0;
41c445ff
JB		 3941}
3942
3943/**
3944 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3945 * @vsi: the VSI being configured
3946 * @enabled_tc: TC bitmap
3947 * @bw_credits: BW shared credits per TC
3948 *
3949 * Returns 0 on success, negative value on failure
3950 **/
dcae29be 3951static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3952 u8 *bw_share)
3953{
3954 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3955 i40e_status aq_ret;
3956 int i;
41c445ff
JB		 3957
3958 bw_data.tc_valid_bits = enabled_tc;
3959 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3960 bw_data.tc_bw_credits[i] = bw_share[i];
3961
dcae29be
JB		 3962 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3963 NULL);
3964 if (aq_ret) {
41c445ff 3965 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3966 "AQ command Config VSI BW allocation per TC failed = %d\n",
3967 vsi->back->hw.aq.asq_last_status);
dcae29be 3968 return -EINVAL;
41c445ff
JB		 3969 }
3970
3971 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3972 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3973
dcae29be 3974 return 0;
41c445ff
JB		 3975}
3976
3977/**
3978 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3979 * @vsi: the VSI being configured
3980 * @enabled_tc: TC map to be enabled
3981 *
3982 **/
3983static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3984{
3985 struct net_device *netdev = vsi->netdev;
3986 struct i40e_pf *pf = vsi->back;
3987 struct i40e_hw *hw = &pf->hw;
3988 u8 netdev_tc = 0;
3989 int i;
3990 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3991
3992 if (!netdev)
3993 return;
3994
3995 if (!enabled_tc) {
3996 netdev_reset_tc(netdev);
3997 return;
3998 }
3999
4000 /* Set up actual enabled TCs on the VSI */
4001 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4002 return;
4003
4004 /* set per TC queues for the VSI */
4005 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4006 /* Only set TC queues for enabled tcs
4007 *
4008 * e.g. For a VSI that has TC0 and TC3 enabled the
4009 * enabled_tc bitmap would be 0x00001001; the driver
4010 * will set the numtc for netdev as 2 that will be
4011 * referenced by the netdev layer as TC 0 and 1.
4012 */
4013 if (vsi->tc_config.enabled_tc & (1 << i))
4014 netdev_set_tc_queue(netdev,
4015 vsi->tc_config.tc_info[i].netdev_tc,
4016 vsi->tc_config.tc_info[i].qcount,
4017 vsi->tc_config.tc_info[i].qoffset);
4018 }
4019
4020 /* Assign UP2TC map for the VSI */
4021 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4022 /* Get the actual TC# for the UP */
4023 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4024 /* Get the mapped netdev TC# for the UP */
4025 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4026 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4027 }
4028}
4029
4030/**
4031 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4032 * @vsi: the VSI being configured
4033 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4034 **/
4035static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4036 struct i40e_vsi_context *ctxt)
4037{
4038 /* copy just the sections touched not the entire info
4039 * since not all sections are valid as returned by
4040 * update vsi params
4041 */
4042 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4043 memcpy(&vsi->info.queue_mapping,
4044 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4045 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4046 sizeof(vsi->info.tc_mapping));
4047}
4048
4049/**
4050 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4051 * @vsi: VSI to be configured
4052 * @enabled_tc: TC bitmap
4053 *
4054 * This configures a particular VSI for TCs that are mapped to the
4055 * given TC bitmap. It uses default bandwidth share for TCs across
4056 * VSIs to configure TC for a particular VSI.
4057 *
4058 * NOTE:
4059 * It is expected that the VSI queues have been quisced before calling
4060 * this function.
4061 **/
4062static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4063{
4064 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4065 struct i40e_vsi_context ctxt;
4066 int ret = 0;
4067 int i;
4068
4069 /* Check if enabled_tc is same as existing or new TCs */
4070 if (vsi->tc_config.enabled_tc == enabled_tc)
4071 return ret;
4072
4073 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4074 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4075 if (enabled_tc & (1 << i))
4076 bw_share[i] = 1;
4077 }
4078
4079 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4080 if (ret) {
4081 dev_info(&vsi->back->pdev->dev,
4082 "Failed configuring TC map %d for VSI %d\n",
4083 enabled_tc, vsi->seid);
4084 goto out;
4085 }
4086
4087 /* Update Queue Pairs Mapping for currently enabled UPs */
4088 ctxt.seid = vsi->seid;
4089 ctxt.pf_num = vsi->back->hw.pf_id;
4090 ctxt.vf_num = 0;
4091 ctxt.uplink_seid = vsi->uplink_seid;
4092 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4093 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4094
4095 /* Update the VSI after updating the VSI queue-mapping information */
4096 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4097 if (ret) {
4098 dev_info(&vsi->back->pdev->dev,
4099 "update vsi failed, aq_err=%d\n",
4100 vsi->back->hw.aq.asq_last_status);
4101 goto out;
4102 }
4103 /* update the local VSI info with updated queue map */
4104 i40e_vsi_update_queue_map(vsi, &ctxt);
4105 vsi->info.valid_sections = 0;
4106
4107 /* Update current VSI BW information */
4108 ret = i40e_vsi_get_bw_info(vsi);
4109 if (ret) {
4110 dev_info(&vsi->back->pdev->dev,
4111 "Failed updating vsi bw info, aq_err=%d\n",
4112 vsi->back->hw.aq.asq_last_status);
4113 goto out;
4114 }
4115
4116 /* Update the netdev TC setup */
4117 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4118out:
4119 return ret;
4120}
4121
4e3b35b0
NP		 4122/**
4123 * i40e_veb_config_tc - Configure TCs for given VEB
4124 * @veb: given VEB
4125 * @enabled_tc: TC bitmap
4126 *
4127 * Configures given TC bitmap for VEB (switching) element
4128 **/
4129int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4130{
4131 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4132 struct i40e_pf *pf = veb->pf;
4133 int ret = 0;
4134 int i;
4135
4136 /* No TCs or already enabled TCs just return */
4137 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4138 return ret;
4139
4140 bw_data.tc_valid_bits = enabled_tc;
4141 /* bw_data.absolute_credits is not set (relative) */
4142
4143 /* Enable ETS TCs with equal BW Share for now */
4144 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4145 if (enabled_tc & (1 << i))
4146 bw_data.tc_bw_share_credits[i] = 1;
4147 }
4148
4149 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4150 &bw_data, NULL);
4151 if (ret) {
4152 dev_info(&pf->pdev->dev,
4153 "veb bw config failed, aq_err=%d\n",
4154 pf->hw.aq.asq_last_status);
4155 goto out;
4156 }
4157
4158 /* Update the BW information */
4159 ret = i40e_veb_get_bw_info(veb);
4160 if (ret) {
4161 dev_info(&pf->pdev->dev,
4162 "Failed getting veb bw config, aq_err=%d\n",
4163 pf->hw.aq.asq_last_status);
4164 }
4165
4166out:
4167 return ret;
4168}
4169
4170#ifdef CONFIG_I40E_DCB
4171/**
4172 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4173 * @pf: PF struct
4174 *
4175 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4176 * the caller would've quiesce all the VSIs before calling
4177 * this function
4178 **/
4179static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4180{
4181 u8 tc_map = 0;
4182 int ret;
4183 u8 v;
4184
4185 /* Enable the TCs available on PF to all VEBs */
4186 tc_map = i40e_pf_get_tc_map(pf);
4187 for (v = 0; v < I40E_MAX_VEB; v++) {
4188 if (!pf->veb[v])
4189 continue;
4190 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4191 if (ret) {
4192 dev_info(&pf->pdev->dev,
4193 "Failed configuring TC for VEB seid=%d\n",
4194 pf->veb[v]->seid);
4195 /* Will try to configure as many components */
4196 }
4197 }
4198
4199 /* Update each VSI */
505682cd 4200 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4201 if (!pf->vsi[v])
4202 continue;
4203
4204 /* - Enable all TCs for the LAN VSI
4205 * - For all others keep them at TC0 for now
4206 */
4207 if (v == pf->lan_vsi)
4208 tc_map = i40e_pf_get_tc_map(pf);
4209 else
4210 tc_map = i40e_pf_get_default_tc(pf);
4211
4212 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4213 if (ret) {
4214 dev_info(&pf->pdev->dev,
4215 "Failed configuring TC for VSI seid=%d\n",
4216 pf->vsi[v]->seid);
4217 /* Will try to configure as many components */
4218 } else {
0672a091
NP		 4219 /* Re-configure VSI vectors based on updated TC map */
4220 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4221 if (pf->vsi[v]->netdev)
4222 i40e_dcbnl_set_all(pf->vsi[v]);
4223 }
4224 }
4225}
4226
4227/**
4228 * i40e_init_pf_dcb - Initialize DCB configuration
4229 * @pf: PF being configured
4230 *
4231 * Query the current DCB configuration and cache it
4232 * in the hardware structure
4233 **/
4234static int i40e_init_pf_dcb(struct i40e_pf *pf)
4235{
4236 struct i40e_hw *hw = &pf->hw;
4237 int err = 0;
4238
4239 if (pf->hw.func_caps.npar_enable)
4240 goto out;
4241
4242 /* Get the initial DCB configuration */
4243 err = i40e_init_dcb(hw);
4244 if (!err) {
4245 /* Device/Function is not DCBX capable */
4246 if ((!hw->func_caps.dcb) ||
4247 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4248 dev_info(&pf->pdev->dev,
4249 "DCBX offload is not supported or is disabled for this PF.\n");
4250
4251 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4252 goto out;
4253
4254 } else {
4255 /* When status is not DISABLED then DCBX in FW */
4256 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4257 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4258
4259 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4260 /* Enable DCB tagging only when more than one TC */
4261 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4262 pf->flags |= I40E_FLAG_DCB_ENABLED;
4e3b35b0 4263 }
014269ff
NP		 4264 } else {
4265 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4266 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4267 }
4268
4269out:
4270 return err;
4271}
4272#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4273#define SPEED_SIZE 14
4274#define FC_SIZE 8
4275/**
4276 * i40e_print_link_message - print link up or down
4277 * @vsi: the VSI for which link needs a message
4278 */
4279static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4280{
4281 char speed[SPEED_SIZE] = "Unknown";
4282 char fc[FC_SIZE] = "RX/TX";
4283
4284 if (!isup) {
4285 netdev_info(vsi->netdev, "NIC Link is Down\n");
4286 return;
4287 }
4288
4289 switch (vsi->back->hw.phy.link_info.link_speed) {
4290 case I40E_LINK_SPEED_40GB:
4291 strncpy(speed, "40 Gbps", SPEED_SIZE);
4292 break;
4293 case I40E_LINK_SPEED_10GB:
4294 strncpy(speed, "10 Gbps", SPEED_SIZE);
4295 break;
4296 case I40E_LINK_SPEED_1GB:
4297 strncpy(speed, "1000 Mbps", SPEED_SIZE);
4298 break;
4299 default:
4300 break;
4301 }
4302
4303 switch (vsi->back->hw.fc.current_mode) {
4304 case I40E_FC_FULL:
4305 strncpy(fc, "RX/TX", FC_SIZE);
4306 break;
4307 case I40E_FC_TX_PAUSE:
4308 strncpy(fc, "TX", FC_SIZE);
4309 break;
4310 case I40E_FC_RX_PAUSE:
4311 strncpy(fc, "RX", FC_SIZE);
4312 break;
4313 default:
4314 strncpy(fc, "None", FC_SIZE);
4315 break;
4316 }
4317
4318 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4319 speed, fc);
4320}
4e3b35b0 4321
41c445ff
JB		 4322/**
4323 * i40e_up_complete - Finish the last steps of bringing up a connection
4324 * @vsi: the VSI being configured
4325 **/
4326static int i40e_up_complete(struct i40e_vsi *vsi)
4327{
4328 struct i40e_pf *pf = vsi->back;
c56999f9 4329 u8 set_fc_aq_fail = 0;
41c445ff
JB		 4330 int err;
4331
c56999f9
CS		 4332 /* force flow control off */
4333 i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
4334
41c445ff
JB		 4335 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4336 i40e_vsi_configure_msix(vsi);
4337 else
4338 i40e_configure_msi_and_legacy(vsi);
4339
4340 /* start rings */
4341 err = i40e_vsi_control_rings(vsi, true);
4342 if (err)
4343 return err;
4344
4345 clear_bit(__I40E_DOWN, &vsi->state);
4346 i40e_napi_enable_all(vsi);
4347 i40e_vsi_enable_irq(vsi);
4348
4349 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4350 (vsi->netdev)) {
cf05ed08 4351 i40e_print_link_message(vsi, true);
41c445ff
JB		 4352 netif_tx_start_all_queues(vsi->netdev);
4353 netif_carrier_on(vsi->netdev);
6d779b41 4354 } else if (vsi->netdev) {
cf05ed08 4355 i40e_print_link_message(vsi, false);
41c445ff 4356 }
ca64fa4e
ASJ		 4357
4358 /* replay FDIR SB filters */
4359 if (vsi->type == I40E_VSI_FDIR)
4360 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4361 i40e_service_event_schedule(pf);
4362
4363 return 0;
4364}
4365
4366/**
4367 * i40e_vsi_reinit_locked - Reset the VSI
4368 * @vsi: the VSI being configured
4369 *
4370 * Rebuild the ring structs after some configuration
4371 * has changed, e.g. MTU size.
4372 **/
4373static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4374{
4375 struct i40e_pf *pf = vsi->back;
4376
4377 WARN_ON(in_interrupt());
4378 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4379 usleep_range(1000, 2000);
4380 i40e_down(vsi);
4381
4382 /* Give a VF some time to respond to the reset. The
4383 * two second wait is based upon the watchdog cycle in
4384 * the VF driver.
4385 */
4386 if (vsi->type == I40E_VSI_SRIOV)
4387 msleep(2000);
4388 i40e_up(vsi);
4389 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4390}
4391
4392/**
4393 * i40e_up - Bring the connection back up after being down
4394 * @vsi: the VSI being configured
4395 **/
4396int i40e_up(struct i40e_vsi *vsi)
4397{
4398 int err;
4399
4400 err = i40e_vsi_configure(vsi);
4401 if (!err)
4402 err = i40e_up_complete(vsi);
4403
4404 return err;
4405}
4406
4407/**
4408 * i40e_down - Shutdown the connection processing
4409 * @vsi: the VSI being stopped
4410 **/
4411void i40e_down(struct i40e_vsi *vsi)
4412{
4413 int i;
4414
4415 /* It is assumed that the caller of this function
4416 * sets the vsi->state __I40E_DOWN bit.
4417 */
4418 if (vsi->netdev) {
4419 netif_carrier_off(vsi->netdev);
4420 netif_tx_disable(vsi->netdev);
4421 }
4422 i40e_vsi_disable_irq(vsi);
4423 i40e_vsi_control_rings(vsi, false);
4424 i40e_napi_disable_all(vsi);
4425
4426 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4427 i40e_clean_tx_ring(vsi->tx_rings[i]);
4428 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4429 }
4430}
4431
4432/**
4433 * i40e_setup_tc - configure multiple traffic classes
4434 * @netdev: net device to configure
4435 * @tc: number of traffic classes to enable
4436 **/
4437static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4438{
4439 struct i40e_netdev_priv *np = netdev_priv(netdev);
4440 struct i40e_vsi *vsi = np->vsi;
4441 struct i40e_pf *pf = vsi->back;
4442 u8 enabled_tc = 0;
4443 int ret = -EINVAL;
4444 int i;
4445
4446 /* Check if DCB enabled to continue */
4447 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4448 netdev_info(netdev, "DCB is not enabled for adapter\n");
4449 goto exit;
4450 }
4451
4452 /* Check if MFP enabled */
4453 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4454 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4455 goto exit;
4456 }
4457
4458 /* Check whether tc count is within enabled limit */
4459 if (tc > i40e_pf_get_num_tc(pf)) {
4460 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4461 goto exit;
4462 }
4463
4464 /* Generate TC map for number of tc requested */
4465 for (i = 0; i < tc; i++)
4466 enabled_tc |= (1 << i);
4467
4468 /* Requesting same TC configuration as already enabled */
4469 if (enabled_tc == vsi->tc_config.enabled_tc)
4470 return 0;
4471
4472 /* Quiesce VSI queues */
4473 i40e_quiesce_vsi(vsi);
4474
4475 /* Configure VSI for enabled TCs */
4476 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4477 if (ret) {
4478 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4479 vsi->seid);
4480 goto exit;
4481 }
4482
4483 /* Unquiesce VSI */
4484 i40e_unquiesce_vsi(vsi);
4485
4486exit:
4487 return ret;
4488}
4489
4490/**
4491 * i40e_open - Called when a network interface is made active
4492 * @netdev: network interface device structure
4493 *
4494 * The open entry point is called when a network interface is made
4495 * active by the system (IFF_UP). At this point all resources needed
4496 * for transmit and receive operations are allocated, the interrupt
4497 * handler is registered with the OS, the netdev watchdog subtask is
4498 * enabled, and the stack is notified that the interface is ready.
4499 *
4500 * Returns 0 on success, negative value on failure
4501 **/
4502static int i40e_open(struct net_device *netdev)
4503{
4504 struct i40e_netdev_priv *np = netdev_priv(netdev);
4505 struct i40e_vsi *vsi = np->vsi;
4506 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4507 int err;
4508
4eb3f768
SN		 4509 /* disallow open during test or if eeprom is broken */
4510 if (test_bit(__I40E_TESTING, &pf->state) ||
4511 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4512 return -EBUSY;
4513
4514 netif_carrier_off(netdev);
4515
6c167f58
EK		 4516 err = i40e_vsi_open(vsi);
4517 if (err)
4518 return err;
4519
059dab69
JB		 4520 /* configure global TSO hardware offload settings */
4521 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4522 TCP_FLAG_FIN) >> 16);
4523 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4524 TCP_FLAG_FIN |
4525 TCP_FLAG_CWR) >> 16);
4526 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4527
6c167f58
EK		 4528#ifdef CONFIG_I40E_VXLAN
4529 vxlan_get_rx_port(netdev);
4530#endif
4531
4532 return 0;
4533}
4534
4535/**
4536 * i40e_vsi_open -
4537 * @vsi: the VSI to open
4538 *
4539 * Finish initialization of the VSI.
4540 *
4541 * Returns 0 on success, negative value on failure
4542 **/
4543int i40e_vsi_open(struct i40e_vsi *vsi)
4544{
4545 struct i40e_pf *pf = vsi->back;
4546 char int_name[IFNAMSIZ];
4547 int err;
4548
41c445ff
JB		 4549 /* allocate descriptors */
4550 err = i40e_vsi_setup_tx_resources(vsi);
4551 if (err)
4552 goto err_setup_tx;
4553 err = i40e_vsi_setup_rx_resources(vsi);
4554 if (err)
4555 goto err_setup_rx;
4556
4557 err = i40e_vsi_configure(vsi);
4558 if (err)
4559 goto err_setup_rx;
4560
c22e3c6c
SN		 4561 if (vsi->netdev) {
4562 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4563 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4564 err = i40e_vsi_request_irq(vsi, int_name);
4565 if (err)
4566 goto err_setup_rx;
41c445ff 4567
c22e3c6c
SN		 4568 /* Notify the stack of the actual queue counts. */
4569 err = netif_set_real_num_tx_queues(vsi->netdev,
4570 vsi->num_queue_pairs);
4571 if (err)
4572 goto err_set_queues;
25946ddb 4573
c22e3c6c
SN		 4574 err = netif_set_real_num_rx_queues(vsi->netdev,
4575 vsi->num_queue_pairs);
4576 if (err)
4577 goto err_set_queues;
8a9eb7d3
SN		 4578
4579 } else if (vsi->type == I40E_VSI_FDIR) {
4580 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4581 dev_driver_string(&pf->pdev->dev));
4582 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4583 } else {
ce9ccb17 4584 err = -EINVAL;
6c167f58
EK		 4585 goto err_setup_rx;
4586 }
25946ddb 4587
41c445ff
JB		 4588 err = i40e_up_complete(vsi);
4589 if (err)
4590 goto err_up_complete;
4591
41c445ff
JB		 4592 return 0;
4593
4594err_up_complete:
4595 i40e_down(vsi);
25946ddb 4596err_set_queues:
41c445ff
JB		 4597 i40e_vsi_free_irq(vsi);
4598err_setup_rx:
4599 i40e_vsi_free_rx_resources(vsi);
4600err_setup_tx:
4601 i40e_vsi_free_tx_resources(vsi);
4602 if (vsi == pf->vsi[pf->lan_vsi])
4603 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4604
4605 return err;
4606}
4607
17a73f6b
JG		 4608/**
4609 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4610 * @pf: Pointer to pf
4611 *
4612 * This function destroys the hlist where all the Flow Director
4613 * filters were saved.
4614 **/
4615static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4616{
4617 struct i40e_fdir_filter *filter;
4618 struct hlist_node *node2;
4619
4620 hlist_for_each_entry_safe(filter, node2,
4621 &pf->fdir_filter_list, fdir_node) {
4622 hlist_del(&filter->fdir_node);
4623 kfree(filter);
4624 }
4625 pf->fdir_pf_active_filters = 0;
4626}
4627
41c445ff
JB		 4628/**
4629 * i40e_close - Disables a network interface
4630 * @netdev: network interface device structure
4631 *
4632 * The close entry point is called when an interface is de-activated
4633 * by the OS. The hardware is still under the driver's control, but
4634 * this netdev interface is disabled.
4635 *
4636 * Returns 0, this is not allowed to fail
4637 **/
4638static int i40e_close(struct net_device *netdev)
4639{
4640 struct i40e_netdev_priv *np = netdev_priv(netdev);
4641 struct i40e_vsi *vsi = np->vsi;
4642
90ef8d47 4643 i40e_vsi_close(vsi);
41c445ff
JB		 4644
4645 return 0;
4646}
4647
4648/**
4649 * i40e_do_reset - Start a PF or Core Reset sequence
4650 * @pf: board private structure
4651 * @reset_flags: which reset is requested
4652 *
4653 * The essential difference in resets is that the PF Reset
4654 * doesn't clear the packet buffers, doesn't reset the PE
4655 * firmware, and doesn't bother the other PFs on the chip.
4656 **/
4657void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4658{
4659 u32 val;
4660
4661 WARN_ON(in_interrupt());
4662
263fc48f
MW		 4663 if (i40e_check_asq_alive(&pf->hw))
4664 i40e_vc_notify_reset(pf);
4665
41c445ff
JB		 4666 /* do the biggest reset indicated */
4667 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4668
4669 /* Request a Global Reset
4670 *
4671 * This will start the chip's countdown to the actual full
4672 * chip reset event, and a warning interrupt to be sent
4673 * to all PFs, including the requestor. Our handler
4674 * for the warning interrupt will deal with the shutdown
4675 * and recovery of the switch setup.
4676 */
69bfb110 4677 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4678 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4679 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4680 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4681
4682 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4683
4684 /* Request a Core Reset
4685 *
4686 * Same as Global Reset, except does *not* include the MAC/PHY
4687 */
69bfb110 4688 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4689 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4690 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4691 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4692 i40e_flush(&pf->hw);
4693
7823fe34
SN		 4694 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4695
4696 /* Request a Firmware Reset
4697 *
4698 * Same as Global reset, plus restarting the
4699 * embedded firmware engine.
4700 */
4701 /* enable EMP Reset */
4702 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4703 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4704 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4705
4706 /* force the reset */
4707 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4708 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4709 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4710 i40e_flush(&pf->hw);
4711
41c445ff
JB		 4712 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4713
4714 /* Request a PF Reset
4715 *
4716 * Resets only the PF-specific registers
4717 *
4718 * This goes directly to the tear-down and rebuild of
4719 * the switch, since we need to do all the recovery as
4720 * for the Core Reset.
4721 */
69bfb110 4722 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4723 i40e_handle_reset_warning(pf);
4724
4725 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4726 int v;
4727
4728 /* Find the VSI(s) that requested a re-init */
4729 dev_info(&pf->pdev->dev,
4730 "VSI reinit requested\n");
505682cd 4731 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4732 struct i40e_vsi *vsi = pf->vsi[v];
4733 if (vsi != NULL &&
4734 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4735 i40e_vsi_reinit_locked(pf->vsi[v]);
4736 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4737 }
4738 }
4739
b5d06f05
NP		 4740 /* no further action needed, so return now */
4741 return;
4742 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4743 int v;
4744
4745 /* Find the VSI(s) that needs to be brought down */
4746 dev_info(&pf->pdev->dev, "VSI down requested\n");
4747 for (v = 0; v < pf->num_alloc_vsi; v++) {
4748 struct i40e_vsi *vsi = pf->vsi[v];
4749 if (vsi != NULL &&
4750 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4751 set_bit(__I40E_DOWN, &vsi->state);
4752 i40e_down(vsi);
4753 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4754 }
4755 }
4756
41c445ff
JB		 4757 /* no further action needed, so return now */
4758 return;
4759 } else {
4760 dev_info(&pf->pdev->dev,
4761 "bad reset request 0x%08x\n", reset_flags);
4762 return;
4763 }
4764}
4765
4e3b35b0
NP		 4766#ifdef CONFIG_I40E_DCB
4767/**
4768 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4769 * @pf: board private structure
4770 * @old_cfg: current DCB config
4771 * @new_cfg: new DCB config
4772 **/
4773bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4774 struct i40e_dcbx_config *old_cfg,
4775 struct i40e_dcbx_config *new_cfg)
4776{
4777 bool need_reconfig = false;
4778
4779 /* Check if ETS configuration has changed */
4780 if (memcmp(&new_cfg->etscfg,
4781 &old_cfg->etscfg,
4782 sizeof(new_cfg->etscfg))) {
4783 /* If Priority Table has changed reconfig is needed */
4784 if (memcmp(&new_cfg->etscfg.prioritytable,
4785 &old_cfg->etscfg.prioritytable,
4786 sizeof(new_cfg->etscfg.prioritytable))) {
4787 need_reconfig = true;
69bfb110 4788 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4789 }
4790
4791 if (memcmp(&new_cfg->etscfg.tcbwtable,
4792 &old_cfg->etscfg.tcbwtable,
4793 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4794 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4795
4796 if (memcmp(&new_cfg->etscfg.tsatable,
4797 &old_cfg->etscfg.tsatable,
4798 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4799 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4800 }
4801
4802 /* Check if PFC configuration has changed */
4803 if (memcmp(&new_cfg->pfc,
4804 &old_cfg->pfc,
4805 sizeof(new_cfg->pfc))) {
4806 need_reconfig = true;
69bfb110 4807 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4808 }
4809
4810 /* Check if APP Table has changed */
4811 if (memcmp(&new_cfg->app,
4812 &old_cfg->app,
3d9667a9 4813 sizeof(new_cfg->app))) {
4e3b35b0 4814 need_reconfig = true;
69bfb110 4815 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4816 }
4e3b35b0
NP		 4817
4818 return need_reconfig;
4819}
4820
4821/**
4822 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4823 * @pf: board private structure
4824 * @e: event info posted on ARQ
4825 **/
4826static int i40e_handle_lldp_event(struct i40e_pf *pf,
4827 struct i40e_arq_event_info *e)
4828{
4829 struct i40e_aqc_lldp_get_mib *mib =
4830 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4831 struct i40e_hw *hw = &pf->hw;
4832 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4833 struct i40e_dcbx_config tmp_dcbx_cfg;
4834 bool need_reconfig = false;
4835 int ret = 0;
4836 u8 type;
4837
4d9b6043
NP		 4838 /* Not DCB capable or capability disabled */
4839 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
4840 return ret;
4841
4e3b35b0
NP		 4842 /* Ignore if event is not for Nearest Bridge */
4843 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4844 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4845 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4846 return ret;
4847
4848 /* Check MIB Type and return if event for Remote MIB update */
4849 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4850 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4851 /* Update the remote cached instance and return */
4852 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4853 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4854 &hw->remote_dcbx_config);
4855 goto exit;
4856 }
4857
4858 /* Convert/store the DCBX data from LLDPDU temporarily */
4859 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4860 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4861 if (ret) {
4862 /* Error in LLDPDU parsing return */
4863 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4864 goto exit;
4865 }
4866
4867 /* No change detected in DCBX configs */
4868 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4869 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4870 goto exit;
4871 }
4872
4873 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4874
4875 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4876
4877 /* Overwrite the new configuration */
4878 *dcbx_cfg = tmp_dcbx_cfg;
4879
4880 if (!need_reconfig)
4881 goto exit;
4882
4d9b6043
NP		 4883 /* Enable DCB tagging only when more than one TC */
4884 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
4885 pf->flags |= I40E_FLAG_DCB_ENABLED;
4886 else
4887 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
4888
4e3b35b0
NP		 4889 /* Reconfiguration needed quiesce all VSIs */
4890 i40e_pf_quiesce_all_vsi(pf);
4891
4892 /* Changes in configuration update VEB/VSI */
4893 i40e_dcb_reconfigure(pf);
4894
4895 i40e_pf_unquiesce_all_vsi(pf);
4896exit:
4897 return ret;
4898}
4899#endif /* CONFIG_I40E_DCB */
4900
23326186
ASJ		 4901/**
4902 * i40e_do_reset_safe - Protected reset path for userland calls.
4903 * @pf: board private structure
4904 * @reset_flags: which reset is requested
4905 *
4906 **/
4907void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4908{
4909 rtnl_lock();
4910 i40e_do_reset(pf, reset_flags);
4911 rtnl_unlock();
4912}
4913
41c445ff
JB		 4914/**
4915 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4916 * @pf: board private structure
4917 * @e: event info posted on ARQ
4918 *
4919 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4920 * and VF queues
4921 **/
4922static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4923 struct i40e_arq_event_info *e)
4924{
4925 struct i40e_aqc_lan_overflow *data =
4926 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4927 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4928 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4929 struct i40e_hw *hw = &pf->hw;
4930 struct i40e_vf *vf;
4931 u16 vf_id;
4932
69bfb110
JB		 4933 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4934 queue, qtx_ctl);
41c445ff
JB		 4935
4936 /* Queue belongs to VF, find the VF and issue VF reset */
4937 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4938 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4939 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4940 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4941 vf_id -= hw->func_caps.vf_base_id;
4942 vf = &pf->vf[vf_id];
4943 i40e_vc_notify_vf_reset(vf);
4944 /* Allow VF to process pending reset notification */
4945 msleep(20);
4946 i40e_reset_vf(vf, false);
4947 }
4948}
4949
4950/**
4951 * i40e_service_event_complete - Finish up the service event
4952 * @pf: board private structure
4953 **/
4954static void i40e_service_event_complete(struct i40e_pf *pf)
4955{
4956 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4957
4958 /* flush memory to make sure state is correct before next watchog */
4e857c58 4959 smp_mb__before_atomic();
41c445ff
JB		 4960 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4961}
4962
55a5e60b 4963/**
12957388
ASJ		 4964 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
4965 * @pf: board private structure
4966 **/
4967int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
4968{
4969 int val, fcnt_prog;
4970
4971 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4972 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
4973 return fcnt_prog;
4974}
4975
4976/**
4977 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 4978 * @pf: board private structure
4979 **/
4980int i40e_get_current_fd_count(struct i40e_pf *pf)
4981{
4982 int val, fcnt_prog;
4983 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4984 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4985 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4986 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4987 return fcnt_prog;
4988}
55a5e60b
ASJ		 4989/**
4990 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4991 * @pf: board private structure
4992 **/
4993void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4994{
4995 u32 fcnt_prog, fcnt_avail;
4996
4997 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4998 * to re-enable
4999 */
5000 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5001 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
5002 return;
12957388
ASJ		 5003 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5004 fcnt_avail = pf->fdir_pf_filter_count;
55a5e60b
ASJ		 5005 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
5006 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5007 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5008 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5009 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5010 }
5011 }
5012 /* Wait for some more space to be available to turn on ATR */
5013 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5014 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5015 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5016 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5017 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5018 }
5019 }
5020}
5021
41c445ff
JB		 5022/**
5023 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5024 * @pf: board private structure
5025 **/
5026static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5027{
5028 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
5029 return;
5030
41c445ff
JB		 5031 /* if interface is down do nothing */
5032 if (test_bit(__I40E_DOWN, &pf->state))
5033 return;
55a5e60b
ASJ		 5034 i40e_fdir_check_and_reenable(pf);
5035
5036 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5037 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
5038 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 5039}
5040
5041/**
5042 * i40e_vsi_link_event - notify VSI of a link event
5043 * @vsi: vsi to be notified
5044 * @link_up: link up or down
5045 **/
5046static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5047{
5048 if (!vsi)
5049 return;
5050
5051 switch (vsi->type) {
5052 case I40E_VSI_MAIN:
5053 if (!vsi->netdev || !vsi->netdev_registered)
5054 break;
5055
5056 if (link_up) {
5057 netif_carrier_on(vsi->netdev);
5058 netif_tx_wake_all_queues(vsi->netdev);
5059 } else {
5060 netif_carrier_off(vsi->netdev);
5061 netif_tx_stop_all_queues(vsi->netdev);
5062 }
5063 break;
5064
5065 case I40E_VSI_SRIOV:
5066 break;
5067
5068 case I40E_VSI_VMDQ2:
5069 case I40E_VSI_CTRL:
5070 case I40E_VSI_MIRROR:
5071 default:
5072 /* there is no notification for other VSIs */
5073 break;
5074 }
5075}
5076
5077/**
5078 * i40e_veb_link_event - notify elements on the veb of a link event
5079 * @veb: veb to be notified
5080 * @link_up: link up or down
5081 **/
5082static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5083{
5084 struct i40e_pf *pf;
5085 int i;
5086
5087 if (!veb || !veb->pf)
5088 return;
5089 pf = veb->pf;
5090
5091 /* depth first... */
5092 for (i = 0; i < I40E_MAX_VEB; i++)
5093 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5094 i40e_veb_link_event(pf->veb[i], link_up);
5095
5096 /* ... now the local VSIs */
505682cd 5097 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5098 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5099 i40e_vsi_link_event(pf->vsi[i], link_up);
5100}
5101
5102/**
5103 * i40e_link_event - Update netif_carrier status
5104 * @pf: board private structure
5105 **/
5106static void i40e_link_event(struct i40e_pf *pf)
5107{
5108 bool new_link, old_link;
5109
5110 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
5111 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
5112
5113 if (new_link == old_link)
5114 return;
6d779b41 5115 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 5116 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 5117
5118 /* Notify the base of the switch tree connected to
5119 * the link. Floating VEBs are not notified.
5120 */
5121 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5122 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5123 else
5124 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
5125
5126 if (pf->vf)
5127 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5128
5129 if (pf->flags & I40E_FLAG_PTP)
5130 i40e_ptp_set_increment(pf);
41c445ff
JB		 5131}
5132
5133/**
5134 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5135 * @pf: board private structure
5136 *
5137 * Set the per-queue flags to request a check for stuck queues in the irq
5138 * clean functions, then force interrupts to be sure the irq clean is called.
5139 **/
5140static void i40e_check_hang_subtask(struct i40e_pf *pf)
5141{
5142 int i, v;
5143
5144 /* If we're down or resetting, just bail */
5145 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5146 return;
5147
5148 /* for each VSI/netdev
5149 * for each Tx queue
5150 * set the check flag
5151 * for each q_vector
5152 * force an interrupt
5153 */
505682cd 5154 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5155 struct i40e_vsi *vsi = pf->vsi[v];
5156 int armed = 0;
5157
5158 if (!pf->vsi[v] ||
5159 test_bit(__I40E_DOWN, &vsi->state) ||
5160 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5161 continue;
5162
5163 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5164 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5165 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5166 &vsi->tx_rings[i]->state))
41c445ff
JB		 5167 armed++;
5168 }
5169
5170 if (armed) {
5171 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5172 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5173 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5174 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5175 } else {
5176 u16 vec = vsi->base_vector - 1;
5177 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5178 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5179 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5180 wr32(&vsi->back->hw,
5181 I40E_PFINT_DYN_CTLN(vec), val);
5182 }
5183 i40e_flush(&vsi->back->hw);
5184 }
5185 }
5186}
5187
5188/**
5189 * i40e_watchdog_subtask - Check and bring link up
5190 * @pf: board private structure
5191 **/
5192static void i40e_watchdog_subtask(struct i40e_pf *pf)
5193{
5194 int i;
5195
5196 /* if interface is down do nothing */
5197 if (test_bit(__I40E_DOWN, &pf->state) ||
5198 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5199 return;
5200
5201 /* Update the stats for active netdevs so the network stack
5202 * can look at updated numbers whenever it cares to
5203 */
505682cd 5204 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5205 if (pf->vsi[i] && pf->vsi[i]->netdev)
5206 i40e_update_stats(pf->vsi[i]);
5207
5208 /* Update the stats for the active switching components */
5209 for (i = 0; i < I40E_MAX_VEB; i++)
5210 if (pf->veb[i])
5211 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5212
5213 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5214}
5215
5216/**
5217 * i40e_reset_subtask - Set up for resetting the device and driver
5218 * @pf: board private structure
5219 **/
5220static void i40e_reset_subtask(struct i40e_pf *pf)
5221{
5222 u32 reset_flags = 0;
5223
23326186 5224 rtnl_lock();
41c445ff
JB		 5225 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5226 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5227 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5228 }
5229 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5230 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5231 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5232 }
5233 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5234 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5235 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5236 }
5237 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5238 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5239 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5240 }
b5d06f05
NP		 5241 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5242 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5243 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5244 }
41c445ff
JB		 5245
5246 /* If there's a recovery already waiting, it takes
5247 * precedence before starting a new reset sequence.
5248 */
5249 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5250 i40e_handle_reset_warning(pf);
23326186 5251 goto unlock;
41c445ff
JB		 5252 }
5253
5254 /* If we're already down or resetting, just bail */
5255 if (reset_flags &&
5256 !test_bit(__I40E_DOWN, &pf->state) &&
5257 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5258 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5259
5260unlock:
5261 rtnl_unlock();
41c445ff
JB		 5262}
5263
5264/**
5265 * i40e_handle_link_event - Handle link event
5266 * @pf: board private structure
5267 * @e: event info posted on ARQ
5268 **/
5269static void i40e_handle_link_event(struct i40e_pf *pf,
5270 struct i40e_arq_event_info *e)
5271{
5272 struct i40e_hw *hw = &pf->hw;
5273 struct i40e_aqc_get_link_status *status =
5274 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5275 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5276
5277 /* save off old link status information */
5278 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5279 sizeof(pf->hw.phy.link_info_old));
5280
5281 /* update link status */
5282 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5283 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5284 hw_link_info->link_info = status->link_info;
5285 hw_link_info->an_info = status->an_info;
5286 hw_link_info->ext_info = status->ext_info;
5287 hw_link_info->lse_enable =
5288 le16_to_cpu(status->command_flags) &
5289 I40E_AQ_LSE_ENABLE;
5290
5291 /* process the event */
5292 i40e_link_event(pf);
5293
5294 /* Do a new status request to re-enable LSE reporting
5295 * and load new status information into the hw struct,
5296 * then see if the status changed while processing the
5297 * initial event.
5298 */
8109e123 5299 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 5300 i40e_link_event(pf);
5301}
5302
5303/**
5304 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5305 * @pf: board private structure
5306 **/
5307static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5308{
5309 struct i40e_arq_event_info event;
5310 struct i40e_hw *hw = &pf->hw;
5311 u16 pending, i = 0;
5312 i40e_status ret;
5313 u16 opcode;
86df242b 5314 u32 oldval;
41c445ff
JB		 5315 u32 val;
5316
86df242b
SN		 5317 /* check for error indications */
5318 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5319 oldval = val;
5320 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5321 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5322 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5323 }
5324 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5325 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5326 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5327 }
5328 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5329 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5330 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5331 }
5332 if (oldval != val)
5333 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5334
5335 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5336 oldval = val;
5337 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5338 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5339 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5340 }
5341 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5342 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5343 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5344 }
5345 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5346 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5347 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5348 }
5349 if (oldval != val)
5350 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5351
3197ce22 5352 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5353 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5354 if (!event.msg_buf)
5355 return;
5356
5357 do {
2f019123 5358 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff 5359 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5360 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5361 break;
56497978 5362 else if (ret) {
41c445ff
JB		 5363 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5364 break;
5365 }
5366
5367 opcode = le16_to_cpu(event.desc.opcode);
5368 switch (opcode) {
5369
5370 case i40e_aqc_opc_get_link_status:
5371 i40e_handle_link_event(pf, &event);
5372 break;
5373 case i40e_aqc_opc_send_msg_to_pf:
5374 ret = i40e_vc_process_vf_msg(pf,
5375 le16_to_cpu(event.desc.retval),
5376 le32_to_cpu(event.desc.cookie_high),
5377 le32_to_cpu(event.desc.cookie_low),
5378 event.msg_buf,
5379 event.msg_size);
5380 break;
5381 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5382 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5383#ifdef CONFIG_I40E_DCB
5384 rtnl_lock();
5385 ret = i40e_handle_lldp_event(pf, &event);
5386 rtnl_unlock();
5387#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5388 break;
5389 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5390 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5391 i40e_handle_lan_overflow_event(pf, &event);
5392 break;
0467bc91
SN		 5393 case i40e_aqc_opc_send_msg_to_peer:
5394 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5395 break;
41c445ff
JB		 5396 default:
5397 dev_info(&pf->pdev->dev,
0467bc91
SN		 5398 "ARQ Error: Unknown event 0x%04x received\n",
5399 opcode);
41c445ff
JB		 5400 break;
5401 }
5402 } while (pending && (i++ < pf->adminq_work_limit));
5403
5404 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5405 /* re-enable Admin queue interrupt cause */
5406 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5407 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5408 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5409 i40e_flush(hw);
5410
5411 kfree(event.msg_buf);
5412}
5413
4eb3f768
SN		 5414/**
5415 * i40e_verify_eeprom - make sure eeprom is good to use
5416 * @pf: board private structure
5417 **/
5418static void i40e_verify_eeprom(struct i40e_pf *pf)
5419{
5420 int err;
5421
5422 err = i40e_diag_eeprom_test(&pf->hw);
5423 if (err) {
5424 /* retry in case of garbage read */
5425 err = i40e_diag_eeprom_test(&pf->hw);
5426 if (err) {
5427 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5428 err);
5429 set_bit(__I40E_BAD_EEPROM, &pf->state);
5430 }
5431 }
5432
5433 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5434 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5435 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5436 }
5437}
5438
41c445ff
JB		 5439/**
5440 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5441 * @veb: pointer to the VEB instance
5442 *
5443 * This is a recursive function that first builds the attached VSIs then
5444 * recurses in to build the next layer of VEB. We track the connections
5445 * through our own index numbers because the seid's from the HW could
5446 * change across the reset.
5447 **/
5448static int i40e_reconstitute_veb(struct i40e_veb *veb)
5449{
5450 struct i40e_vsi *ctl_vsi = NULL;
5451 struct i40e_pf *pf = veb->pf;
5452 int v, veb_idx;
5453 int ret;
5454
5455 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5456 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5457 if (pf->vsi[v] &&
5458 pf->vsi[v]->veb_idx == veb->idx &&
5459 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5460 ctl_vsi = pf->vsi[v];
5461 break;
5462 }
5463 }
5464 if (!ctl_vsi) {
5465 dev_info(&pf->pdev->dev,
5466 "missing owner VSI for veb_idx %d\n", veb->idx);
5467 ret = -ENOENT;
5468 goto end_reconstitute;
5469 }
5470 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5471 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5472 ret = i40e_add_vsi(ctl_vsi);
5473 if (ret) {
5474 dev_info(&pf->pdev->dev,
5475 "rebuild of owner VSI failed: %d\n", ret);
5476 goto end_reconstitute;
5477 }
5478 i40e_vsi_reset_stats(ctl_vsi);
5479
5480 /* create the VEB in the switch and move the VSI onto the VEB */
5481 ret = i40e_add_veb(veb, ctl_vsi);
5482 if (ret)
5483 goto end_reconstitute;
5484
5485 /* create the remaining VSIs attached to this VEB */
505682cd 5486 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5487 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5488 continue;
5489
5490 if (pf->vsi[v]->veb_idx == veb->idx) {
5491 struct i40e_vsi *vsi = pf->vsi[v];
5492 vsi->uplink_seid = veb->seid;
5493 ret = i40e_add_vsi(vsi);
5494 if (ret) {
5495 dev_info(&pf->pdev->dev,
5496 "rebuild of vsi_idx %d failed: %d\n",
5497 v, ret);
5498 goto end_reconstitute;
5499 }
5500 i40e_vsi_reset_stats(vsi);
5501 }
5502 }
5503
5504 /* create any VEBs attached to this VEB - RECURSION */
5505 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5506 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5507 pf->veb[veb_idx]->uplink_seid = veb->seid;
5508 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5509 if (ret)
5510 break;
5511 }
5512 }
5513
5514end_reconstitute:
5515 return ret;
5516}
5517
5518/**
5519 * i40e_get_capabilities - get info about the HW
5520 * @pf: the PF struct
5521 **/
5522static int i40e_get_capabilities(struct i40e_pf *pf)
5523{
5524 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5525 u16 data_size;
5526 int buf_len;
5527 int err;
5528
5529 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5530 do {
5531 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5532 if (!cap_buf)
5533 return -ENOMEM;
5534
5535 /* this loads the data into the hw struct for us */
5536 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5537 &data_size,
5538 i40e_aqc_opc_list_func_capabilities,
5539 NULL);
5540 /* data loaded, buffer no longer needed */
5541 kfree(cap_buf);
5542
5543 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5544 /* retry with a larger buffer */
5545 buf_len = data_size;
5546 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5547 dev_info(&pf->pdev->dev,
5548 "capability discovery failed: aq=%d\n",
5549 pf->hw.aq.asq_last_status);
5550 return -ENODEV;
5551 }
5552 } while (err);
5553
ac71b7ba
ASJ		 5554 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5555 (pf->hw.aq.fw_maj_ver < 2)) {
5556 pf->hw.func_caps.num_msix_vectors++;
5557 pf->hw.func_caps.num_msix_vectors_vf++;
5558 }
5559
41c445ff
JB		 5560 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5561 dev_info(&pf->pdev->dev,
5562 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5563 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5564 pf->hw.func_caps.num_msix_vectors,
5565 pf->hw.func_caps.num_msix_vectors_vf,
5566 pf->hw.func_caps.fd_filters_guaranteed,
5567 pf->hw.func_caps.fd_filters_best_effort,
5568 pf->hw.func_caps.num_tx_qp,
5569 pf->hw.func_caps.num_vsis);
5570
7134f9ce
JB		 5571#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5572 + pf->hw.func_caps.num_vfs)
5573 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5574 dev_info(&pf->pdev->dev,
5575 "got num_vsis %d, setting num_vsis to %d\n",
5576 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5577 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5578 }
5579
41c445ff
JB		 5580 return 0;
5581}
5582
cbf61325
ASJ		 5583static int i40e_vsi_clear(struct i40e_vsi *vsi);
5584
41c445ff 5585/**
cbf61325 5586 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5587 * @pf: board private structure
5588 **/
cbf61325 5589static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5590{
5591 struct i40e_vsi *vsi;
8a9eb7d3 5592 int i;
41c445ff 5593
407e063c
JB		 5594 /* quick workaround for an NVM issue that leaves a critical register
5595 * uninitialized
5596 */
5597 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5598 static const u32 hkey[] = {
5599 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5600 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5601 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5602 0x95b3a76d};
5603
5604 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5605 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5606 }
5607
cbf61325 5608 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5609 return;
5610
cbf61325 5611 /* find existing VSI and see if it needs configuring */
41c445ff 5612 vsi = NULL;
505682cd 5613 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5614 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5615 vsi = pf->vsi[i];
cbf61325
ASJ		 5616 break;
5617 }
5618 }
5619
5620 /* create a new VSI if none exists */
41c445ff 5621 if (!vsi) {
cbf61325
ASJ		 5622 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5623 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5624 if (!vsi) {
5625 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5626 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5627 return;
41c445ff 5628 }
cbf61325 5629 }
41c445ff 5630
8a9eb7d3 5631 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5632}
5633
5634/**
5635 * i40e_fdir_teardown - release the Flow Director resources
5636 * @pf: board private structure
5637 **/
5638static void i40e_fdir_teardown(struct i40e_pf *pf)
5639{
5640 int i;
5641
17a73f6b 5642 i40e_fdir_filter_exit(pf);
505682cd 5643 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5644 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5645 i40e_vsi_release(pf->vsi[i]);
5646 break;
5647 }
5648 }
5649}
5650
5651/**
f650a38b 5652 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5653 * @pf: board private structure
5654 *
f650a38b
ASJ		 5655 * Close up the VFs and other things in prep for pf Reset.
5656 **/
23cfbe07 5657static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5658{
41c445ff 5659 struct i40e_hw *hw = &pf->hw;
60442dea 5660 i40e_status ret = 0;
41c445ff
JB		 5661 u32 v;
5662
5663 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5664 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 5665 return;
41c445ff 5666
69bfb110 5667 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5668
41c445ff
JB		 5669 /* quiesce the VSIs and their queues that are not already DOWN */
5670 i40e_pf_quiesce_all_vsi(pf);
5671
505682cd 5672 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5673 if (pf->vsi[v])
5674 pf->vsi[v]->seid = 0;
5675 }
5676
5677 i40e_shutdown_adminq(&pf->hw);
5678
f650a38b 5679 /* call shutdown HMC */
60442dea
SN		 5680 if (hw->hmc.hmc_obj) {
5681 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 5682 if (ret)
60442dea
SN		 5683 dev_warn(&pf->pdev->dev,
5684 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 5685 }
f650a38b
ASJ		 5686}
5687
44033fac
JB		 5688/**
5689 * i40e_send_version - update firmware with driver version
5690 * @pf: PF struct
5691 */
5692static void i40e_send_version(struct i40e_pf *pf)
5693{
5694 struct i40e_driver_version dv;
5695
5696 dv.major_version = DRV_VERSION_MAJOR;
5697 dv.minor_version = DRV_VERSION_MINOR;
5698 dv.build_version = DRV_VERSION_BUILD;
5699 dv.subbuild_version = 0;
5700 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
5701 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5702}
5703
f650a38b 5704/**
4dda12e6 5705 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5706 * @pf: board private structure
bc7d338f 5707 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5708 **/
bc7d338f 5709static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5710{
f650a38b
ASJ		 5711 struct i40e_hw *hw = &pf->hw;
5712 i40e_status ret;
5713 u32 v;
5714
41c445ff
JB		 5715 /* Now we wait for GRST to settle out.
5716 * We don't have to delete the VEBs or VSIs from the hw switch
5717 * because the reset will make them disappear.
5718 */
5719 ret = i40e_pf_reset(hw);
b5565400 5720 if (ret) {
41c445ff 5721 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5722 goto end_core_reset;
5723 }
41c445ff
JB		 5724 pf->pfr_count++;
5725
5726 if (test_bit(__I40E_DOWN, &pf->state))
5727 goto end_core_reset;
69bfb110 5728 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5729
5730 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5731 ret = i40e_init_adminq(&pf->hw);
5732 if (ret) {
5733 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5734 goto end_core_reset;
5735 }
5736
4eb3f768
SN		 5737 /* re-verify the eeprom if we just had an EMP reset */
5738 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5739 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5740 i40e_verify_eeprom(pf);
5741 }
5742
e78ac4bf 5743 i40e_clear_pxe_mode(hw);
41c445ff
JB		 5744 ret = i40e_get_capabilities(pf);
5745 if (ret) {
5746 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5747 ret);
5748 goto end_core_reset;
5749 }
5750
41c445ff
JB		 5751 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5752 hw->func_caps.num_rx_qp,
5753 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5754 if (ret) {
5755 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5756 goto end_core_reset;
5757 }
5758 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5759 if (ret) {
5760 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5761 goto end_core_reset;
5762 }
5763
4e3b35b0
NP		 5764#ifdef CONFIG_I40E_DCB
5765 ret = i40e_init_pf_dcb(pf);
5766 if (ret) {
5767 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5768 goto end_core_reset;
5769 }
5770#endif /* CONFIG_I40E_DCB */
5771
41c445ff 5772 /* do basic switch setup */
bc7d338f 5773 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5774 if (ret)
5775 goto end_core_reset;
5776
5777 /* Rebuild the VSIs and VEBs that existed before reset.
5778 * They are still in our local switch element arrays, so only
5779 * need to rebuild the switch model in the HW.
5780 *
5781 * If there were VEBs but the reconstitution failed, we'll try
5782 * try to recover minimal use by getting the basic PF VSI working.
5783 */
5784 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5785 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5786 /* find the one VEB connected to the MAC, and find orphans */
5787 for (v = 0; v < I40E_MAX_VEB; v++) {
5788 if (!pf->veb[v])
5789 continue;
5790
5791 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5792 pf->veb[v]->uplink_seid == 0) {
5793 ret = i40e_reconstitute_veb(pf->veb[v]);
5794
5795 if (!ret)
5796 continue;
5797
5798 /* If Main VEB failed, we're in deep doodoo,
5799 * so give up rebuilding the switch and set up
5800 * for minimal rebuild of PF VSI.
5801 * If orphan failed, we'll report the error
5802 * but try to keep going.
5803 */
5804 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5805 dev_info(&pf->pdev->dev,
5806 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5807 ret);
5808 pf->vsi[pf->lan_vsi]->uplink_seid
5809 = pf->mac_seid;
5810 break;
5811 } else if (pf->veb[v]->uplink_seid == 0) {
5812 dev_info(&pf->pdev->dev,
5813 "rebuild of orphan VEB failed: %d\n",
5814 ret);
5815 }
5816 }
5817 }
5818 }
5819
5820 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 5821 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 5822 /* no VEB, so rebuild only the Main VSI */
5823 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5824 if (ret) {
5825 dev_info(&pf->pdev->dev,
5826 "rebuild of Main VSI failed: %d\n", ret);
5827 goto end_core_reset;
5828 }
5829 }
5830
5831 /* reinit the misc interrupt */
5832 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5833 ret = i40e_setup_misc_vector(pf);
5834
5835 /* restart the VSIs that were rebuilt and running before the reset */
5836 i40e_pf_unquiesce_all_vsi(pf);
5837
69f64b2b
MW		 5838 if (pf->num_alloc_vfs) {
5839 for (v = 0; v < pf->num_alloc_vfs; v++)
5840 i40e_reset_vf(&pf->vf[v], true);
5841 }
5842
41c445ff 5843 /* tell the firmware that we're starting */
44033fac 5844 i40e_send_version(pf);
41c445ff
JB		 5845
5846end_core_reset:
5847 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5848}
5849
f650a38b
ASJ		 5850/**
5851 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5852 * @pf: board private structure
5853 *
5854 * Close up the VFs and other things in prep for a Core Reset,
5855 * then get ready to rebuild the world.
5856 **/
5857static void i40e_handle_reset_warning(struct i40e_pf *pf)
5858{
23cfbe07
SN		 5859 i40e_prep_for_reset(pf);
5860 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5861}
5862
41c445ff
JB		 5863/**
5864 * i40e_handle_mdd_event
5865 * @pf: pointer to the pf structure
5866 *
5867 * Called from the MDD irq handler to identify possibly malicious vfs
5868 **/
5869static void i40e_handle_mdd_event(struct i40e_pf *pf)
5870{
5871 struct i40e_hw *hw = &pf->hw;
5872 bool mdd_detected = false;
df430b12 5873 bool pf_mdd_detected = false;
41c445ff
JB		 5874 struct i40e_vf *vf;
5875 u32 reg;
5876 int i;
5877
5878 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5879 return;
5880
5881 /* find what triggered the MDD event */
5882 reg = rd32(hw, I40E_GL_MDET_TX);
5883 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 5884 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
5885 I40E_GL_MDET_TX_PF_NUM_SHIFT;
5886 u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
5887 I40E_GL_MDET_TX_VF_NUM_SHIFT;
5888 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) >>
5889 I40E_GL_MDET_TX_EVENT_SHIFT;
5890 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
5891 I40E_GL_MDET_TX_QUEUE_SHIFT;
41c445ff 5892 dev_info(&pf->pdev->dev,
4c33f83a
ASJ		 5893 "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
5894 event, queue, pf_num, vf_num);
41c445ff
JB		 5895 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5896 mdd_detected = true;
5897 }
5898 reg = rd32(hw, I40E_GL_MDET_RX);
5899 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 5900 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
5901 I40E_GL_MDET_RX_FUNCTION_SHIFT;
5902 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) >>
5903 I40E_GL_MDET_RX_EVENT_SHIFT;
5904 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
5905 I40E_GL_MDET_RX_QUEUE_SHIFT;
41c445ff 5906 dev_info(&pf->pdev->dev,
f29eaa3d 5907 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5908 event, queue, func);
5909 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5910 mdd_detected = true;
5911 }
5912
df430b12
NP		 5913 if (mdd_detected) {
5914 reg = rd32(hw, I40E_PF_MDET_TX);
5915 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
5916 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
5917 dev_info(&pf->pdev->dev,
5918 "MDD TX event is for this function 0x%08x, requesting PF reset.\n",
5919 reg);
5920 pf_mdd_detected = true;
5921 }
5922 reg = rd32(hw, I40E_PF_MDET_RX);
5923 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
5924 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
5925 dev_info(&pf->pdev->dev,
5926 "MDD RX event is for this function 0x%08x, requesting PF reset.\n",
5927 reg);
5928 pf_mdd_detected = true;
5929 }
5930 /* Queue belongs to the PF, initiate a reset */
5931 if (pf_mdd_detected) {
5932 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5933 i40e_service_event_schedule(pf);
5934 }
5935 }
5936
41c445ff
JB		 5937 /* see if one of the VFs needs its hand slapped */
5938 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5939 vf = &(pf->vf[i]);
5940 reg = rd32(hw, I40E_VP_MDET_TX(i));
5941 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5942 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5943 vf->num_mdd_events++;
5944 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5945 }
5946
5947 reg = rd32(hw, I40E_VP_MDET_RX(i));
5948 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5949 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5950 vf->num_mdd_events++;
5951 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5952 }
5953
5954 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5955 dev_info(&pf->pdev->dev,
5956 "Too many MDD events on VF %d, disabled\n", i);
5957 dev_info(&pf->pdev->dev,
5958 "Use PF Control I/F to re-enable the VF\n");
5959 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5960 }
5961 }
5962
5963 /* re-enable mdd interrupt cause */
5964 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5965 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5966 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5967 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5968 i40e_flush(hw);
5969}
5970
a1c9a9d9
JK		 5971#ifdef CONFIG_I40E_VXLAN
5972/**
5973 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5974 * @pf: board private structure
5975 **/
5976static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5977{
a1c9a9d9
JK		 5978 struct i40e_hw *hw = &pf->hw;
5979 i40e_status ret;
5980 u8 filter_index;
5981 __be16 port;
5982 int i;
5983
5984 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5985 return;
5986
5987 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5988
5989 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5990 if (pf->pending_vxlan_bitmap & (1 << i)) {
5991 pf->pending_vxlan_bitmap &= ~(1 << i);
5992 port = pf->vxlan_ports[i];
5993 ret = port ?
5994 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5995 I40E_AQC_TUNNEL_TYPE_VXLAN,
5996 &filter_index, NULL)
5997 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5998
5999 if (ret) {
6000 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6001 port ? "adding" : "deleting",
6002 ntohs(port), port ? i : i);
6003
6004 pf->vxlan_ports[i] = 0;
6005 } else {
6006 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6007 port ? "Added" : "Deleted",
6008 ntohs(port), port ? i : filter_index);
6009 }
6010 }
6011 }
6012}
6013
6014#endif
41c445ff
JB		 6015/**
6016 * i40e_service_task - Run the driver's async subtasks
6017 * @work: pointer to work_struct containing our data
6018 **/
6019static void i40e_service_task(struct work_struct *work)
6020{
6021 struct i40e_pf *pf = container_of(work,
6022 struct i40e_pf,
6023 service_task);
6024 unsigned long start_time = jiffies;
6025
e57a2fea
SN		 6026 /* don't bother with service tasks if a reset is in progress */
6027 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6028 i40e_service_event_complete(pf);
6029 return;
6030 }
6031
41c445ff
JB		 6032 i40e_reset_subtask(pf);
6033 i40e_handle_mdd_event(pf);
6034 i40e_vc_process_vflr_event(pf);
6035 i40e_watchdog_subtask(pf);
6036 i40e_fdir_reinit_subtask(pf);
6037 i40e_check_hang_subtask(pf);
6038 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6039#ifdef CONFIG_I40E_VXLAN
6040 i40e_sync_vxlan_filters_subtask(pf);
6041#endif
41c445ff
JB		 6042 i40e_clean_adminq_subtask(pf);
6043
6044 i40e_service_event_complete(pf);
6045
6046 /* If the tasks have taken longer than one timer cycle or there
6047 * is more work to be done, reschedule the service task now
6048 * rather than wait for the timer to tick again.
6049 */
6050 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6051 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6052 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6053 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6054 i40e_service_event_schedule(pf);
6055}
6056
6057/**
6058 * i40e_service_timer - timer callback
6059 * @data: pointer to PF struct
6060 **/
6061static void i40e_service_timer(unsigned long data)
6062{
6063 struct i40e_pf *pf = (struct i40e_pf *)data;
6064
6065 mod_timer(&pf->service_timer,
6066 round_jiffies(jiffies + pf->service_timer_period));
6067 i40e_service_event_schedule(pf);
6068}
6069
6070/**
6071 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6072 * @vsi: the VSI being configured
6073 **/
6074static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6075{
6076 struct i40e_pf *pf = vsi->back;
6077
6078 switch (vsi->type) {
6079 case I40E_VSI_MAIN:
6080 vsi->alloc_queue_pairs = pf->num_lan_qps;
6081 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6082 I40E_REQ_DESCRIPTOR_MULTIPLE);
6083 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6084 vsi->num_q_vectors = pf->num_lan_msix;
6085 else
6086 vsi->num_q_vectors = 1;
6087
6088 break;
6089
6090 case I40E_VSI_FDIR:
6091 vsi->alloc_queue_pairs = 1;
6092 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6093 I40E_REQ_DESCRIPTOR_MULTIPLE);
6094 vsi->num_q_vectors = 1;
6095 break;
6096
6097 case I40E_VSI_VMDQ2:
6098 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6099 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6100 I40E_REQ_DESCRIPTOR_MULTIPLE);
6101 vsi->num_q_vectors = pf->num_vmdq_msix;
6102 break;
6103
6104 case I40E_VSI_SRIOV:
6105 vsi->alloc_queue_pairs = pf->num_vf_qps;
6106 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6107 I40E_REQ_DESCRIPTOR_MULTIPLE);
6108 break;
6109
6110 default:
6111 WARN_ON(1);
6112 return -ENODATA;
6113 }
6114
6115 return 0;
6116}
6117
f650a38b
ASJ		 6118/**
6119 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6120 * @type: VSI pointer
bc7d338f 6121 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6122 *
6123 * On error: returns error code (negative)
6124 * On success: returns 0
6125 **/
bc7d338f 6126static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6127{
6128 int size;
6129 int ret = 0;
6130
ac6c5e3d 6131 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6132 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6133 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6134 if (!vsi->tx_rings)
6135 return -ENOMEM;
f650a38b
ASJ		 6136 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6137
bc7d338f
ASJ		 6138 if (alloc_qvectors) {
6139 /* allocate memory for q_vector pointers */
6140 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
6141 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6142 if (!vsi->q_vectors) {
6143 ret = -ENOMEM;
6144 goto err_vectors;
6145 }
f650a38b
ASJ		 6146 }
6147 return ret;
6148
6149err_vectors:
6150 kfree(vsi->tx_rings);
6151 return ret;
6152}
6153
41c445ff
JB		 6154/**
6155 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6156 * @pf: board private structure
6157 * @type: type of VSI
6158 *
6159 * On error: returns error code (negative)
6160 * On success: returns vsi index in PF (positive)
6161 **/
6162static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6163{
6164 int ret = -ENODEV;
6165 struct i40e_vsi *vsi;
6166 int vsi_idx;
6167 int i;
6168
6169 /* Need to protect the allocation of the VSIs at the PF level */
6170 mutex_lock(&pf->switch_mutex);
6171
6172 /* VSI list may be fragmented if VSI creation/destruction has
6173 * been happening. We can afford to do a quick scan to look
6174 * for any free VSIs in the list.
6175 *
6176 * find next empty vsi slot, looping back around if necessary
6177 */
6178 i = pf->next_vsi;
505682cd 6179 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6180 i++;
505682cd 6181 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6182 i = 0;
6183 while (i < pf->next_vsi && pf->vsi[i])
6184 i++;
6185 }
6186
505682cd 6187 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6188 vsi_idx = i; /* Found one! */
6189 } else {
6190 ret = -ENODEV;
493fb300 6191 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6192 }
6193 pf->next_vsi = ++i;
6194
6195 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6196 if (!vsi) {
6197 ret = -ENOMEM;
493fb300 6198 goto unlock_pf;
41c445ff
JB		 6199 }
6200 vsi->type = type;
6201 vsi->back = pf;
6202 set_bit(__I40E_DOWN, &vsi->state);
6203 vsi->flags = 0;
6204 vsi->idx = vsi_idx;
6205 vsi->rx_itr_setting = pf->rx_itr_default;
6206 vsi->tx_itr_setting = pf->tx_itr_default;
6207 vsi->netdev_registered = false;
6208 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6209 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6210 vsi->irqs_ready = false;
41c445ff 6211
9f65e15b
AD		 6212 ret = i40e_set_num_rings_in_vsi(vsi);
6213 if (ret)
6214 goto err_rings;
6215
bc7d338f 6216 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6217 if (ret)
9f65e15b 6218 goto err_rings;
493fb300 6219
41c445ff
JB		 6220 /* Setup default MSIX irq handler for VSI */
6221 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6222
6223 pf->vsi[vsi_idx] = vsi;
6224 ret = vsi_idx;
493fb300
AD		 6225 goto unlock_pf;
6226
9f65e15b 6227err_rings:
493fb300
AD		 6228 pf->next_vsi = i - 1;
6229 kfree(vsi);
6230unlock_pf:
41c445ff
JB		 6231 mutex_unlock(&pf->switch_mutex);
6232 return ret;
6233}
6234
f650a38b
ASJ		 6235/**
6236 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6237 * @type: VSI pointer
bc7d338f 6238 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6239 *
6240 * On error: returns error code (negative)
6241 * On success: returns 0
6242 **/
bc7d338f 6243static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6244{
6245 /* free the ring and vector containers */
bc7d338f
ASJ		 6246 if (free_qvectors) {
6247 kfree(vsi->q_vectors);
6248 vsi->q_vectors = NULL;
6249 }
f650a38b
ASJ		 6250 kfree(vsi->tx_rings);
6251 vsi->tx_rings = NULL;
6252 vsi->rx_rings = NULL;
6253}
6254
41c445ff
JB		 6255/**
6256 * i40e_vsi_clear - Deallocate the VSI provided
6257 * @vsi: the VSI being un-configured
6258 **/
6259static int i40e_vsi_clear(struct i40e_vsi *vsi)
6260{
6261 struct i40e_pf *pf;
6262
6263 if (!vsi)
6264 return 0;
6265
6266 if (!vsi->back)
6267 goto free_vsi;
6268 pf = vsi->back;
6269
6270 mutex_lock(&pf->switch_mutex);
6271 if (!pf->vsi[vsi->idx]) {
6272 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6273 vsi->idx, vsi->idx, vsi, vsi->type);
6274 goto unlock_vsi;
6275 }
6276
6277 if (pf->vsi[vsi->idx] != vsi) {
6278 dev_err(&pf->pdev->dev,
6279 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6280 pf->vsi[vsi->idx]->idx,
6281 pf->vsi[vsi->idx],
6282 pf->vsi[vsi->idx]->type,
6283 vsi->idx, vsi, vsi->type);
6284 goto unlock_vsi;
6285 }
6286
6287 /* updates the pf for this cleared vsi */
6288 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6289 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6290
bc7d338f 6291 i40e_vsi_free_arrays(vsi, true);
493fb300 6292
41c445ff
JB		 6293 pf->vsi[vsi->idx] = NULL;
6294 if (vsi->idx < pf->next_vsi)
6295 pf->next_vsi = vsi->idx;
6296
6297unlock_vsi:
6298 mutex_unlock(&pf->switch_mutex);
6299free_vsi:
6300 kfree(vsi);
6301
6302 return 0;
6303}
6304
9f65e15b
AD		 6305/**
6306 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6307 * @vsi: the VSI being cleaned
6308 **/
be1d5eea 6309static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6310{
6311 int i;
6312
8e9dca53 6313 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6314 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6315 kfree_rcu(vsi->tx_rings[i], rcu);
6316 vsi->tx_rings[i] = NULL;
6317 vsi->rx_rings[i] = NULL;
6318 }
be1d5eea 6319 }
9f65e15b
AD		 6320}
6321
41c445ff
JB		 6322/**
6323 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6324 * @vsi: the VSI being configured
6325 **/
6326static int i40e_alloc_rings(struct i40e_vsi *vsi)
6327{
e7046ee1 6328 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6329 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6330 int i;
6331
41c445ff 6332 /* Set basic values in the rings to be used later during open() */
d7397644 6333 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6334 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6335 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6336 if (!tx_ring)
6337 goto err_out;
41c445ff
JB		 6338
6339 tx_ring->queue_index = i;
6340 tx_ring->reg_idx = vsi->base_queue + i;
6341 tx_ring->ring_active = false;
6342 tx_ring->vsi = vsi;
6343 tx_ring->netdev = vsi->netdev;
6344 tx_ring->dev = &pf->pdev->dev;
6345 tx_ring->count = vsi->num_desc;
6346 tx_ring->size = 0;
6347 tx_ring->dcb_tc = 0;
9f65e15b 6348 vsi->tx_rings[i] = tx_ring;
41c445ff 6349
9f65e15b 6350 rx_ring = &tx_ring[1];
41c445ff
JB		 6351 rx_ring->queue_index = i;
6352 rx_ring->reg_idx = vsi->base_queue + i;
6353 rx_ring->ring_active = false;
6354 rx_ring->vsi = vsi;
6355 rx_ring->netdev = vsi->netdev;
6356 rx_ring->dev = &pf->pdev->dev;
6357 rx_ring->count = vsi->num_desc;
6358 rx_ring->size = 0;
6359 rx_ring->dcb_tc = 0;
6360 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6361 set_ring_16byte_desc_enabled(rx_ring);
6362 else
6363 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6364 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6365 }
6366
6367 return 0;
9f65e15b
AD		 6368
6369err_out:
6370 i40e_vsi_clear_rings(vsi);
6371 return -ENOMEM;
41c445ff
JB		 6372}
6373
6374/**
6375 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6376 * @pf: board private structure
6377 * @vectors: the number of MSI-X vectors to request
6378 *
6379 * Returns the number of vectors reserved, or error
6380 **/
6381static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6382{
7b37f376
AG		 6383 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6384 I40E_MIN_MSIX, vectors);
6385 if (vectors < 0) {
41c445ff 6386 dev_info(&pf->pdev->dev,
7b37f376 6387 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6388 vectors = 0;
6389 }
6390
6391 return vectors;
6392}
6393
6394/**
6395 * i40e_init_msix - Setup the MSIX capability
6396 * @pf: board private structure
6397 *
6398 * Work with the OS to set up the MSIX vectors needed.
6399 *
6400 * Returns 0 on success, negative on failure
6401 **/
6402static int i40e_init_msix(struct i40e_pf *pf)
6403{
6404 i40e_status err = 0;
6405 struct i40e_hw *hw = &pf->hw;
6406 int v_budget, i;
6407 int vec;
6408
6409 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6410 return -ENODEV;
6411
6412 /* The number of vectors we'll request will be comprised of:
6413 * - Add 1 for "other" cause for Admin Queue events, etc.
6414 * - The number of LAN queue pairs
f8ff1464
ASJ		 6415 * - Queues being used for RSS.
6416 * We don't need as many as max_rss_size vectors.
6417 * use rss_size instead in the calculation since that
6418 * is governed by number of cpus in the system.
6419 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6420 * - The number of VMDq pairs
6421 * Once we count this up, try the request.
6422 *
6423 * If we can't get what we want, we'll simplify to nearly nothing
6424 * and try again. If that still fails, we punt.
6425 */
f8ff1464 6426 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6427 pf->num_vmdq_msix = pf->num_vmdq_qps;
6428 v_budget = 1 + pf->num_lan_msix;
6429 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6430 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6431 v_budget++;
6432
6433 /* Scale down if necessary, and the rings will share vectors */
6434 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6435
6436 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6437 GFP_KERNEL);
6438 if (!pf->msix_entries)
6439 return -ENOMEM;
6440
6441 for (i = 0; i < v_budget; i++)
6442 pf->msix_entries[i].entry = i;
6443 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6444
6445 if (vec != v_budget) {
6446 /* If we have limited resources, we will start with no vectors
6447 * for the special features and then allocate vectors to some
6448 * of these features based on the policy and at the end disable
6449 * the features that did not get any vectors.
6450 */
6451 pf->num_vmdq_msix = 0;
6452 }
6453
41c445ff
JB		 6454 if (vec < I40E_MIN_MSIX) {
6455 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6456 kfree(pf->msix_entries);
6457 pf->msix_entries = NULL;
6458 return -ENODEV;
6459
6460 } else if (vec == I40E_MIN_MSIX) {
6461 /* Adjust for minimal MSIX use */
41c445ff
JB		 6462 pf->num_vmdq_vsis = 0;
6463 pf->num_vmdq_qps = 0;
41c445ff
JB		 6464 pf->num_lan_qps = 1;
6465 pf->num_lan_msix = 1;
6466
6467 } else if (vec != v_budget) {
a34977ba
ASJ		 6468 /* reserve the misc vector */
6469 vec--;
6470
41c445ff
JB		 6471 /* Scale vector usage down */
6472 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6473 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6474
6475 /* partition out the remaining vectors */
6476 switch (vec) {
6477 case 2:
41c445ff
JB		 6478 pf->num_lan_msix = 1;
6479 break;
6480 case 3:
41c445ff
JB		 6481 pf->num_lan_msix = 2;
6482 break;
6483 default:
6484 pf->num_lan_msix = min_t(int, (vec / 2),
6485 pf->num_lan_qps);
6486 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6487 I40E_DEFAULT_NUM_VMDQ_VSI);
6488 break;
6489 }
6490 }
6491
a34977ba
ASJ		 6492 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6493 (pf->num_vmdq_msix == 0)) {
6494 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6495 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6496 }
41c445ff
JB		 6497 return err;
6498}
6499
493fb300 6500/**
90e04070 6501 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6502 * @vsi: the VSI being configured
6503 * @v_idx: index of the vector in the vsi struct
6504 *
6505 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6506 **/
90e04070 6507static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6508{
6509 struct i40e_q_vector *q_vector;
6510
6511 /* allocate q_vector */
6512 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6513 if (!q_vector)
6514 return -ENOMEM;
6515
6516 q_vector->vsi = vsi;
6517 q_vector->v_idx = v_idx;
6518 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6519 if (vsi->netdev)
6520 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6521 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6522
cd0b6fa6
AD		 6523 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6524 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6525
493fb300
AD		 6526 /* tie q_vector and vsi together */
6527 vsi->q_vectors[v_idx] = q_vector;
6528
6529 return 0;
6530}
6531
41c445ff 6532/**
90e04070 6533 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6534 * @vsi: the VSI being configured
6535 *
6536 * We allocate one q_vector per queue interrupt. If allocation fails we
6537 * return -ENOMEM.
6538 **/
90e04070 6539static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6540{
6541 struct i40e_pf *pf = vsi->back;
6542 int v_idx, num_q_vectors;
493fb300 6543 int err;
41c445ff
JB		 6544
6545 /* if not MSIX, give the one vector only to the LAN VSI */
6546 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6547 num_q_vectors = vsi->num_q_vectors;
6548 else if (vsi == pf->vsi[pf->lan_vsi])
6549 num_q_vectors = 1;
6550 else
6551 return -EINVAL;
6552
41c445ff 6553 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6554 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6555 if (err)
6556 goto err_out;
41c445ff
JB		 6557 }
6558
6559 return 0;
493fb300
AD		 6560
6561err_out:
6562 while (v_idx--)
6563 i40e_free_q_vector(vsi, v_idx);
6564
6565 return err;
41c445ff
JB		 6566}
6567
6568/**
6569 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6570 * @pf: board private structure to initialize
6571 **/
6572static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6573{
6574 int err = 0;
6575
6576 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6577 err = i40e_init_msix(pf);
6578 if (err) {
60ea5f83
JB		 6579 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6580 I40E_FLAG_RSS_ENABLED |
4d9b6043 6581 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6582 I40E_FLAG_SRIOV_ENABLED |
6583 I40E_FLAG_FD_SB_ENABLED |
6584 I40E_FLAG_FD_ATR_ENABLED |
6585 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6586
6587 /* rework the queue expectations without MSIX */
6588 i40e_determine_queue_usage(pf);
6589 }
6590 }
6591
6592 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6593 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6594 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6595 err = pci_enable_msi(pf->pdev);
6596 if (err) {
958a3e3b 6597 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6598 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6599 }
6600 }
6601
958a3e3b 6602 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6603 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6604
41c445ff
JB		 6605 /* track first vector for misc interrupts */
6606 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6607}
6608
6609/**
6610 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6611 * @pf: board private structure
6612 *
6613 * This sets up the handler for MSIX 0, which is used to manage the
6614 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6615 * when in MSI or Legacy interrupt mode.
6616 **/
6617static int i40e_setup_misc_vector(struct i40e_pf *pf)
6618{
6619 struct i40e_hw *hw = &pf->hw;
6620 int err = 0;
6621
6622 /* Only request the irq if this is the first time through, and
6623 * not when we're rebuilding after a Reset
6624 */
6625 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6626 err = request_irq(pf->msix_entries[0].vector,
6627 i40e_intr, 0, pf->misc_int_name, pf);
6628 if (err) {
6629 dev_info(&pf->pdev->dev,
77fa28be
CS		 6630 "request_irq for %s failed: %d\n",
6631 pf->misc_int_name, err);
41c445ff
JB		 6632 return -EFAULT;
6633 }
6634 }
6635
6636 i40e_enable_misc_int_causes(hw);
6637
6638 /* associate no queues to the misc vector */
6639 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6640 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6641
6642 i40e_flush(hw);
6643
6644 i40e_irq_dynamic_enable_icr0(pf);
6645
6646 return err;
6647}
6648
6649/**
6650 * i40e_config_rss - Prepare for RSS if used
6651 * @pf: board private structure
6652 **/
6653static int i40e_config_rss(struct i40e_pf *pf)
6654{
41c445ff
JB		 6655 /* Set of random keys generated using kernel random number generator */
6656 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6657 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6658 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6659 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6660 struct i40e_hw *hw = &pf->hw;
6661 u32 lut = 0;
6662 int i, j;
6663 u64 hena;
e157ea30 6664 u32 reg_val;
41c445ff
JB		 6665
6666 /* Fill out hash function seed */
6667 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6668 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6669
6670 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6671 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6672 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6673 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6674 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6675 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6676
e157ea30
CW		 6677 /* Check capability and Set table size and register per hw expectation*/
6678 reg_val = rd32(hw, I40E_PFQF_CTL_0);
6679 if (hw->func_caps.rss_table_size == 512) {
6680 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6681 pf->rss_table_size = 512;
6682 } else {
6683 pf->rss_table_size = 128;
6684 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6685 }
6686 wr32(hw, I40E_PFQF_CTL_0, reg_val);
6687
41c445ff 6688 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 6689 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 6690
6691 /* The assumption is that lan qp count will be the highest
6692 * qp count for any PF VSI that needs RSS.
6693 * If multiple VSIs need RSS support, all the qp counts
6694 * for those VSIs should be a power of 2 for RSS to work.
6695 * If LAN VSI is the only consumer for RSS then this requirement
6696 * is not necessary.
6697 */
6698 if (j == pf->rss_size)
6699 j = 0;
6700 /* lut = 4-byte sliding window of 4 lut entries */
6701 lut = (lut << 8) | (j &
6702 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6703 /* On i = 3, we have 4 entries in lut; write to the register */
6704 if ((i & 3) == 3)
6705 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6706 }
6707 i40e_flush(hw);
6708
6709 return 0;
6710}
6711
f8ff1464
ASJ		 6712/**
6713 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6714 * @pf: board private structure
6715 * @queue_count: the requested queue count for rss.
6716 *
6717 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6718 * count which may be different from the requested queue count.
6719 **/
6720int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6721{
6722 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6723 return 0;
6724
6725 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 6726
6727 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6728 i40e_prep_for_reset(pf);
6729
f8ff1464
ASJ		 6730 pf->rss_size = queue_count;
6731
6732 i40e_reset_and_rebuild(pf, true);
6733 i40e_config_rss(pf);
6734 }
6735 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6736 return pf->rss_size;
6737}
6738
41c445ff
JB		 6739/**
6740 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6741 * @pf: board private structure to initialize
6742 *
6743 * i40e_sw_init initializes the Adapter private data structure.
6744 * Fields are initialized based on PCI device information and
6745 * OS network device settings (MTU size).
6746 **/
6747static int i40e_sw_init(struct i40e_pf *pf)
6748{
6749 int err = 0;
6750 int size;
6751
6752 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6753 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6754 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6755 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6756 if (I40E_DEBUG_USER & debug)
6757 pf->hw.debug_mask = debug;
6758 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6759 I40E_DEFAULT_MSG_ENABLE);
6760 }
6761
6762 /* Set default capability flags */
6763 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6764 I40E_FLAG_MSI_ENABLED |
6765 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6766 I40E_FLAG_RX_1BUF_ENABLED;
6767
ca99eb99
MW		 6768 /* Set default ITR */
6769 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6770 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6771
7134f9ce
JB		 6772 /* Depending on PF configurations, it is possible that the RSS
6773 * maximum might end up larger than the available queues
6774 */
41c445ff 6775 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 6776 pf->rss_size = 1;
7134f9ce
JB		 6777 pf->rss_size_max = min_t(int, pf->rss_size_max,
6778 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6779 if (pf->hw.func_caps.rss) {
6780 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6781 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 6782 }
6783
2050bc65
CS		 6784 /* MFP mode enabled */
6785 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6786 pf->flags |= I40E_FLAG_MFP_ENABLED;
6787 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6788 }
6789
cbf61325
ASJ		 6790 /* FW/NVM is not yet fixed in this regard */
6791 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6792 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6793 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6794 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 6795 /* Setup a counter for fd_atr per pf */
6796 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 6797 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6798 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 6799 /* Setup a counter for fd_sb per pf */
6800 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 6801 } else {
6802 dev_info(&pf->pdev->dev,
0b67584f 6803 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6804 }
cbf61325
ASJ		 6805 pf->fdir_pf_filter_count =
6806 pf->hw.func_caps.fd_filters_guaranteed;
6807 pf->hw.fdir_shared_filter_count =
6808 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6809 }
6810
6811 if (pf->hw.func_caps.vmdq) {
6812 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6813 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6814 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6815 }
6816
41c445ff
JB		 6817#ifdef CONFIG_PCI_IOV
6818 if (pf->hw.func_caps.num_vfs) {
6819 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6820 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6821 pf->num_req_vfs = min_t(int,
6822 pf->hw.func_caps.num_vfs,
6823 I40E_MAX_VF_COUNT);
6824 }
6825#endif /* CONFIG_PCI_IOV */
6826 pf->eeprom_version = 0xDEAD;
6827 pf->lan_veb = I40E_NO_VEB;
6828 pf->lan_vsi = I40E_NO_VSI;
6829
6830 /* set up queue assignment tracking */
6831 size = sizeof(struct i40e_lump_tracking)
6832 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6833 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6834 if (!pf->qp_pile) {
6835 err = -ENOMEM;
6836 goto sw_init_done;
6837 }
6838 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6839 pf->qp_pile->search_hint = 0;
6840
6841 /* set up vector assignment tracking */
6842 size = sizeof(struct i40e_lump_tracking)
6843 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6844 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6845 if (!pf->irq_pile) {
6846 kfree(pf->qp_pile);
6847 err = -ENOMEM;
6848 goto sw_init_done;
6849 }
6850 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6851 pf->irq_pile->search_hint = 0;
6852
327fe04b
ASJ		 6853 pf->tx_timeout_recovery_level = 1;
6854
41c445ff
JB		 6855 mutex_init(&pf->switch_mutex);
6856
6857sw_init_done:
6858 return err;
6859}
6860
7c3c288b
ASJ		 6861/**
6862 * i40e_set_ntuple - set the ntuple feature flag and take action
6863 * @pf: board private structure to initialize
6864 * @features: the feature set that the stack is suggesting
6865 *
6866 * returns a bool to indicate if reset needs to happen
6867 **/
6868bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6869{
6870 bool need_reset = false;
6871
6872 /* Check if Flow Director n-tuple support was enabled or disabled. If
6873 * the state changed, we need to reset.
6874 */
6875 if (features & NETIF_F_NTUPLE) {
6876 /* Enable filters and mark for reset */
6877 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6878 need_reset = true;
6879 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6880 } else {
6881 /* turn off filters, mark for reset and clear SW filter list */
6882 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6883 need_reset = true;
6884 i40e_fdir_filter_exit(pf);
6885 }
6886 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb
ASJ		 6887 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
6888 /* if ATR was auto disabled it can be re-enabled. */
6889 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
6890 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
6891 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 6892 }
6893 return need_reset;
6894}
6895
41c445ff
JB		 6896/**
6897 * i40e_set_features - set the netdev feature flags
6898 * @netdev: ptr to the netdev being adjusted
6899 * @features: the feature set that the stack is suggesting
6900 **/
6901static int i40e_set_features(struct net_device *netdev,
6902 netdev_features_t features)
6903{
6904 struct i40e_netdev_priv *np = netdev_priv(netdev);
6905 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6906 struct i40e_pf *pf = vsi->back;
6907 bool need_reset;
41c445ff
JB		 6908
6909 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6910 i40e_vlan_stripping_enable(vsi);
6911 else
6912 i40e_vlan_stripping_disable(vsi);
6913
7c3c288b
ASJ		 6914 need_reset = i40e_set_ntuple(pf, features);
6915
6916 if (need_reset)
6917 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6918
41c445ff
JB		 6919 return 0;
6920}
6921
a1c9a9d9
JK		 6922#ifdef CONFIG_I40E_VXLAN
6923/**
6924 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6925 * @pf: board private structure
6926 * @port: The UDP port to look up
6927 *
6928 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6929 **/
6930static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6931{
6932 u8 i;
6933
6934 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6935 if (pf->vxlan_ports[i] == port)
6936 return i;
6937 }
6938
6939 return i;
6940}
6941
6942/**
6943 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6944 * @netdev: This physical port's netdev
6945 * @sa_family: Socket Family that VXLAN is notifying us about
6946 * @port: New UDP port number that VXLAN started listening to
6947 **/
6948static void i40e_add_vxlan_port(struct net_device *netdev,
6949 sa_family_t sa_family, __be16 port)
6950{
6951 struct i40e_netdev_priv *np = netdev_priv(netdev);
6952 struct i40e_vsi *vsi = np->vsi;
6953 struct i40e_pf *pf = vsi->back;
6954 u8 next_idx;
6955 u8 idx;
6956
6957 if (sa_family == AF_INET6)
6958 return;
6959
6960 idx = i40e_get_vxlan_port_idx(pf, port);
6961
6962 /* Check if port already exists */
6963 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6964 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6965 return;
6966 }
6967
6968 /* Now check if there is space to add the new port */
6969 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6970
6971 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6972 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6973 ntohs(port));
6974 return;
6975 }
6976
6977 /* New port: add it and mark its index in the bitmap */
6978 pf->vxlan_ports[next_idx] = port;
6979 pf->pending_vxlan_bitmap |= (1 << next_idx);
6980
6981 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6982}
6983
6984/**
6985 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6986 * @netdev: This physical port's netdev
6987 * @sa_family: Socket Family that VXLAN is notifying us about
6988 * @port: UDP port number that VXLAN stopped listening to
6989 **/
6990static void i40e_del_vxlan_port(struct net_device *netdev,
6991 sa_family_t sa_family, __be16 port)
6992{
6993 struct i40e_netdev_priv *np = netdev_priv(netdev);
6994 struct i40e_vsi *vsi = np->vsi;
6995 struct i40e_pf *pf = vsi->back;
6996 u8 idx;
6997
6998 if (sa_family == AF_INET6)
6999 return;
7000
7001 idx = i40e_get_vxlan_port_idx(pf, port);
7002
7003 /* Check if port already exists */
7004 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7005 /* if port exists, set it to 0 (mark for deletion)
7006 * and make it pending
7007 */
7008 pf->vxlan_ports[idx] = 0;
7009
7010 pf->pending_vxlan_bitmap |= (1 << idx);
7011
7012 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7013 } else {
7014 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7015 ntohs(port));
7016 }
7017}
7018
7019#endif
1f224ad2
NP		 7020static int i40e_get_phys_port_id(struct net_device *netdev,
7021 struct netdev_phys_port_id *ppid)
7022{
7023 struct i40e_netdev_priv *np = netdev_priv(netdev);
7024 struct i40e_pf *pf = np->vsi->back;
7025 struct i40e_hw *hw = &pf->hw;
7026
7027 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7028 return -EOPNOTSUPP;
7029
7030 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7031 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7032
7033 return 0;
7034}
7035
4ba0dea5
GR		 7036#ifdef HAVE_FDB_OPS
7037#ifdef USE_CONST_DEV_UC_CHAR
7038static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7039 struct net_device *dev,
7040 const unsigned char *addr,
7041 u16 flags)
7042#else
7043static int i40e_ndo_fdb_add(struct ndmsg *ndm,
7044 struct net_device *dev,
7045 unsigned char *addr,
7046 u16 flags)
7047#endif
7048{
7049 struct i40e_netdev_priv *np = netdev_priv(dev);
7050 struct i40e_pf *pf = np->vsi->back;
7051 int err = 0;
7052
7053 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7054 return -EOPNOTSUPP;
7055
7056 /* Hardware does not support aging addresses so if a
7057 * ndm_state is given only allow permanent addresses
7058 */
7059 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7060 netdev_info(dev, "FDB only supports static addresses\n");
7061 return -EINVAL;
7062 }
7063
7064 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7065 err = dev_uc_add_excl(dev, addr);
7066 else if (is_multicast_ether_addr(addr))
7067 err = dev_mc_add_excl(dev, addr);
7068 else
7069 err = -EINVAL;
7070
7071 /* Only return duplicate errors if NLM_F_EXCL is set */
7072 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7073 err = 0;
7074
7075 return err;
7076}
7077
7078#ifndef USE_DEFAULT_FDB_DEL_DUMP
7079#ifdef USE_CONST_DEV_UC_CHAR
7080static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7081 struct net_device *dev,
7082 const unsigned char *addr)
7083#else
7084static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7085 struct net_device *dev,
7086 unsigned char *addr)
7087#endif
7088{
7089 struct i40e_netdev_priv *np = netdev_priv(dev);
7090 struct i40e_pf *pf = np->vsi->back;
7091 int err = -EOPNOTSUPP;
7092
7093 if (ndm->ndm_state & NUD_PERMANENT) {
7094 netdev_info(dev, "FDB only supports static addresses\n");
7095 return -EINVAL;
7096 }
7097
7098 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7099 if (is_unicast_ether_addr(addr))
7100 err = dev_uc_del(dev, addr);
7101 else if (is_multicast_ether_addr(addr))
7102 err = dev_mc_del(dev, addr);
7103 else
7104 err = -EINVAL;
7105 }
7106
7107 return err;
7108}
7109
7110static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7111 struct netlink_callback *cb,
7112 struct net_device *dev,
5d5eacb3 7113 struct net_device *filter_dev,
4ba0dea5
GR		 7114 int idx)
7115{
7116 struct i40e_netdev_priv *np = netdev_priv(dev);
7117 struct i40e_pf *pf = np->vsi->back;
7118
7119 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
5d5eacb3 7120 idx = ndo_dflt_fdb_dump(skb, cb, dev, filter_dev, idx);
4ba0dea5
GR		 7121
7122 return idx;
7123}
7124
7125#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7126#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7127static const struct net_device_ops i40e_netdev_ops = {
7128 .ndo_open = i40e_open,
7129 .ndo_stop = i40e_close,
7130 .ndo_start_xmit = i40e_lan_xmit_frame,
7131 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7132 .ndo_set_rx_mode = i40e_set_rx_mode,
7133 .ndo_validate_addr = eth_validate_addr,
7134 .ndo_set_mac_address = i40e_set_mac,
7135 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7136 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7137 .ndo_tx_timeout = i40e_tx_timeout,
7138 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7139 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7140#ifdef CONFIG_NET_POLL_CONTROLLER
7141 .ndo_poll_controller = i40e_netpoll,
7142#endif
7143 .ndo_setup_tc = i40e_setup_tc,
7144 .ndo_set_features = i40e_set_features,
7145 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7146 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7147 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7148 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7149 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
c674d125 7150 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofck,
a1c9a9d9
JK		 7151#ifdef CONFIG_I40E_VXLAN
7152 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7153 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7154#endif
1f224ad2 7155 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5
GR		 7156#ifdef HAVE_FDB_OPS
7157 .ndo_fdb_add = i40e_ndo_fdb_add,
7158#ifndef USE_DEFAULT_FDB_DEL_DUMP
7159 .ndo_fdb_del = i40e_ndo_fdb_del,
7160 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7161#endif
7162#endif
41c445ff
JB		 7163};
7164
7165/**
7166 * i40e_config_netdev - Setup the netdev flags
7167 * @vsi: the VSI being configured
7168 *
7169 * Returns 0 on success, negative value on failure
7170 **/
7171static int i40e_config_netdev(struct i40e_vsi *vsi)
7172{
1a10370a 7173 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7174 struct i40e_pf *pf = vsi->back;
7175 struct i40e_hw *hw = &pf->hw;
7176 struct i40e_netdev_priv *np;
7177 struct net_device *netdev;
7178 u8 mac_addr[ETH_ALEN];
7179 int etherdev_size;
7180
7181 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7182 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7183 if (!netdev)
7184 return -ENOMEM;
7185
7186 vsi->netdev = netdev;
7187 np = netdev_priv(netdev);
7188 np->vsi = vsi;
7189
d70e941b 7190 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7191 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7192 NETIF_F_TSO;
41c445ff
JB		 7193
7194 netdev->features = NETIF_F_SG |
7195 NETIF_F_IP_CSUM |
7196 NETIF_F_SCTP_CSUM |
7197 NETIF_F_HIGHDMA |
7198 NETIF_F_GSO_UDP_TUNNEL |
7199 NETIF_F_HW_VLAN_CTAG_TX |
7200 NETIF_F_HW_VLAN_CTAG_RX |
7201 NETIF_F_HW_VLAN_CTAG_FILTER |
7202 NETIF_F_IPV6_CSUM |
7203 NETIF_F_TSO |
059dab69 7204 NETIF_F_TSO_ECN |
41c445ff
JB		 7205 NETIF_F_TSO6 |
7206 NETIF_F_RXCSUM |
7207 NETIF_F_RXHASH |
7208 0;
7209
2e86a0b6
ASJ		 7210 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7211 netdev->features |= NETIF_F_NTUPLE;
7212
41c445ff
JB		 7213 /* copy netdev features into list of user selectable features */
7214 netdev->hw_features |= netdev->features;
7215
7216 if (vsi->type == I40E_VSI_MAIN) {
7217 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7218 ether_addr_copy(mac_addr, hw->mac.perm_addr);
8c27d42e
GR		 7219 /* The following two steps are necessary to prevent reception
7220 * of tagged packets - by default the NVM loads a MAC-VLAN
7221 * filter that will accept any tagged packet. This is to
7222 * prevent that during normal operations until a specific
7223 * VLAN tag filter has been set.
7224 */
7225 i40e_rm_default_mac_filter(vsi, mac_addr);
7226 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true);
41c445ff
JB		 7227 } else {
7228 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7229 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7230 pf->vsi[pf->lan_vsi]->netdev->name);
7231 random_ether_addr(mac_addr);
7232 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7233 }
1a10370a 7234 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7235
9a173901
GR		 7236 ether_addr_copy(netdev->dev_addr, mac_addr);
7237 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7238 /* vlan gets same features (except vlan offload)
7239 * after any tweaks for specific VSI types
7240 */
7241 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7242 NETIF_F_HW_VLAN_CTAG_RX |
7243 NETIF_F_HW_VLAN_CTAG_FILTER);
7244 netdev->priv_flags |= IFF_UNICAST_FLT;
7245 netdev->priv_flags |= IFF_SUPP_NOFCS;
7246 /* Setup netdev TC information */
7247 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7248
7249 netdev->netdev_ops = &i40e_netdev_ops;
7250 netdev->watchdog_timeo = 5 * HZ;
7251 i40e_set_ethtool_ops(netdev);
7252
7253 return 0;
7254}
7255
7256/**
7257 * i40e_vsi_delete - Delete a VSI from the switch
7258 * @vsi: the VSI being removed
7259 *
7260 * Returns 0 on success, negative value on failure
7261 **/
7262static void i40e_vsi_delete(struct i40e_vsi *vsi)
7263{
7264 /* remove default VSI is not allowed */
7265 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7266 return;
7267
41c445ff 7268 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7269}
7270
7271/**
7272 * i40e_add_vsi - Add a VSI to the switch
7273 * @vsi: the VSI being configured
7274 *
7275 * This initializes a VSI context depending on the VSI type to be added and
7276 * passes it down to the add_vsi aq command.
7277 **/
7278static int i40e_add_vsi(struct i40e_vsi *vsi)
7279{
7280 int ret = -ENODEV;
7281 struct i40e_mac_filter *f, *ftmp;
7282 struct i40e_pf *pf = vsi->back;
7283 struct i40e_hw *hw = &pf->hw;
7284 struct i40e_vsi_context ctxt;
7285 u8 enabled_tc = 0x1; /* TC0 enabled */
7286 int f_count = 0;
7287
7288 memset(&ctxt, 0, sizeof(ctxt));
7289 switch (vsi->type) {
7290 case I40E_VSI_MAIN:
7291 /* The PF's main VSI is already setup as part of the
7292 * device initialization, so we'll not bother with
7293 * the add_vsi call, but we will retrieve the current
7294 * VSI context.
7295 */
7296 ctxt.seid = pf->main_vsi_seid;
7297 ctxt.pf_num = pf->hw.pf_id;
7298 ctxt.vf_num = 0;
7299 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7300 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7301 if (ret) {
7302 dev_info(&pf->pdev->dev,
7303 "couldn't get pf vsi config, err %d, aq_err %d\n",
7304 ret, pf->hw.aq.asq_last_status);
7305 return -ENOENT;
7306 }
7307 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7308 vsi->info.valid_sections = 0;
7309
7310 vsi->seid = ctxt.seid;
7311 vsi->id = ctxt.vsi_number;
7312
7313 enabled_tc = i40e_pf_get_tc_map(pf);
7314
7315 /* MFP mode setup queue map and update VSI */
7316 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7317 memset(&ctxt, 0, sizeof(ctxt));
7318 ctxt.seid = pf->main_vsi_seid;
7319 ctxt.pf_num = pf->hw.pf_id;
7320 ctxt.vf_num = 0;
7321 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7322 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7323 if (ret) {
7324 dev_info(&pf->pdev->dev,
7325 "update vsi failed, aq_err=%d\n",
7326 pf->hw.aq.asq_last_status);
7327 ret = -ENOENT;
7328 goto err;
7329 }
7330 /* update the local VSI info queue map */
7331 i40e_vsi_update_queue_map(vsi, &ctxt);
7332 vsi->info.valid_sections = 0;
7333 } else {
7334 /* Default/Main VSI is only enabled for TC0
7335 * reconfigure it to enable all TCs that are
7336 * available on the port in SFP mode.
7337 */
7338 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7339 if (ret) {
7340 dev_info(&pf->pdev->dev,
7341 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7342 enabled_tc, ret,
7343 pf->hw.aq.asq_last_status);
7344 ret = -ENOENT;
7345 }
7346 }
7347 break;
7348
7349 case I40E_VSI_FDIR:
cbf61325
ASJ		 7350 ctxt.pf_num = hw->pf_id;
7351 ctxt.vf_num = 0;
7352 ctxt.uplink_seid = vsi->uplink_seid;
7353 ctxt.connection_type = 0x1; /* regular data port */
7354 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7355 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7356 break;
7357
7358 case I40E_VSI_VMDQ2:
7359 ctxt.pf_num = hw->pf_id;
7360 ctxt.vf_num = 0;
7361 ctxt.uplink_seid = vsi->uplink_seid;
7362 ctxt.connection_type = 0x1; /* regular data port */
7363 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7364
7365 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7366
7367 /* This VSI is connected to VEB so the switch_id
7368 * should be set to zero by default.
7369 */
7370 ctxt.info.switch_id = 0;
7371 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
7372 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7373
7374 /* Setup the VSI tx/rx queue map for TC0 only for now */
7375 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7376 break;
7377
7378 case I40E_VSI_SRIOV:
7379 ctxt.pf_num = hw->pf_id;
7380 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7381 ctxt.uplink_seid = vsi->uplink_seid;
7382 ctxt.connection_type = 0x1; /* regular data port */
7383 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7384
7385 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7386
7387 /* This VSI is connected to VEB so the switch_id
7388 * should be set to zero by default.
7389 */
7390 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7391
7392 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7393 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7394 if (pf->vf[vsi->vf_id].spoofchk) {
7395 ctxt.info.valid_sections |=
7396 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7397 ctxt.info.sec_flags |=
7398 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7399 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7400 }
41c445ff
JB		 7401 /* Setup the VSI tx/rx queue map for TC0 only for now */
7402 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7403 break;
7404
7405 default:
7406 return -ENODEV;
7407 }
7408
7409 if (vsi->type != I40E_VSI_MAIN) {
7410 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7411 if (ret) {
7412 dev_info(&vsi->back->pdev->dev,
7413 "add vsi failed, aq_err=%d\n",
7414 vsi->back->hw.aq.asq_last_status);
7415 ret = -ENOENT;
7416 goto err;
7417 }
7418 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7419 vsi->info.valid_sections = 0;
7420 vsi->seid = ctxt.seid;
7421 vsi->id = ctxt.vsi_number;
7422 }
7423
7424 /* If macvlan filters already exist, force them to get loaded */
7425 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7426 f->changed = true;
7427 f_count++;
6252c7e4
SN		 7428
7429 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
7430 i40e_aq_mac_address_write(&vsi->back->hw,
7431 I40E_AQC_WRITE_TYPE_LAA_WOL,
7432 f->macaddr, NULL);
7433 }
41c445ff
JB		 7434 }
7435 if (f_count) {
7436 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7437 pf->flags |= I40E_FLAG_FILTER_SYNC;
7438 }
7439
7440 /* Update VSI BW information */
7441 ret = i40e_vsi_get_bw_info(vsi);
7442 if (ret) {
7443 dev_info(&pf->pdev->dev,
7444 "couldn't get vsi bw info, err %d, aq_err %d\n",
7445 ret, pf->hw.aq.asq_last_status);
7446 /* VSI is already added so not tearing that up */
7447 ret = 0;
7448 }
7449
7450err:
7451 return ret;
7452}
7453
7454/**
7455 * i40e_vsi_release - Delete a VSI and free its resources
7456 * @vsi: the VSI being removed
7457 *
7458 * Returns 0 on success or < 0 on error
7459 **/
7460int i40e_vsi_release(struct i40e_vsi *vsi)
7461{
7462 struct i40e_mac_filter *f, *ftmp;
7463 struct i40e_veb *veb = NULL;
7464 struct i40e_pf *pf;
7465 u16 uplink_seid;
7466 int i, n;
7467
7468 pf = vsi->back;
7469
7470 /* release of a VEB-owner or last VSI is not allowed */
7471 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7472 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7473 vsi->seid, vsi->uplink_seid);
7474 return -ENODEV;
7475 }
7476 if (vsi == pf->vsi[pf->lan_vsi] &&
7477 !test_bit(__I40E_DOWN, &pf->state)) {
7478 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7479 return -ENODEV;
7480 }
7481
7482 uplink_seid = vsi->uplink_seid;
7483 if (vsi->type != I40E_VSI_SRIOV) {
7484 if (vsi->netdev_registered) {
7485 vsi->netdev_registered = false;
7486 if (vsi->netdev) {
7487 /* results in a call to i40e_close() */
7488 unregister_netdev(vsi->netdev);
41c445ff
JB		 7489 }
7490 } else {
90ef8d47 7491 i40e_vsi_close(vsi);
41c445ff
JB		 7492 }
7493 i40e_vsi_disable_irq(vsi);
7494 }
7495
7496 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7497 i40e_del_filter(vsi, f->macaddr, f->vlan,
7498 f->is_vf, f->is_netdev);
7499 i40e_sync_vsi_filters(vsi);
7500
7501 i40e_vsi_delete(vsi);
7502 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7503 if (vsi->netdev) {
7504 free_netdev(vsi->netdev);
7505 vsi->netdev = NULL;
7506 }
41c445ff
JB		 7507 i40e_vsi_clear_rings(vsi);
7508 i40e_vsi_clear(vsi);
7509
7510 /* If this was the last thing on the VEB, except for the
7511 * controlling VSI, remove the VEB, which puts the controlling
7512 * VSI onto the next level down in the switch.
7513 *
7514 * Well, okay, there's one more exception here: don't remove
7515 * the orphan VEBs yet. We'll wait for an explicit remove request
7516 * from up the network stack.
7517 */
505682cd 7518 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7519 if (pf->vsi[i] &&
7520 pf->vsi[i]->uplink_seid == uplink_seid &&
7521 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7522 n++; /* count the VSIs */
7523 }
7524 }
7525 for (i = 0; i < I40E_MAX_VEB; i++) {
7526 if (!pf->veb[i])
7527 continue;
7528 if (pf->veb[i]->uplink_seid == uplink_seid)
7529 n++; /* count the VEBs */
7530 if (pf->veb[i]->seid == uplink_seid)
7531 veb = pf->veb[i];
7532 }
7533 if (n == 0 && veb && veb->uplink_seid != 0)
7534 i40e_veb_release(veb);
7535
7536 return 0;
7537}
7538
7539/**
7540 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7541 * @vsi: ptr to the VSI
7542 *
7543 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7544 * corresponding SW VSI structure and initializes num_queue_pairs for the
7545 * newly allocated VSI.
7546 *
7547 * Returns 0 on success or negative on failure
7548 **/
7549static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7550{
7551 int ret = -ENOENT;
7552 struct i40e_pf *pf = vsi->back;
7553
493fb300 7554 if (vsi->q_vectors[0]) {
41c445ff
JB		 7555 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7556 vsi->seid);
7557 return -EEXIST;
7558 }
7559
7560 if (vsi->base_vector) {
f29eaa3d 7561 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7562 vsi->seid, vsi->base_vector);
7563 return -EEXIST;
7564 }
7565
90e04070 7566 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7567 if (ret) {
7568 dev_info(&pf->pdev->dev,
7569 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7570 vsi->num_q_vectors, vsi->seid, ret);
7571 vsi->num_q_vectors = 0;
7572 goto vector_setup_out;
7573 }
7574
958a3e3b
SN		 7575 if (vsi->num_q_vectors)
7576 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7577 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7578 if (vsi->base_vector < 0) {
7579 dev_info(&pf->pdev->dev,
f29eaa3d 7580 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7581 vsi->seid, vsi->base_vector);
7582 i40e_vsi_free_q_vectors(vsi);
7583 ret = -ENOENT;
7584 goto vector_setup_out;
7585 }
7586
7587vector_setup_out:
7588 return ret;
7589}
7590
bc7d338f
ASJ		 7591/**
7592 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7593 * @vsi: pointer to the vsi.
7594 *
7595 * This re-allocates a vsi's queue resources.
7596 *
7597 * Returns pointer to the successfully allocated and configured VSI sw struct
7598 * on success, otherwise returns NULL on failure.
7599 **/
7600static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7601{
7602 struct i40e_pf *pf = vsi->back;
7603 u8 enabled_tc;
7604 int ret;
7605
7606 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7607 i40e_vsi_clear_rings(vsi);
7608
7609 i40e_vsi_free_arrays(vsi, false);
7610 i40e_set_num_rings_in_vsi(vsi);
7611 ret = i40e_vsi_alloc_arrays(vsi, false);
7612 if (ret)
7613 goto err_vsi;
7614
7615 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7616 if (ret < 0) {
7617 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7618 vsi->seid, ret);
7619 goto err_vsi;
7620 }
7621 vsi->base_queue = ret;
7622
7623 /* Update the FW view of the VSI. Force a reset of TC and queue
7624 * layout configurations.
7625 */
7626 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7627 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7628 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7629 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7630
7631 /* assign it some queues */
7632 ret = i40e_alloc_rings(vsi);
7633 if (ret)
7634 goto err_rings;
7635
7636 /* map all of the rings to the q_vectors */
7637 i40e_vsi_map_rings_to_vectors(vsi);
7638 return vsi;
7639
7640err_rings:
7641 i40e_vsi_free_q_vectors(vsi);
7642 if (vsi->netdev_registered) {
7643 vsi->netdev_registered = false;
7644 unregister_netdev(vsi->netdev);
7645 free_netdev(vsi->netdev);
7646 vsi->netdev = NULL;
7647 }
7648 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7649err_vsi:
7650 i40e_vsi_clear(vsi);
7651 return NULL;
7652}
7653
41c445ff
JB		 7654/**
7655 * i40e_vsi_setup - Set up a VSI by a given type
7656 * @pf: board private structure
7657 * @type: VSI type
7658 * @uplink_seid: the switch element to link to
7659 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7660 *
7661 * This allocates the sw VSI structure and its queue resources, then add a VSI
7662 * to the identified VEB.
7663 *
7664 * Returns pointer to the successfully allocated and configure VSI sw struct on
7665 * success, otherwise returns NULL on failure.
7666 **/
7667struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7668 u16 uplink_seid, u32 param1)
7669{
7670 struct i40e_vsi *vsi = NULL;
7671 struct i40e_veb *veb = NULL;
7672 int ret, i;
7673 int v_idx;
7674
7675 /* The requested uplink_seid must be either
7676 * - the PF's port seid
7677 * no VEB is needed because this is the PF
7678 * or this is a Flow Director special case VSI
7679 * - seid of an existing VEB
7680 * - seid of a VSI that owns an existing VEB
7681 * - seid of a VSI that doesn't own a VEB
7682 * a new VEB is created and the VSI becomes the owner
7683 * - seid of the PF VSI, which is what creates the first VEB
7684 * this is a special case of the previous
7685 *
7686 * Find which uplink_seid we were given and create a new VEB if needed
7687 */
7688 for (i = 0; i < I40E_MAX_VEB; i++) {
7689 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7690 veb = pf->veb[i];
7691 break;
7692 }
7693 }
7694
7695 if (!veb && uplink_seid != pf->mac_seid) {
7696
505682cd 7697 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7698 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7699 vsi = pf->vsi[i];
7700 break;
7701 }
7702 }
7703 if (!vsi) {
7704 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7705 uplink_seid);
7706 return NULL;
7707 }
7708
7709 if (vsi->uplink_seid == pf->mac_seid)
7710 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7711 vsi->tc_config.enabled_tc);
7712 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7713 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7714 vsi->tc_config.enabled_tc);
7715
7716 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7717 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7718 veb = pf->veb[i];
7719 }
7720 if (!veb) {
7721 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7722 return NULL;
7723 }
7724
7725 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7726 uplink_seid = veb->seid;
7727 }
7728
7729 /* get vsi sw struct */
7730 v_idx = i40e_vsi_mem_alloc(pf, type);
7731 if (v_idx < 0)
7732 goto err_alloc;
7733 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7734 if (!vsi)
7735 goto err_alloc;
41c445ff
JB		 7736 vsi->type = type;
7737 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7738
7739 if (type == I40E_VSI_MAIN)
7740 pf->lan_vsi = v_idx;
7741 else if (type == I40E_VSI_SRIOV)
7742 vsi->vf_id = param1;
7743 /* assign it some queues */
cbf61325
ASJ		 7744 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7745 vsi->idx);
41c445ff
JB		 7746 if (ret < 0) {
7747 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7748 vsi->seid, ret);
7749 goto err_vsi;
7750 }
7751 vsi->base_queue = ret;
7752
7753 /* get a VSI from the hardware */
7754 vsi->uplink_seid = uplink_seid;
7755 ret = i40e_add_vsi(vsi);
7756 if (ret)
7757 goto err_vsi;
7758
7759 switch (vsi->type) {
7760 /* setup the netdev if needed */
7761 case I40E_VSI_MAIN:
7762 case I40E_VSI_VMDQ2:
7763 ret = i40e_config_netdev(vsi);
7764 if (ret)
7765 goto err_netdev;
7766 ret = register_netdev(vsi->netdev);
7767 if (ret)
7768 goto err_netdev;
7769 vsi->netdev_registered = true;
7770 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7771#ifdef CONFIG_I40E_DCB
7772 /* Setup DCB netlink interface */
7773 i40e_dcbnl_setup(vsi);
7774#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7775 /* fall through */
7776
7777 case I40E_VSI_FDIR:
7778 /* set up vectors and rings if needed */
7779 ret = i40e_vsi_setup_vectors(vsi);
7780 if (ret)
7781 goto err_msix;
7782
7783 ret = i40e_alloc_rings(vsi);
7784 if (ret)
7785 goto err_rings;
7786
7787 /* map all of the rings to the q_vectors */
7788 i40e_vsi_map_rings_to_vectors(vsi);
7789
7790 i40e_vsi_reset_stats(vsi);
7791 break;
7792
7793 default:
7794 /* no netdev or rings for the other VSI types */
7795 break;
7796 }
7797
7798 return vsi;
7799
7800err_rings:
7801 i40e_vsi_free_q_vectors(vsi);
7802err_msix:
7803 if (vsi->netdev_registered) {
7804 vsi->netdev_registered = false;
7805 unregister_netdev(vsi->netdev);
7806 free_netdev(vsi->netdev);
7807 vsi->netdev = NULL;
7808 }
7809err_netdev:
7810 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7811err_vsi:
7812 i40e_vsi_clear(vsi);
7813err_alloc:
7814 return NULL;
7815}
7816
7817/**
7818 * i40e_veb_get_bw_info - Query VEB BW information
7819 * @veb: the veb to query
7820 *
7821 * Query the Tx scheduler BW configuration data for given VEB
7822 **/
7823static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7824{
7825 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7826 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7827 struct i40e_pf *pf = veb->pf;
7828 struct i40e_hw *hw = &pf->hw;
7829 u32 tc_bw_max;
7830 int ret = 0;
7831 int i;
7832
7833 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7834 &bw_data, NULL);
7835 if (ret) {
7836 dev_info(&pf->pdev->dev,
7837 "query veb bw config failed, aq_err=%d\n",
7838 hw->aq.asq_last_status);
7839 goto out;
7840 }
7841
7842 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7843 &ets_data, NULL);
7844 if (ret) {
7845 dev_info(&pf->pdev->dev,
7846 "query veb bw ets config failed, aq_err=%d\n",
7847 hw->aq.asq_last_status);
7848 goto out;
7849 }
7850
7851 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7852 veb->bw_max_quanta = ets_data.tc_bw_max;
7853 veb->is_abs_credits = bw_data.absolute_credits_enable;
7854 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7855 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7856 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7857 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7858 veb->bw_tc_limit_credits[i] =
7859 le16_to_cpu(bw_data.tc_bw_limits[i]);
7860 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7861 }
7862
7863out:
7864 return ret;
7865}
7866
7867/**
7868 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7869 * @pf: board private structure
7870 *
7871 * On error: returns error code (negative)
7872 * On success: returns vsi index in PF (positive)
7873 **/
7874static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7875{
7876 int ret = -ENOENT;
7877 struct i40e_veb *veb;
7878 int i;
7879
7880 /* Need to protect the allocation of switch elements at the PF level */
7881 mutex_lock(&pf->switch_mutex);
7882
7883 /* VEB list may be fragmented if VEB creation/destruction has
7884 * been happening. We can afford to do a quick scan to look
7885 * for any free slots in the list.
7886 *
7887 * find next empty veb slot, looping back around if necessary
7888 */
7889 i = 0;
7890 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7891 i++;
7892 if (i >= I40E_MAX_VEB) {
7893 ret = -ENOMEM;
7894 goto err_alloc_veb; /* out of VEB slots! */
7895 }
7896
7897 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7898 if (!veb) {
7899 ret = -ENOMEM;
7900 goto err_alloc_veb;
7901 }
7902 veb->pf = pf;
7903 veb->idx = i;
7904 veb->enabled_tc = 1;
7905
7906 pf->veb[i] = veb;
7907 ret = i;
7908err_alloc_veb:
7909 mutex_unlock(&pf->switch_mutex);
7910 return ret;
7911}
7912
7913/**
7914 * i40e_switch_branch_release - Delete a branch of the switch tree
7915 * @branch: where to start deleting
7916 *
7917 * This uses recursion to find the tips of the branch to be
7918 * removed, deleting until we get back to and can delete this VEB.
7919 **/
7920static void i40e_switch_branch_release(struct i40e_veb *branch)
7921{
7922 struct i40e_pf *pf = branch->pf;
7923 u16 branch_seid = branch->seid;
7924 u16 veb_idx = branch->idx;
7925 int i;
7926
7927 /* release any VEBs on this VEB - RECURSION */
7928 for (i = 0; i < I40E_MAX_VEB; i++) {
7929 if (!pf->veb[i])
7930 continue;
7931 if (pf->veb[i]->uplink_seid == branch->seid)
7932 i40e_switch_branch_release(pf->veb[i]);
7933 }
7934
7935 /* Release the VSIs on this VEB, but not the owner VSI.
7936 *
7937 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7938 * the VEB itself, so don't use (*branch) after this loop.
7939 */
505682cd 7940 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7941 if (!pf->vsi[i])
7942 continue;
7943 if (pf->vsi[i]->uplink_seid == branch_seid &&
7944 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7945 i40e_vsi_release(pf->vsi[i]);
7946 }
7947 }
7948
7949 /* There's one corner case where the VEB might not have been
7950 * removed, so double check it here and remove it if needed.
7951 * This case happens if the veb was created from the debugfs
7952 * commands and no VSIs were added to it.
7953 */
7954 if (pf->veb[veb_idx])
7955 i40e_veb_release(pf->veb[veb_idx]);
7956}
7957
7958/**
7959 * i40e_veb_clear - remove veb struct
7960 * @veb: the veb to remove
7961 **/
7962static void i40e_veb_clear(struct i40e_veb *veb)
7963{
7964 if (!veb)
7965 return;
7966
7967 if (veb->pf) {
7968 struct i40e_pf *pf = veb->pf;
7969
7970 mutex_lock(&pf->switch_mutex);
7971 if (pf->veb[veb->idx] == veb)
7972 pf->veb[veb->idx] = NULL;
7973 mutex_unlock(&pf->switch_mutex);
7974 }
7975
7976 kfree(veb);
7977}
7978
7979/**
7980 * i40e_veb_release - Delete a VEB and free its resources
7981 * @veb: the VEB being removed
7982 **/
7983void i40e_veb_release(struct i40e_veb *veb)
7984{
7985 struct i40e_vsi *vsi = NULL;
7986 struct i40e_pf *pf;
7987 int i, n = 0;
7988
7989 pf = veb->pf;
7990
7991 /* find the remaining VSI and check for extras */
505682cd 7992 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7993 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7994 n++;
7995 vsi = pf->vsi[i];
7996 }
7997 }
7998 if (n != 1) {
7999 dev_info(&pf->pdev->dev,
8000 "can't remove VEB %d with %d VSIs left\n",
8001 veb->seid, n);
8002 return;
8003 }
8004
8005 /* move the remaining VSI to uplink veb */
8006 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8007 if (veb->uplink_seid) {
8008 vsi->uplink_seid = veb->uplink_seid;
8009 if (veb->uplink_seid == pf->mac_seid)
8010 vsi->veb_idx = I40E_NO_VEB;
8011 else
8012 vsi->veb_idx = veb->veb_idx;
8013 } else {
8014 /* floating VEB */
8015 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8016 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8017 }
8018
8019 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8020 i40e_veb_clear(veb);
41c445ff
JB		 8021}
8022
8023/**
8024 * i40e_add_veb - create the VEB in the switch
8025 * @veb: the VEB to be instantiated
8026 * @vsi: the controlling VSI
8027 **/
8028static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8029{
56747264 8030 bool is_default = false;
e1c51b95 8031 bool is_cloud = false;
41c445ff
JB		 8032 int ret;
8033
8034 /* get a VEB from the hardware */
8035 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8036 veb->enabled_tc, is_default,
8037 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8038 if (ret) {
8039 dev_info(&veb->pf->pdev->dev,
8040 "couldn't add VEB, err %d, aq_err %d\n",
8041 ret, veb->pf->hw.aq.asq_last_status);
8042 return -EPERM;
8043 }
8044
8045 /* get statistics counter */
8046 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8047 &veb->stats_idx, NULL, NULL, NULL);
8048 if (ret) {
8049 dev_info(&veb->pf->pdev->dev,
8050 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8051 ret, veb->pf->hw.aq.asq_last_status);
8052 return -EPERM;
8053 }
8054 ret = i40e_veb_get_bw_info(veb);
8055 if (ret) {
8056 dev_info(&veb->pf->pdev->dev,
8057 "couldn't get VEB bw info, err %d, aq_err %d\n",
8058 ret, veb->pf->hw.aq.asq_last_status);
8059 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8060 return -ENOENT;
8061 }
8062
8063 vsi->uplink_seid = veb->seid;
8064 vsi->veb_idx = veb->idx;
8065 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8066
8067 return 0;
8068}
8069
8070/**
8071 * i40e_veb_setup - Set up a VEB
8072 * @pf: board private structure
8073 * @flags: VEB setup flags
8074 * @uplink_seid: the switch element to link to
8075 * @vsi_seid: the initial VSI seid
8076 * @enabled_tc: Enabled TC bit-map
8077 *
8078 * This allocates the sw VEB structure and links it into the switch
8079 * It is possible and legal for this to be a duplicate of an already
8080 * existing VEB. It is also possible for both uplink and vsi seids
8081 * to be zero, in order to create a floating VEB.
8082 *
8083 * Returns pointer to the successfully allocated VEB sw struct on
8084 * success, otherwise returns NULL on failure.
8085 **/
8086struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8087 u16 uplink_seid, u16 vsi_seid,
8088 u8 enabled_tc)
8089{
8090 struct i40e_veb *veb, *uplink_veb = NULL;
8091 int vsi_idx, veb_idx;
8092 int ret;
8093
8094 /* if one seid is 0, the other must be 0 to create a floating relay */
8095 if ((uplink_seid == 0 || vsi_seid == 0) &&
8096 (uplink_seid + vsi_seid != 0)) {
8097 dev_info(&pf->pdev->dev,
8098 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8099 uplink_seid, vsi_seid);
8100 return NULL;
8101 }
8102
8103 /* make sure there is such a vsi and uplink */
505682cd 8104 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8105 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8106 break;
505682cd 8107 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8108 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8109 vsi_seid);
8110 return NULL;
8111 }
8112
8113 if (uplink_seid && uplink_seid != pf->mac_seid) {
8114 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8115 if (pf->veb[veb_idx] &&
8116 pf->veb[veb_idx]->seid == uplink_seid) {
8117 uplink_veb = pf->veb[veb_idx];
8118 break;
8119 }
8120 }
8121 if (!uplink_veb) {
8122 dev_info(&pf->pdev->dev,
8123 "uplink seid %d not found\n", uplink_seid);
8124 return NULL;
8125 }
8126 }
8127
8128 /* get veb sw struct */
8129 veb_idx = i40e_veb_mem_alloc(pf);
8130 if (veb_idx < 0)
8131 goto err_alloc;
8132 veb = pf->veb[veb_idx];
8133 veb->flags = flags;
8134 veb->uplink_seid = uplink_seid;
8135 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8136 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8137
8138 /* create the VEB in the switch */
8139 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8140 if (ret)
8141 goto err_veb;
1bb8b935
SN		 8142 if (vsi_idx == pf->lan_vsi)
8143 pf->lan_veb = veb->idx;
41c445ff
JB		 8144
8145 return veb;
8146
8147err_veb:
8148 i40e_veb_clear(veb);
8149err_alloc:
8150 return NULL;
8151}
8152
8153/**
8154 * i40e_setup_pf_switch_element - set pf vars based on switch type
8155 * @pf: board private structure
8156 * @ele: element we are building info from
8157 * @num_reported: total number of elements
8158 * @printconfig: should we print the contents
8159 *
8160 * helper function to assist in extracting a few useful SEID values.
8161 **/
8162static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8163 struct i40e_aqc_switch_config_element_resp *ele,
8164 u16 num_reported, bool printconfig)
8165{
8166 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8167 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8168 u8 element_type = ele->element_type;
8169 u16 seid = le16_to_cpu(ele->seid);
8170
8171 if (printconfig)
8172 dev_info(&pf->pdev->dev,
8173 "type=%d seid=%d uplink=%d downlink=%d\n",
8174 element_type, seid, uplink_seid, downlink_seid);
8175
8176 switch (element_type) {
8177 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8178 pf->mac_seid = seid;
8179 break;
8180 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8181 /* Main VEB? */
8182 if (uplink_seid != pf->mac_seid)
8183 break;
8184 if (pf->lan_veb == I40E_NO_VEB) {
8185 int v;
8186
8187 /* find existing or else empty VEB */
8188 for (v = 0; v < I40E_MAX_VEB; v++) {
8189 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8190 pf->lan_veb = v;
8191 break;
8192 }
8193 }
8194 if (pf->lan_veb == I40E_NO_VEB) {
8195 v = i40e_veb_mem_alloc(pf);
8196 if (v < 0)
8197 break;
8198 pf->lan_veb = v;
8199 }
8200 }
8201
8202 pf->veb[pf->lan_veb]->seid = seid;
8203 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8204 pf->veb[pf->lan_veb]->pf = pf;
8205 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8206 break;
8207 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8208 if (num_reported != 1)
8209 break;
8210 /* This is immediately after a reset so we can assume this is
8211 * the PF's VSI
8212 */
8213 pf->mac_seid = uplink_seid;
8214 pf->pf_seid = downlink_seid;
8215 pf->main_vsi_seid = seid;
8216 if (printconfig)
8217 dev_info(&pf->pdev->dev,
8218 "pf_seid=%d main_vsi_seid=%d\n",
8219 pf->pf_seid, pf->main_vsi_seid);
8220 break;
8221 case I40E_SWITCH_ELEMENT_TYPE_PF:
8222 case I40E_SWITCH_ELEMENT_TYPE_VF:
8223 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8224 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8225 case I40E_SWITCH_ELEMENT_TYPE_PE:
8226 case I40E_SWITCH_ELEMENT_TYPE_PA:
8227 /* ignore these for now */
8228 break;
8229 default:
8230 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8231 element_type, seid);
8232 break;
8233 }
8234}
8235
8236/**
8237 * i40e_fetch_switch_configuration - Get switch config from firmware
8238 * @pf: board private structure
8239 * @printconfig: should we print the contents
8240 *
8241 * Get the current switch configuration from the device and
8242 * extract a few useful SEID values.
8243 **/
8244int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8245{
8246 struct i40e_aqc_get_switch_config_resp *sw_config;
8247 u16 next_seid = 0;
8248 int ret = 0;
8249 u8 *aq_buf;
8250 int i;
8251
8252 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8253 if (!aq_buf)
8254 return -ENOMEM;
8255
8256 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8257 do {
8258 u16 num_reported, num_total;
8259
8260 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8261 I40E_AQ_LARGE_BUF,
8262 &next_seid, NULL);
8263 if (ret) {
8264 dev_info(&pf->pdev->dev,
8265 "get switch config failed %d aq_err=%x\n",
8266 ret, pf->hw.aq.asq_last_status);
8267 kfree(aq_buf);
8268 return -ENOENT;
8269 }
8270
8271 num_reported = le16_to_cpu(sw_config->header.num_reported);
8272 num_total = le16_to_cpu(sw_config->header.num_total);
8273
8274 if (printconfig)
8275 dev_info(&pf->pdev->dev,
8276 "header: %d reported %d total\n",
8277 num_reported, num_total);
8278
41c445ff
JB		 8279 for (i = 0; i < num_reported; i++) {
8280 struct i40e_aqc_switch_config_element_resp *ele =
8281 &sw_config->element[i];
8282
8283 i40e_setup_pf_switch_element(pf, ele, num_reported,
8284 printconfig);
8285 }
8286 } while (next_seid != 0);
8287
8288 kfree(aq_buf);
8289 return ret;
8290}
8291
8292/**
8293 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8294 * @pf: board private structure
bc7d338f 8295 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8296 *
8297 * Returns 0 on success, negative value on failure
8298 **/
bc7d338f 8299static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 8300{
8301 int ret;
8302
8303 /* find out what's out there already */
8304 ret = i40e_fetch_switch_configuration(pf, false);
8305 if (ret) {
8306 dev_info(&pf->pdev->dev,
8307 "couldn't fetch switch config, err %d, aq_err %d\n",
8308 ret, pf->hw.aq.asq_last_status);
8309 return ret;
8310 }
8311 i40e_pf_reset_stats(pf);
8312
41c445ff 8313 /* first time setup */
bc7d338f 8314 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8315 struct i40e_vsi *vsi = NULL;
8316 u16 uplink_seid;
8317
8318 /* Set up the PF VSI associated with the PF's main VSI
8319 * that is already in the HW switch
8320 */
8321 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8322 uplink_seid = pf->veb[pf->lan_veb]->seid;
8323 else
8324 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8325 if (pf->lan_vsi == I40E_NO_VSI)
8326 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8327 else if (reinit)
8328 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8329 if (!vsi) {
8330 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8331 i40e_fdir_teardown(pf);
8332 return -EAGAIN;
8333 }
41c445ff
JB		 8334 } else {
8335 /* force a reset of TC and queue layout configurations */
8336 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8337 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8338 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8339 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8340 }
8341 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8342
cbf61325
ASJ		 8343 i40e_fdir_sb_setup(pf);
8344
41c445ff
JB		 8345 /* Setup static PF queue filter control settings */
8346 ret = i40e_setup_pf_filter_control(pf);
8347 if (ret) {
8348 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8349 ret);
8350 /* Failure here should not stop continuing other steps */
8351 }
8352
8353 /* enable RSS in the HW, even for only one queue, as the stack can use
8354 * the hash
8355 */
8356 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8357 i40e_config_rss(pf);
8358
8359 /* fill in link information and enable LSE reporting */
8109e123 8360 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 8361 i40e_link_event(pf);
8362
d52c20b7 8363 /* Initialize user-specific link properties */
41c445ff
JB		 8364 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8365 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 8366
beb0dff1
JK		 8367 i40e_ptp_init(pf);
8368
41c445ff
JB		 8369 return ret;
8370}
8371
41c445ff
JB		 8372/**
8373 * i40e_determine_queue_usage - Work out queue distribution
8374 * @pf: board private structure
8375 **/
8376static void i40e_determine_queue_usage(struct i40e_pf *pf)
8377{
41c445ff
JB		 8378 int queues_left;
8379
8380 pf->num_lan_qps = 0;
41c445ff
JB		 8381
8382 /* Find the max queues to be put into basic use. We'll always be
8383 * using TC0, whether or not DCB is running, and TC0 will get the
8384 * big RSS set.
8385 */
8386 queues_left = pf->hw.func_caps.num_tx_qp;
8387
cbf61325 8388 if ((queues_left == 1) ||
9aa7e935 8389 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8390 /* one qp for PF, no queues for anything else */
8391 queues_left = 0;
8392 pf->rss_size = pf->num_lan_qps = 1;
8393
8394 /* make sure all the fancies are disabled */
60ea5f83
JB		 8395 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8396 I40E_FLAG_FD_SB_ENABLED |
8397 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8398 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8399 I40E_FLAG_SRIOV_ENABLED |
8400 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8401 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8402 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8403 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8404 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8405 /* one qp for PF */
8406 pf->rss_size = pf->num_lan_qps = 1;
8407 queues_left -= pf->num_lan_qps;
8408
8409 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8410 I40E_FLAG_FD_SB_ENABLED |
8411 I40E_FLAG_FD_ATR_ENABLED |
8412 I40E_FLAG_DCB_ENABLED |
8413 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8414 } else {
cbf61325 8415 /* Not enough queues for all TCs */
4d9b6043 8416 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8417 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8418 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8419 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8420 }
8421 pf->num_lan_qps = pf->rss_size_max;
8422 queues_left -= pf->num_lan_qps;
8423 }
8424
8425 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8426 if (queues_left > 1) {
8427 queues_left -= 1; /* save 1 queue for FD */
8428 } else {
8429 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8430 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8431 }
41c445ff
JB		 8432 }
8433
8434 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8435 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8436 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8437 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8438 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8439 }
8440
8441 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8442 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8443 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8444 (queues_left / pf->num_vmdq_qps));
8445 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8446 }
8447
f8ff1464 8448 pf->queues_left = queues_left;
41c445ff
JB		 8449}
8450
8451/**
8452 * i40e_setup_pf_filter_control - Setup PF static filter control
8453 * @pf: PF to be setup
8454 *
8455 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8456 * settings. If PE/FCoE are enabled then it will also set the per PF
8457 * based filter sizes required for them. It also enables Flow director,
8458 * ethertype and macvlan type filter settings for the pf.
8459 *
8460 * Returns 0 on success, negative on failure
8461 **/
8462static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8463{
8464 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8465
8466 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8467
8468 /* Flow Director is enabled */
60ea5f83 8469 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8470 settings->enable_fdir = true;
8471
8472 /* Ethtype and MACVLAN filters enabled for PF */
8473 settings->enable_ethtype = true;
8474 settings->enable_macvlan = true;
8475
8476 if (i40e_set_filter_control(&pf->hw, settings))
8477 return -ENOENT;
8478
8479 return 0;
8480}
8481
0c22b3dd
JB		 8482#define INFO_STRING_LEN 255
8483static void i40e_print_features(struct i40e_pf *pf)
8484{
8485 struct i40e_hw *hw = &pf->hw;
8486 char *buf, *string;
8487
8488 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8489 if (!string) {
8490 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8491 return;
8492 }
8493
8494 buf = string;
8495
8496 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8497#ifdef CONFIG_PCI_IOV
8498 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8499#endif
8500 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8501 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8502
8503 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8504 buf += sprintf(buf, "RSS ");
0c22b3dd 8505 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8506 buf += sprintf(buf, "FD_ATR ");
8507 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8508 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8509 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8510 }
4d9b6043 8511 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8512 buf += sprintf(buf, "DCB ");
8513 if (pf->flags & I40E_FLAG_PTP)
8514 buf += sprintf(buf, "PTP ");
8515
8516 BUG_ON(buf > (string + INFO_STRING_LEN));
8517 dev_info(&pf->pdev->dev, "%s\n", string);
8518 kfree(string);
8519}
8520
41c445ff
JB		 8521/**
8522 * i40e_probe - Device initialization routine
8523 * @pdev: PCI device information struct
8524 * @ent: entry in i40e_pci_tbl
8525 *
8526 * i40e_probe initializes a pf identified by a pci_dev structure.
8527 * The OS initialization, configuring of the pf private structure,
8528 * and a hardware reset occur.
8529 *
8530 * Returns 0 on success, negative on failure
8531 **/
8532static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8533{
41c445ff
JB		 8534 struct i40e_pf *pf;
8535 struct i40e_hw *hw;
93cd765b 8536 static u16 pfs_found;
d4dfb81a 8537 u16 link_status;
41c445ff
JB		 8538 int err = 0;
8539 u32 len;
8a9eb7d3 8540 u32 i;
41c445ff
JB		 8541
8542 err = pci_enable_device_mem(pdev);
8543 if (err)
8544 return err;
8545
8546 /* set up for high or low dma */
6494294f 8547 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8548 if (err) {
e3e3bfdd
JS		 8549 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8550 if (err) {
8551 dev_err(&pdev->dev,
8552 "DMA configuration failed: 0x%x\n", err);
8553 goto err_dma;
8554 }
41c445ff
JB		 8555 }
8556
8557 /* set up pci connections */
8558 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8559 IORESOURCE_MEM), i40e_driver_name);
8560 if (err) {
8561 dev_info(&pdev->dev,
8562 "pci_request_selected_regions failed %d\n", err);
8563 goto err_pci_reg;
8564 }
8565
8566 pci_enable_pcie_error_reporting(pdev);
8567 pci_set_master(pdev);
8568
8569 /* Now that we have a PCI connection, we need to do the
8570 * low level device setup. This is primarily setting up
8571 * the Admin Queue structures and then querying for the
8572 * device's current profile information.
8573 */
8574 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8575 if (!pf) {
8576 err = -ENOMEM;
8577 goto err_pf_alloc;
8578 }
8579 pf->next_vsi = 0;
8580 pf->pdev = pdev;
8581 set_bit(__I40E_DOWN, &pf->state);
8582
8583 hw = &pf->hw;
8584 hw->back = pf;
8585 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8586 pci_resource_len(pdev, 0));
8587 if (!hw->hw_addr) {
8588 err = -EIO;
8589 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8590 (unsigned int)pci_resource_start(pdev, 0),
8591 (unsigned int)pci_resource_len(pdev, 0), err);
8592 goto err_ioremap;
8593 }
8594 hw->vendor_id = pdev->vendor;
8595 hw->device_id = pdev->device;
8596 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8597 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8598 hw->subsystem_device_id = pdev->subsystem_device;
8599 hw->bus.device = PCI_SLOT(pdev->devfn);
8600 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8601 pf->instance = pfs_found;
41c445ff 8602
7134f9ce
JB		 8603 /* do a special CORER for clearing PXE mode once at init */
8604 if (hw->revision_id == 0 &&
8605 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8606 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8607 i40e_flush(hw);
8608 msleep(200);
8609 pf->corer_count++;
8610
8611 i40e_clear_pxe_mode(hw);
8612 }
8613
41c445ff 8614 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 8615 i40e_clear_hw(hw);
41c445ff
JB		 8616 err = i40e_pf_reset(hw);
8617 if (err) {
8618 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8619 goto err_pf_reset;
8620 }
8621 pf->pfr_count++;
8622
8623 hw->aq.num_arq_entries = I40E_AQ_LEN;
8624 hw->aq.num_asq_entries = I40E_AQ_LEN;
8625 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8626 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8627 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8628 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8629 "%s-pf%d:misc",
8630 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8631
8632 err = i40e_init_shared_code(hw);
8633 if (err) {
8634 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8635 goto err_pf_reset;
8636 }
8637
d52c20b7
JB		 8638 /* set up a default setting for link flow control */
8639 pf->hw.fc.requested_mode = I40E_FC_NONE;
8640
41c445ff
JB		 8641 err = i40e_init_adminq(hw);
8642 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8643 if (err) {
8644 dev_info(&pdev->dev,
8645 "init_adminq failed: %d expecting API %02x.%02x\n",
8646 err,
8647 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8648 goto err_pf_reset;
8649 }
8650
278b6f62
SN		 8651 if (hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
8652 dev_info(&pdev->dev,
8653 "Note: FW API version %02x.%02x newer than expected %02x.%02x, recommend driver update.\n",
8654 hw->aq.api_maj_ver, hw->aq.api_min_ver,
8655 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8656
8657 if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
8658 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR-1))
8659 dev_info(&pdev->dev,
8660 "Note: FW API version %02x.%02x older than expected %02x.%02x, recommend nvm update.\n",
8661 hw->aq.api_maj_ver, hw->aq.api_min_ver,
8662 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8663
8664
4eb3f768
SN		 8665 i40e_verify_eeprom(pf);
8666
2c5fe33b
JB		 8667 /* Rev 0 hardware was never productized */
8668 if (hw->revision_id < 1)
8669 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
8670
6ff4ef86 8671 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8672 err = i40e_get_capabilities(pf);
8673 if (err)
8674 goto err_adminq_setup;
8675
8676 err = i40e_sw_init(pf);
8677 if (err) {
8678 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8679 goto err_sw_init;
8680 }
8681
8682 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8683 hw->func_caps.num_rx_qp,
8684 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8685 if (err) {
8686 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8687 goto err_init_lan_hmc;
8688 }
8689
8690 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8691 if (err) {
8692 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8693 err = -ENOENT;
8694 goto err_configure_lan_hmc;
8695 }
8696
8697 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8698 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8699 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8700 err = -EIO;
8701 goto err_mac_addr;
8702 }
8703 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 8704 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 8705 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
8706 if (is_valid_ether_addr(hw->mac.port_addr))
8707 pf->flags |= I40E_FLAG_PORT_ID_VALID;
41c445ff
JB		 8708
8709 pci_set_drvdata(pdev, pf);
8710 pci_save_state(pdev);
4e3b35b0
NP		 8711#ifdef CONFIG_I40E_DCB
8712 err = i40e_init_pf_dcb(pf);
8713 if (err) {
8714 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 8715 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 8716 /* Continue without DCB enabled */
4e3b35b0
NP		 8717 }
8718#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8719
8720 /* set up periodic task facility */
8721 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8722 pf->service_timer_period = HZ;
8723
8724 INIT_WORK(&pf->service_task, i40e_service_task);
8725 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8726 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8727 pf->link_check_timeout = jiffies;
8728
8e2773ae
SN		 8729 /* WoL defaults to disabled */
8730 pf->wol_en = false;
8731 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8732
41c445ff
JB		 8733 /* set up the main switch operations */
8734 i40e_determine_queue_usage(pf);
8735 i40e_init_interrupt_scheme(pf);
8736
505682cd
MW		 8737 /* The number of VSIs reported by the FW is the minimum guaranteed
8738 * to us; HW supports far more and we share the remaining pool with
8739 * the other PFs. We allocate space for more than the guarantee with
8740 * the understanding that we might not get them all later.
41c445ff 8741 */
505682cd
MW		 8742 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
8743 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
8744 else
8745 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
8746
8747 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
8748 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 8749 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8750 if (!pf->vsi) {
8751 err = -ENOMEM;
41c445ff 8752 goto err_switch_setup;
ed87ac09 8753 }
41c445ff 8754
bc7d338f 8755 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8756 if (err) {
8757 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8758 goto err_vsis;
8759 }
8a9eb7d3 8760 /* if FDIR VSI was set up, start it now */
505682cd 8761 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 8762 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8763 i40e_vsi_open(pf->vsi[i]);
8764 break;
8765 }
8766 }
41c445ff
JB		 8767
8768 /* The main driver is (mostly) up and happy. We need to set this state
8769 * before setting up the misc vector or we get a race and the vector
8770 * ends up disabled forever.
8771 */
8772 clear_bit(__I40E_DOWN, &pf->state);
8773
8774 /* In case of MSIX we are going to setup the misc vector right here
8775 * to handle admin queue events etc. In case of legacy and MSI
8776 * the misc functionality and queue processing is combined in
8777 * the same vector and that gets setup at open.
8778 */
8779 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8780 err = i40e_setup_misc_vector(pf);
8781 if (err) {
8782 dev_info(&pdev->dev,
8783 "setup of misc vector failed: %d\n", err);
8784 goto err_vsis;
8785 }
8786 }
8787
df805f62 8788#ifdef CONFIG_PCI_IOV
41c445ff
JB		 8789 /* prep for VF support */
8790 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8791 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8792 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8793 u32 val;
8794
8795 /* disable link interrupts for VFs */
8796 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8797 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8798 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8799 i40e_flush(hw);
4aeec010
MW		 8800
8801 if (pci_num_vf(pdev)) {
8802 dev_info(&pdev->dev,
8803 "Active VFs found, allocating resources.\n");
8804 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8805 if (err)
8806 dev_info(&pdev->dev,
8807 "Error %d allocating resources for existing VFs\n",
8808 err);
8809 }
41c445ff 8810 }
df805f62 8811#endif /* CONFIG_PCI_IOV */
41c445ff 8812
93cd765b
ASJ		 8813 pfs_found++;
8814
41c445ff
JB		 8815 i40e_dbg_pf_init(pf);
8816
8817 /* tell the firmware that we're starting */
44033fac 8818 i40e_send_version(pf);
41c445ff
JB		 8819
8820 /* since everything's happy, start the service_task timer */
8821 mod_timer(&pf->service_timer,
8822 round_jiffies(jiffies + pf->service_timer_period));
8823
d4dfb81a
CS		 8824 /* Get the negotiated link width and speed from PCI config space */
8825 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8826
8827 i40e_set_pci_config_data(hw, link_status);
8828
69bfb110 8829 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8830 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8831 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8832 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8833 "Unknown"),
8834 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8835 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8836 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8837 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8838 "Unknown"));
8839
8840 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8841 hw->bus.speed < i40e_bus_speed_8000) {
8842 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8843 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8844 }
8845
0c22b3dd
JB		 8846 /* print a string summarizing features */
8847 i40e_print_features(pf);
8848
41c445ff
JB		 8849 return 0;
8850
8851 /* Unwind what we've done if something failed in the setup */
8852err_vsis:
8853 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8854 i40e_clear_interrupt_scheme(pf);
8855 kfree(pf->vsi);
04b03013
SN		 8856err_switch_setup:
8857 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8858 del_timer_sync(&pf->service_timer);
8859err_mac_addr:
8860err_configure_lan_hmc:
8861 (void)i40e_shutdown_lan_hmc(hw);
8862err_init_lan_hmc:
8863 kfree(pf->qp_pile);
8864 kfree(pf->irq_pile);
8865err_sw_init:
8866err_adminq_setup:
8867 (void)i40e_shutdown_adminq(hw);
8868err_pf_reset:
8869 iounmap(hw->hw_addr);
8870err_ioremap:
8871 kfree(pf);
8872err_pf_alloc:
8873 pci_disable_pcie_error_reporting(pdev);
8874 pci_release_selected_regions(pdev,
8875 pci_select_bars(pdev, IORESOURCE_MEM));
8876err_pci_reg:
8877err_dma:
8878 pci_disable_device(pdev);
8879 return err;
8880}
8881
8882/**
8883 * i40e_remove - Device removal routine
8884 * @pdev: PCI device information struct
8885 *
8886 * i40e_remove is called by the PCI subsystem to alert the driver
8887 * that is should release a PCI device. This could be caused by a
8888 * Hot-Plug event, or because the driver is going to be removed from
8889 * memory.
8890 **/
8891static void i40e_remove(struct pci_dev *pdev)
8892{
8893 struct i40e_pf *pf = pci_get_drvdata(pdev);
8894 i40e_status ret_code;
41c445ff
JB		 8895 int i;
8896
8897 i40e_dbg_pf_exit(pf);
8898
beb0dff1
JK		 8899 i40e_ptp_stop(pf);
8900
41c445ff
JB		 8901 /* no more scheduling of any task */
8902 set_bit(__I40E_DOWN, &pf->state);
8903 del_timer_sync(&pf->service_timer);
8904 cancel_work_sync(&pf->service_task);
8905
eb2d80bc
MW		 8906 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8907 i40e_free_vfs(pf);
8908 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8909 }
8910
41c445ff
JB		 8911 i40e_fdir_teardown(pf);
8912
8913 /* If there is a switch structure or any orphans, remove them.
8914 * This will leave only the PF's VSI remaining.
8915 */
8916 for (i = 0; i < I40E_MAX_VEB; i++) {
8917 if (!pf->veb[i])
8918 continue;
8919
8920 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8921 pf->veb[i]->uplink_seid == 0)
8922 i40e_switch_branch_release(pf->veb[i]);
8923 }
8924
8925 /* Now we can shutdown the PF's VSI, just before we kill
8926 * adminq and hmc.
8927 */
8928 if (pf->vsi[pf->lan_vsi])
8929 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8930
8931 i40e_stop_misc_vector(pf);
8932 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8933 synchronize_irq(pf->msix_entries[0].vector);
8934 free_irq(pf->msix_entries[0].vector, pf);
8935 }
8936
8937 /* shutdown and destroy the HMC */
60442dea
SN		 8938 if (pf->hw.hmc.hmc_obj) {
8939 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8940 if (ret_code)
8941 dev_warn(&pdev->dev,
8942 "Failed to destroy the HMC resources: %d\n",
8943 ret_code);
8944 }
41c445ff
JB		 8945
8946 /* shutdown the adminq */
41c445ff
JB		 8947 ret_code = i40e_shutdown_adminq(&pf->hw);
8948 if (ret_code)
8949 dev_warn(&pdev->dev,
8950 "Failed to destroy the Admin Queue resources: %d\n",
8951 ret_code);
8952
8953 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8954 i40e_clear_interrupt_scheme(pf);
505682cd 8955 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8956 if (pf->vsi[i]) {
8957 i40e_vsi_clear_rings(pf->vsi[i]);
8958 i40e_vsi_clear(pf->vsi[i]);
8959 pf->vsi[i] = NULL;
8960 }
8961 }
8962
8963 for (i = 0; i < I40E_MAX_VEB; i++) {
8964 kfree(pf->veb[i]);
8965 pf->veb[i] = NULL;
8966 }
8967
8968 kfree(pf->qp_pile);
8969 kfree(pf->irq_pile);
41c445ff
JB		 8970 kfree(pf->vsi);
8971
41c445ff
JB		 8972 iounmap(pf->hw.hw_addr);
8973 kfree(pf);
8974 pci_release_selected_regions(pdev,
8975 pci_select_bars(pdev, IORESOURCE_MEM));
8976
8977 pci_disable_pcie_error_reporting(pdev);
8978 pci_disable_device(pdev);
8979}
8980
8981/**
8982 * i40e_pci_error_detected - warning that something funky happened in PCI land
8983 * @pdev: PCI device information struct
8984 *
8985 * Called to warn that something happened and the error handling steps
8986 * are in progress. Allows the driver to quiesce things, be ready for
8987 * remediation.
8988 **/
8989static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8990 enum pci_channel_state error)
8991{
8992 struct i40e_pf *pf = pci_get_drvdata(pdev);
8993
8994 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8995
8996 /* shutdown all operations */
9007bccd
SN		 8997 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8998 rtnl_lock();
8999 i40e_prep_for_reset(pf);
9000 rtnl_unlock();
9001 }
41c445ff
JB		 9002
9003 /* Request a slot reset */
9004 return PCI_ERS_RESULT_NEED_RESET;
9005}
9006
9007/**
9008 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9009 * @pdev: PCI device information struct
9010 *
9011 * Called to find if the driver can work with the device now that
9012 * the pci slot has been reset. If a basic connection seems good
9013 * (registers are readable and have sane content) then return a
9014 * happy little PCI_ERS_RESULT_xxx.
9015 **/
9016static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9017{
9018 struct i40e_pf *pf = pci_get_drvdata(pdev);
9019 pci_ers_result_t result;
9020 int err;
9021 u32 reg;
9022
9023 dev_info(&pdev->dev, "%s\n", __func__);
9024 if (pci_enable_device_mem(pdev)) {
9025 dev_info(&pdev->dev,
9026 "Cannot re-enable PCI device after reset.\n");
9027 result = PCI_ERS_RESULT_DISCONNECT;
9028 } else {
9029 pci_set_master(pdev);
9030 pci_restore_state(pdev);
9031 pci_save_state(pdev);
9032 pci_wake_from_d3(pdev, false);
9033
9034 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9035 if (reg == 0)
9036 result = PCI_ERS_RESULT_RECOVERED;
9037 else
9038 result = PCI_ERS_RESULT_DISCONNECT;
9039 }
9040
9041 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9042 if (err) {
9043 dev_info(&pdev->dev,
9044 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9045 err);
9046 /* non-fatal, continue */
9047 }
9048
9049 return result;
9050}
9051
9052/**
9053 * i40e_pci_error_resume - restart operations after PCI error recovery
9054 * @pdev: PCI device information struct
9055 *
9056 * Called to allow the driver to bring things back up after PCI error
9057 * and/or reset recovery has finished.
9058 **/
9059static void i40e_pci_error_resume(struct pci_dev *pdev)
9060{
9061 struct i40e_pf *pf = pci_get_drvdata(pdev);
9062
9063 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9064 if (test_bit(__I40E_SUSPENDED, &pf->state))
9065 return;
9066
9067 rtnl_lock();
41c445ff 9068 i40e_handle_reset_warning(pf);
9007bccd
SN		 9069 rtnl_lock();
9070}
9071
9072/**
9073 * i40e_shutdown - PCI callback for shutting down
9074 * @pdev: PCI device information struct
9075 **/
9076static void i40e_shutdown(struct pci_dev *pdev)
9077{
9078 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9079 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9080
9081 set_bit(__I40E_SUSPENDED, &pf->state);
9082 set_bit(__I40E_DOWN, &pf->state);
9083 rtnl_lock();
9084 i40e_prep_for_reset(pf);
9085 rtnl_unlock();
9086
8e2773ae
SN		 9087 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9088 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9089
9007bccd 9090 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9091 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9092 pci_set_power_state(pdev, PCI_D3hot);
9093 }
9094}
9095
9096#ifdef CONFIG_PM
9097/**
9098 * i40e_suspend - PCI callback for moving to D3
9099 * @pdev: PCI device information struct
9100 **/
9101static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9102{
9103 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9104 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9105
9106 set_bit(__I40E_SUSPENDED, &pf->state);
9107 set_bit(__I40E_DOWN, &pf->state);
9108 rtnl_lock();
9109 i40e_prep_for_reset(pf);
9110 rtnl_unlock();
9111
8e2773ae
SN		 9112 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9113 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9114
9115 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9116 pci_set_power_state(pdev, PCI_D3hot);
9117
9118 return 0;
41c445ff
JB		 9119}
9120
9007bccd
SN		 9121/**
9122 * i40e_resume - PCI callback for waking up from D3
9123 * @pdev: PCI device information struct
9124 **/
9125static int i40e_resume(struct pci_dev *pdev)
9126{
9127 struct i40e_pf *pf = pci_get_drvdata(pdev);
9128 u32 err;
9129
9130 pci_set_power_state(pdev, PCI_D0);
9131 pci_restore_state(pdev);
9132 /* pci_restore_state() clears dev->state_saves, so
9133 * call pci_save_state() again to restore it.
9134 */
9135 pci_save_state(pdev);
9136
9137 err = pci_enable_device_mem(pdev);
9138 if (err) {
9139 dev_err(&pdev->dev,
9140 "%s: Cannot enable PCI device from suspend\n",
9141 __func__);
9142 return err;
9143 }
9144 pci_set_master(pdev);
9145
9146 /* no wakeup events while running */
9147 pci_wake_from_d3(pdev, false);
9148
9149 /* handling the reset will rebuild the device state */
9150 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9151 clear_bit(__I40E_DOWN, &pf->state);
9152 rtnl_lock();
9153 i40e_reset_and_rebuild(pf, false);
9154 rtnl_unlock();
9155 }
9156
9157 return 0;
9158}
9159
9160#endif
41c445ff
JB		 9161static const struct pci_error_handlers i40e_err_handler = {
9162 .error_detected = i40e_pci_error_detected,
9163 .slot_reset = i40e_pci_error_slot_reset,
9164 .resume = i40e_pci_error_resume,
9165};
9166
9167static struct pci_driver i40e_driver = {
9168 .name = i40e_driver_name,
9169 .id_table = i40e_pci_tbl,
9170 .probe = i40e_probe,
9171 .remove = i40e_remove,
9007bccd
SN		 9172#ifdef CONFIG_PM
9173 .suspend = i40e_suspend,
9174 .resume = i40e_resume,
9175#endif
9176 .shutdown = i40e_shutdown,
41c445ff
JB		 9177 .err_handler = &i40e_err_handler,
9178 .sriov_configure = i40e_pci_sriov_configure,
9179};
9180
9181/**
9182 * i40e_init_module - Driver registration routine
9183 *
9184 * i40e_init_module is the first routine called when the driver is
9185 * loaded. All it does is register with the PCI subsystem.
9186 **/
9187static int __init i40e_init_module(void)
9188{
9189 pr_info("%s: %s - version %s\n", i40e_driver_name,
9190 i40e_driver_string, i40e_driver_version_str);
9191 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9192 i40e_dbg_init();
9193 return pci_register_driver(&i40e_driver);
9194}
9195module_init(i40e_init_module);
9196
9197/**
9198 * i40e_exit_module - Driver exit cleanup routine
9199 *
9200 * i40e_exit_module is called just before the driver is removed
9201 * from memory.
9202 **/
9203static void __exit i40e_exit_module(void)
9204{
9205 pci_unregister_driver(&i40e_driver);
9206 i40e_dbg_exit();
9207}
9208module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)