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i40e: call clear_pxe after adminq is initialized
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
21aa5675 41#define DRV_VERSION_BUILD 27
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
46static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
57
58/* i40e_pci_tbl - PCI Device ID Table
59 *
60 * Last entry must be all 0s
61 *
62 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
63 * Class, Class Mask, private data (not used) }
64 */
65static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
66 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
67 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
76 /* required last entry */
77 {0, }
78};
79MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
80
81#define I40E_MAX_VF_COUNT 128
82static int debug = -1;
83module_param(debug, int, 0);
84MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
85
86MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
87MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
88MODULE_LICENSE("GPL");
89MODULE_VERSION(DRV_VERSION);
90
91/**
92 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
93 * @hw: pointer to the HW structure
94 * @mem: ptr to mem struct to fill out
95 * @size: size of memory requested
96 * @alignment: what to align the allocation to
97 **/
98int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
99 u64 size, u32 alignment)
100{
101 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
102
103 mem->size = ALIGN(size, alignment);
104 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
105 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 106 if (!mem->va)
107 return -ENOMEM;
41c445ff 108
93bc73b8 109 return 0;
41c445ff
JB		 110}
111
112/**
113 * i40e_free_dma_mem_d - OS specific memory free for shared code
114 * @hw: pointer to the HW structure
115 * @mem: ptr to mem struct to free
116 **/
117int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
122 mem->va = NULL;
123 mem->pa = 0;
124 mem->size = 0;
125
126 return 0;
127}
128
129/**
130 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
131 * @hw: pointer to the HW structure
132 * @mem: ptr to mem struct to fill out
133 * @size: size of memory requested
134 **/
135int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
136 u32 size)
137{
138 mem->size = size;
139 mem->va = kzalloc(size, GFP_KERNEL);
140
93bc73b8
JB		 141 if (!mem->va)
142 return -ENOMEM;
41c445ff 143
93bc73b8 144 return 0;
41c445ff
JB		 145}
146
147/**
148 * i40e_free_virt_mem_d - OS specific memory free for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to free
151 **/
152int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
153{
154 /* it's ok to kfree a NULL pointer */
155 kfree(mem->va);
156 mem->va = NULL;
157 mem->size = 0;
158
159 return 0;
160}
161
162/**
163 * i40e_get_lump - find a lump of free generic resource
164 * @pf: board private structure
165 * @pile: the pile of resource to search
166 * @needed: the number of items needed
167 * @id: an owner id to stick on the items assigned
168 *
169 * Returns the base item index of the lump, or negative for error
170 *
171 * The search_hint trick and lack of advanced fit-finding only work
172 * because we're highly likely to have all the same size lump requests.
173 * Linear search time and any fragmentation should be minimal.
174 **/
175static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
176 u16 needed, u16 id)
177{
178 int ret = -ENOMEM;
ddf434ac 179 int i, j;
41c445ff
JB		 180
181 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
182 dev_info(&pf->pdev->dev,
183 "param err: pile=%p needed=%d id=0x%04x\n",
184 pile, needed, id);
185 return -EINVAL;
186 }
187
188 /* start the linear search with an imperfect hint */
189 i = pile->search_hint;
ddf434ac 190 while (i < pile->num_entries) {
41c445ff
JB		 191 /* skip already allocated entries */
192 if (pile->list[i] & I40E_PILE_VALID_BIT) {
193 i++;
194 continue;
195 }
196
197 /* do we have enough in this lump? */
198 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
199 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
200 break;
201 }
202
203 if (j == needed) {
204 /* there was enough, so assign it to the requestor */
205 for (j = 0; j < needed; j++)
206 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
207 ret = i;
208 pile->search_hint = i + j;
ddf434ac 209 break;
41c445ff
JB		 210 } else {
211 /* not enough, so skip over it and continue looking */
212 i += j;
213 }
214 }
215
216 return ret;
217}
218
219/**
220 * i40e_put_lump - return a lump of generic resource
221 * @pile: the pile of resource to search
222 * @index: the base item index
223 * @id: the owner id of the items assigned
224 *
225 * Returns the count of items in the lump
226 **/
227static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
228{
229 int valid_id = (id | I40E_PILE_VALID_BIT);
230 int count = 0;
231 int i;
232
233 if (!pile || index >= pile->num_entries)
234 return -EINVAL;
235
236 for (i = index;
237 i < pile->num_entries && pile->list[i] == valid_id;
238 i++) {
239 pile->list[i] = 0;
240 count++;
241 }
242
243 if (count && index < pile->search_hint)
244 pile->search_hint = index;
245
246 return count;
247}
248
249/**
250 * i40e_service_event_schedule - Schedule the service task to wake up
251 * @pf: board private structure
252 *
253 * If not already scheduled, this puts the task into the work queue
254 **/
255static void i40e_service_event_schedule(struct i40e_pf *pf)
256{
257 if (!test_bit(__I40E_DOWN, &pf->state) &&
258 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
259 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
260 schedule_work(&pf->service_task);
261}
262
263/**
264 * i40e_tx_timeout - Respond to a Tx Hang
265 * @netdev: network interface device structure
266 *
267 * If any port has noticed a Tx timeout, it is likely that the whole
268 * device is munged, not just the one netdev port, so go for the full
269 * reset.
270 **/
271static void i40e_tx_timeout(struct net_device *netdev)
272{
273 struct i40e_netdev_priv *np = netdev_priv(netdev);
274 struct i40e_vsi *vsi = np->vsi;
275 struct i40e_pf *pf = vsi->back;
276
277 pf->tx_timeout_count++;
278
279 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
280 pf->tx_timeout_recovery_level = 0;
281 pf->tx_timeout_last_recovery = jiffies;
282 netdev_info(netdev, "tx_timeout recovery level %d\n",
283 pf->tx_timeout_recovery_level);
284
285 switch (pf->tx_timeout_recovery_level) {
286 case 0:
287 /* disable and re-enable queues for the VSI */
288 if (in_interrupt()) {
289 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
290 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
291 } else {
292 i40e_vsi_reinit_locked(vsi);
293 }
294 break;
295 case 1:
296 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
297 break;
298 case 2:
299 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
300 break;
301 case 3:
302 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
303 break;
304 default:
305 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
306 i40e_down(vsi);
307 break;
308 }
309 i40e_service_event_schedule(pf);
310 pf->tx_timeout_recovery_level++;
311}
312
313/**
314 * i40e_release_rx_desc - Store the new tail and head values
315 * @rx_ring: ring to bump
316 * @val: new head index
317 **/
318static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
319{
320 rx_ring->next_to_use = val;
321
322 /* Force memory writes to complete before letting h/w
323 * know there are new descriptors to fetch. (Only
324 * applicable for weak-ordered memory model archs,
325 * such as IA-64).
326 */
327 wmb();
328 writel(val, rx_ring->tail);
329}
330
331/**
332 * i40e_get_vsi_stats_struct - Get System Network Statistics
333 * @vsi: the VSI we care about
334 *
335 * Returns the address of the device statistics structure.
336 * The statistics are actually updated from the service task.
337 **/
338struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
339{
340 return &vsi->net_stats;
341}
342
343/**
344 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
345 * @netdev: network interface device structure
346 *
347 * Returns the address of the device statistics structure.
348 * The statistics are actually updated from the service task.
349 **/
350static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
351 struct net_device *netdev,
980e9b11 352 struct rtnl_link_stats64 *stats)
41c445ff
JB		 353{
354 struct i40e_netdev_priv *np = netdev_priv(netdev);
355 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 356 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
357 int i;
358
143c9054 359
bc7d338f
ASJ		 360 if (test_bit(__I40E_DOWN, &vsi->state))
361 return stats;
362
3c325ced
JB		 363 if (!vsi->tx_rings)
364 return stats;
365
980e9b11
AD		 366 rcu_read_lock();
367 for (i = 0; i < vsi->num_queue_pairs; i++) {
368 struct i40e_ring *tx_ring, *rx_ring;
369 u64 bytes, packets;
370 unsigned int start;
371
372 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
373 if (!tx_ring)
374 continue;
375
376 do {
377 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
378 packets = tx_ring->stats.packets;
379 bytes = tx_ring->stats.bytes;
380 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
381
382 stats->tx_packets += packets;
383 stats->tx_bytes += bytes;
384 rx_ring = &tx_ring[1];
385
386 do {
387 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
388 packets = rx_ring->stats.packets;
389 bytes = rx_ring->stats.bytes;
390 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 391
980e9b11
AD		 392 stats->rx_packets += packets;
393 stats->rx_bytes += bytes;
394 }
395 rcu_read_unlock();
396
397 /* following stats updated by ixgbe_watchdog_task() */
398 stats->multicast = vsi_stats->multicast;
399 stats->tx_errors = vsi_stats->tx_errors;
400 stats->tx_dropped = vsi_stats->tx_dropped;
401 stats->rx_errors = vsi_stats->rx_errors;
402 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
403 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 404
980e9b11 405 return stats;
41c445ff
JB		 406}
407
408/**
409 * i40e_vsi_reset_stats - Resets all stats of the given vsi
410 * @vsi: the VSI to have its stats reset
411 **/
412void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
413{
414 struct rtnl_link_stats64 *ns;
415 int i;
416
417 if (!vsi)
418 return;
419
420 ns = i40e_get_vsi_stats_struct(vsi);
421 memset(ns, 0, sizeof(*ns));
422 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
423 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
424 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 425 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 426 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 427 memset(&vsi->rx_rings[i]->stats, 0 ,
428 sizeof(vsi->rx_rings[i]->stats));
429 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
430 sizeof(vsi->rx_rings[i]->rx_stats));
431 memset(&vsi->tx_rings[i]->stats, 0 ,
432 sizeof(vsi->tx_rings[i]->stats));
433 memset(&vsi->tx_rings[i]->tx_stats, 0,
434 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 435 }
8e9dca53 436 }
41c445ff
JB		 437 vsi->stat_offsets_loaded = false;
438}
439
440/**
441 * i40e_pf_reset_stats - Reset all of the stats for the given pf
442 * @pf: the PF to be reset
443 **/
444void i40e_pf_reset_stats(struct i40e_pf *pf)
445{
446 memset(&pf->stats, 0, sizeof(pf->stats));
447 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
448 pf->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_stat_update48 - read and update a 48 bit stat from the chip
453 * @hw: ptr to the hardware info
454 * @hireg: the high 32 bit reg to read
455 * @loreg: the low 32 bit reg to read
456 * @offset_loaded: has the initial offset been loaded yet
457 * @offset: ptr to current offset value
458 * @stat: ptr to the stat
459 *
460 * Since the device stats are not reset at PFReset, they likely will not
461 * be zeroed when the driver starts. We'll save the first values read
462 * and use them as offsets to be subtracted from the raw values in order
463 * to report stats that count from zero. In the process, we also manage
464 * the potential roll-over.
465 **/
466static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
467 bool offset_loaded, u64 *offset, u64 *stat)
468{
469 u64 new_data;
470
471 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
472 new_data = rd32(hw, loreg);
473 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
474 } else {
475 new_data = rd64(hw, loreg);
476 }
477 if (!offset_loaded)
478 *offset = new_data;
479 if (likely(new_data >= *offset))
480 *stat = new_data - *offset;
481 else
482 *stat = (new_data + ((u64)1 << 48)) - *offset;
483 *stat &= 0xFFFFFFFFFFFFULL;
484}
485
486/**
487 * i40e_stat_update32 - read and update a 32 bit stat from the chip
488 * @hw: ptr to the hardware info
489 * @reg: the hw reg to read
490 * @offset_loaded: has the initial offset been loaded yet
491 * @offset: ptr to current offset value
492 * @stat: ptr to the stat
493 **/
494static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
495 bool offset_loaded, u64 *offset, u64 *stat)
496{
497 u32 new_data;
498
499 new_data = rd32(hw, reg);
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = (u32)(new_data - *offset);
504 else
505 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
506}
507
508/**
509 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
510 * @vsi: the VSI to be updated
511 **/
512void i40e_update_eth_stats(struct i40e_vsi *vsi)
513{
514 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
515 struct i40e_pf *pf = vsi->back;
516 struct i40e_hw *hw = &pf->hw;
517 struct i40e_eth_stats *oes;
518 struct i40e_eth_stats *es; /* device's eth stats */
519
520 es = &vsi->eth_stats;
521 oes = &vsi->eth_stats_offsets;
522
523 /* Gather up the stats that the hw collects */
524 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
525 vsi->stat_offsets_loaded,
526 &oes->tx_errors, &es->tx_errors);
527 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->rx_discards, &es->rx_discards);
530
531 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
532 I40E_GLV_GORCL(stat_idx),
533 vsi->stat_offsets_loaded,
534 &oes->rx_bytes, &es->rx_bytes);
535 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
536 I40E_GLV_UPRCL(stat_idx),
537 vsi->stat_offsets_loaded,
538 &oes->rx_unicast, &es->rx_unicast);
539 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
540 I40E_GLV_MPRCL(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_multicast, &es->rx_multicast);
543 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
544 I40E_GLV_BPRCL(stat_idx),
545 vsi->stat_offsets_loaded,
546 &oes->rx_broadcast, &es->rx_broadcast);
547
548 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
549 I40E_GLV_GOTCL(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->tx_bytes, &es->tx_bytes);
552 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
553 I40E_GLV_UPTCL(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->tx_unicast, &es->tx_unicast);
556 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
557 I40E_GLV_MPTCL(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_multicast, &es->tx_multicast);
560 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
561 I40E_GLV_BPTCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->tx_broadcast, &es->tx_broadcast);
564 vsi->stat_offsets_loaded = true;
565}
566
567/**
568 * i40e_update_veb_stats - Update Switch component statistics
569 * @veb: the VEB being updated
570 **/
571static void i40e_update_veb_stats(struct i40e_veb *veb)
572{
573 struct i40e_pf *pf = veb->pf;
574 struct i40e_hw *hw = &pf->hw;
575 struct i40e_eth_stats *oes;
576 struct i40e_eth_stats *es; /* device's eth stats */
577 int idx = 0;
578
579 idx = veb->stats_idx;
580 es = &veb->stats;
581 oes = &veb->stats_offsets;
582
583 /* Gather up the stats that the hw collects */
584 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
585 veb->stat_offsets_loaded,
586 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 587 if (hw->revision_id > 0)
588 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
589 veb->stat_offsets_loaded,
590 &oes->rx_unknown_protocol,
591 &es->rx_unknown_protocol);
41c445ff
JB		 592 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
593 veb->stat_offsets_loaded,
594 &oes->rx_bytes, &es->rx_bytes);
595 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unicast, &es->rx_unicast);
598 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_multicast, &es->rx_multicast);
601 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_broadcast, &es->rx_broadcast);
604
605 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->tx_bytes, &es->tx_bytes);
608 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_unicast, &es->tx_unicast);
611 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_multicast, &es->tx_multicast);
614 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_broadcast, &es->tx_broadcast);
617 veb->stat_offsets_loaded = true;
618}
619
620/**
621 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
622 * @pf: the corresponding PF
623 *
624 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
625 **/
626static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
627{
628 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
629 struct i40e_hw_port_stats *nsd = &pf->stats;
630 struct i40e_hw *hw = &pf->hw;
631 u64 xoff = 0;
632 u16 i, v;
633
634 if ((hw->fc.current_mode != I40E_FC_FULL) &&
635 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
636 return;
637
638 xoff = nsd->link_xoff_rx;
639 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
640 pf->stat_offsets_loaded,
641 &osd->link_xoff_rx, &nsd->link_xoff_rx);
642
643 /* No new LFC xoff rx */
644 if (!(nsd->link_xoff_rx - xoff))
645 return;
646
647 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
648 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
649 struct i40e_vsi *vsi = pf->vsi[v];
650
651 if (!vsi)
652 continue;
653
654 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 655 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 656 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
657 }
658 }
659}
660
661/**
662 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
663 * @pf: the corresponding PF
664 *
665 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
666 **/
667static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
668{
669 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
670 struct i40e_hw_port_stats *nsd = &pf->stats;
671 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
672 struct i40e_dcbx_config *dcb_cfg;
673 struct i40e_hw *hw = &pf->hw;
674 u16 i, v;
675 u8 tc;
676
677 dcb_cfg = &hw->local_dcbx_config;
678
679 /* See if DCB enabled with PFC TC */
680 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
681 !(dcb_cfg->pfc.pfcenable)) {
682 i40e_update_link_xoff_rx(pf);
683 return;
684 }
685
686 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
687 u64 prio_xoff = nsd->priority_xoff_rx[i];
688 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
689 pf->stat_offsets_loaded,
690 &osd->priority_xoff_rx[i],
691 &nsd->priority_xoff_rx[i]);
692
693 /* No new PFC xoff rx */
694 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
695 continue;
696 /* Get the TC for given priority */
697 tc = dcb_cfg->etscfg.prioritytable[i];
698 xoff[tc] = true;
699 }
700
701 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
702 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
703 struct i40e_vsi *vsi = pf->vsi[v];
704
705 if (!vsi)
706 continue;
707
708 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 709 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 710
711 tc = ring->dcb_tc;
712 if (xoff[tc])
713 clear_bit(__I40E_HANG_CHECK_ARMED,
714 &ring->state);
715 }
716 }
717}
718
719/**
720 * i40e_update_stats - Update the board statistics counters.
721 * @vsi: the VSI to be updated
722 *
723 * There are a few instances where we store the same stat in a
724 * couple of different structs. This is partly because we have
725 * the netdev stats that need to be filled out, which is slightly
726 * different from the "eth_stats" defined by the chip and used in
727 * VF communications. We sort it all out here in a central place.
728 **/
729void i40e_update_stats(struct i40e_vsi *vsi)
730{
731 struct i40e_pf *pf = vsi->back;
732 struct i40e_hw *hw = &pf->hw;
733 struct rtnl_link_stats64 *ons;
734 struct rtnl_link_stats64 *ns; /* netdev stats */
735 struct i40e_eth_stats *oes;
736 struct i40e_eth_stats *es; /* device's eth stats */
737 u32 tx_restart, tx_busy;
738 u32 rx_page, rx_buf;
739 u64 rx_p, rx_b;
740 u64 tx_p, tx_b;
741 int i;
742 u16 q;
743
744 if (test_bit(__I40E_DOWN, &vsi->state) ||
745 test_bit(__I40E_CONFIG_BUSY, &pf->state))
746 return;
747
748 ns = i40e_get_vsi_stats_struct(vsi);
749 ons = &vsi->net_stats_offsets;
750 es = &vsi->eth_stats;
751 oes = &vsi->eth_stats_offsets;
752
753 /* Gather up the netdev and vsi stats that the driver collects
754 * on the fly during packet processing
755 */
756 rx_b = rx_p = 0;
757 tx_b = tx_p = 0;
758 tx_restart = tx_busy = 0;
759 rx_page = 0;
760 rx_buf = 0;
980e9b11 761 rcu_read_lock();
41c445ff
JB		 762 for (q = 0; q < vsi->num_queue_pairs; q++) {
763 struct i40e_ring *p;
980e9b11
AD		 764 u64 bytes, packets;
765 unsigned int start;
766
767 /* locate Tx ring */
768 p = ACCESS_ONCE(vsi->tx_rings[q]);
769
770 do {
771 start = u64_stats_fetch_begin_bh(&p->syncp);
772 packets = p->stats.packets;
773 bytes = p->stats.bytes;
774 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
775 tx_b += bytes;
776 tx_p += packets;
777 tx_restart += p->tx_stats.restart_queue;
778 tx_busy += p->tx_stats.tx_busy;
41c445ff 779
980e9b11
AD		 780 /* Rx queue is part of the same block as Tx queue */
781 p = &p[1];
782 do {
783 start = u64_stats_fetch_begin_bh(&p->syncp);
784 packets = p->stats.packets;
785 bytes = p->stats.bytes;
786 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
787 rx_b += bytes;
788 rx_p += packets;
420136cc
MW		 789 rx_buf += p->rx_stats.alloc_buff_failed;
790 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 791 }
980e9b11 792 rcu_read_unlock();
41c445ff
JB		 793 vsi->tx_restart = tx_restart;
794 vsi->tx_busy = tx_busy;
795 vsi->rx_page_failed = rx_page;
796 vsi->rx_buf_failed = rx_buf;
797
798 ns->rx_packets = rx_p;
799 ns->rx_bytes = rx_b;
800 ns->tx_packets = tx_p;
801 ns->tx_bytes = tx_b;
802
803 i40e_update_eth_stats(vsi);
804 /* update netdev stats from eth stats */
805 ons->rx_errors = oes->rx_errors;
806 ns->rx_errors = es->rx_errors;
807 ons->tx_errors = oes->tx_errors;
808 ns->tx_errors = es->tx_errors;
809 ons->multicast = oes->rx_multicast;
810 ns->multicast = es->rx_multicast;
811 ons->tx_dropped = oes->tx_discards;
812 ns->tx_dropped = es->tx_discards;
813
814 /* Get the port data only if this is the main PF VSI */
815 if (vsi == pf->vsi[pf->lan_vsi]) {
816 struct i40e_hw_port_stats *nsd = &pf->stats;
817 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
818
819 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
820 I40E_GLPRT_GORCL(hw->port),
821 pf->stat_offsets_loaded,
822 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
823 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
824 I40E_GLPRT_GOTCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
827 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
828 pf->stat_offsets_loaded,
829 &osd->eth.rx_discards,
830 &nsd->eth.rx_discards);
831 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.tx_discards,
834 &nsd->eth.tx_discards);
835 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
836 I40E_GLPRT_MPRCL(hw->port),
837 pf->stat_offsets_loaded,
838 &osd->eth.rx_multicast,
839 &nsd->eth.rx_multicast);
840
841 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
842 pf->stat_offsets_loaded,
843 &osd->tx_dropped_link_down,
844 &nsd->tx_dropped_link_down);
845
846 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->crc_errors, &nsd->crc_errors);
849 ns->rx_crc_errors = nsd->crc_errors;
850
851 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->illegal_bytes, &nsd->illegal_bytes);
854 ns->rx_errors = nsd->crc_errors
855 + nsd->illegal_bytes;
856
857 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->mac_local_faults,
860 &nsd->mac_local_faults);
861 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_remote_faults,
864 &nsd->mac_remote_faults);
865
866 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
867 pf->stat_offsets_loaded,
868 &osd->rx_length_errors,
869 &nsd->rx_length_errors);
870 ns->rx_length_errors = nsd->rx_length_errors;
871
872 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->link_xon_rx, &nsd->link_xon_rx);
875 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
876 pf->stat_offsets_loaded,
877 &osd->link_xon_tx, &nsd->link_xon_tx);
878 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
879 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xoff_tx, &nsd->link_xoff_tx);
882
883 for (i = 0; i < 8; i++) {
884 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
885 pf->stat_offsets_loaded,
886 &osd->priority_xon_rx[i],
887 &nsd->priority_xon_rx[i]);
888 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_tx[i],
891 &nsd->priority_xon_tx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xoff_tx[i],
895 &nsd->priority_xoff_tx[i]);
896 i40e_stat_update32(hw,
897 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
898 pf->stat_offsets_loaded,
899 &osd->priority_xon_2_xoff[i],
900 &nsd->priority_xon_2_xoff[i]);
901 }
902
903 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
904 I40E_GLPRT_PRC64L(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->rx_size_64, &nsd->rx_size_64);
907 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
908 I40E_GLPRT_PRC127L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_127, &nsd->rx_size_127);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
912 I40E_GLPRT_PRC255L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_255, &nsd->rx_size_255);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
916 I40E_GLPRT_PRC511L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_511, &nsd->rx_size_511);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
920 I40E_GLPRT_PRC1023L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_1023, &nsd->rx_size_1023);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
924 I40E_GLPRT_PRC1522L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1522, &nsd->rx_size_1522);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
928 I40E_GLPRT_PRC9522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_big, &nsd->rx_size_big);
931
932 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
933 I40E_GLPRT_PTC64L(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->tx_size_64, &nsd->tx_size_64);
936 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
937 I40E_GLPRT_PTC127L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_127, &nsd->tx_size_127);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
941 I40E_GLPRT_PTC255L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_255, &nsd->tx_size_255);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
945 I40E_GLPRT_PTC511L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_511, &nsd->tx_size_511);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
949 I40E_GLPRT_PTC1023L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_1023, &nsd->tx_size_1023);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
953 I40E_GLPRT_PTC1522L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1522, &nsd->tx_size_1522);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
957 I40E_GLPRT_PTC9522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_big, &nsd->tx_size_big);
960
961 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->rx_undersize, &nsd->rx_undersize);
964 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_fragments, &nsd->rx_fragments);
967 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->rx_oversize, &nsd->rx_oversize);
970 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_jabber, &nsd->rx_jabber);
973 }
974
975 pf->stat_offsets_loaded = true;
976}
977
978/**
979 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
980 * @vsi: the VSI to be searched
981 * @macaddr: the MAC address
982 * @vlan: the vlan
983 * @is_vf: make sure its a vf filter, else doesn't matter
984 * @is_netdev: make sure its a netdev filter, else doesn't matter
985 *
986 * Returns ptr to the filter object or NULL
987 **/
988static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
989 u8 *macaddr, s16 vlan,
990 bool is_vf, bool is_netdev)
991{
992 struct i40e_mac_filter *f;
993
994 if (!vsi || !macaddr)
995 return NULL;
996
997 list_for_each_entry(f, &vsi->mac_filter_list, list) {
998 if ((ether_addr_equal(macaddr, f->macaddr)) &&
999 (vlan == f->vlan) &&
1000 (!is_vf || f->is_vf) &&
1001 (!is_netdev || f->is_netdev))
1002 return f;
1003 }
1004 return NULL;
1005}
1006
1007/**
1008 * i40e_find_mac - Find a mac addr in the macvlan filters list
1009 * @vsi: the VSI to be searched
1010 * @macaddr: the MAC address we are searching for
1011 * @is_vf: make sure its a vf filter, else doesn't matter
1012 * @is_netdev: make sure its a netdev filter, else doesn't matter
1013 *
1014 * Returns the first filter with the provided MAC address or NULL if
1015 * MAC address was not found
1016 **/
1017struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1018 bool is_vf, bool is_netdev)
1019{
1020 struct i40e_mac_filter *f;
1021
1022 if (!vsi || !macaddr)
1023 return NULL;
1024
1025 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1026 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1027 (!is_vf || f->is_vf) &&
1028 (!is_netdev || f->is_netdev))
1029 return f;
1030 }
1031 return NULL;
1032}
1033
1034/**
1035 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1036 * @vsi: the VSI to be searched
1037 *
1038 * Returns true if VSI is in vlan mode or false otherwise
1039 **/
1040bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1041{
1042 struct i40e_mac_filter *f;
1043
1044 /* Only -1 for all the filters denotes not in vlan mode
1045 * so we have to go through all the list in order to make sure
1046 */
1047 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1048 if (f->vlan >= 0)
1049 return true;
1050 }
1051
1052 return false;
1053}
1054
1055/**
1056 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1057 * @vsi: the VSI to be searched
1058 * @macaddr: the mac address to be filtered
1059 * @is_vf: true if it is a vf
1060 * @is_netdev: true if it is a netdev
1061 *
1062 * Goes through all the macvlan filters and adds a
1063 * macvlan filter for each unique vlan that already exists
1064 *
1065 * Returns first filter found on success, else NULL
1066 **/
1067struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1068 bool is_vf, bool is_netdev)
1069{
1070 struct i40e_mac_filter *f;
1071
1072 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1073 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1074 is_vf, is_netdev)) {
1075 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev))
1077 return NULL;
1078 }
1079 }
1080
1081 return list_first_entry_or_null(&vsi->mac_filter_list,
1082 struct i40e_mac_filter, list);
1083}
1084
1085/**
1086 * i40e_add_filter - Add a mac/vlan filter to the VSI
1087 * @vsi: the VSI to be searched
1088 * @macaddr: the MAC address
1089 * @vlan: the vlan
1090 * @is_vf: make sure its a vf filter, else doesn't matter
1091 * @is_netdev: make sure its a netdev filter, else doesn't matter
1092 *
1093 * Returns ptr to the filter object or NULL when no memory available.
1094 **/
1095struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1096 u8 *macaddr, s16 vlan,
1097 bool is_vf, bool is_netdev)
1098{
1099 struct i40e_mac_filter *f;
1100
1101 if (!vsi || !macaddr)
1102 return NULL;
1103
1104 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1105 if (!f) {
1106 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1107 if (!f)
1108 goto add_filter_out;
1109
1110 memcpy(f->macaddr, macaddr, ETH_ALEN);
1111 f->vlan = vlan;
1112 f->changed = true;
1113
1114 INIT_LIST_HEAD(&f->list);
1115 list_add(&f->list, &vsi->mac_filter_list);
1116 }
1117
1118 /* increment counter and add a new flag if needed */
1119 if (is_vf) {
1120 if (!f->is_vf) {
1121 f->is_vf = true;
1122 f->counter++;
1123 }
1124 } else if (is_netdev) {
1125 if (!f->is_netdev) {
1126 f->is_netdev = true;
1127 f->counter++;
1128 }
1129 } else {
1130 f->counter++;
1131 }
1132
1133 /* changed tells sync_filters_subtask to
1134 * push the filter down to the firmware
1135 */
1136 if (f->changed) {
1137 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1138 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1139 }
1140
1141add_filter_out:
1142 return f;
1143}
1144
1145/**
1146 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
1150 * @is_vf: make sure it's a vf filter, else doesn't matter
1151 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1152 **/
1153void i40e_del_filter(struct i40e_vsi *vsi,
1154 u8 *macaddr, s16 vlan,
1155 bool is_vf, bool is_netdev)
1156{
1157 struct i40e_mac_filter *f;
1158
1159 if (!vsi || !macaddr)
1160 return;
1161
1162 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1163 if (!f || f->counter == 0)
1164 return;
1165
1166 if (is_vf) {
1167 if (f->is_vf) {
1168 f->is_vf = false;
1169 f->counter--;
1170 }
1171 } else if (is_netdev) {
1172 if (f->is_netdev) {
1173 f->is_netdev = false;
1174 f->counter--;
1175 }
1176 } else {
1177 /* make sure we don't remove a filter in use by vf or netdev */
1178 int min_f = 0;
1179 min_f += (f->is_vf ? 1 : 0);
1180 min_f += (f->is_netdev ? 1 : 0);
1181
1182 if (f->counter > min_f)
1183 f->counter--;
1184 }
1185
1186 /* counter == 0 tells sync_filters_subtask to
1187 * remove the filter from the firmware's list
1188 */
1189 if (f->counter == 0) {
1190 f->changed = true;
1191 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1192 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1193 }
1194}
1195
1196/**
1197 * i40e_set_mac - NDO callback to set mac address
1198 * @netdev: network interface device structure
1199 * @p: pointer to an address structure
1200 *
1201 * Returns 0 on success, negative on failure
1202 **/
1203static int i40e_set_mac(struct net_device *netdev, void *p)
1204{
1205 struct i40e_netdev_priv *np = netdev_priv(netdev);
1206 struct i40e_vsi *vsi = np->vsi;
1207 struct sockaddr *addr = p;
1208 struct i40e_mac_filter *f;
1209
1210 if (!is_valid_ether_addr(addr->sa_data))
1211 return -EADDRNOTAVAIL;
1212
1213 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1214
1215 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1216 return 0;
1217
80f6428f
ASJ		 1218 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1219 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1220 return -EADDRNOTAVAIL;
1221
41c445ff
JB		 1222 if (vsi->type == I40E_VSI_MAIN) {
1223 i40e_status ret;
1224 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1225 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1226 addr->sa_data, NULL);
1227 if (ret) {
1228 netdev_info(netdev,
1229 "Addr change for Main VSI failed: %d\n",
1230 ret);
1231 return -EADDRNOTAVAIL;
1232 }
1233
1234 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1235 }
1236
1237 /* In order to be sure to not drop any packets, add the new address
1238 * then delete the old one.
1239 */
1240 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1241 if (!f)
1242 return -ENOMEM;
1243
1244 i40e_sync_vsi_filters(vsi);
1245 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1246 i40e_sync_vsi_filters(vsi);
1247
1248 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1249
1250 return 0;
1251}
1252
1253/**
1254 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1255 * @vsi: the VSI being setup
1256 * @ctxt: VSI context structure
1257 * @enabled_tc: Enabled TCs bitmap
1258 * @is_add: True if called before Add VSI
1259 *
1260 * Setup VSI queue mapping for enabled traffic classes.
1261 **/
1262static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1263 struct i40e_vsi_context *ctxt,
1264 u8 enabled_tc,
1265 bool is_add)
1266{
1267 struct i40e_pf *pf = vsi->back;
1268 u16 sections = 0;
1269 u8 netdev_tc = 0;
1270 u16 numtc = 0;
1271 u16 qcount;
1272 u8 offset;
1273 u16 qmap;
1274 int i;
1275
1276 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1277 offset = 0;
1278
1279 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1280 /* Find numtc from enabled TC bitmap */
1281 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1282 if (enabled_tc & (1 << i)) /* TC is enabled */
1283 numtc++;
1284 }
1285 if (!numtc) {
1286 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1287 numtc = 1;
1288 }
1289 } else {
1290 /* At least TC0 is enabled in case of non-DCB case */
1291 numtc = 1;
1292 }
1293
1294 vsi->tc_config.numtc = numtc;
1295 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1296
1297 /* Setup queue offset/count for all TCs for given VSI */
1298 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1299 /* See if the given TC is enabled for the given VSI */
1300 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1301 int pow, num_qps;
1302
1303 vsi->tc_config.tc_info[i].qoffset = offset;
1304 switch (vsi->type) {
1305 case I40E_VSI_MAIN:
1306 if (i == 0)
1307 qcount = pf->rss_size;
1308 else
1309 qcount = pf->num_tc_qps;
1310 vsi->tc_config.tc_info[i].qcount = qcount;
1311 break;
1312 case I40E_VSI_FDIR:
1313 case I40E_VSI_SRIOV:
1314 case I40E_VSI_VMDQ2:
1315 default:
1316 qcount = vsi->alloc_queue_pairs;
1317 vsi->tc_config.tc_info[i].qcount = qcount;
1318 WARN_ON(i != 0);
1319 break;
1320 }
1321
1322 /* find the power-of-2 of the number of queue pairs */
1323 num_qps = vsi->tc_config.tc_info[i].qcount;
1324 pow = 0;
1325 while (num_qps &&
1326 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1327 pow++;
1328 num_qps >>= 1;
1329 }
1330
1331 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1332 qmap =
1333 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1334 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1335
1336 offset += vsi->tc_config.tc_info[i].qcount;
1337 } else {
1338 /* TC is not enabled so set the offset to
1339 * default queue and allocate one queue
1340 * for the given TC.
1341 */
1342 vsi->tc_config.tc_info[i].qoffset = 0;
1343 vsi->tc_config.tc_info[i].qcount = 1;
1344 vsi->tc_config.tc_info[i].netdev_tc = 0;
1345
1346 qmap = 0;
1347 }
1348 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1349 }
1350
1351 /* Set actual Tx/Rx queue pairs */
1352 vsi->num_queue_pairs = offset;
1353
1354 /* Scheduler section valid can only be set for ADD VSI */
1355 if (is_add) {
1356 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1357
1358 ctxt->info.up_enable_bits = enabled_tc;
1359 }
1360 if (vsi->type == I40E_VSI_SRIOV) {
1361 ctxt->info.mapping_flags |=
1362 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1363 for (i = 0; i < vsi->num_queue_pairs; i++)
1364 ctxt->info.queue_mapping[i] =
1365 cpu_to_le16(vsi->base_queue + i);
1366 } else {
1367 ctxt->info.mapping_flags |=
1368 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1369 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1370 }
1371 ctxt->info.valid_sections |= cpu_to_le16(sections);
1372}
1373
1374/**
1375 * i40e_set_rx_mode - NDO callback to set the netdev filters
1376 * @netdev: network interface device structure
1377 **/
1378static void i40e_set_rx_mode(struct net_device *netdev)
1379{
1380 struct i40e_netdev_priv *np = netdev_priv(netdev);
1381 struct i40e_mac_filter *f, *ftmp;
1382 struct i40e_vsi *vsi = np->vsi;
1383 struct netdev_hw_addr *uca;
1384 struct netdev_hw_addr *mca;
1385 struct netdev_hw_addr *ha;
1386
1387 /* add addr if not already in the filter list */
1388 netdev_for_each_uc_addr(uca, netdev) {
1389 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1390 if (i40e_is_vsi_in_vlan(vsi))
1391 i40e_put_mac_in_vlan(vsi, uca->addr,
1392 false, true);
1393 else
1394 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1395 false, true);
1396 }
1397 }
1398
1399 netdev_for_each_mc_addr(mca, netdev) {
1400 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1401 if (i40e_is_vsi_in_vlan(vsi))
1402 i40e_put_mac_in_vlan(vsi, mca->addr,
1403 false, true);
1404 else
1405 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1406 false, true);
1407 }
1408 }
1409
1410 /* remove filter if not in netdev list */
1411 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1412 bool found = false;
1413
1414 if (!f->is_netdev)
1415 continue;
1416
1417 if (is_multicast_ether_addr(f->macaddr)) {
1418 netdev_for_each_mc_addr(mca, netdev) {
1419 if (ether_addr_equal(mca->addr, f->macaddr)) {
1420 found = true;
1421 break;
1422 }
1423 }
1424 } else {
1425 netdev_for_each_uc_addr(uca, netdev) {
1426 if (ether_addr_equal(uca->addr, f->macaddr)) {
1427 found = true;
1428 break;
1429 }
1430 }
1431
1432 for_each_dev_addr(netdev, ha) {
1433 if (ether_addr_equal(ha->addr, f->macaddr)) {
1434 found = true;
1435 break;
1436 }
1437 }
1438 }
1439 if (!found)
1440 i40e_del_filter(
1441 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1442 }
1443
1444 /* check for other flag changes */
1445 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1446 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1447 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1448 }
1449}
1450
1451/**
1452 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1453 * @vsi: ptr to the VSI
1454 *
1455 * Push any outstanding VSI filter changes through the AdminQ.
1456 *
1457 * Returns 0 or error value
1458 **/
1459int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1460{
1461 struct i40e_mac_filter *f, *ftmp;
1462 bool promisc_forced_on = false;
1463 bool add_happened = false;
1464 int filter_list_len = 0;
1465 u32 changed_flags = 0;
dcae29be 1466 i40e_status aq_ret = 0;
41c445ff
JB		 1467 struct i40e_pf *pf;
1468 int num_add = 0;
1469 int num_del = 0;
1470 u16 cmd_flags;
1471
1472 /* empty array typed pointers, kcalloc later */
1473 struct i40e_aqc_add_macvlan_element_data *add_list;
1474 struct i40e_aqc_remove_macvlan_element_data *del_list;
1475
1476 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1477 usleep_range(1000, 2000);
1478 pf = vsi->back;
1479
1480 if (vsi->netdev) {
1481 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1482 vsi->current_netdev_flags = vsi->netdev->flags;
1483 }
1484
1485 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1486 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1487
1488 filter_list_len = pf->hw.aq.asq_buf_size /
1489 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1490 del_list = kcalloc(filter_list_len,
1491 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1492 GFP_KERNEL);
1493 if (!del_list)
1494 return -ENOMEM;
1495
1496 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1497 if (!f->changed)
1498 continue;
1499
1500 if (f->counter != 0)
1501 continue;
1502 f->changed = false;
1503 cmd_flags = 0;
1504
1505 /* add to delete list */
1506 memcpy(del_list[num_del].mac_addr,
1507 f->macaddr, ETH_ALEN);
1508 del_list[num_del].vlan_tag =
1509 cpu_to_le16((u16)(f->vlan ==
1510 I40E_VLAN_ANY ? 0 : f->vlan));
1511
41c445ff
JB		 1512 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1513 del_list[num_del].flags = cmd_flags;
1514 num_del++;
1515
1516 /* unlink from filter list */
1517 list_del(&f->list);
1518 kfree(f);
1519
1520 /* flush a full buffer */
1521 if (num_del == filter_list_len) {
dcae29be 1522 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1523 vsi->seid, del_list, num_del,
1524 NULL);
1525 num_del = 0;
1526 memset(del_list, 0, sizeof(*del_list));
1527
dcae29be 1528 if (aq_ret)
41c445ff
JB		 1529 dev_info(&pf->pdev->dev,
1530 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1531 aq_ret,
41c445ff
JB		 1532 pf->hw.aq.asq_last_status);
1533 }
1534 }
1535 if (num_del) {
dcae29be 1536 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1537 del_list, num_del, NULL);
1538 num_del = 0;
1539
dcae29be 1540 if (aq_ret)
41c445ff
JB		 1541 dev_info(&pf->pdev->dev,
1542 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1543 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1544 }
1545
1546 kfree(del_list);
1547 del_list = NULL;
1548
1549 /* do all the adds now */
1550 filter_list_len = pf->hw.aq.asq_buf_size /
1551 sizeof(struct i40e_aqc_add_macvlan_element_data),
1552 add_list = kcalloc(filter_list_len,
1553 sizeof(struct i40e_aqc_add_macvlan_element_data),
1554 GFP_KERNEL);
1555 if (!add_list)
1556 return -ENOMEM;
1557
1558 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1559 if (!f->changed)
1560 continue;
1561
1562 if (f->counter == 0)
1563 continue;
1564 f->changed = false;
1565 add_happened = true;
1566 cmd_flags = 0;
1567
1568 /* add to add array */
1569 memcpy(add_list[num_add].mac_addr,
1570 f->macaddr, ETH_ALEN);
1571 add_list[num_add].vlan_tag =
1572 cpu_to_le16(
1573 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1574 add_list[num_add].queue_number = 0;
1575
1576 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1577 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1578 num_add++;
1579
1580 /* flush a full buffer */
1581 if (num_add == filter_list_len) {
dcae29be
JB		 1582 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1583 add_list, num_add,
1584 NULL);
41c445ff
JB		 1585 num_add = 0;
1586
dcae29be 1587 if (aq_ret)
41c445ff
JB		 1588 break;
1589 memset(add_list, 0, sizeof(*add_list));
1590 }
1591 }
1592 if (num_add) {
dcae29be
JB		 1593 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1594 add_list, num_add, NULL);
41c445ff
JB		 1595 num_add = 0;
1596 }
1597 kfree(add_list);
1598 add_list = NULL;
1599
dcae29be 1600 if (add_happened && (!aq_ret)) {
41c445ff 1601 /* do nothing */;
dcae29be 1602 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1603 dev_info(&pf->pdev->dev,
1604 "add filter failed, err %d, aq_err %d\n",
dcae29be 1605 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1606 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1607 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1608 &vsi->state)) {
1609 promisc_forced_on = true;
1610 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1611 &vsi->state);
1612 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1613 }
1614 }
1615 }
1616
1617 /* check for changes in promiscuous modes */
1618 if (changed_flags & IFF_ALLMULTI) {
1619 bool cur_multipromisc;
1620 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1621 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1622 vsi->seid,
1623 cur_multipromisc,
1624 NULL);
1625 if (aq_ret)
41c445ff
JB		 1626 dev_info(&pf->pdev->dev,
1627 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1628 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1629 }
1630 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1631 bool cur_promisc;
1632 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1633 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1634 &vsi->state));
dcae29be
JB		 1635 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1636 vsi->seid,
1637 cur_promisc, NULL);
1638 if (aq_ret)
41c445ff
JB		 1639 dev_info(&pf->pdev->dev,
1640 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1641 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1642 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1643 vsi->seid,
1644 cur_promisc, NULL);
1645 if (aq_ret)
1646 dev_info(&pf->pdev->dev,
1647 "set brdcast promisc failed, err %d, aq_err %d\n",
1648 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1649 }
1650
1651 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1652 return 0;
1653}
1654
1655/**
1656 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1657 * @pf: board private structure
1658 **/
1659static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1660{
1661 int v;
1662
1663 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1664 return;
1665 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1666
1667 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1668 if (pf->vsi[v] &&
1669 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1670 i40e_sync_vsi_filters(pf->vsi[v]);
1671 }
1672}
1673
1674/**
1675 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1676 * @netdev: network interface device structure
1677 * @new_mtu: new value for maximum frame size
1678 *
1679 * Returns 0 on success, negative on failure
1680 **/
1681static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1682{
1683 struct i40e_netdev_priv *np = netdev_priv(netdev);
1684 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1685 struct i40e_vsi *vsi = np->vsi;
1686
1687 /* MTU < 68 is an error and causes problems on some kernels */
1688 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1689 return -EINVAL;
1690
1691 netdev_info(netdev, "changing MTU from %d to %d\n",
1692 netdev->mtu, new_mtu);
1693 netdev->mtu = new_mtu;
1694 if (netif_running(netdev))
1695 i40e_vsi_reinit_locked(vsi);
1696
1697 return 0;
1698}
1699
1700/**
1701 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1702 * @vsi: the vsi being adjusted
1703 **/
1704void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1705{
1706 struct i40e_vsi_context ctxt;
1707 i40e_status ret;
1708
1709 if ((vsi->info.valid_sections &
1710 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1711 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1712 return; /* already enabled */
1713
1714 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1715 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1716 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1717
1718 ctxt.seid = vsi->seid;
1719 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1720 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1721 if (ret) {
1722 dev_info(&vsi->back->pdev->dev,
1723 "%s: update vsi failed, aq_err=%d\n",
1724 __func__, vsi->back->hw.aq.asq_last_status);
1725 }
1726}
1727
1728/**
1729 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1730 * @vsi: the vsi being adjusted
1731 **/
1732void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1733{
1734 struct i40e_vsi_context ctxt;
1735 i40e_status ret;
1736
1737 if ((vsi->info.valid_sections &
1738 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1739 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1740 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1741 return; /* already disabled */
1742
1743 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1744 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1745 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1746
1747 ctxt.seid = vsi->seid;
1748 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1749 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1750 if (ret) {
1751 dev_info(&vsi->back->pdev->dev,
1752 "%s: update vsi failed, aq_err=%d\n",
1753 __func__, vsi->back->hw.aq.asq_last_status);
1754 }
1755}
1756
1757/**
1758 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1759 * @netdev: network interface to be adjusted
1760 * @features: netdev features to test if VLAN offload is enabled or not
1761 **/
1762static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1763{
1764 struct i40e_netdev_priv *np = netdev_priv(netdev);
1765 struct i40e_vsi *vsi = np->vsi;
1766
1767 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1768 i40e_vlan_stripping_enable(vsi);
1769 else
1770 i40e_vlan_stripping_disable(vsi);
1771}
1772
1773/**
1774 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1775 * @vsi: the vsi being configured
1776 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1777 **/
1778int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1779{
1780 struct i40e_mac_filter *f, *add_f;
1781 bool is_netdev, is_vf;
41c445ff
JB		 1782
1783 is_vf = (vsi->type == I40E_VSI_SRIOV);
1784 is_netdev = !!(vsi->netdev);
1785
1786 if (is_netdev) {
1787 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1788 is_vf, is_netdev);
1789 if (!add_f) {
1790 dev_info(&vsi->back->pdev->dev,
1791 "Could not add vlan filter %d for %pM\n",
1792 vid, vsi->netdev->dev_addr);
1793 return -ENOMEM;
1794 }
1795 }
1796
1797 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1798 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1799 if (!add_f) {
1800 dev_info(&vsi->back->pdev->dev,
1801 "Could not add vlan filter %d for %pM\n",
1802 vid, f->macaddr);
1803 return -ENOMEM;
1804 }
1805 }
1806
41c445ff
JB		 1807 /* Now if we add a vlan tag, make sure to check if it is the first
1808 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1809 * with 0, so we now accept untagged and specified tagged traffic
1810 * (and not any taged and untagged)
1811 */
1812 if (vid > 0) {
1813 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1814 I40E_VLAN_ANY,
1815 is_vf, is_netdev)) {
1816 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1817 I40E_VLAN_ANY, is_vf, is_netdev);
1818 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1819 is_vf, is_netdev);
1820 if (!add_f) {
1821 dev_info(&vsi->back->pdev->dev,
1822 "Could not add filter 0 for %pM\n",
1823 vsi->netdev->dev_addr);
1824 return -ENOMEM;
1825 }
1826 }
1827
1828 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1829 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1830 is_vf, is_netdev)) {
1831 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1832 is_vf, is_netdev);
1833 add_f = i40e_add_filter(vsi, f->macaddr,
1834 0, is_vf, is_netdev);
1835 if (!add_f) {
1836 dev_info(&vsi->back->pdev->dev,
1837 "Could not add filter 0 for %pM\n",
1838 f->macaddr);
1839 return -ENOMEM;
1840 }
1841 }
1842 }
41c445ff
JB		 1843 }
1844
80f6428f
ASJ		 1845 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1846 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1847 return 0;
1848
1849 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1850}
1851
1852/**
1853 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1854 * @vsi: the vsi being configured
1855 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1856 *
1857 * Return: 0 on success or negative otherwise
41c445ff
JB		 1858 **/
1859int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1860{
1861 struct net_device *netdev = vsi->netdev;
1862 struct i40e_mac_filter *f, *add_f;
1863 bool is_vf, is_netdev;
1864 int filter_count = 0;
41c445ff
JB		 1865
1866 is_vf = (vsi->type == I40E_VSI_SRIOV);
1867 is_netdev = !!(netdev);
1868
1869 if (is_netdev)
1870 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1871
1872 list_for_each_entry(f, &vsi->mac_filter_list, list)
1873 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1874
41c445ff
JB		 1875 /* go through all the filters for this VSI and if there is only
1876 * vid == 0 it means there are no other filters, so vid 0 must
1877 * be replaced with -1. This signifies that we should from now
1878 * on accept any traffic (with any tag present, or untagged)
1879 */
1880 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1881 if (is_netdev) {
1882 if (f->vlan &&
1883 ether_addr_equal(netdev->dev_addr, f->macaddr))
1884 filter_count++;
1885 }
1886
1887 if (f->vlan)
1888 filter_count++;
1889 }
1890
1891 if (!filter_count && is_netdev) {
1892 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1893 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1894 is_vf, is_netdev);
1895 if (!f) {
1896 dev_info(&vsi->back->pdev->dev,
1897 "Could not add filter %d for %pM\n",
1898 I40E_VLAN_ANY, netdev->dev_addr);
1899 return -ENOMEM;
1900 }
1901 }
1902
1903 if (!filter_count) {
1904 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1905 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1906 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1907 is_vf, is_netdev);
1908 if (!add_f) {
1909 dev_info(&vsi->back->pdev->dev,
1910 "Could not add filter %d for %pM\n",
1911 I40E_VLAN_ANY, f->macaddr);
1912 return -ENOMEM;
1913 }
1914 }
1915 }
1916
80f6428f
ASJ		 1917 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1918 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1919 return 0;
1920
41c445ff
JB		 1921 return i40e_sync_vsi_filters(vsi);
1922}
1923
1924/**
1925 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1926 * @netdev: network interface to be adjusted
1927 * @vid: vlan id to be added
078b5876
JB		 1928 *
1929 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1930 **/
1931static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1932 __always_unused __be16 proto, u16 vid)
1933{
1934 struct i40e_netdev_priv *np = netdev_priv(netdev);
1935 struct i40e_vsi *vsi = np->vsi;
078b5876 1936 int ret = 0;
41c445ff
JB		 1937
1938 if (vid > 4095)
078b5876
JB		 1939 return -EINVAL;
1940
1941 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1942
41c445ff
JB		 1943 /* If the network stack called us with vid = 0, we should
1944 * indicate to i40e_vsi_add_vlan() that we want to receive
1945 * any traffic (i.e. with any vlan tag, or untagged)
1946 */
1947 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1948
078b5876
JB		 1949 if (!ret && (vid < VLAN_N_VID))
1950 set_bit(vid, vsi->active_vlans);
41c445ff 1951
078b5876 1952 return ret;
41c445ff
JB		 1953}
1954
1955/**
1956 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1957 * @netdev: network interface to be adjusted
1958 * @vid: vlan id to be removed
078b5876
JB		 1959 *
1960 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1961 **/
1962static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1963 __always_unused __be16 proto, u16 vid)
1964{
1965 struct i40e_netdev_priv *np = netdev_priv(netdev);
1966 struct i40e_vsi *vsi = np->vsi;
1967
078b5876
JB		 1968 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1969
41c445ff
JB		 1970 /* return code is ignored as there is nothing a user
1971 * can do about failure to remove and a log message was
078b5876 1972 * already printed from the other function
41c445ff
JB		 1973 */
1974 i40e_vsi_kill_vlan(vsi, vid);
1975
1976 clear_bit(vid, vsi->active_vlans);
078b5876 1977
41c445ff
JB		 1978 return 0;
1979}
1980
1981/**
1982 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
1983 * @vsi: the vsi being brought back up
1984 **/
1985static void i40e_restore_vlan(struct i40e_vsi *vsi)
1986{
1987 u16 vid;
1988
1989 if (!vsi->netdev)
1990 return;
1991
1992 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
1993
1994 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
1995 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
1996 vid);
1997}
1998
1999/**
2000 * i40e_vsi_add_pvid - Add pvid for the VSI
2001 * @vsi: the vsi being adjusted
2002 * @vid: the vlan id to set as a PVID
2003 **/
dcae29be 2004int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2005{
2006 struct i40e_vsi_context ctxt;
dcae29be 2007 i40e_status aq_ret;
41c445ff
JB		 2008
2009 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2010 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2011 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2012 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2013 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2014
2015 ctxt.seid = vsi->seid;
2016 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2017 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2018 if (aq_ret) {
41c445ff
JB		 2019 dev_info(&vsi->back->pdev->dev,
2020 "%s: update vsi failed, aq_err=%d\n",
2021 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2022 return -ENOENT;
41c445ff
JB		 2023 }
2024
dcae29be 2025 return 0;
41c445ff
JB		 2026}
2027
2028/**
2029 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2030 * @vsi: the vsi being adjusted
2031 *
2032 * Just use the vlan_rx_register() service to put it back to normal
2033 **/
2034void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2035{
6c12fcbf
GR		 2036 i40e_vlan_stripping_disable(vsi);
2037
41c445ff 2038 vsi->info.pvid = 0;
41c445ff
JB		 2039}
2040
2041/**
2042 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2043 * @vsi: ptr to the VSI
2044 *
2045 * If this function returns with an error, then it's possible one or
2046 * more of the rings is populated (while the rest are not). It is the
2047 * callers duty to clean those orphaned rings.
2048 *
2049 * Return 0 on success, negative on failure
2050 **/
2051static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2052{
2053 int i, err = 0;
2054
2055 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2056 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2057
2058 return err;
2059}
2060
2061/**
2062 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2063 * @vsi: ptr to the VSI
2064 *
2065 * Free VSI's transmit software resources
2066 **/
2067static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2068{
2069 int i;
2070
8e9dca53
GR		 2071 if (!vsi->tx_rings)
2072 return;
2073
41c445ff 2074 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2075 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2076 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2077}
2078
2079/**
2080 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2081 * @vsi: ptr to the VSI
2082 *
2083 * If this function returns with an error, then it's possible one or
2084 * more of the rings is populated (while the rest are not). It is the
2085 * callers duty to clean those orphaned rings.
2086 *
2087 * Return 0 on success, negative on failure
2088 **/
2089static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2090{
2091 int i, err = 0;
2092
2093 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2094 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2095 return err;
2096}
2097
2098/**
2099 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2100 * @vsi: ptr to the VSI
2101 *
2102 * Free all receive software resources
2103 **/
2104static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2105{
2106 int i;
2107
8e9dca53
GR		 2108 if (!vsi->rx_rings)
2109 return;
2110
41c445ff 2111 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2112 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2113 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2114}
2115
2116/**
2117 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2118 * @ring: The Tx ring to configure
2119 *
2120 * Configure the Tx descriptor ring in the HMC context.
2121 **/
2122static int i40e_configure_tx_ring(struct i40e_ring *ring)
2123{
2124 struct i40e_vsi *vsi = ring->vsi;
2125 u16 pf_q = vsi->base_queue + ring->queue_index;
2126 struct i40e_hw *hw = &vsi->back->hw;
2127 struct i40e_hmc_obj_txq tx_ctx;
2128 i40e_status err = 0;
2129 u32 qtx_ctl = 0;
2130
2131 /* some ATR related tx ring init */
2132 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2133 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2134 ring->atr_count = 0;
2135 } else {
2136 ring->atr_sample_rate = 0;
2137 }
2138
2139 /* initialize XPS */
2140 if (ring->q_vector && ring->netdev &&
2141 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2142 netif_set_xps_queue(ring->netdev,
2143 &ring->q_vector->affinity_mask,
2144 ring->queue_index);
2145
2146 /* clear the context structure first */
2147 memset(&tx_ctx, 0, sizeof(tx_ctx));
2148
2149 tx_ctx.new_context = 1;
2150 tx_ctx.base = (ring->dma / 128);
2151 tx_ctx.qlen = ring->count;
2152 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
2153 I40E_FLAG_FDIR_ATR_ENABLED));
2154
2155 /* As part of VSI creation/update, FW allocates certain
2156 * Tx arbitration queue sets for each TC enabled for
2157 * the VSI. The FW returns the handles to these queue
2158 * sets as part of the response buffer to Add VSI,
2159 * Update VSI, etc. AQ commands. It is expected that
2160 * these queue set handles be associated with the Tx
2161 * queues by the driver as part of the TX queue context
2162 * initialization. This has to be done regardless of
2163 * DCB as by default everything is mapped to TC0.
2164 */
2165 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2166 tx_ctx.rdylist_act = 0;
2167
2168 /* clear the context in the HMC */
2169 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2170 if (err) {
2171 dev_info(&vsi->back->pdev->dev,
2172 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2173 ring->queue_index, pf_q, err);
2174 return -ENOMEM;
2175 }
2176
2177 /* set the context in the HMC */
2178 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2179 if (err) {
2180 dev_info(&vsi->back->pdev->dev,
2181 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2182 ring->queue_index, pf_q, err);
2183 return -ENOMEM;
2184 }
2185
2186 /* Now associate this queue with this PCI function */
2187 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2188 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2189 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2190 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2191 i40e_flush(hw);
2192
2193 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2194
2195 /* cache tail off for easier writes later */
2196 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2197
2198 return 0;
2199}
2200
2201/**
2202 * i40e_configure_rx_ring - Configure a receive ring context
2203 * @ring: The Rx ring to configure
2204 *
2205 * Configure the Rx descriptor ring in the HMC context.
2206 **/
2207static int i40e_configure_rx_ring(struct i40e_ring *ring)
2208{
2209 struct i40e_vsi *vsi = ring->vsi;
2210 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2211 u16 pf_q = vsi->base_queue + ring->queue_index;
2212 struct i40e_hw *hw = &vsi->back->hw;
2213 struct i40e_hmc_obj_rxq rx_ctx;
2214 i40e_status err = 0;
2215
2216 ring->state = 0;
2217
2218 /* clear the context structure first */
2219 memset(&rx_ctx, 0, sizeof(rx_ctx));
2220
2221 ring->rx_buf_len = vsi->rx_buf_len;
2222 ring->rx_hdr_len = vsi->rx_hdr_len;
2223
2224 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2225 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2226
2227 rx_ctx.base = (ring->dma / 128);
2228 rx_ctx.qlen = ring->count;
2229
2230 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2231 set_ring_16byte_desc_enabled(ring);
2232 rx_ctx.dsize = 0;
2233 } else {
2234 rx_ctx.dsize = 1;
2235 }
2236
2237 rx_ctx.dtype = vsi->dtype;
2238 if (vsi->dtype) {
2239 set_ring_ps_enabled(ring);
2240 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2241 I40E_RX_SPLIT_IP |
2242 I40E_RX_SPLIT_TCP_UDP |
2243 I40E_RX_SPLIT_SCTP;
2244 } else {
2245 rx_ctx.hsplit_0 = 0;
2246 }
2247
2248 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2249 (chain_len * ring->rx_buf_len));
2250 rx_ctx.tphrdesc_ena = 1;
2251 rx_ctx.tphwdesc_ena = 1;
2252 rx_ctx.tphdata_ena = 1;
2253 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2254 if (hw->revision_id == 0)
2255 rx_ctx.lrxqthresh = 0;
2256 else
2257 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2258 rx_ctx.crcstrip = 1;
2259 rx_ctx.l2tsel = 1;
2260 rx_ctx.showiv = 1;
2261
2262 /* clear the context in the HMC */
2263 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2264 if (err) {
2265 dev_info(&vsi->back->pdev->dev,
2266 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2267 ring->queue_index, pf_q, err);
2268 return -ENOMEM;
2269 }
2270
2271 /* set the context in the HMC */
2272 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2273 if (err) {
2274 dev_info(&vsi->back->pdev->dev,
2275 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2276 ring->queue_index, pf_q, err);
2277 return -ENOMEM;
2278 }
2279
2280 /* cache tail for quicker writes, and clear the reg before use */
2281 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2282 writel(0, ring->tail);
2283
2284 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2285
2286 return 0;
2287}
2288
2289/**
2290 * i40e_vsi_configure_tx - Configure the VSI for Tx
2291 * @vsi: VSI structure describing this set of rings and resources
2292 *
2293 * Configure the Tx VSI for operation.
2294 **/
2295static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2296{
2297 int err = 0;
2298 u16 i;
2299
9f65e15b
AD		 2300 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2301 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2302
2303 return err;
2304}
2305
2306/**
2307 * i40e_vsi_configure_rx - Configure the VSI for Rx
2308 * @vsi: the VSI being configured
2309 *
2310 * Configure the Rx VSI for operation.
2311 **/
2312static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2313{
2314 int err = 0;
2315 u16 i;
2316
2317 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2318 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2319 + ETH_FCS_LEN + VLAN_HLEN;
2320 else
2321 vsi->max_frame = I40E_RXBUFFER_2048;
2322
2323 /* figure out correct receive buffer length */
2324 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2325 I40E_FLAG_RX_PS_ENABLED)) {
2326 case I40E_FLAG_RX_1BUF_ENABLED:
2327 vsi->rx_hdr_len = 0;
2328 vsi->rx_buf_len = vsi->max_frame;
2329 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2330 break;
2331 case I40E_FLAG_RX_PS_ENABLED:
2332 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2333 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2334 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2335 break;
2336 default:
2337 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2338 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2339 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2340 break;
2341 }
2342
2343 /* round up for the chip's needs */
2344 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2345 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2346 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2347 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2348
2349 /* set up individual rings */
2350 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2351 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2352
2353 return err;
2354}
2355
2356/**
2357 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2358 * @vsi: ptr to the VSI
2359 **/
2360static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2361{
2362 u16 qoffset, qcount;
2363 int i, n;
2364
2365 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2366 return;
2367
2368 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2369 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2370 continue;
2371
2372 qoffset = vsi->tc_config.tc_info[n].qoffset;
2373 qcount = vsi->tc_config.tc_info[n].qcount;
2374 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2375 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2376 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2377 rx_ring->dcb_tc = n;
2378 tx_ring->dcb_tc = n;
2379 }
2380 }
2381}
2382
2383/**
2384 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2385 * @vsi: ptr to the VSI
2386 **/
2387static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2388{
2389 if (vsi->netdev)
2390 i40e_set_rx_mode(vsi->netdev);
2391}
2392
2393/**
2394 * i40e_vsi_configure - Set up the VSI for action
2395 * @vsi: the VSI being configured
2396 **/
2397static int i40e_vsi_configure(struct i40e_vsi *vsi)
2398{
2399 int err;
2400
2401 i40e_set_vsi_rx_mode(vsi);
2402 i40e_restore_vlan(vsi);
2403 i40e_vsi_config_dcb_rings(vsi);
2404 err = i40e_vsi_configure_tx(vsi);
2405 if (!err)
2406 err = i40e_vsi_configure_rx(vsi);
2407
2408 return err;
2409}
2410
2411/**
2412 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2413 * @vsi: the VSI being configured
2414 **/
2415static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2416{
2417 struct i40e_pf *pf = vsi->back;
2418 struct i40e_q_vector *q_vector;
2419 struct i40e_hw *hw = &pf->hw;
2420 u16 vector;
2421 int i, q;
2422 u32 val;
2423 u32 qp;
2424
2425 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2426 * and PFINT_LNKLSTn registers, e.g.:
2427 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2428 */
2429 qp = vsi->base_queue;
2430 vector = vsi->base_vector;
493fb300
AD		 2431 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2432 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2433 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2434 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2435 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2436 q_vector->rx.itr);
2437 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2438 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2439 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2440 q_vector->tx.itr);
2441
2442 /* Linked list for the queuepairs assigned to this vector */
2443 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2444 for (q = 0; q < q_vector->num_ringpairs; q++) {
2445 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2446 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2447 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2448 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2449 (I40E_QUEUE_TYPE_TX
2450 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2451
2452 wr32(hw, I40E_QINT_RQCTL(qp), val);
2453
2454 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2455 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2456 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2457 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2458 (I40E_QUEUE_TYPE_RX
2459 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2460
2461 /* Terminate the linked list */
2462 if (q == (q_vector->num_ringpairs - 1))
2463 val |= (I40E_QUEUE_END_OF_LIST
2464 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2465
2466 wr32(hw, I40E_QINT_TQCTL(qp), val);
2467 qp++;
2468 }
2469 }
2470
2471 i40e_flush(hw);
2472}
2473
2474/**
2475 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2476 * @hw: ptr to the hardware info
2477 **/
2478static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2479{
2480 u32 val;
2481
2482 /* clear things first */
2483 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2484 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2485
2486 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2487 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2488 I40E_PFINT_ICR0_ENA_GRST_MASK |
2489 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2490 I40E_PFINT_ICR0_ENA_GPIO_MASK |
2491 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2492 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2493 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2494 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2495
2496 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2497
2498 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2499 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2500 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2501
2502 /* OTHER_ITR_IDX = 0 */
2503 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2504}
2505
2506/**
2507 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2508 * @vsi: the VSI being configured
2509 **/
2510static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2511{
493fb300 2512 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2513 struct i40e_pf *pf = vsi->back;
2514 struct i40e_hw *hw = &pf->hw;
2515 u32 val;
2516
2517 /* set the ITR configuration */
2518 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2519 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2520 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2521 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2522 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2523 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2524
2525 i40e_enable_misc_int_causes(hw);
2526
2527 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2528 wr32(hw, I40E_PFINT_LNKLST0, 0);
2529
2530 /* Associate the queue pair to the vector and enable the q int */
2531 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2532 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2533 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2534
2535 wr32(hw, I40E_QINT_RQCTL(0), val);
2536
2537 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2538 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2539 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2540
2541 wr32(hw, I40E_QINT_TQCTL(0), val);
2542 i40e_flush(hw);
2543}
2544
2ef28cfb
MW		 2545/**
2546 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2547 * @pf: board private structure
2548 **/
2549void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2550{
2551 struct i40e_hw *hw = &pf->hw;
2552
2553 wr32(hw, I40E_PFINT_DYN_CTL0,
2554 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2555 i40e_flush(hw);
2556}
2557
41c445ff
JB		 2558/**
2559 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2560 * @pf: board private structure
2561 **/
116a57d4 2562void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2563{
2564 struct i40e_hw *hw = &pf->hw;
2565 u32 val;
2566
2567 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2568 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2569 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2570
2571 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2572 i40e_flush(hw);
2573}
2574
2575/**
2576 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2577 * @vsi: pointer to a vsi
2578 * @vector: enable a particular Hw Interrupt vector
2579 **/
2580void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2581{
2582 struct i40e_pf *pf = vsi->back;
2583 struct i40e_hw *hw = &pf->hw;
2584 u32 val;
2585
2586 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2587 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2588 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2589 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2590 /* skip the flush */
41c445ff
JB		 2591}
2592
2593/**
2594 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2595 * @irq: interrupt number
2596 * @data: pointer to a q_vector
2597 **/
2598static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2599{
2600 struct i40e_q_vector *q_vector = data;
2601
cd0b6fa6 2602 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2603 return IRQ_HANDLED;
2604
2605 napi_schedule(&q_vector->napi);
2606
2607 return IRQ_HANDLED;
2608}
2609
2610/**
2611 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2612 * @irq: interrupt number
2613 * @data: pointer to a q_vector
2614 **/
2615static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2616{
2617 struct i40e_q_vector *q_vector = data;
2618
cd0b6fa6 2619 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2620 return IRQ_HANDLED;
2621
2622 pr_info("fdir ring cleaning needed\n");
2623
2624 return IRQ_HANDLED;
2625}
2626
2627/**
2628 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2629 * @vsi: the VSI being configured
2630 * @basename: name for the vector
2631 *
2632 * Allocates MSI-X vectors and requests interrupts from the kernel.
2633 **/
2634static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2635{
2636 int q_vectors = vsi->num_q_vectors;
2637 struct i40e_pf *pf = vsi->back;
2638 int base = vsi->base_vector;
2639 int rx_int_idx = 0;
2640 int tx_int_idx = 0;
2641 int vector, err;
2642
2643 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2644 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2645
cd0b6fa6 2646 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2647 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2648 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2649 tx_int_idx++;
cd0b6fa6 2650 } else if (q_vector->rx.ring) {
41c445ff
JB		 2651 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2652 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2653 } else if (q_vector->tx.ring) {
41c445ff
JB		 2654 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2655 "%s-%s-%d", basename, "tx", tx_int_idx++);
2656 } else {
2657 /* skip this unused q_vector */
2658 continue;
2659 }
2660 err = request_irq(pf->msix_entries[base + vector].vector,
2661 vsi->irq_handler,
2662 0,
2663 q_vector->name,
2664 q_vector);
2665 if (err) {
2666 dev_info(&pf->pdev->dev,
2667 "%s: request_irq failed, error: %d\n",
2668 __func__, err);
2669 goto free_queue_irqs;
2670 }
2671 /* assign the mask for this irq */
2672 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2673 &q_vector->affinity_mask);
2674 }
2675
2676 return 0;
2677
2678free_queue_irqs:
2679 while (vector) {
2680 vector--;
2681 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2682 NULL);
2683 free_irq(pf->msix_entries[base + vector].vector,
2684 &(vsi->q_vectors[vector]));
2685 }
2686 return err;
2687}
2688
2689/**
2690 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2691 * @vsi: the VSI being un-configured
2692 **/
2693static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2694{
2695 struct i40e_pf *pf = vsi->back;
2696 struct i40e_hw *hw = &pf->hw;
2697 int base = vsi->base_vector;
2698 int i;
2699
2700 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2701 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2702 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2703 }
2704
2705 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2706 for (i = vsi->base_vector;
2707 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2708 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2709
2710 i40e_flush(hw);
2711 for (i = 0; i < vsi->num_q_vectors; i++)
2712 synchronize_irq(pf->msix_entries[i + base].vector);
2713 } else {
2714 /* Legacy and MSI mode - this stops all interrupt handling */
2715 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2716 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2717 i40e_flush(hw);
2718 synchronize_irq(pf->pdev->irq);
2719 }
2720}
2721
2722/**
2723 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2724 * @vsi: the VSI being configured
2725 **/
2726static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2727{
2728 struct i40e_pf *pf = vsi->back;
2729 int i;
2730
2731 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2732 for (i = vsi->base_vector;
2733 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2734 i40e_irq_dynamic_enable(vsi, i);
2735 } else {
2736 i40e_irq_dynamic_enable_icr0(pf);
2737 }
2738
1022cb6c 2739 i40e_flush(&pf->hw);
41c445ff
JB		 2740 return 0;
2741}
2742
2743/**
2744 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2745 * @pf: board private structure
2746 **/
2747static void i40e_stop_misc_vector(struct i40e_pf *pf)
2748{
2749 /* Disable ICR 0 */
2750 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2751 i40e_flush(&pf->hw);
2752}
2753
2754/**
2755 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2756 * @irq: interrupt number
2757 * @data: pointer to a q_vector
2758 *
2759 * This is the handler used for all MSI/Legacy interrupts, and deals
2760 * with both queue and non-queue interrupts. This is also used in
2761 * MSIX mode to handle the non-queue interrupts.
2762 **/
2763static irqreturn_t i40e_intr(int irq, void *data)
2764{
2765 struct i40e_pf *pf = (struct i40e_pf *)data;
2766 struct i40e_hw *hw = &pf->hw;
5e823066 2767 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2768 u32 icr0, icr0_remaining;
2769 u32 val, ena_mask;
2770
2771 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2772 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2773
116a57d4
SN		 2774 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2775 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2776 goto enable_intr;
41c445ff 2777
cd92e72f
SN		 2778 /* if interrupt but no bits showing, must be SWINT */
2779 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2780 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2781 pf->sw_int_count++;
2782
41c445ff
JB		 2783 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2784 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2785
2786 /* temporarily disable queue cause for NAPI processing */
2787 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2788 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2789 wr32(hw, I40E_QINT_RQCTL(0), qval);
2790
2791 qval = rd32(hw, I40E_QINT_TQCTL(0));
2792 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2793 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2794
2795 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2796 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2797 }
2798
2799 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2800 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2801 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2802 }
2803
2804 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2805 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2806 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2807 }
2808
2809 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2810 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2811 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2812 }
2813
2814 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2815 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2816 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2817 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2818 val = rd32(hw, I40E_GLGEN_RSTAT);
2819 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2820 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2821 if (val == I40E_RESET_CORER)
41c445ff 2822 pf->corer_count++;
d52cf0a9 2823 else if (val == I40E_RESET_GLOBR)
41c445ff 2824 pf->globr_count++;
d52cf0a9 2825 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2826 pf->empr_count++;
2827 }
2828
9c010ee0
ASJ		 2829 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2830 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2831 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2832 }
2833
41c445ff
JB		 2834 /* If a critical error is pending we have no choice but to reset the
2835 * device.
2836 * Report and mask out any remaining unexpected interrupts.
2837 */
2838 icr0_remaining = icr0 & ena_mask;
2839 if (icr0_remaining) {
2840 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2841 icr0_remaining);
9c010ee0 2842 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2843 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2844 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2845 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2846 dev_info(&pf->pdev->dev, "device will be reset\n");
2847 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2848 i40e_service_event_schedule(pf);
41c445ff
JB		 2849 }
2850 ena_mask &= ~icr0_remaining;
2851 }
5e823066 2852 ret = IRQ_HANDLED;
41c445ff 2853
5e823066 2854enable_intr:
41c445ff
JB		 2855 /* re-enable interrupt causes */
2856 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2857 if (!test_bit(__I40E_DOWN, &pf->state)) {
2858 i40e_service_event_schedule(pf);
2859 i40e_irq_dynamic_enable_icr0(pf);
2860 }
2861
5e823066 2862 return ret;
41c445ff
JB		 2863}
2864
2865/**
cd0b6fa6 2866 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2867 * @vsi: the VSI being configured
2868 * @v_idx: vector index
cd0b6fa6 2869 * @qp_idx: queue pair index
41c445ff 2870 **/
cd0b6fa6 2871static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2872{
493fb300 2873 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2874 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2875 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2876
2877 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2878 tx_ring->next = q_vector->tx.ring;
2879 q_vector->tx.ring = tx_ring;
41c445ff 2880 q_vector->tx.count++;
cd0b6fa6
AD		 2881
2882 rx_ring->q_vector = q_vector;
2883 rx_ring->next = q_vector->rx.ring;
2884 q_vector->rx.ring = rx_ring;
2885 q_vector->rx.count++;
41c445ff
JB		 2886}
2887
2888/**
2889 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2890 * @vsi: the VSI being configured
2891 *
2892 * This function maps descriptor rings to the queue-specific vectors
2893 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2894 * one vector per queue pair, but on a constrained vector budget, we
2895 * group the queue pairs as "efficiently" as possible.
2896 **/
2897static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2898{
2899 int qp_remaining = vsi->num_queue_pairs;
2900 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2901 int num_ringpairs;
41c445ff
JB		 2902 int v_start = 0;
2903 int qp_idx = 0;
2904
2905 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2906 * group them so there are multiple queues per vector.
2907 */
2908 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2909 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2910
2911 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2912
2913 q_vector->num_ringpairs = num_ringpairs;
2914
2915 q_vector->rx.count = 0;
2916 q_vector->tx.count = 0;
2917 q_vector->rx.ring = NULL;
2918 q_vector->tx.ring = NULL;
2919
2920 while (num_ringpairs--) {
2921 map_vector_to_qp(vsi, v_start, qp_idx);
2922 qp_idx++;
2923 qp_remaining--;
41c445ff
JB		 2924 }
2925 }
2926}
2927
2928/**
2929 * i40e_vsi_request_irq - Request IRQ from the OS
2930 * @vsi: the VSI being configured
2931 * @basename: name for the vector
2932 **/
2933static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2934{
2935 struct i40e_pf *pf = vsi->back;
2936 int err;
2937
2938 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2939 err = i40e_vsi_request_irq_msix(vsi, basename);
2940 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2941 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2942 pf->misc_int_name, pf);
2943 else
2944 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2945 pf->misc_int_name, pf);
2946
2947 if (err)
2948 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2949
2950 return err;
2951}
2952
2953#ifdef CONFIG_NET_POLL_CONTROLLER
2954/**
2955 * i40e_netpoll - A Polling 'interrupt'handler
2956 * @netdev: network interface device structure
2957 *
2958 * This is used by netconsole to send skbs without having to re-enable
2959 * interrupts. It's not called while the normal interrupt routine is executing.
2960 **/
2961static void i40e_netpoll(struct net_device *netdev)
2962{
2963 struct i40e_netdev_priv *np = netdev_priv(netdev);
2964 struct i40e_vsi *vsi = np->vsi;
2965 struct i40e_pf *pf = vsi->back;
2966 int i;
2967
2968 /* if interface is down do nothing */
2969 if (test_bit(__I40E_DOWN, &vsi->state))
2970 return;
2971
2972 pf->flags |= I40E_FLAG_IN_NETPOLL;
2973 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2974 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 2975 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 2976 } else {
2977 i40e_intr(pf->pdev->irq, netdev);
2978 }
2979 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
2980}
2981#endif
2982
2983/**
2984 * i40e_vsi_control_tx - Start or stop a VSI's rings
2985 * @vsi: the VSI being configured
2986 * @enable: start or stop the rings
2987 **/
2988static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
2989{
2990 struct i40e_pf *pf = vsi->back;
2991 struct i40e_hw *hw = &pf->hw;
2992 int i, j, pf_q;
2993 u32 tx_reg;
2994
2995 pf_q = vsi->base_queue;
2996 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
2997 j = 1000;
2998 do {
2999 usleep_range(1000, 2000);
3000 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3001 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
3002 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
3003
fda972f6
MW		 3004 /* Skip if the queue is already in the requested state */
3005 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3006 continue;
3007 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3008 continue;
41c445ff
JB		 3009
3010 /* turn on/off the queue */
c5c9eb9e
SN		 3011 if (enable) {
3012 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
41c445ff
JB		 3013 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3014 I40E_QTX_ENA_QENA_STAT_MASK;
c5c9eb9e 3015 } else {
41c445ff 3016 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3017 }
41c445ff
JB		 3018
3019 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3020
3021 /* wait for the change to finish */
3022 for (j = 0; j < 10; j++) {
3023 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3024 if (enable) {
3025 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3026 break;
3027 } else {
3028 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3029 break;
3030 }
3031
3032 udelay(10);
3033 }
3034 if (j >= 10) {
3035 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3036 pf_q, (enable ? "en" : "dis"));
3037 return -ETIMEDOUT;
3038 }
3039 }
3040
7134f9ce
JB		 3041 if (hw->revision_id == 0)
3042 mdelay(50);
3043
41c445ff
JB		 3044 return 0;
3045}
3046
3047/**
3048 * i40e_vsi_control_rx - Start or stop a VSI's rings
3049 * @vsi: the VSI being configured
3050 * @enable: start or stop the rings
3051 **/
3052static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3053{
3054 struct i40e_pf *pf = vsi->back;
3055 struct i40e_hw *hw = &pf->hw;
3056 int i, j, pf_q;
3057 u32 rx_reg;
3058
3059 pf_q = vsi->base_queue;
3060 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3061 j = 1000;
3062 do {
3063 usleep_range(1000, 2000);
3064 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3065 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3066 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3067
3068 if (enable) {
3069 /* is STAT set ? */
3070 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3071 continue;
3072 } else {
3073 /* is !STAT set ? */
3074 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3075 continue;
3076 }
3077
3078 /* turn on/off the queue */
3079 if (enable)
3080 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3081 I40E_QRX_ENA_QENA_STAT_MASK;
3082 else
3083 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3084 I40E_QRX_ENA_QENA_STAT_MASK);
3085 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3086
3087 /* wait for the change to finish */
3088 for (j = 0; j < 10; j++) {
3089 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3090
3091 if (enable) {
3092 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3093 break;
3094 } else {
3095 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3096 break;
3097 }
3098
3099 udelay(10);
3100 }
3101 if (j >= 10) {
3102 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3103 pf_q, (enable ? "en" : "dis"));
3104 return -ETIMEDOUT;
3105 }
3106 }
3107
3108 return 0;
3109}
3110
3111/**
3112 * i40e_vsi_control_rings - Start or stop a VSI's rings
3113 * @vsi: the VSI being configured
3114 * @enable: start or stop the rings
3115 **/
fc18eaa0 3116int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3117{
3b867b28 3118 int ret = 0;
41c445ff
JB		 3119
3120 /* do rx first for enable and last for disable */
3121 if (request) {
3122 ret = i40e_vsi_control_rx(vsi, request);
3123 if (ret)
3124 return ret;
3125 ret = i40e_vsi_control_tx(vsi, request);
3126 } else {
3b867b28
ASJ		 3127 /* Ignore return value, we need to shutdown whatever we can */
3128 i40e_vsi_control_tx(vsi, request);
3129 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3130 }
3131
3132 return ret;
3133}
3134
3135/**
3136 * i40e_vsi_free_irq - Free the irq association with the OS
3137 * @vsi: the VSI being configured
3138 **/
3139static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3140{
3141 struct i40e_pf *pf = vsi->back;
3142 struct i40e_hw *hw = &pf->hw;
3143 int base = vsi->base_vector;
3144 u32 val, qp;
3145 int i;
3146
3147 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3148 if (!vsi->q_vectors)
3149 return;
3150
3151 for (i = 0; i < vsi->num_q_vectors; i++) {
3152 u16 vector = i + base;
3153
3154 /* free only the irqs that were actually requested */
78681b1f
SN		 3155 if (!vsi->q_vectors[i] ||
3156 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3157 continue;
3158
3159 /* clear the affinity_mask in the IRQ descriptor */
3160 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3161 NULL);
3162 free_irq(pf->msix_entries[vector].vector,
493fb300 3163 vsi->q_vectors[i]);
41c445ff
JB		 3164
3165 /* Tear down the interrupt queue link list
3166 *
3167 * We know that they come in pairs and always
3168 * the Rx first, then the Tx. To clear the
3169 * link list, stick the EOL value into the
3170 * next_q field of the registers.
3171 */
3172 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3173 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3174 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3175 val |= I40E_QUEUE_END_OF_LIST
3176 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3177 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3178
3179 while (qp != I40E_QUEUE_END_OF_LIST) {
3180 u32 next;
3181
3182 val = rd32(hw, I40E_QINT_RQCTL(qp));
3183
3184 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3185 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3186 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3187 I40E_QINT_RQCTL_INTEVENT_MASK);
3188
3189 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3190 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3191
3192 wr32(hw, I40E_QINT_RQCTL(qp), val);
3193
3194 val = rd32(hw, I40E_QINT_TQCTL(qp));
3195
3196 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3197 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3198
3199 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3200 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3201 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3202 I40E_QINT_TQCTL_INTEVENT_MASK);
3203
3204 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3205 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3206
3207 wr32(hw, I40E_QINT_TQCTL(qp), val);
3208 qp = next;
3209 }
3210 }
3211 } else {
3212 free_irq(pf->pdev->irq, pf);
3213
3214 val = rd32(hw, I40E_PFINT_LNKLST0);
3215 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3216 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3217 val |= I40E_QUEUE_END_OF_LIST
3218 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3219 wr32(hw, I40E_PFINT_LNKLST0, val);
3220
3221 val = rd32(hw, I40E_QINT_RQCTL(qp));
3222 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3223 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3224 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3225 I40E_QINT_RQCTL_INTEVENT_MASK);
3226
3227 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3228 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3229
3230 wr32(hw, I40E_QINT_RQCTL(qp), val);
3231
3232 val = rd32(hw, I40E_QINT_TQCTL(qp));
3233
3234 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3235 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3236 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3237 I40E_QINT_TQCTL_INTEVENT_MASK);
3238
3239 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3240 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3241
3242 wr32(hw, I40E_QINT_TQCTL(qp), val);
3243 }
3244}
3245
493fb300
AD		 3246/**
3247 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3248 * @vsi: the VSI being configured
3249 * @v_idx: Index of vector to be freed
3250 *
3251 * This function frees the memory allocated to the q_vector. In addition if
3252 * NAPI is enabled it will delete any references to the NAPI struct prior
3253 * to freeing the q_vector.
3254 **/
3255static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3256{
3257 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3258 struct i40e_ring *ring;
493fb300
AD		 3259
3260 if (!q_vector)
3261 return;
3262
3263 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3264 i40e_for_each_ring(ring, q_vector->tx)
3265 ring->q_vector = NULL;
3266
3267 i40e_for_each_ring(ring, q_vector->rx)
3268 ring->q_vector = NULL;
493fb300
AD		 3269
3270 /* only VSI w/ an associated netdev is set up w/ NAPI */
3271 if (vsi->netdev)
3272 netif_napi_del(&q_vector->napi);
3273
3274 vsi->q_vectors[v_idx] = NULL;
3275
3276 kfree_rcu(q_vector, rcu);
3277}
3278
41c445ff
JB		 3279/**
3280 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3281 * @vsi: the VSI being un-configured
3282 *
3283 * This frees the memory allocated to the q_vectors and
3284 * deletes references to the NAPI struct.
3285 **/
3286static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3287{
3288 int v_idx;
3289
493fb300
AD		 3290 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3291 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3292}
3293
3294/**
3295 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3296 * @pf: board private structure
3297 **/
3298static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3299{
3300 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3301 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3302 pci_disable_msix(pf->pdev);
3303 kfree(pf->msix_entries);
3304 pf->msix_entries = NULL;
3305 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3306 pci_disable_msi(pf->pdev);
3307 }
3308 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3309}
3310
3311/**
3312 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3313 * @pf: board private structure
3314 *
3315 * We go through and clear interrupt specific resources and reset the structure
3316 * to pre-load conditions
3317 **/
3318static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3319{
3320 int i;
3321
3322 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3323 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3324 if (pf->vsi[i])
3325 i40e_vsi_free_q_vectors(pf->vsi[i]);
3326 i40e_reset_interrupt_capability(pf);
3327}
3328
3329/**
3330 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3331 * @vsi: the VSI being configured
3332 **/
3333static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3334{
3335 int q_idx;
3336
3337 if (!vsi->netdev)
3338 return;
3339
3340 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3341 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3342}
3343
3344/**
3345 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3346 * @vsi: the VSI being configured
3347 **/
3348static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3349{
3350 int q_idx;
3351
3352 if (!vsi->netdev)
3353 return;
3354
3355 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3356 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3357}
3358
3359/**
3360 * i40e_quiesce_vsi - Pause a given VSI
3361 * @vsi: the VSI being paused
3362 **/
3363static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3364{
3365 if (test_bit(__I40E_DOWN, &vsi->state))
3366 return;
3367
3368 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3369 if (vsi->netdev && netif_running(vsi->netdev)) {
3370 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3371 } else {
3372 set_bit(__I40E_DOWN, &vsi->state);
3373 i40e_down(vsi);
3374 }
3375}
3376
3377/**
3378 * i40e_unquiesce_vsi - Resume a given VSI
3379 * @vsi: the VSI being resumed
3380 **/
3381static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3382{
3383 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3384 return;
3385
3386 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3387 if (vsi->netdev && netif_running(vsi->netdev))
3388 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3389 else
3390 i40e_up(vsi); /* this clears the DOWN bit */
3391}
3392
3393/**
3394 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3395 * @pf: the PF
3396 **/
3397static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3398{
3399 int v;
3400
3401 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3402 if (pf->vsi[v])
3403 i40e_quiesce_vsi(pf->vsi[v]);
3404 }
3405}
3406
3407/**
3408 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3409 * @pf: the PF
3410 **/
3411static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3412{
3413 int v;
3414
3415 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3416 if (pf->vsi[v])
3417 i40e_unquiesce_vsi(pf->vsi[v]);
3418 }
3419}
3420
3421/**
3422 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3423 * @dcbcfg: the corresponding DCBx configuration structure
3424 *
3425 * Return the number of TCs from given DCBx configuration
3426 **/
3427static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3428{
078b5876
JB		 3429 u8 num_tc = 0;
3430 int i;
41c445ff
JB		 3431
3432 /* Scan the ETS Config Priority Table to find
3433 * traffic class enabled for a given priority
3434 * and use the traffic class index to get the
3435 * number of traffic classes enabled
3436 */
3437 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3438 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3439 num_tc = dcbcfg->etscfg.prioritytable[i];
3440 }
3441
3442 /* Traffic class index starts from zero so
3443 * increment to return the actual count
3444 */
078b5876 3445 return num_tc + 1;
41c445ff
JB		 3446}
3447
3448/**
3449 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3450 * @dcbcfg: the corresponding DCBx configuration structure
3451 *
3452 * Query the current DCB configuration and return the number of
3453 * traffic classes enabled from the given DCBX config
3454 **/
3455static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3456{
3457 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3458 u8 enabled_tc = 1;
3459 u8 i;
3460
3461 for (i = 0; i < num_tc; i++)
3462 enabled_tc |= 1 << i;
3463
3464 return enabled_tc;
3465}
3466
3467/**
3468 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3469 * @pf: PF being queried
3470 *
3471 * Return number of traffic classes enabled for the given PF
3472 **/
3473static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3474{
3475 struct i40e_hw *hw = &pf->hw;
3476 u8 i, enabled_tc;
3477 u8 num_tc = 0;
3478 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3479
3480 /* If DCB is not enabled then always in single TC */
3481 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3482 return 1;
3483
3484 /* MFP mode return count of enabled TCs for this PF */
3485 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3486 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3487 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3488 if (enabled_tc & (1 << i))
3489 num_tc++;
3490 }
3491 return num_tc;
3492 }
3493
3494 /* SFP mode will be enabled for all TCs on port */
3495 return i40e_dcb_get_num_tc(dcbcfg);
3496}
3497
3498/**
3499 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3500 * @pf: PF being queried
3501 *
3502 * Return a bitmap for first enabled traffic class for this PF.
3503 **/
3504static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3505{
3506 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3507 u8 i = 0;
3508
3509 if (!enabled_tc)
3510 return 0x1; /* TC0 */
3511
3512 /* Find the first enabled TC */
3513 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3514 if (enabled_tc & (1 << i))
3515 break;
3516 }
3517
3518 return 1 << i;
3519}
3520
3521/**
3522 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3523 * @pf: PF being queried
3524 *
3525 * Return a bitmap for enabled traffic classes for this PF.
3526 **/
3527static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3528{
3529 /* If DCB is not enabled for this PF then just return default TC */
3530 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3531 return i40e_pf_get_default_tc(pf);
3532
3533 /* MFP mode will have enabled TCs set by FW */
3534 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3535 return pf->hw.func_caps.enabled_tcmap;
3536
3537 /* SFP mode we want PF to be enabled for all TCs */
3538 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3539}
3540
3541/**
3542 * i40e_vsi_get_bw_info - Query VSI BW Information
3543 * @vsi: the VSI being queried
3544 *
3545 * Returns 0 on success, negative value on failure
3546 **/
3547static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3548{
3549 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3550 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3551 struct i40e_pf *pf = vsi->back;
3552 struct i40e_hw *hw = &pf->hw;
dcae29be 3553 i40e_status aq_ret;
41c445ff 3554 u32 tc_bw_max;
41c445ff
JB		 3555 int i;
3556
3557 /* Get the VSI level BW configuration */
dcae29be
JB		 3558 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3559 if (aq_ret) {
41c445ff
JB		 3560 dev_info(&pf->pdev->dev,
3561 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3562 aq_ret, pf->hw.aq.asq_last_status);
3563 return -EINVAL;
41c445ff
JB		 3564 }
3565
3566 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3567 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3568 NULL);
3569 if (aq_ret) {
41c445ff
JB		 3570 dev_info(&pf->pdev->dev,
3571 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3572 aq_ret, pf->hw.aq.asq_last_status);
3573 return -EINVAL;
41c445ff
JB		 3574 }
3575
3576 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3577 dev_info(&pf->pdev->dev,
3578 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3579 bw_config.tc_valid_bits,
3580 bw_ets_config.tc_valid_bits);
3581 /* Still continuing */
3582 }
3583
3584 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3585 vsi->bw_max_quanta = bw_config.max_bw;
3586 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3587 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3589 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3590 vsi->bw_ets_limit_credits[i] =
3591 le16_to_cpu(bw_ets_config.credits[i]);
3592 /* 3 bits out of 4 for each TC */
3593 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3594 }
078b5876 3595
dcae29be 3596 return 0;
41c445ff
JB		 3597}
3598
3599/**
3600 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3601 * @vsi: the VSI being configured
3602 * @enabled_tc: TC bitmap
3603 * @bw_credits: BW shared credits per TC
3604 *
3605 * Returns 0 on success, negative value on failure
3606 **/
dcae29be 3607static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3608 u8 *bw_share)
3609{
3610 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3611 i40e_status aq_ret;
3612 int i;
41c445ff
JB		 3613
3614 bw_data.tc_valid_bits = enabled_tc;
3615 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3616 bw_data.tc_bw_credits[i] = bw_share[i];
3617
dcae29be
JB		 3618 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3619 NULL);
3620 if (aq_ret) {
41c445ff
JB		 3621 dev_info(&vsi->back->pdev->dev,
3622 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3623 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3624 return -EINVAL;
41c445ff
JB		 3625 }
3626
3627 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3628 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3629
dcae29be 3630 return 0;
41c445ff
JB		 3631}
3632
3633/**
3634 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3635 * @vsi: the VSI being configured
3636 * @enabled_tc: TC map to be enabled
3637 *
3638 **/
3639static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3640{
3641 struct net_device *netdev = vsi->netdev;
3642 struct i40e_pf *pf = vsi->back;
3643 struct i40e_hw *hw = &pf->hw;
3644 u8 netdev_tc = 0;
3645 int i;
3646 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3647
3648 if (!netdev)
3649 return;
3650
3651 if (!enabled_tc) {
3652 netdev_reset_tc(netdev);
3653 return;
3654 }
3655
3656 /* Set up actual enabled TCs on the VSI */
3657 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3658 return;
3659
3660 /* set per TC queues for the VSI */
3661 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3662 /* Only set TC queues for enabled tcs
3663 *
3664 * e.g. For a VSI that has TC0 and TC3 enabled the
3665 * enabled_tc bitmap would be 0x00001001; the driver
3666 * will set the numtc for netdev as 2 that will be
3667 * referenced by the netdev layer as TC 0 and 1.
3668 */
3669 if (vsi->tc_config.enabled_tc & (1 << i))
3670 netdev_set_tc_queue(netdev,
3671 vsi->tc_config.tc_info[i].netdev_tc,
3672 vsi->tc_config.tc_info[i].qcount,
3673 vsi->tc_config.tc_info[i].qoffset);
3674 }
3675
3676 /* Assign UP2TC map for the VSI */
3677 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3678 /* Get the actual TC# for the UP */
3679 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3680 /* Get the mapped netdev TC# for the UP */
3681 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3682 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3683 }
3684}
3685
3686/**
3687 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3688 * @vsi: the VSI being configured
3689 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3690 **/
3691static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3692 struct i40e_vsi_context *ctxt)
3693{
3694 /* copy just the sections touched not the entire info
3695 * since not all sections are valid as returned by
3696 * update vsi params
3697 */
3698 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3699 memcpy(&vsi->info.queue_mapping,
3700 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3701 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3702 sizeof(vsi->info.tc_mapping));
3703}
3704
3705/**
3706 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3707 * @vsi: VSI to be configured
3708 * @enabled_tc: TC bitmap
3709 *
3710 * This configures a particular VSI for TCs that are mapped to the
3711 * given TC bitmap. It uses default bandwidth share for TCs across
3712 * VSIs to configure TC for a particular VSI.
3713 *
3714 * NOTE:
3715 * It is expected that the VSI queues have been quisced before calling
3716 * this function.
3717 **/
3718static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3719{
3720 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3721 struct i40e_vsi_context ctxt;
3722 int ret = 0;
3723 int i;
3724
3725 /* Check if enabled_tc is same as existing or new TCs */
3726 if (vsi->tc_config.enabled_tc == enabled_tc)
3727 return ret;
3728
3729 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3730 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3731 if (enabled_tc & (1 << i))
3732 bw_share[i] = 1;
3733 }
3734
3735 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3736 if (ret) {
3737 dev_info(&vsi->back->pdev->dev,
3738 "Failed configuring TC map %d for VSI %d\n",
3739 enabled_tc, vsi->seid);
3740 goto out;
3741 }
3742
3743 /* Update Queue Pairs Mapping for currently enabled UPs */
3744 ctxt.seid = vsi->seid;
3745 ctxt.pf_num = vsi->back->hw.pf_id;
3746 ctxt.vf_num = 0;
3747 ctxt.uplink_seid = vsi->uplink_seid;
3748 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3749 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3750
3751 /* Update the VSI after updating the VSI queue-mapping information */
3752 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3753 if (ret) {
3754 dev_info(&vsi->back->pdev->dev,
3755 "update vsi failed, aq_err=%d\n",
3756 vsi->back->hw.aq.asq_last_status);
3757 goto out;
3758 }
3759 /* update the local VSI info with updated queue map */
3760 i40e_vsi_update_queue_map(vsi, &ctxt);
3761 vsi->info.valid_sections = 0;
3762
3763 /* Update current VSI BW information */
3764 ret = i40e_vsi_get_bw_info(vsi);
3765 if (ret) {
3766 dev_info(&vsi->back->pdev->dev,
3767 "Failed updating vsi bw info, aq_err=%d\n",
3768 vsi->back->hw.aq.asq_last_status);
3769 goto out;
3770 }
3771
3772 /* Update the netdev TC setup */
3773 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3774out:
3775 return ret;
3776}
3777
3778/**
3779 * i40e_up_complete - Finish the last steps of bringing up a connection
3780 * @vsi: the VSI being configured
3781 **/
3782static int i40e_up_complete(struct i40e_vsi *vsi)
3783{
3784 struct i40e_pf *pf = vsi->back;
3785 int err;
3786
3787 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3788 i40e_vsi_configure_msix(vsi);
3789 else
3790 i40e_configure_msi_and_legacy(vsi);
3791
3792 /* start rings */
3793 err = i40e_vsi_control_rings(vsi, true);
3794 if (err)
3795 return err;
3796
3797 clear_bit(__I40E_DOWN, &vsi->state);
3798 i40e_napi_enable_all(vsi);
3799 i40e_vsi_enable_irq(vsi);
3800
3801 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3802 (vsi->netdev)) {
6d779b41 3803 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3804 netif_tx_start_all_queues(vsi->netdev);
3805 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3806 } else if (vsi->netdev) {
3807 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3808 }
3809 i40e_service_event_schedule(pf);
3810
3811 return 0;
3812}
3813
3814/**
3815 * i40e_vsi_reinit_locked - Reset the VSI
3816 * @vsi: the VSI being configured
3817 *
3818 * Rebuild the ring structs after some configuration
3819 * has changed, e.g. MTU size.
3820 **/
3821static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3822{
3823 struct i40e_pf *pf = vsi->back;
3824
3825 WARN_ON(in_interrupt());
3826 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3827 usleep_range(1000, 2000);
3828 i40e_down(vsi);
3829
3830 /* Give a VF some time to respond to the reset. The
3831 * two second wait is based upon the watchdog cycle in
3832 * the VF driver.
3833 */
3834 if (vsi->type == I40E_VSI_SRIOV)
3835 msleep(2000);
3836 i40e_up(vsi);
3837 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3838}
3839
3840/**
3841 * i40e_up - Bring the connection back up after being down
3842 * @vsi: the VSI being configured
3843 **/
3844int i40e_up(struct i40e_vsi *vsi)
3845{
3846 int err;
3847
3848 err = i40e_vsi_configure(vsi);
3849 if (!err)
3850 err = i40e_up_complete(vsi);
3851
3852 return err;
3853}
3854
3855/**
3856 * i40e_down - Shutdown the connection processing
3857 * @vsi: the VSI being stopped
3858 **/
3859void i40e_down(struct i40e_vsi *vsi)
3860{
3861 int i;
3862
3863 /* It is assumed that the caller of this function
3864 * sets the vsi->state __I40E_DOWN bit.
3865 */
3866 if (vsi->netdev) {
3867 netif_carrier_off(vsi->netdev);
3868 netif_tx_disable(vsi->netdev);
3869 }
3870 i40e_vsi_disable_irq(vsi);
3871 i40e_vsi_control_rings(vsi, false);
3872 i40e_napi_disable_all(vsi);
3873
3874 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3875 i40e_clean_tx_ring(vsi->tx_rings[i]);
3876 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3877 }
3878}
3879
3880/**
3881 * i40e_setup_tc - configure multiple traffic classes
3882 * @netdev: net device to configure
3883 * @tc: number of traffic classes to enable
3884 **/
3885static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3886{
3887 struct i40e_netdev_priv *np = netdev_priv(netdev);
3888 struct i40e_vsi *vsi = np->vsi;
3889 struct i40e_pf *pf = vsi->back;
3890 u8 enabled_tc = 0;
3891 int ret = -EINVAL;
3892 int i;
3893
3894 /* Check if DCB enabled to continue */
3895 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3896 netdev_info(netdev, "DCB is not enabled for adapter\n");
3897 goto exit;
3898 }
3899
3900 /* Check if MFP enabled */
3901 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3902 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3903 goto exit;
3904 }
3905
3906 /* Check whether tc count is within enabled limit */
3907 if (tc > i40e_pf_get_num_tc(pf)) {
3908 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3909 goto exit;
3910 }
3911
3912 /* Generate TC map for number of tc requested */
3913 for (i = 0; i < tc; i++)
3914 enabled_tc |= (1 << i);
3915
3916 /* Requesting same TC configuration as already enabled */
3917 if (enabled_tc == vsi->tc_config.enabled_tc)
3918 return 0;
3919
3920 /* Quiesce VSI queues */
3921 i40e_quiesce_vsi(vsi);
3922
3923 /* Configure VSI for enabled TCs */
3924 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3925 if (ret) {
3926 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3927 vsi->seid);
3928 goto exit;
3929 }
3930
3931 /* Unquiesce VSI */
3932 i40e_unquiesce_vsi(vsi);
3933
3934exit:
3935 return ret;
3936}
3937
3938/**
3939 * i40e_open - Called when a network interface is made active
3940 * @netdev: network interface device structure
3941 *
3942 * The open entry point is called when a network interface is made
3943 * active by the system (IFF_UP). At this point all resources needed
3944 * for transmit and receive operations are allocated, the interrupt
3945 * handler is registered with the OS, the netdev watchdog subtask is
3946 * enabled, and the stack is notified that the interface is ready.
3947 *
3948 * Returns 0 on success, negative value on failure
3949 **/
3950static int i40e_open(struct net_device *netdev)
3951{
3952 struct i40e_netdev_priv *np = netdev_priv(netdev);
3953 struct i40e_vsi *vsi = np->vsi;
3954 struct i40e_pf *pf = vsi->back;
3955 char int_name[IFNAMSIZ];
3956 int err;
3957
3958 /* disallow open during test */
3959 if (test_bit(__I40E_TESTING, &pf->state))
3960 return -EBUSY;
3961
3962 netif_carrier_off(netdev);
3963
3964 /* allocate descriptors */
3965 err = i40e_vsi_setup_tx_resources(vsi);
3966 if (err)
3967 goto err_setup_tx;
3968 err = i40e_vsi_setup_rx_resources(vsi);
3969 if (err)
3970 goto err_setup_rx;
3971
3972 err = i40e_vsi_configure(vsi);
3973 if (err)
3974 goto err_setup_rx;
3975
3976 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
3977 dev_driver_string(&pf->pdev->dev), netdev->name);
3978 err = i40e_vsi_request_irq(vsi, int_name);
3979 if (err)
3980 goto err_setup_rx;
3981
25946ddb 3982 /* Notify the stack of the actual queue counts. */
d7397644 3983 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3984 if (err)
3985 goto err_set_queues;
3986
d7397644 3987 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3988 if (err)
3989 goto err_set_queues;
3990
41c445ff
JB		 3991 err = i40e_up_complete(vsi);
3992 if (err)
3993 goto err_up_complete;
3994
a1c9a9d9
JK		 3995#ifdef CONFIG_I40E_VXLAN
3996 vxlan_get_rx_port(netdev);
3997#endif
41c445ff
JB		 3998
3999 return 0;
4000
4001err_up_complete:
4002 i40e_down(vsi);
25946ddb 4003err_set_queues:
41c445ff
JB		 4004 i40e_vsi_free_irq(vsi);
4005err_setup_rx:
4006 i40e_vsi_free_rx_resources(vsi);
4007err_setup_tx:
4008 i40e_vsi_free_tx_resources(vsi);
4009 if (vsi == pf->vsi[pf->lan_vsi])
4010 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4011
4012 return err;
4013}
4014
4015/**
4016 * i40e_close - Disables a network interface
4017 * @netdev: network interface device structure
4018 *
4019 * The close entry point is called when an interface is de-activated
4020 * by the OS. The hardware is still under the driver's control, but
4021 * this netdev interface is disabled.
4022 *
4023 * Returns 0, this is not allowed to fail
4024 **/
4025static int i40e_close(struct net_device *netdev)
4026{
4027 struct i40e_netdev_priv *np = netdev_priv(netdev);
4028 struct i40e_vsi *vsi = np->vsi;
4029
4030 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4031 return 0;
4032
4033 i40e_down(vsi);
4034 i40e_vsi_free_irq(vsi);
4035
4036 i40e_vsi_free_tx_resources(vsi);
4037 i40e_vsi_free_rx_resources(vsi);
4038
4039 return 0;
4040}
4041
4042/**
4043 * i40e_do_reset - Start a PF or Core Reset sequence
4044 * @pf: board private structure
4045 * @reset_flags: which reset is requested
4046 *
4047 * The essential difference in resets is that the PF Reset
4048 * doesn't clear the packet buffers, doesn't reset the PE
4049 * firmware, and doesn't bother the other PFs on the chip.
4050 **/
4051void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4052{
4053 u32 val;
4054
4055 WARN_ON(in_interrupt());
4056
4057 /* do the biggest reset indicated */
4058 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4059
4060 /* Request a Global Reset
4061 *
4062 * This will start the chip's countdown to the actual full
4063 * chip reset event, and a warning interrupt to be sent
4064 * to all PFs, including the requestor. Our handler
4065 * for the warning interrupt will deal with the shutdown
4066 * and recovery of the switch setup.
4067 */
4068 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4069 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4070 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4071 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4072
4073 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4074
4075 /* Request a Core Reset
4076 *
4077 * Same as Global Reset, except does *not* include the MAC/PHY
4078 */
4079 dev_info(&pf->pdev->dev, "CoreR requested\n");
4080 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4081 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4082 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4083 i40e_flush(&pf->hw);
4084
7823fe34
SN		 4085 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4086
4087 /* Request a Firmware Reset
4088 *
4089 * Same as Global reset, plus restarting the
4090 * embedded firmware engine.
4091 */
4092 /* enable EMP Reset */
4093 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4094 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4095 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4096
4097 /* force the reset */
4098 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4099 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4100 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4101 i40e_flush(&pf->hw);
4102
41c445ff
JB		 4103 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4104
4105 /* Request a PF Reset
4106 *
4107 * Resets only the PF-specific registers
4108 *
4109 * This goes directly to the tear-down and rebuild of
4110 * the switch, since we need to do all the recovery as
4111 * for the Core Reset.
4112 */
4113 dev_info(&pf->pdev->dev, "PFR requested\n");
4114 i40e_handle_reset_warning(pf);
4115
4116 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4117 int v;
4118
4119 /* Find the VSI(s) that requested a re-init */
4120 dev_info(&pf->pdev->dev,
4121 "VSI reinit requested\n");
4122 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4123 struct i40e_vsi *vsi = pf->vsi[v];
4124 if (vsi != NULL &&
4125 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4126 i40e_vsi_reinit_locked(pf->vsi[v]);
4127 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4128 }
4129 }
4130
4131 /* no further action needed, so return now */
4132 return;
4133 } else {
4134 dev_info(&pf->pdev->dev,
4135 "bad reset request 0x%08x\n", reset_flags);
4136 return;
4137 }
4138}
4139
23326186
ASJ		 4140/**
4141 * i40e_do_reset_safe - Protected reset path for userland calls.
4142 * @pf: board private structure
4143 * @reset_flags: which reset is requested
4144 *
4145 **/
4146void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4147{
4148 rtnl_lock();
4149 i40e_do_reset(pf, reset_flags);
4150 rtnl_unlock();
4151}
4152
41c445ff
JB		 4153/**
4154 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4155 * @pf: board private structure
4156 * @e: event info posted on ARQ
4157 *
4158 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4159 * and VF queues
4160 **/
4161static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4162 struct i40e_arq_event_info *e)
4163{
4164 struct i40e_aqc_lan_overflow *data =
4165 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4166 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4167 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4168 struct i40e_hw *hw = &pf->hw;
4169 struct i40e_vf *vf;
4170 u16 vf_id;
4171
4172 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4173 __func__, queue, qtx_ctl);
4174
4175 /* Queue belongs to VF, find the VF and issue VF reset */
4176 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4177 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4178 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4179 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4180 vf_id -= hw->func_caps.vf_base_id;
4181 vf = &pf->vf[vf_id];
4182 i40e_vc_notify_vf_reset(vf);
4183 /* Allow VF to process pending reset notification */
4184 msleep(20);
4185 i40e_reset_vf(vf, false);
4186 }
4187}
4188
4189/**
4190 * i40e_service_event_complete - Finish up the service event
4191 * @pf: board private structure
4192 **/
4193static void i40e_service_event_complete(struct i40e_pf *pf)
4194{
4195 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4196
4197 /* flush memory to make sure state is correct before next watchog */
4198 smp_mb__before_clear_bit();
4199 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4200}
4201
4202/**
4203 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4204 * @pf: board private structure
4205 **/
4206static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4207{
4208 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4209 return;
4210
4211 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4212
4213 /* if interface is down do nothing */
4214 if (test_bit(__I40E_DOWN, &pf->state))
4215 return;
4216}
4217
4218/**
4219 * i40e_vsi_link_event - notify VSI of a link event
4220 * @vsi: vsi to be notified
4221 * @link_up: link up or down
4222 **/
4223static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4224{
4225 if (!vsi)
4226 return;
4227
4228 switch (vsi->type) {
4229 case I40E_VSI_MAIN:
4230 if (!vsi->netdev || !vsi->netdev_registered)
4231 break;
4232
4233 if (link_up) {
4234 netif_carrier_on(vsi->netdev);
4235 netif_tx_wake_all_queues(vsi->netdev);
4236 } else {
4237 netif_carrier_off(vsi->netdev);
4238 netif_tx_stop_all_queues(vsi->netdev);
4239 }
4240 break;
4241
4242 case I40E_VSI_SRIOV:
4243 break;
4244
4245 case I40E_VSI_VMDQ2:
4246 case I40E_VSI_CTRL:
4247 case I40E_VSI_MIRROR:
4248 default:
4249 /* there is no notification for other VSIs */
4250 break;
4251 }
4252}
4253
4254/**
4255 * i40e_veb_link_event - notify elements on the veb of a link event
4256 * @veb: veb to be notified
4257 * @link_up: link up or down
4258 **/
4259static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4260{
4261 struct i40e_pf *pf;
4262 int i;
4263
4264 if (!veb || !veb->pf)
4265 return;
4266 pf = veb->pf;
4267
4268 /* depth first... */
4269 for (i = 0; i < I40E_MAX_VEB; i++)
4270 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4271 i40e_veb_link_event(pf->veb[i], link_up);
4272
4273 /* ... now the local VSIs */
4274 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4275 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4276 i40e_vsi_link_event(pf->vsi[i], link_up);
4277}
4278
4279/**
4280 * i40e_link_event - Update netif_carrier status
4281 * @pf: board private structure
4282 **/
4283static void i40e_link_event(struct i40e_pf *pf)
4284{
4285 bool new_link, old_link;
4286
4287 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4288 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4289
4290 if (new_link == old_link)
4291 return;
4292
6d779b41
AS		 4293 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4294 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4295 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4296
4297 /* Notify the base of the switch tree connected to
4298 * the link. Floating VEBs are not notified.
4299 */
4300 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4301 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4302 else
4303 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4304
4305 if (pf->vf)
4306 i40e_vc_notify_link_state(pf);
4307}
4308
4309/**
4310 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4311 * @pf: board private structure
4312 *
4313 * Set the per-queue flags to request a check for stuck queues in the irq
4314 * clean functions, then force interrupts to be sure the irq clean is called.
4315 **/
4316static void i40e_check_hang_subtask(struct i40e_pf *pf)
4317{
4318 int i, v;
4319
4320 /* If we're down or resetting, just bail */
4321 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4322 return;
4323
4324 /* for each VSI/netdev
4325 * for each Tx queue
4326 * set the check flag
4327 * for each q_vector
4328 * force an interrupt
4329 */
4330 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4331 struct i40e_vsi *vsi = pf->vsi[v];
4332 int armed = 0;
4333
4334 if (!pf->vsi[v] ||
4335 test_bit(__I40E_DOWN, &vsi->state) ||
4336 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4337 continue;
4338
4339 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4340 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4341 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4342 &vsi->tx_rings[i]->state))
41c445ff
JB		 4343 armed++;
4344 }
4345
4346 if (armed) {
4347 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4348 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4349 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4350 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4351 } else {
4352 u16 vec = vsi->base_vector - 1;
4353 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4354 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4355 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4356 wr32(&vsi->back->hw,
4357 I40E_PFINT_DYN_CTLN(vec), val);
4358 }
4359 i40e_flush(&vsi->back->hw);
4360 }
4361 }
4362}
4363
4364/**
4365 * i40e_watchdog_subtask - Check and bring link up
4366 * @pf: board private structure
4367 **/
4368static void i40e_watchdog_subtask(struct i40e_pf *pf)
4369{
4370 int i;
4371
4372 /* if interface is down do nothing */
4373 if (test_bit(__I40E_DOWN, &pf->state) ||
4374 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4375 return;
4376
4377 /* Update the stats for active netdevs so the network stack
4378 * can look at updated numbers whenever it cares to
4379 */
4380 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4381 if (pf->vsi[i] && pf->vsi[i]->netdev)
4382 i40e_update_stats(pf->vsi[i]);
4383
4384 /* Update the stats for the active switching components */
4385 for (i = 0; i < I40E_MAX_VEB; i++)
4386 if (pf->veb[i])
4387 i40e_update_veb_stats(pf->veb[i]);
4388}
4389
4390/**
4391 * i40e_reset_subtask - Set up for resetting the device and driver
4392 * @pf: board private structure
4393 **/
4394static void i40e_reset_subtask(struct i40e_pf *pf)
4395{
4396 u32 reset_flags = 0;
4397
23326186 4398 rtnl_lock();
41c445ff
JB		 4399 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4400 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4401 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4402 }
4403 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4404 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4405 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4406 }
4407 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4408 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4409 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4410 }
4411 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4412 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4413 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4414 }
4415
4416 /* If there's a recovery already waiting, it takes
4417 * precedence before starting a new reset sequence.
4418 */
4419 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4420 i40e_handle_reset_warning(pf);
23326186 4421 goto unlock;
41c445ff
JB		 4422 }
4423
4424 /* If we're already down or resetting, just bail */
4425 if (reset_flags &&
4426 !test_bit(__I40E_DOWN, &pf->state) &&
4427 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4428 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4429
4430unlock:
4431 rtnl_unlock();
41c445ff
JB		 4432}
4433
4434/**
4435 * i40e_handle_link_event - Handle link event
4436 * @pf: board private structure
4437 * @e: event info posted on ARQ
4438 **/
4439static void i40e_handle_link_event(struct i40e_pf *pf,
4440 struct i40e_arq_event_info *e)
4441{
4442 struct i40e_hw *hw = &pf->hw;
4443 struct i40e_aqc_get_link_status *status =
4444 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4445 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4446
4447 /* save off old link status information */
4448 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4449 sizeof(pf->hw.phy.link_info_old));
4450
4451 /* update link status */
4452 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4453 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4454 hw_link_info->link_info = status->link_info;
4455 hw_link_info->an_info = status->an_info;
4456 hw_link_info->ext_info = status->ext_info;
4457 hw_link_info->lse_enable =
4458 le16_to_cpu(status->command_flags) &
4459 I40E_AQ_LSE_ENABLE;
4460
4461 /* process the event */
4462 i40e_link_event(pf);
4463
4464 /* Do a new status request to re-enable LSE reporting
4465 * and load new status information into the hw struct,
4466 * then see if the status changed while processing the
4467 * initial event.
4468 */
4469 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4470 i40e_link_event(pf);
4471}
4472
4473/**
4474 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4475 * @pf: board private structure
4476 **/
4477static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4478{
4479 struct i40e_arq_event_info event;
4480 struct i40e_hw *hw = &pf->hw;
4481 u16 pending, i = 0;
4482 i40e_status ret;
4483 u16 opcode;
4484 u32 val;
4485
4486 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4487 return;
4488
3197ce22 4489 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4490 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4491 if (!event.msg_buf)
4492 return;
4493
4494 do {
2f019123 4495 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4496 ret = i40e_clean_arq_element(hw, &event, &pending);
4497 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4498 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4499 break;
4500 } else if (ret) {
4501 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4502 break;
4503 }
4504
4505 opcode = le16_to_cpu(event.desc.opcode);
4506 switch (opcode) {
4507
4508 case i40e_aqc_opc_get_link_status:
4509 i40e_handle_link_event(pf, &event);
4510 break;
4511 case i40e_aqc_opc_send_msg_to_pf:
4512 ret = i40e_vc_process_vf_msg(pf,
4513 le16_to_cpu(event.desc.retval),
4514 le32_to_cpu(event.desc.cookie_high),
4515 le32_to_cpu(event.desc.cookie_low),
4516 event.msg_buf,
4517 event.msg_size);
4518 break;
4519 case i40e_aqc_opc_lldp_update_mib:
4520 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4521 break;
4522 case i40e_aqc_opc_event_lan_overflow:
4523 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4524 i40e_handle_lan_overflow_event(pf, &event);
4525 break;
0467bc91
SN		 4526 case i40e_aqc_opc_send_msg_to_peer:
4527 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
4528 break;
41c445ff
JB		 4529 default:
4530 dev_info(&pf->pdev->dev,
0467bc91
SN		 4531 "ARQ Error: Unknown event 0x%04x received\n",
4532 opcode);
41c445ff
JB		 4533 break;
4534 }
4535 } while (pending && (i++ < pf->adminq_work_limit));
4536
4537 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4538 /* re-enable Admin queue interrupt cause */
4539 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4540 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4541 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4542 i40e_flush(hw);
4543
4544 kfree(event.msg_buf);
4545}
4546
4547/**
4548 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4549 * @veb: pointer to the VEB instance
4550 *
4551 * This is a recursive function that first builds the attached VSIs then
4552 * recurses in to build the next layer of VEB. We track the connections
4553 * through our own index numbers because the seid's from the HW could
4554 * change across the reset.
4555 **/
4556static int i40e_reconstitute_veb(struct i40e_veb *veb)
4557{
4558 struct i40e_vsi *ctl_vsi = NULL;
4559 struct i40e_pf *pf = veb->pf;
4560 int v, veb_idx;
4561 int ret;
4562
4563 /* build VSI that owns this VEB, temporarily attached to base VEB */
4564 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4565 if (pf->vsi[v] &&
4566 pf->vsi[v]->veb_idx == veb->idx &&
4567 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4568 ctl_vsi = pf->vsi[v];
4569 break;
4570 }
4571 }
4572 if (!ctl_vsi) {
4573 dev_info(&pf->pdev->dev,
4574 "missing owner VSI for veb_idx %d\n", veb->idx);
4575 ret = -ENOENT;
4576 goto end_reconstitute;
4577 }
4578 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4579 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4580 ret = i40e_add_vsi(ctl_vsi);
4581 if (ret) {
4582 dev_info(&pf->pdev->dev,
4583 "rebuild of owner VSI failed: %d\n", ret);
4584 goto end_reconstitute;
4585 }
4586 i40e_vsi_reset_stats(ctl_vsi);
4587
4588 /* create the VEB in the switch and move the VSI onto the VEB */
4589 ret = i40e_add_veb(veb, ctl_vsi);
4590 if (ret)
4591 goto end_reconstitute;
4592
4593 /* create the remaining VSIs attached to this VEB */
4594 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4595 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4596 continue;
4597
4598 if (pf->vsi[v]->veb_idx == veb->idx) {
4599 struct i40e_vsi *vsi = pf->vsi[v];
4600 vsi->uplink_seid = veb->seid;
4601 ret = i40e_add_vsi(vsi);
4602 if (ret) {
4603 dev_info(&pf->pdev->dev,
4604 "rebuild of vsi_idx %d failed: %d\n",
4605 v, ret);
4606 goto end_reconstitute;
4607 }
4608 i40e_vsi_reset_stats(vsi);
4609 }
4610 }
4611
4612 /* create any VEBs attached to this VEB - RECURSION */
4613 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4614 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4615 pf->veb[veb_idx]->uplink_seid = veb->seid;
4616 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4617 if (ret)
4618 break;
4619 }
4620 }
4621
4622end_reconstitute:
4623 return ret;
4624}
4625
4626/**
4627 * i40e_get_capabilities - get info about the HW
4628 * @pf: the PF struct
4629 **/
4630static int i40e_get_capabilities(struct i40e_pf *pf)
4631{
4632 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4633 u16 data_size;
4634 int buf_len;
4635 int err;
4636
4637 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4638 do {
4639 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4640 if (!cap_buf)
4641 return -ENOMEM;
4642
4643 /* this loads the data into the hw struct for us */
4644 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4645 &data_size,
4646 i40e_aqc_opc_list_func_capabilities,
4647 NULL);
4648 /* data loaded, buffer no longer needed */
4649 kfree(cap_buf);
4650
4651 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4652 /* retry with a larger buffer */
4653 buf_len = data_size;
4654 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4655 dev_info(&pf->pdev->dev,
4656 "capability discovery failed: aq=%d\n",
4657 pf->hw.aq.asq_last_status);
4658 return -ENODEV;
4659 }
4660 } while (err);
4661
2050bc65 4662 if (pf->hw.revision_id == 0 && (pf->flags & I40E_FLAG_MFP_ENABLED)) {
7134f9ce
JB		 4663 pf->hw.func_caps.num_msix_vectors += 1;
4664 pf->hw.func_caps.num_tx_qp =
4665 min_t(int, pf->hw.func_caps.num_tx_qp,
4666 I40E_MAX_NPAR_QPS);
4667 }
4668
41c445ff
JB		 4669 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4670 dev_info(&pf->pdev->dev,
4671 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4672 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4673 pf->hw.func_caps.num_msix_vectors,
4674 pf->hw.func_caps.num_msix_vectors_vf,
4675 pf->hw.func_caps.fd_filters_guaranteed,
4676 pf->hw.func_caps.fd_filters_best_effort,
4677 pf->hw.func_caps.num_tx_qp,
4678 pf->hw.func_caps.num_vsis);
4679
7134f9ce
JB		 4680#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4681 + pf->hw.func_caps.num_vfs)
4682 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4683 dev_info(&pf->pdev->dev,
4684 "got num_vsis %d, setting num_vsis to %d\n",
4685 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4686 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4687 }
4688
41c445ff
JB		 4689 return 0;
4690}
4691
4692/**
4693 * i40e_fdir_setup - initialize the Flow Director resources
4694 * @pf: board private structure
4695 **/
4696static void i40e_fdir_setup(struct i40e_pf *pf)
4697{
4698 struct i40e_vsi *vsi;
4699 bool new_vsi = false;
4700 int err, i;
4701
958a3e3b
SN		 4702 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4703 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4704 return;
4705
4706 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4707
4708 /* find existing or make new FDIR VSI */
4709 vsi = NULL;
4710 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4711 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4712 vsi = pf->vsi[i];
4713 if (!vsi) {
4714 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4715 if (!vsi) {
4716 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4717 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4718 return;
4719 }
4720 new_vsi = true;
4721 }
4722 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4723 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4724
4725 err = i40e_vsi_setup_tx_resources(vsi);
4726 if (!err)
4727 err = i40e_vsi_setup_rx_resources(vsi);
4728 if (!err)
4729 err = i40e_vsi_configure(vsi);
4730 if (!err && new_vsi) {
4731 char int_name[IFNAMSIZ + 9];
4732 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4733 dev_driver_string(&pf->pdev->dev));
4734 err = i40e_vsi_request_irq(vsi, int_name);
4735 }
4736 if (!err)
4737 err = i40e_up_complete(vsi);
4738
4739 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4740}
4741
4742/**
4743 * i40e_fdir_teardown - release the Flow Director resources
4744 * @pf: board private structure
4745 **/
4746static void i40e_fdir_teardown(struct i40e_pf *pf)
4747{
4748 int i;
4749
4750 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4751 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4752 i40e_vsi_release(pf->vsi[i]);
4753 break;
4754 }
4755 }
4756}
4757
4758/**
f650a38b 4759 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4760 * @pf: board private structure
4761 *
f650a38b
ASJ		 4762 * Close up the VFs and other things in prep for pf Reset.
4763 **/
4764static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4765{
41c445ff
JB		 4766 struct i40e_hw *hw = &pf->hw;
4767 i40e_status ret;
4768 u32 v;
4769
4770 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4771 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4772 return 0;
41c445ff
JB		 4773
4774 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4775
37f0be6d
ASJ		 4776 if (i40e_check_asq_alive(hw))
4777 i40e_vc_notify_reset(pf);
41c445ff
JB		 4778
4779 /* quiesce the VSIs and their queues that are not already DOWN */
4780 i40e_pf_quiesce_all_vsi(pf);
4781
4782 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4783 if (pf->vsi[v])
4784 pf->vsi[v]->seid = 0;
4785 }
4786
4787 i40e_shutdown_adminq(&pf->hw);
4788
f650a38b
ASJ		 4789 /* call shutdown HMC */
4790 ret = i40e_shutdown_lan_hmc(hw);
4791 if (ret) {
4792 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4793 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4794 }
4795 return ret;
4796}
4797
4798/**
4dda12e6 4799 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 4800 * @pf: board private structure
bc7d338f 4801 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4802 **/
bc7d338f 4803static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4804{
4805 struct i40e_driver_version dv;
4806 struct i40e_hw *hw = &pf->hw;
4807 i40e_status ret;
4808 u32 v;
4809
41c445ff
JB		 4810 /* Now we wait for GRST to settle out.
4811 * We don't have to delete the VEBs or VSIs from the hw switch
4812 * because the reset will make them disappear.
4813 */
4814 ret = i40e_pf_reset(hw);
4815 if (ret)
4816 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4817 pf->pfr_count++;
4818
4819 if (test_bit(__I40E_DOWN, &pf->state))
4820 goto end_core_reset;
4821 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4822
4823 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4824 ret = i40e_init_adminq(&pf->hw);
4825 if (ret) {
4826 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4827 goto end_core_reset;
4828 }
4829
4830 ret = i40e_get_capabilities(pf);
4831 if (ret) {
4832 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4833 ret);
4834 goto end_core_reset;
4835 }
4836
41c445ff
JB		 4837 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4838 hw->func_caps.num_rx_qp,
4839 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4840 if (ret) {
4841 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4842 goto end_core_reset;
4843 }
4844 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4845 if (ret) {
4846 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4847 goto end_core_reset;
4848 }
4849
4850 /* do basic switch setup */
bc7d338f 4851 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4852 if (ret)
4853 goto end_core_reset;
4854
4855 /* Rebuild the VSIs and VEBs that existed before reset.
4856 * They are still in our local switch element arrays, so only
4857 * need to rebuild the switch model in the HW.
4858 *
4859 * If there were VEBs but the reconstitution failed, we'll try
4860 * try to recover minimal use by getting the basic PF VSI working.
4861 */
4862 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4863 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4864 /* find the one VEB connected to the MAC, and find orphans */
4865 for (v = 0; v < I40E_MAX_VEB; v++) {
4866 if (!pf->veb[v])
4867 continue;
4868
4869 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4870 pf->veb[v]->uplink_seid == 0) {
4871 ret = i40e_reconstitute_veb(pf->veb[v]);
4872
4873 if (!ret)
4874 continue;
4875
4876 /* If Main VEB failed, we're in deep doodoo,
4877 * so give up rebuilding the switch and set up
4878 * for minimal rebuild of PF VSI.
4879 * If orphan failed, we'll report the error
4880 * but try to keep going.
4881 */
4882 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4883 dev_info(&pf->pdev->dev,
4884 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4885 ret);
4886 pf->vsi[pf->lan_vsi]->uplink_seid
4887 = pf->mac_seid;
4888 break;
4889 } else if (pf->veb[v]->uplink_seid == 0) {
4890 dev_info(&pf->pdev->dev,
4891 "rebuild of orphan VEB failed: %d\n",
4892 ret);
4893 }
4894 }
4895 }
4896 }
4897
4898 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4899 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4900 /* no VEB, so rebuild only the Main VSI */
4901 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4902 if (ret) {
4903 dev_info(&pf->pdev->dev,
4904 "rebuild of Main VSI failed: %d\n", ret);
4905 goto end_core_reset;
4906 }
4907 }
4908
4909 /* reinit the misc interrupt */
4910 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4911 ret = i40e_setup_misc_vector(pf);
4912
4913 /* restart the VSIs that were rebuilt and running before the reset */
4914 i40e_pf_unquiesce_all_vsi(pf);
4915
4916 /* tell the firmware that we're starting */
4917 dv.major_version = DRV_VERSION_MAJOR;
4918 dv.minor_version = DRV_VERSION_MINOR;
4919 dv.build_version = DRV_VERSION_BUILD;
4920 dv.subbuild_version = 0;
4921 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4922
4923 dev_info(&pf->pdev->dev, "PF reset done\n");
4924
4925end_core_reset:
4926 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4927}
4928
f650a38b
ASJ		 4929/**
4930 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4931 * @pf: board private structure
4932 *
4933 * Close up the VFs and other things in prep for a Core Reset,
4934 * then get ready to rebuild the world.
4935 **/
4936static void i40e_handle_reset_warning(struct i40e_pf *pf)
4937{
4938 i40e_status ret;
4939
4940 ret = i40e_prep_for_reset(pf);
4941 if (!ret)
bc7d338f 4942 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4943}
4944
41c445ff
JB		 4945/**
4946 * i40e_handle_mdd_event
4947 * @pf: pointer to the pf structure
4948 *
4949 * Called from the MDD irq handler to identify possibly malicious vfs
4950 **/
4951static void i40e_handle_mdd_event(struct i40e_pf *pf)
4952{
4953 struct i40e_hw *hw = &pf->hw;
4954 bool mdd_detected = false;
4955 struct i40e_vf *vf;
4956 u32 reg;
4957 int i;
4958
4959 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
4960 return;
4961
4962 /* find what triggered the MDD event */
4963 reg = rd32(hw, I40E_GL_MDET_TX);
4964 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4965 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
4966 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
4967 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
4968 >> I40E_GL_MDET_TX_EVENT_SHIFT;
4969 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
4970 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
4971 dev_info(&pf->pdev->dev,
4972 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
4973 event, queue, func);
4974 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
4975 mdd_detected = true;
4976 }
4977 reg = rd32(hw, I40E_GL_MDET_RX);
4978 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4979 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
4980 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
4981 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
4982 >> I40E_GL_MDET_RX_EVENT_SHIFT;
4983 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
4984 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
4985 dev_info(&pf->pdev->dev,
4986 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
4987 event, queue, func);
4988 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
4989 mdd_detected = true;
4990 }
4991
4992 /* see if one of the VFs needs its hand slapped */
4993 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
4994 vf = &(pf->vf[i]);
4995 reg = rd32(hw, I40E_VP_MDET_TX(i));
4996 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
4997 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
4998 vf->num_mdd_events++;
4999 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5000 }
5001
5002 reg = rd32(hw, I40E_VP_MDET_RX(i));
5003 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5004 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5005 vf->num_mdd_events++;
5006 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5007 }
5008
5009 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5010 dev_info(&pf->pdev->dev,
5011 "Too many MDD events on VF %d, disabled\n", i);
5012 dev_info(&pf->pdev->dev,
5013 "Use PF Control I/F to re-enable the VF\n");
5014 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5015 }
5016 }
5017
5018 /* re-enable mdd interrupt cause */
5019 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5020 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5021 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5022 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5023 i40e_flush(hw);
5024}
5025
a1c9a9d9
JK		 5026#ifdef CONFIG_I40E_VXLAN
5027/**
5028 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5029 * @pf: board private structure
5030 **/
5031static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5032{
5033 const int vxlan_hdr_qwords = 4;
5034 struct i40e_hw *hw = &pf->hw;
5035 i40e_status ret;
5036 u8 filter_index;
5037 __be16 port;
5038 int i;
5039
5040 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5041 return;
5042
5043 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5044
5045 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5046 if (pf->pending_vxlan_bitmap & (1 << i)) {
5047 pf->pending_vxlan_bitmap &= ~(1 << i);
5048 port = pf->vxlan_ports[i];
5049 ret = port ?
5050 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5051 vxlan_hdr_qwords,
5052 I40E_AQC_TUNNEL_TYPE_VXLAN,
5053 &filter_index, NULL)
5054 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5055
5056 if (ret) {
5057 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5058 port ? "adding" : "deleting",
5059 ntohs(port), port ? i : i);
5060
5061 pf->vxlan_ports[i] = 0;
5062 } else {
5063 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5064 port ? "Added" : "Deleted",
5065 ntohs(port), port ? i : filter_index);
5066 }
5067 }
5068 }
5069}
5070
5071#endif
41c445ff
JB		 5072/**
5073 * i40e_service_task - Run the driver's async subtasks
5074 * @work: pointer to work_struct containing our data
5075 **/
5076static void i40e_service_task(struct work_struct *work)
5077{
5078 struct i40e_pf *pf = container_of(work,
5079 struct i40e_pf,
5080 service_task);
5081 unsigned long start_time = jiffies;
5082
5083 i40e_reset_subtask(pf);
5084 i40e_handle_mdd_event(pf);
5085 i40e_vc_process_vflr_event(pf);
5086 i40e_watchdog_subtask(pf);
5087 i40e_fdir_reinit_subtask(pf);
5088 i40e_check_hang_subtask(pf);
5089 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5090#ifdef CONFIG_I40E_VXLAN
5091 i40e_sync_vxlan_filters_subtask(pf);
5092#endif
41c445ff
JB		 5093 i40e_clean_adminq_subtask(pf);
5094
5095 i40e_service_event_complete(pf);
5096
5097 /* If the tasks have taken longer than one timer cycle or there
5098 * is more work to be done, reschedule the service task now
5099 * rather than wait for the timer to tick again.
5100 */
5101 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5102 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5103 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5104 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5105 i40e_service_event_schedule(pf);
5106}
5107
5108/**
5109 * i40e_service_timer - timer callback
5110 * @data: pointer to PF struct
5111 **/
5112static void i40e_service_timer(unsigned long data)
5113{
5114 struct i40e_pf *pf = (struct i40e_pf *)data;
5115
5116 mod_timer(&pf->service_timer,
5117 round_jiffies(jiffies + pf->service_timer_period));
5118 i40e_service_event_schedule(pf);
5119}
5120
5121/**
5122 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5123 * @vsi: the VSI being configured
5124 **/
5125static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5126{
5127 struct i40e_pf *pf = vsi->back;
5128
5129 switch (vsi->type) {
5130 case I40E_VSI_MAIN:
5131 vsi->alloc_queue_pairs = pf->num_lan_qps;
5132 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5133 I40E_REQ_DESCRIPTOR_MULTIPLE);
5134 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5135 vsi->num_q_vectors = pf->num_lan_msix;
5136 else
5137 vsi->num_q_vectors = 1;
5138
5139 break;
5140
5141 case I40E_VSI_FDIR:
5142 vsi->alloc_queue_pairs = 1;
5143 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5144 I40E_REQ_DESCRIPTOR_MULTIPLE);
5145 vsi->num_q_vectors = 1;
5146 break;
5147
5148 case I40E_VSI_VMDQ2:
5149 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5150 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5151 I40E_REQ_DESCRIPTOR_MULTIPLE);
5152 vsi->num_q_vectors = pf->num_vmdq_msix;
5153 break;
5154
5155 case I40E_VSI_SRIOV:
5156 vsi->alloc_queue_pairs = pf->num_vf_qps;
5157 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5158 I40E_REQ_DESCRIPTOR_MULTIPLE);
5159 break;
5160
5161 default:
5162 WARN_ON(1);
5163 return -ENODATA;
5164 }
5165
5166 return 0;
5167}
5168
f650a38b
ASJ		 5169/**
5170 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5171 * @type: VSI pointer
bc7d338f 5172 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5173 *
5174 * On error: returns error code (negative)
5175 * On success: returns 0
5176 **/
bc7d338f 5177static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5178{
5179 int size;
5180 int ret = 0;
5181
ac6c5e3d 5182 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5183 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5184 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5185 if (!vsi->tx_rings)
5186 return -ENOMEM;
f650a38b
ASJ		 5187 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5188
bc7d338f
ASJ		 5189 if (alloc_qvectors) {
5190 /* allocate memory for q_vector pointers */
5191 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5192 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5193 if (!vsi->q_vectors) {
5194 ret = -ENOMEM;
5195 goto err_vectors;
5196 }
f650a38b
ASJ		 5197 }
5198 return ret;
5199
5200err_vectors:
5201 kfree(vsi->tx_rings);
5202 return ret;
5203}
5204
41c445ff
JB		 5205/**
5206 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5207 * @pf: board private structure
5208 * @type: type of VSI
5209 *
5210 * On error: returns error code (negative)
5211 * On success: returns vsi index in PF (positive)
5212 **/
5213static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5214{
5215 int ret = -ENODEV;
5216 struct i40e_vsi *vsi;
5217 int vsi_idx;
5218 int i;
5219
5220 /* Need to protect the allocation of the VSIs at the PF level */
5221 mutex_lock(&pf->switch_mutex);
5222
5223 /* VSI list may be fragmented if VSI creation/destruction has
5224 * been happening. We can afford to do a quick scan to look
5225 * for any free VSIs in the list.
5226 *
5227 * find next empty vsi slot, looping back around if necessary
5228 */
5229 i = pf->next_vsi;
5230 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5231 i++;
5232 if (i >= pf->hw.func_caps.num_vsis) {
5233 i = 0;
5234 while (i < pf->next_vsi && pf->vsi[i])
5235 i++;
5236 }
5237
5238 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5239 vsi_idx = i; /* Found one! */
5240 } else {
5241 ret = -ENODEV;
493fb300 5242 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5243 }
5244 pf->next_vsi = ++i;
5245
5246 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5247 if (!vsi) {
5248 ret = -ENOMEM;
493fb300 5249 goto unlock_pf;
41c445ff
JB		 5250 }
5251 vsi->type = type;
5252 vsi->back = pf;
5253 set_bit(__I40E_DOWN, &vsi->state);
5254 vsi->flags = 0;
5255 vsi->idx = vsi_idx;
5256 vsi->rx_itr_setting = pf->rx_itr_default;
5257 vsi->tx_itr_setting = pf->tx_itr_default;
5258 vsi->netdev_registered = false;
5259 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5260 INIT_LIST_HEAD(&vsi->mac_filter_list);
5261
9f65e15b
AD		 5262 ret = i40e_set_num_rings_in_vsi(vsi);
5263 if (ret)
5264 goto err_rings;
5265
bc7d338f 5266 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5267 if (ret)
9f65e15b 5268 goto err_rings;
493fb300 5269
41c445ff
JB		 5270 /* Setup default MSIX irq handler for VSI */
5271 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5272
5273 pf->vsi[vsi_idx] = vsi;
5274 ret = vsi_idx;
493fb300
AD		 5275 goto unlock_pf;
5276
9f65e15b 5277err_rings:
493fb300
AD		 5278 pf->next_vsi = i - 1;
5279 kfree(vsi);
5280unlock_pf:
41c445ff
JB		 5281 mutex_unlock(&pf->switch_mutex);
5282 return ret;
5283}
5284
f650a38b
ASJ		 5285/**
5286 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5287 * @type: VSI pointer
bc7d338f 5288 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5289 *
5290 * On error: returns error code (negative)
5291 * On success: returns 0
5292 **/
bc7d338f 5293static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5294{
5295 /* free the ring and vector containers */
bc7d338f
ASJ		 5296 if (free_qvectors) {
5297 kfree(vsi->q_vectors);
5298 vsi->q_vectors = NULL;
5299 }
f650a38b
ASJ		 5300 kfree(vsi->tx_rings);
5301 vsi->tx_rings = NULL;
5302 vsi->rx_rings = NULL;
5303}
5304
41c445ff
JB		 5305/**
5306 * i40e_vsi_clear - Deallocate the VSI provided
5307 * @vsi: the VSI being un-configured
5308 **/
5309static int i40e_vsi_clear(struct i40e_vsi *vsi)
5310{
5311 struct i40e_pf *pf;
5312
5313 if (!vsi)
5314 return 0;
5315
5316 if (!vsi->back)
5317 goto free_vsi;
5318 pf = vsi->back;
5319
5320 mutex_lock(&pf->switch_mutex);
5321 if (!pf->vsi[vsi->idx]) {
5322 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5323 vsi->idx, vsi->idx, vsi, vsi->type);
5324 goto unlock_vsi;
5325 }
5326
5327 if (pf->vsi[vsi->idx] != vsi) {
5328 dev_err(&pf->pdev->dev,
5329 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5330 pf->vsi[vsi->idx]->idx,
5331 pf->vsi[vsi->idx],
5332 pf->vsi[vsi->idx]->type,
5333 vsi->idx, vsi, vsi->type);
5334 goto unlock_vsi;
5335 }
5336
5337 /* updates the pf for this cleared vsi */
5338 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5339 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5340
bc7d338f 5341 i40e_vsi_free_arrays(vsi, true);
493fb300 5342
41c445ff
JB		 5343 pf->vsi[vsi->idx] = NULL;
5344 if (vsi->idx < pf->next_vsi)
5345 pf->next_vsi = vsi->idx;
5346
5347unlock_vsi:
5348 mutex_unlock(&pf->switch_mutex);
5349free_vsi:
5350 kfree(vsi);
5351
5352 return 0;
5353}
5354
9f65e15b
AD		 5355/**
5356 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5357 * @vsi: the VSI being cleaned
5358 **/
be1d5eea 5359static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5360{
5361 int i;
5362
8e9dca53 5363 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5364 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5365 kfree_rcu(vsi->tx_rings[i], rcu);
5366 vsi->tx_rings[i] = NULL;
5367 vsi->rx_rings[i] = NULL;
5368 }
be1d5eea 5369 }
9f65e15b
AD		 5370}
5371
41c445ff
JB		 5372/**
5373 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5374 * @vsi: the VSI being configured
5375 **/
5376static int i40e_alloc_rings(struct i40e_vsi *vsi)
5377{
5378 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5379 int i;
5380
41c445ff 5381 /* Set basic values in the rings to be used later during open() */
d7397644 5382 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5383 struct i40e_ring *tx_ring;
5384 struct i40e_ring *rx_ring;
5385
ac6c5e3d 5386 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5387 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5388 if (!tx_ring)
5389 goto err_out;
41c445ff
JB		 5390
5391 tx_ring->queue_index = i;
5392 tx_ring->reg_idx = vsi->base_queue + i;
5393 tx_ring->ring_active = false;
5394 tx_ring->vsi = vsi;
5395 tx_ring->netdev = vsi->netdev;
5396 tx_ring->dev = &pf->pdev->dev;
5397 tx_ring->count = vsi->num_desc;
5398 tx_ring->size = 0;
5399 tx_ring->dcb_tc = 0;
9f65e15b 5400 vsi->tx_rings[i] = tx_ring;
41c445ff 5401
9f65e15b 5402 rx_ring = &tx_ring[1];
41c445ff
JB		 5403 rx_ring->queue_index = i;
5404 rx_ring->reg_idx = vsi->base_queue + i;
5405 rx_ring->ring_active = false;
5406 rx_ring->vsi = vsi;
5407 rx_ring->netdev = vsi->netdev;
5408 rx_ring->dev = &pf->pdev->dev;
5409 rx_ring->count = vsi->num_desc;
5410 rx_ring->size = 0;
5411 rx_ring->dcb_tc = 0;
5412 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5413 set_ring_16byte_desc_enabled(rx_ring);
5414 else
5415 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5416 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5417 }
5418
5419 return 0;
9f65e15b
AD		 5420
5421err_out:
5422 i40e_vsi_clear_rings(vsi);
5423 return -ENOMEM;
41c445ff
JB		 5424}
5425
5426/**
5427 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5428 * @pf: board private structure
5429 * @vectors: the number of MSI-X vectors to request
5430 *
5431 * Returns the number of vectors reserved, or error
5432 **/
5433static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5434{
5435 int err = 0;
5436
5437 pf->num_msix_entries = 0;
5438 while (vectors >= I40E_MIN_MSIX) {
5439 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5440 if (err == 0) {
5441 /* good to go */
5442 pf->num_msix_entries = vectors;
5443 break;
5444 } else if (err < 0) {
5445 /* total failure */
5446 dev_info(&pf->pdev->dev,
5447 "MSI-X vector reservation failed: %d\n", err);
5448 vectors = 0;
5449 break;
5450 } else {
5451 /* err > 0 is the hint for retry */
5452 dev_info(&pf->pdev->dev,
5453 "MSI-X vectors wanted %d, retrying with %d\n",
5454 vectors, err);
5455 vectors = err;
5456 }
5457 }
5458
5459 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5460 dev_info(&pf->pdev->dev,
5461 "Couldn't get enough vectors, only %d available\n",
5462 vectors);
5463 vectors = 0;
5464 }
5465
5466 return vectors;
5467}
5468
5469/**
5470 * i40e_init_msix - Setup the MSIX capability
5471 * @pf: board private structure
5472 *
5473 * Work with the OS to set up the MSIX vectors needed.
5474 *
5475 * Returns 0 on success, negative on failure
5476 **/
5477static int i40e_init_msix(struct i40e_pf *pf)
5478{
5479 i40e_status err = 0;
5480 struct i40e_hw *hw = &pf->hw;
5481 int v_budget, i;
5482 int vec;
5483
5484 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5485 return -ENODEV;
5486
5487 /* The number of vectors we'll request will be comprised of:
5488 * - Add 1 for "other" cause for Admin Queue events, etc.
5489 * - The number of LAN queue pairs
f8ff1464
ASJ		 5490 * - Queues being used for RSS.
5491 * We don't need as many as max_rss_size vectors.
5492 * use rss_size instead in the calculation since that
5493 * is governed by number of cpus in the system.
5494 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5495 * - The number of VMDq pairs
5496 * Once we count this up, try the request.
5497 *
5498 * If we can't get what we want, we'll simplify to nearly nothing
5499 * and try again. If that still fails, we punt.
5500 */
f8ff1464 5501 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5502 pf->num_vmdq_msix = pf->num_vmdq_qps;
5503 v_budget = 1 + pf->num_lan_msix;
5504 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5505 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5506 v_budget++;
5507
5508 /* Scale down if necessary, and the rings will share vectors */
5509 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5510
5511 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5512 GFP_KERNEL);
5513 if (!pf->msix_entries)
5514 return -ENOMEM;
5515
5516 for (i = 0; i < v_budget; i++)
5517 pf->msix_entries[i].entry = i;
5518 vec = i40e_reserve_msix_vectors(pf, v_budget);
5519 if (vec < I40E_MIN_MSIX) {
5520 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5521 kfree(pf->msix_entries);
5522 pf->msix_entries = NULL;
5523 return -ENODEV;
5524
5525 } else if (vec == I40E_MIN_MSIX) {
5526 /* Adjust for minimal MSIX use */
5527 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5528 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5529 pf->num_vmdq_vsis = 0;
5530 pf->num_vmdq_qps = 0;
5531 pf->num_vmdq_msix = 0;
5532 pf->num_lan_qps = 1;
5533 pf->num_lan_msix = 1;
5534
5535 } else if (vec != v_budget) {
5536 /* Scale vector usage down */
5537 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5538 vec--; /* reserve the misc vector */
5539
5540 /* partition out the remaining vectors */
5541 switch (vec) {
5542 case 2:
5543 pf->num_vmdq_vsis = 1;
5544 pf->num_lan_msix = 1;
5545 break;
5546 case 3:
5547 pf->num_vmdq_vsis = 1;
5548 pf->num_lan_msix = 2;
5549 break;
5550 default:
5551 pf->num_lan_msix = min_t(int, (vec / 2),
5552 pf->num_lan_qps);
5553 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5554 I40E_DEFAULT_NUM_VMDQ_VSI);
5555 break;
5556 }
5557 }
5558
5559 return err;
5560}
5561
493fb300
AD		 5562/**
5563 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5564 * @vsi: the VSI being configured
5565 * @v_idx: index of the vector in the vsi struct
5566 *
5567 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5568 **/
5569static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5570{
5571 struct i40e_q_vector *q_vector;
5572
5573 /* allocate q_vector */
5574 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5575 if (!q_vector)
5576 return -ENOMEM;
5577
5578 q_vector->vsi = vsi;
5579 q_vector->v_idx = v_idx;
5580 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5581 if (vsi->netdev)
5582 netif_napi_add(vsi->netdev, &q_vector->napi,
5583 i40e_napi_poll, vsi->work_limit);
5584
cd0b6fa6
AD		 5585 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5586 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5587
493fb300
AD		 5588 /* tie q_vector and vsi together */
5589 vsi->q_vectors[v_idx] = q_vector;
5590
5591 return 0;
5592}
5593
41c445ff
JB		 5594/**
5595 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5596 * @vsi: the VSI being configured
5597 *
5598 * We allocate one q_vector per queue interrupt. If allocation fails we
5599 * return -ENOMEM.
5600 **/
5601static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5602{
5603 struct i40e_pf *pf = vsi->back;
5604 int v_idx, num_q_vectors;
493fb300 5605 int err;
41c445ff
JB		 5606
5607 /* if not MSIX, give the one vector only to the LAN VSI */
5608 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5609 num_q_vectors = vsi->num_q_vectors;
5610 else if (vsi == pf->vsi[pf->lan_vsi])
5611 num_q_vectors = 1;
5612 else
5613 return -EINVAL;
5614
41c445ff 5615 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5616 err = i40e_alloc_q_vector(vsi, v_idx);
5617 if (err)
5618 goto err_out;
41c445ff
JB		 5619 }
5620
5621 return 0;
493fb300
AD		 5622
5623err_out:
5624 while (v_idx--)
5625 i40e_free_q_vector(vsi, v_idx);
5626
5627 return err;
41c445ff
JB		 5628}
5629
5630/**
5631 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5632 * @pf: board private structure to initialize
5633 **/
5634static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5635{
5636 int err = 0;
5637
5638 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5639 err = i40e_init_msix(pf);
5640 if (err) {
958a3e3b
SN		 5641 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5642 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5643 I40E_FLAG_DCB_ENABLED |
5644 I40E_FLAG_SRIOV_ENABLED |
5645 I40E_FLAG_FDIR_ENABLED |
5646 I40E_FLAG_FDIR_ATR_ENABLED |
5647 I40E_FLAG_VMDQ_ENABLED);
5648
5649 /* rework the queue expectations without MSIX */
5650 i40e_determine_queue_usage(pf);
5651 }
5652 }
5653
5654 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5655 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5656 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5657 err = pci_enable_msi(pf->pdev);
5658 if (err) {
958a3e3b 5659 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5660 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5661 }
5662 }
5663
958a3e3b
SN		 5664 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5665 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5666
41c445ff
JB		 5667 /* track first vector for misc interrupts */
5668 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5669}
5670
5671/**
5672 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5673 * @pf: board private structure
5674 *
5675 * This sets up the handler for MSIX 0, which is used to manage the
5676 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5677 * when in MSI or Legacy interrupt mode.
5678 **/
5679static int i40e_setup_misc_vector(struct i40e_pf *pf)
5680{
5681 struct i40e_hw *hw = &pf->hw;
5682 int err = 0;
5683
5684 /* Only request the irq if this is the first time through, and
5685 * not when we're rebuilding after a Reset
5686 */
5687 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5688 err = request_irq(pf->msix_entries[0].vector,
5689 i40e_intr, 0, pf->misc_int_name, pf);
5690 if (err) {
5691 dev_info(&pf->pdev->dev,
5692 "request_irq for msix_misc failed: %d\n", err);
5693 return -EFAULT;
5694 }
5695 }
5696
5697 i40e_enable_misc_int_causes(hw);
5698
5699 /* associate no queues to the misc vector */
5700 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5701 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5702
5703 i40e_flush(hw);
5704
5705 i40e_irq_dynamic_enable_icr0(pf);
5706
5707 return err;
5708}
5709
5710/**
5711 * i40e_config_rss - Prepare for RSS if used
5712 * @pf: board private structure
5713 **/
5714static int i40e_config_rss(struct i40e_pf *pf)
5715{
41c445ff
JB		 5716 /* Set of random keys generated using kernel random number generator */
5717 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5718 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5719 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5720 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5721 struct i40e_hw *hw = &pf->hw;
5722 u32 lut = 0;
5723 int i, j;
5724 u64 hena;
41c445ff
JB		 5725
5726 /* Fill out hash function seed */
5727 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5728 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5729
5730 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5731 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5732 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 5733 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 5734 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5735 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5736
5737 /* Populate the LUT with max no. of queues in round robin fashion */
5738 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5739
5740 /* The assumption is that lan qp count will be the highest
5741 * qp count for any PF VSI that needs RSS.
5742 * If multiple VSIs need RSS support, all the qp counts
5743 * for those VSIs should be a power of 2 for RSS to work.
5744 * If LAN VSI is the only consumer for RSS then this requirement
5745 * is not necessary.
5746 */
5747 if (j == pf->rss_size)
5748 j = 0;
5749 /* lut = 4-byte sliding window of 4 lut entries */
5750 lut = (lut << 8) | (j &
5751 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5752 /* On i = 3, we have 4 entries in lut; write to the register */
5753 if ((i & 3) == 3)
5754 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5755 }
5756 i40e_flush(hw);
5757
5758 return 0;
5759}
5760
f8ff1464
ASJ		 5761/**
5762 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5763 * @pf: board private structure
5764 * @queue_count: the requested queue count for rss.
5765 *
5766 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5767 * count which may be different from the requested queue count.
5768 **/
5769int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5770{
5771 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5772 return 0;
5773
5774 queue_count = min_t(int, queue_count, pf->rss_size_max);
5775 queue_count = rounddown_pow_of_two(queue_count);
5776
5777 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 5778 i40e_prep_for_reset(pf);
5779
f8ff1464
ASJ		 5780 pf->rss_size = queue_count;
5781
5782 i40e_reset_and_rebuild(pf, true);
5783 i40e_config_rss(pf);
5784 }
5785 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5786 return pf->rss_size;
5787}
5788
41c445ff
JB		 5789/**
5790 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5791 * @pf: board private structure to initialize
5792 *
5793 * i40e_sw_init initializes the Adapter private data structure.
5794 * Fields are initialized based on PCI device information and
5795 * OS network device settings (MTU size).
5796 **/
5797static int i40e_sw_init(struct i40e_pf *pf)
5798{
5799 int err = 0;
5800 int size;
5801
5802 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5803 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5804 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5805 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5806 if (I40E_DEBUG_USER & debug)
5807 pf->hw.debug_mask = debug;
5808 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5809 I40E_DEFAULT_MSG_ENABLE);
5810 }
5811
5812 /* Set default capability flags */
5813 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5814 I40E_FLAG_MSI_ENABLED |
5815 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 5816 I40E_FLAG_RX_1BUF_ENABLED;
5817
7134f9ce
JB		 5818 /* Depending on PF configurations, it is possible that the RSS
5819 * maximum might end up larger than the available queues
5820 */
41c445ff 5821 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5822 pf->rss_size_max = min_t(int, pf->rss_size_max,
5823 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5824 if (pf->hw.func_caps.rss) {
5825 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5826 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5827 } else {
5828 pf->rss_size = 1;
5829 }
5830
2050bc65
CS		 5831 /* MFP mode enabled */
5832 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5833 pf->flags |= I40E_FLAG_MFP_ENABLED;
5834 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5835 }
5836
41c445ff
JB		 5837 if (pf->hw.func_caps.dcb)
5838 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5839 else
5840 pf->num_tc_qps = 0;
5841
5842 if (pf->hw.func_caps.fd) {
5843 /* FW/NVM is not yet fixed in this regard */
5844 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5845 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5846 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5847 dev_info(&pf->pdev->dev,
5848 "Flow Director ATR mode Enabled\n");
5849 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5850 dev_info(&pf->pdev->dev,
5851 "Flow Director Side Band mode Enabled\n");
5852 pf->fdir_pf_filter_count =
5853 pf->hw.func_caps.fd_filters_guaranteed;
5854 }
5855 } else {
5856 pf->fdir_pf_filter_count = 0;
5857 }
5858
5859 if (pf->hw.func_caps.vmdq) {
5860 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5861 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5862 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5863 }
5864
41c445ff
JB		 5865#ifdef CONFIG_PCI_IOV
5866 if (pf->hw.func_caps.num_vfs) {
5867 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5868 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5869 pf->num_req_vfs = min_t(int,
5870 pf->hw.func_caps.num_vfs,
5871 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5872 dev_info(&pf->pdev->dev,
5873 "Number of VFs being requested for PF[%d] = %d\n",
5874 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5875 }
5876#endif /* CONFIG_PCI_IOV */
5877 pf->eeprom_version = 0xDEAD;
5878 pf->lan_veb = I40E_NO_VEB;
5879 pf->lan_vsi = I40E_NO_VSI;
5880
5881 /* set up queue assignment tracking */
5882 size = sizeof(struct i40e_lump_tracking)
5883 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5884 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5885 if (!pf->qp_pile) {
5886 err = -ENOMEM;
5887 goto sw_init_done;
5888 }
5889 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5890 pf->qp_pile->search_hint = 0;
5891
5892 /* set up vector assignment tracking */
5893 size = sizeof(struct i40e_lump_tracking)
5894 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5895 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5896 if (!pf->irq_pile) {
5897 kfree(pf->qp_pile);
5898 err = -ENOMEM;
5899 goto sw_init_done;
5900 }
5901 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5902 pf->irq_pile->search_hint = 0;
5903
5904 mutex_init(&pf->switch_mutex);
5905
5906sw_init_done:
5907 return err;
5908}
5909
5910/**
5911 * i40e_set_features - set the netdev feature flags
5912 * @netdev: ptr to the netdev being adjusted
5913 * @features: the feature set that the stack is suggesting
5914 **/
5915static int i40e_set_features(struct net_device *netdev,
5916 netdev_features_t features)
5917{
5918 struct i40e_netdev_priv *np = netdev_priv(netdev);
5919 struct i40e_vsi *vsi = np->vsi;
5920
5921 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5922 i40e_vlan_stripping_enable(vsi);
5923 else
5924 i40e_vlan_stripping_disable(vsi);
5925
5926 return 0;
5927}
5928
a1c9a9d9
JK		 5929#ifdef CONFIG_I40E_VXLAN
5930/**
5931 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5932 * @pf: board private structure
5933 * @port: The UDP port to look up
5934 *
5935 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5936 **/
5937static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5938{
5939 u8 i;
5940
5941 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5942 if (pf->vxlan_ports[i] == port)
5943 return i;
5944 }
5945
5946 return i;
5947}
5948
5949/**
5950 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5951 * @netdev: This physical port's netdev
5952 * @sa_family: Socket Family that VXLAN is notifying us about
5953 * @port: New UDP port number that VXLAN started listening to
5954 **/
5955static void i40e_add_vxlan_port(struct net_device *netdev,
5956 sa_family_t sa_family, __be16 port)
5957{
5958 struct i40e_netdev_priv *np = netdev_priv(netdev);
5959 struct i40e_vsi *vsi = np->vsi;
5960 struct i40e_pf *pf = vsi->back;
5961 u8 next_idx;
5962 u8 idx;
5963
5964 if (sa_family == AF_INET6)
5965 return;
5966
5967 idx = i40e_get_vxlan_port_idx(pf, port);
5968
5969 /* Check if port already exists */
5970 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5971 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
5972 return;
5973 }
5974
5975 /* Now check if there is space to add the new port */
5976 next_idx = i40e_get_vxlan_port_idx(pf, 0);
5977
5978 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5979 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
5980 ntohs(port));
5981 return;
5982 }
5983
5984 /* New port: add it and mark its index in the bitmap */
5985 pf->vxlan_ports[next_idx] = port;
5986 pf->pending_vxlan_bitmap |= (1 << next_idx);
5987
5988 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
5989}
5990
5991/**
5992 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
5993 * @netdev: This physical port's netdev
5994 * @sa_family: Socket Family that VXLAN is notifying us about
5995 * @port: UDP port number that VXLAN stopped listening to
5996 **/
5997static void i40e_del_vxlan_port(struct net_device *netdev,
5998 sa_family_t sa_family, __be16 port)
5999{
6000 struct i40e_netdev_priv *np = netdev_priv(netdev);
6001 struct i40e_vsi *vsi = np->vsi;
6002 struct i40e_pf *pf = vsi->back;
6003 u8 idx;
6004
6005 if (sa_family == AF_INET6)
6006 return;
6007
6008 idx = i40e_get_vxlan_port_idx(pf, port);
6009
6010 /* Check if port already exists */
6011 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6012 /* if port exists, set it to 0 (mark for deletion)
6013 * and make it pending
6014 */
6015 pf->vxlan_ports[idx] = 0;
6016
6017 pf->pending_vxlan_bitmap |= (1 << idx);
6018
6019 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6020 } else {
6021 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6022 ntohs(port));
6023 }
6024}
6025
6026#endif
41c445ff
JB		 6027static const struct net_device_ops i40e_netdev_ops = {
6028 .ndo_open = i40e_open,
6029 .ndo_stop = i40e_close,
6030 .ndo_start_xmit = i40e_lan_xmit_frame,
6031 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6032 .ndo_set_rx_mode = i40e_set_rx_mode,
6033 .ndo_validate_addr = eth_validate_addr,
6034 .ndo_set_mac_address = i40e_set_mac,
6035 .ndo_change_mtu = i40e_change_mtu,
6036 .ndo_tx_timeout = i40e_tx_timeout,
6037 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6038 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6039#ifdef CONFIG_NET_POLL_CONTROLLER
6040 .ndo_poll_controller = i40e_netpoll,
6041#endif
6042 .ndo_setup_tc = i40e_setup_tc,
6043 .ndo_set_features = i40e_set_features,
6044 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6045 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6046 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6047 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6048#ifdef CONFIG_I40E_VXLAN
6049 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6050 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6051#endif
41c445ff
JB		 6052};
6053
6054/**
6055 * i40e_config_netdev - Setup the netdev flags
6056 * @vsi: the VSI being configured
6057 *
6058 * Returns 0 on success, negative value on failure
6059 **/
6060static int i40e_config_netdev(struct i40e_vsi *vsi)
6061{
1a10370a 6062 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6063 struct i40e_pf *pf = vsi->back;
6064 struct i40e_hw *hw = &pf->hw;
6065 struct i40e_netdev_priv *np;
6066 struct net_device *netdev;
6067 u8 mac_addr[ETH_ALEN];
6068 int etherdev_size;
6069
6070 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6071 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6072 if (!netdev)
6073 return -ENOMEM;
6074
6075 vsi->netdev = netdev;
6076 np = netdev_priv(netdev);
6077 np->vsi = vsi;
6078
6079 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6080 NETIF_F_GSO_UDP_TUNNEL |
6081 NETIF_F_TSO |
6082 NETIF_F_SG;
6083
6084 netdev->features = NETIF_F_SG |
6085 NETIF_F_IP_CSUM |
6086 NETIF_F_SCTP_CSUM |
6087 NETIF_F_HIGHDMA |
6088 NETIF_F_GSO_UDP_TUNNEL |
6089 NETIF_F_HW_VLAN_CTAG_TX |
6090 NETIF_F_HW_VLAN_CTAG_RX |
6091 NETIF_F_HW_VLAN_CTAG_FILTER |
6092 NETIF_F_IPV6_CSUM |
6093 NETIF_F_TSO |
6094 NETIF_F_TSO6 |
6095 NETIF_F_RXCSUM |
6096 NETIF_F_RXHASH |
6097 0;
6098
6099 /* copy netdev features into list of user selectable features */
6100 netdev->hw_features |= netdev->features;
6101
6102 if (vsi->type == I40E_VSI_MAIN) {
6103 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6104 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6105 } else {
6106 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6107 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6108 pf->vsi[pf->lan_vsi]->netdev->name);
6109 random_ether_addr(mac_addr);
6110 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6111 }
1a10370a 6112 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6113
6114 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6115 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6116 /* vlan gets same features (except vlan offload)
6117 * after any tweaks for specific VSI types
6118 */
6119 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6120 NETIF_F_HW_VLAN_CTAG_RX |
6121 NETIF_F_HW_VLAN_CTAG_FILTER);
6122 netdev->priv_flags |= IFF_UNICAST_FLT;
6123 netdev->priv_flags |= IFF_SUPP_NOFCS;
6124 /* Setup netdev TC information */
6125 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6126
6127 netdev->netdev_ops = &i40e_netdev_ops;
6128 netdev->watchdog_timeo = 5 * HZ;
6129 i40e_set_ethtool_ops(netdev);
6130
6131 return 0;
6132}
6133
6134/**
6135 * i40e_vsi_delete - Delete a VSI from the switch
6136 * @vsi: the VSI being removed
6137 *
6138 * Returns 0 on success, negative value on failure
6139 **/
6140static void i40e_vsi_delete(struct i40e_vsi *vsi)
6141{
6142 /* remove default VSI is not allowed */
6143 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6144 return;
6145
6146 /* there is no HW VSI for FDIR */
6147 if (vsi->type == I40E_VSI_FDIR)
6148 return;
6149
6150 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6151 return;
6152}
6153
6154/**
6155 * i40e_add_vsi - Add a VSI to the switch
6156 * @vsi: the VSI being configured
6157 *
6158 * This initializes a VSI context depending on the VSI type to be added and
6159 * passes it down to the add_vsi aq command.
6160 **/
6161static int i40e_add_vsi(struct i40e_vsi *vsi)
6162{
6163 int ret = -ENODEV;
6164 struct i40e_mac_filter *f, *ftmp;
6165 struct i40e_pf *pf = vsi->back;
6166 struct i40e_hw *hw = &pf->hw;
6167 struct i40e_vsi_context ctxt;
6168 u8 enabled_tc = 0x1; /* TC0 enabled */
6169 int f_count = 0;
6170
6171 memset(&ctxt, 0, sizeof(ctxt));
6172 switch (vsi->type) {
6173 case I40E_VSI_MAIN:
6174 /* The PF's main VSI is already setup as part of the
6175 * device initialization, so we'll not bother with
6176 * the add_vsi call, but we will retrieve the current
6177 * VSI context.
6178 */
6179 ctxt.seid = pf->main_vsi_seid;
6180 ctxt.pf_num = pf->hw.pf_id;
6181 ctxt.vf_num = 0;
6182 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6183 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6184 if (ret) {
6185 dev_info(&pf->pdev->dev,
6186 "couldn't get pf vsi config, err %d, aq_err %d\n",
6187 ret, pf->hw.aq.asq_last_status);
6188 return -ENOENT;
6189 }
6190 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6191 vsi->info.valid_sections = 0;
6192
6193 vsi->seid = ctxt.seid;
6194 vsi->id = ctxt.vsi_number;
6195
6196 enabled_tc = i40e_pf_get_tc_map(pf);
6197
6198 /* MFP mode setup queue map and update VSI */
6199 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6200 memset(&ctxt, 0, sizeof(ctxt));
6201 ctxt.seid = pf->main_vsi_seid;
6202 ctxt.pf_num = pf->hw.pf_id;
6203 ctxt.vf_num = 0;
6204 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6205 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6206 if (ret) {
6207 dev_info(&pf->pdev->dev,
6208 "update vsi failed, aq_err=%d\n",
6209 pf->hw.aq.asq_last_status);
6210 ret = -ENOENT;
6211 goto err;
6212 }
6213 /* update the local VSI info queue map */
6214 i40e_vsi_update_queue_map(vsi, &ctxt);
6215 vsi->info.valid_sections = 0;
6216 } else {
6217 /* Default/Main VSI is only enabled for TC0
6218 * reconfigure it to enable all TCs that are
6219 * available on the port in SFP mode.
6220 */
6221 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6222 if (ret) {
6223 dev_info(&pf->pdev->dev,
6224 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6225 enabled_tc, ret,
6226 pf->hw.aq.asq_last_status);
6227 ret = -ENOENT;
6228 }
6229 }
6230 break;
6231
6232 case I40E_VSI_FDIR:
6233 /* no queue mapping or actual HW VSI needed */
6234 vsi->info.valid_sections = 0;
6235 vsi->seid = 0;
6236 vsi->id = 0;
6237 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6238 return 0;
6239 break;
6240
6241 case I40E_VSI_VMDQ2:
6242 ctxt.pf_num = hw->pf_id;
6243 ctxt.vf_num = 0;
6244 ctxt.uplink_seid = vsi->uplink_seid;
6245 ctxt.connection_type = 0x1; /* regular data port */
6246 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6247
6248 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6249
6250 /* This VSI is connected to VEB so the switch_id
6251 * should be set to zero by default.
6252 */
6253 ctxt.info.switch_id = 0;
6254 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6255 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6256
6257 /* Setup the VSI tx/rx queue map for TC0 only for now */
6258 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6259 break;
6260
6261 case I40E_VSI_SRIOV:
6262 ctxt.pf_num = hw->pf_id;
6263 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6264 ctxt.uplink_seid = vsi->uplink_seid;
6265 ctxt.connection_type = 0x1; /* regular data port */
6266 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6267
6268 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6269
6270 /* This VSI is connected to VEB so the switch_id
6271 * should be set to zero by default.
6272 */
6273 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6274
6275 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6276 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6277 /* Setup the VSI tx/rx queue map for TC0 only for now */
6278 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6279 break;
6280
6281 default:
6282 return -ENODEV;
6283 }
6284
6285 if (vsi->type != I40E_VSI_MAIN) {
6286 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6287 if (ret) {
6288 dev_info(&vsi->back->pdev->dev,
6289 "add vsi failed, aq_err=%d\n",
6290 vsi->back->hw.aq.asq_last_status);
6291 ret = -ENOENT;
6292 goto err;
6293 }
6294 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6295 vsi->info.valid_sections = 0;
6296 vsi->seid = ctxt.seid;
6297 vsi->id = ctxt.vsi_number;
6298 }
6299
6300 /* If macvlan filters already exist, force them to get loaded */
6301 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6302 f->changed = true;
6303 f_count++;
6304 }
6305 if (f_count) {
6306 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6307 pf->flags |= I40E_FLAG_FILTER_SYNC;
6308 }
6309
6310 /* Update VSI BW information */
6311 ret = i40e_vsi_get_bw_info(vsi);
6312 if (ret) {
6313 dev_info(&pf->pdev->dev,
6314 "couldn't get vsi bw info, err %d, aq_err %d\n",
6315 ret, pf->hw.aq.asq_last_status);
6316 /* VSI is already added so not tearing that up */
6317 ret = 0;
6318 }
6319
6320err:
6321 return ret;
6322}
6323
6324/**
6325 * i40e_vsi_release - Delete a VSI and free its resources
6326 * @vsi: the VSI being removed
6327 *
6328 * Returns 0 on success or < 0 on error
6329 **/
6330int i40e_vsi_release(struct i40e_vsi *vsi)
6331{
6332 struct i40e_mac_filter *f, *ftmp;
6333 struct i40e_veb *veb = NULL;
6334 struct i40e_pf *pf;
6335 u16 uplink_seid;
6336 int i, n;
6337
6338 pf = vsi->back;
6339
6340 /* release of a VEB-owner or last VSI is not allowed */
6341 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6342 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6343 vsi->seid, vsi->uplink_seid);
6344 return -ENODEV;
6345 }
6346 if (vsi == pf->vsi[pf->lan_vsi] &&
6347 !test_bit(__I40E_DOWN, &pf->state)) {
6348 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6349 return -ENODEV;
6350 }
6351
6352 uplink_seid = vsi->uplink_seid;
6353 if (vsi->type != I40E_VSI_SRIOV) {
6354 if (vsi->netdev_registered) {
6355 vsi->netdev_registered = false;
6356 if (vsi->netdev) {
6357 /* results in a call to i40e_close() */
6358 unregister_netdev(vsi->netdev);
6359 free_netdev(vsi->netdev);
6360 vsi->netdev = NULL;
6361 }
6362 } else {
6363 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6364 i40e_down(vsi);
6365 i40e_vsi_free_irq(vsi);
6366 i40e_vsi_free_tx_resources(vsi);
6367 i40e_vsi_free_rx_resources(vsi);
6368 }
6369 i40e_vsi_disable_irq(vsi);
6370 }
6371
6372 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6373 i40e_del_filter(vsi, f->macaddr, f->vlan,
6374 f->is_vf, f->is_netdev);
6375 i40e_sync_vsi_filters(vsi);
6376
6377 i40e_vsi_delete(vsi);
6378 i40e_vsi_free_q_vectors(vsi);
6379 i40e_vsi_clear_rings(vsi);
6380 i40e_vsi_clear(vsi);
6381
6382 /* If this was the last thing on the VEB, except for the
6383 * controlling VSI, remove the VEB, which puts the controlling
6384 * VSI onto the next level down in the switch.
6385 *
6386 * Well, okay, there's one more exception here: don't remove
6387 * the orphan VEBs yet. We'll wait for an explicit remove request
6388 * from up the network stack.
6389 */
6390 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6391 if (pf->vsi[i] &&
6392 pf->vsi[i]->uplink_seid == uplink_seid &&
6393 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6394 n++; /* count the VSIs */
6395 }
6396 }
6397 for (i = 0; i < I40E_MAX_VEB; i++) {
6398 if (!pf->veb[i])
6399 continue;
6400 if (pf->veb[i]->uplink_seid == uplink_seid)
6401 n++; /* count the VEBs */
6402 if (pf->veb[i]->seid == uplink_seid)
6403 veb = pf->veb[i];
6404 }
6405 if (n == 0 && veb && veb->uplink_seid != 0)
6406 i40e_veb_release(veb);
6407
6408 return 0;
6409}
6410
6411/**
6412 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6413 * @vsi: ptr to the VSI
6414 *
6415 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6416 * corresponding SW VSI structure and initializes num_queue_pairs for the
6417 * newly allocated VSI.
6418 *
6419 * Returns 0 on success or negative on failure
6420 **/
6421static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6422{
6423 int ret = -ENOENT;
6424 struct i40e_pf *pf = vsi->back;
6425
493fb300 6426 if (vsi->q_vectors[0]) {
41c445ff
JB		 6427 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6428 vsi->seid);
6429 return -EEXIST;
6430 }
6431
6432 if (vsi->base_vector) {
6433 dev_info(&pf->pdev->dev,
6434 "VSI %d has non-zero base vector %d\n",
6435 vsi->seid, vsi->base_vector);
6436 return -EEXIST;
6437 }
6438
6439 ret = i40e_alloc_q_vectors(vsi);
6440 if (ret) {
6441 dev_info(&pf->pdev->dev,
6442 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6443 vsi->num_q_vectors, vsi->seid, ret);
6444 vsi->num_q_vectors = 0;
6445 goto vector_setup_out;
6446 }
6447
958a3e3b
SN		 6448 if (vsi->num_q_vectors)
6449 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6450 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6451 if (vsi->base_vector < 0) {
6452 dev_info(&pf->pdev->dev,
6453 "failed to get q tracking for VSI %d, err=%d\n",
6454 vsi->seid, vsi->base_vector);
6455 i40e_vsi_free_q_vectors(vsi);
6456 ret = -ENOENT;
6457 goto vector_setup_out;
6458 }
6459
6460vector_setup_out:
6461 return ret;
6462}
6463
bc7d338f
ASJ		 6464/**
6465 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6466 * @vsi: pointer to the vsi.
6467 *
6468 * This re-allocates a vsi's queue resources.
6469 *
6470 * Returns pointer to the successfully allocated and configured VSI sw struct
6471 * on success, otherwise returns NULL on failure.
6472 **/
6473static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6474{
6475 struct i40e_pf *pf = vsi->back;
6476 u8 enabled_tc;
6477 int ret;
6478
6479 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6480 i40e_vsi_clear_rings(vsi);
6481
6482 i40e_vsi_free_arrays(vsi, false);
6483 i40e_set_num_rings_in_vsi(vsi);
6484 ret = i40e_vsi_alloc_arrays(vsi, false);
6485 if (ret)
6486 goto err_vsi;
6487
6488 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6489 if (ret < 0) {
6490 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6491 vsi->seid, ret);
6492 goto err_vsi;
6493 }
6494 vsi->base_queue = ret;
6495
6496 /* Update the FW view of the VSI. Force a reset of TC and queue
6497 * layout configurations.
6498 */
6499 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6500 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6501 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6502 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6503
6504 /* assign it some queues */
6505 ret = i40e_alloc_rings(vsi);
6506 if (ret)
6507 goto err_rings;
6508
6509 /* map all of the rings to the q_vectors */
6510 i40e_vsi_map_rings_to_vectors(vsi);
6511 return vsi;
6512
6513err_rings:
6514 i40e_vsi_free_q_vectors(vsi);
6515 if (vsi->netdev_registered) {
6516 vsi->netdev_registered = false;
6517 unregister_netdev(vsi->netdev);
6518 free_netdev(vsi->netdev);
6519 vsi->netdev = NULL;
6520 }
6521 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6522err_vsi:
6523 i40e_vsi_clear(vsi);
6524 return NULL;
6525}
6526
41c445ff
JB		 6527/**
6528 * i40e_vsi_setup - Set up a VSI by a given type
6529 * @pf: board private structure
6530 * @type: VSI type
6531 * @uplink_seid: the switch element to link to
6532 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6533 *
6534 * This allocates the sw VSI structure and its queue resources, then add a VSI
6535 * to the identified VEB.
6536 *
6537 * Returns pointer to the successfully allocated and configure VSI sw struct on
6538 * success, otherwise returns NULL on failure.
6539 **/
6540struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6541 u16 uplink_seid, u32 param1)
6542{
6543 struct i40e_vsi *vsi = NULL;
6544 struct i40e_veb *veb = NULL;
6545 int ret, i;
6546 int v_idx;
6547
6548 /* The requested uplink_seid must be either
6549 * - the PF's port seid
6550 * no VEB is needed because this is the PF
6551 * or this is a Flow Director special case VSI
6552 * - seid of an existing VEB
6553 * - seid of a VSI that owns an existing VEB
6554 * - seid of a VSI that doesn't own a VEB
6555 * a new VEB is created and the VSI becomes the owner
6556 * - seid of the PF VSI, which is what creates the first VEB
6557 * this is a special case of the previous
6558 *
6559 * Find which uplink_seid we were given and create a new VEB if needed
6560 */
6561 for (i = 0; i < I40E_MAX_VEB; i++) {
6562 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6563 veb = pf->veb[i];
6564 break;
6565 }
6566 }
6567
6568 if (!veb && uplink_seid != pf->mac_seid) {
6569
6570 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6571 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6572 vsi = pf->vsi[i];
6573 break;
6574 }
6575 }
6576 if (!vsi) {
6577 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6578 uplink_seid);
6579 return NULL;
6580 }
6581
6582 if (vsi->uplink_seid == pf->mac_seid)
6583 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6584 vsi->tc_config.enabled_tc);
6585 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6586 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6587 vsi->tc_config.enabled_tc);
6588
6589 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6590 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6591 veb = pf->veb[i];
6592 }
6593 if (!veb) {
6594 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6595 return NULL;
6596 }
6597
6598 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6599 uplink_seid = veb->seid;
6600 }
6601
6602 /* get vsi sw struct */
6603 v_idx = i40e_vsi_mem_alloc(pf, type);
6604 if (v_idx < 0)
6605 goto err_alloc;
6606 vsi = pf->vsi[v_idx];
6607 vsi->type = type;
6608 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6609
6610 if (type == I40E_VSI_MAIN)
6611 pf->lan_vsi = v_idx;
6612 else if (type == I40E_VSI_SRIOV)
6613 vsi->vf_id = param1;
6614 /* assign it some queues */
6615 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6616 if (ret < 0) {
6617 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6618 vsi->seid, ret);
6619 goto err_vsi;
6620 }
6621 vsi->base_queue = ret;
6622
6623 /* get a VSI from the hardware */
6624 vsi->uplink_seid = uplink_seid;
6625 ret = i40e_add_vsi(vsi);
6626 if (ret)
6627 goto err_vsi;
6628
6629 switch (vsi->type) {
6630 /* setup the netdev if needed */
6631 case I40E_VSI_MAIN:
6632 case I40E_VSI_VMDQ2:
6633 ret = i40e_config_netdev(vsi);
6634 if (ret)
6635 goto err_netdev;
6636 ret = register_netdev(vsi->netdev);
6637 if (ret)
6638 goto err_netdev;
6639 vsi->netdev_registered = true;
6640 netif_carrier_off(vsi->netdev);
6641 /* fall through */
6642
6643 case I40E_VSI_FDIR:
6644 /* set up vectors and rings if needed */
6645 ret = i40e_vsi_setup_vectors(vsi);
6646 if (ret)
6647 goto err_msix;
6648
6649 ret = i40e_alloc_rings(vsi);
6650 if (ret)
6651 goto err_rings;
6652
6653 /* map all of the rings to the q_vectors */
6654 i40e_vsi_map_rings_to_vectors(vsi);
6655
6656 i40e_vsi_reset_stats(vsi);
6657 break;
6658
6659 default:
6660 /* no netdev or rings for the other VSI types */
6661 break;
6662 }
6663
6664 return vsi;
6665
6666err_rings:
6667 i40e_vsi_free_q_vectors(vsi);
6668err_msix:
6669 if (vsi->netdev_registered) {
6670 vsi->netdev_registered = false;
6671 unregister_netdev(vsi->netdev);
6672 free_netdev(vsi->netdev);
6673 vsi->netdev = NULL;
6674 }
6675err_netdev:
6676 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6677err_vsi:
6678 i40e_vsi_clear(vsi);
6679err_alloc:
6680 return NULL;
6681}
6682
6683/**
6684 * i40e_veb_get_bw_info - Query VEB BW information
6685 * @veb: the veb to query
6686 *
6687 * Query the Tx scheduler BW configuration data for given VEB
6688 **/
6689static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6690{
6691 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6692 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6693 struct i40e_pf *pf = veb->pf;
6694 struct i40e_hw *hw = &pf->hw;
6695 u32 tc_bw_max;
6696 int ret = 0;
6697 int i;
6698
6699 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6700 &bw_data, NULL);
6701 if (ret) {
6702 dev_info(&pf->pdev->dev,
6703 "query veb bw config failed, aq_err=%d\n",
6704 hw->aq.asq_last_status);
6705 goto out;
6706 }
6707
6708 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6709 &ets_data, NULL);
6710 if (ret) {
6711 dev_info(&pf->pdev->dev,
6712 "query veb bw ets config failed, aq_err=%d\n",
6713 hw->aq.asq_last_status);
6714 goto out;
6715 }
6716
6717 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6718 veb->bw_max_quanta = ets_data.tc_bw_max;
6719 veb->is_abs_credits = bw_data.absolute_credits_enable;
6720 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6721 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6722 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6723 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6724 veb->bw_tc_limit_credits[i] =
6725 le16_to_cpu(bw_data.tc_bw_limits[i]);
6726 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6727 }
6728
6729out:
6730 return ret;
6731}
6732
6733/**
6734 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6735 * @pf: board private structure
6736 *
6737 * On error: returns error code (negative)
6738 * On success: returns vsi index in PF (positive)
6739 **/
6740static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6741{
6742 int ret = -ENOENT;
6743 struct i40e_veb *veb;
6744 int i;
6745
6746 /* Need to protect the allocation of switch elements at the PF level */
6747 mutex_lock(&pf->switch_mutex);
6748
6749 /* VEB list may be fragmented if VEB creation/destruction has
6750 * been happening. We can afford to do a quick scan to look
6751 * for any free slots in the list.
6752 *
6753 * find next empty veb slot, looping back around if necessary
6754 */
6755 i = 0;
6756 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6757 i++;
6758 if (i >= I40E_MAX_VEB) {
6759 ret = -ENOMEM;
6760 goto err_alloc_veb; /* out of VEB slots! */
6761 }
6762
6763 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6764 if (!veb) {
6765 ret = -ENOMEM;
6766 goto err_alloc_veb;
6767 }
6768 veb->pf = pf;
6769 veb->idx = i;
6770 veb->enabled_tc = 1;
6771
6772 pf->veb[i] = veb;
6773 ret = i;
6774err_alloc_veb:
6775 mutex_unlock(&pf->switch_mutex);
6776 return ret;
6777}
6778
6779/**
6780 * i40e_switch_branch_release - Delete a branch of the switch tree
6781 * @branch: where to start deleting
6782 *
6783 * This uses recursion to find the tips of the branch to be
6784 * removed, deleting until we get back to and can delete this VEB.
6785 **/
6786static void i40e_switch_branch_release(struct i40e_veb *branch)
6787{
6788 struct i40e_pf *pf = branch->pf;
6789 u16 branch_seid = branch->seid;
6790 u16 veb_idx = branch->idx;
6791 int i;
6792
6793 /* release any VEBs on this VEB - RECURSION */
6794 for (i = 0; i < I40E_MAX_VEB; i++) {
6795 if (!pf->veb[i])
6796 continue;
6797 if (pf->veb[i]->uplink_seid == branch->seid)
6798 i40e_switch_branch_release(pf->veb[i]);
6799 }
6800
6801 /* Release the VSIs on this VEB, but not the owner VSI.
6802 *
6803 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6804 * the VEB itself, so don't use (*branch) after this loop.
6805 */
6806 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6807 if (!pf->vsi[i])
6808 continue;
6809 if (pf->vsi[i]->uplink_seid == branch_seid &&
6810 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6811 i40e_vsi_release(pf->vsi[i]);
6812 }
6813 }
6814
6815 /* There's one corner case where the VEB might not have been
6816 * removed, so double check it here and remove it if needed.
6817 * This case happens if the veb was created from the debugfs
6818 * commands and no VSIs were added to it.
6819 */
6820 if (pf->veb[veb_idx])
6821 i40e_veb_release(pf->veb[veb_idx]);
6822}
6823
6824/**
6825 * i40e_veb_clear - remove veb struct
6826 * @veb: the veb to remove
6827 **/
6828static void i40e_veb_clear(struct i40e_veb *veb)
6829{
6830 if (!veb)
6831 return;
6832
6833 if (veb->pf) {
6834 struct i40e_pf *pf = veb->pf;
6835
6836 mutex_lock(&pf->switch_mutex);
6837 if (pf->veb[veb->idx] == veb)
6838 pf->veb[veb->idx] = NULL;
6839 mutex_unlock(&pf->switch_mutex);
6840 }
6841
6842 kfree(veb);
6843}
6844
6845/**
6846 * i40e_veb_release - Delete a VEB and free its resources
6847 * @veb: the VEB being removed
6848 **/
6849void i40e_veb_release(struct i40e_veb *veb)
6850{
6851 struct i40e_vsi *vsi = NULL;
6852 struct i40e_pf *pf;
6853 int i, n = 0;
6854
6855 pf = veb->pf;
6856
6857 /* find the remaining VSI and check for extras */
6858 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6859 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6860 n++;
6861 vsi = pf->vsi[i];
6862 }
6863 }
6864 if (n != 1) {
6865 dev_info(&pf->pdev->dev,
6866 "can't remove VEB %d with %d VSIs left\n",
6867 veb->seid, n);
6868 return;
6869 }
6870
6871 /* move the remaining VSI to uplink veb */
6872 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6873 if (veb->uplink_seid) {
6874 vsi->uplink_seid = veb->uplink_seid;
6875 if (veb->uplink_seid == pf->mac_seid)
6876 vsi->veb_idx = I40E_NO_VEB;
6877 else
6878 vsi->veb_idx = veb->veb_idx;
6879 } else {
6880 /* floating VEB */
6881 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6882 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6883 }
6884
6885 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6886 i40e_veb_clear(veb);
6887
6888 return;
6889}
6890
6891/**
6892 * i40e_add_veb - create the VEB in the switch
6893 * @veb: the VEB to be instantiated
6894 * @vsi: the controlling VSI
6895 **/
6896static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6897{
56747264 6898 bool is_default = false;
e1c51b95 6899 bool is_cloud = false;
41c445ff
JB		 6900 int ret;
6901
6902 /* get a VEB from the hardware */
6903 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6904 veb->enabled_tc, is_default,
6905 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6906 if (ret) {
6907 dev_info(&veb->pf->pdev->dev,
6908 "couldn't add VEB, err %d, aq_err %d\n",
6909 ret, veb->pf->hw.aq.asq_last_status);
6910 return -EPERM;
6911 }
6912
6913 /* get statistics counter */
6914 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6915 &veb->stats_idx, NULL, NULL, NULL);
6916 if (ret) {
6917 dev_info(&veb->pf->pdev->dev,
6918 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6919 ret, veb->pf->hw.aq.asq_last_status);
6920 return -EPERM;
6921 }
6922 ret = i40e_veb_get_bw_info(veb);
6923 if (ret) {
6924 dev_info(&veb->pf->pdev->dev,
6925 "couldn't get VEB bw info, err %d, aq_err %d\n",
6926 ret, veb->pf->hw.aq.asq_last_status);
6927 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6928 return -ENOENT;
6929 }
6930
6931 vsi->uplink_seid = veb->seid;
6932 vsi->veb_idx = veb->idx;
6933 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6934
6935 return 0;
6936}
6937
6938/**
6939 * i40e_veb_setup - Set up a VEB
6940 * @pf: board private structure
6941 * @flags: VEB setup flags
6942 * @uplink_seid: the switch element to link to
6943 * @vsi_seid: the initial VSI seid
6944 * @enabled_tc: Enabled TC bit-map
6945 *
6946 * This allocates the sw VEB structure and links it into the switch
6947 * It is possible and legal for this to be a duplicate of an already
6948 * existing VEB. It is also possible for both uplink and vsi seids
6949 * to be zero, in order to create a floating VEB.
6950 *
6951 * Returns pointer to the successfully allocated VEB sw struct on
6952 * success, otherwise returns NULL on failure.
6953 **/
6954struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6955 u16 uplink_seid, u16 vsi_seid,
6956 u8 enabled_tc)
6957{
6958 struct i40e_veb *veb, *uplink_veb = NULL;
6959 int vsi_idx, veb_idx;
6960 int ret;
6961
6962 /* if one seid is 0, the other must be 0 to create a floating relay */
6963 if ((uplink_seid == 0 || vsi_seid == 0) &&
6964 (uplink_seid + vsi_seid != 0)) {
6965 dev_info(&pf->pdev->dev,
6966 "one, not both seid's are 0: uplink=%d vsi=%d\n",
6967 uplink_seid, vsi_seid);
6968 return NULL;
6969 }
6970
6971 /* make sure there is such a vsi and uplink */
6972 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
6973 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
6974 break;
6975 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
6976 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
6977 vsi_seid);
6978 return NULL;
6979 }
6980
6981 if (uplink_seid && uplink_seid != pf->mac_seid) {
6982 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6983 if (pf->veb[veb_idx] &&
6984 pf->veb[veb_idx]->seid == uplink_seid) {
6985 uplink_veb = pf->veb[veb_idx];
6986 break;
6987 }
6988 }
6989 if (!uplink_veb) {
6990 dev_info(&pf->pdev->dev,
6991 "uplink seid %d not found\n", uplink_seid);
6992 return NULL;
6993 }
6994 }
6995
6996 /* get veb sw struct */
6997 veb_idx = i40e_veb_mem_alloc(pf);
6998 if (veb_idx < 0)
6999 goto err_alloc;
7000 veb = pf->veb[veb_idx];
7001 veb->flags = flags;
7002 veb->uplink_seid = uplink_seid;
7003 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7004 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7005
7006 /* create the VEB in the switch */
7007 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7008 if (ret)
7009 goto err_veb;
7010
7011 return veb;
7012
7013err_veb:
7014 i40e_veb_clear(veb);
7015err_alloc:
7016 return NULL;
7017}
7018
7019/**
7020 * i40e_setup_pf_switch_element - set pf vars based on switch type
7021 * @pf: board private structure
7022 * @ele: element we are building info from
7023 * @num_reported: total number of elements
7024 * @printconfig: should we print the contents
7025 *
7026 * helper function to assist in extracting a few useful SEID values.
7027 **/
7028static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7029 struct i40e_aqc_switch_config_element_resp *ele,
7030 u16 num_reported, bool printconfig)
7031{
7032 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7033 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7034 u8 element_type = ele->element_type;
7035 u16 seid = le16_to_cpu(ele->seid);
7036
7037 if (printconfig)
7038 dev_info(&pf->pdev->dev,
7039 "type=%d seid=%d uplink=%d downlink=%d\n",
7040 element_type, seid, uplink_seid, downlink_seid);
7041
7042 switch (element_type) {
7043 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7044 pf->mac_seid = seid;
7045 break;
7046 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7047 /* Main VEB? */
7048 if (uplink_seid != pf->mac_seid)
7049 break;
7050 if (pf->lan_veb == I40E_NO_VEB) {
7051 int v;
7052
7053 /* find existing or else empty VEB */
7054 for (v = 0; v < I40E_MAX_VEB; v++) {
7055 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7056 pf->lan_veb = v;
7057 break;
7058 }
7059 }
7060 if (pf->lan_veb == I40E_NO_VEB) {
7061 v = i40e_veb_mem_alloc(pf);
7062 if (v < 0)
7063 break;
7064 pf->lan_veb = v;
7065 }
7066 }
7067
7068 pf->veb[pf->lan_veb]->seid = seid;
7069 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7070 pf->veb[pf->lan_veb]->pf = pf;
7071 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7072 break;
7073 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7074 if (num_reported != 1)
7075 break;
7076 /* This is immediately after a reset so we can assume this is
7077 * the PF's VSI
7078 */
7079 pf->mac_seid = uplink_seid;
7080 pf->pf_seid = downlink_seid;
7081 pf->main_vsi_seid = seid;
7082 if (printconfig)
7083 dev_info(&pf->pdev->dev,
7084 "pf_seid=%d main_vsi_seid=%d\n",
7085 pf->pf_seid, pf->main_vsi_seid);
7086 break;
7087 case I40E_SWITCH_ELEMENT_TYPE_PF:
7088 case I40E_SWITCH_ELEMENT_TYPE_VF:
7089 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7090 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7091 case I40E_SWITCH_ELEMENT_TYPE_PE:
7092 case I40E_SWITCH_ELEMENT_TYPE_PA:
7093 /* ignore these for now */
7094 break;
7095 default:
7096 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7097 element_type, seid);
7098 break;
7099 }
7100}
7101
7102/**
7103 * i40e_fetch_switch_configuration - Get switch config from firmware
7104 * @pf: board private structure
7105 * @printconfig: should we print the contents
7106 *
7107 * Get the current switch configuration from the device and
7108 * extract a few useful SEID values.
7109 **/
7110int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7111{
7112 struct i40e_aqc_get_switch_config_resp *sw_config;
7113 u16 next_seid = 0;
7114 int ret = 0;
7115 u8 *aq_buf;
7116 int i;
7117
7118 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7119 if (!aq_buf)
7120 return -ENOMEM;
7121
7122 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7123 do {
7124 u16 num_reported, num_total;
7125
7126 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7127 I40E_AQ_LARGE_BUF,
7128 &next_seid, NULL);
7129 if (ret) {
7130 dev_info(&pf->pdev->dev,
7131 "get switch config failed %d aq_err=%x\n",
7132 ret, pf->hw.aq.asq_last_status);
7133 kfree(aq_buf);
7134 return -ENOENT;
7135 }
7136
7137 num_reported = le16_to_cpu(sw_config->header.num_reported);
7138 num_total = le16_to_cpu(sw_config->header.num_total);
7139
7140 if (printconfig)
7141 dev_info(&pf->pdev->dev,
7142 "header: %d reported %d total\n",
7143 num_reported, num_total);
7144
7145 if (num_reported) {
7146 int sz = sizeof(*sw_config) * num_reported;
7147
7148 kfree(pf->sw_config);
7149 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7150 if (pf->sw_config)
7151 memcpy(pf->sw_config, sw_config, sz);
7152 }
7153
7154 for (i = 0; i < num_reported; i++) {
7155 struct i40e_aqc_switch_config_element_resp *ele =
7156 &sw_config->element[i];
7157
7158 i40e_setup_pf_switch_element(pf, ele, num_reported,
7159 printconfig);
7160 }
7161 } while (next_seid != 0);
7162
7163 kfree(aq_buf);
7164 return ret;
7165}
7166
7167/**
7168 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7169 * @pf: board private structure
bc7d338f 7170 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7171 *
7172 * Returns 0 on success, negative value on failure
7173 **/
bc7d338f 7174static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7175{
895106a5 7176 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7177 int ret;
7178
7179 /* find out what's out there already */
7180 ret = i40e_fetch_switch_configuration(pf, false);
7181 if (ret) {
7182 dev_info(&pf->pdev->dev,
7183 "couldn't fetch switch config, err %d, aq_err %d\n",
7184 ret, pf->hw.aq.asq_last_status);
7185 return ret;
7186 }
7187 i40e_pf_reset_stats(pf);
7188
7189 /* fdir VSI must happen first to be sure it gets queue 0, but only
7190 * if there is enough room for the fdir VSI
7191 */
7192 if (pf->num_lan_qps > 1)
7193 i40e_fdir_setup(pf);
7194
7195 /* first time setup */
bc7d338f 7196 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7197 struct i40e_vsi *vsi = NULL;
7198 u16 uplink_seid;
7199
7200 /* Set up the PF VSI associated with the PF's main VSI
7201 * that is already in the HW switch
7202 */
7203 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7204 uplink_seid = pf->veb[pf->lan_veb]->seid;
7205 else
7206 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7207 if (pf->lan_vsi == I40E_NO_VSI)
7208 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7209 else if (reinit)
7210 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7211 if (!vsi) {
7212 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7213 i40e_fdir_teardown(pf);
7214 return -EAGAIN;
7215 }
41c445ff
JB		 7216 } else {
7217 /* force a reset of TC and queue layout configurations */
7218 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7219 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7220 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7221 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7222 }
7223 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7224
7225 /* Setup static PF queue filter control settings */
7226 ret = i40e_setup_pf_filter_control(pf);
7227 if (ret) {
7228 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7229 ret);
7230 /* Failure here should not stop continuing other steps */
7231 }
7232
7233 /* enable RSS in the HW, even for only one queue, as the stack can use
7234 * the hash
7235 */
7236 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7237 i40e_config_rss(pf);
7238
7239 /* fill in link information and enable LSE reporting */
7240 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7241 i40e_link_event(pf);
7242
d52c20b7 7243 /* Initialize user-specific link properties */
41c445ff
JB		 7244 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7245 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7246 /* requested_mode is set in probe or by ethtool */
7247 if (!pf->fc_autoneg_status)
7248 goto no_autoneg;
7249
7250 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7251 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7252 pf->hw.fc.current_mode = I40E_FC_FULL;
7253 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7254 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7255 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7256 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7257 else
d52c20b7
JB		 7258 pf->hw.fc.current_mode = I40E_FC_NONE;
7259
7260 /* sync the flow control settings with the auto-neg values */
7261 switch (pf->hw.fc.current_mode) {
7262 case I40E_FC_FULL:
7263 txfc = 1;
7264 rxfc = 1;
7265 break;
7266 case I40E_FC_TX_PAUSE:
7267 txfc = 1;
7268 rxfc = 0;
7269 break;
7270 case I40E_FC_RX_PAUSE:
7271 txfc = 0;
7272 rxfc = 1;
7273 break;
7274 case I40E_FC_NONE:
7275 case I40E_FC_DEFAULT:
7276 txfc = 0;
7277 rxfc = 0;
7278 break;
7279 case I40E_FC_PFC:
7280 /* TBD */
7281 break;
7282 /* no default case, we have to handle all possibilities here */
7283 }
7284
7285 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7286
7287 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7288 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7289 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7290
7291 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7292
d52c20b7
JB		 7293 goto fc_complete;
7294
7295no_autoneg:
7296 /* disable L2 flow control, user can turn it on if they wish */
7297 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7298 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7299 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7300
7301fc_complete:
41c445ff
JB		 7302 return ret;
7303}
7304
7305/**
7306 * i40e_set_rss_size - helper to set rss_size
7307 * @pf: board private structure
7308 * @queues_left: how many queues
7309 */
7310static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7311{
7312 int num_tc0;
7313
7314 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7315 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7316 num_tc0 = rounddown_pow_of_two(num_tc0);
7317
7318 return num_tc0;
7319}
7320
7321/**
7322 * i40e_determine_queue_usage - Work out queue distribution
7323 * @pf: board private structure
7324 **/
7325static void i40e_determine_queue_usage(struct i40e_pf *pf)
7326{
7327 int accum_tc_size;
7328 int queues_left;
7329
7330 pf->num_lan_qps = 0;
7331 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7332 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7333
7334 /* Find the max queues to be put into basic use. We'll always be
7335 * using TC0, whether or not DCB is running, and TC0 will get the
7336 * big RSS set.
7337 */
7338 queues_left = pf->hw.func_caps.num_tx_qp;
7339
9f52987b 7340 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
41c445ff
JB		 7341 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7342 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7343 (queues_left == 1)) {
7344
7345 /* one qp for PF, no queues for anything else */
7346 queues_left = 0;
7347 pf->rss_size = pf->num_lan_qps = 1;
7348
7349 /* make sure all the fancies are disabled */
7350 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 7351 I40E_FLAG_FDIR_ENABLED |
7352 I40E_FLAG_FDIR_ATR_ENABLED |
7353 I40E_FLAG_DCB_ENABLED |
7354 I40E_FLAG_SRIOV_ENABLED |
7355 I40E_FLAG_VMDQ_ENABLED);
7356
7357 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7358 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7359 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7360
7361 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7362
7363 queues_left -= pf->rss_size;
f8ff1464 7364 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7365
7366 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7367 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7368 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7369
7370 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7371 * are set up for RSS in TC0
7372 */
7373 queues_left -= accum_tc_size;
7374
7375 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7376
7377 queues_left -= pf->rss_size;
7378 if (queues_left < 0) {
7379 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7380 return;
7381 }
7382
f8ff1464 7383 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7384
7385 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7386 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7387 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7388
7389 queues_left -= 1; /* save 1 queue for FD */
7390
7391 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7392
7393 queues_left -= pf->rss_size;
7394 if (queues_left < 0) {
7395 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7396 return;
7397 }
7398
f8ff1464 7399 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7400
7401 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7402 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7403 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7404
7405 /* save 1 queue for TCs 1 thru 7,
7406 * 1 queue for flow director,
7407 * and the rest are set up for RSS in TC0
7408 */
7409 queues_left -= 1;
7410 queues_left -= accum_tc_size;
7411
7412 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7413 queues_left -= pf->rss_size;
7414 if (queues_left < 0) {
7415 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7416 return;
7417 }
7418
f8ff1464 7419 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7420
7421 } else {
7422 dev_info(&pf->pdev->dev,
7423 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7424 return;
7425 }
7426
7427 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7428 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7429 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7430 pf->num_vf_qps));
7431 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7432 }
7433
7434 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7435 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7436 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7437 (queues_left / pf->num_vmdq_qps));
7438 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7439 }
7440
f8ff1464 7441 pf->queues_left = queues_left;
41c445ff
JB		 7442 return;
7443}
7444
7445/**
7446 * i40e_setup_pf_filter_control - Setup PF static filter control
7447 * @pf: PF to be setup
7448 *
7449 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7450 * settings. If PE/FCoE are enabled then it will also set the per PF
7451 * based filter sizes required for them. It also enables Flow director,
7452 * ethertype and macvlan type filter settings for the pf.
7453 *
7454 * Returns 0 on success, negative on failure
7455 **/
7456static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7457{
7458 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7459
7460 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7461
7462 /* Flow Director is enabled */
7463 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7464 settings->enable_fdir = true;
7465
7466 /* Ethtype and MACVLAN filters enabled for PF */
7467 settings->enable_ethtype = true;
7468 settings->enable_macvlan = true;
7469
7470 if (i40e_set_filter_control(&pf->hw, settings))
7471 return -ENOENT;
7472
7473 return 0;
7474}
7475
7476/**
7477 * i40e_probe - Device initialization routine
7478 * @pdev: PCI device information struct
7479 * @ent: entry in i40e_pci_tbl
7480 *
7481 * i40e_probe initializes a pf identified by a pci_dev structure.
7482 * The OS initialization, configuring of the pf private structure,
7483 * and a hardware reset occur.
7484 *
7485 * Returns 0 on success, negative on failure
7486 **/
7487static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7488{
7489 struct i40e_driver_version dv;
7490 struct i40e_pf *pf;
7491 struct i40e_hw *hw;
93cd765b 7492 static u16 pfs_found;
d4dfb81a 7493 u16 link_status;
41c445ff
JB		 7494 int err = 0;
7495 u32 len;
7496
7497 err = pci_enable_device_mem(pdev);
7498 if (err)
7499 return err;
7500
7501 /* set up for high or low dma */
7502 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7503 /* coherent mask for the same size will always succeed if
7504 * dma_set_mask does
7505 */
7506 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7507 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7508 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7509 } else {
7510 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7511 err = -EIO;
7512 goto err_dma;
7513 }
7514
7515 /* set up pci connections */
7516 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7517 IORESOURCE_MEM), i40e_driver_name);
7518 if (err) {
7519 dev_info(&pdev->dev,
7520 "pci_request_selected_regions failed %d\n", err);
7521 goto err_pci_reg;
7522 }
7523
7524 pci_enable_pcie_error_reporting(pdev);
7525 pci_set_master(pdev);
7526
7527 /* Now that we have a PCI connection, we need to do the
7528 * low level device setup. This is primarily setting up
7529 * the Admin Queue structures and then querying for the
7530 * device's current profile information.
7531 */
7532 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7533 if (!pf) {
7534 err = -ENOMEM;
7535 goto err_pf_alloc;
7536 }
7537 pf->next_vsi = 0;
7538 pf->pdev = pdev;
7539 set_bit(__I40E_DOWN, &pf->state);
7540
7541 hw = &pf->hw;
7542 hw->back = pf;
7543 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7544 pci_resource_len(pdev, 0));
7545 if (!hw->hw_addr) {
7546 err = -EIO;
7547 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7548 (unsigned int)pci_resource_start(pdev, 0),
7549 (unsigned int)pci_resource_len(pdev, 0), err);
7550 goto err_ioremap;
7551 }
7552 hw->vendor_id = pdev->vendor;
7553 hw->device_id = pdev->device;
7554 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7555 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7556 hw->subsystem_device_id = pdev->subsystem_device;
7557 hw->bus.device = PCI_SLOT(pdev->devfn);
7558 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7559 pf->instance = pfs_found;
41c445ff 7560
7134f9ce
JB		 7561 /* do a special CORER for clearing PXE mode once at init */
7562 if (hw->revision_id == 0 &&
7563 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7564 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7565 i40e_flush(hw);
7566 msleep(200);
7567 pf->corer_count++;
7568
7569 i40e_clear_pxe_mode(hw);
7570 }
7571
41c445ff
JB		 7572 /* Reset here to make sure all is clean and to define PF 'n' */
7573 err = i40e_pf_reset(hw);
7574 if (err) {
7575 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7576 goto err_pf_reset;
7577 }
7578 pf->pfr_count++;
7579
7580 hw->aq.num_arq_entries = I40E_AQ_LEN;
7581 hw->aq.num_asq_entries = I40E_AQ_LEN;
7582 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7583 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7584 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7585 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7586 "%s-pf%d:misc",
7587 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7588
7589 err = i40e_init_shared_code(hw);
7590 if (err) {
7591 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7592 goto err_pf_reset;
7593 }
7594
d52c20b7
JB		 7595 /* set up a default setting for link flow control */
7596 pf->hw.fc.requested_mode = I40E_FC_NONE;
7597
41c445ff
JB		 7598 err = i40e_init_adminq(hw);
7599 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7600 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7601 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7602 dev_info(&pdev->dev,
7603 "warning: NVM version not supported, supported version: %02x.%02x\n",
7604 I40E_CURRENT_NVM_VERSION_HI,
7605 I40E_CURRENT_NVM_VERSION_LO);
7606 }
41c445ff
JB		 7607 if (err) {
7608 dev_info(&pdev->dev,
7609 "init_adminq failed: %d expecting API %02x.%02x\n",
7610 err,
7611 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7612 goto err_pf_reset;
7613 }
7614
6ff4ef86 7615 i40e_clear_pxe_mode(hw);
41c445ff
JB		 7616 err = i40e_get_capabilities(pf);
7617 if (err)
7618 goto err_adminq_setup;
7619
7620 err = i40e_sw_init(pf);
7621 if (err) {
7622 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7623 goto err_sw_init;
7624 }
7625
7626 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7627 hw->func_caps.num_rx_qp,
7628 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7629 if (err) {
7630 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7631 goto err_init_lan_hmc;
7632 }
7633
7634 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7635 if (err) {
7636 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7637 err = -ENOENT;
7638 goto err_configure_lan_hmc;
7639 }
7640
7641 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7642 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7643 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7644 err = -EIO;
7645 goto err_mac_addr;
7646 }
7647 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7648 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7649
7650 pci_set_drvdata(pdev, pf);
7651 pci_save_state(pdev);
7652
7653 /* set up periodic task facility */
7654 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7655 pf->service_timer_period = HZ;
7656
7657 INIT_WORK(&pf->service_task, i40e_service_task);
7658 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7659 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7660 pf->link_check_timeout = jiffies;
7661
8e2773ae
SN		 7662 /* WoL defaults to disabled */
7663 pf->wol_en = false;
7664 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7665
41c445ff
JB		 7666 /* set up the main switch operations */
7667 i40e_determine_queue_usage(pf);
7668 i40e_init_interrupt_scheme(pf);
7669
7670 /* Set up the *vsi struct based on the number of VSIs in the HW,
7671 * and set up our local tracking of the MAIN PF vsi.
7672 */
7673 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7674 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7675 if (!pf->vsi) {
7676 err = -ENOMEM;
41c445ff 7677 goto err_switch_setup;
ed87ac09 7678 }
41c445ff 7679
bc7d338f 7680 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7681 if (err) {
7682 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7683 goto err_vsis;
7684 }
7685
7686 /* The main driver is (mostly) up and happy. We need to set this state
7687 * before setting up the misc vector or we get a race and the vector
7688 * ends up disabled forever.
7689 */
7690 clear_bit(__I40E_DOWN, &pf->state);
7691
7692 /* In case of MSIX we are going to setup the misc vector right here
7693 * to handle admin queue events etc. In case of legacy and MSI
7694 * the misc functionality and queue processing is combined in
7695 * the same vector and that gets setup at open.
7696 */
7697 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7698 err = i40e_setup_misc_vector(pf);
7699 if (err) {
7700 dev_info(&pdev->dev,
7701 "setup of misc vector failed: %d\n", err);
7702 goto err_vsis;
7703 }
7704 }
7705
7706 /* prep for VF support */
7707 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7708 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7709 u32 val;
7710
7711 /* disable link interrupts for VFs */
7712 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7713 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7714 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7715 i40e_flush(hw);
7716 }
7717
93cd765b
ASJ		 7718 pfs_found++;
7719
41c445ff
JB		 7720 i40e_dbg_pf_init(pf);
7721
7722 /* tell the firmware that we're starting */
7723 dv.major_version = DRV_VERSION_MAJOR;
7724 dv.minor_version = DRV_VERSION_MINOR;
7725 dv.build_version = DRV_VERSION_BUILD;
7726 dv.subbuild_version = 0;
7727 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7728
7729 /* since everything's happy, start the service_task timer */
7730 mod_timer(&pf->service_timer,
7731 round_jiffies(jiffies + pf->service_timer_period));
7732
d4dfb81a
CS		 7733 /* Get the negotiated link width and speed from PCI config space */
7734 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7735
7736 i40e_set_pci_config_data(hw, link_status);
7737
7738 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7739 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7740 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7741 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7742 "Unknown"),
7743 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7744 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7745 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7746 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7747 "Unknown"));
7748
7749 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7750 hw->bus.speed < i40e_bus_speed_8000) {
7751 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7752 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7753 }
7754
41c445ff
JB		 7755 return 0;
7756
7757 /* Unwind what we've done if something failed in the setup */
7758err_vsis:
7759 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 7760 i40e_clear_interrupt_scheme(pf);
7761 kfree(pf->vsi);
04b03013
SN		 7762err_switch_setup:
7763 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 7764 del_timer_sync(&pf->service_timer);
7765err_mac_addr:
7766err_configure_lan_hmc:
7767 (void)i40e_shutdown_lan_hmc(hw);
7768err_init_lan_hmc:
7769 kfree(pf->qp_pile);
7770 kfree(pf->irq_pile);
7771err_sw_init:
7772err_adminq_setup:
7773 (void)i40e_shutdown_adminq(hw);
7774err_pf_reset:
7775 iounmap(hw->hw_addr);
7776err_ioremap:
7777 kfree(pf);
7778err_pf_alloc:
7779 pci_disable_pcie_error_reporting(pdev);
7780 pci_release_selected_regions(pdev,
7781 pci_select_bars(pdev, IORESOURCE_MEM));
7782err_pci_reg:
7783err_dma:
7784 pci_disable_device(pdev);
7785 return err;
7786}
7787
7788/**
7789 * i40e_remove - Device removal routine
7790 * @pdev: PCI device information struct
7791 *
7792 * i40e_remove is called by the PCI subsystem to alert the driver
7793 * that is should release a PCI device. This could be caused by a
7794 * Hot-Plug event, or because the driver is going to be removed from
7795 * memory.
7796 **/
7797static void i40e_remove(struct pci_dev *pdev)
7798{
7799 struct i40e_pf *pf = pci_get_drvdata(pdev);
7800 i40e_status ret_code;
7801 u32 reg;
7802 int i;
7803
7804 i40e_dbg_pf_exit(pf);
7805
7806 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7807 i40e_free_vfs(pf);
7808 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7809 }
7810
7811 /* no more scheduling of any task */
7812 set_bit(__I40E_DOWN, &pf->state);
7813 del_timer_sync(&pf->service_timer);
7814 cancel_work_sync(&pf->service_task);
7815
7816 i40e_fdir_teardown(pf);
7817
7818 /* If there is a switch structure or any orphans, remove them.
7819 * This will leave only the PF's VSI remaining.
7820 */
7821 for (i = 0; i < I40E_MAX_VEB; i++) {
7822 if (!pf->veb[i])
7823 continue;
7824
7825 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7826 pf->veb[i]->uplink_seid == 0)
7827 i40e_switch_branch_release(pf->veb[i]);
7828 }
7829
7830 /* Now we can shutdown the PF's VSI, just before we kill
7831 * adminq and hmc.
7832 */
7833 if (pf->vsi[pf->lan_vsi])
7834 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7835
7836 i40e_stop_misc_vector(pf);
7837 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7838 synchronize_irq(pf->msix_entries[0].vector);
7839 free_irq(pf->msix_entries[0].vector, pf);
7840 }
7841
7842 /* shutdown and destroy the HMC */
7843 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7844 if (ret_code)
7845 dev_warn(&pdev->dev,
7846 "Failed to destroy the HMC resources: %d\n", ret_code);
7847
7848 /* shutdown the adminq */
41c445ff
JB		 7849 ret_code = i40e_shutdown_adminq(&pf->hw);
7850 if (ret_code)
7851 dev_warn(&pdev->dev,
7852 "Failed to destroy the Admin Queue resources: %d\n",
7853 ret_code);
7854
7855 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7856 i40e_clear_interrupt_scheme(pf);
7857 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7858 if (pf->vsi[i]) {
7859 i40e_vsi_clear_rings(pf->vsi[i]);
7860 i40e_vsi_clear(pf->vsi[i]);
7861 pf->vsi[i] = NULL;
7862 }
7863 }
7864
7865 for (i = 0; i < I40E_MAX_VEB; i++) {
7866 kfree(pf->veb[i]);
7867 pf->veb[i] = NULL;
7868 }
7869
7870 kfree(pf->qp_pile);
7871 kfree(pf->irq_pile);
7872 kfree(pf->sw_config);
7873 kfree(pf->vsi);
7874
7875 /* force a PF reset to clean anything leftover */
7876 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7877 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7878 i40e_flush(&pf->hw);
7879
7880 iounmap(pf->hw.hw_addr);
7881 kfree(pf);
7882 pci_release_selected_regions(pdev,
7883 pci_select_bars(pdev, IORESOURCE_MEM));
7884
7885 pci_disable_pcie_error_reporting(pdev);
7886 pci_disable_device(pdev);
7887}
7888
7889/**
7890 * i40e_pci_error_detected - warning that something funky happened in PCI land
7891 * @pdev: PCI device information struct
7892 *
7893 * Called to warn that something happened and the error handling steps
7894 * are in progress. Allows the driver to quiesce things, be ready for
7895 * remediation.
7896 **/
7897static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7898 enum pci_channel_state error)
7899{
7900 struct i40e_pf *pf = pci_get_drvdata(pdev);
7901
7902 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7903
7904 /* shutdown all operations */
9007bccd
SN		 7905 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7906 rtnl_lock();
7907 i40e_prep_for_reset(pf);
7908 rtnl_unlock();
7909 }
41c445ff
JB		 7910
7911 /* Request a slot reset */
7912 return PCI_ERS_RESULT_NEED_RESET;
7913}
7914
7915/**
7916 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7917 * @pdev: PCI device information struct
7918 *
7919 * Called to find if the driver can work with the device now that
7920 * the pci slot has been reset. If a basic connection seems good
7921 * (registers are readable and have sane content) then return a
7922 * happy little PCI_ERS_RESULT_xxx.
7923 **/
7924static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7925{
7926 struct i40e_pf *pf = pci_get_drvdata(pdev);
7927 pci_ers_result_t result;
7928 int err;
7929 u32 reg;
7930
7931 dev_info(&pdev->dev, "%s\n", __func__);
7932 if (pci_enable_device_mem(pdev)) {
7933 dev_info(&pdev->dev,
7934 "Cannot re-enable PCI device after reset.\n");
7935 result = PCI_ERS_RESULT_DISCONNECT;
7936 } else {
7937 pci_set_master(pdev);
7938 pci_restore_state(pdev);
7939 pci_save_state(pdev);
7940 pci_wake_from_d3(pdev, false);
7941
7942 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7943 if (reg == 0)
7944 result = PCI_ERS_RESULT_RECOVERED;
7945 else
7946 result = PCI_ERS_RESULT_DISCONNECT;
7947 }
7948
7949 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7950 if (err) {
7951 dev_info(&pdev->dev,
7952 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7953 err);
7954 /* non-fatal, continue */
7955 }
7956
7957 return result;
7958}
7959
7960/**
7961 * i40e_pci_error_resume - restart operations after PCI error recovery
7962 * @pdev: PCI device information struct
7963 *
7964 * Called to allow the driver to bring things back up after PCI error
7965 * and/or reset recovery has finished.
7966 **/
7967static void i40e_pci_error_resume(struct pci_dev *pdev)
7968{
7969 struct i40e_pf *pf = pci_get_drvdata(pdev);
7970
7971 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 7972 if (test_bit(__I40E_SUSPENDED, &pf->state))
7973 return;
7974
7975 rtnl_lock();
41c445ff 7976 i40e_handle_reset_warning(pf);
9007bccd
SN		 7977 rtnl_lock();
7978}
7979
7980/**
7981 * i40e_shutdown - PCI callback for shutting down
7982 * @pdev: PCI device information struct
7983 **/
7984static void i40e_shutdown(struct pci_dev *pdev)
7985{
7986 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 7987 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 7988
7989 set_bit(__I40E_SUSPENDED, &pf->state);
7990 set_bit(__I40E_DOWN, &pf->state);
7991 rtnl_lock();
7992 i40e_prep_for_reset(pf);
7993 rtnl_unlock();
7994
8e2773ae
SN		 7995 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
7996 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
7997
9007bccd 7998 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 7999 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8000 pci_set_power_state(pdev, PCI_D3hot);
8001 }
8002}
8003
8004#ifdef CONFIG_PM
8005/**
8006 * i40e_suspend - PCI callback for moving to D3
8007 * @pdev: PCI device information struct
8008 **/
8009static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8010{
8011 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8012 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8013
8014 set_bit(__I40E_SUSPENDED, &pf->state);
8015 set_bit(__I40E_DOWN, &pf->state);
8016 rtnl_lock();
8017 i40e_prep_for_reset(pf);
8018 rtnl_unlock();
8019
8e2773ae
SN		 8020 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8021 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8022
8023 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8024 pci_set_power_state(pdev, PCI_D3hot);
8025
8026 return 0;
41c445ff
JB		 8027}
8028
9007bccd
SN		 8029/**
8030 * i40e_resume - PCI callback for waking up from D3
8031 * @pdev: PCI device information struct
8032 **/
8033static int i40e_resume(struct pci_dev *pdev)
8034{
8035 struct i40e_pf *pf = pci_get_drvdata(pdev);
8036 u32 err;
8037
8038 pci_set_power_state(pdev, PCI_D0);
8039 pci_restore_state(pdev);
8040 /* pci_restore_state() clears dev->state_saves, so
8041 * call pci_save_state() again to restore it.
8042 */
8043 pci_save_state(pdev);
8044
8045 err = pci_enable_device_mem(pdev);
8046 if (err) {
8047 dev_err(&pdev->dev,
8048 "%s: Cannot enable PCI device from suspend\n",
8049 __func__);
8050 return err;
8051 }
8052 pci_set_master(pdev);
8053
8054 /* no wakeup events while running */
8055 pci_wake_from_d3(pdev, false);
8056
8057 /* handling the reset will rebuild the device state */
8058 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8059 clear_bit(__I40E_DOWN, &pf->state);
8060 rtnl_lock();
8061 i40e_reset_and_rebuild(pf, false);
8062 rtnl_unlock();
8063 }
8064
8065 return 0;
8066}
8067
8068#endif
41c445ff
JB		 8069static const struct pci_error_handlers i40e_err_handler = {
8070 .error_detected = i40e_pci_error_detected,
8071 .slot_reset = i40e_pci_error_slot_reset,
8072 .resume = i40e_pci_error_resume,
8073};
8074
8075static struct pci_driver i40e_driver = {
8076 .name = i40e_driver_name,
8077 .id_table = i40e_pci_tbl,
8078 .probe = i40e_probe,
8079 .remove = i40e_remove,
9007bccd
SN		 8080#ifdef CONFIG_PM
8081 .suspend = i40e_suspend,
8082 .resume = i40e_resume,
8083#endif
8084 .shutdown = i40e_shutdown,
41c445ff
JB		 8085 .err_handler = &i40e_err_handler,
8086 .sriov_configure = i40e_pci_sriov_configure,
8087};
8088
8089/**
8090 * i40e_init_module - Driver registration routine
8091 *
8092 * i40e_init_module is the first routine called when the driver is
8093 * loaded. All it does is register with the PCI subsystem.
8094 **/
8095static int __init i40e_init_module(void)
8096{
8097 pr_info("%s: %s - version %s\n", i40e_driver_name,
8098 i40e_driver_string, i40e_driver_version_str);
8099 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8100 i40e_dbg_init();
8101 return pci_register_driver(&i40e_driver);
8102}
8103module_init(i40e_init_module);
8104
8105/**
8106 * i40e_exit_module - Driver exit cleanup routine
8107 *
8108 * i40e_exit_module is called just before the driver is removed
8109 * from memory.
8110 **/
8111static void __exit i40e_exit_module(void)
8112{
8113 pci_unregister_driver(&i40e_driver);
8114 i40e_dbg_exit();
8115}
8116module_exit(i40e_exit_module);
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