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i40e: allow user to set LAA again
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
e454d6bf 41#define DRV_VERSION_MINOR 4
7974d5e5 42#define DRV_VERSION_BUILD 13
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
281 pf->tx_timeout_recovery_level = 0;
282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 307 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
308 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 309 break;
310 }
311 i40e_service_event_schedule(pf);
312 pf->tx_timeout_recovery_level++;
313}
314
315/**
316 * i40e_release_rx_desc - Store the new tail and head values
317 * @rx_ring: ring to bump
318 * @val: new head index
319 **/
320static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
321{
322 rx_ring->next_to_use = val;
323
324 /* Force memory writes to complete before letting h/w
325 * know there are new descriptors to fetch. (Only
326 * applicable for weak-ordered memory model archs,
327 * such as IA-64).
328 */
329 wmb();
330 writel(val, rx_ring->tail);
331}
332
333/**
334 * i40e_get_vsi_stats_struct - Get System Network Statistics
335 * @vsi: the VSI we care about
336 *
337 * Returns the address of the device statistics structure.
338 * The statistics are actually updated from the service task.
339 **/
340struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
341{
342 return &vsi->net_stats;
343}
344
345/**
346 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
347 * @netdev: network interface device structure
348 *
349 * Returns the address of the device statistics structure.
350 * The statistics are actually updated from the service task.
351 **/
352static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
353 struct net_device *netdev,
980e9b11 354 struct rtnl_link_stats64 *stats)
41c445ff
JB		 355{
356 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 357 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
57a7744e 378 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
57a7744e 381 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
57a7744e 388 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
57a7744e 391 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
a5282f44 398 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 426 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 436 }
8e9dca53 437 }
41c445ff
JB		 438 vsi->stat_offsets_loaded = false;
439}
440
441/**
442 * i40e_pf_reset_stats - Reset all of the stats for the given pf
443 * @pf: the PF to be reset
444 **/
445void i40e_pf_reset_stats(struct i40e_pf *pf)
446{
e91fdf76
SN		 447 int i;
448
41c445ff
JB		 449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
e91fdf76
SN		 452
453 for (i = 0; i < I40E_MAX_VEB; i++) {
454 if (pf->veb[i]) {
455 memset(&pf->veb[i]->stats, 0,
456 sizeof(pf->veb[i]->stats));
457 memset(&pf->veb[i]->stats_offsets, 0,
458 sizeof(pf->veb[i]->stats_offsets));
459 pf->veb[i]->stat_offsets_loaded = false;
460 }
461 }
41c445ff
JB		 462}
463
464/**
465 * i40e_stat_update48 - read and update a 48 bit stat from the chip
466 * @hw: ptr to the hardware info
467 * @hireg: the high 32 bit reg to read
468 * @loreg: the low 32 bit reg to read
469 * @offset_loaded: has the initial offset been loaded yet
470 * @offset: ptr to current offset value
471 * @stat: ptr to the stat
472 *
473 * Since the device stats are not reset at PFReset, they likely will not
474 * be zeroed when the driver starts. We'll save the first values read
475 * and use them as offsets to be subtracted from the raw values in order
476 * to report stats that count from zero. In the process, we also manage
477 * the potential roll-over.
478 **/
479static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
480 bool offset_loaded, u64 *offset, u64 *stat)
481{
482 u64 new_data;
483
ab60085e 484 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 485 new_data = rd32(hw, loreg);
486 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
487 } else {
488 new_data = rd64(hw, loreg);
489 }
490 if (!offset_loaded)
491 *offset = new_data;
492 if (likely(new_data >= *offset))
493 *stat = new_data - *offset;
494 else
495 *stat = (new_data + ((u64)1 << 48)) - *offset;
496 *stat &= 0xFFFFFFFFFFFFULL;
497}
498
499/**
500 * i40e_stat_update32 - read and update a 32 bit stat from the chip
501 * @hw: ptr to the hardware info
502 * @reg: the hw reg to read
503 * @offset_loaded: has the initial offset been loaded yet
504 * @offset: ptr to current offset value
505 * @stat: ptr to the stat
506 **/
507static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
508 bool offset_loaded, u64 *offset, u64 *stat)
509{
510 u32 new_data;
511
512 new_data = rd32(hw, reg);
513 if (!offset_loaded)
514 *offset = new_data;
515 if (likely(new_data >= *offset))
516 *stat = (u32)(new_data - *offset);
517 else
518 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
519}
520
521/**
522 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
523 * @vsi: the VSI to be updated
524 **/
525void i40e_update_eth_stats(struct i40e_vsi *vsi)
526{
527 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
528 struct i40e_pf *pf = vsi->back;
529 struct i40e_hw *hw = &pf->hw;
530 struct i40e_eth_stats *oes;
531 struct i40e_eth_stats *es; /* device's eth stats */
532
533 es = &vsi->eth_stats;
534 oes = &vsi->eth_stats_offsets;
535
536 /* Gather up the stats that the hw collects */
537 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
538 vsi->stat_offsets_loaded,
539 &oes->tx_errors, &es->tx_errors);
540 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 543 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
546 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
547 vsi->stat_offsets_loaded,
548 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 549
550 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
551 I40E_GLV_GORCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_bytes, &es->rx_bytes);
554 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
555 I40E_GLV_UPRCL(stat_idx),
556 vsi->stat_offsets_loaded,
557 &oes->rx_unicast, &es->rx_unicast);
558 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
559 I40E_GLV_MPRCL(stat_idx),
560 vsi->stat_offsets_loaded,
561 &oes->rx_multicast, &es->rx_multicast);
562 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
563 I40E_GLV_BPRCL(stat_idx),
564 vsi->stat_offsets_loaded,
565 &oes->rx_broadcast, &es->rx_broadcast);
566
567 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
568 I40E_GLV_GOTCL(stat_idx),
569 vsi->stat_offsets_loaded,
570 &oes->tx_bytes, &es->tx_bytes);
571 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
572 I40E_GLV_UPTCL(stat_idx),
573 vsi->stat_offsets_loaded,
574 &oes->tx_unicast, &es->tx_unicast);
575 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
576 I40E_GLV_MPTCL(stat_idx),
577 vsi->stat_offsets_loaded,
578 &oes->tx_multicast, &es->tx_multicast);
579 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
580 I40E_GLV_BPTCL(stat_idx),
581 vsi->stat_offsets_loaded,
582 &oes->tx_broadcast, &es->tx_broadcast);
583 vsi->stat_offsets_loaded = true;
584}
585
586/**
587 * i40e_update_veb_stats - Update Switch component statistics
588 * @veb: the VEB being updated
589 **/
590static void i40e_update_veb_stats(struct i40e_veb *veb)
591{
592 struct i40e_pf *pf = veb->pf;
593 struct i40e_hw *hw = &pf->hw;
594 struct i40e_eth_stats *oes;
595 struct i40e_eth_stats *es; /* device's eth stats */
596 int idx = 0;
597
598 idx = veb->stats_idx;
599 es = &veb->stats;
600 oes = &veb->stats_offsets;
601
602 /* Gather up the stats that the hw collects */
603 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
604 veb->stat_offsets_loaded,
605 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 606 if (hw->revision_id > 0)
607 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
608 veb->stat_offsets_loaded,
609 &oes->rx_unknown_protocol,
610 &es->rx_unknown_protocol);
41c445ff
JB		 611 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->rx_bytes, &es->rx_bytes);
614 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->rx_unicast, &es->rx_unicast);
617 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->rx_multicast, &es->rx_multicast);
620 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
621 veb->stat_offsets_loaded,
622 &oes->rx_broadcast, &es->rx_broadcast);
623
624 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
625 veb->stat_offsets_loaded,
626 &oes->tx_bytes, &es->tx_bytes);
627 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
628 veb->stat_offsets_loaded,
629 &oes->tx_unicast, &es->tx_unicast);
630 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
631 veb->stat_offsets_loaded,
632 &oes->tx_multicast, &es->tx_multicast);
633 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
634 veb->stat_offsets_loaded,
635 &oes->tx_broadcast, &es->tx_broadcast);
636 veb->stat_offsets_loaded = true;
637}
638
639/**
640 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
641 * @pf: the corresponding PF
642 *
643 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
644 **/
645static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
646{
647 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
648 struct i40e_hw_port_stats *nsd = &pf->stats;
649 struct i40e_hw *hw = &pf->hw;
650 u64 xoff = 0;
651 u16 i, v;
652
653 if ((hw->fc.current_mode != I40E_FC_FULL) &&
654 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
655 return;
656
657 xoff = nsd->link_xoff_rx;
658 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
659 pf->stat_offsets_loaded,
660 &osd->link_xoff_rx, &nsd->link_xoff_rx);
661
662 /* No new LFC xoff rx */
663 if (!(nsd->link_xoff_rx - xoff))
664 return;
665
666 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 667 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 668 struct i40e_vsi *vsi = pf->vsi[v];
669
ddfda80f 670 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 671 continue;
672
673 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 674 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 675 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
676 }
677 }
678}
679
680/**
681 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
682 * @pf: the corresponding PF
683 *
684 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
685 **/
686static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
687{
688 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
689 struct i40e_hw_port_stats *nsd = &pf->stats;
690 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
691 struct i40e_dcbx_config *dcb_cfg;
692 struct i40e_hw *hw = &pf->hw;
693 u16 i, v;
694 u8 tc;
695
696 dcb_cfg = &hw->local_dcbx_config;
697
698 /* See if DCB enabled with PFC TC */
699 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
700 !(dcb_cfg->pfc.pfcenable)) {
701 i40e_update_link_xoff_rx(pf);
702 return;
703 }
704
705 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
706 u64 prio_xoff = nsd->priority_xoff_rx[i];
707 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
708 pf->stat_offsets_loaded,
709 &osd->priority_xoff_rx[i],
710 &nsd->priority_xoff_rx[i]);
711
712 /* No new PFC xoff rx */
713 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
714 continue;
715 /* Get the TC for given priority */
716 tc = dcb_cfg->etscfg.prioritytable[i];
717 xoff[tc] = true;
718 }
719
720 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 721 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 722 struct i40e_vsi *vsi = pf->vsi[v];
723
ddfda80f 724 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 725 continue;
726
727 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 728 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 729
730 tc = ring->dcb_tc;
731 if (xoff[tc])
732 clear_bit(__I40E_HANG_CHECK_ARMED,
733 &ring->state);
734 }
735 }
736}
737
738/**
7812fddc 739 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 740 * @vsi: the VSI to be updated
741 *
742 * There are a few instances where we store the same stat in a
743 * couple of different structs. This is partly because we have
744 * the netdev stats that need to be filled out, which is slightly
745 * different from the "eth_stats" defined by the chip and used in
7812fddc 746 * VF communications. We sort it out here.
41c445ff 747 **/
7812fddc 748static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 749{
750 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 751 struct rtnl_link_stats64 *ons;
752 struct rtnl_link_stats64 *ns; /* netdev stats */
753 struct i40e_eth_stats *oes;
754 struct i40e_eth_stats *es; /* device's eth stats */
755 u32 tx_restart, tx_busy;
756 u32 rx_page, rx_buf;
757 u64 rx_p, rx_b;
758 u64 tx_p, tx_b;
41c445ff
JB		 759 u16 q;
760
761 if (test_bit(__I40E_DOWN, &vsi->state) ||
762 test_bit(__I40E_CONFIG_BUSY, &pf->state))
763 return;
764
765 ns = i40e_get_vsi_stats_struct(vsi);
766 ons = &vsi->net_stats_offsets;
767 es = &vsi->eth_stats;
768 oes = &vsi->eth_stats_offsets;
769
770 /* Gather up the netdev and vsi stats that the driver collects
771 * on the fly during packet processing
772 */
773 rx_b = rx_p = 0;
774 tx_b = tx_p = 0;
775 tx_restart = tx_busy = 0;
776 rx_page = 0;
777 rx_buf = 0;
980e9b11 778 rcu_read_lock();
41c445ff
JB		 779 for (q = 0; q < vsi->num_queue_pairs; q++) {
780 struct i40e_ring *p;
980e9b11
AD		 781 u64 bytes, packets;
782 unsigned int start;
783
784 /* locate Tx ring */
785 p = ACCESS_ONCE(vsi->tx_rings[q]);
786
787 do {
57a7744e 788 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 789 packets = p->stats.packets;
790 bytes = p->stats.bytes;
57a7744e 791 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 792 tx_b += bytes;
793 tx_p += packets;
794 tx_restart += p->tx_stats.restart_queue;
795 tx_busy += p->tx_stats.tx_busy;
41c445ff 796
980e9b11
AD		 797 /* Rx queue is part of the same block as Tx queue */
798 p = &p[1];
799 do {
57a7744e 800 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 801 packets = p->stats.packets;
802 bytes = p->stats.bytes;
57a7744e 803 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 804 rx_b += bytes;
805 rx_p += packets;
420136cc
MW		 806 rx_buf += p->rx_stats.alloc_buff_failed;
807 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 808 }
980e9b11 809 rcu_read_unlock();
41c445ff
JB		 810 vsi->tx_restart = tx_restart;
811 vsi->tx_busy = tx_busy;
812 vsi->rx_page_failed = rx_page;
813 vsi->rx_buf_failed = rx_buf;
814
815 ns->rx_packets = rx_p;
816 ns->rx_bytes = rx_b;
817 ns->tx_packets = tx_p;
818 ns->tx_bytes = tx_b;
819
41c445ff 820 /* update netdev stats from eth stats */
7812fddc 821 i40e_update_eth_stats(vsi);
41c445ff
JB		 822 ons->tx_errors = oes->tx_errors;
823 ns->tx_errors = es->tx_errors;
824 ons->multicast = oes->rx_multicast;
825 ns->multicast = es->rx_multicast;
41a9e55c
SN		 826 ons->rx_dropped = oes->rx_discards;
827 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 828 ons->tx_dropped = oes->tx_discards;
829 ns->tx_dropped = es->tx_discards;
830
7812fddc 831 /* pull in a couple PF stats if this is the main vsi */
41c445ff 832 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 833 ns->rx_crc_errors = pf->stats.crc_errors;
834 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
835 ns->rx_length_errors = pf->stats.rx_length_errors;
836 }
837}
41c445ff 838
7812fddc
SN		 839/**
840 * i40e_update_pf_stats - Update the pf statistics counters.
841 * @pf: the PF to be updated
842 **/
843static void i40e_update_pf_stats(struct i40e_pf *pf)
844{
845 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
846 struct i40e_hw_port_stats *nsd = &pf->stats;
847 struct i40e_hw *hw = &pf->hw;
848 u32 val;
849 int i;
41c445ff 850
7812fddc
SN		 851 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
852 I40E_GLPRT_GORCL(hw->port),
853 pf->stat_offsets_loaded,
854 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
855 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
856 I40E_GLPRT_GOTCL(hw->port),
857 pf->stat_offsets_loaded,
858 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
859 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
860 pf->stat_offsets_loaded,
861 &osd->eth.rx_discards,
862 &nsd->eth.rx_discards);
863 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
864 pf->stat_offsets_loaded,
865 &osd->eth.tx_discards,
866 &nsd->eth.tx_discards);
41c445ff 867
532d283d
SN		 868 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
869 I40E_GLPRT_UPRCL(hw->port),
870 pf->stat_offsets_loaded,
871 &osd->eth.rx_unicast,
872 &nsd->eth.rx_unicast);
7812fddc
SN		 873 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
874 I40E_GLPRT_MPRCL(hw->port),
875 pf->stat_offsets_loaded,
876 &osd->eth.rx_multicast,
877 &nsd->eth.rx_multicast);
532d283d
SN		 878 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
879 I40E_GLPRT_BPRCL(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->eth.rx_broadcast,
882 &nsd->eth.rx_broadcast);
883 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
884 I40E_GLPRT_UPTCL(hw->port),
885 pf->stat_offsets_loaded,
886 &osd->eth.tx_unicast,
887 &nsd->eth.tx_unicast);
888 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
889 I40E_GLPRT_MPTCL(hw->port),
890 pf->stat_offsets_loaded,
891 &osd->eth.tx_multicast,
892 &nsd->eth.tx_multicast);
893 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
894 I40E_GLPRT_BPTCL(hw->port),
895 pf->stat_offsets_loaded,
896 &osd->eth.tx_broadcast,
897 &nsd->eth.tx_broadcast);
41c445ff 898
7812fddc
SN		 899 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
900 pf->stat_offsets_loaded,
901 &osd->tx_dropped_link_down,
902 &nsd->tx_dropped_link_down);
41c445ff 903
7812fddc
SN		 904 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->crc_errors, &nsd->crc_errors);
41c445ff 907
7812fddc
SN		 908 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 911
7812fddc
SN		 912 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->mac_local_faults,
915 &nsd->mac_local_faults);
916 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->mac_remote_faults,
919 &nsd->mac_remote_faults);
41c445ff 920
7812fddc
SN		 921 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
922 pf->stat_offsets_loaded,
923 &osd->rx_length_errors,
924 &nsd->rx_length_errors);
41c445ff 925
7812fddc
SN		 926 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
927 pf->stat_offsets_loaded,
928 &osd->link_xon_rx, &nsd->link_xon_rx);
929 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
930 pf->stat_offsets_loaded,
931 &osd->link_xon_tx, &nsd->link_xon_tx);
932 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
933 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 936
7812fddc
SN		 937 for (i = 0; i < 8; i++) {
938 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 939 pf->stat_offsets_loaded,
7812fddc
SN		 940 &osd->priority_xon_rx[i],
941 &nsd->priority_xon_rx[i]);
942 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 943 pf->stat_offsets_loaded,
7812fddc
SN		 944 &osd->priority_xon_tx[i],
945 &nsd->priority_xon_tx[i]);
946 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 947 pf->stat_offsets_loaded,
7812fddc
SN		 948 &osd->priority_xoff_tx[i],
949 &nsd->priority_xoff_tx[i]);
950 i40e_stat_update32(hw,
951 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 952 pf->stat_offsets_loaded,
7812fddc
SN		 953 &osd->priority_xon_2_xoff[i],
954 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 955 }
956
7812fddc
SN		 957 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
958 I40E_GLPRT_PRC64L(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->rx_size_64, &nsd->rx_size_64);
961 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
962 I40E_GLPRT_PRC127L(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->rx_size_127, &nsd->rx_size_127);
965 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
966 I40E_GLPRT_PRC255L(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_size_255, &nsd->rx_size_255);
969 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
970 I40E_GLPRT_PRC511L(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_size_511, &nsd->rx_size_511);
973 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
974 I40E_GLPRT_PRC1023L(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->rx_size_1023, &nsd->rx_size_1023);
977 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
978 I40E_GLPRT_PRC1522L(hw->port),
979 pf->stat_offsets_loaded,
980 &osd->rx_size_1522, &nsd->rx_size_1522);
981 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
982 I40E_GLPRT_PRC9522L(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->rx_size_big, &nsd->rx_size_big);
985
986 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
987 I40E_GLPRT_PTC64L(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->tx_size_64, &nsd->tx_size_64);
990 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
991 I40E_GLPRT_PTC127L(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->tx_size_127, &nsd->tx_size_127);
994 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
995 I40E_GLPRT_PTC255L(hw->port),
996 pf->stat_offsets_loaded,
997 &osd->tx_size_255, &nsd->tx_size_255);
998 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
999 I40E_GLPRT_PTC511L(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->tx_size_511, &nsd->tx_size_511);
1002 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1003 I40E_GLPRT_PTC1023L(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->tx_size_1023, &nsd->tx_size_1023);
1006 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1007 I40E_GLPRT_PTC1522L(hw->port),
1008 pf->stat_offsets_loaded,
1009 &osd->tx_size_1522, &nsd->tx_size_1522);
1010 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1011 I40E_GLPRT_PTC9522L(hw->port),
1012 pf->stat_offsets_loaded,
1013 &osd->tx_size_big, &nsd->tx_size_big);
1014
1015 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1016 pf->stat_offsets_loaded,
1017 &osd->rx_undersize, &nsd->rx_undersize);
1018 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1019 pf->stat_offsets_loaded,
1020 &osd->rx_fragments, &nsd->rx_fragments);
1021 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_oversize, &nsd->rx_oversize);
1024 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_jabber, &nsd->rx_jabber);
1027
433c47de
ASJ		 1028 /* FDIR stats */
1029 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1030 pf->stat_offsets_loaded,
1031 &osd->fd_atr_match, &nsd->fd_atr_match);
1032 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1033 pf->stat_offsets_loaded,
1034 &osd->fd_sb_match, &nsd->fd_sb_match);
1035
7812fddc
SN		 1036 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1037 nsd->tx_lpi_status =
1038 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1039 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1040 nsd->rx_lpi_status =
1041 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1042 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1043 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1044 pf->stat_offsets_loaded,
1045 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1046 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1047 pf->stat_offsets_loaded,
1048 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1049
41c445ff
JB		 1050 pf->stat_offsets_loaded = true;
1051}
1052
7812fddc
SN		 1053/**
1054 * i40e_update_stats - Update the various statistics counters.
1055 * @vsi: the VSI to be updated
1056 *
1057 * Update the various stats for this VSI and its related entities.
1058 **/
1059void i40e_update_stats(struct i40e_vsi *vsi)
1060{
1061 struct i40e_pf *pf = vsi->back;
1062
1063 if (vsi == pf->vsi[pf->lan_vsi])
1064 i40e_update_pf_stats(pf);
1065
1066 i40e_update_vsi_stats(vsi);
1067}
1068
41c445ff
JB		 1069/**
1070 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1071 * @vsi: the VSI to be searched
1072 * @macaddr: the MAC address
1073 * @vlan: the vlan
1074 * @is_vf: make sure its a vf filter, else doesn't matter
1075 * @is_netdev: make sure its a netdev filter, else doesn't matter
1076 *
1077 * Returns ptr to the filter object or NULL
1078 **/
1079static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1080 u8 *macaddr, s16 vlan,
1081 bool is_vf, bool is_netdev)
1082{
1083 struct i40e_mac_filter *f;
1084
1085 if (!vsi || !macaddr)
1086 return NULL;
1087
1088 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1089 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1090 (vlan == f->vlan) &&
1091 (!is_vf || f->is_vf) &&
1092 (!is_netdev || f->is_netdev))
1093 return f;
1094 }
1095 return NULL;
1096}
1097
1098/**
1099 * i40e_find_mac - Find a mac addr in the macvlan filters list
1100 * @vsi: the VSI to be searched
1101 * @macaddr: the MAC address we are searching for
1102 * @is_vf: make sure its a vf filter, else doesn't matter
1103 * @is_netdev: make sure its a netdev filter, else doesn't matter
1104 *
1105 * Returns the first filter with the provided MAC address or NULL if
1106 * MAC address was not found
1107 **/
1108struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1109 bool is_vf, bool is_netdev)
1110{
1111 struct i40e_mac_filter *f;
1112
1113 if (!vsi || !macaddr)
1114 return NULL;
1115
1116 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1117 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1118 (!is_vf || f->is_vf) &&
1119 (!is_netdev || f->is_netdev))
1120 return f;
1121 }
1122 return NULL;
1123}
1124
1125/**
1126 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1127 * @vsi: the VSI to be searched
1128 *
1129 * Returns true if VSI is in vlan mode or false otherwise
1130 **/
1131bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1132{
1133 struct i40e_mac_filter *f;
1134
1135 /* Only -1 for all the filters denotes not in vlan mode
1136 * so we have to go through all the list in order to make sure
1137 */
1138 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1139 if (f->vlan >= 0)
1140 return true;
1141 }
1142
1143 return false;
1144}
1145
1146/**
1147 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1148 * @vsi: the VSI to be searched
1149 * @macaddr: the mac address to be filtered
1150 * @is_vf: true if it is a vf
1151 * @is_netdev: true if it is a netdev
1152 *
1153 * Goes through all the macvlan filters and adds a
1154 * macvlan filter for each unique vlan that already exists
1155 *
1156 * Returns first filter found on success, else NULL
1157 **/
1158struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1159 bool is_vf, bool is_netdev)
1160{
1161 struct i40e_mac_filter *f;
1162
1163 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1164 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1165 is_vf, is_netdev)) {
1166 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1167 is_vf, is_netdev))
41c445ff
JB		 1168 return NULL;
1169 }
1170 }
1171
1172 return list_first_entry_or_null(&vsi->mac_filter_list,
1173 struct i40e_mac_filter, list);
1174}
1175
8c27d42e
GR		 1176/**
1177 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1178 * @vsi: the PF Main VSI - inappropriate for any other VSI
1179 * @macaddr: the MAC address
1180 **/
1181static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
1182{
1183 struct i40e_aqc_remove_macvlan_element_data element;
1184 struct i40e_pf *pf = vsi->back;
1185 i40e_status aq_ret;
1186
1187 /* Only appropriate for the PF main VSI */
1188 if (vsi->type != I40E_VSI_MAIN)
1189 return;
1190
1191 ether_addr_copy(element.mac_addr, macaddr);
1192 element.vlan_tag = 0;
1193 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1194 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1195 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1196 if (aq_ret)
1197 dev_err(&pf->pdev->dev, "Could not remove default MAC-VLAN\n");
1198}
1199
41c445ff
JB		 1200/**
1201 * i40e_add_filter - Add a mac/vlan filter to the VSI
1202 * @vsi: the VSI to be searched
1203 * @macaddr: the MAC address
1204 * @vlan: the vlan
1205 * @is_vf: make sure its a vf filter, else doesn't matter
1206 * @is_netdev: make sure its a netdev filter, else doesn't matter
1207 *
1208 * Returns ptr to the filter object or NULL when no memory available.
1209 **/
1210struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1211 u8 *macaddr, s16 vlan,
1212 bool is_vf, bool is_netdev)
1213{
1214 struct i40e_mac_filter *f;
1215
1216 if (!vsi || !macaddr)
1217 return NULL;
1218
1219 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1220 if (!f) {
1221 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1222 if (!f)
1223 goto add_filter_out;
1224
9a173901 1225 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1226 f->vlan = vlan;
1227 f->changed = true;
1228
1229 INIT_LIST_HEAD(&f->list);
1230 list_add(&f->list, &vsi->mac_filter_list);
1231 }
1232
1233 /* increment counter and add a new flag if needed */
1234 if (is_vf) {
1235 if (!f->is_vf) {
1236 f->is_vf = true;
1237 f->counter++;
1238 }
1239 } else if (is_netdev) {
1240 if (!f->is_netdev) {
1241 f->is_netdev = true;
1242 f->counter++;
1243 }
1244 } else {
1245 f->counter++;
1246 }
1247
1248 /* changed tells sync_filters_subtask to
1249 * push the filter down to the firmware
1250 */
1251 if (f->changed) {
1252 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1253 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1254 }
1255
1256add_filter_out:
1257 return f;
1258}
1259
1260/**
1261 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1262 * @vsi: the VSI to be searched
1263 * @macaddr: the MAC address
1264 * @vlan: the vlan
1265 * @is_vf: make sure it's a vf filter, else doesn't matter
1266 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1267 **/
1268void i40e_del_filter(struct i40e_vsi *vsi,
1269 u8 *macaddr, s16 vlan,
1270 bool is_vf, bool is_netdev)
1271{
1272 struct i40e_mac_filter *f;
1273
1274 if (!vsi || !macaddr)
1275 return;
1276
1277 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1278 if (!f || f->counter == 0)
1279 return;
1280
1281 if (is_vf) {
1282 if (f->is_vf) {
1283 f->is_vf = false;
1284 f->counter--;
1285 }
1286 } else if (is_netdev) {
1287 if (f->is_netdev) {
1288 f->is_netdev = false;
1289 f->counter--;
1290 }
1291 } else {
1292 /* make sure we don't remove a filter in use by vf or netdev */
1293 int min_f = 0;
1294 min_f += (f->is_vf ? 1 : 0);
1295 min_f += (f->is_netdev ? 1 : 0);
1296
1297 if (f->counter > min_f)
1298 f->counter--;
1299 }
1300
1301 /* counter == 0 tells sync_filters_subtask to
1302 * remove the filter from the firmware's list
1303 */
1304 if (f->counter == 0) {
1305 f->changed = true;
1306 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1307 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1308 }
1309}
1310
1311/**
1312 * i40e_set_mac - NDO callback to set mac address
1313 * @netdev: network interface device structure
1314 * @p: pointer to an address structure
1315 *
1316 * Returns 0 on success, negative on failure
1317 **/
1318static int i40e_set_mac(struct net_device *netdev, void *p)
1319{
1320 struct i40e_netdev_priv *np = netdev_priv(netdev);
1321 struct i40e_vsi *vsi = np->vsi;
1322 struct sockaddr *addr = p;
1323 struct i40e_mac_filter *f;
1324
1325 if (!is_valid_ether_addr(addr->sa_data))
1326 return -EADDRNOTAVAIL;
1327
1328 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1329
80f6428f
ASJ		 1330 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1331 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1332 return -EADDRNOTAVAIL;
1333
41c445ff
JB		 1334 if (vsi->type == I40E_VSI_MAIN) {
1335 i40e_status ret;
1336 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1337 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1338 addr->sa_data, NULL);
1339 if (ret) {
1340 netdev_info(netdev,
1341 "Addr change for Main VSI failed: %d\n",
1342 ret);
1343 return -EADDRNOTAVAIL;
1344 }
41c445ff
JB		 1345 }
1346
6c8ad1ba 1347 if (!i40e_find_mac(vsi, addr->sa_data, false, true)) {
41c445ff 1348
6c8ad1ba
SN		 1349 /* In order to be sure to not drop any packets, add the
1350 * new address first then delete the old one.
1351 */
1352 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1353 false, false);
1354 if (!f)
1355 return -ENOMEM;
1356
1357 i40e_sync_vsi_filters(vsi);
1358 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1359 false, false);
1360 i40e_sync_vsi_filters(vsi);
1361 }
41c445ff 1362
6c8ad1ba
SN		 1363 if (!ether_addr_equal(netdev->dev_addr, addr->sa_data))
1364 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1365
1366 return 0;
1367}
1368
1369/**
1370 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1371 * @vsi: the VSI being setup
1372 * @ctxt: VSI context structure
1373 * @enabled_tc: Enabled TCs bitmap
1374 * @is_add: True if called before Add VSI
1375 *
1376 * Setup VSI queue mapping for enabled traffic classes.
1377 **/
1378static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1379 struct i40e_vsi_context *ctxt,
1380 u8 enabled_tc,
1381 bool is_add)
1382{
1383 struct i40e_pf *pf = vsi->back;
1384 u16 sections = 0;
1385 u8 netdev_tc = 0;
1386 u16 numtc = 0;
1387 u16 qcount;
1388 u8 offset;
1389 u16 qmap;
1390 int i;
4e3b35b0 1391 u16 num_tc_qps = 0;
41c445ff
JB		 1392
1393 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1394 offset = 0;
1395
1396 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1397 /* Find numtc from enabled TC bitmap */
1398 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1399 if (enabled_tc & (1 << i)) /* TC is enabled */
1400 numtc++;
1401 }
1402 if (!numtc) {
1403 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1404 numtc = 1;
1405 }
1406 } else {
1407 /* At least TC0 is enabled in case of non-DCB case */
1408 numtc = 1;
1409 }
1410
1411 vsi->tc_config.numtc = numtc;
1412 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1413 /* Number of queues per enabled TC */
eb051afe 1414 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1415 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1416
1417 /* Setup queue offset/count for all TCs for given VSI */
1418 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1419 /* See if the given TC is enabled for the given VSI */
1420 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1421 int pow, num_qps;
1422
41c445ff
JB		 1423 switch (vsi->type) {
1424 case I40E_VSI_MAIN:
4e3b35b0 1425 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1426 break;
1427 case I40E_VSI_FDIR:
1428 case I40E_VSI_SRIOV:
1429 case I40E_VSI_VMDQ2:
1430 default:
4e3b35b0 1431 qcount = num_tc_qps;
41c445ff
JB		 1432 WARN_ON(i != 0);
1433 break;
1434 }
4e3b35b0
NP		 1435 vsi->tc_config.tc_info[i].qoffset = offset;
1436 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1437
1438 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1439 num_qps = qcount;
41c445ff 1440 pow = 0;
4e3b35b0 1441 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1442 pow++;
1443 num_qps >>= 1;
1444 }
1445
1446 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1447 qmap =
1448 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1449 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1450
4e3b35b0 1451 offset += qcount;
41c445ff
JB		 1452 } else {
1453 /* TC is not enabled so set the offset to
1454 * default queue and allocate one queue
1455 * for the given TC.
1456 */
1457 vsi->tc_config.tc_info[i].qoffset = 0;
1458 vsi->tc_config.tc_info[i].qcount = 1;
1459 vsi->tc_config.tc_info[i].netdev_tc = 0;
1460
1461 qmap = 0;
1462 }
1463 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1464 }
1465
1466 /* Set actual Tx/Rx queue pairs */
1467 vsi->num_queue_pairs = offset;
1468
1469 /* Scheduler section valid can only be set for ADD VSI */
1470 if (is_add) {
1471 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1472
1473 ctxt->info.up_enable_bits = enabled_tc;
1474 }
1475 if (vsi->type == I40E_VSI_SRIOV) {
1476 ctxt->info.mapping_flags |=
1477 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1478 for (i = 0; i < vsi->num_queue_pairs; i++)
1479 ctxt->info.queue_mapping[i] =
1480 cpu_to_le16(vsi->base_queue + i);
1481 } else {
1482 ctxt->info.mapping_flags |=
1483 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1484 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1485 }
1486 ctxt->info.valid_sections |= cpu_to_le16(sections);
1487}
1488
1489/**
1490 * i40e_set_rx_mode - NDO callback to set the netdev filters
1491 * @netdev: network interface device structure
1492 **/
1493static void i40e_set_rx_mode(struct net_device *netdev)
1494{
1495 struct i40e_netdev_priv *np = netdev_priv(netdev);
1496 struct i40e_mac_filter *f, *ftmp;
1497 struct i40e_vsi *vsi = np->vsi;
1498 struct netdev_hw_addr *uca;
1499 struct netdev_hw_addr *mca;
1500 struct netdev_hw_addr *ha;
1501
1502 /* add addr if not already in the filter list */
1503 netdev_for_each_uc_addr(uca, netdev) {
1504 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1505 if (i40e_is_vsi_in_vlan(vsi))
1506 i40e_put_mac_in_vlan(vsi, uca->addr,
1507 false, true);
1508 else
1509 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1510 false, true);
1511 }
1512 }
1513
1514 netdev_for_each_mc_addr(mca, netdev) {
1515 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1516 if (i40e_is_vsi_in_vlan(vsi))
1517 i40e_put_mac_in_vlan(vsi, mca->addr,
1518 false, true);
1519 else
1520 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1521 false, true);
1522 }
1523 }
1524
1525 /* remove filter if not in netdev list */
1526 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1527 bool found = false;
1528
1529 if (!f->is_netdev)
1530 continue;
1531
1532 if (is_multicast_ether_addr(f->macaddr)) {
1533 netdev_for_each_mc_addr(mca, netdev) {
1534 if (ether_addr_equal(mca->addr, f->macaddr)) {
1535 found = true;
1536 break;
1537 }
1538 }
1539 } else {
1540 netdev_for_each_uc_addr(uca, netdev) {
1541 if (ether_addr_equal(uca->addr, f->macaddr)) {
1542 found = true;
1543 break;
1544 }
1545 }
1546
1547 for_each_dev_addr(netdev, ha) {
1548 if (ether_addr_equal(ha->addr, f->macaddr)) {
1549 found = true;
1550 break;
1551 }
1552 }
1553 }
1554 if (!found)
1555 i40e_del_filter(
1556 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1557 }
1558
1559 /* check for other flag changes */
1560 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1561 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1562 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1563 }
1564}
1565
1566/**
1567 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1568 * @vsi: ptr to the VSI
1569 *
1570 * Push any outstanding VSI filter changes through the AdminQ.
1571 *
1572 * Returns 0 or error value
1573 **/
1574int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1575{
1576 struct i40e_mac_filter *f, *ftmp;
1577 bool promisc_forced_on = false;
1578 bool add_happened = false;
1579 int filter_list_len = 0;
1580 u32 changed_flags = 0;
dcae29be 1581 i40e_status aq_ret = 0;
41c445ff
JB		 1582 struct i40e_pf *pf;
1583 int num_add = 0;
1584 int num_del = 0;
1585 u16 cmd_flags;
1586
1587 /* empty array typed pointers, kcalloc later */
1588 struct i40e_aqc_add_macvlan_element_data *add_list;
1589 struct i40e_aqc_remove_macvlan_element_data *del_list;
1590
1591 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1592 usleep_range(1000, 2000);
1593 pf = vsi->back;
1594
1595 if (vsi->netdev) {
1596 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1597 vsi->current_netdev_flags = vsi->netdev->flags;
1598 }
1599
1600 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1601 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1602
1603 filter_list_len = pf->hw.aq.asq_buf_size /
1604 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1605 del_list = kcalloc(filter_list_len,
1606 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1607 GFP_KERNEL);
1608 if (!del_list)
1609 return -ENOMEM;
1610
1611 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1612 if (!f->changed)
1613 continue;
1614
1615 if (f->counter != 0)
1616 continue;
1617 f->changed = false;
1618 cmd_flags = 0;
1619
1620 /* add to delete list */
9a173901 1621 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1622 del_list[num_del].vlan_tag =
1623 cpu_to_le16((u16)(f->vlan ==
1624 I40E_VLAN_ANY ? 0 : f->vlan));
1625
41c445ff
JB		 1626 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1627 del_list[num_del].flags = cmd_flags;
1628 num_del++;
1629
1630 /* unlink from filter list */
1631 list_del(&f->list);
1632 kfree(f);
1633
1634 /* flush a full buffer */
1635 if (num_del == filter_list_len) {
dcae29be 1636 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1637 vsi->seid, del_list, num_del,
1638 NULL);
1639 num_del = 0;
1640 memset(del_list, 0, sizeof(*del_list));
1641
fdfe9cbe
SN		 1642 if (aq_ret &&
1643 pf->hw.aq.asq_last_status !=
1644 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1645 dev_info(&pf->pdev->dev,
1646 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1647 aq_ret,
41c445ff
JB		 1648 pf->hw.aq.asq_last_status);
1649 }
1650 }
1651 if (num_del) {
dcae29be 1652 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1653 del_list, num_del, NULL);
1654 num_del = 0;
1655
fdfe9cbe
SN		 1656 if (aq_ret &&
1657 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1658 dev_info(&pf->pdev->dev,
1659 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1660 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1661 }
1662
1663 kfree(del_list);
1664 del_list = NULL;
1665
1666 /* do all the adds now */
1667 filter_list_len = pf->hw.aq.asq_buf_size /
1668 sizeof(struct i40e_aqc_add_macvlan_element_data),
1669 add_list = kcalloc(filter_list_len,
1670 sizeof(struct i40e_aqc_add_macvlan_element_data),
1671 GFP_KERNEL);
1672 if (!add_list)
1673 return -ENOMEM;
1674
1675 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1676 if (!f->changed)
1677 continue;
1678
1679 if (f->counter == 0)
1680 continue;
1681 f->changed = false;
1682 add_happened = true;
1683 cmd_flags = 0;
1684
1685 /* add to add array */
9a173901 1686 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1687 add_list[num_add].vlan_tag =
1688 cpu_to_le16(
1689 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1690 add_list[num_add].queue_number = 0;
1691
1692 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1693 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1694 num_add++;
1695
1696 /* flush a full buffer */
1697 if (num_add == filter_list_len) {
dcae29be
JB		 1698 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1699 add_list, num_add,
1700 NULL);
41c445ff
JB		 1701 num_add = 0;
1702
dcae29be 1703 if (aq_ret)
41c445ff
JB		 1704 break;
1705 memset(add_list, 0, sizeof(*add_list));
1706 }
1707 }
1708 if (num_add) {
dcae29be
JB		 1709 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1710 add_list, num_add, NULL);
41c445ff
JB		 1711 num_add = 0;
1712 }
1713 kfree(add_list);
1714 add_list = NULL;
1715
dcae29be 1716 if (add_happened && (!aq_ret)) {
41c445ff 1717 /* do nothing */;
dcae29be 1718 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1719 dev_info(&pf->pdev->dev,
1720 "add filter failed, err %d, aq_err %d\n",
dcae29be 1721 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1722 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1723 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1724 &vsi->state)) {
1725 promisc_forced_on = true;
1726 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1727 &vsi->state);
1728 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1729 }
1730 }
1731 }
1732
1733 /* check for changes in promiscuous modes */
1734 if (changed_flags & IFF_ALLMULTI) {
1735 bool cur_multipromisc;
1736 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1737 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1738 vsi->seid,
1739 cur_multipromisc,
1740 NULL);
1741 if (aq_ret)
41c445ff
JB		 1742 dev_info(&pf->pdev->dev,
1743 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1744 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1745 }
1746 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1747 bool cur_promisc;
1748 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1749 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1750 &vsi->state));
dcae29be
JB		 1751 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1752 vsi->seid,
1753 cur_promisc, NULL);
1754 if (aq_ret)
41c445ff
JB		 1755 dev_info(&pf->pdev->dev,
1756 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1757 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1758 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1759 vsi->seid,
1760 cur_promisc, NULL);
1761 if (aq_ret)
1762 dev_info(&pf->pdev->dev,
1763 "set brdcast promisc failed, err %d, aq_err %d\n",
1764 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1765 }
1766
1767 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1768 return 0;
1769}
1770
1771/**
1772 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1773 * @pf: board private structure
1774 **/
1775static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1776{
1777 int v;
1778
1779 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1780 return;
1781 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1782
505682cd 1783 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1784 if (pf->vsi[v] &&
1785 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1786 i40e_sync_vsi_filters(pf->vsi[v]);
1787 }
1788}
1789
1790/**
1791 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1792 * @netdev: network interface device structure
1793 * @new_mtu: new value for maximum frame size
1794 *
1795 * Returns 0 on success, negative on failure
1796 **/
1797static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1798{
1799 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1800 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1801 struct i40e_vsi *vsi = np->vsi;
1802
1803 /* MTU < 68 is an error and causes problems on some kernels */
1804 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1805 return -EINVAL;
1806
1807 netdev_info(netdev, "changing MTU from %d to %d\n",
1808 netdev->mtu, new_mtu);
1809 netdev->mtu = new_mtu;
1810 if (netif_running(netdev))
1811 i40e_vsi_reinit_locked(vsi);
1812
1813 return 0;
1814}
1815
beb0dff1
JK		 1816/**
1817 * i40e_ioctl - Access the hwtstamp interface
1818 * @netdev: network interface device structure
1819 * @ifr: interface request data
1820 * @cmd: ioctl command
1821 **/
1822int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1823{
1824 struct i40e_netdev_priv *np = netdev_priv(netdev);
1825 struct i40e_pf *pf = np->vsi->back;
1826
1827 switch (cmd) {
1828 case SIOCGHWTSTAMP:
1829 return i40e_ptp_get_ts_config(pf, ifr);
1830 case SIOCSHWTSTAMP:
1831 return i40e_ptp_set_ts_config(pf, ifr);
1832 default:
1833 return -EOPNOTSUPP;
1834 }
1835}
1836
41c445ff
JB		 1837/**
1838 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1839 * @vsi: the vsi being adjusted
1840 **/
1841void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1842{
1843 struct i40e_vsi_context ctxt;
1844 i40e_status ret;
1845
1846 if ((vsi->info.valid_sections &
1847 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1848 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1849 return; /* already enabled */
1850
1851 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1852 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1853 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1854
1855 ctxt.seid = vsi->seid;
1856 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1857 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1858 if (ret) {
1859 dev_info(&vsi->back->pdev->dev,
1860 "%s: update vsi failed, aq_err=%d\n",
1861 __func__, vsi->back->hw.aq.asq_last_status);
1862 }
1863}
1864
1865/**
1866 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1867 * @vsi: the vsi being adjusted
1868 **/
1869void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1870{
1871 struct i40e_vsi_context ctxt;
1872 i40e_status ret;
1873
1874 if ((vsi->info.valid_sections &
1875 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1876 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1877 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1878 return; /* already disabled */
1879
1880 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1881 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1882 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1883
1884 ctxt.seid = vsi->seid;
1885 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1886 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1887 if (ret) {
1888 dev_info(&vsi->back->pdev->dev,
1889 "%s: update vsi failed, aq_err=%d\n",
1890 __func__, vsi->back->hw.aq.asq_last_status);
1891 }
1892}
1893
1894/**
1895 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1896 * @netdev: network interface to be adjusted
1897 * @features: netdev features to test if VLAN offload is enabled or not
1898 **/
1899static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1900{
1901 struct i40e_netdev_priv *np = netdev_priv(netdev);
1902 struct i40e_vsi *vsi = np->vsi;
1903
1904 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1905 i40e_vlan_stripping_enable(vsi);
1906 else
1907 i40e_vlan_stripping_disable(vsi);
1908}
1909
1910/**
1911 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1912 * @vsi: the vsi being configured
1913 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1914 **/
1915int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1916{
1917 struct i40e_mac_filter *f, *add_f;
1918 bool is_netdev, is_vf;
41c445ff
JB		 1919
1920 is_vf = (vsi->type == I40E_VSI_SRIOV);
1921 is_netdev = !!(vsi->netdev);
1922
1923 if (is_netdev) {
1924 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1925 is_vf, is_netdev);
1926 if (!add_f) {
1927 dev_info(&vsi->back->pdev->dev,
1928 "Could not add vlan filter %d for %pM\n",
1929 vid, vsi->netdev->dev_addr);
1930 return -ENOMEM;
1931 }
1932 }
1933
1934 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1935 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1936 if (!add_f) {
1937 dev_info(&vsi->back->pdev->dev,
1938 "Could not add vlan filter %d for %pM\n",
1939 vid, f->macaddr);
1940 return -ENOMEM;
1941 }
1942 }
1943
41c445ff
JB		 1944 /* Now if we add a vlan tag, make sure to check if it is the first
1945 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1946 * with 0, so we now accept untagged and specified tagged traffic
1947 * (and not any taged and untagged)
1948 */
1949 if (vid > 0) {
1950 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1951 I40E_VLAN_ANY,
1952 is_vf, is_netdev)) {
1953 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1954 I40E_VLAN_ANY, is_vf, is_netdev);
1955 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1956 is_vf, is_netdev);
1957 if (!add_f) {
1958 dev_info(&vsi->back->pdev->dev,
1959 "Could not add filter 0 for %pM\n",
1960 vsi->netdev->dev_addr);
1961 return -ENOMEM;
1962 }
1963 }
8d82a7c5 1964 }
41c445ff 1965
8d82a7c5
GR		 1966 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1967 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1968 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1969 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1970 is_vf, is_netdev)) {
1971 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1972 is_vf, is_netdev);
1973 add_f = i40e_add_filter(vsi, f->macaddr,
1974 0, is_vf, is_netdev);
1975 if (!add_f) {
1976 dev_info(&vsi->back->pdev->dev,
1977 "Could not add filter 0 for %pM\n",
1978 f->macaddr);
1979 return -ENOMEM;
1980 }
1981 }
1982 }
41c445ff
JB		 1983 }
1984
80f6428f
ASJ		 1985 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1986 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1987 return 0;
1988
1989 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1990}
1991
1992/**
1993 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1994 * @vsi: the vsi being configured
1995 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1996 *
1997 * Return: 0 on success or negative otherwise
41c445ff
JB		 1998 **/
1999int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2000{
2001 struct net_device *netdev = vsi->netdev;
2002 struct i40e_mac_filter *f, *add_f;
2003 bool is_vf, is_netdev;
2004 int filter_count = 0;
41c445ff
JB		 2005
2006 is_vf = (vsi->type == I40E_VSI_SRIOV);
2007 is_netdev = !!(netdev);
2008
2009 if (is_netdev)
2010 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2011
2012 list_for_each_entry(f, &vsi->mac_filter_list, list)
2013 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2014
41c445ff
JB		 2015 /* go through all the filters for this VSI and if there is only
2016 * vid == 0 it means there are no other filters, so vid 0 must
2017 * be replaced with -1. This signifies that we should from now
2018 * on accept any traffic (with any tag present, or untagged)
2019 */
2020 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2021 if (is_netdev) {
2022 if (f->vlan &&
2023 ether_addr_equal(netdev->dev_addr, f->macaddr))
2024 filter_count++;
2025 }
2026
2027 if (f->vlan)
2028 filter_count++;
2029 }
2030
2031 if (!filter_count && is_netdev) {
2032 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2033 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2034 is_vf, is_netdev);
2035 if (!f) {
2036 dev_info(&vsi->back->pdev->dev,
2037 "Could not add filter %d for %pM\n",
2038 I40E_VLAN_ANY, netdev->dev_addr);
2039 return -ENOMEM;
2040 }
2041 }
2042
2043 if (!filter_count) {
2044 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2045 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2046 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2047 is_vf, is_netdev);
2048 if (!add_f) {
2049 dev_info(&vsi->back->pdev->dev,
2050 "Could not add filter %d for %pM\n",
2051 I40E_VLAN_ANY, f->macaddr);
2052 return -ENOMEM;
2053 }
2054 }
2055 }
2056
80f6428f
ASJ		 2057 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2058 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2059 return 0;
2060
41c445ff
JB		 2061 return i40e_sync_vsi_filters(vsi);
2062}
2063
2064/**
2065 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2066 * @netdev: network interface to be adjusted
2067 * @vid: vlan id to be added
078b5876
JB		 2068 *
2069 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 2070 **/
2071static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2072 __always_unused __be16 proto, u16 vid)
2073{
2074 struct i40e_netdev_priv *np = netdev_priv(netdev);
2075 struct i40e_vsi *vsi = np->vsi;
078b5876 2076 int ret = 0;
41c445ff
JB		 2077
2078 if (vid > 4095)
078b5876
JB		 2079 return -EINVAL;
2080
2081 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2082
6982d429
ASJ		 2083 /* If the network stack called us with vid = 0 then
2084 * it is asking to receive priority tagged packets with
2085 * vlan id 0. Our HW receives them by default when configured
2086 * to receive untagged packets so there is no need to add an
2087 * extra filter for vlan 0 tagged packets.
41c445ff 2088 */
6982d429
ASJ		 2089 if (vid)
2090 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2091
078b5876
JB		 2092 if (!ret && (vid < VLAN_N_VID))
2093 set_bit(vid, vsi->active_vlans);
41c445ff 2094
078b5876 2095 return ret;
41c445ff
JB		 2096}
2097
2098/**
2099 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2100 * @netdev: network interface to be adjusted
2101 * @vid: vlan id to be removed
078b5876 2102 *
fdfd943e 2103 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2104 **/
2105static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2106 __always_unused __be16 proto, u16 vid)
2107{
2108 struct i40e_netdev_priv *np = netdev_priv(netdev);
2109 struct i40e_vsi *vsi = np->vsi;
2110
078b5876
JB		 2111 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2112
41c445ff
JB		 2113 /* return code is ignored as there is nothing a user
2114 * can do about failure to remove and a log message was
078b5876 2115 * already printed from the other function
41c445ff
JB		 2116 */
2117 i40e_vsi_kill_vlan(vsi, vid);
2118
2119 clear_bit(vid, vsi->active_vlans);
078b5876 2120
41c445ff
JB		 2121 return 0;
2122}
2123
2124/**
2125 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2126 * @vsi: the vsi being brought back up
2127 **/
2128static void i40e_restore_vlan(struct i40e_vsi *vsi)
2129{
2130 u16 vid;
2131
2132 if (!vsi->netdev)
2133 return;
2134
2135 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2136
2137 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2138 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2139 vid);
2140}
2141
2142/**
2143 * i40e_vsi_add_pvid - Add pvid for the VSI
2144 * @vsi: the vsi being adjusted
2145 * @vid: the vlan id to set as a PVID
2146 **/
dcae29be 2147int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2148{
2149 struct i40e_vsi_context ctxt;
dcae29be 2150 i40e_status aq_ret;
41c445ff
JB		 2151
2152 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2153 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2154 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2155 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2156 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2157
2158 ctxt.seid = vsi->seid;
2159 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2160 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2161 if (aq_ret) {
41c445ff
JB		 2162 dev_info(&vsi->back->pdev->dev,
2163 "%s: update vsi failed, aq_err=%d\n",
2164 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2165 return -ENOENT;
41c445ff
JB		 2166 }
2167
dcae29be 2168 return 0;
41c445ff
JB		 2169}
2170
2171/**
2172 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2173 * @vsi: the vsi being adjusted
2174 *
2175 * Just use the vlan_rx_register() service to put it back to normal
2176 **/
2177void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2178{
6c12fcbf
GR		 2179 i40e_vlan_stripping_disable(vsi);
2180
41c445ff 2181 vsi->info.pvid = 0;
41c445ff
JB		 2182}
2183
2184/**
2185 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2186 * @vsi: ptr to the VSI
2187 *
2188 * If this function returns with an error, then it's possible one or
2189 * more of the rings is populated (while the rest are not). It is the
2190 * callers duty to clean those orphaned rings.
2191 *
2192 * Return 0 on success, negative on failure
2193 **/
2194static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2195{
2196 int i, err = 0;
2197
2198 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2199 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2200
2201 return err;
2202}
2203
2204/**
2205 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2206 * @vsi: ptr to the VSI
2207 *
2208 * Free VSI's transmit software resources
2209 **/
2210static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2211{
2212 int i;
2213
8e9dca53
GR		 2214 if (!vsi->tx_rings)
2215 return;
2216
41c445ff 2217 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2218 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2219 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2220}
2221
2222/**
2223 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2224 * @vsi: ptr to the VSI
2225 *
2226 * If this function returns with an error, then it's possible one or
2227 * more of the rings is populated (while the rest are not). It is the
2228 * callers duty to clean those orphaned rings.
2229 *
2230 * Return 0 on success, negative on failure
2231 **/
2232static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2233{
2234 int i, err = 0;
2235
2236 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2237 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2238 return err;
2239}
2240
2241/**
2242 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2243 * @vsi: ptr to the VSI
2244 *
2245 * Free all receive software resources
2246 **/
2247static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2248{
2249 int i;
2250
8e9dca53
GR		 2251 if (!vsi->rx_rings)
2252 return;
2253
41c445ff 2254 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2255 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2256 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2257}
2258
2259/**
2260 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2261 * @ring: The Tx ring to configure
2262 *
2263 * Configure the Tx descriptor ring in the HMC context.
2264 **/
2265static int i40e_configure_tx_ring(struct i40e_ring *ring)
2266{
2267 struct i40e_vsi *vsi = ring->vsi;
2268 u16 pf_q = vsi->base_queue + ring->queue_index;
2269 struct i40e_hw *hw = &vsi->back->hw;
2270 struct i40e_hmc_obj_txq tx_ctx;
2271 i40e_status err = 0;
2272 u32 qtx_ctl = 0;
2273
2274 /* some ATR related tx ring init */
60ea5f83 2275 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2276 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2277 ring->atr_count = 0;
2278 } else {
2279 ring->atr_sample_rate = 0;
2280 }
2281
2282 /* initialize XPS */
2283 if (ring->q_vector && ring->netdev &&
4e3b35b0 2284 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2285 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2286 netif_set_xps_queue(ring->netdev,
2287 &ring->q_vector->affinity_mask,
2288 ring->queue_index);
2289
2290 /* clear the context structure first */
2291 memset(&tx_ctx, 0, sizeof(tx_ctx));
2292
2293 tx_ctx.new_context = 1;
2294 tx_ctx.base = (ring->dma / 128);
2295 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2296 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2297 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2298 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2299 /* FDIR VSI tx ring can still use RS bit and writebacks */
2300 if (vsi->type != I40E_VSI_FDIR)
2301 tx_ctx.head_wb_ena = 1;
2302 tx_ctx.head_wb_addr = ring->dma +
2303 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2304
2305 /* As part of VSI creation/update, FW allocates certain
2306 * Tx arbitration queue sets for each TC enabled for
2307 * the VSI. The FW returns the handles to these queue
2308 * sets as part of the response buffer to Add VSI,
2309 * Update VSI, etc. AQ commands. It is expected that
2310 * these queue set handles be associated with the Tx
2311 * queues by the driver as part of the TX queue context
2312 * initialization. This has to be done regardless of
2313 * DCB as by default everything is mapped to TC0.
2314 */
2315 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2316 tx_ctx.rdylist_act = 0;
2317
2318 /* clear the context in the HMC */
2319 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2320 if (err) {
2321 dev_info(&vsi->back->pdev->dev,
2322 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2323 ring->queue_index, pf_q, err);
2324 return -ENOMEM;
2325 }
2326
2327 /* set the context in the HMC */
2328 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2329 if (err) {
2330 dev_info(&vsi->back->pdev->dev,
2331 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2332 ring->queue_index, pf_q, err);
2333 return -ENOMEM;
2334 }
2335
2336 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2337 if (vsi->type == I40E_VSI_VMDQ2)
2338 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2339 else
2340 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2341 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2342 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2343 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2344 i40e_flush(hw);
2345
2346 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2347
2348 /* cache tail off for easier writes later */
2349 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2350
2351 return 0;
2352}
2353
2354/**
2355 * i40e_configure_rx_ring - Configure a receive ring context
2356 * @ring: The Rx ring to configure
2357 *
2358 * Configure the Rx descriptor ring in the HMC context.
2359 **/
2360static int i40e_configure_rx_ring(struct i40e_ring *ring)
2361{
2362 struct i40e_vsi *vsi = ring->vsi;
2363 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2364 u16 pf_q = vsi->base_queue + ring->queue_index;
2365 struct i40e_hw *hw = &vsi->back->hw;
2366 struct i40e_hmc_obj_rxq rx_ctx;
2367 i40e_status err = 0;
2368
2369 ring->state = 0;
2370
2371 /* clear the context structure first */
2372 memset(&rx_ctx, 0, sizeof(rx_ctx));
2373
2374 ring->rx_buf_len = vsi->rx_buf_len;
2375 ring->rx_hdr_len = vsi->rx_hdr_len;
2376
2377 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2378 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2379
2380 rx_ctx.base = (ring->dma / 128);
2381 rx_ctx.qlen = ring->count;
2382
2383 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2384 set_ring_16byte_desc_enabled(ring);
2385 rx_ctx.dsize = 0;
2386 } else {
2387 rx_ctx.dsize = 1;
2388 }
2389
2390 rx_ctx.dtype = vsi->dtype;
2391 if (vsi->dtype) {
2392 set_ring_ps_enabled(ring);
2393 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2394 I40E_RX_SPLIT_IP |
2395 I40E_RX_SPLIT_TCP_UDP |
2396 I40E_RX_SPLIT_SCTP;
2397 } else {
2398 rx_ctx.hsplit_0 = 0;
2399 }
2400
2401 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2402 (chain_len * ring->rx_buf_len));
2403 rx_ctx.tphrdesc_ena = 1;
2404 rx_ctx.tphwdesc_ena = 1;
2405 rx_ctx.tphdata_ena = 1;
2406 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2407 if (hw->revision_id == 0)
2408 rx_ctx.lrxqthresh = 0;
2409 else
2410 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2411 rx_ctx.crcstrip = 1;
2412 rx_ctx.l2tsel = 1;
2413 rx_ctx.showiv = 1;
acb3676b
CS		 2414 /* set the prefena field to 1 because the manual says to */
2415 rx_ctx.prefena = 1;
41c445ff
JB		 2416
2417 /* clear the context in the HMC */
2418 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2419 if (err) {
2420 dev_info(&vsi->back->pdev->dev,
2421 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2422 ring->queue_index, pf_q, err);
2423 return -ENOMEM;
2424 }
2425
2426 /* set the context in the HMC */
2427 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2428 if (err) {
2429 dev_info(&vsi->back->pdev->dev,
2430 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2431 ring->queue_index, pf_q, err);
2432 return -ENOMEM;
2433 }
2434
2435 /* cache tail for quicker writes, and clear the reg before use */
2436 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2437 writel(0, ring->tail);
2438
2439 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2440
2441 return 0;
2442}
2443
2444/**
2445 * i40e_vsi_configure_tx - Configure the VSI for Tx
2446 * @vsi: VSI structure describing this set of rings and resources
2447 *
2448 * Configure the Tx VSI for operation.
2449 **/
2450static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2451{
2452 int err = 0;
2453 u16 i;
2454
9f65e15b
AD		 2455 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2456 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2457
2458 return err;
2459}
2460
2461/**
2462 * i40e_vsi_configure_rx - Configure the VSI for Rx
2463 * @vsi: the VSI being configured
2464 *
2465 * Configure the Rx VSI for operation.
2466 **/
2467static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2468{
2469 int err = 0;
2470 u16 i;
2471
2472 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2473 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2474 + ETH_FCS_LEN + VLAN_HLEN;
2475 else
2476 vsi->max_frame = I40E_RXBUFFER_2048;
2477
2478 /* figure out correct receive buffer length */
2479 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2480 I40E_FLAG_RX_PS_ENABLED)) {
2481 case I40E_FLAG_RX_1BUF_ENABLED:
2482 vsi->rx_hdr_len = 0;
2483 vsi->rx_buf_len = vsi->max_frame;
2484 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2485 break;
2486 case I40E_FLAG_RX_PS_ENABLED:
2487 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2488 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2489 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2490 break;
2491 default:
2492 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2493 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2494 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2495 break;
2496 }
2497
2498 /* round up for the chip's needs */
2499 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2500 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2501 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2502 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2503
2504 /* set up individual rings */
2505 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2506 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2507
2508 return err;
2509}
2510
2511/**
2512 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2513 * @vsi: ptr to the VSI
2514 **/
2515static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2516{
e7046ee1 2517 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2518 u16 qoffset, qcount;
2519 int i, n;
2520
2521 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2522 return;
2523
2524 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2525 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2526 continue;
2527
2528 qoffset = vsi->tc_config.tc_info[n].qoffset;
2529 qcount = vsi->tc_config.tc_info[n].qcount;
2530 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2531 rx_ring = vsi->rx_rings[i];
2532 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2533 rx_ring->dcb_tc = n;
2534 tx_ring->dcb_tc = n;
2535 }
2536 }
2537}
2538
2539/**
2540 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2541 * @vsi: ptr to the VSI
2542 **/
2543static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2544{
2545 if (vsi->netdev)
2546 i40e_set_rx_mode(vsi->netdev);
2547}
2548
17a73f6b
JG		 2549/**
2550 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2551 * @vsi: Pointer to the targeted VSI
2552 *
2553 * This function replays the hlist on the hw where all the SB Flow Director
2554 * filters were saved.
2555 **/
2556static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2557{
2558 struct i40e_fdir_filter *filter;
2559 struct i40e_pf *pf = vsi->back;
2560 struct hlist_node *node;
2561
55a5e60b
ASJ		 2562 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2563 return;
2564
17a73f6b
JG		 2565 hlist_for_each_entry_safe(filter, node,
2566 &pf->fdir_filter_list, fdir_node) {
2567 i40e_add_del_fdir(vsi, filter, true);
2568 }
2569}
2570
41c445ff
JB		 2571/**
2572 * i40e_vsi_configure - Set up the VSI for action
2573 * @vsi: the VSI being configured
2574 **/
2575static int i40e_vsi_configure(struct i40e_vsi *vsi)
2576{
2577 int err;
2578
2579 i40e_set_vsi_rx_mode(vsi);
2580 i40e_restore_vlan(vsi);
2581 i40e_vsi_config_dcb_rings(vsi);
2582 err = i40e_vsi_configure_tx(vsi);
2583 if (!err)
2584 err = i40e_vsi_configure_rx(vsi);
2585
2586 return err;
2587}
2588
2589/**
2590 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2591 * @vsi: the VSI being configured
2592 **/
2593static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2594{
2595 struct i40e_pf *pf = vsi->back;
2596 struct i40e_q_vector *q_vector;
2597 struct i40e_hw *hw = &pf->hw;
2598 u16 vector;
2599 int i, q;
2600 u32 val;
2601 u32 qp;
2602
2603 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2604 * and PFINT_LNKLSTn registers, e.g.:
2605 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2606 */
2607 qp = vsi->base_queue;
2608 vector = vsi->base_vector;
493fb300
AD		 2609 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2610 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2611 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2612 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2613 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2614 q_vector->rx.itr);
2615 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2616 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2617 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2618 q_vector->tx.itr);
2619
2620 /* Linked list for the queuepairs assigned to this vector */
2621 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2622 for (q = 0; q < q_vector->num_ringpairs; q++) {
2623 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2624 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2625 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2626 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2627 (I40E_QUEUE_TYPE_TX
2628 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2629
2630 wr32(hw, I40E_QINT_RQCTL(qp), val);
2631
2632 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2633 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2634 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2635 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2636 (I40E_QUEUE_TYPE_RX
2637 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2638
2639 /* Terminate the linked list */
2640 if (q == (q_vector->num_ringpairs - 1))
2641 val |= (I40E_QUEUE_END_OF_LIST
2642 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2643
2644 wr32(hw, I40E_QINT_TQCTL(qp), val);
2645 qp++;
2646 }
2647 }
2648
2649 i40e_flush(hw);
2650}
2651
2652/**
2653 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2654 * @hw: ptr to the hardware info
2655 **/
2656static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2657{
2658 u32 val;
2659
2660 /* clear things first */
2661 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2662 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2663
2664 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2665 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2666 I40E_PFINT_ICR0_ENA_GRST_MASK |
2667 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2668 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2669 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2670 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2671 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2672 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2673
2674 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2675
2676 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2677 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2678 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2679
2680 /* OTHER_ITR_IDX = 0 */
2681 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2682}
2683
2684/**
2685 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2686 * @vsi: the VSI being configured
2687 **/
2688static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2689{
493fb300 2690 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2691 struct i40e_pf *pf = vsi->back;
2692 struct i40e_hw *hw = &pf->hw;
2693 u32 val;
2694
2695 /* set the ITR configuration */
2696 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2697 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2698 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2699 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2700 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2701 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2702
2703 i40e_enable_misc_int_causes(hw);
2704
2705 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2706 wr32(hw, I40E_PFINT_LNKLST0, 0);
2707
f29eaa3d 2708 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2709 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2710 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2711 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2712
2713 wr32(hw, I40E_QINT_RQCTL(0), val);
2714
2715 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2716 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2717 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2718
2719 wr32(hw, I40E_QINT_TQCTL(0), val);
2720 i40e_flush(hw);
2721}
2722
2ef28cfb
MW		 2723/**
2724 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2725 * @pf: board private structure
2726 **/
2727void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2728{
2729 struct i40e_hw *hw = &pf->hw;
2730
2731 wr32(hw, I40E_PFINT_DYN_CTL0,
2732 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2733 i40e_flush(hw);
2734}
2735
41c445ff
JB		 2736/**
2737 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2738 * @pf: board private structure
2739 **/
116a57d4 2740void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2741{
2742 struct i40e_hw *hw = &pf->hw;
2743 u32 val;
2744
2745 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2746 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2747 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2748
2749 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2750 i40e_flush(hw);
2751}
2752
2753/**
2754 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2755 * @vsi: pointer to a vsi
2756 * @vector: enable a particular Hw Interrupt vector
2757 **/
2758void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2759{
2760 struct i40e_pf *pf = vsi->back;
2761 struct i40e_hw *hw = &pf->hw;
2762 u32 val;
2763
2764 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2765 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2766 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2767 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2768 /* skip the flush */
41c445ff
JB		 2769}
2770
5c2cebda
CW		 2771/**
2772 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2773 * @vsi: pointer to a vsi
2774 * @vector: enable a particular Hw Interrupt vector
2775 **/
2776void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2777{
2778 struct i40e_pf *pf = vsi->back;
2779 struct i40e_hw *hw = &pf->hw;
2780 u32 val;
2781
2782 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2783 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2784 i40e_flush(hw);
2785}
2786
41c445ff
JB		 2787/**
2788 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2789 * @irq: interrupt number
2790 * @data: pointer to a q_vector
2791 **/
2792static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2793{
2794 struct i40e_q_vector *q_vector = data;
2795
cd0b6fa6 2796 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2797 return IRQ_HANDLED;
2798
2799 napi_schedule(&q_vector->napi);
2800
2801 return IRQ_HANDLED;
2802}
2803
41c445ff
JB		 2804/**
2805 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2806 * @vsi: the VSI being configured
2807 * @basename: name for the vector
2808 *
2809 * Allocates MSI-X vectors and requests interrupts from the kernel.
2810 **/
2811static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2812{
2813 int q_vectors = vsi->num_q_vectors;
2814 struct i40e_pf *pf = vsi->back;
2815 int base = vsi->base_vector;
2816 int rx_int_idx = 0;
2817 int tx_int_idx = 0;
2818 int vector, err;
2819
2820 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2821 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2822
cd0b6fa6 2823 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2824 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2825 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2826 tx_int_idx++;
cd0b6fa6 2827 } else if (q_vector->rx.ring) {
41c445ff
JB		 2828 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2829 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2830 } else if (q_vector->tx.ring) {
41c445ff
JB		 2831 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2832 "%s-%s-%d", basename, "tx", tx_int_idx++);
2833 } else {
2834 /* skip this unused q_vector */
2835 continue;
2836 }
2837 err = request_irq(pf->msix_entries[base + vector].vector,
2838 vsi->irq_handler,
2839 0,
2840 q_vector->name,
2841 q_vector);
2842 if (err) {
2843 dev_info(&pf->pdev->dev,
2844 "%s: request_irq failed, error: %d\n",
2845 __func__, err);
2846 goto free_queue_irqs;
2847 }
2848 /* assign the mask for this irq */
2849 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2850 &q_vector->affinity_mask);
2851 }
2852
63741846 2853 vsi->irqs_ready = true;
41c445ff
JB		 2854 return 0;
2855
2856free_queue_irqs:
2857 while (vector) {
2858 vector--;
2859 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2860 NULL);
2861 free_irq(pf->msix_entries[base + vector].vector,
2862 &(vsi->q_vectors[vector]));
2863 }
2864 return err;
2865}
2866
2867/**
2868 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2869 * @vsi: the VSI being un-configured
2870 **/
2871static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2872{
2873 struct i40e_pf *pf = vsi->back;
2874 struct i40e_hw *hw = &pf->hw;
2875 int base = vsi->base_vector;
2876 int i;
2877
2878 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2879 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2880 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2881 }
2882
2883 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2884 for (i = vsi->base_vector;
2885 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2886 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2887
2888 i40e_flush(hw);
2889 for (i = 0; i < vsi->num_q_vectors; i++)
2890 synchronize_irq(pf->msix_entries[i + base].vector);
2891 } else {
2892 /* Legacy and MSI mode - this stops all interrupt handling */
2893 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2894 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2895 i40e_flush(hw);
2896 synchronize_irq(pf->pdev->irq);
2897 }
2898}
2899
2900/**
2901 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2902 * @vsi: the VSI being configured
2903 **/
2904static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2905{
2906 struct i40e_pf *pf = vsi->back;
2907 int i;
2908
2909 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2910 for (i = vsi->base_vector;
2911 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2912 i40e_irq_dynamic_enable(vsi, i);
2913 } else {
2914 i40e_irq_dynamic_enable_icr0(pf);
2915 }
2916
1022cb6c 2917 i40e_flush(&pf->hw);
41c445ff
JB		 2918 return 0;
2919}
2920
2921/**
2922 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2923 * @pf: board private structure
2924 **/
2925static void i40e_stop_misc_vector(struct i40e_pf *pf)
2926{
2927 /* Disable ICR 0 */
2928 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2929 i40e_flush(&pf->hw);
2930}
2931
2932/**
2933 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2934 * @irq: interrupt number
2935 * @data: pointer to a q_vector
2936 *
2937 * This is the handler used for all MSI/Legacy interrupts, and deals
2938 * with both queue and non-queue interrupts. This is also used in
2939 * MSIX mode to handle the non-queue interrupts.
2940 **/
2941static irqreturn_t i40e_intr(int irq, void *data)
2942{
2943 struct i40e_pf *pf = (struct i40e_pf *)data;
2944 struct i40e_hw *hw = &pf->hw;
5e823066 2945 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2946 u32 icr0, icr0_remaining;
2947 u32 val, ena_mask;
2948
2949 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2950 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2951
116a57d4
SN		 2952 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2953 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2954 goto enable_intr;
41c445ff 2955
cd92e72f
SN		 2956 /* if interrupt but no bits showing, must be SWINT */
2957 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2958 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2959 pf->sw_int_count++;
2960
41c445ff
JB		 2961 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2962 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2963
2964 /* temporarily disable queue cause for NAPI processing */
2965 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2966 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2967 wr32(hw, I40E_QINT_RQCTL(0), qval);
2968
2969 qval = rd32(hw, I40E_QINT_TQCTL(0));
2970 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2971 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2972
2973 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2974 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2975 }
2976
2977 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2978 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2979 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2980 }
2981
2982 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2983 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2984 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2985 }
2986
2987 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2988 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2989 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2990 }
2991
2992 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2993 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2994 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2995 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2996 val = rd32(hw, I40E_GLGEN_RSTAT);
2997 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2998 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2999 if (val == I40E_RESET_CORER) {
41c445ff 3000 pf->corer_count++;
4eb3f768 3001 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3002 pf->globr_count++;
4eb3f768 3003 } else if (val == I40E_RESET_EMPR) {
41c445ff 3004 pf->empr_count++;
4eb3f768
SN		 3005 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3006 }
41c445ff
JB		 3007 }
3008
9c010ee0
ASJ		 3009 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3010 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3011 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3012 }
3013
beb0dff1
JK		 3014 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3015 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3016
3017 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3018 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3019 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3020 }
beb0dff1
JK		 3021 }
3022
41c445ff
JB		 3023 /* If a critical error is pending we have no choice but to reset the
3024 * device.
3025 * Report and mask out any remaining unexpected interrupts.
3026 */
3027 icr0_remaining = icr0 & ena_mask;
3028 if (icr0_remaining) {
3029 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3030 icr0_remaining);
9c010ee0 3031 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3032 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3033 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3034 dev_info(&pf->pdev->dev, "device will be reset\n");
3035 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3036 i40e_service_event_schedule(pf);
41c445ff
JB		 3037 }
3038 ena_mask &= ~icr0_remaining;
3039 }
5e823066 3040 ret = IRQ_HANDLED;
41c445ff 3041
5e823066 3042enable_intr:
41c445ff
JB		 3043 /* re-enable interrupt causes */
3044 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3045 if (!test_bit(__I40E_DOWN, &pf->state)) {
3046 i40e_service_event_schedule(pf);
3047 i40e_irq_dynamic_enable_icr0(pf);
3048 }
3049
5e823066 3050 return ret;
41c445ff
JB		 3051}
3052
cbf61325
ASJ		 3053/**
3054 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3055 * @tx_ring: tx ring to clean
3056 * @budget: how many cleans we're allowed
3057 *
3058 * Returns true if there's any budget left (e.g. the clean is finished)
3059 **/
3060static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3061{
3062 struct i40e_vsi *vsi = tx_ring->vsi;
3063 u16 i = tx_ring->next_to_clean;
3064 struct i40e_tx_buffer *tx_buf;
3065 struct i40e_tx_desc *tx_desc;
3066
3067 tx_buf = &tx_ring->tx_bi[i];
3068 tx_desc = I40E_TX_DESC(tx_ring, i);
3069 i -= tx_ring->count;
3070
3071 do {
3072 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3073
3074 /* if next_to_watch is not set then there is no work pending */
3075 if (!eop_desc)
3076 break;
3077
3078 /* prevent any other reads prior to eop_desc */
3079 read_barrier_depends();
3080
3081 /* if the descriptor isn't done, no work yet to do */
3082 if (!(eop_desc->cmd_type_offset_bsz &
3083 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3084 break;
3085
3086 /* clear next_to_watch to prevent false hangs */
3087 tx_buf->next_to_watch = NULL;
3088
3089 /* unmap skb header data */
3090 dma_unmap_single(tx_ring->dev,
3091 dma_unmap_addr(tx_buf, dma),
3092 dma_unmap_len(tx_buf, len),
3093 DMA_TO_DEVICE);
3094
3095 dma_unmap_len_set(tx_buf, len, 0);
3096
3097
3098 /* move to the next desc and buffer to clean */
3099 tx_buf++;
3100 tx_desc++;
3101 i++;
3102 if (unlikely(!i)) {
3103 i -= tx_ring->count;
3104 tx_buf = tx_ring->tx_bi;
3105 tx_desc = I40E_TX_DESC(tx_ring, 0);
3106 }
3107
3108 /* update budget accounting */
3109 budget--;
3110 } while (likely(budget));
3111
3112 i += tx_ring->count;
3113 tx_ring->next_to_clean = i;
3114
3115 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3116 i40e_irq_dynamic_enable(vsi,
3117 tx_ring->q_vector->v_idx + vsi->base_vector);
3118 }
3119 return budget > 0;
3120}
3121
3122/**
3123 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3124 * @irq: interrupt number
3125 * @data: pointer to a q_vector
3126 **/
3127static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3128{
3129 struct i40e_q_vector *q_vector = data;
3130 struct i40e_vsi *vsi;
3131
3132 if (!q_vector->tx.ring)
3133 return IRQ_HANDLED;
3134
3135 vsi = q_vector->tx.ring->vsi;
3136 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3137
3138 return IRQ_HANDLED;
3139}
3140
41c445ff 3141/**
cd0b6fa6 3142 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3143 * @vsi: the VSI being configured
3144 * @v_idx: vector index
cd0b6fa6 3145 * @qp_idx: queue pair index
41c445ff 3146 **/
cd0b6fa6 3147static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3148{
493fb300 3149 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3150 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3151 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3152
3153 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3154 tx_ring->next = q_vector->tx.ring;
3155 q_vector->tx.ring = tx_ring;
41c445ff 3156 q_vector->tx.count++;
cd0b6fa6
AD		 3157
3158 rx_ring->q_vector = q_vector;
3159 rx_ring->next = q_vector->rx.ring;
3160 q_vector->rx.ring = rx_ring;
3161 q_vector->rx.count++;
41c445ff
JB		 3162}
3163
3164/**
3165 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3166 * @vsi: the VSI being configured
3167 *
3168 * This function maps descriptor rings to the queue-specific vectors
3169 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3170 * one vector per queue pair, but on a constrained vector budget, we
3171 * group the queue pairs as "efficiently" as possible.
3172 **/
3173static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3174{
3175 int qp_remaining = vsi->num_queue_pairs;
3176 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3177 int num_ringpairs;
41c445ff
JB		 3178 int v_start = 0;
3179 int qp_idx = 0;
3180
3181 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3182 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3183 * It is also important to go through all the vectors available to be
3184 * sure that if we don't use all the vectors, that the remaining vectors
3185 * are cleared. This is especially important when decreasing the
3186 * number of queues in use.
41c445ff 3187 */
70114ec4 3188 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3189 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3190
3191 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3192
3193 q_vector->num_ringpairs = num_ringpairs;
3194
3195 q_vector->rx.count = 0;
3196 q_vector->tx.count = 0;
3197 q_vector->rx.ring = NULL;
3198 q_vector->tx.ring = NULL;
3199
3200 while (num_ringpairs--) {
3201 map_vector_to_qp(vsi, v_start, qp_idx);
3202 qp_idx++;
3203 qp_remaining--;
41c445ff
JB		 3204 }
3205 }
3206}
3207
3208/**
3209 * i40e_vsi_request_irq - Request IRQ from the OS
3210 * @vsi: the VSI being configured
3211 * @basename: name for the vector
3212 **/
3213static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3214{
3215 struct i40e_pf *pf = vsi->back;
3216 int err;
3217
3218 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3219 err = i40e_vsi_request_irq_msix(vsi, basename);
3220 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3221 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3222 pf->misc_int_name, pf);
3223 else
3224 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3225 pf->misc_int_name, pf);
3226
3227 if (err)
3228 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3229
3230 return err;
3231}
3232
3233#ifdef CONFIG_NET_POLL_CONTROLLER
3234/**
3235 * i40e_netpoll - A Polling 'interrupt'handler
3236 * @netdev: network interface device structure
3237 *
3238 * This is used by netconsole to send skbs without having to re-enable
3239 * interrupts. It's not called while the normal interrupt routine is executing.
3240 **/
3241static void i40e_netpoll(struct net_device *netdev)
3242{
3243 struct i40e_netdev_priv *np = netdev_priv(netdev);
3244 struct i40e_vsi *vsi = np->vsi;
3245 struct i40e_pf *pf = vsi->back;
3246 int i;
3247
3248 /* if interface is down do nothing */
3249 if (test_bit(__I40E_DOWN, &vsi->state))
3250 return;
3251
3252 pf->flags |= I40E_FLAG_IN_NETPOLL;
3253 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3254 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3255 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3256 } else {
3257 i40e_intr(pf->pdev->irq, netdev);
3258 }
3259 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3260}
3261#endif
3262
23527308
NP		 3263/**
3264 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3265 * @pf: the PF being configured
3266 * @pf_q: the PF queue
3267 * @enable: enable or disable state of the queue
3268 *
3269 * This routine will wait for the given Tx queue of the PF to reach the
3270 * enabled or disabled state.
3271 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3272 * multiple retries; else will return 0 in case of success.
3273 **/
3274static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3275{
3276 int i;
3277 u32 tx_reg;
3278
3279 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3280 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3281 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3282 break;
3283
3284 udelay(10);
3285 }
3286 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3287 return -ETIMEDOUT;
3288
3289 return 0;
3290}
3291
41c445ff
JB		 3292/**
3293 * i40e_vsi_control_tx - Start or stop a VSI's rings
3294 * @vsi: the VSI being configured
3295 * @enable: start or stop the rings
3296 **/
3297static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3298{
3299 struct i40e_pf *pf = vsi->back;
3300 struct i40e_hw *hw = &pf->hw;
23527308 3301 int i, j, pf_q, ret = 0;
41c445ff
JB		 3302 u32 tx_reg;
3303
3304 pf_q = vsi->base_queue;
3305 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3306
3307 /* warn the TX unit of coming changes */
3308 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3309 if (!enable)
3310 udelay(10);
3311
6c5ef620 3312 for (j = 0; j < 50; j++) {
41c445ff 3313 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3314 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3315 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3316 break;
3317 usleep_range(1000, 2000);
3318 }
fda972f6 3319 /* Skip if the queue is already in the requested state */
7c122007 3320 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3321 continue;
41c445ff
JB		 3322
3323 /* turn on/off the queue */
c5c9eb9e
SN		 3324 if (enable) {
3325 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3326 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3327 } else {
41c445ff 3328 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3329 }
41c445ff
JB		 3330
3331 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3332
3333 /* wait for the change to finish */
23527308
NP		 3334 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3335 if (ret) {
3336 dev_info(&pf->pdev->dev,
3337 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3338 __func__, vsi->seid, pf_q,
3339 (enable ? "en" : "dis"));
3340 break;
41c445ff
JB		 3341 }
3342 }
3343
7134f9ce
JB		 3344 if (hw->revision_id == 0)
3345 mdelay(50);
23527308
NP		 3346 return ret;
3347}
3348
3349/**
3350 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3351 * @pf: the PF being configured
3352 * @pf_q: the PF queue
3353 * @enable: enable or disable state of the queue
3354 *
3355 * This routine will wait for the given Rx queue of the PF to reach the
3356 * enabled or disabled state.
3357 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3358 * multiple retries; else will return 0 in case of success.
3359 **/
3360static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3361{
3362 int i;
3363 u32 rx_reg;
3364
3365 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3366 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3367 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3368 break;
3369
3370 udelay(10);
3371 }
3372 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3373 return -ETIMEDOUT;
7134f9ce 3374
41c445ff
JB		 3375 return 0;
3376}
3377
3378/**
3379 * i40e_vsi_control_rx - Start or stop a VSI's rings
3380 * @vsi: the VSI being configured
3381 * @enable: start or stop the rings
3382 **/
3383static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3384{
3385 struct i40e_pf *pf = vsi->back;
3386 struct i40e_hw *hw = &pf->hw;
23527308 3387 int i, j, pf_q, ret = 0;
41c445ff
JB		 3388 u32 rx_reg;
3389
3390 pf_q = vsi->base_queue;
3391 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3392 for (j = 0; j < 50; j++) {
41c445ff 3393 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3394 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3395 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3396 break;
3397 usleep_range(1000, 2000);
3398 }
41c445ff 3399
7c122007
CS		 3400 /* Skip if the queue is already in the requested state */
3401 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3402 continue;
41c445ff
JB		 3403
3404 /* turn on/off the queue */
3405 if (enable)
6c5ef620 3406 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3407 else
6c5ef620 3408 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3409 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3410
3411 /* wait for the change to finish */
23527308
NP		 3412 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3413 if (ret) {
3414 dev_info(&pf->pdev->dev,
3415 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3416 __func__, vsi->seid, pf_q,
3417 (enable ? "en" : "dis"));
3418 break;
41c445ff
JB		 3419 }
3420 }
3421
23527308 3422 return ret;
41c445ff
JB		 3423}
3424
3425/**
3426 * i40e_vsi_control_rings - Start or stop a VSI's rings
3427 * @vsi: the VSI being configured
3428 * @enable: start or stop the rings
3429 **/
fc18eaa0 3430int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3431{
3b867b28 3432 int ret = 0;
41c445ff
JB		 3433
3434 /* do rx first for enable and last for disable */
3435 if (request) {
3436 ret = i40e_vsi_control_rx(vsi, request);
3437 if (ret)
3438 return ret;
3439 ret = i40e_vsi_control_tx(vsi, request);
3440 } else {
3b867b28
ASJ		 3441 /* Ignore return value, we need to shutdown whatever we can */
3442 i40e_vsi_control_tx(vsi, request);
3443 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3444 }
3445
3446 return ret;
3447}
3448
3449/**
3450 * i40e_vsi_free_irq - Free the irq association with the OS
3451 * @vsi: the VSI being configured
3452 **/
3453static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3454{
3455 struct i40e_pf *pf = vsi->back;
3456 struct i40e_hw *hw = &pf->hw;
3457 int base = vsi->base_vector;
3458 u32 val, qp;
3459 int i;
3460
3461 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3462 if (!vsi->q_vectors)
3463 return;
3464
63741846
SN		 3465 if (!vsi->irqs_ready)
3466 return;
3467
3468 vsi->irqs_ready = false;
41c445ff
JB		 3469 for (i = 0; i < vsi->num_q_vectors; i++) {
3470 u16 vector = i + base;
3471
3472 /* free only the irqs that were actually requested */
78681b1f
SN		 3473 if (!vsi->q_vectors[i] ||
3474 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3475 continue;
3476
3477 /* clear the affinity_mask in the IRQ descriptor */
3478 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3479 NULL);
3480 free_irq(pf->msix_entries[vector].vector,
493fb300 3481 vsi->q_vectors[i]);
41c445ff
JB		 3482
3483 /* Tear down the interrupt queue link list
3484 *
3485 * We know that they come in pairs and always
3486 * the Rx first, then the Tx. To clear the
3487 * link list, stick the EOL value into the
3488 * next_q field of the registers.
3489 */
3490 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3491 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3492 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3493 val |= I40E_QUEUE_END_OF_LIST
3494 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3495 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3496
3497 while (qp != I40E_QUEUE_END_OF_LIST) {
3498 u32 next;
3499
3500 val = rd32(hw, I40E_QINT_RQCTL(qp));
3501
3502 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3503 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3504 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3505 I40E_QINT_RQCTL_INTEVENT_MASK);
3506
3507 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3508 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3509
3510 wr32(hw, I40E_QINT_RQCTL(qp), val);
3511
3512 val = rd32(hw, I40E_QINT_TQCTL(qp));
3513
3514 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3515 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3516
3517 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3518 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3519 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3520 I40E_QINT_TQCTL_INTEVENT_MASK);
3521
3522 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3523 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3524
3525 wr32(hw, I40E_QINT_TQCTL(qp), val);
3526 qp = next;
3527 }
3528 }
3529 } else {
3530 free_irq(pf->pdev->irq, pf);
3531
3532 val = rd32(hw, I40E_PFINT_LNKLST0);
3533 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3534 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3535 val |= I40E_QUEUE_END_OF_LIST
3536 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3537 wr32(hw, I40E_PFINT_LNKLST0, val);
3538
3539 val = rd32(hw, I40E_QINT_RQCTL(qp));
3540 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3541 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3542 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3543 I40E_QINT_RQCTL_INTEVENT_MASK);
3544
3545 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3546 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3547
3548 wr32(hw, I40E_QINT_RQCTL(qp), val);
3549
3550 val = rd32(hw, I40E_QINT_TQCTL(qp));
3551
3552 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3553 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3554 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3555 I40E_QINT_TQCTL_INTEVENT_MASK);
3556
3557 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3558 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3559
3560 wr32(hw, I40E_QINT_TQCTL(qp), val);
3561 }
3562}
3563
493fb300
AD		 3564/**
3565 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3566 * @vsi: the VSI being configured
3567 * @v_idx: Index of vector to be freed
3568 *
3569 * This function frees the memory allocated to the q_vector. In addition if
3570 * NAPI is enabled it will delete any references to the NAPI struct prior
3571 * to freeing the q_vector.
3572 **/
3573static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3574{
3575 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3576 struct i40e_ring *ring;
493fb300
AD		 3577
3578 if (!q_vector)
3579 return;
3580
3581 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3582 i40e_for_each_ring(ring, q_vector->tx)
3583 ring->q_vector = NULL;
3584
3585 i40e_for_each_ring(ring, q_vector->rx)
3586 ring->q_vector = NULL;
493fb300
AD		 3587
3588 /* only VSI w/ an associated netdev is set up w/ NAPI */
3589 if (vsi->netdev)
3590 netif_napi_del(&q_vector->napi);
3591
3592 vsi->q_vectors[v_idx] = NULL;
3593
3594 kfree_rcu(q_vector, rcu);
3595}
3596
41c445ff
JB		 3597/**
3598 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3599 * @vsi: the VSI being un-configured
3600 *
3601 * This frees the memory allocated to the q_vectors and
3602 * deletes references to the NAPI struct.
3603 **/
3604static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3605{
3606 int v_idx;
3607
493fb300
AD		 3608 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3609 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3610}
3611
3612/**
3613 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3614 * @pf: board private structure
3615 **/
3616static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3617{
3618 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3619 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3620 pci_disable_msix(pf->pdev);
3621 kfree(pf->msix_entries);
3622 pf->msix_entries = NULL;
3623 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3624 pci_disable_msi(pf->pdev);
3625 }
3626 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3627}
3628
3629/**
3630 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3631 * @pf: board private structure
3632 *
3633 * We go through and clear interrupt specific resources and reset the structure
3634 * to pre-load conditions
3635 **/
3636static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3637{
3638 int i;
3639
3640 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3641 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3642 if (pf->vsi[i])
3643 i40e_vsi_free_q_vectors(pf->vsi[i]);
3644 i40e_reset_interrupt_capability(pf);
3645}
3646
3647/**
3648 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3649 * @vsi: the VSI being configured
3650 **/
3651static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3652{
3653 int q_idx;
3654
3655 if (!vsi->netdev)
3656 return;
3657
3658 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3659 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3660}
3661
3662/**
3663 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3664 * @vsi: the VSI being configured
3665 **/
3666static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3667{
3668 int q_idx;
3669
3670 if (!vsi->netdev)
3671 return;
3672
3673 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3674 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3675}
3676
90ef8d47
SN		 3677/**
3678 * i40e_vsi_close - Shut down a VSI
3679 * @vsi: the vsi to be quelled
3680 **/
3681static void i40e_vsi_close(struct i40e_vsi *vsi)
3682{
3683 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3684 i40e_down(vsi);
3685 i40e_vsi_free_irq(vsi);
3686 i40e_vsi_free_tx_resources(vsi);
3687 i40e_vsi_free_rx_resources(vsi);
3688}
3689
41c445ff
JB		 3690/**
3691 * i40e_quiesce_vsi - Pause a given VSI
3692 * @vsi: the VSI being paused
3693 **/
3694static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3695{
3696 if (test_bit(__I40E_DOWN, &vsi->state))
3697 return;
3698
3699 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3700 if (vsi->netdev && netif_running(vsi->netdev)) {
3701 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3702 } else {
90ef8d47 3703 i40e_vsi_close(vsi);
41c445ff
JB		 3704 }
3705}
3706
3707/**
3708 * i40e_unquiesce_vsi - Resume a given VSI
3709 * @vsi: the VSI being resumed
3710 **/
3711static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3712{
3713 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3714 return;
3715
3716 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3717 if (vsi->netdev && netif_running(vsi->netdev))
3718 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3719 else
8276f757 3720 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3721}
3722
3723/**
3724 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3725 * @pf: the PF
3726 **/
3727static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3728{
3729 int v;
3730
505682cd 3731 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3732 if (pf->vsi[v])
3733 i40e_quiesce_vsi(pf->vsi[v]);
3734 }
3735}
3736
3737/**
3738 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3739 * @pf: the PF
3740 **/
3741static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3742{
3743 int v;
3744
505682cd 3745 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3746 if (pf->vsi[v])
3747 i40e_unquiesce_vsi(pf->vsi[v]);
3748 }
3749}
3750
3751/**
3752 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3753 * @dcbcfg: the corresponding DCBx configuration structure
3754 *
3755 * Return the number of TCs from given DCBx configuration
3756 **/
3757static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3758{
078b5876
JB		 3759 u8 num_tc = 0;
3760 int i;
41c445ff
JB		 3761
3762 /* Scan the ETS Config Priority Table to find
3763 * traffic class enabled for a given priority
3764 * and use the traffic class index to get the
3765 * number of traffic classes enabled
3766 */
3767 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3768 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3769 num_tc = dcbcfg->etscfg.prioritytable[i];
3770 }
3771
3772 /* Traffic class index starts from zero so
3773 * increment to return the actual count
3774 */
078b5876 3775 return num_tc + 1;
41c445ff
JB		 3776}
3777
3778/**
3779 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3780 * @dcbcfg: the corresponding DCBx configuration structure
3781 *
3782 * Query the current DCB configuration and return the number of
3783 * traffic classes enabled from the given DCBX config
3784 **/
3785static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3786{
3787 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3788 u8 enabled_tc = 1;
3789 u8 i;
3790
3791 for (i = 0; i < num_tc; i++)
3792 enabled_tc |= 1 << i;
3793
3794 return enabled_tc;
3795}
3796
3797/**
3798 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3799 * @pf: PF being queried
3800 *
3801 * Return number of traffic classes enabled for the given PF
3802 **/
3803static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3804{
3805 struct i40e_hw *hw = &pf->hw;
3806 u8 i, enabled_tc;
3807 u8 num_tc = 0;
3808 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3809
3810 /* If DCB is not enabled then always in single TC */
3811 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3812 return 1;
3813
3814 /* MFP mode return count of enabled TCs for this PF */
3815 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3816 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3817 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3818 if (enabled_tc & (1 << i))
3819 num_tc++;
3820 }
3821 return num_tc;
3822 }
3823
3824 /* SFP mode will be enabled for all TCs on port */
3825 return i40e_dcb_get_num_tc(dcbcfg);
3826}
3827
3828/**
3829 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3830 * @pf: PF being queried
3831 *
3832 * Return a bitmap for first enabled traffic class for this PF.
3833 **/
3834static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3835{
3836 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3837 u8 i = 0;
3838
3839 if (!enabled_tc)
3840 return 0x1; /* TC0 */
3841
3842 /* Find the first enabled TC */
3843 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3844 if (enabled_tc & (1 << i))
3845 break;
3846 }
3847
3848 return 1 << i;
3849}
3850
3851/**
3852 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3853 * @pf: PF being queried
3854 *
3855 * Return a bitmap for enabled traffic classes for this PF.
3856 **/
3857static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3858{
3859 /* If DCB is not enabled for this PF then just return default TC */
3860 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3861 return i40e_pf_get_default_tc(pf);
3862
3863 /* MFP mode will have enabled TCs set by FW */
3864 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3865 return pf->hw.func_caps.enabled_tcmap;
3866
3867 /* SFP mode we want PF to be enabled for all TCs */
3868 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3869}
3870
3871/**
3872 * i40e_vsi_get_bw_info - Query VSI BW Information
3873 * @vsi: the VSI being queried
3874 *
3875 * Returns 0 on success, negative value on failure
3876 **/
3877static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3878{
3879 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3880 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3881 struct i40e_pf *pf = vsi->back;
3882 struct i40e_hw *hw = &pf->hw;
dcae29be 3883 i40e_status aq_ret;
41c445ff 3884 u32 tc_bw_max;
41c445ff
JB		 3885 int i;
3886
3887 /* Get the VSI level BW configuration */
dcae29be
JB		 3888 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3889 if (aq_ret) {
41c445ff
JB		 3890 dev_info(&pf->pdev->dev,
3891 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3892 aq_ret, pf->hw.aq.asq_last_status);
3893 return -EINVAL;
41c445ff
JB		 3894 }
3895
3896 /* Get the VSI level BW configuration per TC */
dcae29be 3897 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3898 NULL);
dcae29be 3899 if (aq_ret) {
41c445ff
JB		 3900 dev_info(&pf->pdev->dev,
3901 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3902 aq_ret, pf->hw.aq.asq_last_status);
3903 return -EINVAL;
41c445ff
JB		 3904 }
3905
3906 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3907 dev_info(&pf->pdev->dev,
3908 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3909 bw_config.tc_valid_bits,
3910 bw_ets_config.tc_valid_bits);
3911 /* Still continuing */
3912 }
3913
3914 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3915 vsi->bw_max_quanta = bw_config.max_bw;
3916 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3917 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3918 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3919 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3920 vsi->bw_ets_limit_credits[i] =
3921 le16_to_cpu(bw_ets_config.credits[i]);
3922 /* 3 bits out of 4 for each TC */
3923 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3924 }
078b5876 3925
dcae29be 3926 return 0;
41c445ff
JB		 3927}
3928
3929/**
3930 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3931 * @vsi: the VSI being configured
3932 * @enabled_tc: TC bitmap
3933 * @bw_credits: BW shared credits per TC
3934 *
3935 * Returns 0 on success, negative value on failure
3936 **/
dcae29be 3937static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3938 u8 *bw_share)
3939{
3940 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3941 i40e_status aq_ret;
3942 int i;
41c445ff
JB		 3943
3944 bw_data.tc_valid_bits = enabled_tc;
3945 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3946 bw_data.tc_bw_credits[i] = bw_share[i];
3947
dcae29be
JB		 3948 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3949 NULL);
3950 if (aq_ret) {
41c445ff 3951 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3952 "AQ command Config VSI BW allocation per TC failed = %d\n",
3953 vsi->back->hw.aq.asq_last_status);
dcae29be 3954 return -EINVAL;
41c445ff
JB		 3955 }
3956
3957 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3958 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3959
dcae29be 3960 return 0;
41c445ff
JB		 3961}
3962
3963/**
3964 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3965 * @vsi: the VSI being configured
3966 * @enabled_tc: TC map to be enabled
3967 *
3968 **/
3969static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3970{
3971 struct net_device *netdev = vsi->netdev;
3972 struct i40e_pf *pf = vsi->back;
3973 struct i40e_hw *hw = &pf->hw;
3974 u8 netdev_tc = 0;
3975 int i;
3976 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3977
3978 if (!netdev)
3979 return;
3980
3981 if (!enabled_tc) {
3982 netdev_reset_tc(netdev);
3983 return;
3984 }
3985
3986 /* Set up actual enabled TCs on the VSI */
3987 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3988 return;
3989
3990 /* set per TC queues for the VSI */
3991 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3992 /* Only set TC queues for enabled tcs
3993 *
3994 * e.g. For a VSI that has TC0 and TC3 enabled the
3995 * enabled_tc bitmap would be 0x00001001; the driver
3996 * will set the numtc for netdev as 2 that will be
3997 * referenced by the netdev layer as TC 0 and 1.
3998 */
3999 if (vsi->tc_config.enabled_tc & (1 << i))
4000 netdev_set_tc_queue(netdev,
4001 vsi->tc_config.tc_info[i].netdev_tc,
4002 vsi->tc_config.tc_info[i].qcount,
4003 vsi->tc_config.tc_info[i].qoffset);
4004 }
4005
4006 /* Assign UP2TC map for the VSI */
4007 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4008 /* Get the actual TC# for the UP */
4009 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4010 /* Get the mapped netdev TC# for the UP */
4011 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4012 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4013 }
4014}
4015
4016/**
4017 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4018 * @vsi: the VSI being configured
4019 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4020 **/
4021static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4022 struct i40e_vsi_context *ctxt)
4023{
4024 /* copy just the sections touched not the entire info
4025 * since not all sections are valid as returned by
4026 * update vsi params
4027 */
4028 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4029 memcpy(&vsi->info.queue_mapping,
4030 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4031 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4032 sizeof(vsi->info.tc_mapping));
4033}
4034
4035/**
4036 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4037 * @vsi: VSI to be configured
4038 * @enabled_tc: TC bitmap
4039 *
4040 * This configures a particular VSI for TCs that are mapped to the
4041 * given TC bitmap. It uses default bandwidth share for TCs across
4042 * VSIs to configure TC for a particular VSI.
4043 *
4044 * NOTE:
4045 * It is expected that the VSI queues have been quisced before calling
4046 * this function.
4047 **/
4048static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4049{
4050 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4051 struct i40e_vsi_context ctxt;
4052 int ret = 0;
4053 int i;
4054
4055 /* Check if enabled_tc is same as existing or new TCs */
4056 if (vsi->tc_config.enabled_tc == enabled_tc)
4057 return ret;
4058
4059 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4060 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4061 if (enabled_tc & (1 << i))
4062 bw_share[i] = 1;
4063 }
4064
4065 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4066 if (ret) {
4067 dev_info(&vsi->back->pdev->dev,
4068 "Failed configuring TC map %d for VSI %d\n",
4069 enabled_tc, vsi->seid);
4070 goto out;
4071 }
4072
4073 /* Update Queue Pairs Mapping for currently enabled UPs */
4074 ctxt.seid = vsi->seid;
4075 ctxt.pf_num = vsi->back->hw.pf_id;
4076 ctxt.vf_num = 0;
4077 ctxt.uplink_seid = vsi->uplink_seid;
4078 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4079 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4080
4081 /* Update the VSI after updating the VSI queue-mapping information */
4082 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4083 if (ret) {
4084 dev_info(&vsi->back->pdev->dev,
4085 "update vsi failed, aq_err=%d\n",
4086 vsi->back->hw.aq.asq_last_status);
4087 goto out;
4088 }
4089 /* update the local VSI info with updated queue map */
4090 i40e_vsi_update_queue_map(vsi, &ctxt);
4091 vsi->info.valid_sections = 0;
4092
4093 /* Update current VSI BW information */
4094 ret = i40e_vsi_get_bw_info(vsi);
4095 if (ret) {
4096 dev_info(&vsi->back->pdev->dev,
4097 "Failed updating vsi bw info, aq_err=%d\n",
4098 vsi->back->hw.aq.asq_last_status);
4099 goto out;
4100 }
4101
4102 /* Update the netdev TC setup */
4103 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4104out:
4105 return ret;
4106}
4107
4e3b35b0
NP		 4108/**
4109 * i40e_veb_config_tc - Configure TCs for given VEB
4110 * @veb: given VEB
4111 * @enabled_tc: TC bitmap
4112 *
4113 * Configures given TC bitmap for VEB (switching) element
4114 **/
4115int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4116{
4117 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4118 struct i40e_pf *pf = veb->pf;
4119 int ret = 0;
4120 int i;
4121
4122 /* No TCs or already enabled TCs just return */
4123 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4124 return ret;
4125
4126 bw_data.tc_valid_bits = enabled_tc;
4127 /* bw_data.absolute_credits is not set (relative) */
4128
4129 /* Enable ETS TCs with equal BW Share for now */
4130 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4131 if (enabled_tc & (1 << i))
4132 bw_data.tc_bw_share_credits[i] = 1;
4133 }
4134
4135 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4136 &bw_data, NULL);
4137 if (ret) {
4138 dev_info(&pf->pdev->dev,
4139 "veb bw config failed, aq_err=%d\n",
4140 pf->hw.aq.asq_last_status);
4141 goto out;
4142 }
4143
4144 /* Update the BW information */
4145 ret = i40e_veb_get_bw_info(veb);
4146 if (ret) {
4147 dev_info(&pf->pdev->dev,
4148 "Failed getting veb bw config, aq_err=%d\n",
4149 pf->hw.aq.asq_last_status);
4150 }
4151
4152out:
4153 return ret;
4154}
4155
4156#ifdef CONFIG_I40E_DCB
4157/**
4158 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4159 * @pf: PF struct
4160 *
4161 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4162 * the caller would've quiesce all the VSIs before calling
4163 * this function
4164 **/
4165static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4166{
4167 u8 tc_map = 0;
4168 int ret;
4169 u8 v;
4170
4171 /* Enable the TCs available on PF to all VEBs */
4172 tc_map = i40e_pf_get_tc_map(pf);
4173 for (v = 0; v < I40E_MAX_VEB; v++) {
4174 if (!pf->veb[v])
4175 continue;
4176 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4177 if (ret) {
4178 dev_info(&pf->pdev->dev,
4179 "Failed configuring TC for VEB seid=%d\n",
4180 pf->veb[v]->seid);
4181 /* Will try to configure as many components */
4182 }
4183 }
4184
4185 /* Update each VSI */
505682cd 4186 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4187 if (!pf->vsi[v])
4188 continue;
4189
4190 /* - Enable all TCs for the LAN VSI
4191 * - For all others keep them at TC0 for now
4192 */
4193 if (v == pf->lan_vsi)
4194 tc_map = i40e_pf_get_tc_map(pf);
4195 else
4196 tc_map = i40e_pf_get_default_tc(pf);
4197
4198 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4199 if (ret) {
4200 dev_info(&pf->pdev->dev,
4201 "Failed configuring TC for VSI seid=%d\n",
4202 pf->vsi[v]->seid);
4203 /* Will try to configure as many components */
4204 } else {
0672a091
NP		 4205 /* Re-configure VSI vectors based on updated TC map */
4206 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4207 if (pf->vsi[v]->netdev)
4208 i40e_dcbnl_set_all(pf->vsi[v]);
4209 }
4210 }
4211}
4212
4213/**
4214 * i40e_init_pf_dcb - Initialize DCB configuration
4215 * @pf: PF being configured
4216 *
4217 * Query the current DCB configuration and cache it
4218 * in the hardware structure
4219 **/
4220static int i40e_init_pf_dcb(struct i40e_pf *pf)
4221{
4222 struct i40e_hw *hw = &pf->hw;
4223 int err = 0;
4224
4225 if (pf->hw.func_caps.npar_enable)
4226 goto out;
4227
4228 /* Get the initial DCB configuration */
4229 err = i40e_init_dcb(hw);
4230 if (!err) {
4231 /* Device/Function is not DCBX capable */
4232 if ((!hw->func_caps.dcb) ||
4233 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4234 dev_info(&pf->pdev->dev,
4235 "DCBX offload is not supported or is disabled for this PF.\n");
4236
4237 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4238 goto out;
4239
4240 } else {
4241 /* When status is not DISABLED then DCBX in FW */
4242 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4243 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4244
4245 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4246 /* Enable DCB tagging only when more than one TC */
4247 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4248 pf->flags |= I40E_FLAG_DCB_ENABLED;
4e3b35b0 4249 }
014269ff
NP		 4250 } else {
4251 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4252 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4253 }
4254
4255out:
4256 return err;
4257}
4258#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4259#define SPEED_SIZE 14
4260#define FC_SIZE 8
4261/**
4262 * i40e_print_link_message - print link up or down
4263 * @vsi: the VSI for which link needs a message
4264 */
4265static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4266{
4267 char speed[SPEED_SIZE] = "Unknown";
4268 char fc[FC_SIZE] = "RX/TX";
4269
4270 if (!isup) {
4271 netdev_info(vsi->netdev, "NIC Link is Down\n");
4272 return;
4273 }
4274
4275 switch (vsi->back->hw.phy.link_info.link_speed) {
4276 case I40E_LINK_SPEED_40GB:
4277 strncpy(speed, "40 Gbps", SPEED_SIZE);
4278 break;
4279 case I40E_LINK_SPEED_10GB:
4280 strncpy(speed, "10 Gbps", SPEED_SIZE);
4281 break;
4282 case I40E_LINK_SPEED_1GB:
4283 strncpy(speed, "1000 Mbps", SPEED_SIZE);
4284 break;
4285 default:
4286 break;
4287 }
4288
4289 switch (vsi->back->hw.fc.current_mode) {
4290 case I40E_FC_FULL:
4291 strncpy(fc, "RX/TX", FC_SIZE);
4292 break;
4293 case I40E_FC_TX_PAUSE:
4294 strncpy(fc, "TX", FC_SIZE);
4295 break;
4296 case I40E_FC_RX_PAUSE:
4297 strncpy(fc, "RX", FC_SIZE);
4298 break;
4299 default:
4300 strncpy(fc, "None", FC_SIZE);
4301 break;
4302 }
4303
4304 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4305 speed, fc);
4306}
4e3b35b0 4307
41c445ff
JB		 4308/**
4309 * i40e_up_complete - Finish the last steps of bringing up a connection
4310 * @vsi: the VSI being configured
4311 **/
4312static int i40e_up_complete(struct i40e_vsi *vsi)
4313{
4314 struct i40e_pf *pf = vsi->back;
4315 int err;
4316
4317 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4318 i40e_vsi_configure_msix(vsi);
4319 else
4320 i40e_configure_msi_and_legacy(vsi);
4321
4322 /* start rings */
4323 err = i40e_vsi_control_rings(vsi, true);
4324 if (err)
4325 return err;
4326
4327 clear_bit(__I40E_DOWN, &vsi->state);
4328 i40e_napi_enable_all(vsi);
4329 i40e_vsi_enable_irq(vsi);
4330
4331 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4332 (vsi->netdev)) {
cf05ed08 4333 i40e_print_link_message(vsi, true);
41c445ff
JB		 4334 netif_tx_start_all_queues(vsi->netdev);
4335 netif_carrier_on(vsi->netdev);
6d779b41 4336 } else if (vsi->netdev) {
cf05ed08 4337 i40e_print_link_message(vsi, false);
41c445ff 4338 }
ca64fa4e
ASJ		 4339
4340 /* replay FDIR SB filters */
4341 if (vsi->type == I40E_VSI_FDIR)
4342 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4343 i40e_service_event_schedule(pf);
4344
4345 return 0;
4346}
4347
4348/**
4349 * i40e_vsi_reinit_locked - Reset the VSI
4350 * @vsi: the VSI being configured
4351 *
4352 * Rebuild the ring structs after some configuration
4353 * has changed, e.g. MTU size.
4354 **/
4355static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4356{
4357 struct i40e_pf *pf = vsi->back;
4358
4359 WARN_ON(in_interrupt());
4360 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4361 usleep_range(1000, 2000);
4362 i40e_down(vsi);
4363
4364 /* Give a VF some time to respond to the reset. The
4365 * two second wait is based upon the watchdog cycle in
4366 * the VF driver.
4367 */
4368 if (vsi->type == I40E_VSI_SRIOV)
4369 msleep(2000);
4370 i40e_up(vsi);
4371 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4372}
4373
4374/**
4375 * i40e_up - Bring the connection back up after being down
4376 * @vsi: the VSI being configured
4377 **/
4378int i40e_up(struct i40e_vsi *vsi)
4379{
4380 int err;
4381
4382 err = i40e_vsi_configure(vsi);
4383 if (!err)
4384 err = i40e_up_complete(vsi);
4385
4386 return err;
4387}
4388
4389/**
4390 * i40e_down - Shutdown the connection processing
4391 * @vsi: the VSI being stopped
4392 **/
4393void i40e_down(struct i40e_vsi *vsi)
4394{
4395 int i;
4396
4397 /* It is assumed that the caller of this function
4398 * sets the vsi->state __I40E_DOWN bit.
4399 */
4400 if (vsi->netdev) {
4401 netif_carrier_off(vsi->netdev);
4402 netif_tx_disable(vsi->netdev);
4403 }
4404 i40e_vsi_disable_irq(vsi);
4405 i40e_vsi_control_rings(vsi, false);
4406 i40e_napi_disable_all(vsi);
4407
4408 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4409 i40e_clean_tx_ring(vsi->tx_rings[i]);
4410 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4411 }
4412}
4413
4414/**
4415 * i40e_setup_tc - configure multiple traffic classes
4416 * @netdev: net device to configure
4417 * @tc: number of traffic classes to enable
4418 **/
4419static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4420{
4421 struct i40e_netdev_priv *np = netdev_priv(netdev);
4422 struct i40e_vsi *vsi = np->vsi;
4423 struct i40e_pf *pf = vsi->back;
4424 u8 enabled_tc = 0;
4425 int ret = -EINVAL;
4426 int i;
4427
4428 /* Check if DCB enabled to continue */
4429 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4430 netdev_info(netdev, "DCB is not enabled for adapter\n");
4431 goto exit;
4432 }
4433
4434 /* Check if MFP enabled */
4435 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4436 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4437 goto exit;
4438 }
4439
4440 /* Check whether tc count is within enabled limit */
4441 if (tc > i40e_pf_get_num_tc(pf)) {
4442 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4443 goto exit;
4444 }
4445
4446 /* Generate TC map for number of tc requested */
4447 for (i = 0; i < tc; i++)
4448 enabled_tc |= (1 << i);
4449
4450 /* Requesting same TC configuration as already enabled */
4451 if (enabled_tc == vsi->tc_config.enabled_tc)
4452 return 0;
4453
4454 /* Quiesce VSI queues */
4455 i40e_quiesce_vsi(vsi);
4456
4457 /* Configure VSI for enabled TCs */
4458 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4459 if (ret) {
4460 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4461 vsi->seid);
4462 goto exit;
4463 }
4464
4465 /* Unquiesce VSI */
4466 i40e_unquiesce_vsi(vsi);
4467
4468exit:
4469 return ret;
4470}
4471
4472/**
4473 * i40e_open - Called when a network interface is made active
4474 * @netdev: network interface device structure
4475 *
4476 * The open entry point is called when a network interface is made
4477 * active by the system (IFF_UP). At this point all resources needed
4478 * for transmit and receive operations are allocated, the interrupt
4479 * handler is registered with the OS, the netdev watchdog subtask is
4480 * enabled, and the stack is notified that the interface is ready.
4481 *
4482 * Returns 0 on success, negative value on failure
4483 **/
4484static int i40e_open(struct net_device *netdev)
4485{
4486 struct i40e_netdev_priv *np = netdev_priv(netdev);
4487 struct i40e_vsi *vsi = np->vsi;
4488 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4489 int err;
4490
4eb3f768
SN		 4491 /* disallow open during test or if eeprom is broken */
4492 if (test_bit(__I40E_TESTING, &pf->state) ||
4493 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4494 return -EBUSY;
4495
4496 netif_carrier_off(netdev);
4497
6c167f58
EK		 4498 err = i40e_vsi_open(vsi);
4499 if (err)
4500 return err;
4501
059dab69
JB		 4502 /* configure global TSO hardware offload settings */
4503 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4504 TCP_FLAG_FIN) >> 16);
4505 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4506 TCP_FLAG_FIN |
4507 TCP_FLAG_CWR) >> 16);
4508 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4509
6c167f58
EK		 4510#ifdef CONFIG_I40E_VXLAN
4511 vxlan_get_rx_port(netdev);
4512#endif
4513
4514 return 0;
4515}
4516
4517/**
4518 * i40e_vsi_open -
4519 * @vsi: the VSI to open
4520 *
4521 * Finish initialization of the VSI.
4522 *
4523 * Returns 0 on success, negative value on failure
4524 **/
4525int i40e_vsi_open(struct i40e_vsi *vsi)
4526{
4527 struct i40e_pf *pf = vsi->back;
4528 char int_name[IFNAMSIZ];
4529 int err;
4530
41c445ff
JB		 4531 /* allocate descriptors */
4532 err = i40e_vsi_setup_tx_resources(vsi);
4533 if (err)
4534 goto err_setup_tx;
4535 err = i40e_vsi_setup_rx_resources(vsi);
4536 if (err)
4537 goto err_setup_rx;
4538
4539 err = i40e_vsi_configure(vsi);
4540 if (err)
4541 goto err_setup_rx;
4542
c22e3c6c
SN		 4543 if (vsi->netdev) {
4544 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4545 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4546 err = i40e_vsi_request_irq(vsi, int_name);
4547 if (err)
4548 goto err_setup_rx;
41c445ff 4549
c22e3c6c
SN		 4550 /* Notify the stack of the actual queue counts. */
4551 err = netif_set_real_num_tx_queues(vsi->netdev,
4552 vsi->num_queue_pairs);
4553 if (err)
4554 goto err_set_queues;
25946ddb 4555
c22e3c6c
SN		 4556 err = netif_set_real_num_rx_queues(vsi->netdev,
4557 vsi->num_queue_pairs);
4558 if (err)
4559 goto err_set_queues;
8a9eb7d3
SN		 4560
4561 } else if (vsi->type == I40E_VSI_FDIR) {
4562 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4563 dev_driver_string(&pf->pdev->dev));
4564 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4565 } else {
ce9ccb17 4566 err = -EINVAL;
6c167f58
EK		 4567 goto err_setup_rx;
4568 }
25946ddb 4569
41c445ff
JB		 4570 err = i40e_up_complete(vsi);
4571 if (err)
4572 goto err_up_complete;
4573
41c445ff
JB		 4574 return 0;
4575
4576err_up_complete:
4577 i40e_down(vsi);
25946ddb 4578err_set_queues:
41c445ff
JB		 4579 i40e_vsi_free_irq(vsi);
4580err_setup_rx:
4581 i40e_vsi_free_rx_resources(vsi);
4582err_setup_tx:
4583 i40e_vsi_free_tx_resources(vsi);
4584 if (vsi == pf->vsi[pf->lan_vsi])
4585 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4586
4587 return err;
4588}
4589
17a73f6b
JG		 4590/**
4591 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4592 * @pf: Pointer to pf
4593 *
4594 * This function destroys the hlist where all the Flow Director
4595 * filters were saved.
4596 **/
4597static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4598{
4599 struct i40e_fdir_filter *filter;
4600 struct hlist_node *node2;
4601
4602 hlist_for_each_entry_safe(filter, node2,
4603 &pf->fdir_filter_list, fdir_node) {
4604 hlist_del(&filter->fdir_node);
4605 kfree(filter);
4606 }
4607 pf->fdir_pf_active_filters = 0;
4608}
4609
41c445ff
JB		 4610/**
4611 * i40e_close - Disables a network interface
4612 * @netdev: network interface device structure
4613 *
4614 * The close entry point is called when an interface is de-activated
4615 * by the OS. The hardware is still under the driver's control, but
4616 * this netdev interface is disabled.
4617 *
4618 * Returns 0, this is not allowed to fail
4619 **/
4620static int i40e_close(struct net_device *netdev)
4621{
4622 struct i40e_netdev_priv *np = netdev_priv(netdev);
4623 struct i40e_vsi *vsi = np->vsi;
4624
90ef8d47 4625 i40e_vsi_close(vsi);
41c445ff
JB		 4626
4627 return 0;
4628}
4629
4630/**
4631 * i40e_do_reset - Start a PF or Core Reset sequence
4632 * @pf: board private structure
4633 * @reset_flags: which reset is requested
4634 *
4635 * The essential difference in resets is that the PF Reset
4636 * doesn't clear the packet buffers, doesn't reset the PE
4637 * firmware, and doesn't bother the other PFs on the chip.
4638 **/
4639void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4640{
4641 u32 val;
4642
4643 WARN_ON(in_interrupt());
4644
263fc48f
MW		 4645 if (i40e_check_asq_alive(&pf->hw))
4646 i40e_vc_notify_reset(pf);
4647
41c445ff
JB		 4648 /* do the biggest reset indicated */
4649 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4650
4651 /* Request a Global Reset
4652 *
4653 * This will start the chip's countdown to the actual full
4654 * chip reset event, and a warning interrupt to be sent
4655 * to all PFs, including the requestor. Our handler
4656 * for the warning interrupt will deal with the shutdown
4657 * and recovery of the switch setup.
4658 */
69bfb110 4659 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4660 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4661 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4662 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4663
4664 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4665
4666 /* Request a Core Reset
4667 *
4668 * Same as Global Reset, except does *not* include the MAC/PHY
4669 */
69bfb110 4670 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4671 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4672 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4673 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4674 i40e_flush(&pf->hw);
4675
7823fe34
SN		 4676 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4677
4678 /* Request a Firmware Reset
4679 *
4680 * Same as Global reset, plus restarting the
4681 * embedded firmware engine.
4682 */
4683 /* enable EMP Reset */
4684 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4685 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4686 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4687
4688 /* force the reset */
4689 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4690 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4691 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4692 i40e_flush(&pf->hw);
4693
41c445ff
JB		 4694 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4695
4696 /* Request a PF Reset
4697 *
4698 * Resets only the PF-specific registers
4699 *
4700 * This goes directly to the tear-down and rebuild of
4701 * the switch, since we need to do all the recovery as
4702 * for the Core Reset.
4703 */
69bfb110 4704 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4705 i40e_handle_reset_warning(pf);
4706
4707 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4708 int v;
4709
4710 /* Find the VSI(s) that requested a re-init */
4711 dev_info(&pf->pdev->dev,
4712 "VSI reinit requested\n");
505682cd 4713 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4714 struct i40e_vsi *vsi = pf->vsi[v];
4715 if (vsi != NULL &&
4716 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4717 i40e_vsi_reinit_locked(pf->vsi[v]);
4718 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4719 }
4720 }
4721
b5d06f05
NP		 4722 /* no further action needed, so return now */
4723 return;
4724 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4725 int v;
4726
4727 /* Find the VSI(s) that needs to be brought down */
4728 dev_info(&pf->pdev->dev, "VSI down requested\n");
4729 for (v = 0; v < pf->num_alloc_vsi; v++) {
4730 struct i40e_vsi *vsi = pf->vsi[v];
4731 if (vsi != NULL &&
4732 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4733 set_bit(__I40E_DOWN, &vsi->state);
4734 i40e_down(vsi);
4735 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4736 }
4737 }
4738
41c445ff
JB		 4739 /* no further action needed, so return now */
4740 return;
4741 } else {
4742 dev_info(&pf->pdev->dev,
4743 "bad reset request 0x%08x\n", reset_flags);
4744 return;
4745 }
4746}
4747
4e3b35b0
NP		 4748#ifdef CONFIG_I40E_DCB
4749/**
4750 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4751 * @pf: board private structure
4752 * @old_cfg: current DCB config
4753 * @new_cfg: new DCB config
4754 **/
4755bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4756 struct i40e_dcbx_config *old_cfg,
4757 struct i40e_dcbx_config *new_cfg)
4758{
4759 bool need_reconfig = false;
4760
4761 /* Check if ETS configuration has changed */
4762 if (memcmp(&new_cfg->etscfg,
4763 &old_cfg->etscfg,
4764 sizeof(new_cfg->etscfg))) {
4765 /* If Priority Table has changed reconfig is needed */
4766 if (memcmp(&new_cfg->etscfg.prioritytable,
4767 &old_cfg->etscfg.prioritytable,
4768 sizeof(new_cfg->etscfg.prioritytable))) {
4769 need_reconfig = true;
69bfb110 4770 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4771 }
4772
4773 if (memcmp(&new_cfg->etscfg.tcbwtable,
4774 &old_cfg->etscfg.tcbwtable,
4775 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4776 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4777
4778 if (memcmp(&new_cfg->etscfg.tsatable,
4779 &old_cfg->etscfg.tsatable,
4780 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4781 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4782 }
4783
4784 /* Check if PFC configuration has changed */
4785 if (memcmp(&new_cfg->pfc,
4786 &old_cfg->pfc,
4787 sizeof(new_cfg->pfc))) {
4788 need_reconfig = true;
69bfb110 4789 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4790 }
4791
4792 /* Check if APP Table has changed */
4793 if (memcmp(&new_cfg->app,
4794 &old_cfg->app,
3d9667a9 4795 sizeof(new_cfg->app))) {
4e3b35b0 4796 need_reconfig = true;
69bfb110 4797 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4798 }
4e3b35b0
NP		 4799
4800 return need_reconfig;
4801}
4802
4803/**
4804 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4805 * @pf: board private structure
4806 * @e: event info posted on ARQ
4807 **/
4808static int i40e_handle_lldp_event(struct i40e_pf *pf,
4809 struct i40e_arq_event_info *e)
4810{
4811 struct i40e_aqc_lldp_get_mib *mib =
4812 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4813 struct i40e_hw *hw = &pf->hw;
4814 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4815 struct i40e_dcbx_config tmp_dcbx_cfg;
4816 bool need_reconfig = false;
4817 int ret = 0;
4818 u8 type;
4819
4d9b6043
NP		 4820 /* Not DCB capable or capability disabled */
4821 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
4822 return ret;
4823
4e3b35b0
NP		 4824 /* Ignore if event is not for Nearest Bridge */
4825 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4826 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4827 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4828 return ret;
4829
4830 /* Check MIB Type and return if event for Remote MIB update */
4831 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4832 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4833 /* Update the remote cached instance and return */
4834 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4835 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4836 &hw->remote_dcbx_config);
4837 goto exit;
4838 }
4839
4840 /* Convert/store the DCBX data from LLDPDU temporarily */
4841 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4842 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4843 if (ret) {
4844 /* Error in LLDPDU parsing return */
4845 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4846 goto exit;
4847 }
4848
4849 /* No change detected in DCBX configs */
4850 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4851 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4852 goto exit;
4853 }
4854
4855 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4856
4857 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4858
4859 /* Overwrite the new configuration */
4860 *dcbx_cfg = tmp_dcbx_cfg;
4861
4862 if (!need_reconfig)
4863 goto exit;
4864
4d9b6043
NP		 4865 /* Enable DCB tagging only when more than one TC */
4866 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
4867 pf->flags |= I40E_FLAG_DCB_ENABLED;
4868 else
4869 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
4870
4e3b35b0
NP		 4871 /* Reconfiguration needed quiesce all VSIs */
4872 i40e_pf_quiesce_all_vsi(pf);
4873
4874 /* Changes in configuration update VEB/VSI */
4875 i40e_dcb_reconfigure(pf);
4876
4877 i40e_pf_unquiesce_all_vsi(pf);
4878exit:
4879 return ret;
4880}
4881#endif /* CONFIG_I40E_DCB */
4882
23326186
ASJ		 4883/**
4884 * i40e_do_reset_safe - Protected reset path for userland calls.
4885 * @pf: board private structure
4886 * @reset_flags: which reset is requested
4887 *
4888 **/
4889void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4890{
4891 rtnl_lock();
4892 i40e_do_reset(pf, reset_flags);
4893 rtnl_unlock();
4894}
4895
41c445ff
JB		 4896/**
4897 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4898 * @pf: board private structure
4899 * @e: event info posted on ARQ
4900 *
4901 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4902 * and VF queues
4903 **/
4904static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4905 struct i40e_arq_event_info *e)
4906{
4907 struct i40e_aqc_lan_overflow *data =
4908 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4909 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4910 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4911 struct i40e_hw *hw = &pf->hw;
4912 struct i40e_vf *vf;
4913 u16 vf_id;
4914
69bfb110
JB		 4915 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4916 queue, qtx_ctl);
41c445ff
JB		 4917
4918 /* Queue belongs to VF, find the VF and issue VF reset */
4919 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4920 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4921 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4922 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4923 vf_id -= hw->func_caps.vf_base_id;
4924 vf = &pf->vf[vf_id];
4925 i40e_vc_notify_vf_reset(vf);
4926 /* Allow VF to process pending reset notification */
4927 msleep(20);
4928 i40e_reset_vf(vf, false);
4929 }
4930}
4931
4932/**
4933 * i40e_service_event_complete - Finish up the service event
4934 * @pf: board private structure
4935 **/
4936static void i40e_service_event_complete(struct i40e_pf *pf)
4937{
4938 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4939
4940 /* flush memory to make sure state is correct before next watchog */
4e857c58 4941 smp_mb__before_atomic();
41c445ff
JB		 4942 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4943}
4944
55a5e60b
ASJ		 4945/**
4946 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4947 * @pf: board private structure
4948 **/
4949int i40e_get_current_fd_count(struct i40e_pf *pf)
4950{
4951 int val, fcnt_prog;
4952 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4953 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4954 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4955 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4956 return fcnt_prog;
4957}
4958
4959/**
4960 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4961 * @pf: board private structure
4962 **/
4963void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4964{
4965 u32 fcnt_prog, fcnt_avail;
4966
4967 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4968 * to re-enable
4969 */
4970 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4971 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4972 return;
4973 fcnt_prog = i40e_get_current_fd_count(pf);
89132783 4974 fcnt_avail = i40e_get_fd_cnt_all(pf);
55a5e60b
ASJ		 4975 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4976 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4977 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4978 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4979 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4980 }
4981 }
4982 /* Wait for some more space to be available to turn on ATR */
4983 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4984 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4985 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4986 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4987 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4988 }
4989 }
4990}
4991
41c445ff
JB		 4992/**
4993 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4994 * @pf: board private structure
4995 **/
4996static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4997{
4998 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4999 return;
5000
41c445ff
JB		 5001 /* if interface is down do nothing */
5002 if (test_bit(__I40E_DOWN, &pf->state))
5003 return;
55a5e60b
ASJ		 5004 i40e_fdir_check_and_reenable(pf);
5005
5006 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5007 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
5008 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 5009}
5010
5011/**
5012 * i40e_vsi_link_event - notify VSI of a link event
5013 * @vsi: vsi to be notified
5014 * @link_up: link up or down
5015 **/
5016static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5017{
5018 if (!vsi)
5019 return;
5020
5021 switch (vsi->type) {
5022 case I40E_VSI_MAIN:
5023 if (!vsi->netdev || !vsi->netdev_registered)
5024 break;
5025
5026 if (link_up) {
5027 netif_carrier_on(vsi->netdev);
5028 netif_tx_wake_all_queues(vsi->netdev);
5029 } else {
5030 netif_carrier_off(vsi->netdev);
5031 netif_tx_stop_all_queues(vsi->netdev);
5032 }
5033 break;
5034
5035 case I40E_VSI_SRIOV:
5036 break;
5037
5038 case I40E_VSI_VMDQ2:
5039 case I40E_VSI_CTRL:
5040 case I40E_VSI_MIRROR:
5041 default:
5042 /* there is no notification for other VSIs */
5043 break;
5044 }
5045}
5046
5047/**
5048 * i40e_veb_link_event - notify elements on the veb of a link event
5049 * @veb: veb to be notified
5050 * @link_up: link up or down
5051 **/
5052static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5053{
5054 struct i40e_pf *pf;
5055 int i;
5056
5057 if (!veb || !veb->pf)
5058 return;
5059 pf = veb->pf;
5060
5061 /* depth first... */
5062 for (i = 0; i < I40E_MAX_VEB; i++)
5063 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5064 i40e_veb_link_event(pf->veb[i], link_up);
5065
5066 /* ... now the local VSIs */
505682cd 5067 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5068 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5069 i40e_vsi_link_event(pf->vsi[i], link_up);
5070}
5071
5072/**
5073 * i40e_link_event - Update netif_carrier status
5074 * @pf: board private structure
5075 **/
5076static void i40e_link_event(struct i40e_pf *pf)
5077{
5078 bool new_link, old_link;
5079
5080 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
5081 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
5082
5083 if (new_link == old_link)
5084 return;
6d779b41 5085 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 5086 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 5087
5088 /* Notify the base of the switch tree connected to
5089 * the link. Floating VEBs are not notified.
5090 */
5091 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5092 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5093 else
5094 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
5095
5096 if (pf->vf)
5097 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5098
5099 if (pf->flags & I40E_FLAG_PTP)
5100 i40e_ptp_set_increment(pf);
41c445ff
JB		 5101}
5102
5103/**
5104 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5105 * @pf: board private structure
5106 *
5107 * Set the per-queue flags to request a check for stuck queues in the irq
5108 * clean functions, then force interrupts to be sure the irq clean is called.
5109 **/
5110static void i40e_check_hang_subtask(struct i40e_pf *pf)
5111{
5112 int i, v;
5113
5114 /* If we're down or resetting, just bail */
5115 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5116 return;
5117
5118 /* for each VSI/netdev
5119 * for each Tx queue
5120 * set the check flag
5121 * for each q_vector
5122 * force an interrupt
5123 */
505682cd 5124 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5125 struct i40e_vsi *vsi = pf->vsi[v];
5126 int armed = 0;
5127
5128 if (!pf->vsi[v] ||
5129 test_bit(__I40E_DOWN, &vsi->state) ||
5130 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5131 continue;
5132
5133 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5134 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5135 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5136 &vsi->tx_rings[i]->state))
41c445ff
JB		 5137 armed++;
5138 }
5139
5140 if (armed) {
5141 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5142 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5143 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5144 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5145 } else {
5146 u16 vec = vsi->base_vector - 1;
5147 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5148 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5149 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5150 wr32(&vsi->back->hw,
5151 I40E_PFINT_DYN_CTLN(vec), val);
5152 }
5153 i40e_flush(&vsi->back->hw);
5154 }
5155 }
5156}
5157
5158/**
5159 * i40e_watchdog_subtask - Check and bring link up
5160 * @pf: board private structure
5161 **/
5162static void i40e_watchdog_subtask(struct i40e_pf *pf)
5163{
5164 int i;
5165
5166 /* if interface is down do nothing */
5167 if (test_bit(__I40E_DOWN, &pf->state) ||
5168 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5169 return;
5170
5171 /* Update the stats for active netdevs so the network stack
5172 * can look at updated numbers whenever it cares to
5173 */
505682cd 5174 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5175 if (pf->vsi[i] && pf->vsi[i]->netdev)
5176 i40e_update_stats(pf->vsi[i]);
5177
5178 /* Update the stats for the active switching components */
5179 for (i = 0; i < I40E_MAX_VEB; i++)
5180 if (pf->veb[i])
5181 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5182
5183 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5184}
5185
5186/**
5187 * i40e_reset_subtask - Set up for resetting the device and driver
5188 * @pf: board private structure
5189 **/
5190static void i40e_reset_subtask(struct i40e_pf *pf)
5191{
5192 u32 reset_flags = 0;
5193
23326186 5194 rtnl_lock();
41c445ff
JB		 5195 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5196 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5197 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5198 }
5199 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5200 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5201 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5202 }
5203 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5204 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5205 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5206 }
5207 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5208 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5209 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5210 }
b5d06f05
NP		 5211 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5212 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5213 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5214 }
41c445ff
JB		 5215
5216 /* If there's a recovery already waiting, it takes
5217 * precedence before starting a new reset sequence.
5218 */
5219 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5220 i40e_handle_reset_warning(pf);
23326186 5221 goto unlock;
41c445ff
JB		 5222 }
5223
5224 /* If we're already down or resetting, just bail */
5225 if (reset_flags &&
5226 !test_bit(__I40E_DOWN, &pf->state) &&
5227 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5228 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5229
5230unlock:
5231 rtnl_unlock();
41c445ff
JB		 5232}
5233
5234/**
5235 * i40e_handle_link_event - Handle link event
5236 * @pf: board private structure
5237 * @e: event info posted on ARQ
5238 **/
5239static void i40e_handle_link_event(struct i40e_pf *pf,
5240 struct i40e_arq_event_info *e)
5241{
5242 struct i40e_hw *hw = &pf->hw;
5243 struct i40e_aqc_get_link_status *status =
5244 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5245 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5246
5247 /* save off old link status information */
5248 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5249 sizeof(pf->hw.phy.link_info_old));
5250
5251 /* update link status */
5252 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5253 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5254 hw_link_info->link_info = status->link_info;
5255 hw_link_info->an_info = status->an_info;
5256 hw_link_info->ext_info = status->ext_info;
5257 hw_link_info->lse_enable =
5258 le16_to_cpu(status->command_flags) &
5259 I40E_AQ_LSE_ENABLE;
5260
5261 /* process the event */
5262 i40e_link_event(pf);
5263
5264 /* Do a new status request to re-enable LSE reporting
5265 * and load new status information into the hw struct,
5266 * then see if the status changed while processing the
5267 * initial event.
5268 */
5269 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5270 i40e_link_event(pf);
5271}
5272
5273/**
5274 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5275 * @pf: board private structure
5276 **/
5277static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5278{
5279 struct i40e_arq_event_info event;
5280 struct i40e_hw *hw = &pf->hw;
5281 u16 pending, i = 0;
5282 i40e_status ret;
5283 u16 opcode;
86df242b 5284 u32 oldval;
41c445ff
JB		 5285 u32 val;
5286
5287 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5288 return;
5289
86df242b
SN		 5290 /* check for error indications */
5291 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5292 oldval = val;
5293 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5294 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5295 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5296 }
5297 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5298 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5299 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5300 }
5301 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5302 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5303 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5304 }
5305 if (oldval != val)
5306 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5307
5308 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5309 oldval = val;
5310 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5311 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5312 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5313 }
5314 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5315 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5316 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5317 }
5318 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5319 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5320 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5321 }
5322 if (oldval != val)
5323 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5324
3197ce22 5325 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5326 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5327 if (!event.msg_buf)
5328 return;
5329
5330 do {
2f019123 5331 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5332 ret = i40e_clean_arq_element(hw, &event, &pending);
5333 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5334 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5335 break;
5336 } else if (ret) {
5337 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5338 break;
5339 }
5340
5341 opcode = le16_to_cpu(event.desc.opcode);
5342 switch (opcode) {
5343
5344 case i40e_aqc_opc_get_link_status:
5345 i40e_handle_link_event(pf, &event);
5346 break;
5347 case i40e_aqc_opc_send_msg_to_pf:
5348 ret = i40e_vc_process_vf_msg(pf,
5349 le16_to_cpu(event.desc.retval),
5350 le32_to_cpu(event.desc.cookie_high),
5351 le32_to_cpu(event.desc.cookie_low),
5352 event.msg_buf,
5353 event.msg_size);
5354 break;
5355 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5356 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5357#ifdef CONFIG_I40E_DCB
5358 rtnl_lock();
5359 ret = i40e_handle_lldp_event(pf, &event);
5360 rtnl_unlock();
5361#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5362 break;
5363 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5364 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5365 i40e_handle_lan_overflow_event(pf, &event);
5366 break;
0467bc91
SN		 5367 case i40e_aqc_opc_send_msg_to_peer:
5368 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5369 break;
41c445ff
JB		 5370 default:
5371 dev_info(&pf->pdev->dev,
0467bc91
SN		 5372 "ARQ Error: Unknown event 0x%04x received\n",
5373 opcode);
41c445ff
JB		 5374 break;
5375 }
5376 } while (pending && (i++ < pf->adminq_work_limit));
5377
5378 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5379 /* re-enable Admin queue interrupt cause */
5380 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5381 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5382 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5383 i40e_flush(hw);
5384
5385 kfree(event.msg_buf);
5386}
5387
4eb3f768
SN		 5388/**
5389 * i40e_verify_eeprom - make sure eeprom is good to use
5390 * @pf: board private structure
5391 **/
5392static void i40e_verify_eeprom(struct i40e_pf *pf)
5393{
5394 int err;
5395
5396 err = i40e_diag_eeprom_test(&pf->hw);
5397 if (err) {
5398 /* retry in case of garbage read */
5399 err = i40e_diag_eeprom_test(&pf->hw);
5400 if (err) {
5401 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5402 err);
5403 set_bit(__I40E_BAD_EEPROM, &pf->state);
5404 }
5405 }
5406
5407 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5408 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5409 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5410 }
5411}
5412
41c445ff
JB		 5413/**
5414 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5415 * @veb: pointer to the VEB instance
5416 *
5417 * This is a recursive function that first builds the attached VSIs then
5418 * recurses in to build the next layer of VEB. We track the connections
5419 * through our own index numbers because the seid's from the HW could
5420 * change across the reset.
5421 **/
5422static int i40e_reconstitute_veb(struct i40e_veb *veb)
5423{
5424 struct i40e_vsi *ctl_vsi = NULL;
5425 struct i40e_pf *pf = veb->pf;
5426 int v, veb_idx;
5427 int ret;
5428
5429 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5430 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5431 if (pf->vsi[v] &&
5432 pf->vsi[v]->veb_idx == veb->idx &&
5433 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5434 ctl_vsi = pf->vsi[v];
5435 break;
5436 }
5437 }
5438 if (!ctl_vsi) {
5439 dev_info(&pf->pdev->dev,
5440 "missing owner VSI for veb_idx %d\n", veb->idx);
5441 ret = -ENOENT;
5442 goto end_reconstitute;
5443 }
5444 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5445 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5446 ret = i40e_add_vsi(ctl_vsi);
5447 if (ret) {
5448 dev_info(&pf->pdev->dev,
5449 "rebuild of owner VSI failed: %d\n", ret);
5450 goto end_reconstitute;
5451 }
5452 i40e_vsi_reset_stats(ctl_vsi);
5453
5454 /* create the VEB in the switch and move the VSI onto the VEB */
5455 ret = i40e_add_veb(veb, ctl_vsi);
5456 if (ret)
5457 goto end_reconstitute;
5458
5459 /* create the remaining VSIs attached to this VEB */
505682cd 5460 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5461 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5462 continue;
5463
5464 if (pf->vsi[v]->veb_idx == veb->idx) {
5465 struct i40e_vsi *vsi = pf->vsi[v];
5466 vsi->uplink_seid = veb->seid;
5467 ret = i40e_add_vsi(vsi);
5468 if (ret) {
5469 dev_info(&pf->pdev->dev,
5470 "rebuild of vsi_idx %d failed: %d\n",
5471 v, ret);
5472 goto end_reconstitute;
5473 }
5474 i40e_vsi_reset_stats(vsi);
5475 }
5476 }
5477
5478 /* create any VEBs attached to this VEB - RECURSION */
5479 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5480 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5481 pf->veb[veb_idx]->uplink_seid = veb->seid;
5482 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5483 if (ret)
5484 break;
5485 }
5486 }
5487
5488end_reconstitute:
5489 return ret;
5490}
5491
5492/**
5493 * i40e_get_capabilities - get info about the HW
5494 * @pf: the PF struct
5495 **/
5496static int i40e_get_capabilities(struct i40e_pf *pf)
5497{
5498 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5499 u16 data_size;
5500 int buf_len;
5501 int err;
5502
5503 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5504 do {
5505 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5506 if (!cap_buf)
5507 return -ENOMEM;
5508
5509 /* this loads the data into the hw struct for us */
5510 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5511 &data_size,
5512 i40e_aqc_opc_list_func_capabilities,
5513 NULL);
5514 /* data loaded, buffer no longer needed */
5515 kfree(cap_buf);
5516
5517 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5518 /* retry with a larger buffer */
5519 buf_len = data_size;
5520 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5521 dev_info(&pf->pdev->dev,
5522 "capability discovery failed: aq=%d\n",
5523 pf->hw.aq.asq_last_status);
5524 return -ENODEV;
5525 }
5526 } while (err);
5527
ac71b7ba
ASJ		 5528 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5529 (pf->hw.aq.fw_maj_ver < 2)) {
5530 pf->hw.func_caps.num_msix_vectors++;
5531 pf->hw.func_caps.num_msix_vectors_vf++;
5532 }
5533
41c445ff
JB		 5534 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5535 dev_info(&pf->pdev->dev,
5536 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5537 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5538 pf->hw.func_caps.num_msix_vectors,
5539 pf->hw.func_caps.num_msix_vectors_vf,
5540 pf->hw.func_caps.fd_filters_guaranteed,
5541 pf->hw.func_caps.fd_filters_best_effort,
5542 pf->hw.func_caps.num_tx_qp,
5543 pf->hw.func_caps.num_vsis);
5544
7134f9ce
JB		 5545#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5546 + pf->hw.func_caps.num_vfs)
5547 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5548 dev_info(&pf->pdev->dev,
5549 "got num_vsis %d, setting num_vsis to %d\n",
5550 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5551 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5552 }
5553
41c445ff
JB		 5554 return 0;
5555}
5556
cbf61325
ASJ		 5557static int i40e_vsi_clear(struct i40e_vsi *vsi);
5558
41c445ff 5559/**
cbf61325 5560 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5561 * @pf: board private structure
5562 **/
cbf61325 5563static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5564{
5565 struct i40e_vsi *vsi;
8a9eb7d3 5566 int i;
41c445ff 5567
407e063c
JB		 5568 /* quick workaround for an NVM issue that leaves a critical register
5569 * uninitialized
5570 */
5571 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5572 static const u32 hkey[] = {
5573 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5574 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5575 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5576 0x95b3a76d};
5577
5578 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5579 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5580 }
5581
cbf61325 5582 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5583 return;
5584
cbf61325 5585 /* find existing VSI and see if it needs configuring */
41c445ff 5586 vsi = NULL;
505682cd 5587 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5588 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5589 vsi = pf->vsi[i];
cbf61325
ASJ		 5590 break;
5591 }
5592 }
5593
5594 /* create a new VSI if none exists */
41c445ff 5595 if (!vsi) {
cbf61325
ASJ		 5596 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5597 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5598 if (!vsi) {
5599 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5600 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5601 return;
41c445ff 5602 }
cbf61325 5603 }
41c445ff 5604
8a9eb7d3 5605 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5606}
5607
5608/**
5609 * i40e_fdir_teardown - release the Flow Director resources
5610 * @pf: board private structure
5611 **/
5612static void i40e_fdir_teardown(struct i40e_pf *pf)
5613{
5614 int i;
5615
17a73f6b 5616 i40e_fdir_filter_exit(pf);
505682cd 5617 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5618 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5619 i40e_vsi_release(pf->vsi[i]);
5620 break;
5621 }
5622 }
5623}
5624
5625/**
f650a38b 5626 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5627 * @pf: board private structure
5628 *
f650a38b
ASJ		 5629 * Close up the VFs and other things in prep for pf Reset.
5630 **/
23cfbe07 5631static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5632{
41c445ff 5633 struct i40e_hw *hw = &pf->hw;
60442dea 5634 i40e_status ret = 0;
41c445ff
JB		 5635 u32 v;
5636
5637 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5638 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 5639 return;
41c445ff 5640
69bfb110 5641 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5642
41c445ff
JB		 5643 /* quiesce the VSIs and their queues that are not already DOWN */
5644 i40e_pf_quiesce_all_vsi(pf);
5645
505682cd 5646 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5647 if (pf->vsi[v])
5648 pf->vsi[v]->seid = 0;
5649 }
5650
5651 i40e_shutdown_adminq(&pf->hw);
5652
f650a38b 5653 /* call shutdown HMC */
60442dea
SN		 5654 if (hw->hmc.hmc_obj) {
5655 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 5656 if (ret)
60442dea
SN		 5657 dev_warn(&pf->pdev->dev,
5658 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 5659 }
f650a38b
ASJ		 5660}
5661
44033fac
JB		 5662/**
5663 * i40e_send_version - update firmware with driver version
5664 * @pf: PF struct
5665 */
5666static void i40e_send_version(struct i40e_pf *pf)
5667{
5668 struct i40e_driver_version dv;
5669
5670 dv.major_version = DRV_VERSION_MAJOR;
5671 dv.minor_version = DRV_VERSION_MINOR;
5672 dv.build_version = DRV_VERSION_BUILD;
5673 dv.subbuild_version = 0;
5674 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
5675 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5676}
5677
f650a38b 5678/**
4dda12e6 5679 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5680 * @pf: board private structure
bc7d338f 5681 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5682 **/
bc7d338f 5683static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5684{
f650a38b
ASJ		 5685 struct i40e_hw *hw = &pf->hw;
5686 i40e_status ret;
5687 u32 v;
5688
41c445ff
JB		 5689 /* Now we wait for GRST to settle out.
5690 * We don't have to delete the VEBs or VSIs from the hw switch
5691 * because the reset will make them disappear.
5692 */
5693 ret = i40e_pf_reset(hw);
b5565400 5694 if (ret) {
41c445ff 5695 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5696 goto end_core_reset;
5697 }
41c445ff
JB		 5698 pf->pfr_count++;
5699
5700 if (test_bit(__I40E_DOWN, &pf->state))
5701 goto end_core_reset;
69bfb110 5702 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5703
5704 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5705 ret = i40e_init_adminq(&pf->hw);
5706 if (ret) {
5707 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5708 goto end_core_reset;
5709 }
5710
4eb3f768
SN		 5711 /* re-verify the eeprom if we just had an EMP reset */
5712 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5713 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5714 i40e_verify_eeprom(pf);
5715 }
5716
e78ac4bf 5717 i40e_clear_pxe_mode(hw);
41c445ff
JB		 5718 ret = i40e_get_capabilities(pf);
5719 if (ret) {
5720 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5721 ret);
5722 goto end_core_reset;
5723 }
5724
41c445ff
JB		 5725 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5726 hw->func_caps.num_rx_qp,
5727 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5728 if (ret) {
5729 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5730 goto end_core_reset;
5731 }
5732 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5733 if (ret) {
5734 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5735 goto end_core_reset;
5736 }
5737
4e3b35b0
NP		 5738#ifdef CONFIG_I40E_DCB
5739 ret = i40e_init_pf_dcb(pf);
5740 if (ret) {
5741 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5742 goto end_core_reset;
5743 }
5744#endif /* CONFIG_I40E_DCB */
5745
41c445ff 5746 /* do basic switch setup */
bc7d338f 5747 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5748 if (ret)
5749 goto end_core_reset;
5750
5751 /* Rebuild the VSIs and VEBs that existed before reset.
5752 * They are still in our local switch element arrays, so only
5753 * need to rebuild the switch model in the HW.
5754 *
5755 * If there were VEBs but the reconstitution failed, we'll try
5756 * try to recover minimal use by getting the basic PF VSI working.
5757 */
5758 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5759 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5760 /* find the one VEB connected to the MAC, and find orphans */
5761 for (v = 0; v < I40E_MAX_VEB; v++) {
5762 if (!pf->veb[v])
5763 continue;
5764
5765 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5766 pf->veb[v]->uplink_seid == 0) {
5767 ret = i40e_reconstitute_veb(pf->veb[v]);
5768
5769 if (!ret)
5770 continue;
5771
5772 /* If Main VEB failed, we're in deep doodoo,
5773 * so give up rebuilding the switch and set up
5774 * for minimal rebuild of PF VSI.
5775 * If orphan failed, we'll report the error
5776 * but try to keep going.
5777 */
5778 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5779 dev_info(&pf->pdev->dev,
5780 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5781 ret);
5782 pf->vsi[pf->lan_vsi]->uplink_seid
5783 = pf->mac_seid;
5784 break;
5785 } else if (pf->veb[v]->uplink_seid == 0) {
5786 dev_info(&pf->pdev->dev,
5787 "rebuild of orphan VEB failed: %d\n",
5788 ret);
5789 }
5790 }
5791 }
5792 }
5793
5794 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 5795 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 5796 /* no VEB, so rebuild only the Main VSI */
5797 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5798 if (ret) {
5799 dev_info(&pf->pdev->dev,
5800 "rebuild of Main VSI failed: %d\n", ret);
5801 goto end_core_reset;
5802 }
5803 }
5804
5805 /* reinit the misc interrupt */
5806 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5807 ret = i40e_setup_misc_vector(pf);
5808
5809 /* restart the VSIs that were rebuilt and running before the reset */
5810 i40e_pf_unquiesce_all_vsi(pf);
5811
69f64b2b
MW		 5812 if (pf->num_alloc_vfs) {
5813 for (v = 0; v < pf->num_alloc_vfs; v++)
5814 i40e_reset_vf(&pf->vf[v], true);
5815 }
5816
41c445ff 5817 /* tell the firmware that we're starting */
44033fac 5818 i40e_send_version(pf);
41c445ff
JB		 5819
5820end_core_reset:
5821 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5822}
5823
f650a38b
ASJ		 5824/**
5825 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5826 * @pf: board private structure
5827 *
5828 * Close up the VFs and other things in prep for a Core Reset,
5829 * then get ready to rebuild the world.
5830 **/
5831static void i40e_handle_reset_warning(struct i40e_pf *pf)
5832{
23cfbe07
SN		 5833 i40e_prep_for_reset(pf);
5834 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5835}
5836
41c445ff
JB		 5837/**
5838 * i40e_handle_mdd_event
5839 * @pf: pointer to the pf structure
5840 *
5841 * Called from the MDD irq handler to identify possibly malicious vfs
5842 **/
5843static void i40e_handle_mdd_event(struct i40e_pf *pf)
5844{
5845 struct i40e_hw *hw = &pf->hw;
5846 bool mdd_detected = false;
df430b12 5847 bool pf_mdd_detected = false;
41c445ff
JB		 5848 struct i40e_vf *vf;
5849 u32 reg;
5850 int i;
5851
5852 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5853 return;
5854
5855 /* find what triggered the MDD event */
5856 reg = rd32(hw, I40E_GL_MDET_TX);
5857 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 5858 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
5859 I40E_GL_MDET_TX_PF_NUM_SHIFT;
5860 u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
5861 I40E_GL_MDET_TX_VF_NUM_SHIFT;
5862 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) >>
5863 I40E_GL_MDET_TX_EVENT_SHIFT;
5864 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
5865 I40E_GL_MDET_TX_QUEUE_SHIFT;
41c445ff 5866 dev_info(&pf->pdev->dev,
4c33f83a
ASJ		 5867 "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
5868 event, queue, pf_num, vf_num);
41c445ff
JB		 5869 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5870 mdd_detected = true;
5871 }
5872 reg = rd32(hw, I40E_GL_MDET_RX);
5873 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 5874 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
5875 I40E_GL_MDET_RX_FUNCTION_SHIFT;
5876 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) >>
5877 I40E_GL_MDET_RX_EVENT_SHIFT;
5878 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
5879 I40E_GL_MDET_RX_QUEUE_SHIFT;
41c445ff 5880 dev_info(&pf->pdev->dev,
f29eaa3d 5881 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5882 event, queue, func);
5883 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5884 mdd_detected = true;
5885 }
5886
df430b12
NP		 5887 if (mdd_detected) {
5888 reg = rd32(hw, I40E_PF_MDET_TX);
5889 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
5890 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
5891 dev_info(&pf->pdev->dev,
5892 "MDD TX event is for this function 0x%08x, requesting PF reset.\n",
5893 reg);
5894 pf_mdd_detected = true;
5895 }
5896 reg = rd32(hw, I40E_PF_MDET_RX);
5897 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
5898 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
5899 dev_info(&pf->pdev->dev,
5900 "MDD RX event is for this function 0x%08x, requesting PF reset.\n",
5901 reg);
5902 pf_mdd_detected = true;
5903 }
5904 /* Queue belongs to the PF, initiate a reset */
5905 if (pf_mdd_detected) {
5906 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5907 i40e_service_event_schedule(pf);
5908 }
5909 }
5910
41c445ff
JB		 5911 /* see if one of the VFs needs its hand slapped */
5912 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5913 vf = &(pf->vf[i]);
5914 reg = rd32(hw, I40E_VP_MDET_TX(i));
5915 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5916 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5917 vf->num_mdd_events++;
5918 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5919 }
5920
5921 reg = rd32(hw, I40E_VP_MDET_RX(i));
5922 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5923 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5924 vf->num_mdd_events++;
5925 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5926 }
5927
5928 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5929 dev_info(&pf->pdev->dev,
5930 "Too many MDD events on VF %d, disabled\n", i);
5931 dev_info(&pf->pdev->dev,
5932 "Use PF Control I/F to re-enable the VF\n");
5933 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5934 }
5935 }
5936
5937 /* re-enable mdd interrupt cause */
5938 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5939 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5940 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5941 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5942 i40e_flush(hw);
5943}
5944
a1c9a9d9
JK		 5945#ifdef CONFIG_I40E_VXLAN
5946/**
5947 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5948 * @pf: board private structure
5949 **/
5950static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5951{
a1c9a9d9
JK		 5952 struct i40e_hw *hw = &pf->hw;
5953 i40e_status ret;
5954 u8 filter_index;
5955 __be16 port;
5956 int i;
5957
5958 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5959 return;
5960
5961 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5962
5963 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5964 if (pf->pending_vxlan_bitmap & (1 << i)) {
5965 pf->pending_vxlan_bitmap &= ~(1 << i);
5966 port = pf->vxlan_ports[i];
5967 ret = port ?
5968 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5969 I40E_AQC_TUNNEL_TYPE_VXLAN,
5970 &filter_index, NULL)
5971 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5972
5973 if (ret) {
5974 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5975 port ? "adding" : "deleting",
5976 ntohs(port), port ? i : i);
5977
5978 pf->vxlan_ports[i] = 0;
5979 } else {
5980 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5981 port ? "Added" : "Deleted",
5982 ntohs(port), port ? i : filter_index);
5983 }
5984 }
5985 }
5986}
5987
5988#endif
41c445ff
JB		 5989/**
5990 * i40e_service_task - Run the driver's async subtasks
5991 * @work: pointer to work_struct containing our data
5992 **/
5993static void i40e_service_task(struct work_struct *work)
5994{
5995 struct i40e_pf *pf = container_of(work,
5996 struct i40e_pf,
5997 service_task);
5998 unsigned long start_time = jiffies;
5999
e57a2fea
SN		 6000 /* don't bother with service tasks if a reset is in progress */
6001 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6002 i40e_service_event_complete(pf);
6003 return;
6004 }
6005
41c445ff
JB		 6006 i40e_reset_subtask(pf);
6007 i40e_handle_mdd_event(pf);
6008 i40e_vc_process_vflr_event(pf);
6009 i40e_watchdog_subtask(pf);
6010 i40e_fdir_reinit_subtask(pf);
6011 i40e_check_hang_subtask(pf);
6012 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6013#ifdef CONFIG_I40E_VXLAN
6014 i40e_sync_vxlan_filters_subtask(pf);
6015#endif
41c445ff
JB		 6016 i40e_clean_adminq_subtask(pf);
6017
6018 i40e_service_event_complete(pf);
6019
6020 /* If the tasks have taken longer than one timer cycle or there
6021 * is more work to be done, reschedule the service task now
6022 * rather than wait for the timer to tick again.
6023 */
6024 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6025 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6026 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6027 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6028 i40e_service_event_schedule(pf);
6029}
6030
6031/**
6032 * i40e_service_timer - timer callback
6033 * @data: pointer to PF struct
6034 **/
6035static void i40e_service_timer(unsigned long data)
6036{
6037 struct i40e_pf *pf = (struct i40e_pf *)data;
6038
6039 mod_timer(&pf->service_timer,
6040 round_jiffies(jiffies + pf->service_timer_period));
6041 i40e_service_event_schedule(pf);
6042}
6043
6044/**
6045 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6046 * @vsi: the VSI being configured
6047 **/
6048static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6049{
6050 struct i40e_pf *pf = vsi->back;
6051
6052 switch (vsi->type) {
6053 case I40E_VSI_MAIN:
6054 vsi->alloc_queue_pairs = pf->num_lan_qps;
6055 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6056 I40E_REQ_DESCRIPTOR_MULTIPLE);
6057 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6058 vsi->num_q_vectors = pf->num_lan_msix;
6059 else
6060 vsi->num_q_vectors = 1;
6061
6062 break;
6063
6064 case I40E_VSI_FDIR:
6065 vsi->alloc_queue_pairs = 1;
6066 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6067 I40E_REQ_DESCRIPTOR_MULTIPLE);
6068 vsi->num_q_vectors = 1;
6069 break;
6070
6071 case I40E_VSI_VMDQ2:
6072 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6073 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6074 I40E_REQ_DESCRIPTOR_MULTIPLE);
6075 vsi->num_q_vectors = pf->num_vmdq_msix;
6076 break;
6077
6078 case I40E_VSI_SRIOV:
6079 vsi->alloc_queue_pairs = pf->num_vf_qps;
6080 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6081 I40E_REQ_DESCRIPTOR_MULTIPLE);
6082 break;
6083
6084 default:
6085 WARN_ON(1);
6086 return -ENODATA;
6087 }
6088
6089 return 0;
6090}
6091
f650a38b
ASJ		 6092/**
6093 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6094 * @type: VSI pointer
bc7d338f 6095 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6096 *
6097 * On error: returns error code (negative)
6098 * On success: returns 0
6099 **/
bc7d338f 6100static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6101{
6102 int size;
6103 int ret = 0;
6104
ac6c5e3d 6105 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6106 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6107 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6108 if (!vsi->tx_rings)
6109 return -ENOMEM;
f650a38b
ASJ		 6110 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6111
bc7d338f
ASJ		 6112 if (alloc_qvectors) {
6113 /* allocate memory for q_vector pointers */
6114 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
6115 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6116 if (!vsi->q_vectors) {
6117 ret = -ENOMEM;
6118 goto err_vectors;
6119 }
f650a38b
ASJ		 6120 }
6121 return ret;
6122
6123err_vectors:
6124 kfree(vsi->tx_rings);
6125 return ret;
6126}
6127
41c445ff
JB		 6128/**
6129 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6130 * @pf: board private structure
6131 * @type: type of VSI
6132 *
6133 * On error: returns error code (negative)
6134 * On success: returns vsi index in PF (positive)
6135 **/
6136static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6137{
6138 int ret = -ENODEV;
6139 struct i40e_vsi *vsi;
6140 int vsi_idx;
6141 int i;
6142
6143 /* Need to protect the allocation of the VSIs at the PF level */
6144 mutex_lock(&pf->switch_mutex);
6145
6146 /* VSI list may be fragmented if VSI creation/destruction has
6147 * been happening. We can afford to do a quick scan to look
6148 * for any free VSIs in the list.
6149 *
6150 * find next empty vsi slot, looping back around if necessary
6151 */
6152 i = pf->next_vsi;
505682cd 6153 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6154 i++;
505682cd 6155 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6156 i = 0;
6157 while (i < pf->next_vsi && pf->vsi[i])
6158 i++;
6159 }
6160
505682cd 6161 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6162 vsi_idx = i; /* Found one! */
6163 } else {
6164 ret = -ENODEV;
493fb300 6165 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6166 }
6167 pf->next_vsi = ++i;
6168
6169 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6170 if (!vsi) {
6171 ret = -ENOMEM;
493fb300 6172 goto unlock_pf;
41c445ff
JB		 6173 }
6174 vsi->type = type;
6175 vsi->back = pf;
6176 set_bit(__I40E_DOWN, &vsi->state);
6177 vsi->flags = 0;
6178 vsi->idx = vsi_idx;
6179 vsi->rx_itr_setting = pf->rx_itr_default;
6180 vsi->tx_itr_setting = pf->tx_itr_default;
6181 vsi->netdev_registered = false;
6182 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6183 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6184 vsi->irqs_ready = false;
41c445ff 6185
9f65e15b
AD		 6186 ret = i40e_set_num_rings_in_vsi(vsi);
6187 if (ret)
6188 goto err_rings;
6189
bc7d338f 6190 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6191 if (ret)
9f65e15b 6192 goto err_rings;
493fb300 6193
41c445ff
JB		 6194 /* Setup default MSIX irq handler for VSI */
6195 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6196
6197 pf->vsi[vsi_idx] = vsi;
6198 ret = vsi_idx;
493fb300
AD		 6199 goto unlock_pf;
6200
9f65e15b 6201err_rings:
493fb300
AD		 6202 pf->next_vsi = i - 1;
6203 kfree(vsi);
6204unlock_pf:
41c445ff
JB		 6205 mutex_unlock(&pf->switch_mutex);
6206 return ret;
6207}
6208
f650a38b
ASJ		 6209/**
6210 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6211 * @type: VSI pointer
bc7d338f 6212 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6213 *
6214 * On error: returns error code (negative)
6215 * On success: returns 0
6216 **/
bc7d338f 6217static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6218{
6219 /* free the ring and vector containers */
bc7d338f
ASJ		 6220 if (free_qvectors) {
6221 kfree(vsi->q_vectors);
6222 vsi->q_vectors = NULL;
6223 }
f650a38b
ASJ		 6224 kfree(vsi->tx_rings);
6225 vsi->tx_rings = NULL;
6226 vsi->rx_rings = NULL;
6227}
6228
41c445ff
JB		 6229/**
6230 * i40e_vsi_clear - Deallocate the VSI provided
6231 * @vsi: the VSI being un-configured
6232 **/
6233static int i40e_vsi_clear(struct i40e_vsi *vsi)
6234{
6235 struct i40e_pf *pf;
6236
6237 if (!vsi)
6238 return 0;
6239
6240 if (!vsi->back)
6241 goto free_vsi;
6242 pf = vsi->back;
6243
6244 mutex_lock(&pf->switch_mutex);
6245 if (!pf->vsi[vsi->idx]) {
6246 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6247 vsi->idx, vsi->idx, vsi, vsi->type);
6248 goto unlock_vsi;
6249 }
6250
6251 if (pf->vsi[vsi->idx] != vsi) {
6252 dev_err(&pf->pdev->dev,
6253 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6254 pf->vsi[vsi->idx]->idx,
6255 pf->vsi[vsi->idx],
6256 pf->vsi[vsi->idx]->type,
6257 vsi->idx, vsi, vsi->type);
6258 goto unlock_vsi;
6259 }
6260
6261 /* updates the pf for this cleared vsi */
6262 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6263 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6264
bc7d338f 6265 i40e_vsi_free_arrays(vsi, true);
493fb300 6266
41c445ff
JB		 6267 pf->vsi[vsi->idx] = NULL;
6268 if (vsi->idx < pf->next_vsi)
6269 pf->next_vsi = vsi->idx;
6270
6271unlock_vsi:
6272 mutex_unlock(&pf->switch_mutex);
6273free_vsi:
6274 kfree(vsi);
6275
6276 return 0;
6277}
6278
9f65e15b
AD		 6279/**
6280 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6281 * @vsi: the VSI being cleaned
6282 **/
be1d5eea 6283static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6284{
6285 int i;
6286
8e9dca53 6287 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6288 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6289 kfree_rcu(vsi->tx_rings[i], rcu);
6290 vsi->tx_rings[i] = NULL;
6291 vsi->rx_rings[i] = NULL;
6292 }
be1d5eea 6293 }
9f65e15b
AD		 6294}
6295
41c445ff
JB		 6296/**
6297 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6298 * @vsi: the VSI being configured
6299 **/
6300static int i40e_alloc_rings(struct i40e_vsi *vsi)
6301{
e7046ee1 6302 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6303 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6304 int i;
6305
41c445ff 6306 /* Set basic values in the rings to be used later during open() */
d7397644 6307 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6308 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6309 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6310 if (!tx_ring)
6311 goto err_out;
41c445ff
JB		 6312
6313 tx_ring->queue_index = i;
6314 tx_ring->reg_idx = vsi->base_queue + i;
6315 tx_ring->ring_active = false;
6316 tx_ring->vsi = vsi;
6317 tx_ring->netdev = vsi->netdev;
6318 tx_ring->dev = &pf->pdev->dev;
6319 tx_ring->count = vsi->num_desc;
6320 tx_ring->size = 0;
6321 tx_ring->dcb_tc = 0;
9f65e15b 6322 vsi->tx_rings[i] = tx_ring;
41c445ff 6323
9f65e15b 6324 rx_ring = &tx_ring[1];
41c445ff
JB		 6325 rx_ring->queue_index = i;
6326 rx_ring->reg_idx = vsi->base_queue + i;
6327 rx_ring->ring_active = false;
6328 rx_ring->vsi = vsi;
6329 rx_ring->netdev = vsi->netdev;
6330 rx_ring->dev = &pf->pdev->dev;
6331 rx_ring->count = vsi->num_desc;
6332 rx_ring->size = 0;
6333 rx_ring->dcb_tc = 0;
6334 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6335 set_ring_16byte_desc_enabled(rx_ring);
6336 else
6337 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6338 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6339 }
6340
6341 return 0;
9f65e15b
AD		 6342
6343err_out:
6344 i40e_vsi_clear_rings(vsi);
6345 return -ENOMEM;
41c445ff
JB		 6346}
6347
6348/**
6349 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6350 * @pf: board private structure
6351 * @vectors: the number of MSI-X vectors to request
6352 *
6353 * Returns the number of vectors reserved, or error
6354 **/
6355static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6356{
7b37f376
AG		 6357 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6358 I40E_MIN_MSIX, vectors);
6359 if (vectors < 0) {
41c445ff 6360 dev_info(&pf->pdev->dev,
7b37f376 6361 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6362 vectors = 0;
6363 }
6364
6365 return vectors;
6366}
6367
6368/**
6369 * i40e_init_msix - Setup the MSIX capability
6370 * @pf: board private structure
6371 *
6372 * Work with the OS to set up the MSIX vectors needed.
6373 *
6374 * Returns 0 on success, negative on failure
6375 **/
6376static int i40e_init_msix(struct i40e_pf *pf)
6377{
6378 i40e_status err = 0;
6379 struct i40e_hw *hw = &pf->hw;
6380 int v_budget, i;
6381 int vec;
6382
6383 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6384 return -ENODEV;
6385
6386 /* The number of vectors we'll request will be comprised of:
6387 * - Add 1 for "other" cause for Admin Queue events, etc.
6388 * - The number of LAN queue pairs
f8ff1464
ASJ		 6389 * - Queues being used for RSS.
6390 * We don't need as many as max_rss_size vectors.
6391 * use rss_size instead in the calculation since that
6392 * is governed by number of cpus in the system.
6393 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6394 * - The number of VMDq pairs
6395 * Once we count this up, try the request.
6396 *
6397 * If we can't get what we want, we'll simplify to nearly nothing
6398 * and try again. If that still fails, we punt.
6399 */
f8ff1464 6400 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6401 pf->num_vmdq_msix = pf->num_vmdq_qps;
6402 v_budget = 1 + pf->num_lan_msix;
6403 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6404 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6405 v_budget++;
6406
6407 /* Scale down if necessary, and the rings will share vectors */
6408 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6409
6410 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6411 GFP_KERNEL);
6412 if (!pf->msix_entries)
6413 return -ENOMEM;
6414
6415 for (i = 0; i < v_budget; i++)
6416 pf->msix_entries[i].entry = i;
6417 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6418
6419 if (vec != v_budget) {
6420 /* If we have limited resources, we will start with no vectors
6421 * for the special features and then allocate vectors to some
6422 * of these features based on the policy and at the end disable
6423 * the features that did not get any vectors.
6424 */
6425 pf->num_vmdq_msix = 0;
6426 }
6427
41c445ff
JB		 6428 if (vec < I40E_MIN_MSIX) {
6429 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6430 kfree(pf->msix_entries);
6431 pf->msix_entries = NULL;
6432 return -ENODEV;
6433
6434 } else if (vec == I40E_MIN_MSIX) {
6435 /* Adjust for minimal MSIX use */
41c445ff
JB		 6436 pf->num_vmdq_vsis = 0;
6437 pf->num_vmdq_qps = 0;
41c445ff
JB		 6438 pf->num_lan_qps = 1;
6439 pf->num_lan_msix = 1;
6440
6441 } else if (vec != v_budget) {
a34977ba
ASJ		 6442 /* reserve the misc vector */
6443 vec--;
6444
41c445ff
JB		 6445 /* Scale vector usage down */
6446 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6447 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6448
6449 /* partition out the remaining vectors */
6450 switch (vec) {
6451 case 2:
41c445ff
JB		 6452 pf->num_lan_msix = 1;
6453 break;
6454 case 3:
41c445ff
JB		 6455 pf->num_lan_msix = 2;
6456 break;
6457 default:
6458 pf->num_lan_msix = min_t(int, (vec / 2),
6459 pf->num_lan_qps);
6460 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6461 I40E_DEFAULT_NUM_VMDQ_VSI);
6462 break;
6463 }
6464 }
6465
a34977ba
ASJ		 6466 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6467 (pf->num_vmdq_msix == 0)) {
6468 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6469 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6470 }
41c445ff
JB		 6471 return err;
6472}
6473
493fb300 6474/**
90e04070 6475 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6476 * @vsi: the VSI being configured
6477 * @v_idx: index of the vector in the vsi struct
6478 *
6479 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6480 **/
90e04070 6481static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6482{
6483 struct i40e_q_vector *q_vector;
6484
6485 /* allocate q_vector */
6486 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6487 if (!q_vector)
6488 return -ENOMEM;
6489
6490 q_vector->vsi = vsi;
6491 q_vector->v_idx = v_idx;
6492 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6493 if (vsi->netdev)
6494 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6495 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6496
cd0b6fa6
AD		 6497 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6498 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6499
493fb300
AD		 6500 /* tie q_vector and vsi together */
6501 vsi->q_vectors[v_idx] = q_vector;
6502
6503 return 0;
6504}
6505
41c445ff 6506/**
90e04070 6507 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6508 * @vsi: the VSI being configured
6509 *
6510 * We allocate one q_vector per queue interrupt. If allocation fails we
6511 * return -ENOMEM.
6512 **/
90e04070 6513static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6514{
6515 struct i40e_pf *pf = vsi->back;
6516 int v_idx, num_q_vectors;
493fb300 6517 int err;
41c445ff
JB		 6518
6519 /* if not MSIX, give the one vector only to the LAN VSI */
6520 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6521 num_q_vectors = vsi->num_q_vectors;
6522 else if (vsi == pf->vsi[pf->lan_vsi])
6523 num_q_vectors = 1;
6524 else
6525 return -EINVAL;
6526
41c445ff 6527 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6528 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6529 if (err)
6530 goto err_out;
41c445ff
JB		 6531 }
6532
6533 return 0;
493fb300
AD		 6534
6535err_out:
6536 while (v_idx--)
6537 i40e_free_q_vector(vsi, v_idx);
6538
6539 return err;
41c445ff
JB		 6540}
6541
6542/**
6543 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6544 * @pf: board private structure to initialize
6545 **/
6546static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6547{
6548 int err = 0;
6549
6550 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6551 err = i40e_init_msix(pf);
6552 if (err) {
60ea5f83
JB		 6553 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6554 I40E_FLAG_RSS_ENABLED |
4d9b6043 6555 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6556 I40E_FLAG_SRIOV_ENABLED |
6557 I40E_FLAG_FD_SB_ENABLED |
6558 I40E_FLAG_FD_ATR_ENABLED |
6559 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6560
6561 /* rework the queue expectations without MSIX */
6562 i40e_determine_queue_usage(pf);
6563 }
6564 }
6565
6566 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6567 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6568 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6569 err = pci_enable_msi(pf->pdev);
6570 if (err) {
958a3e3b 6571 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6572 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6573 }
6574 }
6575
958a3e3b 6576 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6577 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6578
41c445ff
JB		 6579 /* track first vector for misc interrupts */
6580 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6581}
6582
6583/**
6584 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6585 * @pf: board private structure
6586 *
6587 * This sets up the handler for MSIX 0, which is used to manage the
6588 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6589 * when in MSI or Legacy interrupt mode.
6590 **/
6591static int i40e_setup_misc_vector(struct i40e_pf *pf)
6592{
6593 struct i40e_hw *hw = &pf->hw;
6594 int err = 0;
6595
6596 /* Only request the irq if this is the first time through, and
6597 * not when we're rebuilding after a Reset
6598 */
6599 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6600 err = request_irq(pf->msix_entries[0].vector,
6601 i40e_intr, 0, pf->misc_int_name, pf);
6602 if (err) {
6603 dev_info(&pf->pdev->dev,
77fa28be
CS		 6604 "request_irq for %s failed: %d\n",
6605 pf->misc_int_name, err);
41c445ff
JB		 6606 return -EFAULT;
6607 }
6608 }
6609
6610 i40e_enable_misc_int_causes(hw);
6611
6612 /* associate no queues to the misc vector */
6613 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6614 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6615
6616 i40e_flush(hw);
6617
6618 i40e_irq_dynamic_enable_icr0(pf);
6619
6620 return err;
6621}
6622
6623/**
6624 * i40e_config_rss - Prepare for RSS if used
6625 * @pf: board private structure
6626 **/
6627static int i40e_config_rss(struct i40e_pf *pf)
6628{
41c445ff
JB		 6629 /* Set of random keys generated using kernel random number generator */
6630 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6631 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6632 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6633 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6634 struct i40e_hw *hw = &pf->hw;
6635 u32 lut = 0;
6636 int i, j;
6637 u64 hena;
e157ea30 6638 u32 reg_val;
41c445ff
JB		 6639
6640 /* Fill out hash function seed */
6641 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6642 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6643
6644 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6645 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6646 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6647 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6648 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6649 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6650
e157ea30
CW		 6651 /* Check capability and Set table size and register per hw expectation*/
6652 reg_val = rd32(hw, I40E_PFQF_CTL_0);
6653 if (hw->func_caps.rss_table_size == 512) {
6654 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6655 pf->rss_table_size = 512;
6656 } else {
6657 pf->rss_table_size = 128;
6658 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6659 }
6660 wr32(hw, I40E_PFQF_CTL_0, reg_val);
6661
41c445ff 6662 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 6663 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 6664
6665 /* The assumption is that lan qp count will be the highest
6666 * qp count for any PF VSI that needs RSS.
6667 * If multiple VSIs need RSS support, all the qp counts
6668 * for those VSIs should be a power of 2 for RSS to work.
6669 * If LAN VSI is the only consumer for RSS then this requirement
6670 * is not necessary.
6671 */
6672 if (j == pf->rss_size)
6673 j = 0;
6674 /* lut = 4-byte sliding window of 4 lut entries */
6675 lut = (lut << 8) | (j &
6676 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6677 /* On i = 3, we have 4 entries in lut; write to the register */
6678 if ((i & 3) == 3)
6679 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6680 }
6681 i40e_flush(hw);
6682
6683 return 0;
6684}
6685
f8ff1464
ASJ		 6686/**
6687 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6688 * @pf: board private structure
6689 * @queue_count: the requested queue count for rss.
6690 *
6691 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6692 * count which may be different from the requested queue count.
6693 **/
6694int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6695{
6696 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6697 return 0;
6698
6699 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 6700
6701 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6702 i40e_prep_for_reset(pf);
6703
f8ff1464
ASJ		 6704 pf->rss_size = queue_count;
6705
6706 i40e_reset_and_rebuild(pf, true);
6707 i40e_config_rss(pf);
6708 }
6709 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6710 return pf->rss_size;
6711}
6712
41c445ff
JB		 6713/**
6714 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6715 * @pf: board private structure to initialize
6716 *
6717 * i40e_sw_init initializes the Adapter private data structure.
6718 * Fields are initialized based on PCI device information and
6719 * OS network device settings (MTU size).
6720 **/
6721static int i40e_sw_init(struct i40e_pf *pf)
6722{
6723 int err = 0;
6724 int size;
6725
6726 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6727 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6728 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6729 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6730 if (I40E_DEBUG_USER & debug)
6731 pf->hw.debug_mask = debug;
6732 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6733 I40E_DEFAULT_MSG_ENABLE);
6734 }
6735
6736 /* Set default capability flags */
6737 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6738 I40E_FLAG_MSI_ENABLED |
6739 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6740 I40E_FLAG_RX_1BUF_ENABLED;
6741
ca99eb99
MW		 6742 /* Set default ITR */
6743 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6744 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6745
7134f9ce
JB		 6746 /* Depending on PF configurations, it is possible that the RSS
6747 * maximum might end up larger than the available queues
6748 */
41c445ff 6749 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6750 pf->rss_size_max = min_t(int, pf->rss_size_max,
6751 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6752 if (pf->hw.func_caps.rss) {
6753 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6754 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 6755 } else {
6756 pf->rss_size = 1;
6757 }
6758
2050bc65
CS		 6759 /* MFP mode enabled */
6760 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6761 pf->flags |= I40E_FLAG_MFP_ENABLED;
6762 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6763 }
6764
cbf61325
ASJ		 6765 /* FW/NVM is not yet fixed in this regard */
6766 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6767 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6768 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6769 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 6770 /* Setup a counter for fd_atr per pf */
6771 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 6772 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6773 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 6774 /* Setup a counter for fd_sb per pf */
6775 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 6776 } else {
6777 dev_info(&pf->pdev->dev,
0b67584f 6778 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6779 }
cbf61325
ASJ		 6780 pf->fdir_pf_filter_count =
6781 pf->hw.func_caps.fd_filters_guaranteed;
6782 pf->hw.fdir_shared_filter_count =
6783 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6784 }
6785
6786 if (pf->hw.func_caps.vmdq) {
6787 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6788 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6789 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6790 }
6791
41c445ff
JB		 6792#ifdef CONFIG_PCI_IOV
6793 if (pf->hw.func_caps.num_vfs) {
6794 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6795 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6796 pf->num_req_vfs = min_t(int,
6797 pf->hw.func_caps.num_vfs,
6798 I40E_MAX_VF_COUNT);
6799 }
6800#endif /* CONFIG_PCI_IOV */
6801 pf->eeprom_version = 0xDEAD;
6802 pf->lan_veb = I40E_NO_VEB;
6803 pf->lan_vsi = I40E_NO_VSI;
6804
6805 /* set up queue assignment tracking */
6806 size = sizeof(struct i40e_lump_tracking)
6807 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6808 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6809 if (!pf->qp_pile) {
6810 err = -ENOMEM;
6811 goto sw_init_done;
6812 }
6813 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6814 pf->qp_pile->search_hint = 0;
6815
6816 /* set up vector assignment tracking */
6817 size = sizeof(struct i40e_lump_tracking)
6818 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6819 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6820 if (!pf->irq_pile) {
6821 kfree(pf->qp_pile);
6822 err = -ENOMEM;
6823 goto sw_init_done;
6824 }
6825 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6826 pf->irq_pile->search_hint = 0;
6827
6828 mutex_init(&pf->switch_mutex);
6829
6830sw_init_done:
6831 return err;
6832}
6833
7c3c288b
ASJ		 6834/**
6835 * i40e_set_ntuple - set the ntuple feature flag and take action
6836 * @pf: board private structure to initialize
6837 * @features: the feature set that the stack is suggesting
6838 *
6839 * returns a bool to indicate if reset needs to happen
6840 **/
6841bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6842{
6843 bool need_reset = false;
6844
6845 /* Check if Flow Director n-tuple support was enabled or disabled. If
6846 * the state changed, we need to reset.
6847 */
6848 if (features & NETIF_F_NTUPLE) {
6849 /* Enable filters and mark for reset */
6850 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6851 need_reset = true;
6852 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6853 } else {
6854 /* turn off filters, mark for reset and clear SW filter list */
6855 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6856 need_reset = true;
6857 i40e_fdir_filter_exit(pf);
6858 }
6859 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6860 /* if ATR was disabled it can be re-enabled. */
6861 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6862 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6863 }
6864 return need_reset;
6865}
6866
41c445ff
JB		 6867/**
6868 * i40e_set_features - set the netdev feature flags
6869 * @netdev: ptr to the netdev being adjusted
6870 * @features: the feature set that the stack is suggesting
6871 **/
6872static int i40e_set_features(struct net_device *netdev,
6873 netdev_features_t features)
6874{
6875 struct i40e_netdev_priv *np = netdev_priv(netdev);
6876 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6877 struct i40e_pf *pf = vsi->back;
6878 bool need_reset;
41c445ff
JB		 6879
6880 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6881 i40e_vlan_stripping_enable(vsi);
6882 else
6883 i40e_vlan_stripping_disable(vsi);
6884
7c3c288b
ASJ		 6885 need_reset = i40e_set_ntuple(pf, features);
6886
6887 if (need_reset)
6888 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6889
41c445ff
JB		 6890 return 0;
6891}
6892
a1c9a9d9
JK		 6893#ifdef CONFIG_I40E_VXLAN
6894/**
6895 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6896 * @pf: board private structure
6897 * @port: The UDP port to look up
6898 *
6899 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6900 **/
6901static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6902{
6903 u8 i;
6904
6905 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6906 if (pf->vxlan_ports[i] == port)
6907 return i;
6908 }
6909
6910 return i;
6911}
6912
6913/**
6914 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6915 * @netdev: This physical port's netdev
6916 * @sa_family: Socket Family that VXLAN is notifying us about
6917 * @port: New UDP port number that VXLAN started listening to
6918 **/
6919static void i40e_add_vxlan_port(struct net_device *netdev,
6920 sa_family_t sa_family, __be16 port)
6921{
6922 struct i40e_netdev_priv *np = netdev_priv(netdev);
6923 struct i40e_vsi *vsi = np->vsi;
6924 struct i40e_pf *pf = vsi->back;
6925 u8 next_idx;
6926 u8 idx;
6927
6928 if (sa_family == AF_INET6)
6929 return;
6930
6931 idx = i40e_get_vxlan_port_idx(pf, port);
6932
6933 /* Check if port already exists */
6934 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6935 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6936 return;
6937 }
6938
6939 /* Now check if there is space to add the new port */
6940 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6941
6942 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6943 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6944 ntohs(port));
6945 return;
6946 }
6947
6948 /* New port: add it and mark its index in the bitmap */
6949 pf->vxlan_ports[next_idx] = port;
6950 pf->pending_vxlan_bitmap |= (1 << next_idx);
6951
6952 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6953}
6954
6955/**
6956 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6957 * @netdev: This physical port's netdev
6958 * @sa_family: Socket Family that VXLAN is notifying us about
6959 * @port: UDP port number that VXLAN stopped listening to
6960 **/
6961static void i40e_del_vxlan_port(struct net_device *netdev,
6962 sa_family_t sa_family, __be16 port)
6963{
6964 struct i40e_netdev_priv *np = netdev_priv(netdev);
6965 struct i40e_vsi *vsi = np->vsi;
6966 struct i40e_pf *pf = vsi->back;
6967 u8 idx;
6968
6969 if (sa_family == AF_INET6)
6970 return;
6971
6972 idx = i40e_get_vxlan_port_idx(pf, port);
6973
6974 /* Check if port already exists */
6975 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6976 /* if port exists, set it to 0 (mark for deletion)
6977 * and make it pending
6978 */
6979 pf->vxlan_ports[idx] = 0;
6980
6981 pf->pending_vxlan_bitmap |= (1 << idx);
6982
6983 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6984 } else {
6985 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6986 ntohs(port));
6987 }
6988}
6989
6990#endif
4ba0dea5
GR		 6991#ifdef HAVE_FDB_OPS
6992#ifdef USE_CONST_DEV_UC_CHAR
6993static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6994 struct net_device *dev,
6995 const unsigned char *addr,
6996 u16 flags)
6997#else
6998static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6999 struct net_device *dev,
7000 unsigned char *addr,
7001 u16 flags)
7002#endif
7003{
7004 struct i40e_netdev_priv *np = netdev_priv(dev);
7005 struct i40e_pf *pf = np->vsi->back;
7006 int err = 0;
7007
7008 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7009 return -EOPNOTSUPP;
7010
7011 /* Hardware does not support aging addresses so if a
7012 * ndm_state is given only allow permanent addresses
7013 */
7014 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7015 netdev_info(dev, "FDB only supports static addresses\n");
7016 return -EINVAL;
7017 }
7018
7019 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7020 err = dev_uc_add_excl(dev, addr);
7021 else if (is_multicast_ether_addr(addr))
7022 err = dev_mc_add_excl(dev, addr);
7023 else
7024 err = -EINVAL;
7025
7026 /* Only return duplicate errors if NLM_F_EXCL is set */
7027 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7028 err = 0;
7029
7030 return err;
7031}
7032
7033#ifndef USE_DEFAULT_FDB_DEL_DUMP
7034#ifdef USE_CONST_DEV_UC_CHAR
7035static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7036 struct net_device *dev,
7037 const unsigned char *addr)
7038#else
7039static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7040 struct net_device *dev,
7041 unsigned char *addr)
7042#endif
7043{
7044 struct i40e_netdev_priv *np = netdev_priv(dev);
7045 struct i40e_pf *pf = np->vsi->back;
7046 int err = -EOPNOTSUPP;
7047
7048 if (ndm->ndm_state & NUD_PERMANENT) {
7049 netdev_info(dev, "FDB only supports static addresses\n");
7050 return -EINVAL;
7051 }
7052
7053 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7054 if (is_unicast_ether_addr(addr))
7055 err = dev_uc_del(dev, addr);
7056 else if (is_multicast_ether_addr(addr))
7057 err = dev_mc_del(dev, addr);
7058 else
7059 err = -EINVAL;
7060 }
7061
7062 return err;
7063}
7064
7065static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7066 struct netlink_callback *cb,
7067 struct net_device *dev,
7068 int idx)
7069{
7070 struct i40e_netdev_priv *np = netdev_priv(dev);
7071 struct i40e_pf *pf = np->vsi->back;
7072
7073 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
7074 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7075
7076 return idx;
7077}
7078
7079#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7080#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7081static const struct net_device_ops i40e_netdev_ops = {
7082 .ndo_open = i40e_open,
7083 .ndo_stop = i40e_close,
7084 .ndo_start_xmit = i40e_lan_xmit_frame,
7085 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7086 .ndo_set_rx_mode = i40e_set_rx_mode,
7087 .ndo_validate_addr = eth_validate_addr,
7088 .ndo_set_mac_address = i40e_set_mac,
7089 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7090 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7091 .ndo_tx_timeout = i40e_tx_timeout,
7092 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7093 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7094#ifdef CONFIG_NET_POLL_CONTROLLER
7095 .ndo_poll_controller = i40e_netpoll,
7096#endif
7097 .ndo_setup_tc = i40e_setup_tc,
7098 .ndo_set_features = i40e_set_features,
7099 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7100 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7101 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7102 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7103 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
c674d125 7104 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofck,
a1c9a9d9
JK		 7105#ifdef CONFIG_I40E_VXLAN
7106 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7107 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7108#endif
4ba0dea5
GR		 7109#ifdef HAVE_FDB_OPS
7110 .ndo_fdb_add = i40e_ndo_fdb_add,
7111#ifndef USE_DEFAULT_FDB_DEL_DUMP
7112 .ndo_fdb_del = i40e_ndo_fdb_del,
7113 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7114#endif
7115#endif
41c445ff
JB		 7116};
7117
7118/**
7119 * i40e_config_netdev - Setup the netdev flags
7120 * @vsi: the VSI being configured
7121 *
7122 * Returns 0 on success, negative value on failure
7123 **/
7124static int i40e_config_netdev(struct i40e_vsi *vsi)
7125{
1a10370a 7126 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7127 struct i40e_pf *pf = vsi->back;
7128 struct i40e_hw *hw = &pf->hw;
7129 struct i40e_netdev_priv *np;
7130 struct net_device *netdev;
7131 u8 mac_addr[ETH_ALEN];
7132 int etherdev_size;
7133
7134 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7135 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7136 if (!netdev)
7137 return -ENOMEM;
7138
7139 vsi->netdev = netdev;
7140 np = netdev_priv(netdev);
7141 np->vsi = vsi;
7142
d70e941b 7143 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7144 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7145 NETIF_F_TSO;
41c445ff
JB		 7146
7147 netdev->features = NETIF_F_SG |
7148 NETIF_F_IP_CSUM |
7149 NETIF_F_SCTP_CSUM |
7150 NETIF_F_HIGHDMA |
7151 NETIF_F_GSO_UDP_TUNNEL |
7152 NETIF_F_HW_VLAN_CTAG_TX |
7153 NETIF_F_HW_VLAN_CTAG_RX |
7154 NETIF_F_HW_VLAN_CTAG_FILTER |
7155 NETIF_F_IPV6_CSUM |
7156 NETIF_F_TSO |
059dab69 7157 NETIF_F_TSO_ECN |
41c445ff
JB		 7158 NETIF_F_TSO6 |
7159 NETIF_F_RXCSUM |
7160 NETIF_F_RXHASH |
7161 0;
7162
2e86a0b6
ASJ		 7163 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7164 netdev->features |= NETIF_F_NTUPLE;
7165
41c445ff
JB		 7166 /* copy netdev features into list of user selectable features */
7167 netdev->hw_features |= netdev->features;
7168
7169 if (vsi->type == I40E_VSI_MAIN) {
7170 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7171 ether_addr_copy(mac_addr, hw->mac.perm_addr);
8c27d42e
GR		 7172 /* The following two steps are necessary to prevent reception
7173 * of tagged packets - by default the NVM loads a MAC-VLAN
7174 * filter that will accept any tagged packet. This is to
7175 * prevent that during normal operations until a specific
7176 * VLAN tag filter has been set.
7177 */
7178 i40e_rm_default_mac_filter(vsi, mac_addr);
7179 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true);
41c445ff
JB		 7180 } else {
7181 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7182 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7183 pf->vsi[pf->lan_vsi]->netdev->name);
7184 random_ether_addr(mac_addr);
7185 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7186 }
1a10370a 7187 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7188
9a173901
GR		 7189 ether_addr_copy(netdev->dev_addr, mac_addr);
7190 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7191 /* vlan gets same features (except vlan offload)
7192 * after any tweaks for specific VSI types
7193 */
7194 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7195 NETIF_F_HW_VLAN_CTAG_RX |
7196 NETIF_F_HW_VLAN_CTAG_FILTER);
7197 netdev->priv_flags |= IFF_UNICAST_FLT;
7198 netdev->priv_flags |= IFF_SUPP_NOFCS;
7199 /* Setup netdev TC information */
7200 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7201
7202 netdev->netdev_ops = &i40e_netdev_ops;
7203 netdev->watchdog_timeo = 5 * HZ;
7204 i40e_set_ethtool_ops(netdev);
7205
7206 return 0;
7207}
7208
7209/**
7210 * i40e_vsi_delete - Delete a VSI from the switch
7211 * @vsi: the VSI being removed
7212 *
7213 * Returns 0 on success, negative value on failure
7214 **/
7215static void i40e_vsi_delete(struct i40e_vsi *vsi)
7216{
7217 /* remove default VSI is not allowed */
7218 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7219 return;
7220
41c445ff 7221 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7222}
7223
7224/**
7225 * i40e_add_vsi - Add a VSI to the switch
7226 * @vsi: the VSI being configured
7227 *
7228 * This initializes a VSI context depending on the VSI type to be added and
7229 * passes it down to the add_vsi aq command.
7230 **/
7231static int i40e_add_vsi(struct i40e_vsi *vsi)
7232{
7233 int ret = -ENODEV;
7234 struct i40e_mac_filter *f, *ftmp;
7235 struct i40e_pf *pf = vsi->back;
7236 struct i40e_hw *hw = &pf->hw;
7237 struct i40e_vsi_context ctxt;
7238 u8 enabled_tc = 0x1; /* TC0 enabled */
7239 int f_count = 0;
7240
7241 memset(&ctxt, 0, sizeof(ctxt));
7242 switch (vsi->type) {
7243 case I40E_VSI_MAIN:
7244 /* The PF's main VSI is already setup as part of the
7245 * device initialization, so we'll not bother with
7246 * the add_vsi call, but we will retrieve the current
7247 * VSI context.
7248 */
7249 ctxt.seid = pf->main_vsi_seid;
7250 ctxt.pf_num = pf->hw.pf_id;
7251 ctxt.vf_num = 0;
7252 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7253 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7254 if (ret) {
7255 dev_info(&pf->pdev->dev,
7256 "couldn't get pf vsi config, err %d, aq_err %d\n",
7257 ret, pf->hw.aq.asq_last_status);
7258 return -ENOENT;
7259 }
7260 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7261 vsi->info.valid_sections = 0;
7262
7263 vsi->seid = ctxt.seid;
7264 vsi->id = ctxt.vsi_number;
7265
7266 enabled_tc = i40e_pf_get_tc_map(pf);
7267
7268 /* MFP mode setup queue map and update VSI */
7269 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7270 memset(&ctxt, 0, sizeof(ctxt));
7271 ctxt.seid = pf->main_vsi_seid;
7272 ctxt.pf_num = pf->hw.pf_id;
7273 ctxt.vf_num = 0;
7274 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7275 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7276 if (ret) {
7277 dev_info(&pf->pdev->dev,
7278 "update vsi failed, aq_err=%d\n",
7279 pf->hw.aq.asq_last_status);
7280 ret = -ENOENT;
7281 goto err;
7282 }
7283 /* update the local VSI info queue map */
7284 i40e_vsi_update_queue_map(vsi, &ctxt);
7285 vsi->info.valid_sections = 0;
7286 } else {
7287 /* Default/Main VSI is only enabled for TC0
7288 * reconfigure it to enable all TCs that are
7289 * available on the port in SFP mode.
7290 */
7291 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7292 if (ret) {
7293 dev_info(&pf->pdev->dev,
7294 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7295 enabled_tc, ret,
7296 pf->hw.aq.asq_last_status);
7297 ret = -ENOENT;
7298 }
7299 }
7300 break;
7301
7302 case I40E_VSI_FDIR:
cbf61325
ASJ		 7303 ctxt.pf_num = hw->pf_id;
7304 ctxt.vf_num = 0;
7305 ctxt.uplink_seid = vsi->uplink_seid;
7306 ctxt.connection_type = 0x1; /* regular data port */
7307 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7308 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7309 break;
7310
7311 case I40E_VSI_VMDQ2:
7312 ctxt.pf_num = hw->pf_id;
7313 ctxt.vf_num = 0;
7314 ctxt.uplink_seid = vsi->uplink_seid;
7315 ctxt.connection_type = 0x1; /* regular data port */
7316 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7317
7318 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7319
7320 /* This VSI is connected to VEB so the switch_id
7321 * should be set to zero by default.
7322 */
7323 ctxt.info.switch_id = 0;
7324 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
7325 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7326
7327 /* Setup the VSI tx/rx queue map for TC0 only for now */
7328 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7329 break;
7330
7331 case I40E_VSI_SRIOV:
7332 ctxt.pf_num = hw->pf_id;
7333 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7334 ctxt.uplink_seid = vsi->uplink_seid;
7335 ctxt.connection_type = 0x1; /* regular data port */
7336 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7337
7338 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7339
7340 /* This VSI is connected to VEB so the switch_id
7341 * should be set to zero by default.
7342 */
7343 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7344
7345 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7346 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7347 if (pf->vf[vsi->vf_id].spoofchk) {
7348 ctxt.info.valid_sections |=
7349 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7350 ctxt.info.sec_flags |=
7351 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7352 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7353 }
41c445ff
JB		 7354 /* Setup the VSI tx/rx queue map for TC0 only for now */
7355 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7356 break;
7357
7358 default:
7359 return -ENODEV;
7360 }
7361
7362 if (vsi->type != I40E_VSI_MAIN) {
7363 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7364 if (ret) {
7365 dev_info(&vsi->back->pdev->dev,
7366 "add vsi failed, aq_err=%d\n",
7367 vsi->back->hw.aq.asq_last_status);
7368 ret = -ENOENT;
7369 goto err;
7370 }
7371 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7372 vsi->info.valid_sections = 0;
7373 vsi->seid = ctxt.seid;
7374 vsi->id = ctxt.vsi_number;
7375 }
7376
7377 /* If macvlan filters already exist, force them to get loaded */
7378 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7379 f->changed = true;
7380 f_count++;
7381 }
7382 if (f_count) {
7383 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7384 pf->flags |= I40E_FLAG_FILTER_SYNC;
7385 }
7386
7387 /* Update VSI BW information */
7388 ret = i40e_vsi_get_bw_info(vsi);
7389 if (ret) {
7390 dev_info(&pf->pdev->dev,
7391 "couldn't get vsi bw info, err %d, aq_err %d\n",
7392 ret, pf->hw.aq.asq_last_status);
7393 /* VSI is already added so not tearing that up */
7394 ret = 0;
7395 }
7396
7397err:
7398 return ret;
7399}
7400
7401/**
7402 * i40e_vsi_release - Delete a VSI and free its resources
7403 * @vsi: the VSI being removed
7404 *
7405 * Returns 0 on success or < 0 on error
7406 **/
7407int i40e_vsi_release(struct i40e_vsi *vsi)
7408{
7409 struct i40e_mac_filter *f, *ftmp;
7410 struct i40e_veb *veb = NULL;
7411 struct i40e_pf *pf;
7412 u16 uplink_seid;
7413 int i, n;
7414
7415 pf = vsi->back;
7416
7417 /* release of a VEB-owner or last VSI is not allowed */
7418 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7419 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7420 vsi->seid, vsi->uplink_seid);
7421 return -ENODEV;
7422 }
7423 if (vsi == pf->vsi[pf->lan_vsi] &&
7424 !test_bit(__I40E_DOWN, &pf->state)) {
7425 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7426 return -ENODEV;
7427 }
7428
7429 uplink_seid = vsi->uplink_seid;
7430 if (vsi->type != I40E_VSI_SRIOV) {
7431 if (vsi->netdev_registered) {
7432 vsi->netdev_registered = false;
7433 if (vsi->netdev) {
7434 /* results in a call to i40e_close() */
7435 unregister_netdev(vsi->netdev);
41c445ff
JB		 7436 }
7437 } else {
90ef8d47 7438 i40e_vsi_close(vsi);
41c445ff
JB		 7439 }
7440 i40e_vsi_disable_irq(vsi);
7441 }
7442
7443 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7444 i40e_del_filter(vsi, f->macaddr, f->vlan,
7445 f->is_vf, f->is_netdev);
7446 i40e_sync_vsi_filters(vsi);
7447
7448 i40e_vsi_delete(vsi);
7449 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7450 if (vsi->netdev) {
7451 free_netdev(vsi->netdev);
7452 vsi->netdev = NULL;
7453 }
41c445ff
JB		 7454 i40e_vsi_clear_rings(vsi);
7455 i40e_vsi_clear(vsi);
7456
7457 /* If this was the last thing on the VEB, except for the
7458 * controlling VSI, remove the VEB, which puts the controlling
7459 * VSI onto the next level down in the switch.
7460 *
7461 * Well, okay, there's one more exception here: don't remove
7462 * the orphan VEBs yet. We'll wait for an explicit remove request
7463 * from up the network stack.
7464 */
505682cd 7465 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7466 if (pf->vsi[i] &&
7467 pf->vsi[i]->uplink_seid == uplink_seid &&
7468 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7469 n++; /* count the VSIs */
7470 }
7471 }
7472 for (i = 0; i < I40E_MAX_VEB; i++) {
7473 if (!pf->veb[i])
7474 continue;
7475 if (pf->veb[i]->uplink_seid == uplink_seid)
7476 n++; /* count the VEBs */
7477 if (pf->veb[i]->seid == uplink_seid)
7478 veb = pf->veb[i];
7479 }
7480 if (n == 0 && veb && veb->uplink_seid != 0)
7481 i40e_veb_release(veb);
7482
7483 return 0;
7484}
7485
7486/**
7487 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7488 * @vsi: ptr to the VSI
7489 *
7490 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7491 * corresponding SW VSI structure and initializes num_queue_pairs for the
7492 * newly allocated VSI.
7493 *
7494 * Returns 0 on success or negative on failure
7495 **/
7496static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7497{
7498 int ret = -ENOENT;
7499 struct i40e_pf *pf = vsi->back;
7500
493fb300 7501 if (vsi->q_vectors[0]) {
41c445ff
JB		 7502 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7503 vsi->seid);
7504 return -EEXIST;
7505 }
7506
7507 if (vsi->base_vector) {
f29eaa3d 7508 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7509 vsi->seid, vsi->base_vector);
7510 return -EEXIST;
7511 }
7512
90e04070 7513 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7514 if (ret) {
7515 dev_info(&pf->pdev->dev,
7516 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7517 vsi->num_q_vectors, vsi->seid, ret);
7518 vsi->num_q_vectors = 0;
7519 goto vector_setup_out;
7520 }
7521
958a3e3b
SN		 7522 if (vsi->num_q_vectors)
7523 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7524 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7525 if (vsi->base_vector < 0) {
7526 dev_info(&pf->pdev->dev,
f29eaa3d 7527 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7528 vsi->seid, vsi->base_vector);
7529 i40e_vsi_free_q_vectors(vsi);
7530 ret = -ENOENT;
7531 goto vector_setup_out;
7532 }
7533
7534vector_setup_out:
7535 return ret;
7536}
7537
bc7d338f
ASJ		 7538/**
7539 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7540 * @vsi: pointer to the vsi.
7541 *
7542 * This re-allocates a vsi's queue resources.
7543 *
7544 * Returns pointer to the successfully allocated and configured VSI sw struct
7545 * on success, otherwise returns NULL on failure.
7546 **/
7547static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7548{
7549 struct i40e_pf *pf = vsi->back;
7550 u8 enabled_tc;
7551 int ret;
7552
7553 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7554 i40e_vsi_clear_rings(vsi);
7555
7556 i40e_vsi_free_arrays(vsi, false);
7557 i40e_set_num_rings_in_vsi(vsi);
7558 ret = i40e_vsi_alloc_arrays(vsi, false);
7559 if (ret)
7560 goto err_vsi;
7561
7562 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7563 if (ret < 0) {
7564 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7565 vsi->seid, ret);
7566 goto err_vsi;
7567 }
7568 vsi->base_queue = ret;
7569
7570 /* Update the FW view of the VSI. Force a reset of TC and queue
7571 * layout configurations.
7572 */
7573 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7574 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7575 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7576 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7577
7578 /* assign it some queues */
7579 ret = i40e_alloc_rings(vsi);
7580 if (ret)
7581 goto err_rings;
7582
7583 /* map all of the rings to the q_vectors */
7584 i40e_vsi_map_rings_to_vectors(vsi);
7585 return vsi;
7586
7587err_rings:
7588 i40e_vsi_free_q_vectors(vsi);
7589 if (vsi->netdev_registered) {
7590 vsi->netdev_registered = false;
7591 unregister_netdev(vsi->netdev);
7592 free_netdev(vsi->netdev);
7593 vsi->netdev = NULL;
7594 }
7595 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7596err_vsi:
7597 i40e_vsi_clear(vsi);
7598 return NULL;
7599}
7600
41c445ff
JB		 7601/**
7602 * i40e_vsi_setup - Set up a VSI by a given type
7603 * @pf: board private structure
7604 * @type: VSI type
7605 * @uplink_seid: the switch element to link to
7606 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7607 *
7608 * This allocates the sw VSI structure and its queue resources, then add a VSI
7609 * to the identified VEB.
7610 *
7611 * Returns pointer to the successfully allocated and configure VSI sw struct on
7612 * success, otherwise returns NULL on failure.
7613 **/
7614struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7615 u16 uplink_seid, u32 param1)
7616{
7617 struct i40e_vsi *vsi = NULL;
7618 struct i40e_veb *veb = NULL;
7619 int ret, i;
7620 int v_idx;
7621
7622 /* The requested uplink_seid must be either
7623 * - the PF's port seid
7624 * no VEB is needed because this is the PF
7625 * or this is a Flow Director special case VSI
7626 * - seid of an existing VEB
7627 * - seid of a VSI that owns an existing VEB
7628 * - seid of a VSI that doesn't own a VEB
7629 * a new VEB is created and the VSI becomes the owner
7630 * - seid of the PF VSI, which is what creates the first VEB
7631 * this is a special case of the previous
7632 *
7633 * Find which uplink_seid we were given and create a new VEB if needed
7634 */
7635 for (i = 0; i < I40E_MAX_VEB; i++) {
7636 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7637 veb = pf->veb[i];
7638 break;
7639 }
7640 }
7641
7642 if (!veb && uplink_seid != pf->mac_seid) {
7643
505682cd 7644 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7645 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7646 vsi = pf->vsi[i];
7647 break;
7648 }
7649 }
7650 if (!vsi) {
7651 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7652 uplink_seid);
7653 return NULL;
7654 }
7655
7656 if (vsi->uplink_seid == pf->mac_seid)
7657 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7658 vsi->tc_config.enabled_tc);
7659 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7660 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7661 vsi->tc_config.enabled_tc);
7662
7663 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7664 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7665 veb = pf->veb[i];
7666 }
7667 if (!veb) {
7668 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7669 return NULL;
7670 }
7671
7672 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7673 uplink_seid = veb->seid;
7674 }
7675
7676 /* get vsi sw struct */
7677 v_idx = i40e_vsi_mem_alloc(pf, type);
7678 if (v_idx < 0)
7679 goto err_alloc;
7680 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7681 if (!vsi)
7682 goto err_alloc;
41c445ff
JB		 7683 vsi->type = type;
7684 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7685
7686 if (type == I40E_VSI_MAIN)
7687 pf->lan_vsi = v_idx;
7688 else if (type == I40E_VSI_SRIOV)
7689 vsi->vf_id = param1;
7690 /* assign it some queues */
cbf61325
ASJ		 7691 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7692 vsi->idx);
41c445ff
JB		 7693 if (ret < 0) {
7694 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7695 vsi->seid, ret);
7696 goto err_vsi;
7697 }
7698 vsi->base_queue = ret;
7699
7700 /* get a VSI from the hardware */
7701 vsi->uplink_seid = uplink_seid;
7702 ret = i40e_add_vsi(vsi);
7703 if (ret)
7704 goto err_vsi;
7705
7706 switch (vsi->type) {
7707 /* setup the netdev if needed */
7708 case I40E_VSI_MAIN:
7709 case I40E_VSI_VMDQ2:
7710 ret = i40e_config_netdev(vsi);
7711 if (ret)
7712 goto err_netdev;
7713 ret = register_netdev(vsi->netdev);
7714 if (ret)
7715 goto err_netdev;
7716 vsi->netdev_registered = true;
7717 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7718#ifdef CONFIG_I40E_DCB
7719 /* Setup DCB netlink interface */
7720 i40e_dcbnl_setup(vsi);
7721#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7722 /* fall through */
7723
7724 case I40E_VSI_FDIR:
7725 /* set up vectors and rings if needed */
7726 ret = i40e_vsi_setup_vectors(vsi);
7727 if (ret)
7728 goto err_msix;
7729
7730 ret = i40e_alloc_rings(vsi);
7731 if (ret)
7732 goto err_rings;
7733
7734 /* map all of the rings to the q_vectors */
7735 i40e_vsi_map_rings_to_vectors(vsi);
7736
7737 i40e_vsi_reset_stats(vsi);
7738 break;
7739
7740 default:
7741 /* no netdev or rings for the other VSI types */
7742 break;
7743 }
7744
7745 return vsi;
7746
7747err_rings:
7748 i40e_vsi_free_q_vectors(vsi);
7749err_msix:
7750 if (vsi->netdev_registered) {
7751 vsi->netdev_registered = false;
7752 unregister_netdev(vsi->netdev);
7753 free_netdev(vsi->netdev);
7754 vsi->netdev = NULL;
7755 }
7756err_netdev:
7757 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7758err_vsi:
7759 i40e_vsi_clear(vsi);
7760err_alloc:
7761 return NULL;
7762}
7763
7764/**
7765 * i40e_veb_get_bw_info - Query VEB BW information
7766 * @veb: the veb to query
7767 *
7768 * Query the Tx scheduler BW configuration data for given VEB
7769 **/
7770static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7771{
7772 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7773 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7774 struct i40e_pf *pf = veb->pf;
7775 struct i40e_hw *hw = &pf->hw;
7776 u32 tc_bw_max;
7777 int ret = 0;
7778 int i;
7779
7780 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7781 &bw_data, NULL);
7782 if (ret) {
7783 dev_info(&pf->pdev->dev,
7784 "query veb bw config failed, aq_err=%d\n",
7785 hw->aq.asq_last_status);
7786 goto out;
7787 }
7788
7789 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7790 &ets_data, NULL);
7791 if (ret) {
7792 dev_info(&pf->pdev->dev,
7793 "query veb bw ets config failed, aq_err=%d\n",
7794 hw->aq.asq_last_status);
7795 goto out;
7796 }
7797
7798 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7799 veb->bw_max_quanta = ets_data.tc_bw_max;
7800 veb->is_abs_credits = bw_data.absolute_credits_enable;
7801 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7802 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7803 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7804 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7805 veb->bw_tc_limit_credits[i] =
7806 le16_to_cpu(bw_data.tc_bw_limits[i]);
7807 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7808 }
7809
7810out:
7811 return ret;
7812}
7813
7814/**
7815 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7816 * @pf: board private structure
7817 *
7818 * On error: returns error code (negative)
7819 * On success: returns vsi index in PF (positive)
7820 **/
7821static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7822{
7823 int ret = -ENOENT;
7824 struct i40e_veb *veb;
7825 int i;
7826
7827 /* Need to protect the allocation of switch elements at the PF level */
7828 mutex_lock(&pf->switch_mutex);
7829
7830 /* VEB list may be fragmented if VEB creation/destruction has
7831 * been happening. We can afford to do a quick scan to look
7832 * for any free slots in the list.
7833 *
7834 * find next empty veb slot, looping back around if necessary
7835 */
7836 i = 0;
7837 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7838 i++;
7839 if (i >= I40E_MAX_VEB) {
7840 ret = -ENOMEM;
7841 goto err_alloc_veb; /* out of VEB slots! */
7842 }
7843
7844 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7845 if (!veb) {
7846 ret = -ENOMEM;
7847 goto err_alloc_veb;
7848 }
7849 veb->pf = pf;
7850 veb->idx = i;
7851 veb->enabled_tc = 1;
7852
7853 pf->veb[i] = veb;
7854 ret = i;
7855err_alloc_veb:
7856 mutex_unlock(&pf->switch_mutex);
7857 return ret;
7858}
7859
7860/**
7861 * i40e_switch_branch_release - Delete a branch of the switch tree
7862 * @branch: where to start deleting
7863 *
7864 * This uses recursion to find the tips of the branch to be
7865 * removed, deleting until we get back to and can delete this VEB.
7866 **/
7867static void i40e_switch_branch_release(struct i40e_veb *branch)
7868{
7869 struct i40e_pf *pf = branch->pf;
7870 u16 branch_seid = branch->seid;
7871 u16 veb_idx = branch->idx;
7872 int i;
7873
7874 /* release any VEBs on this VEB - RECURSION */
7875 for (i = 0; i < I40E_MAX_VEB; i++) {
7876 if (!pf->veb[i])
7877 continue;
7878 if (pf->veb[i]->uplink_seid == branch->seid)
7879 i40e_switch_branch_release(pf->veb[i]);
7880 }
7881
7882 /* Release the VSIs on this VEB, but not the owner VSI.
7883 *
7884 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7885 * the VEB itself, so don't use (*branch) after this loop.
7886 */
505682cd 7887 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7888 if (!pf->vsi[i])
7889 continue;
7890 if (pf->vsi[i]->uplink_seid == branch_seid &&
7891 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7892 i40e_vsi_release(pf->vsi[i]);
7893 }
7894 }
7895
7896 /* There's one corner case where the VEB might not have been
7897 * removed, so double check it here and remove it if needed.
7898 * This case happens if the veb was created from the debugfs
7899 * commands and no VSIs were added to it.
7900 */
7901 if (pf->veb[veb_idx])
7902 i40e_veb_release(pf->veb[veb_idx]);
7903}
7904
7905/**
7906 * i40e_veb_clear - remove veb struct
7907 * @veb: the veb to remove
7908 **/
7909static void i40e_veb_clear(struct i40e_veb *veb)
7910{
7911 if (!veb)
7912 return;
7913
7914 if (veb->pf) {
7915 struct i40e_pf *pf = veb->pf;
7916
7917 mutex_lock(&pf->switch_mutex);
7918 if (pf->veb[veb->idx] == veb)
7919 pf->veb[veb->idx] = NULL;
7920 mutex_unlock(&pf->switch_mutex);
7921 }
7922
7923 kfree(veb);
7924}
7925
7926/**
7927 * i40e_veb_release - Delete a VEB and free its resources
7928 * @veb: the VEB being removed
7929 **/
7930void i40e_veb_release(struct i40e_veb *veb)
7931{
7932 struct i40e_vsi *vsi = NULL;
7933 struct i40e_pf *pf;
7934 int i, n = 0;
7935
7936 pf = veb->pf;
7937
7938 /* find the remaining VSI and check for extras */
505682cd 7939 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7940 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7941 n++;
7942 vsi = pf->vsi[i];
7943 }
7944 }
7945 if (n != 1) {
7946 dev_info(&pf->pdev->dev,
7947 "can't remove VEB %d with %d VSIs left\n",
7948 veb->seid, n);
7949 return;
7950 }
7951
7952 /* move the remaining VSI to uplink veb */
7953 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7954 if (veb->uplink_seid) {
7955 vsi->uplink_seid = veb->uplink_seid;
7956 if (veb->uplink_seid == pf->mac_seid)
7957 vsi->veb_idx = I40E_NO_VEB;
7958 else
7959 vsi->veb_idx = veb->veb_idx;
7960 } else {
7961 /* floating VEB */
7962 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7963 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7964 }
7965
7966 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7967 i40e_veb_clear(veb);
41c445ff
JB		 7968}
7969
7970/**
7971 * i40e_add_veb - create the VEB in the switch
7972 * @veb: the VEB to be instantiated
7973 * @vsi: the controlling VSI
7974 **/
7975static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7976{
56747264 7977 bool is_default = false;
e1c51b95 7978 bool is_cloud = false;
41c445ff
JB		 7979 int ret;
7980
7981 /* get a VEB from the hardware */
7982 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7983 veb->enabled_tc, is_default,
7984 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7985 if (ret) {
7986 dev_info(&veb->pf->pdev->dev,
7987 "couldn't add VEB, err %d, aq_err %d\n",
7988 ret, veb->pf->hw.aq.asq_last_status);
7989 return -EPERM;
7990 }
7991
7992 /* get statistics counter */
7993 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7994 &veb->stats_idx, NULL, NULL, NULL);
7995 if (ret) {
7996 dev_info(&veb->pf->pdev->dev,
7997 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7998 ret, veb->pf->hw.aq.asq_last_status);
7999 return -EPERM;
8000 }
8001 ret = i40e_veb_get_bw_info(veb);
8002 if (ret) {
8003 dev_info(&veb->pf->pdev->dev,
8004 "couldn't get VEB bw info, err %d, aq_err %d\n",
8005 ret, veb->pf->hw.aq.asq_last_status);
8006 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8007 return -ENOENT;
8008 }
8009
8010 vsi->uplink_seid = veb->seid;
8011 vsi->veb_idx = veb->idx;
8012 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8013
8014 return 0;
8015}
8016
8017/**
8018 * i40e_veb_setup - Set up a VEB
8019 * @pf: board private structure
8020 * @flags: VEB setup flags
8021 * @uplink_seid: the switch element to link to
8022 * @vsi_seid: the initial VSI seid
8023 * @enabled_tc: Enabled TC bit-map
8024 *
8025 * This allocates the sw VEB structure and links it into the switch
8026 * It is possible and legal for this to be a duplicate of an already
8027 * existing VEB. It is also possible for both uplink and vsi seids
8028 * to be zero, in order to create a floating VEB.
8029 *
8030 * Returns pointer to the successfully allocated VEB sw struct on
8031 * success, otherwise returns NULL on failure.
8032 **/
8033struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8034 u16 uplink_seid, u16 vsi_seid,
8035 u8 enabled_tc)
8036{
8037 struct i40e_veb *veb, *uplink_veb = NULL;
8038 int vsi_idx, veb_idx;
8039 int ret;
8040
8041 /* if one seid is 0, the other must be 0 to create a floating relay */
8042 if ((uplink_seid == 0 || vsi_seid == 0) &&
8043 (uplink_seid + vsi_seid != 0)) {
8044 dev_info(&pf->pdev->dev,
8045 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8046 uplink_seid, vsi_seid);
8047 return NULL;
8048 }
8049
8050 /* make sure there is such a vsi and uplink */
505682cd 8051 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8052 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8053 break;
505682cd 8054 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8055 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8056 vsi_seid);
8057 return NULL;
8058 }
8059
8060 if (uplink_seid && uplink_seid != pf->mac_seid) {
8061 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8062 if (pf->veb[veb_idx] &&
8063 pf->veb[veb_idx]->seid == uplink_seid) {
8064 uplink_veb = pf->veb[veb_idx];
8065 break;
8066 }
8067 }
8068 if (!uplink_veb) {
8069 dev_info(&pf->pdev->dev,
8070 "uplink seid %d not found\n", uplink_seid);
8071 return NULL;
8072 }
8073 }
8074
8075 /* get veb sw struct */
8076 veb_idx = i40e_veb_mem_alloc(pf);
8077 if (veb_idx < 0)
8078 goto err_alloc;
8079 veb = pf->veb[veb_idx];
8080 veb->flags = flags;
8081 veb->uplink_seid = uplink_seid;
8082 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8083 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8084
8085 /* create the VEB in the switch */
8086 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8087 if (ret)
8088 goto err_veb;
1bb8b935
SN		 8089 if (vsi_idx == pf->lan_vsi)
8090 pf->lan_veb = veb->idx;
41c445ff
JB		 8091
8092 return veb;
8093
8094err_veb:
8095 i40e_veb_clear(veb);
8096err_alloc:
8097 return NULL;
8098}
8099
8100/**
8101 * i40e_setup_pf_switch_element - set pf vars based on switch type
8102 * @pf: board private structure
8103 * @ele: element we are building info from
8104 * @num_reported: total number of elements
8105 * @printconfig: should we print the contents
8106 *
8107 * helper function to assist in extracting a few useful SEID values.
8108 **/
8109static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8110 struct i40e_aqc_switch_config_element_resp *ele,
8111 u16 num_reported, bool printconfig)
8112{
8113 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8114 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8115 u8 element_type = ele->element_type;
8116 u16 seid = le16_to_cpu(ele->seid);
8117
8118 if (printconfig)
8119 dev_info(&pf->pdev->dev,
8120 "type=%d seid=%d uplink=%d downlink=%d\n",
8121 element_type, seid, uplink_seid, downlink_seid);
8122
8123 switch (element_type) {
8124 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8125 pf->mac_seid = seid;
8126 break;
8127 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8128 /* Main VEB? */
8129 if (uplink_seid != pf->mac_seid)
8130 break;
8131 if (pf->lan_veb == I40E_NO_VEB) {
8132 int v;
8133
8134 /* find existing or else empty VEB */
8135 for (v = 0; v < I40E_MAX_VEB; v++) {
8136 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8137 pf->lan_veb = v;
8138 break;
8139 }
8140 }
8141 if (pf->lan_veb == I40E_NO_VEB) {
8142 v = i40e_veb_mem_alloc(pf);
8143 if (v < 0)
8144 break;
8145 pf->lan_veb = v;
8146 }
8147 }
8148
8149 pf->veb[pf->lan_veb]->seid = seid;
8150 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8151 pf->veb[pf->lan_veb]->pf = pf;
8152 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8153 break;
8154 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8155 if (num_reported != 1)
8156 break;
8157 /* This is immediately after a reset so we can assume this is
8158 * the PF's VSI
8159 */
8160 pf->mac_seid = uplink_seid;
8161 pf->pf_seid = downlink_seid;
8162 pf->main_vsi_seid = seid;
8163 if (printconfig)
8164 dev_info(&pf->pdev->dev,
8165 "pf_seid=%d main_vsi_seid=%d\n",
8166 pf->pf_seid, pf->main_vsi_seid);
8167 break;
8168 case I40E_SWITCH_ELEMENT_TYPE_PF:
8169 case I40E_SWITCH_ELEMENT_TYPE_VF:
8170 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8171 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8172 case I40E_SWITCH_ELEMENT_TYPE_PE:
8173 case I40E_SWITCH_ELEMENT_TYPE_PA:
8174 /* ignore these for now */
8175 break;
8176 default:
8177 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8178 element_type, seid);
8179 break;
8180 }
8181}
8182
8183/**
8184 * i40e_fetch_switch_configuration - Get switch config from firmware
8185 * @pf: board private structure
8186 * @printconfig: should we print the contents
8187 *
8188 * Get the current switch configuration from the device and
8189 * extract a few useful SEID values.
8190 **/
8191int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8192{
8193 struct i40e_aqc_get_switch_config_resp *sw_config;
8194 u16 next_seid = 0;
8195 int ret = 0;
8196 u8 *aq_buf;
8197 int i;
8198
8199 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8200 if (!aq_buf)
8201 return -ENOMEM;
8202
8203 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8204 do {
8205 u16 num_reported, num_total;
8206
8207 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8208 I40E_AQ_LARGE_BUF,
8209 &next_seid, NULL);
8210 if (ret) {
8211 dev_info(&pf->pdev->dev,
8212 "get switch config failed %d aq_err=%x\n",
8213 ret, pf->hw.aq.asq_last_status);
8214 kfree(aq_buf);
8215 return -ENOENT;
8216 }
8217
8218 num_reported = le16_to_cpu(sw_config->header.num_reported);
8219 num_total = le16_to_cpu(sw_config->header.num_total);
8220
8221 if (printconfig)
8222 dev_info(&pf->pdev->dev,
8223 "header: %d reported %d total\n",
8224 num_reported, num_total);
8225
41c445ff
JB		 8226 for (i = 0; i < num_reported; i++) {
8227 struct i40e_aqc_switch_config_element_resp *ele =
8228 &sw_config->element[i];
8229
8230 i40e_setup_pf_switch_element(pf, ele, num_reported,
8231 printconfig);
8232 }
8233 } while (next_seid != 0);
8234
8235 kfree(aq_buf);
8236 return ret;
8237}
8238
8239/**
8240 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8241 * @pf: board private structure
bc7d338f 8242 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8243 *
8244 * Returns 0 on success, negative value on failure
8245 **/
bc7d338f 8246static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 8247{
895106a5 8248 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 8249 int ret;
8250
8251 /* find out what's out there already */
8252 ret = i40e_fetch_switch_configuration(pf, false);
8253 if (ret) {
8254 dev_info(&pf->pdev->dev,
8255 "couldn't fetch switch config, err %d, aq_err %d\n",
8256 ret, pf->hw.aq.asq_last_status);
8257 return ret;
8258 }
8259 i40e_pf_reset_stats(pf);
8260
41c445ff 8261 /* first time setup */
bc7d338f 8262 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8263 struct i40e_vsi *vsi = NULL;
8264 u16 uplink_seid;
8265
8266 /* Set up the PF VSI associated with the PF's main VSI
8267 * that is already in the HW switch
8268 */
8269 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8270 uplink_seid = pf->veb[pf->lan_veb]->seid;
8271 else
8272 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8273 if (pf->lan_vsi == I40E_NO_VSI)
8274 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8275 else if (reinit)
8276 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8277 if (!vsi) {
8278 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8279 i40e_fdir_teardown(pf);
8280 return -EAGAIN;
8281 }
41c445ff
JB		 8282 } else {
8283 /* force a reset of TC and queue layout configurations */
8284 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8285 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8286 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8287 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8288 }
8289 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8290
cbf61325
ASJ		 8291 i40e_fdir_sb_setup(pf);
8292
41c445ff
JB		 8293 /* Setup static PF queue filter control settings */
8294 ret = i40e_setup_pf_filter_control(pf);
8295 if (ret) {
8296 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8297 ret);
8298 /* Failure here should not stop continuing other steps */
8299 }
8300
8301 /* enable RSS in the HW, even for only one queue, as the stack can use
8302 * the hash
8303 */
8304 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8305 i40e_config_rss(pf);
8306
8307 /* fill in link information and enable LSE reporting */
8308 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
8309 i40e_link_event(pf);
8310
d52c20b7 8311 /* Initialize user-specific link properties */
41c445ff
JB		 8312 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8313 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 8314 /* requested_mode is set in probe or by ethtool */
8315 if (!pf->fc_autoneg_status)
8316 goto no_autoneg;
8317
8318 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
8319 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 8320 pf->hw.fc.current_mode = I40E_FC_FULL;
8321 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
8322 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
8323 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
8324 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
8325 else
d52c20b7
JB		 8326 pf->hw.fc.current_mode = I40E_FC_NONE;
8327
8328 /* sync the flow control settings with the auto-neg values */
8329 switch (pf->hw.fc.current_mode) {
8330 case I40E_FC_FULL:
8331 txfc = 1;
8332 rxfc = 1;
8333 break;
8334 case I40E_FC_TX_PAUSE:
8335 txfc = 1;
8336 rxfc = 0;
8337 break;
8338 case I40E_FC_RX_PAUSE:
8339 txfc = 0;
8340 rxfc = 1;
8341 break;
8342 case I40E_FC_NONE:
8343 case I40E_FC_DEFAULT:
8344 txfc = 0;
8345 rxfc = 0;
8346 break;
8347 case I40E_FC_PFC:
8348 /* TBD */
8349 break;
8350 /* no default case, we have to handle all possibilities here */
8351 }
8352
8353 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8354
8355 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8356 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8357 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8358
8359 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8360
d52c20b7
JB		 8361 goto fc_complete;
8362
8363no_autoneg:
8364 /* disable L2 flow control, user can turn it on if they wish */
8365 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8366 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8367 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8368
8369fc_complete:
beb0dff1
JK		 8370 i40e_ptp_init(pf);
8371
41c445ff
JB		 8372 return ret;
8373}
8374
41c445ff
JB		 8375/**
8376 * i40e_determine_queue_usage - Work out queue distribution
8377 * @pf: board private structure
8378 **/
8379static void i40e_determine_queue_usage(struct i40e_pf *pf)
8380{
41c445ff
JB		 8381 int queues_left;
8382
8383 pf->num_lan_qps = 0;
41c445ff
JB		 8384
8385 /* Find the max queues to be put into basic use. We'll always be
8386 * using TC0, whether or not DCB is running, and TC0 will get the
8387 * big RSS set.
8388 */
8389 queues_left = pf->hw.func_caps.num_tx_qp;
8390
cbf61325 8391 if ((queues_left == 1) ||
9aa7e935 8392 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8393 /* one qp for PF, no queues for anything else */
8394 queues_left = 0;
8395 pf->rss_size = pf->num_lan_qps = 1;
8396
8397 /* make sure all the fancies are disabled */
60ea5f83
JB		 8398 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8399 I40E_FLAG_FD_SB_ENABLED |
8400 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8401 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8402 I40E_FLAG_SRIOV_ENABLED |
8403 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8404 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8405 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8406 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8407 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8408 /* one qp for PF */
8409 pf->rss_size = pf->num_lan_qps = 1;
8410 queues_left -= pf->num_lan_qps;
8411
8412 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8413 I40E_FLAG_FD_SB_ENABLED |
8414 I40E_FLAG_FD_ATR_ENABLED |
8415 I40E_FLAG_DCB_ENABLED |
8416 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8417 } else {
cbf61325 8418 /* Not enough queues for all TCs */
4d9b6043 8419 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8420 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8421 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8422 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8423 }
8424 pf->num_lan_qps = pf->rss_size_max;
8425 queues_left -= pf->num_lan_qps;
8426 }
8427
8428 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8429 if (queues_left > 1) {
8430 queues_left -= 1; /* save 1 queue for FD */
8431 } else {
8432 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8433 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8434 }
41c445ff
JB		 8435 }
8436
8437 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8438 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8439 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8440 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8441 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8442 }
8443
8444 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8445 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8446 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8447 (queues_left / pf->num_vmdq_qps));
8448 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8449 }
8450
f8ff1464 8451 pf->queues_left = queues_left;
41c445ff
JB		 8452}
8453
8454/**
8455 * i40e_setup_pf_filter_control - Setup PF static filter control
8456 * @pf: PF to be setup
8457 *
8458 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8459 * settings. If PE/FCoE are enabled then it will also set the per PF
8460 * based filter sizes required for them. It also enables Flow director,
8461 * ethertype and macvlan type filter settings for the pf.
8462 *
8463 * Returns 0 on success, negative on failure
8464 **/
8465static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8466{
8467 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8468
8469 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8470
8471 /* Flow Director is enabled */
60ea5f83 8472 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8473 settings->enable_fdir = true;
8474
8475 /* Ethtype and MACVLAN filters enabled for PF */
8476 settings->enable_ethtype = true;
8477 settings->enable_macvlan = true;
8478
8479 if (i40e_set_filter_control(&pf->hw, settings))
8480 return -ENOENT;
8481
8482 return 0;
8483}
8484
0c22b3dd
JB		 8485#define INFO_STRING_LEN 255
8486static void i40e_print_features(struct i40e_pf *pf)
8487{
8488 struct i40e_hw *hw = &pf->hw;
8489 char *buf, *string;
8490
8491 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8492 if (!string) {
8493 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8494 return;
8495 }
8496
8497 buf = string;
8498
8499 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8500#ifdef CONFIG_PCI_IOV
8501 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8502#endif
8503 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8504 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8505
8506 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8507 buf += sprintf(buf, "RSS ");
0c22b3dd 8508 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8509 buf += sprintf(buf, "FD_ATR ");
8510 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8511 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8512 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8513 }
4d9b6043 8514 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8515 buf += sprintf(buf, "DCB ");
8516 if (pf->flags & I40E_FLAG_PTP)
8517 buf += sprintf(buf, "PTP ");
8518
8519 BUG_ON(buf > (string + INFO_STRING_LEN));
8520 dev_info(&pf->pdev->dev, "%s\n", string);
8521 kfree(string);
8522}
8523
41c445ff
JB		 8524/**
8525 * i40e_probe - Device initialization routine
8526 * @pdev: PCI device information struct
8527 * @ent: entry in i40e_pci_tbl
8528 *
8529 * i40e_probe initializes a pf identified by a pci_dev structure.
8530 * The OS initialization, configuring of the pf private structure,
8531 * and a hardware reset occur.
8532 *
8533 * Returns 0 on success, negative on failure
8534 **/
8535static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8536{
41c445ff
JB		 8537 struct i40e_pf *pf;
8538 struct i40e_hw *hw;
93cd765b 8539 static u16 pfs_found;
d4dfb81a 8540 u16 link_status;
41c445ff
JB		 8541 int err = 0;
8542 u32 len;
8a9eb7d3 8543 u32 i;
41c445ff
JB		 8544
8545 err = pci_enable_device_mem(pdev);
8546 if (err)
8547 return err;
8548
8549 /* set up for high or low dma */
6494294f 8550 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8551 if (err) {
e3e3bfdd
JS		 8552 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8553 if (err) {
8554 dev_err(&pdev->dev,
8555 "DMA configuration failed: 0x%x\n", err);
8556 goto err_dma;
8557 }
41c445ff
JB		 8558 }
8559
8560 /* set up pci connections */
8561 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8562 IORESOURCE_MEM), i40e_driver_name);
8563 if (err) {
8564 dev_info(&pdev->dev,
8565 "pci_request_selected_regions failed %d\n", err);
8566 goto err_pci_reg;
8567 }
8568
8569 pci_enable_pcie_error_reporting(pdev);
8570 pci_set_master(pdev);
8571
8572 /* Now that we have a PCI connection, we need to do the
8573 * low level device setup. This is primarily setting up
8574 * the Admin Queue structures and then querying for the
8575 * device's current profile information.
8576 */
8577 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8578 if (!pf) {
8579 err = -ENOMEM;
8580 goto err_pf_alloc;
8581 }
8582 pf->next_vsi = 0;
8583 pf->pdev = pdev;
8584 set_bit(__I40E_DOWN, &pf->state);
8585
8586 hw = &pf->hw;
8587 hw->back = pf;
8588 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8589 pci_resource_len(pdev, 0));
8590 if (!hw->hw_addr) {
8591 err = -EIO;
8592 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8593 (unsigned int)pci_resource_start(pdev, 0),
8594 (unsigned int)pci_resource_len(pdev, 0), err);
8595 goto err_ioremap;
8596 }
8597 hw->vendor_id = pdev->vendor;
8598 hw->device_id = pdev->device;
8599 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8600 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8601 hw->subsystem_device_id = pdev->subsystem_device;
8602 hw->bus.device = PCI_SLOT(pdev->devfn);
8603 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8604 pf->instance = pfs_found;
41c445ff 8605
7134f9ce
JB		 8606 /* do a special CORER for clearing PXE mode once at init */
8607 if (hw->revision_id == 0 &&
8608 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8609 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8610 i40e_flush(hw);
8611 msleep(200);
8612 pf->corer_count++;
8613
8614 i40e_clear_pxe_mode(hw);
8615 }
8616
41c445ff
JB		 8617 /* Reset here to make sure all is clean and to define PF 'n' */
8618 err = i40e_pf_reset(hw);
8619 if (err) {
8620 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8621 goto err_pf_reset;
8622 }
8623 pf->pfr_count++;
8624
8625 hw->aq.num_arq_entries = I40E_AQ_LEN;
8626 hw->aq.num_asq_entries = I40E_AQ_LEN;
8627 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8628 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8629 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8630 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8631 "%s-pf%d:misc",
8632 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8633
8634 err = i40e_init_shared_code(hw);
8635 if (err) {
8636 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8637 goto err_pf_reset;
8638 }
8639
d52c20b7
JB		 8640 /* set up a default setting for link flow control */
8641 pf->hw.fc.requested_mode = I40E_FC_NONE;
8642
41c445ff
JB		 8643 err = i40e_init_adminq(hw);
8644 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8645 if (err) {
8646 dev_info(&pdev->dev,
8647 "init_adminq failed: %d expecting API %02x.%02x\n",
8648 err,
8649 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8650 goto err_pf_reset;
8651 }
8652
278b6f62
SN		 8653 if (hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
8654 dev_info(&pdev->dev,
8655 "Note: FW API version %02x.%02x newer than expected %02x.%02x, recommend driver update.\n",
8656 hw->aq.api_maj_ver, hw->aq.api_min_ver,
8657 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8658
8659 if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
8660 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR-1))
8661 dev_info(&pdev->dev,
8662 "Note: FW API version %02x.%02x older than expected %02x.%02x, recommend nvm update.\n",
8663 hw->aq.api_maj_ver, hw->aq.api_min_ver,
8664 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8665
8666
4eb3f768
SN		 8667 i40e_verify_eeprom(pf);
8668
2c5fe33b
JB		 8669 /* Rev 0 hardware was never productized */
8670 if (hw->revision_id < 1)
8671 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
8672
6ff4ef86 8673 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8674 err = i40e_get_capabilities(pf);
8675 if (err)
8676 goto err_adminq_setup;
8677
8678 err = i40e_sw_init(pf);
8679 if (err) {
8680 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8681 goto err_sw_init;
8682 }
8683
8684 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8685 hw->func_caps.num_rx_qp,
8686 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8687 if (err) {
8688 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8689 goto err_init_lan_hmc;
8690 }
8691
8692 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8693 if (err) {
8694 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8695 err = -ENOENT;
8696 goto err_configure_lan_hmc;
8697 }
8698
8699 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8700 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8701 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8702 err = -EIO;
8703 goto err_mac_addr;
8704 }
8705 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 8706 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
41c445ff
JB		 8707
8708 pci_set_drvdata(pdev, pf);
8709 pci_save_state(pdev);
4e3b35b0
NP		 8710#ifdef CONFIG_I40E_DCB
8711 err = i40e_init_pf_dcb(pf);
8712 if (err) {
8713 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 8714 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 8715 /* Continue without DCB enabled */
4e3b35b0
NP		 8716 }
8717#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8718
8719 /* set up periodic task facility */
8720 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8721 pf->service_timer_period = HZ;
8722
8723 INIT_WORK(&pf->service_task, i40e_service_task);
8724 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8725 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8726 pf->link_check_timeout = jiffies;
8727
8e2773ae
SN		 8728 /* WoL defaults to disabled */
8729 pf->wol_en = false;
8730 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8731
41c445ff
JB		 8732 /* set up the main switch operations */
8733 i40e_determine_queue_usage(pf);
8734 i40e_init_interrupt_scheme(pf);
8735
505682cd
MW		 8736 /* The number of VSIs reported by the FW is the minimum guaranteed
8737 * to us; HW supports far more and we share the remaining pool with
8738 * the other PFs. We allocate space for more than the guarantee with
8739 * the understanding that we might not get them all later.
41c445ff 8740 */
505682cd
MW		 8741 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
8742 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
8743 else
8744 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
8745
8746 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
8747 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 8748 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8749 if (!pf->vsi) {
8750 err = -ENOMEM;
41c445ff 8751 goto err_switch_setup;
ed87ac09 8752 }
41c445ff 8753
bc7d338f 8754 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8755 if (err) {
8756 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8757 goto err_vsis;
8758 }
8a9eb7d3 8759 /* if FDIR VSI was set up, start it now */
505682cd 8760 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 8761 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8762 i40e_vsi_open(pf->vsi[i]);
8763 break;
8764 }
8765 }
41c445ff
JB		 8766
8767 /* The main driver is (mostly) up and happy. We need to set this state
8768 * before setting up the misc vector or we get a race and the vector
8769 * ends up disabled forever.
8770 */
8771 clear_bit(__I40E_DOWN, &pf->state);
8772
8773 /* In case of MSIX we are going to setup the misc vector right here
8774 * to handle admin queue events etc. In case of legacy and MSI
8775 * the misc functionality and queue processing is combined in
8776 * the same vector and that gets setup at open.
8777 */
8778 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8779 err = i40e_setup_misc_vector(pf);
8780 if (err) {
8781 dev_info(&pdev->dev,
8782 "setup of misc vector failed: %d\n", err);
8783 goto err_vsis;
8784 }
8785 }
8786
df805f62 8787#ifdef CONFIG_PCI_IOV
41c445ff
JB		 8788 /* prep for VF support */
8789 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8790 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8791 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8792 u32 val;
8793
8794 /* disable link interrupts for VFs */
8795 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8796 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8797 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8798 i40e_flush(hw);
4aeec010
MW		 8799
8800 if (pci_num_vf(pdev)) {
8801 dev_info(&pdev->dev,
8802 "Active VFs found, allocating resources.\n");
8803 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8804 if (err)
8805 dev_info(&pdev->dev,
8806 "Error %d allocating resources for existing VFs\n",
8807 err);
8808 }
41c445ff 8809 }
df805f62 8810#endif /* CONFIG_PCI_IOV */
41c445ff 8811
93cd765b
ASJ		 8812 pfs_found++;
8813
41c445ff
JB		 8814 i40e_dbg_pf_init(pf);
8815
8816 /* tell the firmware that we're starting */
44033fac 8817 i40e_send_version(pf);
41c445ff
JB		 8818
8819 /* since everything's happy, start the service_task timer */
8820 mod_timer(&pf->service_timer,
8821 round_jiffies(jiffies + pf->service_timer_period));
8822
d4dfb81a
CS		 8823 /* Get the negotiated link width and speed from PCI config space */
8824 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8825
8826 i40e_set_pci_config_data(hw, link_status);
8827
69bfb110 8828 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8829 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8830 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8831 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8832 "Unknown"),
8833 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8834 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8835 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8836 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8837 "Unknown"));
8838
8839 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8840 hw->bus.speed < i40e_bus_speed_8000) {
8841 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8842 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8843 }
8844
0c22b3dd
JB		 8845 /* print a string summarizing features */
8846 i40e_print_features(pf);
8847
41c445ff
JB		 8848 return 0;
8849
8850 /* Unwind what we've done if something failed in the setup */
8851err_vsis:
8852 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8853 i40e_clear_interrupt_scheme(pf);
8854 kfree(pf->vsi);
04b03013
SN		 8855err_switch_setup:
8856 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8857 del_timer_sync(&pf->service_timer);
8858err_mac_addr:
8859err_configure_lan_hmc:
8860 (void)i40e_shutdown_lan_hmc(hw);
8861err_init_lan_hmc:
8862 kfree(pf->qp_pile);
8863 kfree(pf->irq_pile);
8864err_sw_init:
8865err_adminq_setup:
8866 (void)i40e_shutdown_adminq(hw);
8867err_pf_reset:
8868 iounmap(hw->hw_addr);
8869err_ioremap:
8870 kfree(pf);
8871err_pf_alloc:
8872 pci_disable_pcie_error_reporting(pdev);
8873 pci_release_selected_regions(pdev,
8874 pci_select_bars(pdev, IORESOURCE_MEM));
8875err_pci_reg:
8876err_dma:
8877 pci_disable_device(pdev);
8878 return err;
8879}
8880
8881/**
8882 * i40e_remove - Device removal routine
8883 * @pdev: PCI device information struct
8884 *
8885 * i40e_remove is called by the PCI subsystem to alert the driver
8886 * that is should release a PCI device. This could be caused by a
8887 * Hot-Plug event, or because the driver is going to be removed from
8888 * memory.
8889 **/
8890static void i40e_remove(struct pci_dev *pdev)
8891{
8892 struct i40e_pf *pf = pci_get_drvdata(pdev);
8893 i40e_status ret_code;
8894 u32 reg;
8895 int i;
8896
8897 i40e_dbg_pf_exit(pf);
8898
beb0dff1
JK		 8899 i40e_ptp_stop(pf);
8900
41c445ff
JB		 8901 /* no more scheduling of any task */
8902 set_bit(__I40E_DOWN, &pf->state);
8903 del_timer_sync(&pf->service_timer);
8904 cancel_work_sync(&pf->service_task);
8905
eb2d80bc
MW		 8906 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8907 i40e_free_vfs(pf);
8908 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8909 }
8910
41c445ff
JB		 8911 i40e_fdir_teardown(pf);
8912
8913 /* If there is a switch structure or any orphans, remove them.
8914 * This will leave only the PF's VSI remaining.
8915 */
8916 for (i = 0; i < I40E_MAX_VEB; i++) {
8917 if (!pf->veb[i])
8918 continue;
8919
8920 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8921 pf->veb[i]->uplink_seid == 0)
8922 i40e_switch_branch_release(pf->veb[i]);
8923 }
8924
8925 /* Now we can shutdown the PF's VSI, just before we kill
8926 * adminq and hmc.
8927 */
8928 if (pf->vsi[pf->lan_vsi])
8929 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8930
8931 i40e_stop_misc_vector(pf);
8932 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8933 synchronize_irq(pf->msix_entries[0].vector);
8934 free_irq(pf->msix_entries[0].vector, pf);
8935 }
8936
8937 /* shutdown and destroy the HMC */
60442dea
SN		 8938 if (pf->hw.hmc.hmc_obj) {
8939 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8940 if (ret_code)
8941 dev_warn(&pdev->dev,
8942 "Failed to destroy the HMC resources: %d\n",
8943 ret_code);
8944 }
41c445ff
JB		 8945
8946 /* shutdown the adminq */
41c445ff
JB		 8947 ret_code = i40e_shutdown_adminq(&pf->hw);
8948 if (ret_code)
8949 dev_warn(&pdev->dev,
8950 "Failed to destroy the Admin Queue resources: %d\n",
8951 ret_code);
8952
8953 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8954 i40e_clear_interrupt_scheme(pf);
505682cd 8955 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8956 if (pf->vsi[i]) {
8957 i40e_vsi_clear_rings(pf->vsi[i]);
8958 i40e_vsi_clear(pf->vsi[i]);
8959 pf->vsi[i] = NULL;
8960 }
8961 }
8962
8963 for (i = 0; i < I40E_MAX_VEB; i++) {
8964 kfree(pf->veb[i]);
8965 pf->veb[i] = NULL;
8966 }
8967
8968 kfree(pf->qp_pile);
8969 kfree(pf->irq_pile);
41c445ff
JB		 8970 kfree(pf->vsi);
8971
8972 /* force a PF reset to clean anything leftover */
8973 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8974 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8975 i40e_flush(&pf->hw);
8976
8977 iounmap(pf->hw.hw_addr);
8978 kfree(pf);
8979 pci_release_selected_regions(pdev,
8980 pci_select_bars(pdev, IORESOURCE_MEM));
8981
8982 pci_disable_pcie_error_reporting(pdev);
8983 pci_disable_device(pdev);
8984}
8985
8986/**
8987 * i40e_pci_error_detected - warning that something funky happened in PCI land
8988 * @pdev: PCI device information struct
8989 *
8990 * Called to warn that something happened and the error handling steps
8991 * are in progress. Allows the driver to quiesce things, be ready for
8992 * remediation.
8993 **/
8994static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8995 enum pci_channel_state error)
8996{
8997 struct i40e_pf *pf = pci_get_drvdata(pdev);
8998
8999 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9000
9001 /* shutdown all operations */
9007bccd
SN		 9002 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9003 rtnl_lock();
9004 i40e_prep_for_reset(pf);
9005 rtnl_unlock();
9006 }
41c445ff
JB		 9007
9008 /* Request a slot reset */
9009 return PCI_ERS_RESULT_NEED_RESET;
9010}
9011
9012/**
9013 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9014 * @pdev: PCI device information struct
9015 *
9016 * Called to find if the driver can work with the device now that
9017 * the pci slot has been reset. If a basic connection seems good
9018 * (registers are readable and have sane content) then return a
9019 * happy little PCI_ERS_RESULT_xxx.
9020 **/
9021static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9022{
9023 struct i40e_pf *pf = pci_get_drvdata(pdev);
9024 pci_ers_result_t result;
9025 int err;
9026 u32 reg;
9027
9028 dev_info(&pdev->dev, "%s\n", __func__);
9029 if (pci_enable_device_mem(pdev)) {
9030 dev_info(&pdev->dev,
9031 "Cannot re-enable PCI device after reset.\n");
9032 result = PCI_ERS_RESULT_DISCONNECT;
9033 } else {
9034 pci_set_master(pdev);
9035 pci_restore_state(pdev);
9036 pci_save_state(pdev);
9037 pci_wake_from_d3(pdev, false);
9038
9039 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9040 if (reg == 0)
9041 result = PCI_ERS_RESULT_RECOVERED;
9042 else
9043 result = PCI_ERS_RESULT_DISCONNECT;
9044 }
9045
9046 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9047 if (err) {
9048 dev_info(&pdev->dev,
9049 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9050 err);
9051 /* non-fatal, continue */
9052 }
9053
9054 return result;
9055}
9056
9057/**
9058 * i40e_pci_error_resume - restart operations after PCI error recovery
9059 * @pdev: PCI device information struct
9060 *
9061 * Called to allow the driver to bring things back up after PCI error
9062 * and/or reset recovery has finished.
9063 **/
9064static void i40e_pci_error_resume(struct pci_dev *pdev)
9065{
9066 struct i40e_pf *pf = pci_get_drvdata(pdev);
9067
9068 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9069 if (test_bit(__I40E_SUSPENDED, &pf->state))
9070 return;
9071
9072 rtnl_lock();
41c445ff 9073 i40e_handle_reset_warning(pf);
9007bccd
SN		 9074 rtnl_lock();
9075}
9076
9077/**
9078 * i40e_shutdown - PCI callback for shutting down
9079 * @pdev: PCI device information struct
9080 **/
9081static void i40e_shutdown(struct pci_dev *pdev)
9082{
9083 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9084 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9085
9086 set_bit(__I40E_SUSPENDED, &pf->state);
9087 set_bit(__I40E_DOWN, &pf->state);
9088 rtnl_lock();
9089 i40e_prep_for_reset(pf);
9090 rtnl_unlock();
9091
8e2773ae
SN		 9092 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9093 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9094
9007bccd 9095 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9096 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9097 pci_set_power_state(pdev, PCI_D3hot);
9098 }
9099}
9100
9101#ifdef CONFIG_PM
9102/**
9103 * i40e_suspend - PCI callback for moving to D3
9104 * @pdev: PCI device information struct
9105 **/
9106static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9107{
9108 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9109 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9110
9111 set_bit(__I40E_SUSPENDED, &pf->state);
9112 set_bit(__I40E_DOWN, &pf->state);
9113 rtnl_lock();
9114 i40e_prep_for_reset(pf);
9115 rtnl_unlock();
9116
8e2773ae
SN		 9117 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9118 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9119
9120 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9121 pci_set_power_state(pdev, PCI_D3hot);
9122
9123 return 0;
41c445ff
JB		 9124}
9125
9007bccd
SN		 9126/**
9127 * i40e_resume - PCI callback for waking up from D3
9128 * @pdev: PCI device information struct
9129 **/
9130static int i40e_resume(struct pci_dev *pdev)
9131{
9132 struct i40e_pf *pf = pci_get_drvdata(pdev);
9133 u32 err;
9134
9135 pci_set_power_state(pdev, PCI_D0);
9136 pci_restore_state(pdev);
9137 /* pci_restore_state() clears dev->state_saves, so
9138 * call pci_save_state() again to restore it.
9139 */
9140 pci_save_state(pdev);
9141
9142 err = pci_enable_device_mem(pdev);
9143 if (err) {
9144 dev_err(&pdev->dev,
9145 "%s: Cannot enable PCI device from suspend\n",
9146 __func__);
9147 return err;
9148 }
9149 pci_set_master(pdev);
9150
9151 /* no wakeup events while running */
9152 pci_wake_from_d3(pdev, false);
9153
9154 /* handling the reset will rebuild the device state */
9155 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9156 clear_bit(__I40E_DOWN, &pf->state);
9157 rtnl_lock();
9158 i40e_reset_and_rebuild(pf, false);
9159 rtnl_unlock();
9160 }
9161
9162 return 0;
9163}
9164
9165#endif
41c445ff
JB		 9166static const struct pci_error_handlers i40e_err_handler = {
9167 .error_detected = i40e_pci_error_detected,
9168 .slot_reset = i40e_pci_error_slot_reset,
9169 .resume = i40e_pci_error_resume,
9170};
9171
9172static struct pci_driver i40e_driver = {
9173 .name = i40e_driver_name,
9174 .id_table = i40e_pci_tbl,
9175 .probe = i40e_probe,
9176 .remove = i40e_remove,
9007bccd
SN		 9177#ifdef CONFIG_PM
9178 .suspend = i40e_suspend,
9179 .resume = i40e_resume,
9180#endif
9181 .shutdown = i40e_shutdown,
41c445ff
JB		 9182 .err_handler = &i40e_err_handler,
9183 .sriov_configure = i40e_pci_sriov_configure,
9184};
9185
9186/**
9187 * i40e_init_module - Driver registration routine
9188 *
9189 * i40e_init_module is the first routine called when the driver is
9190 * loaded. All it does is register with the PCI subsystem.
9191 **/
9192static int __init i40e_init_module(void)
9193{
9194 pr_info("%s: %s - version %s\n", i40e_driver_name,
9195 i40e_driver_string, i40e_driver_version_str);
9196 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9197 i40e_dbg_init();
9198 return pci_register_driver(&i40e_driver);
9199}
9200module_init(i40e_init_module);
9201
9202/**
9203 * i40e_exit_module - Driver exit cleanup routine
9204 *
9205 * i40e_exit_module is called just before the driver is removed
9206 * from memory.
9207 **/
9208static void __exit i40e_exit_module(void)
9209{
9210 pci_unregister_driver(&i40e_driver);
9211 i40e_dbg_exit();
9212}
9213module_exit(i40e_exit_module);
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