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i40e: Enable VF Tx bandwidth setting
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
db446094 42#define DRV_VERSION_BUILD 36
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
83
84#define I40E_MAX_VF_COUNT 128
85static int debug = -1;
86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
90MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/**
95 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
96 * @hw: pointer to the HW structure
97 * @mem: ptr to mem struct to fill out
98 * @size: size of memory requested
99 * @alignment: what to align the allocation to
100 **/
101int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
102 u64 size, u32 alignment)
103{
104 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
105
106 mem->size = ALIGN(size, alignment);
107 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
108 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 109 if (!mem->va)
110 return -ENOMEM;
41c445ff 111
93bc73b8 112 return 0;
41c445ff
JB		 113}
114
115/**
116 * i40e_free_dma_mem_d - OS specific memory free for shared code
117 * @hw: pointer to the HW structure
118 * @mem: ptr to mem struct to free
119 **/
120int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
125 mem->va = NULL;
126 mem->pa = 0;
127 mem->size = 0;
128
129 return 0;
130}
131
132/**
133 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
134 * @hw: pointer to the HW structure
135 * @mem: ptr to mem struct to fill out
136 * @size: size of memory requested
137 **/
138int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
139 u32 size)
140{
141 mem->size = size;
142 mem->va = kzalloc(size, GFP_KERNEL);
143
93bc73b8
JB		 144 if (!mem->va)
145 return -ENOMEM;
41c445ff 146
93bc73b8 147 return 0;
41c445ff
JB		 148}
149
150/**
151 * i40e_free_virt_mem_d - OS specific memory free for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to free
154 **/
155int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
156{
157 /* it's ok to kfree a NULL pointer */
158 kfree(mem->va);
159 mem->va = NULL;
160 mem->size = 0;
161
162 return 0;
163}
164
165/**
166 * i40e_get_lump - find a lump of free generic resource
167 * @pf: board private structure
168 * @pile: the pile of resource to search
169 * @needed: the number of items needed
170 * @id: an owner id to stick on the items assigned
171 *
172 * Returns the base item index of the lump, or negative for error
173 *
174 * The search_hint trick and lack of advanced fit-finding only work
175 * because we're highly likely to have all the same size lump requests.
176 * Linear search time and any fragmentation should be minimal.
177 **/
178static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
179 u16 needed, u16 id)
180{
181 int ret = -ENOMEM;
ddf434ac 182 int i, j;
41c445ff
JB		 183
184 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
185 dev_info(&pf->pdev->dev,
186 "param err: pile=%p needed=%d id=0x%04x\n",
187 pile, needed, id);
188 return -EINVAL;
189 }
190
191 /* start the linear search with an imperfect hint */
192 i = pile->search_hint;
ddf434ac 193 while (i < pile->num_entries) {
41c445ff
JB		 194 /* skip already allocated entries */
195 if (pile->list[i] & I40E_PILE_VALID_BIT) {
196 i++;
197 continue;
198 }
199
200 /* do we have enough in this lump? */
201 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
202 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
203 break;
204 }
205
206 if (j == needed) {
207 /* there was enough, so assign it to the requestor */
208 for (j = 0; j < needed; j++)
209 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
210 ret = i;
211 pile->search_hint = i + j;
ddf434ac 212 break;
41c445ff
JB		 213 } else {
214 /* not enough, so skip over it and continue looking */
215 i += j;
216 }
217 }
218
219 return ret;
220}
221
222/**
223 * i40e_put_lump - return a lump of generic resource
224 * @pile: the pile of resource to search
225 * @index: the base item index
226 * @id: the owner id of the items assigned
227 *
228 * Returns the count of items in the lump
229 **/
230static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
231{
232 int valid_id = (id | I40E_PILE_VALID_BIT);
233 int count = 0;
234 int i;
235
236 if (!pile || index >= pile->num_entries)
237 return -EINVAL;
238
239 for (i = index;
240 i < pile->num_entries && pile->list[i] == valid_id;
241 i++) {
242 pile->list[i] = 0;
243 count++;
244 }
245
246 if (count && index < pile->search_hint)
247 pile->search_hint = index;
248
249 return count;
250}
251
252/**
253 * i40e_service_event_schedule - Schedule the service task to wake up
254 * @pf: board private structure
255 *
256 * If not already scheduled, this puts the task into the work queue
257 **/
258static void i40e_service_event_schedule(struct i40e_pf *pf)
259{
260 if (!test_bit(__I40E_DOWN, &pf->state) &&
261 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
262 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
263 schedule_work(&pf->service_task);
264}
265
266/**
267 * i40e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 *
270 * If any port has noticed a Tx timeout, it is likely that the whole
271 * device is munged, not just the one netdev port, so go for the full
272 * reset.
273 **/
274static void i40e_tx_timeout(struct net_device *netdev)
275{
276 struct i40e_netdev_priv *np = netdev_priv(netdev);
277 struct i40e_vsi *vsi = np->vsi;
278 struct i40e_pf *pf = vsi->back;
279
280 pf->tx_timeout_count++;
281
282 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
283 pf->tx_timeout_recovery_level = 0;
284 pf->tx_timeout_last_recovery = jiffies;
285 netdev_info(netdev, "tx_timeout recovery level %d\n",
286 pf->tx_timeout_recovery_level);
287
288 switch (pf->tx_timeout_recovery_level) {
289 case 0:
290 /* disable and re-enable queues for the VSI */
291 if (in_interrupt()) {
292 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
293 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
294 } else {
295 i40e_vsi_reinit_locked(vsi);
296 }
297 break;
298 case 1:
299 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
300 break;
301 case 2:
302 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
303 break;
304 case 3:
305 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
306 break;
307 default:
308 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 309 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 310 i40e_down(vsi);
311 break;
312 }
313 i40e_service_event_schedule(pf);
314 pf->tx_timeout_recovery_level++;
315}
316
317/**
318 * i40e_release_rx_desc - Store the new tail and head values
319 * @rx_ring: ring to bump
320 * @val: new head index
321 **/
322static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
323{
324 rx_ring->next_to_use = val;
325
326 /* Force memory writes to complete before letting h/w
327 * know there are new descriptors to fetch. (Only
328 * applicable for weak-ordered memory model archs,
329 * such as IA-64).
330 */
331 wmb();
332 writel(val, rx_ring->tail);
333}
334
335/**
336 * i40e_get_vsi_stats_struct - Get System Network Statistics
337 * @vsi: the VSI we care about
338 *
339 * Returns the address of the device statistics structure.
340 * The statistics are actually updated from the service task.
341 **/
342struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
343{
344 return &vsi->net_stats;
345}
346
347/**
348 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
349 * @netdev: network interface device structure
350 *
351 * Returns the address of the device statistics structure.
352 * The statistics are actually updated from the service task.
353 **/
354static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
355 struct net_device *netdev,
980e9b11 356 struct rtnl_link_stats64 *stats)
41c445ff
JB		 357{
358 struct i40e_netdev_priv *np = netdev_priv(netdev);
359 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 360 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
361 int i;
362
bc7d338f
ASJ		 363 if (test_bit(__I40E_DOWN, &vsi->state))
364 return stats;
365
3c325ced
JB		 366 if (!vsi->tx_rings)
367 return stats;
368
980e9b11
AD		 369 rcu_read_lock();
370 for (i = 0; i < vsi->num_queue_pairs; i++) {
371 struct i40e_ring *tx_ring, *rx_ring;
372 u64 bytes, packets;
373 unsigned int start;
374
375 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
376 if (!tx_ring)
377 continue;
378
379 do {
57a7744e 380 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 381 packets = tx_ring->stats.packets;
382 bytes = tx_ring->stats.bytes;
57a7744e 383 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 384
385 stats->tx_packets += packets;
386 stats->tx_bytes += bytes;
387 rx_ring = &tx_ring[1];
388
389 do {
57a7744e 390 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 391 packets = rx_ring->stats.packets;
392 bytes = rx_ring->stats.bytes;
57a7744e 393 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 394
980e9b11
AD		 395 stats->rx_packets += packets;
396 stats->rx_bytes += bytes;
397 }
398 rcu_read_unlock();
399
400 /* following stats updated by ixgbe_watchdog_task() */
401 stats->multicast = vsi_stats->multicast;
402 stats->tx_errors = vsi_stats->tx_errors;
403 stats->tx_dropped = vsi_stats->tx_dropped;
404 stats->rx_errors = vsi_stats->rx_errors;
405 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
406 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 407
980e9b11 408 return stats;
41c445ff
JB		 409}
410
411/**
412 * i40e_vsi_reset_stats - Resets all stats of the given vsi
413 * @vsi: the VSI to have its stats reset
414 **/
415void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
416{
417 struct rtnl_link_stats64 *ns;
418 int i;
419
420 if (!vsi)
421 return;
422
423 ns = i40e_get_vsi_stats_struct(vsi);
424 memset(ns, 0, sizeof(*ns));
425 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
426 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
427 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 428 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 429 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 430 memset(&vsi->rx_rings[i]->stats, 0 ,
431 sizeof(vsi->rx_rings[i]->stats));
432 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
433 sizeof(vsi->rx_rings[i]->rx_stats));
434 memset(&vsi->tx_rings[i]->stats, 0 ,
435 sizeof(vsi->tx_rings[i]->stats));
436 memset(&vsi->tx_rings[i]->tx_stats, 0,
437 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 438 }
8e9dca53 439 }
41c445ff
JB		 440 vsi->stat_offsets_loaded = false;
441}
442
443/**
444 * i40e_pf_reset_stats - Reset all of the stats for the given pf
445 * @pf: the PF to be reset
446 **/
447void i40e_pf_reset_stats(struct i40e_pf *pf)
448{
449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
452}
453
454/**
455 * i40e_stat_update48 - read and update a 48 bit stat from the chip
456 * @hw: ptr to the hardware info
457 * @hireg: the high 32 bit reg to read
458 * @loreg: the low 32 bit reg to read
459 * @offset_loaded: has the initial offset been loaded yet
460 * @offset: ptr to current offset value
461 * @stat: ptr to the stat
462 *
463 * Since the device stats are not reset at PFReset, they likely will not
464 * be zeroed when the driver starts. We'll save the first values read
465 * and use them as offsets to be subtracted from the raw values in order
466 * to report stats that count from zero. In the process, we also manage
467 * the potential roll-over.
468 **/
469static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
470 bool offset_loaded, u64 *offset, u64 *stat)
471{
472 u64 new_data;
473
ab60085e 474 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 475 new_data = rd32(hw, loreg);
476 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
477 } else {
478 new_data = rd64(hw, loreg);
479 }
480 if (!offset_loaded)
481 *offset = new_data;
482 if (likely(new_data >= *offset))
483 *stat = new_data - *offset;
484 else
485 *stat = (new_data + ((u64)1 << 48)) - *offset;
486 *stat &= 0xFFFFFFFFFFFFULL;
487}
488
489/**
490 * i40e_stat_update32 - read and update a 32 bit stat from the chip
491 * @hw: ptr to the hardware info
492 * @reg: the hw reg to read
493 * @offset_loaded: has the initial offset been loaded yet
494 * @offset: ptr to current offset value
495 * @stat: ptr to the stat
496 **/
497static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
498 bool offset_loaded, u64 *offset, u64 *stat)
499{
500 u32 new_data;
501
502 new_data = rd32(hw, reg);
503 if (!offset_loaded)
504 *offset = new_data;
505 if (likely(new_data >= *offset))
506 *stat = (u32)(new_data - *offset);
507 else
508 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
509}
510
511/**
512 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
513 * @vsi: the VSI to be updated
514 **/
515void i40e_update_eth_stats(struct i40e_vsi *vsi)
516{
517 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
518 struct i40e_pf *pf = vsi->back;
519 struct i40e_hw *hw = &pf->hw;
520 struct i40e_eth_stats *oes;
521 struct i40e_eth_stats *es; /* device's eth stats */
522
523 es = &vsi->eth_stats;
524 oes = &vsi->eth_stats_offsets;
525
526 /* Gather up the stats that the hw collects */
527 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->tx_errors, &es->tx_errors);
530 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
531 vsi->stat_offsets_loaded,
532 &oes->rx_discards, &es->rx_discards);
533
534 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
535 I40E_GLV_GORCL(stat_idx),
536 vsi->stat_offsets_loaded,
537 &oes->rx_bytes, &es->rx_bytes);
538 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
539 I40E_GLV_UPRCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_unicast, &es->rx_unicast);
542 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
543 I40E_GLV_MPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_multicast, &es->rx_multicast);
546 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
547 I40E_GLV_BPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_broadcast, &es->rx_broadcast);
550
551 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
552 I40E_GLV_GOTCL(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->tx_bytes, &es->tx_bytes);
555 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
556 I40E_GLV_UPTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_unicast, &es->tx_unicast);
559 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
560 I40E_GLV_MPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_multicast, &es->tx_multicast);
563 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
564 I40E_GLV_BPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_broadcast, &es->tx_broadcast);
567 vsi->stat_offsets_loaded = true;
568}
569
570/**
571 * i40e_update_veb_stats - Update Switch component statistics
572 * @veb: the VEB being updated
573 **/
574static void i40e_update_veb_stats(struct i40e_veb *veb)
575{
576 struct i40e_pf *pf = veb->pf;
577 struct i40e_hw *hw = &pf->hw;
578 struct i40e_eth_stats *oes;
579 struct i40e_eth_stats *es; /* device's eth stats */
580 int idx = 0;
581
582 idx = veb->stats_idx;
583 es = &veb->stats;
584 oes = &veb->stats_offsets;
585
586 /* Gather up the stats that the hw collects */
587 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
588 veb->stat_offsets_loaded,
589 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 590 if (hw->revision_id > 0)
591 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
592 veb->stat_offsets_loaded,
593 &oes->rx_unknown_protocol,
594 &es->rx_unknown_protocol);
41c445ff
JB		 595 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_bytes, &es->rx_bytes);
598 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_unicast, &es->rx_unicast);
601 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_multicast, &es->rx_multicast);
604 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->rx_broadcast, &es->rx_broadcast);
607
608 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_bytes, &es->tx_bytes);
611 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_unicast, &es->tx_unicast);
614 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_multicast, &es->tx_multicast);
617 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->tx_broadcast, &es->tx_broadcast);
620 veb->stat_offsets_loaded = true;
621}
622
623/**
624 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
625 * @pf: the corresponding PF
626 *
627 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
628 **/
629static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
630{
631 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
632 struct i40e_hw_port_stats *nsd = &pf->stats;
633 struct i40e_hw *hw = &pf->hw;
634 u64 xoff = 0;
635 u16 i, v;
636
637 if ((hw->fc.current_mode != I40E_FC_FULL) &&
638 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
639 return;
640
641 xoff = nsd->link_xoff_rx;
642 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
643 pf->stat_offsets_loaded,
644 &osd->link_xoff_rx, &nsd->link_xoff_rx);
645
646 /* No new LFC xoff rx */
647 if (!(nsd->link_xoff_rx - xoff))
648 return;
649
650 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
651 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
652 struct i40e_vsi *vsi = pf->vsi[v];
653
654 if (!vsi)
655 continue;
656
657 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 658 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 659 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
660 }
661 }
662}
663
664/**
665 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
666 * @pf: the corresponding PF
667 *
668 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
669 **/
670static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
671{
672 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
673 struct i40e_hw_port_stats *nsd = &pf->stats;
674 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
675 struct i40e_dcbx_config *dcb_cfg;
676 struct i40e_hw *hw = &pf->hw;
677 u16 i, v;
678 u8 tc;
679
680 dcb_cfg = &hw->local_dcbx_config;
681
682 /* See if DCB enabled with PFC TC */
683 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
684 !(dcb_cfg->pfc.pfcenable)) {
685 i40e_update_link_xoff_rx(pf);
686 return;
687 }
688
689 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
690 u64 prio_xoff = nsd->priority_xoff_rx[i];
691 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
692 pf->stat_offsets_loaded,
693 &osd->priority_xoff_rx[i],
694 &nsd->priority_xoff_rx[i]);
695
696 /* No new PFC xoff rx */
697 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
698 continue;
699 /* Get the TC for given priority */
700 tc = dcb_cfg->etscfg.prioritytable[i];
701 xoff[tc] = true;
702 }
703
704 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
705 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
706 struct i40e_vsi *vsi = pf->vsi[v];
707
708 if (!vsi)
709 continue;
710
711 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 712 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 713
714 tc = ring->dcb_tc;
715 if (xoff[tc])
716 clear_bit(__I40E_HANG_CHECK_ARMED,
717 &ring->state);
718 }
719 }
720}
721
722/**
723 * i40e_update_stats - Update the board statistics counters.
724 * @vsi: the VSI to be updated
725 *
726 * There are a few instances where we store the same stat in a
727 * couple of different structs. This is partly because we have
728 * the netdev stats that need to be filled out, which is slightly
729 * different from the "eth_stats" defined by the chip and used in
730 * VF communications. We sort it all out here in a central place.
731 **/
732void i40e_update_stats(struct i40e_vsi *vsi)
733{
734 struct i40e_pf *pf = vsi->back;
735 struct i40e_hw *hw = &pf->hw;
736 struct rtnl_link_stats64 *ons;
737 struct rtnl_link_stats64 *ns; /* netdev stats */
738 struct i40e_eth_stats *oes;
739 struct i40e_eth_stats *es; /* device's eth stats */
740 u32 tx_restart, tx_busy;
741 u32 rx_page, rx_buf;
742 u64 rx_p, rx_b;
743 u64 tx_p, tx_b;
bee5af7e 744 u32 val;
41c445ff
JB		 745 int i;
746 u16 q;
747
748 if (test_bit(__I40E_DOWN, &vsi->state) ||
749 test_bit(__I40E_CONFIG_BUSY, &pf->state))
750 return;
751
752 ns = i40e_get_vsi_stats_struct(vsi);
753 ons = &vsi->net_stats_offsets;
754 es = &vsi->eth_stats;
755 oes = &vsi->eth_stats_offsets;
756
757 /* Gather up the netdev and vsi stats that the driver collects
758 * on the fly during packet processing
759 */
760 rx_b = rx_p = 0;
761 tx_b = tx_p = 0;
762 tx_restart = tx_busy = 0;
763 rx_page = 0;
764 rx_buf = 0;
980e9b11 765 rcu_read_lock();
41c445ff
JB		 766 for (q = 0; q < vsi->num_queue_pairs; q++) {
767 struct i40e_ring *p;
980e9b11
AD		 768 u64 bytes, packets;
769 unsigned int start;
770
771 /* locate Tx ring */
772 p = ACCESS_ONCE(vsi->tx_rings[q]);
773
774 do {
57a7744e 775 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 776 packets = p->stats.packets;
777 bytes = p->stats.bytes;
57a7744e 778 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 779 tx_b += bytes;
780 tx_p += packets;
781 tx_restart += p->tx_stats.restart_queue;
782 tx_busy += p->tx_stats.tx_busy;
41c445ff 783
980e9b11
AD		 784 /* Rx queue is part of the same block as Tx queue */
785 p = &p[1];
786 do {
57a7744e 787 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 788 packets = p->stats.packets;
789 bytes = p->stats.bytes;
57a7744e 790 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 791 rx_b += bytes;
792 rx_p += packets;
420136cc
MW		 793 rx_buf += p->rx_stats.alloc_buff_failed;
794 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 795 }
980e9b11 796 rcu_read_unlock();
41c445ff
JB		 797 vsi->tx_restart = tx_restart;
798 vsi->tx_busy = tx_busy;
799 vsi->rx_page_failed = rx_page;
800 vsi->rx_buf_failed = rx_buf;
801
802 ns->rx_packets = rx_p;
803 ns->rx_bytes = rx_b;
804 ns->tx_packets = tx_p;
805 ns->tx_bytes = tx_b;
806
807 i40e_update_eth_stats(vsi);
808 /* update netdev stats from eth stats */
809 ons->rx_errors = oes->rx_errors;
810 ns->rx_errors = es->rx_errors;
811 ons->tx_errors = oes->tx_errors;
812 ns->tx_errors = es->tx_errors;
813 ons->multicast = oes->rx_multicast;
814 ns->multicast = es->rx_multicast;
815 ons->tx_dropped = oes->tx_discards;
816 ns->tx_dropped = es->tx_discards;
817
818 /* Get the port data only if this is the main PF VSI */
819 if (vsi == pf->vsi[pf->lan_vsi]) {
820 struct i40e_hw_port_stats *nsd = &pf->stats;
821 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
822
823 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
824 I40E_GLPRT_GORCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
827 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
828 I40E_GLPRT_GOTCL(hw->port),
829 pf->stat_offsets_loaded,
830 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
831 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.rx_discards,
834 &nsd->eth.rx_discards);
835 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
836 pf->stat_offsets_loaded,
837 &osd->eth.tx_discards,
838 &nsd->eth.tx_discards);
839 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
840 I40E_GLPRT_MPRCL(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->eth.rx_multicast,
843 &nsd->eth.rx_multicast);
844
845 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
846 pf->stat_offsets_loaded,
847 &osd->tx_dropped_link_down,
848 &nsd->tx_dropped_link_down);
849
850 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->crc_errors, &nsd->crc_errors);
853 ns->rx_crc_errors = nsd->crc_errors;
854
855 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
856 pf->stat_offsets_loaded,
857 &osd->illegal_bytes, &nsd->illegal_bytes);
858 ns->rx_errors = nsd->crc_errors
859 + nsd->illegal_bytes;
860
861 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_local_faults,
864 &nsd->mac_local_faults);
865 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
866 pf->stat_offsets_loaded,
867 &osd->mac_remote_faults,
868 &nsd->mac_remote_faults);
869
870 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
871 pf->stat_offsets_loaded,
872 &osd->rx_length_errors,
873 &nsd->rx_length_errors);
874 ns->rx_length_errors = nsd->rx_length_errors;
875
876 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
877 pf->stat_offsets_loaded,
878 &osd->link_xon_rx, &nsd->link_xon_rx);
879 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xon_tx, &nsd->link_xon_tx);
882 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
883 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
884 pf->stat_offsets_loaded,
885 &osd->link_xoff_tx, &nsd->link_xoff_tx);
886
887 for (i = 0; i < 8; i++) {
888 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_rx[i],
891 &nsd->priority_xon_rx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xon_tx[i],
895 &nsd->priority_xon_tx[i]);
896 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
897 pf->stat_offsets_loaded,
898 &osd->priority_xoff_tx[i],
899 &nsd->priority_xoff_tx[i]);
900 i40e_stat_update32(hw,
901 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
902 pf->stat_offsets_loaded,
903 &osd->priority_xon_2_xoff[i],
904 &nsd->priority_xon_2_xoff[i]);
905 }
906
907 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
908 I40E_GLPRT_PRC64L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_64, &nsd->rx_size_64);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
912 I40E_GLPRT_PRC127L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_127, &nsd->rx_size_127);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
916 I40E_GLPRT_PRC255L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_255, &nsd->rx_size_255);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
920 I40E_GLPRT_PRC511L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_511, &nsd->rx_size_511);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
924 I40E_GLPRT_PRC1023L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1023, &nsd->rx_size_1023);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
928 I40E_GLPRT_PRC1522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_1522, &nsd->rx_size_1522);
931 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
932 I40E_GLPRT_PRC9522L(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->rx_size_big, &nsd->rx_size_big);
935
936 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
937 I40E_GLPRT_PTC64L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_64, &nsd->tx_size_64);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
941 I40E_GLPRT_PTC127L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_127, &nsd->tx_size_127);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
945 I40E_GLPRT_PTC255L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_255, &nsd->tx_size_255);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
949 I40E_GLPRT_PTC511L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_511, &nsd->tx_size_511);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
953 I40E_GLPRT_PTC1023L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1023, &nsd->tx_size_1023);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
957 I40E_GLPRT_PTC1522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_1522, &nsd->tx_size_1522);
960 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
961 I40E_GLPRT_PTC9522L(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->tx_size_big, &nsd->tx_size_big);
964
965 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->rx_undersize, &nsd->rx_undersize);
968 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
969 pf->stat_offsets_loaded,
970 &osd->rx_fragments, &nsd->rx_fragments);
971 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->rx_oversize, &nsd->rx_oversize);
974 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->rx_jabber, &nsd->rx_jabber);
bee5af7e
ASJ		 977
978 val = rd32(hw, I40E_PRTPM_EEE_STAT);
979 nsd->tx_lpi_status =
980 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
981 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
982 nsd->rx_lpi_status =
983 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
984 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
985 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
986 pf->stat_offsets_loaded,
987 &osd->tx_lpi_count, &nsd->tx_lpi_count);
988 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
989 pf->stat_offsets_loaded,
990 &osd->rx_lpi_count, &nsd->rx_lpi_count);
41c445ff
JB		 991 }
992
993 pf->stat_offsets_loaded = true;
994}
995
996/**
997 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
998 * @vsi: the VSI to be searched
999 * @macaddr: the MAC address
1000 * @vlan: the vlan
1001 * @is_vf: make sure its a vf filter, else doesn't matter
1002 * @is_netdev: make sure its a netdev filter, else doesn't matter
1003 *
1004 * Returns ptr to the filter object or NULL
1005 **/
1006static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1007 u8 *macaddr, s16 vlan,
1008 bool is_vf, bool is_netdev)
1009{
1010 struct i40e_mac_filter *f;
1011
1012 if (!vsi || !macaddr)
1013 return NULL;
1014
1015 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1016 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1017 (vlan == f->vlan) &&
1018 (!is_vf || f->is_vf) &&
1019 (!is_netdev || f->is_netdev))
1020 return f;
1021 }
1022 return NULL;
1023}
1024
1025/**
1026 * i40e_find_mac - Find a mac addr in the macvlan filters list
1027 * @vsi: the VSI to be searched
1028 * @macaddr: the MAC address we are searching for
1029 * @is_vf: make sure its a vf filter, else doesn't matter
1030 * @is_netdev: make sure its a netdev filter, else doesn't matter
1031 *
1032 * Returns the first filter with the provided MAC address or NULL if
1033 * MAC address was not found
1034 **/
1035struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1036 bool is_vf, bool is_netdev)
1037{
1038 struct i40e_mac_filter *f;
1039
1040 if (!vsi || !macaddr)
1041 return NULL;
1042
1043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1044 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1045 (!is_vf || f->is_vf) &&
1046 (!is_netdev || f->is_netdev))
1047 return f;
1048 }
1049 return NULL;
1050}
1051
1052/**
1053 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1054 * @vsi: the VSI to be searched
1055 *
1056 * Returns true if VSI is in vlan mode or false otherwise
1057 **/
1058bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1059{
1060 struct i40e_mac_filter *f;
1061
1062 /* Only -1 for all the filters denotes not in vlan mode
1063 * so we have to go through all the list in order to make sure
1064 */
1065 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1066 if (f->vlan >= 0)
1067 return true;
1068 }
1069
1070 return false;
1071}
1072
1073/**
1074 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1075 * @vsi: the VSI to be searched
1076 * @macaddr: the mac address to be filtered
1077 * @is_vf: true if it is a vf
1078 * @is_netdev: true if it is a netdev
1079 *
1080 * Goes through all the macvlan filters and adds a
1081 * macvlan filter for each unique vlan that already exists
1082 *
1083 * Returns first filter found on success, else NULL
1084 **/
1085struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1086 bool is_vf, bool is_netdev)
1087{
1088 struct i40e_mac_filter *f;
1089
1090 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1091 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1092 is_vf, is_netdev)) {
1093 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1094 is_vf, is_netdev))
41c445ff
JB		 1095 return NULL;
1096 }
1097 }
1098
1099 return list_first_entry_or_null(&vsi->mac_filter_list,
1100 struct i40e_mac_filter, list);
1101}
1102
1103/**
1104 * i40e_add_filter - Add a mac/vlan filter to the VSI
1105 * @vsi: the VSI to be searched
1106 * @macaddr: the MAC address
1107 * @vlan: the vlan
1108 * @is_vf: make sure its a vf filter, else doesn't matter
1109 * @is_netdev: make sure its a netdev filter, else doesn't matter
1110 *
1111 * Returns ptr to the filter object or NULL when no memory available.
1112 **/
1113struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1114 u8 *macaddr, s16 vlan,
1115 bool is_vf, bool is_netdev)
1116{
1117 struct i40e_mac_filter *f;
1118
1119 if (!vsi || !macaddr)
1120 return NULL;
1121
1122 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1123 if (!f) {
1124 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1125 if (!f)
1126 goto add_filter_out;
1127
1128 memcpy(f->macaddr, macaddr, ETH_ALEN);
1129 f->vlan = vlan;
1130 f->changed = true;
1131
1132 INIT_LIST_HEAD(&f->list);
1133 list_add(&f->list, &vsi->mac_filter_list);
1134 }
1135
1136 /* increment counter and add a new flag if needed */
1137 if (is_vf) {
1138 if (!f->is_vf) {
1139 f->is_vf = true;
1140 f->counter++;
1141 }
1142 } else if (is_netdev) {
1143 if (!f->is_netdev) {
1144 f->is_netdev = true;
1145 f->counter++;
1146 }
1147 } else {
1148 f->counter++;
1149 }
1150
1151 /* changed tells sync_filters_subtask to
1152 * push the filter down to the firmware
1153 */
1154 if (f->changed) {
1155 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1156 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1157 }
1158
1159add_filter_out:
1160 return f;
1161}
1162
1163/**
1164 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1165 * @vsi: the VSI to be searched
1166 * @macaddr: the MAC address
1167 * @vlan: the vlan
1168 * @is_vf: make sure it's a vf filter, else doesn't matter
1169 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1170 **/
1171void i40e_del_filter(struct i40e_vsi *vsi,
1172 u8 *macaddr, s16 vlan,
1173 bool is_vf, bool is_netdev)
1174{
1175 struct i40e_mac_filter *f;
1176
1177 if (!vsi || !macaddr)
1178 return;
1179
1180 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1181 if (!f || f->counter == 0)
1182 return;
1183
1184 if (is_vf) {
1185 if (f->is_vf) {
1186 f->is_vf = false;
1187 f->counter--;
1188 }
1189 } else if (is_netdev) {
1190 if (f->is_netdev) {
1191 f->is_netdev = false;
1192 f->counter--;
1193 }
1194 } else {
1195 /* make sure we don't remove a filter in use by vf or netdev */
1196 int min_f = 0;
1197 min_f += (f->is_vf ? 1 : 0);
1198 min_f += (f->is_netdev ? 1 : 0);
1199
1200 if (f->counter > min_f)
1201 f->counter--;
1202 }
1203
1204 /* counter == 0 tells sync_filters_subtask to
1205 * remove the filter from the firmware's list
1206 */
1207 if (f->counter == 0) {
1208 f->changed = true;
1209 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1210 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1211 }
1212}
1213
1214/**
1215 * i40e_set_mac - NDO callback to set mac address
1216 * @netdev: network interface device structure
1217 * @p: pointer to an address structure
1218 *
1219 * Returns 0 on success, negative on failure
1220 **/
1221static int i40e_set_mac(struct net_device *netdev, void *p)
1222{
1223 struct i40e_netdev_priv *np = netdev_priv(netdev);
1224 struct i40e_vsi *vsi = np->vsi;
1225 struct sockaddr *addr = p;
1226 struct i40e_mac_filter *f;
1227
1228 if (!is_valid_ether_addr(addr->sa_data))
1229 return -EADDRNOTAVAIL;
1230
1231 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1232
1233 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1234 return 0;
1235
80f6428f
ASJ		 1236 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1237 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1238 return -EADDRNOTAVAIL;
1239
41c445ff
JB		 1240 if (vsi->type == I40E_VSI_MAIN) {
1241 i40e_status ret;
1242 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1243 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1244 addr->sa_data, NULL);
1245 if (ret) {
1246 netdev_info(netdev,
1247 "Addr change for Main VSI failed: %d\n",
1248 ret);
1249 return -EADDRNOTAVAIL;
1250 }
1251
1252 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1253 }
1254
1255 /* In order to be sure to not drop any packets, add the new address
1256 * then delete the old one.
1257 */
1258 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1259 if (!f)
1260 return -ENOMEM;
1261
1262 i40e_sync_vsi_filters(vsi);
1263 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1264 i40e_sync_vsi_filters(vsi);
1265
1266 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1267
1268 return 0;
1269}
1270
1271/**
1272 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1273 * @vsi: the VSI being setup
1274 * @ctxt: VSI context structure
1275 * @enabled_tc: Enabled TCs bitmap
1276 * @is_add: True if called before Add VSI
1277 *
1278 * Setup VSI queue mapping for enabled traffic classes.
1279 **/
1280static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1281 struct i40e_vsi_context *ctxt,
1282 u8 enabled_tc,
1283 bool is_add)
1284{
1285 struct i40e_pf *pf = vsi->back;
1286 u16 sections = 0;
1287 u8 netdev_tc = 0;
1288 u16 numtc = 0;
1289 u16 qcount;
1290 u8 offset;
1291 u16 qmap;
1292 int i;
4e3b35b0 1293 u16 num_tc_qps = 0;
41c445ff
JB		 1294
1295 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1296 offset = 0;
1297
1298 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1299 /* Find numtc from enabled TC bitmap */
1300 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1301 if (enabled_tc & (1 << i)) /* TC is enabled */
1302 numtc++;
1303 }
1304 if (!numtc) {
1305 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1306 numtc = 1;
1307 }
1308 } else {
1309 /* At least TC0 is enabled in case of non-DCB case */
1310 numtc = 1;
1311 }
1312
1313 vsi->tc_config.numtc = numtc;
1314 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1315 /* Number of queues per enabled TC */
1316 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1317 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1318
1319 /* Setup queue offset/count for all TCs for given VSI */
1320 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1321 /* See if the given TC is enabled for the given VSI */
1322 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1323 int pow, num_qps;
1324
41c445ff
JB		 1325 switch (vsi->type) {
1326 case I40E_VSI_MAIN:
4e3b35b0 1327 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1328 break;
1329 case I40E_VSI_FDIR:
1330 case I40E_VSI_SRIOV:
1331 case I40E_VSI_VMDQ2:
1332 default:
4e3b35b0 1333 qcount = num_tc_qps;
41c445ff
JB		 1334 WARN_ON(i != 0);
1335 break;
1336 }
4e3b35b0
NP		 1337 vsi->tc_config.tc_info[i].qoffset = offset;
1338 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1339
1340 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1341 num_qps = qcount;
41c445ff 1342 pow = 0;
4e3b35b0 1343 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1344 pow++;
1345 num_qps >>= 1;
1346 }
1347
1348 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1349 qmap =
1350 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1351 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1352
4e3b35b0 1353 offset += qcount;
41c445ff
JB		 1354 } else {
1355 /* TC is not enabled so set the offset to
1356 * default queue and allocate one queue
1357 * for the given TC.
1358 */
1359 vsi->tc_config.tc_info[i].qoffset = 0;
1360 vsi->tc_config.tc_info[i].qcount = 1;
1361 vsi->tc_config.tc_info[i].netdev_tc = 0;
1362
1363 qmap = 0;
1364 }
1365 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1366 }
1367
1368 /* Set actual Tx/Rx queue pairs */
1369 vsi->num_queue_pairs = offset;
1370
1371 /* Scheduler section valid can only be set for ADD VSI */
1372 if (is_add) {
1373 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1374
1375 ctxt->info.up_enable_bits = enabled_tc;
1376 }
1377 if (vsi->type == I40E_VSI_SRIOV) {
1378 ctxt->info.mapping_flags |=
1379 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1380 for (i = 0; i < vsi->num_queue_pairs; i++)
1381 ctxt->info.queue_mapping[i] =
1382 cpu_to_le16(vsi->base_queue + i);
1383 } else {
1384 ctxt->info.mapping_flags |=
1385 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1386 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1387 }
1388 ctxt->info.valid_sections |= cpu_to_le16(sections);
1389}
1390
1391/**
1392 * i40e_set_rx_mode - NDO callback to set the netdev filters
1393 * @netdev: network interface device structure
1394 **/
1395static void i40e_set_rx_mode(struct net_device *netdev)
1396{
1397 struct i40e_netdev_priv *np = netdev_priv(netdev);
1398 struct i40e_mac_filter *f, *ftmp;
1399 struct i40e_vsi *vsi = np->vsi;
1400 struct netdev_hw_addr *uca;
1401 struct netdev_hw_addr *mca;
1402 struct netdev_hw_addr *ha;
1403
1404 /* add addr if not already in the filter list */
1405 netdev_for_each_uc_addr(uca, netdev) {
1406 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1407 if (i40e_is_vsi_in_vlan(vsi))
1408 i40e_put_mac_in_vlan(vsi, uca->addr,
1409 false, true);
1410 else
1411 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1412 false, true);
1413 }
1414 }
1415
1416 netdev_for_each_mc_addr(mca, netdev) {
1417 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1418 if (i40e_is_vsi_in_vlan(vsi))
1419 i40e_put_mac_in_vlan(vsi, mca->addr,
1420 false, true);
1421 else
1422 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1423 false, true);
1424 }
1425 }
1426
1427 /* remove filter if not in netdev list */
1428 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1429 bool found = false;
1430
1431 if (!f->is_netdev)
1432 continue;
1433
1434 if (is_multicast_ether_addr(f->macaddr)) {
1435 netdev_for_each_mc_addr(mca, netdev) {
1436 if (ether_addr_equal(mca->addr, f->macaddr)) {
1437 found = true;
1438 break;
1439 }
1440 }
1441 } else {
1442 netdev_for_each_uc_addr(uca, netdev) {
1443 if (ether_addr_equal(uca->addr, f->macaddr)) {
1444 found = true;
1445 break;
1446 }
1447 }
1448
1449 for_each_dev_addr(netdev, ha) {
1450 if (ether_addr_equal(ha->addr, f->macaddr)) {
1451 found = true;
1452 break;
1453 }
1454 }
1455 }
1456 if (!found)
1457 i40e_del_filter(
1458 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1459 }
1460
1461 /* check for other flag changes */
1462 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1463 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1464 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1465 }
1466}
1467
1468/**
1469 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1470 * @vsi: ptr to the VSI
1471 *
1472 * Push any outstanding VSI filter changes through the AdminQ.
1473 *
1474 * Returns 0 or error value
1475 **/
1476int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1477{
1478 struct i40e_mac_filter *f, *ftmp;
1479 bool promisc_forced_on = false;
1480 bool add_happened = false;
1481 int filter_list_len = 0;
1482 u32 changed_flags = 0;
dcae29be 1483 i40e_status aq_ret = 0;
41c445ff
JB		 1484 struct i40e_pf *pf;
1485 int num_add = 0;
1486 int num_del = 0;
1487 u16 cmd_flags;
1488
1489 /* empty array typed pointers, kcalloc later */
1490 struct i40e_aqc_add_macvlan_element_data *add_list;
1491 struct i40e_aqc_remove_macvlan_element_data *del_list;
1492
1493 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1494 usleep_range(1000, 2000);
1495 pf = vsi->back;
1496
1497 if (vsi->netdev) {
1498 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1499 vsi->current_netdev_flags = vsi->netdev->flags;
1500 }
1501
1502 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1503 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1504
1505 filter_list_len = pf->hw.aq.asq_buf_size /
1506 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1507 del_list = kcalloc(filter_list_len,
1508 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1509 GFP_KERNEL);
1510 if (!del_list)
1511 return -ENOMEM;
1512
1513 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1514 if (!f->changed)
1515 continue;
1516
1517 if (f->counter != 0)
1518 continue;
1519 f->changed = false;
1520 cmd_flags = 0;
1521
1522 /* add to delete list */
1523 memcpy(del_list[num_del].mac_addr,
1524 f->macaddr, ETH_ALEN);
1525 del_list[num_del].vlan_tag =
1526 cpu_to_le16((u16)(f->vlan ==
1527 I40E_VLAN_ANY ? 0 : f->vlan));
1528
41c445ff
JB		 1529 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1530 del_list[num_del].flags = cmd_flags;
1531 num_del++;
1532
1533 /* unlink from filter list */
1534 list_del(&f->list);
1535 kfree(f);
1536
1537 /* flush a full buffer */
1538 if (num_del == filter_list_len) {
dcae29be 1539 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1540 vsi->seid, del_list, num_del,
1541 NULL);
1542 num_del = 0;
1543 memset(del_list, 0, sizeof(*del_list));
1544
dcae29be 1545 if (aq_ret)
41c445ff
JB		 1546 dev_info(&pf->pdev->dev,
1547 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1548 aq_ret,
41c445ff
JB		 1549 pf->hw.aq.asq_last_status);
1550 }
1551 }
1552 if (num_del) {
dcae29be 1553 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1554 del_list, num_del, NULL);
1555 num_del = 0;
1556
dcae29be 1557 if (aq_ret)
41c445ff
JB		 1558 dev_info(&pf->pdev->dev,
1559 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1560 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1561 }
1562
1563 kfree(del_list);
1564 del_list = NULL;
1565
1566 /* do all the adds now */
1567 filter_list_len = pf->hw.aq.asq_buf_size /
1568 sizeof(struct i40e_aqc_add_macvlan_element_data),
1569 add_list = kcalloc(filter_list_len,
1570 sizeof(struct i40e_aqc_add_macvlan_element_data),
1571 GFP_KERNEL);
1572 if (!add_list)
1573 return -ENOMEM;
1574
1575 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1576 if (!f->changed)
1577 continue;
1578
1579 if (f->counter == 0)
1580 continue;
1581 f->changed = false;
1582 add_happened = true;
1583 cmd_flags = 0;
1584
1585 /* add to add array */
1586 memcpy(add_list[num_add].mac_addr,
1587 f->macaddr, ETH_ALEN);
1588 add_list[num_add].vlan_tag =
1589 cpu_to_le16(
1590 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1591 add_list[num_add].queue_number = 0;
1592
1593 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1594 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1595 num_add++;
1596
1597 /* flush a full buffer */
1598 if (num_add == filter_list_len) {
dcae29be
JB		 1599 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1600 add_list, num_add,
1601 NULL);
41c445ff
JB		 1602 num_add = 0;
1603
dcae29be 1604 if (aq_ret)
41c445ff
JB		 1605 break;
1606 memset(add_list, 0, sizeof(*add_list));
1607 }
1608 }
1609 if (num_add) {
dcae29be
JB		 1610 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1611 add_list, num_add, NULL);
41c445ff
JB		 1612 num_add = 0;
1613 }
1614 kfree(add_list);
1615 add_list = NULL;
1616
dcae29be 1617 if (add_happened && (!aq_ret)) {
41c445ff 1618 /* do nothing */;
dcae29be 1619 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1620 dev_info(&pf->pdev->dev,
1621 "add filter failed, err %d, aq_err %d\n",
dcae29be 1622 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1623 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1624 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1625 &vsi->state)) {
1626 promisc_forced_on = true;
1627 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1628 &vsi->state);
1629 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1630 }
1631 }
1632 }
1633
1634 /* check for changes in promiscuous modes */
1635 if (changed_flags & IFF_ALLMULTI) {
1636 bool cur_multipromisc;
1637 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1638 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1639 vsi->seid,
1640 cur_multipromisc,
1641 NULL);
1642 if (aq_ret)
41c445ff
JB		 1643 dev_info(&pf->pdev->dev,
1644 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1645 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1646 }
1647 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1648 bool cur_promisc;
1649 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1650 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1651 &vsi->state));
dcae29be
JB		 1652 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1653 vsi->seid,
1654 cur_promisc, NULL);
1655 if (aq_ret)
41c445ff
JB		 1656 dev_info(&pf->pdev->dev,
1657 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1658 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1659 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1660 vsi->seid,
1661 cur_promisc, NULL);
1662 if (aq_ret)
1663 dev_info(&pf->pdev->dev,
1664 "set brdcast promisc failed, err %d, aq_err %d\n",
1665 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1666 }
1667
1668 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1669 return 0;
1670}
1671
1672/**
1673 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1674 * @pf: board private structure
1675 **/
1676static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1677{
1678 int v;
1679
1680 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1681 return;
1682 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1683
1684 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1685 if (pf->vsi[v] &&
1686 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1687 i40e_sync_vsi_filters(pf->vsi[v]);
1688 }
1689}
1690
1691/**
1692 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1693 * @netdev: network interface device structure
1694 * @new_mtu: new value for maximum frame size
1695 *
1696 * Returns 0 on success, negative on failure
1697 **/
1698static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1699{
1700 struct i40e_netdev_priv *np = netdev_priv(netdev);
1701 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1702 struct i40e_vsi *vsi = np->vsi;
1703
1704 /* MTU < 68 is an error and causes problems on some kernels */
1705 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1706 return -EINVAL;
1707
1708 netdev_info(netdev, "changing MTU from %d to %d\n",
1709 netdev->mtu, new_mtu);
1710 netdev->mtu = new_mtu;
1711 if (netif_running(netdev))
1712 i40e_vsi_reinit_locked(vsi);
1713
1714 return 0;
1715}
1716
beb0dff1
JK		 1717/**
1718 * i40e_ioctl - Access the hwtstamp interface
1719 * @netdev: network interface device structure
1720 * @ifr: interface request data
1721 * @cmd: ioctl command
1722 **/
1723int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1724{
1725 struct i40e_netdev_priv *np = netdev_priv(netdev);
1726 struct i40e_pf *pf = np->vsi->back;
1727
1728 switch (cmd) {
1729 case SIOCGHWTSTAMP:
1730 return i40e_ptp_get_ts_config(pf, ifr);
1731 case SIOCSHWTSTAMP:
1732 return i40e_ptp_set_ts_config(pf, ifr);
1733 default:
1734 return -EOPNOTSUPP;
1735 }
1736}
1737
41c445ff
JB		 1738/**
1739 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1740 * @vsi: the vsi being adjusted
1741 **/
1742void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1743{
1744 struct i40e_vsi_context ctxt;
1745 i40e_status ret;
1746
1747 if ((vsi->info.valid_sections &
1748 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1749 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1750 return; /* already enabled */
1751
1752 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1753 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1754 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1755
1756 ctxt.seid = vsi->seid;
1757 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1758 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1759 if (ret) {
1760 dev_info(&vsi->back->pdev->dev,
1761 "%s: update vsi failed, aq_err=%d\n",
1762 __func__, vsi->back->hw.aq.asq_last_status);
1763 }
1764}
1765
1766/**
1767 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1768 * @vsi: the vsi being adjusted
1769 **/
1770void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1771{
1772 struct i40e_vsi_context ctxt;
1773 i40e_status ret;
1774
1775 if ((vsi->info.valid_sections &
1776 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1777 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1778 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1779 return; /* already disabled */
1780
1781 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1782 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1783 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1784
1785 ctxt.seid = vsi->seid;
1786 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1787 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1788 if (ret) {
1789 dev_info(&vsi->back->pdev->dev,
1790 "%s: update vsi failed, aq_err=%d\n",
1791 __func__, vsi->back->hw.aq.asq_last_status);
1792 }
1793}
1794
1795/**
1796 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1797 * @netdev: network interface to be adjusted
1798 * @features: netdev features to test if VLAN offload is enabled or not
1799 **/
1800static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1801{
1802 struct i40e_netdev_priv *np = netdev_priv(netdev);
1803 struct i40e_vsi *vsi = np->vsi;
1804
1805 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1806 i40e_vlan_stripping_enable(vsi);
1807 else
1808 i40e_vlan_stripping_disable(vsi);
1809}
1810
1811/**
1812 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1813 * @vsi: the vsi being configured
1814 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1815 **/
1816int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1817{
1818 struct i40e_mac_filter *f, *add_f;
1819 bool is_netdev, is_vf;
41c445ff
JB		 1820
1821 is_vf = (vsi->type == I40E_VSI_SRIOV);
1822 is_netdev = !!(vsi->netdev);
1823
1824 if (is_netdev) {
1825 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1826 is_vf, is_netdev);
1827 if (!add_f) {
1828 dev_info(&vsi->back->pdev->dev,
1829 "Could not add vlan filter %d for %pM\n",
1830 vid, vsi->netdev->dev_addr);
1831 return -ENOMEM;
1832 }
1833 }
1834
1835 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1836 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1837 if (!add_f) {
1838 dev_info(&vsi->back->pdev->dev,
1839 "Could not add vlan filter %d for %pM\n",
1840 vid, f->macaddr);
1841 return -ENOMEM;
1842 }
1843 }
1844
41c445ff
JB		 1845 /* Now if we add a vlan tag, make sure to check if it is the first
1846 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1847 * with 0, so we now accept untagged and specified tagged traffic
1848 * (and not any taged and untagged)
1849 */
1850 if (vid > 0) {
1851 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1852 I40E_VLAN_ANY,
1853 is_vf, is_netdev)) {
1854 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1855 I40E_VLAN_ANY, is_vf, is_netdev);
1856 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1857 is_vf, is_netdev);
1858 if (!add_f) {
1859 dev_info(&vsi->back->pdev->dev,
1860 "Could not add filter 0 for %pM\n",
1861 vsi->netdev->dev_addr);
1862 return -ENOMEM;
1863 }
1864 }
8d82a7c5 1865 }
41c445ff 1866
8d82a7c5
GR		 1867 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1868 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1869 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1870 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1871 is_vf, is_netdev)) {
1872 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1873 is_vf, is_netdev);
1874 add_f = i40e_add_filter(vsi, f->macaddr,
1875 0, is_vf, is_netdev);
1876 if (!add_f) {
1877 dev_info(&vsi->back->pdev->dev,
1878 "Could not add filter 0 for %pM\n",
1879 f->macaddr);
1880 return -ENOMEM;
1881 }
1882 }
1883 }
41c445ff
JB		 1884 }
1885
80f6428f
ASJ		 1886 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1887 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1888 return 0;
1889
1890 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1891}
1892
1893/**
1894 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1895 * @vsi: the vsi being configured
1896 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1897 *
1898 * Return: 0 on success or negative otherwise
41c445ff
JB		 1899 **/
1900int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1901{
1902 struct net_device *netdev = vsi->netdev;
1903 struct i40e_mac_filter *f, *add_f;
1904 bool is_vf, is_netdev;
1905 int filter_count = 0;
41c445ff
JB		 1906
1907 is_vf = (vsi->type == I40E_VSI_SRIOV);
1908 is_netdev = !!(netdev);
1909
1910 if (is_netdev)
1911 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1912
1913 list_for_each_entry(f, &vsi->mac_filter_list, list)
1914 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1915
41c445ff
JB		 1916 /* go through all the filters for this VSI and if there is only
1917 * vid == 0 it means there are no other filters, so vid 0 must
1918 * be replaced with -1. This signifies that we should from now
1919 * on accept any traffic (with any tag present, or untagged)
1920 */
1921 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1922 if (is_netdev) {
1923 if (f->vlan &&
1924 ether_addr_equal(netdev->dev_addr, f->macaddr))
1925 filter_count++;
1926 }
1927
1928 if (f->vlan)
1929 filter_count++;
1930 }
1931
1932 if (!filter_count && is_netdev) {
1933 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1934 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1935 is_vf, is_netdev);
1936 if (!f) {
1937 dev_info(&vsi->back->pdev->dev,
1938 "Could not add filter %d for %pM\n",
1939 I40E_VLAN_ANY, netdev->dev_addr);
1940 return -ENOMEM;
1941 }
1942 }
1943
1944 if (!filter_count) {
1945 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1946 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1947 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1948 is_vf, is_netdev);
1949 if (!add_f) {
1950 dev_info(&vsi->back->pdev->dev,
1951 "Could not add filter %d for %pM\n",
1952 I40E_VLAN_ANY, f->macaddr);
1953 return -ENOMEM;
1954 }
1955 }
1956 }
1957
80f6428f
ASJ		 1958 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1959 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1960 return 0;
1961
41c445ff
JB		 1962 return i40e_sync_vsi_filters(vsi);
1963}
1964
1965/**
1966 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1967 * @netdev: network interface to be adjusted
1968 * @vid: vlan id to be added
078b5876
JB		 1969 *
1970 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1971 **/
1972static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1973 __always_unused __be16 proto, u16 vid)
1974{
1975 struct i40e_netdev_priv *np = netdev_priv(netdev);
1976 struct i40e_vsi *vsi = np->vsi;
078b5876 1977 int ret = 0;
41c445ff
JB		 1978
1979 if (vid > 4095)
078b5876
JB		 1980 return -EINVAL;
1981
1982 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1983
6982d429
ASJ		 1984 /* If the network stack called us with vid = 0 then
1985 * it is asking to receive priority tagged packets with
1986 * vlan id 0. Our HW receives them by default when configured
1987 * to receive untagged packets so there is no need to add an
1988 * extra filter for vlan 0 tagged packets.
41c445ff 1989 */
6982d429
ASJ		 1990 if (vid)
1991 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 1992
078b5876
JB		 1993 if (!ret && (vid < VLAN_N_VID))
1994 set_bit(vid, vsi->active_vlans);
41c445ff 1995
078b5876 1996 return ret;
41c445ff
JB		 1997}
1998
1999/**
2000 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2001 * @netdev: network interface to be adjusted
2002 * @vid: vlan id to be removed
078b5876 2003 *
fdfd943e 2004 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2005 **/
2006static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2007 __always_unused __be16 proto, u16 vid)
2008{
2009 struct i40e_netdev_priv *np = netdev_priv(netdev);
2010 struct i40e_vsi *vsi = np->vsi;
2011
078b5876
JB		 2012 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2013
41c445ff
JB		 2014 /* return code is ignored as there is nothing a user
2015 * can do about failure to remove and a log message was
078b5876 2016 * already printed from the other function
41c445ff
JB		 2017 */
2018 i40e_vsi_kill_vlan(vsi, vid);
2019
2020 clear_bit(vid, vsi->active_vlans);
078b5876 2021
41c445ff
JB		 2022 return 0;
2023}
2024
2025/**
2026 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2027 * @vsi: the vsi being brought back up
2028 **/
2029static void i40e_restore_vlan(struct i40e_vsi *vsi)
2030{
2031 u16 vid;
2032
2033 if (!vsi->netdev)
2034 return;
2035
2036 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2037
2038 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2039 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2040 vid);
2041}
2042
2043/**
2044 * i40e_vsi_add_pvid - Add pvid for the VSI
2045 * @vsi: the vsi being adjusted
2046 * @vid: the vlan id to set as a PVID
2047 **/
dcae29be 2048int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2049{
2050 struct i40e_vsi_context ctxt;
dcae29be 2051 i40e_status aq_ret;
41c445ff
JB		 2052
2053 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2054 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2055 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2056 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2057 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2058
2059 ctxt.seid = vsi->seid;
2060 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2061 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2062 if (aq_ret) {
41c445ff
JB		 2063 dev_info(&vsi->back->pdev->dev,
2064 "%s: update vsi failed, aq_err=%d\n",
2065 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2066 return -ENOENT;
41c445ff
JB		 2067 }
2068
dcae29be 2069 return 0;
41c445ff
JB		 2070}
2071
2072/**
2073 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2074 * @vsi: the vsi being adjusted
2075 *
2076 * Just use the vlan_rx_register() service to put it back to normal
2077 **/
2078void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2079{
6c12fcbf
GR		 2080 i40e_vlan_stripping_disable(vsi);
2081
41c445ff 2082 vsi->info.pvid = 0;
41c445ff
JB		 2083}
2084
2085/**
2086 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2087 * @vsi: ptr to the VSI
2088 *
2089 * If this function returns with an error, then it's possible one or
2090 * more of the rings is populated (while the rest are not). It is the
2091 * callers duty to clean those orphaned rings.
2092 *
2093 * Return 0 on success, negative on failure
2094 **/
2095static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2096{
2097 int i, err = 0;
2098
2099 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2100 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2101
2102 return err;
2103}
2104
2105/**
2106 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2107 * @vsi: ptr to the VSI
2108 *
2109 * Free VSI's transmit software resources
2110 **/
2111static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2112{
2113 int i;
2114
8e9dca53
GR		 2115 if (!vsi->tx_rings)
2116 return;
2117
41c445ff 2118 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2119 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2120 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2121}
2122
2123/**
2124 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2125 * @vsi: ptr to the VSI
2126 *
2127 * If this function returns with an error, then it's possible one or
2128 * more of the rings is populated (while the rest are not). It is the
2129 * callers duty to clean those orphaned rings.
2130 *
2131 * Return 0 on success, negative on failure
2132 **/
2133static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2134{
2135 int i, err = 0;
2136
2137 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2138 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2139 return err;
2140}
2141
2142/**
2143 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2144 * @vsi: ptr to the VSI
2145 *
2146 * Free all receive software resources
2147 **/
2148static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2149{
2150 int i;
2151
8e9dca53
GR		 2152 if (!vsi->rx_rings)
2153 return;
2154
41c445ff 2155 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2156 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2157 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2158}
2159
2160/**
2161 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2162 * @ring: The Tx ring to configure
2163 *
2164 * Configure the Tx descriptor ring in the HMC context.
2165 **/
2166static int i40e_configure_tx_ring(struct i40e_ring *ring)
2167{
2168 struct i40e_vsi *vsi = ring->vsi;
2169 u16 pf_q = vsi->base_queue + ring->queue_index;
2170 struct i40e_hw *hw = &vsi->back->hw;
2171 struct i40e_hmc_obj_txq tx_ctx;
2172 i40e_status err = 0;
2173 u32 qtx_ctl = 0;
2174
2175 /* some ATR related tx ring init */
60ea5f83 2176 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2177 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2178 ring->atr_count = 0;
2179 } else {
2180 ring->atr_sample_rate = 0;
2181 }
2182
2183 /* initialize XPS */
2184 if (ring->q_vector && ring->netdev &&
4e3b35b0 2185 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2186 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2187 netif_set_xps_queue(ring->netdev,
2188 &ring->q_vector->affinity_mask,
2189 ring->queue_index);
2190
2191 /* clear the context structure first */
2192 memset(&tx_ctx, 0, sizeof(tx_ctx));
2193
2194 tx_ctx.new_context = 1;
2195 tx_ctx.base = (ring->dma / 128);
2196 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2197 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2198 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2199 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2200 /* FDIR VSI tx ring can still use RS bit and writebacks */
2201 if (vsi->type != I40E_VSI_FDIR)
2202 tx_ctx.head_wb_ena = 1;
2203 tx_ctx.head_wb_addr = ring->dma +
2204 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2205
2206 /* As part of VSI creation/update, FW allocates certain
2207 * Tx arbitration queue sets for each TC enabled for
2208 * the VSI. The FW returns the handles to these queue
2209 * sets as part of the response buffer to Add VSI,
2210 * Update VSI, etc. AQ commands. It is expected that
2211 * these queue set handles be associated with the Tx
2212 * queues by the driver as part of the TX queue context
2213 * initialization. This has to be done regardless of
2214 * DCB as by default everything is mapped to TC0.
2215 */
2216 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2217 tx_ctx.rdylist_act = 0;
2218
2219 /* clear the context in the HMC */
2220 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2221 if (err) {
2222 dev_info(&vsi->back->pdev->dev,
2223 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2224 ring->queue_index, pf_q, err);
2225 return -ENOMEM;
2226 }
2227
2228 /* set the context in the HMC */
2229 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2230 if (err) {
2231 dev_info(&vsi->back->pdev->dev,
2232 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2233 ring->queue_index, pf_q, err);
2234 return -ENOMEM;
2235 }
2236
2237 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2238 if (vsi->type == I40E_VSI_VMDQ2)
2239 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2240 else
2241 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2242 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2243 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2244 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2245 i40e_flush(hw);
2246
2247 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2248
2249 /* cache tail off for easier writes later */
2250 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2251
2252 return 0;
2253}
2254
2255/**
2256 * i40e_configure_rx_ring - Configure a receive ring context
2257 * @ring: The Rx ring to configure
2258 *
2259 * Configure the Rx descriptor ring in the HMC context.
2260 **/
2261static int i40e_configure_rx_ring(struct i40e_ring *ring)
2262{
2263 struct i40e_vsi *vsi = ring->vsi;
2264 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2265 u16 pf_q = vsi->base_queue + ring->queue_index;
2266 struct i40e_hw *hw = &vsi->back->hw;
2267 struct i40e_hmc_obj_rxq rx_ctx;
2268 i40e_status err = 0;
2269
2270 ring->state = 0;
2271
2272 /* clear the context structure first */
2273 memset(&rx_ctx, 0, sizeof(rx_ctx));
2274
2275 ring->rx_buf_len = vsi->rx_buf_len;
2276 ring->rx_hdr_len = vsi->rx_hdr_len;
2277
2278 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2279 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2280
2281 rx_ctx.base = (ring->dma / 128);
2282 rx_ctx.qlen = ring->count;
2283
2284 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2285 set_ring_16byte_desc_enabled(ring);
2286 rx_ctx.dsize = 0;
2287 } else {
2288 rx_ctx.dsize = 1;
2289 }
2290
2291 rx_ctx.dtype = vsi->dtype;
2292 if (vsi->dtype) {
2293 set_ring_ps_enabled(ring);
2294 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2295 I40E_RX_SPLIT_IP |
2296 I40E_RX_SPLIT_TCP_UDP |
2297 I40E_RX_SPLIT_SCTP;
2298 } else {
2299 rx_ctx.hsplit_0 = 0;
2300 }
2301
2302 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2303 (chain_len * ring->rx_buf_len));
2304 rx_ctx.tphrdesc_ena = 1;
2305 rx_ctx.tphwdesc_ena = 1;
2306 rx_ctx.tphdata_ena = 1;
2307 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2308 if (hw->revision_id == 0)
2309 rx_ctx.lrxqthresh = 0;
2310 else
2311 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2312 rx_ctx.crcstrip = 1;
2313 rx_ctx.l2tsel = 1;
2314 rx_ctx.showiv = 1;
2315
2316 /* clear the context in the HMC */
2317 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2318 if (err) {
2319 dev_info(&vsi->back->pdev->dev,
2320 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2321 ring->queue_index, pf_q, err);
2322 return -ENOMEM;
2323 }
2324
2325 /* set the context in the HMC */
2326 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2327 if (err) {
2328 dev_info(&vsi->back->pdev->dev,
2329 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2330 ring->queue_index, pf_q, err);
2331 return -ENOMEM;
2332 }
2333
2334 /* cache tail for quicker writes, and clear the reg before use */
2335 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2336 writel(0, ring->tail);
2337
2338 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2339
2340 return 0;
2341}
2342
2343/**
2344 * i40e_vsi_configure_tx - Configure the VSI for Tx
2345 * @vsi: VSI structure describing this set of rings and resources
2346 *
2347 * Configure the Tx VSI for operation.
2348 **/
2349static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2350{
2351 int err = 0;
2352 u16 i;
2353
9f65e15b
AD		 2354 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2355 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2356
2357 return err;
2358}
2359
2360/**
2361 * i40e_vsi_configure_rx - Configure the VSI for Rx
2362 * @vsi: the VSI being configured
2363 *
2364 * Configure the Rx VSI for operation.
2365 **/
2366static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2367{
2368 int err = 0;
2369 u16 i;
2370
2371 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2372 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2373 + ETH_FCS_LEN + VLAN_HLEN;
2374 else
2375 vsi->max_frame = I40E_RXBUFFER_2048;
2376
2377 /* figure out correct receive buffer length */
2378 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2379 I40E_FLAG_RX_PS_ENABLED)) {
2380 case I40E_FLAG_RX_1BUF_ENABLED:
2381 vsi->rx_hdr_len = 0;
2382 vsi->rx_buf_len = vsi->max_frame;
2383 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2384 break;
2385 case I40E_FLAG_RX_PS_ENABLED:
2386 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2387 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2388 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2389 break;
2390 default:
2391 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2392 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2393 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2394 break;
2395 }
2396
2397 /* round up for the chip's needs */
2398 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2399 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2400 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2401 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2402
2403 /* set up individual rings */
2404 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2405 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2406
2407 return err;
2408}
2409
2410/**
2411 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2412 * @vsi: ptr to the VSI
2413 **/
2414static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2415{
2416 u16 qoffset, qcount;
2417 int i, n;
2418
2419 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2420 return;
2421
2422 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2423 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2424 continue;
2425
2426 qoffset = vsi->tc_config.tc_info[n].qoffset;
2427 qcount = vsi->tc_config.tc_info[n].qcount;
2428 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2429 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2430 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2431 rx_ring->dcb_tc = n;
2432 tx_ring->dcb_tc = n;
2433 }
2434 }
2435}
2436
2437/**
2438 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2439 * @vsi: ptr to the VSI
2440 **/
2441static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2442{
2443 if (vsi->netdev)
2444 i40e_set_rx_mode(vsi->netdev);
2445}
2446
17a73f6b
JG		 2447/**
2448 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2449 * @vsi: Pointer to the targeted VSI
2450 *
2451 * This function replays the hlist on the hw where all the SB Flow Director
2452 * filters were saved.
2453 **/
2454static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2455{
2456 struct i40e_fdir_filter *filter;
2457 struct i40e_pf *pf = vsi->back;
2458 struct hlist_node *node;
2459
55a5e60b
ASJ		 2460 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2461 return;
2462
17a73f6b
JG		 2463 hlist_for_each_entry_safe(filter, node,
2464 &pf->fdir_filter_list, fdir_node) {
2465 i40e_add_del_fdir(vsi, filter, true);
2466 }
2467}
2468
41c445ff
JB		 2469/**
2470 * i40e_vsi_configure - Set up the VSI for action
2471 * @vsi: the VSI being configured
2472 **/
2473static int i40e_vsi_configure(struct i40e_vsi *vsi)
2474{
2475 int err;
2476
2477 i40e_set_vsi_rx_mode(vsi);
2478 i40e_restore_vlan(vsi);
2479 i40e_vsi_config_dcb_rings(vsi);
2480 err = i40e_vsi_configure_tx(vsi);
2481 if (!err)
2482 err = i40e_vsi_configure_rx(vsi);
2483
2484 return err;
2485}
2486
2487/**
2488 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2489 * @vsi: the VSI being configured
2490 **/
2491static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2492{
2493 struct i40e_pf *pf = vsi->back;
2494 struct i40e_q_vector *q_vector;
2495 struct i40e_hw *hw = &pf->hw;
2496 u16 vector;
2497 int i, q;
2498 u32 val;
2499 u32 qp;
2500
2501 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2502 * and PFINT_LNKLSTn registers, e.g.:
2503 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2504 */
2505 qp = vsi->base_queue;
2506 vector = vsi->base_vector;
493fb300
AD		 2507 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2508 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2509 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2510 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2511 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2512 q_vector->rx.itr);
2513 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2514 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2515 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2516 q_vector->tx.itr);
2517
2518 /* Linked list for the queuepairs assigned to this vector */
2519 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2520 for (q = 0; q < q_vector->num_ringpairs; q++) {
2521 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2522 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2523 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2524 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2525 (I40E_QUEUE_TYPE_TX
2526 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2527
2528 wr32(hw, I40E_QINT_RQCTL(qp), val);
2529
2530 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2531 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2532 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2533 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2534 (I40E_QUEUE_TYPE_RX
2535 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2536
2537 /* Terminate the linked list */
2538 if (q == (q_vector->num_ringpairs - 1))
2539 val |= (I40E_QUEUE_END_OF_LIST
2540 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2541
2542 wr32(hw, I40E_QINT_TQCTL(qp), val);
2543 qp++;
2544 }
2545 }
2546
2547 i40e_flush(hw);
2548}
2549
2550/**
2551 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2552 * @hw: ptr to the hardware info
2553 **/
2554static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2555{
2556 u32 val;
2557
2558 /* clear things first */
2559 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2560 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2561
2562 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2563 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2564 I40E_PFINT_ICR0_ENA_GRST_MASK |
2565 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2566 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2567 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2568 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2569 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2570 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2571 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2572
2573 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2574
2575 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2576 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2577 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2578
2579 /* OTHER_ITR_IDX = 0 */
2580 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2581}
2582
2583/**
2584 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2585 * @vsi: the VSI being configured
2586 **/
2587static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2588{
493fb300 2589 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2590 struct i40e_pf *pf = vsi->back;
2591 struct i40e_hw *hw = &pf->hw;
2592 u32 val;
2593
2594 /* set the ITR configuration */
2595 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2596 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2597 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2598 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2599 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2600 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2601
2602 i40e_enable_misc_int_causes(hw);
2603
2604 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2605 wr32(hw, I40E_PFINT_LNKLST0, 0);
2606
f29eaa3d 2607 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2608 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2609 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2610 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2611
2612 wr32(hw, I40E_QINT_RQCTL(0), val);
2613
2614 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2615 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2616 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2617
2618 wr32(hw, I40E_QINT_TQCTL(0), val);
2619 i40e_flush(hw);
2620}
2621
2ef28cfb
MW		 2622/**
2623 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2624 * @pf: board private structure
2625 **/
2626void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2627{
2628 struct i40e_hw *hw = &pf->hw;
2629
2630 wr32(hw, I40E_PFINT_DYN_CTL0,
2631 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2632 i40e_flush(hw);
2633}
2634
41c445ff
JB		 2635/**
2636 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2637 * @pf: board private structure
2638 **/
116a57d4 2639void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2640{
2641 struct i40e_hw *hw = &pf->hw;
2642 u32 val;
2643
2644 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2645 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2646 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2647
2648 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2649 i40e_flush(hw);
2650}
2651
2652/**
2653 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2654 * @vsi: pointer to a vsi
2655 * @vector: enable a particular Hw Interrupt vector
2656 **/
2657void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2658{
2659 struct i40e_pf *pf = vsi->back;
2660 struct i40e_hw *hw = &pf->hw;
2661 u32 val;
2662
2663 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2664 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2665 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2666 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2667 /* skip the flush */
41c445ff
JB		 2668}
2669
2670/**
2671 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2672 * @irq: interrupt number
2673 * @data: pointer to a q_vector
2674 **/
2675static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2676{
2677 struct i40e_q_vector *q_vector = data;
2678
cd0b6fa6 2679 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2680 return IRQ_HANDLED;
2681
2682 napi_schedule(&q_vector->napi);
2683
2684 return IRQ_HANDLED;
2685}
2686
41c445ff
JB		 2687/**
2688 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2689 * @vsi: the VSI being configured
2690 * @basename: name for the vector
2691 *
2692 * Allocates MSI-X vectors and requests interrupts from the kernel.
2693 **/
2694static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2695{
2696 int q_vectors = vsi->num_q_vectors;
2697 struct i40e_pf *pf = vsi->back;
2698 int base = vsi->base_vector;
2699 int rx_int_idx = 0;
2700 int tx_int_idx = 0;
2701 int vector, err;
2702
2703 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2704 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2705
cd0b6fa6 2706 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2707 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2708 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2709 tx_int_idx++;
cd0b6fa6 2710 } else if (q_vector->rx.ring) {
41c445ff
JB		 2711 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2712 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2713 } else if (q_vector->tx.ring) {
41c445ff
JB		 2714 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2715 "%s-%s-%d", basename, "tx", tx_int_idx++);
2716 } else {
2717 /* skip this unused q_vector */
2718 continue;
2719 }
2720 err = request_irq(pf->msix_entries[base + vector].vector,
2721 vsi->irq_handler,
2722 0,
2723 q_vector->name,
2724 q_vector);
2725 if (err) {
2726 dev_info(&pf->pdev->dev,
2727 "%s: request_irq failed, error: %d\n",
2728 __func__, err);
2729 goto free_queue_irqs;
2730 }
2731 /* assign the mask for this irq */
2732 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2733 &q_vector->affinity_mask);
2734 }
2735
2736 return 0;
2737
2738free_queue_irqs:
2739 while (vector) {
2740 vector--;
2741 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2742 NULL);
2743 free_irq(pf->msix_entries[base + vector].vector,
2744 &(vsi->q_vectors[vector]));
2745 }
2746 return err;
2747}
2748
2749/**
2750 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2751 * @vsi: the VSI being un-configured
2752 **/
2753static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2754{
2755 struct i40e_pf *pf = vsi->back;
2756 struct i40e_hw *hw = &pf->hw;
2757 int base = vsi->base_vector;
2758 int i;
2759
2760 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2761 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2762 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2763 }
2764
2765 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2766 for (i = vsi->base_vector;
2767 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2768 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2769
2770 i40e_flush(hw);
2771 for (i = 0; i < vsi->num_q_vectors; i++)
2772 synchronize_irq(pf->msix_entries[i + base].vector);
2773 } else {
2774 /* Legacy and MSI mode - this stops all interrupt handling */
2775 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2776 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2777 i40e_flush(hw);
2778 synchronize_irq(pf->pdev->irq);
2779 }
2780}
2781
2782/**
2783 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2784 * @vsi: the VSI being configured
2785 **/
2786static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2787{
2788 struct i40e_pf *pf = vsi->back;
2789 int i;
2790
2791 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2792 for (i = vsi->base_vector;
2793 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2794 i40e_irq_dynamic_enable(vsi, i);
2795 } else {
2796 i40e_irq_dynamic_enable_icr0(pf);
2797 }
2798
1022cb6c 2799 i40e_flush(&pf->hw);
41c445ff
JB		 2800 return 0;
2801}
2802
2803/**
2804 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2805 * @pf: board private structure
2806 **/
2807static void i40e_stop_misc_vector(struct i40e_pf *pf)
2808{
2809 /* Disable ICR 0 */
2810 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2811 i40e_flush(&pf->hw);
2812}
2813
2814/**
2815 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2816 * @irq: interrupt number
2817 * @data: pointer to a q_vector
2818 *
2819 * This is the handler used for all MSI/Legacy interrupts, and deals
2820 * with both queue and non-queue interrupts. This is also used in
2821 * MSIX mode to handle the non-queue interrupts.
2822 **/
2823static irqreturn_t i40e_intr(int irq, void *data)
2824{
2825 struct i40e_pf *pf = (struct i40e_pf *)data;
2826 struct i40e_hw *hw = &pf->hw;
5e823066 2827 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2828 u32 icr0, icr0_remaining;
2829 u32 val, ena_mask;
2830
2831 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2832 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2833
116a57d4
SN		 2834 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2835 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2836 goto enable_intr;
41c445ff 2837
cd92e72f
SN		 2838 /* if interrupt but no bits showing, must be SWINT */
2839 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2840 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2841 pf->sw_int_count++;
2842
41c445ff
JB		 2843 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2844 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2845
2846 /* temporarily disable queue cause for NAPI processing */
2847 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2848 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2849 wr32(hw, I40E_QINT_RQCTL(0), qval);
2850
2851 qval = rd32(hw, I40E_QINT_TQCTL(0));
2852 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2853 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2854
2855 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2856 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2857 }
2858
2859 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2860 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2861 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2862 }
2863
2864 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2865 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2866 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2867 }
2868
2869 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2870 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2871 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2872 }
2873
2874 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2875 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2876 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2877 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2878 val = rd32(hw, I40E_GLGEN_RSTAT);
2879 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2880 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2881 if (val == I40E_RESET_CORER) {
41c445ff 2882 pf->corer_count++;
4eb3f768 2883 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2884 pf->globr_count++;
4eb3f768 2885 } else if (val == I40E_RESET_EMPR) {
41c445ff 2886 pf->empr_count++;
4eb3f768
SN		 2887 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2888 }
41c445ff
JB		 2889 }
2890
9c010ee0
ASJ		 2891 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2892 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2893 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2894 }
2895
beb0dff1
JK		 2896 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2897 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2898
2899 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2900 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2901 i40e_ptp_tx_hwtstamp(pf);
2902 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2903 }
2904
2905 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2906 }
2907
41c445ff
JB		 2908 /* If a critical error is pending we have no choice but to reset the
2909 * device.
2910 * Report and mask out any remaining unexpected interrupts.
2911 */
2912 icr0_remaining = icr0 & ena_mask;
2913 if (icr0_remaining) {
2914 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2915 icr0_remaining);
9c010ee0 2916 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2917 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2918 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2919 dev_info(&pf->pdev->dev, "device will be reset\n");
2920 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2921 i40e_service_event_schedule(pf);
41c445ff
JB		 2922 }
2923 ena_mask &= ~icr0_remaining;
2924 }
5e823066 2925 ret = IRQ_HANDLED;
41c445ff 2926
5e823066 2927enable_intr:
41c445ff
JB		 2928 /* re-enable interrupt causes */
2929 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2930 if (!test_bit(__I40E_DOWN, &pf->state)) {
2931 i40e_service_event_schedule(pf);
2932 i40e_irq_dynamic_enable_icr0(pf);
2933 }
2934
5e823066 2935 return ret;
41c445ff
JB		 2936}
2937
cbf61325
ASJ		 2938/**
2939 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2940 * @tx_ring: tx ring to clean
2941 * @budget: how many cleans we're allowed
2942 *
2943 * Returns true if there's any budget left (e.g. the clean is finished)
2944 **/
2945static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2946{
2947 struct i40e_vsi *vsi = tx_ring->vsi;
2948 u16 i = tx_ring->next_to_clean;
2949 struct i40e_tx_buffer *tx_buf;
2950 struct i40e_tx_desc *tx_desc;
2951
2952 tx_buf = &tx_ring->tx_bi[i];
2953 tx_desc = I40E_TX_DESC(tx_ring, i);
2954 i -= tx_ring->count;
2955
2956 do {
2957 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2958
2959 /* if next_to_watch is not set then there is no work pending */
2960 if (!eop_desc)
2961 break;
2962
2963 /* prevent any other reads prior to eop_desc */
2964 read_barrier_depends();
2965
2966 /* if the descriptor isn't done, no work yet to do */
2967 if (!(eop_desc->cmd_type_offset_bsz &
2968 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2969 break;
2970
2971 /* clear next_to_watch to prevent false hangs */
2972 tx_buf->next_to_watch = NULL;
2973
2974 /* unmap skb header data */
2975 dma_unmap_single(tx_ring->dev,
2976 dma_unmap_addr(tx_buf, dma),
2977 dma_unmap_len(tx_buf, len),
2978 DMA_TO_DEVICE);
2979
2980 dma_unmap_len_set(tx_buf, len, 0);
2981
2982
2983 /* move to the next desc and buffer to clean */
2984 tx_buf++;
2985 tx_desc++;
2986 i++;
2987 if (unlikely(!i)) {
2988 i -= tx_ring->count;
2989 tx_buf = tx_ring->tx_bi;
2990 tx_desc = I40E_TX_DESC(tx_ring, 0);
2991 }
2992
2993 /* update budget accounting */
2994 budget--;
2995 } while (likely(budget));
2996
2997 i += tx_ring->count;
2998 tx_ring->next_to_clean = i;
2999
3000 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3001 i40e_irq_dynamic_enable(vsi,
3002 tx_ring->q_vector->v_idx + vsi->base_vector);
3003 }
3004 return budget > 0;
3005}
3006
3007/**
3008 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3009 * @irq: interrupt number
3010 * @data: pointer to a q_vector
3011 **/
3012static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3013{
3014 struct i40e_q_vector *q_vector = data;
3015 struct i40e_vsi *vsi;
3016
3017 if (!q_vector->tx.ring)
3018 return IRQ_HANDLED;
3019
3020 vsi = q_vector->tx.ring->vsi;
3021 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3022
3023 return IRQ_HANDLED;
3024}
3025
41c445ff 3026/**
cd0b6fa6 3027 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3028 * @vsi: the VSI being configured
3029 * @v_idx: vector index
cd0b6fa6 3030 * @qp_idx: queue pair index
41c445ff 3031 **/
cd0b6fa6 3032static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3033{
493fb300 3034 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3035 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3036 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3037
3038 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3039 tx_ring->next = q_vector->tx.ring;
3040 q_vector->tx.ring = tx_ring;
41c445ff 3041 q_vector->tx.count++;
cd0b6fa6
AD		 3042
3043 rx_ring->q_vector = q_vector;
3044 rx_ring->next = q_vector->rx.ring;
3045 q_vector->rx.ring = rx_ring;
3046 q_vector->rx.count++;
41c445ff
JB		 3047}
3048
3049/**
3050 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3051 * @vsi: the VSI being configured
3052 *
3053 * This function maps descriptor rings to the queue-specific vectors
3054 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3055 * one vector per queue pair, but on a constrained vector budget, we
3056 * group the queue pairs as "efficiently" as possible.
3057 **/
3058static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3059{
3060 int qp_remaining = vsi->num_queue_pairs;
3061 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3062 int num_ringpairs;
41c445ff
JB		 3063 int v_start = 0;
3064 int qp_idx = 0;
3065
3066 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3067 * group them so there are multiple queues per vector.
3068 */
3069 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3070 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3071
3072 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3073
3074 q_vector->num_ringpairs = num_ringpairs;
3075
3076 q_vector->rx.count = 0;
3077 q_vector->tx.count = 0;
3078 q_vector->rx.ring = NULL;
3079 q_vector->tx.ring = NULL;
3080
3081 while (num_ringpairs--) {
3082 map_vector_to_qp(vsi, v_start, qp_idx);
3083 qp_idx++;
3084 qp_remaining--;
41c445ff
JB		 3085 }
3086 }
3087}
3088
3089/**
3090 * i40e_vsi_request_irq - Request IRQ from the OS
3091 * @vsi: the VSI being configured
3092 * @basename: name for the vector
3093 **/
3094static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3095{
3096 struct i40e_pf *pf = vsi->back;
3097 int err;
3098
3099 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3100 err = i40e_vsi_request_irq_msix(vsi, basename);
3101 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3102 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3103 pf->misc_int_name, pf);
3104 else
3105 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3106 pf->misc_int_name, pf);
3107
3108 if (err)
3109 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3110
3111 return err;
3112}
3113
3114#ifdef CONFIG_NET_POLL_CONTROLLER
3115/**
3116 * i40e_netpoll - A Polling 'interrupt'handler
3117 * @netdev: network interface device structure
3118 *
3119 * This is used by netconsole to send skbs without having to re-enable
3120 * interrupts. It's not called while the normal interrupt routine is executing.
3121 **/
3122static void i40e_netpoll(struct net_device *netdev)
3123{
3124 struct i40e_netdev_priv *np = netdev_priv(netdev);
3125 struct i40e_vsi *vsi = np->vsi;
3126 struct i40e_pf *pf = vsi->back;
3127 int i;
3128
3129 /* if interface is down do nothing */
3130 if (test_bit(__I40E_DOWN, &vsi->state))
3131 return;
3132
3133 pf->flags |= I40E_FLAG_IN_NETPOLL;
3134 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3135 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3136 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3137 } else {
3138 i40e_intr(pf->pdev->irq, netdev);
3139 }
3140 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3141}
3142#endif
0b3aec85
JB		 3143 /* set the prefena field to 1 because the manual says to */
3144 rx_ctx.prefena = 1;
41c445ff
JB		 3145
3146/**
3147 * i40e_vsi_control_tx - Start or stop a VSI's rings
3148 * @vsi: the VSI being configured
3149 * @enable: start or stop the rings
3150 **/
3151static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3152{
3153 struct i40e_pf *pf = vsi->back;
3154 struct i40e_hw *hw = &pf->hw;
3155 int i, j, pf_q;
3156 u32 tx_reg;
3157
3158 pf_q = vsi->base_queue;
3159 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3160 for (j = 0; j < 50; j++) {
41c445ff 3161 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3162 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3163 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3164 break;
3165 usleep_range(1000, 2000);
3166 }
fda972f6
MW		 3167 /* Skip if the queue is already in the requested state */
3168 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3169 continue;
3170 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3171 continue;
41c445ff
JB		 3172
3173 /* turn on/off the queue */
c5c9eb9e
SN		 3174 if (enable) {
3175 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3176 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3177 } else {
41c445ff 3178 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3179 }
41c445ff
JB		 3180
3181 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3182
3183 /* wait for the change to finish */
3184 for (j = 0; j < 10; j++) {
3185 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3186 if (enable) {
3187 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3188 break;
3189 } else {
3190 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3191 break;
3192 }
3193
3194 udelay(10);
3195 }
3196 if (j >= 10) {
3197 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3198 pf_q, (enable ? "en" : "dis"));
3199 return -ETIMEDOUT;
3200 }
3201 }
3202
7134f9ce
JB		 3203 if (hw->revision_id == 0)
3204 mdelay(50);
3205
41c445ff
JB		 3206 return 0;
3207}
3208
3209/**
3210 * i40e_vsi_control_rx - Start or stop a VSI's rings
3211 * @vsi: the VSI being configured
3212 * @enable: start or stop the rings
3213 **/
3214static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3215{
3216 struct i40e_pf *pf = vsi->back;
3217 struct i40e_hw *hw = &pf->hw;
3218 int i, j, pf_q;
3219 u32 rx_reg;
3220
3221 pf_q = vsi->base_queue;
3222 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3223 for (j = 0; j < 50; j++) {
41c445ff 3224 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3225 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3226 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3227 break;
3228 usleep_range(1000, 2000);
3229 }
41c445ff
JB		 3230
3231 if (enable) {
3232 /* is STAT set ? */
3233 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3234 continue;
3235 } else {
3236 /* is !STAT set ? */
3237 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3238 continue;
3239 }
3240
3241 /* turn on/off the queue */
3242 if (enable)
6c5ef620 3243 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3244 else
6c5ef620 3245 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3246 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3247
3248 /* wait for the change to finish */
3249 for (j = 0; j < 10; j++) {
3250 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3251
3252 if (enable) {
3253 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3254 break;
3255 } else {
3256 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3257 break;
3258 }
3259
3260 udelay(10);
3261 }
3262 if (j >= 10) {
3263 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3264 pf_q, (enable ? "en" : "dis"));
3265 return -ETIMEDOUT;
3266 }
3267 }
3268
3269 return 0;
3270}
3271
3272/**
3273 * i40e_vsi_control_rings - Start or stop a VSI's rings
3274 * @vsi: the VSI being configured
3275 * @enable: start or stop the rings
3276 **/
fc18eaa0 3277int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3278{
3b867b28 3279 int ret = 0;
41c445ff
JB		 3280
3281 /* do rx first for enable and last for disable */
3282 if (request) {
3283 ret = i40e_vsi_control_rx(vsi, request);
3284 if (ret)
3285 return ret;
3286 ret = i40e_vsi_control_tx(vsi, request);
3287 } else {
3b867b28
ASJ		 3288 /* Ignore return value, we need to shutdown whatever we can */
3289 i40e_vsi_control_tx(vsi, request);
3290 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3291 }
3292
3293 return ret;
3294}
3295
3296/**
3297 * i40e_vsi_free_irq - Free the irq association with the OS
3298 * @vsi: the VSI being configured
3299 **/
3300static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3301{
3302 struct i40e_pf *pf = vsi->back;
3303 struct i40e_hw *hw = &pf->hw;
3304 int base = vsi->base_vector;
3305 u32 val, qp;
3306 int i;
3307
3308 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3309 if (!vsi->q_vectors)
3310 return;
3311
3312 for (i = 0; i < vsi->num_q_vectors; i++) {
3313 u16 vector = i + base;
3314
3315 /* free only the irqs that were actually requested */
78681b1f
SN		 3316 if (!vsi->q_vectors[i] ||
3317 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3318 continue;
3319
3320 /* clear the affinity_mask in the IRQ descriptor */
3321 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3322 NULL);
3323 free_irq(pf->msix_entries[vector].vector,
493fb300 3324 vsi->q_vectors[i]);
41c445ff
JB		 3325
3326 /* Tear down the interrupt queue link list
3327 *
3328 * We know that they come in pairs and always
3329 * the Rx first, then the Tx. To clear the
3330 * link list, stick the EOL value into the
3331 * next_q field of the registers.
3332 */
3333 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3334 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3335 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3336 val |= I40E_QUEUE_END_OF_LIST
3337 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3338 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3339
3340 while (qp != I40E_QUEUE_END_OF_LIST) {
3341 u32 next;
3342
3343 val = rd32(hw, I40E_QINT_RQCTL(qp));
3344
3345 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3346 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3347 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3348 I40E_QINT_RQCTL_INTEVENT_MASK);
3349
3350 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3351 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3352
3353 wr32(hw, I40E_QINT_RQCTL(qp), val);
3354
3355 val = rd32(hw, I40E_QINT_TQCTL(qp));
3356
3357 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3358 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3359
3360 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3361 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3362 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3363 I40E_QINT_TQCTL_INTEVENT_MASK);
3364
3365 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3366 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3367
3368 wr32(hw, I40E_QINT_TQCTL(qp), val);
3369 qp = next;
3370 }
3371 }
3372 } else {
3373 free_irq(pf->pdev->irq, pf);
3374
3375 val = rd32(hw, I40E_PFINT_LNKLST0);
3376 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3377 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3378 val |= I40E_QUEUE_END_OF_LIST
3379 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3380 wr32(hw, I40E_PFINT_LNKLST0, val);
3381
3382 val = rd32(hw, I40E_QINT_RQCTL(qp));
3383 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3384 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3385 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3386 I40E_QINT_RQCTL_INTEVENT_MASK);
3387
3388 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3389 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3390
3391 wr32(hw, I40E_QINT_RQCTL(qp), val);
3392
3393 val = rd32(hw, I40E_QINT_TQCTL(qp));
3394
3395 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3396 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3397 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3398 I40E_QINT_TQCTL_INTEVENT_MASK);
3399
3400 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3401 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3402
3403 wr32(hw, I40E_QINT_TQCTL(qp), val);
3404 }
3405}
3406
493fb300
AD		 3407/**
3408 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3409 * @vsi: the VSI being configured
3410 * @v_idx: Index of vector to be freed
3411 *
3412 * This function frees the memory allocated to the q_vector. In addition if
3413 * NAPI is enabled it will delete any references to the NAPI struct prior
3414 * to freeing the q_vector.
3415 **/
3416static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3417{
3418 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3419 struct i40e_ring *ring;
493fb300
AD		 3420
3421 if (!q_vector)
3422 return;
3423
3424 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3425 i40e_for_each_ring(ring, q_vector->tx)
3426 ring->q_vector = NULL;
3427
3428 i40e_for_each_ring(ring, q_vector->rx)
3429 ring->q_vector = NULL;
493fb300
AD		 3430
3431 /* only VSI w/ an associated netdev is set up w/ NAPI */
3432 if (vsi->netdev)
3433 netif_napi_del(&q_vector->napi);
3434
3435 vsi->q_vectors[v_idx] = NULL;
3436
3437 kfree_rcu(q_vector, rcu);
3438}
3439
41c445ff
JB		 3440/**
3441 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3442 * @vsi: the VSI being un-configured
3443 *
3444 * This frees the memory allocated to the q_vectors and
3445 * deletes references to the NAPI struct.
3446 **/
3447static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3448{
3449 int v_idx;
3450
493fb300
AD		 3451 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3452 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3453}
3454
3455/**
3456 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3457 * @pf: board private structure
3458 **/
3459static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3460{
3461 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3462 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3463 pci_disable_msix(pf->pdev);
3464 kfree(pf->msix_entries);
3465 pf->msix_entries = NULL;
3466 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3467 pci_disable_msi(pf->pdev);
3468 }
3469 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3470}
3471
3472/**
3473 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3474 * @pf: board private structure
3475 *
3476 * We go through and clear interrupt specific resources and reset the structure
3477 * to pre-load conditions
3478 **/
3479static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3480{
3481 int i;
3482
3483 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3484 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3485 if (pf->vsi[i])
3486 i40e_vsi_free_q_vectors(pf->vsi[i]);
3487 i40e_reset_interrupt_capability(pf);
3488}
3489
3490/**
3491 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3492 * @vsi: the VSI being configured
3493 **/
3494static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3495{
3496 int q_idx;
3497
3498 if (!vsi->netdev)
3499 return;
3500
3501 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3502 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3503}
3504
3505/**
3506 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3507 * @vsi: the VSI being configured
3508 **/
3509static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3510{
3511 int q_idx;
3512
3513 if (!vsi->netdev)
3514 return;
3515
3516 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3517 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3518}
3519
3520/**
3521 * i40e_quiesce_vsi - Pause a given VSI
3522 * @vsi: the VSI being paused
3523 **/
3524static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3525{
3526 if (test_bit(__I40E_DOWN, &vsi->state))
3527 return;
3528
3529 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3530 if (vsi->netdev && netif_running(vsi->netdev)) {
3531 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3532 } else {
3533 set_bit(__I40E_DOWN, &vsi->state);
3534 i40e_down(vsi);
3535 }
3536}
3537
3538/**
3539 * i40e_unquiesce_vsi - Resume a given VSI
3540 * @vsi: the VSI being resumed
3541 **/
3542static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3543{
3544 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3545 return;
3546
3547 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3548 if (vsi->netdev && netif_running(vsi->netdev))
3549 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3550 else
3551 i40e_up(vsi); /* this clears the DOWN bit */
3552}
3553
3554/**
3555 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3556 * @pf: the PF
3557 **/
3558static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3559{
3560 int v;
3561
3562 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3563 if (pf->vsi[v])
3564 i40e_quiesce_vsi(pf->vsi[v]);
3565 }
3566}
3567
3568/**
3569 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3570 * @pf: the PF
3571 **/
3572static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3573{
3574 int v;
3575
3576 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3577 if (pf->vsi[v])
3578 i40e_unquiesce_vsi(pf->vsi[v]);
3579 }
3580}
3581
3582/**
3583 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3584 * @dcbcfg: the corresponding DCBx configuration structure
3585 *
3586 * Return the number of TCs from given DCBx configuration
3587 **/
3588static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3589{
078b5876
JB		 3590 u8 num_tc = 0;
3591 int i;
41c445ff
JB		 3592
3593 /* Scan the ETS Config Priority Table to find
3594 * traffic class enabled for a given priority
3595 * and use the traffic class index to get the
3596 * number of traffic classes enabled
3597 */
3598 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3599 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3600 num_tc = dcbcfg->etscfg.prioritytable[i];
3601 }
3602
3603 /* Traffic class index starts from zero so
3604 * increment to return the actual count
3605 */
078b5876 3606 return num_tc + 1;
41c445ff
JB		 3607}
3608
3609/**
3610 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3611 * @dcbcfg: the corresponding DCBx configuration structure
3612 *
3613 * Query the current DCB configuration and return the number of
3614 * traffic classes enabled from the given DCBX config
3615 **/
3616static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3617{
3618 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3619 u8 enabled_tc = 1;
3620 u8 i;
3621
3622 for (i = 0; i < num_tc; i++)
3623 enabled_tc |= 1 << i;
3624
3625 return enabled_tc;
3626}
3627
3628/**
3629 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3630 * @pf: PF being queried
3631 *
3632 * Return number of traffic classes enabled for the given PF
3633 **/
3634static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3635{
3636 struct i40e_hw *hw = &pf->hw;
3637 u8 i, enabled_tc;
3638 u8 num_tc = 0;
3639 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3640
3641 /* If DCB is not enabled then always in single TC */
3642 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3643 return 1;
3644
3645 /* MFP mode return count of enabled TCs for this PF */
3646 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3647 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3648 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3649 if (enabled_tc & (1 << i))
3650 num_tc++;
3651 }
3652 return num_tc;
3653 }
3654
3655 /* SFP mode will be enabled for all TCs on port */
3656 return i40e_dcb_get_num_tc(dcbcfg);
3657}
3658
3659/**
3660 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3661 * @pf: PF being queried
3662 *
3663 * Return a bitmap for first enabled traffic class for this PF.
3664 **/
3665static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3666{
3667 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3668 u8 i = 0;
3669
3670 if (!enabled_tc)
3671 return 0x1; /* TC0 */
3672
3673 /* Find the first enabled TC */
3674 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3675 if (enabled_tc & (1 << i))
3676 break;
3677 }
3678
3679 return 1 << i;
3680}
3681
3682/**
3683 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3684 * @pf: PF being queried
3685 *
3686 * Return a bitmap for enabled traffic classes for this PF.
3687 **/
3688static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3689{
3690 /* If DCB is not enabled for this PF then just return default TC */
3691 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3692 return i40e_pf_get_default_tc(pf);
3693
3694 /* MFP mode will have enabled TCs set by FW */
3695 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3696 return pf->hw.func_caps.enabled_tcmap;
3697
3698 /* SFP mode we want PF to be enabled for all TCs */
3699 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3700}
3701
3702/**
3703 * i40e_vsi_get_bw_info - Query VSI BW Information
3704 * @vsi: the VSI being queried
3705 *
3706 * Returns 0 on success, negative value on failure
3707 **/
3708static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3709{
3710 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3711 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3712 struct i40e_pf *pf = vsi->back;
3713 struct i40e_hw *hw = &pf->hw;
dcae29be 3714 i40e_status aq_ret;
41c445ff 3715 u32 tc_bw_max;
41c445ff
JB		 3716 int i;
3717
3718 /* Get the VSI level BW configuration */
dcae29be
JB		 3719 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3720 if (aq_ret) {
41c445ff
JB		 3721 dev_info(&pf->pdev->dev,
3722 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3723 aq_ret, pf->hw.aq.asq_last_status);
3724 return -EINVAL;
41c445ff
JB		 3725 }
3726
3727 /* Get the VSI level BW configuration per TC */
dcae29be 3728 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3729 NULL);
dcae29be 3730 if (aq_ret) {
41c445ff
JB		 3731 dev_info(&pf->pdev->dev,
3732 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3733 aq_ret, pf->hw.aq.asq_last_status);
3734 return -EINVAL;
41c445ff
JB		 3735 }
3736
3737 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3738 dev_info(&pf->pdev->dev,
3739 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3740 bw_config.tc_valid_bits,
3741 bw_ets_config.tc_valid_bits);
3742 /* Still continuing */
3743 }
3744
3745 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3746 vsi->bw_max_quanta = bw_config.max_bw;
3747 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3748 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3749 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3750 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3751 vsi->bw_ets_limit_credits[i] =
3752 le16_to_cpu(bw_ets_config.credits[i]);
3753 /* 3 bits out of 4 for each TC */
3754 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3755 }
078b5876 3756
dcae29be 3757 return 0;
41c445ff
JB		 3758}
3759
3760/**
3761 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3762 * @vsi: the VSI being configured
3763 * @enabled_tc: TC bitmap
3764 * @bw_credits: BW shared credits per TC
3765 *
3766 * Returns 0 on success, negative value on failure
3767 **/
dcae29be 3768static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3769 u8 *bw_share)
3770{
3771 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3772 i40e_status aq_ret;
3773 int i;
41c445ff
JB		 3774
3775 bw_data.tc_valid_bits = enabled_tc;
3776 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3777 bw_data.tc_bw_credits[i] = bw_share[i];
3778
dcae29be
JB		 3779 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3780 NULL);
3781 if (aq_ret) {
41c445ff 3782 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3783 "AQ command Config VSI BW allocation per TC failed = %d\n",
3784 vsi->back->hw.aq.asq_last_status);
dcae29be 3785 return -EINVAL;
41c445ff
JB		 3786 }
3787
3788 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3789 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3790
dcae29be 3791 return 0;
41c445ff
JB		 3792}
3793
3794/**
3795 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3796 * @vsi: the VSI being configured
3797 * @enabled_tc: TC map to be enabled
3798 *
3799 **/
3800static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3801{
3802 struct net_device *netdev = vsi->netdev;
3803 struct i40e_pf *pf = vsi->back;
3804 struct i40e_hw *hw = &pf->hw;
3805 u8 netdev_tc = 0;
3806 int i;
3807 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3808
3809 if (!netdev)
3810 return;
3811
3812 if (!enabled_tc) {
3813 netdev_reset_tc(netdev);
3814 return;
3815 }
3816
3817 /* Set up actual enabled TCs on the VSI */
3818 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3819 return;
3820
3821 /* set per TC queues for the VSI */
3822 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3823 /* Only set TC queues for enabled tcs
3824 *
3825 * e.g. For a VSI that has TC0 and TC3 enabled the
3826 * enabled_tc bitmap would be 0x00001001; the driver
3827 * will set the numtc for netdev as 2 that will be
3828 * referenced by the netdev layer as TC 0 and 1.
3829 */
3830 if (vsi->tc_config.enabled_tc & (1 << i))
3831 netdev_set_tc_queue(netdev,
3832 vsi->tc_config.tc_info[i].netdev_tc,
3833 vsi->tc_config.tc_info[i].qcount,
3834 vsi->tc_config.tc_info[i].qoffset);
3835 }
3836
3837 /* Assign UP2TC map for the VSI */
3838 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3839 /* Get the actual TC# for the UP */
3840 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3841 /* Get the mapped netdev TC# for the UP */
3842 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3843 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3844 }
3845}
3846
3847/**
3848 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3849 * @vsi: the VSI being configured
3850 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3851 **/
3852static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3853 struct i40e_vsi_context *ctxt)
3854{
3855 /* copy just the sections touched not the entire info
3856 * since not all sections are valid as returned by
3857 * update vsi params
3858 */
3859 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3860 memcpy(&vsi->info.queue_mapping,
3861 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3862 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3863 sizeof(vsi->info.tc_mapping));
3864}
3865
3866/**
3867 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3868 * @vsi: VSI to be configured
3869 * @enabled_tc: TC bitmap
3870 *
3871 * This configures a particular VSI for TCs that are mapped to the
3872 * given TC bitmap. It uses default bandwidth share for TCs across
3873 * VSIs to configure TC for a particular VSI.
3874 *
3875 * NOTE:
3876 * It is expected that the VSI queues have been quisced before calling
3877 * this function.
3878 **/
3879static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3880{
3881 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3882 struct i40e_vsi_context ctxt;
3883 int ret = 0;
3884 int i;
3885
3886 /* Check if enabled_tc is same as existing or new TCs */
3887 if (vsi->tc_config.enabled_tc == enabled_tc)
3888 return ret;
3889
3890 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3891 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3892 if (enabled_tc & (1 << i))
3893 bw_share[i] = 1;
3894 }
3895
3896 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3897 if (ret) {
3898 dev_info(&vsi->back->pdev->dev,
3899 "Failed configuring TC map %d for VSI %d\n",
3900 enabled_tc, vsi->seid);
3901 goto out;
3902 }
3903
3904 /* Update Queue Pairs Mapping for currently enabled UPs */
3905 ctxt.seid = vsi->seid;
3906 ctxt.pf_num = vsi->back->hw.pf_id;
3907 ctxt.vf_num = 0;
3908 ctxt.uplink_seid = vsi->uplink_seid;
3909 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3910 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3911
3912 /* Update the VSI after updating the VSI queue-mapping information */
3913 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3914 if (ret) {
3915 dev_info(&vsi->back->pdev->dev,
3916 "update vsi failed, aq_err=%d\n",
3917 vsi->back->hw.aq.asq_last_status);
3918 goto out;
3919 }
3920 /* update the local VSI info with updated queue map */
3921 i40e_vsi_update_queue_map(vsi, &ctxt);
3922 vsi->info.valid_sections = 0;
3923
3924 /* Update current VSI BW information */
3925 ret = i40e_vsi_get_bw_info(vsi);
3926 if (ret) {
3927 dev_info(&vsi->back->pdev->dev,
3928 "Failed updating vsi bw info, aq_err=%d\n",
3929 vsi->back->hw.aq.asq_last_status);
3930 goto out;
3931 }
3932
3933 /* Update the netdev TC setup */
3934 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3935out:
3936 return ret;
3937}
3938
4e3b35b0
NP		 3939/**
3940 * i40e_veb_config_tc - Configure TCs for given VEB
3941 * @veb: given VEB
3942 * @enabled_tc: TC bitmap
3943 *
3944 * Configures given TC bitmap for VEB (switching) element
3945 **/
3946int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3947{
3948 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3949 struct i40e_pf *pf = veb->pf;
3950 int ret = 0;
3951 int i;
3952
3953 /* No TCs or already enabled TCs just return */
3954 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3955 return ret;
3956
3957 bw_data.tc_valid_bits = enabled_tc;
3958 /* bw_data.absolute_credits is not set (relative) */
3959
3960 /* Enable ETS TCs with equal BW Share for now */
3961 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3962 if (enabled_tc & (1 << i))
3963 bw_data.tc_bw_share_credits[i] = 1;
3964 }
3965
3966 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3967 &bw_data, NULL);
3968 if (ret) {
3969 dev_info(&pf->pdev->dev,
3970 "veb bw config failed, aq_err=%d\n",
3971 pf->hw.aq.asq_last_status);
3972 goto out;
3973 }
3974
3975 /* Update the BW information */
3976 ret = i40e_veb_get_bw_info(veb);
3977 if (ret) {
3978 dev_info(&pf->pdev->dev,
3979 "Failed getting veb bw config, aq_err=%d\n",
3980 pf->hw.aq.asq_last_status);
3981 }
3982
3983out:
3984 return ret;
3985}
3986
3987#ifdef CONFIG_I40E_DCB
3988/**
3989 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
3990 * @pf: PF struct
3991 *
3992 * Reconfigure VEB/VSIs on a given PF; it is assumed that
3993 * the caller would've quiesce all the VSIs before calling
3994 * this function
3995 **/
3996static void i40e_dcb_reconfigure(struct i40e_pf *pf)
3997{
3998 u8 tc_map = 0;
3999 int ret;
4000 u8 v;
4001
4002 /* Enable the TCs available on PF to all VEBs */
4003 tc_map = i40e_pf_get_tc_map(pf);
4004 for (v = 0; v < I40E_MAX_VEB; v++) {
4005 if (!pf->veb[v])
4006 continue;
4007 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4008 if (ret) {
4009 dev_info(&pf->pdev->dev,
4010 "Failed configuring TC for VEB seid=%d\n",
4011 pf->veb[v]->seid);
4012 /* Will try to configure as many components */
4013 }
4014 }
4015
4016 /* Update each VSI */
4017 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4018 if (!pf->vsi[v])
4019 continue;
4020
4021 /* - Enable all TCs for the LAN VSI
4022 * - For all others keep them at TC0 for now
4023 */
4024 if (v == pf->lan_vsi)
4025 tc_map = i40e_pf_get_tc_map(pf);
4026 else
4027 tc_map = i40e_pf_get_default_tc(pf);
4028
4029 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4030 if (ret) {
4031 dev_info(&pf->pdev->dev,
4032 "Failed configuring TC for VSI seid=%d\n",
4033 pf->vsi[v]->seid);
4034 /* Will try to configure as many components */
4035 } else {
4036 if (pf->vsi[v]->netdev)
4037 i40e_dcbnl_set_all(pf->vsi[v]);
4038 }
4039 }
4040}
4041
4042/**
4043 * i40e_init_pf_dcb - Initialize DCB configuration
4044 * @pf: PF being configured
4045 *
4046 * Query the current DCB configuration and cache it
4047 * in the hardware structure
4048 **/
4049static int i40e_init_pf_dcb(struct i40e_pf *pf)
4050{
4051 struct i40e_hw *hw = &pf->hw;
4052 int err = 0;
4053
4054 if (pf->hw.func_caps.npar_enable)
4055 goto out;
4056
4057 /* Get the initial DCB configuration */
4058 err = i40e_init_dcb(hw);
4059 if (!err) {
4060 /* Device/Function is not DCBX capable */
4061 if ((!hw->func_caps.dcb) ||
4062 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4063 dev_info(&pf->pdev->dev,
4064 "DCBX offload is not supported or is disabled for this PF.\n");
4065
4066 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4067 goto out;
4068
4069 } else {
4070 /* When status is not DISABLED then DCBX in FW */
4071 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4072 DCB_CAP_DCBX_VER_IEEE;
4073 pf->flags |= I40E_FLAG_DCB_ENABLED;
4074 }
4075 }
4076
4077out:
4078 return err;
4079}
4080#endif /* CONFIG_I40E_DCB */
4081
41c445ff
JB		 4082/**
4083 * i40e_up_complete - Finish the last steps of bringing up a connection
4084 * @vsi: the VSI being configured
4085 **/
4086static int i40e_up_complete(struct i40e_vsi *vsi)
4087{
4088 struct i40e_pf *pf = vsi->back;
4089 int err;
4090
4091 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4092 i40e_vsi_configure_msix(vsi);
4093 else
4094 i40e_configure_msi_and_legacy(vsi);
4095
4096 /* start rings */
4097 err = i40e_vsi_control_rings(vsi, true);
4098 if (err)
4099 return err;
4100
4101 clear_bit(__I40E_DOWN, &vsi->state);
4102 i40e_napi_enable_all(vsi);
4103 i40e_vsi_enable_irq(vsi);
4104
4105 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4106 (vsi->netdev)) {
6d779b41 4107 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4108 netif_tx_start_all_queues(vsi->netdev);
4109 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4110 } else if (vsi->netdev) {
4111 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff 4112 }
ca64fa4e
ASJ		 4113
4114 /* replay FDIR SB filters */
4115 if (vsi->type == I40E_VSI_FDIR)
4116 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4117 i40e_service_event_schedule(pf);
4118
4119 return 0;
4120}
4121
4122/**
4123 * i40e_vsi_reinit_locked - Reset the VSI
4124 * @vsi: the VSI being configured
4125 *
4126 * Rebuild the ring structs after some configuration
4127 * has changed, e.g. MTU size.
4128 **/
4129static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4130{
4131 struct i40e_pf *pf = vsi->back;
4132
4133 WARN_ON(in_interrupt());
4134 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4135 usleep_range(1000, 2000);
4136 i40e_down(vsi);
4137
4138 /* Give a VF some time to respond to the reset. The
4139 * two second wait is based upon the watchdog cycle in
4140 * the VF driver.
4141 */
4142 if (vsi->type == I40E_VSI_SRIOV)
4143 msleep(2000);
4144 i40e_up(vsi);
4145 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4146}
4147
4148/**
4149 * i40e_up - Bring the connection back up after being down
4150 * @vsi: the VSI being configured
4151 **/
4152int i40e_up(struct i40e_vsi *vsi)
4153{
4154 int err;
4155
4156 err = i40e_vsi_configure(vsi);
4157 if (!err)
4158 err = i40e_up_complete(vsi);
4159
4160 return err;
4161}
4162
4163/**
4164 * i40e_down - Shutdown the connection processing
4165 * @vsi: the VSI being stopped
4166 **/
4167void i40e_down(struct i40e_vsi *vsi)
4168{
4169 int i;
4170
4171 /* It is assumed that the caller of this function
4172 * sets the vsi->state __I40E_DOWN bit.
4173 */
4174 if (vsi->netdev) {
4175 netif_carrier_off(vsi->netdev);
4176 netif_tx_disable(vsi->netdev);
4177 }
4178 i40e_vsi_disable_irq(vsi);
4179 i40e_vsi_control_rings(vsi, false);
4180 i40e_napi_disable_all(vsi);
4181
4182 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4183 i40e_clean_tx_ring(vsi->tx_rings[i]);
4184 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4185 }
4186}
4187
4188/**
4189 * i40e_setup_tc - configure multiple traffic classes
4190 * @netdev: net device to configure
4191 * @tc: number of traffic classes to enable
4192 **/
4193static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4194{
4195 struct i40e_netdev_priv *np = netdev_priv(netdev);
4196 struct i40e_vsi *vsi = np->vsi;
4197 struct i40e_pf *pf = vsi->back;
4198 u8 enabled_tc = 0;
4199 int ret = -EINVAL;
4200 int i;
4201
4202 /* Check if DCB enabled to continue */
4203 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4204 netdev_info(netdev, "DCB is not enabled for adapter\n");
4205 goto exit;
4206 }
4207
4208 /* Check if MFP enabled */
4209 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4210 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4211 goto exit;
4212 }
4213
4214 /* Check whether tc count is within enabled limit */
4215 if (tc > i40e_pf_get_num_tc(pf)) {
4216 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4217 goto exit;
4218 }
4219
4220 /* Generate TC map for number of tc requested */
4221 for (i = 0; i < tc; i++)
4222 enabled_tc |= (1 << i);
4223
4224 /* Requesting same TC configuration as already enabled */
4225 if (enabled_tc == vsi->tc_config.enabled_tc)
4226 return 0;
4227
4228 /* Quiesce VSI queues */
4229 i40e_quiesce_vsi(vsi);
4230
4231 /* Configure VSI for enabled TCs */
4232 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4233 if (ret) {
4234 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4235 vsi->seid);
4236 goto exit;
4237 }
4238
4239 /* Unquiesce VSI */
4240 i40e_unquiesce_vsi(vsi);
4241
4242exit:
4243 return ret;
4244}
4245
4246/**
4247 * i40e_open - Called when a network interface is made active
4248 * @netdev: network interface device structure
4249 *
4250 * The open entry point is called when a network interface is made
4251 * active by the system (IFF_UP). At this point all resources needed
4252 * for transmit and receive operations are allocated, the interrupt
4253 * handler is registered with the OS, the netdev watchdog subtask is
4254 * enabled, and the stack is notified that the interface is ready.
4255 *
4256 * Returns 0 on success, negative value on failure
4257 **/
4258static int i40e_open(struct net_device *netdev)
4259{
4260 struct i40e_netdev_priv *np = netdev_priv(netdev);
4261 struct i40e_vsi *vsi = np->vsi;
4262 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4263 int err;
4264
4eb3f768
SN		 4265 /* disallow open during test or if eeprom is broken */
4266 if (test_bit(__I40E_TESTING, &pf->state) ||
4267 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4268 return -EBUSY;
4269
4270 netif_carrier_off(netdev);
4271
6c167f58
EK		 4272 err = i40e_vsi_open(vsi);
4273 if (err)
4274 return err;
4275
4276#ifdef CONFIG_I40E_VXLAN
4277 vxlan_get_rx_port(netdev);
4278#endif
4279
4280 return 0;
4281}
4282
4283/**
4284 * i40e_vsi_open -
4285 * @vsi: the VSI to open
4286 *
4287 * Finish initialization of the VSI.
4288 *
4289 * Returns 0 on success, negative value on failure
4290 **/
4291int i40e_vsi_open(struct i40e_vsi *vsi)
4292{
4293 struct i40e_pf *pf = vsi->back;
4294 char int_name[IFNAMSIZ];
4295 int err;
4296
41c445ff
JB		 4297 /* allocate descriptors */
4298 err = i40e_vsi_setup_tx_resources(vsi);
4299 if (err)
4300 goto err_setup_tx;
4301 err = i40e_vsi_setup_rx_resources(vsi);
4302 if (err)
4303 goto err_setup_rx;
4304
4305 err = i40e_vsi_configure(vsi);
4306 if (err)
4307 goto err_setup_rx;
4308
6c167f58
EK		 4309 if (!vsi->netdev) {
4310 err = EINVAL;
4311 goto err_setup_rx;
4312 }
41c445ff 4313 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
6c167f58 4314 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
41c445ff
JB		 4315 err = i40e_vsi_request_irq(vsi, int_name);
4316 if (err)
4317 goto err_setup_rx;
4318
25946ddb 4319 /* Notify the stack of the actual queue counts. */
6c167f58 4320 err = netif_set_real_num_tx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4321 if (err)
4322 goto err_set_queues;
4323
6c167f58 4324 err = netif_set_real_num_rx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4325 if (err)
4326 goto err_set_queues;
4327
41c445ff
JB		 4328 err = i40e_up_complete(vsi);
4329 if (err)
4330 goto err_up_complete;
4331
41c445ff
JB		 4332 return 0;
4333
4334err_up_complete:
4335 i40e_down(vsi);
25946ddb 4336err_set_queues:
41c445ff
JB		 4337 i40e_vsi_free_irq(vsi);
4338err_setup_rx:
4339 i40e_vsi_free_rx_resources(vsi);
4340err_setup_tx:
4341 i40e_vsi_free_tx_resources(vsi);
4342 if (vsi == pf->vsi[pf->lan_vsi])
4343 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4344
4345 return err;
4346}
4347
17a73f6b
JG		 4348/**
4349 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4350 * @pf: Pointer to pf
4351 *
4352 * This function destroys the hlist where all the Flow Director
4353 * filters were saved.
4354 **/
4355static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4356{
4357 struct i40e_fdir_filter *filter;
4358 struct hlist_node *node2;
4359
4360 hlist_for_each_entry_safe(filter, node2,
4361 &pf->fdir_filter_list, fdir_node) {
4362 hlist_del(&filter->fdir_node);
4363 kfree(filter);
4364 }
4365 pf->fdir_pf_active_filters = 0;
4366}
4367
41c445ff
JB		 4368/**
4369 * i40e_close - Disables a network interface
4370 * @netdev: network interface device structure
4371 *
4372 * The close entry point is called when an interface is de-activated
4373 * by the OS. The hardware is still under the driver's control, but
4374 * this netdev interface is disabled.
4375 *
4376 * Returns 0, this is not allowed to fail
4377 **/
4378static int i40e_close(struct net_device *netdev)
4379{
4380 struct i40e_netdev_priv *np = netdev_priv(netdev);
4381 struct i40e_vsi *vsi = np->vsi;
4382
4383 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4384 return 0;
4385
4386 i40e_down(vsi);
4387 i40e_vsi_free_irq(vsi);
4388
4389 i40e_vsi_free_tx_resources(vsi);
4390 i40e_vsi_free_rx_resources(vsi);
4391
4392 return 0;
4393}
4394
4395/**
4396 * i40e_do_reset - Start a PF or Core Reset sequence
4397 * @pf: board private structure
4398 * @reset_flags: which reset is requested
4399 *
4400 * The essential difference in resets is that the PF Reset
4401 * doesn't clear the packet buffers, doesn't reset the PE
4402 * firmware, and doesn't bother the other PFs on the chip.
4403 **/
4404void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4405{
4406 u32 val;
4407
4408 WARN_ON(in_interrupt());
4409
4410 /* do the biggest reset indicated */
4411 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4412
4413 /* Request a Global Reset
4414 *
4415 * This will start the chip's countdown to the actual full
4416 * chip reset event, and a warning interrupt to be sent
4417 * to all PFs, including the requestor. Our handler
4418 * for the warning interrupt will deal with the shutdown
4419 * and recovery of the switch setup.
4420 */
69bfb110 4421 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4422 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4423 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4424 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4425
4426 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4427
4428 /* Request a Core Reset
4429 *
4430 * Same as Global Reset, except does *not* include the MAC/PHY
4431 */
69bfb110 4432 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4433 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4434 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4435 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4436 i40e_flush(&pf->hw);
4437
7823fe34
SN		 4438 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4439
4440 /* Request a Firmware Reset
4441 *
4442 * Same as Global reset, plus restarting the
4443 * embedded firmware engine.
4444 */
4445 /* enable EMP Reset */
4446 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4447 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4448 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4449
4450 /* force the reset */
4451 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4452 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4453 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4454 i40e_flush(&pf->hw);
4455
41c445ff
JB		 4456 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4457
4458 /* Request a PF Reset
4459 *
4460 * Resets only the PF-specific registers
4461 *
4462 * This goes directly to the tear-down and rebuild of
4463 * the switch, since we need to do all the recovery as
4464 * for the Core Reset.
4465 */
69bfb110 4466 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4467 i40e_handle_reset_warning(pf);
4468
4469 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4470 int v;
4471
4472 /* Find the VSI(s) that requested a re-init */
4473 dev_info(&pf->pdev->dev,
4474 "VSI reinit requested\n");
4475 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4476 struct i40e_vsi *vsi = pf->vsi[v];
4477 if (vsi != NULL &&
4478 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4479 i40e_vsi_reinit_locked(pf->vsi[v]);
4480 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4481 }
4482 }
4483
4484 /* no further action needed, so return now */
4485 return;
4486 } else {
4487 dev_info(&pf->pdev->dev,
4488 "bad reset request 0x%08x\n", reset_flags);
4489 return;
4490 }
4491}
4492
4e3b35b0
NP		 4493#ifdef CONFIG_I40E_DCB
4494/**
4495 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4496 * @pf: board private structure
4497 * @old_cfg: current DCB config
4498 * @new_cfg: new DCB config
4499 **/
4500bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4501 struct i40e_dcbx_config *old_cfg,
4502 struct i40e_dcbx_config *new_cfg)
4503{
4504 bool need_reconfig = false;
4505
4506 /* Check if ETS configuration has changed */
4507 if (memcmp(&new_cfg->etscfg,
4508 &old_cfg->etscfg,
4509 sizeof(new_cfg->etscfg))) {
4510 /* If Priority Table has changed reconfig is needed */
4511 if (memcmp(&new_cfg->etscfg.prioritytable,
4512 &old_cfg->etscfg.prioritytable,
4513 sizeof(new_cfg->etscfg.prioritytable))) {
4514 need_reconfig = true;
69bfb110 4515 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4516 }
4517
4518 if (memcmp(&new_cfg->etscfg.tcbwtable,
4519 &old_cfg->etscfg.tcbwtable,
4520 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4521 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4522
4523 if (memcmp(&new_cfg->etscfg.tsatable,
4524 &old_cfg->etscfg.tsatable,
4525 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4526 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4527 }
4528
4529 /* Check if PFC configuration has changed */
4530 if (memcmp(&new_cfg->pfc,
4531 &old_cfg->pfc,
4532 sizeof(new_cfg->pfc))) {
4533 need_reconfig = true;
69bfb110 4534 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4535 }
4536
4537 /* Check if APP Table has changed */
4538 if (memcmp(&new_cfg->app,
4539 &old_cfg->app,
3d9667a9 4540 sizeof(new_cfg->app))) {
4e3b35b0 4541 need_reconfig = true;
69bfb110 4542 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4543 }
4e3b35b0
NP		 4544
4545 return need_reconfig;
4546}
4547
4548/**
4549 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4550 * @pf: board private structure
4551 * @e: event info posted on ARQ
4552 **/
4553static int i40e_handle_lldp_event(struct i40e_pf *pf,
4554 struct i40e_arq_event_info *e)
4555{
4556 struct i40e_aqc_lldp_get_mib *mib =
4557 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4558 struct i40e_hw *hw = &pf->hw;
4559 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4560 struct i40e_dcbx_config tmp_dcbx_cfg;
4561 bool need_reconfig = false;
4562 int ret = 0;
4563 u8 type;
4564
4565 /* Ignore if event is not for Nearest Bridge */
4566 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4567 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4568 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4569 return ret;
4570
4571 /* Check MIB Type and return if event for Remote MIB update */
4572 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4573 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4574 /* Update the remote cached instance and return */
4575 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4576 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4577 &hw->remote_dcbx_config);
4578 goto exit;
4579 }
4580
4581 /* Convert/store the DCBX data from LLDPDU temporarily */
4582 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4583 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4584 if (ret) {
4585 /* Error in LLDPDU parsing return */
4586 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4587 goto exit;
4588 }
4589
4590 /* No change detected in DCBX configs */
4591 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4592 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4593 goto exit;
4594 }
4595
4596 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4597
4598 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4599
4600 /* Overwrite the new configuration */
4601 *dcbx_cfg = tmp_dcbx_cfg;
4602
4603 if (!need_reconfig)
4604 goto exit;
4605
4606 /* Reconfiguration needed quiesce all VSIs */
4607 i40e_pf_quiesce_all_vsi(pf);
4608
4609 /* Changes in configuration update VEB/VSI */
4610 i40e_dcb_reconfigure(pf);
4611
4612 i40e_pf_unquiesce_all_vsi(pf);
4613exit:
4614 return ret;
4615}
4616#endif /* CONFIG_I40E_DCB */
4617
23326186
ASJ		 4618/**
4619 * i40e_do_reset_safe - Protected reset path for userland calls.
4620 * @pf: board private structure
4621 * @reset_flags: which reset is requested
4622 *
4623 **/
4624void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4625{
4626 rtnl_lock();
4627 i40e_do_reset(pf, reset_flags);
4628 rtnl_unlock();
4629}
4630
41c445ff
JB		 4631/**
4632 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4633 * @pf: board private structure
4634 * @e: event info posted on ARQ
4635 *
4636 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4637 * and VF queues
4638 **/
4639static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4640 struct i40e_arq_event_info *e)
4641{
4642 struct i40e_aqc_lan_overflow *data =
4643 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4644 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4645 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4646 struct i40e_hw *hw = &pf->hw;
4647 struct i40e_vf *vf;
4648 u16 vf_id;
4649
69bfb110
JB		 4650 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4651 queue, qtx_ctl);
41c445ff
JB		 4652
4653 /* Queue belongs to VF, find the VF and issue VF reset */
4654 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4655 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4656 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4657 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4658 vf_id -= hw->func_caps.vf_base_id;
4659 vf = &pf->vf[vf_id];
4660 i40e_vc_notify_vf_reset(vf);
4661 /* Allow VF to process pending reset notification */
4662 msleep(20);
4663 i40e_reset_vf(vf, false);
4664 }
4665}
4666
4667/**
4668 * i40e_service_event_complete - Finish up the service event
4669 * @pf: board private structure
4670 **/
4671static void i40e_service_event_complete(struct i40e_pf *pf)
4672{
4673 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4674
4675 /* flush memory to make sure state is correct before next watchog */
4676 smp_mb__before_clear_bit();
4677 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4678}
4679
55a5e60b
ASJ		 4680/**
4681 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4682 * @pf: board private structure
4683 **/
4684int i40e_get_current_fd_count(struct i40e_pf *pf)
4685{
4686 int val, fcnt_prog;
4687 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4688 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4689 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4690 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4691 return fcnt_prog;
4692}
4693
4694/**
4695 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4696 * @pf: board private structure
4697 **/
4698void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4699{
4700 u32 fcnt_prog, fcnt_avail;
4701
4702 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4703 * to re-enable
4704 */
4705 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4706 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4707 return;
4708 fcnt_prog = i40e_get_current_fd_count(pf);
4709 fcnt_avail = pf->hw.fdir_shared_filter_count +
4710 pf->fdir_pf_filter_count;
4711 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4712 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4713 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4714 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4715 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4716 }
4717 }
4718 /* Wait for some more space to be available to turn on ATR */
4719 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4720 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4721 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4722 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4723 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4724 }
4725 }
4726}
4727
41c445ff
JB		 4728/**
4729 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4730 * @pf: board private structure
4731 **/
4732static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4733{
4734 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4735 return;
4736
41c445ff
JB		 4737 /* if interface is down do nothing */
4738 if (test_bit(__I40E_DOWN, &pf->state))
4739 return;
55a5e60b
ASJ		 4740 i40e_fdir_check_and_reenable(pf);
4741
4742 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4743 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4744 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4745}
4746
4747/**
4748 * i40e_vsi_link_event - notify VSI of a link event
4749 * @vsi: vsi to be notified
4750 * @link_up: link up or down
4751 **/
4752static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4753{
4754 if (!vsi)
4755 return;
4756
4757 switch (vsi->type) {
4758 case I40E_VSI_MAIN:
4759 if (!vsi->netdev || !vsi->netdev_registered)
4760 break;
4761
4762 if (link_up) {
4763 netif_carrier_on(vsi->netdev);
4764 netif_tx_wake_all_queues(vsi->netdev);
4765 } else {
4766 netif_carrier_off(vsi->netdev);
4767 netif_tx_stop_all_queues(vsi->netdev);
4768 }
4769 break;
4770
4771 case I40E_VSI_SRIOV:
4772 break;
4773
4774 case I40E_VSI_VMDQ2:
4775 case I40E_VSI_CTRL:
4776 case I40E_VSI_MIRROR:
4777 default:
4778 /* there is no notification for other VSIs */
4779 break;
4780 }
4781}
4782
4783/**
4784 * i40e_veb_link_event - notify elements on the veb of a link event
4785 * @veb: veb to be notified
4786 * @link_up: link up or down
4787 **/
4788static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4789{
4790 struct i40e_pf *pf;
4791 int i;
4792
4793 if (!veb || !veb->pf)
4794 return;
4795 pf = veb->pf;
4796
4797 /* depth first... */
4798 for (i = 0; i < I40E_MAX_VEB; i++)
4799 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4800 i40e_veb_link_event(pf->veb[i], link_up);
4801
4802 /* ... now the local VSIs */
4803 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4804 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4805 i40e_vsi_link_event(pf->vsi[i], link_up);
4806}
4807
4808/**
4809 * i40e_link_event - Update netif_carrier status
4810 * @pf: board private structure
4811 **/
4812static void i40e_link_event(struct i40e_pf *pf)
4813{
4814 bool new_link, old_link;
4815
4816 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4817 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4818
4819 if (new_link == old_link)
4820 return;
4821
6d779b41
AS		 4822 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4823 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4824 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4825
4826 /* Notify the base of the switch tree connected to
4827 * the link. Floating VEBs are not notified.
4828 */
4829 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4830 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4831 else
4832 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4833
4834 if (pf->vf)
4835 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4836
4837 if (pf->flags & I40E_FLAG_PTP)
4838 i40e_ptp_set_increment(pf);
41c445ff
JB		 4839}
4840
4841/**
4842 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4843 * @pf: board private structure
4844 *
4845 * Set the per-queue flags to request a check for stuck queues in the irq
4846 * clean functions, then force interrupts to be sure the irq clean is called.
4847 **/
4848static void i40e_check_hang_subtask(struct i40e_pf *pf)
4849{
4850 int i, v;
4851
4852 /* If we're down or resetting, just bail */
4853 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4854 return;
4855
4856 /* for each VSI/netdev
4857 * for each Tx queue
4858 * set the check flag
4859 * for each q_vector
4860 * force an interrupt
4861 */
4862 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4863 struct i40e_vsi *vsi = pf->vsi[v];
4864 int armed = 0;
4865
4866 if (!pf->vsi[v] ||
4867 test_bit(__I40E_DOWN, &vsi->state) ||
4868 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4869 continue;
4870
4871 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4872 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4873 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4874 &vsi->tx_rings[i]->state))
41c445ff
JB		 4875 armed++;
4876 }
4877
4878 if (armed) {
4879 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4880 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4881 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4882 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4883 } else {
4884 u16 vec = vsi->base_vector - 1;
4885 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4886 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4887 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4888 wr32(&vsi->back->hw,
4889 I40E_PFINT_DYN_CTLN(vec), val);
4890 }
4891 i40e_flush(&vsi->back->hw);
4892 }
4893 }
4894}
4895
4896/**
4897 * i40e_watchdog_subtask - Check and bring link up
4898 * @pf: board private structure
4899 **/
4900static void i40e_watchdog_subtask(struct i40e_pf *pf)
4901{
4902 int i;
4903
4904 /* if interface is down do nothing */
4905 if (test_bit(__I40E_DOWN, &pf->state) ||
4906 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4907 return;
4908
4909 /* Update the stats for active netdevs so the network stack
4910 * can look at updated numbers whenever it cares to
4911 */
4912 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4913 if (pf->vsi[i] && pf->vsi[i]->netdev)
4914 i40e_update_stats(pf->vsi[i]);
4915
4916 /* Update the stats for the active switching components */
4917 for (i = 0; i < I40E_MAX_VEB; i++)
4918 if (pf->veb[i])
4919 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4920
4921 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4922}
4923
4924/**
4925 * i40e_reset_subtask - Set up for resetting the device and driver
4926 * @pf: board private structure
4927 **/
4928static void i40e_reset_subtask(struct i40e_pf *pf)
4929{
4930 u32 reset_flags = 0;
4931
23326186 4932 rtnl_lock();
41c445ff
JB		 4933 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4934 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4935 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4936 }
4937 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4938 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4939 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4940 }
4941 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4942 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4943 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4944 }
4945 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4946 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4947 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4948 }
4949
4950 /* If there's a recovery already waiting, it takes
4951 * precedence before starting a new reset sequence.
4952 */
4953 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4954 i40e_handle_reset_warning(pf);
23326186 4955 goto unlock;
41c445ff
JB		 4956 }
4957
4958 /* If we're already down or resetting, just bail */
4959 if (reset_flags &&
4960 !test_bit(__I40E_DOWN, &pf->state) &&
4961 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4962 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4963
4964unlock:
4965 rtnl_unlock();
41c445ff
JB		 4966}
4967
4968/**
4969 * i40e_handle_link_event - Handle link event
4970 * @pf: board private structure
4971 * @e: event info posted on ARQ
4972 **/
4973static void i40e_handle_link_event(struct i40e_pf *pf,
4974 struct i40e_arq_event_info *e)
4975{
4976 struct i40e_hw *hw = &pf->hw;
4977 struct i40e_aqc_get_link_status *status =
4978 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4979 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4980
4981 /* save off old link status information */
4982 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4983 sizeof(pf->hw.phy.link_info_old));
4984
4985 /* update link status */
4986 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4987 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4988 hw_link_info->link_info = status->link_info;
4989 hw_link_info->an_info = status->an_info;
4990 hw_link_info->ext_info = status->ext_info;
4991 hw_link_info->lse_enable =
4992 le16_to_cpu(status->command_flags) &
4993 I40E_AQ_LSE_ENABLE;
4994
4995 /* process the event */
4996 i40e_link_event(pf);
4997
4998 /* Do a new status request to re-enable LSE reporting
4999 * and load new status information into the hw struct,
5000 * then see if the status changed while processing the
5001 * initial event.
5002 */
5003 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5004 i40e_link_event(pf);
5005}
5006
5007/**
5008 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5009 * @pf: board private structure
5010 **/
5011static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5012{
5013 struct i40e_arq_event_info event;
5014 struct i40e_hw *hw = &pf->hw;
5015 u16 pending, i = 0;
5016 i40e_status ret;
5017 u16 opcode;
5018 u32 val;
5019
5020 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5021 return;
5022
3197ce22 5023 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5024 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5025 if (!event.msg_buf)
5026 return;
5027
5028 do {
2f019123 5029 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5030 ret = i40e_clean_arq_element(hw, &event, &pending);
5031 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5032 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5033 break;
5034 } else if (ret) {
5035 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5036 break;
5037 }
5038
5039 opcode = le16_to_cpu(event.desc.opcode);
5040 switch (opcode) {
5041
5042 case i40e_aqc_opc_get_link_status:
5043 i40e_handle_link_event(pf, &event);
5044 break;
5045 case i40e_aqc_opc_send_msg_to_pf:
5046 ret = i40e_vc_process_vf_msg(pf,
5047 le16_to_cpu(event.desc.retval),
5048 le32_to_cpu(event.desc.cookie_high),
5049 le32_to_cpu(event.desc.cookie_low),
5050 event.msg_buf,
5051 event.msg_size);
5052 break;
5053 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5054 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5055#ifdef CONFIG_I40E_DCB
5056 rtnl_lock();
5057 ret = i40e_handle_lldp_event(pf, &event);
5058 rtnl_unlock();
5059#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5060 break;
5061 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5062 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5063 i40e_handle_lan_overflow_event(pf, &event);
5064 break;
0467bc91
SN		 5065 case i40e_aqc_opc_send_msg_to_peer:
5066 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5067 break;
41c445ff
JB		 5068 default:
5069 dev_info(&pf->pdev->dev,
0467bc91
SN		 5070 "ARQ Error: Unknown event 0x%04x received\n",
5071 opcode);
41c445ff
JB		 5072 break;
5073 }
5074 } while (pending && (i++ < pf->adminq_work_limit));
5075
5076 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5077 /* re-enable Admin queue interrupt cause */
5078 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5079 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5080 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5081 i40e_flush(hw);
5082
5083 kfree(event.msg_buf);
5084}
5085
4eb3f768
SN		 5086/**
5087 * i40e_verify_eeprom - make sure eeprom is good to use
5088 * @pf: board private structure
5089 **/
5090static void i40e_verify_eeprom(struct i40e_pf *pf)
5091{
5092 int err;
5093
5094 err = i40e_diag_eeprom_test(&pf->hw);
5095 if (err) {
5096 /* retry in case of garbage read */
5097 err = i40e_diag_eeprom_test(&pf->hw);
5098 if (err) {
5099 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5100 err);
5101 set_bit(__I40E_BAD_EEPROM, &pf->state);
5102 }
5103 }
5104
5105 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5106 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5107 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5108 }
5109}
5110
41c445ff
JB		 5111/**
5112 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5113 * @veb: pointer to the VEB instance
5114 *
5115 * This is a recursive function that first builds the attached VSIs then
5116 * recurses in to build the next layer of VEB. We track the connections
5117 * through our own index numbers because the seid's from the HW could
5118 * change across the reset.
5119 **/
5120static int i40e_reconstitute_veb(struct i40e_veb *veb)
5121{
5122 struct i40e_vsi *ctl_vsi = NULL;
5123 struct i40e_pf *pf = veb->pf;
5124 int v, veb_idx;
5125 int ret;
5126
5127 /* build VSI that owns this VEB, temporarily attached to base VEB */
5128 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5129 if (pf->vsi[v] &&
5130 pf->vsi[v]->veb_idx == veb->idx &&
5131 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5132 ctl_vsi = pf->vsi[v];
5133 break;
5134 }
5135 }
5136 if (!ctl_vsi) {
5137 dev_info(&pf->pdev->dev,
5138 "missing owner VSI for veb_idx %d\n", veb->idx);
5139 ret = -ENOENT;
5140 goto end_reconstitute;
5141 }
5142 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5143 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5144 ret = i40e_add_vsi(ctl_vsi);
5145 if (ret) {
5146 dev_info(&pf->pdev->dev,
5147 "rebuild of owner VSI failed: %d\n", ret);
5148 goto end_reconstitute;
5149 }
5150 i40e_vsi_reset_stats(ctl_vsi);
5151
5152 /* create the VEB in the switch and move the VSI onto the VEB */
5153 ret = i40e_add_veb(veb, ctl_vsi);
5154 if (ret)
5155 goto end_reconstitute;
5156
5157 /* create the remaining VSIs attached to this VEB */
5158 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5159 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5160 continue;
5161
5162 if (pf->vsi[v]->veb_idx == veb->idx) {
5163 struct i40e_vsi *vsi = pf->vsi[v];
5164 vsi->uplink_seid = veb->seid;
5165 ret = i40e_add_vsi(vsi);
5166 if (ret) {
5167 dev_info(&pf->pdev->dev,
5168 "rebuild of vsi_idx %d failed: %d\n",
5169 v, ret);
5170 goto end_reconstitute;
5171 }
5172 i40e_vsi_reset_stats(vsi);
5173 }
5174 }
5175
5176 /* create any VEBs attached to this VEB - RECURSION */
5177 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5178 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5179 pf->veb[veb_idx]->uplink_seid = veb->seid;
5180 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5181 if (ret)
5182 break;
5183 }
5184 }
5185
5186end_reconstitute:
5187 return ret;
5188}
5189
5190/**
5191 * i40e_get_capabilities - get info about the HW
5192 * @pf: the PF struct
5193 **/
5194static int i40e_get_capabilities(struct i40e_pf *pf)
5195{
5196 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5197 u16 data_size;
5198 int buf_len;
5199 int err;
5200
5201 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5202 do {
5203 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5204 if (!cap_buf)
5205 return -ENOMEM;
5206
5207 /* this loads the data into the hw struct for us */
5208 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5209 &data_size,
5210 i40e_aqc_opc_list_func_capabilities,
5211 NULL);
5212 /* data loaded, buffer no longer needed */
5213 kfree(cap_buf);
5214
5215 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5216 /* retry with a larger buffer */
5217 buf_len = data_size;
5218 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5219 dev_info(&pf->pdev->dev,
5220 "capability discovery failed: aq=%d\n",
5221 pf->hw.aq.asq_last_status);
5222 return -ENODEV;
5223 }
5224 } while (err);
5225
d0b10249
JB		 5226 /* increment MSI-X count because current FW skips one */
5227 pf->hw.func_caps.num_msix_vectors++;
7134f9ce 5228
ac71b7ba
ASJ		 5229 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5230 (pf->hw.aq.fw_maj_ver < 2)) {
5231 pf->hw.func_caps.num_msix_vectors++;
5232 pf->hw.func_caps.num_msix_vectors_vf++;
5233 }
5234
41c445ff
JB		 5235 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5236 dev_info(&pf->pdev->dev,
5237 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5238 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5239 pf->hw.func_caps.num_msix_vectors,
5240 pf->hw.func_caps.num_msix_vectors_vf,
5241 pf->hw.func_caps.fd_filters_guaranteed,
5242 pf->hw.func_caps.fd_filters_best_effort,
5243 pf->hw.func_caps.num_tx_qp,
5244 pf->hw.func_caps.num_vsis);
5245
7134f9ce
JB		 5246#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5247 + pf->hw.func_caps.num_vfs)
5248 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5249 dev_info(&pf->pdev->dev,
5250 "got num_vsis %d, setting num_vsis to %d\n",
5251 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5252 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5253 }
5254
41c445ff
JB		 5255 return 0;
5256}
5257
cbf61325
ASJ		 5258static int i40e_vsi_clear(struct i40e_vsi *vsi);
5259
41c445ff 5260/**
cbf61325 5261 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5262 * @pf: board private structure
5263 **/
cbf61325 5264static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5265{
5266 struct i40e_vsi *vsi;
5267 bool new_vsi = false;
5268 int err, i;
5269
cbf61325 5270 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5271 return;
5272
cbf61325 5273 /* find existing VSI and see if it needs configuring */
41c445ff 5274 vsi = NULL;
cbf61325
ASJ		 5275 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5276 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5277 vsi = pf->vsi[i];
cbf61325
ASJ		 5278 break;
5279 }
5280 }
5281
5282 /* create a new VSI if none exists */
41c445ff 5283 if (!vsi) {
cbf61325
ASJ		 5284 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5285 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5286 if (!vsi) {
5287 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
cbf61325 5288 goto err_vsi;
41c445ff
JB		 5289 }
5290 new_vsi = true;
5291 }
cbf61325 5292 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5293
5294 err = i40e_vsi_setup_tx_resources(vsi);
cbf61325
ASJ		 5295 if (err)
5296 goto err_setup_tx;
5297 err = i40e_vsi_setup_rx_resources(vsi);
5298 if (err)
5299 goto err_setup_rx;
5300
5301 if (new_vsi) {
41c445ff 5302 char int_name[IFNAMSIZ + 9];
cbf61325
ASJ		 5303 err = i40e_vsi_configure(vsi);
5304 if (err)
5305 goto err_setup_rx;
41c445ff
JB		 5306 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
5307 dev_driver_string(&pf->pdev->dev));
5308 err = i40e_vsi_request_irq(vsi, int_name);
cbf61325
ASJ		 5309 if (err)
5310 goto err_setup_rx;
41c445ff 5311 err = i40e_up_complete(vsi);
cbf61325
ASJ		 5312 if (err)
5313 goto err_up_complete;
17a73f6b 5314 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
cbf61325 5315 }
41c445ff 5316
cbf61325
ASJ		 5317 return;
5318
5319err_up_complete:
5320 i40e_down(vsi);
5321 i40e_vsi_free_irq(vsi);
5322err_setup_rx:
5323 i40e_vsi_free_rx_resources(vsi);
5324err_setup_tx:
5325 i40e_vsi_free_tx_resources(vsi);
5326err_vsi:
5327 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5328 i40e_vsi_clear(vsi);
41c445ff
JB		 5329}
5330
5331/**
5332 * i40e_fdir_teardown - release the Flow Director resources
5333 * @pf: board private structure
5334 **/
5335static void i40e_fdir_teardown(struct i40e_pf *pf)
5336{
5337 int i;
5338
17a73f6b 5339 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5340 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5341 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5342 i40e_vsi_release(pf->vsi[i]);
5343 break;
5344 }
5345 }
5346}
5347
5348/**
f650a38b 5349 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5350 * @pf: board private structure
5351 *
f650a38b
ASJ		 5352 * Close up the VFs and other things in prep for pf Reset.
5353 **/
5354static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5355{
41c445ff
JB		 5356 struct i40e_hw *hw = &pf->hw;
5357 i40e_status ret;
5358 u32 v;
5359
5360 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5361 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5362 return 0;
41c445ff 5363
69bfb110 5364 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5365
37f0be6d
ASJ		 5366 if (i40e_check_asq_alive(hw))
5367 i40e_vc_notify_reset(pf);
41c445ff
JB		 5368
5369 /* quiesce the VSIs and their queues that are not already DOWN */
5370 i40e_pf_quiesce_all_vsi(pf);
5371
5372 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5373 if (pf->vsi[v])
5374 pf->vsi[v]->seid = 0;
5375 }
5376
5377 i40e_shutdown_adminq(&pf->hw);
5378
f650a38b
ASJ		 5379 /* call shutdown HMC */
5380 ret = i40e_shutdown_lan_hmc(hw);
5381 if (ret) {
5382 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5383 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5384 }
5385 return ret;
5386}
5387
5388/**
4dda12e6 5389 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5390 * @pf: board private structure
bc7d338f 5391 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5392 **/
bc7d338f 5393static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 5394{
5395 struct i40e_driver_version dv;
5396 struct i40e_hw *hw = &pf->hw;
5397 i40e_status ret;
5398 u32 v;
5399
41c445ff
JB		 5400 /* Now we wait for GRST to settle out.
5401 * We don't have to delete the VEBs or VSIs from the hw switch
5402 * because the reset will make them disappear.
5403 */
5404 ret = i40e_pf_reset(hw);
5405 if (ret)
5406 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
5407 pf->pfr_count++;
5408
5409 if (test_bit(__I40E_DOWN, &pf->state))
5410 goto end_core_reset;
69bfb110 5411 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5412
5413 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5414 ret = i40e_init_adminq(&pf->hw);
5415 if (ret) {
5416 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5417 goto end_core_reset;
5418 }
5419
4eb3f768
SN		 5420 /* re-verify the eeprom if we just had an EMP reset */
5421 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5422 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5423 i40e_verify_eeprom(pf);
5424 }
5425
41c445ff
JB		 5426 ret = i40e_get_capabilities(pf);
5427 if (ret) {
5428 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5429 ret);
5430 goto end_core_reset;
5431 }
5432
41c445ff
JB		 5433 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5434 hw->func_caps.num_rx_qp,
5435 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5436 if (ret) {
5437 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5438 goto end_core_reset;
5439 }
5440 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5441 if (ret) {
5442 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5443 goto end_core_reset;
5444 }
5445
4e3b35b0
NP		 5446#ifdef CONFIG_I40E_DCB
5447 ret = i40e_init_pf_dcb(pf);
5448 if (ret) {
5449 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5450 goto end_core_reset;
5451 }
5452#endif /* CONFIG_I40E_DCB */
5453
41c445ff 5454 /* do basic switch setup */
bc7d338f 5455 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5456 if (ret)
5457 goto end_core_reset;
5458
5459 /* Rebuild the VSIs and VEBs that existed before reset.
5460 * They are still in our local switch element arrays, so only
5461 * need to rebuild the switch model in the HW.
5462 *
5463 * If there were VEBs but the reconstitution failed, we'll try
5464 * try to recover minimal use by getting the basic PF VSI working.
5465 */
5466 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5467 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5468 /* find the one VEB connected to the MAC, and find orphans */
5469 for (v = 0; v < I40E_MAX_VEB; v++) {
5470 if (!pf->veb[v])
5471 continue;
5472
5473 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5474 pf->veb[v]->uplink_seid == 0) {
5475 ret = i40e_reconstitute_veb(pf->veb[v]);
5476
5477 if (!ret)
5478 continue;
5479
5480 /* If Main VEB failed, we're in deep doodoo,
5481 * so give up rebuilding the switch and set up
5482 * for minimal rebuild of PF VSI.
5483 * If orphan failed, we'll report the error
5484 * but try to keep going.
5485 */
5486 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5487 dev_info(&pf->pdev->dev,
5488 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5489 ret);
5490 pf->vsi[pf->lan_vsi]->uplink_seid
5491 = pf->mac_seid;
5492 break;
5493 } else if (pf->veb[v]->uplink_seid == 0) {
5494 dev_info(&pf->pdev->dev,
5495 "rebuild of orphan VEB failed: %d\n",
5496 ret);
5497 }
5498 }
5499 }
5500 }
5501
5502 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5503 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5504 /* no VEB, so rebuild only the Main VSI */
5505 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5506 if (ret) {
5507 dev_info(&pf->pdev->dev,
5508 "rebuild of Main VSI failed: %d\n", ret);
5509 goto end_core_reset;
5510 }
5511 }
5512
5513 /* reinit the misc interrupt */
5514 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5515 ret = i40e_setup_misc_vector(pf);
5516
5517 /* restart the VSIs that were rebuilt and running before the reset */
5518 i40e_pf_unquiesce_all_vsi(pf);
5519
69f64b2b
MW		 5520 if (pf->num_alloc_vfs) {
5521 for (v = 0; v < pf->num_alloc_vfs; v++)
5522 i40e_reset_vf(&pf->vf[v], true);
5523 }
5524
41c445ff
JB		 5525 /* tell the firmware that we're starting */
5526 dv.major_version = DRV_VERSION_MAJOR;
5527 dv.minor_version = DRV_VERSION_MINOR;
5528 dv.build_version = DRV_VERSION_BUILD;
5529 dv.subbuild_version = 0;
5530 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5531
69bfb110 5532 dev_info(&pf->pdev->dev, "reset complete\n");
41c445ff
JB		 5533
5534end_core_reset:
5535 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5536}
5537
f650a38b
ASJ		 5538/**
5539 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5540 * @pf: board private structure
5541 *
5542 * Close up the VFs and other things in prep for a Core Reset,
5543 * then get ready to rebuild the world.
5544 **/
5545static void i40e_handle_reset_warning(struct i40e_pf *pf)
5546{
5547 i40e_status ret;
5548
5549 ret = i40e_prep_for_reset(pf);
5550 if (!ret)
bc7d338f 5551 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5552}
5553
41c445ff
JB		 5554/**
5555 * i40e_handle_mdd_event
5556 * @pf: pointer to the pf structure
5557 *
5558 * Called from the MDD irq handler to identify possibly malicious vfs
5559 **/
5560static void i40e_handle_mdd_event(struct i40e_pf *pf)
5561{
5562 struct i40e_hw *hw = &pf->hw;
5563 bool mdd_detected = false;
5564 struct i40e_vf *vf;
5565 u32 reg;
5566 int i;
5567
5568 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5569 return;
5570
5571 /* find what triggered the MDD event */
5572 reg = rd32(hw, I40E_GL_MDET_TX);
5573 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5574 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5575 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5576 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5577 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5578 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5579 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5580 dev_info(&pf->pdev->dev,
f29eaa3d 5581 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5582 event, queue, func);
5583 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5584 mdd_detected = true;
5585 }
5586 reg = rd32(hw, I40E_GL_MDET_RX);
5587 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5588 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5589 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5590 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5591 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5592 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5593 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5594 dev_info(&pf->pdev->dev,
f29eaa3d 5595 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5596 event, queue, func);
5597 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5598 mdd_detected = true;
5599 }
5600
5601 /* see if one of the VFs needs its hand slapped */
5602 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5603 vf = &(pf->vf[i]);
5604 reg = rd32(hw, I40E_VP_MDET_TX(i));
5605 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5606 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5607 vf->num_mdd_events++;
5608 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5609 }
5610
5611 reg = rd32(hw, I40E_VP_MDET_RX(i));
5612 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5613 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5614 vf->num_mdd_events++;
5615 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5616 }
5617
5618 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5619 dev_info(&pf->pdev->dev,
5620 "Too many MDD events on VF %d, disabled\n", i);
5621 dev_info(&pf->pdev->dev,
5622 "Use PF Control I/F to re-enable the VF\n");
5623 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5624 }
5625 }
5626
5627 /* re-enable mdd interrupt cause */
5628 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5629 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5630 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5631 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5632 i40e_flush(hw);
5633}
5634
a1c9a9d9
JK		 5635#ifdef CONFIG_I40E_VXLAN
5636/**
5637 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5638 * @pf: board private structure
5639 **/
5640static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5641{
5642 const int vxlan_hdr_qwords = 4;
5643 struct i40e_hw *hw = &pf->hw;
5644 i40e_status ret;
5645 u8 filter_index;
5646 __be16 port;
5647 int i;
5648
5649 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5650 return;
5651
5652 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5653
5654 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5655 if (pf->pending_vxlan_bitmap & (1 << i)) {
5656 pf->pending_vxlan_bitmap &= ~(1 << i);
5657 port = pf->vxlan_ports[i];
5658 ret = port ?
5659 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5660 vxlan_hdr_qwords,
5661 I40E_AQC_TUNNEL_TYPE_VXLAN,
5662 &filter_index, NULL)
5663 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5664
5665 if (ret) {
5666 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5667 port ? "adding" : "deleting",
5668 ntohs(port), port ? i : i);
5669
5670 pf->vxlan_ports[i] = 0;
5671 } else {
5672 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5673 port ? "Added" : "Deleted",
5674 ntohs(port), port ? i : filter_index);
5675 }
5676 }
5677 }
5678}
5679
5680#endif
41c445ff
JB		 5681/**
5682 * i40e_service_task - Run the driver's async subtasks
5683 * @work: pointer to work_struct containing our data
5684 **/
5685static void i40e_service_task(struct work_struct *work)
5686{
5687 struct i40e_pf *pf = container_of(work,
5688 struct i40e_pf,
5689 service_task);
5690 unsigned long start_time = jiffies;
5691
5692 i40e_reset_subtask(pf);
5693 i40e_handle_mdd_event(pf);
5694 i40e_vc_process_vflr_event(pf);
5695 i40e_watchdog_subtask(pf);
5696 i40e_fdir_reinit_subtask(pf);
5697 i40e_check_hang_subtask(pf);
5698 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5699#ifdef CONFIG_I40E_VXLAN
5700 i40e_sync_vxlan_filters_subtask(pf);
5701#endif
41c445ff
JB		 5702 i40e_clean_adminq_subtask(pf);
5703
5704 i40e_service_event_complete(pf);
5705
5706 /* If the tasks have taken longer than one timer cycle or there
5707 * is more work to be done, reschedule the service task now
5708 * rather than wait for the timer to tick again.
5709 */
5710 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5711 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5712 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5713 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5714 i40e_service_event_schedule(pf);
5715}
5716
5717/**
5718 * i40e_service_timer - timer callback
5719 * @data: pointer to PF struct
5720 **/
5721static void i40e_service_timer(unsigned long data)
5722{
5723 struct i40e_pf *pf = (struct i40e_pf *)data;
5724
5725 mod_timer(&pf->service_timer,
5726 round_jiffies(jiffies + pf->service_timer_period));
5727 i40e_service_event_schedule(pf);
5728}
5729
5730/**
5731 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5732 * @vsi: the VSI being configured
5733 **/
5734static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5735{
5736 struct i40e_pf *pf = vsi->back;
5737
5738 switch (vsi->type) {
5739 case I40E_VSI_MAIN:
5740 vsi->alloc_queue_pairs = pf->num_lan_qps;
5741 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5742 I40E_REQ_DESCRIPTOR_MULTIPLE);
5743 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5744 vsi->num_q_vectors = pf->num_lan_msix;
5745 else
5746 vsi->num_q_vectors = 1;
5747
5748 break;
5749
5750 case I40E_VSI_FDIR:
5751 vsi->alloc_queue_pairs = 1;
5752 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5753 I40E_REQ_DESCRIPTOR_MULTIPLE);
5754 vsi->num_q_vectors = 1;
5755 break;
5756
5757 case I40E_VSI_VMDQ2:
5758 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5759 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5760 I40E_REQ_DESCRIPTOR_MULTIPLE);
5761 vsi->num_q_vectors = pf->num_vmdq_msix;
5762 break;
5763
5764 case I40E_VSI_SRIOV:
5765 vsi->alloc_queue_pairs = pf->num_vf_qps;
5766 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5767 I40E_REQ_DESCRIPTOR_MULTIPLE);
5768 break;
5769
5770 default:
5771 WARN_ON(1);
5772 return -ENODATA;
5773 }
5774
5775 return 0;
5776}
5777
f650a38b
ASJ		 5778/**
5779 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5780 * @type: VSI pointer
bc7d338f 5781 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5782 *
5783 * On error: returns error code (negative)
5784 * On success: returns 0
5785 **/
bc7d338f 5786static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5787{
5788 int size;
5789 int ret = 0;
5790
ac6c5e3d 5791 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5792 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5793 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5794 if (!vsi->tx_rings)
5795 return -ENOMEM;
f650a38b
ASJ		 5796 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5797
bc7d338f
ASJ		 5798 if (alloc_qvectors) {
5799 /* allocate memory for q_vector pointers */
5800 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5801 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5802 if (!vsi->q_vectors) {
5803 ret = -ENOMEM;
5804 goto err_vectors;
5805 }
f650a38b
ASJ		 5806 }
5807 return ret;
5808
5809err_vectors:
5810 kfree(vsi->tx_rings);
5811 return ret;
5812}
5813
41c445ff
JB		 5814/**
5815 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5816 * @pf: board private structure
5817 * @type: type of VSI
5818 *
5819 * On error: returns error code (negative)
5820 * On success: returns vsi index in PF (positive)
5821 **/
5822static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5823{
5824 int ret = -ENODEV;
5825 struct i40e_vsi *vsi;
5826 int vsi_idx;
5827 int i;
5828
5829 /* Need to protect the allocation of the VSIs at the PF level */
5830 mutex_lock(&pf->switch_mutex);
5831
5832 /* VSI list may be fragmented if VSI creation/destruction has
5833 * been happening. We can afford to do a quick scan to look
5834 * for any free VSIs in the list.
5835 *
5836 * find next empty vsi slot, looping back around if necessary
5837 */
5838 i = pf->next_vsi;
5839 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5840 i++;
5841 if (i >= pf->hw.func_caps.num_vsis) {
5842 i = 0;
5843 while (i < pf->next_vsi && pf->vsi[i])
5844 i++;
5845 }
5846
5847 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5848 vsi_idx = i; /* Found one! */
5849 } else {
5850 ret = -ENODEV;
493fb300 5851 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5852 }
5853 pf->next_vsi = ++i;
5854
5855 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5856 if (!vsi) {
5857 ret = -ENOMEM;
493fb300 5858 goto unlock_pf;
41c445ff
JB		 5859 }
5860 vsi->type = type;
5861 vsi->back = pf;
5862 set_bit(__I40E_DOWN, &vsi->state);
5863 vsi->flags = 0;
5864 vsi->idx = vsi_idx;
5865 vsi->rx_itr_setting = pf->rx_itr_default;
5866 vsi->tx_itr_setting = pf->tx_itr_default;
5867 vsi->netdev_registered = false;
5868 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5869 INIT_LIST_HEAD(&vsi->mac_filter_list);
5870
9f65e15b
AD		 5871 ret = i40e_set_num_rings_in_vsi(vsi);
5872 if (ret)
5873 goto err_rings;
5874
bc7d338f 5875 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5876 if (ret)
9f65e15b 5877 goto err_rings;
493fb300 5878
41c445ff
JB		 5879 /* Setup default MSIX irq handler for VSI */
5880 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5881
5882 pf->vsi[vsi_idx] = vsi;
5883 ret = vsi_idx;
493fb300
AD		 5884 goto unlock_pf;
5885
9f65e15b 5886err_rings:
493fb300
AD		 5887 pf->next_vsi = i - 1;
5888 kfree(vsi);
5889unlock_pf:
41c445ff
JB		 5890 mutex_unlock(&pf->switch_mutex);
5891 return ret;
5892}
5893
f650a38b
ASJ		 5894/**
5895 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5896 * @type: VSI pointer
bc7d338f 5897 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5898 *
5899 * On error: returns error code (negative)
5900 * On success: returns 0
5901 **/
bc7d338f 5902static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5903{
5904 /* free the ring and vector containers */
bc7d338f
ASJ		 5905 if (free_qvectors) {
5906 kfree(vsi->q_vectors);
5907 vsi->q_vectors = NULL;
5908 }
f650a38b
ASJ		 5909 kfree(vsi->tx_rings);
5910 vsi->tx_rings = NULL;
5911 vsi->rx_rings = NULL;
5912}
5913
41c445ff
JB		 5914/**
5915 * i40e_vsi_clear - Deallocate the VSI provided
5916 * @vsi: the VSI being un-configured
5917 **/
5918static int i40e_vsi_clear(struct i40e_vsi *vsi)
5919{
5920 struct i40e_pf *pf;
5921
5922 if (!vsi)
5923 return 0;
5924
5925 if (!vsi->back)
5926 goto free_vsi;
5927 pf = vsi->back;
5928
5929 mutex_lock(&pf->switch_mutex);
5930 if (!pf->vsi[vsi->idx]) {
5931 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5932 vsi->idx, vsi->idx, vsi, vsi->type);
5933 goto unlock_vsi;
5934 }
5935
5936 if (pf->vsi[vsi->idx] != vsi) {
5937 dev_err(&pf->pdev->dev,
5938 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5939 pf->vsi[vsi->idx]->idx,
5940 pf->vsi[vsi->idx],
5941 pf->vsi[vsi->idx]->type,
5942 vsi->idx, vsi, vsi->type);
5943 goto unlock_vsi;
5944 }
5945
5946 /* updates the pf for this cleared vsi */
5947 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5948 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5949
bc7d338f 5950 i40e_vsi_free_arrays(vsi, true);
493fb300 5951
41c445ff
JB		 5952 pf->vsi[vsi->idx] = NULL;
5953 if (vsi->idx < pf->next_vsi)
5954 pf->next_vsi = vsi->idx;
5955
5956unlock_vsi:
5957 mutex_unlock(&pf->switch_mutex);
5958free_vsi:
5959 kfree(vsi);
5960
5961 return 0;
5962}
5963
9f65e15b
AD		 5964/**
5965 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5966 * @vsi: the VSI being cleaned
5967 **/
be1d5eea 5968static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5969{
5970 int i;
5971
8e9dca53 5972 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5973 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5974 kfree_rcu(vsi->tx_rings[i], rcu);
5975 vsi->tx_rings[i] = NULL;
5976 vsi->rx_rings[i] = NULL;
5977 }
be1d5eea 5978 }
9f65e15b
AD		 5979}
5980
41c445ff
JB		 5981/**
5982 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5983 * @vsi: the VSI being configured
5984 **/
5985static int i40e_alloc_rings(struct i40e_vsi *vsi)
5986{
5987 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5988 int i;
5989
41c445ff 5990 /* Set basic values in the rings to be used later during open() */
d7397644 5991 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5992 struct i40e_ring *tx_ring;
5993 struct i40e_ring *rx_ring;
5994
ac6c5e3d 5995 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5996 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5997 if (!tx_ring)
5998 goto err_out;
41c445ff
JB		 5999
6000 tx_ring->queue_index = i;
6001 tx_ring->reg_idx = vsi->base_queue + i;
6002 tx_ring->ring_active = false;
6003 tx_ring->vsi = vsi;
6004 tx_ring->netdev = vsi->netdev;
6005 tx_ring->dev = &pf->pdev->dev;
6006 tx_ring->count = vsi->num_desc;
6007 tx_ring->size = 0;
6008 tx_ring->dcb_tc = 0;
9f65e15b 6009 vsi->tx_rings[i] = tx_ring;
41c445ff 6010
9f65e15b 6011 rx_ring = &tx_ring[1];
41c445ff
JB		 6012 rx_ring->queue_index = i;
6013 rx_ring->reg_idx = vsi->base_queue + i;
6014 rx_ring->ring_active = false;
6015 rx_ring->vsi = vsi;
6016 rx_ring->netdev = vsi->netdev;
6017 rx_ring->dev = &pf->pdev->dev;
6018 rx_ring->count = vsi->num_desc;
6019 rx_ring->size = 0;
6020 rx_ring->dcb_tc = 0;
6021 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6022 set_ring_16byte_desc_enabled(rx_ring);
6023 else
6024 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6025 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6026 }
6027
6028 return 0;
9f65e15b
AD		 6029
6030err_out:
6031 i40e_vsi_clear_rings(vsi);
6032 return -ENOMEM;
41c445ff
JB		 6033}
6034
6035/**
6036 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6037 * @pf: board private structure
6038 * @vectors: the number of MSI-X vectors to request
6039 *
6040 * Returns the number of vectors reserved, or error
6041 **/
6042static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6043{
7b37f376
AG		 6044 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6045 I40E_MIN_MSIX, vectors);
6046 if (vectors < 0) {
41c445ff 6047 dev_info(&pf->pdev->dev,
7b37f376 6048 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6049 vectors = 0;
6050 }
6051
7b37f376
AG		 6052 pf->num_msix_entries = vectors;
6053
41c445ff
JB		 6054 return vectors;
6055}
6056
6057/**
6058 * i40e_init_msix - Setup the MSIX capability
6059 * @pf: board private structure
6060 *
6061 * Work with the OS to set up the MSIX vectors needed.
6062 *
6063 * Returns 0 on success, negative on failure
6064 **/
6065static int i40e_init_msix(struct i40e_pf *pf)
6066{
6067 i40e_status err = 0;
6068 struct i40e_hw *hw = &pf->hw;
6069 int v_budget, i;
6070 int vec;
6071
6072 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6073 return -ENODEV;
6074
6075 /* The number of vectors we'll request will be comprised of:
6076 * - Add 1 for "other" cause for Admin Queue events, etc.
6077 * - The number of LAN queue pairs
f8ff1464
ASJ		 6078 * - Queues being used for RSS.
6079 * We don't need as many as max_rss_size vectors.
6080 * use rss_size instead in the calculation since that
6081 * is governed by number of cpus in the system.
6082 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6083 * - The number of VMDq pairs
6084 * Once we count this up, try the request.
6085 *
6086 * If we can't get what we want, we'll simplify to nearly nothing
6087 * and try again. If that still fails, we punt.
6088 */
f8ff1464 6089 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6090 pf->num_vmdq_msix = pf->num_vmdq_qps;
6091 v_budget = 1 + pf->num_lan_msix;
6092 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6093 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6094 v_budget++;
6095
6096 /* Scale down if necessary, and the rings will share vectors */
6097 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6098
6099 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6100 GFP_KERNEL);
6101 if (!pf->msix_entries)
6102 return -ENOMEM;
6103
6104 for (i = 0; i < v_budget; i++)
6105 pf->msix_entries[i].entry = i;
6106 vec = i40e_reserve_msix_vectors(pf, v_budget);
6107 if (vec < I40E_MIN_MSIX) {
6108 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6109 kfree(pf->msix_entries);
6110 pf->msix_entries = NULL;
6111 return -ENODEV;
6112
6113 } else if (vec == I40E_MIN_MSIX) {
6114 /* Adjust for minimal MSIX use */
77fa28be 6115 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6116 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6117 pf->num_vmdq_vsis = 0;
6118 pf->num_vmdq_qps = 0;
6119 pf->num_vmdq_msix = 0;
6120 pf->num_lan_qps = 1;
6121 pf->num_lan_msix = 1;
6122
6123 } else if (vec != v_budget) {
6124 /* Scale vector usage down */
6125 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6126 vec--; /* reserve the misc vector */
6127
6128 /* partition out the remaining vectors */
6129 switch (vec) {
6130 case 2:
6131 pf->num_vmdq_vsis = 1;
6132 pf->num_lan_msix = 1;
6133 break;
6134 case 3:
6135 pf->num_vmdq_vsis = 1;
6136 pf->num_lan_msix = 2;
6137 break;
6138 default:
6139 pf->num_lan_msix = min_t(int, (vec / 2),
6140 pf->num_lan_qps);
6141 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6142 I40E_DEFAULT_NUM_VMDQ_VSI);
6143 break;
6144 }
6145 }
6146
6147 return err;
6148}
6149
493fb300 6150/**
90e04070 6151 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6152 * @vsi: the VSI being configured
6153 * @v_idx: index of the vector in the vsi struct
6154 *
6155 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6156 **/
90e04070 6157static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6158{
6159 struct i40e_q_vector *q_vector;
6160
6161 /* allocate q_vector */
6162 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6163 if (!q_vector)
6164 return -ENOMEM;
6165
6166 q_vector->vsi = vsi;
6167 q_vector->v_idx = v_idx;
6168 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6169 if (vsi->netdev)
6170 netif_napi_add(vsi->netdev, &q_vector->napi,
6171 i40e_napi_poll, vsi->work_limit);
6172
cd0b6fa6
AD		 6173 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6174 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6175
493fb300
AD		 6176 /* tie q_vector and vsi together */
6177 vsi->q_vectors[v_idx] = q_vector;
6178
6179 return 0;
6180}
6181
41c445ff 6182/**
90e04070 6183 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6184 * @vsi: the VSI being configured
6185 *
6186 * We allocate one q_vector per queue interrupt. If allocation fails we
6187 * return -ENOMEM.
6188 **/
90e04070 6189static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6190{
6191 struct i40e_pf *pf = vsi->back;
6192 int v_idx, num_q_vectors;
493fb300 6193 int err;
41c445ff
JB		 6194
6195 /* if not MSIX, give the one vector only to the LAN VSI */
6196 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6197 num_q_vectors = vsi->num_q_vectors;
6198 else if (vsi == pf->vsi[pf->lan_vsi])
6199 num_q_vectors = 1;
6200 else
6201 return -EINVAL;
6202
41c445ff 6203 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6204 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6205 if (err)
6206 goto err_out;
41c445ff
JB		 6207 }
6208
6209 return 0;
493fb300
AD		 6210
6211err_out:
6212 while (v_idx--)
6213 i40e_free_q_vector(vsi, v_idx);
6214
6215 return err;
41c445ff
JB		 6216}
6217
6218/**
6219 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6220 * @pf: board private structure to initialize
6221 **/
6222static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6223{
6224 int err = 0;
6225
6226 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6227 err = i40e_init_msix(pf);
6228 if (err) {
60ea5f83
JB		 6229 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6230 I40E_FLAG_RSS_ENABLED |
6231 I40E_FLAG_DCB_ENABLED |
6232 I40E_FLAG_SRIOV_ENABLED |
6233 I40E_FLAG_FD_SB_ENABLED |
6234 I40E_FLAG_FD_ATR_ENABLED |
6235 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6236
6237 /* rework the queue expectations without MSIX */
6238 i40e_determine_queue_usage(pf);
6239 }
6240 }
6241
6242 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6243 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6244 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6245 err = pci_enable_msi(pf->pdev);
6246 if (err) {
958a3e3b 6247 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6248 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6249 }
6250 }
6251
958a3e3b 6252 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6253 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6254
41c445ff
JB		 6255 /* track first vector for misc interrupts */
6256 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6257}
6258
6259/**
6260 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6261 * @pf: board private structure
6262 *
6263 * This sets up the handler for MSIX 0, which is used to manage the
6264 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6265 * when in MSI or Legacy interrupt mode.
6266 **/
6267static int i40e_setup_misc_vector(struct i40e_pf *pf)
6268{
6269 struct i40e_hw *hw = &pf->hw;
6270 int err = 0;
6271
6272 /* Only request the irq if this is the first time through, and
6273 * not when we're rebuilding after a Reset
6274 */
6275 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6276 err = request_irq(pf->msix_entries[0].vector,
6277 i40e_intr, 0, pf->misc_int_name, pf);
6278 if (err) {
6279 dev_info(&pf->pdev->dev,
77fa28be
CS		 6280 "request_irq for %s failed: %d\n",
6281 pf->misc_int_name, err);
41c445ff
JB		 6282 return -EFAULT;
6283 }
6284 }
6285
6286 i40e_enable_misc_int_causes(hw);
6287
6288 /* associate no queues to the misc vector */
6289 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6290 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6291
6292 i40e_flush(hw);
6293
6294 i40e_irq_dynamic_enable_icr0(pf);
6295
6296 return err;
6297}
6298
6299/**
6300 * i40e_config_rss - Prepare for RSS if used
6301 * @pf: board private structure
6302 **/
6303static int i40e_config_rss(struct i40e_pf *pf)
6304{
41c445ff
JB		 6305 /* Set of random keys generated using kernel random number generator */
6306 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6307 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6308 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6309 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6310 struct i40e_hw *hw = &pf->hw;
6311 u32 lut = 0;
6312 int i, j;
6313 u64 hena;
41c445ff
JB		 6314
6315 /* Fill out hash function seed */
6316 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6317 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6318
6319 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6320 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6321 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6322 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6323 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6324 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6325
6326 /* Populate the LUT with max no. of queues in round robin fashion */
6327 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6328
6329 /* The assumption is that lan qp count will be the highest
6330 * qp count for any PF VSI that needs RSS.
6331 * If multiple VSIs need RSS support, all the qp counts
6332 * for those VSIs should be a power of 2 for RSS to work.
6333 * If LAN VSI is the only consumer for RSS then this requirement
6334 * is not necessary.
6335 */
6336 if (j == pf->rss_size)
6337 j = 0;
6338 /* lut = 4-byte sliding window of 4 lut entries */
6339 lut = (lut << 8) | (j &
6340 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6341 /* On i = 3, we have 4 entries in lut; write to the register */
6342 if ((i & 3) == 3)
6343 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6344 }
6345 i40e_flush(hw);
6346
6347 return 0;
6348}
6349
f8ff1464
ASJ		 6350/**
6351 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6352 * @pf: board private structure
6353 * @queue_count: the requested queue count for rss.
6354 *
6355 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6356 * count which may be different from the requested queue count.
6357 **/
6358int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6359{
6360 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6361 return 0;
6362
6363 queue_count = min_t(int, queue_count, pf->rss_size_max);
6364 queue_count = rounddown_pow_of_two(queue_count);
6365
6366 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6367 i40e_prep_for_reset(pf);
6368
f8ff1464
ASJ		 6369 pf->rss_size = queue_count;
6370
6371 i40e_reset_and_rebuild(pf, true);
6372 i40e_config_rss(pf);
6373 }
6374 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6375 return pf->rss_size;
6376}
6377
41c445ff
JB		 6378/**
6379 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6380 * @pf: board private structure to initialize
6381 *
6382 * i40e_sw_init initializes the Adapter private data structure.
6383 * Fields are initialized based on PCI device information and
6384 * OS network device settings (MTU size).
6385 **/
6386static int i40e_sw_init(struct i40e_pf *pf)
6387{
6388 int err = 0;
6389 int size;
6390
6391 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6392 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6393 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6394 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6395 if (I40E_DEBUG_USER & debug)
6396 pf->hw.debug_mask = debug;
6397 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6398 I40E_DEFAULT_MSG_ENABLE);
6399 }
6400
6401 /* Set default capability flags */
6402 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6403 I40E_FLAG_MSI_ENABLED |
6404 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6405 I40E_FLAG_RX_1BUF_ENABLED;
6406
7134f9ce
JB		 6407 /* Depending on PF configurations, it is possible that the RSS
6408 * maximum might end up larger than the available queues
6409 */
41c445ff 6410 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6411 pf->rss_size_max = min_t(int, pf->rss_size_max,
6412 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6413 if (pf->hw.func_caps.rss) {
6414 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6415 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6416 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6417 } else {
6418 pf->rss_size = 1;
6419 }
6420
2050bc65
CS		 6421 /* MFP mode enabled */
6422 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6423 pf->flags |= I40E_FLAG_MFP_ENABLED;
6424 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6425 }
6426
cbf61325
ASJ		 6427 /* FW/NVM is not yet fixed in this regard */
6428 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6429 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6430 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6431 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6432 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6433 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6434 } else {
6435 dev_info(&pf->pdev->dev,
0b67584f 6436 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6437 }
cbf61325
ASJ		 6438 pf->fdir_pf_filter_count =
6439 pf->hw.func_caps.fd_filters_guaranteed;
6440 pf->hw.fdir_shared_filter_count =
6441 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6442 }
6443
6444 if (pf->hw.func_caps.vmdq) {
6445 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6446 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6447 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6448 }
6449
41c445ff
JB		 6450#ifdef CONFIG_PCI_IOV
6451 if (pf->hw.func_caps.num_vfs) {
6452 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6453 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6454 pf->num_req_vfs = min_t(int,
6455 pf->hw.func_caps.num_vfs,
6456 I40E_MAX_VF_COUNT);
6457 }
6458#endif /* CONFIG_PCI_IOV */
6459 pf->eeprom_version = 0xDEAD;
6460 pf->lan_veb = I40E_NO_VEB;
6461 pf->lan_vsi = I40E_NO_VSI;
6462
6463 /* set up queue assignment tracking */
6464 size = sizeof(struct i40e_lump_tracking)
6465 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6466 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6467 if (!pf->qp_pile) {
6468 err = -ENOMEM;
6469 goto sw_init_done;
6470 }
6471 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6472 pf->qp_pile->search_hint = 0;
6473
6474 /* set up vector assignment tracking */
6475 size = sizeof(struct i40e_lump_tracking)
6476 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6477 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6478 if (!pf->irq_pile) {
6479 kfree(pf->qp_pile);
6480 err = -ENOMEM;
6481 goto sw_init_done;
6482 }
6483 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6484 pf->irq_pile->search_hint = 0;
6485
6486 mutex_init(&pf->switch_mutex);
6487
6488sw_init_done:
6489 return err;
6490}
6491
7c3c288b
ASJ		 6492/**
6493 * i40e_set_ntuple - set the ntuple feature flag and take action
6494 * @pf: board private structure to initialize
6495 * @features: the feature set that the stack is suggesting
6496 *
6497 * returns a bool to indicate if reset needs to happen
6498 **/
6499bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6500{
6501 bool need_reset = false;
6502
6503 /* Check if Flow Director n-tuple support was enabled or disabled. If
6504 * the state changed, we need to reset.
6505 */
6506 if (features & NETIF_F_NTUPLE) {
6507 /* Enable filters and mark for reset */
6508 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6509 need_reset = true;
6510 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6511 } else {
6512 /* turn off filters, mark for reset and clear SW filter list */
6513 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6514 need_reset = true;
6515 i40e_fdir_filter_exit(pf);
6516 }
6517 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6518 /* if ATR was disabled it can be re-enabled. */
6519 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6520 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6521 }
6522 return need_reset;
6523}
6524
41c445ff
JB		 6525/**
6526 * i40e_set_features - set the netdev feature flags
6527 * @netdev: ptr to the netdev being adjusted
6528 * @features: the feature set that the stack is suggesting
6529 **/
6530static int i40e_set_features(struct net_device *netdev,
6531 netdev_features_t features)
6532{
6533 struct i40e_netdev_priv *np = netdev_priv(netdev);
6534 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6535 struct i40e_pf *pf = vsi->back;
6536 bool need_reset;
41c445ff
JB		 6537
6538 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6539 i40e_vlan_stripping_enable(vsi);
6540 else
6541 i40e_vlan_stripping_disable(vsi);
6542
7c3c288b
ASJ		 6543 need_reset = i40e_set_ntuple(pf, features);
6544
6545 if (need_reset)
6546 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6547
41c445ff
JB		 6548 return 0;
6549}
6550
a1c9a9d9
JK		 6551#ifdef CONFIG_I40E_VXLAN
6552/**
6553 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6554 * @pf: board private structure
6555 * @port: The UDP port to look up
6556 *
6557 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6558 **/
6559static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6560{
6561 u8 i;
6562
6563 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6564 if (pf->vxlan_ports[i] == port)
6565 return i;
6566 }
6567
6568 return i;
6569}
6570
6571/**
6572 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6573 * @netdev: This physical port's netdev
6574 * @sa_family: Socket Family that VXLAN is notifying us about
6575 * @port: New UDP port number that VXLAN started listening to
6576 **/
6577static void i40e_add_vxlan_port(struct net_device *netdev,
6578 sa_family_t sa_family, __be16 port)
6579{
6580 struct i40e_netdev_priv *np = netdev_priv(netdev);
6581 struct i40e_vsi *vsi = np->vsi;
6582 struct i40e_pf *pf = vsi->back;
6583 u8 next_idx;
6584 u8 idx;
6585
6586 if (sa_family == AF_INET6)
6587 return;
6588
6589 idx = i40e_get_vxlan_port_idx(pf, port);
6590
6591 /* Check if port already exists */
6592 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6593 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6594 return;
6595 }
6596
6597 /* Now check if there is space to add the new port */
6598 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6599
6600 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6601 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6602 ntohs(port));
6603 return;
6604 }
6605
6606 /* New port: add it and mark its index in the bitmap */
6607 pf->vxlan_ports[next_idx] = port;
6608 pf->pending_vxlan_bitmap |= (1 << next_idx);
6609
6610 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6611}
6612
6613/**
6614 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6615 * @netdev: This physical port's netdev
6616 * @sa_family: Socket Family that VXLAN is notifying us about
6617 * @port: UDP port number that VXLAN stopped listening to
6618 **/
6619static void i40e_del_vxlan_port(struct net_device *netdev,
6620 sa_family_t sa_family, __be16 port)
6621{
6622 struct i40e_netdev_priv *np = netdev_priv(netdev);
6623 struct i40e_vsi *vsi = np->vsi;
6624 struct i40e_pf *pf = vsi->back;
6625 u8 idx;
6626
6627 if (sa_family == AF_INET6)
6628 return;
6629
6630 idx = i40e_get_vxlan_port_idx(pf, port);
6631
6632 /* Check if port already exists */
6633 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6634 /* if port exists, set it to 0 (mark for deletion)
6635 * and make it pending
6636 */
6637 pf->vxlan_ports[idx] = 0;
6638
6639 pf->pending_vxlan_bitmap |= (1 << idx);
6640
6641 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6642 } else {
6643 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6644 ntohs(port));
6645 }
6646}
6647
6648#endif
4ba0dea5
GR		 6649#ifdef HAVE_FDB_OPS
6650#ifdef USE_CONST_DEV_UC_CHAR
6651static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6652 struct net_device *dev,
6653 const unsigned char *addr,
6654 u16 flags)
6655#else
6656static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6657 struct net_device *dev,
6658 unsigned char *addr,
6659 u16 flags)
6660#endif
6661{
6662 struct i40e_netdev_priv *np = netdev_priv(dev);
6663 struct i40e_pf *pf = np->vsi->back;
6664 int err = 0;
6665
6666 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6667 return -EOPNOTSUPP;
6668
6669 /* Hardware does not support aging addresses so if a
6670 * ndm_state is given only allow permanent addresses
6671 */
6672 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6673 netdev_info(dev, "FDB only supports static addresses\n");
6674 return -EINVAL;
6675 }
6676
6677 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6678 err = dev_uc_add_excl(dev, addr);
6679 else if (is_multicast_ether_addr(addr))
6680 err = dev_mc_add_excl(dev, addr);
6681 else
6682 err = -EINVAL;
6683
6684 /* Only return duplicate errors if NLM_F_EXCL is set */
6685 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6686 err = 0;
6687
6688 return err;
6689}
6690
6691#ifndef USE_DEFAULT_FDB_DEL_DUMP
6692#ifdef USE_CONST_DEV_UC_CHAR
6693static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6694 struct net_device *dev,
6695 const unsigned char *addr)
6696#else
6697static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6698 struct net_device *dev,
6699 unsigned char *addr)
6700#endif
6701{
6702 struct i40e_netdev_priv *np = netdev_priv(dev);
6703 struct i40e_pf *pf = np->vsi->back;
6704 int err = -EOPNOTSUPP;
6705
6706 if (ndm->ndm_state & NUD_PERMANENT) {
6707 netdev_info(dev, "FDB only supports static addresses\n");
6708 return -EINVAL;
6709 }
6710
6711 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6712 if (is_unicast_ether_addr(addr))
6713 err = dev_uc_del(dev, addr);
6714 else if (is_multicast_ether_addr(addr))
6715 err = dev_mc_del(dev, addr);
6716 else
6717 err = -EINVAL;
6718 }
6719
6720 return err;
6721}
6722
6723static int i40e_ndo_fdb_dump(struct sk_buff *skb,
6724 struct netlink_callback *cb,
6725 struct net_device *dev,
6726 int idx)
6727{
6728 struct i40e_netdev_priv *np = netdev_priv(dev);
6729 struct i40e_pf *pf = np->vsi->back;
6730
6731 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
6732 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6733
6734 return idx;
6735}
6736
6737#endif /* USE_DEFAULT_FDB_DEL_DUMP */
6738#endif /* HAVE_FDB_OPS */
41c445ff
JB		 6739static const struct net_device_ops i40e_netdev_ops = {
6740 .ndo_open = i40e_open,
6741 .ndo_stop = i40e_close,
6742 .ndo_start_xmit = i40e_lan_xmit_frame,
6743 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6744 .ndo_set_rx_mode = i40e_set_rx_mode,
6745 .ndo_validate_addr = eth_validate_addr,
6746 .ndo_set_mac_address = i40e_set_mac,
6747 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6748 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6749 .ndo_tx_timeout = i40e_tx_timeout,
6750 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6751 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6752#ifdef CONFIG_NET_POLL_CONTROLLER
6753 .ndo_poll_controller = i40e_netpoll,
6754#endif
6755 .ndo_setup_tc = i40e_setup_tc,
6756 .ndo_set_features = i40e_set_features,
6757 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6758 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6759 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6760 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6761 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6762#ifdef CONFIG_I40E_VXLAN
6763 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6764 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6765#endif
4ba0dea5
GR		 6766#ifdef HAVE_FDB_OPS
6767 .ndo_fdb_add = i40e_ndo_fdb_add,
6768#ifndef USE_DEFAULT_FDB_DEL_DUMP
6769 .ndo_fdb_del = i40e_ndo_fdb_del,
6770 .ndo_fdb_dump = i40e_ndo_fdb_dump,
6771#endif
6772#endif
41c445ff
JB		 6773};
6774
6775/**
6776 * i40e_config_netdev - Setup the netdev flags
6777 * @vsi: the VSI being configured
6778 *
6779 * Returns 0 on success, negative value on failure
6780 **/
6781static int i40e_config_netdev(struct i40e_vsi *vsi)
6782{
1a10370a 6783 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6784 struct i40e_pf *pf = vsi->back;
6785 struct i40e_hw *hw = &pf->hw;
6786 struct i40e_netdev_priv *np;
6787 struct net_device *netdev;
6788 u8 mac_addr[ETH_ALEN];
6789 int etherdev_size;
6790
6791 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6792 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6793 if (!netdev)
6794 return -ENOMEM;
6795
6796 vsi->netdev = netdev;
6797 np = netdev_priv(netdev);
6798 np->vsi = vsi;
6799
d70e941b 6800 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6801 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6802 NETIF_F_TSO;
41c445ff
JB		 6803
6804 netdev->features = NETIF_F_SG |
6805 NETIF_F_IP_CSUM |
6806 NETIF_F_SCTP_CSUM |
6807 NETIF_F_HIGHDMA |
6808 NETIF_F_GSO_UDP_TUNNEL |
6809 NETIF_F_HW_VLAN_CTAG_TX |
6810 NETIF_F_HW_VLAN_CTAG_RX |
6811 NETIF_F_HW_VLAN_CTAG_FILTER |
6812 NETIF_F_IPV6_CSUM |
6813 NETIF_F_TSO |
6814 NETIF_F_TSO6 |
6815 NETIF_F_RXCSUM |
7c3c288b 6816 NETIF_F_NTUPLE |
41c445ff
JB		 6817 NETIF_F_RXHASH |
6818 0;
6819
6820 /* copy netdev features into list of user selectable features */
6821 netdev->hw_features |= netdev->features;
6822
6823 if (vsi->type == I40E_VSI_MAIN) {
6824 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6825 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6826 } else {
6827 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6828 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6829 pf->vsi[pf->lan_vsi]->netdev->name);
6830 random_ether_addr(mac_addr);
6831 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6832 }
1a10370a 6833 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6834
6835 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6836 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6837 /* vlan gets same features (except vlan offload)
6838 * after any tweaks for specific VSI types
6839 */
6840 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6841 NETIF_F_HW_VLAN_CTAG_RX |
6842 NETIF_F_HW_VLAN_CTAG_FILTER);
6843 netdev->priv_flags |= IFF_UNICAST_FLT;
6844 netdev->priv_flags |= IFF_SUPP_NOFCS;
6845 /* Setup netdev TC information */
6846 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6847
6848 netdev->netdev_ops = &i40e_netdev_ops;
6849 netdev->watchdog_timeo = 5 * HZ;
6850 i40e_set_ethtool_ops(netdev);
6851
6852 return 0;
6853}
6854
6855/**
6856 * i40e_vsi_delete - Delete a VSI from the switch
6857 * @vsi: the VSI being removed
6858 *
6859 * Returns 0 on success, negative value on failure
6860 **/
6861static void i40e_vsi_delete(struct i40e_vsi *vsi)
6862{
6863 /* remove default VSI is not allowed */
6864 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6865 return;
6866
41c445ff
JB		 6867 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6868 return;
6869}
6870
6871/**
6872 * i40e_add_vsi - Add a VSI to the switch
6873 * @vsi: the VSI being configured
6874 *
6875 * This initializes a VSI context depending on the VSI type to be added and
6876 * passes it down to the add_vsi aq command.
6877 **/
6878static int i40e_add_vsi(struct i40e_vsi *vsi)
6879{
6880 int ret = -ENODEV;
6881 struct i40e_mac_filter *f, *ftmp;
6882 struct i40e_pf *pf = vsi->back;
6883 struct i40e_hw *hw = &pf->hw;
6884 struct i40e_vsi_context ctxt;
6885 u8 enabled_tc = 0x1; /* TC0 enabled */
6886 int f_count = 0;
6887
6888 memset(&ctxt, 0, sizeof(ctxt));
6889 switch (vsi->type) {
6890 case I40E_VSI_MAIN:
6891 /* The PF's main VSI is already setup as part of the
6892 * device initialization, so we'll not bother with
6893 * the add_vsi call, but we will retrieve the current
6894 * VSI context.
6895 */
6896 ctxt.seid = pf->main_vsi_seid;
6897 ctxt.pf_num = pf->hw.pf_id;
6898 ctxt.vf_num = 0;
6899 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6900 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6901 if (ret) {
6902 dev_info(&pf->pdev->dev,
6903 "couldn't get pf vsi config, err %d, aq_err %d\n",
6904 ret, pf->hw.aq.asq_last_status);
6905 return -ENOENT;
6906 }
6907 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6908 vsi->info.valid_sections = 0;
6909
6910 vsi->seid = ctxt.seid;
6911 vsi->id = ctxt.vsi_number;
6912
6913 enabled_tc = i40e_pf_get_tc_map(pf);
6914
6915 /* MFP mode setup queue map and update VSI */
6916 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6917 memset(&ctxt, 0, sizeof(ctxt));
6918 ctxt.seid = pf->main_vsi_seid;
6919 ctxt.pf_num = pf->hw.pf_id;
6920 ctxt.vf_num = 0;
6921 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6922 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6923 if (ret) {
6924 dev_info(&pf->pdev->dev,
6925 "update vsi failed, aq_err=%d\n",
6926 pf->hw.aq.asq_last_status);
6927 ret = -ENOENT;
6928 goto err;
6929 }
6930 /* update the local VSI info queue map */
6931 i40e_vsi_update_queue_map(vsi, &ctxt);
6932 vsi->info.valid_sections = 0;
6933 } else {
6934 /* Default/Main VSI is only enabled for TC0
6935 * reconfigure it to enable all TCs that are
6936 * available on the port in SFP mode.
6937 */
6938 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6939 if (ret) {
6940 dev_info(&pf->pdev->dev,
6941 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6942 enabled_tc, ret,
6943 pf->hw.aq.asq_last_status);
6944 ret = -ENOENT;
6945 }
6946 }
6947 break;
6948
6949 case I40E_VSI_FDIR:
cbf61325
ASJ		 6950 ctxt.pf_num = hw->pf_id;
6951 ctxt.vf_num = 0;
6952 ctxt.uplink_seid = vsi->uplink_seid;
6953 ctxt.connection_type = 0x1; /* regular data port */
6954 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6955 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6956 break;
6957
6958 case I40E_VSI_VMDQ2:
6959 ctxt.pf_num = hw->pf_id;
6960 ctxt.vf_num = 0;
6961 ctxt.uplink_seid = vsi->uplink_seid;
6962 ctxt.connection_type = 0x1; /* regular data port */
6963 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6964
6965 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6966
6967 /* This VSI is connected to VEB so the switch_id
6968 * should be set to zero by default.
6969 */
6970 ctxt.info.switch_id = 0;
6971 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6972 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6973
6974 /* Setup the VSI tx/rx queue map for TC0 only for now */
6975 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6976 break;
6977
6978 case I40E_VSI_SRIOV:
6979 ctxt.pf_num = hw->pf_id;
6980 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6981 ctxt.uplink_seid = vsi->uplink_seid;
6982 ctxt.connection_type = 0x1; /* regular data port */
6983 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6984
6985 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6986
6987 /* This VSI is connected to VEB so the switch_id
6988 * should be set to zero by default.
6989 */
6990 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6991
6992 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6993 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6994 /* Setup the VSI tx/rx queue map for TC0 only for now */
6995 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6996 break;
6997
6998 default:
6999 return -ENODEV;
7000 }
7001
7002 if (vsi->type != I40E_VSI_MAIN) {
7003 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7004 if (ret) {
7005 dev_info(&vsi->back->pdev->dev,
7006 "add vsi failed, aq_err=%d\n",
7007 vsi->back->hw.aq.asq_last_status);
7008 ret = -ENOENT;
7009 goto err;
7010 }
7011 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7012 vsi->info.valid_sections = 0;
7013 vsi->seid = ctxt.seid;
7014 vsi->id = ctxt.vsi_number;
7015 }
7016
7017 /* If macvlan filters already exist, force them to get loaded */
7018 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7019 f->changed = true;
7020 f_count++;
7021 }
7022 if (f_count) {
7023 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7024 pf->flags |= I40E_FLAG_FILTER_SYNC;
7025 }
7026
7027 /* Update VSI BW information */
7028 ret = i40e_vsi_get_bw_info(vsi);
7029 if (ret) {
7030 dev_info(&pf->pdev->dev,
7031 "couldn't get vsi bw info, err %d, aq_err %d\n",
7032 ret, pf->hw.aq.asq_last_status);
7033 /* VSI is already added so not tearing that up */
7034 ret = 0;
7035 }
7036
7037err:
7038 return ret;
7039}
7040
7041/**
7042 * i40e_vsi_release - Delete a VSI and free its resources
7043 * @vsi: the VSI being removed
7044 *
7045 * Returns 0 on success or < 0 on error
7046 **/
7047int i40e_vsi_release(struct i40e_vsi *vsi)
7048{
7049 struct i40e_mac_filter *f, *ftmp;
7050 struct i40e_veb *veb = NULL;
7051 struct i40e_pf *pf;
7052 u16 uplink_seid;
7053 int i, n;
7054
7055 pf = vsi->back;
7056
7057 /* release of a VEB-owner or last VSI is not allowed */
7058 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7059 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7060 vsi->seid, vsi->uplink_seid);
7061 return -ENODEV;
7062 }
7063 if (vsi == pf->vsi[pf->lan_vsi] &&
7064 !test_bit(__I40E_DOWN, &pf->state)) {
7065 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7066 return -ENODEV;
7067 }
7068
7069 uplink_seid = vsi->uplink_seid;
7070 if (vsi->type != I40E_VSI_SRIOV) {
7071 if (vsi->netdev_registered) {
7072 vsi->netdev_registered = false;
7073 if (vsi->netdev) {
7074 /* results in a call to i40e_close() */
7075 unregister_netdev(vsi->netdev);
41c445ff
JB		 7076 }
7077 } else {
7078 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
7079 i40e_down(vsi);
7080 i40e_vsi_free_irq(vsi);
7081 i40e_vsi_free_tx_resources(vsi);
7082 i40e_vsi_free_rx_resources(vsi);
7083 }
7084 i40e_vsi_disable_irq(vsi);
7085 }
7086
7087 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7088 i40e_del_filter(vsi, f->macaddr, f->vlan,
7089 f->is_vf, f->is_netdev);
7090 i40e_sync_vsi_filters(vsi);
7091
7092 i40e_vsi_delete(vsi);
7093 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7094 if (vsi->netdev) {
7095 free_netdev(vsi->netdev);
7096 vsi->netdev = NULL;
7097 }
41c445ff
JB		 7098 i40e_vsi_clear_rings(vsi);
7099 i40e_vsi_clear(vsi);
7100
7101 /* If this was the last thing on the VEB, except for the
7102 * controlling VSI, remove the VEB, which puts the controlling
7103 * VSI onto the next level down in the switch.
7104 *
7105 * Well, okay, there's one more exception here: don't remove
7106 * the orphan VEBs yet. We'll wait for an explicit remove request
7107 * from up the network stack.
7108 */
7109 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7110 if (pf->vsi[i] &&
7111 pf->vsi[i]->uplink_seid == uplink_seid &&
7112 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7113 n++; /* count the VSIs */
7114 }
7115 }
7116 for (i = 0; i < I40E_MAX_VEB; i++) {
7117 if (!pf->veb[i])
7118 continue;
7119 if (pf->veb[i]->uplink_seid == uplink_seid)
7120 n++; /* count the VEBs */
7121 if (pf->veb[i]->seid == uplink_seid)
7122 veb = pf->veb[i];
7123 }
7124 if (n == 0 && veb && veb->uplink_seid != 0)
7125 i40e_veb_release(veb);
7126
7127 return 0;
7128}
7129
7130/**
7131 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7132 * @vsi: ptr to the VSI
7133 *
7134 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7135 * corresponding SW VSI structure and initializes num_queue_pairs for the
7136 * newly allocated VSI.
7137 *
7138 * Returns 0 on success or negative on failure
7139 **/
7140static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7141{
7142 int ret = -ENOENT;
7143 struct i40e_pf *pf = vsi->back;
7144
493fb300 7145 if (vsi->q_vectors[0]) {
41c445ff
JB		 7146 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7147 vsi->seid);
7148 return -EEXIST;
7149 }
7150
7151 if (vsi->base_vector) {
f29eaa3d 7152 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7153 vsi->seid, vsi->base_vector);
7154 return -EEXIST;
7155 }
7156
90e04070 7157 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7158 if (ret) {
7159 dev_info(&pf->pdev->dev,
7160 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7161 vsi->num_q_vectors, vsi->seid, ret);
7162 vsi->num_q_vectors = 0;
7163 goto vector_setup_out;
7164 }
7165
958a3e3b
SN		 7166 if (vsi->num_q_vectors)
7167 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7168 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7169 if (vsi->base_vector < 0) {
7170 dev_info(&pf->pdev->dev,
f29eaa3d 7171 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7172 vsi->seid, vsi->base_vector);
7173 i40e_vsi_free_q_vectors(vsi);
7174 ret = -ENOENT;
7175 goto vector_setup_out;
7176 }
7177
7178vector_setup_out:
7179 return ret;
7180}
7181
bc7d338f
ASJ		 7182/**
7183 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7184 * @vsi: pointer to the vsi.
7185 *
7186 * This re-allocates a vsi's queue resources.
7187 *
7188 * Returns pointer to the successfully allocated and configured VSI sw struct
7189 * on success, otherwise returns NULL on failure.
7190 **/
7191static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7192{
7193 struct i40e_pf *pf = vsi->back;
7194 u8 enabled_tc;
7195 int ret;
7196
7197 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7198 i40e_vsi_clear_rings(vsi);
7199
7200 i40e_vsi_free_arrays(vsi, false);
7201 i40e_set_num_rings_in_vsi(vsi);
7202 ret = i40e_vsi_alloc_arrays(vsi, false);
7203 if (ret)
7204 goto err_vsi;
7205
7206 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7207 if (ret < 0) {
7208 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7209 vsi->seid, ret);
7210 goto err_vsi;
7211 }
7212 vsi->base_queue = ret;
7213
7214 /* Update the FW view of the VSI. Force a reset of TC and queue
7215 * layout configurations.
7216 */
7217 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7218 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7219 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7220 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7221
7222 /* assign it some queues */
7223 ret = i40e_alloc_rings(vsi);
7224 if (ret)
7225 goto err_rings;
7226
7227 /* map all of the rings to the q_vectors */
7228 i40e_vsi_map_rings_to_vectors(vsi);
7229 return vsi;
7230
7231err_rings:
7232 i40e_vsi_free_q_vectors(vsi);
7233 if (vsi->netdev_registered) {
7234 vsi->netdev_registered = false;
7235 unregister_netdev(vsi->netdev);
7236 free_netdev(vsi->netdev);
7237 vsi->netdev = NULL;
7238 }
7239 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7240err_vsi:
7241 i40e_vsi_clear(vsi);
7242 return NULL;
7243}
7244
41c445ff
JB		 7245/**
7246 * i40e_vsi_setup - Set up a VSI by a given type
7247 * @pf: board private structure
7248 * @type: VSI type
7249 * @uplink_seid: the switch element to link to
7250 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7251 *
7252 * This allocates the sw VSI structure and its queue resources, then add a VSI
7253 * to the identified VEB.
7254 *
7255 * Returns pointer to the successfully allocated and configure VSI sw struct on
7256 * success, otherwise returns NULL on failure.
7257 **/
7258struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7259 u16 uplink_seid, u32 param1)
7260{
7261 struct i40e_vsi *vsi = NULL;
7262 struct i40e_veb *veb = NULL;
7263 int ret, i;
7264 int v_idx;
7265
7266 /* The requested uplink_seid must be either
7267 * - the PF's port seid
7268 * no VEB is needed because this is the PF
7269 * or this is a Flow Director special case VSI
7270 * - seid of an existing VEB
7271 * - seid of a VSI that owns an existing VEB
7272 * - seid of a VSI that doesn't own a VEB
7273 * a new VEB is created and the VSI becomes the owner
7274 * - seid of the PF VSI, which is what creates the first VEB
7275 * this is a special case of the previous
7276 *
7277 * Find which uplink_seid we were given and create a new VEB if needed
7278 */
7279 for (i = 0; i < I40E_MAX_VEB; i++) {
7280 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7281 veb = pf->veb[i];
7282 break;
7283 }
7284 }
7285
7286 if (!veb && uplink_seid != pf->mac_seid) {
7287
7288 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7289 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7290 vsi = pf->vsi[i];
7291 break;
7292 }
7293 }
7294 if (!vsi) {
7295 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7296 uplink_seid);
7297 return NULL;
7298 }
7299
7300 if (vsi->uplink_seid == pf->mac_seid)
7301 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7302 vsi->tc_config.enabled_tc);
7303 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7304 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7305 vsi->tc_config.enabled_tc);
7306
7307 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7308 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7309 veb = pf->veb[i];
7310 }
7311 if (!veb) {
7312 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7313 return NULL;
7314 }
7315
7316 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7317 uplink_seid = veb->seid;
7318 }
7319
7320 /* get vsi sw struct */
7321 v_idx = i40e_vsi_mem_alloc(pf, type);
7322 if (v_idx < 0)
7323 goto err_alloc;
7324 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7325 if (!vsi)
7326 goto err_alloc;
41c445ff
JB		 7327 vsi->type = type;
7328 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7329
7330 if (type == I40E_VSI_MAIN)
7331 pf->lan_vsi = v_idx;
7332 else if (type == I40E_VSI_SRIOV)
7333 vsi->vf_id = param1;
7334 /* assign it some queues */
cbf61325
ASJ		 7335 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7336 vsi->idx);
41c445ff
JB		 7337 if (ret < 0) {
7338 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7339 vsi->seid, ret);
7340 goto err_vsi;
7341 }
7342 vsi->base_queue = ret;
7343
7344 /* get a VSI from the hardware */
7345 vsi->uplink_seid = uplink_seid;
7346 ret = i40e_add_vsi(vsi);
7347 if (ret)
7348 goto err_vsi;
7349
7350 switch (vsi->type) {
7351 /* setup the netdev if needed */
7352 case I40E_VSI_MAIN:
7353 case I40E_VSI_VMDQ2:
7354 ret = i40e_config_netdev(vsi);
7355 if (ret)
7356 goto err_netdev;
7357 ret = register_netdev(vsi->netdev);
7358 if (ret)
7359 goto err_netdev;
7360 vsi->netdev_registered = true;
7361 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7362#ifdef CONFIG_I40E_DCB
7363 /* Setup DCB netlink interface */
7364 i40e_dcbnl_setup(vsi);
7365#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7366 /* fall through */
7367
7368 case I40E_VSI_FDIR:
7369 /* set up vectors and rings if needed */
7370 ret = i40e_vsi_setup_vectors(vsi);
7371 if (ret)
7372 goto err_msix;
7373
7374 ret = i40e_alloc_rings(vsi);
7375 if (ret)
7376 goto err_rings;
7377
7378 /* map all of the rings to the q_vectors */
7379 i40e_vsi_map_rings_to_vectors(vsi);
7380
7381 i40e_vsi_reset_stats(vsi);
7382 break;
7383
7384 default:
7385 /* no netdev or rings for the other VSI types */
7386 break;
7387 }
7388
7389 return vsi;
7390
7391err_rings:
7392 i40e_vsi_free_q_vectors(vsi);
7393err_msix:
7394 if (vsi->netdev_registered) {
7395 vsi->netdev_registered = false;
7396 unregister_netdev(vsi->netdev);
7397 free_netdev(vsi->netdev);
7398 vsi->netdev = NULL;
7399 }
7400err_netdev:
7401 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7402err_vsi:
7403 i40e_vsi_clear(vsi);
7404err_alloc:
7405 return NULL;
7406}
7407
7408/**
7409 * i40e_veb_get_bw_info - Query VEB BW information
7410 * @veb: the veb to query
7411 *
7412 * Query the Tx scheduler BW configuration data for given VEB
7413 **/
7414static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7415{
7416 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7417 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7418 struct i40e_pf *pf = veb->pf;
7419 struct i40e_hw *hw = &pf->hw;
7420 u32 tc_bw_max;
7421 int ret = 0;
7422 int i;
7423
7424 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7425 &bw_data, NULL);
7426 if (ret) {
7427 dev_info(&pf->pdev->dev,
7428 "query veb bw config failed, aq_err=%d\n",
7429 hw->aq.asq_last_status);
7430 goto out;
7431 }
7432
7433 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7434 &ets_data, NULL);
7435 if (ret) {
7436 dev_info(&pf->pdev->dev,
7437 "query veb bw ets config failed, aq_err=%d\n",
7438 hw->aq.asq_last_status);
7439 goto out;
7440 }
7441
7442 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7443 veb->bw_max_quanta = ets_data.tc_bw_max;
7444 veb->is_abs_credits = bw_data.absolute_credits_enable;
7445 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7446 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7447 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7448 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7449 veb->bw_tc_limit_credits[i] =
7450 le16_to_cpu(bw_data.tc_bw_limits[i]);
7451 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7452 }
7453
7454out:
7455 return ret;
7456}
7457
7458/**
7459 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7460 * @pf: board private structure
7461 *
7462 * On error: returns error code (negative)
7463 * On success: returns vsi index in PF (positive)
7464 **/
7465static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7466{
7467 int ret = -ENOENT;
7468 struct i40e_veb *veb;
7469 int i;
7470
7471 /* Need to protect the allocation of switch elements at the PF level */
7472 mutex_lock(&pf->switch_mutex);
7473
7474 /* VEB list may be fragmented if VEB creation/destruction has
7475 * been happening. We can afford to do a quick scan to look
7476 * for any free slots in the list.
7477 *
7478 * find next empty veb slot, looping back around if necessary
7479 */
7480 i = 0;
7481 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7482 i++;
7483 if (i >= I40E_MAX_VEB) {
7484 ret = -ENOMEM;
7485 goto err_alloc_veb; /* out of VEB slots! */
7486 }
7487
7488 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7489 if (!veb) {
7490 ret = -ENOMEM;
7491 goto err_alloc_veb;
7492 }
7493 veb->pf = pf;
7494 veb->idx = i;
7495 veb->enabled_tc = 1;
7496
7497 pf->veb[i] = veb;
7498 ret = i;
7499err_alloc_veb:
7500 mutex_unlock(&pf->switch_mutex);
7501 return ret;
7502}
7503
7504/**
7505 * i40e_switch_branch_release - Delete a branch of the switch tree
7506 * @branch: where to start deleting
7507 *
7508 * This uses recursion to find the tips of the branch to be
7509 * removed, deleting until we get back to and can delete this VEB.
7510 **/
7511static void i40e_switch_branch_release(struct i40e_veb *branch)
7512{
7513 struct i40e_pf *pf = branch->pf;
7514 u16 branch_seid = branch->seid;
7515 u16 veb_idx = branch->idx;
7516 int i;
7517
7518 /* release any VEBs on this VEB - RECURSION */
7519 for (i = 0; i < I40E_MAX_VEB; i++) {
7520 if (!pf->veb[i])
7521 continue;
7522 if (pf->veb[i]->uplink_seid == branch->seid)
7523 i40e_switch_branch_release(pf->veb[i]);
7524 }
7525
7526 /* Release the VSIs on this VEB, but not the owner VSI.
7527 *
7528 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7529 * the VEB itself, so don't use (*branch) after this loop.
7530 */
7531 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7532 if (!pf->vsi[i])
7533 continue;
7534 if (pf->vsi[i]->uplink_seid == branch_seid &&
7535 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7536 i40e_vsi_release(pf->vsi[i]);
7537 }
7538 }
7539
7540 /* There's one corner case where the VEB might not have been
7541 * removed, so double check it here and remove it if needed.
7542 * This case happens if the veb was created from the debugfs
7543 * commands and no VSIs were added to it.
7544 */
7545 if (pf->veb[veb_idx])
7546 i40e_veb_release(pf->veb[veb_idx]);
7547}
7548
7549/**
7550 * i40e_veb_clear - remove veb struct
7551 * @veb: the veb to remove
7552 **/
7553static void i40e_veb_clear(struct i40e_veb *veb)
7554{
7555 if (!veb)
7556 return;
7557
7558 if (veb->pf) {
7559 struct i40e_pf *pf = veb->pf;
7560
7561 mutex_lock(&pf->switch_mutex);
7562 if (pf->veb[veb->idx] == veb)
7563 pf->veb[veb->idx] = NULL;
7564 mutex_unlock(&pf->switch_mutex);
7565 }
7566
7567 kfree(veb);
7568}
7569
7570/**
7571 * i40e_veb_release - Delete a VEB and free its resources
7572 * @veb: the VEB being removed
7573 **/
7574void i40e_veb_release(struct i40e_veb *veb)
7575{
7576 struct i40e_vsi *vsi = NULL;
7577 struct i40e_pf *pf;
7578 int i, n = 0;
7579
7580 pf = veb->pf;
7581
7582 /* find the remaining VSI and check for extras */
7583 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7584 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7585 n++;
7586 vsi = pf->vsi[i];
7587 }
7588 }
7589 if (n != 1) {
7590 dev_info(&pf->pdev->dev,
7591 "can't remove VEB %d with %d VSIs left\n",
7592 veb->seid, n);
7593 return;
7594 }
7595
7596 /* move the remaining VSI to uplink veb */
7597 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7598 if (veb->uplink_seid) {
7599 vsi->uplink_seid = veb->uplink_seid;
7600 if (veb->uplink_seid == pf->mac_seid)
7601 vsi->veb_idx = I40E_NO_VEB;
7602 else
7603 vsi->veb_idx = veb->veb_idx;
7604 } else {
7605 /* floating VEB */
7606 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7607 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7608 }
7609
7610 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7611 i40e_veb_clear(veb);
7612
7613 return;
7614}
7615
7616/**
7617 * i40e_add_veb - create the VEB in the switch
7618 * @veb: the VEB to be instantiated
7619 * @vsi: the controlling VSI
7620 **/
7621static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7622{
56747264 7623 bool is_default = false;
e1c51b95 7624 bool is_cloud = false;
41c445ff
JB		 7625 int ret;
7626
7627 /* get a VEB from the hardware */
7628 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7629 veb->enabled_tc, is_default,
7630 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7631 if (ret) {
7632 dev_info(&veb->pf->pdev->dev,
7633 "couldn't add VEB, err %d, aq_err %d\n",
7634 ret, veb->pf->hw.aq.asq_last_status);
7635 return -EPERM;
7636 }
7637
7638 /* get statistics counter */
7639 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7640 &veb->stats_idx, NULL, NULL, NULL);
7641 if (ret) {
7642 dev_info(&veb->pf->pdev->dev,
7643 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7644 ret, veb->pf->hw.aq.asq_last_status);
7645 return -EPERM;
7646 }
7647 ret = i40e_veb_get_bw_info(veb);
7648 if (ret) {
7649 dev_info(&veb->pf->pdev->dev,
7650 "couldn't get VEB bw info, err %d, aq_err %d\n",
7651 ret, veb->pf->hw.aq.asq_last_status);
7652 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7653 return -ENOENT;
7654 }
7655
7656 vsi->uplink_seid = veb->seid;
7657 vsi->veb_idx = veb->idx;
7658 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7659
7660 return 0;
7661}
7662
7663/**
7664 * i40e_veb_setup - Set up a VEB
7665 * @pf: board private structure
7666 * @flags: VEB setup flags
7667 * @uplink_seid: the switch element to link to
7668 * @vsi_seid: the initial VSI seid
7669 * @enabled_tc: Enabled TC bit-map
7670 *
7671 * This allocates the sw VEB structure and links it into the switch
7672 * It is possible and legal for this to be a duplicate of an already
7673 * existing VEB. It is also possible for both uplink and vsi seids
7674 * to be zero, in order to create a floating VEB.
7675 *
7676 * Returns pointer to the successfully allocated VEB sw struct on
7677 * success, otherwise returns NULL on failure.
7678 **/
7679struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7680 u16 uplink_seid, u16 vsi_seid,
7681 u8 enabled_tc)
7682{
7683 struct i40e_veb *veb, *uplink_veb = NULL;
7684 int vsi_idx, veb_idx;
7685 int ret;
7686
7687 /* if one seid is 0, the other must be 0 to create a floating relay */
7688 if ((uplink_seid == 0 || vsi_seid == 0) &&
7689 (uplink_seid + vsi_seid != 0)) {
7690 dev_info(&pf->pdev->dev,
7691 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7692 uplink_seid, vsi_seid);
7693 return NULL;
7694 }
7695
7696 /* make sure there is such a vsi and uplink */
7697 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7698 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7699 break;
7700 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7701 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7702 vsi_seid);
7703 return NULL;
7704 }
7705
7706 if (uplink_seid && uplink_seid != pf->mac_seid) {
7707 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7708 if (pf->veb[veb_idx] &&
7709 pf->veb[veb_idx]->seid == uplink_seid) {
7710 uplink_veb = pf->veb[veb_idx];
7711 break;
7712 }
7713 }
7714 if (!uplink_veb) {
7715 dev_info(&pf->pdev->dev,
7716 "uplink seid %d not found\n", uplink_seid);
7717 return NULL;
7718 }
7719 }
7720
7721 /* get veb sw struct */
7722 veb_idx = i40e_veb_mem_alloc(pf);
7723 if (veb_idx < 0)
7724 goto err_alloc;
7725 veb = pf->veb[veb_idx];
7726 veb->flags = flags;
7727 veb->uplink_seid = uplink_seid;
7728 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7729 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7730
7731 /* create the VEB in the switch */
7732 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7733 if (ret)
7734 goto err_veb;
7735
7736 return veb;
7737
7738err_veb:
7739 i40e_veb_clear(veb);
7740err_alloc:
7741 return NULL;
7742}
7743
7744/**
7745 * i40e_setup_pf_switch_element - set pf vars based on switch type
7746 * @pf: board private structure
7747 * @ele: element we are building info from
7748 * @num_reported: total number of elements
7749 * @printconfig: should we print the contents
7750 *
7751 * helper function to assist in extracting a few useful SEID values.
7752 **/
7753static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7754 struct i40e_aqc_switch_config_element_resp *ele,
7755 u16 num_reported, bool printconfig)
7756{
7757 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7758 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7759 u8 element_type = ele->element_type;
7760 u16 seid = le16_to_cpu(ele->seid);
7761
7762 if (printconfig)
7763 dev_info(&pf->pdev->dev,
7764 "type=%d seid=%d uplink=%d downlink=%d\n",
7765 element_type, seid, uplink_seid, downlink_seid);
7766
7767 switch (element_type) {
7768 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7769 pf->mac_seid = seid;
7770 break;
7771 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7772 /* Main VEB? */
7773 if (uplink_seid != pf->mac_seid)
7774 break;
7775 if (pf->lan_veb == I40E_NO_VEB) {
7776 int v;
7777
7778 /* find existing or else empty VEB */
7779 for (v = 0; v < I40E_MAX_VEB; v++) {
7780 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7781 pf->lan_veb = v;
7782 break;
7783 }
7784 }
7785 if (pf->lan_veb == I40E_NO_VEB) {
7786 v = i40e_veb_mem_alloc(pf);
7787 if (v < 0)
7788 break;
7789 pf->lan_veb = v;
7790 }
7791 }
7792
7793 pf->veb[pf->lan_veb]->seid = seid;
7794 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7795 pf->veb[pf->lan_veb]->pf = pf;
7796 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7797 break;
7798 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7799 if (num_reported != 1)
7800 break;
7801 /* This is immediately after a reset so we can assume this is
7802 * the PF's VSI
7803 */
7804 pf->mac_seid = uplink_seid;
7805 pf->pf_seid = downlink_seid;
7806 pf->main_vsi_seid = seid;
7807 if (printconfig)
7808 dev_info(&pf->pdev->dev,
7809 "pf_seid=%d main_vsi_seid=%d\n",
7810 pf->pf_seid, pf->main_vsi_seid);
7811 break;
7812 case I40E_SWITCH_ELEMENT_TYPE_PF:
7813 case I40E_SWITCH_ELEMENT_TYPE_VF:
7814 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7815 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7816 case I40E_SWITCH_ELEMENT_TYPE_PE:
7817 case I40E_SWITCH_ELEMENT_TYPE_PA:
7818 /* ignore these for now */
7819 break;
7820 default:
7821 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7822 element_type, seid);
7823 break;
7824 }
7825}
7826
7827/**
7828 * i40e_fetch_switch_configuration - Get switch config from firmware
7829 * @pf: board private structure
7830 * @printconfig: should we print the contents
7831 *
7832 * Get the current switch configuration from the device and
7833 * extract a few useful SEID values.
7834 **/
7835int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7836{
7837 struct i40e_aqc_get_switch_config_resp *sw_config;
7838 u16 next_seid = 0;
7839 int ret = 0;
7840 u8 *aq_buf;
7841 int i;
7842
7843 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7844 if (!aq_buf)
7845 return -ENOMEM;
7846
7847 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7848 do {
7849 u16 num_reported, num_total;
7850
7851 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7852 I40E_AQ_LARGE_BUF,
7853 &next_seid, NULL);
7854 if (ret) {
7855 dev_info(&pf->pdev->dev,
7856 "get switch config failed %d aq_err=%x\n",
7857 ret, pf->hw.aq.asq_last_status);
7858 kfree(aq_buf);
7859 return -ENOENT;
7860 }
7861
7862 num_reported = le16_to_cpu(sw_config->header.num_reported);
7863 num_total = le16_to_cpu(sw_config->header.num_total);
7864
7865 if (printconfig)
7866 dev_info(&pf->pdev->dev,
7867 "header: %d reported %d total\n",
7868 num_reported, num_total);
7869
7870 if (num_reported) {
7871 int sz = sizeof(*sw_config) * num_reported;
7872
7873 kfree(pf->sw_config);
7874 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7875 if (pf->sw_config)
7876 memcpy(pf->sw_config, sw_config, sz);
7877 }
7878
7879 for (i = 0; i < num_reported; i++) {
7880 struct i40e_aqc_switch_config_element_resp *ele =
7881 &sw_config->element[i];
7882
7883 i40e_setup_pf_switch_element(pf, ele, num_reported,
7884 printconfig);
7885 }
7886 } while (next_seid != 0);
7887
7888 kfree(aq_buf);
7889 return ret;
7890}
7891
7892/**
7893 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7894 * @pf: board private structure
bc7d338f 7895 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7896 *
7897 * Returns 0 on success, negative value on failure
7898 **/
bc7d338f 7899static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7900{
895106a5 7901 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7902 int ret;
7903
7904 /* find out what's out there already */
7905 ret = i40e_fetch_switch_configuration(pf, false);
7906 if (ret) {
7907 dev_info(&pf->pdev->dev,
7908 "couldn't fetch switch config, err %d, aq_err %d\n",
7909 ret, pf->hw.aq.asq_last_status);
7910 return ret;
7911 }
7912 i40e_pf_reset_stats(pf);
7913
41c445ff 7914 /* first time setup */
bc7d338f 7915 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7916 struct i40e_vsi *vsi = NULL;
7917 u16 uplink_seid;
7918
7919 /* Set up the PF VSI associated with the PF's main VSI
7920 * that is already in the HW switch
7921 */
7922 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7923 uplink_seid = pf->veb[pf->lan_veb]->seid;
7924 else
7925 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7926 if (pf->lan_vsi == I40E_NO_VSI)
7927 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7928 else if (reinit)
7929 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7930 if (!vsi) {
7931 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7932 i40e_fdir_teardown(pf);
7933 return -EAGAIN;
7934 }
41c445ff
JB		 7935 } else {
7936 /* force a reset of TC and queue layout configurations */
7937 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7938 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7939 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7940 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7941 }
7942 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7943
cbf61325
ASJ		 7944 i40e_fdir_sb_setup(pf);
7945
41c445ff
JB		 7946 /* Setup static PF queue filter control settings */
7947 ret = i40e_setup_pf_filter_control(pf);
7948 if (ret) {
7949 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7950 ret);
7951 /* Failure here should not stop continuing other steps */
7952 }
7953
7954 /* enable RSS in the HW, even for only one queue, as the stack can use
7955 * the hash
7956 */
7957 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7958 i40e_config_rss(pf);
7959
7960 /* fill in link information and enable LSE reporting */
7961 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7962 i40e_link_event(pf);
7963
d52c20b7 7964 /* Initialize user-specific link properties */
41c445ff
JB		 7965 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7966 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7967 /* requested_mode is set in probe or by ethtool */
7968 if (!pf->fc_autoneg_status)
7969 goto no_autoneg;
7970
7971 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7972 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7973 pf->hw.fc.current_mode = I40E_FC_FULL;
7974 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7975 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7976 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7977 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7978 else
d52c20b7
JB		 7979 pf->hw.fc.current_mode = I40E_FC_NONE;
7980
7981 /* sync the flow control settings with the auto-neg values */
7982 switch (pf->hw.fc.current_mode) {
7983 case I40E_FC_FULL:
7984 txfc = 1;
7985 rxfc = 1;
7986 break;
7987 case I40E_FC_TX_PAUSE:
7988 txfc = 1;
7989 rxfc = 0;
7990 break;
7991 case I40E_FC_RX_PAUSE:
7992 txfc = 0;
7993 rxfc = 1;
7994 break;
7995 case I40E_FC_NONE:
7996 case I40E_FC_DEFAULT:
7997 txfc = 0;
7998 rxfc = 0;
7999 break;
8000 case I40E_FC_PFC:
8001 /* TBD */
8002 break;
8003 /* no default case, we have to handle all possibilities here */
8004 }
8005
8006 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8007
8008 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8009 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8010 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8011
8012 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8013
d52c20b7
JB		 8014 goto fc_complete;
8015
8016no_autoneg:
8017 /* disable L2 flow control, user can turn it on if they wish */
8018 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8019 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8020 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8021
8022fc_complete:
beb0dff1
JK		 8023 i40e_ptp_init(pf);
8024
41c445ff
JB		 8025 return ret;
8026}
8027
41c445ff
JB		 8028/**
8029 * i40e_determine_queue_usage - Work out queue distribution
8030 * @pf: board private structure
8031 **/
8032static void i40e_determine_queue_usage(struct i40e_pf *pf)
8033{
41c445ff
JB		 8034 int queues_left;
8035
8036 pf->num_lan_qps = 0;
41c445ff
JB		 8037
8038 /* Find the max queues to be put into basic use. We'll always be
8039 * using TC0, whether or not DCB is running, and TC0 will get the
8040 * big RSS set.
8041 */
8042 queues_left = pf->hw.func_caps.num_tx_qp;
8043
cbf61325
ASJ		 8044 if ((queues_left == 1) ||
8045 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
8046 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
8047 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 8048 /* one qp for PF, no queues for anything else */
8049 queues_left = 0;
8050 pf->rss_size = pf->num_lan_qps = 1;
8051
8052 /* make sure all the fancies are disabled */
60ea5f83
JB		 8053 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8054 I40E_FLAG_FD_SB_ENABLED |
8055 I40E_FLAG_FD_ATR_ENABLED |
8056 I40E_FLAG_DCB_ENABLED |
8057 I40E_FLAG_SRIOV_ENABLED |
8058 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8059 } else {
cbf61325
ASJ		 8060 /* Not enough queues for all TCs */
8061 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
8062 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
8063 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8064 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8065 }
8066 pf->num_lan_qps = pf->rss_size_max;
8067 queues_left -= pf->num_lan_qps;
8068 }
8069
8070 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8071 if (queues_left > 1) {
8072 queues_left -= 1; /* save 1 queue for FD */
8073 } else {
8074 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8075 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8076 }
41c445ff
JB		 8077 }
8078
8079 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8080 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8081 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8082 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8083 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8084 }
8085
8086 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8087 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8088 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8089 (queues_left / pf->num_vmdq_qps));
8090 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8091 }
8092
f8ff1464 8093 pf->queues_left = queues_left;
41c445ff
JB		 8094 return;
8095}
8096
8097/**
8098 * i40e_setup_pf_filter_control - Setup PF static filter control
8099 * @pf: PF to be setup
8100 *
8101 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8102 * settings. If PE/FCoE are enabled then it will also set the per PF
8103 * based filter sizes required for them. It also enables Flow director,
8104 * ethertype and macvlan type filter settings for the pf.
8105 *
8106 * Returns 0 on success, negative on failure
8107 **/
8108static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8109{
8110 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8111
8112 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8113
8114 /* Flow Director is enabled */
60ea5f83 8115 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8116 settings->enable_fdir = true;
8117
8118 /* Ethtype and MACVLAN filters enabled for PF */
8119 settings->enable_ethtype = true;
8120 settings->enable_macvlan = true;
8121
8122 if (i40e_set_filter_control(&pf->hw, settings))
8123 return -ENOENT;
8124
8125 return 0;
8126}
8127
0c22b3dd
JB		 8128#define INFO_STRING_LEN 255
8129static void i40e_print_features(struct i40e_pf *pf)
8130{
8131 struct i40e_hw *hw = &pf->hw;
8132 char *buf, *string;
8133
8134 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8135 if (!string) {
8136 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8137 return;
8138 }
8139
8140 buf = string;
8141
8142 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8143#ifdef CONFIG_PCI_IOV
8144 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8145#endif
8146 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8147 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8148
8149 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8150 buf += sprintf(buf, "RSS ");
8151 buf += sprintf(buf, "FDir ");
8152 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
8153 buf += sprintf(buf, "ATR ");
8154 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
8155 buf += sprintf(buf, "NTUPLE ");
8156 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8157 buf += sprintf(buf, "DCB ");
8158 if (pf->flags & I40E_FLAG_PTP)
8159 buf += sprintf(buf, "PTP ");
8160
8161 BUG_ON(buf > (string + INFO_STRING_LEN));
8162 dev_info(&pf->pdev->dev, "%s\n", string);
8163 kfree(string);
8164}
8165
41c445ff
JB		 8166/**
8167 * i40e_probe - Device initialization routine
8168 * @pdev: PCI device information struct
8169 * @ent: entry in i40e_pci_tbl
8170 *
8171 * i40e_probe initializes a pf identified by a pci_dev structure.
8172 * The OS initialization, configuring of the pf private structure,
8173 * and a hardware reset occur.
8174 *
8175 * Returns 0 on success, negative on failure
8176 **/
8177static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8178{
8179 struct i40e_driver_version dv;
8180 struct i40e_pf *pf;
8181 struct i40e_hw *hw;
93cd765b 8182 static u16 pfs_found;
d4dfb81a 8183 u16 link_status;
41c445ff
JB		 8184 int err = 0;
8185 u32 len;
8186
8187 err = pci_enable_device_mem(pdev);
8188 if (err)
8189 return err;
8190
8191 /* set up for high or low dma */
6494294f 8192 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8193 if (err) {
e3e3bfdd
JS		 8194 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8195 if (err) {
8196 dev_err(&pdev->dev,
8197 "DMA configuration failed: 0x%x\n", err);
8198 goto err_dma;
8199 }
41c445ff
JB		 8200 }
8201
8202 /* set up pci connections */
8203 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8204 IORESOURCE_MEM), i40e_driver_name);
8205 if (err) {
8206 dev_info(&pdev->dev,
8207 "pci_request_selected_regions failed %d\n", err);
8208 goto err_pci_reg;
8209 }
8210
8211 pci_enable_pcie_error_reporting(pdev);
8212 pci_set_master(pdev);
8213
8214 /* Now that we have a PCI connection, we need to do the
8215 * low level device setup. This is primarily setting up
8216 * the Admin Queue structures and then querying for the
8217 * device's current profile information.
8218 */
8219 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8220 if (!pf) {
8221 err = -ENOMEM;
8222 goto err_pf_alloc;
8223 }
8224 pf->next_vsi = 0;
8225 pf->pdev = pdev;
8226 set_bit(__I40E_DOWN, &pf->state);
8227
8228 hw = &pf->hw;
8229 hw->back = pf;
8230 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8231 pci_resource_len(pdev, 0));
8232 if (!hw->hw_addr) {
8233 err = -EIO;
8234 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8235 (unsigned int)pci_resource_start(pdev, 0),
8236 (unsigned int)pci_resource_len(pdev, 0), err);
8237 goto err_ioremap;
8238 }
8239 hw->vendor_id = pdev->vendor;
8240 hw->device_id = pdev->device;
8241 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8242 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8243 hw->subsystem_device_id = pdev->subsystem_device;
8244 hw->bus.device = PCI_SLOT(pdev->devfn);
8245 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8246 pf->instance = pfs_found;
41c445ff 8247
7134f9ce
JB		 8248 /* do a special CORER for clearing PXE mode once at init */
8249 if (hw->revision_id == 0 &&
8250 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8251 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8252 i40e_flush(hw);
8253 msleep(200);
8254 pf->corer_count++;
8255
8256 i40e_clear_pxe_mode(hw);
8257 }
8258
41c445ff
JB		 8259 /* Reset here to make sure all is clean and to define PF 'n' */
8260 err = i40e_pf_reset(hw);
8261 if (err) {
8262 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8263 goto err_pf_reset;
8264 }
8265 pf->pfr_count++;
8266
8267 hw->aq.num_arq_entries = I40E_AQ_LEN;
8268 hw->aq.num_asq_entries = I40E_AQ_LEN;
8269 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8270 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8271 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8272 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8273 "%s-pf%d:misc",
8274 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8275
8276 err = i40e_init_shared_code(hw);
8277 if (err) {
8278 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8279 goto err_pf_reset;
8280 }
8281
d52c20b7
JB		 8282 /* set up a default setting for link flow control */
8283 pf->hw.fc.requested_mode = I40E_FC_NONE;
8284
41c445ff
JB		 8285 err = i40e_init_adminq(hw);
8286 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8287 if (err) {
8288 dev_info(&pdev->dev,
8289 "init_adminq failed: %d expecting API %02x.%02x\n",
8290 err,
8291 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8292 goto err_pf_reset;
8293 }
8294
4eb3f768
SN		 8295 i40e_verify_eeprom(pf);
8296
6ff4ef86 8297 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8298 err = i40e_get_capabilities(pf);
8299 if (err)
8300 goto err_adminq_setup;
8301
8302 err = i40e_sw_init(pf);
8303 if (err) {
8304 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8305 goto err_sw_init;
8306 }
8307
8308 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8309 hw->func_caps.num_rx_qp,
8310 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8311 if (err) {
8312 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8313 goto err_init_lan_hmc;
8314 }
8315
8316 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8317 if (err) {
8318 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8319 err = -ENOENT;
8320 goto err_configure_lan_hmc;
8321 }
8322
8323 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8324 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8325 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8326 err = -EIO;
8327 goto err_mac_addr;
8328 }
8329 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8330 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8331
8332 pci_set_drvdata(pdev, pf);
8333 pci_save_state(pdev);
4e3b35b0
NP		 8334#ifdef CONFIG_I40E_DCB
8335 err = i40e_init_pf_dcb(pf);
8336 if (err) {
8337 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8338 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8339 goto err_init_dcb;
8340 }
8341#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8342
8343 /* set up periodic task facility */
8344 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8345 pf->service_timer_period = HZ;
8346
8347 INIT_WORK(&pf->service_task, i40e_service_task);
8348 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8349 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8350 pf->link_check_timeout = jiffies;
8351
8e2773ae
SN		 8352 /* WoL defaults to disabled */
8353 pf->wol_en = false;
8354 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8355
41c445ff
JB		 8356 /* set up the main switch operations */
8357 i40e_determine_queue_usage(pf);
8358 i40e_init_interrupt_scheme(pf);
8359
8360 /* Set up the *vsi struct based on the number of VSIs in the HW,
8361 * and set up our local tracking of the MAIN PF vsi.
8362 */
8363 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8364 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8365 if (!pf->vsi) {
8366 err = -ENOMEM;
41c445ff 8367 goto err_switch_setup;
ed87ac09 8368 }
41c445ff 8369
bc7d338f 8370 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8371 if (err) {
8372 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8373 goto err_vsis;
8374 }
8375
8376 /* The main driver is (mostly) up and happy. We need to set this state
8377 * before setting up the misc vector or we get a race and the vector
8378 * ends up disabled forever.
8379 */
8380 clear_bit(__I40E_DOWN, &pf->state);
8381
8382 /* In case of MSIX we are going to setup the misc vector right here
8383 * to handle admin queue events etc. In case of legacy and MSI
8384 * the misc functionality and queue processing is combined in
8385 * the same vector and that gets setup at open.
8386 */
8387 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8388 err = i40e_setup_misc_vector(pf);
8389 if (err) {
8390 dev_info(&pdev->dev,
8391 "setup of misc vector failed: %d\n", err);
8392 goto err_vsis;
8393 }
8394 }
8395
8396 /* prep for VF support */
8397 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8398 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8399 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8400 u32 val;
8401
8402 /* disable link interrupts for VFs */
8403 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8404 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8405 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8406 i40e_flush(hw);
4aeec010
MW		 8407
8408 if (pci_num_vf(pdev)) {
8409 dev_info(&pdev->dev,
8410 "Active VFs found, allocating resources.\n");
8411 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8412 if (err)
8413 dev_info(&pdev->dev,
8414 "Error %d allocating resources for existing VFs\n",
8415 err);
8416 }
41c445ff
JB		 8417 }
8418
93cd765b
ASJ		 8419 pfs_found++;
8420
41c445ff
JB		 8421 i40e_dbg_pf_init(pf);
8422
8423 /* tell the firmware that we're starting */
8424 dv.major_version = DRV_VERSION_MAJOR;
8425 dv.minor_version = DRV_VERSION_MINOR;
8426 dv.build_version = DRV_VERSION_BUILD;
8427 dv.subbuild_version = 0;
8428 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
8429
8430 /* since everything's happy, start the service_task timer */
8431 mod_timer(&pf->service_timer,
8432 round_jiffies(jiffies + pf->service_timer_period));
8433
d4dfb81a
CS		 8434 /* Get the negotiated link width and speed from PCI config space */
8435 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8436
8437 i40e_set_pci_config_data(hw, link_status);
8438
69bfb110 8439 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8440 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8441 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8442 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8443 "Unknown"),
8444 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8445 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8446 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8447 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8448 "Unknown"));
8449
8450 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8451 hw->bus.speed < i40e_bus_speed_8000) {
8452 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8453 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8454 }
8455
0c22b3dd
JB		 8456 /* print a string summarizing features */
8457 i40e_print_features(pf);
8458
41c445ff
JB		 8459 return 0;
8460
8461 /* Unwind what we've done if something failed in the setup */
8462err_vsis:
8463 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8464 i40e_clear_interrupt_scheme(pf);
8465 kfree(pf->vsi);
04b03013
SN		 8466err_switch_setup:
8467 i40e_reset_interrupt_capability(pf);
41c445ff 8468 del_timer_sync(&pf->service_timer);
4e3b35b0
NP		 8469#ifdef CONFIG_I40E_DCB
8470err_init_dcb:
8471#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8472err_mac_addr:
8473err_configure_lan_hmc:
8474 (void)i40e_shutdown_lan_hmc(hw);
8475err_init_lan_hmc:
8476 kfree(pf->qp_pile);
8477 kfree(pf->irq_pile);
8478err_sw_init:
8479err_adminq_setup:
8480 (void)i40e_shutdown_adminq(hw);
8481err_pf_reset:
8482 iounmap(hw->hw_addr);
8483err_ioremap:
8484 kfree(pf);
8485err_pf_alloc:
8486 pci_disable_pcie_error_reporting(pdev);
8487 pci_release_selected_regions(pdev,
8488 pci_select_bars(pdev, IORESOURCE_MEM));
8489err_pci_reg:
8490err_dma:
8491 pci_disable_device(pdev);
8492 return err;
8493}
8494
8495/**
8496 * i40e_remove - Device removal routine
8497 * @pdev: PCI device information struct
8498 *
8499 * i40e_remove is called by the PCI subsystem to alert the driver
8500 * that is should release a PCI device. This could be caused by a
8501 * Hot-Plug event, or because the driver is going to be removed from
8502 * memory.
8503 **/
8504static void i40e_remove(struct pci_dev *pdev)
8505{
8506 struct i40e_pf *pf = pci_get_drvdata(pdev);
8507 i40e_status ret_code;
8508 u32 reg;
8509 int i;
8510
8511 i40e_dbg_pf_exit(pf);
8512
beb0dff1
JK		 8513 i40e_ptp_stop(pf);
8514
41c445ff
JB		 8515 /* no more scheduling of any task */
8516 set_bit(__I40E_DOWN, &pf->state);
8517 del_timer_sync(&pf->service_timer);
8518 cancel_work_sync(&pf->service_task);
8519
eb2d80bc
MW		 8520 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8521 i40e_free_vfs(pf);
8522 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8523 }
8524
41c445ff
JB		 8525 i40e_fdir_teardown(pf);
8526
8527 /* If there is a switch structure or any orphans, remove them.
8528 * This will leave only the PF's VSI remaining.
8529 */
8530 for (i = 0; i < I40E_MAX_VEB; i++) {
8531 if (!pf->veb[i])
8532 continue;
8533
8534 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8535 pf->veb[i]->uplink_seid == 0)
8536 i40e_switch_branch_release(pf->veb[i]);
8537 }
8538
8539 /* Now we can shutdown the PF's VSI, just before we kill
8540 * adminq and hmc.
8541 */
8542 if (pf->vsi[pf->lan_vsi])
8543 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8544
8545 i40e_stop_misc_vector(pf);
8546 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8547 synchronize_irq(pf->msix_entries[0].vector);
8548 free_irq(pf->msix_entries[0].vector, pf);
8549 }
8550
8551 /* shutdown and destroy the HMC */
8552 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8553 if (ret_code)
8554 dev_warn(&pdev->dev,
8555 "Failed to destroy the HMC resources: %d\n", ret_code);
8556
8557 /* shutdown the adminq */
41c445ff
JB		 8558 ret_code = i40e_shutdown_adminq(&pf->hw);
8559 if (ret_code)
8560 dev_warn(&pdev->dev,
8561 "Failed to destroy the Admin Queue resources: %d\n",
8562 ret_code);
8563
8564 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8565 i40e_clear_interrupt_scheme(pf);
8566 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8567 if (pf->vsi[i]) {
8568 i40e_vsi_clear_rings(pf->vsi[i]);
8569 i40e_vsi_clear(pf->vsi[i]);
8570 pf->vsi[i] = NULL;
8571 }
8572 }
8573
8574 for (i = 0; i < I40E_MAX_VEB; i++) {
8575 kfree(pf->veb[i]);
8576 pf->veb[i] = NULL;
8577 }
8578
8579 kfree(pf->qp_pile);
8580 kfree(pf->irq_pile);
8581 kfree(pf->sw_config);
8582 kfree(pf->vsi);
8583
8584 /* force a PF reset to clean anything leftover */
8585 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8586 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8587 i40e_flush(&pf->hw);
8588
8589 iounmap(pf->hw.hw_addr);
8590 kfree(pf);
8591 pci_release_selected_regions(pdev,
8592 pci_select_bars(pdev, IORESOURCE_MEM));
8593
8594 pci_disable_pcie_error_reporting(pdev);
8595 pci_disable_device(pdev);
8596}
8597
8598/**
8599 * i40e_pci_error_detected - warning that something funky happened in PCI land
8600 * @pdev: PCI device information struct
8601 *
8602 * Called to warn that something happened and the error handling steps
8603 * are in progress. Allows the driver to quiesce things, be ready for
8604 * remediation.
8605 **/
8606static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8607 enum pci_channel_state error)
8608{
8609 struct i40e_pf *pf = pci_get_drvdata(pdev);
8610
8611 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8612
8613 /* shutdown all operations */
9007bccd
SN		 8614 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8615 rtnl_lock();
8616 i40e_prep_for_reset(pf);
8617 rtnl_unlock();
8618 }
41c445ff
JB		 8619
8620 /* Request a slot reset */
8621 return PCI_ERS_RESULT_NEED_RESET;
8622}
8623
8624/**
8625 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8626 * @pdev: PCI device information struct
8627 *
8628 * Called to find if the driver can work with the device now that
8629 * the pci slot has been reset. If a basic connection seems good
8630 * (registers are readable and have sane content) then return a
8631 * happy little PCI_ERS_RESULT_xxx.
8632 **/
8633static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8634{
8635 struct i40e_pf *pf = pci_get_drvdata(pdev);
8636 pci_ers_result_t result;
8637 int err;
8638 u32 reg;
8639
8640 dev_info(&pdev->dev, "%s\n", __func__);
8641 if (pci_enable_device_mem(pdev)) {
8642 dev_info(&pdev->dev,
8643 "Cannot re-enable PCI device after reset.\n");
8644 result = PCI_ERS_RESULT_DISCONNECT;
8645 } else {
8646 pci_set_master(pdev);
8647 pci_restore_state(pdev);
8648 pci_save_state(pdev);
8649 pci_wake_from_d3(pdev, false);
8650
8651 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8652 if (reg == 0)
8653 result = PCI_ERS_RESULT_RECOVERED;
8654 else
8655 result = PCI_ERS_RESULT_DISCONNECT;
8656 }
8657
8658 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8659 if (err) {
8660 dev_info(&pdev->dev,
8661 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8662 err);
8663 /* non-fatal, continue */
8664 }
8665
8666 return result;
8667}
8668
8669/**
8670 * i40e_pci_error_resume - restart operations after PCI error recovery
8671 * @pdev: PCI device information struct
8672 *
8673 * Called to allow the driver to bring things back up after PCI error
8674 * and/or reset recovery has finished.
8675 **/
8676static void i40e_pci_error_resume(struct pci_dev *pdev)
8677{
8678 struct i40e_pf *pf = pci_get_drvdata(pdev);
8679
8680 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8681 if (test_bit(__I40E_SUSPENDED, &pf->state))
8682 return;
8683
8684 rtnl_lock();
41c445ff 8685 i40e_handle_reset_warning(pf);
9007bccd
SN		 8686 rtnl_lock();
8687}
8688
8689/**
8690 * i40e_shutdown - PCI callback for shutting down
8691 * @pdev: PCI device information struct
8692 **/
8693static void i40e_shutdown(struct pci_dev *pdev)
8694{
8695 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8696 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8697
8698 set_bit(__I40E_SUSPENDED, &pf->state);
8699 set_bit(__I40E_DOWN, &pf->state);
8700 rtnl_lock();
8701 i40e_prep_for_reset(pf);
8702 rtnl_unlock();
8703
8e2773ae
SN		 8704 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8705 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8706
9007bccd 8707 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8708 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8709 pci_set_power_state(pdev, PCI_D3hot);
8710 }
8711}
8712
8713#ifdef CONFIG_PM
8714/**
8715 * i40e_suspend - PCI callback for moving to D3
8716 * @pdev: PCI device information struct
8717 **/
8718static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8719{
8720 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8721 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8722
8723 set_bit(__I40E_SUSPENDED, &pf->state);
8724 set_bit(__I40E_DOWN, &pf->state);
8725 rtnl_lock();
8726 i40e_prep_for_reset(pf);
8727 rtnl_unlock();
8728
8e2773ae
SN		 8729 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8730 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8731
8732 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8733 pci_set_power_state(pdev, PCI_D3hot);
8734
8735 return 0;
41c445ff
JB		 8736}
8737
9007bccd
SN		 8738/**
8739 * i40e_resume - PCI callback for waking up from D3
8740 * @pdev: PCI device information struct
8741 **/
8742static int i40e_resume(struct pci_dev *pdev)
8743{
8744 struct i40e_pf *pf = pci_get_drvdata(pdev);
8745 u32 err;
8746
8747 pci_set_power_state(pdev, PCI_D0);
8748 pci_restore_state(pdev);
8749 /* pci_restore_state() clears dev->state_saves, so
8750 * call pci_save_state() again to restore it.
8751 */
8752 pci_save_state(pdev);
8753
8754 err = pci_enable_device_mem(pdev);
8755 if (err) {
8756 dev_err(&pdev->dev,
8757 "%s: Cannot enable PCI device from suspend\n",
8758 __func__);
8759 return err;
8760 }
8761 pci_set_master(pdev);
8762
8763 /* no wakeup events while running */
8764 pci_wake_from_d3(pdev, false);
8765
8766 /* handling the reset will rebuild the device state */
8767 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8768 clear_bit(__I40E_DOWN, &pf->state);
8769 rtnl_lock();
8770 i40e_reset_and_rebuild(pf, false);
8771 rtnl_unlock();
8772 }
8773
8774 return 0;
8775}
8776
8777#endif
41c445ff
JB		 8778static const struct pci_error_handlers i40e_err_handler = {
8779 .error_detected = i40e_pci_error_detected,
8780 .slot_reset = i40e_pci_error_slot_reset,
8781 .resume = i40e_pci_error_resume,
8782};
8783
8784static struct pci_driver i40e_driver = {
8785 .name = i40e_driver_name,
8786 .id_table = i40e_pci_tbl,
8787 .probe = i40e_probe,
8788 .remove = i40e_remove,
9007bccd
SN		 8789#ifdef CONFIG_PM
8790 .suspend = i40e_suspend,
8791 .resume = i40e_resume,
8792#endif
8793 .shutdown = i40e_shutdown,
41c445ff
JB		 8794 .err_handler = &i40e_err_handler,
8795 .sriov_configure = i40e_pci_sriov_configure,
8796};
8797
8798/**
8799 * i40e_init_module - Driver registration routine
8800 *
8801 * i40e_init_module is the first routine called when the driver is
8802 * loaded. All it does is register with the PCI subsystem.
8803 **/
8804static int __init i40e_init_module(void)
8805{
8806 pr_info("%s: %s - version %s\n", i40e_driver_name,
8807 i40e_driver_string, i40e_driver_version_str);
8808 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8809 i40e_dbg_init();
8810 return pci_register_driver(&i40e_driver);
8811}
8812module_init(i40e_init_module);
8813
8814/**
8815 * i40e_exit_module - Driver exit cleanup routine
8816 *
8817 * i40e_exit_module is called just before the driver is removed
8818 * from memory.
8819 **/
8820static void __exit i40e_exit_module(void)
8821{
8822 pci_unregister_driver(&i40e_driver);
8823 i40e_dbg_exit();
8824}
8825module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)